irqchip: nvic: Support hierarchy irq domain
authorStefan Agner <stefan@agner.ch>
Sat, 16 May 2015 09:44:16 +0000 (11:44 +0200)
committerThomas Gleixner <tglx@linutronix.de>
Mon, 18 May 2015 15:32:44 +0000 (17:32 +0200)
Add support for hierarchy irq domains. This is required to stack
the MSCM interrupt router and the NVIC controller found in Vybrid
SoC.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Cc: marc.zyngier@arm.com
Cc: linux@arm.linux.org.uk
Cc: u.kleine-koenig@pengutronix.de
Cc: olof@lixom.net
Cc: arnd@arndb.de
Cc: daniel.lezcano@linaro.org
Cc: mark.rutland@arm.com
Cc: pawel.moll@arm.com
Cc: robh+dt@kernel.org
Cc: ijc+devicetree@hellion.org.uk
Cc: galak@codeaurora.org
Cc: mcoquelin.stm32@gmail.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: shawn.guo@linaro.org
Cc: kernel@pengutronix.de
Cc: jason@lakedaemon.net
Link: http://lkml.kernel.org/r/1431769465-26867-5-git-send-email-stefan@agner.ch
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
drivers/irqchip/Kconfig
drivers/irqchip/irq-nvic.c

index 6de62a96e79c80e9d442ca07f53549cf334f8c7c..99b9a979297531e67960a75d35917e93c2223368 100644 (file)
@@ -30,6 +30,7 @@ config ARM_GIC_V3_ITS
 config ARM_NVIC
        bool
        select IRQ_DOMAIN
+       select IRQ_DOMAIN_HIERARCHY
        select GENERIC_IRQ_CHIP
 
 config ARM_VIC
index 4ff0805fca017376ea879f918517b9d61abf5ff6..5fac9100f6cbee9f7abf144eb4dcb9efeb3aaee0 100644 (file)
@@ -49,6 +49,31 @@ nvic_handle_irq(irq_hw_number_t hwirq, struct pt_regs *regs)
        handle_IRQ(irq, regs);
 }
 
+static int nvic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
+                               unsigned int nr_irqs, void *arg)
+{
+       int i, ret;
+       irq_hw_number_t hwirq;
+       unsigned int type = IRQ_TYPE_NONE;
+       struct of_phandle_args *irq_data = arg;
+
+       ret = irq_domain_xlate_onecell(domain, irq_data->np, irq_data->args,
+                                  irq_data->args_count, &hwirq, &type);
+       if (ret)
+               return ret;
+
+       for (i = 0; i < nr_irqs; i++)
+               irq_map_generic_chip(domain, virq + i, hwirq + i);
+
+       return 0;
+}
+
+static const struct irq_domain_ops nvic_irq_domain_ops = {
+       .xlate = irq_domain_xlate_onecell,
+       .alloc = nvic_irq_domain_alloc,
+       .free = irq_domain_free_irqs_top,
+};
+
 static int __init nvic_of_init(struct device_node *node,
                               struct device_node *parent)
 {
@@ -70,7 +95,8 @@ static int __init nvic_of_init(struct device_node *node,
                irqs = NVIC_MAX_IRQ;
 
        nvic_irq_domain =
-               irq_domain_add_linear(node, irqs, &irq_generic_chip_ops, NULL);
+               irq_domain_add_linear(node, irqs, &nvic_irq_domain_ops, NULL);
+
        if (!nvic_irq_domain) {
                pr_warn("Failed to allocate irq domain\n");
                return -ENOMEM;