add iomux for spi
authorcmc <cmc@rock-chips.com>
Tue, 7 Dec 2010 08:08:45 +0000 (16:08 +0800)
committercmc <cmc@rock-chips.com>
Tue, 7 Dec 2010 08:08:45 +0000 (16:08 +0800)
arch/arm/mach-rk29/board-rk29sdk.c
arch/arm/mach-rk29/include/mach/iomux.h [changed mode: 0644->0755]
arch/arm/mach-rk29/iomux.c [changed mode: 0644->0755]
drivers/spi/rk29_spim.c

index 934626a29c924c5637b45ce4aa61f69c25da05b3..26ecad0789f6d81d0ac18a986b0eda224044eb74 100755 (executable)
@@ -775,6 +775,18 @@ static void __init rk29_board_iomux_init(void)
        rk29_mux_api_set(GPIO2B4_UART3CTSN_I2C3SDA_NAME, GPIO2L_UART3_CTS_N);\r
        #endif\r
        #endif\r
+       #ifdef CONFIG_SPIM0_RK29\r
+    rk29_mux_api_set(GPIO2C0_SPI0CLK_NAME, GPIO2H_SPI0_CLK);\r
+       rk29_mux_api_set(GPIO2C1_SPI0CSN0_NAME, GPIO2H_SPI0_CSN0);\r
+       rk29_mux_api_set(GPIO2C2_SPI0TXD_NAME, GPIO2H_SPI0_TXD);\r
+       rk29_mux_api_set(GPIO2C3_SPI0RXD_NAME, GPIO2H_SPI0_RXD);\r
+    #endif\r
+    #ifdef CONFIG_SPIM1_RK29\r
+    rk29_mux_api_set(GPIO2C4_SPI1CLK_NAME, GPIO2H_SPI1_CLK);\r
+       rk29_mux_api_set(GPIO2C5_SPI1CSN0_NAME, GPIO2H_SPI1_CSN0);\r
+       rk29_mux_api_set(GPIO2C6_SPI1TXD_NAME, GPIO2H_SPI1_TXD);\r
+       rk29_mux_api_set(GPIO2C7_SPI1RXD_NAME, GPIO2H_SPI1_RXD);\r
+    #endif\r
 }\r
 \r
 static struct platform_device *devices[] __initdata = {\r
@@ -870,13 +882,13 @@ struct spi_cs_gpio rk29xx_spi1_cs_gpios[SPI_CHIPSELECT_NUM] = {
                .name = "spi1 cs1",\r
                .cs_gpio = RK29_PIN1_PA3,\r
                .cs_iomux_name = GPIO1A3_EMMCDETECTN_SPI1CS1_NAME,//if no iomux,set it NULL\r
-               .cs_iomux_mode = GPIO1L_SPI0_CSN1,\r
+               .cs_iomux_mode = GPIO1L_SPI1_CSN1,\r
        }\r
 };\r
 \r
 static int spi_io_init(struct spi_cs_gpio *cs_gpios, int cs_num)\r
 {\r
-#if 0\r
+#if 1\r
        int i,j,ret;\r
 \r
        //cs\r
@@ -901,7 +913,7 @@ static int spi_io_init(struct spi_cs_gpio *cs_gpios, int cs_num)
 \r
 static int spi_io_deinit(struct spi_cs_gpio *cs_gpios, int cs_num)\r
 {\r
-#if 0\r
+#if 1\r
        int i;\r
 \r
        if (cs_gpios) {\r
old mode 100644 (file)
new mode 100755 (executable)
index 41fade1..fb98223
 #define GPIO2D2_I2S0LRCKRX_MIITXERR_NAME                       "gpio2d2_i2s0lrckrx_miitxerr_name"
 #define GPIO2D1_I2S0SCLK_MIICRS_NAME                           "gpio2d1_i2s0sclk_miicrs_name"
 #define GPIO2D0_I2S0CLK_MIIRXCLKIN_NAME                                "gpio2d0_i2s0clk_miirxclkin_name"
-#define GPIO2C7_SPI1TXD_NAME                                           "gpio2c7_spi1txd_name"
+#define GPIO2C7_SPI1RXD_NAME                                           "gpio2c7_spi1rxd_name"
 #define GPIO2C6_SPI1TXD_NAME                                           "gpio2c6_spi1txd_name"
 #define GPIO2C5_SPI1CSN0_NAME                                          "gpio2c5_spi1csn0_name"
 #define GPIO2C4_SPI1CLK_NAME                                           "gpio2c4_spi1clk_name"
old mode 100644 (file)
new mode 100755 (executable)
index 914c40b..428e541
@@ -117,7 +117,7 @@ MUX_CFG(GPIO2D3_I2S0SDI_MIICOL_NAME,                                GPIO2H,   22,    2,       0,    DEFAULT)
 MUX_CFG(GPIO2D2_I2S0LRCKRX_MIITXERR_NAME,                      GPIO2H,   20,    2,       0,    DEFAULT)  
 MUX_CFG(GPIO2D1_I2S0SCLK_MIICRS_NAME,                          GPIO2H,   18,    2,       0,    DEFAULT) 
 MUX_CFG(GPIO2D0_I2S0CLK_MIIRXCLKIN_NAME,                       GPIO2H,   16,    2,       0,    DEFAULT) 
-MUX_CFG(GPIO2C7_SPI1TXD_NAME,                                          GPIO2H,   14,    2,       0,    DEFAULT) 
+MUX_CFG(GPIO2C7_SPI1RXD_NAME,                                          GPIO2H,   14,    2,       0,    DEFAULT) 
 MUX_CFG(GPIO2C6_SPI1TXD_NAME,                                          GPIO2H,   12,    2,       0,    DEFAULT) 
 MUX_CFG(GPIO2C5_SPI1CSN0_NAME,                                         GPIO2H,   10,    2,       0,    DEFAULT) 
 MUX_CFG(GPIO2C4_SPI1CLK_NAME,                                          GPIO2H,   8,     2,       0,    DEFAULT) 
index 9d15abc10d5998b3e5194c360589603cb3045598..b2ffd2ca1605e2ee6f0d0801a52d47e3c378365f 100755 (executable)
@@ -24,7 +24,7 @@
 #include <linux/dma-mapping.h>\r
 #include <asm/dma.h>\r
 \r
-#include "rk29xx_spim.h"\r
+#include "rk29_spim.h"\r
 #include <linux/spi/spi.h>\r
 #include <mach/board.h>\r
 \r
@@ -88,6 +88,28 @@ struct chip_data {
 #define RXBUSY    (1<<2)\r
 #define TXBUSY    (1<<3)\r
 \r
+static void spi_dump_regs(struct rk29xx_spi *dws) {\r
+       printk("MRST SPI0 registers:\n");\r
+       printk("=================================\n");\r
+       printk("CTRL0: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_CTRLR0));\r
+       printk("CTRL1: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_CTRLR1));\r
+       printk("SSIENR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_ENR));\r
+       printk("SER: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_SER));\r
+       printk("BAUDR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_BAUDR));\r
+       printk("TXFTLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_TXFTLR));\r
+       printk("RXFTLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_RXFTLR));\r
+       printk("TXFLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_TXFLR));\r
+       printk("RXFLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_RXFLR));\r
+       printk("SR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_SR));\r
+       printk("IMR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_IMR));\r
+       printk("ISR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_ISR));\r
+       printk("DMACR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_DMACR));\r
+       printk("DMATDLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_DMATDLR));\r
+       printk("DMARDLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_DMARDLR));\r
+       printk("=================================\n");\r
+\r
+}\r
+\r
 #ifdef CONFIG_DEBUG_FS\r
 static int spi_show_regs_open(struct inode *inode, struct file *file)\r
 {\r
@@ -220,9 +242,11 @@ static void flush(struct rk29xx_spi *dws)
        wait_till_not_busy(dws);\r
 }\r
 \r
-#if 0\r
 static void spi_cs_control(struct rk29xx_spi *dws, u32 cs, u8 flag)\r
 {\r
+       #if 1\r
+           return;\r
+       #else\r
        struct rk29xx_spi_platform_data *pdata = dws->master->dev.platform_data;\r
        struct spi_cs_gpio *cs_gpios = pdata->chipselect_gpios;\r
 \r
@@ -230,8 +254,8 @@ static void spi_cs_control(struct rk29xx_spi *dws, u32 cs, u8 flag)
                gpio_direction_output(cs_gpios[cs].cs_gpio, GPIO_HIGH);\r
        else\r
                gpio_direction_output(cs_gpios[cs].cs_gpio, GPIO_LOW);\r
+       #endif\r
 }\r
-#endif\r
 \r
 static int null_writer(struct rk29xx_spi *dws)\r
 {\r
@@ -261,6 +285,8 @@ static int null_reader(struct rk29xx_spi *dws)
 \r
 static int u8_writer(struct rk29xx_spi *dws)\r
 {      \r
+       spi_dump_regs(dws);\r
+       DBG("tx: 0x%02x\n", *(u8 *)(dws->tx));\r
        if ((rk29xx_readw(dws, SPIM_SR) & SR_TF_FULL)\r
                || (dws->tx == dws->tx_end))\r
                return 0;\r
@@ -353,12 +379,14 @@ static void rk29_spi_dma_txcb(void *buf_id,
        struct rk29xx_spi *dws = buf_id;\r
        unsigned long flags;\r
 \r
+       DBG("func: %s, line: %d\n", __FUNCTION__, __LINE__);\r
+\r
        spin_lock_irqsave(&dws->lock, flags);\r
 \r
        if (res == RK29_RES_OK)\r
                dws->state &= ~TXBUSY;\r
        else\r
-               dev_err(&dws->master->dev, "DmaAbrtTx-%d \n", size);\r
+               dev_err(&dws->master->dev, "DmaAbrtTx-%d, size: %d \n", res, size);\r
 \r
        /* If the other done */\r
        if (!(dws->state & RXBUSY)) \r
@@ -421,7 +449,7 @@ static int map_dma_buffers(struct rk29xx_spi *dws)
                        return -1;\r
                }\r
                if (rk29_dma_devconfig(dws->tx_dmach, RK29_DMASRC_MEM,\r
-                                       (unsigned long)dws->sfr_start + SPIM_TXDR)) {\r
+                                       dws->sfr_start + SPIM_TXDR)) {\r
                        dev_err(&dws->master->dev, "rk29_dma_devconfig fail\n");\r
                        return -1;\r
                }\r
@@ -434,7 +462,7 @@ static int map_dma_buffers(struct rk29xx_spi *dws)
                        return -1;\r
                }\r
                if (rk29_dma_devconfig(dws->rx_dmach, RK29_DMASRC_HW,\r
-                                       (unsigned long)dws->sfr_start + SPIM_RXDR)) {\r
+                                       dws->sfr_start + SPIM_RXDR)) {\r
                        dev_err(&dws->master->dev, "rk29_dma_devconfig fail\n");\r
                        return -1;\r
                }\r
@@ -464,7 +492,7 @@ static void giveback(struct rk29xx_spi *dws)
                                        struct spi_transfer,\r
                                        transfer_list);\r
 \r
-       if (!last_transfer->cs_change)\r
+       if (!last_transfer->cs_change && dws->cs_control)\r
                dws->cs_control(dws,msg->spi->chip_select, MRST_SPI_DEASSERT);\r
 \r
        msg->state = NULL;\r
@@ -501,7 +529,7 @@ static void transfer_complete(struct rk29xx_spi *dws)
 \r
 static irqreturn_t interrupt_transfer(struct rk29xx_spi *dws)\r
 {\r
-       u16 irq_status, irq_mask = 0x3f;\r
+       u16 irq_status, irq_mask = 0x1f;\r
        u32 int_level = dws->fifo_len / 2;\r
        u32 left;\r
        \r
@@ -563,7 +591,7 @@ static void spi_chip_sel(struct rk29xx_spi *dws, u16 cs)
                return;\r
 \r
        if (dws->cs_control){\r
-           dws->cs_control(dws, cs, 1);\r
+           dws->cs_control(dws, cs, MRST_SPI_ASSERT);\r
        }\r
        rk29xx_writel(dws, SPIM_SER, 1 << cs);\r
 }\r
@@ -593,8 +621,7 @@ static void pump_transfers(unsigned long data)
        chip = dws->cur_chip;\r
        spi = message->spi;     \r
        if (unlikely(!chip->clk_div))\r
-               //chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz;       \r
-           chip->clk_div = 40000000 / chip->speed_hz;  \r
+               chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz; \r
        if (message->state == ERROR_STATE) {\r
                message->status = -EIO;\r
                goto early_exit;\r
@@ -769,6 +796,7 @@ static void dma_transfer(struct rk29xx_spi *dws) //int cs_change)
        unsigned long val;\r
        int ms;\r
        int iRet;\r
+       int burst;\r
        u8 bits = 0;\r
        u8 spi_dfs = 0;\r
        u8 cs_change = 0;\r
@@ -795,7 +823,7 @@ static void dma_transfer(struct rk29xx_spi *dws) //int cs_change)
        chip = dws->cur_chip;\r
        spi = message->spi;     \r
        if (unlikely(!chip->clk_div))\r
-               chip->clk_div = 40000000 / chip->speed_hz;      \r
+               chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz; \r
        if (message->state == ERROR_STATE) {\r
                message->status = -EIO;\r
                goto err_out;\r
@@ -936,10 +964,18 @@ static void dma_transfer(struct rk29xx_spi *dws) //int cs_change)
        } \r
 \r
        INIT_COMPLETION(dws->xfer_completion);\r
-       \r
+\r
+       spi_dump_regs(dws);\r
+       DBG("dws->tx_dmach: %d, dws->rx_dmach: %d, transfer->tx_dma: 0x%x\n", dws->tx_dmach, dws->rx_dmach, (unsigned int)transfer->tx_dma);\r
        if (transfer->tx_buf != NULL) {\r
                dws->state |= TXBUSY;\r
-               if (rk29_dma_config(dws->tx_dmach, 1)) {\r
+               if (transfer->len & 0x3) {\r
+                       burst = 1;\r
+               }\r
+               else {\r
+                       burst = 4;\r
+               }\r
+               if (rk29_dma_config(dws->tx_dmach, burst)) {\r
                        dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);\r
                        goto err_out;\r
                }\r
@@ -979,10 +1015,10 @@ static void dma_transfer(struct rk29xx_spi *dws) //int cs_change)
        }\r
 \r
        /* millisecs to xfer 'len' bytes @ 'cur_speed' */\r
-       ms = transfer->len * 8 * 1000 / dws->cur_chip->speed_hz;\r
+       ms = transfer->len * 8 / dws->cur_chip->speed_hz;\r
        ms += 10; \r
 \r
-       val = msecs_to_jiffies(ms) + 500;\r
+       val = msecs_to_jiffies(ms) + 10;\r
        if (!wait_for_completion_timeout(&dws->xfer_completion, val)) {\r
                if (transfer->rx_buf != NULL && (dws->state & RXBUSY)) {\r
                        rk29_dma_ctrl(dws->rx_dmach, RK29_DMAOP_FLUSH);\r
@@ -1118,7 +1154,7 @@ static void msg_giveback(struct rk29xx_spi *dws)
                                        struct spi_transfer,\r
                                        transfer_list);\r
 \r
-       if (!last_transfer->cs_change)\r
+       if (!last_transfer->cs_change && dws->cs_control)\r
                dws->cs_control(dws,msg->spi->chip_select,MRST_SPI_DEASSERT);\r
 \r
        msg->state = NULL;      \r
@@ -1511,7 +1547,7 @@ static int rk29xx_spi_setup(struct spi_device *spi)
                if (!chip)\r
                        return -ENOMEM;\r
 \r
-               chip->cs_control = NULL;\r
+               chip->cs_control = spi_cs_control;\r
                chip->enable_dma = 1;  //0;\r
        }\r
 \r
@@ -1570,6 +1606,7 @@ static int rk29xx_spi_setup(struct spi_device *spi)
                        | (chip->tmode << SPI_TMOD_OFFSET);\r
 \r
        spi_set_ctldata(spi, chip);\r
+       DBG("RK29XX_SPI_SETUP: CRO: 0x%x ???????????????????\n", chip->cr0);\r
        return 0;\r
 }\r
 \r
@@ -1661,9 +1698,7 @@ static void spi_hw_init(struct rk29xx_spi *dws)
 {\r
        spi_enable_chip(dws, 0);\r
        spi_mask_intr(dws, 0xff);\r
-       spi_enable_chip(dws, 1);\r
-       flush(dws);\r
-\r
+       \r
        /*\r
         * Try to detect the FIFO depth if not set by interface driver,\r
         * the depth could be from 2 to 32 from HW spec\r
@@ -1679,6 +1714,9 @@ static void spi_hw_init(struct rk29xx_spi *dws)
                dws->fifo_len = (fifo == 31) ? 0 : fifo;\r
                rk29xx_writew(dws, SPIM_TXFTLR, 0);\r
        }\r
+       \r
+       spi_enable_chip(dws, 1);\r
+       flush(dws);\r
 }\r
 \r
 /* cpufreq driver support */\r
@@ -1833,7 +1871,7 @@ static int __init rk29xx_spim_probe(struct platform_device *pdev)
         dev_err(&master->dev, "rk29xx spim failed to init cpufreq support\n");\r
         goto err_queue_alloc;\r
     }\r
-       DBG(KERN_INFO "rk29xx_spim: driver initialized\n");\r
+       DBG(KERN_INFO "rk29xx_spim: driver initialized, fifo_len: %d\n", dws->fifo_len);\r
        mrst_spi_debugfs_init(dws);\r
        return 0;\r
 \r