#include <linux/dma-mapping.h>\r
#include <asm/dma.h>\r
\r
-#include "rk29xx_spim.h"\r
+#include "rk29_spim.h"\r
#include <linux/spi/spi.h>\r
#include <mach/board.h>\r
\r
#define RXBUSY (1<<2)\r
#define TXBUSY (1<<3)\r
\r
+static void spi_dump_regs(struct rk29xx_spi *dws) {\r
+ printk("MRST SPI0 registers:\n");\r
+ printk("=================================\n");\r
+ printk("CTRL0: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_CTRLR0));\r
+ printk("CTRL1: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_CTRLR1));\r
+ printk("SSIENR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_ENR));\r
+ printk("SER: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_SER));\r
+ printk("BAUDR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_BAUDR));\r
+ printk("TXFTLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_TXFTLR));\r
+ printk("RXFTLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_RXFTLR));\r
+ printk("TXFLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_TXFLR));\r
+ printk("RXFLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_RXFLR));\r
+ printk("SR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_SR));\r
+ printk("IMR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_IMR));\r
+ printk("ISR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_ISR));\r
+ printk("DMACR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_DMACR));\r
+ printk("DMATDLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_DMATDLR));\r
+ printk("DMARDLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_DMARDLR));\r
+ printk("=================================\n");\r
+\r
+}\r
+\r
#ifdef CONFIG_DEBUG_FS\r
static int spi_show_regs_open(struct inode *inode, struct file *file)\r
{\r
wait_till_not_busy(dws);\r
}\r
\r
-#if 0\r
static void spi_cs_control(struct rk29xx_spi *dws, u32 cs, u8 flag)\r
{\r
+ #if 1\r
+ return;\r
+ #else\r
struct rk29xx_spi_platform_data *pdata = dws->master->dev.platform_data;\r
struct spi_cs_gpio *cs_gpios = pdata->chipselect_gpios;\r
\r
gpio_direction_output(cs_gpios[cs].cs_gpio, GPIO_HIGH);\r
else\r
gpio_direction_output(cs_gpios[cs].cs_gpio, GPIO_LOW);\r
+ #endif\r
}\r
-#endif\r
\r
static int null_writer(struct rk29xx_spi *dws)\r
{\r
\r
static int u8_writer(struct rk29xx_spi *dws)\r
{ \r
+ spi_dump_regs(dws);\r
+ DBG("tx: 0x%02x\n", *(u8 *)(dws->tx));\r
if ((rk29xx_readw(dws, SPIM_SR) & SR_TF_FULL)\r
|| (dws->tx == dws->tx_end))\r
return 0;\r
struct rk29xx_spi *dws = buf_id;\r
unsigned long flags;\r
\r
+ DBG("func: %s, line: %d\n", __FUNCTION__, __LINE__);\r
+\r
spin_lock_irqsave(&dws->lock, flags);\r
\r
if (res == RK29_RES_OK)\r
dws->state &= ~TXBUSY;\r
else\r
- dev_err(&dws->master->dev, "DmaAbrtTx-%d \n", size);\r
+ dev_err(&dws->master->dev, "DmaAbrtTx-%d, size: %d \n", res, size);\r
\r
/* If the other done */\r
if (!(dws->state & RXBUSY)) \r
return -1;\r
}\r
if (rk29_dma_devconfig(dws->tx_dmach, RK29_DMASRC_MEM,\r
- (unsigned long)dws->sfr_start + SPIM_TXDR)) {\r
+ dws->sfr_start + SPIM_TXDR)) {\r
dev_err(&dws->master->dev, "rk29_dma_devconfig fail\n");\r
return -1;\r
}\r
return -1;\r
}\r
if (rk29_dma_devconfig(dws->rx_dmach, RK29_DMASRC_HW,\r
- (unsigned long)dws->sfr_start + SPIM_RXDR)) {\r
+ dws->sfr_start + SPIM_RXDR)) {\r
dev_err(&dws->master->dev, "rk29_dma_devconfig fail\n");\r
return -1;\r
}\r
struct spi_transfer,\r
transfer_list);\r
\r
- if (!last_transfer->cs_change)\r
+ if (!last_transfer->cs_change && dws->cs_control)\r
dws->cs_control(dws,msg->spi->chip_select, MRST_SPI_DEASSERT);\r
\r
msg->state = NULL;\r
\r
static irqreturn_t interrupt_transfer(struct rk29xx_spi *dws)\r
{\r
- u16 irq_status, irq_mask = 0x3f;\r
+ u16 irq_status, irq_mask = 0x1f;\r
u32 int_level = dws->fifo_len / 2;\r
u32 left;\r
\r
return;\r
\r
if (dws->cs_control){\r
- dws->cs_control(dws, cs, 1);\r
+ dws->cs_control(dws, cs, MRST_SPI_ASSERT);\r
}\r
rk29xx_writel(dws, SPIM_SER, 1 << cs);\r
}\r
chip = dws->cur_chip;\r
spi = message->spi; \r
if (unlikely(!chip->clk_div))\r
- //chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz; \r
- chip->clk_div = 40000000 / chip->speed_hz; \r
+ chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz; \r
if (message->state == ERROR_STATE) {\r
message->status = -EIO;\r
goto early_exit;\r
unsigned long val;\r
int ms;\r
int iRet;\r
+ int burst;\r
u8 bits = 0;\r
u8 spi_dfs = 0;\r
u8 cs_change = 0;\r
chip = dws->cur_chip;\r
spi = message->spi; \r
if (unlikely(!chip->clk_div))\r
- chip->clk_div = 40000000 / chip->speed_hz; \r
+ chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz; \r
if (message->state == ERROR_STATE) {\r
message->status = -EIO;\r
goto err_out;\r
} \r
\r
INIT_COMPLETION(dws->xfer_completion);\r
- \r
+\r
+ spi_dump_regs(dws);\r
+ DBG("dws->tx_dmach: %d, dws->rx_dmach: %d, transfer->tx_dma: 0x%x\n", dws->tx_dmach, dws->rx_dmach, (unsigned int)transfer->tx_dma);\r
if (transfer->tx_buf != NULL) {\r
dws->state |= TXBUSY;\r
- if (rk29_dma_config(dws->tx_dmach, 1)) {\r
+ if (transfer->len & 0x3) {\r
+ burst = 1;\r
+ }\r
+ else {\r
+ burst = 4;\r
+ }\r
+ if (rk29_dma_config(dws->tx_dmach, burst)) {\r
dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);\r
goto err_out;\r
}\r
}\r
\r
/* millisecs to xfer 'len' bytes @ 'cur_speed' */\r
- ms = transfer->len * 8 * 1000 / dws->cur_chip->speed_hz;\r
+ ms = transfer->len * 8 / dws->cur_chip->speed_hz;\r
ms += 10; \r
\r
- val = msecs_to_jiffies(ms) + 500;\r
+ val = msecs_to_jiffies(ms) + 10;\r
if (!wait_for_completion_timeout(&dws->xfer_completion, val)) {\r
if (transfer->rx_buf != NULL && (dws->state & RXBUSY)) {\r
rk29_dma_ctrl(dws->rx_dmach, RK29_DMAOP_FLUSH);\r
struct spi_transfer,\r
transfer_list);\r
\r
- if (!last_transfer->cs_change)\r
+ if (!last_transfer->cs_change && dws->cs_control)\r
dws->cs_control(dws,msg->spi->chip_select,MRST_SPI_DEASSERT);\r
\r
msg->state = NULL; \r
if (!chip)\r
return -ENOMEM;\r
\r
- chip->cs_control = NULL;\r
+ chip->cs_control = spi_cs_control;\r
chip->enable_dma = 1; //0;\r
}\r
\r
| (chip->tmode << SPI_TMOD_OFFSET);\r
\r
spi_set_ctldata(spi, chip);\r
+ DBG("RK29XX_SPI_SETUP: CRO: 0x%x ???????????????????\n", chip->cr0);\r
return 0;\r
}\r
\r
{\r
spi_enable_chip(dws, 0);\r
spi_mask_intr(dws, 0xff);\r
- spi_enable_chip(dws, 1);\r
- flush(dws);\r
-\r
+ \r
/*\r
* Try to detect the FIFO depth if not set by interface driver,\r
* the depth could be from 2 to 32 from HW spec\r
dws->fifo_len = (fifo == 31) ? 0 : fifo;\r
rk29xx_writew(dws, SPIM_TXFTLR, 0);\r
}\r
+ \r
+ spi_enable_chip(dws, 1);\r
+ flush(dws);\r
}\r
\r
/* cpufreq driver support */\r
dev_err(&master->dev, "rk29xx spim failed to init cpufreq support\n");\r
goto err_queue_alloc;\r
}\r
- DBG(KERN_INFO "rk29xx_spim: driver initialized\n");\r
+ DBG(KERN_INFO "rk29xx_spim: driver initialized, fifo_len: %d\n", dws->fifo_len);\r
mrst_spi_debugfs_init(dws);\r
return 0;\r
\r