drm/radeon: remove special handling for the DMA ring
authorChristian König <christian.koenig@amd.com>
Tue, 13 Aug 2013 09:56:52 +0000 (11:56 +0200)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 30 Aug 2013 20:30:41 +0000 (16:30 -0400)
Now that we have callbacks for [rw]ptr handling we can
remove the special handling for the DMA rings and use
the callbacks instead.

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/radeon/cik.c
drivers/gpu/drm/radeon/evergreen.c
drivers/gpu/drm/radeon/ni.c
drivers/gpu/drm/radeon/r100.c
drivers/gpu/drm/radeon/r600.c
drivers/gpu/drm/radeon/radeon.h
drivers/gpu/drm/radeon/radeon_asic.c
drivers/gpu/drm/radeon/radeon_asic.h
drivers/gpu/drm/radeon/radeon_ring.c
drivers/gpu/drm/radeon/rv770.c
drivers/gpu/drm/radeon/si.c

index ce7036ae9f5a3e6a21187f4bcf3498688ac65509..34be795de173fb40ef5063b0720500ab89065fd0 100644 (file)
@@ -3414,7 +3414,6 @@ u32 cik_compute_ring_get_rptr(struct radeon_device *rdev,
                cik_srbm_select(rdev, 0, 0, 0, 0);
                mutex_unlock(&rdev->srbm_mutex);
        }
-       rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
 
        return rptr;
 }
@@ -3433,7 +3432,6 @@ u32 cik_compute_ring_get_wptr(struct radeon_device *rdev,
                cik_srbm_select(rdev, 0, 0, 0, 0);
                mutex_unlock(&rdev->srbm_mutex);
        }
-       wptr = (wptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
 
        return wptr;
 }
@@ -3441,10 +3439,8 @@ u32 cik_compute_ring_get_wptr(struct radeon_device *rdev,
 void cik_compute_ring_set_wptr(struct radeon_device *rdev,
                               struct radeon_ring *ring)
 {
-       u32 wptr = (ring->wptr << ring->ptr_reg_shift) & ring->ptr_reg_mask;
-
-       rdev->wb.wb[ring->wptr_offs/4] = cpu_to_le32(wptr);
-       WDOORBELL32(ring->doorbell_offset, wptr);
+       rdev->wb.wb[ring->wptr_offs/4] = cpu_to_le32(ring->wptr);
+       WDOORBELL32(ring->doorbell_offset, ring->wptr);
 }
 
 /**
@@ -7649,7 +7645,7 @@ static int cik_startup(struct radeon_device *rdev)
        ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
        r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
                             CP_RB0_RPTR, CP_RB0_WPTR,
-                            0, 0xfffff, RADEON_CP_PACKET2);
+                            RADEON_CP_PACKET2);
        if (r)
                return r;
 
@@ -7658,7 +7654,7 @@ static int cik_startup(struct radeon_device *rdev)
        ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
        r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
                             CP_HQD_PQ_RPTR, CP_HQD_PQ_WPTR,
-                            0, 0xfffff, PACKET3(PACKET3_NOP, 0x3FFF));
+                            PACKET3(PACKET3_NOP, 0x3FFF));
        if (r)
                return r;
        ring->me = 1; /* first MEC */
@@ -7670,7 +7666,7 @@ static int cik_startup(struct radeon_device *rdev)
        ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
        r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
                             CP_HQD_PQ_RPTR, CP_HQD_PQ_WPTR,
-                            0, 0xffffffff, PACKET3(PACKET3_NOP, 0x3FFF));
+                            PACKET3(PACKET3_NOP, 0x3FFF));
        if (r)
                return r;
        /* dGPU only have 1 MEC */
@@ -7683,7 +7679,7 @@ static int cik_startup(struct radeon_device *rdev)
        r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
                             SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET,
                             SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET,
-                            2, 0xfffffffc, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
+                            SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
        if (r)
                return r;
 
@@ -7691,7 +7687,7 @@ static int cik_startup(struct radeon_device *rdev)
        r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
                             SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET,
                             SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET,
-                            2, 0xfffffffc, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
+                            SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
        if (r)
                return r;
 
@@ -7707,7 +7703,7 @@ static int cik_startup(struct radeon_device *rdev)
        if (ring->ring_size) {
                r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
                                     UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
-                                    0, 0xfffff, RADEON_CP_PACKET2);
+                                    RADEON_CP_PACKET2);
                if (!r)
                        r = r600_uvd_init(rdev, true);
                if (r)
index 2139f6c64341f944bf1e6f7f640e50f09c7299a9..389f5a981358b9cbab6093034f31fee0ff27952e 100644 (file)
@@ -5268,14 +5268,14 @@ static int evergreen_startup(struct radeon_device *rdev)
        ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
        r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
                             R600_CP_RB_RPTR, R600_CP_RB_WPTR,
-                            0, 0xfffff, RADEON_CP_PACKET2);
+                            RADEON_CP_PACKET2);
        if (r)
                return r;
 
        ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
        r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
                             DMA_RB_RPTR, DMA_RB_WPTR,
-                            2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0));
+                            DMA_PACKET(DMA_PACKET_NOP, 0, 0));
        if (r)
                return r;
 
@@ -5293,7 +5293,7 @@ static int evergreen_startup(struct radeon_device *rdev)
        if (ring->ring_size) {
                r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
                                     UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
-                                    0, 0xfffff, RADEON_CP_PACKET2);
+                                    RADEON_CP_PACKET2);
                if (!r)
                        r = r600_uvd_init(rdev, true);
 
index f543f4ca4ddaadb8d3b339e521969eab34ba962a..e04b17338336e0648f1e8ec21a29b97df836bab8 100644 (file)
@@ -2192,7 +2192,7 @@ static int cayman_startup(struct radeon_device *rdev)
 
        r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
                             CP_RB0_RPTR, CP_RB0_WPTR,
-                            0, 0xfffff, RADEON_CP_PACKET2);
+                            RADEON_CP_PACKET2);
        if (r)
                return r;
 
@@ -2200,7 +2200,7 @@ static int cayman_startup(struct radeon_device *rdev)
        r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
                             DMA_RB_RPTR + DMA0_REGISTER_OFFSET,
                             DMA_RB_WPTR + DMA0_REGISTER_OFFSET,
-                            2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
+                            DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
        if (r)
                return r;
 
@@ -2208,7 +2208,7 @@ static int cayman_startup(struct radeon_device *rdev)
        r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
                             DMA_RB_RPTR + DMA1_REGISTER_OFFSET,
                             DMA_RB_WPTR + DMA1_REGISTER_OFFSET,
-                            2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
+                            DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
        if (r)
                return r;
 
@@ -2227,7 +2227,7 @@ static int cayman_startup(struct radeon_device *rdev)
        if (ring->ring_size) {
                r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
                                     UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
-                                    0, 0xfffff, RADEON_CP_PACKET2);
+                                    RADEON_CP_PACKET2);
                if (!r)
                        r = r600_uvd_init(rdev, true);
                if (r)
index 75349cdaa84b181186d6dee878d582437521a96a..2cbc512645d467be744a1ebc70e038876336b3e2 100644 (file)
@@ -1102,7 +1102,7 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
        r100_cp_load_microcode(rdev);
        r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
                             RADEON_CP_RB_RPTR, RADEON_CP_RB_WPTR,
-                            0, 0x7fffff, RADEON_CP_PACKET2);
+                            RADEON_CP_PACKET2);
        if (r) {
                return r;
        }
index c1b0aba4431ae03e44f4ae347ccd0a01bf1579b9..30849eca6e07353ef35997831218a8cbca5debaa 100644 (file)
@@ -2504,6 +2504,49 @@ void r600_cp_fini(struct radeon_device *rdev)
  * solid fills, and a number of other things.  It also
  * has support for tiling/detiling of buffers.
  */
+
+/**
+ * r600_dma_get_rptr - get the current read pointer
+ *
+ * @rdev: radeon_device pointer
+ * @ring: radeon ring pointer
+ *
+ * Get the current rptr from the hardware (r6xx+).
+ */
+uint32_t r600_dma_get_rptr(struct radeon_device *rdev,
+                          struct radeon_ring *ring)
+{
+       return (radeon_ring_generic_get_rptr(rdev, ring) & 0x3fffc) >> 2;
+}
+
+/**
+ * r600_dma_get_wptr - get the current write pointer
+ *
+ * @rdev: radeon_device pointer
+ * @ring: radeon ring pointer
+ *
+ * Get the current wptr from the hardware (r6xx+).
+ */
+uint32_t r600_dma_get_wptr(struct radeon_device *rdev,
+                          struct radeon_ring *ring)
+{
+       return (RREG32(ring->wptr_reg) & 0x3fffc) >> 2;
+}
+
+/**
+ * r600_dma_set_wptr - commit the write pointer
+ *
+ * @rdev: radeon_device pointer
+ * @ring: radeon ring pointer
+ *
+ * Write the wptr back to the hardware (r6xx+).
+ */
+void r600_dma_set_wptr(struct radeon_device *rdev,
+                      struct radeon_ring *ring)
+{
+       WREG32(ring->wptr_reg, (ring->wptr << 2) & 0x3fffc);
+}
+
 /**
  * r600_dma_stop - stop the async dma engine
  *
@@ -3386,14 +3429,14 @@ static int r600_startup(struct radeon_device *rdev)
        ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
        r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
                             R600_CP_RB_RPTR, R600_CP_RB_WPTR,
-                            0, 0xfffff, RADEON_CP_PACKET2);
+                            RADEON_CP_PACKET2);
        if (r)
                return r;
 
        ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
        r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
                             DMA_RB_RPTR, DMA_RB_WPTR,
-                            2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
+                            DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
        if (r)
                return r;
 
index 2eab174bf22e0de5ee1dc6d526dfa1b9cc1f80db..791cc8de6395e63571ee13be832d767f55ce2218 100644 (file)
@@ -760,8 +760,6 @@ struct radeon_ring {
        uint32_t                align_mask;
        uint32_t                ptr_mask;
        bool                    ready;
-       u32                     ptr_reg_shift;
-       u32                     ptr_reg_mask;
        u32                     nop;
        u32                     idx;
        u64                     last_semaphore_signal_addr;
@@ -912,8 +910,7 @@ unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring
 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
                        unsigned size, uint32_t *data);
 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
-                    unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
-                    u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
+                    unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, u32 nop);
 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
 
 
index 7432247a812afb0b0b3eaafe6b5951f69ca30ba2..785b7a7add776c4387da5eac94f8b33a18063cca 100644 (file)
@@ -896,9 +896,9 @@ static struct radeon_asic_ring r600_dma_ring = {
        .ring_test = &r600_dma_ring_test,
        .ib_test = &r600_dma_ib_test,
        .is_lockup = &r600_dma_is_lockup,
-       .get_rptr = &radeon_ring_generic_get_rptr,
-       .get_wptr = &radeon_ring_generic_get_wptr,
-       .set_wptr = &radeon_ring_generic_set_wptr,
+       .get_rptr = &r600_dma_get_rptr,
+       .get_wptr = &r600_dma_get_wptr,
+       .set_wptr = &r600_dma_set_wptr,
 };
 
 static struct radeon_asic r600_asic = {
@@ -1275,9 +1275,9 @@ static struct radeon_asic_ring evergreen_dma_ring = {
        .ring_test = &r600_dma_ring_test,
        .ib_test = &r600_dma_ib_test,
        .is_lockup = &evergreen_dma_is_lockup,
-       .get_rptr = &radeon_ring_generic_get_rptr,
-       .get_wptr = &radeon_ring_generic_get_wptr,
-       .set_wptr = &radeon_ring_generic_set_wptr,
+       .get_rptr = &r600_dma_get_rptr,
+       .get_wptr = &r600_dma_get_wptr,
+       .set_wptr = &r600_dma_set_wptr,
 };
 
 static struct radeon_asic evergreen_asic = {
@@ -1580,9 +1580,9 @@ static struct radeon_asic_ring cayman_dma_ring = {
        .ib_test = &r600_dma_ib_test,
        .is_lockup = &cayman_dma_is_lockup,
        .vm_flush = &cayman_dma_vm_flush,
-       .get_rptr = &radeon_ring_generic_get_rptr,
-       .get_wptr = &radeon_ring_generic_get_wptr,
-       .set_wptr = &radeon_ring_generic_set_wptr
+       .get_rptr = &r600_dma_get_rptr,
+       .get_wptr = &r600_dma_get_wptr,
+       .set_wptr = &r600_dma_set_wptr
 };
 
 static struct radeon_asic_ring cayman_uvd_ring = {
@@ -1822,9 +1822,9 @@ static struct radeon_asic_ring si_dma_ring = {
        .ib_test = &r600_dma_ib_test,
        .is_lockup = &si_dma_is_lockup,
        .vm_flush = &si_dma_vm_flush,
-       .get_rptr = &radeon_ring_generic_get_rptr,
-       .get_wptr = &radeon_ring_generic_get_wptr,
-       .set_wptr = &radeon_ring_generic_set_wptr,
+       .get_rptr = &r600_dma_get_rptr,
+       .get_wptr = &r600_dma_get_wptr,
+       .set_wptr = &r600_dma_set_wptr,
 };
 
 static struct radeon_asic si_asic = {
@@ -1966,9 +1966,9 @@ static struct radeon_asic_ring ci_dma_ring = {
        .ib_test = &cik_sdma_ib_test,
        .is_lockup = &cik_sdma_is_lockup,
        .vm_flush = &cik_dma_vm_flush,
-       .get_rptr = &radeon_ring_generic_get_rptr,
-       .get_wptr = &radeon_ring_generic_get_wptr,
-       .set_wptr = &radeon_ring_generic_set_wptr,
+       .get_rptr = &r600_dma_get_rptr,
+       .get_wptr = &r600_dma_get_wptr,
+       .set_wptr = &r600_dma_set_wptr,
 };
 
 static struct radeon_asic ci_asic = {
index 37baf9c696f0ac21a8453109c74433665193437e..5c53eb78b22dd397ea4d9f5f4a41e7682ec8518c 100644 (file)
@@ -392,6 +392,13 @@ uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev);
 int rv6xx_get_temp(struct radeon_device *rdev);
 int r600_dpm_pre_set_power_state(struct radeon_device *rdev);
 void r600_dpm_post_set_power_state(struct radeon_device *rdev);
+/* r600 dma */
+uint32_t r600_dma_get_rptr(struct radeon_device *rdev,
+                          struct radeon_ring *ring);
+uint32_t r600_dma_get_wptr(struct radeon_device *rdev,
+                          struct radeon_ring *ring);
+void r600_dma_set_wptr(struct radeon_device *rdev,
+                      struct radeon_ring *ring);
 /* rv6xx dpm */
 int rv6xx_dpm_init(struct radeon_device *rdev);
 int rv6xx_dpm_enable(struct radeon_device *rdev);
index cb4b931d8d9f2f6be1cd82f4f148ca450a605508..46a25f037b843b70ebfb04e77ad55901111efd02 100644 (file)
@@ -367,7 +367,6 @@ u32 radeon_ring_generic_get_rptr(struct radeon_device *rdev,
                rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
        else
                rptr = RREG32(ring->rptr_reg);
-       rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
 
        return rptr;
 }
@@ -378,7 +377,6 @@ u32 radeon_ring_generic_get_wptr(struct radeon_device *rdev,
        u32 wptr;
 
        wptr = RREG32(ring->wptr_reg);
-       wptr = (wptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
 
        return wptr;
 }
@@ -386,7 +384,7 @@ u32 radeon_ring_generic_get_wptr(struct radeon_device *rdev,
 void radeon_ring_generic_set_wptr(struct radeon_device *rdev,
                                  struct radeon_ring *ring)
 {
-       WREG32(ring->wptr_reg, (ring->wptr << ring->ptr_reg_shift) & ring->ptr_reg_mask);
+       WREG32(ring->wptr_reg, ring->wptr);
        (void)RREG32(ring->wptr_reg);
 }
 
@@ -719,16 +717,13 @@ int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
  * @rptr_offs: offset of the rptr writeback location in the WB buffer
  * @rptr_reg: MMIO offset of the rptr register
  * @wptr_reg: MMIO offset of the wptr register
- * @ptr_reg_shift: bit offset of the rptr/wptr values
- * @ptr_reg_mask: bit mask of the rptr/wptr values
  * @nop: nop packet for this ring
  *
  * Initialize the driver information for the selected ring (all asics).
  * Returns 0 on success, error on failure.
  */
 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size,
-                    unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
-                    u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop)
+                    unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, u32 nop)
 {
        int r;
 
@@ -736,8 +731,6 @@ int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsig
        ring->rptr_offs = rptr_offs;
        ring->rptr_reg = rptr_reg;
        ring->wptr_reg = wptr_reg;
-       ring->ptr_reg_shift = ptr_reg_shift;
-       ring->ptr_reg_mask = ptr_reg_mask;
        ring->nop = nop;
        /* Allocate ring buffer */
        if (ring->ring_obj == NULL) {
index 1e8cf49d5871f0ef73236b34e0e0611cd02bc399..fd9dcb2d182bb07f08b3710b8d4538d837a50ea9 100644 (file)
@@ -1899,14 +1899,14 @@ static int rv770_startup(struct radeon_device *rdev)
        ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
        r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
                             R600_CP_RB_RPTR, R600_CP_RB_WPTR,
-                            0, 0xfffff, RADEON_CP_PACKET2);
+                            RADEON_CP_PACKET2);
        if (r)
                return r;
 
        ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
        r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
                             DMA_RB_RPTR, DMA_RB_WPTR,
-                            2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
+                            DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
        if (r)
                return r;
 
@@ -1925,7 +1925,7 @@ static int rv770_startup(struct radeon_device *rdev)
        if (ring->ring_size) {
                r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
                                     UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
-                                    0, 0xfffff, RADEON_CP_PACKET2);
+                                    RADEON_CP_PACKET2);
                if (!r)
                        r = r600_uvd_init(rdev, true);
 
index 4ff59c8f508f6c32d2b6f1b2caaf1d4c8200556a..ae232be62921e24334f924c24ecd70985fedb708 100644 (file)
@@ -6368,21 +6368,21 @@ static int si_startup(struct radeon_device *rdev)
        ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
        r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
                             CP_RB0_RPTR, CP_RB0_WPTR,
-                            0, 0xfffff, RADEON_CP_PACKET2);
+                            RADEON_CP_PACKET2);
        if (r)
                return r;
 
        ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
        r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
                             CP_RB1_RPTR, CP_RB1_WPTR,
-                            0, 0xfffff, RADEON_CP_PACKET2);
+                            RADEON_CP_PACKET2);
        if (r)
                return r;
 
        ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
        r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
                             CP_RB2_RPTR, CP_RB2_WPTR,
-                            0, 0xfffff, RADEON_CP_PACKET2);
+                            RADEON_CP_PACKET2);
        if (r)
                return r;
 
@@ -6390,7 +6390,7 @@ static int si_startup(struct radeon_device *rdev)
        r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
                             DMA_RB_RPTR + DMA0_REGISTER_OFFSET,
                             DMA_RB_WPTR + DMA0_REGISTER_OFFSET,
-                            2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
+                            DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
        if (r)
                return r;
 
@@ -6398,7 +6398,7 @@ static int si_startup(struct radeon_device *rdev)
        r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
                             DMA_RB_RPTR + DMA1_REGISTER_OFFSET,
                             DMA_RB_WPTR + DMA1_REGISTER_OFFSET,
-                            2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
+                            DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
        if (r)
                return r;
 
@@ -6418,7 +6418,7 @@ static int si_startup(struct radeon_device *rdev)
                if (ring->ring_size) {
                        r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
                                             UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
-                                            0, 0xfffff, RADEON_CP_PACKET2);
+                                            RADEON_CP_PACKET2);
                        if (!r)
                                r = r600_uvd_init(rdev, true);
                        if (r)