* reg offset inter mode
*/
//GPIO0A
-MUX_CFG(GPIO0A7_I2S8CHSDI_NAME, GPIO0A, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO0A6_HOSTDRVVBUS_NAME, GPIO0A, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO0A5_OTGDRVVBUS_NAME, GPIO0A, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO0A4_PWM1_NAME, GPIO0A, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO0A3_PWM0_NAME, GPIO0A, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO0A2_HDMII2CSDA_NAME, GPIO0A, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO0A1_HDMII2CSCL_NAME, GPIO0A, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO0A0_HDMIHOTPLUGIN_NAME, GPIO0A, 0, 2, 0, DEFAULT)
+MUX_CFG(GPIO0A7_I2S8CHSDI_NAME, GPIO0A, 14, 1, 0, DEFAULT)
+MUX_CFG(GPIO0A6_HOSTDRVVBUS_NAME, GPIO0A, 12, 1, 0, DEFAULT)
+MUX_CFG(GPIO0A5_OTGDRVVBUS_NAME, GPIO0A, 10, 1, 0, DEFAULT)
+MUX_CFG(GPIO0A4_PWM1_NAME, GPIO0A, 8, 1, 0, DEFAULT)
+MUX_CFG(GPIO0A3_PWM0_NAME, GPIO0A, 6, 1, 0, DEFAULT)
+MUX_CFG(GPIO0A2_HDMII2CSDA_NAME, GPIO0A, 4, 1, 0, DEFAULT)
+MUX_CFG(GPIO0A1_HDMII2CSCL_NAME, GPIO0A, 2, 1, 0, DEFAULT)
+MUX_CFG(GPIO0A0_HDMIHOTPLUGIN_NAME, GPIO0A, 0, 1, 0, DEFAULT)
//GPIO0B
-MUX_CFG(GPIO0B7_I2S8CHSDO3_NAME, GPIO0B, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO0B6_I2S8CHSDO2_NAME, GPIO0B, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO0B5_I2S8CHSDO1_NAME, GPIO0B, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO0B4_I2S8CHSDO0_NAME, GPIO0B, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO0B3_I2S8CHLRCKTX_NAME, GPIO0B, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO0B2_I2S8CHLRCKRX_NAME, GPIO0B, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO0B1_I2S8CHSCLK_NAME, GPIO0B, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO0B0_I2S8CHCLK_NAME, GPIO0B, 0, 2, 0, DEFAULT)
+MUX_CFG(GPIO0B7_I2S8CHSDO3_NAME, GPIO0B, 14, 1, 0, DEFAULT)
+MUX_CFG(GPIO0B6_I2S8CHSDO2_NAME, GPIO0B, 12, 1, 0, DEFAULT)
+MUX_CFG(GPIO0B5_I2S8CHSDO1_NAME, GPIO0B, 10, 1, 0, DEFAULT)
+MUX_CFG(GPIO0B4_I2S8CHSDO0_NAME, GPIO0B, 8, 1, 0, DEFAULT)
+MUX_CFG(GPIO0B3_I2S8CHLRCKTX_NAME, GPIO0B, 6, 1, 0, DEFAULT)
+MUX_CFG(GPIO0B2_I2S8CHLRCKRX_NAME, GPIO0B, 4, 1, 0, DEFAULT)
+MUX_CFG(GPIO0B1_I2S8CHSCLK_NAME, GPIO0B, 2, 1, 0, DEFAULT)
+MUX_CFG(GPIO0B0_I2S8CHCLK_NAME, GPIO0B, 0, 1, 0, DEFAULT)
//GPIO0C
-MUX_CFG(GPIO0C7_TRACECTL_SMCADDR3_NAME, GPIO0C, 14, 2, 0, DEFAULT)
+MUX_CFG(GPIO0C7_TRACECTL_SMCADDR3_NAME, GPIO0C, 14, 1, 0, DEFAULT)
MUX_CFG(GPIO0C6_TRACECLK_SMCADDR2_NAME, GPIO0C, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO0C5_I2S12CHSDO_NAME, GPIO0C, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO0C4_I2S12CHSDI_NAME, GPIO0C, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO0C3_I2S12CHLRCKTX_NAME, GPIO0C, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO0C2_I2S12CHLRCKRX_NAME, GPIO0C, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO0C1_I2S12CHSCLK_NAME, GPIO0C, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO0C0_I2S12CHCLK_NAME, GPIO0C, 0, 2, 0, DEFAULT)
+MUX_CFG(GPIO0C5_I2S12CHSDO_NAME, GPIO0C, 10, 1, 0, DEFAULT)
+MUX_CFG(GPIO0C4_I2S12CHSDI_NAME, GPIO0C, 8, 1, 0, DEFAULT)
+MUX_CFG(GPIO0C3_I2S12CHLRCKTX_NAME, GPIO0C, 6, 1, 0, DEFAULT)
+MUX_CFG(GPIO0C2_I2S12CHLRCKRX_NAME, GPIO0C, 4, 1, 0, DEFAULT)
+MUX_CFG(GPIO0C1_I2S12CHSCLK_NAME, GPIO0C, 2, 1, 0, DEFAULT)
+MUX_CFG(GPIO0C0_I2S12CHCLK_NAME, GPIO0C, 0, 1, 0, DEFAULT)
//GPIO0D
-MUX_CFG(GPIO0D7_PWM3_NAME, GPIO0D, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO0D6_PWM2_NAME, GPIO0D, 12, 2, 0, DEFAULT)
+MUX_CFG(GPIO0D7_PWM3_NAME, GPIO0D, 14, 1, 0, DEFAULT)
+MUX_CFG(GPIO0D6_PWM2_NAME, GPIO0D, 12, 1, 0, DEFAULT)
MUX_CFG(GPIO0D5_I2S22CHSDO_SMCADDR1_NAME, GPIO0D, 10, 2, 0, DEFAULT)
MUX_CFG(GPIO0D4_I2S22CHSDI_SMCADDR0_NAME, GPIO0D, 8, 2, 0, DEFAULT)
MUX_CFG(GPIO0D3_I2S22CHLRCKTX_SMCADVN_NAME, GPIO0D, 6, 2, 0, DEFAULT)
MUX_CFG(GPIO1A6_UART1CTSN_SPI0RXD_NAME, GPIO1A, 12, 2, 0, DEFAULT)
MUX_CFG(GPIO1A5_UART1SOUT_SPI0CLK_NAME, GPIO1A, 10, 2, 0, DEFAULT)
MUX_CFG(GPIO1A4_UART1SIN_SPI0CSN0_NAME, GPIO1A, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO1A3_UART0RTSN_NAME, GPIO1A, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO1A2_UART0CTSN_NAME, GPIO1A, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO1A1_UART0SOUT_NAME, GPIO1A, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO1A0_UART0SIN_NAME, GPIO1A, 0, 2, 0, DEFAULT)
+MUX_CFG(GPIO1A3_UART0RTSN_NAME, GPIO1A, 6, 1, 0, DEFAULT)
+MUX_CFG(GPIO1A2_UART0CTSN_NAME, GPIO1A, 4, 1, 0, DEFAULT)
+MUX_CFG(GPIO1A1_UART0SOUT_NAME, GPIO1A, 2, 1, 0, DEFAULT)
+MUX_CFG(GPIO1A0_UART0SIN_NAME, GPIO1A, 0, 1, 0, DEFAULT)
//GPIO1B
-MUX_CFG(GPIO1B7_CIFDATA11_NAME, GPIO1B, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO1B6_CIFDATA10_NAME, GPIO1B, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO1B5_CIF0DATA1_NAME, GPIO1B, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO1B4_CIF0DATA0_NAME, GPIO1B, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO1B3_CIF0CLKOUT_NAME, GPIO1B, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO1B2_SPDIFTX_NAME, GPIO1B, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO1B1_UART2SOUT_NAME, GPIO1B, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO1B0_UART2SIN_NAME, GPIO1B, 0, 2, 0, DEFAULT)
+MUX_CFG(GPIO1B7_CIFDATA11_NAME, GPIO1B, 14, 1, 0, DEFAULT)
+MUX_CFG(GPIO1B6_CIFDATA10_NAME, GPIO1B, 12, 1, 0, DEFAULT)
+MUX_CFG(GPIO1B5_CIF0DATA1_NAME, GPIO1B, 10, 1, 0, DEFAULT)
+MUX_CFG(GPIO1B4_CIF0DATA0_NAME, GPIO1B, 8, 1, 0, DEFAULT)
+MUX_CFG(GPIO1B3_CIF0CLKOUT_NAME, GPIO1B, 6, 1, 0, DEFAULT)
+MUX_CFG(GPIO1B2_SPDIFTX_NAME, GPIO1B, 4, 1, 0, DEFAULT)
+MUX_CFG(GPIO1B1_UART2SOUT_NAME, GPIO1B, 2, 1, 0, DEFAULT)
+MUX_CFG(GPIO1B0_UART2SIN_NAME, GPIO1B, 0, 1, 0, DEFAULT)
//GPIO1C
MUX_CFG(GPIO1C7_CIFDATA9_RMIIRXD0_NAME, GPIO1C, 14, 2, 0, DEFAULT)
MUX_CFG(GPIO1C0_CIF1DATA2_RMIICLKOUT_RMIICLKIN_NAME, GPIO1C, 0, 2, 0, DEFAULT)
//GPIO1D
-MUX_CFG(GPIO1D7_CIF1CLKOUT_NAME, GPIO1D, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO1D6_CIF1DATA11_NAME, GPIO1D, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO1D5_CIF1DATA10_NAME, GPIO1D, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO1D4_CIF1DATA1_NAME, GPIO1D, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO1D3_CIF1DATA0_NAME, GPIO1D, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO1D2_CIF1CLKIN_NAME, GPIO1D, 4, 2, 0, DEFAULT)
+MUX_CFG(GPIO1D7_CIF1CLKOUT_NAME, GPIO1D, 14, 1, 0, DEFAULT)
+MUX_CFG(GPIO1D6_CIF1DATA11_NAME, GPIO1D, 12, 1, 0, DEFAULT)
+MUX_CFG(GPIO1D5_CIF1DATA10_NAME, GPIO1D, 10, 1, 0, DEFAULT)
+MUX_CFG(GPIO1D4_CIF1DATA1_NAME, GPIO1D, 8, 1, 0, DEFAULT)
+MUX_CFG(GPIO1D3_CIF1DATA0_NAME, GPIO1D, 6, 1, 0, DEFAULT)
+MUX_CFG(GPIO1D2_CIF1CLKIN_NAME, GPIO1D, 4, 1, 0, DEFAULT)
MUX_CFG(GPIO1D1_CIF1HREF_MIIMDCLK_NAME, GPIO1D, 2, 2, 0, DEFAULT)
MUX_CFG(GPIO1D0_CIF1VSYNC_MIIMD_NAME, GPIO1D, 0, 2, 0, DEFAULT)
MUX_CFG(GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME, GPIO2C, 0, 2, 0, DEFAULT)
//GPIO2D
-MUX_CFG(GPIO2D7_I2C1SCL_NAME, GPIO2D, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO2D6_I2C1SDA_NAME, GPIO2D, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO2D5_I2C0SCL_NAME, GPIO2D, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO2D4_I2C0SDA_NAME, GPIO2D, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO2D3_LCDC1VSYNC_NAME, GPIO2D, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO2D2_LCDC1HSYNC_NAME, GPIO2D, 4, 2, 0, DEFAULT)
+MUX_CFG(GPIO2D7_I2C1SCL_NAME, GPIO2D, 14, 1, 0, DEFAULT)
+MUX_CFG(GPIO2D6_I2C1SDA_NAME, GPIO2D, 12, 1, 0, DEFAULT)
+MUX_CFG(GPIO2D5_I2C0SCL_NAME, GPIO2D, 10, 1, 0, DEFAULT)
+MUX_CFG(GPIO2D4_I2C0SDA_NAME, GPIO2D, 8, 1, 0, DEFAULT)
+MUX_CFG(GPIO2D3_LCDC1VSYNC_NAME, GPIO2D, 6, 1, 0, DEFAULT)
+MUX_CFG(GPIO2D2_LCDC1HSYNC_NAME, GPIO2D, 4, 1, 0, DEFAULT)
MUX_CFG(GPIO2D1_LCDC1DEN_SMCCSN1_NAME, GPIO2D, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO2D0_LCDC1DCLK_NAME, GPIO2D, 0, 2, 0, DEFAULT)
+MUX_CFG(GPIO2D0_LCDC1DCLK_NAME, GPIO2D, 0, 1, 0, DEFAULT)
//GPIO3A
-//MUX_CFG(GPIO3A7_SDMMC0WRITEPRT_NAME, GPIO3A, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO3A7_SDMMC0PWREN_NAME, GPIO3A, 14, 2, 0, DEFAULT) //Modifyed by xbw,at 2012-03-05
-
-MUX_CFG(GPIO3A6_SDMMC0RSTNOUT_NAME, GPIO3A, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO3A5_I2C4SCL_NAME, GPIO3A, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO3A4_I2C4SDA_NAME, GPIO3A, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO3A3_I2C3SCL_NAME, GPIO3A, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO3A2_I2C3SDA_NAME, GPIO3A, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO3A1_I2C2SCL_NAME, GPIO3A, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO3A0_I2C2SDA_NAME, GPIO3A, 0, 2, 0, DEFAULT)
+MUX_CFG(GPIO3A7_SDMMC0PWREN_NAME, GPIO3A, 14, 1, 0, DEFAULT) //Modifyed by xbw,at 2012-03-05
+MUX_CFG(GPIO3A6_SDMMC0RSTNOUT_NAME, GPIO3A, 12, 1, 0, DEFAULT)
+MUX_CFG(GPIO3A5_I2C4SCL_NAME, GPIO3A, 10, 1, 0, DEFAULT)
+MUX_CFG(GPIO3A4_I2C4SDA_NAME, GPIO3A, 8, 1, 0, DEFAULT)
+MUX_CFG(GPIO3A3_I2C3SCL_NAME, GPIO3A, 6, 1, 0, DEFAULT)
+MUX_CFG(GPIO3A2_I2C3SDA_NAME, GPIO3A, 4, 1, 0, DEFAULT)
+MUX_CFG(GPIO3A1_I2C2SCL_NAME, GPIO3A, 2, 1, 0, DEFAULT)
+MUX_CFG(GPIO3A0_I2C2SDA_NAME, GPIO3A, 0, 1, 0, DEFAULT)
//GPIO3B
-MUX_CFG(GPIO3B7_SDMMC0WRITEPRT_NAME, GPIO3B, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO3B6_SDMMC0DETECTN_NAME, GPIO3B, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO3B5_SDMMC0DATA3_NAME, GPIO3B, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO3B4_SDMMC0DATA2_NAME, GPIO3B, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO3B3_SDMMC0DATA1_NAME, GPIO3B, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO3B2_SDMMC0DATA0_NAME, GPIO3B, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO3B1_SDMMC0CMD_NAME, GPIO3B, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO3B0_SDMMC0CLKOUT_NAME, GPIO3B, 0, 2, 0, DEFAULT)
+MUX_CFG(GPIO3B7_SDMMC0WRITEPRT_NAME, GPIO3B, 14, 1, 0, DEFAULT)
+MUX_CFG(GPIO3B6_SDMMC0DETECTN_NAME, GPIO3B, 12, 1, 0, DEFAULT)
+MUX_CFG(GPIO3B5_SDMMC0DATA3_NAME, GPIO3B, 10, 1, 0, DEFAULT)
+MUX_CFG(GPIO3B4_SDMMC0DATA2_NAME, GPIO3B, 8, 1, 0, DEFAULT)
+MUX_CFG(GPIO3B3_SDMMC0DATA1_NAME, GPIO3B, 6, 1, 0, DEFAULT)
+MUX_CFG(GPIO3B2_SDMMC0DATA0_NAME, GPIO3B, 4, 1, 0, DEFAULT)
+MUX_CFG(GPIO3B1_SDMMC0CMD_NAME, GPIO3B, 2, 1, 0, DEFAULT)
+MUX_CFG(GPIO3B0_SDMMC0CLKOUT_NAME, GPIO3B, 0, 1, 0, DEFAULT)
//GPIO3C
-MUX_CFG(GPIO3C7_SDMMC1WRITEPRT_NAME, GPIO3C, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO3C6_SDMMC1DETECTN_NAME, GPIO3C, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO3C5_SDMMC1CLKOUT_NAME, GPIO3C, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO3C4_SDMMC1DATA3_NAME, GPIO3C, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO3C3_SDMMC1DATA2_NAME, GPIO3C, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO3C2_SDMMC1DATA1_NAME, GPIO3C, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO3C1_SDMMC1DATA0_NAME, GPIO3C, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO3C0_SMMC1CMD_NAME, GPIO3C, 0, 2, 0, DEFAULT)
+MUX_CFG(GPIO3C7_SDMMC1WRITEPRT_NAME, GPIO3C, 14, 1, 0, DEFAULT)
+MUX_CFG(GPIO3C6_SDMMC1DETECTN_NAME, GPIO3C, 12, 1, 0, DEFAULT)
+MUX_CFG(GPIO3C5_SDMMC1CLKOUT_NAME, GPIO3C, 10, 1, 0, DEFAULT)
+MUX_CFG(GPIO3C4_SDMMC1DATA3_NAME, GPIO3C, 8, 1, 0, DEFAULT)
+MUX_CFG(GPIO3C3_SDMMC1DATA2_NAME, GPIO3C, 6, 1, 0, DEFAULT)
+MUX_CFG(GPIO3C2_SDMMC1DATA1_NAME, GPIO3C, 4, 1, 0, DEFAULT)
+MUX_CFG(GPIO3C1_SDMMC1DATA0_NAME, GPIO3C, 2, 1, 0, DEFAULT)
+MUX_CFG(GPIO3C0_SMMC1CMD_NAME, GPIO3C, 0, 1, 0, DEFAULT)
//GPIO3D
MUX_CFG(GPIO3D7_FLASHDQS_EMMCCLKOUT_NAME, GPIO3D, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO3D6_UART3RTSN_NAME, GPIO3D, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO3D5_UART3CTSN_NAME, GPIO3D, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO3D4_UART3SOUT_NAME, GPIO3D, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO3D3_UART3SIN_NAME, GPIO3D, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO3D2_SDMMC1INTN_NAME, GPIO3D, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO3D1_SDMMC1BACKENDPWR_NAME, GPIO3D, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO3D0_SDMMC1PWREN_NAME, GPIO3D, 0, 2, 0, DEFAULT)
+MUX_CFG(GPIO3D6_UART3RTSN_NAME, GPIO3D, 12, 1, 0, DEFAULT)
+MUX_CFG(GPIO3D5_UART3CTSN_NAME, GPIO3D, 10, 1, 0, DEFAULT)
+MUX_CFG(GPIO3D4_UART3SOUT_NAME, GPIO3D, 8, 1, 0, DEFAULT)
+MUX_CFG(GPIO3D3_UART3SIN_NAME, GPIO3D, 6, 1, 0, DEFAULT)
+MUX_CFG(GPIO3D2_SDMMC1INTN_NAME, GPIO3D, 4, 1, 0, DEFAULT)
+MUX_CFG(GPIO3D1_SDMMC1BACKENDPWR_NAME, GPIO3D, 2, 1, 0, DEFAULT)
+MUX_CFG(GPIO3D0_SDMMC1PWREN_NAME, GPIO3D, 0, 1, 0, DEFAULT)
//GPIO4A
-MUX_CFG(GPIO4A7_FLASHDATA15_NAME, GPIO4A, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO4A6_FLASHDATA14_NAME, GPIO4A, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO4A5_FLASHDATA13_NAME, GPIO4A, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO4A4_FLASHDATA12_NAME, GPIO4A, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO4A3_FLASHDATA11_NAME, GPIO4A, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO4A2_FLASHDATA10_NAME, GPIO4A, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO4A1_FLASHDATA9_NAME, GPIO4A, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO4A0_FLASHDATA8_NAME, GPIO4A, 0, 2, 0, DEFAULT)
+MUX_CFG(GPIO4A7_FLASHDATA15_NAME, GPIO4A, 14, 1, 0, DEFAULT)
+MUX_CFG(GPIO4A6_FLASHDATA14_NAME, GPIO4A, 12, 1, 0, DEFAULT)
+MUX_CFG(GPIO4A5_FLASHDATA13_NAME, GPIO4A, 10, 1, 0, DEFAULT)
+MUX_CFG(GPIO4A4_FLASHDATA12_NAME, GPIO4A, 8, 1, 0, DEFAULT)
+MUX_CFG(GPIO4A3_FLASHDATA11_NAME, GPIO4A, 6, 1, 0, DEFAULT)
+MUX_CFG(GPIO4A2_FLASHDATA10_NAME, GPIO4A, 4, 1, 0, DEFAULT)
+MUX_CFG(GPIO4A1_FLASHDATA9_NAME, GPIO4A, 2, 1, 0, DEFAULT)
+MUX_CFG(GPIO4A0_FLASHDATA8_NAME, GPIO4A, 0, 1, 0, DEFAULT)
//GPIO4B
-MUX_CFG(GPIO4B7_SPI0CSN1_NAME, GPIO4B, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO4B6_FLASHCSN7_NAME, GPIO4B, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO4B5_FLASHCSN6_NAME, GPIO4B, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO4B4_FLASHCSN5_NAME, GPIO4B, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO4B3_FLASHCSN4_NAME, GPIO4B, 6, 2, 0, DEFAULT)
+MUX_CFG(GPIO4B7_SPI0CSN1_NAME, GPIO4B, 14, 1, 0, DEFAULT)
+MUX_CFG(GPIO4B6_FLASHCSN7_NAME, GPIO4B, 12, 1, 0, DEFAULT)
+MUX_CFG(GPIO4B5_FLASHCSN6_NAME, GPIO4B, 10, 1, 0, DEFAULT)
+MUX_CFG(GPIO4B4_FLASHCSN5_NAME, GPIO4B, 8, 1, 0, DEFAULT)
+MUX_CFG(GPIO4B3_FLASHCSN4_NAME, GPIO4B, 6, 1, 0, DEFAULT)
MUX_CFG(GPIO4B2_FLASHCSN3_EMMCRSTNOUT_NAME, GPIO4B, 4, 2, 0, DEFAULT)
MUX_CFG(GPIO4B1_FLASHCSN2_EMMCCMD_NAME, GPIO4B, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO4B0_FLASHCSN1_NAME, GPIO4B, 0, 2, 0, DEFAULT)
+MUX_CFG(GPIO4B0_FLASHCSN1_NAME, GPIO4B, 0, 1, 0, DEFAULT)
//GPIO4C
MUX_CFG(GPIO4C7_SMCDATA7_TRACEDATA7_NAME, GPIO4C, 14, 2, 0, DEFAULT)
MUX_CFG(GPIO4D0_SMCDATA8_TRACEDATA8_NAME, GPIO4D, 0, 2, 0, DEFAULT)
//GPIO6B
-MUX_CFG(GPIO6B7_TESTCLOCKOUT_NAME, GPIO6B, 14, 2, 0, DEFAULT)
+MUX_CFG(GPIO6B7_TESTCLOCKOUT_NAME, GPIO6B, 14, 1, 0, DEFAULT)
};
void rk30_mux_set(struct mux_config *cfg)
{
- int regValue;
+ int regValue = 0;
int mask;
- mask = ((1<<(cfg->interleave))-1)<<cfg->offset;
- regValue = readl(cfg->mux_reg);
- regValue &=~mask;
+ mask = ((1<<(cfg->interleave))-1)<<cfg->offset << 16;
+ //regValue = readl(cfg->mux_reg);
+ regValue |= mask;
regValue |=(cfg->mode<<cfg->offset);
- #ifdef IOMUX_DBG
+#ifdef IOMUX_DBG
printk("%s::reg=0x%p,Value=0x%x,mask=0x%x\n",__FUNCTION__,cfg->mux_reg,regValue,mask);
- #endif
- writel(regValue,cfg->mux_reg);
+#endif
+ writel_relaxed(regValue,cfg->mux_reg);
+ dsb();
return;
}
+
int __init rk30_iomux_init(void)
{
int i;
projects / firefly-linux-kernel-4.4.55.git / commitdiff