[WebAssembly] Enable SSA lowering and other pre-regalloc passes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247008 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp b/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
index 25fe846fc7f9dec7f0edaf0af643c8ccf8364af8..4950e3bbea730a4eaf1a26f1e3729d89da9ed648 100644 (file)
--- a/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
+++ b/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
@@ -164,7 +164,27 @@ bool WebAssemblyPassConfig::addILPOpts() { return true; }
 
 void WebAssemblyPassConfig::addPreRegAlloc() {}
 
-void WebAssemblyPassConfig::addRegAllocPasses(bool Optimized) {}
+void WebAssemblyPassConfig::addRegAllocPasses(bool Optimized) {
+  // This is list is derived from the regalloc pass list used in
+  // addFastRegAlloc and addOptimizedRegAlloc in lib/CodeGen/Passes.cpp. We
+  // don't run the actual register allocator, but we do run the passes which
+  // lower SSA form, so after these passes are complete, we have non-SSA
+  // virtual registers.
+
+  if (Optimized) {
+    addPass(&ProcessImplicitDefsID);
+    addPass(&LiveVariablesID);
+    addPass(&MachineLoopInfoID);
+  }
+
+  addPass(&PHIEliminationID);
+  addPass(&TwoAddressInstructionPassID, false);
+
+  if (Optimized) {
+    addPass(&RegisterCoalescerID);
+    addPass(&MachineSchedulerID);
+  }
+}
 
 void WebAssemblyPassConfig::addPostRegAlloc() {
   // FIXME: the following passes dislike virtual registers. Disable them for now

diff --git a/test/CodeGen/WebAssembly/phi.ll b/test/CodeGen/WebAssembly/phi.ll
new file mode 100644 (file)
index 0000000..c217cbf
--- /dev/null
+++ b/test/CodeGen/WebAssembly/phi.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -asm-verbose=false | FileCheck %s
+
+; Test that phis are lowered.
+
+target datalayout = "e-p:32:32-i64:64-v128:8:128-n32:64-S128"
+target triple = "wasm32-unknown-unknown"
+
+; CHECK-LABEL: test0
+; CHECK: (setlocal [[REG:@.*]] (argument 0))
+; CHECK: (setlocal [[REG]] (sdiv [[REG]] {{.*}}))
+; CHECK: (return [[REG]])
+define i32 @test0(i32 %p) {
+entry:
+  %t = icmp slt i32 %p, 0
+  br i1 %t, label %true, label %done
+true:
+  %a = sdiv i32 %p, 3
+  br label %done
+done:
+  %s = phi i32 [ %a, %true ], [ %p, %entry ]
+  ret i32 %s
+}