Added missing 'rs1' field to F3_rdrs1imm13, 'rd' to F3_rdrs1rs2.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6618 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/SparcV9/SparcV9_F3.td b/lib/Target/SparcV9/SparcV9_F3.td
index a0033d84ce1f6f457f9a0fcab072b1c2227c3a58..46b702151d3bdc98c94a11bc5ffdf05ab057c1ba 100644 (file)
--- a/lib/Target/SparcV9/SparcV9_F3.td
+++ b/lib/Target/SparcV9/SparcV9_F3.td
@@ -75,14 +75,13 @@ class F3_rdrs1 : F3_rd {
 }
 
 // F3_rdrs1simm13 - Common class of instructions that have rd, rs1, and simm13
-class F3_rdrs1simm13 : F3_rd {
+class F3_rdrs1simm13 : F3_rdrs1 {
   bits<13> simm13;
   set Inst{12-0} = simm13;
 }
 
-
 // F3_rdrs1rs2 - Common class of instructions that have rd, rs1, and rs2 fields
-class F3_rdrs1rs2 : F3_rs1 {
+class F3_rdrs1rs2 : F3_rdrs1 {
   bits<5> rs2;
   set Inst{4-0} = rs2;
 }