}
#define APIC_DFR_VALUE (APIC_DFR_FLAT)
-#define NO_BALANCE_IRQ (0)
static inline unsigned long
bigsmp_check_apicid_used(physid_mask_t bitmap, int apicid)
#define APIC_DFR_VALUE_CLUSTER (APIC_DFR_CLUSTER)
#define INT_DELIVERY_MODE_CLUSTER (dest_LowestPrio)
#define INT_DEST_MODE_CLUSTER (1) /* logical delivery broadcast to all procs */
-#define NO_BALANCE_IRQ_CLUSTER (1)
#define APIC_DFR_VALUE (APIC_DFR_FLAT)
-#define NO_BALANCE_IRQ (0)
static inline unsigned long
es7000_check_apicid_used(physid_mask_t bitmap, int apicid)
unsigned long (*check_apicid_used)(physid_mask_t bitmap, int apicid);
unsigned long (*check_apicid_present)(int apicid);
- int no_balance_irq;
- int no_ioapic_check;
-
void (*vector_allocation_domain)(int cpu, struct cpumask *retmask);
void (*init_apic_ldr)(void);
#endif
}
-#define NO_BALANCE_IRQ (0)
-
#ifdef CONFIG_X86_64
#include <asm/genapic.h>
#define init_apic_ldr (apic->init_apic_ldr)
#include <asm/genapic.h>
-#define NO_BALANCE_IRQ (apic->no_balance_irq)
#define init_apic_ldr (apic->init_apic_ldr)
#define ioapic_phys_id_map (apic->ioapic_phys_id_map)
#define setup_apic_routing (apic->setup_apic_routing)
return &CPU_MASK_ALL;
}
-#define NO_BALANCE_IRQ (1)
-
static inline unsigned long
numaq_check_apicid_used(physid_mask_t bitmap, int apicid)
{
#include <asm/smp.h>
#include <linux/gfp.h>
-#define NO_BALANCE_IRQ (0)
-
/* In clustered mode, the high nibble of APIC ID is a cluster number.
* The low nibble is a 4-bit bitmap. */
#define XAPIC_DEST_CPUS_SHIFT 4
.check_apicid_used = NULL,
.check_apicid_present = NULL,
- .no_balance_irq = 0,
- .no_ioapic_check = 0,
-
.vector_allocation_domain = flat_vector_allocation_domain,
.init_apic_ldr = flat_init_apic_ldr,
.check_apicid_used = NULL,
.check_apicid_present = NULL,
- .no_balance_irq = 0,
- .no_ioapic_check = 0,
-
.vector_allocation_domain = physflat_vector_allocation_domain,
/* not needed, but shouldn't hurt: */
.init_apic_ldr = flat_init_apic_ldr,
.check_apicid_used = NULL,
.check_apicid_present = NULL,
- .no_balance_irq = 0,
- .no_ioapic_check = 0,
-
.vector_allocation_domain = x2apic_vector_allocation_domain,
.init_apic_ldr = init_x2apic_ldr,
.check_apicid_used = NULL,
.check_apicid_present = NULL,
- .no_balance_irq = 0,
- .no_ioapic_check = 0,
-
.vector_allocation_domain = x2apic_vector_allocation_domain,
.init_apic_ldr = init_x2apic_ldr,
.check_apicid_used = NULL,
.check_apicid_present = NULL,
- .no_balance_irq = 0,
- .no_ioapic_check = 0,
-
.vector_allocation_domain = uv_vector_allocation_domain,
.init_apic_ldr = uv_init_apic_ldr,
.check_apicid_used = bigsmp_check_apicid_used,
.check_apicid_present = bigsmp_check_apicid_present,
- .no_balance_irq = NO_BALANCE_IRQ,
- .no_ioapic_check = 0,
-
.vector_allocation_domain = vector_allocation_domain,
.init_apic_ldr = init_apic_ldr,
.check_apicid_used = default_check_apicid_used,
.check_apicid_present = default_check_apicid_present,
- .no_balance_irq = NO_BALANCE_IRQ,
- .no_ioapic_check = 0,
-
.vector_allocation_domain = vector_allocation_domain,
.init_apic_ldr = init_apic_ldr,
apic->target_cpus = target_cpus_cluster;
apic->irq_delivery_mode = INT_DELIVERY_MODE_CLUSTER;
apic->irq_dest_mode = INT_DEST_MODE_CLUSTER;
- apic->no_balance_irq = NO_BALANCE_IRQ_CLUSTER;
apic->init_apic_ldr = init_apic_ldr_cluster;
.check_apicid_used = es7000_check_apicid_used,
.check_apicid_present = es7000_check_apicid_present,
- .no_balance_irq = NO_BALANCE_IRQ,
- .no_ioapic_check = 0,
-
.vector_allocation_domain = vector_allocation_domain,
.init_apic_ldr = init_apic_ldr,
.check_apicid_used = numaq_check_apicid_used,
.check_apicid_present = numaq_check_apicid_present,
- .no_balance_irq = NO_BALANCE_IRQ,
- .no_ioapic_check = 0,
-
.vector_allocation_domain = vector_allocation_domain,
.init_apic_ldr = init_apic_ldr,
.check_apicid_used = summit_check_apicid_used,
.check_apicid_present = summit_check_apicid_present,
- .no_balance_irq = NO_BALANCE_IRQ,
- .no_ioapic_check = 0,
-
.vector_allocation_domain = vector_allocation_domain,
.init_apic_ldr = init_apic_ldr,