let Inst{5-0} = funct;
}
+//===----------------------------------------------------------------------===//
+// System calls format <op|code_|funct>
+//===----------------------------------------------------------------------===//
+
+class SYS_FM<bits<6> funct>
+{
+ bits<20> code_;
+ bits<32> Inst;
+ let Inst{31-26} = 0x0;
+ let Inst{25-6} = code_;
+ let Inst{5-0} = funct;
+}
+
+//===----------------------------------------------------------------------===//
+// Break instruction format <op|code_1|funct>
+//===----------------------------------------------------------------------===//
+
+class BRK_FM<bits<6> funct>
+{
+ bits<10> code_1;
+ bits<10> code_2;
+ bits<32> Inst;
+ let Inst{31-26} = 0x0;
+ let Inst{25-16} = code_1;
+ let Inst{15-6} = code_2;
+ let Inst{5-0} = funct;
+}
+
//===----------------------------------------------------------------------===//
//
// FLOATING POINT INSTRUCTION FORMATS
def simm20 : Operand<i32> {
}
+def uimm20 : Operand<i32> {
+}
+
+def uimm10 : Operand<i32> {
+}
+
def simm16_64 : Operand<i64>;
def shamt : Operand<i32>;
let hasDelaySlot = 1;
let Defs = [RA];
}
+// Syscall
+class SYS_FT<string opstr> :
+ InstSE<(outs), (ins uimm20:$code_),
+ !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI>;
+// Break
+class BRK_FT<string opstr> :
+ InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
+ !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary, FrmOther>;
// Sync
let hasSideEffects = 1 in
def SYNC : SYNC_FT, SYNC_FM;
def TEQ : TEQ_FT<"teq", CPURegsOpnd>, TEQ_FM<0x34>;
+def BREAK : BRK_FT<"break">, BRK_FM<0xd>;
+def SYSCALL : SYS_FT<"syscall">, SYS_FM<0xc>;
+
/// Load-linked, Store-conditional
let Predicates = [NotN64, HasStdEnc] in {
def LL : LLBase<"ll", CPURegsOpnd, mem>, LW_FM<0x30>;
def : InstAlias<"beqz $rs,$offset",
(BEQ CPURegsOpnd:$rs, ZERO, brtarget:$offset), 1>,
Requires<[NotMips64]>;
+def : InstAlias<"syscall", (SYSCALL 0), 1>;
+
+def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
+def : InstAlias<"break", (BREAK 0, 0), 1>;
//===----------------------------------------------------------------------===//
// Assembler Pseudo Instructions
//===----------------------------------------------------------------------===//
.set FPU_MASK,$f7
.set r3,$3
.set f6,$f6
-#CHECK: abs.s $f6, $f7 # encoding: [0x46,0x00,0x39,0x85]
-#CHECK: and $3, $15, $15 # encoding: [0x01,0xef,0x18,0x24]
+# CHECK: abs.s $f6, $f7 # encoding: [0x46,0x00,0x39,0x85]
+# CHECK: and $3, $15, $15 # encoding: [0x01,0xef,0x18,0x24]
+# CHECK: break # encoding: [0x00,0x00,0x00,0x0d]
+# CHECK: break 7, 0 # encoding: [0x00,0x07,0x00,0x0d]
+# CHECK: break 7, 5 # encoding: [0x00,0x07,0x01,0x4d]
+# CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c]
+# CHECK: syscall 13396 # encoding: [0x00,0x0d,0x15,0x0c]
abs.s f6,FPU_MASK
and r3,$t7,STORE_MASK
+ break
+ break 7
+ break 7,5
+ syscall
+ syscall 0x3454