--- /dev/null
+CONFIG_EXPERIMENTAL=y
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_KERNEL_LZO=y
+CONFIG_LOG_BUF_SHIFT=19
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_DEBUG=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_PANIC_TIMEOUT=1
+# CONFIG_SYSCTL_SYSCALL is not set
+# CONFIG_ELF_CORE is not set
+CONFIG_ASHMEM=y
+# CONFIG_AIO is not set
+CONFIG_EMBEDDED=y
+# CONFIG_SLUB_DEBUG is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_ARCH_RK2928=y
+CONFIG_RK_CLOCK_PROC=y
+CONFIG_RK_USB_UART=y
+CONFIG_MACH_RK2928_TB=y
+CONFIG_FIQ_DEBUGGER=y
+CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
+CONFIG_FIQ_DEBUGGER_CONSOLE=y
+CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_HIGHMEM=y
+CONFIG_COMPACTION=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_IDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_WAKELOCK=y
+CONFIG_PM_RUNTIME=y
+CONFIG_PM_DEBUG=y
+CONFIG_SUSPEND_TIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM_USER=y
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_INET_ESP=y
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_IPV6=y
+CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_INET6_AH=y
+CONFIG_INET6_ESP=y
+CONFIG_INET6_IPCOMP=y
+CONFIG_IPV6_MIP6=y
+CONFIG_IPV6_TUNNEL=y
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_NETFILTER=y
+# CONFIG_BRIDGE_NETFILTER is not set
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CT_PROTO_DCCP=y
+CONFIG_NF_CT_PROTO_SCTP=y
+CONFIG_NF_CT_PROTO_UDPLITE=y
+CONFIG_NF_CONNTRACK_AMANDA=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_H323=y
+CONFIG_NF_CONNTRACK_IRC=y
+CONFIG_NF_CONNTRACK_NETBIOS_NS=y
+CONFIG_NF_CONNTRACK_PPTP=y
+CONFIG_NF_CONNTRACK_SANE=y
+CONFIG_NF_CONNTRACK_SIP=y
+CONFIG_NF_CONNTRACK_TFTP=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NETFILTER_TPROXY=y
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+CONFIG_NETFILTER_XT_TARGET_NFLOG=y
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
+CONFIG_NETFILTER_XT_TARGET_TPROXY=y
+CONFIG_NETFILTER_XT_TARGET_TRACE=y
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_HELPER=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+CONFIG_NETFILTER_XT_MATCH_LENGTH=y
+CONFIG_NETFILTER_XT_MATCH_LIMIT=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+CONFIG_NETFILTER_XT_MATCH_POLICY=y
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
+CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
+CONFIG_NETFILTER_XT_MATCH_SOCKET=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
+CONFIG_NETFILTER_XT_MATCH_STRING=y
+CONFIG_NETFILTER_XT_MATCH_TIME=y
+CONFIG_NETFILTER_XT_MATCH_U32=y
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_AH=y
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_REJECT_SKERR=y
+CONFIG_IP_NF_TARGET_LOG=y
+CONFIG_NF_NAT=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_RAW=y
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+CONFIG_IP_NF_ARP_MANGLE=y
+CONFIG_NF_CONNTRACK_IPV6=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_TARGET_LOG=y
+CONFIG_IP6_NF_FILTER=y
+CONFIG_IP6_NF_TARGET_REJECT=y
+CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
+CONFIG_IP6_NF_MANGLE=y
+CONFIG_IP6_NF_RAW=y
+CONFIG_BRIDGE=y
+# CONFIG_BRIDGE_IGMP_SNOOPING is not set
+CONFIG_PHONET=y
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_HTB=y
+CONFIG_NET_SCH_INGRESS=y
+CONFIG_NET_CLS_U32=y
+CONFIG_NET_EMATCH=y
+CONFIG_NET_EMATCH_U32=y
+CONFIG_NET_CLS_ACT=y
+CONFIG_NET_ACT_POLICE=y
+CONFIG_NET_ACT_GACT=y
+CONFIG_NET_ACT_MIRRED=y
+CONFIG_BT=y
+CONFIG_BT_L2CAP=y
+CONFIG_BT_SCO=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_HIDP=y
+CONFIG_BT_HCIUART=y
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_LL=y
+CONFIG_BT_HCIBCM4325=y
+CONFIG_BT_AUTOSLEEP=y
+CONFIG_RFKILL=y
+CONFIG_RFKILL_RK=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_RKNAND=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_MISC_DEVICES=y
+CONFIG_UID_STAT=y
+CONFIG_APANIC=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_DM=y
+CONFIG_DM_CRYPT=y
+CONFIG_DM_UEVENT=y
+CONFIG_NETDEVICES=y
+CONFIG_PHYLIB=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+CONFIG_WLAN_80211=y
+CONFIG_RKWIFI=y
+CONFIG_USB_USBNET=y
+CONFIG_PPP=y
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=y
+CONFIG_PPP_SYNC_TTY=y
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_BSDCOMP=y
+CONFIG_PPP_MPPE=y
+CONFIG_PPPOLAC=y
+CONFIG_PPPOPNS=y
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_KEYRESET=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_JOYSTICK=y
+CONFIG_JOYSTICK_XPAD=y
+CONFIG_JOYSTICK_XPAD_FF=y
+CONFIG_INPUT_TABLET=y
+CONFIG_TABLET_USB_ACECAD=y
+CONFIG_TABLET_USB_AIPTEK=y
+CONFIG_TABLET_USB_GTCO=y
+CONFIG_TABLET_USB_HANWANG=y
+CONFIG_TABLET_USB_KBTAB=y
+CONFIG_TABLET_USB_WACOM=y
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_EETI_EGALAX=y
+CONFIG_EETI_EGALAX_MAX_X=1087
+CONFIG_EETI_EGALAX_MAX_Y=800
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_KEYCHORD=y
+CONFIG_INPUT_UINPUT=y
+CONFIG_COMPASS_AK8975=y
+CONFIG_GS_MMA8452=y
+CONFIG_GYRO_L3G4200D=y
+CONFIG_LS_CM3217=y
+CONFIG_SENSOR_DEVICE=y
+CONFIG_GSENSOR_DEVICE=y
+CONFIG_COMPASS_DEVICE=y
+CONFIG_GYROSCOPE_DEVICE=y
+CONFIG_LIGHT_DEVICE=y
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_RK29=y
+CONFIG_UART0_RK29=y
+CONFIG_UART0_CTS_RTS_RK29=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C0_CONTROLLER_RK30=y
+CONFIG_I2C1_CONTROLLER_RK30=y
+CONFIG_I2C2_CONTROLLER_RK30=y
+CONFIG_ADC_RK30=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_EXPANDED_GPIO_NUM=0
+CONFIG_EXPANDED_GPIO_IRQ_NUM=0
+CONFIG_SPI_FPGA_GPIO_NUM=0
+CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
+CONFIG_POWER_SUPPLY=y
+CONFIG_TEST_POWER=y
+# CONFIG_HWMON is not set
+CONFIG_MFD_TPS65910=y
+CONFIG_MFD_TPS65090=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_TPS65910=y
+CONFIG_RK30_PWM_REGULATOR=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_VIDEO_DEV=y
+CONFIG_SOC_CAMERA=y
+CONFIG_SOC_CAMERA_OV2659=y
+CONFIG_SOC_CAMERA_OV5642=y
+CONFIG_VIDEO_RK29=y
+CONFIG_VIDEO_RK29_CAMMEM_ION=y
+CONFIG_ION=y
+CONFIG_ION_ROCKCHIP=y
+CONFIG_FB=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_DISPLAY_SUPPORT=y
+CONFIG_LCD_HSD100PXN=y
+CONFIG_FB_ROCKCHIP=y
+CONFIG_LCDC_RK2928=y
+CONFIG_RK_HDMI=y
+CONFIG_HDMI_RK2928=y
+CONFIG_RGA_RK30=y
+CONFIG_RK_LVDS=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_SOUND=y
+CONFIG_SND=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_ARM is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_RK29_SOC=y
+CONFIG_SND_I2S_DMA_EVENT_STATIC=y
+CONFIG_SND_RK_SOC_RK2928=y
+CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
+CONFIG_HID_A4TECH=y
+CONFIG_HID_ACRUX=y
+CONFIG_HID_ACRUX_FF=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_DRAGONRISE=y
+CONFIG_DRAGONRISE_FF=y
+CONFIG_HID_EMS_FF=y
+CONFIG_HID_ELECOM=y
+CONFIG_HID_EZKEY=y
+CONFIG_HID_KEYTOUCH=y
+CONFIG_HID_KYE=y
+CONFIG_HID_UCLOGIC=y
+CONFIG_HID_WALTOP=y
+CONFIG_HID_GYRATION=y
+CONFIG_HID_TWINHAN=y
+CONFIG_HID_KENSINGTON=y
+CONFIG_HID_LCPOWER=y
+CONFIG_HID_LOGITECH=y
+CONFIG_LOGITECH_FF=y
+CONFIG_LOGIRUMBLEPAD2_FF=y
+CONFIG_LOGIG940_FF=y
+CONFIG_LOGIWII_FF=y
+CONFIG_HID_MAGICMOUSE=y
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+CONFIG_HID_MULTITOUCH=y
+CONFIG_HID_NTRIG=y
+CONFIG_HID_ORTEK=y
+CONFIG_HID_PANTHERLORD=y
+CONFIG_PANTHERLORD_FF=y
+CONFIG_HID_PETALYNX=y
+CONFIG_HID_PICOLCD=y
+CONFIG_HID_QUANTA=y
+CONFIG_HID_ROCCAT_ARVO=y
+CONFIG_HID_ROCCAT_KONE=y
+CONFIG_HID_ROCCAT_KONEPLUS=y
+CONFIG_HID_ROCCAT_KOVAPLUS=y
+CONFIG_HID_ROCCAT_PYRA=y
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SONY=y
+CONFIG_HID_SUNPLUS=y
+CONFIG_HID_GREENASIA=y
+CONFIG_GREENASIA_FF=y
+CONFIG_HID_SMARTJOYPLUS=y
+CONFIG_SMARTJOYPLUS_FF=y
+CONFIG_HID_TOPSEED=y
+CONFIG_HID_THRUSTMASTER=y
+CONFIG_THRUSTMASTER_FF=y
+CONFIG_HID_WACOM=y
+CONFIG_HID_ZEROPLUS=y
+CONFIG_ZEROPLUS_FF=y
+CONFIG_HID_ZYDACRON=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_OTG_BLACKLIST_HUB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_OPTION=y
+CONFIG_USB_GADGET=y
+CONFIG_USB20_HOST=y
+CONFIG_USB20_OTG=y
+CONFIG_MMC=y
+CONFIG_MMC_UNSAFE_RESUME=y
+CONFIG_MMC_EMBEDDED_SDIO=y
+CONFIG_MMC_PARANOID_SD_INIT=y
+CONFIG_SDMMC_RK29=y
+CONFIG_SWITCH=y
+CONFIG_SWITCH_GPIO=y
+CONFIG_RTC_CLASS=y
+CONFIG_TPS65910_RTC=y
+CONFIG_STAGING=y
+CONFIG_ANDROID=y
+CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_ANDROID_LOGGER=y
+CONFIG_ANDROID_LOW_MEMORY_KILLER=y
+# CONFIG_CMMB is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_PRINTK_TIME=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_SCHEDSTATS=y
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
+CONFIG_ENABLE_DEFAULT_TRACERS=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_TWOFISH=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
--- /dev/null
+#include <linux/regulator/machine.h>
+#include <linux/i2c/twl.h>
+#include <linux/mfd/tps65910.h>
+#include <mach/sram.h>
+#include <linux/platform_device.h>
+
+#include <mach/gpio.h>
+#include <mach/iomux.h>
+
+#define gpio_readl(offset) readl_relaxed(RK2928_GPIO3_BASE + offset)
+#define gpio_writel(v, offset) do { writel_relaxed(v, RK2928_GPIO3_BASE + offset); dsb(); } while (0)
+
+#define GPIO_SWPORTA_DR 0x0000
+#define GPIO_SWPORTA_DDR 0x0004
+
+#define GPIO3_D2_OUTPUT (1<<26)
+#define GPIO3_D2_OUTPUT_HIGH (1<<26)
+#define GPIO3_D2_OUTPUT_LOW (~(1<<26))
+
+#ifdef CONFIG_MFD_TPS65910
+#define PMU_POWER_SLEEP RK2928_PIN3_PD2
+extern int platform_device_register(struct platform_device *pdev);
+
+int tps65910_pre_init(struct tps65910 *tps65910){
+
+ int val = 0;
+ int i = 0;
+ int err = -1;
+
+ printk("%s,line=%d\n", __func__,__LINE__);
+ gpio_request(PMU_POWER_SLEEP, "NULL");
+ gpio_direction_output(PMU_POWER_SLEEP, GPIO_LOW);
+
+ val = tps65910_reg_read(tps65910, TPS65910_DEVCTRL2);
+ if (val<0) {
+ printk(KERN_ERR "Unable to read TPS65910_DEVCTRL2 reg\n");
+ return val;
+ }
+ /* Set sleep state active high and allow device turn-off after PWRON long press */
+ val |= (DEVCTRL2_SLEEPSIG_POL_MASK | DEVCTRL2_PWON_LP_OFF_MASK);
+
+ err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL2, val);
+ if (err) {
+ printk(KERN_ERR "Unable to write TPS65910_DEVCTRL2 reg\n");
+ return err;
+ }
+ #if 1
+ /* set PSKIP=0 */
+ val = tps65910_reg_read(tps65910, TPS65910_DCDCCTRL);
+ if (val<0) {
+ printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
+ return val;
+ }
+
+ val &= ~DEVCTRL_DEV_OFF_MASK;
+ val &= ~DEVCTRL_DEV_SLP_MASK;
+ err = tps65910_reg_write(tps65910, TPS65910_DCDCCTRL, val);
+ if (err) {
+ printk(KERN_ERR "Unable to write TPS65910_DCDCCTRL reg\n");
+ return err;
+ }
+ #endif
+ /* Set the maxinum load current */
+ /* VDD1 */
+ val = tps65910_reg_read(tps65910, TPS65910_VDD1);
+ if (val<0) {
+ printk(KERN_ERR "Unable to read TPS65910_VDD1 reg\n");
+ return val;
+ }
+
+ val |= (1<<5); //when 1: 1.5 A
+ val |= (0x07<<2); //TSTEP[2:0] = 111 : 2.5 mV/|¨¬s(sampling 3 Mhz/5)
+ err = tps65910_reg_write(tps65910, TPS65910_VDD1, val);
+ if (err) {
+ printk(KERN_ERR "Unable to write TPS65910_VDD1 reg\n");
+ return err;
+ }
+
+ /* VDD2 */
+ val = tps65910_reg_read(tps65910, TPS65910_VDD2);
+ if (val<0) {
+ printk(KERN_ERR "Unable to read TPS65910_VDD2 reg\n");
+ return val;
+ }
+
+ val |= (1<<5); //when 1: 1.5 A
+ err = tps65910_reg_write(tps65910, TPS65910_VDD2, val);
+ if (err) {
+ printk(KERN_ERR "Unable to write TPS65910_VDD2 reg\n");
+ return err;
+ }
+
+ /* VIO */
+ val = tps65910_reg_read(tps65910, TPS65910_VIO);
+ if (val<0) {
+ printk(KERN_ERR "Unable to read TPS65910_VIO reg\n");
+ return -EIO;
+ }
+
+ val |= (1<<6); //when 01: 1.0 A
+ err = tps65910_reg_write(tps65910, TPS65910_VIO, val);
+ if (err) {
+ printk(KERN_ERR "Unable to write TPS65910_VIO reg\n");
+ return err;
+ }
+ #if 1
+ /* Mask ALL interrupts */
+ err = tps65910_reg_write(tps65910,TPS65910_INT_MSK, 0xFF);
+ if (err) {
+ printk(KERN_ERR "Unable to write TPS65910_INT_MSK reg\n");
+ return err;
+ }
+
+ err = tps65910_reg_write(tps65910, TPS65910_INT_MSK2, 0x03);
+ if (err) {
+ printk(KERN_ERR "Unable to write TPS65910_INT_MSK2 reg\n");
+ return err;
+ }
+
+ /* Set RTC Power, disable Smart Reflex in DEVCTRL_REG */
+ #if 1
+ val = 0;
+ val |= (DEVCTRL_SR_CTL_I2C_SEL_MASK);
+ err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL, val);
+ if (err) {
+ printk(KERN_ERR "Unable to write TPS65910_DEVCTRL reg\n");
+ return err;
+ }
+ printk(KERN_INFO "TPS65910 Set default voltage.\n");
+ #endif
+ #if 0
+ //read sleep control register for debug
+ for(i=0; i<6; i++)
+ {
+ err = tps65910_reg_read(tps65910, &val, TPS65910_DEVCTRL+i);
+ if (err) {
+ printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
+ return -EIO;
+ }
+ else
+ printk("%s.......is 0x%04x\n",__FUNCTION__,val);
+ }
+ #endif
+
+ #if 1
+ //sleep control register
+ /*set func when in sleep mode */
+ val = tps65910_reg_read(tps65910, TPS65910_DEVCTRL);
+ if (val<0) {
+ printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
+ return val;
+ }
+
+ val |= (1 << 1);
+ err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL, val);
+ if (err) {
+ printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
+ \n", TPS65910_VDIG1);
+ return err;
+ }
+
+ /* open ldo when in sleep mode */
+ val = tps65910_reg_read(tps65910, TPS65910_SLEEP_KEEP_LDO_ON);
+ if (val<0) {
+ printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
+ return val;
+ }
+
+ val &= 0;
+ err = tps65910_reg_write(tps65910, TPS65910_SLEEP_KEEP_LDO_ON, val);
+ if (err) {
+ printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
+ \n", TPS65910_VDIG1);
+ return err;
+ }
+
+ /*set dc mode when in sleep mode */
+ val = tps65910_reg_read(tps65910, TPS65910_SLEEP_KEEP_RES_ON);
+ if (val<0) {
+ printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
+ return val;
+ }
+
+ val |= 0xff;
+ err = tps65910_reg_write(tps65910, TPS65910_SLEEP_KEEP_RES_ON, val);
+ if (err) {
+ printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
+ \n", TPS65910_VDIG1);
+ return err;
+ }
+
+ /*close ldo when in sleep mode */
+ val = tps65910_reg_read(tps65910, TPS65910_SLEEP_SET_LDO_OFF);
+ if (val<0) {
+ printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
+ return val;
+ }
+
+ val |= 0x9B;
+ err = tps65910_reg_write(tps65910, TPS65910_SLEEP_SET_LDO_OFF, val);
+ if (err) {
+ printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
+ \n", TPS65910_VDIG1);
+ return err;
+ }
+
+ #endif
+ #if 0
+ //read sleep control register for debug
+ for(i=0; i<6; i++)
+ {
+ err = tps65910_reg_read(tps65910, &val, TPS65910_DEVCTRL+i);
+ if (err) {
+ printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
+ return -EIO;
+ }
+ else
+ printk("%s.......is 0x%4x\n",__FUNCTION__,val);
+ }
+ #endif
+ #endif
+
+ printk("%s,line=%d\n", __func__,__LINE__);
+ return 0;
+
+}
+int tps65910_post_init(struct tps65910 *tps65910)
+{
+ struct regulator *dcdc;
+ struct regulator *ldo;
+ printk("%s,line=%d\n", __func__,__LINE__);
+
+ #ifdef CONFIG_RK30_PWM_REGULATOR
+ platform_device_register(&pwm_regulator_device[0]);
+ #endif
+
+ dcdc = regulator_get(NULL, "vio"); //vcc_io
+ regulator_set_voltage(dcdc, 3300000, 3300000);
+ regulator_enable(dcdc);
+ printk("%s set vio vcc_io=%dmV end\n", __func__, regulator_get_voltage(dcdc));
+ regulator_put(dcdc);
+ udelay(100);
+
+ ldo = regulator_get(NULL, "vpll"); // vcc25
+ regulator_set_voltage(ldo, 2500000, 2500000);
+ regulator_enable(ldo);
+ printk("%s set vpll vcc25=%dmV end\n", __func__, regulator_get_voltage(ldo));
+ regulator_put(ldo);
+ udelay(100);
+
+ ldo = regulator_get(NULL, "vdig2"); // vdd12
+ regulator_set_voltage(ldo, 1200000, 1200000);
+ regulator_enable(ldo);
+ printk("%s set vdig2 vdd12=%dmV end\n", __func__, regulator_get_voltage(ldo));
+ regulator_put(ldo);
+ udelay(100);
+
+ ldo = regulator_get(NULL, "vaux33"); //vcc_tp
+ regulator_set_voltage(ldo, 3300000, 3300000);
+ regulator_enable(ldo);
+ printk("%s set vaux33 vcc_tp=%dmV end\n", __func__, regulator_get_voltage(ldo));
+ regulator_put(ldo);
+ udelay(100);
+
+ dcdc = regulator_get(NULL, "vdd_cpu"); //vdd_cpu
+ regulator_set_voltage(dcdc, 1200000, 1200000);
+ regulator_enable(dcdc);
+ printk("%s set vdd1 vdd_cpu=%dmV end\n", __func__, regulator_get_voltage(dcdc));
+ regulator_put(dcdc);
+ udelay(100);
+
+ dcdc = regulator_get(NULL, "vdd2"); //vcc_ddr
+ regulator_set_voltage(dcdc, 1200000, 1200000); // 1.5*4/5 = 1.2 and Vout=1.5v
+ regulator_enable(dcdc);
+ printk("%s set vdd2 vcc_ddr=%dmV end\n", __func__, regulator_get_voltage(dcdc));
+ regulator_put(dcdc);
+ udelay(100);
+
+ ldo = regulator_get(NULL, "vdig1"); //vcc18_cif
+ regulator_set_voltage(ldo, 1800000, 1800000);
+ regulator_enable(ldo);
+ printk("%s set vdig1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo));
+ regulator_put(ldo);
+ udelay(100);
+
+ dcdc = regulator_get(NULL, "vaux1"); //vcc28_cif
+ regulator_set_voltage(dcdc,2800000,2800000);
+ regulator_enable(dcdc);
+ printk("%s set vaux1 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(dcdc));
+ regulator_put(dcdc);
+ udelay(100);
+
+ ldo = regulator_get(NULL, "vaux2"); //vcca33
+ regulator_set_voltage(ldo, 3300000, 3300000);
+ regulator_enable(ldo);
+ printk("%s set vaux2 vcca33=%dmV end\n", __func__, regulator_get_voltage(ldo));
+ regulator_put(ldo);
+ udelay(100);
+
+ ldo = regulator_get(NULL, "vdac"); //
+ regulator_set_voltage(ldo,1800000,1800000);
+ regulator_enable(ldo);
+ printk("%s set vdac =%dmV end\n", __func__, regulator_get_voltage(ldo));
+ regulator_put(ldo);
+ udelay(100);
+
+ ldo = regulator_get(NULL, "vmmc"); //vccio_wl
+ regulator_set_voltage(ldo,3300000,3300000);
+ regulator_enable(ldo);
+ printk("%s set vmmc vccio_wl=%dmV end\n", __func__, regulator_get_voltage(ldo));
+ regulator_put(ldo);
+ udelay(100);
+
+ printk("%s,line=%d END\n", __func__,__LINE__);
+
+ return 0;
+}
+
+static struct regulator_consumer_supply tps65910_smps1_supply[] = {
+ {
+ .supply = "vdd1",
+ },
+ {
+ .supply = "vdd_cpu",
+ },
+};
+static struct regulator_consumer_supply tps65910_smps2_supply[] = {
+ {
+ .supply = "vdd2",
+ },
+
+};
+static struct regulator_consumer_supply tps65910_smps3_supply[] = {
+ {
+ .supply = "vdd3",
+ },
+};
+static struct regulator_consumer_supply tps65910_smps4_supply[] = {
+ {
+ .supply = "vio",
+ },
+};
+static struct regulator_consumer_supply tps65910_ldo1_supply[] = {
+ {
+ .supply = "vdig1",
+ },
+};
+static struct regulator_consumer_supply tps65910_ldo2_supply[] = {
+ {
+ .supply = "vdig2",
+ },
+};
+
+static struct regulator_consumer_supply tps65910_ldo3_supply[] = {
+ {
+ .supply = "vaux1",
+ },
+};
+static struct regulator_consumer_supply tps65910_ldo4_supply[] = {
+ {
+ .supply = "vaux2",
+ },
+};
+static struct regulator_consumer_supply tps65910_ldo5_supply[] = {
+ {
+ .supply = "vaux33",
+ },
+};
+static struct regulator_consumer_supply tps65910_ldo6_supply[] = {
+ {
+ .supply = "vmmc",
+ },
+};
+static struct regulator_consumer_supply tps65910_ldo7_supply[] = {
+ {
+ .supply = "vdac",
+ },
+};
+
+static struct regulator_consumer_supply tps65910_ldo8_supply[] = {
+ {
+ .supply = "vpll",
+ },
+};
+
+static struct regulator_init_data tps65910_smps1 = {
+ .constraints = {
+ .name = "VDD1",
+ .min_uV = 600000,
+ .max_uV = 1500000,
+ .apply_uV = 1,
+ .always_on = 1,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
+ .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
+
+ },
+ .num_consumer_supplies = ARRAY_SIZE(tps65910_smps1_supply),
+ .consumer_supplies = tps65910_smps1_supply,
+};
+
+/* */
+static struct regulator_init_data tps65910_smps2 = {
+ .constraints = {
+ .name = "VDD2",
+ .min_uV = 600000,
+ .max_uV = 1500000,
+ .apply_uV = 1,
+ .always_on = 1,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
+ .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
+
+ },
+ .num_consumer_supplies = ARRAY_SIZE(tps65910_smps2_supply),
+ .consumer_supplies = tps65910_smps2_supply,
+};
+
+/* */
+static struct regulator_init_data tps65910_smps3 = {
+ .constraints = {
+ .name = "VDD3",
+ .min_uV = 1000000,
+ .max_uV = 1400000,
+ .apply_uV = 1,
+ .always_on = 1,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
+ .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
+
+ },
+ .num_consumer_supplies = ARRAY_SIZE(tps65910_smps3_supply),
+ .consumer_supplies = tps65910_smps3_supply,
+};
+
+static struct regulator_init_data tps65910_smps4 = {
+ .constraints = {
+ .name = "VIO",
+ .min_uV = 1800000,
+ .max_uV = 3300000,
+ .apply_uV = 1,
+ .always_on = 1,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
+ .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
+
+ },
+ .num_consumer_supplies = ARRAY_SIZE(tps65910_smps4_supply),
+ .consumer_supplies = tps65910_smps4_supply,
+};
+static struct regulator_init_data tps65910_ldo1 = {
+ .constraints = {
+ .name = "VDIG1",
+ .min_uV = 1200000,
+ .max_uV = 2700000,
+ .apply_uV = 1,
+
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
+ .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
+
+ },
+ .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo1_supply),
+ .consumer_supplies = tps65910_ldo1_supply,
+};
+
+/* */
+static struct regulator_init_data tps65910_ldo2 = {
+ .constraints = {
+ .name = "VDIG2",
+ .min_uV = 1000000,
+ .max_uV = 1800000,
+ .apply_uV = 1,
+
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
+ .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
+
+ },
+ .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo2_supply),
+ .consumer_supplies = tps65910_ldo2_supply,
+};
+
+/* */
+static struct regulator_init_data tps65910_ldo3 = {
+ .constraints = {
+ .name = "VAUX1",
+ .min_uV = 1800000,
+ .max_uV = 3300000,
+ .apply_uV = 1,
+
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
+ .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
+
+ },
+ .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo3_supply),
+ .consumer_supplies = tps65910_ldo3_supply,
+};
+
+/* */
+static struct regulator_init_data tps65910_ldo4 = {
+ .constraints = {
+ .name = "VAUX2",
+ .min_uV = 1800000,
+ .max_uV = 3300000,
+ .apply_uV = 1,
+
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
+ .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
+
+ },
+ .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo4_supply),
+ .consumer_supplies = tps65910_ldo4_supply,
+};
+
+/* */
+static struct regulator_init_data tps65910_ldo5 = {
+ .constraints = {
+ .name = "VAUX33",
+ .min_uV = 1800000,
+ .max_uV = 3300000,
+ .apply_uV = 1,
+
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
+ .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
+
+ },
+ .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo5_supply),
+ .consumer_supplies = tps65910_ldo5_supply,
+};
+
+/* */
+static struct regulator_init_data tps65910_ldo6 = {
+ .constraints = {
+ .name = "VMMC",
+ .min_uV = 1800000,
+ .max_uV = 3300000,
+ .apply_uV = 1,
+
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
+ .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
+
+ },
+ .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo6_supply),
+ .consumer_supplies = tps65910_ldo6_supply,
+};
+
+/* */
+static struct regulator_init_data tps65910_ldo7 = {
+ .constraints = {
+ .name = "VDAC",
+ .min_uV = 1800000,
+ .max_uV = 2850000,
+ .apply_uV = 1,
+
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
+ .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
+
+ },
+ .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo7_supply),
+ .consumer_supplies = tps65910_ldo7_supply,
+};
+
+/* */
+static struct regulator_init_data tps65910_ldo8 = {
+ .constraints = {
+ .name = "VPLL",
+ .min_uV = 1000000,
+ .max_uV = 2500000,
+ .apply_uV = 1,
+ .always_on = 1,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
+ .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
+
+ },
+ .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo8_supply),
+ .consumer_supplies = tps65910_ldo8_supply,
+};
+
+void __sramfunc board_pmu_suspend(void)
+{
+ int ret;
+ ret = gpio_readl(GPIO_SWPORTA_DDR);
+ gpio_writel(ret | GPIO3_D2_OUTPUT, GPIO_SWPORTA_DDR);
+ ret = gpio_readl(GPIO_SWPORTA_DR);
+ gpio_writel(ret | GPIO3_D2_OUTPUT_HIGH, GPIO_SWPORTA_DR); //set pmu_sleep output high
+}
+void __sramfunc board_pmu_resume(void)
+{
+ int ret;
+ ret = gpio_readl(GPIO_SWPORTA_DDR);
+ gpio_writel(ret | GPIO3_D2_OUTPUT, GPIO_SWPORTA_DDR);
+ ret = gpio_readl(GPIO_SWPORTA_DR);
+ gpio_writel(ret & GPIO3_D2_OUTPUT_LOW, GPIO_SWPORTA_DR); //set pmu_sleep output low
+ sram_udelay(2000);
+}
+
+static struct tps65910_board tps65910_data = {
+ .irq = (unsigned)TPS65910_HOST_IRQ,
+ .irq_base = NR_GIC_IRQS + NR_GPIO_IRQS,
+ .gpio_base = TPS65910_GPIO_EXPANDER_BASE,
+
+ .pre_init = tps65910_pre_init,
+ .post_init = tps65910_post_init,
+
+ //TPS65910_NUM_REGS = 13
+ // Regulators
+ .tps65910_pmic_init_data[TPS65910_REG_VRTC] = NULL,
+ .tps65910_pmic_init_data[TPS65910_REG_VIO] = &tps65910_smps4,
+ .tps65910_pmic_init_data[TPS65910_REG_VDD1] = &tps65910_smps1,
+ .tps65910_pmic_init_data[TPS65910_REG_VDD2] = &tps65910_smps2,
+ .tps65910_pmic_init_data[TPS65910_REG_VDD3] = &tps65910_smps3,
+ .tps65910_pmic_init_data[TPS65910_REG_VDIG1] = &tps65910_ldo1,
+ .tps65910_pmic_init_data[TPS65910_REG_VDIG2] = &tps65910_ldo2,
+ .tps65910_pmic_init_data[TPS65910_REG_VPLL] = &tps65910_ldo8,
+ .tps65910_pmic_init_data[TPS65910_REG_VDAC] = &tps65910_ldo7,
+ .tps65910_pmic_init_data[TPS65910_REG_VAUX1] = &tps65910_ldo3,
+ .tps65910_pmic_init_data[TPS65910_REG_VAUX2] = &tps65910_ldo4,
+ .tps65910_pmic_init_data[TPS65910_REG_VAUX33] = &tps65910_ldo5,
+ .tps65910_pmic_init_data[TPS65910_REG_VMMC] = &tps65910_ldo6,
+
+
+};
+
+#endif
+
--- /dev/null
+/* arch/arm/mach-rk2928/board-rk2928-fpga.c
+ *
+ * Copyright (C) 2012 ROCKCHIP, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/input.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/skbuff.h>
+#include <linux/spi/spi.h>
+#include <linux/mmc/host.h>
+#include <linux/ion.h>
+#include <linux/cpufreq.h>
+#include <linux/clk.h>
+
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/flash.h>
+#include <asm/hardware/gic.h>
+#include <mach/dvfs.h>
+
+#include <mach/board.h>
+#include <mach/hardware.h>
+#include <mach/io.h>
+#include <mach/gpio.h>
+#include <mach/iomux.h>
+#include <linux/fb.h>
+#include <linux/regulator/machine.h>
+#include <linux/rfkill-rk.h>
+#include <linux/sensor-dev.h>
+#include <linux/mfd/tps65910.h>
+#include <linux/regulator/rk29-pwm-regulator.h>
+#if defined(CONFIG_HDMI_RK30)
+ #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
+#endif
+
+#if defined(CONFIG_SPIM_RK29)
+#include "../../../drivers/spi/rk29_spim.h"
+#endif
+#if defined(CONFIG_GPS_RK)
+#include "../../../drivers/misc/gps/rk_gps/rk_gps.h"
+#endif
+
+
+#ifdef CONFIG_THREE_FB_BUFFER
+#define RK30_FB0_MEM_SIZE 12*SZ_1M
+#else
+#define RK30_FB0_MEM_SIZE 8*SZ_1M
+#endif
+
+#include "board-rk2928-sdk-camera.c"
+#include "board-rk2928-sdk-key.c"
+
+#if defined (CONFIG_EETI_EGALAX)
+#define TOUCH_RESET_PIN RK2928_PIN3_PC3
+#define TOUCH_INT_PIN RK2928_PIN3_PC7
+
+static int EETI_EGALAX_init_platform_hw(void)
+{
+ if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
+ gpio_free(TOUCH_RESET_PIN);
+ printk("p1003_init_platform_hw gpio_request error\n");
+ return -EIO;
+ }
+
+ if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
+ gpio_free(TOUCH_INT_PIN);
+ printk("p1003_init_platform_hw gpio_request error\n");
+ return -EIO;
+ }
+ gpio_pull_updown(TOUCH_INT_PIN, 1);
+ gpio_direction_output(TOUCH_RESET_PIN, 0);
+ msleep(500);
+ gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
+ msleep(500);
+ gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
+
+ return 0;
+}
+
+
+static struct eeti_egalax_platform_data eeti_egalax_info = {
+ .model= 1003,
+ .init_platform_hw= EETI_EGALAX_init_platform_hw,
+ .standby_pin = INVALID_GPIO,
+ //.standby_value = GPIO_HIGH,
+ .disp_on_pin = INVALID_GPIO,
+ //.disp_on_value = GPIO_HIGH,
+};
+#endif
+
+static struct spi_board_info board_spi_devices[] = {
+};
+
+/***********************************************************
+* rk30 backlight
+************************************************************/
+#ifdef CONFIG_BACKLIGHT_RK29_BL
+#define PWM_ID 0
+#define PWM_MUX_NAME GPIO0D2_PWM_0_NAME
+#define PWM_MUX_MODE GPIO0D_PWM_0
+#define PWM_MUX_MODE_GPIO GPIO0D_GPIO0D2
+#define PWM_GPIO RK2928_PIN0_PD2
+#define PWM_EFFECT_VALUE 1
+
+#define LCD_DISP_ON_PIN
+
+#ifdef LCD_DISP_ON_PIN
+
+#define BL_EN_PIN RK2928_PIN3_PC4
+#define BL_EN_VALUE GPIO_HIGH
+#endif
+static int rk29_backlight_io_init(void)
+{
+ int ret = 0;
+ rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
+#ifdef LCD_DISP_ON_PIN
+ // rk30_mux_api_set(BL_EN_MUX_NAME, BL_EN_MUX_MODE);
+
+ ret = gpio_request(BL_EN_PIN, NULL);
+ if (ret != 0) {
+ gpio_free(BL_EN_PIN);
+ }
+
+ gpio_direction_output(BL_EN_PIN, 0);
+ gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
+#endif
+ return ret;
+}
+
+static int rk29_backlight_io_deinit(void)
+{
+ int ret = 0;
+#ifdef LCD_DISP_ON_PIN
+ gpio_free(BL_EN_PIN);
+#endif
+ rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
+ return ret;
+}
+
+static int rk29_backlight_pwm_suspend(void)
+{
+ int ret = 0;
+ rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
+ if (gpio_request(PWM_GPIO, NULL)) {
+ printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
+ return -1;
+ }
+ gpio_direction_output(PWM_GPIO, GPIO_LOW);
+#ifdef LCD_DISP_ON_PIN
+ gpio_direction_output(BL_EN_PIN, 0);
+ gpio_set_value(BL_EN_PIN, !BL_EN_VALUE);
+#endif
+
+ return ret;
+}
+
+static int rk29_backlight_pwm_resume(void)
+{
+ gpio_free(PWM_GPIO);
+ rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
+#ifdef LCD_DISP_ON_PIN
+ msleep(30);
+ gpio_direction_output(BL_EN_PIN, 1);
+ gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
+#endif
+ return 0;
+}
+
+static struct rk29_bl_info rk29_bl_info = {
+ .pwm_id = PWM_ID,
+ .bl_ref = PWM_EFFECT_VALUE,
+ .io_init = rk29_backlight_io_init,
+ .io_deinit = rk29_backlight_io_deinit,
+ .pwm_suspend = rk29_backlight_pwm_suspend,
+ .pwm_resume = rk29_backlight_pwm_resume,
+};
+
+static struct platform_device rk29_device_backlight = {
+ .name = "rk29_backlight",
+ .id = -1,
+ .dev = {
+ .platform_data = &rk29_bl_info,
+ }
+};
+
+#endif
+
+/*MMA8452 gsensor*/
+#if defined (CONFIG_GS_MMA8452)
+
+static int mma8452_init_platform_hw(void)
+{
+ return 0;
+}
+
+static struct sensor_platform_data mma8452_info = {
+ .type = SENSOR_TYPE_ACCEL,
+ .irq_enable = 1,
+ .poll_delay_ms = 30,
+ .init_platform_hw = mma8452_init_platform_hw,
+ .orientation = {-1, 0, 0, 0, 0, 1, 0, -1, 0},
+};
+#endif
+#if defined (CONFIG_COMPASS_AK8975)
+static struct sensor_platform_data akm8975_info =
+{
+ .type = SENSOR_TYPE_COMPASS,
+ .irq_enable = 1,
+ .poll_delay_ms = 30,
+ .m_layout =
+ {
+ {
+ {1, 0, 0},
+ {0, 1, 0},
+ {0, 0, 1},
+ },
+
+ {
+ {1, 0, 0},
+ {0, 1, 0},
+ {0, 0, 1},
+ },
+
+ {
+ {1, 0, 0},
+ {0, 1, 0},
+ {0, 0, 1},
+ },
+
+ {
+ {1, 0, 0},
+ {0, 1, 0},
+ {0, 0, 1},
+ },
+ }
+};
+
+#endif
+
+#if defined(CONFIG_GYRO_L3G4200D)
+
+#include <linux/l3g4200d.h>
+
+static int l3g4200d_init_platform_hw(void)
+{
+ return 0;
+}
+
+static struct sensor_platform_data l3g4200d_info = {
+ .type = SENSOR_TYPE_GYROSCOPE,
+ .irq_enable = 1,
+ .poll_delay_ms = 30,
+ .orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
+ .init_platform_hw = l3g4200d_init_platform_hw,
+ .x_min = 40,//x_min,y_min,z_min = (0-100) according to hardware
+ .y_min = 40,
+ .z_min = 20,
+};
+
+#endif
+
+#ifdef CONFIG_LS_CM3217
+static struct sensor_platform_data cm3217_info = {
+ .type = SENSOR_TYPE_LIGHT,
+ .irq_enable = 0,
+ .poll_delay_ms = 500,
+};
+
+#endif
+
+#ifdef CONFIG_FB_ROCKCHIP
+
+#define LCD_CABC_MUX_NAME GPIO2D1_LCDC0_D23_LCDC1_D23_NAME
+#define LCD_CABC_GPIO_MODE GPIO2D_GPIO2D1
+
+#define LCD_CABC_EN RK2928_PIN2_PD1
+#define LCD_CABC_EN_VALUE GPIO_HIGH
+
+static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
+{
+ int ret = 0;
+
+ rk30_mux_api_set(LCD_CABC_MUX_NAME, LCD_CABC_GPIO_MODE);
+
+ ret = gpio_request(LCD_CABC_EN, NULL);
+ if (ret != 0)
+ {
+ gpio_free(LCD_CABC_EN);
+ printk(KERN_ERR "request lcd cabc en pin fail!\n");
+ return -1;
+ }
+ else
+ {
+ gpio_direction_output(LCD_CABC_EN, !LCD_CABC_EN_VALUE); //disable
+ }
+ return 0;
+}
+static int rk_fb_io_disable(void)
+{
+ return 0;
+}
+static int rk_fb_io_enable(void)
+{
+ return 0;
+}
+
+#if defined(CONFIG_LCDC_RK2928)
+struct rk29fb_info lcdc_screen_info = {
+ .prop = PRMRY, //primary display device
+ .io_init = rk_fb_io_init,
+ .io_disable = rk_fb_io_disable,
+ .io_enable = rk_fb_io_enable,
+ .set_screen_info = set_lcd_info,
+};
+#endif
+
+static struct resource resource_fb[] = {
+ [0] = {
+ .name = "fb0 buf",
+ .start = 0,
+ .end = 0,//RK30_FB0_MEM_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .name = "ipp buf", //for rotate
+ .start = 0,
+ .end = 0,//RK30_FB0_MEM_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [2] = {
+ .name = "fb2 buf",
+ .start = 0,
+ .end = 0,//RK30_FB0_MEM_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device device_fb = {
+ .name = "rk-fb",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(resource_fb),
+ .resource = resource_fb,
+};
+#endif
+
+//LCDC
+#ifdef CONFIG_LCDC_RK2928
+static struct resource resource_lcdc[] = {
+ [0] = {
+ .name = "lcdc reg",
+ .start = RK2928_LCDC_PHYS,
+ .end = RK2928_LCDC_PHYS + RK2928_LCDC_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+
+ [1] = {
+ .name = "lcdc irq",
+ .start = IRQ_LCDC,
+ .end = IRQ_LCDC,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device device_lcdc = {
+ .name = "rk2928-lcdc",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(resource_lcdc),
+ .resource = resource_lcdc,
+ .dev = {
+ .platform_data = &lcdc_screen_info,
+ },
+};
+#endif
+
+#ifdef CONFIG_ION
+#define ION_RESERVE_SIZE (80 * SZ_1M)
+static struct ion_platform_data rk30_ion_pdata = {
+ .nr = 1,
+ .heaps = {
+ {
+ .type = ION_HEAP_TYPE_CARVEOUT,
+ .id = ION_NOR_HEAP_ID,
+ .name = "norheap",
+ .size = ION_RESERVE_SIZE,
+ }
+ },
+};
+
+static struct platform_device device_ion = {
+ .name = "ion-rockchip",
+ .id = 0,
+ .dev = {
+ .platform_data = &rk30_ion_pdata,
+ },
+};
+#endif
+
+#ifdef CONFIG_RK30_PWM_REGULATOR
+const static int pwm_voltage_map[] = {
+ 1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000, 1375000, 1400000
+};
+
+static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
+ {
+ .supply = "vdd_core",
+ }
+};
+
+struct regulator_init_data pwm_regulator_init_dcdc[1] =
+{
+ {
+ .constraints = {
+ .name = "PWM_DCDC1",
+ .min_uV = 600000,
+ .max_uV = 1800000, //0.6-1.8V
+ .apply_uV = true,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
+ .consumer_supplies = pwm_dcdc1_consumers,
+ },
+};
+
+static struct pwm_platform_data pwm_regulator_info[1] = {
+ {
+ .pwm_id = 2,
+ .pwm_gpio = RK2928_PIN0_PD4,
+ .pwm_iomux_name = GPIO0D4_PWM_2_NAME,
+ .pwm_iomux_pwm = GPIO0D_PWM_2,
+ .pwm_iomux_gpio = GPIO0D_GPIO0D4,
+ .pwm_voltage = 1200000,
+ .suspend_voltage = 1050000,
+ .min_uV = 1000000,
+ .max_uV = 1400000,
+ .coefficient = 455, //45.5%
+ .pwm_voltage_map = pwm_voltage_map,
+ .init_data = &pwm_regulator_init_dcdc[0],
+ },
+};
+
+struct platform_device pwm_regulator_device[1] = {
+ {
+ .name = "pwm-voltage-regulator",
+ .id = 0,
+ .dev = {
+ .platform_data = &pwm_regulator_info[0],
+ }
+ },
+};
+#endif
+/**************************************************************************************************
+ * SDMMC devices, include the module of SD,MMC,and sdio.noted by xbw at 2012-03-05
+**************************************************************************************************/
+#ifdef CONFIG_SDMMC_RK29
+#include "board-rk2928-sdk-sdmmc.c"
+
+#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
+#define SDMMC0_WRITE_PROTECT_PIN RK2928_PIN1_PA7 //According to your own project to set the value of write-protect-pin.
+#endif
+
+#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
+#define SDMMC1_WRITE_PROTECT_PIN RK2928_PIN0_PD5 //According to your own project to set the value of write-protect-pin.
+#endif
+
+#define RK29SDK_WIFI_SDIO_CARD_DETECT_N RK2928_PIN0_PB2
+
+#endif //endif ---#ifdef CONFIG_SDMMC_RK29
+
+#ifdef CONFIG_SDMMC0_RK29
+static int rk29_sdmmc0_cfg_gpio(void)
+{
+ rk29_sdmmc_set_iomux(0, 0xFFFF);
+
+ rk30_mux_api_set(GPIO1C1_MMC0_DETN_NAME, GPIO1C_MMC0_DETN);
+
+#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
+ gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
+ gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
+#endif
+
+ return 0;
+}
+
+#define CONFIG_SDMMC0_USE_DMA
+struct rk29_sdmmc_platform_data default_sdmmc0_data = {
+ .host_ocr_avail =
+ (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
+ MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
+ MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
+ .host_caps =
+ (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
+ .io_init = rk29_sdmmc0_cfg_gpio,
+
+#if !defined(CONFIG_SDMMC_RK29_OLD)
+ .set_iomux = rk29_sdmmc_set_iomux,
+#endif
+
+ .dma_name = "sd_mmc",
+#ifdef CONFIG_SDMMC0_USE_DMA
+ .use_dma = 1,
+#else
+ .use_dma = 0,
+#endif
+ .detect_irq = RK2928_PIN1_PC1, // INVALID_GPIO
+ .enable_sd_wakeup = 0,
+
+#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
+ .write_prt = SDMMC0_WRITE_PROTECT_PIN,
+#else
+ .write_prt = INVALID_GPIO,
+#endif
+};
+#endif // CONFIG_SDMMC0_RK29
+
+#ifdef CONFIG_SDMMC1_RK29
+#define CONFIG_SDMMC1_USE_DMA
+static int rk29_sdmmc1_cfg_gpio(void)
+{
+#if defined(CONFIG_SDMMC_RK29_OLD)
+ rk30_mux_api_set(GPIO0B0_MMC1_CMD_NAME, GPIO0B_MMC1_CMD);
+ rk30_mux_api_set(GPIO0B1_MMC1_CLKOUT_NAME, GPIO0B_MMC1_CLKOUT);
+ rk30_mux_api_set(GPIO0B3_MMC1_D0_NAME, GPIO0B_MMC1_D0);
+ rk30_mux_api_set(GPIO0B4_MMC1_D1_NAME, GPIO0B_MMC1_D1);
+ rk30_mux_api_set(GPIO0B5_MMC1_D2_NAME, GPIO0B_MMC1_D2);
+ rk30_mux_api_set(GPIO0B6_MMC1_D3_NAME, GPIO0B_MMC1_D3);
+ //rk30_mux_api_set(GPIO0B2_MMC1_DETN_NAME, GPIO0B_MMC1_DETN);
+
+#else
+
+#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
+ gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
+ gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
+#endif
+
+#endif
+
+ return 0;
+}
+
+struct rk29_sdmmc_platform_data default_sdmmc1_data = {
+ .host_ocr_avail =
+ (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
+ MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
+ MMC_VDD_33_34),
+
+#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
+ .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
+ MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
+#else
+ .host_caps =
+ (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
+#endif
+
+ .io_init = rk29_sdmmc1_cfg_gpio,
+
+#if !defined(CONFIG_SDMMC_RK29_OLD)
+ .set_iomux = rk29_sdmmc_set_iomux,
+#endif
+
+ .dma_name = "sdio",
+#ifdef CONFIG_SDMMC1_USE_DMA
+ .use_dma = 1,
+#else
+ .use_dma = 0,
+#endif
+
+#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
+#ifdef CONFIG_WIFI_CONTROL_FUNC
+ .status = rk29sdk_wifi_status,
+ .register_status_notify = rk29sdk_wifi_status_register,
+#endif
+#if 0
+ .detect_irq = RK29SDK_WIFI_SDIO_CARD_DETECT_N,
+#endif
+
+#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
+ .write_prt = SDMMC1_WRITE_PROTECT_PIN,
+#else
+ .write_prt = INVALID_GPIO,
+#endif
+
+#else
+ .detect_irq = INVALID_GPIO,
+ .enable_sd_wakeup = 0,
+#endif
+
+};
+#endif //endif--#ifdef CONFIG_SDMMC1_RK29
+
+/**************************************************************************************************
+ * the end of setting for SDMMC devices
+**************************************************************************************************/
+
+
+
+#ifdef CONFIG_RFKILL_RK
+// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
+static struct rfkill_rk_platform_data rfkill_rk_platdata = {
+ .type = RFKILL_TYPE_BLUETOOTH,
+
+ .poweron_gpio = { // BT_REG_ON
+ .io = INVALID_GPIO,
+ .enable = GPIO_HIGH,
+ .iomux = {
+ .name = NULL,
+ },
+ },
+
+ .reset_gpio = { // BT_RST
+ .io = RK2928_PIN3_PD5, // set io to INVALID_GPIO for disable it
+ .enable = GPIO_LOW,
+ .iomux = {
+ .name = NULL,
+ },
+ },
+
+ .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
+ .io = RK2928_PIN0_PC6, // set io to INVALID_GPIO for disable it
+ .enable = GPIO_HIGH,
+ .iomux = {
+ .name = NULL,
+ },
+ },
+
+ .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
+ .gpio = {
+ .io = RK2928_PIN0_PC5, // set io to INVALID_GPIO for disable it
+ .enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
+ .iomux = {
+ .name = NULL,
+ },
+ },
+ },
+
+ .rts_gpio = { // UART_RTS, enable or disable BT's data coming
+ .io = RK2928_PIN0_PC3, // set io to INVALID_GPIO for disable it
+ .enable = GPIO_LOW,
+ .iomux = {
+ .name = GPIO0C3_UART0_CTSN_NAME,
+ .fgpio = GPIO0C_GPIO0C3,
+ .fmux = GPIO0C_UART0_CTSN,
+ },
+ },
+};
+
+static struct platform_device device_rfkill_rk = {
+ .name = "rfkill_rk",
+ .id = -1,
+ .dev = {
+ .platform_data = &rfkill_rk_platdata,
+ },
+};
+#endif
+
+#ifdef CONFIG_SND_SOC_RK2928
+static struct resource resources_acodec[] = {
+ {
+ .start = RK2928_ACODEC_PHYS,
+ .end = RK2928_ACODEC_PHYS + RK2928_ACODEC_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = RK2928_PIN3_PD4,
+ .end = RK2928_PIN3_PD4,
+ .flags = IORESOURCE_IO,
+ },
+};
+
+static struct platform_device device_acodec = {
+ .name = "rk2928-codec",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(resources_acodec),
+ .resource = resources_acodec,
+};
+#endif
+
+#if defined(CONFIG_GPS_RK)
+int rk_gps_io_init(void)
+{
+ printk("%s \n", __FUNCTION__);
+ rk30_mux_api_set(GPIO1B1_SPI_TXD_UART1_SOUT_NAME, GPIO1B_GPIO1B1);//VCC_EN
+ gpio_request(RK2928_PIN1_PB1, NULL);
+ gpio_direction_output(RK2928_PIN1_PB1, GPIO_LOW);
+
+ rk30_mux_api_set(GPIO1A2_I2S_LRCKRX_GPS_CLK_NAME, GPIO1A_GPS_CLK);//GPS_CLK
+ rk30_mux_api_set(GPIO1A4_I2S_SDO_GPS_MAG_NAME, GPIO1A_GPS_MAG);//GPS_MAG
+ rk30_mux_api_set(GPIO1A5_I2S_SDI_GPS_SIGN_NAME, GPIO1A_GPS_SIGN);//GPS_SIGN
+
+ rk30_mux_api_set(GPIO1B0_SPI_CLK_UART1_CTSN_NAME, GPIO1B_GPIO1B0);//SPI_CLK
+ gpio_request(RK2928_PIN1_PB0, NULL);
+ gpio_direction_output(RK2928_PIN1_PB0, GPIO_LOW);
+
+ rk30_mux_api_set(GPIO1B2_SPI_RXD_UART1_SIN_NAME, GPIO1B_GPIO1B2);//SPI_MOSI
+ gpio_request(RK2928_PIN1_PB2, NULL);
+ gpio_direction_output(RK2928_PIN1_PB2, GPIO_LOW);
+
+ rk30_mux_api_set(GPIO1B3_SPI_CSN0_UART1_RTSN_NAME, GPIO1B_GPIO1B3);//SPI_CS
+ gpio_request(RK2928_PIN1_PB3, NULL);
+ gpio_direction_output(RK2928_PIN1_PB3, GPIO_LOW);
+ return 0;
+}
+int rk_gps_power_up(void)
+{
+ printk("%s \n", __FUNCTION__);
+
+ return 0;
+}
+
+int rk_gps_power_down(void)
+{
+ printk("%s \n", __FUNCTION__);
+
+ return 0;
+}
+
+int rk_gps_reset_set(int level)
+{
+ return 0;
+}
+int rk_enable_hclk_gps(void)
+{
+ printk("%s \n", __FUNCTION__);
+ clk_enable(clk_get(NULL, "aclk_gps"));
+ return 0;
+}
+int rk_disable_hclk_gps(void)
+{
+ printk("%s \n", __FUNCTION__);
+ clk_disable(clk_get(NULL, "aclk_gps"));
+ return 0;
+}
+struct rk_gps_data rk_gps_info = {
+ .io_init = rk_gps_io_init,
+ .power_up = rk_gps_power_up,
+ .power_down = rk_gps_power_down,
+ .reset = rk_gps_reset_set,
+ .enable_hclk_gps = rk_enable_hclk_gps,
+ .disable_hclk_gps = rk_disable_hclk_gps,
+ .GpsSign = RK2928_PIN1_PA5,
+ .GpsMag = RK2928_PIN1_PA4, //GPIO index
+ .GpsClk = RK2928_PIN1_PA2, //GPIO index
+ .GpsVCCEn = RK2928_PIN1_PB1, //GPIO index
+ .GpsSpi_CSO = RK2928_PIN1_PB3, //GPIO index
+ .GpsSpiClk = RK2928_PIN1_PB0, //GPIO index
+ .GpsSpiMOSI = RK2928_PIN1_PB2, //GPIO index
+ .GpsIrq = IRQ_GPS,
+ .GpsSpiEn = 1,
+ .GpsAdcCh = 2,
+ .u32GpsPhyAddr = RK2928_GPS_PHYS,
+ .u32GpsPhySize = RK2928_GPS_SIZE,
+};
+
+struct platform_device rk_device_gps = {
+ .name = "gps_hv5820b",
+ .id = -1,
+ .dev = {
+ .platform_data = &rk_gps_info,
+ }
+ };
+#endif
+
+
+static struct platform_device *devices[] __initdata = {
+#ifdef CONFIG_FB_ROCKCHIP
+ &device_fb,
+#endif
+#ifdef CONFIG_LCDC_RK2928
+ &device_lcdc,
+#endif
+#ifdef CONFIG_BACKLIGHT_RK29_BL
+ &rk29_device_backlight,
+#endif
+#ifdef CONFIG_ION
+ &device_ion,
+#endif
+#ifdef CONFIG_WIFI_CONTROL_FUNC
+ &rk29sdk_wifi_device,
+#endif
+#ifdef CONFIG_RFKILL_RK
+ &device_rfkill_rk,
+#endif
+#ifdef CONFIG_SND_SOC_RK2928
+ &device_acodec,
+#endif
+#ifdef CONFIG_GPS_RK
+ &rk_device_gps,
+#endif
+
+};
+//i2c
+#ifdef CONFIG_I2C0_RK30
+static struct i2c_board_info __initdata i2c0_info[] = {
+#if defined (CONFIG_GS_MMA8452)
+ {
+ .type = "gs_mma8452",
+ .addr = 0x1d,
+ .flags = 0,
+ .irq = RK2928_PIN3_PD1,
+ .platform_data = &mma8452_info,
+ },
+#endif
+#if defined (CONFIG_COMPASS_AK8975)
+ {
+ .type = "ak8975",
+ .addr = 0x0d,
+ .flags = 0,
+ .irq = RK2928_PIN3_PD2,
+ .platform_data = &akm8975_info,
+ },
+#endif
+#if defined (CONFIG_GYRO_L3G4200D)
+ {
+ .type = "l3g4200d_gryo",
+ .addr = 0x69,
+ .flags = 0,
+ .irq = RK2928_PIN3_PD3,
+ .platform_data = &l3g4200d_info,
+ },
+#endif
+};
+#endif
+#ifdef CONFIG_I2C1_RK30
+#ifdef CONFIG_MFD_TPS65910
+#define TPS65910_HOST_IRQ RK2928_PIN3_PC6
+#include "board-rk2928-tb-tps65910.c"
+#endif
+static struct i2c_board_info __initdata i2c1_info[] = {
+
+#if defined (CONFIG_MFD_TPS65910)
+ {
+ .type = "tps65910",
+ .addr = TPS65910_I2C_ID0,
+ .flags = 0,
+ .irq = TPS65910_HOST_IRQ,
+ .platform_data = &tps65910_data,
+ },
+#endif
+
+};
+#endif
+#ifdef CONFIG_I2C2_RK30
+static struct i2c_board_info __initdata i2c2_info[] = {
+#if defined (CONFIG_EETI_EGALAX)
+ {
+ .type = "egalax_i2c",
+ .addr = 0x04,
+ .flags = 0,
+ .irq = RK2928_PIN3_PC7,
+ .platform_data = &eeti_egalax_info,
+ },
+#endif
+#if defined (CONFIG_LS_CM3217)
+ {
+ .type = "lightsensor",
+ .addr = 0x10,
+ .flags = 0,
+ .platform_data = &cm3217_info,
+ },
+#endif
+};
+#endif
+#ifdef CONFIG_I2C3_RK30
+static struct i2c_board_info __initdata i2c3_info[] = {
+};
+#endif
+#ifdef CONFIG_I2C_GPIO_RK30
+#define I2C_SDA_PIN INVALID_GPIO //set sda_pin here
+#define I2C_SCL_PIN INVALID_GPIO //set scl_pin here
+static int rk30_i2c_io_init(void)
+{
+ //set iomux (gpio) here
+
+ return 0;
+}
+struct i2c_gpio_platform_data default_i2c_gpio_data = {
+ .sda_pin = I2C_SDA_PIN,
+ .scl_pin = I2C_SCL_PIN,
+ .udelay = 5, // clk = 500/udelay = 100Khz
+ .timeout = 100,//msecs_to_jiffies(100),
+ .bus_num = 5,
+ .io_init = rk30_i2c_io_init,
+};
+static struct i2c_board_info __initdata i2c_gpio_info[] = {
+};
+#endif
+static void __init rk30_i2c_register_board_info(void)
+{
+#ifdef CONFIG_I2C0_RK30
+ i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
+#endif
+#ifdef CONFIG_I2C1_RK30
+ i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
+#endif
+#ifdef CONFIG_I2C2_RK30
+ i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
+#endif
+#ifdef CONFIG_I2C3_RK30
+ i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
+#endif
+#ifdef CONFIG_I2C_GPIO_RK30
+ i2c_register_board_info(4, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
+#endif
+}
+//end of i2c
+
+#define POWER_ON_PIN RK2928_PIN3_PC5 //power_hold
+static void rk2928_pm_power_off(void)
+{
+ printk(KERN_ERR "rk2928_pm_power_off start...\n");
+
+ #if defined(CONFIG_MFD_TPS65910)
+ tps65910_device_shutdown();//tps65910 shutdown
+ #endif
+ gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
+
+};
+
+static void __init rk2928_board_init(void)
+{
+ gpio_request(POWER_ON_PIN, "poweronpin");
+ gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
+ gpio_free(POWER_ON_PIN);
+
+ pm_power_off = rk2928_pm_power_off;
+
+ rk30_i2c_register_board_info();
+ spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
+ platform_add_devices(devices, ARRAY_SIZE(devices));
+ //RK2928 USB DETECT IRQ: IRQ_OTG_BVALID
+ //board_usb_detect_init(RK30_PIN6_PA3);
+
+#ifdef CONFIG_WIFI_CONTROL_FUNC
+ rk29sdk_wifi_bt_gpio_control_init();
+#endif
+}
+
+static void __init rk2928_reserve(void)
+{
+#ifdef CONFIG_ION
+ rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
+#endif
+#ifdef CONFIG_FB_ROCKCHIP
+ resource_fb[0].start = board_mem_reserve_add("fb0", RK30_FB0_MEM_SIZE);
+ resource_fb[0].end = resource_fb[0].start + RK30_FB0_MEM_SIZE - 1;
+#if 0
+ resource_fb[1].start = board_mem_reserve_add("ipp buf", RK30_FB0_MEM_SIZE);
+ resource_fb[1].end = resource_fb[1].start + RK30_FB0_MEM_SIZE - 1;
+ resource_fb[2].start = board_mem_reserve_add("fb2", RK30_FB0_MEM_SIZE);
+ resource_fb[2].end = resource_fb[2].start + RK30_FB0_MEM_SIZE - 1;
+#endif
+#endif
+#ifdef CONFIG_VIDEO_RK29
+ rk30_camera_request_reserve_mem();
+#endif
+
+#ifdef CONFIG_GPS_RK
+ //it must be more than 8MB
+ rk_gps_info.u32MemoryPhyAddr = board_mem_reserve_add("gps", SZ_8M);
+#endif
+
+ board_mem_reserved();
+}
+/**
+ * dvfs_cpu_logic_table: table for arm and logic dvfs
+ * @frequency : arm frequency
+ * @cpu_volt : arm voltage depend on frequency
+ * @logic_volt : logic voltage arm requests depend on frequency
+ * comments : min arm/logic voltage
+ */
+static struct dvfs_arm_table dvfs_cpu_logic_table[] = {
+ {.frequency = 216 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},
+ {.frequency = 312 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},
+ {.frequency = 408 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},
+ {.frequency = 504 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},
+ {.frequency = 600 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},
+ {.frequency = 696 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
+ {.frequency = 816 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
+ {.frequency = 912 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
+#if 0
+ {.frequency = 1008 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
+ {.frequency = 1104 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
+ {.frequency = 1200 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
+ {.frequency = 1104 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
+ {.frequency = 1248 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
+#endif
+ //{.frequency = 1000 * 1000, .cpu_volt = 1225 * 1000, .logic_volt = 1200 * 1000},
+ {.frequency = CPUFREQ_TABLE_END},
+};
+
+static struct cpufreq_frequency_table dvfs_gpu_table[] = {
+ {.frequency = 266 * 1000, .index = 1050 * 1000},
+ {.frequency = 400 * 1000, .index = 1275 * 1000},
+ {.frequency = CPUFREQ_TABLE_END},
+};
+
+static struct cpufreq_frequency_table dvfs_ddr_table[] = {
+ {.frequency = 300 * 1000, .index = 1050 * 1000},
+ {.frequency = 400 * 1000, .index = 1125 * 1000},
+ {.frequency = CPUFREQ_TABLE_END},
+};
+
+#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
+static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
+static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
+
+void __init board_clock_init(void)
+{
+ rk2928_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
+ dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
+ dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
+ //dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
+ printk("%s end\n", __func__);
+}
+
+
+MACHINE_START(RK2928, "RK2928board")
+ .boot_params = PLAT_PHYS_OFFSET + 0x800,
+ .fixup = rk2928_fixup,
+ .reserve = &rk2928_reserve,
+ .map_io = rk2928_map_io,
+ .init_irq = rk2928_init_irq,
+ .timer = &rk2928_timer,
+ .init_machine = rk2928_board_init,
+MACHINE_END
projects / firefly-linux-kernel-4.4.55.git / commitdiff