[media] au8522: Handle differences in comb filter config for s-video input
authorDevin Heitmueller <dheitmueller@kernellabs.com>
Sun, 27 Jun 2010 21:12:42 +0000 (18:12 -0300)
committerMauro Carvalho Chehab <mchehab@redhat.com>
Wed, 29 Dec 2010 10:16:34 +0000 (08:16 -0200)
Tweak the comb filter config when in s-video mode to match the Hauppauge
Windows driver values (based on register dumps).

This work was sponsored by GetWellNetwork Inc.

Signed-off-by: Devin Heitmueller <dheitmueller@kernellabs.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
drivers/media/dvb/frontends/au8522_decoder.c
drivers/media/dvb/frontends/au8522_priv.h

index 5ec8697064096838803a6024b28c80e8703d9793..b537891a4cc9d8c2e647c68eec420a1e9aaa1723 100644 (file)
@@ -278,10 +278,18 @@ static void setup_decoder_defaults(struct au8522_state *state, u8 input_mode)
                        AU8522_TVDEC_COMB_HDIF_THR2_REG06AH_CVBS);
        au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR3_REG06BH,
                        AU8522_TVDEC_COMB_HDIF_THR3_REG06BH_CVBS);
-       au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,
-                       AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_CVBS);
-       au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,
-                       AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_CVBS);
+       if (input_mode == AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13 ||
+           input_mode == AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH24) {
+               au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,
+                               AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_SVIDEO);
+               au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,
+                               AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_SVIDEO);
+       } else {
+               au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,
+                               AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_CVBS);
+               au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,
+                               AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_CVBS);
+       }
        au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH,
                        AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH_CVBS);
        au8522_writereg(state, AU8522_TVDEC_UV_SEP_THR_REG06FH,
index 609cf04bc3129490cc20d7a18333442c96d33710..751e17d692a90aee5763885ee644e7f09a0dfc7c 100644 (file)
@@ -397,7 +397,9 @@ void au8522_release_state(struct au8522_state *state);
 #define AU8522_TVDEC_COMB_HDIF_THR2_REG06AH_CVBS               0x0A
 #define AU8522_TVDEC_COMB_HDIF_THR3_REG06BH_CVBS               0x32
 #define AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_CVBS              0x34
+#define AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_SVIDEO            0x2a
 #define AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_CVBS              0x05
+#define AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_SVIDEO            0x15
 #define AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH_CVBS              0x6E
 #define AU8522_TVDEC_UV_SEP_THR_REG06FH_CVBS                   0x0F
 #define AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H_CVBS            0x80