Allow pseudos to have patterns, no functionality change

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23988 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td
index ee04dd62ee36d5ddf63a24d0b8374f021043ab11..2ec71532d808b0e2fd6305d3f1cb9042e0f8da20 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/lib/Target/PowerPC/PPCInstrFormats.td
@@ -550,10 +550,10 @@ class MDForm_1<bits<6> opcode, bits<3> xo, dag OL, string asmstr,
 
 //===----------------------------------------------------------------------===//
 def NoItin : InstrItinClass;
-class Pseudo<dag OL, string asmstr>
+class Pseudo<dag OL, string asmstr, list<dag> pattern>
     : I<0, OL, asmstr, NoItin> {
   let PPC64 = 0;
   let VMX = 0;
-
+  let Pattern = pattern;
   let Inst{31-0} = 0;
 }

diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index ca931f62b8dbd82f11961c8a4782d78179b568aa..ad16835f914f23cf2177a0a10f3b7177a4bc251d 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -147,25 +147,25 @@ def crbitm: Operand<i8> {
 // PowerPC Instruction Definitions.
 
 // Pseudo-instructions:
-def PHI : Pseudo<(ops variable_ops), "; PHI">;
+def PHI : Pseudo<(ops variable_ops), "; PHI", []>;
 
 let isLoad = 1 in {
-def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKDOWN">;
-def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKUP">;
+def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKDOWN", []>;
+def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKUP", []>;
 }
-def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC">;
-def IMPLICIT_DEF_F8  : Pseudo<(ops F8RC:$rD), "; %rD = IMPLICIT_DEF_F8">;
-def IMPLICIT_DEF_F4  : Pseudo<(ops F4RC:$rD), "; %rD = IMPLICIT_DEF_F4">;
+def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC", []>;
+def IMPLICIT_DEF_F8  : Pseudo<(ops F8RC:$rD), "; %rD = IMPLICIT_DEF_F8", []>;
+def IMPLICIT_DEF_F4  : Pseudo<(ops F4RC:$rD), "; %rD = IMPLICIT_DEF_F4", []>;
 
 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation.  Expanded by the
 // scheduler into a branch sequence.
 let usesCustomDAGSchedInserter = 1 in {  // Expanded by the scheduler.
   def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
-                              i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
+                              i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
   def SELECT_CC_F4  : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
-                              i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
+                              i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
   def SELECT_CC_F8  : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
-                              i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
+                              i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
 }
 
 
@@ -176,12 +176,12 @@ let isTerminator = 1 in {
 }
 
 let Defs = [LR] in
-  def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">;
+  def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>;
 
 let isBranch = 1, isTerminator = 1 in {
   def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc,
                                 target:$true, target:$false),
-                           "; COND_BRANCH">;
+                           "; COND_BRANCH", []>;
   def B   : IForm<18, 0, 0, (ops target:$func), "b $func", BrB>;
 //def BA  : IForm<18, 1, 0, (ops target:$func), "ba $func", BrB>;
   def BL  : IForm<18, 0, 1, (ops target:$func), "bl $func", BrB>;