.flags = 0,\r
},\r
#endif\r
+#if defined (CONFIG_SND_SOC_WM8900)\r
+ {\r
+ .type = "wm8900",\r
+ .addr = 0x1A,\r
+ .flags = 0,\r
+ },\r
+#endif\r
#if defined (CONFIG_BATTERY_STC3100)\r
{\r
.type = "stc3100-battery",\r
.flags = 0,\r
},\r
#endif\r
+#if defined (CONFIG_RTC_HYM8563)\r
+ {\r
+ .type = "rtc_hym8563",\r
+ .addr = 0x51,\r
+ .flags = 0,\r
+ ///.irq = RK2818_PIN_PA4,\r
+ },\r
+#endif\r
};\r
#endif\r
\r
#define RK2818_I2C_TIMEOUT (msecs_to_jiffies(500))
#define RK2818_DELAY_TIME 2
-#if 1
+#if 0
#define i2c_dbg(dev, format, arg...) \
dev_printk(KERN_INFO , dev , format , ## arg)
#else
u32 opr,xfer,fifosts;
I2S_DBG("Enter %s, %d >>>>>>>>>>>\n", __func__, __LINE__);
-
- opr = readl(pheadi2s->I2S_DMACR);
- xfer = readl(pheadi2s->I2S_XFER);
-
+ opr = readl(&(pheadi2s->I2S_DMACR));
+ xfer = readl(&(pheadi2s->I2S_XFER));
opr &= ~I2S_TRAN_DMA_ENABLE;
- xfer &= ~I2S_TX_TRAN_START;
+ xfer &= ~I2S_TX_TRAN_START;
if (on)
{
writel(opr, &(pheadi2s->I2S_DMACR));
{
writel(opr, &(pheadi2s->I2S_DMACR));
writel(xfer, &(pheadi2s->I2S_XFER));
- }
+ }
}
static void rockchip_snd_rxctrl(struct rk29_i2s_info *i2s, int on)
I2S_DBG("Enter %s, %d >>>>>>>>>>>\n", __func__, __LINE__);
- opr = readl(pheadi2s->I2S_DMACR);
- xfer = readl(pheadi2s->I2S_XFER);
+ opr = readl(&(pheadi2s->I2S_DMACR));
+ xfer = readl(&(pheadi2s->I2S_XFER));
opr &= ~I2S_RECE_DMA_ENABLE;
xfer &= ~I2S_RX_TRAN_START;
base = res->start;
}
- i2s->regs = ioremap(base, resource_size(res));
+ i2s->regs = ioremap(base, (res->end - res->start) + 1); ////res));
if (i2s->regs == NULL) {
dev_err(dev, "cannot ioremap registers\n");
return -ENXIO;