Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140415 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 6be49169b4c57dc189ac88fcc238facf3797368f..a775cf61b555cb9cbc4cc0144ef27686c3d640f7 100644 (file)
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -2660,7 +2660,7 @@ static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
       break;
     default: {
       unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
-      if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
+      if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
     return MCDisassembler::Fail;
     }
   }

diff --git a/test/MC/Disassembler/ARM/thumb2.txt b/test/MC/Disassembler/ARM/thumb2.txt
index 19351e01f50a3adab2d4cbf0cf80ec4d6b863889..2af27b4f347185ddd3662cf4d323539b8bdeeceb 100644 (file)
--- a/test/MC/Disassembler/ARM/thumb2.txt
+++ b/test/MC/Disassembler/ARM/thumb2.txt
@@ -649,14 +649,14 @@
 # CHECK: ldrh.w r5, [r6, #33]
 # CHECK: ldrh.w r5, [r6, #257]
 # CHECK: ldrh.w lr, [r7, #257]
-# CHECK: ldrh.w sp, [pc, #-21]
+# CHECK: ldrh.w r0, [pc, #-21]
 
 0x35 0xf8 0x04 0x5c
 0x35 0x8c
 0xb6 0xf8 0x21 0x50
 0xb6 0xf8 0x01 0x51
 0xb7 0xf8 0x01 0xe1
-0x3f 0xf8 0x15 0xd0
+0x3f 0xf8 0x15 0x00
 
 
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