ARM: S5PC100: Modified files for SPI consolidation work
authorPadmavathi Venna <padma.v@samsung.com>
Fri, 23 Dec 2011 01:14:45 +0000 (10:14 +0900)
committerKukjin Kim <kgene.kim@samsung.com>
Fri, 23 Dec 2011 01:50:01 +0000 (10:50 +0900)
As SPI platform devices are consolidated to plat-samsung, some
corresponding changes are required in the respective machine folder.
Added SPI Setup file for GPIO configurations and platform data
initialization.

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
arch/arm/mach-s5pc100/Kconfig
arch/arm/mach-s5pc100/Makefile
arch/arm/mach-s5pc100/include/mach/map.h
arch/arm/mach-s5pc100/setup-spi.c [new file with mode: 0644]
arch/arm/plat-samsung/devs.c
arch/arm/plat-samsung/include/plat/s3c64xx-spi.h

index e538a4c67e9cc72d18924c3c5945e83c53bbbb4a..75a26eaf26334d9e0abf65131fda20e5e0cb2204 100644 (file)
@@ -45,6 +45,11 @@ config S5PC100_SETUP_SDHCI_GPIO
        help
          Common setup code for SDHCI gpio.
 
+config S5PC100_SETUP_SPI
+       bool
+       help
+         Common setup code for SPI GPIO configurations.
+
 config MACH_SMDKC100
        bool "SMDKC100"
        select CPU_S5PC100
index 238a836b3f7f45d27c4b115abfc46aa6587b0497..291e246c0ec01215409b0609ad63d99e1b5a7eda 100644 (file)
@@ -22,6 +22,7 @@ obj-$(CONFIG_S5PC100_SETUP_I2C1)      += setup-i2c1.o
 obj-$(CONFIG_S5PC100_SETUP_IDE)                += setup-ide.o
 obj-$(CONFIG_S5PC100_SETUP_KEYPAD)     += setup-keypad.o
 obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
+obj-$(CONFIG_S5PC100_SETUP_SPI)        += setup-spi.o
 
 # device support
 obj-y                          += dev-audio.o
index ccbe6b767f7d82179adb3d72e8f0300a561a91b7..54bc4f82e17a1fa0ce9ec19b52dc84edc3b08bcc 100644 (file)
 #define S3C_PA_USB_HSOTG               S5PC100_PA_USB_HSOTG
 #define S3C_PA_USB_HSPHY               S5PC100_PA_USB_HSPHY
 #define S3C_PA_WDT                     S5PC100_PA_WATCHDOG
+#define S3C_PA_SPI0                    S5PC100_PA_SPI0
+#define S3C_PA_SPI1                    S5PC100_PA_SPI1
+#define S3C_PA_SPI2                    S5PC100_PA_SPI2
 
 #define S5P_PA_CHIPID                  S5PC100_PA_CHIPID
 #define S5P_PA_FIMC0                   S5PC100_PA_FIMC0
diff --git a/arch/arm/mach-s5pc100/setup-spi.c b/arch/arm/mach-s5pc100/setup-spi.c
new file mode 100644 (file)
index 0000000..431a6f7
--- /dev/null
@@ -0,0 +1,65 @@
+/* linux/arch/arm/mach-s5pc100/setup-spi.c
+ *
+ * Copyright (C) 2011 Samsung Electronics Ltd.
+ *             http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/s3c64xx-spi.h>
+
+#ifdef CONFIG_S3C64XX_DEV_SPI0
+struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
+       .fifo_lvl_mask  = 0x7f,
+       .rx_lvl_offset  = 13,
+       .high_speed     = 1,
+       .tx_st_done     = 21,
+};
+
+int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+{
+       s3c_gpio_cfgall_range(S5PC100_GPB(0), 3,
+                               S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+       return 0;
+}
+#endif
+
+#ifdef CONFIG_S3C64XX_DEV_SPI1
+struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
+       .fifo_lvl_mask  = 0x7f,
+       .rx_lvl_offset  = 13,
+       .high_speed     = 1,
+       .tx_st_done     = 21,
+};
+
+int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+{
+       s3c_gpio_cfgall_range(S5PC100_GPB(4), 3,
+                               S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+       return 0;
+}
+#endif
+
+#ifdef CONFIG_S3C64XX_DEV_SPI2
+struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = {
+       .fifo_lvl_mask  = 0x7f,
+       .rx_lvl_offset  = 13,
+       .high_speed     = 1,
+       .tx_st_done     = 21,
+};
+
+int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)
+{
+       s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));
+       s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP);
+       s3c_gpio_cfgall_range(S5PC100_GPB(2), 2,
+                               S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
+       return 0;
+}
+#endif
index 080ea18d3f94c83a7b538d3186350efcaa7e11fc..de0d88d6a0f15e04dad6565e216f517551c768fa 100644 (file)
@@ -1582,6 +1582,9 @@ void __init s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
 
        pd->num_cs = num_cs;
        pd->src_clk_nr = src_clk_nr;
+       if (!pd->cfg_gpio)
+               pd->cfg_gpio = s3c64xx_spi2_cfg_gpio;
+
        s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi2);
 }
 #endif /* CONFIG_S3C64XX_DEV_SPI2 */
index d3e2209c809902f4f3a815f8644a3045640c8886..aea68b60ef98af7bac8c5841536c8150d803888f 100644 (file)
@@ -75,7 +75,9 @@ extern void s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
 /* defined by architecture to configure gpio */
 extern int s3c64xx_spi0_cfg_gpio(struct platform_device *dev);
 extern int s3c64xx_spi1_cfg_gpio(struct platform_device *dev);
+extern int s3c64xx_spi2_cfg_gpio(struct platform_device *dev);
 
 extern struct s3c64xx_spi_info s3c64xx_spi0_pdata;
 extern struct s3c64xx_spi_info s3c64xx_spi1_pdata;
+extern struct s3c64xx_spi_info s3c64xx_spi2_pdata;
 #endif /* __S3C64XX_PLAT_SPI_H */