add ddr auto powerdown in DDR_Initand change comment from chinese to english

diff --git a/arch/arm/mach-rk29/ddr.c b/arch/arm/mach-rk29/ddr.c
index 42896358579a3f48400beac9ab962a974c5facb9..657b59e9acea2b3ac29a2f80f3421ddc00ad8a01 100644 (file)
--- a/arch/arm/mach-rk29/ddr.c
+++ b/arch/arm/mach-rk29/ddr.c
@@ -1,13 +1,12 @@
 /****************************************************************\r
 *      CopyRight(C) 2010 by Rock-Chip Fuzhou\r
 *     All Rights Reserved\r
-*      ÎļþÃû:ddr.c\r
-*      ÃèÊö: ddr driver implement\r
-*      ×÷Õß:hcy\r
-*      ´´½¨ÈÕÆÚ:2011-01-04\r
-*      ¸ü¸Ä¼Ç¼:\r
-*      $Log: ddr.c,v $\r
-*      µ±Ç°°æ±¾:1.00   20110104 hcy Ìá½»³õʼ°æ±¾\r
+*      File name       :ddr.c\r
+*      Description: ddr driver implement\r
+*      Author :hcy\r
+*      Create date :2011-01-04\r
+*      Change log:\r
+*      Current version:1.00   20110104 hcy \r
 ****************************************************************/\r
 \r
 #include <linux/init.h>\r
@@ -33,7 +32,7 @@
 \r
 #include <asm/io.h>\r
 \r
-// save_sp ±ØÐ붨ÒåΪ¾²Ì¬È«¾Ö±äÁ¿\r
+// save_sp  must be static global variable  \r
 \r
 static unsigned long save_sp;\r
 \r
@@ -369,7 +368,7 @@ typedef enum tagDDRDLLMode
 \r
 \r
 static __sramdata u32 bFreqRaise;\r
-static __sramdata u32 capability;  //µ¥¸öCSµÄÈÝÁ¿\r
+static __sramdata u32 capability;  // one chip cs capability\r
 \r
 //DDR2\r
 static __sramdata u32 tRFC;\r
@@ -386,8 +385,8 @@ static __sramdata u32 tXP;
 \r
 \r
 /****************************************************************************\r
-ÄÚ²¿sram µÄus ÑÓʱº¯Êý\r
-¼Ù¶¨cpu ×î¸ßƵÂÊ1.2 GHz\r
+Internal sram us delay function\r
+Cpu highest frequency is 1.2 GHz\r
 1 cycle = 1/1.2 ns\r
 1 us = 1000 ns = 1000 * 1.2 cycles = 1200 cycles\r
 *****************************************************************************/\r
@@ -471,15 +470,14 @@ u32 __sramfunc GetDDRCL(u32 newMHz)
     }\r
 }\r
 \r
-/****************************************************************/\r
-//º¯ÊýÃû:SDRAM_EnterSelfRefresh\r
-//ÃèÊö:SDRAM½øÈë×ÔË¢ÐÂģʽ\r
-//²ÎÊý˵Ã÷:\r
-//·µ»ØÖµ:\r
-//Ïà¹ØÈ«¾Ö±äÁ¿:\r
-//×¢Òâ:(1)ϵͳÍêÈ«idleºó²ÅÄܽøÈë×ÔË¢ÐÂģʽ£¬½øÈë×Ôˢкó²»ÄÜÔÙ·ÃÎÊSDRAM\r
-//     (2)Òª½øÈë×ÔË¢ÐÂģʽ£¬±ØÐë±£Ö¤ÔËÐÐʱÕâ¸öº¯ÊýËùµ÷Óõ½µÄËùÓдúÂë²»ÔÚSDRAMÉÏ\r
-/****************************************************************/\r
+/*-------------------------------------------------------------------\r
+Name    : EnterDDRSelfRefresh\r
+Desc    :   DDR enter self refresh\r
+Params  :\r
+Return  :\r
+Notes   :      1.  ddr enter sel-refresh must be after system enter idle ,after ddr enter sel-refresh must not access ddr \r
+               2.  ddr enter sel-refresh code must not be in ddr \r
+-------------------------------------------------------------------*/\r
 void __sramfunc EnterDDRSelfRefresh(void)\r
 {    \r
     pDDR_Reg->CCR &= ~HOSTEN;  //disable host port\r
@@ -489,15 +487,14 @@ void __sramfunc EnterDDRSelfRefresh(void)
     delayus(10);\r
 }\r
 \r
-/****************************************************************/\r
-//º¯ÊýÃû:SDRAM_ExitSelfRefresh\r
-//ÃèÊö:SDRAMÍ˳ö×ÔË¢ÐÂģʽ\r
-//²ÎÊý˵Ã÷:\r
-//·µ»ØÖµ:\r
-//Ïà¹ØÈ«¾Ö±äÁ¿:\r
-//×¢Òâ:(1)SDRAMÔÚ×ÔË¢ÐÂģʽºó²»Äܱ»·ÃÎÊ£¬±ØÐëÏÈÍ˳ö×ÔË¢ÐÂģʽ\r
-//     (2)±ØÐë±£Ö¤ÔËÐÐʱÕâ¸öº¯ÊýµÄ´úÂë²»ÔÚSDRAMÉÏ\r
-/****************************************************************/\r
+/*-------------------------------------------------------------------\r
+Name   :   ExitDDRSelfRefresh\r
+Desc    :   DDR exit self refresh\r
+Params  :\r
+Return  :\r
+Notes   :      1.  ddr enter sel-refresh must be after system enter idle ,after ddr enter sel-refresh must not access ddr \r
+              2.  ddr enter sel-refresh code must not be in ddr \r
+-------------------------------------------------------------------*/\r
 void __sramfunc ExitDDRSelfRefresh(void)\r
 {\r
 \r
@@ -515,12 +512,12 @@ void __sramfunc ExitDDRSelfRefresh(void)
 \r
 /*-------------------------------------------------------------------\r
 Name    : PLLGetAHBFreq\r
-Desc    : »ñÈ¡DDRµÄƵÂÊ\r
+Desc    :  get DDR frequency\r
 Params  :\r
-Return  : DDRƵÂÊ,  KHz Ϊµ¥Î»\r
+Return  : DDR frequency,  min is KHz\r
 Notes   :\r
 -------------------------------------------------------------------*/\r
-static u32 PLLGetDDRFreq(void)\r
+static u32 PLLGetDDRFreq(void)  // ??????????????? need to check it by huangtao , Is DPLL only used by DDR?\r
 {\r
     u32 nr;\r
     u32 nf;\r
@@ -893,15 +890,13 @@ DDR_CONFIG_T    ddrConfig[3][10] = {
     }\r
 };\r
 \r
-\r
-/****************************************************************/\r
-//º¯ÊýÃû:SDRAM_Init\r
-//ÃèÊö:DDR ³õʼ»¯\r
-//²ÎÊý˵Ã÷:\r
-//·µ»ØÖµ:\r
-//Ïà¹ØÈ«¾Ö±äÁ¿:\r
-//×¢Òâ:\r
-/****************************************************************/\r
+/*-------------------------------------------------------------------\r
+Name    : DDR_Init\r
+Desc    :  ddr initialize\r
+Params  :\r
+Return  :\r
+Notes   : \r
+-------------------------------------------------------------------*/\r
 u32 ddrDataTraining[16];\r
 void DDR_Init(void)\r
 {\r
@@ -916,20 +911,16 @@ void DDR_Init(void)
     u32          bank;\r
     u32          n;\r
 \r
-    //ËãÎïÀí¶ÔÆëµØÖ·\r
-    n = (unsigned long)ddrDataTraining;\r
-       printk("\n#################### VA = 0x%x\n", n);\r
+    // caculate aglined physical address \r
     addr =  __pa((unsigned long)ddrDataTraining);\r
-       printk("#################### PA = 0x%x", addr);\r
     if(addr&0x1F)\r
     {\r
         addr += (32-(addr&0x1F));\r
     }\r
     addr -= 0x60000000;\r
-       printk("#################### PA aligned = 0x%x\n", addr);\r
-    //ËãÊý¾ÝÏß¿í\r
+    // caculate data width\r
     bw = ((((pDDR_Reg->DCR >> 7) & 0x7)+1)>>1);\r
-    //²é³öcol£¬row£¬bank\r
+    // find out col£¬row£¬bank\r
     for(n=0;n<10; n++)\r
     {\r
         if(ddrConfig[(pDDR_Reg->DCR & 0x3)][n].config == (pDDR_Reg->DCR & 0x7c))\r
@@ -946,8 +937,8 @@ void DDR_Init(void)
     {\r
         //ASSERT\r
     }\r
-       printk("#################### bw = 0x%x, col = 0x%x, row = 0x%x, bank = 0x%x\n", bw, col, row, bank);\r
-    //¸ù¾Ý²»Í¬µÄµØÖ·Ó³É䷽ʽ£¬Ëã³öDTAR¼Ä´æÆ÷µÄÅäÖÃ\r
+\r
+    // according different address mapping, caculate DTAR register value\r
     value = pDDR_Reg->DTAR;\r
     value &= ~(0x7FFFFFFF);\r
     switch(pDDR_Reg->DCR & (0x3<<14))\r
@@ -975,16 +966,15 @@ void DDR_Init(void)
                 value |= ((addr>>(bw+col+row)) & ((0x1<<bank)-1)) << 28;  // bank\r
             }\r
             break;\r
-        case AMAP_FIX:    //²»Ö§³ÖÕâÖ̶ֹ¨µÄ·½Ê½\r
+        case AMAP_FIX:    // can not support AMAP_FIX mode \r
         default:\r
             break;\r
     }\r
-       printk("#################### value = 0x%x\n", value);\r
     pDDR_Reg->DTAR = value;\r
 \r
     if(memType == DDRII)\r
     {\r
-        pDDR_Reg->ALPMR = LPPERIOD_POWER_DOWN(0xFF); /* | AUTOPD;*/\r
+        pDDR_Reg->ALPMR = LPPERIOD_POWER_DOWN(0xFF)|AUTOPD;\r
     }\r
     else\r
     {\r
@@ -1001,8 +991,17 @@ void DDR_Init(void)
     DDRPreUpdateTiming(MHz);\r
     DDRUpdateRef();\r
     DDRUpdateTiming();\r
+       \r
 }\r
 \r
+/*-------------------------------------------------------------------\r
+Name    : DDR_ChangeFreq\r
+Desc    :  change ddr frequency \r
+Params  :\r
+Return  :\r
+Notes   :  close interrupt before call it\r
+              open interrupt after call it\r
+-------------------------------------------------------------------*/\r
 void DDR_ChangeFreq(u32 DDRoldMHz, u32 DDRnewMHz)\r
 {\r
 \r
@@ -1017,15 +1016,14 @@ void DDR_ChangeFreq(u32 DDRoldMHz, u32 DDRnewMHz)
 \r
 ////////////////////////////////////////////////////////////////////////////////////\r
 \r
-/****************************************************************/\r
-//º¯ÊýÃû:SDRAM_EnterSelfRefresh\r
-//ÃèÊö:SDRAM½øÈë×ÔË¢ÐÂģʽ\r
-//²ÎÊý˵Ã÷:\r
-//·µ»ØÖµ:\r
-//Ïà¹ØÈ«¾Ö±äÁ¿:\r
-//×¢Òâ:(1)ϵͳÍêÈ«idleºó²ÅÄܽøÈë×ÔË¢ÐÂģʽ£¬½øÈë×Ôˢкó²»ÄÜÔÙ·ÃÎÊSDRAM\r
-//     (2)Òª½øÈë×ÔË¢ÐÂģʽ£¬±ØÐë±£Ö¤ÔËÐÐʱÕâ¸öº¯ÊýËùµ÷Óõ½µÄËùÓдúÂë²»ÔÚSDRAMÉÏ\r
-/****************************************************************/\r
+/*-------------------------------------------------------------------\r
+Name    :  DDR_EnterSelfRefresh\r
+Desc    :   DDR enter self refresh call in ddr\r
+Params  :\r
+Return  :\r
+Notes   :      1.  ddr enter sel-refresh must be after system enter idle ,after ddr enter sel-refresh must not access ddr \r
+               2.  ddr enter sel-refresh code must not be in ddr \r
+-------------------------------------------------------------------*/\r
 void __sramfunc DDR_EnterSelfRefresh(void)\r
 {\r
     EnterDDRSelfRefresh();\r
@@ -1041,15 +1039,14 @@ void __sramfunc DDR_EnterSelfRefresh(void)
 #endif\r
 }\r
 \r
-/****************************************************************/\r
-//º¯ÊýÃû:SDRAM_ExitSelfRefresh\r
-//ÃèÊö:SDRAMÍ˳ö×ÔË¢ÐÂģʽ\r
-//²ÎÊý˵Ã÷:\r
-//·µ»ØÖµ:\r
-//Ïà¹ØÈ«¾Ö±äÁ¿:\r
-//×¢Òâ:(1)SDRAMÔÚ×ÔË¢ÐÂģʽºó²»Äܱ»·ÃÎÊ£¬±ØÐëÏÈÍ˳ö×ÔË¢ÐÂģʽ\r
-//     (2)±ØÐë±£Ö¤ÔËÐÐʱÕâ¸öº¯ÊýµÄ´úÂë²»ÔÚSDRAMÉÏ\r
-/****************************************************************/\r
+/*-------------------------------------------------------------------\r
+Name   :   DDR_ExitSelfRefresh\r
+Desc    :   DDR exit self refresh\r
+Params  :\r
+Return  :\r
+Notes   :      1.  ddr enter sel-refresh must be after system enter idle ,after ddr enter sel-refresh must not access ddr \r
+              2.  ddr enter sel-refresh code must not be in ddr \r
+-------------------------------------------------------------------*/\r
 void __sramfunc DDR_ExitSelfRefresh(void)\r
 {\r
 #if 1\r
@@ -1076,7 +1073,7 @@ void __sramfunc DDR_ExitSelfRefresh(void)
                "mcr p15,0,%2,c10,c0,1\n\t"\r
                ::"r"(vaddr) , "r"(0x00000001), "r"(0x08400000));\r
 }\r
-// ¿¼ÂÇcpu  Ԥȡ¡¢mmu cache\r
+// consider  cpu prefetch¡¢mmu cache\r
 static void __sramfunc do_selfrefreshtest(void)\r
 {\r
        volatile u32 n; \r