drm/rockchip: vop: correct vop register's version

Change-Id: Ic7a85e3107501ed652b79e41a7c849b7538f0f81
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index b5a486d0c40342e103fed10d40dd8e1b58bab2f1..d07fca15d19447517b1c4edcc8f1fa87755c293f 100644 (file)
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -188,10 +188,10 @@ static const struct vop_ctrl rk3288_ctrl_data = {
        .post_lb_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 18, 3, 2, -1),
        .global_regdone_en = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 11, 3, 2, -1),
        .overlay_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 16, 3, 2, -1),
-       .core_dclk_div = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 4, 3, 4, -1),
-       .p2i_en = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 5, 3, 4, -1),
-       .dclk_ddr = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 8, 3, 4, -1),
-       .dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11),
+       .core_dclk_div = VOP_REG_VER(RK3366_DSP_CTRL0, 0x1, 4, 3, 4, -1),
+       .p2i_en = VOP_REG_VER(RK3366_DSP_CTRL0, 0x1, 5, 3, 4, -1),
+       .dclk_ddr = VOP_REG_VER(RK3366_DSP_CTRL0, 0x1, 8, 3, 4, -1),
+       .dp_en = VOP_REG_VER(RK3399_SYS_CTRL, 0x1, 11, 3, 5, -1),
        .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
        .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
        .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
@@ -215,13 +215,16 @@ static const struct vop_ctrl rk3288_ctrl_data = {
        .dsp_lut_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 0),
        .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
 
-       .afbdc_rstn = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 3),
-       .afbdc_en = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 0),
-       .afbdc_sel = VOP_REG(RK3399_AFBCD0_CTRL, 0x3, 1),
-       .afbdc_format = VOP_REG(RK3399_AFBCD0_CTRL, 0x1f, 16),
-       .afbdc_hreg_block_split = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 21),
-       .afbdc_hdr_ptr = VOP_REG(RK3399_AFBCD0_HDR_PTR, 0xffffffff, 0),
-       .afbdc_pic_size = VOP_REG(RK3399_AFBCD0_PIC_SIZE, 0xffffffff, 0),
+       .afbdc_rstn = VOP_REG_VER(RK3399_AFBCD0_CTRL, 0x1, 3, 3, 5, -1),
+       .afbdc_en = VOP_REG_VER(RK3399_AFBCD0_CTRL, 0x1, 0, 3, 5, -1),
+       .afbdc_sel = VOP_REG_VER(RK3399_AFBCD0_CTRL, 0x3, 1, 3, 5, -1),
+       .afbdc_format = VOP_REG_VER(RK3399_AFBCD0_CTRL, 0x1f, 16, 3, 5, -1),
+       .afbdc_hreg_block_split = VOP_REG_VER(RK3399_AFBCD0_CTRL,
+                                             0x1, 21, 3, 5, -1),
+       .afbdc_hdr_ptr = VOP_REG_VER(RK3399_AFBCD0_HDR_PTR, 0xffffffff,
+                                    0, 3, 5, -1),
+       .afbdc_pic_size = VOP_REG_VER(RK3399_AFBCD0_PIC_SIZE, 0xffffffff,
+                                     0, 3, 5, -1),
 
        .xmirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 22),
        .ymirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 23),