Atom has SIMD instruction set extension up to SSSE3
authorMichael Liao <michael.liao@intel.com>
Thu, 25 Oct 2012 07:06:48 +0000 (07:06 +0000)
committerMichael Liao <michael.liao@intel.com>
Thu, 25 Oct 2012 07:06:48 +0000 (07:06 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166665 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86.td

index 1dc4aa998923a86bb1373d18453a440a78a5bdf8..1b5c4d97539263558a30b839ba415a8257e84045 100644 (file)
@@ -162,7 +162,7 @@ def : Proc<"core2",           [FeatureSSSE3, FeatureCMPXCHG16B,
                                FeatureSlowBTMem]>;
 def : Proc<"penryn",          [FeatureSSE41, FeatureCMPXCHG16B,
                                FeatureSlowBTMem]>;
-def : AtomProc<"atom",        [ProcIntelAtom, FeatureSSE3, FeatureCMPXCHG16B,
+def : AtomProc<"atom",        [ProcIntelAtom, FeatureSSSE3, FeatureCMPXCHG16B,
                                FeatureMOVBE, FeatureSlowBTMem, FeatureLeaForSP,
                                FeatureSlowDivide]>;
 // "Arrandale" along with corei3 and corei5