return STI.getFeatureBits() & Mips::FeatureMips16;
}
- bool abiUsesSoftFloat() const {
+ bool useSoftFloat() const {
return (STI.getFeatureBits() & Mips::FeatureSoftFloat);
}
template <class PredicateLibrary>
void setCPR1SizeFromPredicates(const PredicateLibrary &P) {
- if (P.abiUsesSoftFloat())
+ if (P.useSoftFloat())
CPR1Size = Mips::AFL_REG_NONE;
else if (P.hasMSA())
CPR1Size = Mips::AFL_REG_128;
Is32BitABI = P.isABI_O32();
FpABI = FpABIKind::ANY;
- if (P.abiUsesSoftFloat())
+ if (P.useSoftFloat())
FpABI = FpABIKind::SOFT;
else if (P.isABI_N32() || P.isABI_N64())
FpABI = FpABIKind::S64;
// Set up the register classes
addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
- if (!Subtarget.abiUsesSoftFloat())
+ if (!Subtarget.useSoftFloat())
setMips16HardFloatLibCalls();
setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
// Handle F128 specially since we can't identify the original type during the
// tablegen-erated code.
def RetCC_F128 : CallingConv<[
- CCIfSubtarget<"abiUsesSoftFloat()",
+ CCIfSubtarget<"useSoftFloat()",
CCIfType<[i64], CCDelegateTo<RetCC_F128SoftFloat>>>,
- CCIfSubtargetNot<"abiUsesSoftFloat()",
+ CCIfSubtargetNot<"useSoftFloat()",
CCIfType<[i64], CCDelegateTo<RetCC_F128HardFloat>>>
]>;
CCIfType<[i8, i16, i32], CCIfOrigArgWasNotFloat<CCPromoteToType<i64>>>,
// The only i32's we have left are soft-float arguments.
- CCIfSubtarget<"abiUsesSoftFloat()", CCIfType<[i32], CCDelegateTo<CC_MipsN_SoftFloat>>>,
+ CCIfSubtarget<"useSoftFloat()", CCIfType<[i32], CCDelegateTo<CC_MipsN_SoftFloat>>>,
// Integer arguments are passed in integer registers.
CCIfType<[i64], CCAssignToRegWithShadow<[A0_64, A1_64, A2_64, A3_64,
// f128 should only occur for the N64 ABI where long double is 128-bit. On
// N32, long double is equivalent to double.
CCIfType<[i64],
- CCIfSubtargetNot<"abiUsesSoftFloat()",
+ CCIfSubtargetNot<"useSoftFloat()",
CCIfOrigArgWasF128<CCBitConvertToType<f64>>>>,
CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_Mips_FastCC>>,
// when allocating floating point values to integer registers.
// This shouldn't influence how we load the value into registers unless
// we are targetting softfloat.
- if (VA.getValVT().isFloatingPoint() && !Subtarget.abiUsesSoftFloat())
+ if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat())
LocVT = VA.getValVT();
}
bool
MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
- if (Subtarget.hasMips3() && Subtarget.abiUsesSoftFloat()) {
+ if (Subtarget.hasMips3() && Subtarget.useSoftFloat()) {
if (Type == MVT::i32)
return true;
}
AssemblerPredicate<"FeatureSingleFloat">;
def IsNotSingleFloat : Predicate<"!Subtarget->isSingleFloat()">,
AssemblerPredicate<"!FeatureSingleFloat">;
-def IsNotSoftFloat : Predicate<"!Subtarget->abiUsesSoftFloat()">,
+def IsNotSoftFloat : Predicate<"!Subtarget->useSoftFloat()">,
AssemblerPredicate<"!FeatureSoftFloat">;
//===----------------------------------------------------------------------===//
setTargetDAGCombine(ISD::XOR);
}
- if (!Subtarget.abiUsesSoftFloat()) {
+ if (!Subtarget.useSoftFloat()) {
addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
// When dealing with single precision only, use libcalls
bool hasStandardEncoding() const { return !inMips16Mode(); }
- bool abiUsesSoftFloat() const {
- return IsSoftFloat && !InMips16HardFloat;
- }
+ bool useSoftFloat() const { return IsSoftFloat && !InMips16HardFloat; }
bool enableLongBranchPass() const {
return hasStandardEncoding() || allowMixed16_32();