--- /dev/null
+# RUN: llvm-mc -triple=hexagon -filetype=obj %s | llvm-objdump -d -r - | FileCheck %s
+#
+
+# Verify that capitaizled endloops work
+
+ { R0 = mpyi(R0,R0) } : endloop0
+ { R0 = mpyi(R0,R0) } : ENDLOOP0
+ { R0 = mpyi(R0,R0) }:endloop0
+
+ { R0 = mpyi(R0,R0) } : endloop1
+ { R0 = mpyi(R0,R0) } : ENDLOOP1
+ { R0 = mpyi(R0,R0) }:endloop1
+
+ { R0 = mpyi(R0,R0) } : endloop0 : endloop1
+ { R0 = mpyi(R0,R0) } : ENDLOOP0 : ENDLOOP1
+ { R0 = mpyi(R0,R0) }:endloop0:endloop1
+
+# CHECK: r0 = mpyi(r0, r0)
+# CHECK: :endloop0
+# CHECK: :endloop0
+# CHECK: :endloop0
+# CHECK: :endloop1
+# CHECK: :endloop1
+# CHECK: :endloop1
+# CHECK: :endloop0 :endloop1
+# CHECK: :endloop0 :endloop1
+# CHECK: :endloop0 :endloop1
+
+
--- /dev/null
+# RUN: llvm-mc -triple=hexagon -filetype=obj -mno-pairing %s -o %t; llvm-objdump -d %t | FileCheck %s
+
+# Check that DCFETCH is correctly shuffled.
+
+ { dcfetch(r2 + #0); r1 = memw(r2) }
+# CHECK: 9402c000
+
+# Bug 17424: This should be a legal packet
+{
+ P3 = SP1LOOP0(#8,R18)
+ R7:6 = MEMUBH(R4++#4)
+ R13:12 = VALIGNB(R11:10,R9:8,P2)
+ DCFETCH(R5+#(8+0))
+}
+# CHECK-NOT: error:
--- /dev/null
+# RUN: llvm-mc -triple=hexagon -filetype=asm %s 2>%t; FileCheck %s <%t
+
+# Check that a branch in an end-loop packet is caught.
+
+1:
+{
+ r0 = #1
+ p0 = cmp.eq (r1, r2)
+ if (p0) jump 1b
+}:endloop0
+
+2:
+{
+ r0 = #1
+ p0 = cmp.eq (r1, r2)
+ if (p0) jump 2b
+}:endloop1
+
+# CHECK: rror: packet marked with `:endloop{{.}}' cannot contain instructions that modify register
--- /dev/null
+# RUN: llvm-mc -triple=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s
+# Make sure relaxation doesn't hinder newvalue calculation
+
+#CHECK: r18 = add(r2, #-6)
+#CHECK-NEXT: immext(#0)
+#CHECK-NEXT: if (!cmp.gt(r18.new, #1)) jump:t
+{
+ r18 = add(r2, #-6)
+ if (!cmp.gt(r18.new, #1)) jump:t .unknown
+}