Move the Imp tblgen class from the X86 backend to common code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30907 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index 75d3d7b4f8266d99681e8b5336fcefa3402a6d81..bb87265be3b0d8b11a999963ed36f56b82b12833 100644 (file)
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -173,6 +173,13 @@ class Instruction {
   InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
 }
 
+/// Imp - Helper class for specifying the implicit uses/defs set for an
+/// instruction.
+class Imp<list<Register> uses, list<Register> defs> {
+  list<Register> Uses = uses;
+  list<Register> Defs = defs;
+}
+
 /// Predicates - These are extra conditionals which are turned into instruction
 /// selector matching code. Currently each predicate is just a string.
 class Predicate<string cond> {

diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index f7a5af20f9994537461dcaaec5a08123a9c468ed..ac3a985344f722035354b76906861a9c52d994c9 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -228,11 +228,6 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string AsmStr>
   bits<3> FPFormBits = 0;
 }
 
-class Imp<list<Register> uses, list<Register> defs> {
-  list<Register> Uses = uses;
-  list<Register> Defs = defs;
-}
-
 
 // Prefix byte classes which are used to indicate to the ad-hoc machine code
 // emitter that various prefix bytes are required.