rk3066B: support set_rate_even div = 1

diff --git a/arch/arm/mach-rk30/clock_data-rk3066b.c b/arch/arm/mach-rk30/clock_data-rk3066b.c
index 2c1d69adcf6d56a92924aa5d39a57160abbd9ee3..6021ca769ac1cb47cf186cd30b9c962cce6373f0 100644 (file)
--- a/arch/arm/mach-rk30/clock_data-rk3066b.c
+++ b/arch/arm/mach-rk30/clock_data-rk3066b.c
@@ -301,9 +301,11 @@ static int clksel_set_rate_shift_2(struct clk *clk, unsigned long rate)
 //for div 1 2 4 2*n
 static int clksel_set_rate_even(struct clk *clk, unsigned long rate)
 {
-       u32 div;
-       for (div = 2; div < clk->div_max; div += 2) {
-               u32 new_rate = clk->parent->rate / div;
+       u32 div = 0, new_rate = 0;
+       for (div = 1; div < clk->div_max; div++) {
+               if (div >= 3 && div % 2 != 0)
+                       continue;
+               new_rate = clk->parent->rate / div;
                if (new_rate <= rate) {
                        set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
                        clk->rate = new_rate;