FROMLIST: arm64: dts: rockchip: support the pmu node for rk3399

This patch add to enable the ARM Performance Monitor Units for rk3399.
ARM cores often have a PMU for counting cpu and cache events like cache
misses and hits.

Also, as the Marc posted the patches [0] to support Partitioning per-cpu
interrupts. Let's add this patch to match it on rk3399 SoCs.

[0]:
https://lkml.org/lkml/2016/4/11/182
https://patchwork.kernel.org/patch/9209369/

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Marc Zyngier <marc.zyngier@arm.com>
CC: linux-arm-kernel@lists.infradead.org
Acked-by: Mark Rutland <mark.rutland@arm.com>
(Remove the original dts PMU)
Change-Id: I7e06c479bff7a431b0dc03309df08a640060bafd
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
(am https://patchwork.kernel.org/patch/9215663/)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 7ee53786ce00cc02c130f013290649faa47c567b..59f41e21796e168fa04bd6bc01daf1f63fdeee42 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -260,9 +260,14 @@
                             <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
        };
 
-       arm-pmu {
-               compatible = "arm,armv8-pmuv3";
-               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW 0>;
+       pmu_a53 {
+               compatible = "arm,cortex-a53-pmu";
+               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>;
+       };
+
+       pmu_a72 {
+               compatible = "arm,cortex-a72-pmu";
+               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>;
        };
 
        xin24m: xin24m {
@@ -488,6 +493,16 @@
                        msi-controller;
                        reg = <0x0 0xfee20000 0x0 0x20000>;
                };
+
+               ppi-partitions {
+                       part0: interrupt-partition-0 {
+                               affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
+                       };
+
+                       part1: interrupt-partition-1 {
+                               affinity = <&cpu_b0 &cpu_b1>;
+                       };
+               };
        };
 
        saradc: saradc@ff100000 {