clocks = <&clk_gpll>;
clock-output-names = "clk_gpll_div2";
clock-div = <2>;
- clock-mult = <20>;
+ clock-mult = <1>;
#clock-cells = <0>;
};
clocks = <&clk_gpll>;
clock-output-names = "clk_gpll_div3";
clock-div = <3>;
- clock-mult = <20>;
+ clock-mult = <1>;
#clock-cells = <0>;
};
clocks = <&xin24m>;
clock-output-names = "clk_pvtm_func";
clock-div = <1>;
- clock-mult = <20>;
+ clock-mult = <1>;
#clock-cells = <0>;
};
#clock-cells = <0>;
};
+ pclkin_cif_inv: pclkin_cif_inv {
+ compatible = "rockchip,rk-fixed-factor-clock";
+ clocks = <&clk_gates3 3>;
+ clock-output-names = "pclkin_cif_inv";
+ clock-div = <1>;
+ clock-mult = <1>;
+ #clock-cells = <0>;
+ };
+
};
clock_regs {
clock-output-names = "clk_cpll";
rockchip,pll-type = <CLK_PLL_312XPLUS>;
#clock-cells = <0>;
+ #clock-init-cells = <1>;
};
clk_gpll: pll-clk@0030 {
#clock-init-cells = <1>;
};
- aclk_cpu_pre_div: aclk_cpu_pre_div {
+ aclk_cpu_div: aclk_cpu_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
- clocks = <&aclk_cpu_pre>;
- clock-output-names = "aclk_cpu_pre";
+ clocks = <&aclk_cpu>;
+ clock-output-names = "aclk_cpu";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
};
- aclk_cpu_pre: aclk_cpu_pre_mux {
+ aclk_cpu: aclk_cpu_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <13 2>;
clocks = <&clk_apll>, <&clk_gpll>,<&clk_gpll_div2>,<&clk_gpll_div3>;
- clock-output-names = "aclk_cpu_pre";
+ clock-output-names = "aclk_cpu";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
hclk_cpu_pre: hclk_cpu_pre_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 2>;
- clocks = <&aclk_cpu_pre>;
+ clocks = <&aclk_cpu>;
clock-output-names = "hclk_cpu_pre";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
pclk_cpu_pre: pclk_cpu_pre_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <12 3>;
- clocks = <&aclk_cpu_pre>;
+ clocks = <&aclk_cpu>;
clock-output-names = "pclk_cpu_pre";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>;
clock-output-names = "clk_nandc";
#clock-cells = <0>;
+ #clock-init-cells = <1>;
};
};
rockchip,bits = <8 5>;
clocks = <&xin24m>;
clock-output-names = "clk_24m";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
};
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
+ #clock-init-cells = <1>;
};
/* reg[5]: reserved */
#address-cells = <1>;
#size-cells = <1>;
- aclk_peri_pre_div: aclk_peri_pre_div {
+ aclk_peri_div: aclk_peri_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
- clocks = <&aclk_peri_pre>;
- clock-output-names = "aclk_peri_pre";
+ clocks = <&aclk_peri>;
+ clock-output-names = "aclk_peri";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
hclk_peri_pre: hclk_peri_pre_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 2>;
- clocks = <&aclk_peri_pre>;
+ clocks = <&aclk_peri>;
clock-output-names = "hclk_peri_pre";
rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
rockchip,div-relations =
pclk_peri_pre: pclk_peri_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <12 2>;
- clocks = <&aclk_peri_pre>;
+ clocks = <&aclk_peri>;
clock-output-names = "pclk_peri_pre";
rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
rockchip,div-relations =
#clock-init-cells = <1>;
};
- aclk_peri_pre: aclk_peri_pre_mux {
+ aclk_peri: aclk_peri_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&clk_gpll>,<&clk_cpll>,<&clk_gpll_div2>,<&clk_gpll_div3>;
- clock-output-names = "aclk_peri_pre";
+ clock-output-names = "aclk_peri";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>, <&xin24m>;
clock-output-names = "clk_sdio";
#clock-cells = <0>;
+ #clock-init-cells = <1>;
};
clk_emmc_div: clk_emmc_div {
clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>, <&xin24m>;
clock-output-names = "clk_emmc";
#clock-cells = <0>;
+ #clock-init-cells = <1>;
};
};
clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>;
clock-output-names = "dclk_ebc";
#clock-cells = <0>;
+ #clock-init-cells = <1>;
};
/* reg[7:2]: reserved */
clk_crypto_div: clk_crypto_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 2>;
- clocks = <&aclk_cpu_pre>;
+ clocks = <&aclk_cpu>;
clock-output-names = "clk_crypto";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
clk_ddr: ddr_clk_pll_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <8 1>;
- clocks = <&clk_dpll>, <&clk_gpll_div2>;
+ clocks = <&clk_dpll>, <&dummy>;
clock-output-names = "clk_ddr";
#clock-cells = <0>;
};
clk_cif0_in: clk_cif0_in_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <7 1>;
- clocks = <&pclkin_cif>, <&dummy>;
+ clocks = <&pclkin_cif>, <&pclkin_cif_inv>;
clock-output-names = "clk_cif0_in";
#clock-cells = <0>;
#clock-init-cells = <1>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
+ rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
};
clk_vepu: clk_vepu_mux {
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
+ rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
};
clk_vdpu: clk_vdpu_mux {
clk_gpu_pre: clk_gpu_pre_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <5 3>;
- clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
+ clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
clock-output-names = "clk_gpu_pre";
#clock-cells = <0>;
#clock-init-cells = <1>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
+ rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
};
clk_hevc_core: clk_hevc_core_mux {
reg = <0x00d0 0x4>;
clocks =
<&clk_core>, <&dummy>,
- <&dummy>, <&aclk_cpu_pre>,
+ <&dummy>, <&aclk_cpu>,
- <&aclk_cpu_pre>, <&aclk_cpu_pre>,
+ <&aclk_cpu>, <&aclk_cpu>,
<&dummy>, <&clk_core>,
<&dummy>, <&clk_i2s_2ch_pll>,
<&i2s_2ch_frac>, <&hclk_vio_pre>,
- <&aclk_cpu_pre>, <&clk_i2s_2ch_out>,
+ <&aclk_cpu>, <&clk_i2s_2ch_out>,
<&clk_i2s_2ch>, <&dummy>;
clock-output-names =
- "pclk_dbg", "aclk_cpu_pre", /*clk_cpu_cpll*/
+ "pclk_dbg", "aclk_cpu", /*clk_cpu_cpll*/
"clk_ddr", "aclk_cpu_pre",
"hclk_cpu_pre", "pclk_cpu_pre",
compatible = "rockchip,rk3188-gate-clk";
reg = <0x00d8 0x4>;
clocks =
- <&dummy>, <&aclk_peri_pre>,
- <&aclk_peri_pre>, <&aclk_peri_pre>,
+ <&aclk_peri>, <&aclk_peri>,
+ <&aclk_peri>, <&aclk_peri>,
<&clk_mac_ref>, <&clk_mac_ref>,
<&clk_mac_ref>, <&clk_mac_ref>,
<&spdif_frac>, <&clk_sdio>,
<&clk_emmc>, <&xin24m>;
clock-output-names =
- "aclk_peri_pre", "aclk_peri_pre",
+ "aclk_peri", "aclk_peri_pre",
"hclk_peri_pre", "pclk_peri_pre",
"clk_mac_ref", "clk_mac_refout",
<&clk_hevc_core>, <&clk_vdpu>,
<&hclk_vdpu>, <&clk_gpu_pre>,
- <&aclk_peri_pre>, <&clk_sfc>;
+ <&aclk_peri>, <&clk_sfc>;
clock-output-names =
"aclk_vio0_pre", "dclk_lcdc0",
reg = <0x00e0 0x4>;
clocks =
<&hclk_peri_pre>, <&pclk_peri_pre>,
- <&aclk_peri_pre>, <&aclk_peri_pre>,
+ <&aclk_peri>, <&aclk_peri>,
<&clk_i2s_8ch_pll>, <&i2s_8ch_frac>,
<&clk_i2s_8ch>, <&dummy>,
<&dummy>, <&dummy>,
- <&aclk_cpu_pre>, <&dummy>,
+ <&aclk_cpu>, <&dummy>,
- <&aclk_cpu_pre>, <&dummy>,
+ <&aclk_cpu>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
compatible = "rockchip,rk3188-gate-clk";
reg = <0x00e4 0x4>;
clocks =
- <&pclk_cpu_pre>, <&aclk_peri_pre>,
+ <&pclk_cpu_pre>, <&aclk_peri>,
<&pclk_peri_pre>, <&dummy>,
<&pclk_cpu_pre>, <&dummy>,
<&aclk_vio1_pre>, <&dummy>,
<&pclk_peri_pre>, <&hclk_peri_pre>,
- <&hclk_peri_pre>, <&aclk_peri_pre>;
+ <&hclk_peri_pre>, <&aclk_peri>;
clock-output-names =
"reserved", "reserved",
<&xin24m>, <&xin24m>,
<&xin24m>, <&hclk_peri_pre>,
- <&aclk_peri_pre>, <&pclk_peri_pre>,
+ <&aclk_peri>, <&pclk_peri_pre>,
<&hclk_peri_pre>, <&clk_tsp_in>,
<&hclk_peri_pre>, <&clk_nandc>;
status = "disabled";
};
+ clocks-init{
+ compatible = "rockchip,clocks-init";
+ rockchip,clocks-init-parent =
+ <&clk_core &clk_apll>, <&aclk_cpu &clk_gpll_div2>,
+ <&aclk_peri &clk_gpll_div2>, <&clk_uart0_pll &clk_gpll>,
+ <&clk_uart2_pll &clk_gpll>, <&clk_i2s_2ch_pll &clk_gpll>,
+ <&clk_i2s_8ch_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
+ <&clk_vepu &clk_gpll_div2>, <&clk_vdpu &clk_gpll_div2>,
+ <&clk_hevc_core &clk_gpll>, <&aclk_vio0_pre &clk_gpll_div2>,
+ <&aclk_vio1_pre &clk_gpll_div2>, <&hclk_vio_pre &clk_gpll_div2>,
+ <&sclk_lcdc0 &clk_cpll>, <&clk_gpu_pre &clk_gpll_div2>,
+ <&clk_cif_pll &clk_gpll_div2>, <&dclk_ebc &clk_gpll_div2>,
+ <&clk_emmc &clk_gpll_div2>, <&clk_sdio &clk_gpll_div2>,
+ <&clk_sfc &clk_gpll_div2>, <&clk_sdmmc0 &clk_gpll_div2>,
+ <&clk_tsp &clk_gpll_div2>, <&clk_nandc &clk_gpll_div2>,
+ <&clk_mac_pll &clk_cpll>;
+ rockchip,clocks-init-rate =
+ <&clk_core 816000000>, <&clk_gpll 594000000>,
+ <&clk_cpll 400000000>, <&aclk_cpu 300000000>,
+ <&hclk_cpu_pre 150000000>, <&pclk_cpu_pre 75000000>,
+ <&aclk_peri 300000000>, <&hclk_peri_pre 150000000>,
+ <&pclk_peri_pre 75000000>, <&clk_gpu_pre 300000000>,
+ <&aclk_vio0_pre 300000000>, <&hclk_vio_pre 150000000>,
+ <&aclk_vio1_pre 300000000>, <&clk_vepu 300000000>,
+ <&clk_vdpu 300000000>, <&clk_hevc_core 200000000>,
+ <&clk_mac_ref 50000000>;
+ /* rockchip,clocks-uboot-has-init =
+ <&aclk_vio1>;*/
+ };
+
+ clocks-enable {
+ compatible = "rockchip,clocks-enable";
+ clocks =
+ /*PD_CORE*/
+ <&clk_gates0 6>,<&clk_gates0 0>,
+ <&clk_gates0 7>,
+
+ /*PD_CPU*/
+ <&clk_gates0 1>, <&clk_gates0 3>,
+ <&clk_gates0 4>, <&clk_gates0 5>,
+ <&clk_gates0 12>,
+
+ /*TIMER*/
+ <&clk_gates10 3>, <&clk_gates10 4>,
+ <&clk_gates10 5>, <&clk_gates10 6>,
+ <&clk_gates10 7>, <&clk_gates10 8>,
+
+ /*PD_PERI*/
+ <&clk_gates2 0>, <&hclk_peri_pre>,
+ <&pclk_peri_pre>, <&clk_gates2 1>,
+
+ /*aclk_cpu_pre*/
+ <&clk_gates4 12>,/*aclk_intmem*/
+ <&clk_gates4 10>,/*aclk_strc_sys*/
+
+ /*hclk_cpu_pre*/
+ <&clk_gates5 6>,/*hclk_rom*/
+ <&clk_gates3 5>,/*hclk_crypto*/
+
+ /*pclk_cpu_pre*/
+ <&clk_gates5 4>,/*pclk_grf*/
+ <&clk_gates5 7>,/*pclk_ddrupctl*/
+ <&clk_gates5 14>,/*pclk_acodec*/
+ <&clk_gates3 8>,/*pclk_hdmi*/
+
+ /*aclk_peri_pre*/
+ <&clk_gates10 10>,/*aclk_gmac*/
+ <&clk_gates4 3>,/*aclk_peri_axi_matrix*/
+ <&clk_gates5 1>,/*aclk_dmac2*/
+ <&clk_gates9 15>,/*aclk_peri_niu*/
+ <&clk_gates4 2>,/*aclk_cpu_peri*/
+
+ /*hclk_peri_pre*/
+ <&clk_gates4 0>,/*hclk_peri_matrix*/
+ <&clk_gates9 13>,/*hclk_usb_peri*/
+ <&clk_gates9 14>,/*hclk_peri_arbi*/
+
+ /*pclk_peri_pre*/
+ <&clk_gates4 1>,/*pclk_peri_axi_matrix*/
+
+ /*hclk_vio_pre*/
+ <&clk_gates6 12>,/*hclk_vio_niu*/
+ <&clk_gates6 1>,/*hclk_lcdc*/
+
+ /*aclk_vio0_pre*/
+ <&clk_gates6 13>,/*aclk_vio*/
+ <&clk_gates6 0>,/*aclk_lcdc*/
+
+ /*aclk_vio1_pre*/
+ <&clk_gates9 10>,/*aclk_vio1_niu*/
+
+ /*UART*/
+ <&clk_gates1 12>,
+ <&clk_gates1 13>,
+ <&clk_gates8 2>,/*pclk_uart2*/
+
+ <&clk_gpu_pre>,
+
+ /*jtag*/
+ <&clk_gates1 3>,/*clk_jtag*/
+
+ /*pmu*/
+ <&clk_gates1 0>;/*pclk_pmu_pre*/
+ };
+
i2c0: i2c@20070000 {
compatible = "rockchip,rk30-i2c";
reg = <0x20070000 0x1000>;
reg = <0x10104000 0x800>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_enc", "irq_dec";
- clocks = <&aclk_vcodec_pre>, <&clk_gates3 12>;
+ clocks = <&clk_vdpu>, <&hclk_vdpu>;
clock-names = "aclk_vcodec", "hclk_vcodec";
name = "vpu_service";
status = "disabled";
reg = <0x10104000 0x400>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_dec";
- clocks = <&aclk_vcodec_pre>, <&clk_gates3 12>, <&clk_hevc_core>;
+ clocks = <&clk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>;
clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
name = "hevc_service";
status = "disabled";
};
static const struct pll_clk_set rk3036plus_pll_com_table[] = {
-// _RK3036_PLL_SET_CLKS(297000, 2, 99, 4, 1, 1, 0),
- _RK3036_PLL_SET_CLKS(594000, 2, 99, 2, 1, 1, 0),
_RK3036_PLL_SET_CLKS(1188000, 2, 99, 1, 1, 1, 0),
-
+ _RK3036_PLL_SET_CLKS(594000, 2, 99, 2, 1, 1, 0),
+ /*_RK3036_PLL_SET_CLKS(297000, 2, 99, 4, 1, 1, 0),*/
};
static const struct pll_clk_set rk312xplus_pll_com_table[] = {
- _RK3036_PLL_SET_CLKS(798000, 4, 133, 1, 1, 1, 0),
+ /*_RK3036_PLL_SET_CLKS(1064000, 3, 133, 1, 1, 1, 0),*/
+ /*_RK3036_PLL_SET_CLKS(798000, 2, 133, 2, 1, 1, 0),*/
_RK3036_PLL_SET_CLKS(594000, 2, 99, 2, 1, 1, 0),
- _RK3036_PLL_SET_CLKS(1064000, 3, 133, 1, 1, 1, 0),
-
+ _RK3036_PLL_SET_CLKS(500000, 6, 250, 2, 1, 1, 0),
+ _RK3036_PLL_SET_CLKS(400000, 6, 400, 2, 2, 1, 0),
};
static void pll_wait_lock(struct clk_hw *hw)
clk_debug("clksel0 %08x\n", cru_readl(RK3036_CRU_CLKSELS_CON(0)));
clk_debug("clksel1 %08x\n", cru_readl(RK3036_CRU_CLKSELS_CON(1)));
if (ps->rate == rate) {
- printk("apll get a rate\n");
+ clk_debug("apll get a rate\n");
/*enter slowmode*/
local_irq_save(flags);
.set_rate = clk_pll_set_rate_3036plus_auto,
};
+static long clk_cpll_round_rate_312xplus(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ struct clk *parent = __clk_get_parent(hw->clk);
+
+ if (parent && (rate == __clk_get_rate(parent))) {
+ clk_debug("pll %s round rate=%lu equal to parent rate\n",
+ __clk_get_name(hw->clk), rate);
+ return rate;
+ }
+
+ return (pll_com_get_best_set(rate, rk312xplus_pll_com_table)->rate);
+}
+
static int clk_cpll_set_rate_312xplus(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
static const struct clk_ops clk_pll_ops_312xplus = {
.recalc_rate = clk_pll_recalc_rate_3036_apll,
- .round_rate = clk_pll_round_rate_3036plus_auto,
+ .round_rate = clk_cpll_round_rate_312xplus,
.set_rate = clk_cpll_set_rate_312xplus,
};
projects / firefly-linux-kernel-4.4.55.git / commitdiff