Ignore multi-instruction patterns. e.g.

def : Pat<(i8 (trunc GR32:$src)),
          (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src), x86_subreg_8bit))>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55875 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/utils/TableGen/FastISelEmitter.cpp b/utils/TableGen/FastISelEmitter.cpp
index 3d07405be55894278f4f1860204b3e1cab8b774d..6f47c633e164beaedc0d60c3052962e0151cfef4 100644 (file)
--- a/utils/TableGen/FastISelEmitter.cpp
+++ b/utils/TableGen/FastISelEmitter.cpp
@@ -259,6 +259,20 @@ void FastISelMap::CollectPatterns(CodeGenDAGPatterns &CGP) {
     if (II.OperandList.empty())
       continue;
 
+    // For now, ignore multi-instruction patterns.
+    bool MultiInsts = false;
+    for (unsigned i = 0, e = Dst->getNumChildren(); i != e; ++i) {
+      TreePatternNode *ChildOp = Dst->getChild(i);
+      if (ChildOp->isLeaf())
+        continue;
+      if (ChildOp->getOperator()->isSubClassOf("Instruction")) {
+        MultiInsts = true;
+        break;
+      }
+    }
+    if (MultiInsts)
+      continue;
+
     // For now, ignore instructions where the first operand is not an
     // output register.
     const CodeGenRegisterClass *DstRC = 0;