Tighten operand checking on CPS instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137172 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index dc19f4657c5f5e7434d27410d9b8d5a4dfe3df77..34b3e62a2e2f2ddca9001d509f36703708dc0a2e 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -1390,6 +1390,7 @@ class CPS<dag iops, string asm_ops>
   let Inst{4-0}   = mode;
 }
 
+let DecoderMethod = "DecodeCPSInstruction" in {
 let M = 1 in
   def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
                   "$imod\t$iflags, $mode">;
@@ -1398,6 +1399,7 @@ let mode = 0, M = 0 in
 
 let imod = 0, iflags = 0, M = 1 in
   def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
+}
 
 // Preload signals the memory system of possible future data/instruction access.
 // These are for disassembly only.

diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index d7b88560d711b7247fa34c925780854a4254bbef..a3fa138ba64ee383de9e8974bcbce15947d6dcc3 100644 (file)
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -83,6 +83,8 @@ static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
                                                   const void *Decoder);
 static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
+static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
+                               uint64_t Address, const void *Decoder);
 static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
 static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
@@ -1139,6 +1141,9 @@ static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
   unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
   unsigned mode = fieldFromInstruction32(Insn, 0, 5);
 
+  // imod == '01' --> UNPREDICTABLE
+  if (imod == 1) return false;
+
   if (M && mode && imod && iflags) {
     Inst.setOpcode(ARM::CPS3p);
     Inst.addOperand(MCOperand::CreateImm(imod));

diff --git a/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt b/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt
index d3a75cb80c21b7ebffe22dc0b2599fa14556961d..10748e9b1269d532042052c50c1fafdd01648944 100644 (file)
--- a/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt
+++ b/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt
@@ -1,5 +1,4 @@
 # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
-# XFAIL: *
 
 # invalid imod value (0b01)
 0xc0 0x67 0x4 0xf1

diff --git a/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt b/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt
index cc6062eae4fc17786a47be60b9e490ef96f3f05b..5202217b6a71d4578cb03c4e012298accedb6772 100644 (file)
--- a/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt
+++ b/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt
@@ -1,5 +1,4 @@
 # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
-# XFAIL: *
 
 # invalid (imod, M, iflags) combination
 0x93 0x1c 0x02 0xf1