m68knommu: make ColdFire Park and Assignment register definitions absolute addresses

Make all definitions of the ColdFire MPARK and IRQ Assignment registers
absolute addresses. Currently some are relative to the MBAR peripheral
region.

The various ColdFire parts use different methods to address the internal
registers, some are absolute, some are relative to peripheral regions
which can be mapped at different address ranges (such as the MBAR and IPSBAR
registers). We don't want to deal with this in the code when we are
accessing these registers, so make all register definitions the absolute
address - factoring out whether it is an offset into a peripheral region.

This makes them all consistently defined, and reduces the occasional bugs
caused by inconsistent definition of the register addresses.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>

diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
index 02ada05f53f9570eee0a6e5df04e4f60e098bb6a..3d9c7d73982918e3387f1e0124b18517107f2a14 100644 (file)
--- a/arch/m68k/include/asm/m5249sim.h
+++ b/arch/m68k/include/asm/m5249sim.h
@@ -30,8 +30,8 @@
 #define        MCFSIM_SWIVR            (MCF_MBAR + 0x02)       /* SW Watchdog intr */
 #define        MCFSIM_SWSR             (MCF_MBAR + 0x03)       /* SW Watchdog srv */
 #define        MCFSIM_PAR              (MCF_MBAR + 0x04)       /* Pin Assignment */
-#define        MCFSIM_IRQPAR           0x06            /* Interrupt Assignment reg (r/w) */
-#define        MCFSIM_MPARK            0x0C            /* BUS Master Control Reg*/
+#define        MCFSIM_IRQPAR           (MCF_MBAR + 0x06)       /* Intr Assignment */
+#define        MCFSIM_MPARK            (MCF_MBAR + 0x0C)       /* BUS Master Ctrl */
 #define        MCFSIM_IPR              (MCF_MBAR + 0x40)       /* Interrupt Pending */
 #define        MCFSIM_IMR              (MCF_MBAR + 0x44)       /* Interrupt Mask */
 #define        MCFSIM_AVR              (MCF_MBAR + 0x4b)       /* Autovector Ctrl */

diff --git a/arch/m68k/include/asm/m525xsim.h b/arch/m68k/include/asm/m525xsim.h
index 158fdd4df51f4084847199a35f9fc00d5eae3435..acab61cb91ed9589922724c11501123230ea51c4 100644 (file)
--- a/arch/m68k/include/asm/m525xsim.h
+++ b/arch/m68k/include/asm/m525xsim.h
@@ -30,7 +30,7 @@
 #define MCFSIM_SYPCR           (MCF_MBAR + 0x01)       /* System Protection */
 #define MCFSIM_SWIVR           (MCF_MBAR + 0x02)       /* SW Watchdog intr */
 #define MCFSIM_SWSR            (MCF_MBAR + 0x03)       /* SW Watchdog srv */
-#define MCFSIM_MPARK           0x0C            /* BUS Master Control Reg*/
+#define MCFSIM_MPARK           (MCF_MBAR + 0x0C)       /* BUS Master Ctrl */
 #define MCFSIM_IPR             (MCF_MBAR + 0x40)       /* Interrupt Pending */
 #define MCFSIM_IMR             (MCF_MBAR + 0x44)       /* Interrupt Mask */
 #define MCFSIM_ICR0            (MCF_MBAR + 0x4c)       /* Intr Ctrl reg 0 */

diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
index a02071889fb3f4f4ccb2e2726d8873c04aaeead9..a8e7519c49850227b52f79b95dcb09837ed25824 100644 (file)
--- a/arch/m68k/include/asm/m5307sim.h
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -28,9 +28,9 @@
 #define        MCFSIM_SWIVR            (MCF_MBAR + 0x02)       /* SW Watchdog intr */
 #define        MCFSIM_SWSR             (MCF_MBAR + 0x03)       /* SW Watchdog service*/
 #define        MCFSIM_PAR              (MCF_MBAR + 0x04)       /* Pin Assignment */
-#define        MCFSIM_IRQPAR           0x06            /* Interrupt Assignment reg (r/w) */
-#define        MCFSIM_PLLCR            0x08            /* PLL Control Reg*/
-#define        MCFSIM_MPARK            0x0C            /* BUS Master Control Reg*/
+#define        MCFSIM_IRQPAR           (MCF_MBAR + 0x06)       /* Itr Assignment */
+#define        MCFSIM_PLLCR            (MCF_MBAR + 0x08)       /* PLL Ctrl Reg */
+#define        MCFSIM_MPARK            (MCF_MBAR + 0x0C)       /* BUS Master Ctrl */
 #define        MCFSIM_IPR              (MCF_MBAR + 0x40)       /* Interrupt Pend */
 #define        MCFSIM_IMR              (MCF_MBAR + 0x44)       /* Interrupt Mask */
 #define        MCFSIM_AVR              (MCF_MBAR + 0x4b)       /* Autovector Ctrl */

diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h
index e6e48c1ee2db3866e058330e27d20a4bc21d9255..cc485ba31bc8abee7950508d1ac1c88215c3b9e2 100644 (file)
--- a/arch/m68k/include/asm/m5407sim.h
+++ b/arch/m68k/include/asm/m5407sim.h
@@ -28,9 +28,9 @@
 #define        MCFSIM_SWIVR            (MCF_MBAR + 0x02)       /* SW Watchdog intr */
 #define        MCFSIM_SWSR             (MCF_MBAR + 0x03)       /* SW Watchdog service*/
 #define        MCFSIM_PAR              (MCF_MBAR + 0x04)       /* Pin Assignment */
-#define        MCFSIM_IRQPAR           0x06            /* Interrupt Assignment reg (r/w) */
-#define        MCFSIM_PLLCR            0x08            /* PLL Control Reg*/
-#define        MCFSIM_MPARK            0x0C            /* BUS Master Control Reg*/
+#define        MCFSIM_IRQPAR           (MCF_MBAR + 0x06)       /* Intr Assignment */
+#define        MCFSIM_PLLCR            (MCF_MBAR + 0x08)       /* PLL Ctrl */
+#define        MCFSIM_MPARK            (MCF_MBAR + 0x0C)       /* BUS Master Ctrl */
 #define        MCFSIM_IPR              (MCF_MBAR + 0x40)       /* Interrupt Pending */
 #define        MCFSIM_IMR              (MCF_MBAR + 0x44)       /* Interrupt Mask */
 #define        MCFSIM_AVR              (MCF_MBAR + 0x4b)       /* Autovector Ctrl */