MachineOperand &MO = MI->getOperand(OpIdx);
MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
- // XXX - This shouldn't be VSrc
const TargetRegisterClass *RC = RI.getRegClass(RCID);
unsigned Opcode = AMDGPU::V_MOV_B32_e32;
if (MO.isReg()) {
Opcode = AMDGPU::S_MOV_B32;
}
- unsigned Reg = MRI.createVirtualRegister(RI.getRegClass(RCID));
+ const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
+ unsigned Reg = MRI.createVirtualRegister(VRC);
BuildMI(*MI->getParent(), I, MI->getParent()->findDebugLoc(I), get(Opcode),
Reg).addOperand(MO);
MO.ChangeToRegister(Reg, false);
const TargetRegisterClass *SRC) const {
if (hasVGPRs(SRC)) {
return SRC;
+ } else if (SRC == &AMDGPU::SCCRegRegClass) {
+ return &AMDGPU::VCCRegRegClass;
} else if (getCommonSubClass(SRC, &AMDGPU::SGPR_32RegClass)) {
return &AMDGPU::VReg_32RegClass;
} else if (getCommonSubClass(SRC, &AMDGPU::SGPR_64RegClass)) {
ret void
}
-; SI-LABEL: @one_sgpr:
-define void @one_sgpr(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 addrspace(1)* noalias %in_bar, i64 %a) {
+; Check that the SGPR add operand is correctly moved to a VGPR.
+; SI-LABEL: @sgpr_operand:
+define void @sgpr_operand(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 addrspace(1)* noalias %in_bar, i64 %a) {
%foo = load i64 addrspace(1)* %in, align 8
%result = add i64 %foo, %a
store i64 %result, i64 addrspace(1)* %out
ret void
}
-; FIXME: This case is broken
-;
; Swap the arguments. Check that the SGPR -> VGPR copy works with the
; SGPR as other operand.
;
-; XXXSI-LABEL: @one_sgpr_reversed:
-; define void @one_sgpr_reversed(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 %a) {
-; %foo = load i64 addrspace(1)* %in, align 8
-; %result = add i64 %a, %foo
-; store i64 %result, i64 addrspace(1)* %out
-; ret void
-; }
+; SI-LABEL: @sgpr_operand_reversed:
+define void @sgpr_operand_reversed(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 %a) {
+ %foo = load i64 addrspace(1)* %in, align 8
+ %result = add i64 %a, %foo
+ store i64 %result, i64 addrspace(1)* %out
+ ret void
+}
; SI-LABEL: @test_v2i64_sreg: