clk: vt8500: Fix error in PLL calculations on non-exact match.

When a PLL frequency calculation is performed and a non-exact match
is found the wrong multiplier and divisors are returned.

Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c
index fe25570874d6b63dd937111a3664dbec9d244e32..0cb26bef427dd98af0ca54c64448bb7cf7ea3fdf 100644 (file)
--- a/drivers/clk/clk-vt8500.c
+++ b/drivers/clk/clk-vt8500.c
@@ -361,9 +361,9 @@ static void wm8650_find_pll_bits(unsigned long rate, unsigned long parent_rate,
        /* if we got here, it wasn't an exact match */
        pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
                                                        rate - best_err);
-       *multiplier = mul;
-       *divisor1 = div1;
-       *divisor2 = div2;
+       *multiplier = best_mul;
+       *divisor1 = best_div1;
+       *divisor2 = best_div2;
 }
 
 static int vtwm_pll_set_rate(struct clk_hw *hw, unsigned long rate,