UPSTREAM: clk: rockchip: allow varying mux parameters for cpuclk pll-sources

Thers are only two parent PLLs that APLL and GPLL for core on the
previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed
GPLL as alternate parent when core is switching freq.

Since RK3399 big.LITTLE architecture, we need to select and adapt
more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.7-clk/next
 commit 0fda2be634398f4b8d53c0436311f99557e56c4e)

Conflicts:

	drivers/clk/rockchip/clk-rk3228.c
[zx: there is no rk3228 clock controller, apply this patch for
clk-rk3366.]

Change-Id: I48fde9facccd41585873c997b0b02a7a73972717

diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c
index d07374f48caf7ee6d8c5b8f6ed82cca089e964d0..97821c103487b22c9d574a2357800f77809e0307 100644 (file)
--- a/drivers/clk/rockchip/clk-cpu.c
+++ b/drivers/clk/rockchip/clk-cpu.c
@@ -158,12 +158,16 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk,
 
                writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask,
                                              reg_data->div_core_shift) |
-                      HIWORD_UPDATE(1, 1, reg_data->mux_core_shift),
+                      HIWORD_UPDATE(reg_data->mux_core_alt,
+                                    reg_data->mux_core_mask,
+                                    reg_data->mux_core_shift),
                       cpuclk->reg_base + reg_data->core_reg);
        } else {
                /* select alternate parent */
-               writel(HIWORD_UPDATE(1, 1, reg_data->mux_core_shift),
-                       cpuclk->reg_base + reg_data->core_reg);
+               writel(HIWORD_UPDATE(reg_data->mux_core_alt,
+                                    reg_data->mux_core_mask,
+                                    reg_data->mux_core_shift),
+                      cpuclk->reg_base + reg_data->core_reg);
        }
 
        spin_unlock_irqrestore(cpuclk->lock, flags);
@@ -198,7 +202,9 @@ static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk,
 
        writel(HIWORD_UPDATE(0, reg_data->div_core_mask,
                                reg_data->div_core_shift) |
-              HIWORD_UPDATE(0, 1, reg_data->mux_core_shift),
+              HIWORD_UPDATE(reg_data->mux_core_main,
+                               reg_data->mux_core_mask,
+                               reg_data->mux_core_shift),
               cpuclk->reg_base + reg_data->core_reg);
 
        if (ndata->old_rate > ndata->new_rate)

diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
index c289fdc3a17fcf489cbc2539c6a36fe7cf0e28d7..c9a53209333e04313ee1f88e3777395dc123ec57 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -113,7 +113,10 @@ static const struct rockchip_cpuclk_reg_data rk3036_cpuclk_data = {
        .core_reg = RK2928_CLKSEL_CON(0),
        .div_core_shift = 0,
        .div_core_mask = 0x1f,
+       .mux_core_alt = 1,
+       .mux_core_main = 0,
        .mux_core_shift = 7,
+       .mux_core_mask = 0x1,
 };
 
 PNAME(mux_pll_p)               = { "xin24m", "xin24m" };

diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
index 7f7444cbf6fcc0e62ae85c195792edc10daca2f3..eb1fbda5eedc2ae643fe270e9377b301ad0330d4 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -155,7 +155,10 @@ static const struct rockchip_cpuclk_reg_data rk3066_cpuclk_data = {
        .core_reg = RK2928_CLKSEL_CON(0),
        .div_core_shift = 0,
        .div_core_mask = 0x1f,
+       .mux_core_alt = 1,
+       .mux_core_main = 0,
        .mux_core_shift = 8,
+       .mux_core_mask = 0x1,
 };
 
 #define RK3188_DIV_ACLK_CORE_MASK      0x7
@@ -191,7 +194,10 @@ static const struct rockchip_cpuclk_reg_data rk3188_cpuclk_data = {
        .core_reg = RK2928_CLKSEL_CON(0),
        .div_core_shift = 9,
        .div_core_mask = 0x1f,
+       .mux_core_alt = 1,
+       .mux_core_main = 0,
        .mux_core_shift = 8,
+       .mux_core_mask = 0x1,
 };
 
 PNAME(mux_pll_p)               = { "xin24m", "xin32k" };

diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 05589e56d7da7dea20ba1f7f7c81b921c54c029a..83bd68d86bea9fd922aca5afe1ce5664ed709279 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -165,7 +165,10 @@ static const struct rockchip_cpuclk_reg_data rk3288_cpuclk_data = {
        .core_reg = RK3288_CLKSEL_CON(0),
        .div_core_shift = 8,
        .div_core_mask = 0x1f,
+       .mux_core_alt = 1,
+       .mux_core_main = 0,
        .mux_core_shift = 15,
+       .mux_core_mask = 0x1,
 };
 
 PNAME(mux_pll_p)               = { "xin24m", "xin32k" };

diff --git a/drivers/clk/rockchip/clk-rk3366.c b/drivers/clk/rockchip/clk-rk3366.c
index 8c95e07440851a98b6f24607ceb84074a337eeea..c6d356dced2cc250a8bf2057677f14c98a7592dc 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3366.c
+++ b/drivers/clk/rockchip/clk-rk3366.c
@@ -148,7 +148,10 @@ static const struct rockchip_cpuclk_reg_data rk3366_cpuclk_data = {
        .core_reg = RK3368_CLKSEL_CON(0),
        .div_core_shift = 0,
        .div_core_mask = 0x1f,
+       .mux_core_alt = 1,
+       .mux_core_main = 0,
        .mux_core_shift = 6,
+       .mux_core_mask = 0x1,
 };
 
 #define RK3366_DIV_ACLKM_MASK          0x1f

diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index 74c4ea65d3fe153c6dc8c2328e82b90d6c989c6e..b5c2c363da72db88fa9064a1c3e0da6d296e7a82 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -166,14 +166,20 @@ static const struct rockchip_cpuclk_reg_data rk3368_cpuclkb_data = {
        .core_reg = RK3368_CLKSEL_CON(0),
        .div_core_shift = 0,
        .div_core_mask = 0x1f,
+       .mux_core_alt = 1,
+       .mux_core_main = 0,
        .mux_core_shift = 7,
+       .mux_core_mask = 0x1,
 };
 
 static const struct rockchip_cpuclk_reg_data rk3368_cpuclkl_data = {
        .core_reg = RK3368_CLKSEL_CON(2),
        .div_core_shift = 0,
+       .mux_core_alt = 1,
+       .mux_core_main = 0,
        .div_core_mask = 0x1f,
        .mux_core_shift = 7,
+       .mux_core_mask = 0x1,
 };
 
 #define RK3368_DIV_ACLKM_MASK          0x1f

diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 7e3a084f92c04ba7837b6110af5ac19e06c598fd..5c8079183d62281d6f99fbfa89c15a8c92d60e0a 100644 (file)
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -209,14 +209,20 @@ struct rockchip_cpuclk_rate_table {
  * @core_reg:          register offset of the core settings register
  * @div_core_shift:    core divider offset used to divide the pll value
  * @div_core_mask:     core divider mask
+ * @mux_core_alt:      mux value to select alternate parent
+ * @mux_core_main:     mux value to select main parent of core
  * @mux_core_shift:    offset of the core multiplexer
+ * @mux_core_mask:     core multiplexer mask
  */
 struct rockchip_cpuclk_reg_data {
        int             core_reg;
        u8              div_core_shift;
        u32             div_core_mask;
        int             mux_core_reg;
+       u8              mux_core_alt;
+       u8              mux_core_main;
        u8              mux_core_shift;
+       u32             mux_core_mask;
 };
 
 struct clk *rockchip_clk_register_cpuclk(const char *name,