[mips][microMIPS][DSP] Implement PACKRL.PH, PICK.PH, PICK.QB, SHILO, SHILOV and WRDSP...

Differential Revision: http://reviews.llvm.org/D14429

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255991 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 14e63ad0c2be7f825546a58fef61cb7cb9d0edd4..4e7a20130aebfd64d25221b9627c06c92a6eeaaa 100644 (file)
--- a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -1003,8 +1003,8 @@ public:
   template <unsigned Bits, int Offset = 0> bool isConstantUImm() const {
     return isConstantImm() && isUInt<Bits>(getConstantImm() - Offset);
   }
-  template <unsigned Bits> bool isUImm() const {
-    return isImm() && isConstantImm() && isUInt<Bits>(getConstantImm());
+  template <unsigned Bits> bool isConstantSImm() const {
+    return isConstantImm() && isInt<Bits>(getConstantImm());
   }
   bool isToken() const override {
     // Note: It's not possible to pretend that other operand kinds are tokens.
@@ -3650,6 +3650,12 @@ bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_UImm6_0:
     return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
                  "expected 6-bit unsigned immediate");
+  case Match_SImm6:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+                 "expected 6-bit signed immediate");
+  case Match_UImm7_0:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+                 "expected 7-bit unsigned immediate");
   case Match_UImm8_0:
     return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
                  "expected 8-bit unsigned immediate");

diff --git a/lib/Target/Mips/MicroMipsDSPInstrFormats.td b/lib/Target/Mips/MicroMipsDSPInstrFormats.td
index f24f80282b5e69c783e87a606400c8b9cafd62da..f11c09abfc367dd46798d21240a957cf30750c0d 100644 (file)
--- a/lib/Target/Mips/MicroMipsDSPInstrFormats.td
+++ b/lib/Target/Mips/MicroMipsDSPInstrFormats.td
@@ -16,6 +16,12 @@ class MMDSPInst<string opstr = "">
   let DecoderNamespace = "MicroMips";
 }
 
+class MMDSPInstAlias<string Asm, dag Result, bit Emit = 0b1>
+    : InstAlias<Asm, Result, Emit>, PredicateControl {
+  let InsnPredicates = [HasDSP];
+  let AdditionalPredicates = [InMicroMips];
+}
+
 class POOL32A_3R_FMT<string opstr, bits<11> op> : MMDSPInst<opstr> {
   bits<5> rd;
   bits<5> rs;
@@ -212,3 +218,27 @@ class POOL32A_1RIMM8_FMT<string opstr, bits<6> op> : MMDSPInst<opstr> {
   let Inst{11-6}  = op;
   let Inst{5-0}   = 0b111100;
 }
+
+class POOL32A_4B0SHIFT6AC4B0_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
+  bits<6> shift;
+  bits<2> ac;
+
+  let Inst{31-26} = 0b000000;
+  let Inst{25-22} = 0b0000;
+  let Inst{21-16} = shift;
+  let Inst{15-14} = ac;
+  let Inst{13-10} = 0b0000;
+  let Inst{9-0}   = op;
+}
+
+class POOL32A_5B01RAC_FMT<string opstr, bits<8> op> : MMDSPInst<opstr> {
+  bits<5> rs;
+  bits<2> ac;
+
+  let Inst{31-26} = 0b000000;
+  let Inst{25-21} = 0b00000;
+  let Inst{20-16} = rs;
+  let Inst{15-14} = ac;
+  let Inst{13-6}  = op;
+  let Inst{5-0}   = 0b111100;
+}

diff --git a/lib/Target/Mips/MicroMipsDSPInstrInfo.td b/lib/Target/Mips/MicroMipsDSPInstrInfo.td
index 9b4fb68531803264abecea60f12dea4fe2dde340..b342e2371df4ce3e3c77334105789e834e208916 100644 (file)
--- a/lib/Target/Mips/MicroMipsDSPInstrInfo.td
+++ b/lib/Target/Mips/MicroMipsDSPInstrInfo.td
@@ -149,6 +149,12 @@ class REPL_QB_MM_ENC : POOL32A_1RIMM8_FMT<"repl.qb", 0b010111>;
 class REPLV_PH_MM_ENC : POOL32A_2R_FMT<"replv.ph", 0b0000001100>;
 class REPLV_QB_MM_ENC : POOL32A_2R_FMT<"replv.qb", 0b0001001100>;
 class MTHLIP_MM_ENC : POOL32A_1RAC_FMT<"mthlip", 0b00001001>;
+class PACKRL_PH_MM_ENC : POOL32A_3RB0_FMT<"packrl.ph", 0b0110101101>;
+class PICK_PH_MM_ENC : POOL32A_3RB0_FMT<"pick.ph", 0b1000101101>;
+class PICK_QB_MM_ENC : POOL32A_3RB0_FMT<"pick.qb", 0b0111101101>;
+class SHILO_MM_ENC : POOL32A_4B0SHIFT6AC4B0_FMT<"shilo", 0b0000011101>;
+class SHILOV_MM_ENC : POOL32A_5B01RAC_FMT<"shilov", 0b01001001>;
+class WRDSP_MM_ENC : POOL32A_1RMASK7_FMT<"wrdsp", 0b01011001>;
 
 // Instruction desc.
 class ABSQ_S_PH_MM_R2_DESC_BASE<string opstr, SDPatternOperator OpNode,
@@ -354,6 +360,15 @@ class REPLV_QB_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<"replv.qb", int_mips_repl_qb,
                                                    NoItinerary, DSPROpnd,
                                                    GPR32Opnd>;
 
+class WRDSP_MM_DESC {
+  dag OutOperandList = (outs);
+  dag InOperandList = (ins GPR32Opnd:$rt, uimm7:$mask);
+  string AsmString = !strconcat("wrdsp", "\t$rt, $mask");
+  list<dag> Pattern = [(int_mips_wrdsp GPR32Opnd:$rt, immZExt7:$mask)];
+  InstrItinClass Itinerary = NoItinerary;
+}
+
+// Instruction defs.
 // microMIPS DSP Rev 1
 def ADDQ_PH_MM : DspMMRel, ADDQ_PH_MM_ENC, ADDQ_PH_DESC;
 def ADDQ_S_PH_MM : DspMMRel, ADDQ_S_PH_MM_ENC, ADDQ_S_PH_DESC;
@@ -451,6 +466,12 @@ def REPL_QB_MM : DspMMRel, REPL_QB_MM_ENC, REPL_QB_MM_DESC;
 def REPLV_PH_MM : DspMMRel, REPLV_PH_MM_ENC, REPLV_PH_MM_DESC;
 def REPLV_QB_MM : DspMMRel, REPLV_QB_MM_ENC, REPLV_QB_MM_DESC;
 def MTHLIP_MM : DspMMRel, MTHLIP_MM_ENC, MTHLIP_DESC;
+def PACKRL_PH_MM : DspMMRel, PACKRL_PH_MM_ENC, PACKRL_PH_DESC;
+def PICK_PH_MM : DspMMRel, PICK_PH_MM_ENC, PICK_PH_DESC;
+def PICK_QB_MM : DspMMRel, PICK_QB_MM_ENC, PICK_QB_DESC;
+def SHILO_MM : DspMMRel, SHILO_MM_ENC, SHILO_DESC;
+def SHILOV_MM : DspMMRel, SHILOV_MM_ENC, SHILOV_DESC;
+def WRDSP_MM : DspMMRel, WRDSP_MM_ENC, WRDSP_MM_DESC;
 // microMIPS DSP Rev 2
 def ABSQ_S_QB_MMR2 : DspMMRel, ABSQ_S_QB_MMR2_ENC, ABSQ_S_QB_MMR2_DESC,
                      ISA_DSPR2;
@@ -502,3 +523,6 @@ def PRECR_SRA_PH_W_MMR2 : DspMMRel, PRECR_SRA_PH_W_MMR2_ENC,
 def PRECR_SRA_R_PH_W_MMR2 : DspMMRel, PRECR_SRA_R_PH_W_MMR2_ENC,
                             PRECR_SRA_R_PH_W_DESC, ISA_DSPR2;
 def PREPEND_MMR2 : DspMMRel, PREPEND_MMR2_ENC, PREPEND_DESC, ISA_DSPR2;
+
+// Instruction alias.
+def : MMDSPInstAlias<"wrdsp $rt", (WRDSP_MM GPR32Opnd:$rt, 0x1F), 1>;

diff --git a/lib/Target/Mips/MipsDSPInstrFormats.td b/lib/Target/Mips/MipsDSPInstrFormats.td
index 4279b6fbe3052284271a3b9acecfc3317475ec5f..f959bd4d8db3f7d4a9e4985c4bed8783e754b99a 100644 (file)
--- a/lib/Target/Mips/MipsDSPInstrFormats.td
+++ b/lib/Target/Mips/MipsDSPInstrFormats.td
@@ -41,16 +41,21 @@ def SPECIAL3_OPCODE : Field6<0b011111>;
 def REGIMM_OPCODE : Field6<0b000001>;
 
 class DSPInst<string opstr = "">
-    : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
-  let Predicates = [HasDSP];
+    : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, PredicateControl {
+  let InsnPredicates = [HasDSP];
   string BaseOpcode = opstr;
   string Arch = "dsp";
 }
 
 class PseudoDSP<dag outs, dag ins, list<dag> pattern,
-                InstrItinClass itin = IIPseudo>:
-  MipsPseudo<outs, ins, pattern, itin> {
-  let Predicates = [HasDSP];
+                InstrItinClass itin = IIPseudo>
+    : MipsPseudo<outs, ins, pattern, itin>, PredicateControl {
+  let InsnPredicates = [HasDSP];
+}
+
+class DSPInstAlias<string Asm, dag Result, bit Emit = 0b1>
+    : InstAlias<Asm, Result, Emit>, PredicateControl {
+  let InsnPredicates = [HasDSP];
 }
 
 // ADDU.QB sub-class format.

diff --git a/lib/Target/Mips/MipsDSPInstrInfo.td b/lib/Target/Mips/MipsDSPInstrInfo.td
index f696a38ac0f063f52cddf7a775e1bef4a667ab5d..da6f174e2a199481d90824a62ee7eb7b2c9ee1e5 100644 (file)
--- a/lib/Target/Mips/MipsDSPInstrInfo.td
+++ b/lib/Target/Mips/MipsDSPInstrInfo.td
@@ -16,6 +16,7 @@ def immZExt1 : ImmLeaf<i32, [{return isUInt<1>(Imm);}]>;
 def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>;
 def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>;
 def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>;
+def immZExt7 : ImmLeaf<i32, [{return isUInt<7>(Imm);}]>;
 def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>;
 def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>;
 def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>;
@@ -408,11 +409,12 @@ class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 
 class SHILO_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
-  dag InOperandList = (ins simm16:$shift, ACC64DSPOpnd:$acin);
+  dag InOperandList = (ins simm6:$shift, ACC64DSPOpnd:$acin);
   string AsmString = !strconcat(instr_asm, "\t$ac, $shift");
   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
                         (OpNode immSExt6:$shift, ACC64DSPOpnd:$acin))];
   string Constraints = "$acin = $ac";
+  string BaseOpcode = instr_asm;
 }
 
 class SHILO_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
@@ -422,6 +424,7 @@ class SHILO_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
                         (OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))];
   string Constraints = "$acin = $ac";
+  string BaseOpcode = instr_asm;
 }
 
 class MTHLIP_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
@@ -447,10 +450,11 @@ class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 class WRDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
                       InstrItinClass itin> {
   dag OutOperandList = (outs);
-  dag InOperandList = (ins GPR32Opnd:$rs, uimm16:$mask);
+  dag InOperandList = (ins GPR32Opnd:$rs, uimm10:$mask);
   string AsmString = !strconcat(instr_asm, "\t$rs, $mask");
   list<dag> Pattern = [(OpNode GPR32Opnd:$rs, immZExt10:$mask)];
   InstrItinClass Itinerary = itin;
+  string BaseOpcode = instr_asm;
 }
 
 class DPA_W_PH_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
@@ -1183,13 +1187,13 @@ def CMP_EQ_PH : CMP_EQ_PH_ENC, CMP_EQ_PH_DESC;
 def CMP_LT_PH : CMP_LT_PH_ENC, CMP_LT_PH_DESC;
 def CMP_LE_PH : CMP_LE_PH_ENC, CMP_LE_PH_DESC;
 def BITREV : BITREV_ENC, BITREV_DESC;
-def PACKRL_PH : PACKRL_PH_ENC, PACKRL_PH_DESC;
+def PACKRL_PH : DspMMRel, PACKRL_PH_ENC, PACKRL_PH_DESC;
 def REPL_QB : DspMMRel, REPL_QB_ENC, REPL_QB_DESC;
 def REPL_PH : DspMMRel, REPL_PH_ENC, REPL_PH_DESC;
 def REPLV_QB : DspMMRel, REPLV_QB_ENC, REPLV_QB_DESC;
 def REPLV_PH : DspMMRel, REPLV_PH_ENC, REPLV_PH_DESC;
-def PICK_QB : PICK_QB_ENC, PICK_QB_DESC;
-def PICK_PH : PICK_PH_ENC, PICK_PH_DESC;
+def PICK_QB : DspMMRel, PICK_QB_ENC, PICK_QB_DESC;
+def PICK_PH : DspMMRel, PICK_PH_ENC, PICK_PH_DESC;
 def LWX : DspMMRel, LWX_ENC, LWX_DESC;
 def LHX : DspMMRel, LHX_ENC, LHX_DESC;
 def LBUX : DspMMRel, LBUX_ENC, LBUX_DESC;
@@ -1207,63 +1211,61 @@ def EXTR_RS_W : DspMMRel, EXTR_RS_W_ENC, EXTR_RS_W_DESC;
 def EXTRV_RS_W : DspMMRel, EXTRV_RS_W_ENC, EXTRV_RS_W_DESC;
 def EXTR_S_H : DspMMRel, EXTR_S_H_ENC, EXTR_S_H_DESC;
 def EXTRV_S_H : DspMMRel, EXTRV_S_H_ENC, EXTRV_S_H_DESC;
-def SHILO : SHILO_ENC, SHILO_DESC;
-def SHILOV : SHILOV_ENC, SHILOV_DESC;
+def SHILO : DspMMRel, SHILO_ENC, SHILO_DESC;
+def SHILOV : DspMMRel, SHILOV_ENC, SHILOV_DESC;
 def MTHLIP : DspMMRel, MTHLIP_ENC, MTHLIP_DESC;
 def RDDSP : DspMMRel, RDDSP_ENC, RDDSP_DESC;
-def WRDSP : WRDSP_ENC, WRDSP_DESC;
+let AdditionalPredicates = [NotInMicroMips] in {
+  def WRDSP : WRDSP_ENC, WRDSP_DESC;
+}
 
 // MIPS DSP Rev 2
-let Predicates = [HasDSPR2] in {
-
-def ADDU_PH : DspMMRel, ADDU_PH_ENC, ADDU_PH_DESC;
-def ADDU_S_PH : DspMMRel, ADDU_S_PH_ENC, ADDU_S_PH_DESC;
-def SUBU_PH : DspMMRel, SUBU_PH_ENC, SUBU_PH_DESC;
-def SUBU_S_PH : DspMMRel, SUBU_S_PH_ENC, SUBU_S_PH_DESC;
-def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC;
-def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC;
-def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC;
-def ABSQ_S_QB : DspMMRel, ABSQ_S_QB_ENC, ABSQ_S_QB_DESC;
-def ADDUH_QB : DspMMRel, ADDUH_QB_ENC, ADDUH_QB_DESC;
-def ADDUH_R_QB : DspMMRel, ADDUH_R_QB_ENC, ADDUH_R_QB_DESC;
-def SUBUH_QB : DspMMRel, SUBUH_QB_ENC, SUBUH_QB_DESC;
-def SUBUH_R_QB : DspMMRel, SUBUH_R_QB_ENC, SUBUH_R_QB_DESC;
-def ADDQH_PH : DspMMRel, ADDQH_PH_ENC, ADDQH_PH_DESC;
-def ADDQH_R_PH : DspMMRel, ADDQH_R_PH_ENC, ADDQH_R_PH_DESC;
-def SUBQH_PH : DspMMRel, SUBQH_PH_ENC, SUBQH_PH_DESC;
-def SUBQH_R_PH : DspMMRel, SUBQH_R_PH_ENC, SUBQH_R_PH_DESC;
-def ADDQH_W : DspMMRel, ADDQH_W_ENC, ADDQH_W_DESC;
-def ADDQH_R_W : DspMMRel, ADDQH_R_W_ENC, ADDQH_R_W_DESC;
-def SUBQH_W : DspMMRel, SUBQH_W_ENC, SUBQH_W_DESC;
-def SUBQH_R_W : DspMMRel, SUBQH_R_W_ENC, SUBQH_R_W_DESC;
-def MUL_PH : DspMMRel, MUL_PH_ENC, MUL_PH_DESC;
-def MUL_S_PH : DspMMRel, MUL_S_PH_ENC, MUL_S_PH_DESC;
-def MULQ_S_W : DspMMRel, MULQ_S_W_ENC, MULQ_S_W_DESC;
-def MULQ_RS_W : DspMMRel, MULQ_RS_W_ENC, MULQ_RS_W_DESC;
-def MULQ_S_PH : DspMMRel, MULQ_S_PH_ENC, MULQ_S_PH_DESC;
-def DPA_W_PH : DspMMRel, DPA_W_PH_ENC, DPA_W_PH_DESC;
-def DPS_W_PH : DspMMRel, DPS_W_PH_ENC, DPS_W_PH_DESC;
-def DPAQX_S_W_PH : DspMMRel, DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC;
-def DPAQX_SA_W_PH : DspMMRel, DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC;
-def DPAX_W_PH : DspMMRel, DPAX_W_PH_ENC, DPAX_W_PH_DESC;
-def DPSX_W_PH : DspMMRel, DPSX_W_PH_ENC, DPSX_W_PH_DESC;
-def DPSQX_S_W_PH : DspMMRel, DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC;
-def DPSQX_SA_W_PH : DspMMRel, DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC;
-def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC;
-def PRECR_QB_PH : DspMMRel, PRECR_QB_PH_ENC, PRECR_QB_PH_DESC;
-def PRECR_SRA_PH_W : DspMMRel, PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC;
-def PRECR_SRA_R_PH_W : DspMMRel, PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC;
-def SHRA_QB : DspMMRel, SHRA_QB_ENC, SHRA_QB_DESC;
-def SHRAV_QB : DspMMRel, SHRAV_QB_ENC, SHRAV_QB_DESC;
-def SHRA_R_QB : DspMMRel, SHRA_R_QB_ENC, SHRA_R_QB_DESC;
-def SHRAV_R_QB : DspMMRel, SHRAV_R_QB_ENC, SHRAV_R_QB_DESC;
-def SHRL_PH : DspMMRel, SHRL_PH_ENC, SHRL_PH_DESC;
-def SHRLV_PH : DspMMRel, SHRLV_PH_ENC, SHRLV_PH_DESC;
-def APPEND : APPEND_ENC, APPEND_DESC;
-def BALIGN : BALIGN_ENC, BALIGN_DESC;
-def PREPEND : DspMMRel, PREPEND_ENC, PREPEND_DESC;
-
-}
+def ADDU_PH : DspMMRel, ADDU_PH_ENC, ADDU_PH_DESC, ISA_DSPR2;
+def ADDU_S_PH : DspMMRel, ADDU_S_PH_ENC, ADDU_S_PH_DESC, ISA_DSPR2;
+def SUBU_PH : DspMMRel, SUBU_PH_ENC, SUBU_PH_DESC, ISA_DSPR2;
+def SUBU_S_PH : DspMMRel, SUBU_S_PH_ENC, SUBU_S_PH_DESC, ISA_DSPR2;
+def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC, ISA_DSPR2;
+def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC, ISA_DSPR2;
+def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC, ISA_DSPR2;
+def ABSQ_S_QB : DspMMRel, ABSQ_S_QB_ENC, ABSQ_S_QB_DESC, ISA_DSPR2;
+def ADDUH_QB : DspMMRel, ADDUH_QB_ENC, ADDUH_QB_DESC, ISA_DSPR2;
+def ADDUH_R_QB : DspMMRel, ADDUH_R_QB_ENC, ADDUH_R_QB_DESC, ISA_DSPR2;
+def SUBUH_QB : DspMMRel, SUBUH_QB_ENC, SUBUH_QB_DESC, ISA_DSPR2;
+def SUBUH_R_QB : DspMMRel, SUBUH_R_QB_ENC, SUBUH_R_QB_DESC, ISA_DSPR2;
+def ADDQH_PH : DspMMRel, ADDQH_PH_ENC, ADDQH_PH_DESC, ISA_DSPR2;
+def ADDQH_R_PH : DspMMRel, ADDQH_R_PH_ENC, ADDQH_R_PH_DESC, ISA_DSPR2;
+def SUBQH_PH : DspMMRel, SUBQH_PH_ENC, SUBQH_PH_DESC, ISA_DSPR2;
+def SUBQH_R_PH : DspMMRel, SUBQH_R_PH_ENC, SUBQH_R_PH_DESC, ISA_DSPR2;
+def ADDQH_W : DspMMRel, ADDQH_W_ENC, ADDQH_W_DESC, ISA_DSPR2;
+def ADDQH_R_W : DspMMRel, ADDQH_R_W_ENC, ADDQH_R_W_DESC, ISA_DSPR2;
+def SUBQH_W : DspMMRel, SUBQH_W_ENC, SUBQH_W_DESC, ISA_DSPR2;
+def SUBQH_R_W : DspMMRel, SUBQH_R_W_ENC, SUBQH_R_W_DESC, ISA_DSPR2;
+def MUL_PH : DspMMRel, MUL_PH_ENC, MUL_PH_DESC, ISA_DSPR2;
+def MUL_S_PH : DspMMRel, MUL_S_PH_ENC, MUL_S_PH_DESC, ISA_DSPR2;
+def MULQ_S_W : DspMMRel, MULQ_S_W_ENC, MULQ_S_W_DESC, ISA_DSPR2;
+def MULQ_RS_W : DspMMRel, MULQ_RS_W_ENC, MULQ_RS_W_DESC, ISA_DSPR2;
+def MULQ_S_PH : DspMMRel, MULQ_S_PH_ENC, MULQ_S_PH_DESC, ISA_DSPR2;
+def DPA_W_PH : DspMMRel, DPA_W_PH_ENC, DPA_W_PH_DESC, ISA_DSPR2;
+def DPS_W_PH : DspMMRel, DPS_W_PH_ENC, DPS_W_PH_DESC, ISA_DSPR2;
+def DPAQX_S_W_PH : DspMMRel, DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC, ISA_DSPR2;
+def DPAQX_SA_W_PH : DspMMRel, DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC, ISA_DSPR2;
+def DPAX_W_PH : DspMMRel, DPAX_W_PH_ENC, DPAX_W_PH_DESC, ISA_DSPR2;
+def DPSX_W_PH : DspMMRel, DPSX_W_PH_ENC, DPSX_W_PH_DESC, ISA_DSPR2;
+def DPSQX_S_W_PH : DspMMRel, DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC, ISA_DSPR2;
+def DPSQX_SA_W_PH : DspMMRel, DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC, ISA_DSPR2;
+def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC, ISA_DSPR2;
+def PRECR_QB_PH : DspMMRel, PRECR_QB_PH_ENC, PRECR_QB_PH_DESC, ISA_DSPR2;
+def PRECR_SRA_PH_W : DspMMRel, PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC, ISA_DSPR2;
+def PRECR_SRA_R_PH_W : DspMMRel, PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC, ISA_DSPR2;
+def SHRA_QB : DspMMRel, SHRA_QB_ENC, SHRA_QB_DESC, ISA_DSPR2;
+def SHRAV_QB : DspMMRel, SHRAV_QB_ENC, SHRAV_QB_DESC, ISA_DSPR2;
+def SHRA_R_QB : DspMMRel, SHRA_R_QB_ENC, SHRA_R_QB_DESC, ISA_DSPR2;
+def SHRAV_R_QB : DspMMRel, SHRAV_R_QB_ENC, SHRAV_R_QB_DESC, ISA_DSPR2;
+def SHRL_PH : DspMMRel, SHRL_PH_ENC, SHRL_PH_DESC, ISA_DSPR2;
+def SHRLV_PH : DspMMRel, SHRLV_PH_ENC, SHRLV_PH_DESC, ISA_DSPR2;
+def APPEND : APPEND_ENC, APPEND_DESC, ISA_DSPR2;
+def BALIGN : BALIGN_ENC, BALIGN_DESC, ISA_DSPR2;
+def PREPEND : DspMMRel, PREPEND_ENC, PREPEND_DESC, ISA_DSPR2;
 
 // Pseudos.
 let isPseudo = 1, isCodeGenOnly = 1 in {
@@ -1442,3 +1444,8 @@ let AddedComplexity = 20 in {
   def : IndexedLoadPat<sextloadi16, LHX>;
   def : IndexedLoadPat<load, LWX>;
 }
+
+// Instruction alias.
+let AdditionalPredicates = [NotInMicroMips] in {
+  def : DSPInstAlias<"wrdsp $rt", (WRDSP GPR32Opnd:$rt, 0x1F), 1>;
+}

diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td
index c07edef86731f5b5f38c68bc1f08f7557b87b860..6d83cceab4037562b263c58d401e68a033b98042 100644 (file)
--- a/lib/Target/Mips/MipsInstrInfo.td
+++ b/lib/Target/Mips/MipsInstrInfo.td
@@ -385,6 +385,15 @@ include "MipsInstrFormats.td"
 // Mips Operand, Complex Patterns and Transformations Definitions.
 //===----------------------------------------------------------------------===//
 
+class ConstantSImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = []>
+    : AsmOperandClass {
+  let Name = "ConstantSImm" # Bits;
+  let RenderMethod = "addImmOperands";
+  let PredicateMethod = "isConstantSImm<" # Bits # ">";
+  let SuperClasses = Supers;
+  let DiagnosticType = "SImm" # Bits;
+}
+
 class ConstantUImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = [],
                                   int Offset = 0> : AsmOperandClass {
   let Name = "ConstantUImm" # Bits # "_" # Offset;
@@ -398,8 +407,12 @@ def ConstantUImm10AsmOperandClass
     : ConstantUImmAsmOperandClass<10, []>;
 def ConstantUImm8AsmOperandClass
     : ConstantUImmAsmOperandClass<8, [ConstantUImm10AsmOperandClass]>;
+def ConstantUImm7AsmOperandClass
+    : ConstantUImmAsmOperandClass<7, [ConstantUImm8AsmOperandClass]>;
 def ConstantUImm6AsmOperandClass
-    : ConstantUImmAsmOperandClass<6, [ConstantUImm8AsmOperandClass]>;
+    : ConstantUImmAsmOperandClass<6, [ConstantUImm7AsmOperandClass]>;
+def ConstantSImm6AsmOperandClass
+    : ConstantSImmAsmOperandClass<6, [ConstantUImm7AsmOperandClass]>;
 def ConstantUImm5Plus32AsmOperandClass
     : ConstantUImmAsmOperandClass<5, [ConstantUImm6AsmOperandClass], 32>;
 def ConstantUImm5Plus32NormalizeAsmOperandClass
@@ -468,6 +481,10 @@ def calltarget  : Operand<iPTR> {
 
 def imm64: Operand<i64>;
 
+def simm6 : Operand<i32> {
+  let ParserMatchClass = ConstantSImm6AsmOperandClass;
+  let OperandType = "OPERAND_IMMEDIATE";
+}
 def simm9 : Operand<i32>;
 def simm10 : Operand<i32>;
 def simm11 : Operand<i32>;
@@ -505,7 +522,7 @@ def uimmz       : Operand<i32> {
 }
 
 // Unsigned Operands
-foreach I = {1, 2, 3, 4, 5, 6, 8, 10} in
+foreach I = {1, 2, 3, 4, 5, 6, 7, 8, 10} in
   def uimm # I : Operand<i32> {
     let PrintMethod = "printUnsignedImm";
     let ParserMatchClass =

diff --git a/test/MC/Disassembler/Mips/dsp/valid-el.txt b/test/MC/Disassembler/Mips/dsp/valid-el.txt
index f7efe34671b5913262ff1071633033f68b969c30..56f363b62a217d464997f27e7c0d1aba95075b6b 100644 (file)
--- a/test/MC/Disassembler/Mips/dsp/valid-el.txt
+++ b/test/MC/Disassembler/Mips/dsp/valid-el.txt
@@ -7,3 +7,6 @@
 0x8a 0x51 0x54 0x7f # CHECK: lbux $10, $20($26) 
 0x0a 0x59 0x75 0x7f # CHECK: lhx  $11, $21($27) 
 0x0a 0x60 0x96 0x7f # CHECK: lwx  $12, $22($gp)
+0xb8 0x0e 0x30 0x7c # CHECK: shilo $ac1, 3
+0xf8 0x14 0xa0 0x7c # CHECK: wrdsp $5, 2
+0xf8 0xfc 0xa0 0x7c # CHECK: wrdsp $5

diff --git a/test/MC/Disassembler/Mips/micromips-dsp/valid.txt b/test/MC/Disassembler/Mips/micromips-dsp/valid.txt
index 7fef4e2d08cd1736582f8499fd6f2e2a7cde2fb4..fdd404c43492f194a22d1ab3758301586ba2cb6e 100644 (file)
--- a/test/MC/Disassembler/Mips/micromips-dsp/valid.txt
+++ b/test/MC/Disassembler/Mips/micromips-dsp/valid.txt
@@ -32,6 +32,9 @@
 0x01 0xac 0xba 0xbc # CHECK: msubu $ac2, $12, $13
 0x00 0x62 0xcc 0xbc # CHECK: mult $ac3, $2, $3
 0x00 0xa4 0x9c 0xbc # CHECK: multu $ac2, $4, $5
+0x00 0xa4 0x19 0xad # CHECK: packrl.ph $3, $4, $5
+0x00 0xa4 0x1a 0x2d # CHECK: pick.ph $3, $4, $5
+0x00 0xa4 0x19 0xed # CHECK: pick.qb $3, $4, $5
 0x00 0x22 0x51 0x3c # CHECK: preceq.w.phl $1, $2
 0x00 0x64 0x61 0x3c # CHECK: preceq.w.phr $3, $4
 0x00 0xa6 0x71 0x3c # CHECK: precequ.ph.qbl $5, $6
@@ -46,6 +49,8 @@
 0x01 0xac 0x58 0xad # CHECK: precrq.qb.ph $11, $12, $13
 0x02 0x0f 0x71 0x6d # CHECK: precrqu_s.qb.ph $14, $15, $16
 0x02 0x72 0x89 0x2d # CHECK: precrq_rs.ph.w $17, $18, $19
+0x00 0x03 0x40 0x1d # CHECK: shilo $ac1, 3
+0x00 0x05 0x52 0x7c # CHECK: shilov $ac1, $5
 0x00 0x64 0x53 0xb5 # CHECK: shll.ph $3, $4, 5
 0x00 0x64 0x5b 0xb5 # CHECK: shll_s.ph $3, $4, 5
 0x00 0x64 0xa8 0x7c # CHECK: shll.qb $3, $4, 5
@@ -94,3 +99,5 @@
 0x00 0x22 0x03 0x3c # CHECK: replv.ph $1, $2
 0x00 0x22 0x13 0x3c # CHECK: replv.qb $1, $2
 0x00 0x01 0x82 0x7c # CHECK: mthlip $1, $ac2
+0x00 0xa7 0xd6 0x7c # CHECK: wrdsp $5
+0x00 0xa0 0x96 0x7c # CHECK: wrdsp $5, 2

diff --git a/test/MC/Disassembler/Mips/micromips-dspr2/valid.txt b/test/MC/Disassembler/Mips/micromips-dspr2/valid.txt
index 096b5bda4a34beab5f68256e9c7f9603112e2c83..1d9fc9e80d73891d22a5b140c93caf3c0b32eaaf 100644 (file)
--- a/test/MC/Disassembler/Mips/micromips-dspr2/valid.txt
+++ b/test/MC/Disassembler/Mips/micromips-dspr2/valid.txt
@@ -45,6 +45,9 @@
 0x01 0xac 0xba 0xbc # CHECK: msubu $ac2, $12, $13
 0x00 0x62 0xcc 0xbc # CHECK: mult $ac3, $2, $3
 0x00 0xa4 0x9c 0xbc # CHECK: multu $ac2, $4, $5
+0x00 0xa4 0x19 0xad # CHECK: packrl.ph $3, $4, $5
+0x00 0xa4 0x1a 0x2d # CHECK: pick.ph $3, $4, $5
+0x00 0xa4 0x19 0xed # CHECK: pick.qb $3, $4, $5
 0x00 0x22 0x51 0x3c # CHECK: preceq.w.phl $1, $2
 0x00 0x64 0x61 0x3c # CHECK: preceq.w.phr $3, $4
 0x00 0xa6 0x71 0x3c # CHECK: precequ.ph.qbl $5, $6
@@ -62,6 +65,8 @@
 0x01 0xac 0x58 0xad # CHECK: precrq.qb.ph $11, $12, $13
 0x02 0x0f 0x71 0x6d # CHECK: precrqu_s.qb.ph $14, $15, $16
 0x02 0x72 0x89 0x2d # CHECK: precrq_rs.ph.w $17, $18, $19
+0x00 0x03 0x40 0x1d # CHECK: shilo $ac1, 3
+0x00 0x05 0x52 0x7c # CHECK: shilov $ac1, $5
 0x00 0x64 0x53 0xb5 # CHECK: shll.ph $3, $4, 5
 0x00 0x64 0x5b 0xb5 # CHECK: shll_s.ph $3, $4, 5
 0x00 0x64 0xa8 0x7c # CHECK: shll.qb $3, $4, 5
@@ -116,3 +121,5 @@
 0x00 0x62 0x08 0xd5 # CHECK: muleu_s.ph.qbr $1, $2, $3
 0x00,0x62,0x09,0x15 # CHECK: mulq_rs.ph $1, $2, $3
 0x00 0x22 0x1a 0x55 # CHECK: prepend $1, $2, 3
+0x00 0xa7 0xd6 0x7c # CHECK: wrdsp $5
+0x00 0xa0 0x96 0x7c # CHECK: wrdsp $5, 2

diff --git a/test/MC/Mips/dsp/invalid.s b/test/MC/Mips/dsp/invalid.s
index 9ab471e0100b7fff4bc245a24791c1c7f80007f1..8bd0906e67f872c72c0c35e57ca0d4dfab9fda0e 100644 (file)
--- a/test/MC/Mips/dsp/invalid.s
+++ b/test/MC/Mips/dsp/invalid.s
@@ -19,3 +19,7 @@
   shra_r.w $3, $4, -1      # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
   shrl.qb $3, $4, 8        # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
   shrl.qb $3, $4, -1       # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
+  shilo $ac1, 64           # CHECK: :[[@LINE]]:15: error: expected 6-bit signed immediate
+  shilo $ac1, -64          # CHECK: :[[@LINE]]:15: error: expected 6-bit signed immediate
+  wrdsp $5, 1024           # CHECK: :[[@LINE]]:13: error: expected 10-bit unsigned immediate
+  wrdsp $5, -1             # CHECK: :[[@LINE]]:13: error: expected 10-bit unsigned immediate

diff --git a/test/MC/Mips/dsp/valid.s b/test/MC/Mips/dsp/valid.s
index 804669c5e4646360b8fe3fd9e9ddeef97baee03f..f5926f3e25939f47add587a75cec13968e634981 100644 (file)
--- a/test/MC/Mips/dsp/valid.s
+++ b/test/MC/Mips/dsp/valid.s
@@ -101,6 +101,7 @@
   repl.qb           $1, 85          # CHECK: repl.qb            $1, 85          # encoding: [0x7c,0x55,0x08,0x92]
   replv.ph          $1, $2          # CHECK: replv.ph           $1, $2          # encoding: [0x7c,0x02,0x0a,0xd2]
   replv.qb          $1, $2          # CHECK: replv.qb           $1, $2          # encoding: [0x7c,0x02,0x08,0xd2]
+  shilo             $ac1, 3         # CHECK: shilo              $ac1, 3         # encoding: [0x7c,0x30,0x0e,0xb8]
   shilo             $ac1, 16        # CHECK: shilo              $ac1, 16        # encoding: [0x7d,0x00,0x0e,0xb8]
   shilov            $ac1, $2        # CHECK: shilov             $ac1, $2        # encoding: [0x7c,0x40,0x0e,0xf8]
   shll.ph           $1, $2, 3       # CHECK: shll.ph            $1, $2, 3       # encoding: [0x7c,0x62,0x0a,0x13]
@@ -125,3 +126,6 @@
   subu.qb           $1, $2, $3      # CHECK: subu.qb            $1, $2, $3      # encoding: [0x7c,0x43,0x08,0x50]
   subu_s.qb         $1, $2, $3      # CHECK: subu_s.qb          $1, $2, $3      # encoding: [0x7c,0x43,0x09,0x50]
   wrdsp             $1, 0           # CHECK: wrdsp              $1, 0           # encoding: [0x7c,0x20,0x04,0xf8]
+  wrdsp             $5              # CHECK: wrdsp              $5              # encoding: [0x7c,0xa0,0xfc,0xf8]
+  wrdsp             $5, 2           # CHECK: wrdsp              $5, 2           # encoding: [0x7c,0xa0,0x14,0xf8]
+  wrdsp             $5, 31          # CHECK: wrdsp              $5              # encoding: [0x7c,0xa0,0xfc,0xf8]

diff --git a/test/MC/Mips/dspr2/valid.s b/test/MC/Mips/dspr2/valid.s
index ce9bd7309d7f38627bae8f020946943b8084efed..c50e9d6e5ae1e8d4f7ed42357ec1bdffc6e250e8 100644 (file)
--- a/test/MC/Mips/dspr2/valid.s
+++ b/test/MC/Mips/dspr2/valid.s
@@ -135,6 +135,7 @@
   repl.qb         $1, 85          # CHECK: repl.qb          $1, 85          # encoding: [0x7c,0x55,0x08,0x92]
   replv.ph        $1, $2          # CHECK: replv.ph         $1, $2          # encoding: [0x7c,0x02,0x0a,0xd2]
   replv.qb        $1, $2          # CHECK: replv.qb         $1, $2          # encoding: [0x7c,0x02,0x08,0xd2]
+  shilo           $ac1, 3         # CHECK: shilo            $ac1, 3         # encoding: [0x7c,0x30,0x0e,0xb8]
   shilo           $ac1, 16        # CHECK: shilo            $ac1, 16        # encoding: [0x7d,0x00,0x0e,0xb8]
   shilov          $ac1, $2        # CHECK: shilov           $ac1, $2        # encoding: [0x7c,0x40,0x0e,0xf8]
   shll.ph         $1, $2, 3       # CHECK: shll.ph          $1, $2, 3       # encoding: [0x7c,0x62,0x0a,0x13]
@@ -173,3 +174,6 @@
   subuh.qb        $1, $2, $3      # CHECK: subuh.qb         $1, $2, $3      # encoding: [0x7c,0x43,0x08,0x58]
   subuh_r.qb      $1, $2, $3      # CHECK: subuh_r.qb       $1, $2, $3      # encoding: [0x7c,0x43,0x08,0xd8]
   wrdsp           $1, 0           # CHECK: wrdsp            $1, 0           # encoding: [0x7c,0x20,0x04,0xf8]
+  wrdsp           $5              # CHECK: wrdsp            $5              # encoding: [0x7c,0xa0,0xfc,0xf8]
+  wrdsp           $5, 2           # CHECK: wrdsp            $5, 2           # encoding: [0x7c,0xa0,0x14,0xf8]
+  wrdsp           $5, 31          # CHECK: wrdsp            $5              # encoding: [0x7c,0xa0,0xfc,0xf8]

diff --git a/test/MC/Mips/micromips-dsp/invalid-wrong-error.s b/test/MC/Mips/micromips-dsp/invalid-wrong-error.s
new file mode 100644 (file)
index 0000000..d1ba873
--- /dev/null
+++ b/test/MC/Mips/micromips-dsp/invalid-wrong-error.s
@@ -0,0 +1,7 @@
+# Instructions that are correctly rejected but emit a wrong or misleading error.
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dsp 2>%t1
+# RUN: FileCheck %s < %t1
+
+  .set noat
+  wrdsp $5, 128            # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+  wrdsp $5, -1             # CHECK: :[[@LINE]]:13: error: expected 10-bit unsigned immediate

diff --git a/test/MC/Mips/micromips-dsp/invalid.s b/test/MC/Mips/micromips-dsp/invalid.s
index 8c631e0447b37e47a2bb0302169e7e74dda57226..55a6f8e28737714bd94119b9b1fe6da56b2836c3 100644 (file)
--- a/test/MC/Mips/micromips-dsp/invalid.s
+++ b/test/MC/Mips/micromips-dsp/invalid.s
@@ -19,3 +19,5 @@
   shra_r.w $3, $4, -1      # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
   shrl.qb $3, $4, 8        # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
   shrl.qb $3, $4, -1       # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
+  shilo $ac1, 64           # CHECK: :[[@LINE]]:15: error: expected 6-bit signed immediate
+  shilo $ac1, -64          # CHECK: :[[@LINE]]:15: error: expected 6-bit signed immediate

diff --git a/test/MC/Mips/micromips-dsp/valid.s b/test/MC/Mips/micromips-dsp/valid.s
index 85e3cd6f4b9de8029651468148f6ee76284981ff..c147a6d850acd35842ec47dc790b46212c9f08fe 100644 (file)
--- a/test/MC/Mips/micromips-dsp/valid.s
+++ b/test/MC/Mips/micromips-dsp/valid.s
@@ -33,6 +33,9 @@
   msubu $ac2, $12, $13         # CHECK: msubu $ac2, $12, $13    # encoding: [0x01,0xac,0xba,0xbc]
   mult $ac3, $2, $3            # CHECK: mult $ac3, $2, $3       # encoding: [0x00,0x62,0xcc,0xbc]
   multu $ac2, $4, $5           # CHECK: multu $ac2, $4, $5      # encoding: [0x00,0xa4,0x9c,0xbc]
+  packrl.ph $3, $4, $5         # CHECK: packrl.ph $3, $4, $5    # encoding: [0x00,0xa4,0x19,0xad]
+  pick.ph $3, $4, $5           # CHECK: pick.ph $3, $4, $5      # encoding: [0x00,0xa4,0x1a,0x2d]
+  pick.qb $3, $4, $5           # CHECK: pick.qb $3, $4, $5      # encoding: [0x00,0xa4,0x19,0xed]
   preceq.w.phl $1, $2          # CHECK: preceq.w.phl $1, $2      # encoding: [0x00,0x22,0x51,0x3c]
   preceq.w.phr $3, $4          # CHECK: preceq.w.phr $3, $4      # encoding: [0x00,0x64,0x61,0x3c]
   precequ.ph.qbl $5, $6        # CHECK: precequ.ph.qbl $5, $6    # encoding: [0x00,0xa6,0x71,0x3c]
@@ -47,6 +50,8 @@
   precrq.qb.ph $11, $12, $13    # CHECK: precrq.qb.ph $11, $12, $13    # encoding: [0x01,0xac,0x58,0xad]
   precrqu_s.qb.ph $14, $15, $16 # CHECK: precrqu_s.qb.ph $14, $15, $16 # encoding: [0x02,0x0f,0x71,0x6d]
   precrq_rs.ph.w $17, $18, $19  # CHECK: precrq_rs.ph.w $17, $18, $19  # encoding: [0x02,0x72,0x89,0x2d]
+  shilo $ac1, 3                # CHECK: shilo $ac1, 3           # encoding: [0x00,0x03,0x40,0x1d]
+  shilov $ac1, $5              # CHECK: shilov $ac1, $5         # encoding: [0x00,0x05,0x52,0x7c]
   shll.ph $3, $4, 5            # CHECK: shll.ph $3, $4, 5       # encoding: [0x00,0x64,0x53,0xb5]
   shll_s.ph $3, $4, 5          # CHECK: shll_s.ph $3, $4, 5     # encoding: [0x00,0x64,0x5b,0xb5]
   shll.qb $3, $4, 5            # CHECK: shll.qb $3, $4, 5       # encoding: [0x00,0x64,0xa8,0x7c]
@@ -95,3 +100,6 @@
   replv.ph $1, $2              # CHECK: replv.ph $1, $2         # encoding: [0x00,0x22,0x03,0x3c]
   replv.qb $1, $2              # CHECK: replv.qb $1, $2         # encoding: [0x00,0x22,0x13,0x3c]
   mthlip $1, $ac2              # CHECK: mthlip $1, $ac2         # encoding: [0x00,0x01,0x82,0x7c]
+  wrdsp $5                     # CHECK: wrdsp $5                # encoding: [0x00,0xa7,0xd6,0x7c]
+  wrdsp $5, 2                  # CHECK: wrdsp $5, 2             # encoding: [0x00,0xa0,0x96,0x7c]
+  wrdsp $5, 31                 # CHECK: wrdsp $5                # encoding: [0x00,0xa7,0xd6,0x7c]

diff --git a/test/MC/Mips/micromips-dspr2/valid.s b/test/MC/Mips/micromips-dspr2/valid.s
index b236aea152a720f0b906440bbd5484243fb34ae9..b1d09cbc84c7577dc6d754b426169ec970c84218 100644 (file)
--- a/test/MC/Mips/micromips-dspr2/valid.s
+++ b/test/MC/Mips/micromips-dspr2/valid.s
@@ -46,6 +46,9 @@
   msubu $ac2, $12, $13         # CHECK: msubu $ac2, $12, $13    # encoding: [0x01,0xac,0xba,0xbc]
   mult $ac3, $2, $3            # CHECK: mult $ac3, $2, $3       # encoding: [0x00,0x62,0xcc,0xbc]
   multu $ac2, $4, $5           # CHECK: multu $ac2, $4, $5      # encoding: [0x00,0xa4,0x9c,0xbc]
+  packrl.ph $3, $4, $5         # CHECK: packrl.ph $3, $4, $5    # encoding: [0x00,0xa4,0x19,0xad]
+  pick.ph $3, $4, $5           # CHECK: pick.ph $3, $4, $5      # encoding: [0x00,0xa4,0x1a,0x2d]
+  pick.qb $3, $4, $5           # CHECK: pick.qb $3, $4, $5      # encoding: [0x00,0xa4,0x19,0xed]
   preceq.w.phl $1, $2          # CHECK: preceq.w.phl $1, $2      # encoding: [0x00,0x22,0x51,0x3c]
   preceq.w.phr $3, $4          # CHECK: preceq.w.phr $3, $4      # encoding: [0x00,0x64,0x61,0x3c]
   precequ.ph.qbl $5, $6        # CHECK: precequ.ph.qbl $5, $6    # encoding: [0x00,0xa6,0x71,0x3c]
@@ -63,6 +66,8 @@
   precrq.qb.ph $11, $12, $13    # CHECK: precrq.qb.ph $11, $12, $13    # encoding: [0x01,0xac,0x58,0xad]
   precrqu_s.qb.ph $14, $15, $16 # CHECK: precrqu_s.qb.ph $14, $15, $16 # encoding: [0x02,0x0f,0x71,0x6d]
   precrq_rs.ph.w $17, $18, $19  # CHECK: precrq_rs.ph.w $17, $18, $19  # encoding: [0x02,0x72,0x89,0x2d]
+  shilo $ac1, 3                # CHECK: shilo $ac1, 3           # encoding: [0x00,0x03,0x40,0x1d]
+  shilov $ac1, $5              # CHECK: shilov $ac1, $5         # encoding: [0x00,0x05,0x52,0x7c]
   shll.ph $3, $4, 5            # CHECK: shll.ph $3, $4, 5       # encoding: [0x00,0x64,0x53,0xb5]
   shll_s.ph $3, $4, 5          # CHECK: shll_s.ph $3, $4, 5     # encoding: [0x00,0x64,0x5b,0xb5]
   shll.qb $3, $4, 5            # CHECK: shll.qb $3, $4, 5       # encoding: [0x00,0x64,0xa8,0x7c]
@@ -117,3 +122,6 @@
   muleu_s.ph.qbr $1, $2, $3    # CHECK: muleu_s.ph.qbr $1, $2, $3  # encoding: [0x00,0x62,0x08,0xd5]
   mulq_rs.ph $1, $2, $3        # CHECK: mulq_rs.ph $1, $2, $3      # encoding: [0x00,0x62,0x09,0x15]
   prepend $1, $2, 3            # CHECK: prepend $1, $2, 3          # encoding: [0x00,0x22,0x1a,0x55]
+  wrdsp $5                     # CHECK: wrdsp $5                # encoding: [0x00,0xa7,0xd6,0x7c]
+  wrdsp $5, 2                  # CHECK: wrdsp $5, 2             # encoding: [0x00,0xa0,0x96,0x7c]
+  wrdsp $5, 31                 # CHECK: wrdsp $5                # encoding: [0x00,0xa7,0xd6,0x7c]

diff --git a/test/MC/Mips/micromips-invalid.s b/test/MC/Mips/micromips-invalid.s
index 60c86987b093eef60e467b4acd610dc75f6338d2..7d34e79cf714b318b8ecf0ce962b71a3151844bc 100644 (file)
--- a/test/MC/Mips/micromips-invalid.s
+++ b/test/MC/Mips/micromips-invalid.s
@@ -75,6 +75,11 @@
   movep   $8, $6, $2, $3  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   movep   $5, $6, $5, $3  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   movep   $5, $6, $2, $9  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  break 1024        # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
+  break 1024, 5     # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
+  break 7, 1024     # CHECK: :[[@LINE]]:12: error: expected 10-bit unsigned immediate
+  break 1024, 1024  # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
+  wait 1024         # CHECK: :[[@LINE]]:8: error: expected 10-bit unsigned immediate
   prefx -1, $8($5)  # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
   prefx 32, $8($5)  # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
   jraddiusp 1       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4

diff --git a/test/MC/Mips/micromips32r6/invalid.s b/test/MC/Mips/micromips32r6/invalid.s
index 35f698397ba237c58f0ae362667cf6144824cb1d..92d3f70c65a047e97eddc65802127131c1ecefb0 100644 (file)
--- a/test/MC/Mips/micromips32r6/invalid.s
+++ b/test/MC/Mips/micromips32r6/invalid.s
@@ -22,6 +22,7 @@
   break 1024, 5            # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
   break 7, -1              # CHECK: :[[@LINE]]:12: error: expected 10-bit unsigned immediate
   break 7, 1024            # CHECK: :[[@LINE]]:12: error: expected 10-bit unsigned immediate
+  break 1023, 1024         # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
   cache -1, 255($7)        # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
   cache 32, 255($7)        # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
   ext $2, $3, -1, 31       # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate

diff --git a/test/MC/Mips/mips32r6/invalid.s b/test/MC/Mips/mips32r6/invalid.s
index ace04085cb7e5c65d30d1f7e4d9b8eaca4bc5c75..1656ac1da3507d464d076afd9b2e3b483e77a843 100644 (file)
--- a/test/MC/Mips/mips32r6/invalid.s
+++ b/test/MC/Mips/mips32r6/invalid.s
@@ -21,6 +21,7 @@ local_label:
         break 1024, 5     # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
         break 7, -1       # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate
         break 7, 1024     # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate
+        break 1024, 1024  # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
         // FIXME: Following tests are temporarely disabled, until "PredicateControl not in hierarchy" problem is resolved
         bltl  $7, $8, local_label  # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         bltul $7, $8, local_label  # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

diff --git a/test/MC/Mips/mips64r6/invalid.s b/test/MC/Mips/mips64r6/invalid.s
index 373ad94ad2a5e79f9c7aabdf2d56534953edbe5d..cba20b15eea40352257df62c67aed883a6497c59 100644 (file)
--- a/test/MC/Mips/mips64r6/invalid.s
+++ b/test/MC/Mips/mips64r6/invalid.s
@@ -19,6 +19,7 @@ local_label:
         break 1024, 5     # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
         break 7, -1       # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate
         break 7, 1024     # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate
+        break 1024, 1024  # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
         // FIXME: Following tests are temporarely disabled, until "PredicateControl not in hierarchy" problem is resolved
         bltl  $7, $8, local_label  # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         bltul $7, $8, local_label  # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled