Add tests for NEON encodings of vaddhn and vraddhn.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117064 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/MC/ARM/neon-fp-encoding.ll b/test/MC/ARM/neon-fp-encoding.ll
index d2a70ab04b002d1eaca7a74594c6b9872d509c94..1bffba0c4f2200fe9690c6b3af6c48fc8917dc3b 100644 (file)
--- a/test/MC/ARM/neon-fp-encoding.ll
+++ b/test/MC/ARM/neon-fp-encoding.ll
@@ -591,3 +591,65 @@ define <2 x i64> @vqaddu_2xi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
        %tmp3 = call <2 x i64> @llvm.arm.neon.vqaddu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
        ret <2 x i64> %tmp3
 }
+
+declare <8 x i8>  @llvm.arm.neon.vaddhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vaddhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vaddhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
+
+; CHECK: vaddhn_8xi16
+define <8 x i8> @vaddhn_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+       %tmp1 = load <8 x i16>* %A
+       %tmp2 = load <8 x i16>* %B
+; CHECK: vaddhn.i16    d16, q8, q9     @ encoding: [0xa2,0x04,0xc0,0xf2]
+       %tmp3 = call <8 x i8> @llvm.arm.neon.vaddhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
+       ret <8 x i8> %tmp3
+}
+
+; CHECK: vaddhn_4xi32
+define <4 x i16> @vaddhn_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+       %tmp1 = load <4 x i32>* %A
+       %tmp2 = load <4 x i32>* %B
+; CHECK: vaddhn.i32    d16, q8, q9     @ encoding: [0xa2,0x04,0xd0,0xf2]
+       %tmp3 = call <4 x i16> @llvm.arm.neon.vaddhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
+       ret <4 x i16> %tmp3
+}
+
+; CHECK: vaddhn_2xi64
+define <2 x i32> @vaddhn_2xi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+       %tmp1 = load <2 x i64>* %A
+       %tmp2 = load <2 x i64>* %B
+; CHECK: vaddhn.i64    d16, q8, q9     @ encoding: [0xa2,0x04,0xe0,0xf2]
+       %tmp3 = call <2 x i32> @llvm.arm.neon.vaddhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
+       ret <2 x i32> %tmp3
+}
+
+declare <8 x i8>  @llvm.arm.neon.vraddhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vraddhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vraddhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
+
+; CHECK: vraddhn_8xi16
+define <8 x i8> @vraddhn_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+       %tmp1 = load <8 x i16>* %A
+       %tmp2 = load <8 x i16>* %B
+; CHECK: vraddhn.i16   d16, q8, q9     @ encoding: [0xa2,0x04,0xc0,0xf3]
+       %tmp3 = call <8 x i8> @llvm.arm.neon.vraddhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
+       ret <8 x i8> %tmp3
+}
+
+; CHECK: vraddhn_4xi32
+define <4 x i16> @vraddhn_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+       %tmp1 = load <4 x i32>* %A
+       %tmp2 = load <4 x i32>* %B
+; CHECK: vraddhn.i32   d16, q8, q9     @ encoding: [0xa2,0x04,0xd0,0xf3]
+       %tmp3 = call <4 x i16> @llvm.arm.neon.vraddhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
+       ret <4 x i16> %tmp3
+}
+
+; CHECK: vraddhn_2xi64
+define <2 x i32> @vraddhn_2xi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+       %tmp1 = load <2 x i64>* %A
+       %tmp2 = load <2 x i64>* %B
+; CHECK: vraddhn.i64   d16, q8, q9     @ encoding: [0xa2,0x04,0xe0,0xf3]
+       %tmp3 = call <2 x i32> @llvm.arm.neon.vraddhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
+       ret <2 x i32> %tmp3
+}