class MachineInstr;
class MachineOperand;
class raw_ostream;
-}
struct BitTracker {
struct BitRef;
struct RegisterCell;
struct MachineEvaluator;
- typedef llvm::SetVector<const llvm::MachineBasicBlock*> BranchTargetList;
+ typedef SetVector<const MachineBasicBlock *> BranchTargetList;
struct CellMapType : public std::map<unsigned,RegisterCell> {
bool has(unsigned Reg) const;
};
- BitTracker(const MachineEvaluator &E, llvm::MachineFunction &F);
+ BitTracker(const MachineEvaluator &E, MachineFunction &F);
~BitTracker();
void run();
RegisterCell get(RegisterRef RR) const;
void put(RegisterRef RR, const RegisterCell &RC);
void subst(RegisterRef OldRR, RegisterRef NewRR);
- bool reached(const llvm::MachineBasicBlock *B) const;
+ bool reached(const MachineBasicBlock *B) const;
private:
- void visitPHI(const llvm::MachineInstr *PI);
- void visitNonBranch(const llvm::MachineInstr *MI);
- void visitBranchesFrom(const llvm::MachineInstr *BI);
+ void visitPHI(const MachineInstr *PI);
+ void visitNonBranch(const MachineInstr *MI);
+ void visitBranchesFrom(const MachineInstr *BI);
void visitUsesOf(unsigned Reg);
void reset();
typedef std::pair<int,int> CFGEdge;
typedef std::set<CFGEdge> EdgeSetType;
- typedef std::set<const llvm::MachineInstr*> InstrSetType;
+ typedef std::set<const MachineInstr *> InstrSetType;
typedef std::queue<CFGEdge> EdgeQueueType;
EdgeSetType EdgeExec; // Executable flow graph edges.
bool Trace; // Enable tracing for debugging.
const MachineEvaluator &ME;
- llvm::MachineFunction &MF;
- llvm::MachineRegisterInfo &MRI;
+ MachineFunction &MF;
+ MachineRegisterInfo &MRI;
CellMapType ⤅
};
struct BitTracker::RegisterRef {
RegisterRef(unsigned R = 0, unsigned S = 0)
: Reg(R), Sub(S) {}
- RegisterRef(const llvm::MachineOperand &MO)
- : Reg(MO.getReg()), Sub(MO.getSubReg()) {}
+ RegisterRef(const MachineOperand &MO)
+ : Reg(MO.getReg()), Sub(MO.getSubReg()) {}
unsigned Reg, Sub;
};
return Type == One;
}
- friend llvm::raw_ostream &operator<< (llvm::raw_ostream &OS,
- const BitValue &BV);
+ friend raw_ostream &operator<<(raw_ostream &OS, const BitValue &BV);
};
// The DefaultBitN is here only to avoid frequent reallocation of the
// memory in the vector.
static const unsigned DefaultBitN = 32;
- typedef llvm::SmallVector<BitValue,DefaultBitN> BitValueList;
+ typedef SmallVector<BitValue, DefaultBitN> BitValueList;
BitValueList Bits;
- friend llvm::raw_ostream &operator<< (llvm::raw_ostream &OS,
- const RegisterCell &RC);
+ friend raw_ostream &operator<<(raw_ostream &OS, const RegisterCell &RC);
};
return find(Reg) != end();
}
-
// A class to evaluate target's instructions and update the cell maps.
// This is used internally by the bit tracker. A target that wants to
// utilize this should implement the evaluation functions (noted below)
// in a subclass of this class.
struct BitTracker::MachineEvaluator {
- MachineEvaluator(const llvm::TargetRegisterInfo &T,
- llvm::MachineRegisterInfo &M) : TRI(T), MRI(M) {}
+ MachineEvaluator(const TargetRegisterInfo &T, MachineRegisterInfo &M)
+ : TRI(T), MRI(M) {}
virtual ~MachineEvaluator() {}
uint16_t getRegBitWidth(const RegisterRef &RR) const;
// Generate cell from an immediate value.
RegisterCell eIMM(int64_t V, uint16_t W) const;
- RegisterCell eIMM(const llvm::ConstantInt *CI) const;
+ RegisterCell eIMM(const ConstantInt *CI) const;
// Arithmetic.
RegisterCell eADD(const RegisterCell &A1, const RegisterCell &A2) const;
// does).
virtual BitMask mask(unsigned Reg, unsigned Sub) const;
// Indicate whether a given register class should be tracked.
- virtual bool track(const llvm::TargetRegisterClass *RC) const {
- return true;
- }
+ virtual bool track(const TargetRegisterClass *RC) const { return true; }
// Evaluate a non-branching machine instruction, given the cell map with
// the input values. Place the results in the Outputs map. Return "true"
// if evaluation succeeded, "false" otherwise.
- virtual bool evaluate(const llvm::MachineInstr *MI,
- const CellMapType &Inputs, CellMapType &Outputs) const;
+ virtual bool evaluate(const MachineInstr *MI, const CellMapType &Inputs,
+ CellMapType &Outputs) const;
// Evaluate a branch, given the cell map with the input values. Fill out
// a list of all possible branch targets and indicate (through a flag)
// whether the branch could fall-through. Return "true" if this information
// has been successfully computed, "false" otherwise.
- virtual bool evaluate(const llvm::MachineInstr *BI,
- const CellMapType &Inputs, BranchTargetList &Targets,
- bool &FallsThru) const = 0;
+ virtual bool evaluate(const MachineInstr *BI, const CellMapType &Inputs,
+ BranchTargetList &Targets, bool &FallsThru) const = 0;
- const llvm::TargetRegisterInfo &TRI;
- llvm::MachineRegisterInfo &MRI;
+ const TargetRegisterInfo &TRI;
+ MachineRegisterInfo &MRI;
};
-#endif
+} // end namespace llvm
+#endif
namespace llvm {
class HexagonInstrInfo;
class HexagonRegisterInfo;
-}
struct HexagonEvaluator : public BitTracker::MachineEvaluator {
typedef BitTracker::CellMapType CellMapType;
typedef BitTracker::RegisterCell RegisterCell;
typedef BitTracker::BranchTargetList BranchTargetList;
- HexagonEvaluator(const llvm::HexagonRegisterInfo &tri,
- llvm::MachineRegisterInfo &mri, const llvm::HexagonInstrInfo &tii,
- llvm::MachineFunction &mf);
+ HexagonEvaluator(const HexagonRegisterInfo &tri, MachineRegisterInfo &mri,
+ const HexagonInstrInfo &tii, MachineFunction &mf);
- virtual bool evaluate(const llvm::MachineInstr *MI,
- const CellMapType &Inputs, CellMapType &Outputs) const;
- virtual bool evaluate(const llvm::MachineInstr *BI,
- const CellMapType &Inputs, BranchTargetList &Targets,
- bool &FallsThru) const;
+ bool evaluate(const MachineInstr *MI, const CellMapType &Inputs,
+ CellMapType &Outputs) const override;
+ bool evaluate(const MachineInstr *BI, const CellMapType &Inputs,
+ BranchTargetList &Targets, bool &FallsThru) const override;
- virtual BitTracker::BitMask mask(unsigned Reg, unsigned Sub) const;
+ BitTracker::BitMask mask(unsigned Reg, unsigned Sub) const override;
- llvm::MachineFunction &MF;
- llvm::MachineFrameInfo &MFI;
- const llvm::HexagonInstrInfo &TII;
+ MachineFunction &MF;
+ MachineFrameInfo &MFI;
+ const HexagonInstrInfo &TII;
private:
- bool evaluateLoad(const llvm::MachineInstr *MI, const CellMapType &Inputs,
- CellMapType &Outputs) const;
- bool evaluateFormalCopy(const llvm::MachineInstr *MI,
- const CellMapType &Inputs, CellMapType &Outputs) const;
+ bool evaluateLoad(const MachineInstr *MI, const CellMapType &Inputs,
+ CellMapType &Outputs) const;
+ bool evaluateFormalCopy(const MachineInstr *MI, const CellMapType &Inputs,
+ CellMapType &Outputs) const;
unsigned getNextPhysReg(unsigned PReg, unsigned Width) const;
unsigned getVirtRegFor(unsigned PReg) const;
ExtType(char t, uint16_t w) : Type(t), Width(w) {}
};
// Map VR -> extension type.
- typedef llvm::DenseMap<unsigned,ExtType> RegExtMap;
+ typedef DenseMap<unsigned, ExtType> RegExtMap;
RegExtMap VRX;
};
-#endif
+} // end namespace llvm
+#endif