use proper (82-bit) spills/fills when spilling FP regs, so that

divides don't get broken. this fixes obsequi, smg2000, and probably
a bunch of other stuff (tm)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25385 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/IA64/IA64InstrInfo.td b/lib/Target/IA64/IA64InstrInfo.td
index fc72ad584b289b2551a9e062c3feec6d00958513..3d527206560ef64bfaa00263691cd5056e995107 100644 (file)
--- a/lib/Target/IA64/IA64InstrInfo.td
+++ b/lib/Target/IA64/IA64InstrInfo.td
@@ -537,6 +537,8 @@ let isStore = 1, noResults = 1 in {
     "stfs [$dstPtr] = $value;;">;
   def STF8 : AForm<0x03, 0x0b, (ops GR:$dstPtr, FP:$value),
     "stfd [$dstPtr] = $value;;">;
+  def STF_SPILL : AForm<0x03, 0x0b, (ops GR:$dstPtr, FP:$value),
+    "stf.spill [$dstPtr] = $value;;">;
 }
 
 let isLoad = 1 in {
@@ -552,6 +554,8 @@ let isLoad = 1 in {
     "ldfs $dst = [$srcPtr];;">;
   def LDF8 : AForm<0x03, 0x0b, (ops FP:$dst, GR:$srcPtr),
     "ldfd $dst = [$srcPtr];;">;
+  def LDF_FILL : AForm<0x03, 0x0b, (ops FP:$dst, GR:$srcPtr),
+    "ldf.fill $dst = [$srcPtr];;">;
 }
 
 def POPCNT : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src),

diff --git a/lib/Target/IA64/IA64RegisterInfo.cpp b/lib/Target/IA64/IA64RegisterInfo.cpp
index 14f4e8f3da079c61315dd9c89fd9222e04095921..e51cd8d680925c26077fb0a55f41dc449e27bdfb 100644 (file)
--- a/lib/Target/IA64/IA64RegisterInfo.cpp
+++ b/lib/Target/IA64/IA64RegisterInfo.cpp
@@ -40,7 +40,7 @@ void IA64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
                                            const TargetRegisterClass *RC) const{
 
   if (RC == IA64::FPRegisterClass) {
-    BuildMI(MBB, MI, IA64::STF8, 2).addFrameIndex(FrameIdx).addReg(SrcReg);
+    BuildMI(MBB, MI, IA64::STF_SPILL, 2).addFrameIndex(FrameIdx).addReg(SrcReg);
   } else if (RC == IA64::GRRegisterClass) {
     BuildMI(MBB, MI, IA64::ST8, 2).addFrameIndex(FrameIdx).addReg(SrcReg);
  }
@@ -63,7 +63,7 @@ void IA64RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
                                             const TargetRegisterClass *RC)const{
 
   if (RC == IA64::FPRegisterClass) {
-    BuildMI(MBB, MI, IA64::LDF8, 1, DestReg).addFrameIndex(FrameIdx);
+    BuildMI(MBB, MI, IA64::LDF_FILL, 1, DestReg).addFrameIndex(FrameIdx);
   } else if (RC == IA64::GRRegisterClass) {
     BuildMI(MBB, MI, IA64::LD8, 1, DestReg).addFrameIndex(FrameIdx);
  } else if (RC == IA64::PRRegisterClass) {

diff --git a/lib/Target/IA64/IA64RegisterInfo.td b/lib/Target/IA64/IA64RegisterInfo.td
index 936f123745c8189577aa6acf4e16ebbfac4b45fa..0e65544b51c7105531f9ab6c0ab1995b84990eb2 100644 (file)
--- a/lib/Target/IA64/IA64RegisterInfo.td
+++ b/lib/Target/IA64/IA64RegisterInfo.td
@@ -282,7 +282,11 @@ def GR : RegisterClass<"IA64", [i64], 64,
 
 
 // these are the scratch (+stacked) FP registers
-def FP : RegisterClass<"IA64", [f64], 64, 
+
+// the 128 here is to make stf.spill/ldf.fill happy,
+// when storing full (82-bit) FP regs to stack slots
+// we need to 16-byte align
+def FP : RegisterClass<"IA64", [f64], 128, 
        [F6, F7, 
        F8, F9, F10, F11, F12, F13, F14, F15, 
        F32, F33, F34, F35, F36, F37, F38, F39,