rk: add pll wait lock error dump infomations

diff --git a/arch/arm/mach-rk30/clock_data-rk3066b.c b/arch/arm/mach-rk30/clock_data-rk3066b.c
index 66a2006b695703cc7bedf091c142bfa5bb89d52e..fe79f20bb06911299e791c5b05f02b5497d361f2 100644 (file)
--- a/arch/arm/mach-rk30/clock_data-rk3066b.c
+++ b/arch/arm/mach-rk30/clock_data-rk3066b.c
@@ -615,6 +615,12 @@ static void pll_wait_lock(int pll_idx)
                delay--;
        }
        if (delay == 0) {
+               CLKDATA_ERR("PLL_ID=%d\npll_con0=%08x\npll_con1=%08x\npll_con2=%08x\npll_con3=%08x\n", pll_idx,
+                               cru_readl(PLL_CONS(pll_idx, 0)),
+                               cru_readl(PLL_CONS(pll_idx, 1)),
+                               cru_readl(PLL_CONS(pll_idx, 2)),
+                               cru_readl(PLL_CONS(pll_idx, 3)));
+
                CLKDATA_ERR("wait pll bit 0x%x time out!\n", bit);
                while(1);
        }

diff --git a/arch/arm/mach-rk30/clock_data.c b/arch/arm/mach-rk30/clock_data.c
index 5643b48e27ab643d3612665c17ee8ccefdb6c9c0..6e41a410804e6575df4cecbe5a35717297239c57 100644 (file)
--- a/arch/arm/mach-rk30/clock_data.c
+++ b/arch/arm/mach-rk30/clock_data.c
@@ -559,6 +559,12 @@ static void pll_wait_lock(int pll_idx)
                delay--;
        }
        if (delay == 0) {
+               CRU_PRINTK_ERR("PLL_ID=%d\npll_con0=%08x\npll_con1=%08x\npll_con2=%08x\npll_con3=%08x\n", pll_idx,
+                               cru_readl(PLL_CONS(pll_idx, 0)),
+                               cru_readl(PLL_CONS(pll_idx, 1)),
+                               cru_readl(PLL_CONS(pll_idx, 2)),
+                               cru_readl(PLL_CONS(pll_idx, 3)));
+
                CRU_PRINTK_ERR("wait pll bit 0x%x time out!\n", bit);
                while(1);
        }

diff --git a/arch/arm/mach-rk3188/clock_data.c b/arch/arm/mach-rk3188/clock_data.c
index 5159dd55b1b356a231060222c18c9dca8cf5bc46..cbfbd433bd9b852faa059f2ef54ab25be3119d72 100755 (executable)
--- a/arch/arm/mach-rk3188/clock_data.c
+++ b/arch/arm/mach-rk3188/clock_data.c
@@ -614,6 +614,12 @@ static void pll_wait_lock(int pll_idx)
                delay--;
        }
        if (delay == 0) {
+               CLKDATA_ERR("PLL_ID=%d\npll_con0=%08x\npll_con1=%08x\npll_con2=%08x\npll_con3=%08x\n", pll_idx,
+                               cru_readl(PLL_CONS(pll_idx, 0)),
+                               cru_readl(PLL_CONS(pll_idx, 1)),
+                               cru_readl(PLL_CONS(pll_idx, 2)),
+                               cru_readl(PLL_CONS(pll_idx, 3)));
+
                CLKDATA_ERR("wait pll bit 0x%x time out!\n", bit);
                while(1);
        }