When build with CONFIG_ARCH_DMA_ADDR_T_64BIT enabled:
drivers/usb/dwc_otg_310/dwc_otg_hcd.c: In function 'assign_and_init_hc':
drivers/usb/dwc_otg_310/dwc_otg_hcd.c:1093:19: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
drivers/usb/dwc_otg_310/dwc_otg_hcd.c:1131:21: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
drivers/usb/dwc_otg_310/dwc_otg_hcd.c:1161:21: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
drivers/usb/dwc_otg_310/dwc_otg_hcd.c:1189:21: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
drivers/usb/dwc_otg_310/dwc_otg_hcd_ddma.c: In function 'init_non_isoc_dma_desc':
drivers/usb/dwc_otg_310/dwc_otg_hcd_ddma.c:632:8: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
drivers/usb/dwc_otg_310/dwc_otg_hcd_intr.c: In function 'handle_hc_ahberr_intr':
drivers/usb/dwc_otg_310/dwc_otg_hcd_intr.c:1699:14: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
Change-Id: I4159d1d66ce24c97cc8085ee6e0fc4abde8c7423
Signed-off-by: William Wu <wulf@rock-chips.com>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from commit
b001ce5aa46de28c1f52c82d1e3c111e172bd5e4)
(cherry picked from commit
4952c8819aa0f0902ae620bf5de18f7a19f85e17)
hc->multi_count = 1;
if (hcd->core_if->dma_enable) {
- hc->xfer_buff = (uint8_t *) urb->dma + urb->actual_length;
+ hc->xfer_buff = (uint8_t *)(uintptr_t)urb->dma +
+ urb->actual_length;
/* For non-dword aligned case */
if (((unsigned long)hc->xfer_buff & 0x3)
hc->ep_is_in = 0;
hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
if (hcd->core_if->dma_enable)
- hc->xfer_buff = (uint8_t *) urb->setup_dma;
+ hc->xfer_buff = (uint8_t *)(uintptr_t)urb->setup_dma;
else
hc->xfer_buff = (uint8_t *) urb->setup_packet;
hc->xfer_len = 0;
if (hcd->core_if->dma_enable)
- hc->xfer_buff = (uint8_t *) hcd->status_buf_dma;
+ hc->xfer_buff = (uint8_t *)(uintptr_t)hcd->status_buf_dma;
else
hc->xfer_buff = (uint8_t *) hcd->status_buf;
frame_desc->status = 0;
if (hcd->core_if->dma_enable) {
- hc->xfer_buff = (uint8_t *) urb->dma;
+ hc->xfer_buff = (uint8_t *)(uintptr_t)urb->dma;
} else {
hc->xfer_buff = (uint8_t *) urb->buf;
}
if (n_desc) {
/* SG request - more than 1 QTDs */
hc->xfer_buff =
- (uint8_t *) qtd->urb->dma + qtd->urb->actual_length;
+ (uint8_t *)(uintptr_t)qtd->urb->dma +
+ qtd->urb->actual_length;
hc->xfer_len =
qtd->urb->length - qtd->urb->actual_length;
}
DWC_ERROR(" Max packet size: %d\n",
dwc_otg_hcd_get_mps(&urb->pipe_info));
DWC_ERROR(" Data buffer length: %d\n", urb->length);
- DWC_ERROR(" Transfer buffer: %p, Transfer DMA: %p\n",
- urb->buf, (void *)urb->dma);
- DWC_ERROR(" Setup buffer: %p, Setup DMA: %p\n",
- urb->setup_packet, (void *)urb->setup_dma);
+ DWC_ERROR(" Transfer buffer: %p, Transfer DMA: %pad\n",
+ urb->buf, &urb->dma);
+ DWC_ERROR(" Setup buffer: %p, Setup DMA: %pad\n",
+ urb->setup_packet, &urb->setup_dma);
DWC_ERROR(" Interval: %d\n", urb->interval);
/* Core haltes the channel for Descriptor DMA mode */