add a minor dag combine noticed when looking at PR945

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30915 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 2c15f39db4a6f4b8c1d48cd241c1b6b73b8442ae..70ff8371f7945fa9e629eaf8bb3cc5479dcaf43a 100644 (file)
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -1664,6 +1664,13 @@ SDOperand DAGCombiner::visitSRL(SDNode *N) {
     return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
   }
   
+  // fold (srl (sra X, Y), 31) -> (srl X, 31).  This srl only looks at the sign
+  // bit, which is unmodified by sra.
+  if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) {
+    if (N0.getOpcode() == ISD::SRA)
+      return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1);
+  }
+  
   // fold (srl (ctlz x), "5") -> x  iff x has one bit set (the low bit).
   if (N1C && N0.getOpcode() == ISD::CTLZ && 
       N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {