nand driver: add 2928 nand driver.

diff --git a/arch/arm/mach-rk2928/devices.c b/arch/arm/mach-rk2928/devices.c
index 2fba48058870d7cf03d5e0e24c44a5246660f428..1dc4df27e90bcf1cee92ac830c39c518834b6f3b 100755 (executable)
--- a/arch/arm/mach-rk2928/devices.c
+++ b/arch/arm/mach-rk2928/devices.c
@@ -544,6 +544,22 @@ static void __init rk2928_init_spim(void)
 #endif
 }
 
+#ifdef CONFIG_MTD_NAND_RK29XX
+static struct resource resources_nand[] = {
+       {
+               .start  = RK2928_NANDC_PHYS,
+               .end    = RK2928_NANDC_PHYS + RK2928_NANDC_SIZE - 1,
+               .flags  = IORESOURCE_MEM,
+       }
+};
+
+static struct platform_device device_nand = {
+       .name           = "rk29xxnand",
+       .id             = -1,
+       .resource       = resources_nand,
+       .num_resources  = ARRAY_SIZE(resources_nand),
+};
+#endif
 #ifdef CONFIG_HDMI_RK2928
 static struct resource resource_hdmi[] = {
        [0] = {
@@ -769,6 +785,9 @@ static int __init rk2928_init_devices(void)
        rk2928_init_uart();
        rk2928_init_i2c();
        rk2928_init_spim();
+#ifdef CONFIG_MTD_NAND_RK29XX
+       platform_device_register(&device_nand);
+#endif
 #ifdef CONFIG_ADC_RK30
        platform_device_register(&device_adc);
 #endif

diff --git a/drivers/mtd/rknand/Makefile b/drivers/mtd/rknand/Makefile
index bdda17ab8b2677a5303eef6ec0c01d33e54b883d..964ea55489f3abc660cf390a7d6e1f8b41fe7e38 100755 (executable)
--- a/drivers/mtd/rknand/Makefile
+++ b/drivers/mtd/rknand/Makefile
@@ -4,6 +4,5 @@
 # $Id: Makefile,v 1.3 2011/01/21 10:12:56 Administrator Exp $\r
 #\r
 obj-$(CONFIG_MTD_NAND_RK29XX)          += rknand_base_ko.o \r
-#obj-$(CONFIG_MTD_RKNAND_BUFFER)               += rk30xxnand_ko.o\r
 \r
 \r

diff --git a/drivers/mtd/rknand/api_flash.h b/drivers/mtd/rknand/api_flash.h
index fe004ded9be053772b616462e861f6e25378d453..2340d4bb9c0ddd81ca9afcb3d4a1f599172cef13 100755 (executable)
--- a/drivers/mtd/rknand/api_flash.h
+++ b/drivers/mtd/rknand/api_flash.h
@@ -184,7 +184,7 @@ int FtlPageRead(int Index, int nSec, void *buf);
 Èë¿Ú²ÎÊý:pbuf\r
 ³ö¿Ú²ÎÊý:\r
 µ÷Óú¯Êý:\r
-×¢ÒâÐÅÏ¢£ºÐèÒªÔÚFTLInitºó²ÅÄܵ÷Óã¬pbuf´óСÐèÒª´óÓÚµÈÓÚ512 bytes£¬·µ»ØÐÅϢΪ512\r
+×¢ÒâÐÅÏ¢£ºÐèÒªÔÚflash Çý¶¯¼ÓÔغó²ÅÄܵ÷Óã¬pbuf´óСÐèÒª´óÓÚµÈÓÚ512 bytes£¬·µ»ØÐÅϢΪ512\r
           bytes¡£\r
 ***************************************************************************/\r
 char GetSNSectorInfo(char * pbuf);\r

diff --git a/drivers/mtd/rknand/epphal.h b/drivers/mtd/rknand/epphal.h
deleted file mode 100755 (executable)
index b966cea..0000000
--- a/drivers/mtd/rknand/epphal.h
+++ /dev/null
@@ -1,500 +0,0 @@
-/********************************************************************************\r
-*********************************************************************************\r
-                       COPYRIGHT (c)   2004 BY ROCK-CHIP FUZHOU\r
-                               --  ALL RIGHTS RESERVED  --\r
-\r
-File Name:         epphal.h\r
-Author:                    XUESHAN LIN\r
-Created:        1st Dec 2008\r
-Modified:\r
-Revision:              1.00\r
-********************************************************************************\r
-********************************************************************************/\r
-#ifndef _EPPHAL_H\r
-#define _EPPHAL_H\r
-#define     read_XDATA32(address)           (*((uint32 volatile*)(address)))\r
-#define     write_XDATA32(address, value)   (*((uint32 volatile*)(address)) = value)\r
-\r
-typedef enum _CLK_GATE\r
-{   \r
-    /* SCU CLK GATE 0 CON */    \r
-    CLK_GATE_CORE = 0,  \r
-    CLK_GATE_CORE_APB,  \r
-    CLK_GATE_CORE_ATB,  \r
-    CLK_GATE_CPU_AXI,   \r
-    CLK_GATE_CPU_AXI2,  \r
-    CLK_GATE_CPU_AHB,   \r
-    CLK_GATE_CPU_MATRIX1_AHB,   \r
-    CLK_GATE_CPU_APB,   \r
-    CLK_GATE_CPU_ATB,   \r
-    CLK_GATE_DMA0,  \r
-    CLK_GATE_DMA1,  \r
-    CLK_GATE_GIC,   \r
-    CLK_GATE_IMEM,  \r
-    CLK_GATE_EBROM = 14,    \r
-    CLK_GATE_I2S0,  \r
-    CLK_GATE_I2S1,  \r
-    CLK_GATE_SPDIF, \r
-    CLK_GATE_DDR_PHY,   \r
-    CLK_GATE_DDR_REG,   \r
-    CLK_GATE_DDR_CPU,   \r
-    CLK_GATE_EFUSE, \r
-    CLK_GATE_TZPC,  \r
-    CLK_GATE_TIMER0,    \r
-    CLK_GATE_GPIO0, \r
-    CLK_GATE_UART0, \r
-    CLK_GATE_I2C0,  \r
-    CLK_GATE_DEBUG, \r
-    CLK_GATE_TPIU,  \r
-    CLK_GATE_RTC,   \r
-    CLK_GATE_PMU,   \r
-    CLK_GATE_GRF,   \r
-\r
-    /* SCU CLK GATE 1 CON */    \r
-    CLK_GATE_PEIRPH_AXI = 32,   \r
-    CLK_GATE_PEIRPH_AHB,    \r
-    CLK_GATE_PEIRPH_APB,    \r
-    CLK_GATE_EMEM,  \r
-    CLK_GATE_USB,   \r
-    CLK_GATE_DMA2,  \r
-    CLK_GATE_DDR_PERIPH,    \r
-    CLK_GATE_PERIPH,    \r
-\r
-    /* FIXME */ \r
-    CLK_GATE_SMC_AXI,   \r
-    CLK_GATE_SMC,   \r
-    CLK_GATE_MAC_AHB = 43,  \r
-    CLK_GATE_MAC_PHY,   \r
-    CLK_GATE_MAC_TX,    \r
-    CLK_GATE_MAC_RX,    \r
-    CLK_GATE_HIF,   \r
-    CLK_GATE_NANDC, \r
-    CLK_GATE_HSADC_AHB, \r
-    CLK_GATE_HSADC, \r
-    CLK_GATE_SDMMC0_AHB,    \r
-    CLK_GATE_SDMMC0,    \r
-    CLK_GATE_SDMMC1_AHB,    \r
-    CLK_GATE_SDMMC1,    \r
-    CLK_GATE_EMMC_AHB,  \r
-    CLK_GATE_EMMC,  \r
-    CLK_GATE_USBOTG0,   \r
-    CLK_GATE_USBPHY0,   \r
-    CLK_GATE_USBOTG1,   \r
-    CLK_GATE_USBPHY1,   \r
-    CLK_GATE_UHOST_AHB, \r
-    CLK_GATE_UHOST, \r
-    CLK_GATE_PID_FILTER,    \r
-\r
-    /* SCU CLK GATE 2 CON */    \r
-    CLK_GATE_UART1 = 64,    \r
-    CLK_GATE_UART2, \r
-    CLK_GATE_UART3,\r
-    CLK_GATE_TIMER1,    \r
-    CLK_GATE_TIMER2,    \r
-    CLK_GATE_TIMER3,    \r
-    CLK_GATE_GPIO1, \r
-    CLK_GATE_GPIO2, \r
-    CLK_GATE_GPIO3,\r
-    CLK_GATE_GPIO4, \r
-    CLK_GATE_GPIO5, \r
-    CLK_GATE_GPIO6, \r
-    CLK_GATE_I2C1,  \r
-    CLK_GATE_I2C2,  \r
-    CLK_GATE_I2C3,  \r
-    CLK_GATE_SPI0,  \r
-    CLK_GATE_SPI1,  \r
-    CLK_GATE_VIP_SLAVE = 82,    \r
-    CLK_GATE_WDT,   \r
-    CLK_GATE_SARADC,    \r
-    CLK_GATE_PWM,   \r
-    CLK_GATE_VIP_BUS,   \r
-    CLK_GATE_VIP_MATRIX,    \r
-    CLK_GATE_VIP,   \r
-    CLK_GATE_VIP_INPUT, \r
-    CLK_GATE_JTAG,  \r
-\r
-    /* CRU CLK GATE 3 CON */    \r
-    CLK_GATE_LCDC_AXI = 96, \r
-    CLK_GATE_DDR_LCDC_AXI,  \r
-    CLK_GATE_LCDC_AHB,  \r
-    CLK_GATE_LCDC,  \r
-    CLK_GATE_IPP_AXI,   \r
-    CLK_GATE_IPP_AHB,   \r
-    CLK_GATE_EBOOK_AHB, \r
-    CLK_GATE_EBOOK, \r
-    CLK_GATE_DISPLAY_MATRIX_AXI,    \r
-    CLK_GATE_DISPLAY_MATRIX_AHB,    \r
-    CLK_GAET_VEPU_AXI,  \r
-    CLK_GATE_DDR_VEDU_AXI,  \r
-    CLK_GATE_VDPU_AXI,  \r
-    CLK_GATE_DDR_VDPU_AXI,  \r
-    CLK_GATE_GPU,   \r
-    CLK_GATE_GPU_AXI,   \r
-    CLK_GATE_DDR_GPU_AXI,   \r
-    CLK_GATE_GPU_AHB,   \r
-    CLK_GATE_VEPU_AHB,  \r
-    CLK_GATE_VDPU_AHB,  \r
-    CLK_GATE_CPU_VCODEC_AHB,    \r
-    CLK_GATE_CPU_DISPLAY_AHB,   \r
-    CLK_GATE_MAX\r
-}eCLK_GATE;\r
-\r
-\r
-//1¼Ä´æÆ÷½á¹¹¶¨Òå\r
-//INTC Registers\r
-typedef volatile struct tagGICD_REG\r
-{\r
-    uint32 ICDDCR         ;      //0x000 \r
-    uint32 ICDICTR        ;    //0x004   \r
-    uint32 ICDIIDR        ;    //0x008\r
-    uint32 RESERVED0[29]  ; \r
-    uint32 ICDISR[4]        ;   //   0x080  \r
-    uint32 RESERVED1[28]  ;\r
-    uint32 ICDISER[4]       ;     // 0x100 \r
-    uint32 RESERVED2[28]  ;   \r
-    uint32 ICDICER[4]     ;        //0x180   \r
-    uint32 RESERVED3[28]  ;\r
-    uint32 ICDISPR[4]       ;      //0x200  \r
-    uint32 RESERVED4[28]  ;\r
-    uint32 ICDICPR[4]     ;      //0x280   \r
-    uint32 RESERVED5[28]  ;\r
-    uint32 ICDIABR[4]     ;        //0x300\r
-    uint32 RESERVED6[60]  ;\r
-    uint32 ICDIPR_SGI[4]    ;       // 0x400\r
-    uint32 ICDIPR_PPI[4]    ;         // 0x410 \r
-    uint32 ICDIPR_SPI[18] ;         //0x420\r
-    uint32 RESERVED57[486] ;\r
-    uint32 ICDICFR[7]     ;        //0xc00\r
-    uint32 RESERVED8[185] ;\r
-    uint32 ICDSGIR        ;        //0xf00 \r
-}GICD_REG, *pGICD_REG;  \r
-typedef volatile struct tagGICC_REG\r
-{\r
-    uint32 ICCICR        ;         //0x00 \r
-    uint32 ICCPMR        ;         //0x04 \r
-    uint32 ICCBPR        ;         //0x08 \r
-    uint32 ICCIAR        ;         //0x0c \r
-    uint32 ICCEOIR      ;         //0x10 \r
-    uint32 ICCRPR        ;         //0x14 \r
-    uint32 ICCHPIR      ;         //0x18 \r
-    uint32 ICCABPR      ;         //0x1c \r
-    uint32 RESERVED0[55];\r
-    uint32 ICCIIDR      ;         //0xfc  \r
-}GICC_REG, *pGICC_REG;\r
-\r
-\r
-//SCU Registers\r
-typedef volatile struct tagCRU_REG\r
-{\r
-    uint32 CRU_APLL_CON;//[3];//0:arm 1:ddr 2:codec\r
-    uint32 CRU_DPLL_CON;\r
-    uint32 CRU_CPLL_CON;\r
-    uint32 CRU_PPLL_CON;\r
-    uint32 CRU_MODE_CON;\r
-    uint32 CRU_CLKSEL0_CON;\r
-    uint32 CRU_CLKSEL1_CON;\r
-    uint32 CRU_CLKSEL2_CON;\r
-    uint32 CRU_CLKSEL3_CON;\r
-    uint32 CRU_CLKSEL4_CON;\r
-    uint32 CRU_CLKSEL5_CON;\r
-    uint32 CRU_CLKSEL6_CON;\r
-    uint32 CRU_CLKSEL7_CON;\r
-    uint32 CRU_CLKSEL8_CON;\r
-    uint32 CRU_CLKSEL9_CON;\r
-    uint32 CRU_CLKSEL10_CON;\r
-    uint32 CRU_CLKSEL11_CON;\r
-    uint32 CRU_CLKSEL12_CON;\r
-    uint32 CRU_CLKSEL13_CON;\r
-    uint32 CRU_CLKSEL14_CON;\r
-    uint32 CRU_CLKSEL15_CON;\r
-    uint32 CRU_CLKSEL16_CON;\r
-    uint32 CRU_CLKSEL17_CON;\r
-    uint32 CRU_CLKGATE0_CON;\r
-    uint32 CRU_CLKGATE1_CON;\r
-    uint32 CRU_CLKGATE2_CON;\r
-    uint32 CRU_CLKGATE3_CON;\r
-    uint32 CRU_SOFTRST0_CON;\r
-    uint32 CRU_SOFTRST1_CON;\r
-    uint32 CRU_SOFTRST2_CON;\r
-}CRU_REG,*pCRU_REG;\r
- \r
-//SDMMC0\r
-typedef enum\r
-{\r
-IOMUX_SDMMC_1BIT = 0,\r
-IOMUX_SDMMC_4BIT,  //default\r
-IOMUX_SDMMC_8BIT,\r
-IOMUX_SDMMC_OTHER\r
-}eIOMUX_SDMMC;\r
-typedef enum _IRQ_NUM\r
-{\r
-    INT_SGI0        ,\r
-    INT_SGI1        ,\r
-    INT_SGI2        ,\r
-    INT_SGI3        ,\r
-    INT_SGI4        ,\r
-    INT_SGI5        ,\r
-    INT_SGI6        ,\r
-    INT_SGI7        ,\r
-    INT_SGI8        ,\r
-    INT_SGI9        ,\r
-    INT_SGI10       ,\r
-    INT_SGI11       ,\r
-    INT_SGI12       ,\r
-    INT_SGI13       ,\r
-    INT_SGI14       ,\r
-    INT_SGI15       ,\r
-    INT_PPI0        ,\r
-    INT_PPI1        ,\r
-    INT_PPI2        ,\r
-    INT_PPI3        ,\r
-    INT_PPI4        ,\r
-    INT_PPI5        ,\r
-    INT_PPI6        ,\r
-    INT_PPI7        ,\r
-    INT_PPI8        ,\r
-    INT_PPI9        ,\r
-    INT_PPI10       ,\r
-    INT_PPI11       ,\r
-    INT_PPI12       ,\r
-    INT_PPI13       ,\r
-    INT_PPI14       ,\r
-    INT_PPI15       ,\r
-    \r
-    INT_DMAC0_0     ,\r
-    INT_DMAC0_1     ,\r
-    INT_DMAC0_2     ,\r
-    INT_DMAC0_3     ,\r
-    INT_DMAC2_0     ,\r
-    INT_DMAC2_1     ,\r
-    INT_DMAC2_2     ,\r
-    INT_DMAC2_3     ,\r
-    INT_DMAC2_4     ,\r
-    INT_GPU         ,\r
-    INT_VEPU        ,\r
-    INT_VDPU        ,\r
-    INT_VIP         ,\r
-    INT_LCDC        ,\r
-    INT_IPP         ,\r
-    INT_EBC         ,\r
-    INT_USB_OTG0    ,\r
-    INT_USB_OTG1    ,\r
-    INT_USB_Host    ,\r
-    INT_MAC         ,\r
-    INT_HIF0        ,\r
-    INT_HIF1        ,\r
-    INT_HSADC_TSI   ,\r
-    INT_SDMMC       ,\r
-    INT_SDIO        ,\r
-    INT_eMMC        ,\r
-    INT_SARADC      ,\r
-    INT_NandC       ,\r
-    INT_NandCRDY    ,\r
-    INT_SMC         ,\r
-    INT_PID_FILTER  ,\r
-    INT_I2S_PCM_8CH ,\r
-    INT_I2S_PCM_2CH ,\r
-    INT_SPDIF       ,\r
-    INT_UART0       ,\r
-    INT_UART1       ,\r
-    INT_UART2       ,\r
-    INT_UART3       ,\r
-    INT_SPI0        ,\r
-    INT_SPI1        ,\r
-    INT_I2C0        ,\r
-    INT_I2C1        ,\r
-    INT_I2C2        ,\r
-    INT_I2C3        ,\r
-    INT_TIMER0      ,\r
-    INT_TIMER1      ,\r
-    INT_TIMER2      ,\r
-    INT_TIMER3      ,\r
-    INT_PWM0        ,\r
-    INT_PWM1        ,\r
-    INT_PWM2        ,\r
-    INT_PWM3        ,\r
-    INT_WDT         ,\r
-    INT_RTC         ,\r
-    INT_PMU         ,\r
-    INT_GPIO0       ,\r
-    INT_GPIO1       ,\r
-    INT_GPIO2       ,\r
-    INT_GPIO3       ,\r
-    INT_GPIO4       ,\r
-    INT_GPIO5       ,\r
-    INT_GPIO6       ,\r
-    INT_USB_AHB_ARB ,\r
-    INT_PERI_AHB_ARB,\r
-    INT_A8IRQ0      ,\r
-    INT_A8IRQ1      ,\r
-    INT_A8IRQ2      ,\r
-    INT_A8IRQ3      ,\r
-    INT_MAXNUM      \r
-}eINT_NUM;\r
-\r
-typedef enum _CRU_RST\r
-{\r
-//cru_rst_con0\r
-    CRU_RST_ARMCORE = 0,\r
-    CRU_RST_CPUSUBSYS_INT1AXI,\r
-    CRU_RST_CPUSUBSYS_INT1AHB,\r
-    CRU_RST_CPUSUBSYS_INT1APB,\r
-    CRU_RST_CPUSUBSYS_INT1ATB,\r
-    CRU_RST_CPUSUBSYS_INT2,\r
-    CRU_RST_DMA0,\r
-    CRU_RST_DMA1,\r
-    CRU_RST_GIC,\r
-    CRU_RST_INMEM,\r
-    CRU_RST_TZPC=11,\r
-    CRU_RST_ROM,\r
-    CRU_RST_I2S0,\r
-    CRU_RST_I2S1,\r
-    CRU_RST_SPDIF,\r
-    CRU_RST_UART0,\r
-    CRU_RST_RTC,\r
-    CRU_RST_DDRPHY,\r
-    CRU_RST_DDRDLL_B0,\r
-    CRU_RST_DDRDLL_B1,\r
-    CRU_RST_DDRDLL_B2,\r
-    CRU_RST_DDRDLL_B3,\r
-    CRU_RST_DDRDLL_CMD,\r
-    CRU_RST_DDR_CON,\r
-    CRU_RST_ARMCORE_DEBUG,\r
-    CRU_RST_DAP_DBG,\r
-    CRU_RST_CPU_VODEC_A2A,\r
-    CRU_RST_CPU_DISPLAY_A2A,\r
-    CRU_RST_DAP_SYS,\r
-\r
-// cru_softrst1_con\r
-    CRU_RST_PERIPH_INT1_AXI=32,\r
-    CRU_RST_PERIPH_INT1_AHB,\r
-    CRU_RST_PERIPH_INT1_APB,\r
-    CRU_RST_PERIPH_EMEM=36,\r
-    CRU_RST_PERIPH_USB,\r
-    CRU_RST_DMA2,\r
-    CRU_RST_MAC,\r
-    CRU_RST_HIF,\r
-    CRU_RST_NANDC,\r
-    CRU_RST_SMC,\r
-    CRU_RST_RESERVED1,\r
-    CRU_RST_LSADC,\r
-    CRU_RST_SDMMC0,\r
-    CRU_RST_SDMMC1,\r
-    CRU_RST_EMMC,\r
-    CRU_RST_USBOTG0_AHB,\r
-    CRU_RST_USBPHY0,\r
-    CRU_RST_USBOTG0_CON,\r
-    CRU_RST_USBOTG1_AHB,\r
-    CRU_RST_USBPHY1,\r
-    CRU_RST_USBOTG1_CON,\r
-    CRU_RST_UHOST,\r
-    CRU_RST_VIP,\r
-    CRU_RST_VIP_AHB,\r
-    CRU_RST_SPI0,\r
-    CRU_RST_SPI1,\r
-    CRU_RST_SARADC,\r
-    CRU_RST_UART1,\r
-    CRU_RST_UART2,\r
-    CRU_RST_UART3,\r
-    CRU_RST_PWM,\r
-\r
-//CRU_SOFTRST2_CON\r
-    CRU_RST_DISPLAY_AXI=64,\r
-    CRU_RST_DISPLAY_AHB,\r
-    CRU_RST_LCDC,\r
-    CRU_RST_IPP,\r
-    CRU_RST_EBOOK,\r
-    CRU_RST_RESERVED2,\r
-    CRU_RST_RESERVED3,\r
-    CRU_RST_GPU,\r
-    CRU_RST_DDR_REG,\r
-    CRU_RST_DDR_CPU,\r
-    CRU_RST_PERIPH_CPU_AXI,\r
-    CRU_RST_DDR_PERIPH,\r
-    CRU_RST_DDR_LCDC,\r
-    CRU_RST_RESERVED4,\r
-    CRU_RST_RESERVED5,\r
-    CRU_RST_DDR_VCODEC,\r
-    CRU_RST_DDR_GPU,\r
-    CRU_RST_PID_FILTER,\r
-    CRU_RST_VCODEC_AXI,\r
-    CRU_RST_VCODEC_AHB,\r
-    CRU_RST_TIMER0,\r
-    CRU_RST_TIMER1,\r
-    CRU_RST_TIMER2,\r
-    CRU_RST_TIMER3,\r
-    \r
-    CRU_RST_MAX\r
-}eCRU_RST;\r
-\r
-//GRF Registers\r
-    typedef struct tagGPIO_LH\r
-    {\r
-        uint32 GPIOL;\r
-        uint32 GPIOH;\r
-    }GPIO_LH_T;\r
-    \r
-    typedef struct tagGPIO_IOMUX\r
-    {\r
-        uint32 GPIOA_IOMUX;\r
-        uint32 GPIOB_IOMUX;\r
-        uint32 GPIOC_IOMUX;\r
-        uint32 GPIOD_IOMUX;\r
-    }GPIO_IOMUX_T;\r
-    //REG FILE registers\r
-    typedef volatile struct tagGRF_REG\r
-    {\r
-        GPIO_LH_T GRF_GPIO_DIR[7];\r
-        GPIO_LH_T GRF_GPIO_DO[7];\r
-        GPIO_LH_T GRF_GPIO_EN[7];\r
-        GPIO_IOMUX_T GRF_GPIO_IOMUX[7];\r
-        GPIO_LH_T GRF_GPIO_PULL[7];\r
-        uint32 GRF_SOC_CON[3];\r
-        uint32 GRF_SOC_STATUS0;\r
-        uint32 GRF_DMAC1_CON[3];\r
-        uint32 GRF_DMAC2_CON[4];\r
-        uint32 GRF_UOC0_CON[3];\r
-        uint32 GRF_UOC1_CON[4];\r
-        uint32 GRF_DDRC_CON0;\r
-        uint32 GRF_DDRC_STAT;\r
-        uint32 reserved[(0x1c8-0x1a0)/4];\r
-        uint32 GRF_OS_REG[4];\r
-    } GRF_REG, *pGRF_REG;\r
-    \r
-//TIMER Registers\r
-typedef volatile struct tagTIMER_STRUCT\r
-{\r
-    uint32 TIMER_LOAD_COUNT;\r
-    uint32 TIMER_CURR_VALUE;\r
-    uint32 TIMER_CTRL_REG;\r
-    uint32 TIMER_EOI;\r
-    uint32 TIMER_INT_STATUS;\r
-}TIMER_REG,*pTIMER_REG;\r
-\r
-typedef volatile struct tagPMU_REG\r
-{\r
-    uint32 PMU_WAKEUP_EN0;\r
-    uint32 PMU_WAKEUP_EN1;\r
-    uint32 PMU_WAKEUP_EN2;\r
-    uint32 reserved1;\r
-    uint32 PMU_PG_CON;\r
-    uint32 PMU_MISC_CON;\r
-    uint32 PMU_PLL_CNT;\r
-    uint32 PMU_PD_ST;\r
-    uint32 PMU_INT_ST;\r
-}PMU_REG,*pPMU_REG;\r
-\r
-typedef struct tagSCU_CLK_INFO\r
-{\r
-    uint32 armFreq;     //ARM PLL FREQ\r
-    uint32 dspFreq;     //DSP PLL FREQ\r
-    uint32 AuxFreq;   //AUX PLL FREQ\r
-    uint32 ahbDiv;\r
-    uint32 apbDiv;\r
-    uint32 armFreqLast;\r
-}SCU_CLK_INFO,*pSCU_CLK_INFO;\r
- \r
-#define g_cruReg ((pCRU_REG)RK29_CRU_REG_BASE)\r
-\r
-#endif\r
-       \r

diff --git a/drivers/mtd/rknand/nand_config.h b/drivers/mtd/rknand/nand_config.h
deleted file mode 100755 (executable)
index 1cb460e..0000000
--- a/drivers/mtd/rknand/nand_config.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/********************************************************************************\r
-*********************************************************************************\r
-                       COPYRIGHT (c)   2004 BY ROCK-CHIP FUZHOU\r
-                               --  ALL RIGHTS RESERVED  --\r
-\r
-File Name:  nand_config.h\r
-Author:     RK28XX Driver Develop Group\r
-Created:    25th OCT 2008\r
-Modified:\r
-Revision:   1.00\r
-********************************************************************************\r
-********************************************************************************/\r
-#ifndef     _NAND_CONFIG_H\r
-#define     _NAND_CONFIG_H\r
-#define     DRIVERS_NAND\r
-#define     LINUX\r
-\r
-#include    <linux/kernel.h>\r
-#include    <linux/string.h>\r
-#include    <linux/sched.h>\r
-#include    <linux/delay.h>\r
-#include    <linux/irq.h>\r
-#include    <mach/board.h>\r
-#include    <mach/gpio.h>\r
-#include    <asm/dma.h>\r
-#include    "typedef.h"\r
-\r
-#ifdef CONFIG_ARCH_RK30\r
-#include    <mach/io.h>\r
-#include    <mach/irqs.h>\r
-#endif\r
-#ifdef CONFIG_ARCH_RK29\r
-#include    <mach/rk29_iomap.h>\r
-#include    <mach/iomux.h>\r
-#endif\r
-\r
-#include    <linux/interrupt.h>\r
-#include    "epphal.h"\r
-\r
-//#include    "epphal.h"\r
-#ifndef        TRUE\r
-#define        TRUE    1\r
-#endif\r
-\r
-#ifndef                FALSE\r
-#define        FALSE   0\r
-#endif\r
-\r
-#ifndef                NULL\r
-#define        NULL   (void*)0\r
-#endif\r
-\r
-#include    "FTL_OSDepend.h"\r
-#include    "flash.h"\r
-#include    "ftl.h"\r
-\r
-#ifdef CONFIG_MTD_NAND_RK29XX_DEBUG\r
-#undef RKNAND_DEBUG\r
-#define DEBUG_MSG\r
-#define RKNAND_DEBUG(format, arg...) \\r
-               printk(KERN_NOTICE format, ## arg);\r
-#else\r
-#undef RKNAND_DEBUG\r
-#define RKNAND_DEBUG(n, arg...)\r
-#endif\r
-\r
-extern void rk29_power_reset(void);\r
-extern void rkNand_cond_resched(void);\r
-\r
-#define COND_RESCHED() rkNand_cond_resched()//cond_resched()\r
-\r
-extern unsigned long rk_dma_mem_alloc(int size);\r
-extern unsigned long rk_dma_mem_free(unsigned long buf);\r
-#undef PRINTF\r
-#define PRINTF RKNAND_DEBUG\r
-#endif\r
-\r

diff --git a/drivers/mtd/rknand/rknand_base.h b/drivers/mtd/rknand/rknand_base.h
index e74761a8a32326a7d642514db66e4683e53f258c..b7fa95ab0b844dedbb3d39a7194303bfd42067ae 100755 (executable)
--- a/drivers/mtd/rknand/rknand_base.h
+++ b/drivers/mtd/rknand/rknand_base.h
@@ -70,6 +70,8 @@ struct rknand_info {
     int emmc_clk_power_save_en;\r
     char *pdmaBuf;\r
     void (*nand_timing_config)(unsigned long AHBnKHz);\r
+    void (*rknand_suspend)(void);\r
+    void (*rknand_resume)(void);\r
     int reserved[20];\r
 };\r
 \r

diff --git a/drivers/mtd/rknand/rknand_base_ko.c b/drivers/mtd/rknand/rknand_base_ko.c
index 7043d2d68734badb5c5e3fec4c6b84b7623dc984..ea49e277ea8a58ed4993102d45c152fc9ff74516 100755 (executable)
--- a/drivers/mtd/rknand/rknand_base_ko.c
+++ b/drivers/mtd/rknand/rknand_base_ko.c
@@ -23,10 +23,11 @@
 //#include "api_flash.h"\r
 #include "rknand_base.h"\r
 #include <linux/clk.h>\r
+#include <linux/cpufreq.h>\r
 \r
 #define DRIVER_NAME    "rk29xxnand"\r
 \r
-const char rknand_base_version[] = "rknand_base.c version: 4.34 20120401";\r
+const char rknand_base_version[] = "rknand_base.c version: 4.38 20120717";\r
 #define NAND_DEBUG_LEVEL0 0\r
 #define NAND_DEBUG_LEVEL1 1\r
 #define NAND_DEBUG_LEVEL2 2\r
@@ -67,10 +68,23 @@ static char grknand_trac_buf[MAX_TRAC_BUFFER_SIZE];
 static char *ptrac_buf = grknand_trac_buf;\r
 void trac_log(long lba,int len, int mod)\r
 {\r
+       unsigned long long t;\r
+    unsigned long nanosec_rem;\r
+    t = cpu_clock(UINT_MAX);\r
+    nanosec_rem = do_div(t, 1000000000);\r
     if(mod)\r
-        ptrac_buf += sprintf(ptrac_buf,"W %d %d \n",lba,len);\r
+        ptrac_buf += sprintf(ptrac_buf,"[%5lu.%06lu] W %d %d \n",(unsigned long) t, nanosec_rem / 1000,lba,len);\r
     else\r
-        ptrac_buf += sprintf(ptrac_buf,"R %d %d \n",lba,len);\r
+        ptrac_buf += sprintf(ptrac_buf,"[%5lu.%06lu] R %d %d \n",(unsigned long) t, nanosec_rem / 1000,lba,len);\r
+}\r
+\r
+void trac_logs(char *s)\r
+{\r
+       unsigned long long t;\r
+    unsigned long nanosec_rem;\r
+    t = cpu_clock(UINT_MAX);\r
+    nanosec_rem = do_div(t, 1000000000);\r
+       ptrac_buf += sprintf(ptrac_buf,"[%5lu.%06lu] %s\n",(unsigned long) t, nanosec_rem / 1000,s);\r
 }\r
 \r
 static int rkNand_trac_read(char *page, char **start, off_t off, int count, int *eof,\r
@@ -80,7 +94,7 @@ static int rkNand_trac_read(char *page, char **start, off_t off, int count, int
        int len;\r
 \r
         len = ptrac_buf - grknand_trac_buf - off;\r
-     printk("rkNand_trac_read: page=%x,off=%x,count=%x ,len=%x \n",(int)page,(int)off,count,len);\r
+     //printk("rkNand_trac_read: page=%x,off=%x,count=%x ,len=%x \n",(int)page,(int)off,count,len);\r
 \r
        if (len < 0)\r
                len = 0;\r
@@ -321,7 +335,7 @@ static int rknand_nand_timing_cfg(void)
         if(gpNandInfo->nand_timing_config)\r
         {\r
             nandc_clk_rate = newclk;\r
-            gpNandInfo->nand_timing_config( nandc_clk_rate / 1000); // KHz\r
+            //gpNandInfo->nand_timing_config( nandc_clk_rate / 1000); // KHz\r
         }\r
        }\r
        return 0;\r
@@ -493,12 +507,16 @@ exit_free:
 static int rknand_suspend(struct platform_device *pdev, pm_message_t state)\r
 {\r
     gpNandInfo->rknand.rknand_schedule_enable = 0;\r
+    if(gpNandInfo->rknand_suspend)\r
+        gpNandInfo->rknand_suspend();  \r
        NAND_DEBUG(NAND_DEBUG_LEVEL0,"rknand_suspend: \n");\r
        return 0;\r
 }\r
 \r
 static int rknand_resume(struct platform_device *pdev)\r
 {\r
+    if(gpNandInfo->rknand_resume)\r
+       gpNandInfo->rknand_resume();  \r
     gpNandInfo->rknand.rknand_schedule_enable = 1;\r
        NAND_DEBUG(NAND_DEBUG_LEVEL0,"rknand_resume: \n");\r
        return 0;\r

diff --git a/drivers/mtd/rknand/typedef.h b/drivers/mtd/rknand/typedef.h
deleted file mode 100755 (executable)
index 6b7ad87..0000000
--- a/drivers/mtd/rknand/typedef.h
+++ /dev/null
@@ -1,62 +0,0 @@
-\r
-#ifndef        __TYPEDEF_H\r
-#define __TYPEDEF_H\r
-\r
-typedef volatile unsigned int       REG32;\r
-typedef volatile unsigned short        REG16;\r
-typedef volatile unsigned char         REG8;\r
-\r
-typedef int BOOLEAN;\r
-typedef BOOLEAN BOOL;\r
-typedef     void (*pFunc)(void);               //¶¨Ò庯ÊýÖ¸Õë, ÓÃÓÚµ÷Óþø¶ÔµØÖ·\r
-typedef     void (*pFunc1)(unsigned int);              //¶¨Ò庯ÊýÖ¸Õë, ÓÃÓÚµ÷Óþø¶ÔµØÖ·\r
-typedef     void (*pFunc2)(unsigned int,pFunc);                //¶¨Ò庯ÊýÖ¸Õë, ÓÃÓÚµ÷Óþø¶ÔµØÖ·\r
-\r
-\r
-#define        FALSE   0\r
-#define TRUE    (!FALSE)\r
-#ifndef NULL\r
-    #define    NULL    0\r
-#endif\r
-#define OK                  0\r
-#define ERROR               !0\r
-\r
-//typedef char * va_list; \r
-\r
-\r
-typedef unsigned long            uint32;\r
-typedef unsigned long                  UINT32;\r
-typedef unsigned short                 UINT16;\r
-typedef unsigned char                  UINT8;\r
-typedef int                                            INT32;\r
-typedef short                                  INT16;\r
-typedef char                                   INT8;\r
-\r
-typedef unsigned char                  INT8U;\r
-typedef signed char                    INT8S;\r
-typedef unsigned short                 INT16U;\r
-typedef signed short                   INT16S;\r
-typedef int                                    INT32S;\r
-typedef unsigned int                           INT32U;\r
-\r
-typedef unsigned long  L32U;\r
-typedef signed long  L32S;\r
-\r
-typedef unsigned char  BYTE;\r
-\r
-//typedef volatile unsigned int  data_t;\r
-//typedef volatile unsigned int* addr_t;\r
-\r
-//typedef      void (*pFunc)(void);    //¶¨Ò庯ÊýÖ¸Õë, ÓÃÓÚµ÷Óþø¶ÔµØÖ·\r
-\r
-typedef                unsigned char           uint8;\r
-typedef                signed char                 int8;\r
-typedef                unsigned short      uint16;\r
-typedef                signed short        int16;\r
-typedef                signed long                     int32;\r
-typedef                unsigned long long      uint64;\r
-typedef                signed long long        int64;\r
-//typedef              unsigned char           bool;\r
-typedef     unsigned short      WCHAR;\r
-\r
-#endif  /*__TYPEDEF_H */\r