+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK2928=y
-CONFIG_DDR_FREQ=y
-CONFIG_RK_USB_UART=y
-CONFIG_MACH_RK2926_SDK=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_CFG80211=y
-CONFIG_MAC80211=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RTL8188EU=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_SITRONIX_A720=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_GS_MMA7660=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_BATTERY_RK30_ADC_FAC=y
-CONFIG_BATTERY_RK30_AC_CHARGE=y
-CONFIG_BATTERY_RK30_VOL3V8=y
-CONFIG_POWER_ON_CHARGER_DISPLAY=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_TPS65090=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_ACT8931=y
-CONFIG_RK30_PWM_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_GC0308=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_RK2928_A720=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_LCDC_RK2928=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_RK2928=y
-CONFIG_RGA_RK30=y
-CONFIG_RK_LVDS=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_LOGO_LINUX_CLUT224 is not set
-CONFIG_LOGO_LINUX_800x480_CLUT224=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2SO_USE_DOUBLE_CHANNELS=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK_SOC_RK2928=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO=y
-# CONFIG_SDMMC1_RK29 is not set
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HYM8563=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK2928=y
-CONFIG_RK_CLOCK_PROC=y
-CONFIG_RK_USB_UART=y
-CONFIG_MACH_RK2926_TB=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_CFG80211=y
-CONFIG_MAC80211=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RTL8188EU=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_EETI_EGALAX=y
-CONFIG_EETI_EGALAX_MAX_X=1087
-CONFIG_EETI_EGALAX_MAX_Y=800
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_GS_MMA8452=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_TPS65090=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_RK30_PWM_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV2659=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_HSD100PXN=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_LCDC_RK2928=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_RK2928=y
-CONFIG_RGA_RK30=y
-CONFIG_RK_LVDS=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2SO_USE_DOUBLE_CHANNELS=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK_SOC_RK2928=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO=y
-# CONFIG_SDMMC1_RK29 is not set
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK2928=y
-CONFIG_DDR_FREQ=y
-CONFIG_RK_USB_UART=y
-CONFIG_MACH_RK2926_SDK=y
-CONFIG_MACH_RK2926_V86=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_CFG80211=y
-CONFIG_MAC80211=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RTL8188EU=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GT811_IIC=y
-CONFIG_TOUCHSCREEN_SITRONIX_A720=y
-CONFIG_TOUCHSCREEN_FT5X0X=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_GS_MMA7660=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_BATTERY_RK30_ADC_FAC=y
-CONFIG_BATTERY_RK30_AC_CHARGE=y
-CONFIG_BATTERY_RK30_VOL3V8=y
-CONFIG_POWER_ON_CHARGER_DISPLAY=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_TPS65090=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_ACT8931=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_GC0308=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_RK2926_V86=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_LCDC_RK2928=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_RK2928=y
-CONFIG_RGA_RK30=y
-CONFIG_RK_LVDS=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_LOGO_LINUX_CLUT224 is not set
-CONFIG_LOGO_LINUX_800x480_CLUT224=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2SO_USE_DOUBLE_CHANNELS=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK_SOC_RK2928=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO=y
-# CONFIG_SDMMC1_RK29 is not set
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK2928=y
-CONFIG_RK_CLOCK_PROC=y
-CONFIG_RK_USB_UART=y
-CONFIG_MACH_RK2928_A720=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_CFG80211=y
-CONFIG_MAC80211=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RTL8188EU=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_SITRONIX_A720=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_GS_MMA7660=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_TEST_POWER=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_TPS65090=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_ACT8931=y
-CONFIG_RK30_PWM_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_GC0308=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_RK2928_A720=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_LCDC_RK2928=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_RK2928=y
-CONFIG_RGA_RK30=y
-CONFIG_RK_LVDS=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_LOGO_LINUX_CLUT224 is not set
-CONFIG_LOGO_LINUX_800x480_CLUT224=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2SO_USE_DOUBLE_CHANNELS=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK_SOC_RK2928=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-# CONFIG_SDMMC1_RK29 is not set
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK2928=y
-CONFIG_DDR_FREQ=y
-CONFIG_RK_CLOCK_PROC=y
-CONFIG_RK_USB_UART=y
-CONFIG_MACH_RK2928=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_CFG80211=y
-CONFIG_MAC80211=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_MODEM_SOUND=y
-CONFIG_3G_MODULE=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RTL8188EU=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_EETI_EGALAX=y
-CONFIG_EETI_EGALAX_MAX_X=1087
-CONFIG_EETI_EGALAX_MAX_Y=800
-CONFIG_TOUCHSCREEN_GT811_IIC=y
-CONFIG_TOUCHSCREEN_I30=y
-CONFIG_TOUCHSCREEN_BYD693X=y
-CONFIG_TOUCHSCREEN_SITRONIX_A720=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_GS_MMA7660=y
-CONFIG_GS_MMA8452=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-CONFIG_GS_KXTIK=y
-CONFIG_LIGHT_DEVICE=y
-CONFIG_LS_AP321XX=y
-CONFIG_PROXIMITY_DEVICE=y
-CONFIG_PS_AP321XX=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_RK_HEADSET_DET=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_BATTERY_RK30_ADC_FAC=y
-CONFIG_BATTERY_RK30_AC_CHARGE=y
-CONFIG_BATTERY_RK30_VOL3V8=y
-CONFIG_POWER_ON_CHARGER_DISPLAY=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_TPS65090=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_ACT8931=y
-CONFIG_RK30_PWM_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV2659=y
-CONFIG_SOC_CAMERA_GC0308=y
-CONFIG_SOC_CAMERA_HI704=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_RK2928=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_LCDC_RK2928=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_RK2928=y
-CONFIG_RGA_RK30=y
-CONFIG_RK_LVDS=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_LOGO_LINUX_CLUT224 is not set
-CONFIG_LOGO_LINUX_800x480_CLUT224=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2SO_USE_DOUBLE_CHANNELS=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK_SOC_RK2928=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO=y
-# CONFIG_SDMMC1_RK29 is not set
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HYM8563=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE="root"
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_FORCE_LOAD=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK2928=y
-# CONFIG_DDR_TEST is not set
-# CONFIG_RK29_LAST_LOG is not set
-CONFIG_RK_DEBUG_UART=0
-CONFIG_MACH_RK2928_FPGA=y
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init debug"
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_UNIX=y
-# CONFIG_NET_ACTIVITY_STATS is not set
-# CONFIG_WIRELESS is not set
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MISC_DEVICES=y
-# CONFIG_ANDROID_PMEM is not set
-CONFIG_INPUT_POLLDEV=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-# CONFIG_I2C3_RK30 is not set
-# CONFIG_ADC is not set
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-# CONFIG_HWMON is not set
-# CONFIG_MFD_SUPPORT is not set
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV2659=y
-CONFIG_SOC_CAMERA_OV5642=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_TD043MGEA1=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_LCDC_RK2928=y
-# CONFIG_THREE_FB_BUFFER is not set
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_RTC_CLASS=y
-# CONFIG_CMMB is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DETECT_HUNG_TASK=y
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_SCHEDSTATS=y
-CONFIG_TIMER_STATS=y
-CONFIG_SLUB_DEBUG_ON=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_FTRACE is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK2928=y
-CONFIG_DDR_FREQ=y
-CONFIG_RK_USB_UART=y
-CONFIG_MACH_RK2928_PHONEPAD_760=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_CFG80211=y
-CONFIG_MAC80211=y
-CONFIG_RFKILL=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_MODEM_SOUND=y
-CONFIG_TCC_BT_DEV=y
-CONFIG_BP_AUTO=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RTL8188EU=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TP_760_TS=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_GS_MMA7660=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_DMA_RK29=2
-CONFIG_UART1_RK29=y
-CONFIG_UART1_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_RK_HEADSET_DET=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_BATTERY_RK30_ADC_FAC=y
-CONFIG_BATTERY_RK30_AC_CHARGE=y
-CONFIG_BATTERY_RK30_VOL3V8=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_TPS65090=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_GC0308=y
-CONFIG_SOC_CAMERA_GC2035=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_WY_800X480=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_LCDC_RK2928=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_RK2928=y
-CONFIG_RGA_RK30=y
-CONFIG_RK_LVDS=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_LOGO_LINUX_CLUT224 is not set
-CONFIG_LOGO_LINUX_800x480_CLUT224=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2SO_USE_DOUBLE_CHANNELS=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK_SOC_RK2928=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-# CONFIG_SDMMC1_RK29 is not set
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK2928=y
-CONFIG_DDR_FREQ=y
-CONFIG_RK_USB_UART=y
-CONFIG_MACH_RK2928_PHONEPAD_760=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_CFG80211=y
-CONFIG_MAC80211=y
-CONFIG_RFKILL=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_MODEM_SOUND=y
-CONFIG_TCC_BT_DEV=y
-CONFIG_BP_AUTO=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RTL8188EU=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GT82X_IIC_760=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_GS_MMA7660=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_DMA_RK29=2
-CONFIG_UART1_RK29=y
-CONFIG_UART1_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_RK_HEADSET_DET=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_BATTERY_RK30_ADC_FAC=y
-CONFIG_BATTERY_RK30_AC_CHARGE=y
-CONFIG_BATTERY_RK30_VOL3V8=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_TPS65090=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_GC0308=y
-CONFIG_SOC_CAMERA_GC2035=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_HH070D_LVDS=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_LCDC_RK2928=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_RK2928=y
-CONFIG_RGA_RK30=y
-CONFIG_RK_LVDS=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_LOGO_LINUX_CLUT224 is not set
-CONFIG_LOGO_LINUX_800x480_CLUT224=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2SO_USE_DOUBLE_CHANNELS=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK_SOC_RK2928=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-# CONFIG_SDMMC1_RK29 is not set
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK2928=y
-CONFIG_RK_CLOCK_PROC=y
-CONFIG_RK_USB_UART=y
-CONFIG_MACH_RK2928_PHONEPAD=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_CFG80211=y
-CONFIG_MAC80211=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_MODEM_SOUND=y
-CONFIG_AUDIO_SWITCH=y
-CONFIG_3G_MODULE=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RDA5990=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_I30=y
-CONFIG_TOUCHSCREEN_BYD693X=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-CONFIG_GS_KXTIK=y
-CONFIG_LIGHT_DEVICE=y
-CONFIG_LS_AP321XX=y
-CONFIG_PROXIMITY_DEVICE=y
-CONFIG_PS_AP321XX=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-CONFIG_UART1_RK29=y
-CONFIG_UART1_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_RK_HEADSET_DET=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_BATTERY_RK30_ADC_FAC=y
-CONFIG_BATTERY_RK30_AC_CHARGE=y
-CONFIG_BATTERY_RK30_VOL3V8=y
-CONFIG_POWER_ON_CHARGER_DISPLAY=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_TPS65090=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_RK30_PWM_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_HI704=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_I30_800X480=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_LCDC_RK2928=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_RK2928=y
-CONFIG_RGA_RK30=y
-CONFIG_RK_LVDS=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2SO_USE_DOUBLE_CHANNELS=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK_SOC_RK2928=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK2928=y
-CONFIG_DDR_FREQ=y
-CONFIG_RK_USB_UART=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_CFG80211=y
-CONFIG_MAC80211=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RTL8192CU=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GT811_IIC=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_GS_MMA7660=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_BATTERY_RK30_ADC_FAC=y
-CONFIG_BATTERY_RK30_AC_CHARGE=y
-CONFIG_BATTERY_RK30_VOL3V8=y
-CONFIG_POWER_ON_CHARGER_DISPLAY=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_TPS65090=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_ACT8931=y
-CONFIG_RK30_PWM_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_GC0308=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_RK2928_A720=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_LCDC_RK2928=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_RK2928=y
-CONFIG_RGA_RK30=y
-CONFIG_RK_LVDS=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_LOGO_LINUX_CLUT224 is not set
-CONFIG_LOGO_LINUX_800x480_CLUT224=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2SO_USE_DOUBLE_CHANNELS=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK_SOC_RK2928=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-# CONFIG_SDMMC1_RK29 is not set
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK2928=y
-CONFIG_RK_CLOCK_PROC=y
-CONFIG_MACH_RK2928_TB=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RKWIFI=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_EETI_EGALAX=y
-CONFIG_EETI_EGALAX_MAX_X=1087
-CONFIG_EETI_EGALAX_MAX_Y=800
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_GS_MMA8452=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_TPS65090=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_RK30_PWM_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV2659=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_LCDC_RK2928=y
-CONFIG_LCD_HSD100PXN=y
-CONFIG_RK_TRSM=y
-CONFIG_RK2928_LVDS=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_RK2928=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2SO_USE_DOUBLE_CHANNELS=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK_SOC_HDMI_I2S=y
-CONFIG_SND_RK_SOC_RK2928=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.32.27
-# Wed May 11 10:45:06 2011
-#
-CONFIG_ARM=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_HAVE_SCHED_CLOCK=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_TIME=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-CONFIG_ARCH_HAS_CPUFREQ=y
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-CONFIG_CONSTRUCTORS=y
-
-#
-# General setup
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_LOCK_KERNEL=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_LOCALVERSION=""
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-# CONFIG_SYSVIPC is not set
-# CONFIG_POSIX_MQUEUE is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_AUDIT is not set
-
-#
-# RCU Subsystem
-#
-CONFIG_TREE_RCU=y
-# CONFIG_TREE_PREEMPT_RCU is not set
-# CONFIG_RCU_TRACE is not set
-CONFIG_RCU_FANOUT=32
-# CONFIG_RCU_FANOUT_EXACT is not set
-# CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_IKCONFIG is not set
-CONFIG_LOG_BUF_SHIFT=17
-CONFIG_GROUP_SCHED=y
-CONFIG_FAIR_GROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-# CONFIG_USER_SCHED is not set
-CONFIG_CGROUP_SCHED=y
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-# CONFIG_CGROUP_NS is not set
-CONFIG_CGROUP_FREEZER=y
-# CONFIG_CGROUP_DEVICE is not set
-# CONFIG_CPUSETS is not set
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-# CONFIG_CGROUP_MEM_RES_CTLR is not set
-# CONFIG_SYSFS_DEPRECATED_V2 is not set
-# CONFIG_RELAY is not set
-# CONFIG_NAMESPACES is not set
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_RD_GZIP=y
-# CONFIG_RD_BZIP2 is not set
-# CONFIG_RD_LZMA is not set
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL=y
-CONFIG_ANON_INODES=y
-CONFIG_PANIC_TIMEOUT=5
-CONFIG_EMBEDDED=y
-CONFIG_UID16=y
-# CONFIG_SYSCTL_SYSCALL is not set
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-# CONFIG_ELF_CORE is not set
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_ASHMEM=y
-CONFIG_AIO=y
-
-#
-# Kernel Performance Events And Counters
-#
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_COMPAT_BRK=y
-CONFIG_SLAB=y
-# CONFIG_SLUB is not set
-# CONFIG_SLOB is not set
-# CONFIG_PROFILING is not set
-CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_CLK=y
-
-#
-# GCOV-based kernel profiling
-#
-# CONFIG_SLOW_WORK is not set
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_SLABINFO=y
-CONFIG_RT_MUTEXES=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-# CONFIG_MODULE_FORCE_LOAD is not set
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_MODVERSIONS is not set
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_BLOCK=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_BLK_DEV_INTEGRITY is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-# CONFIG_IOSCHED_AS is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_IOSCHED_CFQ=y
-# CONFIG_DEFAULT_AS is not set
-# CONFIG_DEFAULT_DEADLINE is not set
-CONFIG_DEFAULT_CFQ=y
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="cfq"
-CONFIG_FREEZER=y
-
-#
-# System Type
-#
-CONFIG_MMU=y
-# CONFIG_ARCH_AAEC2000 is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_GEMINI is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_MXC is not set
-# CONFIG_ARCH_STMP3XXX is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_NOMADIK is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP23XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_L7200 is not set
-# CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_LOKI is not set
-# CONFIG_ARCH_MV78XX0 is not set
-# CONFIG_ARCH_ORION5X is not set
-# CONFIG_ARCH_MMP is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
-# CONFIG_ARCH_W90X900 is not set
-# CONFIG_ARCH_PNX4008 is not set
-# CONFIG_ARCH_PXA is not set
-# CONFIG_ARCH_MSM is not set
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_S3C64XX is not set
-# CONFIG_ARCH_S5PC1XX is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_U300 is not set
-# CONFIG_ARCH_DAVINCI is not set
-# CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_BCMRING is not set
-# CONFIG_ARCH_RK2818 is not set
-CONFIG_ARCH_RK29=y
-CONFIG_WIFI_CONTROL_FUNC=y
-# CONFIG_MACH_RK29SDK is not set
-# CONFIG_MACH_RK29SDK_DDR3 is not set
-# CONFIG_MACH_RK29WINACCORD is not set
-CONFIG_MACH_RK29FIH=y
-# CONFIG_MACH_RK29_MALATA is not set
-# CONFIG_MACH_RK29_PHONESDK is not set
-# CONFIG_MACH_RK29_A22 is not set
-# CONFIG_DDR_TYPE_DDRII is not set
-# CONFIG_DDR_TYPE_LPDDR is not set
-# CONFIG_DDR_TYPE_DDR3_800D is not set
-# CONFIG_DDR_TYPE_DDR3_800E is not set
-# CONFIG_DDR_TYPE_DDR3_1066E is not set
-# CONFIG_DDR_TYPE_DDR3_1066F is not set
-# CONFIG_DDR_TYPE_DDR3_1066G is not set
-# CONFIG_DDR_TYPE_DDR3_1333F is not set
-# CONFIG_DDR_TYPE_DDR3_1333G is not set
-# CONFIG_DDR_TYPE_DDR3_1333H is not set
-# CONFIG_DDR_TYPE_DDR3_1333J is not set
-# CONFIG_DDR_TYPE_DDR3_1600G is not set
-# CONFIG_DDR_TYPE_DDR3_1600H is not set
-# CONFIG_DDR_TYPE_DDR3_1600J is not set
-# CONFIG_DDR_TYPE_DDR3_1600K is not set
-# CONFIG_DDR_TYPE_DDR3_1866J is not set
-# CONFIG_DDR_TYPE_DDR3_1866K is not set
-# CONFIG_DDR_TYPE_DDR3_1866L is not set
-# CONFIG_DDR_TYPE_DDR3_1866M is not set
-# CONFIG_DDR_TYPE_DDR3_2133K is not set
-# CONFIG_DDR_TYPE_DDR3_2133L is not set
-# CONFIG_DDR_TYPE_DDR3_2133M is not set
-# CONFIG_DDR_TYPE_DDR3_2133N is not set
-CONFIG_DDR_TYPE_DDR3_DEFAULT=y
-CONFIG_RK29_MEM_SIZE_M=512
-CONFIG_DDR_SDRAM_FREQ=400
-
-#
-# RK29 VPU (Video Processing Unit) support
-#
-CONFIG_RK29_VPU=y
-# CONFIG_RK29_VPU_DEBUG is not set
-# CONFIG_RK29_JTAG is not set
-
-#
-# Processor Type
-#
-CONFIG_CPU_32=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_V7=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_THUMBEE=y
-# CONFIG_CPU_ICACHE_DISABLE is not set
-# CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_HAS_TLS_REG=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-# CONFIG_ARM_ERRATA_430973 is not set
-# CONFIG_ARM_ERRATA_458693 is not set
-# CONFIG_ARM_ERRATA_460075 is not set
-CONFIG_ARM_GIC=y
-CONFIG_PL330=y
-CONFIG_COMMON_CLKDEV=y
-
-#
-# Bus support
-#
-# CONFIG_PCI_SYSCALL is not set
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-# CONFIG_PCCARD is not set
-
-#
-# Kernel Features
-#
-CONFIG_TICK_ONESHOT=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_VMSPLIT_3G=y
-# CONFIG_VMSPLIT_2G is not set
-# CONFIG_VMSPLIT_1G is not set
-CONFIG_PAGE_OFFSET=0xC0000000
-# CONFIG_PREEMPT_NONE is not set
-# CONFIG_PREEMPT_VOLUNTARY is not set
-CONFIG_PREEMPT=y
-CONFIG_HZ=100
-# CONFIG_THUMB2_KERNEL is not set
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_HIGHMEM is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_SPLIT_PTLOCK_CPUS=4
-# CONFIG_PHYS_ADDR_T_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=0
-CONFIG_VIRT_TO_BUS=y
-CONFIG_HAVE_MLOCK=y
-CONFIG_HAVE_MLOCKED_PAGE_BIT=y
-# CONFIG_KSM is not set
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_UACCESS_WITH_MEMCPY is not set
-
-#
-# Boot options
-#
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_CMDLINE=""
-# CONFIG_XIP_KERNEL is not set
-CONFIG_KEXEC=y
-CONFIG_ATAGS_PROC=y
-
-#
-# CPU Power Management
-#
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_TABLE=y
-# CONFIG_CPU_FREQ_DEBUG is not set
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_FREQ_STAT_DETAILS=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-# CONFIG_CPU_IDLE is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_NEON=y
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-CONFIG_HAVE_AOUT=y
-# CONFIG_BINFMT_AOUT is not set
-# CONFIG_BINFMT_MISC is not set
-
-#
-# Power management options
-#
-CONFIG_PM=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_SLEEP=y
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_HAS_WAKELOCK=y
-CONFIG_HAS_EARLYSUSPEND=y
-CONFIG_WAKELOCK=y
-CONFIG_WAKELOCK_STAT=y
-CONFIG_USER_WAKELOCK=y
-CONFIG_EARLYSUSPEND=y
-# CONFIG_NO_USER_SPACE_SCREEN_ACCESS_CONTROL is not set
-CONFIG_CONSOLE_EARLYSUSPEND=y
-# CONFIG_FB_EARLYSUSPEND is not set
-# CONFIG_APM_EMULATION is not set
-# CONFIG_PM_RUNTIME is not set
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
-# CONFIG_XFRM_STATISTICS is not set
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=y
-CONFIG_INET_XFRM_MODE_TUNNEL=y
-CONFIG_INET_XFRM_MODE_BEET=y
-# CONFIG_INET_LRO is not set
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-# CONFIG_IPV6 is not set
-CONFIG_ANDROID_PARANOID_NETWORK=y
-# CONFIG_NETWORK_SECMARK is not set
-# CONFIG_NETFILTER is not set
-# CONFIG_IP_DCCP is not set
-# CONFIG_IP_SCTP is not set
-# CONFIG_RDS is not set
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_NET_DSA is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-# CONFIG_PHONET is not set
-# CONFIG_IEEE802154 is not set
-# CONFIG_NET_SCHED is not set
-# CONFIG_DCB is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_CAN is not set
-# CONFIG_IRDA is not set
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-# CONFIG_BT_BNEP is not set
-# CONFIG_BT_HIDP is not set
-
-#
-# Bluetooth device drivers
-#
-# CONFIG_BT_HCIBTUSB is not set
-# CONFIG_BT_HCIBTSDIO is not set
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-# CONFIG_BT_HCIUART_BCSP is not set
-# CONFIG_BT_HCIUART_LL is not set
-# CONFIG_BT_HCIBCM203X is not set
-# CONFIG_BT_HCIBPA10X is not set
-# CONFIG_BT_HCIBFUSB is not set
-# CONFIG_BT_HCIVHCI is not set
-# CONFIG_BT_MRVL is not set
-CONFIG_BT_HCIBCM4325=y
-CONFIG_IDBLOCK=y
-# CONFIG_WIFI_MAC is not set
-# CONFIG_AF_RXRPC is not set
-CONFIG_WIRELESS=y
-# CONFIG_CFG80211 is not set
-CONFIG_CFG80211_DEFAULT_PS_VALUE=0
-# CONFIG_WIRELESS_OLD_REGULATORY is not set
-CONFIG_WIRELESS_EXT=y
-CONFIG_WIRELESS_EXT_SYSFS=y
-# CONFIG_LIB80211 is not set
-
-#
-# CFG80211 needs to be enabled for MAC80211
-#
-
-#
-# Some wireless drivers require a rate control algorithm
-#
-# CONFIG_WIMAX is not set
-CONFIG_RFKILL=y
-# CONFIG_RFKILL_PM is not set
-# CONFIG_RFKILL_INPUT is not set
-# CONFIG_NET_9P is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_CONNECTOR is not set
-CONFIG_MTD=y
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_TESTS is not set
-# CONFIG_MTD_CONCAT is not set
-CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_REDBOOT_PARTS is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_AFS_PARTS is not set
-# CONFIG_MTD_AR7_PARTS is not set
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
-# CONFIG_INFTL is not set
-# CONFIG_RFD_FTL is not set
-# CONFIG_SSFDC is not set
-# CONFIG_MTD_OOPS is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-# CONFIG_MTD_CFI is not set
-# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_ABSENT is not set
-
-#
-# Mapping drivers for chip access
-#
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_PLATRAM is not set
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLOCK2MTD is not set
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-CONFIG_MTD_NAND_IDS=y
-# CONFIG_MTD_NAND is not set
-CONFIG_MTD_RKNAND=y
-CONFIG_MTD_NAND_RK29XX=y
-CONFIG_RKFTL_PAGECACHE_SIZE=64
-CONFIG_MTD_RKNAND_BUFFER=y
-# CONFIG_MTD_NAND_RK29XX_DEBUG is not set
-# CONFIG_MTD_ONENAND is not set
-
-#
-# LPDDR flash memory drivers
-#
-# CONFIG_MTD_LPDDR is not set
-
-#
-# UBI - Unsorted block images
-#
-# CONFIG_MTD_UBI is not set
-# CONFIG_PARPORT is not set
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=y
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_UB is not set
-# CONFIG_BLK_DEV_RAM is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-# CONFIG_MG_DISK is not set
-CONFIG_MISC_DEVICES=y
-CONFIG_ANDROID_PMEM=y
-# CONFIG_ICS932S401 is not set
-# CONFIG_ENCLOSURE_SERVICES is not set
-# CONFIG_KERNEL_DEBUGGER_CORE is not set
-# CONFIG_ISL29003 is not set
-# CONFIG_UID_STAT is not set
-# CONFIG_WL127X_RFKILL is not set
-CONFIG_APANIC=y
-CONFIG_APANIC_PLABEL="kpanic"
-# CONFIG_STE is not set
-# CONFIG_MTK23D is not set
-# CONFIG_FM580X is not set
-# CONFIG_C2PORT is not set
-
-#
-# EEPROM support
-#
-# CONFIG_EEPROM_AT24 is not set
-# CONFIG_EEPROM_LEGACY is not set
-# CONFIG_EEPROM_MAX6875 is not set
-# CONFIG_EEPROM_93CX6 is not set
-CONFIG_RK29_SUPPORT_MODEM=y
-CONFIG_MODEM_ROCKCHIP_DEMO=y
-CONFIG_RK29_GPS=y
-# CONFIG_GPS_GNS7560 is not set
-
-#
-# Motion Sensors Support
-#
-# CONFIG_MPU_NONE is not set
-CONFIG_SENSORS_MPU3050=y
-# CONFIG_SENSORS_MPU6000 is not set
-# CONFIG_SENSORS_ACCELEROMETER_NONE is not set
-# CONFIG_SENSORS_ADXL346 is not set
-# CONFIG_SENSORS_BMA150 is not set
-# CONFIG_SENSORS_BMA222 is not set
-# CONFIG_SENSORS_KXSD9 is not set
-CONFIG_SENSORS_KXTF9=y
-# CONFIG_SENSORS_LIS331DLH is not set
-# CONFIG_SENSORS_LSM303DLHA is not set
-# CONFIG_SENSORS_MMA8450 is not set
-# CONFIG_SENSORS_MMA8451 is not set
-# CONFIG_SENSORS_COMPASS_NONE is not set
-CONFIG_SENSORS_AK8975=y
-# CONFIG_SENSORS_MMC314X is not set
-# CONFIG_SENSORS_AMI30X is not set
-# CONFIG_SENSORS_HMC5883 is not set
-# CONFIG_SENSORS_LSM303DLHM is not set
-# CONFIG_SENSORS_YAS529 is not set
-# CONFIG_SENSORS_HSCDTD00XX is not set
-CONFIG_SENSORS_PRESSURE_NONE=y
-# CONFIG_SENSORS_BMA085 is not set
-# CONFIG_SENSORS_MPU_DEBUG is not set
-CONFIG_HAVE_IDE=y
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_DMA=y
-# CONFIG_SCSI_TGT is not set
-# CONFIG_SCSI_NETLINK is not set
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=y
-# CONFIG_CHR_DEV_ST is not set
-# CONFIG_CHR_DEV_OSST is not set
-# CONFIG_BLK_DEV_SR is not set
-# CONFIG_CHR_DEV_SG is not set
-# CONFIG_CHR_DEV_SCH is not set
-CONFIG_SCSI_MULTI_LUN=y
-# CONFIG_SCSI_CONSTANTS is not set
-# CONFIG_SCSI_LOGGING is not set
-# CONFIG_SCSI_SCAN_ASYNC is not set
-CONFIG_SCSI_WAIT_SCAN=m
-
-#
-# SCSI Transports
-#
-# CONFIG_SCSI_SPI_ATTRS is not set
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_LIBSAS is not set
-# CONFIG_SCSI_SRP_ATTRS is not set
-CONFIG_SCSI_LOWLEVEL=y
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_LIBFC is not set
-# CONFIG_LIBFCOE is not set
-# CONFIG_SCSI_DEBUG is not set
-# CONFIG_SCSI_DH is not set
-# CONFIG_SCSI_OSD_INITIATOR is not set
-# CONFIG_ATA is not set
-CONFIG_MD=y
-# CONFIG_BLK_DEV_MD is not set
-CONFIG_BLK_DEV_DM=y
-# CONFIG_DM_DEBUG is not set
-CONFIG_DM_CRYPT=y
-# CONFIG_DM_SNAPSHOT is not set
-# CONFIG_DM_MIRROR is not set
-# CONFIG_DM_ZERO is not set
-# CONFIG_DM_MULTIPATH is not set
-# CONFIG_DM_DELAY is not set
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_MACVLAN is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_VETH is not set
-CONFIG_PHYLIB=y
-
-#
-# MII PHY device drivers
-#
-# CONFIG_MARVELL_PHY is not set
-# CONFIG_DAVICOM_PHY is not set
-# CONFIG_QSEMI_PHY is not set
-# CONFIG_LXT_PHY is not set
-# CONFIG_CICADA_PHY is not set
-# CONFIG_VITESSE_PHY is not set
-# CONFIG_SMSC_PHY is not set
-# CONFIG_BROADCOM_PHY is not set
-# CONFIG_ICPLUS_PHY is not set
-# CONFIG_REALTEK_PHY is not set
-# CONFIG_NATIONAL_PHY is not set
-# CONFIG_STE10XP is not set
-# CONFIG_LSI_ET1011C_PHY is not set
-# CONFIG_FIXED_PHY is not set
-# CONFIG_MDIO_BITBANG is not set
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-# CONFIG_AX88796 is not set
-CONFIG_RK29_VMAC=y
-# CONFIG_SMC91X is not set
-# CONFIG_DM9000 is not set
-# CONFIG_ETHOC is not set
-# CONFIG_SMC911X is not set
-# CONFIG_SMSC911X is not set
-# CONFIG_DNET is not set
-# CONFIG_IBM_NEW_EMAC_ZMII is not set
-# CONFIG_IBM_NEW_EMAC_RGMII is not set
-# CONFIG_IBM_NEW_EMAC_TAH is not set
-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
-# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
-# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
-# CONFIG_B44 is not set
-# CONFIG_KS8842 is not set
-# CONFIG_KS8851_MLL is not set
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN=y
-CONFIG_WLAN_80211=y
-# CONFIG_WIFI_NONE is not set
-CONFIG_BCM4329=y
-# CONFIG_MV8686 is not set
-# CONFIG_BCM4319 is not set
-
-#
-# Enable WiMAX (Networking options) to see the WiMAX drivers
-#
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET is not set
-# CONFIG_USB_HSO is not set
-# CONFIG_WAN is not set
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOE=y
-CONFIG_PPPOL2TP=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_SLIP is not set
-CONFIG_SLHC=y
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_ISDN is not set
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-CONFIG_INPUT_POLLDEV=y
-
-#
-# Userland interfaces
-#
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_JOYDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_EVBUG is not set
-CONFIG_INPUT_KEYRESET=y
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYS_RK29=y
-# CONFIG_SYNAPTICS_SO340010 is not set
-# CONFIG_KEYBOARD_ADP5588 is not set
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_QT2160 is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_GPIO is not set
-# CONFIG_KEYBOARD_WM831X_GPIO is not set
-# CONFIG_KEYBOARD_MATRIX is not set
-# CONFIG_KEYBOARD_MAX7359 is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_OPENCORES is not set
-# CONFIG_KEYBOARD_STOWAWAY is not set
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-# CONFIG_TOUCHSCREEN_ILI2102_IIC is not set
-# CONFIG_TOUCHSCREEN_IT7250 is not set
-# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
-# CONFIG_TOUCHSCREEN_AD7879 is not set
-# CONFIG_TOUCHSCREEN_EETI is not set
-# CONFIG_TOUCHSCREEN_FUJITSU is not set
-# CONFIG_TOUCHSCREEN_GUNZE is not set
-# CONFIG_TOUCHSCREEN_ELO is not set
-# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
-# CONFIG_TOUCHSCREEN_MCS5000 is not set
-# CONFIG_TOUCHSCREEN_MTOUCH is not set
-# CONFIG_TOUCHSCREEN_INEXIO is not set
-# CONFIG_TOUCHSCREEN_MK712 is not set
-# CONFIG_TOUCHSCREEN_PENMOUNT is not set
-# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI is not set
-# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
-# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
-# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
-# CONFIG_TOUCHSCREEN_TSC2007 is not set
-# CONFIG_TOUCHSCREEN_W90X900 is not set
-# CONFIG_HANNSTAR_P1003 is not set
-CONFIG_ATMEL_MXT224=y
-CONFIG_MXT224_MAX_X=4095
-CONFIG_MXT224_MAX_Y=4095
-# CONFIG_SINTEK_3FA16 is not set
-# CONFIG_EETI_EGALAX is not set
-# CONFIG_TOUCHSCREEN_IT7260 is not set
-# CONFIG_TOUCHSCREEN_GT801_IIC is not set
-CONFIG_INPUT_MISC=y
-# CONFIG_INPUT_LPSENSOR_ISL29028 is not set
-# CONFIG_INPUT_LPSENSOR_CM3602 is not set
-# CONFIG_INPUT_ATI_REMOTE is not set
-# CONFIG_INPUT_ATI_REMOTE2 is not set
-# CONFIG_INPUT_KEYCHORD is not set
-# CONFIG_INPUT_KEYSPAN_REMOTE is not set
-# CONFIG_INPUT_POWERMATE is not set
-# CONFIG_INPUT_YEALINK is not set
-# CONFIG_INPUT_CM109 is not set
-# CONFIG_INPUT_TPS65910_PWRBUTTON is not set
-# CONFIG_INPUT_UINPUT is not set
-# CONFIG_INPUT_GPIO is not set
-# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
-# CONFIG_MAG_SENSORS is not set
-# CONFIG_G_SENSOR_DEVICE is not set
-# CONFIG_INPUT_JOGBALL is not set
-CONFIG_LIGHT_SENSOR_DEVICE=y
-CONFIG_CM3202=y
-
-#
-# Hardware I/O ports
-#
-# CONFIG_SERIO is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_DEVMEM=y
-CONFIG_DEVKMEM=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-CONFIG_UART1_RK29=y
-CONFIG_UART2_RK29=y
-CONFIG_UART2_CTS_RTS_RK29=y
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-CONFIG_SERIAL_RK29_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
-# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_IPMI_HANDLER is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_R3964 is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_TCG_TPM is not set
-# CONFIG_DCC_TTY is not set
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_HELPER_AUTO=y
-
-#
-# I2C Hardware Bus support
-#
-CONFIG_I2C_RK29=y
-
-#
-# Now, there are four I2C interfaces selected by developer.
-#
-CONFIG_I2C0_RK29=y
-CONFIG_I2C1_RK29=y
-CONFIG_I2C2_RK29=y
-CONFIG_I2C_DEV_RK29=y
-
-#
-# Miscellaneous I2C Chip support
-#
-# CONFIG_DS1682 is not set
-# CONFIG_SENSORS_TSL2550 is not set
-# CONFIG_SENSORS_PCA963X is not set
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-# CONFIG_I2C_DEBUG_CHIP is not set
-# CONFIG_SPI is not set
-CONFIG_ADC=y
-# CONFIG_ADC_RK28 is not set
-CONFIG_ADC_RK29=y
-# CONFIG_SPI_FPGA is not set
-
-#
-# Headset device support
-#
-# CONFIG_RK_HEADSET_DET is not set
-
-#
-# PPS support
-#
-# CONFIG_PPS is not set
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_GPIOLIB=y
-# CONFIG_DEBUG_GPIO is not set
-CONFIG_GPIO_SYSFS=y
-
-#
-# Memory mapped GPIO expanders:
-#
-
-#
-# I2C GPIO expanders:
-#
-# CONFIG_GPIO_MAX732X is not set
-# CONFIG_GPIO_PCA953X is not set
-# CONFIG_GPIO_PCF857X is not set
-# CONFIG_GPIO_TPS65910 is not set
-
-#
-# PCI GPIO expanders:
-#
-
-#
-# SPI GPIO expanders:
-#
-
-#
-# AC97 GPIO expanders:
-#
-# CONFIG_GPIO_PCA9554 is not set
-# CONFIG_IOEXTEND_TCA6424 is not set
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-# CONFIG_EXPAND_GPIO_SOFT_INTERRUPT is not set
-CONFIG_SPI_FPGA_GPIO_NUM=96
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=16
-# CONFIG_W1 is not set
-CONFIG_POWER_SUPPLY=y
-# CONFIG_POWER_SUPPLY_DEBUG is not set
-# CONFIG_PDA_POWER is not set
-# CONFIG_BATTERY_DS2760 is not set
-# CONFIG_BATTERY_DS2782 is not set
-# CONFIG_BATTERY_BQ27x00 is not set
-# CONFIG_BATTERY_MAX17040 is not set
-# CONFIG_BATTERY_STC3100 is not set
-CONFIG_BATTERY_BQ27510=y
-# CONFIG_BATTERY_BQ3060 is not set
-# CONFIG_CHECK_BATT_CAPACITY is not set
-# CONFIG_NO_BATTERY_IC is not set
-# CONFIG_HWMON is not set
-# CONFIG_THERMAL is not set
-# CONFIG_WATCHDOG is not set
-CONFIG_SSB_POSSIBLE=y
-
-#
-# Sonics Silicon Backplane
-#
-# CONFIG_SSB is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_CORE is not set
-# CONFIG_MFD_SM501 is not set
-# CONFIG_MFD_ASIC3 is not set
-# CONFIG_HTC_EGPIO is not set
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_TPS65010 is not set
-# CONFIG_TWL4030_CORE is not set
-CONFIG_TPS65910_CORE=y
-# CONFIG_MFD_TMIO is not set
-# CONFIG_MFD_T7L66XB is not set
-# CONFIG_MFD_TC6387XB is not set
-# CONFIG_MFD_TC6393XB is not set
-# CONFIG_PMIC_DA903X is not set
-# CONFIG_MFD_WM8994 is not set
-# CONFIG_MFD_WM8400 is not set
-# CONFIG_MFD_WM831X_I2C is not set
-# CONFIG_MFD_WM8350_I2C is not set
-# CONFIG_MFD_PCF50633 is not set
-# CONFIG_AB3100_CORE is not set
-CONFIG_REGULATOR=y
-# CONFIG_REGULATOR_DEBUG is not set
-# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
-# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
-# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
-# CONFIG_REGULATOR_BQ24022 is not set
-# CONFIG_REGULATOR_MAX1586 is not set
-CONFIG_REGULATOR_TPS65910=y
-# CONFIG_REGULATOR_LP3971 is not set
-# CONFIG_REGULATOR_TPS65023 is not set
-# CONFIG_REGULATOR_TPS6507X is not set
-# CONFIG_RK2818_REGULATOR_CHARGE is not set
-# CONFIG_RK2818_REGULATOR_LP8725 is not set
-# CONFIG_RK29_PWM_REGULATOR is not set
-CONFIG_MEDIA_SUPPORT=y
-
-#
-# Multimedia core support
-#
-CONFIG_VIDEO_DEV=y
-CONFIG_VIDEO_V4L2_COMMON=y
-CONFIG_VIDEO_ALLOW_V4L1=y
-CONFIG_VIDEO_V4L1_COMPAT=y
-# CONFIG_DVB_CORE is not set
-CONFIG_VIDEO_MEDIA=y
-
-#
-# Multimedia drivers
-#
-# CONFIG_MEDIA_ATTACH is not set
-CONFIG_MEDIA_TUNER=y
-# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
-CONFIG_MEDIA_TUNER_SIMPLE=y
-CONFIG_MEDIA_TUNER_TDA8290=y
-CONFIG_MEDIA_TUNER_TDA9887=y
-CONFIG_MEDIA_TUNER_TEA5761=y
-CONFIG_MEDIA_TUNER_TEA5767=y
-CONFIG_MEDIA_TUNER_MT20XX=y
-CONFIG_MEDIA_TUNER_XC2028=y
-CONFIG_MEDIA_TUNER_XC5000=y
-CONFIG_MEDIA_TUNER_MC44S803=y
-CONFIG_VIDEO_V4L2=y
-CONFIG_VIDEO_V4L1=y
-CONFIG_VIDEOBUF_GEN=y
-CONFIG_VIDEOBUF_DMA_CONTIG=y
-# CONFIG_VIDEO_RK29XX_VOUT is not set
-CONFIG_VIDEO_CAPTURE_DRIVERS=y
-# CONFIG_VIDEO_ADV_DEBUG is not set
-# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
-CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
-# CONFIG_VIDEO_VIVI is not set
-# CONFIG_VIDEO_CPIA is not set
-# CONFIG_VIDEO_CPIA2 is not set
-# CONFIG_VIDEO_SAA5246A is not set
-# CONFIG_VIDEO_SAA5249 is not set
-CONFIG_SOC_CAMERA=y
-# CONFIG_SOC_CAMERA_MT9M001 is not set
-# CONFIG_SOC_CAMERA_MT9M111 is not set
-# CONFIG_SOC_CAMERA_MT9M112 is not set
-# CONFIG_SOC_CAMERA_MT9T031 is not set
-CONFIG_SOC_CAMERA_MT9P111=y
-# CONFIG_SOC_CAMERA_MT9D112 is not set
-# CONFIG_SOC_CAMERA_MT9D113 is not set
-# CONFIG_SOC_CAMERA_MT9V022 is not set
-# CONFIG_SOC_CAMERA_TW9910 is not set
-# CONFIG_SOC_CAMERA_PLATFORM is not set
-# CONFIG_SOC_CAMERA_OV772X is not set
-# CONFIG_SOC_CAMERA_OV7675 is not set
-# CONFIG_SOC_CAMERA_OV2655 is not set
-# CONFIG_SOC_CAMERA_OV2659 is not set
-# CONFIG_SOC_CAMERA_OV9650 is not set
-# CONFIG_SOC_CAMERA_OV2640 is not set
-# CONFIG_SOC_CAMERA_OV3640 is not set
-# CONFIG_SOC_CAMERA_OV5642 is not set
-# CONFIG_SOC_CAMERA_OV5640 is not set
-CONFIG_SOC_CAMERA_S5K6AA=y
-# CONFIG_SOC_CAMERA_GT2005 is not set
-# CONFIG_SOC_CAMERA_GC0308 is not set
-# CONFIG_SOC_CAMERA_GC0309 is not set
-# CONFIG_SOC_CAMERA_GC2015 is not set
-# CONFIG_SOC_CAMERA_HI253 is not set
-# CONFIG_SOC_CAMERA_HI704 is not set
-# CONFIG_SOC_CAMERA_SIV120B is not set
-# CONFIG_SOC_CAMERA_SID130B is not set
-# CONFIG_SOC_CAMERA_NT99250 is not set
-# CONFIG_VIDEO_SH_MOBILE_CEU is not set
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_WORK_ONEFRAME=y
-# CONFIG_VIDEO_RK29_WORK_PINGPONG is not set
-CONFIG_VIDEO_RK29_WORK_IPP=y
-# CONFIG_VIDEO_RK29_WORK_NOT_IPP is not set
-CONFIG_V4L_USB_DRIVERS=y
-# CONFIG_USB_VIDEO_CLASS is not set
-CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
-CONFIG_USB_GSPCA=m
-# CONFIG_USB_M5602 is not set
-# CONFIG_USB_STV06XX is not set
-# CONFIG_USB_GL860 is not set
-# CONFIG_USB_GSPCA_CONEX is not set
-# CONFIG_USB_GSPCA_ETOMS is not set
-# CONFIG_USB_GSPCA_FINEPIX is not set
-# CONFIG_USB_GSPCA_JEILINJ is not set
-# CONFIG_USB_GSPCA_MARS is not set
-# CONFIG_USB_GSPCA_MR97310A is not set
-# CONFIG_USB_GSPCA_OV519 is not set
-# CONFIG_USB_GSPCA_OV534 is not set
-# CONFIG_USB_GSPCA_PAC207 is not set
-# CONFIG_USB_GSPCA_PAC7311 is not set
-# CONFIG_USB_GSPCA_SN9C20X is not set
-# CONFIG_USB_GSPCA_SONIXB is not set
-# CONFIG_USB_GSPCA_SONIXJ is not set
-# CONFIG_USB_GSPCA_SPCA500 is not set
-# CONFIG_USB_GSPCA_SPCA501 is not set
-# CONFIG_USB_GSPCA_SPCA505 is not set
-# CONFIG_USB_GSPCA_SPCA506 is not set
-# CONFIG_USB_GSPCA_SPCA508 is not set
-# CONFIG_USB_GSPCA_SPCA561 is not set
-# CONFIG_USB_GSPCA_SQ905 is not set
-# CONFIG_USB_GSPCA_SQ905C is not set
-# CONFIG_USB_GSPCA_STK014 is not set
-# CONFIG_USB_GSPCA_SUNPLUS is not set
-# CONFIG_USB_GSPCA_T613 is not set
-# CONFIG_USB_GSPCA_TV8532 is not set
-# CONFIG_USB_GSPCA_VC032X is not set
-# CONFIG_USB_GSPCA_ZC3XX is not set
-# CONFIG_VIDEO_PVRUSB2 is not set
-# CONFIG_VIDEO_HDPVR is not set
-# CONFIG_VIDEO_EM28XX is not set
-# CONFIG_VIDEO_CX231XX is not set
-# CONFIG_VIDEO_USBVISION is not set
-# CONFIG_USB_VICAM is not set
-# CONFIG_USB_IBMCAM is not set
-# CONFIG_USB_KONICAWC is not set
-# CONFIG_USB_QUICKCAM_MESSENGER is not set
-# CONFIG_USB_ET61X251 is not set
-# CONFIG_VIDEO_OVCAMCHIP is not set
-# CONFIG_USB_OV511 is not set
-# CONFIG_USB_SE401 is not set
-# CONFIG_USB_SN9C102 is not set
-# CONFIG_USB_STV680 is not set
-# CONFIG_USB_ZC0301 is not set
-# CONFIG_USB_PWC is not set
-CONFIG_USB_PWC_INPUT_EVDEV=y
-# CONFIG_USB_ZR364XX is not set
-# CONFIG_USB_STKWEBCAM is not set
-# CONFIG_USB_S2255 is not set
-CONFIG_RADIO_ADAPTERS=y
-# CONFIG_I2C_SI4713 is not set
-# CONFIG_RADIO_SI4713 is not set
-# CONFIG_USB_DSBR is not set
-# CONFIG_RADIO_SI470X is not set
-# CONFIG_USB_MR800 is not set
-# CONFIG_RADIO_TEA5764 is not set
-# CONFIG_SMS_SIANO_MDTV is not set
-# CONFIG_DAB is not set
-
-#
-# Graphics support
-#
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-CONFIG_FB=y
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB_DDC is not set
-# CONFIG_FB_BOOT_VESA_SUPPORT is not set
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-# CONFIG_FB_SYS_FILLRECT is not set
-# CONFIG_FB_SYS_COPYAREA is not set
-# CONFIG_FB_SYS_IMAGEBLIT is not set
-# CONFIG_FB_FOREIGN_ENDIAN is not set
-# CONFIG_FB_SYS_FOPS is not set
-# CONFIG_FB_SVGALIB is not set
-# CONFIG_FB_MACMODES is not set
-# CONFIG_FB_BACKLIGHT is not set
-# CONFIG_FB_MODE_HELPERS is not set
-# CONFIG_FB_TILEBLITTING is not set
-
-#
-# Frame buffer hardware drivers
-#
-# CONFIG_FB_S1D13XXX is not set
-# CONFIG_FB_RK2818 is not set
-CONFIG_FB_RK29=y
-# CONFIG_FB_WORK_IPP is not set
-# CONFIG_FB_VIRTUAL is not set
-# CONFIG_FB_METRONOME is not set
-# CONFIG_FB_MB862XX is not set
-# CONFIG_FB_BROADSHEET is not set
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_BACKLIGHT_RK29_BL=y
-CONFIG_FIH_TOUCHKEY_LED=y
-# CONFIG_BACKLIGHT_AW9364 is not set
-
-#
-# Display device support
-#
-CONFIG_DISPLAY_SUPPORT=y
-
-#
-# Display hardware drivers
-#
-# CONFIG_LCD_NULL is not set
-# CONFIG_LCD_TD043MGEA1 is not set
-# CONFIG_LCD_HX8357 is not set
-# CONFIG_LCD_TJ048NC01CA is not set
-# CONFIG_LCD_HL070VM4AU is not set
-# CONFIG_LCD_HSD070IDW1 is not set
-# CONFIG_LCD_RGB_TFT480800_25_E is not set
-# CONFIG_LCD_HSD100PXN is not set
-# CONFIG_LCD_B101AW06 is not set
-# CONFIG_LCD_LS035Y8DX02A is not set
-# CONFIG_LCD_A060SE02 is not set
-# CONFIG_LCD_S1D13521 is not set
-# CONFIG_LCD_NT35582 is not set
-# CONFIG_LCD_NT35580 is not set
-# CONFIG_LCD_IPS1P5680_V1_E is not set
-# CONFIG_LCD_MCU_TFT480800_25_E is not set
-# CONFIG_LCD_ILI9803_CPT4_3 is not set
-# CONFIG_DEFAULT_OUT_HDMI is not set
-CONFIG_LCD_AT070TNA2=y
-
-#
-# HDMI
-#
-CONFIG_HDMI=y
-# CONFIG_HDMI_OLD is not set
-CONFIG_HDMI_NEW=y
-CONFIG_ANX7150_NEW=y
-# CONFIG_ANX9030_NEW is not set
-# CONFIG_HDMI_DEBUG is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-CONFIG_FONTS=y
-# CONFIG_FONT_8x8 is not set
-CONFIG_FONT_8x16=y
-# CONFIG_FONT_6x11 is not set
-# CONFIG_FONT_7x14 is not set
-# CONFIG_FONT_PEARL_8x8 is not set
-# CONFIG_FONT_ACORN_8x8 is not set
-# CONFIG_FONT_MINI_4x6 is not set
-# CONFIG_FONT_SUN8x16 is not set
-# CONFIG_FONT_SUN12x22 is not set
-# CONFIG_FONT_10x18 is not set
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_LOGO_LINUX_CLUT224=y
-CONFIG_SOUND=y
-# CONFIG_SOUND_OSS_CORE is not set
-CONFIG_SND=y
-CONFIG_SND_TIMER=y
-CONFIG_SND_PCM=y
-CONFIG_SND_JACK=y
-# CONFIG_SND_SEQUENCER is not set
-# CONFIG_SND_MIXER_OSS is not set
-# CONFIG_SND_PCM_OSS is not set
-# CONFIG_SND_HRTIMER is not set
-# CONFIG_SND_DYNAMIC_MINORS is not set
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_VERBOSE_PRINTK is not set
-# CONFIG_SND_DEBUG is not set
-# CONFIG_SND_RAWMIDI_SEQ is not set
-# CONFIG_SND_OPL3_LIB_SEQ is not set
-# CONFIG_SND_OPL4_LIB_SEQ is not set
-# CONFIG_SND_SBAWE_SEQ is not set
-# CONFIG_SND_EMU10K1_SEQ is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_USB=y
-# CONFIG_SND_USB_AUDIO is not set
-# CONFIG_SND_USB_CAIAQ is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_RK29_SOC_I2S=y
-# CONFIG_SND_RK29_SOC_I2S_2CH is not set
-CONFIG_SND_RK29_SOC_I2S_8CH=y
-# CONFIG_SND_RK29_SOC_WM8988 is not set
-CONFIG_SND_RK29_SOC_WM8900=y
-# CONFIG_SND_RK29_SOC_alc5621 is not set
-# CONFIG_SND_RK29_SOC_alc5631 is not set
-# CONFIG_SND_RK29_SOC_WM8994 is not set
-# CONFIG_SND_RK29_CODEC_SOC_MASTER is not set
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_SND_SOC_I2C_AND_SPI=y
-# CONFIG_SND_SOC_ALL_CODECS is not set
-CONFIG_SND_SOC_WM8900=y
-# CONFIG_SOUND_PRIME is not set
-# CONFIG_HID_SUPPORT is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ARCH_HAS_HCD=y
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-CONFIG_USB=y
-# CONFIG_USB_DEBUG is not set
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-
-#
-# Miscellaneous USB options
-#
-# CONFIG_USB_DEVICEFS is not set
-CONFIG_USB_DEVICE_CLASS=y
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_SUSPEND is not set
-# CONFIG_USB_OTG is not set
-# CONFIG_USB_OTG_WHITELIST is not set
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-# CONFIG_USB_MON is not set
-# CONFIG_USB_WUSB is not set
-# CONFIG_USB_WUSB_CBAF is not set
-
-#
-# USB Host Controller Drivers
-#
-# CONFIG_USB_C67X00_HCD is not set
-# CONFIG_USB_OXU210HP_HCD is not set
-# CONFIG_USB_ISP116X_HCD is not set
-# CONFIG_USB_ISP1760_HCD is not set
-# CONFIG_USB_ISP1362_HCD is not set
-# CONFIG_USB_SL811_HCD is not set
-# CONFIG_USB_R8A66597_HCD is not set
-# CONFIG_USB_HWA_HCD is not set
-# CONFIG_USB_MUSB_HDRC is not set
-# CONFIG_USB_GADGET_MUSB_HDRC is not set
-
-#
-# USB Device Class drivers
-#
-CONFIG_USB_ACM=y
-# CONFIG_USB_PRINTER is not set
-# CONFIG_USB_WDM is not set
-# CONFIG_USB_TMC is not set
-
-#
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
-#
-
-#
-# also be needed; see USB_STORAGE Help for more info
-#
-CONFIG_USB_STORAGE=y
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_USBAT is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_STORAGE_SDDR55 is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_ALAUDA is not set
-# CONFIG_USB_STORAGE_ONETOUCH is not set
-# CONFIG_USB_STORAGE_KARMA is not set
-# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_MICROTEK is not set
-
-#
-# USB port drivers
-#
-CONFIG_USB_SERIAL=y
-# CONFIG_USB_SERIAL_CONSOLE is not set
-# CONFIG_USB_EZUSB is not set
-CONFIG_USB_SERIAL_GENERIC=y
-# CONFIG_USB_SERIAL_AIRCABLE is not set
-# CONFIG_USB_SERIAL_ARK3116 is not set
-# CONFIG_USB_SERIAL_BELKIN is not set
-# CONFIG_USB_SERIAL_CH341 is not set
-# CONFIG_USB_SERIAL_WHITEHEAT is not set
-# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
-# CONFIG_USB_SERIAL_CP210X is not set
-# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
-# CONFIG_USB_SERIAL_EMPEG is not set
-# CONFIG_USB_SERIAL_FTDI_SIO is not set
-# CONFIG_USB_SERIAL_FUNSOFT is not set
-# CONFIG_USB_SERIAL_VISOR is not set
-# CONFIG_USB_SERIAL_IPAQ is not set
-# CONFIG_USB_SERIAL_IR is not set
-# CONFIG_USB_SERIAL_EDGEPORT is not set
-# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
-# CONFIG_USB_SERIAL_GARMIN is not set
-# CONFIG_USB_SERIAL_IPW is not set
-# CONFIG_USB_SERIAL_IUU is not set
-# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
-# CONFIG_USB_SERIAL_KEYSPAN is not set
-# CONFIG_USB_SERIAL_KLSI is not set
-# CONFIG_USB_SERIAL_KOBIL_SCT is not set
-# CONFIG_USB_SERIAL_MCT_U232 is not set
-# CONFIG_USB_SERIAL_MOS7720 is not set
-# CONFIG_USB_SERIAL_MOS7840 is not set
-# CONFIG_USB_SERIAL_MOTOROLA is not set
-# CONFIG_USB_SERIAL_NAVMAN is not set
-# CONFIG_USB_SERIAL_PL2303 is not set
-# CONFIG_USB_SERIAL_OTI6858 is not set
-# CONFIG_USB_SERIAL_QUALCOMM is not set
-# CONFIG_USB_SERIAL_SPCP8X5 is not set
-# CONFIG_USB_SERIAL_HP4X is not set
-# CONFIG_USB_SERIAL_SAFE is not set
-# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
-# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
-# CONFIG_USB_SERIAL_SYMBOL is not set
-# CONFIG_USB_SERIAL_TI is not set
-# CONFIG_USB_SERIAL_CYBERJACK is not set
-# CONFIG_USB_SERIAL_XIRCOM is not set
-CONFIG_USB_SERIAL_OPTION=y
-# CONFIG_USB_SERIAL_OMNINET is not set
-# CONFIG_USB_SERIAL_OPTICON is not set
-# CONFIG_USB_SERIAL_DEBUG is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_SEVSEG is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_BERRY_CHARGE is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYPRESS_CY7C63 is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_FTDI_ELAN is not set
-# CONFIG_USB_APPLEDISPLAY is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TRANCEVIBRATOR is not set
-# CONFIG_USB_IOWARRIOR is not set
-# CONFIG_USB_TEST is not set
-# CONFIG_USB_ISIGHTFW is not set
-# CONFIG_USB_VST is not set
-CONFIG_USB_GADGET=y
-# CONFIG_USB_GADGET_DEBUG is not set
-# CONFIG_USB_GADGET_DEBUG_FILES is not set
-CONFIG_USB_GADGET_VBUS_DRAW=2
-CONFIG_USB_GADGET_SELECTED=y
-# CONFIG_USB_GADGET_AT91 is not set
-# CONFIG_USB_GADGET_ATMEL_USBA is not set
-# CONFIG_USB_GADGET_FSL_USB2 is not set
-# CONFIG_USB_GADGET_LH7A40X is not set
-# CONFIG_USB_GADGET_OMAP is not set
-# CONFIG_USB_GADGET_PXA25X is not set
-# CONFIG_USB_GADGET_R8A66597 is not set
-# CONFIG_USB_GADGET_PXA27X is not set
-# CONFIG_USB_GADGET_S3C_HSOTG is not set
-# CONFIG_USB_GADGET_IMX is not set
-# CONFIG_USB_GADGET_S3C2410 is not set
-# CONFIG_USB_GADGET_M66592 is not set
-# CONFIG_USB_GADGET_AMD5536UDC is not set
-# CONFIG_USB_GADGET_FSL_QE is not set
-# CONFIG_USB_GADGET_CI13XXX is not set
-# CONFIG_USB_GADGET_NET2280 is not set
-# CONFIG_USB_GADGET_GOKU is not set
-# CONFIG_USB_GADGET_LANGWELL is not set
-CONFIG_USB_GADGET_DWC_OTG=y
-CONFIG_USB_DWC_OTG=y
-# CONFIG_USB_GADGET_DUMMY_HCD is not set
-CONFIG_USB_GADGET_DUALSPEED=y
-# CONFIG_USB_ZERO is not set
-# CONFIG_USB_AUDIO is not set
-# CONFIG_USB_ETH is not set
-# CONFIG_USB_GADGETFS is not set
-# CONFIG_USB_FILE_STORAGE is not set
-# CONFIG_USB_G_SERIAL is not set
-# CONFIG_USB_MIDI_GADGET is not set
-# CONFIG_USB_G_PRINTER is not set
-CONFIG_USB_ANDROID=y
-# CONFIG_USB_ANDROID_ACM is not set
-CONFIG_USB_ANDROID_ADB=y
-CONFIG_USB_ANDROID_MASS_STORAGE=y
-# CONFIG_USB_ANDROID_RNDIS is not set
-# CONFIG_USB_CDC_COMPOSITE is not set
-
-#
-# OTG and related infrastructure
-#
-# CONFIG_USB_GPIO_VBUS is not set
-# CONFIG_NOP_USB_XCEIV is not set
-CONFIG_USB11_HOST=y
-CONFIG_USB11_HOST_EN=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_HOST_EN=y
-CONFIG_USB20_OTG=y
-# CONFIG_DWC_OTG_HOST_ONLY is not set
-CONFIG_DWC_OTG_DEVICE_ONLY=y
-CONFIG_DWC_CONN_EN=y
-# CONFIG_DWC_OTG_DEBUG is not set
-CONFIG_DWC_OTG=y
-CONFIG_MMC=y
-# CONFIG_MMC_DEBUG is not set
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-# CONFIG_MMC_PARANOID_SD_INIT is not set
-
-#
-# MMC/SD/SDIO Card Drivers
-#
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_BLOCK_BOUNCE=y
-CONFIG_MMC_BLOCK_DEFERRED_RESUME=y
-# CONFIG_SDIO_UART is not set
-# CONFIG_MMC_TEST is not set
-
-#
-# MMC/SD/SDIO Host Controller Drivers
-#
-CONFIG_SDMMC_RK29=y
-
-#
-# Now, there are two SDMMC controllers selected, SDMMC0 and SDMMC1.
-#
-CONFIG_SDMMC0_RK29=y
-# CONFIG_EMMC_RK29 is not set
-CONFIG_SDMMC1_RK29=y
-# CONFIG_MMC_SDHCI is not set
-# CONFIG_MMC_AT91 is not set
-# CONFIG_MMC_ATMELMCI is not set
-# CONFIG_MEMSTICK is not set
-# CONFIG_NEW_LEDS is not set
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-# CONFIG_ACCESSIBILITY is not set
-CONFIG_RTC_LIB=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HCTOSYS=y
-CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-# CONFIG_RTC_DEBUG is not set
-
-#
-# RTC interfaces
-#
-CONFIG_RTC_INTF_SYSFS=y
-CONFIG_RTC_INTF_PROC=y
-CONFIG_RTC_INTF_DEV=y
-# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-CONFIG_RTC_INTF_ALARM=y
-CONFIG_RTC_INTF_ALARM_DEV=y
-# CONFIG_RTC_DRV_TEST is not set
-
-#
-# I2C RTC drivers
-#
-# CONFIG_RTC_HYM8563 is not set
-# CONFIG_RTC_DRV_DS1307 is not set
-# CONFIG_RTC_DRV_DS1374 is not set
-# CONFIG_RTC_DRV_DS1672 is not set
-# CONFIG_RTC_DRV_MAX6900 is not set
-# CONFIG_RTC_DRV_RS5C372 is not set
-# CONFIG_RTC_DRV_ISL1208 is not set
-# CONFIG_RTC_DRV_X1205 is not set
-# CONFIG_RTC_DRV_PCF8563 is not set
-# CONFIG_RTC_DRV_PCF8583 is not set
-# CONFIG_RTC_DRV_M41T80 is not set
-CONFIG_RTC_DRV_TPS65910=y
-# CONFIG_RTC_DRV_S35390A is not set
-# CONFIG_RTC_DRV_S35392A is not set
-# CONFIG_RTC_DRV_FM3130 is not set
-# CONFIG_RTC_DRV_RX8581 is not set
-# CONFIG_RTC_DRV_RX8025 is not set
-
-#
-# SPI RTC drivers
-#
-
-#
-# Platform RTC drivers
-#
-# CONFIG_RTC_DRV_CMOS is not set
-# CONFIG_RTC_DRV_DS1286 is not set
-# CONFIG_RTC_DRV_DS1511 is not set
-# CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_DS1742 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
-# CONFIG_RTC_DRV_M48T86 is not set
-# CONFIG_RTC_DRV_M48T35 is not set
-# CONFIG_RTC_DRV_M48T59 is not set
-# CONFIG_RTC_DRV_BQ4802 is not set
-# CONFIG_RTC_DRV_V3020 is not set
-
-#
-# on-CPU RTC drivers
-#
-# CONFIG_DMADEVICES is not set
-# CONFIG_AUXDISPLAY is not set
-# CONFIG_UIO is not set
-
-#
-# TI VLYNQ
-#
-CONFIG_STAGING=y
-# CONFIG_STAGING_EXCLUDE_BUILD is not set
-# CONFIG_USB_IP_COMMON is not set
-# CONFIG_PRISM2_USB is not set
-# CONFIG_ECHO is not set
-# CONFIG_COMEDI is not set
-# CONFIG_ASUS_OLED is not set
-# CONFIG_TRANZPORT is not set
-
-#
-# Android
-#
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_RAM_CONSOLE=y
-CONFIG_ANDROID_RAM_CONSOLE_ENABLE_VERBOSE=y
-CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION=y
-CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_DATA_SIZE=128
-CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_ECC_SIZE=16
-CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_SYMBOL_SIZE=8
-CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_POLYNOMIAL=0x11d
-# CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT is not set
-CONFIG_ANDROID_TIMED_OUTPUT=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-
-#
-# Qualcomm MSM Camera And Video
-#
-
-#
-# Camera Sensor Selection
-#
-# CONFIG_DST is not set
-# CONFIG_POHMELFS is not set
-# CONFIG_PLAN9AUTH is not set
-# CONFIG_LINE6_USB is not set
-# CONFIG_USB_SERIAL_QUATECH2 is not set
-# CONFIG_USB_SERIAL_QUATECH_USB2 is not set
-# CONFIG_VT6656 is not set
-# CONFIG_FB_UDL is not set
-
-#
-# RAR Register Driver
-#
-# CONFIG_RAR_REGISTER is not set
-# CONFIG_IIO is not set
-
-#
-# DSP
-#
-# CONFIG_RK2818_DSP is not set
-
-#
-# RK1000 control
-#
-# CONFIG_RK1000_CONTROL is not set
-
-#
-# rk2818 POWER CONTROL
-#
-# CONFIG_RK2818_POWER is not set
-
-#
-# GPU Vivante
-#
-CONFIG_VIVANTE=y
-
-#
-# IPP
-#
-CONFIG_RK29_IPP=y
-
-#
-# CMMB
-#
-# CONFIG_CMMB is not set
-
-#
-# File systems
-#
-# CONFIG_EXT2_FS is not set
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
-CONFIG_EXT3_FS_XATTR=y
-# CONFIG_EXT3_FS_POSIX_ACL is not set
-# CONFIG_EXT3_FS_SECURITY is not set
-# CONFIG_EXT4_FS is not set
-CONFIG_JBD=y
-CONFIG_FS_MBCACHE=y
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
-# CONFIG_XFS_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_BTRFS_FS is not set
-# CONFIG_NILFS2_FS is not set
-CONFIG_FILE_LOCKING=y
-CONFIG_FSNOTIFY=y
-# CONFIG_DNOTIFY is not set
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-# CONFIG_FUSE_FS is not set
-
-#
-# Caches
-#
-# CONFIG_FSCACHE is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=y
-# CONFIG_MSDOS_FS is not set
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-# CONFIG_HUGETLB_PAGE is not set
-# CONFIG_CONFIGFS_FS is not set
-CONFIG_MISC_FILESYSTEMS=y
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-CONFIG_YAFFS_FS=y
-CONFIG_YAFFS_YAFFS1=y
-# CONFIG_YAFFS_9BYTE_TAGS is not set
-# CONFIG_YAFFS_DOES_ECC is not set
-CONFIG_YAFFS_YAFFS2=y
-CONFIG_YAFFS_AUTO_YAFFS2=y
-# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
-# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
-# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
-CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
-# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
-# CONFIG_JFFS2_FS is not set
-CONFIG_CRAMFS=y
-# CONFIG_SQUASHFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_OMFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-
-#
-# Partition Types
-#
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_MSDOS_PARTITION=y
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-1"
-CONFIG_NLS_CODEPAGE_437=y
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-CONFIG_NLS_CODEPAGE_850=y
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-CONFIG_NLS_CODEPAGE_936=y
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ASCII is not set
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-CONFIG_NLS_ISO8859_15=y
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-CONFIG_NLS_UTF8=y
-# CONFIG_DLM is not set
-
-#
-# Kernel hacking
-#
-CONFIG_PRINTK_TIME=y
-CONFIG_ENABLE_WARN_DEPRECATED=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_FRAME_WARN=1024
-CONFIG_MAGIC_SYSRQ=y
-# CONFIG_STRIP_ASM_SYMS is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-CONFIG_DETECT_HUNG_TASK=y
-# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
-CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
-CONFIG_SCHEDSTATS=y
-CONFIG_TIMER_STATS=y
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_KMEMLEAK is not set
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_PROVE_LOCKING is not set
-# CONFIG_LOCK_STAT is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_WRITECOUNT is not set
-# CONFIG_DEBUG_MEMORY_INIT is not set
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_DEBUG_NOTIFIERS is not set
-# CONFIG_DEBUG_CREDENTIALS is not set
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_RCU_TORTURE_TEST is not set
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_BACKTRACE_SELF_TEST is not set
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
-# CONFIG_FAULT_INJECTION is not set
-# CONFIG_LATENCYTOP is not set
-# CONFIG_PAGE_POISONING is not set
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_TRACING_SUPPORT=y
-# CONFIG_FTRACE is not set
-# CONFIG_SAMPLES is not set
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_KGDB is not set
-CONFIG_ARM_UNWIND=y
-# CONFIG_DEBUG_USER is not set
-CONFIG_DEBUG_ERRORS=y
-# CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_DEBUG_LL is not set
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-# CONFIG_SECURITYFS is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_ALGAPI2=y
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_BLKCIPHER=y
-CONFIG_CRYPTO_BLKCIPHER2=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_PCOMP=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-# CONFIG_CRYPTO_GF128MUL is not set
-# CONFIG_CRYPTO_NULL is not set
-CONFIG_CRYPTO_WORKQUEUE=y
-# CONFIG_CRYPTO_CRYPTD is not set
-# CONFIG_CRYPTO_AUTHENC is not set
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Authenticated Encryption with Associated Data
-#
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_SEQIV is not set
-
-#
-# Block modes
-#
-CONFIG_CRYPTO_CBC=y
-# CONFIG_CRYPTO_CTR is not set
-# CONFIG_CRYPTO_CTS is not set
-CONFIG_CRYPTO_ECB=y
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_PCBC is not set
-# CONFIG_CRYPTO_XTS is not set
-
-#
-# Hash modes
-#
-# CONFIG_CRYPTO_HMAC is not set
-# CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_VMAC is not set
-
-#
-# Digest
-#
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_GHASH is not set
-# CONFIG_CRYPTO_MD4 is not set
-CONFIG_CRYPTO_MD5=y
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_RMD128 is not set
-# CONFIG_CRYPTO_RMD160 is not set
-# CONFIG_CRYPTO_RMD256 is not set
-# CONFIG_CRYPTO_RMD320 is not set
-CONFIG_CRYPTO_SHA1=y
-# CONFIG_CRYPTO_SHA256 is not set
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_WP512 is not set
-
-#
-# Ciphers
-#
-# CONFIG_CRYPTO_AES is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-CONFIG_CRYPTO_ARC4=y
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-CONFIG_CRYPTO_DES=y
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_SALSA20 is not set
-# CONFIG_CRYPTO_SEED is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_TEA is not set
-CONFIG_CRYPTO_TWOFISH=y
-CONFIG_CRYPTO_TWOFISH_COMMON=y
-
-#
-# Compression
-#
-# CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_ZLIB is not set
-# CONFIG_CRYPTO_LZO is not set
-
-#
-# Random Number Generation
-#
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRYPTO_HW=y
-# CONFIG_BINARY_PRINTF is not set
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-CONFIG_GENERIC_FIND_LAST_BIT=y
-CONFIG_CRC_CCITT=y
-CONFIG_CRC16=y
-# CONFIG_CRC_T10DIF is not set
-# CONFIG_CRC_ITU_T is not set
-CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
-# CONFIG_LIBCRC32C is not set
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_REED_SOLOMON=y
-CONFIG_REED_SOLOMON_ENC8=y
-CONFIG_REED_SOLOMON_DEC8=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
-CONFIG_NLATTR=y
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-CONFIG_EMBEDDED=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_ARCH_RK29=y
-CONFIG_MACH_RK29_A22=y
-CONFIG_DDR_TYPE_LPDDR=y
-CONFIG_DDR_SDRAM_FREQ=198
-CONFIG_DDR_FREQ=y
-CONFIG_WIFI_CONTROL_FUNC=y
-CONFIG_RK29_WORKING_POWER_MANAGEMENT=y
-CONFIG_RK29_CLK_SWITCH_TO_32K=y
-CONFIG_RK29_GPIO_SUSPEND=y
-CONFIG_RK29_SPI_INSRAM=y
-CONFIG_ARM_THUMBEE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_STAT_DETAILS=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-CONFIG_NETFILTER_DEBUG=y
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_RFKILL=y
-# CONFIG_RFKILL_PM is not set
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_MTK23D=y
-CONFIG_RK29_GPS=y
-CONFIG_GPS_GNS7560=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_MII=y
-CONFIG_PHYLIB=y
-CONFIG_NET_ETHERNET=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_BCM4329=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_INPUT_POLLDEV=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ILI2102_IIC=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_INPUT_WM831X_ON=y
-CONFIG_MAG_SENSORS=y
-CONFIG_COMPASS_AK8975=y
-CONFIG_G_SENSOR_DEVICE=y
-CONFIG_GS_MMA8452=y
-# CONFIG_SERIO is not set
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-CONFIG_UART1_RK29=y
-CONFIG_UART2_RK29=y
-CONFIG_UART2_CTS_RTS_RK29=y
-CONFIG_UART3_RK29=y
-CONFIG_SERIAL_RK29_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_SPI=y
-CONFIG_SPIM_RK29=y
-CONFIG_SPIM0_RK29=y
-CONFIG_SPIM1_RK29=y
-CONFIG_ADC_RK29=y
-CONFIG_RK_HEADSET_DET=y
-CONFIG_GPIO_WM831X=y
-CONFIG_GPIO_WM8994=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_WM831X_BACKUP=y
-CONFIG_WM831X_POWER=y
-CONFIG_WM831X_CHARGER_DISPLAY=y
-CONFIG_WM831X_WITH_BATTERY=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_WM831X_SPI=y
-CONFIG_MFD_WM8994=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_REGULATOR_WM8994=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
-CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_MT9T111=y
-CONFIG_SOC_CAMERA_GC0309=y
-CONFIG_VIDEO_RK29=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_FB_RK29=y
-CONFIG_FB_WORK_IPP=y
-CONFIG_FB_ROTATE_VIDEO=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-# CONFIG_BACKLIGHT_RK29_BL is not set
-CONFIG_BACKLIGHT_AW9364=y
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_NT35510=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_LOGO_LINUX_CLUT224 is not set
-CONFIG_LOGO_CHARGER_CLUT224=y
-CONFIG_LOGO_G3_CLUT224=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-CONFIG_SND_VERBOSE_PRINTK=y
-CONFIG_SND_DEBUG=y
-CONFIG_SND_DEBUG_VERBOSE=y
-CONFIG_SND_PCM_XRUN_DEBUG=y
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-# CONFIG_SND_SPI is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_WM8994=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KYE=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LOGITECH=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_OTG=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_WM831X_STATUS=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_DEINTERLACE is not set
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_CRAMFS=y
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_CODEPAGE_936=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_15=y
-CONFIG_NLS_UTF8=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_SCHEDSTATS=y
-CONFIG_TIMER_STATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_FTRACE is not set
-CONFIG_CRYPTO_ARC4=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-CONFIG_EMBEDDED=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_ARCH_RK29=y
-CONFIG_MACH_RK29SDK_DDR3=y
-CONFIG_DDR_SDRAM_FREQ=456
-CONFIG_WIFI_CONTROL_FUNC=y
-CONFIG_RK29_JTAG=y
-CONFIG_ARM_THUMBEE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_STAT_DETAILS=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-CONFIG_NETFILTER_DEBUG=y
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_RFKILL=y
-# CONFIG_RFKILL_PM is not set
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_RK29_SUPPORT_MODEM=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_BCM4329=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-CONFIG_INPUT_POLLDEV=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_EETI_EGALAX=y
-CONFIG_EETI_EGALAX_MAX_X=1087
-CONFIG_EETI_EGALAX_MAX_Y=800
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_G_SENSOR_DEVICE=y
-CONFIG_GS_MMA8452=y
-# CONFIG_SERIO is not set
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-CONFIG_UART1_RK29=y
-CONFIG_UART2_RK29=y
-CONFIG_UART2_CTS_RTS_RK29=y
-CONFIG_SERIAL_RK29_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_ADC_RK29=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_BATTERY_BQ27510=y
-CONFIG_NO_BATTERY_IC=y
-# CONFIG_HWMON is not set
-CONFIG_REGULATOR=y
-CONFIG_RK29_PWM_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
-CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV2659=y
-CONFIG_SOC_CAMERA_OV5642=y
-CONFIG_VIDEO_RK29=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_FB_RK29=y
-CONFIG_CLOSE_WIN1_DYNAMIC=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_HSD100PXN=y
-CONFIG_HDMI=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_WM8900=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB11_HOST=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HYM8563=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_CRAMFS=y
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_CODEPAGE_936=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_15=y
-CONFIG_NLS_UTF8=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_SCHEDSTATS=y
-CONFIG_TIMER_STATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_FTRACE is not set
-CONFIG_CRYPTO_ARC4=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-CONFIG_EMBEDDED=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_ARCH_RK29=y
-CONFIG_MACH_RK29_K97=y
-CONFIG_RK29_MEM_SIZE_M=1024
-CONFIG_DDR_SDRAM_FREQ=400
-CONFIG_WIFI_CONTROL_FUNC=y
-CONFIG_RK29_JTAG=y
-CONFIG_ARM_THUMBEE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_STAT_DETAILS=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-CONFIG_NETFILTER_DEBUG=y
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_RFKILL=y
-# CONFIG_RFKILL_PM is not set
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_BCM4329=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-CONFIG_INPUT_POLLDEV=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GT8XX=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_G_SENSOR_DEVICE=y
-CONFIG_GS_MMA8452=y
-# CONFIG_SERIO is not set
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-CONFIG_UART1_RK29=y
-CONFIG_UART2_RK29=y
-CONFIG_UART2_CTS_RTS_RK29=y
-CONFIG_SERIAL_RK29_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_DEV_RK29=y
-CONFIG_ADC_RK29=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_BATTERY_RK29_ADC=y
-CONFIG_BATTERY_RK29_AC_CHARGE=y
-# CONFIG_HWMON is not set
-CONFIG_REGULATOR=y
-CONFIG_RK29_PWM_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
-CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV2655=y
-#CONFIG_SOC_CAMERA_OV2655_FRONT=y
-CONFIG_VIDEO_RK29=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_FB_RK29=y
-CONFIG_CLOSE_WIN1_DYNAMIC=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_LG_LP097X02=y
-CONFIG_HDMI=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_RT5631=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HYM8563=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_CRAMFS=y
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_CODEPAGE_936=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_15=y
-CONFIG_NLS_UTF8=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_SCHEDSTATS=y
-CONFIG_TIMER_STATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_FTRACE is not set
-CONFIG_CRYPTO_ARC4=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-CONFIG_EMBEDDED=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_ARCH_RK29=y
-CONFIG_MACH_RK29_PHONEPADSDK=y
-CONFIG_DDR_SDRAM_FREQ=456
-CONFIG_WIFI_CONTROL_FUNC=y
-CONFIG_RK29_JTAG=y
-CONFIG_ARM_THUMBEE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_STAT_DETAILS=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-CONFIG_NETFILTER_DEBUG=y
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_RFKILL=y
-# CONFIG_RFKILL_PM is not set
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_MU509=y
-CONFIG_MPU_SENSORS_TIMERIRQ=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_BCM4329=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-CONFIG_INPUT_POLLDEV=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_LAIBAO_TS=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_G_SENSOR_DEVICE=y
-# CONFIG_GS_MMA7660 is not set
-# CONFIG_SERIO is not set
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-CONFIG_UART1_RK29=y
-CONFIG_UART2_RK29=y
-CONFIG_UART2_CTS_RTS_RK29=y
-CONFIG_SERIAL_RK29_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_ADC_RK29=y
-CONFIG_RK_HEADSET_DET=y
-CONFIG_GPIO_WM8994=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_BATTERY_BQ27541=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_WM8994=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_WM8994=y
-CONFIG_RK29_PWM_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
-CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV2659=y
-CONFIG_SOC_CAMERA_OV5642=y
-CONFIG_VIDEO_RK29=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_FB_RK29=y
-CONFIG_CLOSE_WIN1_DYNAMIC=y
-CONFIG_FB_SCALING_OSD_1080P=y
-CONFIG_FB_ROTATE_VIDEO=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_HSD07PFW1=y
-CONFIG_HDMI=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_WM8994=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB11_HOST=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HYM8563=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_CRAMFS=y
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_CODEPAGE_936=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_15=y
-CONFIG_NLS_UTF8=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_SCHEDSTATS=y
-CONFIG_TIMER_STATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_FTRACE is not set
-CONFIG_CRYPTO_ARC4=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-#
-# Automatically generated make config: don't edit
-# Linux/arm 3.0.8 Kernel Configuration
-#
-CONFIG_ARM=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_HAVE_SCHED_CLOCK=y
-CONFIG_GENERIC_GPIO=y
-# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_KTIME_SCALAR=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-CONFIG_ARCH_HAS_CPUFREQ=y
-CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ZONE_DMA=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_VECTORS_BASE=0xffff0000
-# CONFIG_ARM_PATCH_PHYS_VIRT is not set
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-CONFIG_HAVE_IRQ_WORK=y
-
-#
-# General setup
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_CROSS_COMPILE=""
-CONFIG_LOCALVERSION=""
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_LZO=y
-# CONFIG_KERNEL_GZIP is not set
-# CONFIG_KERNEL_LZMA is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_DEFAULT_HOSTNAME="(none)"
-# CONFIG_SWAP is not set
-# CONFIG_SYSVIPC is not set
-# CONFIG_POSIX_MQUEUE is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_FHANDLE is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_AUDIT is not set
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-
-#
-# IRQ subsystem
-#
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_HAVE_SPARSE_IRQ=y
-CONFIG_GENERIC_IRQ_SHOW=y
-# CONFIG_SPARSE_IRQ is not set
-
-#
-# RCU Subsystem
-#
-CONFIG_TREE_PREEMPT_RCU=y
-# CONFIG_TINY_RCU is not set
-# CONFIG_TINY_PREEMPT_RCU is not set
-CONFIG_PREEMPT_RCU=y
-# CONFIG_RCU_TRACE is not set
-CONFIG_RCU_FANOUT=32
-# CONFIG_RCU_FANOUT_EXACT is not set
-# CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_RCU_BOOST is not set
-# CONFIG_IKCONFIG is not set
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-# CONFIG_CGROUP_DEVICE is not set
-# CONFIG_CPUSETS is not set
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-# CONFIG_CGROUP_MEM_RES_CTLR is not set
-CONFIG_CGROUP_SCHED=y
-CONFIG_FAIR_GROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-# CONFIG_BLK_CGROUP is not set
-# CONFIG_NAMESPACES is not set
-# CONFIG_SCHED_AUTOGROUP is not set
-# CONFIG_SYSFS_DEPRECATED is not set
-# CONFIG_RELAY is not set
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_RD_GZIP=y
-# CONFIG_RD_BZIP2 is not set
-# CONFIG_RD_LZMA is not set
-# CONFIG_RD_XZ is not set
-# CONFIG_RD_LZO is not set
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL=y
-CONFIG_ANON_INODES=y
-CONFIG_PANIC_TIMEOUT=5
-CONFIG_EXPERT=y
-CONFIG_UID16=y
-# CONFIG_SYSCTL_SYSCALL is not set
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-# CONFIG_ELF_CORE is not set
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_ASHMEM=y
-CONFIG_AIO=y
-CONFIG_EMBEDDED=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_PERF_USE_VMALLOC=y
-
-#
-# Kernel Performance Events And Counters
-#
-# CONFIG_PERF_EVENTS is not set
-# CONFIG_PERF_COUNTERS is not set
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_COMPAT_BRK=y
-CONFIG_SLAB=y
-# CONFIG_SLUB is not set
-# CONFIG_SLOB is not set
-# CONFIG_PROFILING is not set
-CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-
-#
-# GCOV-based kernel profiling
-#
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_SLABINFO=y
-CONFIG_RT_MUTEXES=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-# CONFIG_MODULE_FORCE_LOAD is not set
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_MODVERSIONS is not set
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_BLOCK=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_BLK_DEV_INTEGRITY is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_CFQ=y
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="cfq"
-# CONFIG_INLINE_SPIN_TRYLOCK is not set
-# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
-# CONFIG_INLINE_SPIN_LOCK is not set
-# CONFIG_INLINE_SPIN_LOCK_BH is not set
-# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
-# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
-# CONFIG_INLINE_SPIN_UNLOCK is not set
-# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
-# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
-# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
-# CONFIG_INLINE_READ_TRYLOCK is not set
-# CONFIG_INLINE_READ_LOCK is not set
-# CONFIG_INLINE_READ_LOCK_BH is not set
-# CONFIG_INLINE_READ_LOCK_IRQ is not set
-# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
-# CONFIG_INLINE_READ_UNLOCK is not set
-# CONFIG_INLINE_READ_UNLOCK_BH is not set
-# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
-# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
-# CONFIG_INLINE_WRITE_TRYLOCK is not set
-# CONFIG_INLINE_WRITE_LOCK is not set
-# CONFIG_INLINE_WRITE_LOCK_BH is not set
-# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
-# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
-# CONFIG_INLINE_WRITE_UNLOCK is not set
-# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
-# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
-# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
-# CONFIG_MUTEX_SPIN_ON_OWNER is not set
-CONFIG_FREEZER=y
-
-#
-# System Type
-#
-CONFIG_MMU=y
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_VEXPRESS is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_BCMRING is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_CNS3XXX is not set
-# CONFIG_ARCH_GEMINI is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_MXC is not set
-# CONFIG_ARCH_MXS is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP23XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_DOVE is not set
-# CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_LOKI is not set
-# CONFIG_ARCH_LPC32XX is not set
-# CONFIG_ARCH_MV78XX0 is not set
-# CONFIG_ARCH_ORION5X is not set
-# CONFIG_ARCH_MMP is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_W90X900 is not set
-# CONFIG_ARCH_NUC93X is not set
-# CONFIG_ARCH_TEGRA is not set
-# CONFIG_ARCH_PNX4008 is not set
-# CONFIG_ARCH_PXA is not set
-# CONFIG_ARCH_MSM is not set
-# CONFIG_ARCH_SHMOBILE is not set
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_S3C64XX is not set
-# CONFIG_ARCH_S5P64X0 is not set
-# CONFIG_ARCH_S5PC100 is not set
-# CONFIG_ARCH_S5PV210 is not set
-# CONFIG_ARCH_EXYNOS4 is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_TCC_926 is not set
-# CONFIG_ARCH_U300 is not set
-# CONFIG_ARCH_U8500 is not set
-# CONFIG_ARCH_NOMADIK is not set
-# CONFIG_ARCH_DAVINCI is not set
-# CONFIG_ARCH_OMAP is not set
-CONFIG_ARCH_RK29=y
-# CONFIG_PLAT_SPEAR is not set
-# CONFIG_ARCH_VT8500 is not set
-# CONFIG_GPIO_PCA953X is not set
-# CONFIG_KEYBOARD_GPIO_POLLED is not set
-# CONFIG_MACH_RK29SDK is not set
-# CONFIG_MACH_RK29SDK_DDR3 is not set
-# CONFIG_MACH_RK29_K97 is not set
-# CONFIG_MACH_RK29FIH is not set
-CONFIG_MACH_RK29_PHONESDK=y
-# CONFIG_MACH_RK29_A22 is not set
-# CONFIG_MACH_RK29_TD8801_V2 is not set
-# CONFIG_MACH_RK29_PHONEPADSDK is not set
-# CONFIG_MACH_RK29_newton is not set
-# CONFIG_MACH_RK29_PHONE_Z5 is not set
-# CONFIG_DDR_TYPE_DDRII is not set
-CONFIG_DDR_TYPE_LPDDR=y
-# CONFIG_DDR_TYPE_DDR3_800D is not set
-# CONFIG_DDR_TYPE_DDR3_800E is not set
-# CONFIG_DDR_TYPE_DDR3_1066E is not set
-# CONFIG_DDR_TYPE_DDR3_1066F is not set
-# CONFIG_DDR_TYPE_DDR3_1066G is not set
-# CONFIG_DDR_TYPE_DDR3_1333F is not set
-# CONFIG_DDR_TYPE_DDR3_1333G is not set
-# CONFIG_DDR_TYPE_DDR3_1333H is not set
-# CONFIG_DDR_TYPE_DDR3_1333J is not set
-# CONFIG_DDR_TYPE_DDR3_1600G is not set
-# CONFIG_DDR_TYPE_DDR3_1600H is not set
-# CONFIG_DDR_TYPE_DDR3_1600J is not set
-# CONFIG_DDR_TYPE_DDR3_1600K is not set
-# CONFIG_DDR_TYPE_DDR3_1866J is not set
-# CONFIG_DDR_TYPE_DDR3_1866K is not set
-# CONFIG_DDR_TYPE_DDR3_1866L is not set
-# CONFIG_DDR_TYPE_DDR3_1866M is not set
-# CONFIG_DDR_TYPE_DDR3_2133K is not set
-# CONFIG_DDR_TYPE_DDR3_2133L is not set
-# CONFIG_DDR_TYPE_DDR3_2133M is not set
-# CONFIG_DDR_TYPE_DDR3_2133N is not set
-# CONFIG_DDR_TYPE_DDR3_DEFAULT is not set
-CONFIG_RK29_MEM_SIZE_M=512
-CONFIG_DDR_SDRAM_FREQ=192
-CONFIG_DDR_FREQ=y
-# CONFIG_DDR_RECONFIG is not set
-CONFIG_WIFI_CONTROL_FUNC=y
-
-#
-# RK29 VPU (Video Processing Unit) support
-#
-CONFIG_RK29_VPU=y
-# CONFIG_RK29_VPU_DEBUG is not set
-CONFIG_RK29_JTAG=y
-CONFIG_RK29_LAST_LOG=y
-
-#
-# support for RK29 power manage
-#
-# CONFIG_RK29_WORKING_POWER_MANAGEMENT is not set
-CONFIG_RK29_CLK_SWITCH_TO_32K=y
-CONFIG_RK29_GPIO_SUSPEND=y
-# CONFIG_RK29_NEON_POWERDOMAIN_SET is not set
-CONFIG_RK29_SPI_INSRAM=y
-
-#
-# System MMU
-#
-
-#
-# Processor Type
-#
-CONFIG_CPU_V7=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_THUMBEE=y
-# CONFIG_SWP_EMULATE is not set
-# CONFIG_CPU_ICACHE_DISABLE is not set
-# CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_DMA_MEM_BUFFERABLE=y
-CONFIG_CPU_HAS_PMU=y
-# CONFIG_ARM_ERRATA_430973 is not set
-# CONFIG_ARM_ERRATA_458693 is not set
-# CONFIG_ARM_ERRATA_460075 is not set
-# CONFIG_ARM_ERRATA_743622 is not set
-# CONFIG_ARM_ERRATA_754322 is not set
-CONFIG_ARM_GIC=y
-CONFIG_PL330=y
-# CONFIG_FIQ_DEBUGGER is not set
-
-#
-# Bus support
-#
-# CONFIG_PCI_SYSCALL is not set
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-# CONFIG_PCCARD is not set
-
-#
-# Kernel Features
-#
-CONFIG_TICK_ONESHOT=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_VMSPLIT_3G=y
-# CONFIG_VMSPLIT_2G is not set
-# CONFIG_VMSPLIT_1G is not set
-CONFIG_PAGE_OFFSET=0xC0000000
-# CONFIG_PREEMPT_NONE is not set
-# CONFIG_PREEMPT_VOLUNTARY is not set
-CONFIG_PREEMPT=y
-CONFIG_HZ=100
-# CONFIG_THUMB2_KERNEL is not set
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HIGHMEM=y
-# CONFIG_HIGHPTE is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_SPLIT_PTLOCK_CPUS=4
-# CONFIG_COMPACTION is not set
-# CONFIG_PHYS_ADDR_T_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=1
-CONFIG_BOUNCE=y
-CONFIG_VIRT_TO_BUS=y
-# CONFIG_KSM is not set
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_NEED_PER_CPU_KM=y
-# CONFIG_CLEANCACHE is not set
-CONFIG_FORCE_MAX_ZONEORDER=11
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_UACCESS_WITH_MEMCPY is not set
-# CONFIG_SECCOMP is not set
-# CONFIG_CC_STACKPROTECTOR is not set
-# CONFIG_DEPRECATED_PARAM_STRUCT is not set
-# CONFIG_ARM_FLUSH_CONSOLE_ON_RESTART is not set
-
-#
-# Boot options
-#
-# CONFIG_USE_OF is not set
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_CMDLINE=""
-# CONFIG_XIP_KERNEL is not set
-CONFIG_KEXEC=y
-CONFIG_ATAGS_PROC=y
-# CONFIG_CRASH_DUMP is not set
-# CONFIG_AUTO_ZRELADDR is not set
-
-#
-# CPU Power Management
-#
-
-#
-# CPU Frequency scaling
-#
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_TABLE=y
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_FREQ_STAT_DETAILS=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE is not set
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-# CONFIG_CPU_FREQ_GOV_INTERACTIVE is not set
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-# CONFIG_CPU_IDLE is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_NEON=y
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-CONFIG_HAVE_AOUT=y
-# CONFIG_BINFMT_AOUT is not set
-# CONFIG_BINFMT_MISC is not set
-
-#
-# Power management options
-#
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_HAS_WAKELOCK=y
-CONFIG_HAS_EARLYSUSPEND=y
-CONFIG_WAKELOCK=y
-CONFIG_WAKELOCK_STAT=y
-CONFIG_USER_WAKELOCK=y
-CONFIG_EARLYSUSPEND=y
-# CONFIG_NO_USER_SPACE_SCREEN_ACCESS_CONTROL is not set
-# CONFIG_CONSOLE_EARLYSUSPEND is not set
-CONFIG_FB_EARLYSUSPEND=y
-CONFIG_PM_SLEEP=y
-# CONFIG_PM_RUNTIME is not set
-CONFIG_PM=y
-# CONFIG_PM_DEBUG is not set
-# CONFIG_APM_EMULATION is not set
-# CONFIG_SUSPEND_TIME is not set
-CONFIG_SUSPEND_SYNC_WORKQUEUE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
-# CONFIG_XFRM_STATISTICS is not set
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE_DEMUX is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=y
-CONFIG_INET_XFRM_MODE_TUNNEL=y
-CONFIG_INET_XFRM_MODE_BEET=y
-# CONFIG_INET_LRO is not set
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-# CONFIG_IPV6 is not set
-CONFIG_ANDROID_PARANOID_NETWORK=y
-CONFIG_NET_ACTIVITY_STATS=y
-# CONFIG_NETWORK_SECMARK is not set
-# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
-# CONFIG_NETFILTER is not set
-# CONFIG_IP_DCCP is not set
-# CONFIG_IP_SCTP is not set
-# CONFIG_RDS is not set
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_L2TP is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_NET_DSA is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-# CONFIG_PHONET is not set
-# CONFIG_IEEE802154 is not set
-# CONFIG_NET_SCHED is not set
-# CONFIG_DCB is not set
-# CONFIG_BATMAN_ADV is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_CAN is not set
-# CONFIG_IRDA is not set
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-# CONFIG_BT_BNEP_MC_FILTER is not set
-# CONFIG_BT_BNEP_PROTO_FILTER is not set
-CONFIG_BT_HIDP=y
-
-#
-# Bluetooth device drivers
-#
-# CONFIG_BT_HCIBTUSB is not set
-# CONFIG_BT_HCIBTSDIO is not set
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-# CONFIG_BT_HCIUART_BCSP is not set
-# CONFIG_BT_HCIUART_ATH3K is not set
-# CONFIG_BT_HCIUART_LL is not set
-# CONFIG_BT_HCIBCM203X is not set
-# CONFIG_BT_HCIBPA10X is not set
-# CONFIG_BT_HCIBFUSB is not set
-# CONFIG_BT_HCIVHCI is not set
-# CONFIG_BT_MRVL is not set
-CONFIG_BT_HCIBCM4325=y
-CONFIG_IDBLOCK=y
-# CONFIG_WIFI_MAC is not set
-# CONFIG_AF_RXRPC is not set
-CONFIG_WIRELESS=y
-CONFIG_WIRELESS_EXT=y
-CONFIG_WEXT_CORE=y
-CONFIG_WEXT_PROC=y
-CONFIG_WEXT_PRIV=y
-# CONFIG_CFG80211 is not set
-CONFIG_WIRELESS_EXT_SYSFS=y
-# CONFIG_LIB80211 is not set
-
-#
-# CFG80211 needs to be enabled for MAC80211
-#
-# CONFIG_WIMAX is not set
-CONFIG_RFKILL=y
-# CONFIG_RFKILL_PM is not set
-# CONFIG_RFKILL_INPUT is not set
-# CONFIG_RFKILL_REGULATOR is not set
-# CONFIG_RFKILL_GPIO is not set
-# CONFIG_NET_9P is not set
-# CONFIG_CAIF is not set
-# CONFIG_CEPH_LIB is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_CONNECTOR is not set
-CONFIG_MTD=y
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_TESTS is not set
-# CONFIG_MTD_REDBOOT_PARTS is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_AFS_PARTS is not set
-# CONFIG_MTD_AR7_PARTS is not set
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
-# CONFIG_INFTL is not set
-# CONFIG_RFD_FTL is not set
-# CONFIG_SSFDC is not set
-# CONFIG_SM_FTL is not set
-# CONFIG_MTD_OOPS is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-# CONFIG_MTD_CFI is not set
-# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_ABSENT is not set
-
-#
-# Mapping drivers for chip access
-#
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_PLATRAM is not set
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_DATAFLASH is not set
-# CONFIG_MTD_M25P80 is not set
-# CONFIG_MTD_SST25L is not set
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLOCK2MTD is not set
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-CONFIG_MTD_NAND_IDS=y
-# CONFIG_MTD_NAND is not set
-CONFIG_MTD_RKNAND=y
-CONFIG_MTD_NAND_RK29XX=y
-CONFIG_MTD_RKNAND_BUFFER=y
-# CONFIG_MTD_EMMC_CLK_POWER_SAVE is not set
-# CONFIG_MTD_NAND_RK29XX_DEBUG is not set
-# CONFIG_MTD_ONENAND is not set
-
-#
-# LPDDR flash memory drivers
-#
-# CONFIG_MTD_LPDDR is not set
-# CONFIG_MTD_UBI is not set
-# CONFIG_PARPORT is not set
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=y
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-
-#
-# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
-#
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_UB is not set
-# CONFIG_BLK_DEV_RAM is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-# CONFIG_MG_DISK is not set
-# CONFIG_BLK_DEV_RBD is not set
-# CONFIG_SENSORS_LIS3LV02D is not set
-CONFIG_MISC_DEVICES=y
-# CONFIG_AD525X_DPOT is not set
-CONFIG_ANDROID_PMEM=y
-# CONFIG_INTEL_MID_PTI is not set
-# CONFIG_ICS932S401 is not set
-# CONFIG_ENCLOSURE_SERVICES is not set
-# CONFIG_APDS9802ALS is not set
-# CONFIG_ISL29003 is not set
-# CONFIG_ISL29020 is not set
-# CONFIG_SENSORS_TSL2550 is not set
-# CONFIG_SENSORS_BH1780 is not set
-# CONFIG_SENSORS_BH1770 is not set
-# CONFIG_SENSORS_APDS990X is not set
-# CONFIG_HMC6352 is not set
-# CONFIG_SENSORS_AK8975 is not set
-# CONFIG_DS1682 is not set
-# CONFIG_TI_DAC7512 is not set
-# CONFIG_UID_STAT is not set
-# CONFIG_BMP085 is not set
-# CONFIG_WL127X_RFKILL is not set
-CONFIG_APANIC=y
-CONFIG_APANIC_PLABEL="kpanic"
-# CONFIG_STE is not set
-CONFIG_MTK23D=y
-# CONFIG_FM580X is not set
-# CONFIG_MU509 is not set
-# CONFIG_MW100 is not set
-# CONFIG_RK29_NEWTON is not set
-# CONFIG_RK29_SC8800 is not set
-# CONFIG_TDSC8800 is not set
-# CONFIG_C2PORT is not set
-
-#
-# EEPROM support
-#
-# CONFIG_EEPROM_AT24 is not set
-# CONFIG_EEPROM_AT25 is not set
-# CONFIG_EEPROM_LEGACY is not set
-# CONFIG_EEPROM_MAX6875 is not set
-# CONFIG_EEPROM_93CX6 is not set
-# CONFIG_RK29_SUPPORT_MODEM is not set
-CONFIG_RK29_GPS=y
-CONFIG_GPS_GNS7560=y
-CONFIG_MPU_SENSORS_TIMERIRQ=y
-CONFIG_INV_SENSORS=y
-CONFIG_MPU_SENSORS_MPU3050=y
-# CONFIG_MPU_SENSORS_MPU6050A2 is not set
-# CONFIG_MPU_SENSORS_MPU6050B1 is not set
-CONFIG_MPU_SENSORS_MPU3050_GYRO=y
-CONFIG_INV_SENSORS_ACCELEROMETERS=y
-# CONFIG_MPU_SENSORS_ADXL34X is not set
-# CONFIG_MPU_SENSORS_BMA222 is not set
-# CONFIG_MPU_SENSORS_BMA150 is not set
-# CONFIG_MPU_SENSORS_BMA250 is not set
-# CONFIG_MPU_SENSORS_KXSD9 is not set
-CONFIG_MPU_SENSORS_KXTF9=y
-# CONFIG_MPU_SENSORS_LIS331DLH is not set
-# CONFIG_MPU_SENSORS_LIS3DH is not set
-# CONFIG_MPU_SENSORS_LSM303DLX_A is not set
-# CONFIG_MPU_SENSORS_MMA8450 is not set
-# CONFIG_MPU_SENSORS_MMA845X is not set
-CONFIG_INV_SENSORS_COMPASS=y
-CONFIG_MPU_SENSORS_AK8975=y
-# CONFIG_MPU_SENSORS_AK8972 is not set
-# CONFIG_MPU_SENSORS_MMC314X is not set
-# CONFIG_MPU_SENSORS_AMI30X is not set
-# CONFIG_MPU_SENSORS_AMI306 is not set
-# CONFIG_MPU_SENSORS_HMC5883 is not set
-# CONFIG_MPU_SENSORS_LSM303DLX_M is not set
-# CONFIG_MPU_SENSORS_MMC314XMS is not set
-# CONFIG_MPU_SENSORS_YAS530 is not set
-# CONFIG_MPU_SENSORS_HSCDTD002B is not set
-# CONFIG_MPU_SENSORS_HSCDTD004A is not set
-# CONFIG_INV_SENSORS_PRESSURE is not set
-# CONFIG_MPU_USERSPACE_DEBUG is not set
-# CONFIG_IWMC3200TOP is not set
-
-#
-# Texas Instruments shared transport line discipline
-#
-# CONFIG_TI_ST is not set
-# CONFIG_SENSORS_LIS3_SPI is not set
-# CONFIG_SENSORS_LIS3_I2C is not set
-CONFIG_HAVE_IDE=y
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-CONFIG_SCSI_MOD=y
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_DMA=y
-# CONFIG_SCSI_TGT is not set
-# CONFIG_SCSI_NETLINK is not set
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=y
-# CONFIG_CHR_DEV_ST is not set
-# CONFIG_CHR_DEV_OSST is not set
-# CONFIG_BLK_DEV_SR is not set
-# CONFIG_CHR_DEV_SG is not set
-# CONFIG_CHR_DEV_SCH is not set
-CONFIG_SCSI_MULTI_LUN=y
-# CONFIG_SCSI_CONSTANTS is not set
-# CONFIG_SCSI_LOGGING is not set
-# CONFIG_SCSI_SCAN_ASYNC is not set
-CONFIG_SCSI_WAIT_SCAN=m
-
-#
-# SCSI Transports
-#
-# CONFIG_SCSI_SPI_ATTRS is not set
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
-# CONFIG_SCSI_SAS_LIBSAS is not set
-# CONFIG_SCSI_SRP_ATTRS is not set
-CONFIG_SCSI_LOWLEVEL=y
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_ISCSI_BOOT_SYSFS is not set
-# CONFIG_LIBFC is not set
-# CONFIG_LIBFCOE is not set
-# CONFIG_SCSI_DEBUG is not set
-# CONFIG_SCSI_DH is not set
-# CONFIG_SCSI_OSD_INITIATOR is not set
-# CONFIG_ATA is not set
-CONFIG_MD=y
-# CONFIG_BLK_DEV_MD is not set
-CONFIG_BLK_DEV_DM=y
-# CONFIG_DM_DEBUG is not set
-CONFIG_DM_CRYPT=y
-# CONFIG_DM_SNAPSHOT is not set
-# CONFIG_DM_MIRROR is not set
-# CONFIG_DM_RAID is not set
-# CONFIG_DM_ZERO is not set
-# CONFIG_DM_MULTIPATH is not set
-# CONFIG_DM_DELAY is not set
-CONFIG_DM_UEVENT=y
-# CONFIG_DM_FLAKEY is not set
-# CONFIG_TARGET_CORE is not set
-CONFIG_NETDEVICES=y
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_MACVLAN is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_VETH is not set
-CONFIG_MII=y
-CONFIG_PHYLIB=y
-
-#
-# MII PHY device drivers
-#
-# CONFIG_MARVELL_PHY is not set
-# CONFIG_DAVICOM_PHY is not set
-# CONFIG_QSEMI_PHY is not set
-# CONFIG_LXT_PHY is not set
-# CONFIG_CICADA_PHY is not set
-# CONFIG_VITESSE_PHY is not set
-# CONFIG_SMSC_PHY is not set
-# CONFIG_BROADCOM_PHY is not set
-# CONFIG_ICPLUS_PHY is not set
-# CONFIG_REALTEK_PHY is not set
-# CONFIG_NATIONAL_PHY is not set
-# CONFIG_STE10XP is not set
-# CONFIG_LSI_ET1011C_PHY is not set
-# CONFIG_MICREL_PHY is not set
-# CONFIG_FIXED_PHY is not set
-# CONFIG_MDIO_BITBANG is not set
-CONFIG_NET_ETHERNET=y
-# CONFIG_AX88796 is not set
-# CONFIG_RK29_VMAC is not set
-# CONFIG_SMC91X is not set
-# CONFIG_DM9000 is not set
-# CONFIG_ENC28J60 is not set
-# CONFIG_ETHOC is not set
-# CONFIG_SMC911X is not set
-# CONFIG_SMSC911X is not set
-# CONFIG_DNET is not set
-# CONFIG_IBM_NEW_EMAC_ZMII is not set
-# CONFIG_IBM_NEW_EMAC_RGMII is not set
-# CONFIG_IBM_NEW_EMAC_TAH is not set
-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
-# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
-# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
-# CONFIG_B44 is not set
-# CONFIG_KS8851 is not set
-# CONFIG_KS8851_MLL is not set
-# CONFIG_FTMAC100 is not set
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN=y
-CONFIG_WLAN_80211=y
-# CONFIG_WIFI_NONE is not set
-CONFIG_BCM4329=y
-# CONFIG_BCM4319 is not set
-# CONFIG_MV8686 is not set
-# CONFIG_AR6003 is not set
-
-#
-# Enable WiMAX (Networking options) to see the WiMAX drivers
-#
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET is not set
-# CONFIG_USB_HSO is not set
-# CONFIG_USB_IPHETH is not set
-# CONFIG_WAN is not set
-
-#
-# CAIF transport drivers
-#
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-# CONFIG_PPP_MPPE is not set
-# CONFIG_PPPOE is not set
-# CONFIG_PPPOLAC is not set
-# CONFIG_PPPOPNS is not set
-# CONFIG_SLIP is not set
-CONFIG_SLHC=y
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_ISDN is not set
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-CONFIG_INPUT_POLLDEV=y
-# CONFIG_INPUT_SPARSEKMAP is not set
-
-#
-# Userland interfaces
-#
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_JOYDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_EVBUG is not set
-CONFIG_INPUT_KEYRESET=y
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYS_RK29=y
-# CONFIG_KEYS_RK29_NEWTON is not set
-# CONFIG_SYNAPTICS_SO340010 is not set
-# CONFIG_KEYBOARD_ADP5588 is not set
-# CONFIG_KEYBOARD_ADP5589 is not set
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_KEYBOARD_QT1070 is not set
-# CONFIG_KEYBOARD_QT2160 is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_GPIO is not set
-# CONFIG_KEYBOARD_WM831X_GPIO is not set
-# CONFIG_KEYBOARD_TCA6416 is not set
-# CONFIG_KEYBOARD_MATRIX is not set
-# CONFIG_KEYBOARD_MAX7359 is not set
-# CONFIG_KEYBOARD_MCS is not set
-# CONFIG_KEYBOARD_MPR121 is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_OPENCORES is not set
-# CONFIG_KEYBOARD_STOWAWAY is not set
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-# CONFIG_TOUCHSCREEN_XPT2046_SPI is not set
-# CONFIG_TOUCHSCREEN_ADS7846 is not set
-# CONFIG_TOUCHSCREEN_AD7877 is not set
-# CONFIG_TOUCHSCREEN_ILI2102_IIC is not set
-# CONFIG_TOUCHSCREEN_GT8XX is not set
-# CONFIG_TOUCHSCREEN_IT7250 is not set
-# CONFIG_TOUCHSCREEN_AD7879 is not set
-# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
-# CONFIG_TOUCHSCREEN_BU21013 is not set
-# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
-# CONFIG_TOUCHSCREEN_DYNAPRO is not set
-# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
-# CONFIG_TOUCHSCREEN_EETI is not set
-# CONFIG_TOUCHSCREEN_FUJITSU is not set
-# CONFIG_TOUCHSCREEN_GUNZE is not set
-# CONFIG_TOUCHSCREEN_ELO is not set
-# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
-# CONFIG_TOUCHSCREEN_MAX11801 is not set
-# CONFIG_TOUCHSCREEN_MCS5000 is not set
-# CONFIG_TOUCHSCREEN_MTOUCH is not set
-# CONFIG_TOUCHSCREEN_INEXIO is not set
-# CONFIG_TOUCHSCREEN_MK712 is not set
-# CONFIG_TOUCHSCREEN_PENMOUNT is not set
-# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI is not set
-# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
-# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-# CONFIG_TOUCHSCREEN_WM831X is not set
-# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
-# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
-# CONFIG_TOUCHSCREEN_TSC2005 is not set
-# CONFIG_TOUCHSCREEN_TSC2007 is not set
-# CONFIG_TOUCHSCREEN_W90X900 is not set
-# CONFIG_TOUCHSCREEN_ST1232 is not set
-# CONFIG_TOUCHSCREEN_TPS6507X is not set
-# CONFIG_HANNSTAR_P1003 is not set
-# CONFIG_ATMEL_MXT224 is not set
-# CONFIG_SINTEK_3FA16 is not set
-# CONFIG_EETI_EGALAX is not set
-# CONFIG_TOUCHSCREEN_IT7260 is not set
-# CONFIG_TOUCHSCREEN_IT7260_I2C is not set
-# CONFIG_TOUCHSCREEN_NAS is not set
-# CONFIG_LAIBAO_TS is not set
-# CONFIG_TOUCHSCREEN_GT801_IIC is not set
-CONFIG_TOUCHSCREEN_GT818_IIC=y
-# CONFIG_TOUCHSCREEN_PIXCIR is not set
-# CONFIG_D70_L3188A is not set
-# CONFIG_TOUCHSCREEN_GT819 is not set
-# CONFIG_TOUCHSCREEN_FT5306 is not set
-# CONFIG_TOUCHSCREEN_FT5406 is not set
-# CONFIG_ATMEL_MXT1386 is not set
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_LPSENSOR_ISL29028=y
-# CONFIG_INPUT_LPSENSOR_CM3602 is not set
-# CONFIG_INPUT_LPSENSOR_AL3006 is not set
-# CONFIG_INPUT_AD714X is not set
-# CONFIG_INPUT_ATI_REMOTE is not set
-# CONFIG_INPUT_ATI_REMOTE2 is not set
-# CONFIG_INPUT_KEYCHORD is not set
-# CONFIG_INPUT_KEYSPAN_REMOTE is not set
-# CONFIG_INPUT_POWERMATE is not set
-# CONFIG_INPUT_YEALINK is not set
-# CONFIG_INPUT_CM109 is not set
-CONFIG_INPUT_UINPUT=y
-# CONFIG_INPUT_GPIO is not set
-# CONFIG_INPUT_PCF8574 is not set
-# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
-CONFIG_INPUT_WM831X_ON=y
-# CONFIG_INPUT_ADXL34X is not set
-# CONFIG_INPUT_CMA3000 is not set
-# CONFIG_MAG_SENSORS is not set
-CONFIG_G_SENSOR_DEVICE=y
-# CONFIG_GS_MMA7660 is not set
-# CONFIG_GS_MMA8452 is not set
-# CONFIG_GS_KXTF9 is not set
-# CONFIG_GS_LIS3DH is not set
-# CONFIG_GS_L3G4200D is not set
-# CONFIG_GS_BMA023 is not set
-# CONFIG_GYRO_SENSOR_DEVICE is not set
-# CONFIG_INPUT_JOGBALL is not set
-# CONFIG_LIGHT_SENSOR_DEVICE is not set
-
-#
-# Hardware I/O ports
-#
-# CONFIG_SERIO is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_UNIX98_PTYS=y
-# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_SERIAL_NONSTANDARD is not set
-# CONFIG_N_GSM is not set
-# CONFIG_TRACE_SINK is not set
-CONFIG_DEVMEM=y
-CONFIG_DEVKMEM=y
-
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-
-#
-# Non-8250 serial port support
-#
-# CONFIG_SERIAL_MAX3100 is not set
-# CONFIG_SERIAL_MAX3107 is not set
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-# CONFIG_SERIAL_TIMBERDALE is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-# CONFIG_UART0_DMA_RK29 is not set
-CONFIG_UART1_RK29=y
-CONFIG_UART2_RK29=y
-CONFIG_UART2_CTS_RTS_RK29=y
-# CONFIG_UART2_DMA_RK29 is not set
-CONFIG_UART3_RK29=y
-# CONFIG_UART3_CTS_RTS_RK29 is not set
-# CONFIG_UART3_DMA_RK29 is not set
-CONFIG_SERIAL_RK29_CONSOLE=y
-# CONFIG_SERIAL_SC8800 is not set
-# CONFIG_SERIAL_ALTERA_JTAGUART is not set
-# CONFIG_SERIAL_ALTERA_UART is not set
-# CONFIG_SERIAL_IFX6X60 is not set
-# CONFIG_SERIAL_XILINX_PS_UART is not set
-# CONFIG_TTY_PRINTK is not set
-# CONFIG_HVC_DCC is not set
-# CONFIG_IPMI_HANDLER is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_R3964 is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_TCG_TPM is not set
-# CONFIG_DCC_TTY is not set
-# CONFIG_RAMOOPS is not set
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_COMPAT=y
-# CONFIG_I2C_CHARDEV is not set
-# CONFIG_I2C_MUX is not set
-CONFIG_I2C_HELPER_AUTO=y
-
-#
-# I2C Hardware Bus support
-#
-
-#
-# I2C system bus drivers (mostly embedded / system-on-chip)
-#
-# CONFIG_I2C_DESIGNWARE is not set
-# CONFIG_I2C_GPIO is not set
-# CONFIG_I2C_OCORES is not set
-# CONFIG_I2C_PCA_PLATFORM is not set
-# CONFIG_I2C_PXA_PCI is not set
-# CONFIG_I2C_SIMTEC is not set
-# CONFIG_I2C_XILINX is not set
-
-#
-# External I2C/SMBus adapter drivers
-#
-# CONFIG_I2C_DIOLAN_U2C is not set
-# CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_TAOS_EVM is not set
-# CONFIG_I2C_TINY_USB is not set
-
-#
-# Other I2C/SMBus bus drivers
-#
-# CONFIG_I2C_STUB is not set
-CONFIG_I2C_RK29=y
-
-#
-# Now, there are four I2C interfaces selected by developer.
-#
-CONFIG_I2C0_RK29=y
-CONFIG_RK29_I2C0_CONTROLLER=y
-# CONFIG_RK29_I2C0_GPIO is not set
-CONFIG_I2C1_RK29=y
-CONFIG_RK29_I2C1_CONTROLLER=y
-# CONFIG_RK29_I2C1_GPIO is not set
-CONFIG_I2C2_RK29=y
-CONFIG_RK29_I2C2_CONTROLLER=y
-# CONFIG_RK29_I2C2_GPIO is not set
-CONFIG_I2C3_RK29=y
-CONFIG_RK29_I2C3_CONTROLLER=y
-# CONFIG_RK29_I2C3_GPIO is not set
-# CONFIG_I2C_DEV_RK29 is not set
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-CONFIG_SPI=y
-# CONFIG_SPI_DEBUG is not set
-CONFIG_SPI_MASTER=y
-
-#
-# SPI Master Controller Drivers
-#
-# CONFIG_SPI_ALTERA is not set
-# CONFIG_SPI_BITBANG is not set
-# CONFIG_SPI_GPIO is not set
-# CONFIG_SPI_OC_TINY is not set
-# CONFIG_SPI_PXA2XX_PCI is not set
-# CONFIG_SPI_XILINX is not set
-CONFIG_SPIM_RK29=y
-CONFIG_SPIM0_RK29=y
-CONFIG_SPIM1_RK29=y
-CONFIG_LCD_USE_SPIM_CONTROL=y
-# CONFIG_LCD_USE_SPI0 is not set
-CONFIG_LCD_USE_SPI1=y
-# CONFIG_SPI_DESIGNWARE is not set
-
-#
-# SPI Protocol Masters
-#
-# CONFIG_SPI_SPIDEV is not set
-# CONFIG_SPI_TLE62X0 is not set
-CONFIG_ADC=y
-# CONFIG_ADC_RK28 is not set
-CONFIG_ADC_RK29=y
-
-#
-# Headset device support
-#
-CONFIG_RK_HEADSET_DET=y
-
-#
-# PPS support
-#
-# CONFIG_PPS is not set
-
-#
-# PPS generators support
-#
-
-#
-# PTP clock support
-#
-
-#
-# Enable Device Drivers -> PPS to see the PTP clock options.
-#
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_GPIOLIB=y
-# CONFIG_DEBUG_GPIO is not set
-# CONFIG_GPIO_SYSFS is not set
-
-#
-# Memory mapped GPIO drivers:
-#
-# CONFIG_GPIO_BASIC_MMIO is not set
-# CONFIG_GPIO_IT8761E is not set
-
-#
-# I2C GPIO expanders:
-#
-# CONFIG_GPIO_MAX7300 is not set
-# CONFIG_GPIO_MAX732X is not set
-# CONFIG_GPIO_PCF857X is not set
-# CONFIG_GPIO_SX150X is not set
-CONFIG_GPIO_WM831X=y
-CONFIG_GPIO_WM8994=y
-# CONFIG_GPIO_ADP5588 is not set
-
-#
-# PCI GPIO expanders:
-#
-
-#
-# SPI GPIO expanders:
-#
-# CONFIG_GPIO_MAX7301 is not set
-# CONFIG_GPIO_MCP23S08 is not set
-# CONFIG_GPIO_MC33880 is not set
-# CONFIG_GPIO_74X164 is not set
-
-#
-# AC97 GPIO expanders:
-#
-# CONFIG_GPIO_PCA9554 is not set
-# CONFIG_IOEXTEND_TCA6424 is not set
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-# CONFIG_EXPAND_GPIO_SOFT_INTERRUPT is not set
-CONFIG_SPI_FPGA_GPIO_NUM=96
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=16
-
-#
-# MODULbus GPIO expanders:
-#
-# CONFIG_W1 is not set
-CONFIG_POWER_SUPPLY=y
-# CONFIG_POWER_SUPPLY_DEBUG is not set
-# CONFIG_PDA_POWER is not set
-CONFIG_WM831X_BACKUP=y
-CONFIG_WM831X_POWER=y
-# CONFIG_WM831X_CHARGER_DISPLAY is not set
-# CONFIG_WM831X_WITH_BATTERY is not set
-# CONFIG_TEST_POWER is not set
-# CONFIG_BATTERY_DS2780 is not set
-# CONFIG_BATTERY_DS2782 is not set
-# CONFIG_BATTERY_BQ20Z75 is not set
-# CONFIG_BATTERY_BQ27x00 is not set
-# CONFIG_BATTERY_MAX17040 is not set
-# CONFIG_BATTERY_MAX17042 is not set
-# CONFIG_BATTERY_STC3100 is not set
-# CONFIG_BATTERY_BQ27510 is not set
-# CONFIG_BATTERY_BQ27541 is not set
-# CONFIG_BATTERY_BQ3060 is not set
-# CONFIG_CHARGER_MAX8903 is not set
-# CONFIG_CHARGER_GPIO is not set
-# CONFIG_BATTERY_RK29_ADC is not set
-CONFIG_POWER_ON_CHARGER_DISPLAY=y
-# CONFIG_HWMON is not set
-# CONFIG_THERMAL is not set
-# CONFIG_WATCHDOG is not set
-CONFIG_SSB_POSSIBLE=y
-
-#
-# Sonics Silicon Backplane
-#
-# CONFIG_SSB is not set
-CONFIG_BCMA_POSSIBLE=y
-
-#
-# Broadcom specific AMBA
-#
-# CONFIG_BCMA is not set
-CONFIG_MFD_SUPPORT=y
-CONFIG_MFD_CORE=y
-# CONFIG_MFD_88PM860X is not set
-# CONFIG_MFD_SM501 is not set
-# CONFIG_MFD_ASIC3 is not set
-# CONFIG_HTC_EGPIO is not set
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_HTC_I2CPLD is not set
-# CONFIG_TPS6105X is not set
-# CONFIG_TPS65010 is not set
-# CONFIG_TPS6507X is not set
-# CONFIG_MFD_TPS6586X is not set
-# CONFIG_TWL4030_CORE is not set
-# CONFIG_MFD_STMPE is not set
-# CONFIG_MFD_TC3589X is not set
-# CONFIG_MFD_TMIO is not set
-# CONFIG_MFD_T7L66XB is not set
-# CONFIG_MFD_TC6387XB is not set
-# CONFIG_MFD_TC6393XB is not set
-# CONFIG_PMIC_DA903X is not set
-# CONFIG_PMIC_ADP5520 is not set
-# CONFIG_MFD_MAX8925 is not set
-# CONFIG_MFD_MAX8997 is not set
-# CONFIG_MFD_MAX8998 is not set
-# CONFIG_MFD_WM8400 is not set
-CONFIG_MFD_WM831X=y
-# CONFIG_MFD_WM831X_I2C is not set
-CONFIG_MFD_WM831X_SPI=y
-# CONFIG_MFD_WM831X_SPI_A22 is not set
-# CONFIG_MFD_WM8350_I2C is not set
-CONFIG_MFD_WM8994=y
-# CONFIG_MFD_PCF50633 is not set
-# CONFIG_MFD_MC13XXX is not set
-# CONFIG_ABX500_CORE is not set
-# CONFIG_EZX_PCAP is not set
-# CONFIG_MFD_WL1273_CORE is not set
-# CONFIG_MFD_TPS65910 is not set
-CONFIG_REGULATOR=y
-# CONFIG_REGULATOR_DEBUG is not set
-# CONFIG_REGULATOR_DUMMY is not set
-# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
-# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
-# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
-# CONFIG_REGULATOR_BQ24022 is not set
-# CONFIG_REGULATOR_MAX1586 is not set
-# CONFIG_REGULATOR_MAX8649 is not set
-# CONFIG_REGULATOR_MAX8660 is not set
-# CONFIG_REGULATOR_MAX8952 is not set
-CONFIG_REGULATOR_WM831X=y
-CONFIG_REGULATOR_WM8994=y
-# CONFIG_REGULATOR_LP3971 is not set
-# CONFIG_REGULATOR_LP3972 is not set
-# CONFIG_REGULATOR_TPS65023 is not set
-# CONFIG_REGULATOR_TPS6507X is not set
-# CONFIG_RK2818_REGULATOR_CHARGE is not set
-# CONFIG_RK2818_REGULATOR_LP8725 is not set
-# CONFIG_REGULATOR_ACT8891 is not set
-# CONFIG_RK29_PWM_REGULATOR is not set
-# CONFIG_REGULATOR_ISL6271A is not set
-# CONFIG_REGULATOR_AD5398 is not set
-# CONFIG_REGULATOR_TPS6524X is not set
-CONFIG_MEDIA_SUPPORT=y
-
-#
-# Multimedia core support
-#
-# CONFIG_MEDIA_CONTROLLER is not set
-CONFIG_VIDEO_DEV=y
-CONFIG_VIDEO_V4L2_COMMON=y
-# CONFIG_DVB_CORE is not set
-CONFIG_VIDEO_MEDIA=y
-
-#
-# Multimedia drivers
-#
-CONFIG_RC_CORE=y
-CONFIG_LIRC=y
-CONFIG_RC_MAP=y
-CONFIG_IR_NEC_DECODER=y
-CONFIG_IR_RC5_DECODER=y
-CONFIG_IR_RC6_DECODER=y
-CONFIG_IR_JVC_DECODER=y
-CONFIG_IR_SONY_DECODER=y
-CONFIG_IR_RC5_SZ_DECODER=y
-CONFIG_IR_LIRC_CODEC=y
-# CONFIG_IR_IMON is not set
-# CONFIG_IR_MCEUSB is not set
-# CONFIG_IR_REDRAT3 is not set
-# CONFIG_IR_STREAMZAP is not set
-# CONFIG_RC_LOOPBACK is not set
-# CONFIG_MEDIA_ATTACH is not set
-CONFIG_MEDIA_TUNER=y
-# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
-CONFIG_MEDIA_TUNER_SIMPLE=y
-CONFIG_MEDIA_TUNER_TDA8290=y
-CONFIG_MEDIA_TUNER_TDA827X=y
-CONFIG_MEDIA_TUNER_TDA18271=y
-CONFIG_MEDIA_TUNER_TDA9887=y
-CONFIG_MEDIA_TUNER_TEA5761=y
-CONFIG_MEDIA_TUNER_TEA5767=y
-CONFIG_MEDIA_TUNER_MT20XX=y
-CONFIG_MEDIA_TUNER_XC2028=y
-CONFIG_MEDIA_TUNER_XC5000=y
-CONFIG_MEDIA_TUNER_MC44S803=y
-CONFIG_VIDEO_V4L2=y
-CONFIG_VIDEOBUF_GEN=y
-CONFIG_VIDEOBUF_DMA_CONTIG=y
-CONFIG_VIDEOBUF2_CORE=y
-# CONFIG_VIDEO_RK29XX_VOUT is not set
-CONFIG_VIDEO_CAPTURE_DRIVERS=y
-# CONFIG_VIDEO_ADV_DEBUG is not set
-# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
-CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
-CONFIG_VIDEO_IR_I2C=y
-
-#
-# Audio decoders, processors and mixers
-#
-
-#
-# RDS decoders
-#
-
-#
-# Video decoders
-#
-
-#
-# Video and audio decoders
-#
-
-#
-# MPEG video encoders
-#
-
-#
-# Video encoders
-#
-
-#
-# Camera sensor devices
-#
-
-#
-# Video improvement chips
-#
-
-#
-# Miscelaneous helper chips
-#
-# CONFIG_VIDEO_CPIA2 is not set
-# CONFIG_VIDEO_SR030PC30 is not set
-# CONFIG_VIDEO_NOON010PC30 is not set
-CONFIG_SOC_CAMERA=y
-# CONFIG_SOC_CAMERA_IMX074 is not set
-# CONFIG_SOC_CAMERA_MT9M001 is not set
-# CONFIG_SOC_CAMERA_MT9M111 is not set
-# CONFIG_SOC_CAMERA_MT9M112 is not set
-# CONFIG_SOC_CAMERA_MT9T031 is not set
-# CONFIG_SOC_CAMERA_MT9T111 is not set
-# CONFIG_SOC_CAMERA_MT9P111 is not set
-# CONFIG_SOC_CAMERA_MT9D112 is not set
-# CONFIG_SOC_CAMERA_MT9D113 is not set
-# CONFIG_SOC_CAMERA_MT9T112 is not set
-# CONFIG_SOC_CAMERA_MT9V022 is not set
-# CONFIG_SOC_CAMERA_RJ54N1 is not set
-# CONFIG_SOC_CAMERA_TW9910 is not set
-# CONFIG_SOC_CAMERA_PLATFORM is not set
-# CONFIG_SOC_CAMERA_OV2640 is not set
-# CONFIG_SOC_CAMERA_OV6650 is not set
-# CONFIG_SOC_CAMERA_OV772X is not set
-# CONFIG_SOC_CAMERA_OV7675 is not set
-# CONFIG_SOC_CAMERA_OV2655 is not set
-CONFIG_SOC_CAMERA_OV2659=y
-# CONFIG_SOC_CAMERA_OV7690 is not set
-# CONFIG_SOC_CAMERA_OV9650 is not set
-# CONFIG_SOC_CAMERA_OV3640 is not set
-CONFIG_SOC_CAMERA_OV5642=y
-CONFIG_OV5642_AUTOFOCUS=y
-# CONFIG_OV5642_FIXEDFOCUS is not set
-# CONFIG_SOC_CAMERA_OV5640 is not set
-# CONFIG_SOC_CAMERA_OV5640_FOR_TD8801 is not set
-# CONFIG_SOC_CAMERA_S5K6AA is not set
-# CONFIG_SOC_CAMERA_GT2005 is not set
-# CONFIG_SOC_CAMERA_GC0307 is not set
-# CONFIG_SOC_CAMERA_GC0308 is not set
-# CONFIG_SOC_CAMERA_GC0309 is not set
-# CONFIG_SOC_CAMERA_GC0309_FOR_TD8801 is not set
-# CONFIG_SOC_CAMERA_GC2015 is not set
-# CONFIG_SOC_CAMERA_HI253 is not set
-# CONFIG_SOC_CAMERA_HI704 is not set
-# CONFIG_SOC_CAMERA_SIV120B is not set
-# CONFIG_SOC_CAMERA_SID130B is not set
-# CONFIG_SOC_CAMERA_NT99250 is not set
-# CONFIG_SOC_CAMERA_OV9640 is not set
-# CONFIG_SOC_CAMERA_OV9740 is not set
-# CONFIG_VIDEO_SH_MOBILE_CSI2 is not set
-# CONFIG_VIDEO_SH_MOBILE_CEU is not set
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_WORK_ONEFRAME=y
-# CONFIG_VIDEO_RK29_WORK_PINGPONG is not set
-CONFIG_VIDEO_RK29_WORK_IPP=y
-# CONFIG_VIDEO_RK29_WORK_NOT_IPP is not set
-CONFIG_VIDEO_RK29_DIGITALZOOM_IPP_ON=y
-# CONFIG_VIDEO_RK29_DIGITALZOOM_IPP_OFF is not set
-CONFIG_V4L_USB_DRIVERS=y
-# CONFIG_USB_VIDEO_CLASS is not set
-CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
-CONFIG_USB_GSPCA=m
-# CONFIG_USB_M5602 is not set
-# CONFIG_USB_STV06XX is not set
-# CONFIG_USB_GL860 is not set
-# CONFIG_USB_GSPCA_BENQ is not set
-# CONFIG_USB_GSPCA_CONEX is not set
-# CONFIG_USB_GSPCA_CPIA1 is not set
-# CONFIG_USB_GSPCA_ETOMS is not set
-# CONFIG_USB_GSPCA_FINEPIX is not set
-# CONFIG_USB_GSPCA_JEILINJ is not set
-# CONFIG_USB_GSPCA_KINECT is not set
-# CONFIG_USB_GSPCA_KONICA is not set
-# CONFIG_USB_GSPCA_MARS is not set
-# CONFIG_USB_GSPCA_MR97310A is not set
-# CONFIG_USB_GSPCA_NW80X is not set
-# CONFIG_USB_GSPCA_OV519 is not set
-# CONFIG_USB_GSPCA_OV534 is not set
-# CONFIG_USB_GSPCA_OV534_9 is not set
-# CONFIG_USB_GSPCA_PAC207 is not set
-# CONFIG_USB_GSPCA_PAC7302 is not set
-# CONFIG_USB_GSPCA_PAC7311 is not set
-# CONFIG_USB_GSPCA_SN9C2028 is not set
-# CONFIG_USB_GSPCA_SN9C20X is not set
-# CONFIG_USB_GSPCA_SONIXB is not set
-# CONFIG_USB_GSPCA_SONIXJ is not set
-# CONFIG_USB_GSPCA_SPCA500 is not set
-# CONFIG_USB_GSPCA_SPCA501 is not set
-# CONFIG_USB_GSPCA_SPCA505 is not set
-# CONFIG_USB_GSPCA_SPCA506 is not set
-# CONFIG_USB_GSPCA_SPCA508 is not set
-# CONFIG_USB_GSPCA_SPCA561 is not set
-# CONFIG_USB_GSPCA_SPCA1528 is not set
-# CONFIG_USB_GSPCA_SQ905 is not set
-# CONFIG_USB_GSPCA_SQ905C is not set
-# CONFIG_USB_GSPCA_SQ930X is not set
-# CONFIG_USB_GSPCA_STK014 is not set
-# CONFIG_USB_GSPCA_STV0680 is not set
-# CONFIG_USB_GSPCA_SUNPLUS is not set
-# CONFIG_USB_GSPCA_T613 is not set
-# CONFIG_USB_GSPCA_TV8532 is not set
-# CONFIG_USB_GSPCA_VC032X is not set
-# CONFIG_USB_GSPCA_VICAM is not set
-# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
-# CONFIG_USB_GSPCA_ZC3XX is not set
-# CONFIG_VIDEO_PVRUSB2 is not set
-# CONFIG_VIDEO_HDPVR is not set
-# CONFIG_VIDEO_EM28XX is not set
-# CONFIG_VIDEO_CX231XX is not set
-# CONFIG_VIDEO_USBVISION is not set
-# CONFIG_USB_ET61X251 is not set
-# CONFIG_USB_SN9C102 is not set
-# CONFIG_USB_PWC is not set
-# CONFIG_USB_ZR364XX is not set
-# CONFIG_USB_STKWEBCAM is not set
-# CONFIG_USB_S2255 is not set
-# CONFIG_V4L_MEM2MEM_DRIVERS is not set
-CONFIG_RADIO_ADAPTERS=y
-# CONFIG_I2C_SI4713 is not set
-# CONFIG_RADIO_SI4713 is not set
-# CONFIG_USB_DSBR is not set
-# CONFIG_RADIO_SI470X is not set
-# CONFIG_USB_MR800 is not set
-# CONFIG_RADIO_TEA5764 is not set
-# CONFIG_RADIO_SAA7706H is not set
-# CONFIG_RADIO_TEF6862 is not set
-# CONFIG_RADIO_WL1273 is not set
-
-#
-# Texas Instruments WL128x FM driver (ST based)
-#
-# CONFIG_RADIO_WL128X is not set
-# CONFIG_SMS_SIANO_MDTV is not set
-
-#
-# Graphics support
-#
-# CONFIG_DRM is not set
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-CONFIG_FB=y
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB_DDC is not set
-# CONFIG_FB_BOOT_VESA_SUPPORT is not set
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-# CONFIG_FB_SYS_FILLRECT is not set
-# CONFIG_FB_SYS_COPYAREA is not set
-# CONFIG_FB_SYS_IMAGEBLIT is not set
-# CONFIG_FB_FOREIGN_ENDIAN is not set
-# CONFIG_FB_SYS_FOPS is not set
-# CONFIG_FB_WMT_GE_ROPS is not set
-# CONFIG_FB_SVGALIB is not set
-# CONFIG_FB_MACMODES is not set
-# CONFIG_FB_BACKLIGHT is not set
-# CONFIG_FB_MODE_HELPERS is not set
-# CONFIG_FB_TILEBLITTING is not set
-
-#
-# Frame buffer hardware drivers
-#
-# CONFIG_FB_S1D13XXX is not set
-# CONFIG_FB_TMIO is not set
-CONFIG_FB_RK29=y
-CONFIG_FB_WORK_IPP=y
-# CONFIG_FB_SCALING_OSD is not set
-CONFIG_FB_ROTATE_VIDEO=y
-# CONFIG_FB_MIRROR_X_Y is not set
-CONFIG_CLOSE_WIN1_DYNAMIC=y
-# CONFIG_FB_WIMO is not set
-# CONFIG_FB_UDL is not set
-# CONFIG_FB_VIRTUAL is not set
-# CONFIG_FB_METRONOME is not set
-# CONFIG_FB_BROADSHEET is not set
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_BACKLIGHT_WM831X=y
-# CONFIG_BACKLIGHT_RK29_BL is not set
-# CONFIG_BACKLIGHT_RK29_NEWTON_BL is not set
-# CONFIG_FIH_TOUCHKEY_LED is not set
-# CONFIG_BACKLIGHT_AW9364 is not set
-# CONFIG_BUTTON_LIGHT is not set
-# CONFIG_BACKLIGHT_ADP8860 is not set
-# CONFIG_BACKLIGHT_ADP8870 is not set
-
-#
-# Display device support
-#
-CONFIG_DISPLAY_SUPPORT=y
-
-#
-# Display hardware drivers
-#
-# CONFIG_LCD_NULL is not set
-# CONFIG_LCD_LG_LP097X02 is not set
-# CONFIG_LCD_TD043MGEA1 is not set
-# CONFIG_LCD_HX8357 is not set
-# CONFIG_LCD_TJ048NC01CA is not set
-# CONFIG_LCD_HL070VM4AU is not set
-# CONFIG_LCD_HSD070IDW1 is not set
-# CONFIG_LCD_RGB_TFT480800_25_E is not set
-# CONFIG_LCD_HSD100PXN is not set
-# CONFIG_LCD_HSD07PFW1 is not set
-# CONFIG_LCD_BYD8688FTGF is not set
-# CONFIG_LCD_B101AW06 is not set
-CONFIG_LCD_LS035Y8DX02A=y
-# CONFIG_LCD_LS035Y8DX04A is not set
-# CONFIG_LCD_CPTCLAA038LA31XE is not set
-# CONFIG_LCD_A060SE02 is not set
-# CONFIG_LCD_S1D13521 is not set
-# CONFIG_LCD_NT35582 is not set
-# CONFIG_LCD_NT35580 is not set
-# CONFIG_LCD_IPS1P5680_V1_E is not set
-# CONFIG_LCD_MCU_TFT480800_25_E is not set
-# CONFIG_LCD_NT35510 is not set
-# CONFIG_LCD_ILI9803_CPT4_3 is not set
-# CONFIG_LCD_AT070TNA2 is not set
-# CONFIG_LCD_AT070TN93 is not set
-# CONFIG_LCD_TX23D88VM is not set
-# CONFIG_LCD_A050VL01 is not set
-
-#
-# HDMI
-#
-# CONFIG_HDMI is not set
-
-#
-# Console display driver support
-#
-CONFIG_DUMMY_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE is not set
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_LOGO_LINUX_CLUT224 is not set
-# CONFIG_LOGO_CHARGER_CLUT224 is not set
-CONFIG_LOGO_G3_CLUT224=y
-CONFIG_SOUND=y
-# CONFIG_SOUND_OSS_CORE is not set
-CONFIG_SND=y
-CONFIG_SND_TIMER=y
-CONFIG_SND_PCM=y
-CONFIG_SND_JACK=y
-# CONFIG_SND_SEQUENCER is not set
-# CONFIG_SND_MIXER_OSS is not set
-# CONFIG_SND_PCM_OSS is not set
-# CONFIG_SND_HRTIMER is not set
-# CONFIG_SND_DYNAMIC_MINORS is not set
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_VERBOSE_PRINTK is not set
-# CONFIG_SND_DEBUG is not set
-# CONFIG_SND_RAWMIDI_SEQ is not set
-# CONFIG_SND_OPL3_LIB_SEQ is not set
-# CONFIG_SND_OPL4_LIB_SEQ is not set
-# CONFIG_SND_SBAWE_SEQ is not set
-# CONFIG_SND_EMU10K1_SEQ is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-# CONFIG_SND_SPI is not set
-# CONFIG_SND_USB is not set
-CONFIG_SND_SOC=y
-# CONFIG_SND_SOC_CACHE_LZO is not set
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_RK29_SOC_I2S=y
-# CONFIG_SND_RK29_SOC_I2S_2CH is not set
-CONFIG_SND_RK29_SOC_I2S_8CH=y
-# CONFIG_SND_I2S_DMA_EVENT_DYNAMIC is not set
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-# CONFIG_SND_RK29_SOC_WM8988 is not set
-# CONFIG_SND_RK29_SOC_WM8900 is not set
-# CONFIG_SND_RK29_SOC_RT5621 is not set
-# CONFIG_SND_RK29_SOC_RT5631 is not set
-# CONFIG_SND_RK29_SOC_RT5625 is not set
-CONFIG_SND_RK29_SOC_WM8994=y
-# CONFIG_SND_RK29_SOC_CS42L52 is not set
-# CONFIG_SND_RK29_SOC_AIC3111 is not set
-# CONFIG_SND_RK29_CODEC_SOC_MASTER is not set
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-# CONFIG_ADJUST_VOL_BY_CODEC is not set
-CONFIG_SND_SOC_I2C_AND_SPI=y
-# CONFIG_SND_SOC_ALL_CODECS is not set
-CONFIG_SND_SOC_WM_HUBS=y
-CONFIG_SND_SOC_WM8994=y
-# CONFIG_SOUND_PRIME is not set
-CONFIG_HID_SUPPORT=y
-CONFIG_HID=y
-# CONFIG_HIDRAW is not set
-
-#
-# USB Input Devices
-#
-CONFIG_USB_HID=y
-# CONFIG_HID_PID is not set
-# CONFIG_USB_HIDDEV is not set
-
-#
-# Special HID drivers
-#
-# CONFIG_HID_A4TECH is not set
-# CONFIG_HID_ACRUX is not set
-# CONFIG_HID_APPLE is not set
-# CONFIG_HID_BELKIN is not set
-# CONFIG_HID_CHERRY is not set
-# CONFIG_HID_CHICONY is not set
-# CONFIG_HID_PRODIKEYS is not set
-# CONFIG_HID_CYPRESS is not set
-# CONFIG_HID_DRAGONRISE is not set
-# CONFIG_HID_EMS_FF is not set
-# CONFIG_HID_ELECOM is not set
-# CONFIG_HID_EZKEY is not set
-# CONFIG_HID_KEYTOUCH is not set
-# CONFIG_HID_KYE is not set
-# CONFIG_HID_UCLOGIC is not set
-# CONFIG_HID_WALTOP is not set
-# CONFIG_HID_GYRATION is not set
-# CONFIG_HID_TWINHAN is not set
-# CONFIG_HID_KENSINGTON is not set
-# CONFIG_HID_LCPOWER is not set
-# CONFIG_HID_LOGITECH is not set
-# CONFIG_HID_MAGICMOUSE is not set
-# CONFIG_HID_MICROSOFT is not set
-# CONFIG_HID_MONTEREY is not set
-# CONFIG_HID_MULTITOUCH is not set
-# CONFIG_HID_NTRIG is not set
-# CONFIG_HID_ORTEK is not set
-# CONFIG_HID_PANTHERLORD is not set
-# CONFIG_HID_PETALYNX is not set
-# CONFIG_HID_PICOLCD is not set
-# CONFIG_HID_QUANTA is not set
-# CONFIG_HID_ROCCAT is not set
-# CONFIG_HID_ROCCAT_ARVO is not set
-# CONFIG_HID_ROCCAT_KONE is not set
-# CONFIG_HID_ROCCAT_KONEPLUS is not set
-# CONFIG_HID_ROCCAT_KOVAPLUS is not set
-# CONFIG_HID_ROCCAT_PYRA is not set
-# CONFIG_HID_SAMSUNG is not set
-# CONFIG_HID_SONY is not set
-# CONFIG_HID_SUNPLUS is not set
-# CONFIG_HID_GREENASIA is not set
-# CONFIG_HID_SMARTJOYPLUS is not set
-# CONFIG_HID_TOPSEED is not set
-# CONFIG_HID_THRUSTMASTER is not set
-# CONFIG_HID_WACOM is not set
-# CONFIG_HID_ZEROPLUS is not set
-# CONFIG_HID_ZYDACRON is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ARCH_HAS_HCD=y
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-CONFIG_USB=y
-# CONFIG_USB_DEBUG is not set
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-
-#
-# Miscellaneous USB options
-#
-# CONFIG_USB_DEVICEFS is not set
-CONFIG_USB_DEVICE_CLASS=y
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_OTG_WHITELIST is not set
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-# CONFIG_USB_MON is not set
-# CONFIG_USB_WUSB is not set
-# CONFIG_USB_WUSB_CBAF is not set
-
-#
-# USB Host Controller Drivers
-#
-# CONFIG_USB_C67X00_HCD is not set
-# CONFIG_USB_OXU210HP_HCD is not set
-# CONFIG_USB_ISP116X_HCD is not set
-# CONFIG_USB_ISP1760_HCD is not set
-# CONFIG_USB_ISP1362_HCD is not set
-# CONFIG_USB_SL811_HCD is not set
-# CONFIG_USB_R8A66597_HCD is not set
-# CONFIG_USB_HWA_HCD is not set
-# CONFIG_USB_MUSB_HDRC is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-# CONFIG_USB_WDM is not set
-# CONFIG_USB_TMC is not set
-
-#
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
-#
-
-#
-# also be needed; see USB_STORAGE Help for more info
-#
-CONFIG_USB_STORAGE=y
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_REALTEK is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_USBAT is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_STORAGE_SDDR55 is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_ALAUDA is not set
-# CONFIG_USB_STORAGE_ONETOUCH is not set
-# CONFIG_USB_STORAGE_KARMA is not set
-# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
-# CONFIG_USB_STORAGE_ENE_UB6250 is not set
-# CONFIG_USB_UAS is not set
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_MICROTEK is not set
-
-#
-# USB port drivers
-#
-CONFIG_USB_SERIAL=y
-# CONFIG_USB_SERIAL_CONSOLE is not set
-# CONFIG_USB_EZUSB is not set
-CONFIG_USB_SERIAL_GENERIC=y
-# CONFIG_USB_SERIAL_AIRCABLE is not set
-# CONFIG_USB_SERIAL_ARK3116 is not set
-# CONFIG_USB_SERIAL_BELKIN is not set
-# CONFIG_USB_SERIAL_CH341 is not set
-# CONFIG_USB_SERIAL_WHITEHEAT is not set
-# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
-# CONFIG_USB_SERIAL_CP210X is not set
-# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
-# CONFIG_USB_SERIAL_EMPEG is not set
-# CONFIG_USB_SERIAL_FTDI_SIO is not set
-# CONFIG_USB_SERIAL_FUNSOFT is not set
-# CONFIG_USB_SERIAL_VISOR is not set
-# CONFIG_USB_SERIAL_IPAQ is not set
-# CONFIG_USB_SERIAL_IR is not set
-# CONFIG_USB_SERIAL_EDGEPORT is not set
-# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
-# CONFIG_USB_SERIAL_GARMIN is not set
-# CONFIG_USB_SERIAL_IPW is not set
-# CONFIG_USB_SERIAL_IUU is not set
-# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
-# CONFIG_USB_SERIAL_KEYSPAN is not set
-# CONFIG_USB_SERIAL_KLSI is not set
-# CONFIG_USB_SERIAL_KOBIL_SCT is not set
-# CONFIG_USB_SERIAL_MCT_U232 is not set
-# CONFIG_USB_SERIAL_MOS7720 is not set
-# CONFIG_USB_SERIAL_MOS7840 is not set
-# CONFIG_USB_SERIAL_MOTOROLA is not set
-# CONFIG_USB_SERIAL_NAVMAN is not set
-# CONFIG_USB_SERIAL_PL2303 is not set
-# CONFIG_USB_SERIAL_OTI6858 is not set
-# CONFIG_USB_SERIAL_QCAUX is not set
-# CONFIG_USB_SERIAL_QUALCOMM is not set
-# CONFIG_USB_SERIAL_SPCP8X5 is not set
-# CONFIG_USB_SERIAL_HP4X is not set
-# CONFIG_USB_SERIAL_SAFE is not set
-# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
-# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
-# CONFIG_USB_SERIAL_SYMBOL is not set
-# CONFIG_USB_SERIAL_TI is not set
-# CONFIG_USB_SERIAL_CYBERJACK is not set
-# CONFIG_USB_SERIAL_XIRCOM is not set
-CONFIG_USB_SERIAL_WWAN=y
-CONFIG_USB_SERIAL_OPTION=y
-# CONFIG_USB_SERIAL_OMNINET is not set
-# CONFIG_USB_SERIAL_OPTICON is not set
-# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set
-# CONFIG_USB_SERIAL_ZIO is not set
-# CONFIG_USB_SERIAL_SSU100 is not set
-# CONFIG_USB_SERIAL_DEBUG is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_SEVSEG is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYPRESS_CY7C63 is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_FTDI_ELAN is not set
-# CONFIG_USB_APPLEDISPLAY is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TRANCEVIBRATOR is not set
-# CONFIG_USB_IOWARRIOR is not set
-# CONFIG_USB_TEST is not set
-# CONFIG_USB_ISIGHTFW is not set
-# CONFIG_USB_YUREX is not set
-CONFIG_USB_GADGET=y
-# CONFIG_USB_GADGET_DEBUG is not set
-# CONFIG_USB_GADGET_DEBUG_FILES is not set
-CONFIG_USB_GADGET_VBUS_DRAW=2
-CONFIG_USB_GADGET_SELECTED=y
-# CONFIG_USB_GADGET_FUSB300 is not set
-# CONFIG_USB_GADGET_R8A66597 is not set
-# CONFIG_USB_GADGET_PXA_U2O is not set
-# CONFIG_USB_GADGET_M66592 is not set
-CONFIG_USB_GADGET_DWC_OTG=y
-CONFIG_USB_DWC_OTG=y
-# CONFIG_USB_GADGET_DUMMY_HCD is not set
-CONFIG_USB_GADGET_DUALSPEED=y
-# CONFIG_USB_ZERO is not set
-# CONFIG_USB_AUDIO is not set
-# CONFIG_USB_ETH is not set
-# CONFIG_USB_G_NCM is not set
-# CONFIG_USB_GADGETFS is not set
-# CONFIG_USB_FUNCTIONFS is not set
-# CONFIG_USB_FILE_STORAGE is not set
-# CONFIG_USB_MASS_STORAGE is not set
-# CONFIG_USB_G_SERIAL is not set
-# CONFIG_USB_MIDI_GADGET is not set
-# CONFIG_USB_G_PRINTER is not set
-CONFIG_USB_G_ANDROID=y
-# CONFIG_USB_CDC_COMPOSITE is not set
-# CONFIG_USB_G_MULTI is not set
-# CONFIG_USB_G_HID is not set
-# CONFIG_USB_G_DBGP is not set
-# CONFIG_USB_G_WEBCAM is not set
-
-#
-# OTG and related infrastructure
-#
-# CONFIG_USB_OTG_WAKELOCK is not set
-# CONFIG_USB_GPIO_VBUS is not set
-# CONFIG_USB_ULPI is not set
-# CONFIG_NOP_USB_XCEIV is not set
-CONFIG_USB11_HOST=y
-CONFIG_USB11_HOST_EN=y
-# CONFIG_USB20_HOST is not set
-CONFIG_USB20_OTG=y
-# CONFIG_DWC_OTG_HOST_ONLY is not set
-CONFIG_DWC_OTG_DEVICE_ONLY=y
-# CONFIG_DWC_OTG_BOTH_HOST_SLAVE is not set
-CONFIG_DWC_CONN_EN=y
-# CONFIG_DWC_OTG_DEBUG is not set
-# CONFIG_DWC_REMOTE_WAKEUP is not set
-CONFIG_DWC_OTG=y
-CONFIG_MMC=y
-# CONFIG_MMC_DEBUG is not set
-CONFIG_MMC_UNSAFE_RESUME=y
-# CONFIG_MMC_CLKGATE is not set
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-
-#
-# MMC/SD/SDIO Card Drivers
-#
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_BLOCK_MINORS=8
-CONFIG_MMC_BLOCK_BOUNCE=y
-# CONFIG_MMC_BLOCK_DEFERRED_RESUME is not set
-# CONFIG_SDIO_UART is not set
-# CONFIG_MMC_TEST is not set
-
-#
-# MMC/SD/SDIO Host Controller Drivers
-#
-CONFIG_SDMMC_RK29=y
-
-#
-# Now, there are two SDMMC controllers selected, SDMMC0 and SDMMC1.
-#
-# CONFIG_SDMMC_RK29_OLD is not set
-CONFIG_SDMMC0_RK29=y
-# CONFIG_SDMMC0_RK29_WRITE_PROTECT is not set
-CONFIG_SDMMC1_RK29=y
-# CONFIG_SDMMC1_RK29_WRITE_PROTECT is not set
-# CONFIG_MMC_SDHCI is not set
-# CONFIG_MMC_DW is not set
-# CONFIG_MMC_VUB300 is not set
-# CONFIG_MMC_USHC is not set
-# CONFIG_MEMSTICK is not set
-# CONFIG_NEW_LEDS is not set
-# CONFIG_NFC_DEVICES is not set
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-# CONFIG_ACCESSIBILITY is not set
-CONFIG_RTC_LIB=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HCTOSYS=y
-CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-# CONFIG_RTC_DEBUG is not set
-
-#
-# RTC interfaces
-#
-CONFIG_RTC_INTF_SYSFS=y
-CONFIG_RTC_INTF_PROC=y
-CONFIG_RTC_INTF_DEV=y
-# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-CONFIG_RTC_INTF_ALARM=y
-CONFIG_RTC_INTF_ALARM_DEV=y
-# CONFIG_AUTO_WAKE_UP is not set
-# CONFIG_RTC_DRV_TEST is not set
-
-#
-# I2C RTC drivers
-#
-# CONFIG_RTC_HYM8563 is not set
-# CONFIG_RTC_M41T66 is not set
-# CONFIG_RTC_DRV_DS1307 is not set
-# CONFIG_RTC_DRV_DS1374 is not set
-# CONFIG_RTC_DRV_DS1672 is not set
-# CONFIG_RTC_DRV_DS3232 is not set
-# CONFIG_RTC_DRV_MAX6900 is not set
-# CONFIG_RTC_DRV_RS5C372 is not set
-# CONFIG_RTC_DRV_ISL1208 is not set
-# CONFIG_RTC_DRV_ISL12022 is not set
-# CONFIG_RTC_DRV_X1205 is not set
-# CONFIG_RTC_DRV_PCF8563 is not set
-# CONFIG_RTC_DRV_PCF8583 is not set
-# CONFIG_RTC_DRV_M41T80 is not set
-# CONFIG_RTC_DRV_BQ32K is not set
-# CONFIG_RTC_DRV_S35390A is not set
-# CONFIG_RTC_DRV_S35392A is not set
-# CONFIG_RTC_DRV_FM3130 is not set
-# CONFIG_RTC_DRV_RX8581 is not set
-# CONFIG_RTC_DRV_RX8025 is not set
-# CONFIG_RTC_DRV_EM3027 is not set
-# CONFIG_RTC_DRV_RV3029C2 is not set
-
-#
-# SPI RTC drivers
-#
-# CONFIG_RTC_DRV_M41T93 is not set
-# CONFIG_RTC_DRV_M41T94 is not set
-# CONFIG_RTC_DRV_DS1305 is not set
-# CONFIG_RTC_DRV_DS1390 is not set
-# CONFIG_RTC_DRV_MAX6902 is not set
-# CONFIG_RTC_DRV_R9701 is not set
-# CONFIG_RTC_DRV_RS5C348 is not set
-# CONFIG_RTC_DRV_DS3234 is not set
-# CONFIG_RTC_DRV_PCF2123 is not set
-
-#
-# Platform RTC drivers
-#
-# CONFIG_RTC_DRV_CMOS is not set
-# CONFIG_RTC_DRV_DS1286 is not set
-# CONFIG_RTC_DRV_DS1511 is not set
-# CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_DS1742 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
-# CONFIG_RTC_DRV_M48T86 is not set
-# CONFIG_RTC_DRV_M48T35 is not set
-# CONFIG_RTC_DRV_M48T59 is not set
-# CONFIG_RTC_DRV_MSM6242 is not set
-# CONFIG_RTC_DRV_BQ4802 is not set
-# CONFIG_RTC_DRV_RP5C01 is not set
-# CONFIG_RTC_DRV_V3020 is not set
-CONFIG_RTC_DRV_WM831X=y
-
-#
-# on-CPU RTC drivers
-#
-# CONFIG_DMADEVICES is not set
-# CONFIG_AUXDISPLAY is not set
-# CONFIG_UIO is not set
-CONFIG_STAGING=y
-# CONFIG_VIDEO_TM6000 is not set
-# CONFIG_USBIP_CORE is not set
-# CONFIG_ECHO is not set
-# CONFIG_BRCMUTIL is not set
-# CONFIG_ASUS_OLED is not set
-# CONFIG_R8712U is not set
-# CONFIG_TRANZPORT is not set
-
-#
-# Android
-#
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_RAM_CONSOLE=y
-CONFIG_ANDROID_RAM_CONSOLE_ENABLE_VERBOSE=y
-CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION=y
-CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_DATA_SIZE=128
-CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_ECC_SIZE=16
-CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_SYMBOL_SIZE=8
-CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_POLYNOMIAL=0x11d
-# CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT is not set
-CONFIG_ANDROID_TIMED_OUTPUT=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_POHMELFS is not set
-# CONFIG_LINE6_USB is not set
-# CONFIG_USB_SERIAL_QUATECH2 is not set
-# CONFIG_USB_SERIAL_QUATECH_USB2 is not set
-# CONFIG_VT6656 is not set
-# CONFIG_IIO is not set
-
-#
-# GPU Vivante
-#
-CONFIG_VIVANTE=y
-
-#
-# IPP
-#
-CONFIG_RK29_IPP=y
-# CONFIG_DEINTERLACE is not set
-# CONFIG_XVMALLOC is not set
-# CONFIG_ZRAM is not set
-# CONFIG_FB_SM7XX is not set
-# CONFIG_LIRC_STAGING is not set
-# CONFIG_EASYCAP is not set
-CONFIG_MACH_NO_WESTBRIDGE=y
-# CONFIG_USB_ENESTORAGE is not set
-# CONFIG_BCM_WIMAX is not set
-# CONFIG_FT1000 is not set
-
-#
-# Speakup console speech
-#
-# CONFIG_SPEAKUP is not set
-# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set
-# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set
-
-#
-# Altera FPGA firmware download module
-#
-# CONFIG_ALTERA_STAPL is not set
-CONFIG_CLKDEV_LOOKUP=y
-
-#
-# CMMB
-#
-# CONFIG_CMMB is not set
-# CONFIG_TEST_CODE is not set
-# CONFIG_RK29_SMC is not set
-
-#
-# CIR support
-#
-# CONFIG_RK_CIR is not set
-
-#
-# File systems
-#
-# CONFIG_EXT2_FS is not set
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-CONFIG_EXT4_USE_FOR_EXT23=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_EXT4_DEBUG is not set
-CONFIG_JBD=y
-CONFIG_JBD2=y
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_XFS_FS is not set
-# CONFIG_BTRFS_FS is not set
-# CONFIG_NILFS2_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
-CONFIG_FILE_LOCKING=y
-CONFIG_FSNOTIFY=y
-# CONFIG_DNOTIFY is not set
-CONFIG_INOTIFY_USER=y
-# CONFIG_FANOTIFY is not set
-# CONFIG_QUOTA is not set
-# CONFIG_QUOTACTL is not set
-# CONFIG_AUTOFS4_FS is not set
-CONFIG_FUSE_FS=y
-# CONFIG_CUSE is not set
-
-#
-# Caches
-#
-# CONFIG_FSCACHE is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=y
-# CONFIG_MSDOS_FS is not set
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-# CONFIG_TMPFS_XATTR is not set
-# CONFIG_HUGETLB_PAGE is not set
-# CONFIG_CONFIGFS_FS is not set
-CONFIG_MISC_FILESYSTEMS=y
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_YAFFS_FS is not set
-# CONFIG_JFFS2_FS is not set
-# CONFIG_LOGFS is not set
-CONFIG_CRAMFS=y
-# CONFIG_SQUASHFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_OMFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_PSTORE is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-
-#
-# Partition Types
-#
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_MSDOS_PARTITION=y
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-1"
-CONFIG_NLS_CODEPAGE_437=y
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-CONFIG_NLS_CODEPAGE_850=y
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-CONFIG_NLS_CODEPAGE_936=y
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ASCII is not set
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-CONFIG_NLS_ISO8859_15=y
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-CONFIG_NLS_UTF8=y
-
-#
-# Kernel hacking
-#
-CONFIG_PRINTK_TIME=y
-CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
-CONFIG_ENABLE_WARN_DEPRECATED=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_FRAME_WARN=1024
-CONFIG_MAGIC_SYSRQ=y
-# CONFIG_STRIP_ASM_SYMS is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
-# CONFIG_DEBUG_SECTION_MISMATCH is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-# CONFIG_LOCKUP_DETECTOR is not set
-# CONFIG_HARDLOCKUP_DETECTOR is not set
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
-# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
-CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
-CONFIG_SCHEDSTATS=y
-CONFIG_TIMER_STATS=y
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_KMEMLEAK is not set
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_PROVE_LOCKING is not set
-# CONFIG_SPARSE_RCU_POINTER is not set
-# CONFIG_LOCK_STAT is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-CONFIG_STACKTRACE=y
-# CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_DEBUG_KOBJECT is not set
-# CONFIG_DEBUG_HIGHMEM is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_WRITECOUNT is not set
-# CONFIG_DEBUG_MEMORY_INIT is not set
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_TEST_LIST_SORT is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_DEBUG_NOTIFIERS is not set
-# CONFIG_DEBUG_CREDENTIALS is not set
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_RCU_TORTURE_TEST is not set
-CONFIG_RCU_CPU_STALL_TIMEOUT=60
-CONFIG_RCU_CPU_STALL_VERBOSE=y
-# CONFIG_BACKTRACE_SELF_TEST is not set
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
-# CONFIG_FAULT_INJECTION is not set
-# CONFIG_LATENCYTOP is not set
-# CONFIG_SYSCTL_SYSCALL_CHECK is not set
-# CONFIG_DEBUG_PAGEALLOC is not set
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_TRACING_SUPPORT=y
-# CONFIG_FTRACE is not set
-# CONFIG_DMA_API_DEBUG is not set
-# CONFIG_ATOMIC64_SELFTEST is not set
-# CONFIG_SAMPLES is not set
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_KGDB is not set
-# CONFIG_TEST_KSTRTOX is not set
-# CONFIG_STRICT_DEVMEM is not set
-CONFIG_ARM_UNWIND=y
-# CONFIG_DEBUG_USER is not set
-# CONFIG_DEBUG_LL is not set
-# CONFIG_OC_ETM is not set
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY_DMESG_RESTRICT is not set
-# CONFIG_SECURITY is not set
-# CONFIG_SECURITYFS is not set
-CONFIG_DEFAULT_SECURITY_DAC=y
-CONFIG_DEFAULT_SECURITY=""
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_ALGAPI2=y
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_BLKCIPHER=y
-CONFIG_CRYPTO_BLKCIPHER2=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_PCOMP2=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
-# CONFIG_CRYPTO_GF128MUL is not set
-# CONFIG_CRYPTO_NULL is not set
-CONFIG_CRYPTO_WORKQUEUE=y
-# CONFIG_CRYPTO_CRYPTD is not set
-# CONFIG_CRYPTO_AUTHENC is not set
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Authenticated Encryption with Associated Data
-#
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_SEQIV is not set
-
-#
-# Block modes
-#
-CONFIG_CRYPTO_CBC=y
-# CONFIG_CRYPTO_CTR is not set
-# CONFIG_CRYPTO_CTS is not set
-CONFIG_CRYPTO_ECB=y
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_PCBC is not set
-# CONFIG_CRYPTO_XTS is not set
-
-#
-# Hash modes
-#
-# CONFIG_CRYPTO_HMAC is not set
-# CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_VMAC is not set
-
-#
-# Digest
-#
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_GHASH is not set
-# CONFIG_CRYPTO_MD4 is not set
-CONFIG_CRYPTO_MD5=y
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_RMD128 is not set
-# CONFIG_CRYPTO_RMD160 is not set
-# CONFIG_CRYPTO_RMD256 is not set
-# CONFIG_CRYPTO_RMD320 is not set
-CONFIG_CRYPTO_SHA1=y
-# CONFIG_CRYPTO_SHA256 is not set
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_WP512 is not set
-
-#
-# Ciphers
-#
-CONFIG_CRYPTO_AES=y
-# CONFIG_CRYPTO_ANUBIS is not set
-CONFIG_CRYPTO_ARC4=y
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-CONFIG_CRYPTO_DES=y
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_SALSA20 is not set
-# CONFIG_CRYPTO_SEED is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_TEA is not set
-CONFIG_CRYPTO_TWOFISH=y
-CONFIG_CRYPTO_TWOFISH_COMMON=y
-
-#
-# Compression
-#
-# CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_ZLIB is not set
-# CONFIG_CRYPTO_LZO is not set
-
-#
-# Random Number Generation
-#
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_USER_API_HASH is not set
-# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
-CONFIG_CRYPTO_HW=y
-# CONFIG_BINARY_PRINTF is not set
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-CONFIG_CRC_CCITT=y
-CONFIG_CRC16=y
-# CONFIG_CRC_T10DIF is not set
-# CONFIG_CRC_ITU_T is not set
-CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
-# CONFIG_LIBCRC32C is not set
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-# CONFIG_XZ_DEC is not set
-# CONFIG_XZ_DEC_BCJ is not set
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_REED_SOLOMON=y
-CONFIG_REED_SOLOMON_ENC8=y
-CONFIG_REED_SOLOMON_DEC8=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
-CONFIG_NLATTR=y
-# CONFIG_AVERAGE is not set
+++ /dev/null
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.32.27
-# Tue Aug 23 09:55:54 2011
-#
-CONFIG_ARM=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_HAVE_SCHED_CLOCK=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_TIME=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-CONFIG_ARCH_HAS_CPUFREQ=y
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ZONE_DMA=y
-CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-CONFIG_CONSTRUCTORS=y
-
-#
-# General setup
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_LOCK_KERNEL=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_LOCALVERSION=""
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZO=y
-# CONFIG_KERNEL_GZIP is not set
-# CONFIG_KERNEL_BZIP2 is not set
-# CONFIG_KERNEL_LZMA is not set
-CONFIG_KERNEL_LZO=y
-# CONFIG_SWAP is not set
-# CONFIG_SYSVIPC is not set
-# CONFIG_POSIX_MQUEUE is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_AUDIT is not set
-
-#
-# RCU Subsystem
-#
-CONFIG_TREE_RCU=y
-# CONFIG_TREE_PREEMPT_RCU is not set
-# CONFIG_RCU_TRACE is not set
-CONFIG_RCU_FANOUT=32
-# CONFIG_RCU_FANOUT_EXACT is not set
-# CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_IKCONFIG is not set
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-# CONFIG_CGROUP_NS is not set
-CONFIG_CGROUP_FREEZER=y
-# CONFIG_CGROUP_DEVICE is not set
-# CONFIG_CPUSETS is not set
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-# CONFIG_CGROUP_MEM_RES_CTLR is not set
-CONFIG_CGROUP_SCHED=y
-CONFIG_FAIR_GROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-# CONFIG_SYSFS_DEPRECATED_V2 is not set
-# CONFIG_RELAY is not set
-# CONFIG_NAMESPACES is not set
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_RD_GZIP=y
-# CONFIG_RD_BZIP2 is not set
-# CONFIG_RD_LZMA is not set
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL=y
-CONFIG_ANON_INODES=y
-CONFIG_PANIC_TIMEOUT=5
-CONFIG_EMBEDDED=y
-CONFIG_UID16=y
-# CONFIG_SYSCTL_SYSCALL is not set
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-# CONFIG_ELF_CORE is not set
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_ASHMEM=y
-CONFIG_AIO=y
-
-#
-# Kernel Performance Events And Counters
-#
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_COMPAT_BRK=y
-CONFIG_SLAB=y
-# CONFIG_SLUB is not set
-# CONFIG_SLOB is not set
-# CONFIG_PROFILING is not set
-CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_CLK=y
-
-#
-# GCOV-based kernel profiling
-#
-# CONFIG_SLOW_WORK is not set
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_SLABINFO=y
-CONFIG_RT_MUTEXES=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-# CONFIG_MODULE_FORCE_LOAD is not set
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_MODVERSIONS is not set
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_BLOCK=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_BLK_DEV_INTEGRITY is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-# CONFIG_IOSCHED_AS is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_IOSCHED_CFQ=y
-# CONFIG_DEFAULT_AS is not set
-# CONFIG_DEFAULT_DEADLINE is not set
-CONFIG_DEFAULT_CFQ=y
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="cfq"
-CONFIG_FREEZER=y
-
-#
-# System Type
-#
-CONFIG_MMU=y
-# CONFIG_ARCH_AAEC2000 is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_GEMINI is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_MXC is not set
-# CONFIG_ARCH_STMP3XXX is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_NOMADIK is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP23XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_L7200 is not set
-# CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_LOKI is not set
-# CONFIG_ARCH_MV78XX0 is not set
-# CONFIG_ARCH_ORION5X is not set
-# CONFIG_ARCH_MMP is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
-# CONFIG_ARCH_W90X900 is not set
-# CONFIG_ARCH_PNX4008 is not set
-# CONFIG_ARCH_PXA is not set
-# CONFIG_ARCH_MSM is not set
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_S3C64XX is not set
-# CONFIG_ARCH_S5PC1XX is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_U300 is not set
-# CONFIG_ARCH_DAVINCI is not set
-# CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_BCMRING is not set
-CONFIG_ARCH_RK29=y
-CONFIG_MACH_RK29SDK=y
-# CONFIG_MACH_RK29SDK_DDR3 is not set
-# CONFIG_MACH_RK29WINACCORD is not set
-# CONFIG_MACH_RK29FIH is not set
-# CONFIG_MACH_RK29_MALATA is not set
-# CONFIG_MACH_RK29_PHONESDK is not set
-# CONFIG_MACH_RK29_A22 is not set
-# CONFIG_MACH_RK29_PHONEPADSDK is not set
-# CONFIG_MACH_RK29_newton is not set
-# CONFIG_MACH_RK29_P91 is not set
-# CONFIG_DDR_TYPE_DDRII is not set
-# CONFIG_DDR_TYPE_LPDDR is not set
-# CONFIG_DDR_TYPE_DDR3_800D is not set
-# CONFIG_DDR_TYPE_DDR3_800E is not set
-# CONFIG_DDR_TYPE_DDR3_1066E is not set
-# CONFIG_DDR_TYPE_DDR3_1066F is not set
-# CONFIG_DDR_TYPE_DDR3_1066G is not set
-# CONFIG_DDR_TYPE_DDR3_1333F is not set
-# CONFIG_DDR_TYPE_DDR3_1333G is not set
-# CONFIG_DDR_TYPE_DDR3_1333H is not set
-# CONFIG_DDR_TYPE_DDR3_1333J is not set
-# CONFIG_DDR_TYPE_DDR3_1600G is not set
-# CONFIG_DDR_TYPE_DDR3_1600H is not set
-# CONFIG_DDR_TYPE_DDR3_1600J is not set
-# CONFIG_DDR_TYPE_DDR3_1600K is not set
-# CONFIG_DDR_TYPE_DDR3_1866J is not set
-# CONFIG_DDR_TYPE_DDR3_1866K is not set
-# CONFIG_DDR_TYPE_DDR3_1866L is not set
-# CONFIG_DDR_TYPE_DDR3_1866M is not set
-# CONFIG_DDR_TYPE_DDR3_2133K is not set
-# CONFIG_DDR_TYPE_DDR3_2133L is not set
-# CONFIG_DDR_TYPE_DDR3_2133M is not set
-# CONFIG_DDR_TYPE_DDR3_2133N is not set
-CONFIG_DDR_TYPE_DDR3_DEFAULT=y
-CONFIG_RK29_MEM_SIZE_M=512
-CONFIG_DDR_SDRAM_FREQ=400
-CONFIG_DDR_FREQ=y
-# CONFIG_DDR_RECONFIG is not set
-CONFIG_WIFI_CONTROL_FUNC=y
-
-#
-# RK29 VPU (Video Processing Unit) support
-#
-CONFIG_RK29_VPU=y
-CONFIG_RK29_VPU_SERVICE=y
-# CONFIG_RK29_VPU_DEBUG is not set
-CONFIG_RK29_JTAG=y
-CONFIG_RK29_LAST_LOG=y
-
-#
-# support for RK29 power manage
-#
-# CONFIG_RK29_WORKING_POWER_MANAGEMENT is not set
-# CONFIG_RK29_CLK_SWITCH_TO_32K is not set
-# CONFIG_RK29_GPIO_SUSPEND is not set
-CONFIG_RK29_PWM_INSRAM=y
-
-#
-# Processor Type
-#
-CONFIG_CPU_32=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_V7=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_THUMBEE=y
-# CONFIG_CPU_ICACHE_DISABLE is not set
-# CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_HAS_TLS_REG=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-# CONFIG_ARM_ERRATA_430973 is not set
-# CONFIG_ARM_ERRATA_458693 is not set
-# CONFIG_ARM_ERRATA_460075 is not set
-CONFIG_ARM_GIC=y
-CONFIG_PL330=y
-CONFIG_COMMON_CLKDEV=y
-
-#
-# Bus support
-#
-# CONFIG_PCI_SYSCALL is not set
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-# CONFIG_PCCARD is not set
-
-#
-# Kernel Features
-#
-CONFIG_TICK_ONESHOT=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_VMSPLIT_3G=y
-# CONFIG_VMSPLIT_2G is not set
-# CONFIG_VMSPLIT_1G is not set
-CONFIG_PAGE_OFFSET=0xC0000000
-# CONFIG_PREEMPT_NONE is not set
-# CONFIG_PREEMPT_VOLUNTARY is not set
-CONFIG_PREEMPT=y
-CONFIG_HZ=100
-# CONFIG_THUMB2_KERNEL is not set
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-CONFIG_HIGHMEM=y
-# CONFIG_HIGHPTE is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_SPLIT_PTLOCK_CPUS=4
-# CONFIG_PHYS_ADDR_T_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=1
-CONFIG_BOUNCE=y
-CONFIG_VIRT_TO_BUS=y
-CONFIG_HAVE_MLOCK=y
-CONFIG_HAVE_MLOCKED_PAGE_BIT=y
-# CONFIG_KSM is not set
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_UACCESS_WITH_MEMCPY is not set
-
-#
-# Boot options
-#
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_CMDLINE=""
-# CONFIG_XIP_KERNEL is not set
-CONFIG_KEXEC=y
-CONFIG_ATAGS_PROC=y
-
-#
-# CPU Power Management
-#
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_TABLE=y
-# CONFIG_CPU_FREQ_DEBUG is not set
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_FREQ_STAT_DETAILS=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-# CONFIG_CPU_IDLE is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_NEON=y
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-CONFIG_HAVE_AOUT=y
-# CONFIG_BINFMT_AOUT is not set
-# CONFIG_BINFMT_MISC is not set
-
-#
-# Power management options
-#
-CONFIG_PM=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_SLEEP=y
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_HAS_WAKELOCK=y
-CONFIG_HAS_EARLYSUSPEND=y
-CONFIG_WAKELOCK=y
-CONFIG_WAKELOCK_STAT=y
-CONFIG_USER_WAKELOCK=y
-CONFIG_EARLYSUSPEND=y
-# CONFIG_NO_USER_SPACE_SCREEN_ACCESS_CONTROL is not set
-# CONFIG_CONSOLE_EARLYSUSPEND is not set
-CONFIG_FB_EARLYSUSPEND=y
-# CONFIG_APM_EMULATION is not set
-# CONFIG_PM_RUNTIME is not set
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
-# CONFIG_XFRM_STATISTICS is not set
-CONFIG_XFRM_IPCOMP=y
-CONFIG_NET_KEY=y
-# CONFIG_NET_KEY_MIGRATE is not set
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-CONFIG_INET_ESP=y
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-CONFIG_INET_TUNNEL=y
-CONFIG_INET_XFRM_MODE_TRANSPORT=y
-CONFIG_INET_XFRM_MODE_TUNNEL=y
-CONFIG_INET_XFRM_MODE_BEET=y
-# CONFIG_INET_LRO is not set
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-# CONFIG_IPV6_ROUTE_INFO is not set
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_INET6_XFRM_TUNNEL=y
-CONFIG_INET6_TUNNEL=y
-CONFIG_INET6_XFRM_MODE_TRANSPORT=y
-CONFIG_INET6_XFRM_MODE_TUNNEL=y
-CONFIG_INET6_XFRM_MODE_BEET=y
-# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
-CONFIG_IPV6_SIT=y
-CONFIG_IPV6_NDISC_NODETYPE=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-# CONFIG_IPV6_SUBTREES is not set
-# CONFIG_IPV6_MROUTE is not set
-CONFIG_ANDROID_PARANOID_NETWORK=y
-# CONFIG_NETWORK_SECMARK is not set
-CONFIG_NETFILTER=y
-CONFIG_NETFILTER_DEBUG=y
-CONFIG_NETFILTER_ADVANCED=y
-
-#
-# Core Netfilter Configuration
-#
-CONFIG_NETFILTER_NETLINK=y
-CONFIG_NETFILTER_NETLINK_QUEUE=y
-CONFIG_NETFILTER_NETLINK_LOG=y
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CT_ACCT=y
-CONFIG_NF_CONNTRACK_MARK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_GRE=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_XTABLES=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
-# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
-# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
-# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
-# CONFIG_NETFILTER_XT_MATCH_ESP is not set
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_HL=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set
-CONFIG_NETFILTER_XT_MATCH_OWNER=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
-# CONFIG_NETFILTER_XT_MATCH_REALM is not set
-# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
-# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-# CONFIG_NETFILTER_XT_MATCH_OSF is not set
-# CONFIG_IP_VS is not set
-
-#
-# IP: Netfilter Configuration
-#
-CONFIG_NF_DEFRAG_IPV4=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_NF_CONNTRACK_PROC_COMPAT=y
-# CONFIG_IP_NF_QUEUE is not set
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_ADDRTYPE=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_LOG=y
-# CONFIG_IP_NF_TARGET_ULOG is not set
-CONFIG_NF_NAT=y
-CONFIG_NF_NAT_NEEDED=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-# CONFIG_NF_NAT_SNMP_BASIC is not set
-CONFIG_NF_NAT_PROTO_DCCP=y
-CONFIG_NF_NAT_PROTO_GRE=y
-CONFIG_NF_NAT_PROTO_UDPLITE=y
-CONFIG_NF_NAT_PROTO_SCTP=y
-CONFIG_NF_NAT_FTP=y
-CONFIG_NF_NAT_IRC=y
-CONFIG_NF_NAT_TFTP=y
-CONFIG_NF_NAT_AMANDA=y
-CONFIG_NF_NAT_PPTP=y
-CONFIG_NF_NAT_H323=y
-CONFIG_NF_NAT_SIP=y
-# CONFIG_IP_NF_MANGLE is not set
-# CONFIG_IP_NF_TARGET_TTL is not set
-# CONFIG_IP_NF_RAW is not set
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-
-#
-# IPv6: Netfilter Configuration
-#
-# CONFIG_NF_CONNTRACK_IPV6 is not set
-# CONFIG_IP6_NF_QUEUE is not set
-# CONFIG_IP6_NF_IPTABLES is not set
-# CONFIG_IP_DCCP is not set
-# CONFIG_IP_SCTP is not set
-# CONFIG_RDS is not set
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_NET_DSA is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-# CONFIG_PHONET is not set
-# CONFIG_IEEE802154 is not set
-CONFIG_NET_SCHED=y
-
-#
-# Queueing/Scheduling
-#
-# CONFIG_NET_SCH_CBQ is not set
-CONFIG_NET_SCH_HTB=y
-# CONFIG_NET_SCH_HFSC is not set
-# CONFIG_NET_SCH_PRIO is not set
-# CONFIG_NET_SCH_MULTIQ is not set
-# CONFIG_NET_SCH_RED is not set
-# CONFIG_NET_SCH_SFQ is not set
-# CONFIG_NET_SCH_TEQL is not set
-# CONFIG_NET_SCH_TBF is not set
-# CONFIG_NET_SCH_GRED is not set
-# CONFIG_NET_SCH_DSMARK is not set
-# CONFIG_NET_SCH_NETEM is not set
-# CONFIG_NET_SCH_DRR is not set
-CONFIG_NET_SCH_INGRESS=y
-
-#
-# Classification
-#
-CONFIG_NET_CLS=y
-# CONFIG_NET_CLS_BASIC is not set
-# CONFIG_NET_CLS_TCINDEX is not set
-# CONFIG_NET_CLS_ROUTE4 is not set
-# CONFIG_NET_CLS_FW is not set
-CONFIG_NET_CLS_U32=y
-# CONFIG_CLS_U32_PERF is not set
-# CONFIG_CLS_U32_MARK is not set
-# CONFIG_NET_CLS_RSVP is not set
-# CONFIG_NET_CLS_RSVP6 is not set
-# CONFIG_NET_CLS_FLOW is not set
-# CONFIG_NET_CLS_CGROUP is not set
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_STACK=32
-# CONFIG_NET_EMATCH_CMP is not set
-# CONFIG_NET_EMATCH_NBYTE is not set
-CONFIG_NET_EMATCH_U32=y
-# CONFIG_NET_EMATCH_META is not set
-# CONFIG_NET_EMATCH_TEXT is not set
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-# CONFIG_GACT_PROB is not set
-CONFIG_NET_ACT_MIRRED=y
-# CONFIG_NET_ACT_IPT is not set
-# CONFIG_NET_ACT_NAT is not set
-# CONFIG_NET_ACT_PEDIT is not set
-# CONFIG_NET_ACT_SIMP is not set
-# CONFIG_NET_ACT_SKBEDIT is not set
-# CONFIG_NET_CLS_IND is not set
-CONFIG_NET_SCH_FIFO=y
-# CONFIG_DCB is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_CAN is not set
-# CONFIG_IRDA is not set
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-# CONFIG_BT_BNEP is not set
-# CONFIG_BT_HIDP is not set
-
-#
-# Bluetooth device drivers
-#
-# CONFIG_BT_HCIBTUSB is not set
-# CONFIG_BT_HCIBTSDIO is not set
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-# CONFIG_BT_HCIUART_BCSP is not set
-# CONFIG_BT_HCIUART_LL is not set
-# CONFIG_BT_HCIBCM203X is not set
-# CONFIG_BT_HCIBPA10X is not set
-# CONFIG_BT_HCIBFUSB is not set
-# CONFIG_BT_HCIVHCI is not set
-# CONFIG_BT_MRVL is not set
-CONFIG_BT_HCIBCM4325=y
-CONFIG_IDBLOCK=y
-# CONFIG_WIFI_MAC is not set
-# CONFIG_AF_RXRPC is not set
-CONFIG_FIB_RULES=y
-CONFIG_WIRELESS=y
-# CONFIG_CFG80211 is not set
-CONFIG_CFG80211_DEFAULT_PS_VALUE=0
-# CONFIG_WIRELESS_OLD_REGULATORY is not set
-CONFIG_WIRELESS_EXT=y
-CONFIG_WIRELESS_EXT_SYSFS=y
-# CONFIG_LIB80211 is not set
-
-#
-# CFG80211 needs to be enabled for MAC80211
-#
-
-#
-# Some wireless drivers require a rate control algorithm
-#
-# CONFIG_WIMAX is not set
-CONFIG_RFKILL=y
-# CONFIG_RFKILL_PM is not set
-# CONFIG_RFKILL_INPUT is not set
-# CONFIG_NET_9P is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_CONNECTOR is not set
-CONFIG_MTD=y
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_TESTS is not set
-# CONFIG_MTD_CONCAT is not set
-CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_REDBOOT_PARTS is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_AFS_PARTS is not set
-# CONFIG_MTD_AR7_PARTS is not set
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
-# CONFIG_INFTL is not set
-# CONFIG_RFD_FTL is not set
-# CONFIG_SSFDC is not set
-# CONFIG_MTD_OOPS is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-# CONFIG_MTD_CFI is not set
-# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_ABSENT is not set
-
-#
-# Mapping drivers for chip access
-#
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_PLATRAM is not set
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLOCK2MTD is not set
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-CONFIG_MTD_NAND_IDS=y
-# CONFIG_MTD_NAND is not set
-CONFIG_MTD_RKNAND=y
-CONFIG_MTD_NAND_RK29XX=y
-CONFIG_MTD_RKNAND_BUFFER=y
-# CONFIG_MTD_EMMC_CLK_POWER_SAVE is not set
-# CONFIG_MTD_NAND_RK29XX_DEBUG is not set
-# CONFIG_MTD_ONENAND is not set
-
-#
-# LPDDR flash memory drivers
-#
-# CONFIG_MTD_LPDDR is not set
-
-#
-# UBI - Unsorted block images
-#
-# CONFIG_MTD_UBI is not set
-# CONFIG_PARPORT is not set
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=y
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_UB is not set
-# CONFIG_BLK_DEV_RAM is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-# CONFIG_MG_DISK is not set
-CONFIG_MISC_DEVICES=y
-CONFIG_ANDROID_PMEM=y
-# CONFIG_ICS932S401 is not set
-# CONFIG_ENCLOSURE_SERVICES is not set
-# CONFIG_KERNEL_DEBUGGER_CORE is not set
-# CONFIG_ISL29003 is not set
-CONFIG_UID_STAT=y
-# CONFIG_WL127X_RFKILL is not set
-CONFIG_APANIC=y
-CONFIG_APANIC_PLABEL="kpanic"
-# CONFIG_STE is not set
-# CONFIG_MTK23D is not set
-# CONFIG_FM580X is not set
-# CONFIG_MU509 is not set
-# CONFIG_RK29_NEWTON is not set
-# CONFIG_C2PORT is not set
-
-#
-# EEPROM support
-#
-# CONFIG_EEPROM_AT24 is not set
-# CONFIG_EEPROM_LEGACY is not set
-# CONFIG_EEPROM_MAX6875 is not set
-# CONFIG_EEPROM_93CX6 is not set
-CONFIG_RK29_SUPPORT_MODEM=y
-CONFIG_MODEM_ROCKCHIP_DEMO=y
-# CONFIG_MODEM_LONGCHEER_U6300V is not set
-# CONFIG_MODEM_THINKWILL_MW100G is not set
-# CONFIG_RK29_GPS is not set
-
-#
-# Motion Sensors Support
-#
-# CONFIG_MPU_NONE is not set
-# CONFIG_MPU_SENSORS_MPU3050 is not set
-# CONFIG_MPU_SENSORS_MPU6000 is not set
-# CONFIG_MPU_SENSORS_TIMERIRQ is not set
-CONFIG_HAVE_IDE=y
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_DMA=y
-# CONFIG_SCSI_TGT is not set
-# CONFIG_SCSI_NETLINK is not set
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=y
-# CONFIG_CHR_DEV_ST is not set
-# CONFIG_CHR_DEV_OSST is not set
-# CONFIG_BLK_DEV_SR is not set
-# CONFIG_CHR_DEV_SG is not set
-# CONFIG_CHR_DEV_SCH is not set
-CONFIG_SCSI_MULTI_LUN=y
-# CONFIG_SCSI_CONSTANTS is not set
-# CONFIG_SCSI_LOGGING is not set
-# CONFIG_SCSI_SCAN_ASYNC is not set
-CONFIG_SCSI_WAIT_SCAN=m
-
-#
-# SCSI Transports
-#
-# CONFIG_SCSI_SPI_ATTRS is not set
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_LIBSAS is not set
-# CONFIG_SCSI_SRP_ATTRS is not set
-CONFIG_SCSI_LOWLEVEL=y
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_LIBFC is not set
-# CONFIG_LIBFCOE is not set
-# CONFIG_SCSI_DEBUG is not set
-# CONFIG_SCSI_DH is not set
-# CONFIG_SCSI_OSD_INITIATOR is not set
-# CONFIG_ATA is not set
-CONFIG_MD=y
-# CONFIG_BLK_DEV_MD is not set
-CONFIG_BLK_DEV_DM=y
-# CONFIG_DM_DEBUG is not set
-CONFIG_DM_CRYPT=y
-# CONFIG_DM_SNAPSHOT is not set
-# CONFIG_DM_MIRROR is not set
-# CONFIG_DM_ZERO is not set
-# CONFIG_DM_MULTIPATH is not set
-# CONFIG_DM_DELAY is not set
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-# CONFIG_IFB is not set
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_MACVLAN is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_VETH is not set
-CONFIG_PHYLIB=y
-
-#
-# MII PHY device drivers
-#
-# CONFIG_MARVELL_PHY is not set
-# CONFIG_DAVICOM_PHY is not set
-# CONFIG_QSEMI_PHY is not set
-# CONFIG_LXT_PHY is not set
-# CONFIG_CICADA_PHY is not set
-# CONFIG_VITESSE_PHY is not set
-# CONFIG_SMSC_PHY is not set
-# CONFIG_BROADCOM_PHY is not set
-# CONFIG_ICPLUS_PHY is not set
-# CONFIG_REALTEK_PHY is not set
-# CONFIG_NATIONAL_PHY is not set
-# CONFIG_STE10XP is not set
-# CONFIG_LSI_ET1011C_PHY is not set
-# CONFIG_FIXED_PHY is not set
-# CONFIG_MDIO_BITBANG is not set
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-# CONFIG_AX88796 is not set
-CONFIG_RK29_VMAC=y
-# CONFIG_SMC91X is not set
-# CONFIG_DM9000 is not set
-# CONFIG_ETHOC is not set
-# CONFIG_SMC911X is not set
-# CONFIG_SMSC911X is not set
-# CONFIG_DNET is not set
-# CONFIG_IBM_NEW_EMAC_ZMII is not set
-# CONFIG_IBM_NEW_EMAC_RGMII is not set
-# CONFIG_IBM_NEW_EMAC_TAH is not set
-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
-# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
-# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
-# CONFIG_B44 is not set
-# CONFIG_KS8842 is not set
-# CONFIG_KS8851_MLL is not set
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN=y
-CONFIG_WLAN_80211=y
-# CONFIG_WIFI_NONE is not set
-CONFIG_BCM4329=y
-# CONFIG_MV8686 is not set
-# CONFIG_BCM4319 is not set
-
-#
-# Enable WiMAX (Networking options) to see the WiMAX drivers
-#
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET is not set
-# CONFIG_USB_HSO is not set
-# CONFIG_WAN is not set
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-# CONFIG_PPP_MPPE is not set
-# CONFIG_PPPOE is not set
-# CONFIG_PPPOL2TP is not set
-# CONFIG_PPPOLAC is not set
-# CONFIG_PPPOPNS is not set
-# CONFIG_SLIP is not set
-CONFIG_SLHC=y
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_ISDN is not set
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-CONFIG_INPUT_POLLDEV=y
-
-#
-# Userland interfaces
-#
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_JOYDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_EVBUG is not set
-CONFIG_INPUT_KEYRESET=y
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYS_RK29=y
-# CONFIG_SYNAPTICS_SO340010 is not set
-# CONFIG_KEYBOARD_ADP5588 is not set
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_QT2160 is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_GPIO is not set
-# CONFIG_KEYBOARD_WM831X_GPIO is not set
-# CONFIG_KEYBOARD_MATRIX is not set
-# CONFIG_KEYBOARD_MAX7359 is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_OPENCORES is not set
-# CONFIG_KEYBOARD_STOWAWAY is not set
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-# CONFIG_TOUCHSCREEN_ILI2102_IIC is not set
-# CONFIG_TOUCHSCREEN_IT7250 is not set
-# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
-# CONFIG_TOUCHSCREEN_AD7879 is not set
-# CONFIG_TOUCHSCREEN_EETI is not set
-# CONFIG_TOUCHSCREEN_FUJITSU is not set
-# CONFIG_TOUCHSCREEN_GUNZE is not set
-# CONFIG_TOUCHSCREEN_ELO is not set
-# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
-# CONFIG_TOUCHSCREEN_MCS5000 is not set
-# CONFIG_TOUCHSCREEN_MTOUCH is not set
-# CONFIG_TOUCHSCREEN_INEXIO is not set
-# CONFIG_TOUCHSCREEN_MK712 is not set
-# CONFIG_TOUCHSCREEN_PENMOUNT is not set
-# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI is not set
-# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
-# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
-# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
-# CONFIG_TOUCHSCREEN_TSC2007 is not set
-# CONFIG_TOUCHSCREEN_W90X900 is not set
-# CONFIG_HANNSTAR_P1003 is not set
-# CONFIG_ATMEL_MXT224 is not set
-# CONFIG_SINTEK_3FA16 is not set
-CONFIG_EETI_EGALAX=y
-CONFIG_EETI_EGALAX_MAX_X=1087
-CONFIG_EETI_EGALAX_MAX_Y=800
-# CONFIG_EETI_EGALAX_DEBUG is not set
-# CONFIG_TOUCHSCREEN_IT7260 is not set
-# CONFIG_TOUCHSCREEN_NAS is not set
-# CONFIG_LAIBAO_TS is not set
-# CONFIG_TOUCHSCREEN_GT801_IIC is not set
-# CONFIG_TOUCHSCREEN_GT818_IIC is not set
-# CONFIG_D70_L3188A is not set
-# CONFIG_TOUCHSCREEN_GT819 is not set
-# CONFIG_TOUCHSCREEN_FT5406 is not set
-# CONFIG_ATMEL_MXT1386 is not set
-CONFIG_INPUT_MISC=y
-# CONFIG_INPUT_LPSENSOR_ISL29028 is not set
-# CONFIG_INPUT_LPSENSOR_CM3602 is not set
-# CONFIG_INPUT_ATI_REMOTE is not set
-# CONFIG_INPUT_ATI_REMOTE2 is not set
-# CONFIG_INPUT_KEYCHORD is not set
-# CONFIG_INPUT_KEYSPAN_REMOTE is not set
-# CONFIG_INPUT_POWERMATE is not set
-# CONFIG_INPUT_YEALINK is not set
-# CONFIG_INPUT_CM109 is not set
-CONFIG_INPUT_UINPUT=y
-# CONFIG_INPUT_GPIO is not set
-# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
-# CONFIG_MAG_SENSORS is not set
-CONFIG_G_SENSOR_DEVICE=y
-# CONFIG_GS_MMA7660 is not set
-CONFIG_GS_MMA8452=y
-CONFIG_GS_L3G4200D=y
-# CONFIG_INPUT_JOGBALL is not set
-# CONFIG_LIGHT_SENSOR_DEVICE is not set
-
-#
-# Hardware I/O ports
-#
-# CONFIG_SERIO is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_DEVMEM=y
-CONFIG_DEVKMEM=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_SERIAL_RK29=y
-CONFIG_SERIAL_RK29_STANDARD=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-# CONFIG_UART0_DMA_RK29 is not set
-CONFIG_UART1_RK29=y
-CONFIG_UART2_RK29=y
-CONFIG_UART2_CTS_RTS_RK29=y
-# CONFIG_UART2_DMA_RK29 is not set
-# CONFIG_UART3_RK29 is not set
-CONFIG_SERIAL_RK29_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
-# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_IPMI_HANDLER is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_R3964 is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_TCG_TPM is not set
-# CONFIG_DCC_TTY is not set
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_COMPAT=y
-# CONFIG_I2C_CHARDEV is not set
-CONFIG_I2C_HELPER_AUTO=y
-
-#
-# I2C Hardware Bus support
-#
-CONFIG_I2C_RK29=y
-
-#
-# Now, there are four I2C interfaces selected by developer.
-#
-CONFIG_I2C0_RK29=y
-CONFIG_RK29_I2C0_CONTROLLER=y
-# CONFIG_RK29_I2C0_GPIO is not set
-CONFIG_I2C1_RK29=y
-CONFIG_RK29_I2C1_CONTROLLER=y
-# CONFIG_RK29_I2C1_GPIO is not set
-CONFIG_I2C2_RK29=y
-CONFIG_RK29_I2C2_CONTROLLER=y
-# CONFIG_RK29_I2C2_GPIO is not set
-CONFIG_I2C3_RK29=y
-CONFIG_RK29_I2C3_CONTROLLER=y
-# CONFIG_RK29_I2C3_GPIO is not set
-CONFIG_I2C_DEV_RK29=y
-
-#
-# Miscellaneous I2C Chip support
-#
-# CONFIG_DS1682 is not set
-# CONFIG_SENSORS_TSL2550 is not set
-# CONFIG_SENSORS_PCA963X is not set
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-# CONFIG_I2C_DEBUG_CHIP is not set
-# CONFIG_SPI is not set
-CONFIG_ADC=y
-# CONFIG_ADC_RK28 is not set
-CONFIG_ADC_RK29=y
-
-#
-# Headset device support
-#
-# CONFIG_RK_HEADSET_DET is not set
-
-#
-# PPS support
-#
-# CONFIG_PPS is not set
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_GPIOLIB=y
-# CONFIG_DEBUG_GPIO is not set
-# CONFIG_GPIO_SYSFS is not set
-
-#
-# Memory mapped GPIO expanders:
-#
-
-#
-# I2C GPIO expanders:
-#
-# CONFIG_GPIO_MAX732X is not set
-# CONFIG_GPIO_PCA953X is not set
-# CONFIG_GPIO_PCF857X is not set
-
-#
-# PCI GPIO expanders:
-#
-
-#
-# SPI GPIO expanders:
-#
-
-#
-# AC97 GPIO expanders:
-#
-# CONFIG_GPIO_PCA9554 is not set
-# CONFIG_IOEXTEND_TCA6424 is not set
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-# CONFIG_EXPAND_GPIO_SOFT_INTERRUPT is not set
-CONFIG_SPI_FPGA_GPIO_NUM=96
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=16
-# CONFIG_W1 is not set
-CONFIG_POWER_SUPPLY=y
-# CONFIG_POWER_SUPPLY_DEBUG is not set
-# CONFIG_PDA_POWER is not set
-# CONFIG_BATTERY_DS2760 is not set
-# CONFIG_BATTERY_DS2782 is not set
-# CONFIG_BATTERY_BQ27x00 is not set
-# CONFIG_BATTERY_MAX17040 is not set
-# CONFIG_BATTERY_STC3100 is not set
-CONFIG_BATTERY_BQ27510=y
-# CONFIG_BATTERY_BQ27541 is not set
-# CONFIG_BATTERY_BQ3060 is not set
-# CONFIG_CHECK_BATT_CAPACITY is not set
-CONFIG_NO_BATTERY_IC=y
-# CONFIG_HWMON is not set
-# CONFIG_THERMAL is not set
-# CONFIG_WATCHDOG is not set
-CONFIG_SSB_POSSIBLE=y
-
-#
-# Sonics Silicon Backplane
-#
-# CONFIG_SSB is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_CORE is not set
-# CONFIG_MFD_SM501 is not set
-# CONFIG_MFD_ASIC3 is not set
-# CONFIG_HTC_EGPIO is not set
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_TPS65010 is not set
-# CONFIG_TWL4030_CORE is not set
-# CONFIG_TPS65910_CORE is not set
-# CONFIG_MFD_TMIO is not set
-# CONFIG_MFD_T7L66XB is not set
-# CONFIG_MFD_TC6387XB is not set
-# CONFIG_MFD_TC6393XB is not set
-# CONFIG_PMIC_DA903X is not set
-# CONFIG_MFD_WM8400 is not set
-# CONFIG_MFD_WM831X_I2C is not set
-# CONFIG_MFD_WM8350_I2C is not set
-# CONFIG_MFD_PCF50633 is not set
-# CONFIG_AB3100_CORE is not set
-CONFIG_REGULATOR=y
-# CONFIG_REGULATOR_DEBUG is not set
-# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
-# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
-# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
-# CONFIG_REGULATOR_BQ24022 is not set
-# CONFIG_REGULATOR_MAX1586 is not set
-# CONFIG_REGULATOR_LP3971 is not set
-# CONFIG_REGULATOR_TPS65023 is not set
-# CONFIG_REGULATOR_TPS6507X is not set
-# CONFIG_RK2818_REGULATOR_CHARGE is not set
-# CONFIG_RK2818_REGULATOR_LP8725 is not set
-CONFIG_RK29_PWM_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
-
-#
-# Multimedia core support
-#
-CONFIG_VIDEO_DEV=y
-CONFIG_VIDEO_V4L2_COMMON=y
-CONFIG_VIDEO_ALLOW_V4L1=y
-CONFIG_VIDEO_V4L1_COMPAT=y
-# CONFIG_DVB_CORE is not set
-CONFIG_VIDEO_MEDIA=y
-
-#
-# Multimedia drivers
-#
-# CONFIG_MEDIA_ATTACH is not set
-CONFIG_MEDIA_TUNER=y
-# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
-CONFIG_MEDIA_TUNER_SIMPLE=y
-CONFIG_MEDIA_TUNER_TDA8290=y
-CONFIG_MEDIA_TUNER_TDA9887=y
-CONFIG_MEDIA_TUNER_TEA5761=y
-CONFIG_MEDIA_TUNER_TEA5767=y
-CONFIG_MEDIA_TUNER_MT20XX=y
-CONFIG_MEDIA_TUNER_XC2028=y
-CONFIG_MEDIA_TUNER_XC5000=y
-CONFIG_MEDIA_TUNER_MC44S803=y
-CONFIG_VIDEO_V4L2=y
-CONFIG_VIDEO_V4L1=y
-CONFIG_VIDEOBUF_GEN=y
-CONFIG_VIDEOBUF_DMA_CONTIG=y
-# CONFIG_VIDEO_RK29XX_VOUT is not set
-CONFIG_VIDEO_CAPTURE_DRIVERS=y
-# CONFIG_VIDEO_ADV_DEBUG is not set
-# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
-CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
-# CONFIG_VIDEO_VIVI is not set
-# CONFIG_VIDEO_CPIA is not set
-# CONFIG_VIDEO_CPIA2 is not set
-# CONFIG_VIDEO_SAA5246A is not set
-# CONFIG_VIDEO_SAA5249 is not set
-CONFIG_SOC_CAMERA=y
-# CONFIG_SOC_CAMERA_MT9M001 is not set
-# CONFIG_SOC_CAMERA_MT9M111 is not set
-# CONFIG_SOC_CAMERA_MT9M112 is not set
-# CONFIG_SOC_CAMERA_MT9T031 is not set
-# CONFIG_SOC_CAMERA_MT9T111 is not set
-# CONFIG_SOC_CAMERA_MT9P111 is not set
-# CONFIG_SOC_CAMERA_MT9D112 is not set
-# CONFIG_SOC_CAMERA_MT9D113 is not set
-# CONFIG_SOC_CAMERA_MT9V022 is not set
-# CONFIG_SOC_CAMERA_TW9910 is not set
-# CONFIG_SOC_CAMERA_PLATFORM is not set
-# CONFIG_SOC_CAMERA_OV772X is not set
-# CONFIG_SOC_CAMERA_OV7675 is not set
-# CONFIG_SOC_CAMERA_OV2655 is not set
-CONFIG_SOC_CAMERA_OV2659=y
-# CONFIG_SOC_CAMERA_OV9650 is not set
-# CONFIG_SOC_CAMERA_OV2640 is not set
-# CONFIG_SOC_CAMERA_OV3640 is not set
-CONFIG_SOC_CAMERA_OV5642=y
-CONFIG_OV5642_AUTOFOCUS=y
-# CONFIG_OV5642_FIXEDFOCUS is not set
-# CONFIG_SOC_CAMERA_OV5640 is not set
-# CONFIG_SOC_CAMERA_S5K6AA is not set
-# CONFIG_SOC_CAMERA_GT2005 is not set
-# CONFIG_SOC_CAMERA_GC0307 is not set
-# CONFIG_SOC_CAMERA_GC0308 is not set
-# CONFIG_SOC_CAMERA_GC0309 is not set
-# CONFIG_SOC_CAMERA_GC2015 is not set
-# CONFIG_SOC_CAMERA_HI253 is not set
-# CONFIG_SOC_CAMERA_HI704 is not set
-# CONFIG_SOC_CAMERA_SIV120B is not set
-# CONFIG_SOC_CAMERA_SID130B is not set
-# CONFIG_SOC_CAMERA_NT99250 is not set
-# CONFIG_VIDEO_SH_MOBILE_CEU is not set
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_WORK_ONEFRAME=y
-# CONFIG_VIDEO_RK29_WORK_PINGPONG is not set
-CONFIG_VIDEO_RK29_WORK_IPP=y
-# CONFIG_VIDEO_RK29_WORK_NOT_IPP is not set
-CONFIG_V4L_USB_DRIVERS=y
-# CONFIG_USB_VIDEO_CLASS is not set
-CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
-CONFIG_USB_GSPCA=m
-# CONFIG_USB_M5602 is not set
-# CONFIG_USB_STV06XX is not set
-# CONFIG_USB_GL860 is not set
-# CONFIG_USB_GSPCA_CONEX is not set
-# CONFIG_USB_GSPCA_ETOMS is not set
-# CONFIG_USB_GSPCA_FINEPIX is not set
-# CONFIG_USB_GSPCA_JEILINJ is not set
-# CONFIG_USB_GSPCA_MARS is not set
-# CONFIG_USB_GSPCA_MR97310A is not set
-# CONFIG_USB_GSPCA_OV519 is not set
-# CONFIG_USB_GSPCA_OV534 is not set
-# CONFIG_USB_GSPCA_PAC207 is not set
-# CONFIG_USB_GSPCA_PAC7311 is not set
-# CONFIG_USB_GSPCA_SN9C20X is not set
-# CONFIG_USB_GSPCA_SONIXB is not set
-# CONFIG_USB_GSPCA_SONIXJ is not set
-# CONFIG_USB_GSPCA_SPCA500 is not set
-# CONFIG_USB_GSPCA_SPCA501 is not set
-# CONFIG_USB_GSPCA_SPCA505 is not set
-# CONFIG_USB_GSPCA_SPCA506 is not set
-# CONFIG_USB_GSPCA_SPCA508 is not set
-# CONFIG_USB_GSPCA_SPCA561 is not set
-# CONFIG_USB_GSPCA_SQ905 is not set
-# CONFIG_USB_GSPCA_SQ905C is not set
-# CONFIG_USB_GSPCA_STK014 is not set
-# CONFIG_USB_GSPCA_SUNPLUS is not set
-# CONFIG_USB_GSPCA_T613 is not set
-# CONFIG_USB_GSPCA_TV8532 is not set
-# CONFIG_USB_GSPCA_VC032X is not set
-# CONFIG_USB_GSPCA_ZC3XX is not set
-# CONFIG_VIDEO_PVRUSB2 is not set
-# CONFIG_VIDEO_HDPVR is not set
-# CONFIG_VIDEO_EM28XX is not set
-# CONFIG_VIDEO_CX231XX is not set
-# CONFIG_VIDEO_USBVISION is not set
-# CONFIG_USB_VICAM is not set
-# CONFIG_USB_IBMCAM is not set
-# CONFIG_USB_KONICAWC is not set
-# CONFIG_USB_QUICKCAM_MESSENGER is not set
-# CONFIG_USB_ET61X251 is not set
-# CONFIG_VIDEO_OVCAMCHIP is not set
-# CONFIG_USB_OV511 is not set
-# CONFIG_USB_SE401 is not set
-# CONFIG_USB_SN9C102 is not set
-# CONFIG_USB_STV680 is not set
-# CONFIG_USB_ZC0301 is not set
-# CONFIG_USB_PWC is not set
-CONFIG_USB_PWC_INPUT_EVDEV=y
-# CONFIG_USB_ZR364XX is not set
-# CONFIG_USB_STKWEBCAM is not set
-# CONFIG_USB_S2255 is not set
-CONFIG_RADIO_ADAPTERS=y
-# CONFIG_I2C_SI4713 is not set
-# CONFIG_RADIO_SI4713 is not set
-# CONFIG_USB_DSBR is not set
-# CONFIG_RADIO_SI470X is not set
-# CONFIG_USB_MR800 is not set
-# CONFIG_RADIO_TEA5764 is not set
-# CONFIG_SMS_SIANO_MDTV is not set
-# CONFIG_DAB is not set
-
-#
-# Graphics support
-#
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-CONFIG_FB=y
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB_DDC is not set
-# CONFIG_FB_BOOT_VESA_SUPPORT is not set
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-# CONFIG_FB_SYS_FILLRECT is not set
-# CONFIG_FB_SYS_COPYAREA is not set
-# CONFIG_FB_SYS_IMAGEBLIT is not set
-# CONFIG_FB_FOREIGN_ENDIAN is not set
-# CONFIG_FB_SYS_FOPS is not set
-# CONFIG_FB_SVGALIB is not set
-# CONFIG_FB_MACMODES is not set
-# CONFIG_FB_BACKLIGHT is not set
-# CONFIG_FB_MODE_HELPERS is not set
-# CONFIG_FB_TILEBLITTING is not set
-
-#
-# Frame buffer hardware drivers
-#
-# CONFIG_FB_S1D13XXX is not set
-# CONFIG_FB_RK2818 is not set
-CONFIG_FB_RK29=y
-CONFIG_FB_WORK_IPP=y
-CONFIG_FB_SCALING_OSD=y
-# CONFIG_FB_ROTATE_VIDEO is not set
-CONFIG_CLOSE_WIN1_DYNAMIC=y
-# CONFIG_FB_VIRTUAL is not set
-# CONFIG_FB_METRONOME is not set
-# CONFIG_FB_MB862XX is not set
-# CONFIG_FB_BROADSHEET is not set
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_BACKLIGHT_RK29_BL=y
-# CONFIG_FIH_TOUCHKEY_LED is not set
-# CONFIG_BACKLIGHT_AW9364 is not set
-# CONFIG_BUTTON_LIGHT is not set
-
-#
-# Display device support
-#
-CONFIG_DISPLAY_SUPPORT=y
-
-#
-# Display hardware drivers
-#
-# CONFIG_LCD_NULL is not set
-# CONFIG_LCD_TD043MGEA1 is not set
-# CONFIG_LCD_HX8357 is not set
-# CONFIG_LCD_TJ048NC01CA is not set
-# CONFIG_LCD_HL070VM4AU is not set
-# CONFIG_LCD_HSD070IDW1 is not set
-# CONFIG_LCD_RGB_TFT480800_25_E is not set
-CONFIG_LCD_HSD100PXN=y
-# CONFIG_LCD_HSD07PFW1 is not set
-# CONFIG_LCD_BYD8688FTGF is not set
-# CONFIG_LCD_B101AW06 is not set
-# CONFIG_LCD_LS035Y8DX02A is not set
-# CONFIG_LCD_CPTCLAA038LA31XE is not set
-# CONFIG_LCD_A060SE02 is not set
-# CONFIG_LCD_S1D13521 is not set
-# CONFIG_LCD_NT35582 is not set
-# CONFIG_LCD_NT35580 is not set
-# CONFIG_LCD_IPS1P5680_V1_E is not set
-# CONFIG_LCD_MCU_TFT480800_25_E is not set
-# CONFIG_LCD_NT35510 is not set
-# CONFIG_LCD_ILI9803_CPT4_3 is not set
-# CONFIG_DEFAULT_OUT_HDMI is not set
-# CONFIG_LCD_AT070TNA2 is not set
-# CONFIG_LCD_AT070TN93 is not set
-# CONFIG_LCD_TX23D88VM is not set
-
-#
-# HDMI
-#
-CONFIG_HDMI=y
-CONFIG_ANX7150=y
-# CONFIG_ANX9030 is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE is not set
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_LOGO_LINUX_CLUT224=y
-# CONFIG_LOGO_CHARGER_CLUT224 is not set
-CONFIG_SOUND=y
-# CONFIG_SOUND_OSS_CORE is not set
-CONFIG_SND=y
-CONFIG_SND_TIMER=y
-CONFIG_SND_PCM=y
-CONFIG_SND_JACK=y
-# CONFIG_SND_SEQUENCER is not set
-# CONFIG_SND_MIXER_OSS is not set
-# CONFIG_SND_PCM_OSS is not set
-# CONFIG_SND_HRTIMER is not set
-# CONFIG_SND_DYNAMIC_MINORS is not set
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_VERBOSE_PRINTK is not set
-# CONFIG_SND_DEBUG is not set
-# CONFIG_SND_RAWMIDI_SEQ is not set
-# CONFIG_SND_OPL3_LIB_SEQ is not set
-# CONFIG_SND_OPL4_LIB_SEQ is not set
-# CONFIG_SND_SBAWE_SEQ is not set
-# CONFIG_SND_EMU10K1_SEQ is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_USB=y
-# CONFIG_SND_USB_AUDIO is not set
-# CONFIG_SND_USB_CAIAQ is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_RK29_SOC_I2S=y
-# CONFIG_SND_RK29_SOC_I2S_2CH is not set
-CONFIG_SND_RK29_SOC_I2S_8CH=y
-# CONFIG_SND_RK29_SOC_WM8988 is not set
-CONFIG_SND_RK29_SOC_WM8900=y
-# CONFIG_SND_RK29_SOC_alc5621 is not set
-# CONFIG_SND_RK29_SOC_alc5631 is not set
-# CONFIG_SND_RK29_SOC_RT5625 is not set
-# CONFIG_SND_RK29_SOC_WM8994 is not set
-# CONFIG_SND_RK29_SOC_CS42L52 is not set
-# CONFIG_SND_RK29_CODEC_SOC_MASTER is not set
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_SND_SOC_I2C_AND_SPI=y
-# CONFIG_SND_SOC_ALL_CODECS is not set
-CONFIG_SND_SOC_WM8900=y
-# CONFIG_SOUND_PRIME is not set
-CONFIG_HID_SUPPORT=y
-CONFIG_HID=y
-# CONFIG_HIDRAW is not set
-
-#
-# USB Input Devices
-#
-CONFIG_USB_HID=y
-# CONFIG_HID_PID is not set
-# CONFIG_USB_HIDDEV is not set
-
-#
-# Special HID drivers
-#
-# CONFIG_HID_A4TECH is not set
-# CONFIG_HID_APPLE is not set
-# CONFIG_HID_BELKIN is not set
-# CONFIG_HID_CHERRY is not set
-# CONFIG_HID_CHICONY is not set
-# CONFIG_HID_CYPRESS is not set
-# CONFIG_HID_DRAGONRISE is not set
-# CONFIG_HID_EZKEY is not set
-# CONFIG_HID_KYE is not set
-# CONFIG_HID_GYRATION is not set
-# CONFIG_HID_TWINHAN is not set
-# CONFIG_HID_KENSINGTON is not set
-# CONFIG_HID_LOGITECH is not set
-# CONFIG_HID_MICROSOFT is not set
-# CONFIG_HID_MONTEREY is not set
-# CONFIG_HID_NTRIG is not set
-# CONFIG_HID_PANTHERLORD is not set
-# CONFIG_HID_PETALYNX is not set
-# CONFIG_HID_SAMSUNG is not set
-# CONFIG_HID_SONY is not set
-# CONFIG_HID_SUNPLUS is not set
-# CONFIG_HID_GREENASIA is not set
-# CONFIG_HID_SMARTJOYPLUS is not set
-# CONFIG_HID_TOPSEED is not set
-# CONFIG_HID_THRUSTMASTER is not set
-# CONFIG_HID_ZEROPLUS is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ARCH_HAS_HCD=y
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-CONFIG_USB=y
-# CONFIG_USB_DEBUG is not set
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-
-#
-# Miscellaneous USB options
-#
-# CONFIG_USB_DEVICEFS is not set
-CONFIG_USB_DEVICE_CLASS=y
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_SUSPEND is not set
-# CONFIG_USB_OTG is not set
-# CONFIG_USB_OTG_WHITELIST is not set
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-# CONFIG_USB_MON is not set
-# CONFIG_USB_WUSB is not set
-# CONFIG_USB_WUSB_CBAF is not set
-
-#
-# USB Host Controller Drivers
-#
-# CONFIG_USB_C67X00_HCD is not set
-# CONFIG_USB_OXU210HP_HCD is not set
-# CONFIG_USB_ISP116X_HCD is not set
-# CONFIG_USB_ISP1760_HCD is not set
-# CONFIG_USB_ISP1362_HCD is not set
-# CONFIG_USB_SL811_HCD is not set
-# CONFIG_USB_R8A66597_HCD is not set
-# CONFIG_USB_HWA_HCD is not set
-# CONFIG_USB_MUSB_HDRC is not set
-# CONFIG_USB_GADGET_MUSB_HDRC is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-# CONFIG_USB_WDM is not set
-# CONFIG_USB_TMC is not set
-
-#
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
-#
-
-#
-# also be needed; see USB_STORAGE Help for more info
-#
-CONFIG_USB_STORAGE=y
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_USBAT is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_STORAGE_SDDR55 is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_ALAUDA is not set
-# CONFIG_USB_STORAGE_ONETOUCH is not set
-# CONFIG_USB_STORAGE_KARMA is not set
-# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_MICROTEK is not set
-
-#
-# USB port drivers
-#
-CONFIG_USB_SERIAL=y
-# CONFIG_USB_SERIAL_CONSOLE is not set
-# CONFIG_USB_EZUSB is not set
-CONFIG_USB_SERIAL_GENERIC=y
-# CONFIG_USB_SERIAL_AIRCABLE is not set
-# CONFIG_USB_SERIAL_ARK3116 is not set
-# CONFIG_USB_SERIAL_BELKIN is not set
-# CONFIG_USB_SERIAL_CH341 is not set
-# CONFIG_USB_SERIAL_WHITEHEAT is not set
-# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
-# CONFIG_USB_SERIAL_CP210X is not set
-# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
-# CONFIG_USB_SERIAL_EMPEG is not set
-# CONFIG_USB_SERIAL_FTDI_SIO is not set
-# CONFIG_USB_SERIAL_FUNSOFT is not set
-# CONFIG_USB_SERIAL_VISOR is not set
-# CONFIG_USB_SERIAL_IPAQ is not set
-# CONFIG_USB_SERIAL_IR is not set
-# CONFIG_USB_SERIAL_EDGEPORT is not set
-# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
-# CONFIG_USB_SERIAL_GARMIN is not set
-# CONFIG_USB_SERIAL_IPW is not set
-# CONFIG_USB_SERIAL_IUU is not set
-# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
-# CONFIG_USB_SERIAL_KEYSPAN is not set
-# CONFIG_USB_SERIAL_KLSI is not set
-# CONFIG_USB_SERIAL_KOBIL_SCT is not set
-# CONFIG_USB_SERIAL_MCT_U232 is not set
-# CONFIG_USB_SERIAL_MOS7720 is not set
-# CONFIG_USB_SERIAL_MOS7840 is not set
-# CONFIG_USB_SERIAL_MOTOROLA is not set
-# CONFIG_USB_SERIAL_NAVMAN is not set
-# CONFIG_USB_SERIAL_PL2303 is not set
-# CONFIG_USB_SERIAL_OTI6858 is not set
-# CONFIG_USB_SERIAL_QUALCOMM is not set
-# CONFIG_USB_SERIAL_SPCP8X5 is not set
-# CONFIG_USB_SERIAL_HP4X is not set
-# CONFIG_USB_SERIAL_SAFE is not set
-# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
-# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
-# CONFIG_USB_SERIAL_SYMBOL is not set
-# CONFIG_USB_SERIAL_TI is not set
-# CONFIG_USB_SERIAL_CYBERJACK is not set
-# CONFIG_USB_SERIAL_XIRCOM is not set
-CONFIG_USB_SERIAL_OPTION=y
-# CONFIG_USB_SERIAL_OMNINET is not set
-# CONFIG_USB_SERIAL_OPTICON is not set
-# CONFIG_USB_SERIAL_DEBUG is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_SEVSEG is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_BERRY_CHARGE is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYPRESS_CY7C63 is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_FTDI_ELAN is not set
-# CONFIG_USB_APPLEDISPLAY is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TRANCEVIBRATOR is not set
-# CONFIG_USB_IOWARRIOR is not set
-# CONFIG_USB_TEST is not set
-# CONFIG_USB_ISIGHTFW is not set
-# CONFIG_USB_VST is not set
-CONFIG_USB_GADGET=y
-# CONFIG_USB_GADGET_DEBUG is not set
-# CONFIG_USB_GADGET_DEBUG_FILES is not set
-CONFIG_USB_GADGET_VBUS_DRAW=2
-CONFIG_USB_GADGET_SELECTED=y
-# CONFIG_USB_GADGET_AT91 is not set
-# CONFIG_USB_GADGET_ATMEL_USBA is not set
-# CONFIG_USB_GADGET_FSL_USB2 is not set
-# CONFIG_USB_GADGET_LH7A40X is not set
-# CONFIG_USB_GADGET_OMAP is not set
-# CONFIG_USB_GADGET_PXA25X is not set
-# CONFIG_USB_GADGET_R8A66597 is not set
-# CONFIG_USB_GADGET_PXA27X is not set
-# CONFIG_USB_GADGET_S3C_HSOTG is not set
-# CONFIG_USB_GADGET_IMX is not set
-# CONFIG_USB_GADGET_S3C2410 is not set
-# CONFIG_USB_GADGET_M66592 is not set
-# CONFIG_USB_GADGET_AMD5536UDC is not set
-# CONFIG_USB_GADGET_FSL_QE is not set
-# CONFIG_USB_GADGET_CI13XXX is not set
-# CONFIG_USB_GADGET_NET2280 is not set
-# CONFIG_USB_GADGET_GOKU is not set
-# CONFIG_USB_GADGET_LANGWELL is not set
-CONFIG_USB_GADGET_DWC_OTG=y
-CONFIG_USB_DWC_OTG=y
-# CONFIG_USB_GADGET_DUMMY_HCD is not set
-CONFIG_USB_GADGET_DUALSPEED=y
-# CONFIG_USB_ZERO is not set
-# CONFIG_USB_AUDIO is not set
-# CONFIG_USB_ETH is not set
-# CONFIG_USB_GADGETFS is not set
-# CONFIG_USB_FILE_STORAGE is not set
-# CONFIG_USB_G_SERIAL is not set
-# CONFIG_USB_MIDI_GADGET is not set
-# CONFIG_USB_G_PRINTER is not set
-CONFIG_USB_ANDROID=y
-# CONFIG_USB_ANDROID_ACM is not set
-CONFIG_USB_ANDROID_ADB=y
-CONFIG_USB_ANDROID_MASS_STORAGE=y
-# CONFIG_USB_ANDROID_RNDIS is not set
-# CONFIG_USB_CDC_COMPOSITE is not set
-
-#
-# OTG and related infrastructure
-#
-# CONFIG_USB_GPIO_VBUS is not set
-# CONFIG_NOP_USB_XCEIV is not set
-# CONFIG_USB11_HOST is not set
-CONFIG_USB20_HOST=y
-CONFIG_USB20_HOST_EN=y
-CONFIG_USB20_OTG=y
-# CONFIG_DWC_OTG_HOST_ONLY is not set
-CONFIG_DWC_OTG_DEVICE_ONLY=y
-# CONFIG_DWC_OTG_BOTH_HOST_SLAVE is not set
-CONFIG_DWC_CONN_EN=y
-# CONFIG_DWC_OTG_DEBUG is not set
-# CONFIG_DWC_REMOTE_WAKEUP is not set
-CONFIG_DWC_OTG=y
-CONFIG_MMC=y
-# CONFIG_MMC_DEBUG is not set
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-
-#
-# MMC/SD/SDIO Card Drivers
-#
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_BLOCK_BOUNCE=y
-# CONFIG_MMC_BLOCK_DEFERRED_RESUME is not set
-# CONFIG_SDIO_UART is not set
-# CONFIG_MMC_TEST is not set
-
-#
-# MMC/SD/SDIO Host Controller Drivers
-#
-CONFIG_SDMMC_RK29=y
-
-#
-# Now, there are two SDMMC controllers selected, SDMMC0 and SDMMC1.
-#
-# CONFIG_SDMMC_RK29_OLD is not set
-CONFIG_SDMMC0_RK29=y
-CONFIG_SDMMC1_RK29=y
-# CONFIG_MMC_SDHCI is not set
-# CONFIG_MMC_AT91 is not set
-# CONFIG_MMC_ATMELMCI is not set
-# CONFIG_MEMSTICK is not set
-# CONFIG_NEW_LEDS is not set
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-# CONFIG_ACCESSIBILITY is not set
-CONFIG_RTC_LIB=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HCTOSYS=y
-CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-# CONFIG_RTC_DEBUG is not set
-
-#
-# RTC interfaces
-#
-CONFIG_RTC_INTF_SYSFS=y
-CONFIG_RTC_INTF_PROC=y
-CONFIG_RTC_INTF_DEV=y
-# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-CONFIG_RTC_INTF_ALARM=y
-CONFIG_RTC_INTF_ALARM_DEV=y
-# CONFIG_RTC_DRV_TEST is not set
-
-#
-# I2C RTC drivers
-#
-CONFIG_RTC_HYM8563=y
-# CONFIG_RTC_M41T66 is not set
-# CONFIG_RTC_DRV_DS1307 is not set
-# CONFIG_RTC_DRV_DS1374 is not set
-# CONFIG_RTC_DRV_DS1672 is not set
-# CONFIG_RTC_DRV_MAX6900 is not set
-# CONFIG_RTC_DRV_RS5C372 is not set
-# CONFIG_RTC_DRV_ISL1208 is not set
-# CONFIG_RTC_DRV_X1205 is not set
-# CONFIG_RTC_DRV_PCF8563 is not set
-# CONFIG_RTC_DRV_PCF8583 is not set
-# CONFIG_RTC_DRV_M41T80 is not set
-# CONFIG_RTC_DRV_S35390A is not set
-# CONFIG_RTC_DRV_S35392A is not set
-# CONFIG_RTC_DRV_FM3130 is not set
-# CONFIG_RTC_DRV_RX8581 is not set
-# CONFIG_RTC_DRV_RX8025 is not set
-
-#
-# SPI RTC drivers
-#
-
-#
-# Platform RTC drivers
-#
-# CONFIG_RTC_DRV_CMOS is not set
-# CONFIG_RTC_DRV_DS1286 is not set
-# CONFIG_RTC_DRV_DS1511 is not set
-# CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_DS1742 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
-# CONFIG_RTC_DRV_M48T86 is not set
-# CONFIG_RTC_DRV_M48T35 is not set
-# CONFIG_RTC_DRV_M48T59 is not set
-# CONFIG_RTC_DRV_BQ4802 is not set
-# CONFIG_RTC_DRV_V3020 is not set
-
-#
-# on-CPU RTC drivers
-#
-# CONFIG_DMADEVICES is not set
-# CONFIG_AUXDISPLAY is not set
-# CONFIG_UIO is not set
-
-#
-# TI VLYNQ
-#
-CONFIG_STAGING=y
-# CONFIG_STAGING_EXCLUDE_BUILD is not set
-# CONFIG_USB_IP_COMMON is not set
-# CONFIG_PRISM2_USB is not set
-# CONFIG_ECHO is not set
-# CONFIG_COMEDI is not set
-# CONFIG_ASUS_OLED is not set
-# CONFIG_TRANZPORT is not set
-
-#
-# Android
-#
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_RAM_CONSOLE=y
-CONFIG_ANDROID_RAM_CONSOLE_ENABLE_VERBOSE=y
-CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION=y
-CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_DATA_SIZE=128
-CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_ECC_SIZE=16
-CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_SYMBOL_SIZE=8
-CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_POLYNOMIAL=0x11d
-# CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT is not set
-CONFIG_ANDROID_TIMED_OUTPUT=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_DST is not set
-# CONFIG_POHMELFS is not set
-# CONFIG_PLAN9AUTH is not set
-# CONFIG_LINE6_USB is not set
-# CONFIG_USB_SERIAL_QUATECH2 is not set
-# CONFIG_USB_SERIAL_QUATECH_USB2 is not set
-# CONFIG_VT6656 is not set
-# CONFIG_FB_UDL is not set
-
-#
-# RAR Register Driver
-#
-# CONFIG_RAR_REGISTER is not set
-# CONFIG_IIO is not set
-
-#
-# GPU Vivante
-#
-CONFIG_VIVANTE=y
-
-#
-# IPP
-#
-CONFIG_RK29_IPP=y
-
-#
-# CMMB
-#
-# CONFIG_CMMB is not set
-# CONFIG_TEST_CODE is not set
-# CONFIG_RK29_SMC is not set
-
-#
-# CIR support
-#
-# CONFIG_RK_CIR is not set
-
-#
-# File systems
-#
-# CONFIG_EXT2_FS is not set
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_EXT4_DEBUG is not set
-CONFIG_JBD=y
-CONFIG_JBD2=y
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
-# CONFIG_XFS_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_BTRFS_FS is not set
-# CONFIG_NILFS2_FS is not set
-CONFIG_FILE_LOCKING=y
-CONFIG_FSNOTIFY=y
-# CONFIG_DNOTIFY is not set
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-CONFIG_FUSE_FS=y
-# CONFIG_CUSE is not set
-
-#
-# Caches
-#
-# CONFIG_FSCACHE is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=y
-# CONFIG_MSDOS_FS is not set
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-# CONFIG_HUGETLB_PAGE is not set
-# CONFIG_CONFIGFS_FS is not set
-CONFIG_MISC_FILESYSTEMS=y
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_YAFFS_FS is not set
-# CONFIG_JFFS2_FS is not set
-CONFIG_CRAMFS=y
-# CONFIG_SQUASHFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_OMFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-
-#
-# Partition Types
-#
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_MSDOS_PARTITION=y
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-1"
-CONFIG_NLS_CODEPAGE_437=y
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-CONFIG_NLS_CODEPAGE_850=y
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-CONFIG_NLS_CODEPAGE_936=y
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ASCII is not set
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-CONFIG_NLS_ISO8859_15=y
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-CONFIG_NLS_UTF8=y
-# CONFIG_DLM is not set
-
-#
-# Kernel hacking
-#
-CONFIG_PRINTK_TIME=y
-CONFIG_ENABLE_WARN_DEPRECATED=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_FRAME_WARN=1024
-CONFIG_MAGIC_SYSRQ=y
-# CONFIG_STRIP_ASM_SYMS is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-CONFIG_DETECT_HUNG_TASK=y
-# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
-CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
-CONFIG_SCHEDSTATS=y
-CONFIG_TIMER_STATS=y
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_KMEMLEAK is not set
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_PROVE_LOCKING is not set
-# CONFIG_LOCK_STAT is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
-# CONFIG_DEBUG_HIGHMEM is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_WRITECOUNT is not set
-# CONFIG_DEBUG_MEMORY_INIT is not set
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_DEBUG_NOTIFIERS is not set
-# CONFIG_DEBUG_CREDENTIALS is not set
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_RCU_TORTURE_TEST is not set
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_BACKTRACE_SELF_TEST is not set
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
-# CONFIG_FAULT_INJECTION is not set
-# CONFIG_LATENCYTOP is not set
-# CONFIG_PAGE_POISONING is not set
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_TRACING_SUPPORT=y
-# CONFIG_FTRACE is not set
-# CONFIG_SAMPLES is not set
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_KGDB is not set
-CONFIG_ARM_UNWIND=y
-# CONFIG_DEBUG_USER is not set
-CONFIG_DEBUG_ERRORS=y
-# CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_DEBUG_LL is not set
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-# CONFIG_SECURITYFS is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_ALGAPI2=y
-CONFIG_CRYPTO_AEAD=y
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_BLKCIPHER=y
-CONFIG_CRYPTO_BLKCIPHER2=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_PCOMP=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-# CONFIG_CRYPTO_GF128MUL is not set
-# CONFIG_CRYPTO_NULL is not set
-CONFIG_CRYPTO_WORKQUEUE=y
-# CONFIG_CRYPTO_CRYPTD is not set
-CONFIG_CRYPTO_AUTHENC=y
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Authenticated Encryption with Associated Data
-#
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_SEQIV is not set
-
-#
-# Block modes
-#
-CONFIG_CRYPTO_CBC=y
-# CONFIG_CRYPTO_CTR is not set
-# CONFIG_CRYPTO_CTS is not set
-CONFIG_CRYPTO_ECB=y
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_PCBC is not set
-# CONFIG_CRYPTO_XTS is not set
-
-#
-# Hash modes
-#
-CONFIG_CRYPTO_HMAC=y
-# CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_VMAC is not set
-
-#
-# Digest
-#
-CONFIG_CRYPTO_CRC32C=y
-# CONFIG_CRYPTO_GHASH is not set
-# CONFIG_CRYPTO_MD4 is not set
-CONFIG_CRYPTO_MD5=y
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_RMD128 is not set
-# CONFIG_CRYPTO_RMD160 is not set
-# CONFIG_CRYPTO_RMD256 is not set
-# CONFIG_CRYPTO_RMD320 is not set
-CONFIG_CRYPTO_SHA1=y
-# CONFIG_CRYPTO_SHA256 is not set
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_WP512 is not set
-
-#
-# Ciphers
-#
-# CONFIG_CRYPTO_AES is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-CONFIG_CRYPTO_ARC4=y
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-CONFIG_CRYPTO_DES=y
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_SALSA20 is not set
-# CONFIG_CRYPTO_SEED is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_TEA is not set
-CONFIG_CRYPTO_TWOFISH=y
-CONFIG_CRYPTO_TWOFISH_COMMON=y
-
-#
-# Compression
-#
-CONFIG_CRYPTO_DEFLATE=y
-# CONFIG_CRYPTO_ZLIB is not set
-# CONFIG_CRYPTO_LZO is not set
-
-#
-# Random Number Generation
-#
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRYPTO_HW=y
-# CONFIG_BINARY_PRINTF is not set
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-CONFIG_GENERIC_FIND_LAST_BIT=y
-CONFIG_CRC_CCITT=y
-CONFIG_CRC16=y
-# CONFIG_CRC_T10DIF is not set
-# CONFIG_CRC_ITU_T is not set
-CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
-CONFIG_LIBCRC32C=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_REED_SOLOMON=y
-CONFIG_REED_SOLOMON_ENC8=y
-CONFIG_REED_SOLOMON_DEC8=y
-CONFIG_TEXTSEARCH=y
-CONFIG_TEXTSEARCH_KMP=y
-CONFIG_TEXTSEARCH_BM=y
-CONFIG_TEXTSEARCH_FSM=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
-CONFIG_NLATTR=y
+++ /dev/null
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.32.27
-# Wed Dec 29 11:44:27 2010
-#
-CONFIG_ARM=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_TIME=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-CONFIG_ARCH_HAS_CPUFREQ=y
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-CONFIG_CONSTRUCTORS=y
-
-#
-# General setup
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_LOCK_KERNEL=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_LOCALVERSION=""
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-# CONFIG_SYSVIPC is not set
-# CONFIG_POSIX_MQUEUE is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_AUDIT is not set
-
-#
-# RCU Subsystem
-#
-CONFIG_TREE_RCU=y
-# CONFIG_TREE_PREEMPT_RCU is not set
-# CONFIG_RCU_TRACE is not set
-CONFIG_RCU_FANOUT=32
-# CONFIG_RCU_FANOUT_EXACT is not set
-# CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_IKCONFIG is not set
-CONFIG_LOG_BUF_SHIFT=17
-CONFIG_GROUP_SCHED=y
-CONFIG_FAIR_GROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-# CONFIG_USER_SCHED is not set
-CONFIG_CGROUP_SCHED=y
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-# CONFIG_CGROUP_NS is not set
-CONFIG_CGROUP_FREEZER=y
-# CONFIG_CGROUP_DEVICE is not set
-# CONFIG_CPUSETS is not set
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-# CONFIG_CGROUP_MEM_RES_CTLR is not set
-# CONFIG_SYSFS_DEPRECATED_V2 is not set
-# CONFIG_RELAY is not set
-# CONFIG_NAMESPACES is not set
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_RD_GZIP=y
-# CONFIG_RD_BZIP2 is not set
-# CONFIG_RD_LZMA is not set
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL=y
-CONFIG_ANON_INODES=y
-CONFIG_PANIC_TIMEOUT=5
-CONFIG_EMBEDDED=y
-CONFIG_UID16=y
-# CONFIG_SYSCTL_SYSCALL is not set
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-# CONFIG_ELF_CORE is not set
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_ASHMEM=y
-CONFIG_AIO=y
-
-#
-# Kernel Performance Events And Counters
-#
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_COMPAT_BRK=y
-CONFIG_SLAB=y
-# CONFIG_SLUB is not set
-# CONFIG_SLOB is not set
-# CONFIG_PROFILING is not set
-CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_CLK=y
-
-#
-# GCOV-based kernel profiling
-#
-# CONFIG_SLOW_WORK is not set
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_SLABINFO=y
-CONFIG_RT_MUTEXES=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-# CONFIG_MODULE_FORCE_LOAD is not set
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_MODVERSIONS is not set
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_BLOCK=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_BLK_DEV_INTEGRITY is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-# CONFIG_IOSCHED_AS is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_IOSCHED_CFQ=y
-# CONFIG_DEFAULT_AS is not set
-# CONFIG_DEFAULT_DEADLINE is not set
-CONFIG_DEFAULT_CFQ=y
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="cfq"
-CONFIG_FREEZER=y
-
-#
-# System Type
-#
-CONFIG_MMU=y
-# CONFIG_ARCH_AAEC2000 is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_GEMINI is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_MXC is not set
-# CONFIG_ARCH_STMP3XXX is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_NOMADIK is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP23XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_L7200 is not set
-# CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_LOKI is not set
-# CONFIG_ARCH_MV78XX0 is not set
-# CONFIG_ARCH_ORION5X is not set
-# CONFIG_ARCH_MMP is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
-# CONFIG_ARCH_W90X900 is not set
-# CONFIG_ARCH_PNX4008 is not set
-# CONFIG_ARCH_PXA is not set
-# CONFIG_ARCH_MSM is not set
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_S3C64XX is not set
-# CONFIG_ARCH_S5PC1XX is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_U300 is not set
-# CONFIG_ARCH_DAVINCI is not set
-# CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_BCMRING is not set
-# CONFIG_ARCH_RK2818 is not set
-CONFIG_ARCH_RK29=y
-CONFIG_WIFI_CONTROL_FUNC=y
-CONFIG_MACH_RK29SDK=y
-# CONFIG_MACH_RK29WINACCORD is not set
-# CONFIG_MACH_RK29_AIGO is not set
-CONFIG_RK29_MEM_SIZE_M=512
-
-#
-# RK29 VPU (Video Processing Unit) support
-#
-CONFIG_RK29_VPU=y
-# CONFIG_RK29_VPU_DEBUG is not set
-
-#
-# Processor Type
-#
-CONFIG_CPU_32=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_V7=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_THUMBEE=y
-# CONFIG_CPU_ICACHE_DISABLE is not set
-# CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_HAS_TLS_REG=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-# CONFIG_ARM_ERRATA_430973 is not set
-# CONFIG_ARM_ERRATA_458693 is not set
-# CONFIG_ARM_ERRATA_460075 is not set
-CONFIG_ARM_GIC=y
-CONFIG_PL330=y
-CONFIG_COMMON_CLKDEV=y
-
-#
-# Bus support
-#
-# CONFIG_PCI_SYSCALL is not set
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-# CONFIG_PCCARD is not set
-
-#
-# Kernel Features
-#
-CONFIG_TICK_ONESHOT=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_VMSPLIT_3G=y
-# CONFIG_VMSPLIT_2G is not set
-# CONFIG_VMSPLIT_1G is not set
-CONFIG_PAGE_OFFSET=0xC0000000
-# CONFIG_PREEMPT_NONE is not set
-# CONFIG_PREEMPT_VOLUNTARY is not set
-CONFIG_PREEMPT=y
-CONFIG_HZ=100
-# CONFIG_THUMB2_KERNEL is not set
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_HIGHMEM is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_SPLIT_PTLOCK_CPUS=4
-# CONFIG_PHYS_ADDR_T_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=0
-CONFIG_VIRT_TO_BUS=y
-CONFIG_HAVE_MLOCK=y
-CONFIG_HAVE_MLOCKED_PAGE_BIT=y
-# CONFIG_KSM is not set
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_UACCESS_WITH_MEMCPY is not set
-
-#
-# Boot options
-#
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_CMDLINE=""
-# CONFIG_XIP_KERNEL is not set
-CONFIG_KEXEC=y
-CONFIG_ATAGS_PROC=y
-
-#
-# CPU Power Management
-#
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_TABLE=y
-# CONFIG_CPU_FREQ_DEBUG is not set
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_FREQ_STAT_DETAILS=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-# CONFIG_CPU_IDLE is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_NEON=y
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-CONFIG_HAVE_AOUT=y
-# CONFIG_BINFMT_AOUT is not set
-# CONFIG_BINFMT_MISC is not set
-
-#
-# Power management options
-#
-CONFIG_PM=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_SLEEP=y
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_HAS_WAKELOCK=y
-CONFIG_HAS_EARLYSUSPEND=y
-CONFIG_WAKELOCK=y
-CONFIG_WAKELOCK_STAT=y
-CONFIG_USER_WAKELOCK=y
-CONFIG_EARLYSUSPEND=y
-# CONFIG_NO_USER_SPACE_SCREEN_ACCESS_CONTROL is not set
-CONFIG_CONSOLE_EARLYSUSPEND=y
-# CONFIG_FB_EARLYSUSPEND is not set
-# CONFIG_APM_EMULATION is not set
-# CONFIG_PM_RUNTIME is not set
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
-# CONFIG_XFRM_STATISTICS is not set
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=y
-CONFIG_INET_XFRM_MODE_TUNNEL=y
-CONFIG_INET_XFRM_MODE_BEET=y
-# CONFIG_INET_LRO is not set
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-# CONFIG_IPV6 is not set
-CONFIG_ANDROID_PARANOID_NETWORK=y
-# CONFIG_NETWORK_SECMARK is not set
-# CONFIG_NETFILTER is not set
-# CONFIG_IP_DCCP is not set
-# CONFIG_IP_SCTP is not set
-# CONFIG_RDS is not set
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_NET_DSA is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-# CONFIG_PHONET is not set
-# CONFIG_IEEE802154 is not set
-# CONFIG_NET_SCHED is not set
-# CONFIG_DCB is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_CAN is not set
-# CONFIG_IRDA is not set
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-# CONFIG_BT_BNEP is not set
-# CONFIG_BT_HIDP is not set
-
-#
-# Bluetooth device drivers
-#
-# CONFIG_BT_HCIBTUSB is not set
-# CONFIG_BT_HCIBTSDIO is not set
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-# CONFIG_BT_HCIUART_BCSP is not set
-# CONFIG_BT_HCIUART_LL is not set
-# CONFIG_BT_HCIBCM203X is not set
-# CONFIG_BT_HCIBPA10X is not set
-# CONFIG_BT_HCIBFUSB is not set
-# CONFIG_BT_HCIVHCI is not set
-# CONFIG_BT_MRVL is not set
-CONFIG_BT_HCIBCM4325=y
-# CONFIG_AF_RXRPC is not set
-CONFIG_WIRELESS=y
-# CONFIG_CFG80211 is not set
-CONFIG_CFG80211_DEFAULT_PS_VALUE=0
-# CONFIG_WIRELESS_OLD_REGULATORY is not set
-CONFIG_WIRELESS_EXT=y
-CONFIG_WIRELESS_EXT_SYSFS=y
-# CONFIG_LIB80211 is not set
-
-#
-# CFG80211 needs to be enabled for MAC80211
-#
-
-#
-# Some wireless drivers require a rate control algorithm
-#
-# CONFIG_WIMAX is not set
-CONFIG_RFKILL=y
-# CONFIG_RFKILL_PM is not set
-# CONFIG_RFKILL_INPUT is not set
-# CONFIG_NET_9P is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_CONNECTOR is not set
-CONFIG_MTD=y
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_TESTS is not set
-# CONFIG_MTD_CONCAT is not set
-CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_REDBOOT_PARTS is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_AFS_PARTS is not set
-# CONFIG_MTD_AR7_PARTS is not set
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
-# CONFIG_INFTL is not set
-# CONFIG_RFD_FTL is not set
-# CONFIG_SSFDC is not set
-# CONFIG_MTD_OOPS is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-# CONFIG_MTD_CFI is not set
-# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_ABSENT is not set
-
-#
-# Mapping drivers for chip access
-#
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_PLATRAM is not set
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLOCK2MTD is not set
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_NAND=y
-# CONFIG_MTD_NAND_VERIFY_WRITE is not set
-# CONFIG_MTD_NAND_ECC_SMC is not set
-# CONFIG_MTD_NAND_MUSEUM_IDS is not set
-# CONFIG_MTD_NAND_GPIO is not set
-# CONFIG_MTD_NAND_DISKONCHIP is not set
-CONFIG_MTD_NAND_RK29=y
-# CONFIG_MTD_NAND_NANDSIM is not set
-# CONFIG_MTD_NAND_PLATFORM is not set
-# CONFIG_MTD_ALAUDA is not set
-# CONFIG_MTD_RKNAND is not set
-# CONFIG_MTD_ONENAND is not set
-
-#
-# LPDDR flash memory drivers
-#
-# CONFIG_MTD_LPDDR is not set
-
-#
-# UBI - Unsorted block images
-#
-# CONFIG_MTD_UBI is not set
-# CONFIG_PARPORT is not set
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=y
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_UB is not set
-# CONFIG_BLK_DEV_RAM is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-# CONFIG_MG_DISK is not set
-CONFIG_MISC_DEVICES=y
-CONFIG_ANDROID_PMEM=y
-# CONFIG_ICS932S401 is not set
-# CONFIG_ENCLOSURE_SERVICES is not set
-# CONFIG_KERNEL_DEBUGGER_CORE is not set
-# CONFIG_ISL29003 is not set
-# CONFIG_UID_STAT is not set
-# CONFIG_WL127X_RFKILL is not set
-# CONFIG_APANIC is not set
-# CONFIG_STE is not set
-# CONFIG_C2PORT is not set
-
-#
-# EEPROM support
-#
-# CONFIG_EEPROM_AT24 is not set
-# CONFIG_EEPROM_LEGACY is not set
-# CONFIG_EEPROM_MAX6875 is not set
-# CONFIG_EEPROM_93CX6 is not set
-CONFIG_HAVE_IDE=y
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_DMA=y
-# CONFIG_SCSI_TGT is not set
-# CONFIG_SCSI_NETLINK is not set
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=y
-# CONFIG_CHR_DEV_ST is not set
-# CONFIG_CHR_DEV_OSST is not set
-# CONFIG_BLK_DEV_SR is not set
-# CONFIG_CHR_DEV_SG is not set
-# CONFIG_CHR_DEV_SCH is not set
-CONFIG_SCSI_MULTI_LUN=y
-# CONFIG_SCSI_CONSTANTS is not set
-# CONFIG_SCSI_LOGGING is not set
-# CONFIG_SCSI_SCAN_ASYNC is not set
-CONFIG_SCSI_WAIT_SCAN=m
-
-#
-# SCSI Transports
-#
-# CONFIG_SCSI_SPI_ATTRS is not set
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_LIBSAS is not set
-# CONFIG_SCSI_SRP_ATTRS is not set
-CONFIG_SCSI_LOWLEVEL=y
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_LIBFC is not set
-# CONFIG_LIBFCOE is not set
-# CONFIG_SCSI_DEBUG is not set
-# CONFIG_SCSI_DH is not set
-# CONFIG_SCSI_OSD_INITIATOR is not set
-# CONFIG_ATA is not set
-CONFIG_MD=y
-# CONFIG_BLK_DEV_MD is not set
-CONFIG_BLK_DEV_DM=y
-# CONFIG_DM_DEBUG is not set
-CONFIG_DM_CRYPT=y
-# CONFIG_DM_SNAPSHOT is not set
-# CONFIG_DM_MIRROR is not set
-# CONFIG_DM_ZERO is not set
-# CONFIG_DM_MULTIPATH is not set
-# CONFIG_DM_DELAY is not set
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_MACVLAN is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_VETH is not set
-CONFIG_PHYLIB=y
-
-#
-# MII PHY device drivers
-#
-# CONFIG_MARVELL_PHY is not set
-# CONFIG_DAVICOM_PHY is not set
-# CONFIG_QSEMI_PHY is not set
-# CONFIG_LXT_PHY is not set
-# CONFIG_CICADA_PHY is not set
-# CONFIG_VITESSE_PHY is not set
-# CONFIG_SMSC_PHY is not set
-# CONFIG_BROADCOM_PHY is not set
-# CONFIG_ICPLUS_PHY is not set
-# CONFIG_REALTEK_PHY is not set
-# CONFIG_NATIONAL_PHY is not set
-# CONFIG_STE10XP is not set
-# CONFIG_LSI_ET1011C_PHY is not set
-# CONFIG_FIXED_PHY is not set
-# CONFIG_MDIO_BITBANG is not set
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-# CONFIG_AX88796 is not set
-CONFIG_RK29_VMAC=y
-# CONFIG_SMC91X is not set
-# CONFIG_DM9000 is not set
-# CONFIG_ETHOC is not set
-# CONFIG_SMC911X is not set
-# CONFIG_SMSC911X is not set
-# CONFIG_DNET is not set
-# CONFIG_IBM_NEW_EMAC_ZMII is not set
-# CONFIG_IBM_NEW_EMAC_RGMII is not set
-# CONFIG_IBM_NEW_EMAC_TAH is not set
-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
-# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
-# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
-# CONFIG_B44 is not set
-# CONFIG_KS8842 is not set
-# CONFIG_KS8851_MLL is not set
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN=y
-# CONFIG_WLAN_PRE80211 is not set
-CONFIG_WLAN_80211=y
-# CONFIG_LIBERTAS is not set
-# CONFIG_USB_ZD1201 is not set
-# CONFIG_HOSTAP is not set
-CONFIG_BCM4329=m
-CONFIG_BCM4329_FW_PATH="/etc/firmware/fw_bcm4329.bin"
-CONFIG_BCM4329_NVRAM_PATH="/etc/firmware/nvram_bcm4329_B23.txt"
-
-#
-# Enable WiMAX (Networking options) to see the WiMAX drivers
-#
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET is not set
-# CONFIG_USB_HSO is not set
-# CONFIG_WAN is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_ISDN is not set
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-CONFIG_INPUT_POLLDEV=y
-
-#
-# Userland interfaces
-#
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_JOYDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_EVBUG is not set
-CONFIG_INPUT_KEYRESET=y
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYS_RK29=y
-# CONFIG_KEYBOARD_ADP5588 is not set
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_QT2160 is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_GPIO is not set
-# CONFIG_KEYBOARD_MATRIX is not set
-# CONFIG_KEYBOARD_MAX7359 is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_OPENCORES is not set
-# CONFIG_KEYBOARD_STOWAWAY is not set
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_XPT2046_SPI_NOCHOOSE=y
-# CONFIG_TOUCHSCREEN_XPT2046_SPI is not set
-# CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI is not set
-# CONFIG_TOUCHSCREEN_XPT2046_320X480_SPI is not set
-# CONFIG_TOUCHSCREEN_XPT2046_320X480_CBN_SPI is not set
-# CONFIG_TOUCHSCREEN_IT7250 is not set
-# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
-# CONFIG_TOUCHSCREEN_AD7879 is not set
-# CONFIG_TOUCHSCREEN_EETI is not set
-# CONFIG_TOUCHSCREEN_FUJITSU is not set
-# CONFIG_TOUCHSCREEN_GUNZE is not set
-# CONFIG_TOUCHSCREEN_ELO is not set
-# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
-# CONFIG_TOUCHSCREEN_MCS5000 is not set
-# CONFIG_TOUCHSCREEN_MTOUCH is not set
-# CONFIG_TOUCHSCREEN_INEXIO is not set
-# CONFIG_TOUCHSCREEN_MK712 is not set
-# CONFIG_TOUCHSCREEN_PENMOUNT is not set
-# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI is not set
-# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
-# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
-# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
-# CONFIG_TOUCHSCREEN_TSC2007 is not set
-# CONFIG_TOUCHSCREEN_W90X900 is not set
-CONFIG_HANNSTAR_P1003=y
-CONFIG_HANNSTAR_MAX_X=2047
-CONFIG_HANNSTAR_MAX_Y=2047
-# CONFIG_HANNSTAR_DEBUG is not set
-# CONFIG_TOUCHSCREEN_IT7260 is not set
-# CONFIG_INPUT_MISC is not set
-CONFIG_INPUT_GPIO=y
-# CONFIG_G_SENSOR_DEVICE is not set
-# CONFIG_INPUT_JOGBALL is not set
-
-#
-# Hardware I/O ports
-#
-# CONFIG_SERIO is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_DEVMEM=y
-CONFIG_DEVKMEM=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-CONFIG_UART1_RK29=y
-CONFIG_UART2_RK29=y
-CONFIG_UART2_CTS_RTS_RK29=y
-# CONFIG_UART3_RK29 is not set
-CONFIG_SERIAL_RK29_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
-# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_IPMI_HANDLER is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_R3964 is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_TCG_TPM is not set
-# CONFIG_DCC_TTY is not set
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_COMPAT=y
-# CONFIG_I2C_CHARDEV is not set
-CONFIG_I2C_HELPER_AUTO=y
-
-#
-# I2C Hardware Bus support
-#
-CONFIG_I2C_RK29=y
-
-#
-# Now, there are four I2C interfaces selected by developer.
-#
-CONFIG_I2C0_RK29=y
-CONFIG_I2C1_RK29=y
-CONFIG_I2C2_RK29=y
-CONFIG_I2C3_RK29=y
-# CONFIG_I2C_DEV_RK29 is not set
-
-#
-# Miscellaneous I2C Chip support
-#
-# CONFIG_DS1682 is not set
-# CONFIG_SENSORS_TSL2550 is not set
-# CONFIG_SENSORS_PCA963X is not set
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-# CONFIG_I2C_DEBUG_CHIP is not set
-# CONFIG_SPI is not set
-CONFIG_ADC=y
-# CONFIG_ADC_RK28 is not set
-CONFIG_ADC_RK29=y
-# CONFIG_SPI_FPGA is not set
-# CONFIG_HEADSET_DET is not set
-
-#
-# PPS support
-#
-# CONFIG_PPS is not set
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_GPIOLIB=y
-# CONFIG_DEBUG_GPIO is not set
-# CONFIG_GPIO_SYSFS is not set
-
-#
-# Memory mapped GPIO expanders:
-#
-
-#
-# I2C GPIO expanders:
-#
-# CONFIG_GPIO_MAX732X is not set
-# CONFIG_GPIO_PCA953X is not set
-# CONFIG_GPIO_PCF857X is not set
-
-#
-# PCI GPIO expanders:
-#
-
-#
-# SPI GPIO expanders:
-#
-
-#
-# AC97 GPIO expanders:
-#
-# CONFIG_GPIO_PCA9554 is not set
-# CONFIG_IOEXTEND_TCA6424 is not set
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-# CONFIG_EXPAND_GPIO_SOFT_INTERRUPT is not set
-CONFIG_SPI_FPGA_GPIO_NUM=96
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=16
-# CONFIG_W1 is not set
-CONFIG_POWER_SUPPLY=y
-# CONFIG_POWER_SUPPLY_DEBUG is not set
-# CONFIG_PDA_POWER is not set
-# CONFIG_BATTERY_DS2760 is not set
-# CONFIG_BATTERY_DS2782 is not set
-# CONFIG_BATTERY_BQ27x00 is not set
-# CONFIG_BATTERY_MAX17040 is not set
-# CONFIG_BATTERY_STC3100 is not set
-CONFIG_BATTERY_BQ27510=y
-# CONFIG_CHECK_BATT_CAPACITY is not set
-CONFIG_NO_BATTERY_IC=y
-# CONFIG_HWMON is not set
-# CONFIG_THERMAL is not set
-# CONFIG_WATCHDOG is not set
-CONFIG_SSB_POSSIBLE=y
-
-#
-# Sonics Silicon Backplane
-#
-# CONFIG_SSB is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_CORE is not set
-# CONFIG_MFD_SM501 is not set
-# CONFIG_MFD_ASIC3 is not set
-# CONFIG_HTC_EGPIO is not set
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_TPS65010 is not set
-# CONFIG_TWL4030_CORE is not set
-# CONFIG_MFD_TMIO is not set
-# CONFIG_MFD_T7L66XB is not set
-# CONFIG_MFD_TC6387XB is not set
-# CONFIG_MFD_TC6393XB is not set
-# CONFIG_PMIC_DA903X is not set
-# CONFIG_MFD_WM8400 is not set
-# CONFIG_MFD_WM831X is not set
-# CONFIG_MFD_WM8350_I2C is not set
-# CONFIG_MFD_PCF50633 is not set
-# CONFIG_AB3100_CORE is not set
-CONFIG_REGULATOR=y
-# CONFIG_REGULATOR_DEBUG is not set
-# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
-# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
-# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
-# CONFIG_REGULATOR_BQ24022 is not set
-# CONFIG_REGULATOR_MAX1586 is not set
-# CONFIG_REGULATOR_LP3971 is not set
-# CONFIG_REGULATOR_TPS65023 is not set
-# CONFIG_REGULATOR_TPS6507X is not set
-# CONFIG_RK2818_REGULATOR_CHARGE is not set
-# CONFIG_RK2818_REGULATOR_LP8725 is not set
-CONFIG_RK29_PWM_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
-
-#
-# Multimedia core support
-#
-CONFIG_VIDEO_DEV=y
-CONFIG_VIDEO_V4L2_COMMON=y
-CONFIG_VIDEO_ALLOW_V4L1=y
-CONFIG_VIDEO_V4L1_COMPAT=y
-# CONFIG_DVB_CORE is not set
-CONFIG_VIDEO_MEDIA=y
-
-#
-# Multimedia drivers
-#
-# CONFIG_MEDIA_ATTACH is not set
-CONFIG_MEDIA_TUNER=y
-# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
-CONFIG_MEDIA_TUNER_SIMPLE=y
-CONFIG_MEDIA_TUNER_TDA8290=y
-CONFIG_MEDIA_TUNER_TDA9887=y
-CONFIG_MEDIA_TUNER_TEA5761=y
-CONFIG_MEDIA_TUNER_TEA5767=y
-CONFIG_MEDIA_TUNER_MT20XX=y
-CONFIG_MEDIA_TUNER_XC2028=y
-CONFIG_MEDIA_TUNER_XC5000=y
-CONFIG_MEDIA_TUNER_MC44S803=y
-CONFIG_VIDEO_V4L2=y
-CONFIG_VIDEO_V4L1=y
-CONFIG_VIDEOBUF_GEN=y
-CONFIG_VIDEOBUF_DMA_CONTIG=y
-CONFIG_VIDEO_CAPTURE_DRIVERS=y
-# CONFIG_VIDEO_ADV_DEBUG is not set
-# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
-CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
-# CONFIG_VIDEO_VIVI is not set
-# CONFIG_VIDEO_CPIA is not set
-# CONFIG_VIDEO_CPIA2 is not set
-# CONFIG_VIDEO_SAA5246A is not set
-# CONFIG_VIDEO_SAA5249 is not set
-CONFIG_SOC_CAMERA=y
-# CONFIG_SOC_CAMERA_MT9M001 is not set
-# CONFIG_SOC_CAMERA_MT9M111 is not set
-# CONFIG_SOC_CAMERA_MT9T031 is not set
-# CONFIG_SOC_CAMERA_MT9V022 is not set
-# CONFIG_SOC_CAMERA_TW9910 is not set
-# CONFIG_SOC_CAMERA_PLATFORM is not set
-# CONFIG_SOC_CAMERA_OV772X is not set
-# CONFIG_SOC_CAMERA_OV7675 is not set
-# CONFIG_SOC_CAMERA_OV2655 is not set
-CONFIG_SOC_CAMERA_OV2659=y
-# CONFIG_SOC_CAMERA_OV9650 is not set
-# CONFIG_SOC_CAMERA_OV3640 is not set
-CONFIG_SOC_CAMERA_OV5642=y
-CONFIG_OV5642_AUTOFOCUS=y
-# CONFIG_OV5642_FIXEDFOCUS is not set
-# CONFIG_VIDEO_SH_MOBILE_CEU is not set
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_WORK_ONEFRAME=y
-# CONFIG_VIDEO_RK29_WORK_PINGPONG is not set
-CONFIG_VIDEO_RK29_WORK_IPP=y
-# CONFIG_VIDEO_RK29_WORK_NOT_IPP is not set
-CONFIG_V4L_USB_DRIVERS=y
-# CONFIG_USB_VIDEO_CLASS is not set
-CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
-CONFIG_USB_GSPCA=m
-# CONFIG_USB_M5602 is not set
-# CONFIG_USB_STV06XX is not set
-# CONFIG_USB_GL860 is not set
-# CONFIG_USB_GSPCA_CONEX is not set
-# CONFIG_USB_GSPCA_ETOMS is not set
-# CONFIG_USB_GSPCA_FINEPIX is not set
-# CONFIG_USB_GSPCA_JEILINJ is not set
-# CONFIG_USB_GSPCA_MARS is not set
-# CONFIG_USB_GSPCA_MR97310A is not set
-# CONFIG_USB_GSPCA_OV519 is not set
-# CONFIG_USB_GSPCA_OV534 is not set
-# CONFIG_USB_GSPCA_PAC207 is not set
-# CONFIG_USB_GSPCA_PAC7311 is not set
-# CONFIG_USB_GSPCA_SN9C20X is not set
-# CONFIG_USB_GSPCA_SONIXB is not set
-# CONFIG_USB_GSPCA_SONIXJ is not set
-# CONFIG_USB_GSPCA_SPCA500 is not set
-# CONFIG_USB_GSPCA_SPCA501 is not set
-# CONFIG_USB_GSPCA_SPCA505 is not set
-# CONFIG_USB_GSPCA_SPCA506 is not set
-# CONFIG_USB_GSPCA_SPCA508 is not set
-# CONFIG_USB_GSPCA_SPCA561 is not set
-# CONFIG_USB_GSPCA_SQ905 is not set
-# CONFIG_USB_GSPCA_SQ905C is not set
-# CONFIG_USB_GSPCA_STK014 is not set
-# CONFIG_USB_GSPCA_SUNPLUS is not set
-# CONFIG_USB_GSPCA_T613 is not set
-# CONFIG_USB_GSPCA_TV8532 is not set
-# CONFIG_USB_GSPCA_VC032X is not set
-# CONFIG_USB_GSPCA_ZC3XX is not set
-# CONFIG_VIDEO_PVRUSB2 is not set
-# CONFIG_VIDEO_HDPVR is not set
-# CONFIG_VIDEO_EM28XX is not set
-# CONFIG_VIDEO_CX231XX is not set
-# CONFIG_VIDEO_USBVISION is not set
-# CONFIG_USB_VICAM is not set
-# CONFIG_USB_IBMCAM is not set
-# CONFIG_USB_KONICAWC is not set
-# CONFIG_USB_QUICKCAM_MESSENGER is not set
-# CONFIG_USB_ET61X251 is not set
-# CONFIG_VIDEO_OVCAMCHIP is not set
-# CONFIG_USB_OV511 is not set
-# CONFIG_USB_SE401 is not set
-# CONFIG_USB_SN9C102 is not set
-# CONFIG_USB_STV680 is not set
-# CONFIG_USB_ZC0301 is not set
-# CONFIG_USB_PWC is not set
-CONFIG_USB_PWC_INPUT_EVDEV=y
-# CONFIG_USB_ZR364XX is not set
-# CONFIG_USB_STKWEBCAM is not set
-# CONFIG_USB_S2255 is not set
-CONFIG_RADIO_ADAPTERS=y
-# CONFIG_I2C_SI4713 is not set
-# CONFIG_RADIO_SI4713 is not set
-# CONFIG_USB_DSBR is not set
-# CONFIG_RADIO_SI470X is not set
-# CONFIG_USB_MR800 is not set
-# CONFIG_RADIO_TEA5764 is not set
-# CONFIG_SMS_SIANO_MDTV is not set
-# CONFIG_DAB is not set
-
-#
-# Graphics support
-#
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-CONFIG_FB=y
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB_DDC is not set
-# CONFIG_FB_BOOT_VESA_SUPPORT is not set
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-# CONFIG_FB_SYS_FILLRECT is not set
-# CONFIG_FB_SYS_COPYAREA is not set
-# CONFIG_FB_SYS_IMAGEBLIT is not set
-# CONFIG_FB_FOREIGN_ENDIAN is not set
-# CONFIG_FB_SYS_FOPS is not set
-# CONFIG_FB_SVGALIB is not set
-# CONFIG_FB_MACMODES is not set
-# CONFIG_FB_BACKLIGHT is not set
-# CONFIG_FB_MODE_HELPERS is not set
-# CONFIG_FB_TILEBLITTING is not set
-
-#
-# Frame buffer hardware drivers
-#
-# CONFIG_FB_S1D13XXX is not set
-# CONFIG_FB_RK2818 is not set
-CONFIG_FB_RK29=y
-# CONFIG_FB_VIRTUAL is not set
-# CONFIG_FB_METRONOME is not set
-# CONFIG_FB_MB862XX is not set
-# CONFIG_FB_BROADSHEET is not set
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_BACKLIGHT_RK29_BL=y
-
-#
-# Display device support
-#
-CONFIG_DISPLAY_SUPPORT=y
-
-#
-# Display hardware drivers
-#
-# CONFIG_LCD_NULL is not set
-# CONFIG_LCD_TD043MGEA1 is not set
-# CONFIG_LCD_HX8357 is not set
-# CONFIG_LCD_TJ048NC01CA is not set
-# CONFIG_LCD_HL070VM4AU is not set
-# CONFIG_LCD_HSD070IDW1 is not set
-CONFIG_LCD_HSD100PXN=y
-# CONFIG_LCD_A060SE02 is not set
-# CONFIG_LCD_S1D13521 is not set
-# CONFIG_LCD_NT35582 is not set
-# CONFIG_LCD_NT35580 is not set
-# CONFIG_LCD_ANX7150_720P is not set
-
-#
-# HDMI support
-#
-# CONFIG_HDMI is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-CONFIG_FONTS=y
-# CONFIG_FONT_8x8 is not set
-CONFIG_FONT_8x16=y
-# CONFIG_FONT_6x11 is not set
-# CONFIG_FONT_7x14 is not set
-# CONFIG_FONT_PEARL_8x8 is not set
-# CONFIG_FONT_ACORN_8x8 is not set
-# CONFIG_FONT_MINI_4x6 is not set
-# CONFIG_FONT_SUN8x16 is not set
-# CONFIG_FONT_SUN12x22 is not set
-# CONFIG_FONT_10x18 is not set
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_LOGO_LINUX_CLUT224=y
-CONFIG_SOUND=y
-# CONFIG_SOUND_OSS_CORE is not set
-CONFIG_SND=y
-CONFIG_SND_TIMER=y
-CONFIG_SND_PCM=y
-CONFIG_SND_JACK=y
-# CONFIG_SND_SEQUENCER is not set
-# CONFIG_SND_MIXER_OSS is not set
-# CONFIG_SND_PCM_OSS is not set
-# CONFIG_SND_HRTIMER is not set
-# CONFIG_SND_DYNAMIC_MINORS is not set
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_VERBOSE_PRINTK is not set
-# CONFIG_SND_DEBUG is not set
-# CONFIG_SND_RAWMIDI_SEQ is not set
-# CONFIG_SND_OPL3_LIB_SEQ is not set
-# CONFIG_SND_OPL4_LIB_SEQ is not set
-# CONFIG_SND_SBAWE_SEQ is not set
-# CONFIG_SND_EMU10K1_SEQ is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_USB=y
-# CONFIG_SND_USB_AUDIO is not set
-# CONFIG_SND_USB_CAIAQ is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_RK29_SOC_I2S=y
-# CONFIG_SND_RK29_SOC_I2S_2CH is not set
-CONFIG_SND_RK29_SOC_I2S_8CH=y
-# CONFIG_SND_RK29_SOC_WM8988 is not set
-CONFIG_SND_RK29_SOC_WM8900=y
-# CONFIG_SND_RK29_CODEC_SOC_MASTER is not set
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_SND_SOC_I2C_AND_SPI=y
-# CONFIG_SND_SOC_ALL_CODECS is not set
-CONFIG_SND_SOC_WM8900=y
-# CONFIG_SOUND_PRIME is not set
-# CONFIG_HID_SUPPORT is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ARCH_HAS_HCD=y
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-CONFIG_USB=y
-# CONFIG_USB_DEBUG is not set
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-
-#
-# Miscellaneous USB options
-#
-# CONFIG_USB_DEVICEFS is not set
-CONFIG_USB_DEVICE_CLASS=y
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_SUSPEND is not set
-# CONFIG_USB_OTG is not set
-# CONFIG_USB_OTG_WHITELIST is not set
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-# CONFIG_USB_MON is not set
-# CONFIG_USB_WUSB is not set
-# CONFIG_USB_WUSB_CBAF is not set
-
-#
-# USB Host Controller Drivers
-#
-# CONFIG_USB_C67X00_HCD is not set
-# CONFIG_USB_OXU210HP_HCD is not set
-# CONFIG_USB_ISP116X_HCD is not set
-# CONFIG_USB_ISP1760_HCD is not set
-# CONFIG_USB_ISP1362_HCD is not set
-# CONFIG_USB_SL811_HCD is not set
-# CONFIG_USB_R8A66597_HCD is not set
-# CONFIG_USB_HWA_HCD is not set
-# CONFIG_USB_MUSB_HDRC is not set
-# CONFIG_USB_GADGET_MUSB_HDRC is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-# CONFIG_USB_WDM is not set
-# CONFIG_USB_TMC is not set
-
-#
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
-#
-
-#
-# also be needed; see USB_STORAGE Help for more info
-#
-CONFIG_USB_STORAGE=y
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_USBAT is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_STORAGE_SDDR55 is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_ALAUDA is not set
-# CONFIG_USB_STORAGE_ONETOUCH is not set
-# CONFIG_USB_STORAGE_KARMA is not set
-# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_MICROTEK is not set
-
-#
-# USB port drivers
-#
-CONFIG_USB_SERIAL=y
-# CONFIG_USB_SERIAL_CONSOLE is not set
-# CONFIG_USB_EZUSB is not set
-CONFIG_USB_SERIAL_GENERIC=y
-# CONFIG_USB_SERIAL_AIRCABLE is not set
-# CONFIG_USB_SERIAL_ARK3116 is not set
-# CONFIG_USB_SERIAL_BELKIN is not set
-# CONFIG_USB_SERIAL_CH341 is not set
-# CONFIG_USB_SERIAL_WHITEHEAT is not set
-# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
-# CONFIG_USB_SERIAL_CP210X is not set
-# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
-# CONFIG_USB_SERIAL_EMPEG is not set
-# CONFIG_USB_SERIAL_FTDI_SIO is not set
-# CONFIG_USB_SERIAL_FUNSOFT is not set
-# CONFIG_USB_SERIAL_VISOR is not set
-# CONFIG_USB_SERIAL_IPAQ is not set
-# CONFIG_USB_SERIAL_IR is not set
-# CONFIG_USB_SERIAL_EDGEPORT is not set
-# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
-# CONFIG_USB_SERIAL_GARMIN is not set
-# CONFIG_USB_SERIAL_IPW is not set
-# CONFIG_USB_SERIAL_IUU is not set
-# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
-# CONFIG_USB_SERIAL_KEYSPAN is not set
-# CONFIG_USB_SERIAL_KLSI is not set
-# CONFIG_USB_SERIAL_KOBIL_SCT is not set
-# CONFIG_USB_SERIAL_MCT_U232 is not set
-# CONFIG_USB_SERIAL_MOS7720 is not set
-# CONFIG_USB_SERIAL_MOS7840 is not set
-# CONFIG_USB_SERIAL_MOTOROLA is not set
-# CONFIG_USB_SERIAL_NAVMAN is not set
-# CONFIG_USB_SERIAL_PL2303 is not set
-# CONFIG_USB_SERIAL_OTI6858 is not set
-# CONFIG_USB_SERIAL_QUALCOMM is not set
-# CONFIG_USB_SERIAL_SPCP8X5 is not set
-# CONFIG_USB_SERIAL_HP4X is not set
-# CONFIG_USB_SERIAL_SAFE is not set
-# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
-# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
-# CONFIG_USB_SERIAL_SYMBOL is not set
-# CONFIG_USB_SERIAL_TI is not set
-# CONFIG_USB_SERIAL_CYBERJACK is not set
-# CONFIG_USB_SERIAL_XIRCOM is not set
-CONFIG_USB_SERIAL_OPTION=y
-# CONFIG_USB_SERIAL_OMNINET is not set
-# CONFIG_USB_SERIAL_OPTICON is not set
-# CONFIG_USB_SERIAL_DEBUG is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_SEVSEG is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_BERRY_CHARGE is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYPRESS_CY7C63 is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_FTDI_ELAN is not set
-# CONFIG_USB_APPLEDISPLAY is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TRANCEVIBRATOR is not set
-# CONFIG_USB_IOWARRIOR is not set
-# CONFIG_USB_TEST is not set
-# CONFIG_USB_ISIGHTFW is not set
-# CONFIG_USB_VST is not set
-CONFIG_USB_GADGET=y
-# CONFIG_USB_GADGET_DEBUG is not set
-# CONFIG_USB_GADGET_DEBUG_FILES is not set
-CONFIG_USB_GADGET_VBUS_DRAW=2
-CONFIG_USB_GADGET_SELECTED=y
-# CONFIG_USB_GADGET_AT91 is not set
-# CONFIG_USB_GADGET_ATMEL_USBA is not set
-# CONFIG_USB_GADGET_FSL_USB2 is not set
-# CONFIG_USB_GADGET_LH7A40X is not set
-# CONFIG_USB_GADGET_OMAP is not set
-# CONFIG_USB_GADGET_PXA25X is not set
-# CONFIG_USB_GADGET_R8A66597 is not set
-# CONFIG_USB_GADGET_PXA27X is not set
-# CONFIG_USB_GADGET_S3C_HSOTG is not set
-# CONFIG_USB_GADGET_IMX is not set
-# CONFIG_USB_GADGET_S3C2410 is not set
-# CONFIG_USB_GADGET_M66592 is not set
-# CONFIG_USB_GADGET_AMD5536UDC is not set
-# CONFIG_USB_GADGET_FSL_QE is not set
-# CONFIG_USB_GADGET_CI13XXX is not set
-# CONFIG_USB_GADGET_NET2280 is not set
-# CONFIG_USB_GADGET_GOKU is not set
-# CONFIG_USB_GADGET_LANGWELL is not set
-CONFIG_USB_GADGET_DWC_OTG=y
-CONFIG_USB_DWC_OTG=y
-# CONFIG_USB_GADGET_DUMMY_HCD is not set
-CONFIG_USB_GADGET_DUALSPEED=y
-# CONFIG_USB_ZERO is not set
-# CONFIG_USB_AUDIO is not set
-# CONFIG_USB_ETH is not set
-# CONFIG_USB_GADGETFS is not set
-# CONFIG_USB_FILE_STORAGE is not set
-# CONFIG_USB_G_SERIAL is not set
-# CONFIG_USB_MIDI_GADGET is not set
-# CONFIG_USB_G_PRINTER is not set
-CONFIG_USB_ANDROID=y
-# CONFIG_USB_ANDROID_ACM is not set
-CONFIG_USB_ANDROID_ADB=y
-CONFIG_USB_ANDROID_MASS_STORAGE=y
-# CONFIG_USB_ANDROID_RNDIS is not set
-# CONFIG_USB_CDC_COMPOSITE is not set
-
-#
-# OTG and related infrastructure
-#
-# CONFIG_USB_GPIO_VBUS is not set
-# CONFIG_NOP_USB_XCEIV is not set
-CONFIG_USB11_HOST=y
-CONFIG_USB11_HOST_EN=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_HOST_EN=y
-CONFIG_USB20_OTG=y
-# CONFIG_DWC_OTG_HOST_ONLY is not set
-CONFIG_DWC_OTG_DEVICE_ONLY=y
-CONFIG_DWC_CONN_EN=y
-# CONFIG_DWC_OTG_DEBUG is not set
-CONFIG_DWC_OTG=y
-CONFIG_MMC=y
-# CONFIG_MMC_DEBUG is not set
-# CONFIG_MMC_UNSAFE_RESUME is not set
-CONFIG_MMC_EMBEDDED_SDIO=y
-# CONFIG_MMC_PARANOID_SD_INIT is not set
-
-#
-# MMC/SD/SDIO Card Drivers
-#
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_BLOCK_BOUNCE=y
-CONFIG_MMC_BLOCK_DEFERRED_RESUME=y
-# CONFIG_SDIO_UART is not set
-# CONFIG_MMC_TEST is not set
-
-#
-# MMC/SD/SDIO Host Controller Drivers
-#
-CONFIG_SDMMC_RK29=y
-
-#
-# Now, there are two SDMMC controllers selected, SDMMC0 and SDMMC1.
-#
-CONFIG_SDMMC0_RK29=y
-# CONFIG_EMMC_RK29 is not set
-CONFIG_SDMMC1_RK29=y
-# CONFIG_MMC_SDHCI is not set
-# CONFIG_MMC_AT91 is not set
-# CONFIG_MMC_ATMELMCI is not set
-# CONFIG_MEMSTICK is not set
-# CONFIG_NEW_LEDS is not set
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-# CONFIG_ACCESSIBILITY is not set
-CONFIG_RTC_LIB=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HCTOSYS=y
-CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-# CONFIG_RTC_DEBUG is not set
-
-#
-# RTC interfaces
-#
-CONFIG_RTC_INTF_SYSFS=y
-CONFIG_RTC_INTF_PROC=y
-CONFIG_RTC_INTF_DEV=y
-# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-CONFIG_RTC_INTF_ALARM=y
-CONFIG_RTC_INTF_ALARM_DEV=y
-# CONFIG_RTC_DRV_TEST is not set
-
-#
-# I2C RTC drivers
-#
-CONFIG_RTC_HYM8563=y
-# CONFIG_RTC_DRV_DS1307 is not set
-# CONFIG_RTC_DRV_DS1374 is not set
-# CONFIG_RTC_DRV_DS1672 is not set
-# CONFIG_RTC_DRV_MAX6900 is not set
-# CONFIG_RTC_DRV_RS5C372 is not set
-# CONFIG_RTC_DRV_ISL1208 is not set
-# CONFIG_RTC_DRV_X1205 is not set
-# CONFIG_RTC_DRV_PCF8563 is not set
-# CONFIG_RTC_DRV_PCF8583 is not set
-# CONFIG_RTC_DRV_M41T80 is not set
-# CONFIG_RTC_DRV_S35390A is not set
-# CONFIG_RTC_DRV_S35392A is not set
-# CONFIG_RTC_DRV_FM3130 is not set
-# CONFIG_RTC_DRV_RX8581 is not set
-# CONFIG_RTC_DRV_RX8025 is not set
-
-#
-# SPI RTC drivers
-#
-
-#
-# Platform RTC drivers
-#
-# CONFIG_RTC_DRV_CMOS is not set
-# CONFIG_RTC_DRV_DS1286 is not set
-# CONFIG_RTC_DRV_DS1511 is not set
-# CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_DS1742 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
-# CONFIG_RTC_DRV_M48T86 is not set
-# CONFIG_RTC_DRV_M48T35 is not set
-# CONFIG_RTC_DRV_M48T59 is not set
-# CONFIG_RTC_DRV_BQ4802 is not set
-# CONFIG_RTC_DRV_V3020 is not set
-
-#
-# on-CPU RTC drivers
-#
-# CONFIG_DMADEVICES is not set
-# CONFIG_AUXDISPLAY is not set
-# CONFIG_UIO is not set
-
-#
-# TI VLYNQ
-#
-CONFIG_STAGING=y
-# CONFIG_STAGING_EXCLUDE_BUILD is not set
-# CONFIG_USB_IP_COMMON is not set
-# CONFIG_PRISM2_USB is not set
-# CONFIG_ECHO is not set
-# CONFIG_COMEDI is not set
-# CONFIG_ASUS_OLED is not set
-# CONFIG_TRANZPORT is not set
-
-#
-# Android
-#
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_RAM_CONSOLE=y
-CONFIG_ANDROID_RAM_CONSOLE_ENABLE_VERBOSE=y
-CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION=y
-CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_DATA_SIZE=128
-CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_ECC_SIZE=16
-CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_SYMBOL_SIZE=8
-CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_POLYNOMIAL=0x11d
-# CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT is not set
-CONFIG_ANDROID_TIMED_OUTPUT=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-
-#
-# Qualcomm MSM Camera And Video
-#
-
-#
-# Camera Sensor Selection
-#
-# CONFIG_DST is not set
-# CONFIG_POHMELFS is not set
-# CONFIG_PLAN9AUTH is not set
-# CONFIG_LINE6_USB is not set
-# CONFIG_USB_SERIAL_QUATECH2 is not set
-# CONFIG_USB_SERIAL_QUATECH_USB2 is not set
-# CONFIG_VT6656 is not set
-# CONFIG_FB_UDL is not set
-
-#
-# RAR Register Driver
-#
-# CONFIG_RAR_REGISTER is not set
-# CONFIG_IIO is not set
-
-#
-# DSP
-#
-# CONFIG_RK2818_DSP is not set
-
-#
-# RK1000 control
-#
-# CONFIG_RK1000_CONTROL is not set
-
-#
-# rk2818 POWER CONTROL
-#
-# CONFIG_RK2818_POWER is not set
-
-#
-# GPU Vivante
-#
-CONFIG_VIVANTE=y
-
-#
-# IPP
-#
-CONFIG_RK29_IPP=y
-
-#
-# CMMB
-#
-# CONFIG_CMMB is not set
-
-#
-# File systems
-#
-# CONFIG_EXT2_FS is not set
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
-CONFIG_EXT3_FS_XATTR=y
-# CONFIG_EXT3_FS_POSIX_ACL is not set
-# CONFIG_EXT3_FS_SECURITY is not set
-# CONFIG_EXT4_FS is not set
-CONFIG_JBD=y
-CONFIG_FS_MBCACHE=y
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
-# CONFIG_XFS_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_BTRFS_FS is not set
-# CONFIG_NILFS2_FS is not set
-CONFIG_FILE_LOCKING=y
-CONFIG_FSNOTIFY=y
-# CONFIG_DNOTIFY is not set
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-# CONFIG_FUSE_FS is not set
-
-#
-# Caches
-#
-# CONFIG_FSCACHE is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=y
-# CONFIG_MSDOS_FS is not set
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-# CONFIG_HUGETLB_PAGE is not set
-# CONFIG_CONFIGFS_FS is not set
-CONFIG_MISC_FILESYSTEMS=y
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-CONFIG_YAFFS_FS=y
-CONFIG_YAFFS_YAFFS1=y
-# CONFIG_YAFFS_9BYTE_TAGS is not set
-# CONFIG_YAFFS_DOES_ECC is not set
-CONFIG_YAFFS_YAFFS2=y
-CONFIG_YAFFS_AUTO_YAFFS2=y
-# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
-# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
-# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
-CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
-# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
-# CONFIG_JFFS2_FS is not set
-CONFIG_CRAMFS=y
-# CONFIG_SQUASHFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_OMFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-
-#
-# Partition Types
-#
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_MSDOS_PARTITION=y
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-1"
-CONFIG_NLS_CODEPAGE_437=y
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-CONFIG_NLS_CODEPAGE_850=y
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-CONFIG_NLS_CODEPAGE_936=y
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ASCII is not set
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-CONFIG_NLS_ISO8859_15=y
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-CONFIG_NLS_UTF8=y
-# CONFIG_DLM is not set
-
-#
-# Kernel hacking
-#
-CONFIG_PRINTK_TIME=y
-CONFIG_ENABLE_WARN_DEPRECATED=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_FRAME_WARN=1024
-CONFIG_MAGIC_SYSRQ=y
-# CONFIG_STRIP_ASM_SYMS is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-CONFIG_DETECT_HUNG_TASK=y
-# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
-CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
-CONFIG_SCHEDSTATS=y
-CONFIG_TIMER_STATS=y
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_KMEMLEAK is not set
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_PROVE_LOCKING is not set
-# CONFIG_LOCK_STAT is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_WRITECOUNT is not set
-# CONFIG_DEBUG_MEMORY_INIT is not set
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_DEBUG_NOTIFIERS is not set
-# CONFIG_DEBUG_CREDENTIALS is not set
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_RCU_TORTURE_TEST is not set
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_BACKTRACE_SELF_TEST is not set
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
-# CONFIG_FAULT_INJECTION is not set
-# CONFIG_LATENCYTOP is not set
-# CONFIG_PAGE_POISONING is not set
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_TRACING_SUPPORT=y
-# CONFIG_FTRACE is not set
-# CONFIG_SAMPLES is not set
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_KGDB is not set
-CONFIG_ARM_UNWIND=y
-# CONFIG_DEBUG_USER is not set
-CONFIG_DEBUG_ERRORS=y
-# CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_DEBUG_LL is not set
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-# CONFIG_SECURITYFS is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_ALGAPI2=y
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_BLKCIPHER=y
-CONFIG_CRYPTO_BLKCIPHER2=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_PCOMP=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-# CONFIG_CRYPTO_GF128MUL is not set
-# CONFIG_CRYPTO_NULL is not set
-CONFIG_CRYPTO_WORKQUEUE=y
-# CONFIG_CRYPTO_CRYPTD is not set
-# CONFIG_CRYPTO_AUTHENC is not set
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Authenticated Encryption with Associated Data
-#
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_SEQIV is not set
-
-#
-# Block modes
-#
-CONFIG_CRYPTO_CBC=y
-# CONFIG_CRYPTO_CTR is not set
-# CONFIG_CRYPTO_CTS is not set
-CONFIG_CRYPTO_ECB=y
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_PCBC is not set
-# CONFIG_CRYPTO_XTS is not set
-
-#
-# Hash modes
-#
-# CONFIG_CRYPTO_HMAC is not set
-# CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_VMAC is not set
-
-#
-# Digest
-#
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_GHASH is not set
-# CONFIG_CRYPTO_MD4 is not set
-CONFIG_CRYPTO_MD5=y
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_RMD128 is not set
-# CONFIG_CRYPTO_RMD160 is not set
-# CONFIG_CRYPTO_RMD256 is not set
-# CONFIG_CRYPTO_RMD320 is not set
-CONFIG_CRYPTO_SHA1=y
-# CONFIG_CRYPTO_SHA256 is not set
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_WP512 is not set
-
-#
-# Ciphers
-#
-# CONFIG_CRYPTO_AES is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-CONFIG_CRYPTO_ARC4=y
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-CONFIG_CRYPTO_DES=y
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_SALSA20 is not set
-# CONFIG_CRYPTO_SEED is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_TEA is not set
-CONFIG_CRYPTO_TWOFISH=y
-CONFIG_CRYPTO_TWOFISH_COMMON=y
-
-#
-# Compression
-#
-# CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_ZLIB is not set
-# CONFIG_CRYPTO_LZO is not set
-
-#
-# Random Number Generation
-#
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRYPTO_HW=y
-# CONFIG_BINARY_PRINTF is not set
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-CONFIG_GENERIC_FIND_LAST_BIT=y
-CONFIG_CRC_CCITT=y
-CONFIG_CRC16=y
-# CONFIG_CRC_T10DIF is not set
-# CONFIG_CRC_ITU_T is not set
-CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
-# CONFIG_LIBCRC32C is not set
-CONFIG_ZLIB_INFLATE=y
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_REED_SOLOMON=y
-CONFIG_REED_SOLOMON_ENC8=y
-CONFIG_REED_SOLOMON_DEC8=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
-CONFIG_NLATTR=y
+++ /dev/null
-#
-# Automatically generated make config: don't edit
-# Linux/arm 3.0.8 Kernel Configuration
-#
-CONFIG_ARM=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_HAVE_SCHED_CLOCK=y
-CONFIG_GENERIC_GPIO=y
-# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_KTIME_SCALAR=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-CONFIG_ARCH_HAS_CPUFREQ=y
-CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ZONE_DMA=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_VECTORS_BASE=0xffff0000
-# CONFIG_ARM_PATCH_PHYS_VIRT is not set
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-CONFIG_HAVE_IRQ_WORK=y
-
-#
-# General setup
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_CROSS_COMPILE=""
-CONFIG_LOCALVERSION=""
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_LZO=y
-# CONFIG_KERNEL_GZIP is not set
-# CONFIG_KERNEL_LZMA is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_DEFAULT_HOSTNAME="(none)"
-# CONFIG_SWAP is not set
-# CONFIG_SYSVIPC is not set
-# CONFIG_POSIX_MQUEUE is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_FHANDLE is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_AUDIT is not set
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-
-#
-# IRQ subsystem
-#
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_HAVE_SPARSE_IRQ=y
-CONFIG_GENERIC_IRQ_SHOW=y
-# CONFIG_SPARSE_IRQ is not set
-
-#
-# RCU Subsystem
-#
-CONFIG_TREE_PREEMPT_RCU=y
-# CONFIG_TINY_RCU is not set
-# CONFIG_TINY_PREEMPT_RCU is not set
-CONFIG_PREEMPT_RCU=y
-# CONFIG_RCU_TRACE is not set
-CONFIG_RCU_FANOUT=32
-# CONFIG_RCU_FANOUT_EXACT is not set
-# CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_RCU_BOOST is not set
-# CONFIG_IKCONFIG is not set
-CONFIG_LOG_BUF_SHIFT=17
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-# CONFIG_CGROUP_DEVICE is not set
-# CONFIG_CPUSETS is not set
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-# CONFIG_CGROUP_MEM_RES_CTLR is not set
-CONFIG_CGROUP_SCHED=y
-CONFIG_FAIR_GROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-# CONFIG_BLK_CGROUP is not set
-# CONFIG_NAMESPACES is not set
-# CONFIG_SCHED_AUTOGROUP is not set
-# CONFIG_SYSFS_DEPRECATED is not set
-# CONFIG_RELAY is not set
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_RD_GZIP=y
-# CONFIG_RD_BZIP2 is not set
-# CONFIG_RD_LZMA is not set
-# CONFIG_RD_XZ is not set
-# CONFIG_RD_LZO is not set
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL=y
-CONFIG_ANON_INODES=y
-CONFIG_PANIC_TIMEOUT=1
-CONFIG_EXPERT=y
-CONFIG_UID16=y
-# CONFIG_SYSCTL_SYSCALL is not set
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-# CONFIG_ELF_CORE is not set
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_ASHMEM=y
-CONFIG_AIO=y
-CONFIG_EMBEDDED=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_PERF_USE_VMALLOC=y
-
-#
-# Kernel Performance Events And Counters
-#
-# CONFIG_PERF_EVENTS is not set
-# CONFIG_PERF_COUNTERS is not set
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_COMPAT_BRK=y
-CONFIG_SLAB=y
-# CONFIG_SLUB is not set
-# CONFIG_SLOB is not set
-# CONFIG_PROFILING is not set
-CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-
-#
-# GCOV-based kernel profiling
-#
-# CONFIG_GCOV_KERNEL is not set
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_SLABINFO=y
-CONFIG_RT_MUTEXES=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-# CONFIG_MODULE_FORCE_LOAD is not set
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_MODVERSIONS is not set
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_BLOCK=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_BLK_DEV_INTEGRITY is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_CFQ=y
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="cfq"
-# CONFIG_INLINE_SPIN_TRYLOCK is not set
-# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
-# CONFIG_INLINE_SPIN_LOCK is not set
-# CONFIG_INLINE_SPIN_LOCK_BH is not set
-# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
-# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
-# CONFIG_INLINE_SPIN_UNLOCK is not set
-# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
-# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
-# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
-# CONFIG_INLINE_READ_TRYLOCK is not set
-# CONFIG_INLINE_READ_LOCK is not set
-# CONFIG_INLINE_READ_LOCK_BH is not set
-# CONFIG_INLINE_READ_LOCK_IRQ is not set
-# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
-# CONFIG_INLINE_READ_UNLOCK is not set
-# CONFIG_INLINE_READ_UNLOCK_BH is not set
-# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
-# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
-# CONFIG_INLINE_WRITE_TRYLOCK is not set
-# CONFIG_INLINE_WRITE_LOCK is not set
-# CONFIG_INLINE_WRITE_LOCK_BH is not set
-# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
-# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
-# CONFIG_INLINE_WRITE_UNLOCK is not set
-# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
-# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
-# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
-# CONFIG_MUTEX_SPIN_ON_OWNER is not set
-CONFIG_FREEZER=y
-
-#
-# System Type
-#
-CONFIG_MMU=y
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_VEXPRESS is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_BCMRING is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_CNS3XXX is not set
-# CONFIG_ARCH_GEMINI is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_MXC is not set
-# CONFIG_ARCH_MXS is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP23XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_DOVE is not set
-# CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_LOKI is not set
-# CONFIG_ARCH_LPC32XX is not set
-# CONFIG_ARCH_MV78XX0 is not set
-# CONFIG_ARCH_ORION5X is not set
-# CONFIG_ARCH_MMP is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_W90X900 is not set
-# CONFIG_ARCH_NUC93X is not set
-# CONFIG_ARCH_TEGRA is not set
-# CONFIG_ARCH_PNX4008 is not set
-# CONFIG_ARCH_PXA is not set
-# CONFIG_ARCH_MSM is not set
-# CONFIG_ARCH_SHMOBILE is not set
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_S3C64XX is not set
-# CONFIG_ARCH_S5P64X0 is not set
-# CONFIG_ARCH_S5PC100 is not set
-# CONFIG_ARCH_S5PV210 is not set
-# CONFIG_ARCH_EXYNOS4 is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_TCC_926 is not set
-# CONFIG_ARCH_U300 is not set
-# CONFIG_ARCH_U8500 is not set
-# CONFIG_ARCH_NOMADIK is not set
-# CONFIG_ARCH_DAVINCI is not set
-# CONFIG_ARCH_OMAP is not set
-CONFIG_ARCH_RK29=y
-# CONFIG_PLAT_SPEAR is not set
-# CONFIG_ARCH_VT8500 is not set
-# CONFIG_GPIO_PCA953X is not set
-# CONFIG_KEYBOARD_GPIO_POLLED is not set
-# CONFIG_MACH_RK29SDK is not set
-# CONFIG_MACH_RK29SDK_DDR3 is not set
-# CONFIG_MACH_RK29_K97 is not set
-# CONFIG_MACH_RK29FIH is not set
-# CONFIG_MACH_RK29_PHONESDK is not set
-# CONFIG_MACH_RK29_A22 is not set
-CONFIG_MACH_RK29_TD8801_V2=y
-# CONFIG_MACH_RK29_PHONEPADSDK is not set
-# CONFIG_MACH_RK29_newton is not set
-# CONFIG_MACH_RK29_PHONE_Z5 is not set
-# CONFIG_DDR_TYPE_DDRII is not set
-CONFIG_DDR_TYPE_LPDDR=y
-# CONFIG_DDR_TYPE_DDR3_800D is not set
-# CONFIG_DDR_TYPE_DDR3_800E is not set
-# CONFIG_DDR_TYPE_DDR3_1066E is not set
-# CONFIG_DDR_TYPE_DDR3_1066F is not set
-# CONFIG_DDR_TYPE_DDR3_1066G is not set
-# CONFIG_DDR_TYPE_DDR3_1333F is not set
-# CONFIG_DDR_TYPE_DDR3_1333G is not set
-# CONFIG_DDR_TYPE_DDR3_1333H is not set
-# CONFIG_DDR_TYPE_DDR3_1333J is not set
-# CONFIG_DDR_TYPE_DDR3_1600G is not set
-# CONFIG_DDR_TYPE_DDR3_1600H is not set
-# CONFIG_DDR_TYPE_DDR3_1600J is not set
-# CONFIG_DDR_TYPE_DDR3_1600K is not set
-# CONFIG_DDR_TYPE_DDR3_1866J is not set
-# CONFIG_DDR_TYPE_DDR3_1866K is not set
-# CONFIG_DDR_TYPE_DDR3_1866L is not set
-# CONFIG_DDR_TYPE_DDR3_1866M is not set
-# CONFIG_DDR_TYPE_DDR3_2133K is not set
-# CONFIG_DDR_TYPE_DDR3_2133L is not set
-# CONFIG_DDR_TYPE_DDR3_2133M is not set
-# CONFIG_DDR_TYPE_DDR3_2133N is not set
-# CONFIG_DDR_TYPE_DDR3_DEFAULT is not set
-CONFIG_RK29_MEM_SIZE_M=512
-CONFIG_DDR_SDRAM_FREQ=192
-# CONFIG_DDR_FREQ is not set
-# CONFIG_DDR_RECONFIG is not set
-CONFIG_WIFI_CONTROL_FUNC=y
-
-#
-# RK29 VPU (Video Processing Unit) support
-#
-CONFIG_RK29_VPU=y
-# CONFIG_RK29_VPU_DEBUG is not set
-CONFIG_RK29_JTAG=y
-CONFIG_RK29_LAST_LOG=y
-
-#
-# support for RK29 power manage
-#
-# CONFIG_RK29_WORKING_POWER_MANAGEMENT is not set
-CONFIG_RK29_CLK_SWITCH_TO_32K=y
-CONFIG_RK29_GPIO_SUSPEND=y
-CONFIG_RK29_NEON_POWERDOMAIN_SET=y
-# CONFIG_RK29_SPI_INSRAM is not set
-CONFIG_RK29_I2C_INSRAM=y
-# CONFIG_RK29_CHARGE_EARLYSUSPEND is not set
-
-#
-# System MMU
-#
-
-#
-# Processor Type
-#
-CONFIG_CPU_V7=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_THUMBEE=y
-# CONFIG_SWP_EMULATE is not set
-# CONFIG_CPU_ICACHE_DISABLE is not set
-# CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_DMA_MEM_BUFFERABLE=y
-CONFIG_CPU_HAS_PMU=y
-# CONFIG_ARM_ERRATA_430973 is not set
-# CONFIG_ARM_ERRATA_458693 is not set
-# CONFIG_ARM_ERRATA_460075 is not set
-# CONFIG_ARM_ERRATA_743622 is not set
-# CONFIG_ARM_ERRATA_754322 is not set
-CONFIG_ARM_GIC=y
-CONFIG_PL330=y
-# CONFIG_FIQ_DEBUGGER is not set
-
-#
-# Bus support
-#
-# CONFIG_PCI_SYSCALL is not set
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-# CONFIG_PCCARD is not set
-
-#
-# Kernel Features
-#
-CONFIG_TICK_ONESHOT=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_VMSPLIT_3G=y
-# CONFIG_VMSPLIT_2G is not set
-# CONFIG_VMSPLIT_1G is not set
-CONFIG_PAGE_OFFSET=0xC0000000
-# CONFIG_PREEMPT_NONE is not set
-# CONFIG_PREEMPT_VOLUNTARY is not set
-CONFIG_PREEMPT=y
-CONFIG_HZ=100
-# CONFIG_THUMB2_KERNEL is not set
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HIGHMEM=y
-# CONFIG_HIGHPTE is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_SPLIT_PTLOCK_CPUS=4
-CONFIG_COMPACTION=y
-CONFIG_MIGRATION=y
-# CONFIG_PHYS_ADDR_T_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=1
-CONFIG_BOUNCE=y
-CONFIG_VIRT_TO_BUS=y
-# CONFIG_KSM is not set
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_NEED_PER_CPU_KM=y
-# CONFIG_CLEANCACHE is not set
-CONFIG_FORCE_MAX_ZONEORDER=11
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_UACCESS_WITH_MEMCPY is not set
-# CONFIG_SECCOMP is not set
-# CONFIG_CC_STACKPROTECTOR is not set
-# CONFIG_DEPRECATED_PARAM_STRUCT is not set
-# CONFIG_ARM_FLUSH_CONSOLE_ON_RESTART is not set
-
-#
-# Boot options
-#
-# CONFIG_USE_OF is not set
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_CMDLINE=""
-# CONFIG_XIP_KERNEL is not set
-# CONFIG_KEXEC is not set
-# CONFIG_CRASH_DUMP is not set
-# CONFIG_AUTO_ZRELADDR is not set
-
-#
-# CPU Power Management
-#
-
-#
-# CPU Frequency scaling
-#
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_TABLE=y
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_FREQ_STAT_DETAILS=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-# CONFIG_CPU_FREQ_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
-CONFIG_CPU_FREQ_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-# CONFIG_CPU_IDLE is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_NEON=y
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-CONFIG_HAVE_AOUT=y
-# CONFIG_BINFMT_AOUT is not set
-# CONFIG_BINFMT_MISC is not set
-
-#
-# Power management options
-#
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_HAS_WAKELOCK=y
-CONFIG_HAS_EARLYSUSPEND=y
-CONFIG_WAKELOCK=y
-CONFIG_WAKELOCK_STAT=y
-CONFIG_USER_WAKELOCK=y
-CONFIG_EARLYSUSPEND=y
-# CONFIG_NO_USER_SPACE_SCREEN_ACCESS_CONTROL is not set
-# CONFIG_CONSOLE_EARLYSUSPEND is not set
-CONFIG_FB_EARLYSUSPEND=y
-CONFIG_PM_SLEEP=y
-# CONFIG_PM_RUNTIME is not set
-CONFIG_PM=y
-# CONFIG_PM_DEBUG is not set
-# CONFIG_APM_EMULATION is not set
-# CONFIG_SUSPEND_TIME is not set
-CONFIG_SUSPEND_SYNC_WORKQUEUE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
-# CONFIG_XFRM_STATISTICS is not set
-CONFIG_XFRM_IPCOMP=y
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-# CONFIG_IP_FIB_TRIE_STATS is not set
-CONFIG_IP_MULTIPLE_TABLES=y
-# CONFIG_IP_ROUTE_MULTIPATH is not set
-# CONFIG_IP_ROUTE_VERBOSE is not set
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE_DEMUX is not set
-# CONFIG_IP_MROUTE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-CONFIG_INET_TUNNEL=y
-CONFIG_INET_XFRM_MODE_TRANSPORT=y
-CONFIG_INET_XFRM_MODE_TUNNEL=y
-CONFIG_INET_XFRM_MODE_BEET=y
-# CONFIG_INET_LRO is not set
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-# CONFIG_IPV6_ROUTE_INFO is not set
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_INET6_XFRM_TUNNEL=y
-CONFIG_INET6_TUNNEL=y
-CONFIG_INET6_XFRM_MODE_TRANSPORT=y
-CONFIG_INET6_XFRM_MODE_TUNNEL=y
-CONFIG_INET6_XFRM_MODE_BEET=y
-# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
-CONFIG_IPV6_SIT=y
-# CONFIG_IPV6_SIT_6RD is not set
-CONFIG_IPV6_NDISC_NODETYPE=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-# CONFIG_IPV6_SUBTREES is not set
-# CONFIG_IPV6_MROUTE is not set
-CONFIG_ANDROID_PARANOID_NETWORK=y
-CONFIG_NET_ACTIVITY_STATS=y
-# CONFIG_NETWORK_SECMARK is not set
-# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
-CONFIG_NETFILTER=y
-CONFIG_NETFILTER_DEBUG=y
-CONFIG_NETFILTER_ADVANCED=y
-CONFIG_BRIDGE_NETFILTER=y
-
-#
-# Core Netfilter Configuration
-#
-CONFIG_NETFILTER_NETLINK=y
-CONFIG_NETFILTER_NETLINK_QUEUE=y
-CONFIG_NETFILTER_NETLINK_LOG=y
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_MARK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-# CONFIG_NF_CONNTRACK_TIMESTAMP is not set
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_GRE=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_BROADCAST=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-# CONFIG_NF_CONNTRACK_SNMP is not set
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XTABLES=y
-
-#
-# Xtables combined modules
-#
-CONFIG_NETFILTER_XT_MARK=y
-CONFIG_NETFILTER_XT_CONNMARK=y
-
-#
-# Xtables targets
-#
-# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-# CONFIG_NETFILTER_XT_TARGET_CT is not set
-# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
-# CONFIG_NETFILTER_XT_TARGET_HL is not set
-# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set
-# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
-# CONFIG_NETFILTER_XT_TARGET_TEE is not set
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
-# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
-
-#
-# Xtables matches
-#
-# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set
-# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-# CONFIG_NETFILTER_XT_MATCH_CPU is not set
-# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
-# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set
-# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
-# CONFIG_NETFILTER_XT_MATCH_ESP is not set
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_HL=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set
-# CONFIG_NETFILTER_XT_MATCH_OSF is not set
-# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
-# CONFIG_NETFILTER_XT_MATCH_REALM is not set
-# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
-# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-# CONFIG_IP_SET is not set
-# CONFIG_IP_VS is not set
-
-#
-# IP: Netfilter Configuration
-#
-CONFIG_NF_DEFRAG_IPV4=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_NF_CONNTRACK_PROC_COMPAT=y
-# CONFIG_IP_NF_QUEUE is not set
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-# CONFIG_IP_NF_TARGET_ULOG is not set
-CONFIG_NF_NAT=y
-CONFIG_NF_NAT_NEEDED=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_NF_NAT_PROTO_DCCP=y
-CONFIG_NF_NAT_PROTO_GRE=y
-CONFIG_NF_NAT_PROTO_UDPLITE=y
-CONFIG_NF_NAT_PROTO_SCTP=y
-CONFIG_NF_NAT_FTP=y
-CONFIG_NF_NAT_IRC=y
-CONFIG_NF_NAT_TFTP=y
-CONFIG_NF_NAT_AMANDA=y
-CONFIG_NF_NAT_PPTP=y
-CONFIG_NF_NAT_H323=y
-CONFIG_NF_NAT_SIP=y
-CONFIG_IP_NF_MANGLE=y
-# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
-# CONFIG_IP_NF_TARGET_ECN is not set
-# CONFIG_IP_NF_TARGET_TTL is not set
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-
-#
-# IPv6: Netfilter Configuration
-#
-CONFIG_NF_DEFRAG_IPV6=y
-CONFIG_NF_CONNTRACK_IPV6=y
-# CONFIG_IP6_NF_QUEUE is not set
-CONFIG_IP6_NF_IPTABLES=y
-# CONFIG_IP6_NF_MATCH_AH is not set
-# CONFIG_IP6_NF_MATCH_EUI64 is not set
-# CONFIG_IP6_NF_MATCH_FRAG is not set
-# CONFIG_IP6_NF_MATCH_OPTS is not set
-# CONFIG_IP6_NF_MATCH_HL is not set
-# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set
-# CONFIG_IP6_NF_MATCH_MH is not set
-# CONFIG_IP6_NF_MATCH_RT is not set
-# CONFIG_IP6_NF_TARGET_HL is not set
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-# CONFIG_BRIDGE_NF_EBTABLES is not set
-# CONFIG_IP_DCCP is not set
-# CONFIG_IP_SCTP is not set
-# CONFIG_RDS is not set
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_L2TP is not set
-CONFIG_STP=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-# CONFIG_NET_DSA is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-CONFIG_LLC=y
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-CONFIG_PHONET=y
-# CONFIG_IEEE802154 is not set
-CONFIG_NET_SCHED=y
-
-#
-# Queueing/Scheduling
-#
-# CONFIG_NET_SCH_CBQ is not set
-CONFIG_NET_SCH_HTB=y
-# CONFIG_NET_SCH_HFSC is not set
-# CONFIG_NET_SCH_PRIO is not set
-# CONFIG_NET_SCH_MULTIQ is not set
-# CONFIG_NET_SCH_RED is not set
-# CONFIG_NET_SCH_SFB is not set
-# CONFIG_NET_SCH_SFQ is not set
-# CONFIG_NET_SCH_TEQL is not set
-# CONFIG_NET_SCH_TBF is not set
-# CONFIG_NET_SCH_GRED is not set
-# CONFIG_NET_SCH_DSMARK is not set
-# CONFIG_NET_SCH_NETEM is not set
-# CONFIG_NET_SCH_DRR is not set
-# CONFIG_NET_SCH_MQPRIO is not set
-# CONFIG_NET_SCH_CHOKE is not set
-# CONFIG_NET_SCH_QFQ is not set
-CONFIG_NET_SCH_INGRESS=y
-
-#
-# Classification
-#
-CONFIG_NET_CLS=y
-# CONFIG_NET_CLS_BASIC is not set
-# CONFIG_NET_CLS_TCINDEX is not set
-# CONFIG_NET_CLS_ROUTE4 is not set
-# CONFIG_NET_CLS_FW is not set
-CONFIG_NET_CLS_U32=y
-# CONFIG_CLS_U32_PERF is not set
-# CONFIG_CLS_U32_MARK is not set
-# CONFIG_NET_CLS_RSVP is not set
-# CONFIG_NET_CLS_RSVP6 is not set
-# CONFIG_NET_CLS_FLOW is not set
-# CONFIG_NET_CLS_CGROUP is not set
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_STACK=32
-# CONFIG_NET_EMATCH_CMP is not set
-# CONFIG_NET_EMATCH_NBYTE is not set
-CONFIG_NET_EMATCH_U32=y
-# CONFIG_NET_EMATCH_META is not set
-# CONFIG_NET_EMATCH_TEXT is not set
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-# CONFIG_GACT_PROB is not set
-CONFIG_NET_ACT_MIRRED=y
-# CONFIG_NET_ACT_IPT is not set
-# CONFIG_NET_ACT_NAT is not set
-# CONFIG_NET_ACT_PEDIT is not set
-# CONFIG_NET_ACT_SIMP is not set
-# CONFIG_NET_ACT_SKBEDIT is not set
-# CONFIG_NET_ACT_CSUM is not set
-# CONFIG_NET_CLS_IND is not set
-CONFIG_NET_SCH_FIFO=y
-# CONFIG_DCB is not set
-# CONFIG_BATMAN_ADV is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_CAN is not set
-# CONFIG_IRDA is not set
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-# CONFIG_BT_BNEP_MC_FILTER is not set
-# CONFIG_BT_BNEP_PROTO_FILTER is not set
-CONFIG_BT_HIDP=y
-
-#
-# Bluetooth device drivers
-#
-# CONFIG_BT_HCIBTUSB is not set
-# CONFIG_BT_HCIBTSDIO is not set
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-# CONFIG_BT_HCIUART_BCSP is not set
-# CONFIG_BT_HCIUART_ATH3K is not set
-# CONFIG_BT_HCIUART_LL is not set
-# CONFIG_BT_HCIBCM203X is not set
-# CONFIG_BT_HCIBPA10X is not set
-# CONFIG_BT_HCIBFUSB is not set
-# CONFIG_BT_HCIVHCI is not set
-# CONFIG_BT_MRVL is not set
-CONFIG_BT_HCIBCM4325=y
-CONFIG_IDBLOCK=y
-# CONFIG_WIFI_MAC is not set
-# CONFIG_AF_RXRPC is not set
-CONFIG_FIB_RULES=y
-CONFIG_WIRELESS=y
-CONFIG_WIRELESS_EXT=y
-CONFIG_WEXT_CORE=y
-CONFIG_WEXT_PROC=y
-CONFIG_WEXT_PRIV=y
-# CONFIG_CFG80211 is not set
-CONFIG_WIRELESS_EXT_SYSFS=y
-# CONFIG_LIB80211 is not set
-
-#
-# CFG80211 needs to be enabled for MAC80211
-#
-# CONFIG_WIMAX is not set
-CONFIG_RFKILL=y
-# CONFIG_RFKILL_PM is not set
-# CONFIG_RFKILL_INPUT is not set
-# CONFIG_RFKILL_REGULATOR is not set
-# CONFIG_RFKILL_GPIO is not set
-# CONFIG_NET_9P is not set
-# CONFIG_CAIF is not set
-# CONFIG_CEPH_LIB is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_CONNECTOR is not set
-CONFIG_MTD=y
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_TESTS is not set
-# CONFIG_MTD_REDBOOT_PARTS is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_AFS_PARTS is not set
-# CONFIG_MTD_AR7_PARTS is not set
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
-# CONFIG_INFTL is not set
-# CONFIG_RFD_FTL is not set
-# CONFIG_SSFDC is not set
-# CONFIG_SM_FTL is not set
-# CONFIG_MTD_OOPS is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-# CONFIG_MTD_CFI is not set
-# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_ABSENT is not set
-
-#
-# Mapping drivers for chip access
-#
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_PLATRAM is not set
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_DATAFLASH is not set
-# CONFIG_MTD_M25P80 is not set
-# CONFIG_MTD_SST25L is not set
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLOCK2MTD is not set
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-CONFIG_MTD_NAND_IDS=y
-# CONFIG_MTD_NAND is not set
-CONFIG_MTD_RKNAND=y
-CONFIG_MTD_NAND_RK29XX=y
-CONFIG_MTD_RKNAND_BUFFER=y
-# CONFIG_MTD_EMMC_CLK_POWER_SAVE is not set
-# CONFIG_MTD_NAND_RK29XX_DEBUG is not set
-# CONFIG_MTD_ONENAND is not set
-
-#
-# LPDDR flash memory drivers
-#
-# CONFIG_MTD_LPDDR is not set
-# CONFIG_MTD_UBI is not set
-# CONFIG_PARPORT is not set
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=y
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-
-#
-# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
-#
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_UB is not set
-# CONFIG_BLK_DEV_RAM is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-# CONFIG_MG_DISK is not set
-# CONFIG_BLK_DEV_RBD is not set
-# CONFIG_SENSORS_LIS3LV02D is not set
-CONFIG_MISC_DEVICES=y
-# CONFIG_AD525X_DPOT is not set
-CONFIG_ANDROID_PMEM=y
-# CONFIG_INTEL_MID_PTI is not set
-# CONFIG_ICS932S401 is not set
-# CONFIG_ENCLOSURE_SERVICES is not set
-# CONFIG_APDS9802ALS is not set
-# CONFIG_ISL29003 is not set
-# CONFIG_ISL29020 is not set
-# CONFIG_SENSORS_TSL2550 is not set
-# CONFIG_SENSORS_BH1780 is not set
-# CONFIG_SENSORS_BH1770 is not set
-# CONFIG_SENSORS_APDS990X is not set
-# CONFIG_HMC6352 is not set
-# CONFIG_SENSORS_AK8975 is not set
-# CONFIG_DS1682 is not set
-# CONFIG_TI_DAC7512 is not set
-CONFIG_UID_STAT=y
-# CONFIG_BMP085 is not set
-# CONFIG_WL127X_RFKILL is not set
-CONFIG_APANIC=y
-CONFIG_APANIC_PLABEL="kpanic"
-# CONFIG_STE is not set
-# CONFIG_MTK23D is not set
-# CONFIG_FM580X is not set
-# CONFIG_MU509 is not set
-# CONFIG_MW100 is not set
-# CONFIG_RK29_NEWTON is not set
-CONFIG_RK29_SC8800=y
-CONFIG_TDSC8800=y
-# CONFIG_C2PORT is not set
-
-#
-# EEPROM support
-#
-# CONFIG_EEPROM_AT24 is not set
-# CONFIG_EEPROM_AT25 is not set
-# CONFIG_EEPROM_LEGACY is not set
-# CONFIG_EEPROM_MAX6875 is not set
-# CONFIG_EEPROM_93CX6 is not set
-# CONFIG_RK29_SUPPORT_MODEM is not set
-CONFIG_RK29_GPS=y
-CONFIG_GPS_GNS7560=y
-# CONFIG_MPU_SENSORS_TIMERIRQ is not set
-# CONFIG_INV_SENSORS is not set
-# CONFIG_IWMC3200TOP is not set
-
-#
-# Texas Instruments shared transport line discipline
-#
-# CONFIG_TI_ST is not set
-# CONFIG_SENSORS_LIS3_SPI is not set
-# CONFIG_SENSORS_LIS3_I2C is not set
-CONFIG_HAVE_IDE=y
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-CONFIG_SCSI_MOD=y
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_DMA=y
-# CONFIG_SCSI_TGT is not set
-# CONFIG_SCSI_NETLINK is not set
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=y
-# CONFIG_CHR_DEV_ST is not set
-# CONFIG_CHR_DEV_OSST is not set
-# CONFIG_BLK_DEV_SR is not set
-# CONFIG_CHR_DEV_SG is not set
-# CONFIG_CHR_DEV_SCH is not set
-CONFIG_SCSI_MULTI_LUN=y
-# CONFIG_SCSI_CONSTANTS is not set
-# CONFIG_SCSI_LOGGING is not set
-# CONFIG_SCSI_SCAN_ASYNC is not set
-CONFIG_SCSI_WAIT_SCAN=m
-
-#
-# SCSI Transports
-#
-# CONFIG_SCSI_SPI_ATTRS is not set
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
-# CONFIG_SCSI_SAS_LIBSAS is not set
-# CONFIG_SCSI_SRP_ATTRS is not set
-CONFIG_SCSI_LOWLEVEL=y
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_ISCSI_BOOT_SYSFS is not set
-# CONFIG_LIBFC is not set
-# CONFIG_LIBFCOE is not set
-# CONFIG_SCSI_DEBUG is not set
-# CONFIG_SCSI_DH is not set
-# CONFIG_SCSI_OSD_INITIATOR is not set
-# CONFIG_ATA is not set
-CONFIG_MD=y
-# CONFIG_BLK_DEV_MD is not set
-CONFIG_BLK_DEV_DM=y
-# CONFIG_DM_DEBUG is not set
-CONFIG_DM_CRYPT=y
-# CONFIG_DM_SNAPSHOT is not set
-# CONFIG_DM_MIRROR is not set
-# CONFIG_DM_RAID is not set
-# CONFIG_DM_ZERO is not set
-# CONFIG_DM_MULTIPATH is not set
-# CONFIG_DM_DELAY is not set
-CONFIG_DM_UEVENT=y
-# CONFIG_DM_FLAKEY is not set
-# CONFIG_TARGET_CORE is not set
-CONFIG_NETDEVICES=y
-# CONFIG_IFB is not set
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_MACVLAN is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_VETH is not set
-CONFIG_MII=y
-CONFIG_PHYLIB=y
-
-#
-# MII PHY device drivers
-#
-# CONFIG_MARVELL_PHY is not set
-# CONFIG_DAVICOM_PHY is not set
-# CONFIG_QSEMI_PHY is not set
-# CONFIG_LXT_PHY is not set
-# CONFIG_CICADA_PHY is not set
-# CONFIG_VITESSE_PHY is not set
-# CONFIG_SMSC_PHY is not set
-# CONFIG_BROADCOM_PHY is not set
-# CONFIG_ICPLUS_PHY is not set
-# CONFIG_REALTEK_PHY is not set
-# CONFIG_NATIONAL_PHY is not set
-# CONFIG_STE10XP is not set
-# CONFIG_LSI_ET1011C_PHY is not set
-# CONFIG_MICREL_PHY is not set
-# CONFIG_FIXED_PHY is not set
-# CONFIG_MDIO_BITBANG is not set
-CONFIG_NET_ETHERNET=y
-# CONFIG_AX88796 is not set
-# CONFIG_RK29_VMAC is not set
-# CONFIG_SMC91X is not set
-# CONFIG_DM9000 is not set
-# CONFIG_ENC28J60 is not set
-# CONFIG_ETHOC is not set
-# CONFIG_SMC911X is not set
-# CONFIG_SMSC911X is not set
-# CONFIG_DNET is not set
-# CONFIG_IBM_NEW_EMAC_ZMII is not set
-# CONFIG_IBM_NEW_EMAC_RGMII is not set
-# CONFIG_IBM_NEW_EMAC_TAH is not set
-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
-# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
-# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
-# CONFIG_B44 is not set
-# CONFIG_KS8851 is not set
-# CONFIG_KS8851_MLL is not set
-# CONFIG_FTMAC100 is not set
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN=y
-CONFIG_WLAN_80211=y
-# CONFIG_WIFI_NONE is not set
-CONFIG_BCM4329=y
-# CONFIG_BCM4319 is not set
-# CONFIG_MV8686 is not set
-# CONFIG_AR6003 is not set
-
-#
-# Enable WiMAX (Networking options) to see the WiMAX drivers
-#
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET is not set
-# CONFIG_USB_HSO is not set
-# CONFIG_USB_CDC_PHONET is not set
-# CONFIG_USB_IPHETH is not set
-# CONFIG_WAN is not set
-
-#
-# CAIF transport drivers
-#
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-#CONFIG_PPPOE is not set
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_SLIP is not set
-CONFIG_SLHC=y
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_ISDN is not set
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-CONFIG_INPUT_FF_MEMLESS=y
-CONFIG_INPUT_POLLDEV=y
-# CONFIG_INPUT_SPARSEKMAP is not set
-
-#
-# Userland interfaces
-#
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_JOYDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_EVBUG is not set
-CONFIG_INPUT_KEYRESET=y
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYS_RK29=y
-# CONFIG_KEYS_RK29_NEWTON is not set
-# CONFIG_SYNAPTICS_SO340010 is not set
-# CONFIG_KEYBOARD_ADP5588 is not set
-# CONFIG_KEYBOARD_ADP5589 is not set
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_KEYBOARD_QT1070 is not set
-# CONFIG_KEYBOARD_QT2160 is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_GPIO is not set
-# CONFIG_KEYBOARD_WM831X_GPIO is not set
-# CONFIG_KEYBOARD_TCA6416 is not set
-# CONFIG_KEYBOARD_MATRIX is not set
-# CONFIG_KEYBOARD_LM8323 is not set
-# CONFIG_KEYBOARD_MAX7359 is not set
-# CONFIG_KEYBOARD_MCS is not set
-# CONFIG_KEYBOARD_MPR121 is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_OPENCORES is not set
-# CONFIG_KEYBOARD_STOWAWAY is not set
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-# CONFIG_TOUCHSCREEN_XPT2046_SPI is not set
-# CONFIG_TOUCHSCREEN_ADS7846 is not set
-# CONFIG_TOUCHSCREEN_AD7877 is not set
-# CONFIG_TOUCHSCREEN_ILI2102_IIC is not set
-# CONFIG_TOUCHSCREEN_GT8XX is not set
-# CONFIG_TOUCHSCREEN_IT7250 is not set
-# CONFIG_TOUCHSCREEN_AD7879 is not set
-# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
-# CONFIG_TOUCHSCREEN_BU21013 is not set
-# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
-# CONFIG_TOUCHSCREEN_DYNAPRO is not set
-# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
-# CONFIG_TOUCHSCREEN_EETI is not set
-# CONFIG_TOUCHSCREEN_FUJITSU is not set
-# CONFIG_TOUCHSCREEN_GUNZE is not set
-# CONFIG_TOUCHSCREEN_ELO is not set
-# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
-# CONFIG_TOUCHSCREEN_MAX11801 is not set
-# CONFIG_TOUCHSCREEN_MCS5000 is not set
-# CONFIG_TOUCHSCREEN_MTOUCH is not set
-# CONFIG_TOUCHSCREEN_INEXIO is not set
-# CONFIG_TOUCHSCREEN_MK712 is not set
-# CONFIG_TOUCHSCREEN_PENMOUNT is not set
-# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI is not set
-# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
-# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-# CONFIG_TOUCHSCREEN_WM831X is not set
-# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
-# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
-# CONFIG_TOUCHSCREEN_TSC2005 is not set
-# CONFIG_TOUCHSCREEN_TSC2007 is not set
-# CONFIG_TOUCHSCREEN_W90X900 is not set
-# CONFIG_TOUCHSCREEN_ST1232 is not set
-# CONFIG_TOUCHSCREEN_TPS6507X is not set
-# CONFIG_HANNSTAR_P1003 is not set
-# CONFIG_ATMEL_MXT224 is not set
-# CONFIG_SINTEK_3FA16 is not set
-# CONFIG_EETI_EGALAX is not set
-# CONFIG_TOUCHSCREEN_IT7260 is not set
-# CONFIG_TOUCHSCREEN_IT7260_I2C is not set
-# CONFIG_TOUCHSCREEN_NAS is not set
-# CONFIG_LAIBAO_TS is not set
-# CONFIG_TOUCHSCREEN_GT801_IIC is not set
-# CONFIG_TOUCHSCREEN_GT818_IIC is not set
-CONFIG_TOUCHSCREEN_PIXCIR=y
-# CONFIG_D70_L3188A is not set
-# CONFIG_TOUCHSCREEN_GT819 is not set
-# CONFIG_TOUCHSCREEN_FT5306 is not set
-# CONFIG_TOUCHSCREEN_FT5406 is not set
-# CONFIG_ATMEL_MXT1386 is not set
-CONFIG_INPUT_MISC=y
-# CONFIG_INPUT_LPSENSOR_ISL29028 is not set
-# CONFIG_INPUT_LPSENSOR_CM3602 is not set
-# CONFIG_INPUT_LPSENSOR_AL3006 is not set
-# CONFIG_INPUT_AD714X is not set
-# CONFIG_INPUT_ATI_REMOTE is not set
-# CONFIG_INPUT_ATI_REMOTE2 is not set
-CONFIG_INPUT_KEYCHORD=y
-# CONFIG_INPUT_KEYSPAN_REMOTE is not set
-# CONFIG_INPUT_POWERMATE is not set
-# CONFIG_INPUT_YEALINK is not set
-# CONFIG_INPUT_CM109 is not set
-CONFIG_INPUT_UINPUT=y
-# CONFIG_INPUT_GPIO is not set
-# CONFIG_INPUT_PCF8574 is not set
-# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
-CONFIG_INPUT_WM831X_ON=y
-# CONFIG_INPUT_ADXL34X is not set
-# CONFIG_INPUT_CMA3000 is not set
-CONFIG_MAG_SENSORS=y
-CONFIG_COMPASS_AK8975=y
-# CONFIG_COMPASS_AK8973 is not set
-# CONFIG_COMPASS_MMC328X is not set
-CONFIG_G_SENSOR_DEVICE=y
-# CONFIG_GS_MMA7660 is not set
-# CONFIG_GS_MMA8452 is not set
-# CONFIG_GS_KXTF9 is not set
-# CONFIG_GS_LIS3DH is not set
-# CONFIG_GS_L3G4200D is not set
-CONFIG_GS_BMA023=y
-# CONFIG_GYRO_SENSOR_DEVICE is not set
-# CONFIG_INPUT_JOGBALL is not set
-# CONFIG_LIGHT_SENSOR_DEVICE is not set
-
-#
-# Hardware I/O ports
-#
-# CONFIG_SERIO is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_UNIX98_PTYS=y
-# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_SERIAL_NONSTANDARD is not set
-# CONFIG_N_GSM is not set
-# CONFIG_TRACE_SINK is not set
-CONFIG_DEVMEM=y
-CONFIG_DEVKMEM=y
-
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-
-#
-# Non-8250 serial port support
-#
-# CONFIG_SERIAL_MAX3100 is not set
-# CONFIG_SERIAL_MAX3107 is not set
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-# CONFIG_SERIAL_TIMBERDALE is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-# CONFIG_UART0_DMA_RK29 is not set
-CONFIG_UART1_RK29=y
-CONFIG_UART2_RK29=y
-CONFIG_UART2_CTS_RTS_RK29=y
-# CONFIG_UART2_DMA_RK29 is not set
-CONFIG_UART3_RK29=y
-# CONFIG_UART3_CTS_RTS_RK29 is not set
-# CONFIG_UART3_DMA_RK29 is not set
-CONFIG_SERIAL_RK29_CONSOLE=y
-# CONFIG_SERIAL_SC8800 is not set
-# CONFIG_SERIAL_ALTERA_JTAGUART is not set
-# CONFIG_SERIAL_ALTERA_UART is not set
-# CONFIG_SERIAL_IFX6X60 is not set
-# CONFIG_SERIAL_XILINX_PS_UART is not set
-# CONFIG_TTY_PRINTK is not set
-# CONFIG_HVC_DCC is not set
-# CONFIG_IPMI_HANDLER is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_R3964 is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_TCG_TPM is not set
-# CONFIG_DCC_TTY is not set
-# CONFIG_RAMOOPS is not set
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_COMPAT=y
-# CONFIG_I2C_CHARDEV is not set
-# CONFIG_I2C_MUX is not set
-CONFIG_I2C_HELPER_AUTO=y
-
-#
-# I2C Hardware Bus support
-#
-
-#
-# I2C system bus drivers (mostly embedded / system-on-chip)
-#
-# CONFIG_I2C_DESIGNWARE is not set
-# CONFIG_I2C_GPIO is not set
-# CONFIG_I2C_OCORES is not set
-# CONFIG_I2C_PCA_PLATFORM is not set
-# CONFIG_I2C_PXA_PCI is not set
-# CONFIG_I2C_SIMTEC is not set
-# CONFIG_I2C_XILINX is not set
-
-#
-# External I2C/SMBus adapter drivers
-#
-# CONFIG_I2C_DIOLAN_U2C is not set
-# CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_TAOS_EVM is not set
-# CONFIG_I2C_TINY_USB is not set
-
-#
-# Other I2C/SMBus bus drivers
-#
-# CONFIG_I2C_STUB is not set
-CONFIG_I2C_RK29=y
-
-#
-# Now, there are four I2C interfaces selected by developer.
-#
-CONFIG_I2C0_RK29=y
-CONFIG_RK29_I2C0_CONTROLLER=y
-# CONFIG_RK29_I2C0_GPIO is not set
-CONFIG_I2C1_RK29=y
-CONFIG_RK29_I2C1_CONTROLLER=y
-# CONFIG_RK29_I2C1_GPIO is not set
-CONFIG_I2C2_RK29=y
-CONFIG_RK29_I2C2_CONTROLLER=y
-# CONFIG_RK29_I2C2_GPIO is not set
-CONFIG_I2C3_RK29=y
-CONFIG_RK29_I2C3_CONTROLLER=y
-# CONFIG_RK29_I2C3_GPIO is not set
-# CONFIG_I2C_DEV_RK29 is not set
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-CONFIG_SPI=y
-# CONFIG_SPI_DEBUG is not set
-CONFIG_SPI_MASTER=y
-
-#
-# SPI Master Controller Drivers
-#
-# CONFIG_SPI_ALTERA is not set
-# CONFIG_SPI_BITBANG is not set
-# CONFIG_SPI_GPIO is not set
-# CONFIG_SPI_OC_TINY is not set
-# CONFIG_SPI_PXA2XX_PCI is not set
-# CONFIG_SPI_XILINX is not set
-CONFIG_SPIM_RK29=y
-CONFIG_SPIM0_RK29=y
-CONFIG_SPIM1_RK29=y
-CONFIG_LCD_USE_SPIM_CONTROL=y
-# CONFIG_LCD_USE_SPI0 is not set
-CONFIG_LCD_USE_SPI1=y
-# CONFIG_SPI_DESIGNWARE is not set
-
-#
-# SPI Protocol Masters
-#
-# CONFIG_SPI_SPIDEV is not set
-# CONFIG_SPI_TLE62X0 is not set
-CONFIG_ADC=y
-# CONFIG_ADC_RK28 is not set
-CONFIG_ADC_RK29=y
-
-#
-# Headset device support
-#
-CONFIG_RK_HEADSET_DET=y
-
-#
-# PPS support
-#
-# CONFIG_PPS is not set
-
-#
-# PPS generators support
-#
-
-#
-# PTP clock support
-#
-
-#
-# Enable Device Drivers -> PPS to see the PTP clock options.
-#
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_GPIOLIB=y
-# CONFIG_DEBUG_GPIO is not set
-# CONFIG_GPIO_SYSFS is not set
-
-#
-# Memory mapped GPIO drivers:
-#
-# CONFIG_GPIO_BASIC_MMIO is not set
-# CONFIG_GPIO_IT8761E is not set
-
-#
-# I2C GPIO expanders:
-#
-# CONFIG_GPIO_MAX7300 is not set
-# CONFIG_GPIO_MAX732X is not set
-# CONFIG_GPIO_PCF857X is not set
-# CONFIG_GPIO_SX150X is not set
-CONFIG_GPIO_WM831X=y
-CONFIG_GPIO_WM8994=y
-# CONFIG_GPIO_ADP5588 is not set
-
-#
-# PCI GPIO expanders:
-#
-
-#
-# SPI GPIO expanders:
-#
-# CONFIG_GPIO_MAX7301 is not set
-# CONFIG_GPIO_MCP23S08 is not set
-# CONFIG_GPIO_MC33880 is not set
-# CONFIG_GPIO_74X164 is not set
-
-#
-# AC97 GPIO expanders:
-#
-# CONFIG_GPIO_PCA9554 is not set
-# CONFIG_IOEXTEND_TCA6424 is not set
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-# CONFIG_EXPAND_GPIO_SOFT_INTERRUPT is not set
-CONFIG_SPI_FPGA_GPIO_NUM=96
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=16
-
-#
-# MODULbus GPIO expanders:
-#
-# CONFIG_W1 is not set
-CONFIG_POWER_SUPPLY=y
-# CONFIG_POWER_SUPPLY_DEBUG is not set
-# CONFIG_PDA_POWER is not set
-CONFIG_WM831X_BACKUP=y
-CONFIG_WM831X_POWER=y
-# CONFIG_WM831X_CHARGER_DISPLAY is not set
-# CONFIG_WM831X_WITH_BATTERY is not set
-# CONFIG_TEST_POWER is not set
-# CONFIG_BATTERY_DS2780 is not set
-# CONFIG_BATTERY_DS2782 is not set
-# CONFIG_BATTERY_BQ20Z75 is not set
-# CONFIG_BATTERY_BQ27x00 is not set
-# CONFIG_BATTERY_MAX17040 is not set
-# CONFIG_BATTERY_MAX17042 is not set
-# CONFIG_BATTERY_STC3100 is not set
-# CONFIG_BATTERY_BQ27510 is not set
-# CONFIG_BATTERY_BQ27541 is not set
-# CONFIG_BATTERY_BQ3060 is not set
-# CONFIG_CHARGER_MAX8903 is not set
-# CONFIG_CHARGER_GPIO is not set
-# CONFIG_BATTERY_RK29_ADC is not set
-CONFIG_POWER_ON_CHARGER_DISPLAY=y
-# CONFIG_HWMON is not set
-# CONFIG_THERMAL is not set
-# CONFIG_WATCHDOG is not set
-CONFIG_SSB_POSSIBLE=y
-
-#
-# Sonics Silicon Backplane
-#
-# CONFIG_SSB is not set
-CONFIG_BCMA_POSSIBLE=y
-
-#
-# Broadcom specific AMBA
-#
-# CONFIG_BCMA is not set
-CONFIG_MFD_SUPPORT=y
-CONFIG_MFD_CORE=y
-# CONFIG_MFD_88PM860X is not set
-# CONFIG_MFD_SM501 is not set
-# CONFIG_MFD_ASIC3 is not set
-# CONFIG_HTC_EGPIO is not set
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_HTC_I2CPLD is not set
-# CONFIG_TPS6105X is not set
-# CONFIG_TPS65010 is not set
-# CONFIG_TPS6507X is not set
-# CONFIG_MFD_TPS6586X is not set
-# CONFIG_TWL4030_CORE is not set
-# CONFIG_MFD_STMPE is not set
-# CONFIG_MFD_TC3589X is not set
-# CONFIG_MFD_TMIO is not set
-# CONFIG_MFD_T7L66XB is not set
-# CONFIG_MFD_TC6387XB is not set
-# CONFIG_MFD_TC6393XB is not set
-# CONFIG_PMIC_DA903X is not set
-# CONFIG_PMIC_ADP5520 is not set
-# CONFIG_MFD_MAX8925 is not set
-# CONFIG_MFD_MAX8997 is not set
-# CONFIG_MFD_MAX8998 is not set
-# CONFIG_MFD_WM8400 is not set
-CONFIG_MFD_WM831X=y
-CONFIG_MFD_WM831X_I2C=y
-# CONFIG_MFD_WM831X_SPI is not set
-# CONFIG_MFD_WM831X_SPI_A22 is not set
-# CONFIG_MFD_WM8350_I2C is not set
-CONFIG_MFD_WM8994=y
-# CONFIG_MFD_PCF50633 is not set
-# CONFIG_MFD_MC13XXX is not set
-# CONFIG_ABX500_CORE is not set
-# CONFIG_EZX_PCAP is not set
-# CONFIG_MFD_WL1273_CORE is not set
-# CONFIG_MFD_TPS65910 is not set
-CONFIG_REGULATOR=y
-# CONFIG_REGULATOR_DEBUG is not set
-# CONFIG_REGULATOR_DUMMY is not set
-# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
-# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
-# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
-# CONFIG_REGULATOR_BQ24022 is not set
-# CONFIG_REGULATOR_MAX1586 is not set
-# CONFIG_REGULATOR_MAX8649 is not set
-# CONFIG_REGULATOR_MAX8660 is not set
-# CONFIG_REGULATOR_MAX8952 is not set
-CONFIG_REGULATOR_WM831X=y
-CONFIG_REGULATOR_WM8994=y
-# CONFIG_REGULATOR_LP3971 is not set
-# CONFIG_REGULATOR_LP3972 is not set
-# CONFIG_REGULATOR_TPS65023 is not set
-# CONFIG_REGULATOR_TPS6507X is not set
-# CONFIG_RK2818_REGULATOR_CHARGE is not set
-# CONFIG_RK2818_REGULATOR_LP8725 is not set
-# CONFIG_REGULATOR_ACT8891 is not set
-# CONFIG_RK29_PWM_REGULATOR is not set
-# CONFIG_REGULATOR_ISL6271A is not set
-# CONFIG_REGULATOR_AD5398 is not set
-# CONFIG_REGULATOR_TPS6524X is not set
-CONFIG_MEDIA_SUPPORT=y
-
-#
-# Multimedia core support
-#
-# CONFIG_MEDIA_CONTROLLER is not set
-CONFIG_VIDEO_DEV=y
-CONFIG_VIDEO_V4L2_COMMON=y
-# CONFIG_DVB_CORE is not set
-CONFIG_VIDEO_MEDIA=y
-
-#
-# Multimedia drivers
-#
-CONFIG_RC_CORE=y
-CONFIG_LIRC=y
-CONFIG_RC_MAP=y
-CONFIG_IR_NEC_DECODER=y
-CONFIG_IR_RC5_DECODER=y
-CONFIG_IR_RC6_DECODER=y
-CONFIG_IR_JVC_DECODER=y
-CONFIG_IR_SONY_DECODER=y
-CONFIG_IR_RC5_SZ_DECODER=y
-CONFIG_IR_LIRC_CODEC=y
-# CONFIG_IR_IMON is not set
-# CONFIG_IR_MCEUSB is not set
-# CONFIG_IR_REDRAT3 is not set
-# CONFIG_IR_STREAMZAP is not set
-# CONFIG_RC_LOOPBACK is not set
-# CONFIG_MEDIA_ATTACH is not set
-CONFIG_MEDIA_TUNER=y
-# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
-CONFIG_MEDIA_TUNER_SIMPLE=y
-CONFIG_MEDIA_TUNER_TDA8290=y
-CONFIG_MEDIA_TUNER_TDA827X=y
-CONFIG_MEDIA_TUNER_TDA18271=y
-CONFIG_MEDIA_TUNER_TDA9887=y
-CONFIG_MEDIA_TUNER_TEA5761=y
-CONFIG_MEDIA_TUNER_TEA5767=y
-CONFIG_MEDIA_TUNER_MT20XX=y
-CONFIG_MEDIA_TUNER_XC2028=y
-CONFIG_MEDIA_TUNER_XC5000=y
-CONFIG_MEDIA_TUNER_MC44S803=y
-CONFIG_VIDEO_V4L2=y
-CONFIG_VIDEOBUF_GEN=y
-CONFIG_VIDEOBUF_DMA_CONTIG=y
-CONFIG_VIDEOBUF2_CORE=y
-# CONFIG_VIDEO_RK29XX_VOUT is not set
-CONFIG_VIDEO_CAPTURE_DRIVERS=y
-# CONFIG_VIDEO_ADV_DEBUG is not set
-# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
-CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
-CONFIG_VIDEO_IR_I2C=y
-
-#
-# Audio decoders, processors and mixers
-#
-
-#
-# RDS decoders
-#
-
-#
-# Video decoders
-#
-
-#
-# Video and audio decoders
-#
-
-#
-# MPEG video encoders
-#
-
-#
-# Video encoders
-#
-
-#
-# Camera sensor devices
-#
-
-#
-# Video improvement chips
-#
-
-#
-# Miscelaneous helper chips
-#
-# CONFIG_VIDEO_CPIA2 is not set
-# CONFIG_VIDEO_SR030PC30 is not set
-# CONFIG_VIDEO_NOON010PC30 is not set
-CONFIG_SOC_CAMERA=y
-# CONFIG_SOC_CAMERA_IMX074 is not set
-# CONFIG_SOC_CAMERA_MT9M001 is not set
-# CONFIG_SOC_CAMERA_MT9M111 is not set
-# CONFIG_SOC_CAMERA_MT9M112 is not set
-# CONFIG_SOC_CAMERA_MT9T031 is not set
-# CONFIG_SOC_CAMERA_MT9T111 is not set
-# CONFIG_SOC_CAMERA_MT9P111 is not set
-# CONFIG_SOC_CAMERA_MT9D112 is not set
-# CONFIG_SOC_CAMERA_MT9D113 is not set
-# CONFIG_SOC_CAMERA_MT9T112 is not set
-# CONFIG_SOC_CAMERA_MT9V022 is not set
-# CONFIG_SOC_CAMERA_RJ54N1 is not set
-# CONFIG_SOC_CAMERA_TW9910 is not set
-# CONFIG_SOC_CAMERA_PLATFORM is not set
-# CONFIG_SOC_CAMERA_OV2640 is not set
-# CONFIG_SOC_CAMERA_OV6650 is not set
-# CONFIG_SOC_CAMERA_OV772X is not set
-# CONFIG_SOC_CAMERA_OV7675 is not set
-# CONFIG_SOC_CAMERA_OV2655 is not set
-# CONFIG_SOC_CAMERA_OV2659 is not set
-# CONFIG_SOC_CAMERA_OV7690 is not set
-# CONFIG_SOC_CAMERA_OV9650 is not set
-# CONFIG_SOC_CAMERA_OV2640_RK is not set
-# CONFIG_SOC_CAMERA_OV3640 is not set
-# CONFIG_SOC_CAMERA_OV5642 is not set
-# CONFIG_SOC_CAMERA_OV5640 is not set
-CONFIG_SOC_CAMERA_OV5640_FOR_TD8801=y
-CONFIG_OV5640_AUTOFOCUS_FOR_TD8801=y
-# CONFIG_OV5640_FIXEDFOCUS_FOR_TD8801 is not set
-# CONFIG_SOC_CAMERA_S5K6AA is not set
-# CONFIG_SOC_CAMERA_GT2005 is not set
-# CONFIG_SOC_CAMERA_GC0307 is not set
-# CONFIG_SOC_CAMERA_GC0308 is not set
-# CONFIG_SOC_CAMERA_GC0309 is not set
-CONFIG_SOC_CAMERA_GC0309_FOR_TD8801=y
-# CONFIG_SOC_CAMERA_GC2015 is not set
-# CONFIG_SOC_CAMERA_HI253 is not set
-# CONFIG_SOC_CAMERA_HI704 is not set
-# CONFIG_SOC_CAMERA_SIV120B is not set
-# CONFIG_SOC_CAMERA_SID130B is not set
-# CONFIG_SOC_CAMERA_NT99250 is not set
-# CONFIG_SOC_CAMERA_OV9640 is not set
-# CONFIG_SOC_CAMERA_OV9740 is not set
-# CONFIG_VIDEO_SH_MOBILE_CSI2 is not set
-# CONFIG_VIDEO_SH_MOBILE_CEU is not set
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_WORK_ONEFRAME=y
-# CONFIG_VIDEO_RK29_WORK_PINGPONG is not set
-CONFIG_VIDEO_RK29_WORK_IPP=y
-# CONFIG_VIDEO_RK29_WORK_NOT_IPP is not set
-CONFIG_VIDEO_RK29_DIGITALZOOM_IPP_ON=y
-# CONFIG_VIDEO_RK29_DIGITALZOOM_IPP_OFF is not set
-CONFIG_V4L_USB_DRIVERS=y
-# CONFIG_USB_VIDEO_CLASS is not set
-CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
-CONFIG_USB_GSPCA=m
-# CONFIG_USB_M5602 is not set
-# CONFIG_USB_STV06XX is not set
-# CONFIG_USB_GL860 is not set
-# CONFIG_USB_GSPCA_BENQ is not set
-# CONFIG_USB_GSPCA_CONEX is not set
-# CONFIG_USB_GSPCA_CPIA1 is not set
-# CONFIG_USB_GSPCA_ETOMS is not set
-# CONFIG_USB_GSPCA_FINEPIX is not set
-# CONFIG_USB_GSPCA_JEILINJ is not set
-# CONFIG_USB_GSPCA_KINECT is not set
-# CONFIG_USB_GSPCA_KONICA is not set
-# CONFIG_USB_GSPCA_MARS is not set
-# CONFIG_USB_GSPCA_MR97310A is not set
-# CONFIG_USB_GSPCA_NW80X is not set
-# CONFIG_USB_GSPCA_OV519 is not set
-# CONFIG_USB_GSPCA_OV534 is not set
-# CONFIG_USB_GSPCA_OV534_9 is not set
-# CONFIG_USB_GSPCA_PAC207 is not set
-# CONFIG_USB_GSPCA_PAC7302 is not set
-# CONFIG_USB_GSPCA_PAC7311 is not set
-# CONFIG_USB_GSPCA_SN9C2028 is not set
-# CONFIG_USB_GSPCA_SN9C20X is not set
-# CONFIG_USB_GSPCA_SONIXB is not set
-# CONFIG_USB_GSPCA_SONIXJ is not set
-# CONFIG_USB_GSPCA_SPCA500 is not set
-# CONFIG_USB_GSPCA_SPCA501 is not set
-# CONFIG_USB_GSPCA_SPCA505 is not set
-# CONFIG_USB_GSPCA_SPCA506 is not set
-# CONFIG_USB_GSPCA_SPCA508 is not set
-# CONFIG_USB_GSPCA_SPCA561 is not set
-# CONFIG_USB_GSPCA_SPCA1528 is not set
-# CONFIG_USB_GSPCA_SQ905 is not set
-# CONFIG_USB_GSPCA_SQ905C is not set
-# CONFIG_USB_GSPCA_SQ930X is not set
-# CONFIG_USB_GSPCA_STK014 is not set
-# CONFIG_USB_GSPCA_STV0680 is not set
-# CONFIG_USB_GSPCA_SUNPLUS is not set
-# CONFIG_USB_GSPCA_T613 is not set
-# CONFIG_USB_GSPCA_TV8532 is not set
-# CONFIG_USB_GSPCA_VC032X is not set
-# CONFIG_USB_GSPCA_VICAM is not set
-# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
-# CONFIG_USB_GSPCA_ZC3XX is not set
-# CONFIG_VIDEO_PVRUSB2 is not set
-# CONFIG_VIDEO_HDPVR is not set
-# CONFIG_VIDEO_EM28XX is not set
-# CONFIG_VIDEO_CX231XX is not set
-# CONFIG_VIDEO_USBVISION is not set
-# CONFIG_USB_ET61X251 is not set
-# CONFIG_USB_SN9C102 is not set
-# CONFIG_USB_PWC is not set
-# CONFIG_USB_ZR364XX is not set
-# CONFIG_USB_STKWEBCAM is not set
-# CONFIG_USB_S2255 is not set
-# CONFIG_V4L_MEM2MEM_DRIVERS is not set
-CONFIG_RADIO_ADAPTERS=y
-# CONFIG_I2C_SI4713 is not set
-# CONFIG_RADIO_SI4713 is not set
-# CONFIG_USB_DSBR is not set
-# CONFIG_RADIO_SI470X is not set
-# CONFIG_USB_MR800 is not set
-# CONFIG_RADIO_TEA5764 is not set
-# CONFIG_RADIO_SAA7706H is not set
-# CONFIG_RADIO_TEF6862 is not set
-# CONFIG_RADIO_WL1273 is not set
-
-#
-# Texas Instruments WL128x FM driver (ST based)
-#
-# CONFIG_RADIO_WL128X is not set
-CONFIG_SMS_SIANO_MDTV=m
-# CONFIG_SMS_USB_DRV is not set
-# CONFIG_SMS_SDIO_DRV is not set
-
-#
-# Graphics support
-#
-# CONFIG_DRM is not set
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-CONFIG_FB=y
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB_DDC is not set
-# CONFIG_FB_BOOT_VESA_SUPPORT is not set
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-# CONFIG_FB_SYS_FILLRECT is not set
-# CONFIG_FB_SYS_COPYAREA is not set
-# CONFIG_FB_SYS_IMAGEBLIT is not set
-# CONFIG_FB_FOREIGN_ENDIAN is not set
-# CONFIG_FB_SYS_FOPS is not set
-# CONFIG_FB_WMT_GE_ROPS is not set
-# CONFIG_FB_SVGALIB is not set
-# CONFIG_FB_MACMODES is not set
-# CONFIG_FB_BACKLIGHT is not set
-# CONFIG_FB_MODE_HELPERS is not set
-# CONFIG_FB_TILEBLITTING is not set
-
-#
-# Frame buffer hardware drivers
-#
-# CONFIG_FB_S1D13XXX is not set
-# CONFIG_FB_TMIO is not set
-CONFIG_FB_RK29=y
-CONFIG_FB_WORK_IPP=y
-# CONFIG_FB_SCALING_OSD is not set
-CONFIG_FB_ROTATE_VIDEO=y
-# CONFIG_FB_MIRROR_X_Y is not set
-# CONFIG_CLOSE_WIN1_DYNAMIC is not set
-# CONFIG_FB_WIMO is not set
-# CONFIG_FB_UDL is not set
-# CONFIG_FB_VIRTUAL is not set
-# CONFIG_FB_METRONOME is not set
-# CONFIG_FB_BROADSHEET is not set
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_BACKLIGHT_WM831X=y
-# CONFIG_BACKLIGHT_RK29_BL is not set
-# CONFIG_BACKLIGHT_RK29_NEWTON_BL is not set
-# CONFIG_FIH_TOUCHKEY_LED is not set
-# CONFIG_BACKLIGHT_AW9364 is not set
-CONFIG_BUTTON_LIGHT=y
-# CONFIG_BACKLIGHT_ADP8860 is not set
-# CONFIG_BACKLIGHT_ADP8870 is not set
-
-#
-# Display device support
-#
-CONFIG_DISPLAY_SUPPORT=y
-
-#
-# Display hardware drivers
-#
-# CONFIG_LCD_NULL is not set
-# CONFIG_LCD_LG_LP097X02 is not set
-# CONFIG_LCD_TD043MGEA1 is not set
-# CONFIG_LCD_HX8357 is not set
-# CONFIG_LCD_TJ048NC01CA is not set
-# CONFIG_LCD_HL070VM4AU is not set
-# CONFIG_LCD_HSD070IDW1 is not set
-# CONFIG_LCD_RGB_TFT480800_25_E is not set
-# CONFIG_LCD_HSD100PXN is not set
-# CONFIG_LCD_HSD07PFW1 is not set
-# CONFIG_LCD_BYD8688FTGF is not set
-# CONFIG_LCD_B101AW06 is not set
-# CONFIG_LCD_LS035Y8DX02A is not set
-CONFIG_LCD_LS035Y8DX04A=y
-# CONFIG_LCD_CPTCLAA038LA31XE is not set
-# CONFIG_LCD_A060SE02 is not set
-# CONFIG_LCD_S1D13521 is not set
-# CONFIG_LCD_NT35582 is not set
-# CONFIG_LCD_NT35580 is not set
-# CONFIG_LCD_IPS1P5680_V1_E is not set
-# CONFIG_LCD_MCU_TFT480800_25_E is not set
-# CONFIG_LCD_NT35510 is not set
-# CONFIG_LCD_ILI9803_CPT4_3 is not set
-# CONFIG_LCD_AT070TNA2 is not set
-# CONFIG_LCD_AT070TN93 is not set
-# CONFIG_LCD_TX23D88VM is not set
-# CONFIG_LCD_A050VL01 is not set
-
-#
-# HDMI
-#
-# CONFIG_HDMI is not set
-
-#
-# Console display driver support
-#
-CONFIG_DUMMY_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE is not set
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_LOGO_LINUX_CLUT224 is not set
-CONFIG_LOGO_CHARGER_CLUT224=y
-CONFIG_LOGO_G3_CLUT224=y
-CONFIG_SOUND=y
-# CONFIG_SOUND_OSS_CORE is not set
-CONFIG_SND=y
-CONFIG_SND_TIMER=y
-CONFIG_SND_PCM=y
-CONFIG_SND_JACK=y
-# CONFIG_SND_SEQUENCER is not set
-# CONFIG_SND_MIXER_OSS is not set
-# CONFIG_SND_PCM_OSS is not set
-# CONFIG_SND_HRTIMER is not set
-# CONFIG_SND_DYNAMIC_MINORS is not set
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_VERBOSE_PRINTK is not set
-# CONFIG_SND_DEBUG is not set
-# CONFIG_SND_RAWMIDI_SEQ is not set
-# CONFIG_SND_OPL3_LIB_SEQ is not set
-# CONFIG_SND_OPL4_LIB_SEQ is not set
-# CONFIG_SND_SBAWE_SEQ is not set
-# CONFIG_SND_EMU10K1_SEQ is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-# CONFIG_SND_SPI is not set
-# CONFIG_SND_USB is not set
-CONFIG_SND_SOC=y
-# CONFIG_SND_SOC_CACHE_LZO is not set
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_RK29_SOC_I2S=y
-# CONFIG_SND_RK29_SOC_I2S_2CH is not set
-CONFIG_SND_RK29_SOC_I2S_8CH=y
-# CONFIG_SND_I2S_DMA_EVENT_DYNAMIC is not set
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-# CONFIG_SND_RK29_SOC_WM8988 is not set
-# CONFIG_SND_RK29_SOC_WM8900 is not set
-# CONFIG_SND_RK29_SOC_RT5621 is not set
-# CONFIG_SND_RK29_SOC_RT5631 is not set
-# CONFIG_SND_RK29_SOC_RT5625 is not set
-CONFIG_SND_RK29_SOC_WM8994=y
-# CONFIG_SND_RK29_SOC_CS42L52 is not set
-# CONFIG_SND_RK29_SOC_AIC3111 is not set
-# CONFIG_SND_RK29_CODEC_SOC_MASTER is not set
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-# CONFIG_ADJUST_VOL_BY_CODEC is not set
-CONFIG_PHONE_INCALL_IS_SUSPEND=y
-CONFIG_SND_SOC_I2C_AND_SPI=y
-# CONFIG_SND_SOC_ALL_CODECS is not set
-CONFIG_SND_SOC_WM_HUBS=y
-CONFIG_SND_SOC_WM8994=y
-# CONFIG_SOUND_PRIME is not set
-CONFIG_HID_SUPPORT=y
-CONFIG_HID=y
-# CONFIG_HIDRAW is not set
-
-#
-# USB Input Devices
-#
-CONFIG_USB_HID=y
-# CONFIG_HID_PID is not set
-# CONFIG_USB_HIDDEV is not set
-
-#
-# Special HID drivers
-#
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-# CONFIG_HID_PRODIKEYS is not set
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-# CONFIG_HID_PICOLCD_FB is not set
-# CONFIG_HID_PICOLCD_BACKLIGHT is not set
-# CONFIG_HID_PICOLCD_LEDS is not set
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT=y
-CONFIG_HID_ROCCAT_COMMON=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-# CONFIG_HID_WACOM_POWER_SUPPLY is not set
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ARCH_HAS_HCD=y
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-CONFIG_USB=y
-# CONFIG_USB_DEBUG is not set
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-
-#
-# Miscellaneous USB options
-#
-# CONFIG_USB_DEVICEFS is not set
-CONFIG_USB_DEVICE_CLASS=y
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_OTG_WHITELIST is not set
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-# CONFIG_USB_MON is not set
-# CONFIG_USB_WUSB is not set
-# CONFIG_USB_WUSB_CBAF is not set
-
-#
-# USB Host Controller Drivers
-#
-# CONFIG_USB_C67X00_HCD is not set
-# CONFIG_USB_OXU210HP_HCD is not set
-# CONFIG_USB_ISP116X_HCD is not set
-# CONFIG_USB_ISP1760_HCD is not set
-# CONFIG_USB_ISP1362_HCD is not set
-# CONFIG_USB_SL811_HCD is not set
-# CONFIG_USB_R8A66597_HCD is not set
-# CONFIG_USB_HWA_HCD is not set
-# CONFIG_USB_MUSB_HDRC is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-# CONFIG_USB_WDM is not set
-# CONFIG_USB_TMC is not set
-
-#
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
-#
-
-#
-# also be needed; see USB_STORAGE Help for more info
-#
-CONFIG_USB_STORAGE=y
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_REALTEK is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_USBAT is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_STORAGE_SDDR55 is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_ALAUDA is not set
-# CONFIG_USB_STORAGE_ONETOUCH is not set
-# CONFIG_USB_STORAGE_KARMA is not set
-# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
-# CONFIG_USB_STORAGE_ENE_UB6250 is not set
-# CONFIG_USB_UAS is not set
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_MICROTEK is not set
-
-#
-# USB port drivers
-#
-CONFIG_USB_SERIAL=y
-# CONFIG_USB_SERIAL_CONSOLE is not set
-# CONFIG_USB_EZUSB is not set
-CONFIG_USB_SERIAL_GENERIC=y
-# CONFIG_USB_SERIAL_AIRCABLE is not set
-# CONFIG_USB_SERIAL_ARK3116 is not set
-# CONFIG_USB_SERIAL_BELKIN is not set
-# CONFIG_USB_SERIAL_CH341 is not set
-# CONFIG_USB_SERIAL_WHITEHEAT is not set
-# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
-# CONFIG_USB_SERIAL_CP210X is not set
-# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
-# CONFIG_USB_SERIAL_EMPEG is not set
-# CONFIG_USB_SERIAL_FTDI_SIO is not set
-# CONFIG_USB_SERIAL_FUNSOFT is not set
-# CONFIG_USB_SERIAL_VISOR is not set
-# CONFIG_USB_SERIAL_IPAQ is not set
-# CONFIG_USB_SERIAL_IR is not set
-# CONFIG_USB_SERIAL_EDGEPORT is not set
-# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
-# CONFIG_USB_SERIAL_GARMIN is not set
-# CONFIG_USB_SERIAL_IPW is not set
-# CONFIG_USB_SERIAL_IUU is not set
-# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
-# CONFIG_USB_SERIAL_KEYSPAN is not set
-# CONFIG_USB_SERIAL_KLSI is not set
-# CONFIG_USB_SERIAL_KOBIL_SCT is not set
-# CONFIG_USB_SERIAL_MCT_U232 is not set
-# CONFIG_USB_SERIAL_MOS7720 is not set
-# CONFIG_USB_SERIAL_MOS7840 is not set
-# CONFIG_USB_SERIAL_MOTOROLA is not set
-# CONFIG_USB_SERIAL_NAVMAN is not set
-# CONFIG_USB_SERIAL_PL2303 is not set
-# CONFIG_USB_SERIAL_OTI6858 is not set
-# CONFIG_USB_SERIAL_QCAUX is not set
-# CONFIG_USB_SERIAL_QUALCOMM is not set
-# CONFIG_USB_SERIAL_SPCP8X5 is not set
-# CONFIG_USB_SERIAL_HP4X is not set
-# CONFIG_USB_SERIAL_SAFE is not set
-# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
-# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
-# CONFIG_USB_SERIAL_SYMBOL is not set
-# CONFIG_USB_SERIAL_TI is not set
-# CONFIG_USB_SERIAL_CYBERJACK is not set
-# CONFIG_USB_SERIAL_XIRCOM is not set
-CONFIG_USB_SERIAL_WWAN=y
-CONFIG_USB_SERIAL_OPTION=y
-# CONFIG_USB_SERIAL_OMNINET is not set
-# CONFIG_USB_SERIAL_OPTICON is not set
-# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set
-# CONFIG_USB_SERIAL_ZIO is not set
-# CONFIG_USB_SERIAL_SSU100 is not set
-# CONFIG_USB_SERIAL_DEBUG is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_SEVSEG is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYPRESS_CY7C63 is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_FTDI_ELAN is not set
-# CONFIG_USB_APPLEDISPLAY is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TRANCEVIBRATOR is not set
-# CONFIG_USB_IOWARRIOR is not set
-# CONFIG_USB_TEST is not set
-# CONFIG_USB_ISIGHTFW is not set
-# CONFIG_USB_YUREX is not set
-CONFIG_USB_GADGET=y
-# CONFIG_USB_GADGET_DEBUG is not set
-# CONFIG_USB_GADGET_DEBUG_FILES is not set
-# CONFIG_USB_GADGET_DEBUG_FS is not set
-CONFIG_USB_GADGET_VBUS_DRAW=2
-CONFIG_USB_GADGET_SELECTED=y
-# CONFIG_USB_GADGET_FUSB300 is not set
-# CONFIG_USB_GADGET_R8A66597 is not set
-# CONFIG_USB_GADGET_PXA_U2O is not set
-# CONFIG_USB_GADGET_M66592 is not set
-CONFIG_USB_GADGET_DWC_OTG=y
-CONFIG_USB_DWC_OTG=y
-# CONFIG_USB_GADGET_DUMMY_HCD is not set
-CONFIG_USB_GADGET_DUALSPEED=y
-# CONFIG_USB_ZERO is not set
-# CONFIG_USB_AUDIO is not set
-# CONFIG_USB_ETH is not set
-# CONFIG_USB_G_NCM is not set
-# CONFIG_USB_GADGETFS is not set
-# CONFIG_USB_FUNCTIONFS is not set
-# CONFIG_USB_FILE_STORAGE is not set
-# CONFIG_USB_MASS_STORAGE is not set
-# CONFIG_USB_G_SERIAL is not set
-# CONFIG_USB_MIDI_GADGET is not set
-# CONFIG_USB_G_PRINTER is not set
-CONFIG_USB_G_ANDROID=y
-# CONFIG_USB_CDC_COMPOSITE is not set
-# CONFIG_USB_G_NOKIA is not set
-# CONFIG_USB_G_MULTI is not set
-# CONFIG_USB_G_HID is not set
-# CONFIG_USB_G_DBGP is not set
-# CONFIG_USB_G_WEBCAM is not set
-
-#
-# OTG and related infrastructure
-#
-# CONFIG_USB_OTG_WAKELOCK is not set
-# CONFIG_USB_GPIO_VBUS is not set
-# CONFIG_USB_ULPI is not set
-# CONFIG_NOP_USB_XCEIV is not set
-# CONFIG_USB11_HOST is not set
-# CONFIG_USB20_HOST is not set
-CONFIG_USB20_OTG=y
-# CONFIG_DWC_OTG_HOST_ONLY is not set
-CONFIG_DWC_OTG_DEVICE_ONLY=y
-# CONFIG_DWC_OTG_BOTH_HOST_SLAVE is not set
-CONFIG_DWC_CONN_EN=y
-# CONFIG_DWC_OTG_DEBUG is not set
-# CONFIG_DWC_REMOTE_WAKEUP is not set
-CONFIG_DWC_OTG=y
-CONFIG_MMC=y
-# CONFIG_MMC_DEBUG is not set
-CONFIG_MMC_UNSAFE_RESUME=y
-# CONFIG_MMC_CLKGATE is not set
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-
-#
-# MMC/SD/SDIO Card Drivers
-#
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_BLOCK_MINORS=8
-CONFIG_MMC_BLOCK_BOUNCE=y
-# CONFIG_MMC_BLOCK_DEFERRED_RESUME is not set
-# CONFIG_SDIO_UART is not set
-# CONFIG_MMC_TEST is not set
-
-#
-# MMC/SD/SDIO Host Controller Drivers
-#
-CONFIG_SDMMC_RK29=y
-
-#
-# Now, there are two SDMMC controllers selected, SDMMC0 and SDMMC1.
-#
-# CONFIG_SDMMC_RK29_OLD is not set
-CONFIG_SDMMC0_RK29=y
-# CONFIG_SDMMC0_RK29_WRITE_PROTECT is not set
-CONFIG_SDMMC1_RK29=y
-# CONFIG_SDMMC1_RK29_WRITE_PROTECT is not set
-# CONFIG_MMC_SDHCI is not set
-# CONFIG_MMC_DW is not set
-# CONFIG_MMC_VUB300 is not set
-# CONFIG_MMC_USHC is not set
-# CONFIG_MEMSTICK is not set
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-
-#
-# LED drivers
-#
-# CONFIG_LEDS_LM3530 is not set
-# CONFIG_LEDS_PCA9532 is not set
-# CONFIG_LEDS_GPIO is not set
-# CONFIG_LEDS_NEWTON_PWM is not set
-# CONFIG_LEDS_LP3944 is not set
-# CONFIG_LEDS_LP5521 is not set
-# CONFIG_LEDS_LP5523 is not set
-# CONFIG_LEDS_PCA955X is not set
-CONFIG_LEDS_WM831X_STATUS=y
-# CONFIG_LEDS_DAC124S085 is not set
-# CONFIG_LEDS_REGULATOR is not set
-# CONFIG_LEDS_BD2802 is not set
-# CONFIG_LEDS_ATT1272 is not set
-# CONFIG_LEDS_LT3593 is not set
-# CONFIG_LEDS_TRIGGERS is not set
-
-#
-# LED Triggers
-#
-# CONFIG_NFC_DEVICES is not set
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-# CONFIG_ACCESSIBILITY is not set
-CONFIG_RTC_LIB=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HCTOSYS=y
-CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-# CONFIG_RTC_DEBUG is not set
-
-#
-# RTC interfaces
-#
-CONFIG_RTC_INTF_SYSFS=y
-CONFIG_RTC_INTF_PROC=y
-CONFIG_RTC_INTF_DEV=y
-# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-CONFIG_RTC_INTF_ALARM=y
-CONFIG_RTC_INTF_ALARM_DEV=y
-# CONFIG_AUTO_WAKE_UP is not set
-# CONFIG_RTC_DRV_TEST is not set
-
-#
-# I2C RTC drivers
-#
-# CONFIG_RTC_HYM8563 is not set
-# CONFIG_RTC_M41T66 is not set
-# CONFIG_RTC_DRV_DS1307 is not set
-# CONFIG_RTC_DRV_DS1374 is not set
-# CONFIG_RTC_DRV_DS1672 is not set
-# CONFIG_RTC_DRV_DS3232 is not set
-# CONFIG_RTC_DRV_MAX6900 is not set
-# CONFIG_RTC_DRV_RS5C372 is not set
-# CONFIG_RTC_DRV_ISL1208 is not set
-# CONFIG_RTC_DRV_ISL12022 is not set
-# CONFIG_RTC_DRV_X1205 is not set
-# CONFIG_RTC_DRV_PCF8563 is not set
-# CONFIG_RTC_DRV_PCF8583 is not set
-# CONFIG_RTC_DRV_M41T80 is not set
-# CONFIG_RTC_DRV_BQ32K is not set
-# CONFIG_RTC_DRV_S35390A is not set
-# CONFIG_RTC_DRV_S35392A is not set
-# CONFIG_RTC_DRV_FM3130 is not set
-# CONFIG_RTC_DRV_RX8581 is not set
-# CONFIG_RTC_DRV_RX8025 is not set
-# CONFIG_RTC_DRV_EM3027 is not set
-# CONFIG_RTC_DRV_RV3029C2 is not set
-
-#
-# SPI RTC drivers
-#
-# CONFIG_RTC_DRV_M41T93 is not set
-# CONFIG_RTC_DRV_M41T94 is not set
-# CONFIG_RTC_DRV_DS1305 is not set
-# CONFIG_RTC_DRV_DS1390 is not set
-# CONFIG_RTC_DRV_MAX6902 is not set
-# CONFIG_RTC_DRV_R9701 is not set
-# CONFIG_RTC_DRV_RS5C348 is not set
-# CONFIG_RTC_DRV_DS3234 is not set
-# CONFIG_RTC_DRV_PCF2123 is not set
-
-#
-# Platform RTC drivers
-#
-# CONFIG_RTC_DRV_CMOS is not set
-# CONFIG_RTC_DRV_DS1286 is not set
-# CONFIG_RTC_DRV_DS1511 is not set
-# CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_DS1742 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
-# CONFIG_RTC_DRV_M48T86 is not set
-# CONFIG_RTC_DRV_M48T35 is not set
-# CONFIG_RTC_DRV_M48T59 is not set
-# CONFIG_RTC_DRV_MSM6242 is not set
-# CONFIG_RTC_DRV_BQ4802 is not set
-# CONFIG_RTC_DRV_RP5C01 is not set
-# CONFIG_RTC_DRV_V3020 is not set
-CONFIG_RTC_DRV_WM831X=y
-
-#
-# on-CPU RTC drivers
-#
-# CONFIG_DMADEVICES is not set
-# CONFIG_AUXDISPLAY is not set
-# CONFIG_UIO is not set
-CONFIG_STAGING=y
-# CONFIG_VIDEO_TM6000 is not set
-# CONFIG_USBIP_CORE is not set
-# CONFIG_ECHO is not set
-# CONFIG_BRCMUTIL is not set
-# CONFIG_ASUS_OLED is not set
-# CONFIG_R8712U is not set
-# CONFIG_TRANZPORT is not set
-
-#
-# Android
-#
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-# CONFIG_ANDROID_RAM_CONSOLE is not set
-CONFIG_ANDROID_TIMED_OUTPUT=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_POHMELFS is not set
-# CONFIG_LINE6_USB is not set
-# CONFIG_USB_SERIAL_QUATECH2 is not set
-# CONFIG_USB_SERIAL_QUATECH_USB2 is not set
-# CONFIG_VT6656 is not set
-# CONFIG_IIO is not set
-
-#
-# GPU Vivante
-#
-CONFIG_VIVANTE=y
-
-#
-# IPP
-#
-CONFIG_RK29_IPP=y
-# CONFIG_DEINTERLACE is not set
-# CONFIG_XVMALLOC is not set
-# CONFIG_ZRAM is not set
-# CONFIG_FB_SM7XX is not set
-# CONFIG_LIRC_STAGING is not set
-# CONFIG_EASYCAP is not set
-CONFIG_MACH_NO_WESTBRIDGE=y
-# CONFIG_USB_ENESTORAGE is not set
-# CONFIG_BCM_WIMAX is not set
-# CONFIG_FT1000 is not set
-
-#
-# Speakup console speech
-#
-# CONFIG_SPEAKUP is not set
-# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set
-# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set
-
-#
-# Altera FPGA firmware download module
-#
-# CONFIG_ALTERA_STAPL is not set
-CONFIG_CLKDEV_LOOKUP=y
-
-#
-# CMMB
-#
-CONFIG_CMMB=y
-
-#
-# Siano module components
-#
-# CONFIG_SMS_DVB3_SUBSYS is not set
-# CONFIG_SMS_DVB5_S2API_SUBSYS is not set
-CONFIG_SMS_HOSTLIB_SUBSYS=y
-# CONFIG_SMS_NET_SUBSYS is not set
-CONFIG_SMS_SPI_ROCKCHIP=y
-# CONFIG_TEST_CODE is not set
-# CONFIG_RK29_SMC is not set
-
-#
-# CIR support
-#
-# CONFIG_RK_CIR is not set
-
-#
-# File systems
-#
-# CONFIG_EXT2_FS is not set
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-CONFIG_EXT4_USE_FOR_EXT23=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_EXT4_DEBUG is not set
-CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
-CONFIG_JBD2=y
-# CONFIG_JBD2_DEBUG is not set
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_XFS_FS is not set
-# CONFIG_BTRFS_FS is not set
-# CONFIG_NILFS2_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
-CONFIG_FILE_LOCKING=y
-CONFIG_FSNOTIFY=y
-# CONFIG_DNOTIFY is not set
-CONFIG_INOTIFY_USER=y
-# CONFIG_FANOTIFY is not set
-# CONFIG_QUOTA is not set
-# CONFIG_QUOTACTL is not set
-# CONFIG_AUTOFS4_FS is not set
-CONFIG_FUSE_FS=y
-# CONFIG_CUSE is not set
-
-#
-# Caches
-#
-# CONFIG_FSCACHE is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=y
-# CONFIG_MSDOS_FS is not set
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-# CONFIG_TMPFS_XATTR is not set
-# CONFIG_HUGETLB_PAGE is not set
-# CONFIG_CONFIGFS_FS is not set
-CONFIG_MISC_FILESYSTEMS=y
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_YAFFS_FS is not set
-# CONFIG_JFFS2_FS is not set
-# CONFIG_LOGFS is not set
-CONFIG_CRAMFS=y
-# CONFIG_SQUASHFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_OMFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_PSTORE is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-
-#
-# Partition Types
-#
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_MSDOS_PARTITION=y
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-1"
-CONFIG_NLS_CODEPAGE_437=y
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-CONFIG_NLS_CODEPAGE_850=y
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-CONFIG_NLS_CODEPAGE_936=y
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ASCII is not set
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-CONFIG_NLS_ISO8859_15=y
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-CONFIG_NLS_UTF8=y
-
-#
-# Kernel hacking
-#
-CONFIG_PRINTK_TIME=y
-CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
-CONFIG_ENABLE_WARN_DEPRECATED=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_FRAME_WARN=1024
-CONFIG_MAGIC_SYSRQ=y
-# CONFIG_STRIP_ASM_SYMS is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-CONFIG_DEBUG_FS=y
-# CONFIG_HEADERS_CHECK is not set
-# CONFIG_DEBUG_SECTION_MISMATCH is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-# CONFIG_LOCKUP_DETECTOR is not set
-# CONFIG_HARDLOCKUP_DETECTOR is not set
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
-# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
-CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
-CONFIG_SCHEDSTATS=y
-CONFIG_TIMER_STATS=y
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_KMEMLEAK is not set
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_PROVE_LOCKING is not set
-# CONFIG_SPARSE_RCU_POINTER is not set
-# CONFIG_LOCK_STAT is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-CONFIG_STACKTRACE=y
-# CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_DEBUG_KOBJECT is not set
-# CONFIG_DEBUG_HIGHMEM is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_WRITECOUNT is not set
-# CONFIG_DEBUG_MEMORY_INIT is not set
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_TEST_LIST_SORT is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_DEBUG_NOTIFIERS is not set
-# CONFIG_DEBUG_CREDENTIALS is not set
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_RCU_TORTURE_TEST is not set
-CONFIG_RCU_CPU_STALL_TIMEOUT=60
-CONFIG_RCU_CPU_STALL_VERBOSE=y
-# CONFIG_BACKTRACE_SELF_TEST is not set
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
-# CONFIG_LKDTM is not set
-# CONFIG_FAULT_INJECTION is not set
-# CONFIG_LATENCYTOP is not set
-# CONFIG_SYSCTL_SYSCALL_CHECK is not set
-# CONFIG_DEBUG_PAGEALLOC is not set
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_TRACING_SUPPORT=y
-# CONFIG_FTRACE is not set
-# CONFIG_DYNAMIC_DEBUG is not set
-# CONFIG_DMA_API_DEBUG is not set
-# CONFIG_ATOMIC64_SELFTEST is not set
-# CONFIG_SAMPLES is not set
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_KGDB is not set
-# CONFIG_TEST_KSTRTOX is not set
-# CONFIG_STRICT_DEVMEM is not set
-CONFIG_ARM_UNWIND=y
-# CONFIG_DEBUG_USER is not set
-# CONFIG_DEBUG_LL is not set
-# CONFIG_OC_ETM is not set
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY_DMESG_RESTRICT is not set
-# CONFIG_SECURITY is not set
-# CONFIG_SECURITYFS is not set
-CONFIG_DEFAULT_SECURITY_DAC=y
-CONFIG_DEFAULT_SECURITY=""
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_ALGAPI2=y
-CONFIG_CRYPTO_AEAD=y
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_BLKCIPHER=y
-CONFIG_CRYPTO_BLKCIPHER2=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_PCOMP2=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
-# CONFIG_CRYPTO_GF128MUL is not set
-# CONFIG_CRYPTO_NULL is not set
-CONFIG_CRYPTO_WORKQUEUE=y
-# CONFIG_CRYPTO_CRYPTD is not set
-CONFIG_CRYPTO_AUTHENC=y
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Authenticated Encryption with Associated Data
-#
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_SEQIV is not set
-
-#
-# Block modes
-#
-CONFIG_CRYPTO_CBC=y
-# CONFIG_CRYPTO_CTR is not set
-# CONFIG_CRYPTO_CTS is not set
-CONFIG_CRYPTO_ECB=y
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_PCBC is not set
-# CONFIG_CRYPTO_XTS is not set
-
-#
-# Hash modes
-#
-CONFIG_CRYPTO_HMAC=y
-# CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_VMAC is not set
-
-#
-# Digest
-#
-CONFIG_CRYPTO_CRC32C=y
-# CONFIG_CRYPTO_GHASH is not set
-# CONFIG_CRYPTO_MD4 is not set
-CONFIG_CRYPTO_MD5=y
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_RMD128 is not set
-# CONFIG_CRYPTO_RMD160 is not set
-# CONFIG_CRYPTO_RMD256 is not set
-# CONFIG_CRYPTO_RMD320 is not set
-CONFIG_CRYPTO_SHA1=y
-# CONFIG_CRYPTO_SHA256 is not set
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_WP512 is not set
-
-#
-# Ciphers
-#
-CONFIG_CRYPTO_AES=y
-# CONFIG_CRYPTO_ANUBIS is not set
-CONFIG_CRYPTO_ARC4=y
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-CONFIG_CRYPTO_DES=y
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_SALSA20 is not set
-# CONFIG_CRYPTO_SEED is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_TEA is not set
-CONFIG_CRYPTO_TWOFISH=y
-CONFIG_CRYPTO_TWOFISH_COMMON=y
-
-#
-# Compression
-#
-CONFIG_CRYPTO_DEFLATE=y
-# CONFIG_CRYPTO_ZLIB is not set
-# CONFIG_CRYPTO_LZO is not set
-
-#
-# Random Number Generation
-#
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_USER_API_HASH is not set
-# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
-CONFIG_CRYPTO_HW=y
-# CONFIG_BINARY_PRINTF is not set
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-CONFIG_CRC_CCITT=y
-CONFIG_CRC16=y
-# CONFIG_CRC_T10DIF is not set
-# CONFIG_CRC_ITU_T is not set
-CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
-CONFIG_LIBCRC32C=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-# CONFIG_XZ_DEC is not set
-# CONFIG_XZ_DEC_BCJ is not set
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_TEXTSEARCH=y
-CONFIG_TEXTSEARCH_KMP=y
-CONFIG_TEXTSEARCH_BM=y
-CONFIG_TEXTSEARCH_FSM=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
-CONFIG_NLATTR=y
-# CONFIG_AVERAGE is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_PANIC_TIMEOUT=5
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-CONFIG_EMBEDDED=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_ARCH_RK29=y
-CONFIG_MACH_RK29_PHONE_Z5=y
-CONFIG_DDR_TYPE_LPDDR=y
-CONFIG_DDR_SDRAM_FREQ=192
-CONFIG_WIFI_CONTROL_FUNC=y
-CONFIG_RK29_WORKING_POWER_MANAGEMENT=y
-CONFIG_RK29_CLK_SWITCH_TO_32K=y
-CONFIG_RK29_GPIO_SUSPEND=y
-CONFIG_RK29_SPI_INSRAM=y
-CONFIG_ARM_THUMBEE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_KEXEC=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_STAT_DETAILS=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_WIFI_MAC=y
-CONFIG_RFKILL=y
-# CONFIG_RFKILL_PM is not set
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_MTK23D=y
-CONFIG_RK29_GPS=y
-CONFIG_MPU_SENSORS_MPU3050=m
-CONFIG_MPU_SENSORS_MMA845X=y
-CONFIG_MPU_SENSORS_PRESSURE_NONE=y
-CONFIG_MPU_SENSORS_TIMERIRQ=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_MII=y
-CONFIG_PHYLIB=y
-CONFIG_NET_ETHERNET=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_BCM4329=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_INPUT_POLLDEV=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_FT5306=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_INPUT_WM831X_ON=y
-# CONFIG_SERIO is not set
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-CONFIG_UART1_RK29=y
-CONFIG_UART2_RK29=y
-CONFIG_UART2_CTS_RTS_RK29=y
-CONFIG_UART3_RK29=y
-CONFIG_SERIAL_RK29_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_SPI=y
-CONFIG_SPIM_RK29=y
-CONFIG_SPIM0_RK29=y
-CONFIG_SPIM1_RK29=y
-CONFIG_LCD_USE_SPIM_CONTROL=y
-CONFIG_ADC_RK29=y
-CONFIG_RK_HEADSET_DET=y
-CONFIG_GPIO_WM831X=y
-CONFIG_GPIO_WM8994=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_WM831X_BACKUP=y
-CONFIG_WM831X_POWER=y
-CONFIG_WM831X_CHARGER_DISPLAY=y
-CONFIG_WM831X_WITH_BATTERY=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_WM831X_SPI=y
-CONFIG_MFD_WM8994=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_REGULATOR_WM8994=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
-CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV7690=y
-CONFIG_SOC_CAMERA_OV5640=y
-CONFIG_VIDEO_RK29=y
-CONFIG_FB=y
-CONFIG_FB_RK29=y
-CONFIG_FB_WORK_IPP=y
-CONFIG_FB_ROTATE_VIDEO=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_BACKLIGHT_WM831X=y
-# CONFIG_BACKLIGHT_RK29_BL is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_A050VL01=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_LOGO_CHARGER_CLUT224=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-CONFIG_SND_VERBOSE_PRINTK=y
-CONFIG_SND_DEBUG=y
-CONFIG_SND_DEBUG_VERBOSE=y
-CONFIG_SND_PCM_XRUN_DEBUG=y
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-# CONFIG_SND_SPI is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_WM8994=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-# CONFIG_HID_SUPPORT is not set
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_OTG=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_RAM_CONSOLE=y
-CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_DEINTERLACE is not set
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_CRAMFS=y
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_CODEPAGE_936=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_15=y
-CONFIG_NLS_UTF8=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_SCHEDSTATS=y
-CONFIG_TIMER_STATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_FTRACE is not set
-CONFIG_CRYPTO_ARC4=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK3026=y
-CONFIG_DDR_FREQ=y
-# CONFIG_DDR_TEST is not set
-CONFIG_RK_CLOCK_PROC=y
-CONFIG_CLK_SWITCH_TO_32K=y
-CONFIG_RK30_I2C_INSRAM=y
-CONFIG_RK_USB_UART=y
-CONFIG_MACH_RK3026_86V=y
-CONFIG_ARM_ERRATA_761320=y
-CONFIG_ARM_ERRATA_775420=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_CFG80211=y
-CONFIG_MAC80211=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RTL8188EU=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GSLX680_RK3028=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_GS_MMA7660=y
-CONFIG_GS_MMA8452=y
-CONFIG_GS_LIS3DH=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-CONFIG_GS_KXTIK=y
-CONFIG_GS_MXC6225=y
-CONFIG_GS_LSM303D=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_WM831X=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_BATTERY_RK30_ADC_FAC=y
-CONFIG_BATTERY_RK30_AC_CHARGE=y
-CONFIG_BATTERY_RK30_VOL3V8=y
-CONFIG_POWER_ON_CHARGER_DISPLAY=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_MFD_TPS65090=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_REGULATOR_ACT8846=y
-CONFIG_RK30_PWM_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-# CONFIG_SOC_CAMERA_OV3640 is not set
-# CONFIG_SOC_CAMERA_OV5642 is not set
-# CONFIG_SOC_CAMERA_OV5640 is not set
-CONFIG_SOC_CAMERA_GC0308=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL=y
-CONFIG_LCDC_RK3188=y
-CONFIG_LCDC0_RK3188=y
-CONFIG_LCD_RK2926_V86=y
-CONFIG_RK_TRSM=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_LOGO_LOWERPOWER_WARNING=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2SO_USE_DOUBLE_CHANNELS=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK_SOC_RK3026=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_UHID=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_MMC_BLOCK_MINORS=12
-CONFIG_SDMMC_RK29=y
-CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK3026=y
-CONFIG_DDR_FREQ=y
-# CONFIG_DDR_TEST is not set
-CONFIG_RK_CLOCK_PROC=y
-CONFIG_CLK_SWITCH_TO_32K=y
-CONFIG_RK30_I2C_INSRAM=y
-CONFIG_RK_USB_UART=y
-CONFIG_MACH_RK3026_86V_FAC=y
-CONFIG_ARM_ERRATA_761320=y
-CONFIG_ARM_ERRATA_775420=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_CFG80211=y
-CONFIG_MAC80211=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RTL8188EU=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GSLX680_RK3028=y
-CONFIG_TOUCHSCREEN_GT811_IIC=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_GS_MMA7660=y
-CONFIG_GS_MMA8452=y
-CONFIG_GS_LIS3DH=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-CONFIG_GS_KXTIK=y
-CONFIG_GS_MXC6225=y
-CONFIG_GS_LSM303D=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_WM831X=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_BATTERY_RK30_ADC_FAC=y
-CONFIG_BATTERY_RK30_AC_CHARGE=y
-CONFIG_BATTERY_RK30_VOL3V8=y
-CONFIG_POWER_ON_CHARGER_DISPLAY=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_MFD_TPS65090=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_REGULATOR_ACT8846=y
-CONFIG_RK30_PWM_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-# CONFIG_SOC_CAMERA_OV3640 is not set
-# CONFIG_SOC_CAMERA_OV5642 is not set
-# CONFIG_SOC_CAMERA_OV5640 is not set
-CONFIG_SOC_CAMERA_GC0308=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL=y
-CONFIG_LCDC_RK3188=y
-CONFIG_LCDC0_RK3188=y
-CONFIG_LCD_RK3168_FAC=y
-CONFIG_RK_TRSM=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_LOGO_LOWERPOWER_WARNING=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2SO_USE_DOUBLE_CHANNELS=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_ES8323=y
-CONFIG_SND_RK29_SOC_RT5631=y
-CONFIG_SND_RK_SOC_RK3026=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_UHID=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_MMC_BLOCK_MINORS=12
-CONFIG_SDMMC_RK29=y
-CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=12
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-# CONFIG_UID16 is not set
-# CONFIG_HOTPLUG is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_BASE_FULL is not set
-# CONFIG_FUTEX is not set
-# CONFIG_EPOLL is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_SHMEM is not set
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_VM_EVENT_COUNTERS is not set
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_BLOCK is not set
-CONFIG_ARCH_RK3026=y
-# CONFIG_DDR_TEST is not set
-CONFIG_RK_PM_TESTS=y
-# CONFIG_PM_TEST_CLK_RATE is not set
-# CONFIG_PM_TEST_CLK_VOLT is not set
-# CONFIG_PM_TEST_MAXFREQ is not set
-CONFIG_PM_TEST_FT=y
-# CONFIG_RK29_LAST_LOG is not set
-# CONFIG_RK_EARLY_PRINTK is not set
-CONFIG_RK_USB_UART=y
-# CONFIG_RK_CONSOLE_THREAD is not set
-CONFIG_MACH_RK3026_FT=y
-CONFIG_ARM_ERRATA_775420=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0"
-CONFIG_CMDLINE_FORCE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-# CONFIG_BINFMT_ELF is not set
-# CONFIG_SUSPEND is not set
-# CONFIG_FW_LOADER is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_UNIX98_PTYS is not set
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_DEVMEM is not set
-# CONFIG_DEVKMEM is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_ADC is not set
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-# CONFIG_HWMON is not set
-# CONFIG_MFD_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_CMMB is not set
-# CONFIG_FILE_LOCKING is not set
-# CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY_USER is not set
-# CONFIG_PROC_FS is not set
-# CONFIG_MISC_FILESYSTEMS is not set
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_FTRACE is not set
-CONFIG_OC_ETM=y
-# CONFIG_CRC32 is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK3026=y
-CONFIG_DDR_FREQ=y
-# CONFIG_DDR_TEST is not set
-CONFIG_MACH_RK3026_TB=y
-CONFIG_ARM_ERRATA_761320=y
-CONFIG_ARM_ERRATA_775420=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RKWIFI=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GT8XX=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_COMPASS_AK8975=y
-CONFIG_GS_MMA8452=y
-CONFIG_GS_LIS3DH=y
-CONFIG_GYRO_L3G4200D=y
-CONFIG_LS_CM3217=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-CONFIG_GS_KXTIK=y
-CONFIG_COMPASS_DEVICE=y
-CONFIG_GYROSCOPE_DEVICE=y
-CONFIG_LIGHT_DEVICE=y
-CONFIG_LS_AL3006=y
-CONFIG_LS_STK3171=y
-CONFIG_PROXIMITY_DEVICE=y
-CONFIG_PS_AL3006=y
-CONFIG_PS_STK3171=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_WM831X=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_TEST_POWER=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_MFD_TPS65090=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_REGULATOR_ACT8846=y
-CONFIG_RK30_PWM_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV2659=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL=y
-CONFIG_LCDC_RK3188=y
-CONFIG_LCDC0_RK3188=y
-CONFIG_LCDC1_RK3188=y
-CONFIG_LCD_B101EW05=y
-CONFIG_RK_TRSM=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_SOURCE_LCDC1=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2SO_USE_DOUBLE_CHANNELS=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK_SOC_HDMI_I2S=y
-CONFIG_SND_RK_SOC_RK3026=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_UHID=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_MMC_BLOCK_MINORS=12
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK30=y
-CONFIG_DDR_INIT_CHANGE_FREQ=y
-CONFIG_DDR_SDRAM_FREQ=300
-# CONFIG_DDR_TEST is not set
-CONFIG_CLK_SWITCH_TO_32K=y
-CONFIG_SOC_RK3028=y
-CONFIG_MACH_RK3028_86V=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_CFG80211=y
-CONFIG_MAC80211=y
-CONFIG_RFKILL=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RTL8188EU=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GSLX680_RK3028=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-CONFIG_GS_MXC6225=y
-# CONFIG_SERIO is not set
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_DMA_RK29=2
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_BATTERY_RK30_ADC_FAC=y
-CONFIG_BATTERY_RK30_AC_CHARGE=y
-CONFIG_BATTERY_RK30_VOL3V8=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_RK610=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_GC0308=y
-CONFIG_SOC_CAMERA_GC2035=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_RK3028_86V=y
-# CONFIG_RK610_TVOUT is not set
-CONFIG_FB_ROCKCHIP=y
-CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL=y
-CONFIG_LCDC_RK3066B=y
-CONFIG_LCDC1_RK3066B=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_RK610=y
-CONFIG_RK_HDMI_CTL_CODEC=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_RK610=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_UHID=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_AUTO_WAKE_UP=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=12
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-# CONFIG_UID16 is not set
-# CONFIG_HOTPLUG is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_BASE_FULL is not set
-# CONFIG_FUTEX is not set
-# CONFIG_EPOLL is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_SHMEM is not set
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_VM_EVENT_COUNTERS is not set
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_BLOCK is not set
-CONFIG_ARCH_RK30=y
-# CONFIG_DDR_FREQ is not set
-# CONFIG_DDR_TEST is not set
-CONFIG_RK_PM_TESTS=y
-# CONFIG_PM_TEST_CLK_RATE is not set
-# CONFIG_PM_TEST_CLK_VOLT is not set
-# CONFIG_PM_TEST_MAXFREQ is not set
-CONFIG_PM_TEST_FT=y
-# CONFIG_RK29_LAST_LOG is not set
-# CONFIG_RK_EARLY_PRINTK is not set
-CONFIG_RK_DEBUG_UART=0
-# CONFIG_RK_CONSOLE_THREAD is not set
-CONFIG_SOC_RK3028=y
-CONFIG_MACH_RK3028_FT=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0"
-CONFIG_CMDLINE_FORCE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-# CONFIG_BINFMT_ELF is not set
-# CONFIG_SUSPEND is not set
-# CONFIG_FW_LOADER is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_UNIX98_PTYS is not set
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_DEVMEM is not set
-# CONFIG_DEVKMEM is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_ADC is not set
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-# CONFIG_HWMON is not set
-# CONFIG_MFD_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_CMMB is not set
-# CONFIG_FILE_LOCKING is not set
-# CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY_USER is not set
-# CONFIG_PROC_FS is not set
-# CONFIG_MISC_FILESYSTEMS is not set
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_FTRACE is not set
-CONFIG_OC_ETM=y
-# CONFIG_CRC32 is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK30=y
-CONFIG_DDR_INIT_CHANGE_FREQ=y
-CONFIG_DDR_SDRAM_FREQ=300
-# CONFIG_DDR_FREQ is not set
-# CONFIG_DDR_TEST is not set
-CONFIG_RK_CLOCK_PROC=y
-CONFIG_CLK_SWITCH_TO_32K=y
-CONFIG_RK30_I2C_INSRAM=y
-CONFIG_SOC_RK3028=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_NL80211_TESTMODE=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_INPUT=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RKWIFI=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GT8XX=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_COMPASS_AK8975=y
-CONFIG_GS_MMA8452=y
-CONFIG_GS_LIS3DH=y
-CONFIG_GYRO_L3G4200D=y
-CONFIG_LS_CM3217=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-CONFIG_GS_KXTIK=y
-CONFIG_COMPASS_DEVICE=y
-CONFIG_GYROSCOPE_DEVICE=y
-CONFIG_LIGHT_DEVICE=y
-CONFIG_LS_AL3006=y
-CONFIG_LS_STK3171=y
-CONFIG_PROXIMITY_DEVICE=y
-CONFIG_PS_AL3006=y
-CONFIG_PS_STK3171=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_DMA_RK29=2
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_WM831X=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_TEST_POWER=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_RK29_WATCHDOG=y
-CONFIG_RK29_FEED_DOG_BY_INTE=y
-CONFIG_RK29_WATCHDOG_ATBOOT=y
-CONFIG_RK29_WATCHDOG_DEFAULT_TIME=5
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_MFD_TPS65090=y
-CONFIG_MFD_RK610=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_REGULATOR_ACT8846=y
-CONFIG_RK30_PWM_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV2659=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_ONE_LCDC_DUAL_OUTPUT_INF=y
-CONFIG_LCDC_RK3066B=y
-CONFIG_LCD_RK3168M_B101EW05=y
-CONFIG_RK_TRSM=y
-CONFIG_RK610_LVDS=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_RK610=y
-CONFIG_HDMI_SOURCE_LCDC1=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK_SOC_HDMI_I2S=y
-CONFIG_SND_RK29_SOC_RK610=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_UHID=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HYM8563=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_MTK_COMBO=y
-CONFIG_MTK_COMBO_PLAT_PATH="rockchip"
-CONFIG_MTK_COMBO_COMM=m
-CONFIG_MTK_COMBO_COMM_UART=m
-CONFIG_MTK_COMBO_BT_HCI=m
-CONFIG_MTK_COMBO_FM=m
-CONFIG_MTK_COMBO_WIFI=m
-CONFIG_MTK_GPS=m
-CONFIG_MTK_COMBO_GPS=m
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-CONFIG_DEBUG_LIST=y
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK3026=y
-CONFIG_DDR_FREQ=y
-# CONFIG_DDR_TEST is not set
-CONFIG_RK_CLOCK_PROC=y
-CONFIG_RK_USB_UART=y
-CONFIG_MACH_RK3028A_86V=y
-CONFIG_ARM_ERRATA_761320=y
-CONFIG_ARM_ERRATA_775420=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_CFG80211=y
-CONFIG_MAC80211=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RTL8188EU=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GSLX680_RK3028=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_GS_MMA7660=y
-CONFIG_GS_MMA8452=y
-CONFIG_GS_LIS3DH=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-CONFIG_GS_MXC6225=y
-CONFIG_GS_LSM303D=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_WM831X=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_BATTERY_RK30_ADC_FAC=y
-CONFIG_BATTERY_RK30_AC_CHARGE=y
-CONFIG_BATTERY_RK30_USB_CHARGE=y
-CONFIG_BATTERY_RK30_VOL3V8=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_MFD_TPS65090=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_REGULATOR_ACT8846=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-# CONFIG_SOC_CAMERA_OV3640 is not set
-# CONFIG_SOC_CAMERA_OV5642 is not set
-# CONFIG_SOC_CAMERA_OV5640 is not set
-CONFIG_SOC_CAMERA_GC0308=y
-CONFIG_SOC_CAMERA_GC2035=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL=y
-CONFIG_LCDC_RK3188=y
-CONFIG_LCDC0_RK3188=y
-CONFIG_LCDC1_RK3188=y
-CONFIG_LCD_RK3028_86V=y
-CONFIG_RK_TRSM=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_SOURCE_LCDC1=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2SO_USE_DOUBLE_CHANNELS=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK_SOC_HDMI_I2S=y
-CONFIG_SND_RK_SOC_RK3026=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_UHID=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_MMC_BLOCK_MINORS=32
-CONFIG_EMMC_RK=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK3026=y
-CONFIG_DDR_FREQ=y
-# CONFIG_DDR_TEST is not set
-CONFIG_RK_CLOCK_PROC=y
-CONFIG_RK_USB_UART=y
-CONFIG_MACH_RK3028A_FAC=y
-CONFIG_ARM_ERRATA_761320=y
-CONFIG_ARM_ERRATA_775420=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_CFG80211=y
-CONFIG_MAC80211=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RTL8188EU=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GSLX680_RK3028=y
-CONFIG_TOUCHSCREEN_GT811_IIC=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_GS_MMA7660=y
-CONFIG_GS_MMA8452=y
-CONFIG_GS_LIS3DH=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-CONFIG_GS_MXC6225=y
-CONFIG_GS_DMT10=y
-CONFIG_GS_LSM303D=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_WM831X=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_BATTERY_RK30_ADC_FAC=y
-CONFIG_BATTERY_RK30_AC_CHARGE=y
-CONFIG_BATTERY_RK30_USB_CHARGE=y
-CONFIG_BATTERY_RK30_VOL3V8=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_MFD_TPS65090=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_REGULATOR_ACT8846=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-# CONFIG_SOC_CAMERA_OV3640 is not set
-# CONFIG_SOC_CAMERA_OV5642 is not set
-# CONFIG_SOC_CAMERA_OV5640 is not set
-CONFIG_SOC_CAMERA_GC0308=y
-CONFIG_SOC_CAMERA_GC2035=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL=y
-CONFIG_LCDC_RK3188=y
-CONFIG_LCDC0_RK3188=y
-CONFIG_LCDC1_RK3188=y
-CONFIG_LCD_RK3168_FAC=y
-CONFIG_RK_TRSM=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_SOURCE_LCDC1=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2SO_USE_DOUBLE_CHANNELS=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK_SOC_HDMI_I2S=y
-CONFIG_SND_RK29_SOC_ES8323=y
-CONFIG_SND_RK29_SOC_RT5631=y
-CONFIG_SND_RK_SOC_RK3026=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_UHID=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK3026=y
-CONFIG_DDR_FREQ=y
-# CONFIG_DDR_TEST is not set
-CONFIG_RK_CLOCK_PROC=y
-CONFIG_MACH_RK3028A_TB=y
-CONFIG_ARM_ERRATA_761320=y
-CONFIG_ARM_ERRATA_775420=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RKWIFI=y
-CONFIG_BCM4330=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GT8XX=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_COMPASS_AK8975=y
-CONFIG_GS_MMA8452=y
-CONFIG_GS_LIS3DH=y
-CONFIG_GYRO_L3G4200D=y
-CONFIG_LS_CM3217=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-CONFIG_GS_KXTIK=y
-CONFIG_COMPASS_DEVICE=y
-CONFIG_GYROSCOPE_DEVICE=y
-CONFIG_LIGHT_DEVICE=y
-CONFIG_LS_AL3006=y
-CONFIG_LS_STK3171=y
-CONFIG_PROXIMITY_DEVICE=y
-CONFIG_PS_AL3006=y
-CONFIG_PS_STK3171=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_WM831X=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_TEST_POWER=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_MFD_TPS65090=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_REGULATOR_ACT8846=y
-CONFIG_RK30_PWM_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV2659=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL=y
-CONFIG_LCDC_RK3188=y
-CONFIG_LCDC0_RK3188=y
-CONFIG_LCDC1_RK3188=y
-CONFIG_LCD_B101EW05=y
-CONFIG_RK_TRSM=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_SOURCE_LCDC1=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2SO_USE_DOUBLE_CHANNELS=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK_SOC_HDMI_I2S=y
-CONFIG_SND_RK_SOC_RK3026=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_UHID=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_MMC_BLOCK_MINORS=32
-CONFIG_EMMC_RK=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE="/home/addy/work/openwrt/trunk/build_dir/target-arm_v7-a_uClibc-0.9.33.2_eabi/root-rk3066 /home/addy/work/openwrt/trunk/target/linux/generic/image/initramfs-base-files.txt"
-CONFIG_INITRAMFS_ROOT_UID=1000
-CONFIG_INITRAMFS_ROOT_GID=1000
-# CONFIG_RD_GZIP is not set
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK30=y
-CONFIG_CLK_SWITCH_TO_32K=y
-CONFIG_MACH_RK3066_SDK=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_BINFMT_AOUT=y
-CONFIG_BINFMT_MISC=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_RK29_VMAC=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RKWIFI=y
-CONFIG_RKWIFI_26M=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-# CONFIG_SERIO is not set
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_WM831X=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-# CONFIG_HWMON is not set
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_B101EW05=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL=y
-CONFIG_LCDC_RK30=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_RK30=y
-CONFIG_HDMI_SOURCE_LCDC1=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_UHID=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_INFO_REDUCED=y
-# CONFIG_FTRACE is not set
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK30=y
-CONFIG_CLK_SWITCH_TO_32K=y
-CONFIG_MACH_RK3066_SDK=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RKWIFI=y
-CONFIG_RKWIFI_26M=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GT8XX=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_COMPASS_AK8975=y
-CONFIG_GS_LIS3DH=y
-CONFIG_GYRO_L3G4200D=y
-CONFIG_LS_CM3217=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-CONFIG_COMPASS_DEVICE=y
-CONFIG_GYROSCOPE_DEVICE=y
-CONFIG_LIGHT_DEVICE=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_WM831X=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_TEST_POWER=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV2659=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL=y
-CONFIG_LCDC_RK30=y
-CONFIG_LCD_B101EW05=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_RK30=y
-CONFIG_HDMI_SOURCE_LCDC1=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_LOGO_LOWERPOWER_WARNING=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2SO_USE_DOUBLE_CHANNELS=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_RT5631=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_UHID=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK30=y
-CONFIG_CLK_SWITCH_TO_32K=y
-CONFIG_MACH_RK30_Z600T=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_BP_AUTO=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RKWIFI=y
-CONFIG_RKWIFI_26M=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_CT36X=y
-CONFIG_TOUCHSCREEN_CT36XX=y
-CONFIG_TOUCHSCREEN_CT36X_PLATFORM_ROCKCHIP=y
-CONFIG_TOUCHSCREEN_CT36X_CHIP_CT365=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_GS_MMA8452=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_RK_HEADSET_IRQ_HOOK_ADC_DET=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_WM831X=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_WM831X_BACKUP=y
-CONFIG_BATTERY_RK30_ADC_FAC=y
-CONFIG_BATTERY_RK30_AC_CHARGE=y
-CONFIG_BATTERY_RK30_USB_CHARGE=y
-CONFIG_BATTERY_RK30_VOL3V8=y
-CONFIG_POWER_ON_CHARGER_DISPLAY=y
-CONFIG_WM8326_VBAT_LOW_DETECTION=y
-CONFIG_CHARGER_SMB347=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_RK30_PWM_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV2659=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_HJ101NA=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL=y
-CONFIG_LCDC_RK30=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_RK30=y
-CONFIG_HDMI_SOURCE_LCDC1=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2SO_USE_DOUBLE_CHANNELS=y
-CONFIG_SND_RK_SOC_I2S2_2CH=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_RT3224=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE="root"
-CONFIG_INITRAMFS_COMPRESSION_GZIP=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_FORCE_LOAD=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK30=y
-# CONFIG_DDR_TEST is not set
-# CONFIG_RK29_LAST_LOG is not set
-CONFIG_RK_DEBUG_UART=1
-CONFIG_SOC_RK3066B=y
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init debug"
-CONFIG_VFP=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_UNIX=y
-# CONFIG_NET_ACTIVITY_STATS is not set
-# CONFIG_WIRELESS is not set
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MISC_DEVICES=y
-# CONFIG_ANDROID_PMEM is not set
-CONFIG_INPUT_POLLDEV=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-# CONFIG_I2C3_RK30 is not set
-# CONFIG_ADC is not set
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-# CONFIG_HWMON is not set
-# CONFIG_MFD_SUPPORT is not set
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV2659=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_TD043MGEA1=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_LCDC_RK31=y
-CONFIG_LCDC1_RK31=y
-# CONFIG_THREE_FB_BUFFER is not set
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_RK29_SOC_I2S_2CH=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_RK1000=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-# CONFIG_SDMMC1_RK29 is not set
-CONFIG_RTC_CLASS=y
-# CONFIG_CMMB is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DETECT_HUNG_TASK=y
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_SCHEDSTATS=y
-CONFIG_TIMER_STATS=y
-CONFIG_SLUB_DEBUG_ON=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_FTRACE is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK30=y
-# CONFIG_DDR_TEST is not set
-CONFIG_RK_CLOCK_PROC=y
-# CONFIG_RK_CONSOLE_THREAD is not set
-CONFIG_SOC_RK3066B=y
-CONFIG_MACH_RK3066B_M701=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_CFG80211=y
-CONFIG_MAC80211=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_RTL8188EU=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_FT5306_AV=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_GS_MMA7660=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_BATTERY_RK30_ADC_FAC=y
-CONFIG_BATTERY_RK30_AC_CHARGE=y
-CONFIG_BATTERY_RK30_VOL3V8=y
-CONFIG_POWER_ON_CHARGER_DISPLAY=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_TPS65090=y
-CONFIG_MFD_RK610=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_RK30_PWM_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_HI253=y
-CONFIG_SOC_CAMERA_HI704=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_HSD07PFW1=y
-CONFIG_RK610_LVDS=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_ONE_LCDC_DUAL_OUTPUT_INF=y
-CONFIG_LCDC_RK3066B=y
-CONFIG_LCDC1_RK3066B=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_RK610=y
-CONFIG_RK_HDMI_CTL_CODEC=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_RK610=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK30=y
-# CONFIG_DDR_TEST is not set
-CONFIG_SOC_RK3066B=y
-CONFIG_MACH_RK3066B_SDK=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RKWIFI=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GT8XX=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_COMPASS_AK8975=y
-CONFIG_GS_MMA8452=y
-CONFIG_GS_LIS3DH=y
-CONFIG_GYRO_L3G4200D=y
-CONFIG_LS_CM3217=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-CONFIG_GS_KXTIK=y
-CONFIG_COMPASS_DEVICE=y
-CONFIG_GYROSCOPE_DEVICE=y
-CONFIG_LIGHT_DEVICE=y
-CONFIG_LS_AL3006=y
-CONFIG_LS_STK3171=y
-CONFIG_PROXIMITY_DEVICE=y
-CONFIG_PS_AL3006=y
-CONFIG_PS_STK3171=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_WM831X=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_TEST_POWER=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_MFD_TPS65090=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_RK30_PWM_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV2659=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_B101EW05=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_ONE_LCDC_DUAL_OUTPUT_INF=y
-CONFIG_LCDC_RK3066B=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_RT5631=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK30=y
-CONFIG_MACH_RK30_DS1001B=y
-# CONFIG_SWP_EMULATE is not set
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_RFKILL=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RKWIFI=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GT8XX=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_MAG_SENSORS=y
-CONFIG_G_SENSOR_DEVICE=y
-CONFIG_GS_MMA8452=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_GPIO_WM831X=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_BATTERY_RK30_ADC=y
-CONFIG_BATTERY_RK30_AC_CHARGE=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV2655=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_B101EW05=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_LCDC_RK30=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_RK30=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2SO_USE_DOUBLE_CHANNELS=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_RT5631=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK30=y
-CONFIG_CLK_SWITCH_TO_32K=y
-CONFIG_MACH_RK30_DS975=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RKWIFI=y
-CONFIG_RKWIFI_26M=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_CT36X=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_COMPASS_AK8975=y
-CONFIG_GS_MMA8452=y
-CONFIG_GS_LIS3DH=y
-CONFIG_GYRO_L3G4200D=y
-CONFIG_LS_CM3217=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-CONFIG_GS_KXTIK=y
-CONFIG_COMPASS_DEVICE=y
-CONFIG_GYROSCOPE_DEVICE=y
-CONFIG_LIGHT_DEVICE=y
-CONFIG_LS_AL3006=y
-CONFIG_LS_STK3171=y
-CONFIG_PROXIMITY_DEVICE=y
-CONFIG_PS_AL3006=y
-CONFIG_PS_STK3171=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_WM831X=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_BATTERY_RK30_ADC_FAC=y
-CONFIG_BATTERY_RK30_AC_CHARGE=y
-CONFIG_BATTERY_RK30_VOL3V8=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV2659=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_LG_LP097X02=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL=y
-CONFIG_LCDC_RK30=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_RK30=y
-CONFIG_HDMI_SOURCE_LCDC1=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_LOGO_LOWERPOWER_WARNING=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2SO_USE_DOUBLE_CHANNELS=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_RT5631=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK30=y
-CONFIG_DDR_TYPE_LPDDR=y
-CONFIG_DDR_SDRAM_FREQ=300
-CONFIG_MACH_RK30_PHONE_A22=y
-# CONFIG_SWP_EMULATE is not set
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_RFKILL=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_RK29_SC8800=y
-CONFIG_TDSC8800=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_MII=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_BCM4329=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_INPUT_TABLET=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ILI2102_IIC=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_INPUT_WM831X_ON=y
-CONFIG_MAG_SENSORS=y
-CONFIG_COMPASS_AK8975=y
-CONFIG_G_SENSOR_DEVICE=y
-CONFIG_GS_MMA8452=y
-CONFIG_GYRO_SENSOR_DEVICE=y
-CONFIG_LIGHT_SENSOR_DEVICE=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C0_CONTROLLER_RK30=y
-# CONFIG_I2C1_RK30 is not set
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_I2C_GPIO_RK30=y
-CONFIG_SPI=y
-CONFIG_SPIM_RK29=y
-CONFIG_SPIM0_RK29=y
-CONFIG_SPIM1_RK29=y
-CONFIG_RK_HEADSET_DET=y
-CONFIG_GPIO_WM831X=y
-CONFIG_GPIO_WM8994=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_WM831X_BACKUP=y
-CONFIG_WM831X_POWER=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_MFD_WM8994=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_REGULATOR_WM8994=y
-CONFIG_RK30_PWM_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_GC0309=y
-CONFIG_VIDEO_RK29=y
-CONFIG_SMS_SIANO_MDTV=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-# CONFIG_BACKLIGHT_RK29_BL is not set
-CONFIG_BACKLIGHT_AW9364=y
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_NT35510=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_LCDC_RK30=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2SO_USE_DOUBLE_CHANNELS=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_WM8994=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_SCHEDSTATS=y
-CONFIG_TIMER_STATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_FTRACE is not set
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK30=y
-CONFIG_DDR_SDRAM_FREQ=300
-CONFIG_CLK_SWITCH_TO_32K=y
-CONFIG_MACH_RK30_PHONE=y
-# CONFIG_SWP_EMULATE is not set
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_RK29_SC8800=y
-CONFIG_TDSC8800=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_BCM4329=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_INPUT_TABLET=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_FT5306_WPX2=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_TWL6030_PWRBUTTON=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_COMPASS_AK8975=y
-CONFIG_GS_MMA8452=y
-CONFIG_GS_LIS3DH=y
-CONFIG_GYRO_L3G4200D=y
-CONFIG_LS_CM3217=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-CONFIG_GS_KXTIK=y
-CONFIG_COMPASS_DEVICE=y
-CONFIG_GYROSCOPE_DEVICE=y
-CONFIG_LIGHT_DEVICE=y
-CONFIG_LS_AL3006=y
-CONFIG_LS_STK3171=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_SPI=y
-CONFIG_SPIM_RK29=y
-CONFIG_SPIM1_RK29=y
-CONFIG_RK_HEADSET_IRQ_HOOK_ADC_DET=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_TWL6030_BCI_BATTERY=y
-CONFIG_POWER_ON_CHARGER_DISPLAY=y
-CONFIG_TWL60xx_VBAT_LOW_DETECTION=y
-# CONFIG_HWMON is not set
-CONFIG_TWL4030_CORE=y
-CONFIG_TWL6030_POWEROFF=y
-CONFIG_TWL6030_MADC=y
-CONFIG_TWL6030_GPADC=y
-CONFIG_AIC3262_CODEC=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TWL4030=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV7675=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_HSD100PXN_FOR_TDW851=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_LCDC_RK30=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2SO_USE_DOUBLE_CHANNELS=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_AIC3262=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_OTG=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_TWL4030=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_SCHEDSTATS=y
-CONFIG_TIMER_STATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_FTRACE is not set
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK30=y
-CONFIG_DDR_SDRAM_FREQ=300
-CONFIG_CLK_SWITCH_TO_32K=y
-CONFIG_MACH_RK30_PHONE_LOQUAT=y
-# CONFIG_SWP_EMULATE is not set
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_RK29_SC8800=y
-CONFIG_TDSC8800=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_BCM4329=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_INPUT_TABLET=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_SYNAPTICS_RMI4_I2C_RK=y
-CONFIG_TOUCHSCREEN_SYNAPTICS_S3202=y
-CONFIG_RMI4_BUS=y
-CONFIG_RMI4_I2C=y
-CONFIG_RMI4_I2C_SCL_RATE=400000
-CONFIG_RMI4_GENERIC=y
-CONFIG_RMI4_F1A=y
-CONFIG_RMI4_F11=y
-CONFIG_RMI4_F34=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_TWL6030_PWRBUTTON=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_COMPASS_AK8975=y
-CONFIG_GS_MMA8452=y
-CONFIG_GYRO_L3G4200D=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-CONFIG_COMPASS_DEVICE=y
-CONFIG_GYROSCOPE_DEVICE=y
-CONFIG_LIGHT_DEVICE=y
-CONFIG_LS_AL3006=y
-CONFIG_PROXIMITY_DEVICE=y
-CONFIG_PS_AL3006=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_SPI=y
-CONFIG_SPIM_RK29=y
-CONFIG_SPIM1_RK29=y
-CONFIG_RK_HEADSET_IRQ_HOOK_ADC_DET=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_TWL6030_BCI_BATTERY=y
-# CONFIG_HWMON is not set
-CONFIG_TWL4030_CORE=y
-CONFIG_TWL6030_POWEROFF=y
-CONFIG_TWL6030_MADC=y
-CONFIG_TWL6030_GPADC=y
-CONFIG_AIC3262_CODEC=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TWL4030=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_HJ050NA_06A=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_LCDC_RK30=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2SO_USE_DOUBLE_CHANNELS=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_AIC3262=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_TWL4030=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_SCHEDSTATS=y
-CONFIG_TIMER_STATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_FTRACE is not set
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK30=y
-CONFIG_DDR_SDRAM_FREQ=330
-CONFIG_RK_CLOCK_PROC=y
-CONFIG_CLK_SWITCH_TO_32K=y
-CONFIG_RK30_I2C_INSRAM=y
-CONFIG_RK_SRAM_DMA=y
-CONFIG_MACH_RK30_PHONE_PAD=y
-CONFIG_MACH_RK30_PHONE_PAD_C8003=y
-# CONFIG_SWP_EMULATE is not set
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_BP_AUTO=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_TUN=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RKWIFI=y
-CONFIG_RKWIFI_26M=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_WACOM_W8001=y
-CONFIG_TS_AUTO=y
-CONFIG_TS_AUTO_I2C=y
-CONFIG_TS_FT5306=y
-CONFIG_TS_GT8110=y
-CONFIG_TS_GT828=y
-CONFIG_TS_CT360=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_RK_BOARD_ID=y
-CONFIG_COMPASS_AK8975=y
-CONFIG_GS_MMA7660=y
-CONFIG_GS_MMA8452=y
-CONFIG_GS_LIS3DH=y
-CONFIG_GYRO_L3G4200D=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-CONFIG_GS_KXTIK=y
-CONFIG_COMPASS_DEVICE=y
-CONFIG_GYROSCOPE_DEVICE=y
-CONFIG_LIGHT_DEVICE=y
-CONFIG_LS_ISL29023=y
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-CONFIG_UART1_RK29=y
-CONFIG_UART1_CTS_RTS_RK29=y
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_RK_HEADSET_IRQ_HOOK_ADC_DET=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_WM831X=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_WM831X_BACKUP=y
-CONFIG_BATTERY_RK30_ADC_FAC=y
-CONFIG_BATTERY_RK30_AC_CHARGE=y
-CONFIG_BATTERY_RK30_VOL3V8=y
-CONFIG_POWER_ON_CHARGER_DISPLAY=y
-CONFIG_WM8326_VBAT_LOW_DETECTION=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_RK30_PWM_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV2659=y
-CONFIG_SOC_CAMERA_GT2005=y
-CONFIG_SOC_CAMERA_GC0308=y
-CONFIG_SOC_CAMERA_GC2035=y
-CONFIG_SOC_CAMERA_HI253=y
-CONFIG_SOC_CAMERA_HI704=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_AUTO=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL=y
-CONFIG_LCDC_RK30=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_RK30=y
-CONFIG_RK_HDMI_CTL_CODEC=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2SO_USE_DOUBLE_CHANNELS=y
-CONFIG_SND_RK_SOC_I2S2_2CH=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_RT5623=y
-CONFIG_SND_RK29_SOC_RT3224=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_ACM=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_QUALCOMM=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_SERIAL_USI=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK30=y
-CONFIG_DDR_SDRAM_FREQ=330
-CONFIG_RK_CLOCK_PROC=y
-CONFIG_CLK_SWITCH_TO_32K=y
-CONFIG_RK30_I2C_INSRAM=y
-CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC=y
-CONFIG_RK_SRAM_DMA=y
-CONFIG_MACH_RK30_PHONE_PAD=y
-# CONFIG_SWP_EMULATE is not set
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_HIDP=y
-CONFIG_CFG80211=y
-CONFIG_NL80211_TESTMODE=y
-CONFIG_MAC80211=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_INPUT=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_3G_MODULE=y
-CONFIG_MT6229=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_MT6620=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_CT360_IIC=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_COMPASS_AK8975=y
-CONFIG_GS_MMA8452=y
-CONFIG_GS_LIS3DH=y
-CONFIG_GYRO_L3G4200D=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-CONFIG_GS_KXTIK=y
-CONFIG_COMPASS_DEVICE=y
-CONFIG_GYROSCOPE_DEVICE=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_DMA_RK29=3
-CONFIG_UART1_RK29=y
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_RK_HEADSET_IRQ_HOOK_ADC_DET=y
-CONFIG_GPIO_WM831X=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_WM831X_BACKUP=y
-CONFIG_BATTERY_RK30_ADC=y
-CONFIG_BATTERY_RK30_AC_CHARGE=y
-CONFIG_BATTERY_RK30_VOL3V8=y
-CONFIG_POWER_ON_CHARGER_DISPLAY=y
-CONFIG_WM8326_VBAT_LOW_DETECTION=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_RK30_PWM_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_GT2005=y
-CONFIG_SOC_CAMERA_GC0308=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_HV070WSA100=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL=y
-CONFIG_LCDC_RK30=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_RK30=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2SO_USE_DOUBLE_CHANNELS=y
-CONFIG_SND_RK_SOC_I2S2_2CH=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_RT5623=y
-CONFIG_SND_RK29_SOC_RT3224=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_ACM=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_USI=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_RK29_SDIO_IRQ_FROM_GPIO=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_MTK_COMBO=y
-CONFIG_MTK_COMBO_PLAT_PATH="rockchip"
-CONFIG_MTK_COMBO_COMM=m
-CONFIG_MTK_COMBO_BT_HCI=m
-CONFIG_MTK_COMBO_FM=m
-CONFIG_MTK_COMBO_WIFI=m
-CONFIG_MTK_GPS=m
-CONFIG_MTK_COMBO_GPS=m
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK30=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RKWIFI=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GT8XX=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_COMPASS_AK8975=y
-CONFIG_GS_MMA8452=y
-CONFIG_GS_LIS3DH=y
-CONFIG_GYRO_L3G4200D=y
-CONFIG_LS_CM3217=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-CONFIG_GS_KXTIK=y
-CONFIG_COMPASS_DEVICE=y
-CONFIG_GYROSCOPE_DEVICE=y
-CONFIG_LIGHT_DEVICE=y
-CONFIG_LS_AL3006=y
-CONFIG_LS_STK3171=y
-CONFIG_PROXIMITY_DEVICE=y
-CONFIG_PS_AL3006=y
-CONFIG_PS_STK3171=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_WM831X=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_TEST_POWER=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV2659=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_B101EW05=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL=y
-CONFIG_LCDC_RK30=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_RK30=y
-CONFIG_HDMI_SOURCE_LCDC1=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2SO_USE_DOUBLE_CHANNELS=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_RT5631=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK30=y
-# CONFIG_DDR_TEST is not set
-CONFIG_SOC_RK3108=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RKWIFI=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GT8XX=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_COMPASS_AK8975=y
-CONFIG_GS_MMA8452=y
-CONFIG_GS_LIS3DH=y
-CONFIG_GYRO_L3G4200D=y
-CONFIG_LS_CM3217=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-CONFIG_GS_KXTIK=y
-CONFIG_COMPASS_DEVICE=y
-CONFIG_GYROSCOPE_DEVICE=y
-CONFIG_LIGHT_DEVICE=y
-CONFIG_LS_AL3006=y
-CONFIG_LS_STK3171=y
-CONFIG_PROXIMITY_DEVICE=y
-CONFIG_PS_AL3006=y
-CONFIG_PS_STK3171=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_WM831X=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_TEST_POWER=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_MFD_TPS65090=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_RK30_PWM_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV2659=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_B101EW05=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_ONE_LCDC_DUAL_OUTPUT_INF=y
-CONFIG_LCDC_RK3066B=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_RT5631=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK30=y
-CONFIG_DDR_INIT_CHANGE_FREQ=y
-CONFIG_DDR_SDRAM_FREQ=300
-# CONFIG_DDR_TEST is not set
-CONFIG_CLK_SWITCH_TO_32K=y
-CONFIG_SOC_RK3168=y
-CONFIG_MACH_RK3168_86V=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_CFG80211=y
-CONFIG_MAC80211=y
-CONFIG_RFKILL=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RTL8188EU=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GSLX680_RK3168=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_GS_MMA7660=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-CONFIG_GS_MXC6225=y
-# CONFIG_SERIO is not set
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_DMA_RK29=2
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_BATTERY_RK30_ADC_FAC=y
-CONFIG_BATTERY_RK30_AC_CHARGE=y
-CONFIG_BATTERY_RK30_VOL3V8=y
-CONFIG_POWER_ON_CHARGER_DISPLAY=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_REGULATOR_ACT8846=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_GC0308=y
-CONFIG_SOC_CAMERA_GC2035=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_E242868_1024X600=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_ONE_LCDC_DUAL_OUTPUT_INF=y
-CONFIG_LCDC_RK3066B=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_LOGO_LOWERPOWER_WARNING=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_ES8323=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_UHID=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_AUTO_WAKE_UP=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK30=y
-CONFIG_DDR_INIT_CHANGE_FREQ=y
-CONFIG_DDR_SDRAM_FREQ=300
-# CONFIG_DDR_TEST is not set
-CONFIG_RK_CLOCK_PROC=y
-CONFIG_CLK_SWITCH_TO_32K=y
-CONFIG_SOC_RK3168=y
-CONFIG_MACH_RK3168_86V=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_CFG80211=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RTL8188EU=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_86V_GT811_IIC=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_GS_MMA7660=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-# CONFIG_SERIO is not set
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_DMA_RK29=2
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_BATTERY_RK30_ADC_FAC=y
-CONFIG_BATTERY_RK30_AC_CHARGE=y
-CONFIG_BATTERY_RK30_VOL3V8=y
-CONFIG_POWER_ON_CHARGER_DISPLAY=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_MFD_RK610=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_REGULATOR_ACT8846=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_GC0308=y
-CONFIG_SOC_CAMERA_GC2035=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_RK3168_86V=y
-CONFIG_RK610_LVDS=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_ONE_LCDC_DUAL_OUTPUT_INF=y
-CONFIG_LCDC_RK3066B=y
-# CONFIG_LCDC0_RK3066B is not set
-CONFIG_LCDC1_RK3066B=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_LOGO_LOWERPOWER_WARNING=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_RK610=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_UHID=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_AUTO_WAKE_UP=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK30=y
-CONFIG_DDR_INIT_CHANGE_FREQ=y
-CONFIG_DDR_SDRAM_FREQ=324
-# CONFIG_DDR_FREQ is not set
-# CONFIG_DDR_TEST is not set
-CONFIG_RK_CLOCK_PROC=y
-CONFIG_CLK_SWITCH_TO_32K=y
-CONFIG_RK30_I2C_INSRAM=y
-CONFIG_SOC_RK3168=y
-CONFIG_MACH_RK3168_86V_OLD=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_CFG80211=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RTL8188EU=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_86V_GT811_IIC=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_GS_MMA7660=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_DMA_RK29=2
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_BATTERY_RK30_ADC_FAC=y
-CONFIG_BATTERY_RK30_AC_CHARGE=y
-CONFIG_BATTERY_RK30_VOL3V8=y
-CONFIG_POWER_ON_CHARGER_DISPLAY=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_RK29_WATCHDOG=y
-CONFIG_RK29_FEED_DOG_BY_INTE=y
-CONFIG_RK29_WATCHDOG_ATBOOT=y
-CONFIG_RK29_WATCHDOG_DEFAULT_TIME=5
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_RK610=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_ACT8846=y
-CONFIG_RK30_PWM_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_GC0308=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_RK3168_86V=y
-CONFIG_RK610_LVDS=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_ONE_LCDC_DUAL_OUTPUT_INF=y
-CONFIG_LCDC_RK3066B=y
-# CONFIG_LCDC0_RK3066B is not set
-CONFIG_LCDC1_RK3066B=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_RK610=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_UHID=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_AES=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK30=y
-CONFIG_DDR_INIT_CHANGE_FREQ=y
-CONFIG_DDR_SDRAM_FREQ=300
-# CONFIG_DDR_TEST is not set
-CONFIG_RK_CLOCK_PROC=y
-CONFIG_CLK_SWITCH_TO_32K=y
-CONFIG_RK30_I2C_INSRAM=y
-CONFIG_SOC_RK3168=y
-CONFIG_MACH_RK3168_86V=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_MAC80211=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_MT5931_MT6622=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GT82X_IIC=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_GS_LIS3DH=y
-CONFIG_GYRO_L3G4200D=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-CONFIG_COMPASS_DEVICE=y
-CONFIG_COMPASS_AK8963=y
-CONFIG_GYROSCOPE_DEVICE=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_DMA_RK29=2
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_BATTERY_RK30_ADC_FAC=y
-CONFIG_BATTERY_RK30_AC_CHARGE=y
-CONFIG_BATTERY_RK30_VOL3V8=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_RK29_WATCHDOG=y
-CONFIG_RK29_FEED_DOG_BY_INTE=y
-CONFIG_RK29_WATCHDOG_ATBOOT=y
-CONFIG_RK29_WATCHDOG_DEFAULT_TIME=5
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_REGULATOR_ACT8846=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV2659=y
-CONFIG_SOC_CAMERA_GC0308=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_RK3168_AUO_A080SN03=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_ONE_LCDC_DUAL_OUTPUT_INF=y
-CONFIG_LCDC_RK3066B=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_ES8323=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_UHID=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK30=y
-# CONFIG_DDR_TEST is not set
-CONFIG_RK_CLOCK_PROC=y
-CONFIG_SOC_RK3168=y
-CONFIG_MACH_RK3168_DS1006H=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_MT5931_MT6622=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_CT36X_TS=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_COMPASS_AK8975=y
-CONFIG_GS_MMA8452=y
-CONFIG_GS_LIS3DH=y
-CONFIG_GYRO_L3G4200D=y
-CONFIG_LS_CM3217=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-CONFIG_GS_KXTIK=y
-CONFIG_COMPASS_DEVICE=y
-CONFIG_GYROSCOPE_DEVICE=y
-CONFIG_LIGHT_DEVICE=y
-CONFIG_LS_AL3006=y
-CONFIG_LS_STK3171=y
-CONFIG_PROXIMITY_DEVICE=y
-CONFIG_PS_AL3006=y
-CONFIG_PS_STK3171=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_DMA_RK29=2
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_BATTERY_RK30_ADC_FAC=y
-CONFIG_BATTERY_RK30_AC_CHARGE=y
-CONFIG_BATTERY_RK30_VOL3V8=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_RK610=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_ACT8846=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV2659=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_DS1006H=y
-CONFIG_RK610_LVDS=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_ONE_LCDC_DUAL_OUTPUT_INF=y
-CONFIG_LCDC_RK3066B=y
-# CONFIG_LCDC0_RK3066B is not set
-CONFIG_LCDC1_RK3066B=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_RK610=y
-CONFIG_HDMI_SOURCE_LCDC1=y
-CONFIG_RK_HDMI_CTL_CODEC=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_RK610=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_UHID=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HYM8563=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK30=y
-CONFIG_DDR_INIT_CHANGE_FREQ=y
-CONFIG_DDR_SDRAM_FREQ=300
-# CONFIG_DDR_TEST is not set
-CONFIG_RK_CLOCK_PROC=y
-CONFIG_CLK_SWITCH_TO_32K=y
-CONFIG_RK30_I2C_INSRAM=y
-CONFIG_SOC_RK3168=y
-CONFIG_MACH_RK3168_86V=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_MAC80211=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_MT5931_MT6622=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GT82X_IIC=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_GS_LIS3DH=y
-CONFIG_GYRO_L3G4200D=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-CONFIG_COMPASS_DEVICE=y
-CONFIG_COMPASS_AK8963=y
-CONFIG_GYROSCOPE_DEVICE=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_DMA_RK29=2
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_BATTERY_RK30_ADC_FAC=y
-CONFIG_BATTERY_RK30_AC_CHARGE=y
-CONFIG_BATTERY_RK30_VOL3V8=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_RK29_WATCHDOG=y
-CONFIG_RK29_FEED_DOG_BY_INTE=y
-CONFIG_RK29_WATCHDOG_ATBOOT=y
-CONFIG_RK29_WATCHDOG_DEFAULT_TIME=5
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_REGULATOR_ACT8846=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV2659=y
-CONFIG_SOC_CAMERA_GC0308=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_RK3168_AUO_A080SN03=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_ONE_LCDC_DUAL_OUTPUT_INF=y
-CONFIG_LCDC_RK3066B=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_ES8323=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_UHID=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=12
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-# CONFIG_UID16 is not set
-# CONFIG_HOTPLUG is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_BASE_FULL is not set
-# CONFIG_FUTEX is not set
-# CONFIG_EPOLL is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_SHMEM is not set
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_VM_EVENT_COUNTERS is not set
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_BLOCK is not set
-CONFIG_ARCH_RK30=y
-# CONFIG_DDR_FREQ is not set
-# CONFIG_DDR_TEST is not set
-CONFIG_RK_PM_TESTS=y
-# CONFIG_PM_TEST_CLK_RATE is not set
-# CONFIG_PM_TEST_CLK_VOLT is not set
-# CONFIG_PM_TEST_MAXFREQ is not set
-CONFIG_PM_TEST_FT=y
-# CONFIG_RK29_LAST_LOG is not set
-# CONFIG_RK_EARLY_PRINTK is not set
-# CONFIG_RK_CONSOLE_THREAD is not set
-CONFIG_SOC_RK3168=y
-CONFIG_MACH_RK3168_FT=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0"
-CONFIG_CMDLINE_FORCE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-# CONFIG_BINFMT_ELF is not set
-# CONFIG_SUSPEND is not set
-# CONFIG_FW_LOADER is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_UNIX98_PTYS is not set
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_DEVMEM is not set
-# CONFIG_DEVKMEM is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_ADC is not set
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-# CONFIG_HWMON is not set
-# CONFIG_MFD_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_CMMB is not set
-# CONFIG_FILE_LOCKING is not set
-# CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY_USER is not set
-# CONFIG_PROC_FS is not set
-# CONFIG_MISC_FILESYSTEMS is not set
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_FTRACE is not set
-CONFIG_OC_ETM=y
-# CONFIG_CRC32 is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK30=y
-CONFIG_DDR_INIT_CHANGE_FREQ=y
-CONFIG_DDR_SDRAM_FREQ=300
-# CONFIG_DDR_TEST is not set
-CONFIG_CLK_SWITCH_TO_32K=y
-CONFIG_SOC_RK3168=y
-CONFIG_MACH_RK3168_86V=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_CFG80211=y
-CONFIG_MAC80211=y
-CONFIG_RFKILL=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RTL8188EU=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GSLX680_RK3168=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_GS_MMA7660=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-CONFIG_GS_MXC6225=y
-# CONFIG_SERIO is not set
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_DMA_RK29=2
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_BATTERY_RK30_ADC_FAC=y
-CONFIG_BATTERY_RK30_AC_CHARGE=y
-CONFIG_BATTERY_RK30_VOL3V8=y
-CONFIG_POWER_ON_CHARGER_DISPLAY=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_MFD_RK616=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_REGULATOR_ACT8846=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_GC0308=y
-CONFIG_SOC_CAMERA_GC2035=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_ONE_LCDC_DUAL_OUTPUT_INF=y
-CONFIG_LCDC_RK3066B=y
-# CONFIG_LCDC0_RK3066B is not set
-CONFIG_LCDC1_RK3066B=y
-CONFIG_LCD_E242868_RK616_1024X600=y
-CONFIG_RK_TRSM=y
-CONFIG_RK616_LVDS=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_RK616=y
-CONFIG_HDMI_SOURCE_LCDC1=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_LOGO_LOWERPOWER_WARNING=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK_SOC_HDMI_SPDIF=y
-CONFIG_SND_RK_SOC_RK616=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_UHID=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_AUTO_WAKE_UP=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK30=y
-CONFIG_DDR_INIT_CHANGE_FREQ=y
-CONFIG_DDR_SDRAM_FREQ=300
-# CONFIG_DDR_TEST is not set
-CONFIG_CLK_SWITCH_TO_32K=y
-CONFIG_SOC_RK3168=y
-CONFIG_MACH_RK3168_FAC=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_CFG80211=y
-CONFIG_MAC80211=y
-CONFIG_RFKILL=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RTL8188EU=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GSLX680_RK3168=y
-CONFIG_TOUCHSCREEN_GT811_IIC=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_GS_MMA7660=y
-CONFIG_GS_LIS3DH=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-CONFIG_GS_MXC6225=y
-CONFIG_GS_DMT10=y
-# CONFIG_SERIO is not set
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_DMA_RK29=2
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_BATTERY_RK30_ADC_FAC=y
-CONFIG_BATTERY_RK30_AC_CHARGE=y
-CONFIG_BATTERY_RK30_VOL3V8=y
-CONFIG_POWER_ON_CHARGER_DISPLAY=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_MFD_RK616=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_REGULATOR_ACT8846=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_GC0308=y
-CONFIG_SOC_CAMERA_GC2035=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_ONE_LCDC_DUAL_OUTPUT_INF=y
-CONFIG_LCDC_RK3066B=y
-# CONFIG_LCDC0_RK3066B is not set
-CONFIG_LCDC1_RK3066B=y
-CONFIG_LCD_RK3168_FAC=y
-CONFIG_RK_TRSM=y
-CONFIG_RK616_LVDS=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_RK616=y
-CONFIG_HDMI_SOURCE_LCDC1=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_LOGO_LOWERPOWER_WARNING=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2S_DMA_EVENT_DYNAMIC=y
-CONFIG_SND_RK_SOC_HDMI_SPDIF=y
-CONFIG_SND_RK29_SOC_ES8323=y
-CONFIG_SND_RK29_SOC_RT5631=y
-CONFIG_SND_RK_SOC_RK616=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_UHID=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_AUTO_WAKE_UP=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK30=y
-# CONFIG_DDR_TEST is not set
-CONFIG_SOC_RK3168=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RKWIFI=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GT8XX=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_COMPASS_AK8975=y
-CONFIG_GS_MMA8452=y
-CONFIG_GS_LIS3DH=y
-CONFIG_GYRO_L3G4200D=y
-CONFIG_LS_CM3217=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-CONFIG_GS_KXTIK=y
-CONFIG_COMPASS_DEVICE=y
-CONFIG_GYROSCOPE_DEVICE=y
-CONFIG_LIGHT_DEVICE=y
-CONFIG_LS_AL3006=y
-CONFIG_LS_STK3171=y
-CONFIG_PROXIMITY_DEVICE=y
-CONFIG_PS_AL3006=y
-CONFIG_PS_STK3171=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_WM831X=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_TEST_POWER=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_MFD_TPS65090=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_REGULATOR_ACT8846=y
-CONFIG_RK30_PWM_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV2659=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_B101EW05=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_ONE_LCDC_DUAL_OUTPUT_INF=y
-CONFIG_LCDC_RK3066B=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_RT5631=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_UHID=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HYM8563=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK30=y
-# CONFIG_DDR_TEST is not set
-CONFIG_SOC_RK3168M=y
-CONFIG_MACH_RK3168M_F304=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RKWIFI=y
-CONFIG_RKWIFI_26M=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_CT36XX=y
-CONFIG_TOUCHSCREEN_CT36X_PLATFORM_ROCKCHIP=y
-CONFIG_TOUCHSCREEN_CT36X_CHIP_CT365=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_RICOH619_PWRKEY=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_GS_MMA8452=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-# CONFIG_SERIO is not set
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_WM831X=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_BATTERY_RICOH619=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_RICOH619=y
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_MFD_TPS65090=y
-CONFIG_MFD_RK616=y
-CONFIG_RK616_DEBUG=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_REGULATOR_RICOH619=y
-CONFIG_REGULATOR_ACT8846=y
-CONFIG_RK30_PWM_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-# CONFIG_SOC_CAMERA_OV3640 is not set
-# CONFIG_SOC_CAMERA_OV5642 is not set
-# CONFIG_SOC_CAMERA_OV5640 is not set
-CONFIG_SOC_CAMERA_NT99252=y
-CONFIG_SOC_CAMERA_NT99340=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL=y
-CONFIG_LCDC_RK3066B=y
-CONFIG_LCDC1_RK3066B=y
-CONFIG_LCD_LD089WU1_MIPI=y
-CONFIG_RK_TRSM=y
-CONFIG_MIPI_DSI=y
-CONFIG_RK616_MIPI_DSI=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_RK616=y
-CONFIG_RK_HDMI_DEBUG=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK_SOC_HDMI_SPDIF=y
-CONFIG_SND_RK_SOC_RK616=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_UHID=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_TPS65910_RTC=y
-CONFIG_RTC_DRV_RC5T619=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK30=y
-# CONFIG_DDR_TEST is not set
-CONFIG_SOC_RK3168M=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_NR_CPUS=2
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RKWIFI=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GT8XX=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_COMPASS_AK8975=y
-CONFIG_GS_MMA8452=y
-CONFIG_GS_LIS3DH=y
-CONFIG_GYRO_L3G4200D=y
-CONFIG_LS_CM3217=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-CONFIG_GS_KXTIK=y
-CONFIG_COMPASS_DEVICE=y
-CONFIG_GYROSCOPE_DEVICE=y
-CONFIG_LIGHT_DEVICE=y
-CONFIG_LS_AL3006=y
-CONFIG_LS_STK3171=y
-CONFIG_PROXIMITY_DEVICE=y
-CONFIG_PS_AL3006=y
-CONFIG_PS_STK3171=y
-# CONFIG_SERIO is not set
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_WM831X=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_TEST_POWER=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_MFD_TPS65090=y
-CONFIG_MFD_RK616=y
-CONFIG_RK616_USE_MCLK_12M=y
-CONFIG_RK616_DEBUG=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_REGULATOR_ACT8846=y
-CONFIG_RK30_PWM_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV2659=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL=y
-CONFIG_LCDC_RK3066B=y
-CONFIG_LCDC1_RK3066B=y
-CONFIG_LCD_B101EW05=y
-CONFIG_RK_TRSM=y
-CONFIG_RK616_LVDS=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_RK616=y
-CONFIG_HDMI_SOURCE_LCDC1=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK_SOC_HDMI_SPDIF=y
-CONFIG_SND_RK_SOC_RK616=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_UHID=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK3188=y
-CONFIG_DDR_INIT_CHANGE_FREQ=y
-CONFIG_DDR_SDRAM_FREQ=300
-# CONFIG_DDR_TEST is not set
-CONFIG_RK_CLOCK_PROC=y
-CONFIG_CLK_SWITCH_TO_32K=y
-CONFIG_RK_USB_UART=y
-CONFIG_MACH_RK3188_LR097=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_MAC80211=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_MT5931_MT6622=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_CT36X_TS=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_GS_MMA8452=y
-CONFIG_GS_LIS3DH=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-# CONFIG_SERIO is not set
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_DMA_RK29=2
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_WM831X=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_POWER_ON_CHARGER_DISPLAY=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_RK29_WATCHDOG=y
-CONFIG_RK29_FEED_DOG_BY_INTE=y
-CONFIG_RK29_WATCHDOG_ATBOOT=y
-CONFIG_RK29_WATCHDOG_DEFAULT_TIME=5
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_MFD_TPS65090=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_REGULATOR_ACT8846=y
-CONFIG_ACT8846_SUPPORT_RESET=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_GC2035=y
-CONFIG_SOC_CAMERA_SP2518=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL=y
-CONFIG_LCDC_RK3188=y
-CONFIG_LCDC0_RK3188=y
-CONFIG_LCDC1_RK3188=y
-CONFIG_LCD_LP097QX1=y
-CONFIG_RK_TRSM=y
-CONFIG_DP_ANX6345=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_CAT66121=y
-CONFIG_HDMI_SOURCE_LCDC1=y
-CONFIG_RK_HDMI_CTL_CODEC=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2S_USE_33V=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_RT5631=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_UHID=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HYM8563=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_UMS_AS_CDROM=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK3188=y
-# CONFIG_DDR_TEST is not set
-CONFIG_RK_CLOCK_PROC=y
-CONFIG_RK_USB_UART=y
-CONFIG_MACH_RK3188_AC=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCALER_DEVICE=y
-CONFIG_SCALER_DEVICE_DDC=y
-CONFIG_SCALER_TEST=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_RK29_VMAC=y
-CONFIG_PHY_PORT_NUM=5
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-# CONFIG_BCM_OOB_ENABLED is not set
-CONFIG_RKWIFI=y
-CONFIG_AP6210=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_CT36X_TS=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_GS_MMA8452=y
-CONFIG_GS_LIS3DH=y
-CONFIG_GYRO_L3G4200D=y
-CONFIG_LIGHT_SENSOR_DEVICE=y
-CONFIG_LS_US5151=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-CONFIG_COMPASS_DEVICE=y
-CONFIG_COMPASS_AK8963=y
-CONFIG_GYROSCOPE_DEVICE=y
-CONFIG_ROCKCHIP_REMOTECTL=y
-CONFIG_RK_REMOTECTL=y
-CONFIG_RK_IR_WAKEUP=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_BATTERY_RK30_ADC_FAC=y
-CONFIG_BATTERY_RK30_AC_CHARGE=y
-CONFIG_BATTERY_RK30_VOL3V8=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_RK29_WATCHDOG=y
-CONFIG_RK29_FEED_DOG_BY_INTE=y
-CONFIG_RK29_WATCHDOG_ATBOOT=y
-CONFIG_RK29_WATCHDOG_DEFAULT_TIME=5
-CONFIG_MFD_RK610=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_ACT8846=y
-CONFIG_ACT8846_SUPPORT_RESET=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV2659=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_USB_VIDEO_CLASS=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_ONE_LCDC_DUAL_OUTPUT_INF=y
-CONFIG_LCDC_RK3188=y
-CONFIG_LCDC0_RK3188=y
-CONFIG_LCD_ANDROIDCOMPUTER=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_CAT66121=y
-CONFIG_HDMI_SOURCE_LCDC1=y
-CONFIG_RK_HDMI_CTL_CODEC=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK_SOC_HDMI_I2S=y
-CONFIG_SND_RK29_SOC_CX2070X=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_UHID=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_SERIAL_USI=y
-CONFIG_USB_GADGET=y
-CONFIG_BYPASS_INPUT_TO_HIDG=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD=y
-# CONFIG_SDMMC1_RK29 is not set
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HYM8563=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-CONFIG_CIFS=y
-CONFIG_CIFS_STATS=y
-CONFIG_CIFS_STATS2=y
-CONFIG_CIFS_WEAK_PW_HASH=y
-CONFIG_CIFS_XATTR=y
-CONFIG_CIFS_POSIX=y
-CONFIG_CIFS_DEBUG2=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_UTF8=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK3188=y
-# CONFIG_DDR_TEST is not set
-CONFIG_RK_CLOCK_PROC=y
-CONFIG_RK_USB_UART=y
-CONFIG_MACH_RK3188_DS1006H=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_MT5931_MT6622=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_CT36X_TS=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_GS_MMA8452=y
-CONFIG_GS_LIS3DH=y
-CONFIG_GYRO_L3G4200D=y
-CONFIG_LIGHT_SENSOR_DEVICE=y
-CONFIG_LS_US5151=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-CONFIG_COMPASS_DEVICE=y
-CONFIG_COMPASS_AK8963=y
-CONFIG_GYROSCOPE_DEVICE=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_DMA_RK29=2
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_BATTERY_RK30_ADC_FAC=y
-CONFIG_BATTERY_RK30_AC_CHARGE=y
-CONFIG_BATTERY_RK30_VOL3V8=y
-CONFIG_POWER_ON_CHARGER_DISPLAY=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_RK29_WATCHDOG=y
-CONFIG_RK29_FEED_DOG_BY_INTE=y
-CONFIG_RK29_WATCHDOG_ATBOOT=y
-CONFIG_RK29_WATCHDOG_DEFAULT_TIME=5
-CONFIG_MFD_RK610=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_ACT8846=y
-CONFIG_ACT8846_SUPPORT_RESET=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV2659=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_DS1006H=y
-# CONFIG_RK610_TVOUT is not set
-CONFIG_FB_ROCKCHIP=y
-CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL=y
-CONFIG_LCDC_RK3188=y
-CONFIG_LCDC0_RK3188=y
-CONFIG_LCDC1_RK3188=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_CAT66121=y
-CONFIG_RK_HDMI_CTL_CODEC=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2S_USE_33V=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_RT5631=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_UHID=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_SERIAL_USI=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HYM8563=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK3188=y
-# CONFIG_DDR_TEST is not set
-CONFIG_RK_CLOCK_PROC=y
-CONFIG_MACH_RK3188_DS1006H=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_MT5931_MT6622=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_CT36X_TS=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_COMPASS_AK8975=y
-CONFIG_GS_MMA8452=y
-CONFIG_GS_LIS3DH=y
-CONFIG_GYRO_L3G4200D=y
-CONFIG_LIGHT_SENSOR_DEVICE=y
-CONFIG_LS_US5151=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-CONFIG_GS_KXTIK=y
-CONFIG_COMPASS_DEVICE=y
-CONFIG_GYROSCOPE_DEVICE=y
-CONFIG_LIGHT_DEVICE=y
-CONFIG_LS_AL3006=y
-CONFIG_LS_STK3171=y
-CONFIG_PROXIMITY_DEVICE=y
-CONFIG_PS_AL3006=y
-CONFIG_PS_STK3171=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_DMA_RK29=2
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_BATTERY_RK30_ADC_FAC=y
-CONFIG_BATTERY_RK30_AC_CHARGE=y
-CONFIG_BATTERY_RK30_VOL3V8=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_RK610=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_ACT8846=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV2659=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_DS1006H=y
-CONFIG_RK610_LVDS=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_ONE_LCDC_DUAL_OUTPUT_INF=y
-CONFIG_LCDC_RK3188=y
-CONFIG_LCDC1_RK3188=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_RK610=y
-CONFIG_HDMI_SOURCE_LCDC1=y
-CONFIG_RK_HDMI_CTL_CODEC=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_RK610=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_UHID=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HYM8563=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK3188=y
-# CONFIG_DDR_TEST is not set
-CONFIG_RK_CLOCK_PROC=y
-CONFIG_RK_USB_UART=y
-CONFIG_MACH_RK3188_DS1006H=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_MT5931_MT6622=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_CT36X_TS=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_GS_MMA8452=y
-CONFIG_GS_LIS3DH=y
-CONFIG_GYRO_L3G4200D=y
-CONFIG_LIGHT_SENSOR_DEVICE=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-CONFIG_COMPASS_DEVICE=y
-CONFIG_COMPASS_AK8963=y
-CONFIG_GYROSCOPE_DEVICE=y
-CONFIG_LIGHT_DEVICE=y
-CONFIG_LS_PHOTORESISTOR=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_DMA_RK29=2
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_CW2015_BATTERY=y
-CONFIG_POWER_ON_CHARGER_DISPLAY=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_RK29_WATCHDOG=y
-CONFIG_RK29_FEED_DOG_BY_INTE=y
-CONFIG_RK29_WATCHDOG_ATBOOT=y
-CONFIG_RK29_WATCHDOG_DEFAULT_TIME=5
-CONFIG_MFD_RK610=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_ACT8846=y
-CONFIG_ACT8846_SUPPORT_RESET=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV2659=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL=y
-CONFIG_LCDC_RK3188=y
-CONFIG_LCDC0_RK3188=y
-CONFIG_LCDC1_RK3188=y
-CONFIG_LCD_DS1006H=y
-CONFIG_RK_TRSM=y
-CONFIG_RK610_LVDS=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_CAT66121=y
-CONFIG_RK_HDMI_CTL_CODEC=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK_SOC_HDMI_I2S=y
-CONFIG_SND_RK29_SOC_RK610=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_UHID=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_SERIAL_USI=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HYM8563=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE="root"
-CONFIG_INITRAMFS_COMPRESSION_GZIP=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_FORCE_LOAD=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK3188=y
-# CONFIG_DDR_TEST is not set
-# CONFIG_RK29_LAST_LOG is not set
-CONFIG_RK_DEBUG_UART=1
-CONFIG_MACH_RK3188_FPGA=y
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init debug"
-CONFIG_VFP=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_UNIX=y
-# CONFIG_NET_ACTIVITY_STATS is not set
-# CONFIG_WIRELESS is not set
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MISC_DEVICES=y
-CONFIG_INPUT_POLLDEV=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-# CONFIG_I2C3_RK30 is not set
-# CONFIG_ADC is not set
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-# CONFIG_HWMON is not set
-# CONFIG_MFD_SUPPORT is not set
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV2659=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_TD043MGEA1=y
-CONFIG_FB_ROCKCHIP=y
-# CONFIG_THREE_FB_BUFFER is not set
-CONFIG_LCDC_RK3188=y
-CONFIG_LCDC0_RK3188=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_RK29_SOC_I2S_2CH=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_RK1000=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_RTC_CLASS=y
-# CONFIG_CMMB is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DETECT_HUNG_TASK=y
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_SCHEDSTATS=y
-CONFIG_TIMER_STATS=y
-CONFIG_SLUB_DEBUG_ON=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_FTRACE is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=12
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-# CONFIG_UID16 is not set
-# CONFIG_HOTPLUG is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_BASE_FULL is not set
-# CONFIG_FUTEX is not set
-# CONFIG_EPOLL is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_SHMEM is not set
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_VM_EVENT_COUNTERS is not set
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_BLOCK is not set
-CONFIG_ARCH_RK3188=y
-# CONFIG_DDR_FREQ is not set
-# CONFIG_DDR_TEST is not set
-CONFIG_RK_PM_TESTS=y
-# CONFIG_PM_TEST_CLK_RATE is not set
-# CONFIG_PM_TEST_CLK_VOLT is not set
-# CONFIG_PM_TEST_MAXFREQ is not set
-CONFIG_PM_TEST_FT=y
-# CONFIG_RK29_LAST_LOG is not set
-# CONFIG_RK_EARLY_PRINTK is not set
-# CONFIG_RK_CONSOLE_THREAD is not set
-CONFIG_MACH_RK3188_FT=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0"
-CONFIG_CMDLINE_FORCE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-# CONFIG_BINFMT_ELF is not set
-# CONFIG_SUSPEND is not set
-# CONFIG_FW_LOADER is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_UNIX98_PTYS is not set
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_DEVMEM is not set
-# CONFIG_DEVKMEM is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_ADC is not set
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-# CONFIG_HWMON is not set
-# CONFIG_MFD_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_CMMB is not set
-# CONFIG_FILE_LOCKING is not set
-# CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY_USER is not set
-# CONFIG_PROC_FS is not set
-# CONFIG_MISC_FILESYSTEMS is not set
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_FTRACE is not set
-CONFIG_OC_ETM=y
-# CONFIG_CRC32 is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK3188=y
-# CONFIG_DDR_TEST is not set
-CONFIG_RK_CLOCK_PROC=y
-CONFIG_MACH_RK3188_JETTAB=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RKWIFI=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GT8XX=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_COMPASS_AK8975=y
-CONFIG_GS_MMA8452=y
-CONFIG_GS_LIS3DH=y
-CONFIG_GYRO_L3G4200D=y
-CONFIG_LS_CM3217=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-CONFIG_GS_KXTIK=y
-CONFIG_COMPASS_DEVICE=y
-CONFIG_GYROSCOPE_DEVICE=y
-CONFIG_LIGHT_DEVICE=y
-CONFIG_LS_AL3006=y
-CONFIG_LS_STK3171=y
-CONFIG_PROXIMITY_DEVICE=y
-CONFIG_PS_AL3006=y
-CONFIG_PS_STK3171=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_WM831X=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_TEST_POWER=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_MFD_TPS65090=y
-CONFIG_MFD_RK616=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_REGULATOR_ACT8846=y
-CONFIG_RK30_PWM_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV2659=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL=y
-CONFIG_LCDC_RK3188=y
-CONFIG_LCDC0_RK3188=y
-CONFIG_LCDC1_RK3188=y
-CONFIG_LCD_B101EW05=y
-CONFIG_RK_TRSM=y
-CONFIG_RK616_LVDS=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_RK616=y
-CONFIG_RK_HDMI_DEBUG=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK_SOC_HDMI_SPDIF=y
-CONFIG_SND_RK_SOC_RK616=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_UHID=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK3188=y
-# CONFIG_DDR_TEST is not set
-CONFIG_RK_CLOCK_PROC=y
-CONFIG_MACH_RK3188_RK618=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RKWIFI=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GT8XX=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_WM831X=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_TEST_POWER=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_MFD_TPS65090=y
-CONFIG_MFD_RK616=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_REGULATOR_ACT8846=y
-CONFIG_RK30_PWM_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-# CONFIG_VIDEO_CAPTURE_DRIVERS is not set
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL=y
-CONFIG_LCDC_RK3188=y
-CONFIG_LCDC0_RK3188=y
-CONFIG_LCDC1_RK3188=y
-CONFIG_LCD_B101EW05=y
-CONFIG_RK_TRSM=y
-CONFIG_RK616_LVDS=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_RK616=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK_SOC_HDMI_SPDIF=y
-CONFIG_SND_RK_SOC_RK616=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_UHID=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK3188=y
-# CONFIG_DDR_TEST is not set
-CONFIG_RK_CLOCK_PROC=y
-CONFIG_MACH_RK3188_FAC=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RKWIFI=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GT8XX=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_WM831X=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_TEST_POWER=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_MFD_TPS65090=y
-CONFIG_MFD_RK616=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_REGULATOR_ACT8846=y
-CONFIG_RK30_PWM_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-# CONFIG_VIDEO_CAPTURE_DRIVERS is not set
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL=y
-CONFIG_LCDC_RK3188=y
-CONFIG_LCDC0_RK3188=y
-CONFIG_LCDC1_RK3188=y
-CONFIG_LCD_B101EW05=y
-CONFIG_RK_TRSM=y
-CONFIG_RK616_LVDS=y
-CONFIG_RK_HDMI=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK_SOC_HDMI_SPDIF=y
-CONFIG_SND_RK_SOC_RK616=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_UHID=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK3188=y
-# CONFIG_DDR_TEST is not set
-CONFIG_MACH_RK3188_SDK=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_RK29_SUPPORT_MODEM=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RKWIFI=y
-CONFIG_RKWIFI_26M=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GT8XX=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_COMPASS_AK8975=y
-CONFIG_GS_MMA8452=y
-CONFIG_GS_LIS3DH=y
-CONFIG_GYRO_L3G4200D=y
-CONFIG_LS_CM3217=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-CONFIG_GS_KXTIK=y
-CONFIG_COMPASS_DEVICE=y
-CONFIG_GYROSCOPE_DEVICE=y
-CONFIG_LIGHT_DEVICE=y
-CONFIG_LS_AL3006=y
-CONFIG_LS_STK3171=y
-CONFIG_PROXIMITY_DEVICE=y
-CONFIG_PS_AL3006=y
-CONFIG_PS_STK3171=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_WM831X=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_CW2015_BATTERY=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_MFD_TPS65090=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_REGULATOR_ACT8846=y
-CONFIG_RK30_PWM_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV2659=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_B101EW05=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL=y
-CONFIG_LCDC_RK3188=y
-CONFIG_LCDC0_RK3188=y
-CONFIG_LCDC1_RK3188=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_CAT66121=y
-CONFIG_HDMI_SOURCE_LCDC1=y
-CONFIG_RK_HDMI_CTL_CODEC=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_RT5616=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_UHID=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HYM8563=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK3188=y
-# CONFIG_DDR_TEST is not set
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RKWIFI=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GT8XX=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_COMPASS_AK8975=y
-CONFIG_GS_MMA8452=y
-CONFIG_GS_LIS3DH=y
-CONFIG_GYRO_L3G4200D=y
-CONFIG_LS_CM3217=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-CONFIG_GS_KXTIK=y
-CONFIG_COMPASS_DEVICE=y
-CONFIG_GYROSCOPE_DEVICE=y
-CONFIG_LIGHT_DEVICE=y
-CONFIG_LS_AL3006=y
-CONFIG_LS_STK3171=y
-CONFIG_PROXIMITY_DEVICE=y
-CONFIG_PS_AL3006=y
-CONFIG_PS_STK3171=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_WM831X=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_TEST_POWER=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_MFD_TPS65090=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_REGULATOR_ACT8846=y
-CONFIG_RK30_PWM_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV2659=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_LCDC_RK3188=y
-CONFIG_LCDC0_RK3188=y
-CONFIG_LCD_B101EW05=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_RT5631=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_UHID=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HYM8563=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK3188=y
-# CONFIG_DDR_TEST is not set
-CONFIG_RK_CLOCK_PROC=y
-CONFIG_CLK_SWITCH_TO_32K=y
-CONFIG_MACH_RK3188_U30GT2=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RKWIFI=y
-CONFIG_RKWIFI_26M=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_FT5X0X=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_GS_LIS3DH=y
-CONFIG_LIGHT_SENSOR_DEVICE=y
-CONFIG_LS_US5151=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-CONFIG_GYROSCOPE_DEVICE=y
-CONFIG_GYRO_L3G20D=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_CW2015_BATTERY=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_RK29_WATCHDOG=y
-CONFIG_RK29_FEED_DOG_BY_INTE=y
-CONFIG_RK29_WATCHDOG_ATBOOT=y
-CONFIG_RK29_WATCHDOG_DEFAULT_TIME=5
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_ACT8846=y
-CONFIG_ACT8846_SUPPORT_RESET=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV2659=y
-CONFIG_SOC_CAMERA_GC0308=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_LCD_B101UANO_1920x1200=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL=y
-CONFIG_LCDC_RK3188=y
-CONFIG_LCDC0_RK3188=y
-CONFIG_LCDC1_RK3188=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_CAT66121=y
-CONFIG_HDMI_SOURCE_LCDC1=y
-CONFIG_RK_HDMI_CTL_CODEC=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_ES8323=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_UHID=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HYM8563=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK3188=y
-# CONFIG_DDR_TEST is not set
-CONFIG_RK_CLOCK_PROC=y
-CONFIG_SOC_RK3188M=y
-CONFIG_MACH_RK3188M_F304=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RKWIFI=y
-CONFIG_RKWIFI_26M=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_CT36XX=y
-CONFIG_TOUCHSCREEN_CT36X_PLATFORM_ROCKCHIP=y
-CONFIG_TOUCHSCREEN_CT36X_CHIP_CT365=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_RICOH619_PWRKEY=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_GS_MMA8452=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-# CONFIG_SERIO is not set
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_WM831X=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_BATTERY_RICOH619=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_RICOH619=y
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_MFD_TPS65090=y
-CONFIG_MFD_RK616=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_REGULATOR_RICOH619=y
-CONFIG_REGULATOR_ACT8846=y
-CONFIG_RK30_PWM_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-# CONFIG_SOC_CAMERA_OV3640 is not set
-# CONFIG_SOC_CAMERA_OV5642 is not set
-# CONFIG_SOC_CAMERA_OV5640 is not set
-CONFIG_SOC_CAMERA_NT99252=y
-CONFIG_SOC_CAMERA_NT99340=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL=y
-CONFIG_LCDC_RK3188=y
-CONFIG_LCDC0_RK3188=y
-CONFIG_LCDC1_RK3188=y
-CONFIG_LCD_LD089WU1_MIPI=y
-CONFIG_RK_TRSM=y
-CONFIG_MIPI_DSI=y
-CONFIG_RK616_MIPI_DSI=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_RK616=y
-CONFIG_RK_HDMI_DEBUG=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK_SOC_HDMI_I2S=y
-CONFIG_SND_RK_SOC_RK616=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_UHID=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_TPS65910_RTC=y
-CONFIG_RTC_DRV_RC5T619=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK3188=y
-# CONFIG_DDR_TEST is not set
-CONFIG_SOC_RK3188M=y
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_NETFILTER=y
-# CONFIG_BRIDGE_NETFILTER is not set
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TPROXY=y
-CONFIG_NETFILTER_XT_TARGET_TRACE=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
-CONFIG_NETFILTER_XT_MATCH_SOCKET=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_TARGET_LOG=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE=y
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_PHONET=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_CLS_U32=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM4325=y
-CONFIG_BT_AUTOSLEEP=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_RK=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_RKNAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
-CONFIG_UID_STAT=y
-CONFIG_APANIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_UEVENT=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN_80211=y
-CONFIG_RKWIFI=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOLAC=y
-CONFIG_PPPOPNS=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYRESET=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_XPAD=y
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=y
-CONFIG_TABLET_USB_AIPTEK=y
-CONFIG_TABLET_USB_GTCO=y
-CONFIG_TABLET_USB_HANWANG=y
-CONFIG_TABLET_USB_KBTAB=y
-CONFIG_TABLET_USB_WACOM=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GT8XX=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_KEYCHORD=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_COMPASS_AK8975=y
-CONFIG_GS_MMA8452=y
-CONFIG_GS_LIS3DH=y
-CONFIG_GYRO_L3G4200D=y
-CONFIG_LS_CM3217=y
-CONFIG_SENSOR_DEVICE=y
-CONFIG_GSENSOR_DEVICE=y
-CONFIG_GS_KXTIK=y
-CONFIG_COMPASS_DEVICE=y
-CONFIG_GYROSCOPE_DEVICE=y
-CONFIG_LIGHT_DEVICE=y
-CONFIG_LS_AL3006=y
-CONFIG_LS_STK3171=y
-CONFIG_PROXIMITY_DEVICE=y
-CONFIG_PS_AL3006=y
-CONFIG_PS_STK3171=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_RK29=y
-CONFIG_UART0_RK29=y
-CONFIG_UART0_CTS_RTS_RK29=y
-CONFIG_UART3_RK29=y
-CONFIG_UART3_CTS_RTS_RK29=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C0_CONTROLLER_RK30=y
-CONFIG_I2C1_CONTROLLER_RK30=y
-CONFIG_I2C2_CONTROLLER_RK30=y
-CONFIG_I2C3_CONTROLLER_RK30=y
-CONFIG_I2C4_CONTROLLER_RK30=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_WM831X=y
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-CONFIG_POWER_SUPPLY=y
-CONFIG_TEST_POWER=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_MFD_TPS65090=y
-CONFIG_MFD_RK616=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_WM831X=y
-CONFIG_REGULATOR_ACT8846=y
-CONFIG_RK30_PWM_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV2659=y
-CONFIG_VIDEO_RK29=y
-CONFIG_VIDEO_RK29_CAMMEM_ION=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
-CONFIG_FB_ROCKCHIP=y
-CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL=y
-CONFIG_LCDC_RK3188=y
-CONFIG_LCDC0_RK3188=y
-CONFIG_LCDC1_RK3188=y
-CONFIG_LCD_B101EW05=y
-CONFIG_RK_TRSM=y
-CONFIG_RK616_LVDS=y
-CONFIG_RK_HDMI=y
-CONFIG_HDMI_RK616=y
-CONFIG_RK_HDMI_DEBUG=y
-CONFIG_RGA_RK30=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK_SOC_HDMI_I2S=y
-CONFIG_SND_RK_SOC_RK616=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-CONFIG_UHID=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_ACRUX=y
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=y
-CONFIG_HID_ELECOM=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KEYTOUCH=y
-CONFIG_HID_KYE=y
-CONFIG_HID_UCLOGIC=y
-CONFIG_HID_WALTOP=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LCPOWER=y
-CONFIG_HID_LOGITECH=y
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWII_FF=y
-CONFIG_HID_MAGICMOUSE=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_MULTITOUCH=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_PICOLCD=y
-CONFIG_HID_QUANTA=y
-CONFIG_HID_ROCCAT_ARVO=y
-CONFIG_HID_ROCCAT_KONE=y
-CONFIG_HID_ROCCAT_KONEPLUS=y
-CONFIG_HID_ROCCAT_KOVAPLUS=y
-CONFIG_HID_ROCCAT_PYRA=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_WACOM=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_OPTION=y
-CONFIG_USB_GADGET=y
-CONFIG_USB20_HOST=y
-CONFIG_USB20_OTG=y
-CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_SDMMC_RK29=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_SWITCH=y
-CONFIG_SWITCH_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_WM831X=y
-CONFIG_TPS65910_RTC=y
-CONFIG_STAGING=y
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_LOGGER=y
-CONFIG_ANDROID_TIMED_GPIO=y
-CONFIG_ANDROID_LOW_MEMORY_KILLER=y
-# CONFIG_CMMB is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=y
-# CONFIG_EXT4_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE="root"
-# CONFIG_RD_GZIP is not set
-CONFIG_RD_LZO=y
-CONFIG_INITRAMFS_COMPRESSION_LZO=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_PANIC_TIMEOUT=1
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_ASHMEM=y
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_FORCE_LOAD=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_RK319X=y
-# CONFIG_DDR_FREQ is not set
-# CONFIG_DDR_TEST is not set
-# CONFIG_RK29_LAST_LOG is not set
-CONFIG_RK_DEBUG_UART=0
-CONFIG_MACH_RK3190_FPGA=y
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_FIQ_DEBUGGER=y
-CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
-CONFIG_FIQ_DEBUGGER_CONSOLE=y
-CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_HIGHMEM=y
-CONFIG_COMPACTION=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init debug"
-CONFIG_WAKELOCK=y
-CONFIG_PM_RUNTIME=y
-CONFIG_SUSPEND_TIME=y
-CONFIG_NET=y
-CONFIG_UNIX=y
-# CONFIG_NET_ACTIVITY_STATS is not set
-# CONFIG_WIRELESS is not set
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MISC_DEVICES=y
-CONFIG_INPUT_POLLDEV=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C3_RK30 is not set
-# CONFIG_ADC is not set
-CONFIG_EXPANDED_GPIO_NUM=0
-CONFIG_EXPANDED_GPIO_IRQ_NUM=0
-CONFIG_SPI_FPGA_GPIO_NUM=0
-CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
-# CONFIG_HWMON is not set
-# CONFIG_MFD_SUPPORT is not set
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_SOC_CAMERA=y
-CONFIG_ION=y
-CONFIG_ION_ROCKCHIP=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-# CONFIG_BACKLIGHT_RK29_BL is not set
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_RK29_SOC=y
-CONFIG_SND_RK29_SOC_I2S_2CH=y
-CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_RK1000=y
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_RTC_CLASS=y
-# CONFIG_CMMB is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DETECT_HUNG_TASK=y
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_SCHEDSTATS=y
-CONFIG_TIMER_STATS=y
-CONFIG_SLUB_DEBUG_ON=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_FTRACE is not set
+++ /dev/null
-if ARCH_RK29
-
-config MACH_RK29_2906
- bool "ROCKCHIP RK2906 Feature"
-
-choice
- prompt "Select Board Type"
- depends on ARCH_RK29
- default MACH_RK29SDK
-
-config MACH_RK29SDK
- depends on ARCH_RK29
- bool "ROCKCHIP Board Rk29 For Sdk"
- help
- Support for the ROCKCHIP Board For Rk29 Sdk.
-
-config MACH_RK29SDK_DDR3
- depends on ARCH_RK29
- bool "ROCKCHIP Board Rk29 For DDR3 SDK"
- help
- Support for the ROCKCHIP Board For Rk29 Sdk.
-
-config MACH_RK29_K97
- depends on ARCH_RK29
- bool "ROCKCHIP Board Rk29 For K97"
- help
- Support for the ROCKCHIP Board For Rk29 K97.
-
-config MACH_RK29FIH
- depends on ARCH_RK29
- bool "ROCKCHIP Board Rk29 For FIH"
- help
- Support for the ROCKCHIP Board For Rk29 FIH.
-
-config MACH_RK29_PHONESDK
- depends on ARCH_RK29
- bool "ROCKCHIP Board Rk29 For Phone Sdk"
- help
- Support for the ROCKCHIP Board For Rk29 Phone Sdk.
-
-config MACH_RK29_A22
- depends on ARCH_RK29
- bool "ROCKCHIP Board Rk29 For A22"
- help
- Support for the ROCKCHIP Board For A22.
-
-config MACH_RK29_TD8801_V2
- depends on ARCH_RK29
- bool "ROCKCHIP Board Rk29 For TD8801_v2"
- help
- Support for the ROCKCHIP Board For TD8801_v2.
-
-config MACH_RK29_PHONEPADSDK
- depends on ARCH_RK29
- bool "ROCKCHIP Board Rk29 For Phone Pad Sdk"
- help
- Support for the ROCKCHIP Board For Rk29 Phone Pad Sdk.
-
-config MACH_RK29_PHONE_Z5
- depends on ARCH_RK29
- bool "ROCKCHIP Board Rk29 For Z5"
- help
- Support for the ROCKCHIP Board For Z5.
-
-endchoice
-
-config RK29_MEM_SIZE_M
- int "DDR Memory size (in MB)"
- default 512
-
-config DDR_RECONFIG
- bool "Enable dynamic DDR reconfiguration (EXPERIMENTAL)"
-
-config RK29_JTAG
- bool "Enable JTAG support (debug only)"
- help
- This is an option for SDK board. Always enable JTAG clock,
- but consumes more power.
-
-menu "support for RK29 power manage "
-config RK29_WORKING_POWER_MANAGEMENT
- bool "Support power saving in working"
- default n
- help
- a series of measures to reduce working power
-
-config RK29_CLK_SWITCH_TO_32K
- bool "Support clock switch to 32.768k"
- default n
-
-config RK29_GPIO_SUSPEND
- bool "Support gpio suspend"
- default n
-
-config RK29_NEON_POWERDOMAIN_SET
- bool "Support neon powerdomain on and off"
- default n
-
-config RK29_SPI_INSRAM
- tristate "Support spi control interface"
- depends on REGULATOR_WM831X
- default n
-config RK29_I2C_INSRAM
- tristate "Support i2c control interface"
- depends on REGULATOR_WM831X
- default n
-config RK29_CHARGE_EARLYSUSPEND
- bool "Support charge in low power"
- default n
-config RK29_PWM_INSRAM
- tristate "Support pwm control interface"
- depends on RK29_PWM_REGULATOR
- default y
-endmenu
-
-
-endif
+++ /dev/null
-obj-y += timer.o io.o devices.o verifyID.o iomux.o clock.o rk29-pl330.o dma.o ddr.o memcpy_dma.o reset.o
-obj-y += tests.o memtester.o
-obj-$(CONFIG_PM) += pm.o
-obj-$(CONFIG_CPU_FREQ) += cpufreq.o
-obj-$(CONFIG_DDR_FREQ) += ddrfreq.o
-obj-$(CONFIG_RK29_VPU) += vpu_mem.o
-obj-$(CONFIG_RK29_I2C_INSRAM) += i2c_sram.o
-obj-y += spi_sram.o
-obj-$(CONFIG_RK29_PWM_INSRAM) += pwm_sram.o
-obj-$(CONFIG_MACH_RK29SDK) += board-rk29sdk.o board-rk29sdk-key.o board-rk29sdk-rfkill.o board-rk29sdk-power.o
-obj-$(CONFIG_MACH_RK29SDK_DDR3) += board-rk29-ddr3sdk.o board-rk29sdk-key.o board-rk29sdk-power.o
-obj-$(CONFIG_MACH_RK29_PHONESDK) += board-rk29-phonesdk.o board-rk29-phonesdk-key.o board-rk29-phonesdk-rfkill.o
-obj-$(CONFIG_MACH_RK29FIH) += board-rk29-fih.o board-rk29-fih-key.o board-rk29sdk-rfkill.o board-rk29sdk-power.o
-obj-$(CONFIG_MACH_RK29_A22) += board-rk29-a22.o board-rk29-a22-key.o board-rk29-a22-rfkill.o
-obj-$(CONFIG_MACH_RK29_TD8801_V2) += board-rk29-td8801_v2.o board-rk29-td8801_v2-key.o board-rk29-td8801_v2-rfkill.o
-obj-$(CONFIG_MACH_RK29_PHONEPADSDK) += board-rk29phonepadsdk.o board-rk29phonepadsdk-key.o board-rk29phonepadsdk-rfkill.o board-rk29phonepadsdk-power.o
-obj-$(CONFIG_RK29_CHARGE_EARLYSUSPEND) += rk29_charge_lowpower.o
-obj-$(CONFIG_MACH_RK29_K97) += board-rk29-k97.o board-rk29k97-key.o board-rk29sdk-rfkill.o board-rk29sdk-power.o
-obj-$(CONFIG_MACH_RK29_PHONE_Z5) += board-rk29-z5.o board-rk29-z5-key.o board-rk29-z5-rfkill.o
+++ /dev/null
- zreladdr-y := 0x60408000
-params_phys-y := 0x60088000
-initrd_phys-y := 0x60800000
+++ /dev/null
-#include <mach/key.h>
-#include <mach/gpio.h>
-
-#define EV_ENCALL KEY_F4
-#define EV_MENU KEY_F1
-
-#define PRESS_LEV_LOW 1
-#define PRESS_LEV_HIGH 0
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "menu",
- .code = EV_MENU,
- .gpio = RK29_PIN6_PA0,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .gpio = RK29_PIN6_PA1,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .gpio = RK29_PIN6_PA2,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .gpio = RK29_PIN6_PA3,
- .active_low = PRESS_LEV_LOW,
- },
-
- {
- .desc = "search",
- .code = KEY_SEARCH,
- .gpio = RK29_PIN6_PA4,
- .active_low = PRESS_LEV_LOW,
- },
-
- {
- .desc = "esc",
- .code = KEY_BACK,
- .gpio = RK29_PIN6_PA5,
- .active_low = PRESS_LEV_LOW,
- },
-
- {
- .desc = "sensor",
- .code = KEY_CAMERA,
- .gpio = RK29_PIN6_PA6,
- .active_low = PRESS_LEV_LOW,
- },
-#if 0
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK29_PIN6_PA7,
- .active_low = PRESS_LEV_LOW,
- .wakeup = 1,
- },
-#endif
-#if 0
- {
- .desc = "vol+",
- .code = KEY_VOLUMEDOWN,
- .adc_value = 95,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEUP,
- .adc_value = 249,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "menu",
- .code = EV_MENU,
- .adc_value = 406,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .code_long_press = KEY_F4,
- .adc_value = 561,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_ESC,
- .adc_value = 726,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "adkey6",
- .code = KEY_BACK,
- .code_long_press = EV_ENCALL,
- .adc_value = 899,
- .active_low = PRESS_LEV_LOW,
- },
-#endif
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = -1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
+++ /dev/null
-/*
- * Copyright (C) 2010 ROCKCHIP, Inc.
- * Author: roger_chen <cz@rock-chips.com>
- *
- * This program is the bluetooth device bcm4329's driver,
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/module.h>
-#include <linux/device.h>
-#include <linux/rfkill.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/interrupt.h>
-#include <linux/wakelock.h>
-#include <linux/fs.h>
-#include <asm/uaccess.h>
-#include <mach/gpio.h>
-#include <asm/irq.h>
-#include <mach/iomux.h>
-#include <linux/wakelock.h>
-#include <linux/timer.h>
-#include <mach/board.h>
-#if 0
-#define DBG(x...) printk(KERN_INFO x)
-#else
-#define DBG(x...)
-#endif
-
-#define BT_WAKE_HOST_SUPPORT 1
-
-struct bt_ctrl
-{
- struct rfkill *bt_rfk;
-#if BT_WAKE_HOST_SUPPORT
- struct timer_list tl;
- bool b_HostWake;
- struct wake_lock bt_wakelock;
-#endif
-};
-
-#define BT_GPIO_POWER RK29_PIN5_PD6
-#define IOMUX_BT_GPIO_POWER rk29_mux_api_set(GPIO5D6_SDMMC1PWREN_NAME, GPIO5H_GPIO5D6);
-#define BT_GPIO_RESET RK29_PIN6_PC7
-#define BT_GPIO_WAKE_UP RK29_PIN6_PD0
-#define BT_GPIO_WAKE_UP_HOST RK29_PIN4_PD4
-#define IOMUX_BT_GPIO_WAKE_UP_HOST() rk29_mux_api_set(GPIO4D4_CPUTRACECLK_NAME,GPIO4H_GPIO4D4);
-
-//bt cts paired to uart rts
-#define UART_RTS RK29_PIN2_PA7
-#define IOMUX_UART_RTS_GPIO rk29_mux_api_set(GPIO2A7_UART2RTSN_NAME, GPIO2L_GPIO2A7);
-#define IOMUX_UART_RTS rk29_mux_api_set(GPIO2A7_UART2RTSN_NAME, GPIO2L_UART2_RTS_N);
-
-#define BT_WAKE_LOCK_TIMEOUT 10 //s
-
-static const char bt_name[] = "bcm4329";
-extern int rk29sdk_bt_power_state;
-extern int rk29sdk_wifi_power_state;
-
-struct bt_ctrl gBtCtrl;
-
-#if BT_WAKE_HOST_SUPPORT
-void resetBtHostSleepTimer(void)
-{
- mod_timer(&(gBtCtrl.tl),jiffies + BT_WAKE_LOCK_TIMEOUT*HZ);//ÔÙÖØÐÂÉèÖó¬Ê±Öµ¡£
-}
-
-void btWakeupHostLock(void)
-{
- if(gBtCtrl.b_HostWake == false){
- DBG("*************************Lock\n");
-
- wake_lock(&(gBtCtrl.bt_wakelock));
- gBtCtrl.b_HostWake = true;
- }
-}
-
-void btWakeupHostUnlock(void)
-{
- if(gBtCtrl.b_HostWake == true){
- DBG("*************************UnLock\n");
- wake_unlock(&(gBtCtrl.bt_wakelock)); //ÈÃϵͳ˯Ãß
- gBtCtrl.b_HostWake = false;
- }
-}
-
-static void timer_hostSleep(unsigned long arg)
-{
- DBG("%s---b_HostWake=%d\n",__FUNCTION__,gBtCtrl.b_HostWake);
- btWakeupHostUnlock();
-}
-
-
-#ifdef CONFIG_PM
-static int bcm4329_rfkill_suspend(struct platform_device *pdev, pm_message_t state)
-{
- DBG("%s\n",__FUNCTION__);
-
- //To prevent uart to receive bt data when suspended
- IOMUX_UART_RTS_GPIO;
- gpio_request(UART_RTS, "uart_rts");
- gpio_direction_output(UART_RTS, 0);
- gpio_set_value(UART_RTS, GPIO_HIGH);
-
- return 0;
-}
-
-static int bcm4329_rfkill_resume(struct platform_device *pdev)
-{
- DBG("%s\n",__FUNCTION__);
-
- btWakeupHostLock();
- resetBtHostSleepTimer();
-
- gpio_set_value(UART_RTS, GPIO_LOW);
- IOMUX_UART_RTS;
-
- return 0;
-}
-#else
-#define bcm4329_rfkill_suspend NULL
-#define bcm4329_rfkill_resume NULL
-#endif
-
-static irqreturn_t bcm4329_wake_host_irq(int irq, void *dev)
-{
- DBG("%s\n",__FUNCTION__);
-
- btWakeupHostLock();
- resetBtHostSleepTimer();
- return IRQ_HANDLED;
-}
-#endif
-
-#ifdef CONFIG_BT_HCIBCM4325
-int bcm4325_sleep(int bSleep)
-{
- //printk("*************bt enter sleep***************\n");
- if (bSleep)
- gpio_set_value(BT_GPIO_WAKE_UP, GPIO_LOW); //low represent bt device may enter sleep
- else
- gpio_set_value(BT_GPIO_WAKE_UP, GPIO_HIGH); //high represent bt device must be awake
- //printk("sleep=%d\n",bSleep);
- return 0;
-}
-#endif
-
-static int bcm4329_set_block(void *data, bool blocked)
-{
- DBG("%s---blocked :%d\n", __FUNCTION__, blocked);
-
- IOMUX_BT_GPIO_POWER;
-
- if (false == blocked) {
- gpio_set_value(BT_GPIO_POWER, GPIO_HIGH); /* bt power on */
- gpio_set_value(BT_GPIO_RESET, GPIO_LOW);
- mdelay(200);
- gpio_set_value(BT_GPIO_RESET, GPIO_HIGH); /* bt reset deactive*/
- mdelay(200);
-
-#if BT_WAKE_HOST_SUPPORT
- btWakeupHostLock();
-#endif
- pr_info("bt turn on power\n");
- }
- else {
-#if BT_WAKE_HOST_SUPPORT
- btWakeupHostUnlock();
-#endif
- if (!rk29sdk_wifi_power_state) {
- gpio_set_value(BT_GPIO_POWER, GPIO_LOW); /* bt power off */
- mdelay(20);
- pr_info("bt shut off power\n");
- }else {
- pr_info("bt shouldn't shut off power, wifi is using it!\n");
- }
-
- gpio_set_value(BT_GPIO_RESET, GPIO_LOW); /* bt reset active*/
- mdelay(20);
- }
-
- rk29sdk_bt_power_state = !blocked;
- return 0;
-}
-
-
-static const struct rfkill_ops bcm4329_rfk_ops = {
- .set_block = bcm4329_set_block,
-};
-
-static int __devinit bcm4329_rfkill_probe(struct platform_device *pdev)
-{
- int rc = 0;
- bool default_state = true;
-
- DBG("Enter::%s,line=%d\n",__FUNCTION__,__LINE__);
-
- /* default to bluetooth off */
- bcm4329_set_block(NULL, default_state); /* blocked -> bt off */
-
- gBtCtrl.bt_rfk = rfkill_alloc(bt_name,
- NULL,
- RFKILL_TYPE_BLUETOOTH,
- &bcm4329_rfk_ops,
- NULL);
-
- if (!gBtCtrl.bt_rfk)
- {
- printk("fail to rfkill_allocate************\n");
- return -ENOMEM;
- }
-
- rfkill_set_states(gBtCtrl.bt_rfk, default_state, false);
-
- rc = rfkill_register(gBtCtrl.bt_rfk);
- if (rc)
- {
- printk("failed to rfkill_register,rc=0x%x\n",rc);
- rfkill_destroy(gBtCtrl.bt_rfk);
- }
-
- gpio_request(BT_GPIO_POWER, NULL);
- gpio_request(BT_GPIO_RESET, NULL);
- gpio_request(BT_GPIO_WAKE_UP, NULL);
-
-#if BT_WAKE_HOST_SUPPORT
- init_timer(&(gBtCtrl.tl));
- gBtCtrl.tl.expires = jiffies + BT_WAKE_LOCK_TIMEOUT*HZ;
- gBtCtrl.tl.function = timer_hostSleep;
- add_timer(&(gBtCtrl.tl));
- gBtCtrl.b_HostWake = false;
-
- wake_lock_init(&(gBtCtrl.bt_wakelock), WAKE_LOCK_SUSPEND, "bt_wake");
-
- rc = gpio_request(BT_GPIO_WAKE_UP_HOST, "bt_wake");
- if (rc) {
- printk("%s:failed to request RAHO_BT_WAKE_UP_HOST\n",__FUNCTION__);
- }
-
- IOMUX_BT_GPIO_WAKE_UP_HOST();
- gpio_pull_updown(BT_GPIO_WAKE_UP_HOST,GPIOPullUp);
- rc = request_irq(gpio_to_irq(BT_GPIO_WAKE_UP_HOST),bcm4329_wake_host_irq,IRQF_TRIGGER_FALLING,NULL,NULL);
- if(rc)
- {
- printk("%s:failed to request RAHO_BT_WAKE_UP_HOST irq\n",__FUNCTION__);
- gpio_free(BT_GPIO_WAKE_UP_HOST);
- }
- enable_irq_wake(gpio_to_irq(BT_GPIO_WAKE_UP_HOST)); // so RAHO_BT_WAKE_UP_HOST can wake up system
-
- printk(KERN_INFO "bcm4329 module has been initialized,rc=0x%x\n",rc);
- #endif
-
- return rc;
-
-
-}
-
-
-static int __devexit bcm4329_rfkill_remove(struct platform_device *pdev)
-{
- if (gBtCtrl.bt_rfk)
- rfkill_unregister(gBtCtrl.bt_rfk);
- gBtCtrl.bt_rfk = NULL;
-#if BT_WAKE_HOST_SUPPORT
- del_timer(&(gBtCtrl.tl));//ɾµô¶¨Ê±Æ÷
- btWakeupHostUnlock();
- wake_lock_destroy(&(gBtCtrl.bt_wakelock));
-#endif
- platform_set_drvdata(pdev, NULL);
-
- DBG("Enter::%s,line=%d\n",__FUNCTION__,__LINE__);
- return 0;
-}
-
-static struct platform_driver bcm4329_rfkill_driver = {
- .probe = bcm4329_rfkill_probe,
- .remove = __devexit_p(bcm4329_rfkill_remove),
- .driver = {
- .name = "rk29sdk_rfkill",
- .owner = THIS_MODULE,
- },
-#if BT_WAKE_HOST_SUPPORT
- .suspend = bcm4329_rfkill_suspend,
- .resume = bcm4329_rfkill_resume,
-#endif
-};
-
-/*
- * Module initialization
- */
-static int __init bcm4329_mod_init(void)
-{
- int ret;
- DBG("Enter::%s,line=%d\n",__FUNCTION__,__LINE__);
- ret = platform_driver_register(&bcm4329_rfkill_driver);
- printk("ret=0x%x\n", ret);
- return ret;
-}
-
-static void __exit bcm4329_mod_exit(void)
-{
- platform_driver_unregister(&bcm4329_rfkill_driver);
-}
-
-module_init(bcm4329_mod_init);
-module_exit(bcm4329_mod_exit);
-MODULE_DESCRIPTION("bcm4329 Bluetooth driver");
-MODULE_AUTHOR("roger_chen cz@rock-chips.com");
-MODULE_LICENSE("GPL");
-
+++ /dev/null
-/* arch/arm/mach-rk29/board-rk29-phonesdk.c
- *
- * Copyright (C) 2010 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/android_pmem.h>
-#include <linux/usb/android_composite.h>
-#include <linux/mpu.h>
-#include <linux/mpu3050.h>
-#include <linux/ion.h>
-
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/iomux.h>
-#include <mach/gpio.h>
-#include <mach/irqs.h>
-#include <mach/rk29_iomap.h>
-#include <mach/board.h>
-#include <mach/rk29_nand.h>
-#include <mach/rk29_camera.h> /* ddl@rock-chips.com : camera support */
-#include <media/soc_camera.h> /* ddl@rock-chips.com : camera support */
-#include <mach/vpu_mem.h>
-#include <mach/sram.h>
-#include <mach/ddr.h>
-
-#include <linux/regulator/rk29-pwm-regulator.h>
-#include <linux/regulator/machine.h>
-#include <linux/mfd/wm831x/pdata.h>
-#include <linux/mfd/wm831x/core.h>
-#include <linux/mfd/wm831x/gpio.h>
-#include <linux/mfd/wm8994/pdata.h>
-#include <linux/mfd/wm8994/registers.h>
-#include <linux/regulator/fixed.h>
-
-#include <linux/mtd/nand.h>
-#include <linux/mtd/partitions.h>
-#include <linux/leds.h>
-#include <linux/i2c-gpio.h>
-
-#include "devices.h"
-
-#if defined(CONFIG_MTK23D)
-#include <linux/mtk23d.h>
-#endif
-
-#include "../../../drivers/headset_observe/rk_headset.h"
-#include "../../../drivers/staging/android/timed_gpio.h"
-#include "../../../drivers/input/magnetometer/mmc328x.h"
-#include "../../../drivers/video/backlight/aw9364_bl.h"
-/*set touchscreen different type header*/
-#if defined(CONFIG_TOUCHSCREEN_XPT2046_NORMAL_SPI)
-#include "../../../drivers/input/touchscreen/xpt2046_ts.h"
-#elif defined(CONFIG_TOUCHSCREEN_XPT2046_TSLIB_SPI)
-#include "../../../drivers/input/touchscreen/xpt2046_tslib_ts.h"
-#elif defined(CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI)
-#include "../../../drivers/input/touchscreen/xpt2046_cbn_ts.h"
-#endif
-
-#include "../../../drivers/misc/gps/rk29_gps.h"
-#include "../../../drivers/tty/serial/sc8800.h"
-#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Begin ------------------------*/
-#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_MT9T111 /* back camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_0 0x78
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 1
-#define CONFIG_SENSOR_ORIENTATION_0 90
-#define CONFIG_SENSOR_POWER_PIN_0 RK29_PIN5_PA0 //INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 RK29_PIN6_PB7
-#define CONFIG_SENSOR_FALSH_PIN_0 RK29_PIN5_PD2 // RK29_PIN1_PA5
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_H //RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_H
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 8
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 8
-#define CONFIG_SENSOR_CIF_FPS_FIXED_0 8
-#define CONFIG_SENSOR_VGA_FPS_FIXED_0 8
-#define CONFIG_SENSOR_480P_FPS_FIXED_0 8
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 8
-#define CONFIG_SENSOR_720P_FPS_FIXED_0 8
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_GC0309 /* front camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_1 0x42
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 1
-#define CONFIG_SENSOR_ORIENTATION_1 0
-#define CONFIG_SENSOR_POWER_PIN_1 RK29_PIN5_PA0 //INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_1 RK29_PIN5_PD7
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_H
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 18
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 18
-#define CONFIG_SENSOR_CIF_FPS_FIXED_1 18
-#define CONFIG_SENSOR_VGA_FPS_FIXED_1 18
-#define CONFIG_SENSOR_480P_FPS_FIXED_1 18
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 18
-#define CONFIG_SENSOR_720P_FPS_FIXED_1 18
-/*---------------- Camera Sensor Configuration End------------------------*/
-#include "../../../drivers/media/video/rk29_camera.c"
-#endif
-
-
-/* Set memory size of pmem */
-#ifdef CONFIG_RK29_MEM_SIZE_M
-#define SDRAM_SIZE (CONFIG_RK29_MEM_SIZE_M * SZ_1M)
-#else
-#define SDRAM_SIZE SZ_512M
-#endif
-#define PMEM_GPU_SIZE SZ_16M
-#define PMEM_UI_SIZE SZ_32M
-#define PMEM_VPU_SIZE SZ_64M
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-#ifdef CONFIG_VIDEO_RK29_WORK_IPP
-#define MEM_CAMIPP_SIZE SZ_4M
-#else
-#define MEM_CAMIPP_SIZE 0
-#endif
-#define MEM_FB_SIZE (3*SZ_2M)
-#ifdef CONFIG_FB_WORK_IPP
-#ifdef CONFIG_FB_SCALING_OSD_1080P
-#define MEM_FBIPP_SIZE SZ_16M //1920 x 1080 x 2 x 2 //RGB565 = x2;RGB888 = x4
-#else
-#define MEM_FBIPP_SIZE SZ_8M //1920 x 1080 x 2 x 2 //RGB565 = x2;RGB888 = x4
-#endif
-#else
-#define MEM_FBIPP_SIZE 0
-#endif
-#if SDRAM_SIZE > SZ_512M
-#define PMEM_GPU_BASE (RK29_SDRAM_PHYS + SZ_512M - PMEM_GPU_SIZE)
-#else
-#define PMEM_GPU_BASE (RK29_SDRAM_PHYS + SDRAM_SIZE - PMEM_GPU_SIZE)
-#endif
-#define PMEM_UI_BASE (PMEM_GPU_BASE - PMEM_UI_SIZE)
-#define PMEM_VPU_BASE (PMEM_UI_BASE - PMEM_VPU_SIZE)
-#define PMEM_CAM_BASE (PMEM_VPU_BASE - PMEM_CAM_SIZE)
-#define MEM_CAMIPP_BASE (PMEM_CAM_BASE - MEM_CAMIPP_SIZE)
-#define MEM_FB_BASE (MEM_CAMIPP_BASE - MEM_FB_SIZE)
-#define MEM_FBIPP_BASE (MEM_FB_BASE - MEM_FBIPP_SIZE)
-#define LINUX_SIZE (MEM_FBIPP_BASE - RK29_SDRAM_PHYS)
-
-#define PREALLOC_WLAN_SEC_NUM 4
-#define PREALLOC_WLAN_BUF_NUM 160
-#define PREALLOC_WLAN_SECTION_HEADER 24
-
-#define WLAN_SECTION_SIZE_0 (PREALLOC_WLAN_BUF_NUM * 128)
-#define WLAN_SECTION_SIZE_1 (PREALLOC_WLAN_BUF_NUM * 128)
-#define WLAN_SECTION_SIZE_2 (PREALLOC_WLAN_BUF_NUM * 512)
-#define WLAN_SECTION_SIZE_3 (PREALLOC_WLAN_BUF_NUM * 1024)
-
-#define WLAN_SKB_BUF_NUM 16
-#define UNLOCK_SECURITY_KEY ~(0x1<<5)
-#define LOCK_SECURITY_KEY 0x00
-
-static struct sk_buff *wlan_static_skb[WLAN_SKB_BUF_NUM];
-
-struct wifi_mem_prealloc {
- void *mem_ptr;
- unsigned long size;
-};
-
-extern struct sys_timer rk29_timer;
-
-static int rk29_nand_io_init(void)
-{
- return 0;
-}
-
-struct rk29_nand_platform_data rk29_nand_data = {
- .width = 1, /* data bus width in bytes */
- .hw_ecc = 1, /* hw ecc 0: soft ecc */
- .num_flash = 1,
- .io_init = rk29_nand_io_init,
-};
-
-#ifdef CONFIG_FB_RK29
-/*****************************************************************************************
- * lcd devices
- * author: zyw@rock-chips.com
- *****************************************************************************************/
-//#ifdef CONFIG_LCD_TD043MGEA1
-
-#define LCD_TXD_PIN RK29_PIN2_PC2
-#define LCD_CLK_PIN RK29_PIN2_PC0
-#define LCD_CS_PIN RK29_PIN1_PA4
-
-/*****************************************************************************************
-* frame buffer devices
-* author: zyw@rock-chips.com
-*****************************************************************************************/
-#define FB_ID 0
-#define FB_DISPLAY_ON_PIN INVALID_GPIO//RK29_PIN6_PD0
-#define FB_LCD_STANDBY_PIN INVALID_GPIO//RK29_PIN6_PD1
-#define FB_LCD_CABC_EN_PIN INVALID_GPIO//RK29_PIN6_PD2
-#define FB_MCU_FMK_PIN INVALID_GPIO
-
-#define FB_DISPLAY_ON_VALUE GPIO_HIGH
-#define FB_LCD_STANDBY_VALUE GPIO_HIGH
-
-//#endif
-static int rk29_lcd_io_init(void)
-{
- int ret = 0;
- //printk("rk29_lcd_io_init\n");
- //ret = gpio_request(LCD_RXD_PIN, NULL);
- ret = gpio_request(LCD_TXD_PIN, NULL);
- ret = gpio_request(LCD_CLK_PIN, NULL);
- ret = gpio_request(LCD_CS_PIN, NULL);
-
-
- //rk29_mux_api_set(GPIO2C7_SPI1RXD_NAME,GPIO2H_GPIO2C7);
- rk29_mux_api_set(GPIO2C2_SPI0TXD_NAME,GPIO2H_GPIO2C2);
- rk29_mux_api_set(GPIO1A4_EMMCWRITEPRT_SPI0CS1_NAME,GPIO1L_GPIO1A4);
- rk29_mux_api_set(GPIO2C0_SPI0CLK_NAME,GPIO2H_GPIO2C0);
-
-
- gpio_request(RK29_PIN6_PC6, NULL);
- gpio_direction_output(RK29_PIN6_PC6, 1);
- gpio_direction_output(RK29_PIN6_PC6, 0);
- usleep_range(5*1000, 5*1000);
- gpio_set_value(RK29_PIN6_PC6, 1);
- usleep_range(50*1000, 50*1000);
- gpio_free(RK29_PIN6_PC6);
-
- return ret;
-}
-
-#if defined (CONFIG_RK29_WORKING_POWER_MANAGEMENT)
-static int rk29_lcd_io_deinit(void)
-{
- int ret = 0;
-
- gpio_direction_output(LCD_TXD_PIN, 1);
- gpio_direction_output(LCD_CLK_PIN, 1);
-
- gpio_free(LCD_CS_PIN);
- gpio_free(LCD_CLK_PIN);
- gpio_free(LCD_TXD_PIN);
-
- return ret;
-}
-#else
-static int rk29_lcd_io_deinit(void)
-{
- int ret = 0;
- //printk("rk29_lcd_io_deinit\n");
- gpio_free(LCD_CS_PIN);
- gpio_free(LCD_CLK_PIN);
- gpio_free(LCD_TXD_PIN);
- //gpio_free(LCD_RXD_PIN);
-
- rk29_mux_api_set(GPIO2C2_SPI0TXD_NAME,GPIO2H_SPI0_TXD);
- rk29_mux_api_set(GPIO1A4_EMMCWRITEPRT_SPI0CS1_NAME,GPIO1L_SPI0_CSN1);
- rk29_mux_api_set(GPIO2C0_SPI0CLK_NAME,GPIO2H_SPI0_CLK);
-
- return ret;
-}
-#endif
-
-
-static struct rk29lcd_info rk29_lcd_info = {
- .txd_pin = LCD_TXD_PIN,
- .clk_pin = LCD_CLK_PIN,
- .cs_pin = LCD_CS_PIN,
- .io_init = rk29_lcd_io_init,
- .io_deinit = rk29_lcd_io_deinit,
-};
-
-int rk29_fb_io_enable(void)
-{
- if(FB_DISPLAY_ON_PIN != INVALID_GPIO)
- {
- gpio_direction_output(FB_DISPLAY_ON_PIN, 0);
- gpio_set_value(FB_DISPLAY_ON_PIN, FB_DISPLAY_ON_VALUE);
- }
- if(FB_LCD_STANDBY_PIN != INVALID_GPIO)
- {
- gpio_direction_output(FB_LCD_STANDBY_PIN, 0);
- gpio_set_value(FB_LCD_STANDBY_PIN, FB_LCD_STANDBY_VALUE);
- }
- return 0;
-}
-
-int rk29_fb_io_disable(void)
-{
- if(FB_DISPLAY_ON_PIN != INVALID_GPIO)
- {
- gpio_direction_output(FB_DISPLAY_ON_PIN, 0);
- gpio_set_value(FB_DISPLAY_ON_PIN, !FB_DISPLAY_ON_VALUE);
- }
- if(FB_LCD_STANDBY_PIN != INVALID_GPIO)
- {
- gpio_direction_output(FB_LCD_STANDBY_PIN, 0);
- gpio_set_value(FB_LCD_STANDBY_PIN, !FB_LCD_STANDBY_VALUE);
- }
- return 0;
-}
-
-static int rk29_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
- if(fb_setting->mcu_fmk_en && (FB_MCU_FMK_PIN != INVALID_GPIO))
- {
- ret = gpio_request(FB_MCU_FMK_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(FB_MCU_FMK_PIN);
- printk(">>>>>> FB_MCU_FMK_PIN gpio_request err \n ");
- }
- gpio_direction_input(FB_MCU_FMK_PIN);
- }
- if(fb_setting->disp_on_en && (FB_DISPLAY_ON_PIN != INVALID_GPIO))
- {
- ret = gpio_request(FB_DISPLAY_ON_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(FB_DISPLAY_ON_PIN);
- printk(">>>>>> FB_DISPLAY_ON_PIN gpio_request err \n ");
- }
- }
-
- if(fb_setting->disp_on_en && (FB_LCD_STANDBY_PIN != INVALID_GPIO))
- {
- ret = gpio_request(FB_LCD_STANDBY_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(FB_LCD_STANDBY_PIN);
- printk(">>>>>> FB_LCD_STANDBY_PIN gpio_request err \n ");
- }
- }
-
- if(FB_LCD_CABC_EN_PIN != INVALID_GPIO)
- {
- ret = gpio_request(FB_LCD_CABC_EN_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(FB_LCD_CABC_EN_PIN);
- printk(">>>>>> FB_LCD_CABC_EN_PIN gpio_request err \n ");
- }
- gpio_direction_output(FB_LCD_CABC_EN_PIN, 0);
- gpio_set_value(FB_LCD_CABC_EN_PIN, GPIO_LOW);
- }
- rk29_fb_io_enable(); //enable it
-
- return ret;
-}
-
-static struct rk29fb_info rk29_fb_info = {
- .fb_id = FB_ID,
- .mcu_fmk_pin = FB_MCU_FMK_PIN,
- .lcd_info = &rk29_lcd_info,
- .io_init = rk29_fb_io_init,
- .io_enable = rk29_fb_io_enable,
- .io_disable = rk29_fb_io_disable,
-};
-
-/* rk29 fb resource */
-static struct resource rk29_fb_resource[] = {
- [0] = {
- .name = "lcdc reg",
- .start = RK29_LCDC_PHYS,
- .end = RK29_LCDC_PHYS + RK29_LCDC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc irq",
- .start = IRQ_LCDC,
- .end = IRQ_LCDC,
- .flags = IORESOURCE_IRQ,
- },
- [2] = {
- .name = "win1 buf",
- .start = MEM_FB_BASE,
- .end = MEM_FB_BASE + MEM_FB_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- #ifdef CONFIG_FB_WORK_IPP
- [3] = {
- .name = "win1 ipp buf",
- .start = MEM_FBIPP_BASE,
- .end = MEM_FBIPP_BASE + MEM_FBIPP_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- #endif
-};
-
-/*platform_device*/
-struct platform_device rk29_device_fb = {
- .name = "rk29-fb",
- .id = 4,
- .num_resources = ARRAY_SIZE(rk29_fb_resource),
- .resource = rk29_fb_resource,
- .dev = {
- .platform_data = &rk29_fb_info,
- }
-};
-
-struct platform_device rk29_device_dma_cpy = {
- .name = "dma_memcpy",
- .id = 4,
-
-};
-
-#endif
-
-static struct android_pmem_platform_data android_pmem_pdata = {
- .name = "pmem",
- .start = PMEM_UI_BASE,
- .size = PMEM_UI_SIZE,
- .no_allocator = 1,
- .cached = 1,
-};
-
-static struct platform_device android_pmem_device = {
- .name = "android_pmem",
- .id = 0,
- .dev = {
- .platform_data = &android_pmem_pdata,
- },
-};
-
-
-
-static struct vpu_mem_platform_data vpu_mem_pdata = {
- .name = "vpu_mem",
- .start = PMEM_VPU_BASE,
- .size = PMEM_VPU_SIZE,
- .cached = 1,
-};
-
-static struct platform_device rk29_vpu_mem_device = {
- .name = "vpu_mem",
- .id = 2,
- .dev = {
- .platform_data = &vpu_mem_pdata,
- },
-};
-
-static struct platform_device rk29_v4l2_output_devce = {
- .name = "rk29_vout",
-};
-
-/*HANNSTAR_P1003 touch*/
-
-#ifdef CONFIG_ION
-static struct ion_platform_data rk29_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = 0,
- .name = "ui",
- .base = PMEM_UI_BASE,
- .size = PMEM_UI_SIZE,
- }
- },
-};
-
-static struct platform_device rk29_ion_device = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk29_ion_pdata,
- },
-};
-#endif
-#if defined (CONFIG_HANNSTAR_P1003)
-#define TOUCH_RESET_PIN RK29_PIN6_PC3
-#define TOUCH_INT_PIN RK29_PIN4_PD5
-
-int p1003_init_platform_hw(void)
-{
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_pull_updown(TOUCH_INT_PIN, 1);
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
-
- return 0;
-}
-
-
-struct p1003_platform_data p1003_info = {
- .model= 1003,
- .init_platform_hw= p1003_init_platform_hw,
-
-};
-#endif
-
-
-#if defined(CONFIG_TOUCHSCREEN_ILI2102_IIC)
-#include "../../../drivers/input/touchscreen/ili2102_ts.h"
-#define ili2102_GPIO_INT RK29_PIN4_PD5
-#define ili2102_GPIO_RESET RK29_PIN6_PC3
-static struct ili2102_platform_data ili2102_info = {
- .model = 2102,
- .swap_xy = 0,
- .x_min = 0,
- .x_max = 480,
- .y_min = 0,
- .y_max = 800,
- .gpio_reset = ili2102_GPIO_RESET,
- .gpio_reset_active_low = 1,
- .gpio_pendown = ili2102_GPIO_INT,
- .pendown_iomux_name = GPIO4D5_CPUTRACECTL_NAME,
- .resetpin_iomux_name = "",
- .pendown_iomux_mode = GPIO4H_GPIO4D5,
- .resetpin_iomux_mode = 0,
-};
-#endif
-
-
-#if defined (CONFIG_EETI_EGALAX)
-#define TOUCH_RESET_PIN RK29_PIN6_PC3
-#define TOUCH_INT_PIN RK29_PIN4_PD5
-
-static int EETI_EGALAX_init_platform_hw(void)
-{
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_pull_updown(TOUCH_INT_PIN, 1);
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
-
- return 0;
-}
-
-
-static struct eeti_egalax_platform_data eeti_egalax_info = {
- .model= 1003,
- .init_platform_hw= EETI_EGALAX_init_platform_hw,
-
-};
-#endif
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN RK29_PIN6_PC4
-
-static int mma8452_init_platform_hw(void)
-{
-
- if(gpio_request(MMA8452_INT_PIN,NULL) != 0){
- gpio_free(MMA8452_INT_PIN);
- printk("mma8452_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_pull_updown(MMA8452_INT_PIN, 1);
- return 0;
-}
-
-
-static struct gsensor_platform_data mma8452_info = {
- .model= 8452,
- .swap_xy = 0,
- .swap_xyz = 1,
- .orientation = {1,0,0,
- 0,0,-1,
- 0,-1,0},
- .init_platform_hw= mma8452_init_platform_hw,
-
-};
-#endif
-
-#if defined(CONFIG_GPIO_WM831X)
-struct rk29_gpio_expander_info wm831x_gpio_settinginfo[] = {
- {
- .gpio_num =WM831X_P01,// tp3
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
-
- {
- .gpio_num =WM831X_P02,//tp4
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P03,//tp2
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P04,//tp1
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P05,//tp1
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P06,//tp1
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P07,//tp1
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P08,//tp1
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P09,//tp1
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P10,//tp1
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P11,//tp1
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P12,
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
-};
-
-#endif
-
-
-
-#if defined(CONFIG_MFD_WM831X)
-static struct wm831x *gWm831x;
-int wm831x_pre_init(struct wm831x *parm)
-{
- int ret;
- printk("%s\n", __FUNCTION__);
- gWm831x = parm;
- //ILIM = 900ma
- ret = wm831x_reg_read(parm, WM831X_POWER_STATE) & 0xffff;
- wm831x_reg_write(parm, WM831X_POWER_STATE, (ret&0xfff8) | 0x04);
-
- //BATT_FET_ENA = 1
- wm831x_reg_write(parm,WM831X_SECURITY_KEY,0x9716); // unlock security key
- wm831x_set_bits(parm, WM831X_RESET_CONTROL,0x1000,0x1000);
- ret = wm831x_reg_read(parm, WM831X_RESET_CONTROL) & 0xffff&UNLOCK_SECURITY_KEY;// enternal reset active in sleep
- printk("%s:WM831X_RESET_CONTROL=0x%x\n",__FUNCTION__,ret);
- wm831x_reg_write(parm, WM831X_RESET_CONTROL, ret);
-
-
- wm831x_reg_write(parm,WM831X_SECURITY_KEY,LOCK_SECURITY_KEY); // lock securit
-
-#if 0
- wm831x_set_bits(parm, WM831X_LDO_ENABLE, (1 << 3), 0);
- wm831x_set_bits(parm, WM831X_LDO_ENABLE, (1 << 7), 0);
- printk("%s:disable ldo4 and ldo8 because they are enabled in uboot\n",__FUNCTION__);
-#endif
- return 0;
-}
-int wm831x_post_init(struct wm831x *parm)
-{
- struct regulator *dcdc;
- struct regulator *ldo;
-
-
- dcdc = regulator_get(NULL, "dcdc3"); // 1th IO
- regulator_set_voltage(dcdc,3000000,3000000);
- regulator_set_suspend_voltage(dcdc, 2800000);
- regulator_enable(dcdc);
- printk("%s set dcdc3=%dmV end\n", __FUNCTION__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo10"); // 1th modem IO
- regulator_set_voltage(ldo,3000000,3000000);
- regulator_set_suspend_voltage(ldo,3000000);
- regulator_enable(ldo);
- printk("%s set ldo10=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- dcdc = regulator_get(NULL, "dcdc2"); // 2th CORE
- regulator_set_voltage(dcdc,1300000,1300000);
- regulator_set_suspend_voltage(dcdc,1000000);
- regulator_enable(dcdc);
- printk("%s set dcdc2=%dmV end\n", __FUNCTION__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- dcdc = regulator_get(NULL, "dcdc1"); // 3th ddr
- regulator_set_voltage(dcdc,1800000,1800000);
- regulator_set_suspend_voltage(dcdc,1800000);
- regulator_enable(dcdc);
- printk("%s set dcdc1=%dmV end\n", __FUNCTION__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo1"); // 3th nand
- regulator_set_voltage(ldo,1800000,1800000);
- regulator_set_suspend_voltage(ldo,1800000);
- regulator_enable(ldo);
- printk("%s set ldo1=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo4"); // 4th usb
- regulator_set_voltage(ldo,2500000,2500000);
- regulator_set_suspend_voltage(ldo,0000000);
- regulator_enable(ldo);
- printk("%s set ldo4=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo7"); // 5th usb
- regulator_set_voltage(ldo,3300000,3300000);
- regulator_set_suspend_voltage(ldo,3300000);
- regulator_enable(ldo);
- printk("%s set ldo7=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- dcdc = regulator_get(NULL, "dcdc4"); // backlight
- regulator_set_voltage(dcdc,20000000,20000000);
- regulator_set_suspend_voltage(dcdc, 20000000);
- regulator_enable(dcdc);
- printk("%s set dcdc4=%dmV end\n", __FUNCTION__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-#if 1
-
- ldo = regulator_get(NULL, "ldo2"); //lcd
- regulator_set_voltage(ldo,3000000,3000000);
- regulator_set_suspend_voltage(ldo,3000000);
- regulator_enable(ldo);
- printk("%s set ldo2=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo3"); //sram
- regulator_set_voltage(ldo,1800000,1800000);
- regulator_set_suspend_voltage(ldo,1800000);
- regulator_enable(ldo);
- printk("%s set ldo3=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo5"); //tf
- regulator_set_voltage(ldo,3000000,3000000);
- regulator_set_suspend_voltage(ldo,3000000);
- regulator_enable(ldo);
- printk("%s set ldo5=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo6"); //camera
- regulator_set_voltage(ldo,1800000,1800000);
- regulator_set_suspend_voltage(ldo,1800000);
- regulator_enable(ldo);
- printk("%s set ldo6=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo8"); //tp
- regulator_set_voltage(ldo,3000000,3000000);
- regulator_set_suspend_voltage(ldo,3000000);
- regulator_enable(ldo);
- printk("%s set ldo8=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo9"); //cmmb
- regulator_set_voltage(ldo,3000000,3000000);
- regulator_set_suspend_voltage(ldo,3000000);
- regulator_enable(ldo);
- printk("%s set ldo9=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
-
-#endif
-
- ldo = regulator_get(NULL, "ldo11");
- //regulator_enable(ldo);
- printk("%s set ldo11=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
-
-
- return 0;
-}
-
-extern void wm831x_enter_sleep(void);
-extern void wm831x_exit_sleep(void);
-
-void pmu_wm831x_set_suspend_voltage(void)
-{
-
-}
-EXPORT_SYMBOL_GPL(pmu_wm831x_set_suspend_voltage);
-
-void pmu_wm831x_set_resume_voltage(void)
-{
-
-}
-EXPORT_SYMBOL_GPL(pmu_wm831x_set_resume_voltage);
-
-int wm831x_last_deinit(struct wm831x *parm)
-{
- struct regulator* ldo;
-
- printk("%s\n", __FUNCTION__);
-
- ldo = regulator_get(NULL, "ldo1");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo2");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo3");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo4");
- //regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo5");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo6");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo7");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo8");
- //regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo9");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo10");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- return 0;
-}
-
-struct wm831x_backlight_pdata wm831x_backlight_platdata = {
- .isink = 1, /** ISINK to use, 1 or 2 */
- .max_uA = 19484, /** Maximum current to allow */
-};
-
-struct wm831x_backup_pdata wm831x_backup_platdata = {
- .charger_enable = 1,
- .no_constant_voltage = 0, /** Disable constant voltage charging */
- .vlim = 3100, /** Voltage limit in milivolts */
- .ilim = 300, /** Current limit in microamps */
-};
-
-struct wm831x_battery_pdata wm831x_battery_platdata = {
- .enable = 1, /** Enable charging */
- .fast_enable = 1, /** Enable fast charging */
- .off_mask = 1, /** Mask OFF while charging */
- .trickle_ilim = 200, /** Trickle charge current limit, in mA */
- .vsel = 4200, /** Target voltage, in mV */
- .eoc_iterm = 50, /** End of trickle charge current, in mA */
- .fast_ilim = 600, /** Fast charge current limit, in mA */
- .timeout = 480, /** Charge cycle timeout, in minutes */
- .syslo = 3300, /* syslo threshold, in mV*/
- .sysok = 3500, /* sysko threshold, in mV*/
-};
-
-struct wm831x_status_pdata wm831x_status_platdata[WM831X_MAX_STATUS] = {
- {
- .default_src = WM831X_STATUS_OTP,
- .name = "wm831x_status0",
- .default_trigger = "wm831x_otp",
- },
- {
- .default_src = WM831X_STATUS_POWER,
- .name = "wm831x_status1",
- .default_trigger = "wm831x_power",
- },
-};
-
-
-static struct regulator_consumer_supply dcdc1_consumers[] = {
- {
- .supply = "dcdc1",
- }
-};
-static struct regulator_consumer_supply dcdc2_consumers[] = {
- {
- .supply = "dcdc2",
- },
- {
- .supply = "vcore",
- }
-};
-static struct regulator_consumer_supply dcdc3_consumers[] = {
- {
- .supply = "dcdc3",
- }
-};
-static struct regulator_consumer_supply dcdc4_consumers[] = {
- {
- .supply = "dcdc4",
- }
-};
-static struct regulator_consumer_supply epe1_consumers[] = {
- {
- .supply = "epe1",
- }
-};
-static struct regulator_consumer_supply epe2_consumers[] = {
- {
- .supply = "epe2",
- }
-};
-static struct regulator_consumer_supply ldo1_consumers[] = {
- {
- .supply = "ldo1",
- }
-};
-static struct regulator_consumer_supply ldo2_consumers[] = {
- {
- .supply = "ldo2",
- }
-};
-static struct regulator_consumer_supply ldo3_consumers[] = {
- {
- .supply = "ldo3",
- }
-};
-static struct regulator_consumer_supply ldo4_consumers[] = {
- {
- .supply = "ldo4",
- }
-};
-static struct regulator_consumer_supply ldo5_consumers[] = {
- {
- .supply = "ldo5",
- }
-};
-static struct regulator_consumer_supply ldo6_consumers[] = {
- {
- .supply = "ldo6",
- }
-};
-static struct regulator_consumer_supply ldo7_consumers[] = {
- {
- .supply = "ldo7",
- }
-};
-static struct regulator_consumer_supply ldo8_consumers[] = {
- {
- .supply = "ldo8",
- }
-};
-static struct regulator_consumer_supply ldo9_consumers[] = {
- {
- .supply = "ldo9",
- }
-};
-static struct regulator_consumer_supply ldo10_consumers[] = {
- {
- .supply = "ldo10",
- }
-};
-static struct regulator_consumer_supply ldo11_consumers[] = {
- {
- .supply = "ldo11",
- }
-};
-static struct regulator_consumer_supply isink1_consumers[] = {
- {
- .supply = "isink1",
- }
-};
-static struct regulator_consumer_supply isink2_consumers[] = {
- {
- .supply = "isink2",
- }
-};
-
-struct regulator_init_data wm831x_regulator_init_dcdc[WM831X_MAX_DCDC] = {
- {
- .constraints = {
- .name = "DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000,//0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(dcdc1_consumers),
- .consumer_supplies = dcdc1_consumers,
- },
- {
- .constraints = {
- .name = "DCDC2",
- .min_uV = 600000,
- .max_uV = 1800000,//0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(dcdc2_consumers),
- .consumer_supplies = dcdc2_consumers,
- },
- {
- .constraints = {
- .name = "DCDC3",
- .min_uV = 850000,
- .max_uV = 3400000,//0.85-3.4V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(dcdc3_consumers),
- .consumer_supplies = dcdc3_consumers,
- },
- {
- .constraints = {
- .name = "DCDC4",
- .min_uV = 00000000,
- .max_uV = 30000000,//30V/40mA
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(dcdc4_consumers),
- .consumer_supplies = dcdc4_consumers,
- },
-
-};
-struct regulator_init_data wm831x_regulator_init_epe[WM831X_MAX_EPE] = {
- {
- .constraints = {
- .name = "EPE1",
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(epe1_consumers),
- .consumer_supplies = epe1_consumers,
- },
- {
- .constraints = {
- .name = "EPE2",
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(epe2_consumers),
- .consumer_supplies = epe2_consumers,
- },
-};
-
-struct regulator_init_data wm831x_regulator_init_ldo[WM831X_MAX_LDO] = {
- {
- .constraints = {
- .name = "LDO1",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo1_consumers),
- .consumer_supplies = ldo1_consumers,
- },
- {
- .constraints = {
- .name = "LDO2",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
- .consumer_supplies = ldo2_consumers,
- },
- {
- .constraints = {
- .name = "LDO3",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo3_consumers),
- .consumer_supplies = ldo3_consumers,
- },
- {
- .constraints = {
- .name = "LDO4",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo4_consumers),
- .consumer_supplies = ldo4_consumers,
- },
- {
- .constraints = {
- .name = "LDO5",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo5_consumers),
- .consumer_supplies = ldo5_consumers,
- },
- {
- .constraints = {
- .name = "LDO6",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo6_consumers),
- .consumer_supplies = ldo6_consumers,
- },
- {
- .constraints = {
- .name = "LDO7",
- .min_uV = 1000000,
- .max_uV = 3500000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo7_consumers),
- .consumer_supplies = ldo7_consumers,
- },
- {
- .constraints = {
- .name = "LDO8",
- .min_uV = 1000000,
- .max_uV = 3500000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo8_consumers),
- .consumer_supplies = ldo8_consumers,
- },
- {
- .constraints = {
- .name = "LDO9",
- .min_uV = 1000000,
- .max_uV = 3500000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo9_consumers),
- .consumer_supplies = ldo9_consumers,
- },
- {
- .constraints = {
- .name = "LDO10",
- .min_uV = 1000000,
- .max_uV = 3500000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo10_consumers),
- .consumer_supplies = ldo10_consumers,
- },
- {
- .constraints = {
- .name = "LDO11",
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo11_consumers),
- .consumer_supplies = ldo11_consumers,
- },
-};
-
-struct regulator_init_data wm831x_regulator_init_isink[WM831X_MAX_ISINK] = {
- {
- .constraints = {
- .name = "ISINK1",
- .min_uA = 00000,
- .max_uA = 40000,
- .always_on = true,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_CURRENT,
- },
- .num_consumer_supplies = ARRAY_SIZE(isink1_consumers),
- .consumer_supplies = isink1_consumers,
- },
- {
- .constraints = {
- .name = "ISINK2",
- .min_uA = 0000000,
- .max_uA = 0000000,
- .apply_uV = false,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_CURRENT,
- },
- .num_consumer_supplies = ARRAY_SIZE(isink2_consumers),
- .consumer_supplies = isink2_consumers,
- },
-};
-
-static int wm831x_checkrange(int start,int num,int val)
-{
- if((val<(start+num))&&(val>=start))
- return 0;
- else
- return -1;
-}
-
-static int wm831x_init_pin_type(struct wm831x *wm831x)
-{
-#if 1
- struct wm831x_pdata *pdata = wm831x->dev->platform_data;
- struct rk29_gpio_expander_info *wm831x_gpio_settinginfo;
- uint16_t offset = 0;
- uint16_t wm831x_settingpin_num = 0;
- uint16_t ret = 0;
- int i = 0;
-
- if(wm831x)
- {
- wm831x_gpio_settinginfo=pdata->settinginfo;
- if(wm831x_gpio_settinginfo)
- {
- wm831x_settingpin_num = pdata->settinginfolen;
- for(i=0;i<wm831x_settingpin_num;i++)
- {
- if(!wm831x_checkrange(pdata->gpio_base,pdata->gpio_pin_num,wm831x_gpio_settinginfo[i].gpio_num))
- {
- offset = wm831x_gpio_settinginfo[i].gpio_num - pdata->gpio_base;
-
- if(wm831x_gpio_settinginfo[i].pin_type==GPIO_IN)
- {
- wm831x_set_bits(wm831x,(WM831X_GPIO1_CONTROL+offset), WM831X_GPN_DIR_MASK|WM831X_GPN_TRI_MASK, 1<<WM831X_GPN_DIR_SHIFT|1<<WM831X_GPN_TRI_SHIFT);
- }
- else
- {
- wm831x_set_bits(wm831x,(WM831X_GPIO1_CONTROL+offset), WM831X_GPN_DIR_MASK|WM831X_GPN_TRI_MASK, 1<<WM831X_GPN_TRI_SHIFT);
- if(wm831x_gpio_settinginfo[i].pin_value==GPIO_HIGH)
- {
- wm831x_set_bits(wm831x, WM831X_GPIO_LEVEL, (1 << offset),(1 << offset));
- }
- else
- {
- wm831x_set_bits(wm831x, WM831X_GPIO_LEVEL, (1 << offset),(0 << offset));
- }
- }
-
- }
- }
- }
- }
-
- for(i=0;i<pdata->gpio_pin_num;i++)
- {
- wm831x_set_bits(wm831x,(WM831X_GPIO1_CONTROL+i),
- WM831X_GPN_PULL_MASK|WM831X_GPN_POL_MASK|WM831X_GPN_OD_MASK|WM831X_GPN_TRI_MASK,
- 1<<WM831X_GPN_POL_SHIFT|1<<WM831X_GPN_TRI_SHIFT);
- ret = wm831x_reg_read(wm831x, WM831X_GPIO1_CONTROL+i);
- printk("Gpio%d Pin Configuration = %x\n",i,ret);
- }
-#endif
- return 0;
-}
-
-/*
- * GPIO Buttons
- */
-#if defined(CONFIG_KEYBOARD_WM831X_GPIO)
-static struct wm831x_gpio_keys_button wm831x_gpio_buttons[] = {
-{
- .code = KEY_MEDIA,
- .gpio = TCA6424_P21,
- .active_low = 1,
- .desc = "media",
- .wakeup = 0,
- .debounce_interval = 120,
-},
-{
- .code= KEY_VOLUMEUP,
- .gpio= WM831X_P05,
- .active_low= 1,
- .desc= "volume_up",
- .wakeup= 0,
-},
-{
- .code= KEY_CAMERA,
- .gpio= WM831X_P06,
- .active_low= 1,
- .desc= "camera",
- .wakeup= 0,
-},
-{
- .code= KEY_VOLUMEDOWN,
- .gpio= WM831X_P07,
- .active_low= 1,
- .desc= "volume_down",
- .wakeup= 0,
-},
-{
- .code= KEY_END,
- .gpio= WM831X_P09,
- .active_low= 1,
- .desc= "enter",
- .wakeup= 0,
-},
-{
- .code= KEY_MENU,
- .gpio= WM831X_P10,
- .active_low= 1,
- .desc= "menu",
- .wakeup= 0,
-},
-{
- .code= KEY_SEND,
- .gpio= WM831X_P11,
- .active_low= 1,
- .desc= "esc",
- .wakeup= 0,
-},
-{
- .code= KEY_BACK,
- .gpio= WM831X_P12,
- .active_low= 1,
- .desc= "home",
- .wakeup= 0,
-},
-};
-
-struct wm831x_gpio_keys_pdata wm831x_gpio_keys_platdata = {
- .buttons = wm831x_gpio_buttons,
- .nbuttons = ARRAY_SIZE(wm831x_gpio_buttons),
-};
-
-#endif
-struct wm831x_pdata wm831x_platdata = {
- /** Called before subdevices are set up */
- .pre_init= wm831x_pre_init,
- /** Called after subdevices are set up */
- .post_init = wm831x_post_init,
- /** Called before subdevices are power down */
- .last_deinit = wm831x_last_deinit,
-
-#if defined(CONFIG_GPIO_WM831X)
- .gpio_base=WM831X_GPIO_EXPANDER_BASE,
- .gpio_pin_num=WM831X_TOTOL_GPIO_NUM,
- .settinginfo=wm831x_gpio_settinginfo,
- .settinginfolen=ARRAY_SIZE(wm831x_gpio_settinginfo),
- .pin_type_init = wm831x_init_pin_type,
- .irq_base= NR_AIC_IRQS + 7*NUM_GROUP,
-#endif
-
- .backlight = &wm831x_backlight_platdata,
-
- .backup = &wm831x_backup_platdata,
-
- .battery = &wm831x_battery_platdata,
- //.wm831x_touch_pdata = NULL,
- //.watchdog = NULL,
-
-#if defined(CONFIG_KEYBOARD_WM831X_GPIO)
- .gpio_keys = &wm831x_gpio_keys_platdata,
-#endif
-
- /** LED1 = 0 and so on */
- .status = {&wm831x_status_platdata[0], &wm831x_status_platdata[1]},
-
- /** DCDC1 = 0 and so on */
- .dcdc = {&wm831x_regulator_init_dcdc[0], &wm831x_regulator_init_dcdc[1], &wm831x_regulator_init_dcdc[2], &wm831x_regulator_init_dcdc[3]},
-
- /** EPE1 = 0 and so on */
- .epe = {&wm831x_regulator_init_epe[0], &wm831x_regulator_init_epe[1]},
-
- /** LDO1 = 0 and so on */
- .ldo = {&wm831x_regulator_init_ldo[0], &wm831x_regulator_init_ldo[1], &wm831x_regulator_init_ldo[2], &wm831x_regulator_init_ldo[3],
- &wm831x_regulator_init_ldo[4], &wm831x_regulator_init_ldo[5], &wm831x_regulator_init_ldo[6], &wm831x_regulator_init_ldo[7],
- &wm831x_regulator_init_ldo[8], &wm831x_regulator_init_ldo[9], &wm831x_regulator_init_ldo[10]},
-
- /** ISINK1 = 0 and so on*/
- .isink = {&wm831x_regulator_init_isink[0], &wm831x_regulator_init_isink[1]},
-};
-#endif
-
-#if defined(CONFIG_RK29_GPIO_SUSPEND)
-static void gpio_set_request(void)
-{
- gpio_request(RK29_PIN6_PA0, NULL);
- gpio_request(RK29_PIN6_PA1, NULL);
- gpio_request(RK29_PIN6_PA2, NULL);
- gpio_request(RK29_PIN6_PA3, NULL);
- gpio_request(RK29_PIN6_PA4, NULL);
- gpio_request(RK29_PIN6_PA5, NULL);
- gpio_request(RK29_PIN6_PA6, NULL);
-
- gpio_request(RK29_PIN2_PA5, NULL);
- gpio_request(RK29_PIN2_PA4, NULL);
- gpio_request(RK29_PIN2_PB0, NULL);
- gpio_request(RK29_PIN2_PB1, NULL);
- gpio_request(RK29_PIN2_PB2, NULL);
- gpio_request(RK29_PIN2_PB3, NULL);
-
- gpio_request(RK29_PIN1_PA4, NULL);
- gpio_request(RK29_PIN1_PA3, NULL);
-
- gpio_request(RK29_PIN2_PC7, NULL);
- gpio_request(RK29_PIN2_PC6, NULL);
- gpio_request(RK29_PIN2_PC5, NULL);
- gpio_request(RK29_PIN2_PC4, NULL);
- gpio_request(RK29_PIN2_PC3, NULL);
- gpio_request(RK29_PIN2_PC2, NULL);
- gpio_request(RK29_PIN2_PC1, NULL);
- gpio_request(RK29_PIN2_PC0, NULL);
-}
-
-static void gpio_set_free(void)
-{
- gpio_free(RK29_PIN6_PA0);
- gpio_free(RK29_PIN6_PA1);
- gpio_free(RK29_PIN6_PA2);
- gpio_free(RK29_PIN6_PA3);
- gpio_free(RK29_PIN6_PA4);
- gpio_free(RK29_PIN6_PA5);
- gpio_free(RK29_PIN6_PA6);
-
- gpio_free(RK29_PIN2_PA5);
- gpio_free(RK29_PIN2_PA4);
- gpio_free(RK29_PIN2_PB0);
- gpio_free(RK29_PIN2_PB1);
- gpio_free(RK29_PIN2_PB2);
- gpio_free(RK29_PIN2_PB3);
-
- gpio_free(RK29_PIN1_PA4);
- gpio_free(RK29_PIN1_PA3);
-
- gpio_free(RK29_PIN2_PC7);
- gpio_free(RK29_PIN2_PC6);
- gpio_free(RK29_PIN2_PC5);
- gpio_free(RK29_PIN2_PC4);
- gpio_free(RK29_PIN2_PC3);
- gpio_free(RK29_PIN2_PC2);
- gpio_free(RK29_PIN2_PC1);
- gpio_free(RK29_PIN2_PC0);
-}
-
-static void rk29_keygpio_suspend(void)
-{
- gpio_pull_updown(RK29_PIN6_PA0, 0);
- gpio_pull_updown(RK29_PIN6_PA1, 0);
- gpio_pull_updown(RK29_PIN6_PA2, 0);
- gpio_pull_updown(RK29_PIN6_PA3, 0);
- gpio_pull_updown(RK29_PIN6_PA4, 0);
- gpio_pull_updown(RK29_PIN6_PA5, 0);
- gpio_pull_updown(RK29_PIN6_PA6, 0);//key pullup/pulldown disable
-
- gpio_pull_updown(RK29_PIN2_PA4, 0);
- gpio_pull_updown(RK29_PIN2_PA5, 0);
- gpio_pull_updown(RK29_PIN2_PB0, 0);
- gpio_pull_updown(RK29_PIN2_PB1, 0);
- gpio_pull_updown(RK29_PIN2_PB2, 0);
- gpio_pull_updown(RK29_PIN2_PB3, 0);
-}
-
-static void rk29_keygpio_resume(void)
-{
- gpio_pull_updown(RK29_PIN6_PA0, 1);
- gpio_pull_updown(RK29_PIN6_PA1, 1);
- gpio_pull_updown(RK29_PIN6_PA2, 1);
- gpio_pull_updown(RK29_PIN6_PA3, 1);
- gpio_pull_updown(RK29_PIN6_PA4, 1);
- gpio_pull_updown(RK29_PIN6_PA5, 1);
- gpio_pull_updown(RK29_PIN6_PA6, 1);//key pullup/pulldown enable
-
- gpio_pull_updown(RK29_PIN2_PA4, 1);
- gpio_pull_updown(RK29_PIN2_PA5, 1);
- gpio_pull_updown(RK29_PIN2_PB0, 1);
- gpio_pull_updown(RK29_PIN2_PB1, 1);
- gpio_pull_updown(RK29_PIN2_PB2, 1);
- gpio_pull_updown(RK29_PIN2_PB3, 1);
-}
-
-static void spi_gpio_suspend(void)
-{
- rk29_mux_api_set(GPIO1A4_EMMCWRITEPRT_SPI0CS1_NAME,GPIO1L_GPIO1A4); //set iomux is gpio mode
- rk29_mux_api_set(GPIO1A3_EMMCDETECTN_SPI1CS1_NAME,GPIO1L_GPIO1A3);
-
- rk29_mux_api_set(GPIO2C7_SPI1RXD_NAME,GPIO2H_GPIO2C7);
- rk29_mux_api_set(GPIO2C6_SPI1TXD_NAME,GPIO2H_GPIO2C6);
- //rk29_mux_api_set(GPIO2C5_SPI1CSN0_NAME,GPIO2H_GPIO2C5);
- rk29_mux_api_set(GPIO2C4_SPI1CLK_NAME,GPIO2H_GPIO2C4);
- rk29_mux_api_set(GPIO2C3_SPI0RXD_NAME,GPIO2H_GPIO2C3);
- rk29_mux_api_set(GPIO2C2_SPI0TXD_NAME,GPIO2H_GPIO2C2);
- rk29_mux_api_set(GPIO2C1_SPI0CSN0_NAME,GPIO2H_GPIO2C1);
- rk29_mux_api_set(GPIO2C0_SPI0CLK_NAME,GPIO2H_GPIO2C0);
-
- gpio_direction_input(RK29_PIN1_PA4); //set gpio is input
- gpio_direction_input(RK29_PIN1_PA3);
- gpio_direction_input(RK29_PIN2_PC7);
- gpio_direction_input(RK29_PIN2_PC6);
- // gpio_direction_input(RK29_PIN2_PC5);
- gpio_direction_input(RK29_PIN2_PC4);
- gpio_direction_input(RK29_PIN2_PC3);
- gpio_direction_input(RK29_PIN2_PC2);
- gpio_direction_input(RK29_PIN2_PC1);
- gpio_direction_input(RK29_PIN2_PC0);
-
- gpio_pull_updown(RK29_PIN1_PA4, 0); //set gpio pullup/down disable
- gpio_pull_updown(RK29_PIN1_PA3, 0);
-
- gpio_pull_updown(RK29_PIN2_PC7, 0);
- gpio_pull_updown(RK29_PIN2_PC6, 0);
- //gpio_pull_updown(RK29_PIN2_PC5, 0);
- gpio_pull_updown(RK29_PIN2_PC4, 0);
- gpio_pull_updown(RK29_PIN2_PC3, 0);
- gpio_pull_updown(RK29_PIN2_PC2, 0);
- gpio_pull_updown(RK29_PIN2_PC1, 0);
- gpio_pull_updown(RK29_PIN2_PC0, 0);
-}
-
-static void spi_gpio_resume(void)
-{
- gpio_pull_updown(RK29_PIN1_PA4, 1); //set gpio pullup/down enable
- gpio_pull_updown(RK29_PIN1_PA3, 1);
-
- gpio_pull_updown(RK29_PIN2_PC7, 1);
- gpio_pull_updown(RK29_PIN2_PC6, 1);
- //gpio_pull_updown(RK29_PIN2_PC5, 1);
- gpio_pull_updown(RK29_PIN2_PC4, 1);
- gpio_pull_updown(RK29_PIN2_PC3, 1);
- gpio_pull_updown(RK29_PIN2_PC2, 1);
- gpio_pull_updown(RK29_PIN2_PC1, 1);
- gpio_pull_updown(RK29_PIN2_PC0, 1);
-
- rk29_mux_api_set(GPIO1A4_EMMCWRITEPRT_SPI0CS1_NAME,GPIO1L_SPI0_CSN1); //set iomux is spi mode
- rk29_mux_api_set(GPIO1A3_EMMCDETECTN_SPI1CS1_NAME,GPIO1L_SPI1_CSN1);
-
- rk29_mux_api_set(GPIO2C7_SPI1RXD_NAME,GPIO2H_SPI1_RXD);
- rk29_mux_api_set(GPIO2C6_SPI1TXD_NAME,GPIO2H_SPI1_TXD);
- //rk29_mux_api_set(GPIO2C5_SPI1CSN0_NAME,GPIO2H_SPI1_CSN0);
- rk29_mux_api_set(GPIO2C4_SPI1CLK_NAME, GPIO2H_SPI1_CLK);
- rk29_mux_api_set(GPIO2C3_SPI0RXD_NAME,GPIO2H_SPI0_RXD);
- rk29_mux_api_set(GPIO2C2_SPI0TXD_NAME,GPIO2H_SPI0_TXD);
- rk29_mux_api_set(GPIO2C1_SPI0CSN0_NAME,GPIO2H_SPI0_CSN0);
- rk29_mux_api_set(GPIO2C0_SPI0CLK_NAME,GPIO2H_SPI0_CLK);
-}
-
-void rk29_setgpio_suspend_board(void)
-{
- gpio_set_request();
- rk29_keygpio_suspend();
- spi_gpio_suspend();
- gpio_set_free();
-}
-
-void rk29_setgpio_resume_board(void)
-{
- gpio_set_request();
- rk29_keygpio_resume();
- spi_gpio_resume();
- gpio_set_free();
-}
-#endif
-
-#if defined(CONFIG_RK29_GPS)
-
-#define RK29_GPS_POWER_PIN RK29_PIN6_PB2
-#define RK29_GPS_RESET_PIN RK29_PIN6_PC1
-
-int rk29_gps_power_up(void)
-{
- printk("%s \n", __FUNCTION__);
-
- gpio_request(RK29_GPS_POWER_PIN, NULL);
- gpio_direction_output(RK29_GPS_POWER_PIN, GPIO_HIGH);
-
- return 0;
-}
-
-int rk29_gps_power_down(void)
-{
- printk("%s \n", __FUNCTION__);
-
- gpio_request(RK29_GPS_POWER_PIN, NULL);
- gpio_direction_output(RK29_GPS_POWER_PIN, GPIO_LOW);
-
- return 0;
-}
-
-int rk29_gps_reset_set(int level)
-{
- gpio_request(RK29_GPS_RESET_PIN, NULL);
- if (level)
- gpio_direction_output(RK29_GPS_RESET_PIN, GPIO_HIGH);
- else
- gpio_direction_output(RK29_GPS_RESET_PIN, GPIO_LOW);
-
- return 0;
-}
-
-struct rk29_gps_data rk29_gps_info = {
- .power_up = rk29_gps_power_up,
- .power_down = rk29_gps_power_down,
- .reset = rk29_gps_reset_set,
- .uart_id = 3,
-};
-
-struct platform_device rk29_device_gps = {
- .name = "rk29_gps",
- .id = -1,
- .dev = {
- .platform_data = &rk29_gps_info,
- }
- };
-#endif
-
-/*****************************************************************************************
- * wm8994 codec
- * author: qjb@rock-chips.com
- *****************************************************************************************/
-#if defined(CONFIG_MFD_WM8994)
-static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = {
- REGULATOR_SUPPLY("DBVDD", "5-001a"),
- REGULATOR_SUPPLY("AVDD2", "5-001a"),
- REGULATOR_SUPPLY("CPVDD", "5-001a"),
-};
-
-static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = {
- REGULATOR_SUPPLY("SPKVDD1", "5-001a"),
- REGULATOR_SUPPLY("SPKVDD2", "5-001a"),
-};
-
-static struct regulator_init_data wm8994_fixed_voltage0_init_data = {
- .constraints = {
- .always_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage0_supplies),
- .consumer_supplies = wm8994_fixed_voltage0_supplies,
-};
-
-static struct regulator_init_data wm8994_fixed_voltage1_init_data = {
- .constraints = {
- .always_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage1_supplies),
- .consumer_supplies = wm8994_fixed_voltage1_supplies,
-};
-
-static struct fixed_voltage_config wm8994_fixed_voltage0_config = {
- .supply_name = "VCC_1.8V_PDA",
- .microvolts = 1800000,
- .gpio = -EINVAL,
- .init_data = &wm8994_fixed_voltage0_init_data,
-};
-
-static struct fixed_voltage_config wm8994_fixed_voltage1_config = {
- .supply_name = "V_BAT",
- .microvolts = 3700000,
- .gpio = -EINVAL,
- .init_data = &wm8994_fixed_voltage1_init_data,
-};
-
-static struct platform_device wm8994_fixed_voltage0 = {
- .name = "reg-fixed-voltage",
- .id = 0,
- .dev = {
- .platform_data = &wm8994_fixed_voltage0_config,
- },
-};
-
-static struct platform_device wm8994_fixed_voltage1 = {
- .name = "reg-fixed-voltage",
- .id = 1,
- .dev = {
- .platform_data = &wm8994_fixed_voltage1_config,
- },
-};
-
-static struct regulator_consumer_supply wm8994_avdd1_supply =
- REGULATOR_SUPPLY("AVDD1", "5-001a");
-
-static struct regulator_consumer_supply wm8994_dcvdd_supply =
- REGULATOR_SUPPLY("DCVDD", "5-001a");
-
-
-
-static struct regulator_init_data wm8994_ldo1_data = {
- .constraints = {
- .name = "AVDD1_3.0V",
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = 1,
- .consumer_supplies = &wm8994_avdd1_supply,
-};
-
-static struct regulator_init_data wm8994_ldo2_data = {
- .constraints = {
- .name = "DCVDD_1.0V",
- },
- .num_consumer_supplies = 1,
- .consumer_supplies = &wm8994_dcvdd_supply,
-};
-
-static struct wm8994_pdata wm8994_platform_data = {
-#if defined (CONFIG_GPIO_WM8994)
- .gpio_base = WM8994_GPIO_EXPANDER_BASE,
- //Fill value to initialize the GPIO
- //.gpio_defaults ={},
- /* configure gpio1 function: 0x0001(Logic level input/output) */
-// .gpio_defaults[0] = 0x0001,
- /* configure gpio3/4/5/7 function for AIF2 voice */
- .gpio_defaults[2] = 0x2100,
- .gpio_defaults[3] = 0x2100,
- .gpio_defaults[4] = 0xA100,
-// .gpio_defaults[6] = 0x0100,
- /* configure gpio8/9/10/11 function for AIF3 BT */
- .gpio_defaults[7] = 0xA100,
- .gpio_defaults[8] = 0x2100,
- .gpio_defaults[9] = 0x2100,
- .gpio_defaults[10] = 0x2100,
-#endif
-
- .ldo[0] = { RK29_PIN5_PA1, NULL, &wm8994_ldo1_data }, /* XM0FRNB_2 */
- .ldo[1] = { 0, NULL, &wm8994_ldo2_data },
-
- .micdet_irq = 0,
- .irq_base = 0,
-
-// .BB_input_diff = 0,
-// .BB_class = NO_PCM_BB,
-
- .PA_control_pin = RK29_PIN6_PD3,
-};
-#endif
-#ifdef CONFIG_RK_HEADSET_DET
-
-struct rk_headset_pdata rk_headset_info = {
- .Headset_gpio = RK29_PIN3_PA6,
- .headset_in_type= HEADSET_IN_HIGH,
- .Hook_gpio = RK29_PIN4_PD1,//Detection Headset--Must be set
- .hook_key_code = KEY_MEDIA,
-};
-
-struct platform_device rk_device_headset = {
- .name = "rk_headsetdet",
- .id = 0,
- .dev = {
- .platform_data = &rk_headset_info,
- }
-};
-#endif
-
-#if defined (CONFIG_COMPASS_AK8975)
-static struct akm8975_platform_data akm8975_info =
-{
- .m_layout =
- {
- {
- {1, 0, 0 },
- {0, -1, 0 },
- {0, 0, -1 },
- },
-
- {
- {1, 0, 0 },
- {0, 1, 0 },
- {0, 0, 1 },
- },
-
- {
- {1, 0, 0 },
- {0, 1, 0 },
- {0, 0, 1 },
- },
-
- {
- {1, 0, 0 },
- {0, 1, 0 },
- {0, 0, 1 },
- },
- }
-
-};
-
-#endif
-
-
-#if defined (CONFIG_SENSORS_MPU3050)
-/*mpu3050*/
-static struct mpu3050_platform_data mpu3050_data = {
- .int_config = 0x10,
- //.orientation = { 1, 0, 0,0, -1, 0,0, 0, 1 },
- //.orientation = { 0, 1, 0,-1, 0, 0,0, 0, -1 },
- .orientation = { -1, 0, 0,0, -1, 0, 0, 0, -1 },
- .level_shifter = 0,
-#if defined (CONFIG_SENSORS_KXTF9)
- .accel = {
- .get_slave_descr = kxtf9_get_slave_descr ,
- .adapt_num = 0, // The i2c bus to which the mpu device is
- // connected
- .irq = RK29_PIN6_PC4,
- .bus = EXT_SLAVE_BUS_SECONDARY, //The secondary I2C of MPU
- .address = 0x0f,
- //.orientation = { 1, 0, 0,0, 1, 0,0, 0, 1 },
- //.orientation = { 0, -1, 0,-1, 0, 0,0, 0, -1 },
- //.orientation = { 0, 1, 0,1, 0, 0,0, 0, -1 },
- .orientation = {1, 0, 0, 0, -1, 0, 0, 0, -1},
- },
-#endif
-#if defined (CONFIG_SENSORS_AK8975)
- .compass = {
- .get_slave_descr = ak8975_get_slave_descr,/*ak5883_get_slave_descr,*/
- .adapt_num = 0, // The i2c bus to which the compass device is.
- // It can be difference with mpu
- // connected
- .irq = RK29_PIN6_PC5,
- .bus = EXT_SLAVE_BUS_PRIMARY,
- .address = 0x0d,
- //.orientation = { -1, 0, 0,0, -1, 0,0, 0, 1 },
- //.orientation = { 0, -1, 0,-1, 0, 0,0, 0, -1 },
- .orientation = { 0, 1, 0,1, 0, 0,0, 0, -1 },
- },
-#endif
-};
-#endif
-
-
-/*****************************************************************************************
- * i2c devices
- * author: kfx@rock-chips.com
-*****************************************************************************************/
-static int rk29_i2c0_io_init(void)
-{
-#ifdef CONFIG_RK29_I2C0_CONTROLLER
- rk29_mux_api_set(GPIO2B7_I2C0SCL_NAME, GPIO2L_I2C0_SCL);
- rk29_mux_api_set(GPIO2B6_I2C0SDA_NAME, GPIO2L_I2C0_SDA);
-#else
- rk29_mux_api_set(GPIO2B7_I2C0SCL_NAME, GPIO2L_GPIO2B7);
- rk29_mux_api_set(GPIO2B6_I2C0SDA_NAME, GPIO2L_GPIO2B6);
-#endif
- return 0;
-}
-
-static int rk29_i2c1_io_init(void)
-{
-#ifdef CONFIG_RK29_I2C1_CONTROLLER
- rk29_mux_api_set(GPIO1A7_I2C1SCL_NAME, GPIO1L_I2C1_SCL);
- rk29_mux_api_set(GPIO1A6_I2C1SDA_NAME, GPIO1L_I2C1_SDA);
-#else
- rk29_mux_api_set(GPIO1A7_I2C1SCL_NAME, GPIO1L_GPIO1A7);
- rk29_mux_api_set(GPIO1A6_I2C1SDA_NAME, GPIO1L_GPIO1A6);
-#endif
- return 0;
-}
-static int rk29_i2c2_io_init(void)
-{
-#ifdef CONFIG_RK29_I2C2_CONTROLLER
- rk29_mux_api_set(GPIO5D4_I2C2SCL_NAME, GPIO5H_I2C2_SCL);
- rk29_mux_api_set(GPIO5D3_I2C2SDA_NAME, GPIO5H_I2C2_SDA);
-#else
- rk29_mux_api_set(GPIO5D4_I2C2SCL_NAME, GPIO5H_GPIO5D4);
- rk29_mux_api_set(GPIO5D3_I2C2SDA_NAME, GPIO5H_GPIO5D3);
-#endif
- return 0;
-}
-
-static int rk29_i2c3_io_init(void)
-{
-#ifdef CONFIG_RK29_I2C3_CONTROLLER
- rk29_mux_api_set(GPIO2B5_UART3RTSN_I2C3SCL_NAME, GPIO2L_I2C3_SCL);
- rk29_mux_api_set(GPIO2B4_UART3CTSN_I2C3SDA_NAME, GPIO2L_I2C3_SDA);
-#else
- rk29_mux_api_set(GPIO2B5_UART3RTSN_I2C3SCL_NAME, GPIO2L_GPIO2B5);
- rk29_mux_api_set(GPIO2B4_UART3CTSN_I2C3SDA_NAME, GPIO2L_GPIO2B4);
-#endif
- return 0;
-}
-#ifdef CONFIG_RK29_I2C0_CONTROLLER
-struct rk29_i2c_platform_data default_i2c0_data = {
- .bus_num = 0,
- .flags = 0,
- .slave_addr = 0xff,
- .scl_rate = 400*1000,
- .mode = I2C_MODE_IRQ,
- .io_init = rk29_i2c0_io_init,
-};
-#else
-struct i2c_gpio_platform_data default_i2c0_data = {
- .sda_pin = RK29_PIN2_PB6,
- .scl_pin = RK29_PIN2_PB7,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(200),
- .bus_num = 0,
- .io_init = rk29_i2c0_io_init,
-};
-#endif
-#ifdef CONFIG_RK29_I2C1_CONTROLLER
-struct rk29_i2c_platform_data default_i2c1_data = {
- .bus_num = 1,
- .flags = 0,
- .slave_addr = 0xff,
- .scl_rate = 400*1000,
- .mode = I2C_MODE_IRQ,
- .io_init = rk29_i2c1_io_init,
-};
-#else
-struct i2c_gpio_platform_data default_i2c1_data = {
- .sda_pin = RK29_PIN1_PA6,
- .scl_pin = RK29_PIN1_PA7,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(200),
- .bus_num = 1,
- .io_init = rk29_i2c1_io_init,
-};
-#endif
-#ifdef CONFIG_RK29_I2C2_CONTROLLER
-struct rk29_i2c_platform_data default_i2c2_data = {
- .bus_num = 2,
- .flags = 0,
- .slave_addr = 0xff,
- .scl_rate = 400*1000,
- .mode = I2C_MODE_IRQ,
- .io_init = rk29_i2c2_io_init,
-};
-#else
-struct i2c_gpio_platform_data default_i2c2_data = {
- .sda_pin = RK29_PIN5_PD3,
- .scl_pin = RK29_PIN5_PD4,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(200),
- .bus_num = 2,
- .io_init = rk29_i2c2_io_init,
-};
-#endif
-#ifdef CONFIG_RK29_I2C3_CONTROLLER
-struct rk29_i2c_platform_data default_i2c3_data = {
- .bus_num = 3,
- .flags = 0,
- .slave_addr = 0xff,
- .scl_rate = 400*1000,
- .mode = I2C_MODE_IRQ,
- .io_init = rk29_i2c3_io_init,
-};
-#else
-struct i2c_gpio_platform_data default_i2c3_data = {
- .sda_pin = RK29_PIN5_PB5,
- .scl_pin = RK29_PIN5_PB4,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(200),
- .bus_num = 3,
- .io_init = rk29_i2c3_io_init,
-};
-#endif
-#if defined (CONFIG_ANX7150)
-#define HDMI_VDD_CTL RK29_PIN6_PD3
-struct hdmi_platform_data anx7150_data = {
- //.io_init = anx7150_io_init,
-};
-#endif
-
-#ifdef CONFIG_I2C0_RK29
-static struct i2c_board_info __initdata board_i2c0_devices[] = {
-#if defined (CONFIG_RK1000_CONTROL)
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_WM8900)
- {
- .type = "wm8900",
- .addr = 0x1A,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_WM8994)
- {
- .type = "wm8994",
- .addr = 0x1a,
- .flags = 0,
- #if defined(CONFIG_MFD_WM8994)
- .platform_data = &wm8994_platform_data,
- #endif
- },
-#endif
-#if defined (CONFIG_FM580X)
- {
- .type = "fm580x",
- .addr = 0x10,
- .flags = 0,
- },
-#endif
-
-#if defined (CONFIG_BATTERY_STC3100)
- {
- .type = "stc3100",
- .addr = 0x70,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_BATTERY_BQ27510)
- {
- .type = "bq27510",
- .addr = 0x55,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_RTC_HYM8563)
- {
- .type = "rtc_hym8563",
- .addr = 0x51,
- .flags = 0,
- .irq = RK29_PIN0_PA1,
- },
-#endif
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1c,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8973)
- {
- .type = "ak8973",
- .addr = 0x1d,
- .flags = 0,
- .irq = RK29_PIN0_PA4,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK29_PIN6_PC5,
- .platform_data = &akm8975_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_MMC328X)
- {
- .type = "mmc328x",
- .addr = 0x30,
- .flags = I2C_M_NEED_DELAY,
- .udelay = 100,
- .platform_data = NULL,
- },
-#endif
-#if defined (CONFIG_INPUT_LPSENSOR_ISL29028)
- {
- .type = "isl29028",
- .addr = 0x44,
- .flags = 0,
- .irq = RK29_PIN4_PD3,
- },
-#endif
-#if defined (CONFIG_ANX7150)
- {
- .type = "anx7150",
- .addr = 0x39, //0x39, 0x3d
- .flags = 0,
- .irq = RK29_PIN2_PA3,
- .platform_data = &anx7150_data,
- },
-#endif
-#if defined (CONFIG_SENSORS_MPU3050)
- {
- .type = "mpu3050",
- .addr = 0x68,
- .flags = 0,
- .irq = RK29_PIN5_PA3,
- .platform_data = &mpu3050_data,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C1_RK29
-static struct i2c_board_info __initdata board_i2c1_devices[] = {
-#if defined (CONFIG_RK1000_CONTROL1)
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C2_RK29
-static struct i2c_board_info __initdata board_i2c2_devices[] = {
-#if defined (CONFIG_TOUCHSCREEN_ILI2102_IIC)
-{
- .type = "ili2102_ts",
- .addr = 0x41,
- .flags = I2C_M_NEED_DELAY,
- .udelay = 600,
- .irq = RK29_PIN4_PD5,
- .platform_data = &ili2102_info,
-},
-#endif
-#if defined (CONFIG_MFD_WM831X_I2C)
-{
- .type = "wm8310",
- .addr = 0x34,
- .flags = 0,
- .irq = RK29_PIN4_PD0,
- .platform_data = &wm831x_platdata,
-},
-#endif
-#if defined (CONFIG_HANNSTAR_P1003)
- {
- .type = "p1003_touch",
- .addr = 0x04,
- .flags = 0,
- .irq = RK29_PIN0_PA2,
- .platform_data = &p1003_info,
- },
-#endif
-#if defined (CONFIG_EETI_EGALAX)
- {
- .type = "egalax_i2c",
- .addr = 0x04,
- .flags = 0,
- .irq = RK29_PIN4_PD5,
- .platform_data = &eeti_egalax_info,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK29
-static struct i2c_board_info __initdata board_i2c3_devices[] = {
-};
-#endif
-
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#define CONFIG_SENSOR_POWER_IOCTL_USR 0
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 1
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_RESET_IOCTL_USR
-static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
-static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- int camera_flash = res->gpio_flash;
- int camera_ioflag = res->gpio_flag;
- int camera_io_init = res->gpio_init;
- int ret = 0;
-
- printk("###########%s, %d , on = %d\n",__FUNCTION__,__LINE__,on);
-
- if (camera_flash != INVALID_GPIO) {
- if (camera_io_init & RK29_CAM_FLASHACTIVE_MASK) {
- switch (on)
- {
- case Flash_Off:
- {
- gpio_set_value(camera_flash,(((~camera_ioflag)&RK29_CAM_FLASHACTIVE_MASK)>>RK29_CAM_FLASHACTIVE_BITPOS));
- printk("\n%s..%s..FlashPin= %d..PinLevel = %x \n",__FUNCTION__,res->dev_name, camera_flash, (((~camera_ioflag)&RK29_CAM_FLASHACTIVE_MASK)>>RK29_CAM_FLASHACTIVE_BITPOS));
- break;
- }
-
- case Flash_On:
- {
- gpio_set_value(RK29_PIN1_PA5,((camera_ioflag&RK29_CAM_FLASHACTIVE_MASK)>>RK29_CAM_FLASHACTIVE_BITPOS));
- gpio_set_value(camera_flash, ((camera_ioflag&RK29_CAM_FLASHACTIVE_MASK)>>RK29_CAM_FLASHACTIVE_BITPOS));
-
- //gpio_set_value(camera_flash, 0);
- printk("\n%s..%s..FlashPin=%d ..PinLevel = %x \n",__FUNCTION__,res->dev_name,camera_flash, ((camera_ioflag&RK29_CAM_FLASHACTIVE_MASK)>>RK29_CAM_FLASHACTIVE_BITPOS));
- break;
- }
-
- case Flash_Torch:
- {
- gpio_set_value(RK29_PIN1_PA5,((~camera_ioflag&RK29_CAM_FLASHACTIVE_MASK)>>RK29_CAM_FLASHACTIVE_BITPOS));
- gpio_set_value(camera_flash, ((camera_ioflag&RK29_CAM_FLASHACTIVE_MASK)>>RK29_CAM_FLASHACTIVE_BITPOS));
-
- //gpio_set_value(camera_flash, 0);
- printk("\n%s..%s..FlashPin=%d ..PinLevel = %x \n",__FUNCTION__,res->dev_name,camera_flash, ((camera_ioflag&RK29_CAM_FLASHACTIVE_MASK)>>RK29_CAM_FLASHACTIVE_BITPOS));
- break;
- }
-
- default:
- {
- printk("\n%s..%s..Flash command(%d) is invalidate \n",__FUNCTION__,res->dev_name,on);
- break;
- }
- }
- } else {
- ret = RK29_CAM_EIO_REQUESTFAIL;
- printk("\n%s..%s..FlashPin=%d request failed!\n",__FUNCTION__,res->dev_name,camera_flash);
- }
- } else {
- ret = RK29_CAM_EIO_INVALID;
- }
- return ret;
-
- // #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-#include "../../../drivers/media/video/rk29_camera.c"
-#endif
-/*****************************************************************************************
- * backlight devices
- * author: nzy@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- /*
- GPIO1B5_PWM0_NAME, GPIO1L_PWM0
- GPIO5D2_PWM1_UART1SIRIN_NAME, GPIO5H_PWM1
- GPIO2A3_SDMMC0WRITEPRT_PWM2_NAME, GPIO2L_PWM2
- GPIO1A5_EMMCPWREN_PWM3_NAME, GPIO1L_PWM3
- */
-
-#define PWM_ID 0
-#define PWM_MUX_NAME GPIO1B5_PWM0_NAME
-#define PWM_MUX_MODE GPIO1L_PWM0
-#define PWM_MUX_MODE_GPIO GPIO1L_GPIO1B5
-#define PWM_EFFECT_VALUE 1
-
-//#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-#define BL_EN_MUX_NAME GPIOF34_UART3_SEL_NAME
-#define BL_EN_MUX_MODE IOMUXB_GPIO1_B34
-
-#define BL_EN_PIN GPIO0L_GPIO0A5
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
-
- rk29_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
- #ifdef LCD_DISP_ON_PIN
- rk29_mux_api_set(BL_EN_MUX_NAME, BL_EN_MUX_MODE);
-
- ret = gpio_request(BL_EN_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(BL_EN_PIN);
- }
-
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
- #endif
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0;
- #ifdef LCD_DISP_ON_PIN
- gpio_free(BL_EN_PIN);
- #endif
- rk29_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- return ret;
-}
-struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
-};
-#endif
-
-#ifdef CONFIG_BACKLIGHT_AW9364
-static int aw9364_backlight_io_init(void)
-{
- return 0;
-}
-
-static int aw9364_backlight_io_deinit(void)
-{
- return 0;
-}
-struct aw9364_platform_data aw9364_bl_info = {
- .pin_en = RK29_PIN6_PD2,
- .io_init = aw9364_backlight_io_init,
- .io_deinit = aw9364_backlight_io_deinit,
-};
-
-struct platform_device aw9364_device_backlight = {
- .name = "aw9364_backlight",
- .id = -1,
- .dev = {
- .platform_data = &aw9364_bl_info,
- }
- };
-
-#endif
-
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
-#define NUM_LEDS 1
-struct gpio_led rk29_leds[NUM_LEDS] = {
- {
- .name = "rk29_led",
- .gpio = RK29_PIN6_PB4,
- .active_low = 0,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- },
-};
-
-struct gpio_led_platform_data rk29_leds_pdata = {
- .num_leds = NUM_LEDS,
- .leds = &rk29_leds,
-};
-
-struct platform_device rk29_device_gpio_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_leds_pdata,
- },
-};
-
-#endif
-
-/*****************************************************************************************
-* pwm voltage regulator devices
-******************************************************************************************/
-#if defined (CONFIG_RK29_PWM_REGULATOR)
-
-#define REGULATOR_PWM_ID 2
-#define REGULATOR_PWM_MUX_NAME GPIO2A3_SDMMC0WRITEPRT_PWM2_NAME
-#define REGULATOR_PWM_MUX_MODE GPIO2L_PWM2
-#define REGULATOR_PWM_MUX_MODE_GPIO GPIO2L_GPIO2A3
-#define REGULATOR_PWM_GPIO RK29_PIN2_PA3
-
-static struct regulator_consumer_supply pwm_consumers[] = {
- {
- .supply = "vcore",
- }
-};
-
-static struct regulator_init_data rk29_pwm_regulator_data = {
- .constraints = {
- .name = "PWM2",
- .min_uV = 950000,
- .max_uV = 1400000,
- .apply_uV = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_consumers),
- .consumer_supplies = pwm_consumers,
-};
-
-static struct pwm_platform_data rk29_regulator_pwm_platform_data = {
- .pwm_id = REGULATOR_PWM_ID,
- .pwm_gpio = REGULATOR_PWM_GPIO,
- //.pwm_iomux_name[] = REGULATOR_PWM_MUX_NAME;
- .pwm_iomux_name = REGULATOR_PWM_MUX_NAME,
- .pwm_iomux_pwm = REGULATOR_PWM_MUX_MODE,
- .pwm_iomux_gpio = REGULATOR_PWM_MUX_MODE_GPIO,
- .init_data = &rk29_pwm_regulator_data,
-};
-
-static struct platform_device rk29_device_pwm_regulator = {
- .name = "pwm-voltage-regulator",
- .id = -1,
- .dev = {
- .platform_data = &rk29_regulator_pwm_platform_data,
- },
-};
-
-#endif
-
-
-#if defined(CONFIG_MTK23D)
-static int mtk23d_io_init(void)
-{
- return 0;
-}
-
-static int mtk23d_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk2818_23d_data rk2818_23d_info = {
- .io_init = mtk23d_io_init,
- .io_deinit = mtk23d_io_deinit,
- .bp_power = RK29_PIN6_PB0,
- .bp_power_active_low = 0,
- .bp_reset = RK29_PIN6_PB1,
- .bp_reset_active_low = 0,
- .bp_statue = RK29_PIN0_PA2,//input high bp sleep;
- .ap_statue = RK29_PIN0_PA3,//output high ap sleep;
- .ap_bp_wakeup = RK29_PIN0_PA0, //output AP wake up BP used rising edge;
- .bp_ap_wakeup = RK29_PIN0_PA4,//input BP wake up AP
-};
-struct platform_device rk2818_device_mtk23d = {
- .name = "mtk23d",
- .id = -1,
- .dev = {
- .platform_data = &rk2818_23d_info,
- }
- };
-#endif
-
-/*****************************************************************************************
- * SDMMC devices
-*****************************************************************************************/
-#if !defined(CONFIG_SDMMC_RK29_OLD)
-static void rk29_sdmmc_gpio_open(int device_id, int on)
-{
- switch(device_id)
- {
- case 0://mmc0
- {
- #ifdef CONFIG_SDMMC0_RK29
- if(on)
- {
- gpio_direction_output(RK29_PIN1_PD0,GPIO_HIGH);//set mmc0-clk to high
- gpio_direction_output(RK29_PIN1_PD1,GPIO_HIGH);//set mmc0-cmd to high.
- gpio_direction_output(RK29_PIN1_PD2,GPIO_HIGH);//set mmc0-data0 to high.
- gpio_direction_output(RK29_PIN1_PD3,GPIO_HIGH);//set mmc0-data1 to high.
- gpio_direction_output(RK29_PIN1_PD4,GPIO_HIGH);//set mmc0-data2 to high.
- gpio_direction_output(RK29_PIN1_PD5,GPIO_HIGH);//set mmc0-data3 to high.
-
- mdelay(30);
- }
- else
- {
- rk29_mux_api_set(GPIO1D0_SDMMC0CLKOUT_NAME, GPIO1H_GPIO1_D0);
- gpio_request(RK29_PIN1_PD0, "mmc0-clk");
- gpio_direction_output(RK29_PIN1_PD0,GPIO_LOW);//set mmc0-clk to low.
-
- rk29_mux_api_set(GPIO1D1_SDMMC0CMD_NAME, GPIO1H_GPIO1_D1);
- gpio_request(RK29_PIN1_PD1, "mmc0-cmd");
- gpio_direction_output(RK29_PIN1_PD1,GPIO_LOW);//set mmc0-cmd to low.
-
- rk29_mux_api_set(GPIO1D2_SDMMC0DATA0_NAME, GPIO1H_GPIO1D2);
- gpio_request(RK29_PIN1_PD2, "mmc0-data0");
- gpio_direction_output(RK29_PIN1_PD2,GPIO_LOW);//set mmc0-data0 to low.
-
- rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_GPIO1D3);
- gpio_request(RK29_PIN1_PD3, "mmc0-data1");
- gpio_direction_output(RK29_PIN1_PD3,GPIO_LOW);//set mmc0-data1 to low.
-
- rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_GPIO1D4);
- gpio_request(RK29_PIN1_PD4, "mmc0-data2");
- gpio_direction_output(RK29_PIN1_PD4,GPIO_LOW);//set mmc0-data2 to low.
-
- rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_GPIO1D5);
- gpio_request(RK29_PIN1_PD5, "mmc0-data3");
- gpio_direction_output(RK29_PIN1_PD5,GPIO_LOW);//set mmc0-data3 to low.
-
- mdelay(30);
- }
- #endif
- }
- break;
-
- case 1://mmc1
- {
- #ifdef CONFIG_SDMMC1_RK29
- if(on)
- {
- gpio_direction_output(RK29_PIN1_PC7,GPIO_HIGH);//set mmc1-clk to high
- gpio_direction_output(RK29_PIN1_PC2,GPIO_HIGH);//set mmc1-cmd to high.
- gpio_direction_output(RK29_PIN1_PC3,GPIO_HIGH);//set mmc1-data0 to high.
- gpio_direction_output(RK29_PIN1_PC4,GPIO_HIGH);//set mmc1-data1 to high.
- gpio_direction_output(RK29_PIN1_PC5,GPIO_HIGH);//set mmc1-data2 to high.
- gpio_direction_output(RK29_PIN1_PC6,GPIO_HIGH);//set mmc1-data3 to high.
- mdelay(100);
- }
- else
- {
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_GPIO1C7);
- gpio_request(RK29_PIN1_PC7, "mmc1-clk");
- gpio_direction_output(RK29_PIN1_PC7,GPIO_LOW);//set mmc1-clk to low.
-
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_GPIO1C2);
- gpio_request(RK29_PIN1_PC2, "mmc1-cmd");
- gpio_direction_output(RK29_PIN1_PC2,GPIO_LOW);//set mmc1-cmd to low.
-
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_GPIO1C3);
- gpio_request(RK29_PIN1_PC3, "mmc1-data0");
- gpio_direction_output(RK29_PIN1_PC3,GPIO_LOW);//set mmc1-data0 to low.
-
- mdelay(100);
- }
- #endif
- }
- break;
-
- case 2: //mmc2
- break;
-
- default:
- break;
- }
-}
-
-
-static void rk29_sdmmc_set_iomux_mmc0(unsigned int bus_width)
-{
- switch (bus_width)
- {
-
- case 1://SDMMC_CTYPE_4BIT:
- {
- rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_SDMMC0_DATA1);
- rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_SDMMC0_DATA2);
- rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_SDMMC0_DATA3);
- }
- break;
-
- case 0x10000://SDMMC_CTYPE_8BIT:
- break;
- case 0xFFFF: //gpio_reset
- {
- rk29_mux_api_set(GPIO5D5_SDMMC0PWREN_NAME, GPIO5H_GPIO5D5);
- gpio_request(RK29_PIN5_PD5,"sdmmc-power");
- gpio_direction_output(RK29_PIN5_PD5,GPIO_HIGH); //power-off
-
- rk29_sdmmc_gpio_open(0, 0);
-
- gpio_direction_output(RK29_PIN5_PD5,GPIO_LOW); //power-on
-
- rk29_sdmmc_gpio_open(0, 1);
- }
- break;
-
- default: //case 0://SDMMC_CTYPE_1BIT:
- {
- rk29_mux_api_set(GPIO1D1_SDMMC0CMD_NAME, GPIO1H_SDMMC0_CMD);
- rk29_mux_api_set(GPIO1D0_SDMMC0CLKOUT_NAME, GPIO1H_SDMMC0_CLKOUT);
- rk29_mux_api_set(GPIO1D2_SDMMC0DATA0_NAME, GPIO1H_SDMMC0_DATA0);
-
- rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_GPIO1D3);
- gpio_request(RK29_PIN1_PD3, "mmc0-data1");
- gpio_direction_output(RK29_PIN1_PD3,GPIO_HIGH);
-
- rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_GPIO1D4);
- gpio_request(RK29_PIN1_PD4, "mmc0-data2");
- gpio_direction_output(RK29_PIN1_PD4,GPIO_HIGH);
-
- rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_GPIO1D5);
- gpio_request(RK29_PIN1_PD5, "mmc0-data3");
- gpio_direction_output(RK29_PIN1_PD5,GPIO_HIGH);
- }
- break;
- }
-}
-
-static void rk29_sdmmc_set_iomux_mmc1(unsigned int bus_width)
-{
-#if 0
- switch (bus_width)
- {
-
- case 1://SDMMC_CTYPE_4BIT:
- {
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);
- rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_SDMMC1_DATA1);
- rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_SDMMC1_DATA2);
- rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_SDMMC1_DATA3);
- }
- break;
-
- case 0x10000://SDMMC_CTYPE_8BIT:
- break;
- case 0xFFFF:
- {
- rk29_sdmmc_gpio_open(1, 0);
- rk29_sdmmc_gpio_open(1, 1);
- }
- break;
-
- default: //case 0://SDMMC_CTYPE_1BIT:
- {
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);
-
- rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_GPIO1C4);
- gpio_request(RK29_PIN1_PC4, "mmc1-data1");
- gpio_direction_output(RK29_PIN1_PC4,GPIO_HIGH);
-
- rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_GPIO1C5);
- gpio_request(RK29_PIN1_PC5, "mmc1-data2");
- gpio_direction_output(RK29_PIN1_PC5,GPIO_HIGH);
-
- rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_GPIO1C6);
- gpio_request(RK29_PIN1_PC6, "mmc1-data3");
- gpio_direction_output(RK29_PIN1_PC6,GPIO_HIGH);
-
- }
- break;
- }
-#else
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);
- rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_SDMMC1_DATA1);
- rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_SDMMC1_DATA2);
- rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_SDMMC1_DATA3);
-
-#endif
-}
-
-static void rk29_sdmmc_set_iomux_mmc2(unsigned int bus_width)
-{
- ;//
-}
-
-static void rk29_sdmmc_set_iomux(int device_id, unsigned int bus_width)
-{
- switch(device_id)
- {
- case 0:
- #ifdef CONFIG_SDMMC0_RK29
- rk29_sdmmc_set_iomux_mmc0(bus_width);
- #endif
- break;
- case 1:
- #ifdef CONFIG_SDMMC1_RK29
- rk29_sdmmc_set_iomux_mmc1(bus_width);
- #endif
- break;
- case 2:
- rk29_sdmmc_set_iomux_mmc2(bus_width);
- break;
- default:
- break;
- }
-}
-#endif
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
- rk29_mux_api_set(GPIO1D1_SDMMC0CMD_NAME, GPIO1H_SDMMC0_CMD);
- rk29_mux_api_set(GPIO1D0_SDMMC0CLKOUT_NAME, GPIO1H_SDMMC0_CLKOUT);
- rk29_mux_api_set(GPIO1D2_SDMMC0DATA0_NAME, GPIO1H_SDMMC0_DATA0);
- rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_SDMMC0_DATA1);
- rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_SDMMC0_DATA2);
- rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_SDMMC0_DATA3);
-#ifdef CONFIG_SDMMC_RK29_OLD
- rk29_mux_api_set(GPIO2A2_SDMMC0DETECTN_NAME, GPIO2L_GPIO2A2);
-#else
- rk29_mux_api_set(GPIO2A2_SDMMC0DETECTN_NAME, GPIO2L_SDMMC0_DETECT_N);//Modifyed by xbw.
-#endif
- rk29_mux_api_set(GPIO5D5_SDMMC0PWREN_NAME, GPIO5H_GPIO5D5); ///GPIO5H_SDMMC0_PWR_EN); ///GPIO5H_GPIO5D5);
- gpio_request(RK29_PIN5_PD5,"sdmmc");
- gpio_set_value(RK29_PIN5_PD5,GPIO_HIGH);
- mdelay(100);
- gpio_set_value(RK29_PIN5_PD5,GPIO_LOW);
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail = (MMC_VDD_25_26|MMC_VDD_26_27|MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30|
- MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33|
- MMC_VDD_33_34|MMC_VDD_34_35| MMC_VDD_35_36),
- .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
- .detect_irq = INVALID_GPIO,
- .enable_sd_wakeup = 0,
-};
-#endif
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);
- rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_SDMMC1_DATA1);
- rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_SDMMC1_DATA2);
- rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_SDMMC1_DATA3);
- //rk29_mux_api_set(GPIO1C0_UART0CTSN_SDMMC1DETECTN_NAME, GPIO1H_SDMMC1_DETECT_N);
- return 0;
-}
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
-static int rk29sdk_wifi_status(struct device *dev);
-static int rk29sdk_wifi_status_register(void (*callback)(int card_presend, void *dev_id), void *dev_id);
-#endif
-
-#define RK29SDK_WIFI_SDIO_CARD_DETECT_N RK29_PIN1_PD6
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail = (MMC_VDD_25_26|MMC_VDD_26_27|MMC_VDD_27_28|MMC_VDD_28_29|
- MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32|
- MMC_VDD_32_33|MMC_VDD_33_34),
- .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_SDIO_IRQ|
- MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc1_cfg_gpio,
- .dma_name = "sdio",
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-#if 0
- .detect_irq = RK29SDK_WIFI_SDIO_CARD_DETECT_N,
-#endif
-};
-#endif
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
-#define RK29SDK_WIFI_BT_GPIO_POWER_N RK29_PIN5_PD6
-#define RK29SDK_WIFI_GPIO_RESET_N RK29_PIN6_PC0
-#define RK29SDK_BT_GPIO_RESET_N RK29_PIN6_PC7
-
-static int rk29sdk_wifi_cd = 0; /* wifi virtual 'card detect' status */
-static void (*wifi_status_cb)(int card_present, void *dev_id);
-static void *wifi_status_cb_devid;
-int rk29sdk_wifi_power_state = 0;
-int rk29sdk_bt_power_state = 0;
-
-static int rk29sdk_wifi_status(struct device *dev)
-{
- return rk29sdk_wifi_cd;
-}
-
-static int rk29sdk_wifi_status_register(void (*callback)(int card_present, void *dev_id), void *dev_id)
-{
- if(wifi_status_cb)
- return -EAGAIN;
- wifi_status_cb = callback;
- wifi_status_cb_devid = dev_id;
- return 0;
-}
-
-static int rk29sdk_wifi_bt_gpio_control_init(void)
-{
- if (gpio_request(RK29SDK_WIFI_BT_GPIO_POWER_N, "wifi_bt_power")) {
- pr_info("%s: request wifi_bt power gpio failed\n", __func__);
- return -1;
- }
-
- if (gpio_request(RK29SDK_WIFI_GPIO_RESET_N, "wifi reset")) {
- pr_info("%s: request wifi reset gpio failed\n", __func__);
- gpio_free(RK29SDK_WIFI_BT_GPIO_POWER_N);
- return -1;
- }
-
- if (gpio_request(RK29SDK_BT_GPIO_RESET_N, "bt reset")) {
- pr_info("%s: request bt reset gpio failed\n", __func__);
- gpio_free(RK29SDK_WIFI_GPIO_RESET_N);
- return -1;
- }
-
- gpio_direction_output(RK29SDK_WIFI_BT_GPIO_POWER_N, GPIO_LOW);
- gpio_direction_output(RK29SDK_WIFI_GPIO_RESET_N, GPIO_LOW);
- gpio_direction_output(RK29SDK_BT_GPIO_RESET_N, GPIO_LOW);
-
- pr_info("%s: init finished\n",__func__);
-
- return 0;
-}
-
-static int rk29sdk_wifi_power(int on)
-{
- pr_info("%s: %d\n", __func__, on);
- if (on){
- gpio_set_value(RK29SDK_WIFI_BT_GPIO_POWER_N, GPIO_HIGH);
- gpio_set_value(RK29SDK_WIFI_GPIO_RESET_N, GPIO_HIGH);
- mdelay(100);
- pr_info("wifi turn on power\n");
- }else{
- if (!rk29sdk_bt_power_state){
- gpio_set_value(RK29SDK_WIFI_BT_GPIO_POWER_N, GPIO_LOW);
- mdelay(100);
- pr_info("wifi shut off power\n");
- }else
- {
- pr_info("wifi shouldn't shut off power, bt is using it!\n");
- }
- gpio_set_value(RK29SDK_WIFI_GPIO_RESET_N, GPIO_LOW);
-
- }
-
- rk29sdk_wifi_power_state = on;
- return 0;
-}
-
-static int rk29sdk_wifi_reset_state;
-static int rk29sdk_wifi_reset(int on)
-{
- pr_info("%s: %d\n", __func__, on);
- gpio_set_value(RK29SDK_WIFI_GPIO_RESET_N, on);
- mdelay(100);
- rk29sdk_wifi_reset_state = on;
- return 0;
-}
-
-int rk29sdk_wifi_set_carddetect(int val)
-{
- pr_info("%s:%d\n", __func__, val);
- rk29sdk_wifi_cd = val;
- if (wifi_status_cb){
- wifi_status_cb(val, wifi_status_cb_devid);
- }else {
- pr_warning("%s, nobody to notify\n", __func__);
- }
- return 0;
-}
-EXPORT_SYMBOL(rk29sdk_wifi_set_carddetect);
-
-static struct wifi_mem_prealloc wifi_mem_array[PREALLOC_WLAN_SEC_NUM] = {
- {NULL, (WLAN_SECTION_SIZE_0 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_1 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_2 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_3 + PREALLOC_WLAN_SECTION_HEADER)}
-};
-
-static void *rk29sdk_mem_prealloc(int section, unsigned long size)
-{
- if (section == PREALLOC_WLAN_SEC_NUM)
- return wlan_static_skb;
-
- if ((section < 0) || (section > PREALLOC_WLAN_SEC_NUM))
- return NULL;
-
- if (wifi_mem_array[section].size < size)
- return NULL;
-
- return wifi_mem_array[section].mem_ptr;
-}
-
-int __init rk29sdk_init_wifi_mem(void)
-{
- int i;
- int j;
-
- for (i = 0 ; i < WLAN_SKB_BUF_NUM ; i++) {
- wlan_static_skb[i] = dev_alloc_skb(
- ((i < (WLAN_SKB_BUF_NUM / 2)) ? 4096 : 8192));
-
- if (!wlan_static_skb[i])
- goto err_skb_alloc;
- }
-
- for (i = 0 ; i < PREALLOC_WLAN_SEC_NUM ; i++) {
- wifi_mem_array[i].mem_ptr =
- kmalloc(wifi_mem_array[i].size, GFP_KERNEL);
-
- if (!wifi_mem_array[i].mem_ptr)
- goto err_mem_alloc;
- }
- return 0;
-
- err_mem_alloc:
- pr_err("Failed to mem_alloc for WLAN\n");
- for (j = 0 ; j < i ; j++)
- kfree(wifi_mem_array[j].mem_ptr);
-
- i = WLAN_SKB_BUF_NUM;
-
- err_skb_alloc:
- pr_err("Failed to skb_alloc for WLAN\n");
- for (j = 0 ; j < i ; j++)
- dev_kfree_skb(wlan_static_skb[j]);
-
- return -ENOMEM;
-}
-
-static struct wifi_platform_data rk29sdk_wifi_control = {
- .set_power = rk29sdk_wifi_power,
- .set_reset = rk29sdk_wifi_reset,
- .set_carddetect = rk29sdk_wifi_set_carddetect,
- .mem_prealloc = rk29sdk_mem_prealloc,
-};
-static struct platform_device rk29sdk_wifi_device = {
- .name = "bcm4329_wlan",
- .id = 1,
- .dev = {
- .platform_data = &rk29sdk_wifi_control,
- },
-};
-#endif
-
-
-/* bluetooth rfkill device */
-static struct platform_device rk29sdk_rfkill = {
- .name = "rk29sdk_rfkill",
- .id = -1,
-};
-
-
-#ifdef CONFIG_VIVANTE
-static struct resource resources_gpu[] = {
- [0] = {
- .name = "gpu_irq",
- .start = IRQ_GPU,
- .end = IRQ_GPU,
- .flags = IORESOURCE_IRQ,
- },
- [1] = {
- .name = "gpu_base",
- .start = RK29_GPU_PHYS,
- .end = RK29_GPU_PHYS + RK29_GPU_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "gpu_mem",
- .start = PMEM_GPU_BASE,
- .end = PMEM_GPU_BASE + PMEM_GPU_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-static struct platform_device rk29_device_gpu = {
- .name = "galcore",
- .id = 0,
- .num_resources = ARRAY_SIZE(resources_gpu),
- .resource = resources_gpu,
-};
-#endif
-#ifdef CONFIG_KEYS_RK29
-extern struct rk29_keys_platform_data rk29_keys_pdata;
-static struct platform_device rk29_device_keys = {
- .name = "rk29-keypad",
- .id = -1,
- .dev = {
- .platform_data = &rk29_keys_pdata,
- },
-};
-#endif
-
-#if CONFIG_ANDROID_TIMED_GPIO
-static struct timed_gpio timed_gpios[] = {
- {
- .name = "vibrator",
- .gpio = RK29_PIN1_PB5,
- .max_timeout = 1000,
- .active_low = 0,
- .adjust_time =20, //adjust for diff product
- },
-};
-
-struct timed_gpio_platform_data rk29_vibrator_info = {
- .num_gpios = 1,
- .gpios = timed_gpios,
-};
-
-struct platform_device rk29_device_vibrator ={
- .name = "timed-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_vibrator_info,
- },
-
-};
-#endif
-
-static void __init rk29_board_iomux_init(void)
-{
- int err;
-
-#ifdef CONFIG_UART1_RK29
- //disable uart1 pull down
- rk29_mux_api_set(GPIO2A5_UART1SOUT_NAME, GPIO2L_GPIO2A5);
- rk29_mux_api_set(GPIO2A4_UART1SIN_NAME, GPIO2L_GPIO2A4);
-
- gpio_request(RK29_PIN2_PA5, NULL);
- gpio_request(RK29_PIN2_PA4, NULL);
-
- gpio_pull_updown(RK29_PIN2_PA5, PullDisable);
- gpio_pull_updown(RK29_PIN2_PA4, PullDisable);
-
- rk29_mux_api_set(GPIO2A5_UART1SOUT_NAME, GPIO2L_UART1_SOUT);
- rk29_mux_api_set(GPIO2A4_UART1SIN_NAME, GPIO2L_UART1_SIN);
-
- gpio_free(RK29_PIN2_PA5);
- gpio_free(RK29_PIN2_PA4);
-#endif
-
- #if CONFIG_ANDROID_TIMED_GPIO
- rk29_mux_api_set(GPIO1B5_PWM0_NAME, GPIO1L_GPIO1B5);//for timed gpio
- #endif
- #ifdef CONFIG_RK29_PWM_REGULATOR
- rk29_mux_api_set(REGULATOR_PWM_MUX_NAME,REGULATOR_PWM_MUX_MODE);
- #endif
- #ifdef CONFIG_RK_HEADSET_DET
- rk29_mux_api_set(GPIO3A6_SMCADDR14_HOSTDATA14_NAME,GPIO3L_GPIO3A6);
- #endif
-
- rk29_mux_api_set(GPIO4C0_RMIICLKOUT_RMIICLKIN_NAME,GPIO4H_GPIO4C0);
-
- err = gpio_request(RK29_PIN4_PC0, "clk27M_control");
- if (err) {
- gpio_free(RK29_PIN4_PC0);
- printk("-------request RK29_PIN4_PC0 fail--------\n");
- return -1;
- }
- //phy power down
-
- #if defined (CONFIG_RK29_WORKING_POWER_MANAGEMENT)
- gpio_direction_output(RK29_PIN4_PC0, GPIO_HIGH);
- gpio_set_value(RK29_PIN4_PC0, GPIO_HIGH);
- #else
- gpio_direction_output(RK29_PIN4_PC0, GPIO_LOW);
- gpio_set_value(RK29_PIN4_PC0, GPIO_LOW);
- #endif
-
- rk29_mux_api_set(GPIO4C5_RMIICSRDVALID_MIIRXDVALID_NAME,GPIO4H_GPIO4C5);
-
- err = gpio_request(RK29_PIN4_PC5, "clk24M_control");
- if (err) {
- gpio_free(RK29_PIN4_PC5);
- printk("-------request RK29_PIN4_PC5 fail--------\n");
- return -1;
- }
- //phy power down
- gpio_direction_output(RK29_PIN4_PC5, GPIO_LOW);
- gpio_set_value(RK29_PIN4_PC5, GPIO_LOW);
-}
-
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_UART1_RK29
- &rk29_device_uart1,
-#endif
-#ifdef CONFIG_UART0_RK29
- &rk29_device_uart0,
-#endif
-#ifdef CONFIG_UART2_RK29
- &rk29_device_uart2,
-#endif
-#ifdef CONFIG_UART3_RK29
- &rk29_device_uart3,
-#endif
-
-#ifdef CONFIG_RK29_PWM_REGULATOR
- &rk29_device_pwm_regulator,
-#endif
-#ifdef CONFIG_SPIM0_RK29
- &rk29xx_device_spi0m,
-#endif
-#ifdef CONFIG_SPIM1_RK29
- &rk29xx_device_spi1m,
-#endif
-#ifdef CONFIG_ADC_RK29
- &rk29_device_adc,
-#endif
-#ifdef CONFIG_I2C0_RK29
- &rk29_device_i2c0,
-#endif
-#ifdef CONFIG_I2C1_RK29
- &rk29_device_i2c1,
-#endif
-#ifdef CONFIG_I2C2_RK29
- &rk29_device_i2c2,
-#endif
-#ifdef CONFIG_I2C3_RK29
- &rk29_device_i2c3,
-#endif
-
-#ifdef CONFIG_SND_RK29_SOC_I2S_2CH
- &rk29_device_iis_2ch,
-#endif
-#ifdef CONFIG_SND_RK29_SOC_I2S_8CH
- &rk29_device_iis_8ch,
-#endif
-
-#ifdef CONFIG_MFD_WM8994
- &wm8994_fixed_voltage0,
- &wm8994_fixed_voltage1,
-#endif
-
-#ifdef CONFIG_KEYS_RK29
- &rk29_device_keys,
-#endif
-#ifdef CONFIG_SDMMC0_RK29
- &rk29_device_sdmmc0,
-#endif
-#ifdef CONFIG_SDMMC1_RK29
- &rk29_device_sdmmc1,
-#endif
-
-#ifdef CONFIG_MTD_NAND_RK29XX
- &rk29xx_device_nand,
-#endif
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- &rk29sdk_wifi_device,
-#endif
-
-#ifdef CONFIG_BT
- &rk29sdk_rfkill,
-#endif
-
-#if defined(CONFIG_MTK23D)
- &rk2818_device_mtk23d,
-#endif
-
-#ifdef CONFIG_MTD_NAND_RK29
- &rk29_device_nand,
-#endif
-
-#ifdef CONFIG_FB_RK29
- &rk29_device_fb,
- &rk29_device_dma_cpy,
-#endif
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- &rk29_device_backlight,
-#endif
-#ifdef CONFIG_BACKLIGHT_AW9364
- &aw9364_device_backlight,
-#endif
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
- &rk29_device_gpio_leds,
-#endif
-#ifdef CONFIG_RK29_VMAC
- &rk29_device_vmac,
-#endif
-#ifdef CONFIG_VIVANTE
- &rk29_device_gpu,
-#endif
-#ifdef CONFIG_VIDEO_RK29
- &rk29_device_camera, /* ddl@rock-chips.com : camera support */
- #if (CONFIG_SENSOR_IIC_ADDR_0 != 0x00)
- &rk29_soc_camera_pdrv_0,
- #endif
- &rk29_soc_camera_pdrv_1,
- &android_pmem_cam_device,
-#endif
-#ifdef CONFIG_ION
- &rk29_ion_device,
-#endif
- &android_pmem_device,
- &rk29_vpu_mem_device,
-#ifdef CONFIG_USB20_OTG
- &rk29_device_usb20_otg,
-#endif
-#ifdef CONFIG_USB20_HOST
- &rk29_device_usb20_host,
-#endif
-#ifdef CONFIG_USB11_HOST
- &rk29_device_usb11_host,
-#endif
-#ifdef CONFIG_USB_ANDROID
- &android_usb_device,
- &usb_mass_storage_device,
-#endif
-#ifdef CONFIG_RK29_IPP
- &rk29_device_ipp,
-#endif
-#ifdef CONFIG_VIDEO_RK29XX_VOUT
- &rk29_v4l2_output_devce,
-#endif
-#ifdef CONFIG_RK_HEADSET_DET
- &rk_device_headset,
-#endif
-#ifdef CONFIG_RK29_GPS
- &rk29_device_gps,
-#endif
-#ifdef CONFIG_ANDROID_TIMED_GPIO
- &rk29_device_vibrator,
-#endif
-};
-
-#ifdef CONFIG_RK29_VMAC
-/*****************************************************************************************
- * vmac devices
- * author: lyx@rock-chips.com
- *****************************************************************************************/
-static int rk29_vmac_register_set(void)
-{
- //config rk29 vmac as rmii, 100MHz
- u32 value= readl(RK29_GRF_BASE + 0xbc);
- value = (value & 0xfff7ff) | (0x400);
- writel(value, RK29_GRF_BASE + 0xbc);
- return 0;
-}
-
-static int rk29_rmii_io_init(void)
-{
- int err;
-
- //phy power gpio
- err = gpio_request(RK29_PIN6_PB0, "phy_power_en");
- if (err) {
- gpio_free(RK29_PIN6_PB0);
- printk("-------request RK29_PIN6_PB0 fail--------\n");
- return -1;
- }
- //phy power down
- gpio_direction_output(RK29_PIN6_PB0, GPIO_LOW);
- gpio_set_value(RK29_PIN6_PB0, GPIO_LOW);
-
- return 0;
-}
-
-static int rk29_rmii_io_deinit(void)
-{
- //phy power down
- gpio_direction_output(RK29_PIN6_PB0, GPIO_LOW);
- gpio_set_value(RK29_PIN6_PB0, GPIO_LOW);
- //free
- gpio_free(RK29_PIN6_PB0);
- return 0;
-}
-
-static int rk29_rmii_power_control(int enable)
-{
- if (enable) {
- //enable phy power
- gpio_direction_output(RK29_PIN6_PB0, GPIO_HIGH);
- gpio_set_value(RK29_PIN6_PB0, GPIO_HIGH);
- }
- else {
- gpio_direction_output(RK29_PIN6_PB0, GPIO_LOW);
- gpio_set_value(RK29_PIN6_PB0, GPIO_LOW);
- }
- return 0;
-}
-
-struct rk29_vmac_platform_data rk29_vmac_pdata = {
- .vmac_register_set = rk29_vmac_register_set,
- .rmii_io_init = rk29_rmii_io_init,
- .rmii_io_deinit = rk29_rmii_io_deinit,
- .rmii_power_control = rk29_rmii_power_control,
-};
-#endif
-
-/*****************************************************************************************
- * spi devices
- * author: cmc@rock-chips.com
- *****************************************************************************************/
-#define SPI_CHIPSELECT_NUM 2
-static struct spi_cs_gpio rk29xx_spi0_cs_gpios[SPI_CHIPSELECT_NUM] = {
- {
- .name = "spi0 cs0",
- .cs_gpio = RK29_PIN2_PC1,
- .cs_iomux_name = GPIO2C1_SPI0CSN0_NAME,
- .cs_iomux_mode = GPIO2H_SPI0_CSN0,
- },
- {
- .name = "spi0 cs1",
- .cs_gpio = RK29_PIN1_PA4,
- .cs_iomux_name = GPIO1A4_EMMCWRITEPRT_SPI0CS1_NAME,//if no iomux,set it NULL
- .cs_iomux_mode = GPIO1L_SPI0_CSN1,
- }
-};
-
-static struct spi_cs_gpio rk29xx_spi1_cs_gpios[SPI_CHIPSELECT_NUM] = {
- {
- .name = "spi1 cs0",
- .cs_gpio = RK29_PIN2_PC5,
- .cs_iomux_name = GPIO2C5_SPI1CSN0_NAME,
- .cs_iomux_mode = GPIO2H_SPI1_CSN0,
- },
- {
- .name = "spi1 cs1",
- .cs_gpio = RK29_PIN1_PA3,
- .cs_iomux_name = GPIO1A3_EMMCDETECTN_SPI1CS1_NAME,//if no iomux,set it NULL
- .cs_iomux_mode = GPIO1L_SPI1_CSN1,
- }
-};
-
-static int spi_io_init(struct spi_cs_gpio *cs_gpios, int cs_num)
-{
-#if 1
- int i;
- if (cs_gpios) {
- for (i=0; i<cs_num; i++) {
- rk29_mux_api_set(cs_gpios[i].cs_iomux_name, cs_gpios[i].cs_iomux_mode);
- }
- }
-#endif
- return 0;
-}
-
-static int spi_io_deinit(struct spi_cs_gpio *cs_gpios, int cs_num)
-{
- return 0;
-}
-
-static int spi_io_fix_leakage_bug(void)
-{
-#if 0
- gpio_direction_output(RK29_PIN2_PC1, GPIO_LOW);
-#endif
- return 0;
-}
-
-static int spi_io_resume_leakage_bug(void)
-{
-#if 0
- gpio_direction_output(RK29_PIN2_PC1, GPIO_HIGH);
-#endif
- return 0;
-}
-
-struct rk29xx_spi_platform_data rk29xx_spi0_platdata = {
- .num_chipselect = SPI_CHIPSELECT_NUM,
- .chipselect_gpios = rk29xx_spi0_cs_gpios,
- .io_init = spi_io_init,
- .io_deinit = spi_io_deinit,
- .io_fix_leakage_bug = spi_io_fix_leakage_bug,
- .io_resume_leakage_bug = spi_io_resume_leakage_bug,
-};
-
-struct rk29xx_spi_platform_data rk29xx_spi1_platdata = {
- .num_chipselect = SPI_CHIPSELECT_NUM,
- .chipselect_gpios = rk29xx_spi1_cs_gpios,
- .io_init = spi_io_init,
- .io_deinit = spi_io_deinit,
- .io_fix_leakage_bug = spi_io_fix_leakage_bug,
- .io_resume_leakage_bug = spi_io_resume_leakage_bug,
-};
-
-
-/*****************************************************************************************
- * xpt2046 touch panel
- * author: hhb@rock-chips.com
- *****************************************************************************************/
-#if defined(CONFIG_TOUCHSCREEN_XPT2046_NORMAL_SPI) || defined(CONFIG_TOUCHSCREEN_XPT2046_TSLIB_SPI)
-#define XPT2046_GPIO_INT RK29_PIN4_PD5 //中断???#define DEBOUNCE_REPTIME 3
-
-static struct xpt2046_platform_data xpt2046_info = {
- .model = 2046,
- .keep_vref_on = 1,
- .swap_xy = 0,
- .debounce_max = 7,
- .debounce_rep = DEBOUNCE_REPTIME,
- .debounce_tol = 20,
- .gpio_pendown = XPT2046_GPIO_INT,
- .pendown_iomux_name = GPIO4D5_CPUTRACECTL_NAME,
- .pendown_iomux_mode = GPIO4H_GPIO4D5,
- .touch_virtualkey_length = 60,
- .penirq_recheck_delay_usecs = 1,
-#if defined(CONFIG_TOUCHSCREEN_480X800)
- .x_min = 0,
- .x_max = 480,
- .y_min = 0,
- .y_max = 800,
- .touch_ad_top = 3940,
- .touch_ad_bottom = 310,
- .touch_ad_left = 3772,
- .touch_ad_right = 340,
-#elif defined(CONFIG_TOUCHSCREEN_800X480)
- .x_min = 0,
- .x_max = 800,
- .y_min = 0,
- .y_max = 480,
- .touch_ad_top = 2447,
- .touch_ad_bottom = 207,
- .touch_ad_left = 5938,
- .touch_ad_right = 153,
-#elif defined(CONFIG_TOUCHSCREEN_320X480)
- .x_min = 0,
- .x_max = 320,
- .y_min = 0,
- .y_max = 480,
- .touch_ad_top = 3166,
- .touch_ad_bottom = 256,
- .touch_ad_left = 3658,
- .touch_ad_right = 380,
-#endif
-};
-#elif defined(CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI)
-static struct xpt2046_platform_data xpt2046_info = {
- .model = 2046,
- .keep_vref_on = 1,
- .swap_xy = 0,
- .debounce_max = 7,
- .debounce_rep = DEBOUNCE_REPTIME,
- .debounce_tol = 20,
- .gpio_pendown = XPT2046_GPIO_INT,
- .pendown_iomux_name = GPIO4D5_CPUTRACECTL_NAME,
- .pendown_iomux_mode = GPIO4H_GPIO4D5,
- .touch_virtualkey_length = 60,
- .penirq_recheck_delay_usecs = 1,
-
-#if defined(CONFIG_TOUCHSCREEN_480X800)
- .x_min = 0,
- .x_max = 480,
- .y_min = 0,
- .y_max = 800,
- .screen_x = { 70, 410, 70, 410, 240},
- .screen_y = { 50, 50, 740, 740, 400},
- .uncali_x_default = { 3267, 831, 3139, 715, 1845 },
- .uncali_y_default = { 3638, 3664, 564, 591, 2087 },
-#elif defined(CONFIG_TOUCHSCREEN_800X480)
- .x_min = 0,
- .x_max = 800,
- .y_min = 0,
- .y_max = 480,
- .screen_x[5] = { 50, 750, 50, 750, 400};
- .screen_y[5] = { 40, 40, 440, 440, 240};
- .uncali_x_default[5] = { 438, 565, 3507, 3631, 2105 };
- .uncali_y_default[5] = { 3756, 489, 3792, 534, 2159 };
-#elif defined(CONFIG_TOUCHSCREEN_320X480)
- .x_min = 0,
- .x_max = 320,
- .y_min = 0,
- .y_max = 480,
- .screen_x[5] = { 50, 270, 50, 270, 160};
- .screen_y[5] = { 40, 40, 440, 440, 240};
- .uncali_x_default[5] = { 812, 3341, 851, 3371, 2183 };
- .uncali_y_default[5] = { 442, 435, 3193, 3195, 2004 };
-#endif
-};
-#endif
-
-static struct spi_board_info board_spi_devices[] = {
-#if defined(CONFIG_TOUCHSCREEN_XPT2046_SPI)
- {
- .modalias = "xpt2046_ts",
- .chip_select = 0,// 2,
- .max_speed_hz = 125 * 1000 * 26,/* (max sample rate @ 3V) * (cmd + data + overhead) */
- .bus_num = 0,
- .irq = XPT2046_GPIO_INT,
- .platform_data = &xpt2046_info,
- },
-#endif
-
-#if defined(CONFIG_MFD_WM831X_SPI)
- {
- .modalias = "wm8310",
- .chip_select = 1,
- .max_speed_hz = 2*1000*1000,
- .bus_num = 1,
- .irq = RK29_PIN4_PD0,
- .platform_data = &wm831x_platdata,
- },
-#endif
-
-};
-
-
-/**********************************************************************************************
- *
- * The virtual keys for android "back", "home", "menu", "search", these four keys are touch key
- * on the touch screen panel. (added by hhb@rock-chips.com 2011.03.31)
- *
- ***********************************************************************************************/
-static ssize_t rk29xx_virtual_keys_show(struct kobject *kobj,
- struct kobj_attribute *attr, char *buf)
-{
-#if (defined(CONFIG_TOUCHSCREEN_XPT2046_SPI) && defined(CONFIG_TOUCHSCREEN_480X800)) \
- || defined(CONFIG_TOUCHSCREEN_HX8520_IIC) || defined(CONFIG_TOUCHSCREEN_GT801_IIC)
- /* center: x: home: 50, menu: 184, back: 315, search 435, y: 830*/
- /* centerx;centery;width;height; */
- return sprintf(buf,
- __stringify(EV_KEY) ":" __stringify(KEY_BACK) ":315:815:120:50" //":50:830:98:50" //":210:796:98:50"
- ":" __stringify(EV_KEY) ":" __stringify(KEY_MENU) ":85:815:88:50" // ":184:830:120:50" // ":435:796:120:50"
- ":" __stringify(EV_KEY) ":" __stringify(KEY_HOME) ":184:815:100:50" //":315:830:100:50" //":320:796:100:50"
- ":" __stringify(EV_KEY) ":" __stringify(KEY_SEARCH) ":435:815:88:50" //":50:815:98:50" // //":85:796:88:50"
- "\n");
-#endif
- return 0;
-}
-
-static struct kobj_attribute rk29xx_virtual_keys_attr = {
- .attr = {
-#if defined(CONFIG_TOUCHSCREEN_XPT2046_SPI)
- .name = "virtualkeys.xpt2046-touchscreen",
-#elif defined(CONFIG_TOUCHSCREEN_HX8520_IIC)
- .name = "virtualkeys.hx8520-touchscreen",
-#elif defined(CONFIG_TOUCHSCREEN_GT801_IIC)
- .name = "virtualkeys.gt801-touchscreen",
-#elif defined(CONFIG_TOUCHSCREEN_ILI2102_IIC)
- .name = "virtualkeys.ili2102-touchscreen",
-#endif
-
-
- .mode = S_IRUGO,
- },
- .show = &rk29xx_virtual_keys_show,
-};
-
-static struct attribute *rk29xx_properties_attrs[] = {
- &rk29xx_virtual_keys_attr.attr,
- NULL
-};
-
-static struct attribute_group rk29xx_properties_attr_group = {
- .attrs = rk29xx_properties_attrs,
-};
-static int rk29xx_virtual_keys_init(void)
-{
- int ret;
- struct kobject *properties_kobj;
- printk("rk29xx_virtual_keys_init \n");
- properties_kobj = kobject_create_and_add("board_properties", NULL);
- if (properties_kobj)
- ret = sysfs_create_group(properties_kobj,
- &rk29xx_properties_attr_group);
- if (!properties_kobj || ret)
- {
- pr_err("failed to create board_properties\n");
- }
- return ret;
-}
-
-
-static void __init rk29_gic_init_irq(void)
-{
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38))
- gic_init(0, 32, (void __iomem *)RK29_GICPERI_BASE, (void __iomem *)RK29_GICCPU_BASE);
-#else
- gic_dist_init(0, (void __iomem *)RK29_GICPERI_BASE, 32);
- gic_cpu_init(0, (void __iomem *)RK29_GICCPU_BASE);
-#endif
-}
-
-static void __init machine_rk29_init_irq(void)
-{
- rk29_gic_init_irq();
- rk29_gpio_init();
-}
-
-#define POWER_ON_PIN RK29_PIN4_PA4
-
-static void rk29_pm_power_restart(void)
-{
- printk("%s,line=%d\n",__FUNCTION__,__LINE__);
- mdelay(2);
-#if defined(CONFIG_MFD_WM831X)
- wm831x_device_restart(gWm831x);
-#endif
-
-}
-
-static void rk29_pm_power_off(void)
-{
- printk(KERN_ERR "rk29_pm_power_off start...\n");
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
-#if defined(CONFIG_MFD_WM831X)
- if(wm831x_read_usb(gWm831x))
- rk29_pm_power_restart(); //if charging then restart
- else
- wm831x_device_shutdown(gWm831x);//else shutdown
-#endif
- while (1);
-}
-
-extern struct usb_mass_storage_platform_data mass_storage_pdata;
-static void __init machine_rk29_board_init(void)
-{
- rk29_board_iomux_init();
-
- gpio_request(POWER_ON_PIN,"poweronpin");
- gpio_set_value(POWER_ON_PIN, GPIO_HIGH);
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
- pm_power_off = rk29_pm_power_off;
- //arm_pm_restart = rk29_pm_power_restart;
-
- //mass_storage_pdata.nluns = 1;//change number of LUNS
-
- platform_add_devices(devices, ARRAY_SIZE(devices));
-#ifdef CONFIG_I2C0_RK29
- i2c_register_board_info(default_i2c0_data.bus_num, board_i2c0_devices,
- ARRAY_SIZE(board_i2c0_devices));
-#endif
-#ifdef CONFIG_I2C1_RK29
- i2c_register_board_info(default_i2c1_data.bus_num, board_i2c1_devices,
- ARRAY_SIZE(board_i2c1_devices));
-#endif
-#ifdef CONFIG_I2C2_RK29
- i2c_register_board_info(default_i2c2_data.bus_num, board_i2c2_devices,
- ARRAY_SIZE(board_i2c2_devices));
-#endif
-#ifdef CONFIG_I2C3_RK29
- i2c_register_board_info(default_i2c3_data.bus_num, board_i2c3_devices,
- ARRAY_SIZE(board_i2c3_devices));
-#endif
-
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- rk29sdk_wifi_bt_gpio_control_init();
- rk29sdk_init_wifi_mem();
-#endif
-
- rk29xx_virtual_keys_init();
-}
-
-static void __init machine_rk29_fixup(struct machine_desc *desc, struct tag *tags,
- char **cmdline, struct meminfo *mi)
-{
- mi->nr_banks = 1;
- mi->bank[0].start = RK29_SDRAM_PHYS;
- mi->bank[0].size = LINUX_SIZE;
-#if SDRAM_SIZE > SZ_512M
- mi->nr_banks = 2;
- mi->bank[1].start = RK29_SDRAM_PHYS + SZ_512M;
- mi->bank[1].size = SDRAM_SIZE - SZ_512M;
-#endif
-}
-
-static void __init machine_rk29_mapio(void)
-{
- rk29_map_common_io();
- rk29_setup_early_printk();
- rk29_sram_init();
- rk29_clock_init2(periph_pll_96mhz, codec_pll_300mhz, false);
- rk29_iomux_init();
- ddr_init(DDR_TYPE, DDR_FREQ);
-}
-
-MACHINE_START(RK29, "RK29board")
- /* UART for LL DEBUG */
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 37))
- /* UART for LL DEBUG */
- .phys_io = RK29_UART1_PHYS & 0xfff00000,
- .io_pg_offst = ((RK29_UART1_BASE) >> 18) & 0xfffc,
-#endif
- .boot_params = RK29_SDRAM_PHYS + 0x88000,
- .fixup = machine_rk29_fixup,
- .map_io = machine_rk29_mapio,
- .init_irq = machine_rk29_init_irq,
- .init_machine = machine_rk29_board_init,
- .timer = &rk29_timer,
-MACHINE_END
+++ /dev/null
-/* arch/arm/mach-rk29/board-rk29.c
- *
- * Copyright (C) 2010 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/android_pmem.h>
-#ifdef CONFIG_USB_ANDROID
-#include <linux/usb/android_composite.h>
-#endif
-#include <linux/ion.h>
-
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/iomux.h>
-#include <mach/gpio.h>
-#include <mach/irqs.h>
-#include <mach/rk29_iomap.h>
-#include <mach/board.h>
-#include <mach/rk29_nand.h>
-#include <mach/rk29_camera.h> /* ddl@rock-chips.com : camera support */
-#include <media/soc_camera.h> /* ddl@rock-chips.com : camera support */
-#include <mach/vpu_mem.h>
-#include <mach/sram.h>
-#include <mach/ddr.h>
-#include <mach/cpufreq.h>
-#include <mach/rk29_smc.h>
-
-#include <linux/regulator/rk29-pwm-regulator.h>
-#include <linux/regulator/machine.h>
-
-#include <linux/regulator/act8891.h>
-
-#include <linux/mtd/nand.h>
-#include <linux/mtd/partitions.h>
-#include <linux/i2c-gpio.h>
-#include <linux/mpu.h>
-#include "devices.h"
-#include "../../../drivers/input/touchscreen/xpt2046_cbn_ts.h"
-
-#ifdef CONFIG_BU92747GUW_CIR
-#include "../../../drivers/cir/bu92747guw_cir.h"
-#endif
-#include <linux/rfkill-rk.h>
-
-
-#ifdef CONFIG_VIDEO_RK29
-#include <plat/rk_camera.h>
-/* Notes:
-
-Simple camera device registration:
-
- new_camera_device(sensor_name,\ // sensor name, it is equal to CONFIG_SENSOR_X
- face,\ // sensor face information, it can be back or front
- pwdn_io,\ // power down gpio configuration, it is equal to CONFIG_SENSOR_POWERDN_PIN_XX
- flash_attach,\ // sensor is attach flash or not
- mir,\ // sensor image mirror and flip control information
- i2c_chl,\ // i2c channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_IIC_ADAPTER_ID_X
- cif_chl) \ // cif channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_CIF_INDEX_X
-
-Comprehensive camera device registration:
-
- new_camera_device_ex(sensor_name,\
- face,\
- ori,\ // sensor orientation, it is equal to CONFIG_SENSOR_ORIENTATION_X
- pwr_io,\ // sensor power gpio configuration, it is equal to CONFIG_SENSOR_POWER_PIN_XX
- pwr_active,\ // sensor power active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- rst_io,\ // sensor reset gpio configuration, it is equal to CONFIG_SENSOR_RESET_PIN_XX
- rst_active,\ // sensor reset active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- pwdn_io,\
- pwdn_active,\ // sensor power down active level, is equal to CONFIG_SENSOR_POWERDNACTIVE_LEVEL_X
- flash_attach,\
- res,\ // sensor resolution, this is real resolution or resoltuion after interpolate
- mir,\
- i2c_chl,\
- i2c_spd,\ // i2c speed , 100000 = 100KHz
- i2c_addr,\ // the i2c slave device address for sensor
- cif_chl,\
- mclk)\ // sensor input clock rate, 24 or 48
-
-*/
-static struct rkcamera_platform_data new_camera[] = {
- new_camera_device(RK29_CAM_SENSOR_OV5642,
- back,
- RK29_PIN6_PB7,
- 0,
- 0,
- 1,
- 0),
- new_camera_device(RK29_CAM_SENSOR_OV2659,
- front,
- RK29_PIN5_PD7,
- 0,
- 0,
- 1,
- 0),
- new_camera_device_end
-};
-/*---------------- Camera Sensor Macro Define Begin ------------------------*/
-/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
-#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_OV5642 /* back camera sensor 0 */
-#define CONFIG_SENSOR_IIC_ADDR_0 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 1
-#define CONFIG_SENSOR_ORIENTATION_0 90
-#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 RK29_PIN6_PB7
-#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000
-
-#define CONFIG_SENSOR_01 RK29_CAM_SENSOR_OV5642 /* back camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_01 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 1
-#define CONFIG_SENSOR_ORIENTATION_01 90
-#define CONFIG_SENSOR_POWER_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_01 RK29_PIN6_PB7
-#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_01 30000
-
-#define CONFIG_SENSOR_02 RK29_CAM_SENSOR_OV5640 /* back camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_02 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 1
-#define CONFIG_SENSOR_ORIENTATION_02 90
-#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_02 RK29_PIN6_PB7
-#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000
-
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_OV2659 /* front camera sensor 0 */
-#define CONFIG_SENSOR_IIC_ADDR_1 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 1
-#define CONFIG_SENSOR_ORIENTATION_1 270
-#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_1 RK29_PIN5_PD7
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000
-
-#define CONFIG_SENSOR_11 RK29_CAM_SENSOR_OV2659 /* front camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_11 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 1
-#define CONFIG_SENSOR_ORIENTATION_11 270
-#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_11 RK29_PIN5_PD7
-#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_11 30000
-
-#define CONFIG_SENSOR_12 RK29_CAM_SENSOR_OV2655 /* front camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_12 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 1
-#define CONFIG_SENSOR_ORIENTATION_12 270
-#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_12 RK29_PIN5_PD7
-#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_12 30000
-
-
-#endif //#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk29_camera.c"
-/*---------------- Camera Sensor Macro Define End ------------------------*/
-
-
-/* Set memory size of pmem */
-#ifdef CONFIG_RK29_MEM_SIZE_M
-#define SDRAM_SIZE (CONFIG_RK29_MEM_SIZE_M * SZ_1M)
-#else
-#define SDRAM_SIZE SZ_512M
-#endif
-#define PMEM_GPU_SIZE SZ_64M
-#define PMEM_UI_SIZE (48 * SZ_1M) /* 1280x800: 64M 1024x768: 48M ... */
-#define PMEM_VPU_SIZE SZ_64M
-#define PMEM_SKYPE_SIZE 0
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-#ifdef CONFIG_VIDEO_RK29_WORK_IPP
-#define MEM_CAMIPP_SIZE PMEM_CAMIPP_NECESSARY
-#else
-#define MEM_CAMIPP_SIZE 0
-#endif
-#define MEM_FB_SIZE (9*SZ_1M)
-#ifdef CONFIG_FB_WORK_IPP
-#ifdef CONFIG_FB_SCALING_OSD_1080P
-#define MEM_FBIPP_SIZE SZ_16M //1920 x 1080 x 2 x 2 //RGB565 = x2;RGB888 = x4
-#else
-#define MEM_FBIPP_SIZE SZ_8M //1920 x 1080 x 2 x 2 //RGB565 = x2;RGB888 = x4
-#endif
-#else
-#define MEM_FBIPP_SIZE 0
-#endif
-#if SDRAM_SIZE > SZ_512M
-#define PMEM_GPU_BASE (RK29_SDRAM_PHYS + SZ_512M - PMEM_GPU_SIZE)
-#else
-#define PMEM_GPU_BASE (RK29_SDRAM_PHYS + SDRAM_SIZE - PMEM_GPU_SIZE)
-#endif
-#define PMEM_UI_BASE (PMEM_GPU_BASE - PMEM_UI_SIZE)
-#define PMEM_VPU_BASE (PMEM_UI_BASE - PMEM_VPU_SIZE)
-#define PMEM_CAM_BASE (PMEM_VPU_BASE - PMEM_CAM_SIZE)
-#define MEM_CAMIPP_BASE (PMEM_CAM_BASE - MEM_CAMIPP_SIZE)
-#define MEM_FB_BASE (MEM_CAMIPP_BASE - MEM_FB_SIZE)
-#define MEM_FBIPP_BASE (MEM_FB_BASE - MEM_FBIPP_SIZE)
-#define PMEM_SKYPE_BASE (MEM_FBIPP_BASE - PMEM_SKYPE_SIZE)
-#define LINUX_SIZE (PMEM_SKYPE_BASE - RK29_SDRAM_PHYS)
-
-#define PREALLOC_WLAN_SEC_NUM 4
-#define PREALLOC_WLAN_BUF_NUM 160
-#define PREALLOC_WLAN_SECTION_HEADER 24
-
-#define WLAN_SECTION_SIZE_0 (PREALLOC_WLAN_BUF_NUM * 128)
-#define WLAN_SECTION_SIZE_1 (PREALLOC_WLAN_BUF_NUM * 128)
-#define WLAN_SECTION_SIZE_2 (PREALLOC_WLAN_BUF_NUM * 512)
-#define WLAN_SECTION_SIZE_3 (PREALLOC_WLAN_BUF_NUM * 1024)
-
-#define WLAN_SKB_BUF_NUM 16
-
-static struct sk_buff *wlan_static_skb[WLAN_SKB_BUF_NUM];
-
-struct wifi_mem_prealloc {
- void *mem_ptr;
- unsigned long size;
-};
-
-extern struct sys_timer rk29_timer;
-
-static int rk29_nand_io_init(void)
-{
- return 0;
-}
-
-struct rk29_nand_platform_data rk29_nand_data = {
- .width = 1, /* data bus width in bytes */
- .hw_ecc = 1, /* hw ecc 0: soft ecc */
- .num_flash = 1,
- .io_init = rk29_nand_io_init,
-};
-
-#define TOUCH_SCREEN_STANDBY_PIN RK29_PIN6_PD1
-#define TOUCH_SCREEN_STANDBY_VALUE GPIO_HIGH
-#define TOUCH_SCREEN_DISPLAY_PIN INVALID_GPIO
-#define TOUCH_SCREEN_DISPLAY_VALUE GPIO_HIGH
-
-#ifdef CONFIG_FB_RK29
-/*****************************************************************************************
- * lcd devices
- * author: zyw@rock-chips.com
- *****************************************************************************************/
-//#ifdef CONFIG_LCD_TD043MGEA1
-#define LCD_TXD_PIN INVALID_GPIO
-#define LCD_CLK_PIN INVALID_GPIO
-#define LCD_CS_PIN INVALID_GPIO
-/*****************************************************************************************
-* frame buffe devices
-* author: zyw@rock-chips.com
-*****************************************************************************************/
-#define FB_ID 0
-#define FB_DISPLAY_ON_PIN INVALID_GPIO// RK29_PIN6_PD0
-#define FB_LCD_STANDBY_PIN INVALID_GPIO
-#define FB_LCD_CABC_EN_PIN RK29_PIN6_PD2
-#define FB_MCU_FMK_PIN INVALID_GPIO
-
-#define FB_DISPLAY_ON_VALUE GPIO_HIGH
-#define FB_LCD_STANDBY_VALUE GPIO_HIGH
-
-static int rk29_lcd_io_init(void)
-{
- int ret = 0;
- return ret;
-}
-
-static int rk29_lcd_io_deinit(void)
-{
- int ret = 0;
- return ret;
-}
-
-static struct rk29lcd_info rk29_lcd_info = {
- .txd_pin = LCD_TXD_PIN,
- .clk_pin = LCD_CLK_PIN,
- .cs_pin = LCD_CS_PIN,
- .io_init = rk29_lcd_io_init,
- .io_deinit = rk29_lcd_io_deinit,
-};
-
-int rk29_fb_io_enable(void)
-{
- if(FB_DISPLAY_ON_PIN != INVALID_GPIO)
- {
- gpio_direction_output(FB_DISPLAY_ON_PIN, 0);
- gpio_set_value(FB_DISPLAY_ON_PIN, FB_DISPLAY_ON_VALUE);
- }
- if(FB_LCD_STANDBY_PIN != INVALID_GPIO)
- {
- gpio_direction_output(FB_LCD_STANDBY_PIN, 0);
- gpio_set_value(FB_LCD_STANDBY_PIN, FB_LCD_STANDBY_VALUE);
- }
- return 0;
-}
-
-int rk29_fb_io_disable(void)
-{
- if(FB_DISPLAY_ON_PIN != INVALID_GPIO)
- {
- gpio_direction_output(FB_DISPLAY_ON_PIN, 0);
- gpio_set_value(FB_DISPLAY_ON_PIN, !FB_DISPLAY_ON_VALUE);
- }
- if(FB_LCD_STANDBY_PIN != INVALID_GPIO)
- {
- gpio_direction_output(FB_LCD_STANDBY_PIN, 0);
- gpio_set_value(FB_LCD_STANDBY_PIN, !FB_LCD_STANDBY_VALUE);
- }
- return 0;
-}
-
-static int rk29_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
- if(fb_setting->mcu_fmk_en && (FB_MCU_FMK_PIN != INVALID_GPIO))
- {
- ret = gpio_request(FB_MCU_FMK_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(FB_MCU_FMK_PIN);
- printk(">>>>>> FB_MCU_FMK_PIN gpio_request err \n ");
- }
- gpio_direction_input(FB_MCU_FMK_PIN);
- }
- if(fb_setting->disp_on_en)
- {
- if(FB_DISPLAY_ON_PIN != INVALID_GPIO)
- {
- ret = gpio_request(FB_DISPLAY_ON_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(FB_DISPLAY_ON_PIN);
- printk(">>>>>> FB_DISPLAY_ON_PIN gpio_request err \n ");
- }
- }
- else if (TOUCH_SCREEN_DISPLAY_PIN != INVALID_GPIO)
- {
- ret = gpio_request(TOUCH_SCREEN_DISPLAY_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(TOUCH_SCREEN_DISPLAY_PIN);
- printk(">>>>>> TOUCH_SCREEN_DISPLAY_PIN gpio_request err \n ");
- }
- gpio_direction_output(TOUCH_SCREEN_DISPLAY_PIN, 0);
- gpio_set_value(TOUCH_SCREEN_DISPLAY_PIN, TOUCH_SCREEN_DISPLAY_VALUE);
- }
- }
-
- if(fb_setting->disp_on_en)
- {
- if(FB_LCD_STANDBY_PIN != INVALID_GPIO)
- {
- ret = gpio_request(FB_LCD_STANDBY_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(FB_LCD_STANDBY_PIN);
- printk(">>>>>> FB_LCD_STANDBY_PIN gpio_request err \n ");
- }
- }
- else if (TOUCH_SCREEN_STANDBY_PIN != INVALID_GPIO)
- {
- ret = gpio_request(TOUCH_SCREEN_STANDBY_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(TOUCH_SCREEN_STANDBY_PIN);
- printk(">>>>>> TOUCH_SCREEN_STANDBY_PIN gpio_request err \n ");
- }
- gpio_direction_output(TOUCH_SCREEN_STANDBY_PIN, 0);
- gpio_set_value(TOUCH_SCREEN_STANDBY_PIN, TOUCH_SCREEN_STANDBY_VALUE);
- }
- }
-
- if(FB_LCD_CABC_EN_PIN != INVALID_GPIO)
- {
- ret = gpio_request(FB_LCD_CABC_EN_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(FB_LCD_CABC_EN_PIN);
- printk(">>>>>> FB_LCD_CABC_EN_PIN gpio_request err \n ");
- }
- gpio_direction_output(FB_LCD_CABC_EN_PIN, 0);
- gpio_set_value(FB_LCD_CABC_EN_PIN, GPIO_LOW);
- }
-
- rk29_fb_io_enable(); //enable it
-
- return ret;
-}
-
-
-static struct rk29fb_info rk29_fb_info = {
- .fb_id = FB_ID,
- .mcu_fmk_pin = FB_MCU_FMK_PIN,
- .lcd_info = &rk29_lcd_info,
- .io_init = rk29_fb_io_init,
- .io_enable = rk29_fb_io_enable,
- .io_disable = rk29_fb_io_disable,
-};
-
-/* rk29 fb resource */
-static struct resource rk29_fb_resource[] = {
- [0] = {
- .name = "lcdc reg",
- .start = RK29_LCDC_PHYS,
- .end = RK29_LCDC_PHYS + RK29_LCDC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc irq",
- .start = IRQ_LCDC,
- .end = IRQ_LCDC,
- .flags = IORESOURCE_IRQ,
- },
- [2] = {
- .name = "win1 buf",
- .start = MEM_FB_BASE,
- .end = MEM_FB_BASE + MEM_FB_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- #ifdef CONFIG_FB_WORK_IPP
- [3] = {
- .name = "win1 ipp buf",
- .start = MEM_FBIPP_BASE,
- .end = MEM_FBIPP_BASE + MEM_FBIPP_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- #endif
-};
-
-/*platform_device*/
-struct platform_device rk29_device_fb = {
- .name = "rk29-fb",
- .id = 4,
- .num_resources = ARRAY_SIZE(rk29_fb_resource),
- .resource = rk29_fb_resource,
- .dev = {
- .platform_data = &rk29_fb_info,
- }
-};
-
-struct platform_device rk29_device_dma_cpy = {
- .name = "dma_memcpy",
- .id = 4,
-
-};
-
-#endif
-
-#if defined(CONFIG_RK29_GPIO_SUSPEND)
-static void key_gpio_pullupdown_enable(void)
-{
- gpio_pull_updown(RK29_PIN6_PA0, 0);
- gpio_pull_updown(RK29_PIN6_PA1, 0);
- gpio_pull_updown(RK29_PIN6_PA2, 0);
- gpio_pull_updown(RK29_PIN6_PA3, 0);
- gpio_pull_updown(RK29_PIN6_PA4, 0);
- gpio_pull_updown(RK29_PIN6_PA5, 0);
- gpio_pull_updown(RK29_PIN6_PA6, 0);
-}
-
-static void key_gpio_pullupdown_disable(void)
-{
- gpio_pull_updown(RK29_PIN6_PA0, 1);
- gpio_pull_updown(RK29_PIN6_PA1, 1);
- gpio_pull_updown(RK29_PIN6_PA2, 1);
- gpio_pull_updown(RK29_PIN6_PA3, 1);
- gpio_pull_updown(RK29_PIN6_PA4, 1);
- gpio_pull_updown(RK29_PIN6_PA5, 1);
- gpio_pull_updown(RK29_PIN6_PA6, 1);
-}
-
-void rk29_setgpio_suspend_board(void)
-{
- key_gpio_pullupdown_enable();
-}
-
-void rk29_setgpio_resume_board(void)
-{
- key_gpio_pullupdown_disable();
-}
-#endif
-
-#if defined(CONFIG_RK_IRDA) || defined(CONFIG_BU92747GUW_CIR)
-#define BU92747GUW_RESET_PIN RK29_PIN3_PD4// INVALID_GPIO //
-#define BU92747GUW_RESET_MUX_NAME GPIO3D4_HOSTWRN_NAME//NULL //
-#define BU92747GUW_RESET_MUX_MODE GPIO3H_GPIO3D4//NULL //
-
-#define BU92747GUW_PWDN_PIN RK29_PIN3_PD3//RK29_PIN5_PA7 //
-#define BU92747GUW_PWDN_MUX_NAME GPIO3D3_HOSTRDN_NAME//GPIO5A7_HSADCDATA2_NAME //
-#define BU92747GUW_PWDN_MUX_MODE GPIO3H_GPIO3D3//GPIO5L_GPIO5A7 //
-
-static int bu92747guw_io_init(void)
-{
- int ret;
-
- //reset pin
- if(BU92747GUW_RESET_MUX_NAME != NULL)
- {
- rk29_mux_api_set(BU92747GUW_RESET_MUX_NAME, BU92747GUW_RESET_MUX_MODE);
- }
- ret = gpio_request(BU92747GUW_RESET_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(BU92747GUW_RESET_PIN);
- printk(">>>>>> BU92747GUW_RESET_PIN gpio_request err \n ");
- }
- gpio_direction_output(BU92747GUW_RESET_PIN, GPIO_HIGH);
-
- //power down pin
- if(BU92747GUW_PWDN_MUX_NAME != NULL)
- {
- rk29_mux_api_set(BU92747GUW_PWDN_MUX_NAME, BU92747GUW_PWDN_MUX_MODE);
- }
- ret = gpio_request(BU92747GUW_PWDN_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(BU92747GUW_PWDN_PIN);
- printk(">>>>>> BU92747GUW_PWDN_PIN gpio_request err \n ");
- }
-
- //power down as default
- gpio_direction_output(BU92747GUW_PWDN_PIN, GPIO_LOW);
-
- return 0;
-}
-
-
-static int bu92747guw_io_deinit(void)
-{
- gpio_free(BU92747GUW_PWDN_PIN);
- gpio_free(BU92747GUW_RESET_PIN);
- return 0;
-}
-
-//power ctl func is share with irda and remote
-static int nPowerOnCount = 0;
-static DEFINE_MUTEX(bu92747_power_mutex);
-
-//1---power on; 0---power off
-static int bu92747guw_power_ctl(int enable)
-{
- printk("%s \n",__FUNCTION__);
-
- mutex_lock(&bu92747_power_mutex);
- if (enable) {
- nPowerOnCount++;
- if (nPowerOnCount == 1) {//power on first
- //smc0_init(NULL);
- gpio_set_value(BU92747GUW_PWDN_PIN, GPIO_HIGH);
- gpio_set_value(BU92747GUW_RESET_PIN, GPIO_LOW);
- mdelay(5);
- gpio_set_value(BU92747GUW_RESET_PIN, GPIO_HIGH);
- mdelay(5);
- }
- }
- else {
- nPowerOnCount--;
- if (nPowerOnCount <= 0) {//power down final
- nPowerOnCount = 0;
- //smc0_exit();
- gpio_set_value(BU92747GUW_PWDN_PIN, GPIO_LOW);
- }
- }
- mutex_unlock(&bu92747_power_mutex);
- return 0;
-}
-#endif
-
-#ifdef CONFIG_RK_IRDA
-#define IRDA_IRQ_PIN RK29_PIN5_PB2
-#define IRDA_IRQ_MUX_NAME GPIO5B2_HSADCDATA5_NAME
-#define IRDA_IRQ_MUX_MODE GPIO5L_GPIO5B2
-
-int irda_iomux_init(void)
-{
- int ret = 0;
-
- //irda irq pin
- if(IRDA_IRQ_MUX_NAME != NULL)
- {
- rk29_mux_api_set(IRDA_IRQ_MUX_NAME, IRDA_IRQ_MUX_MODE);
- }
- ret = gpio_request(IRDA_IRQ_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(IRDA_IRQ_PIN);
- printk(">>>>>> IRDA_IRQ_PIN gpio_request err \n ");
- }
- gpio_pull_updown(IRDA_IRQ_PIN, GPIO_HIGH);
- gpio_direction_input(IRDA_IRQ_PIN);
-
- return 0;
-}
-
-int irda_iomux_deinit(void)
-{
- gpio_free(IRDA_IRQ_PIN);
- return 0;
-}
-
-static struct irda_info rk29_irda_info = {
- .intr_pin = IRDA_IRQ_PIN,
- .iomux_init = irda_iomux_init,
- .iomux_deinit = irda_iomux_deinit,
- .irda_pwr_ctl = bu92747guw_power_ctl,
-};
-
-static struct platform_device irda_device = {
-#ifdef CONFIG_RK_IRDA_NET
- .name = "rk_irda",
-#else
- .name = "bu92747_irda",
-#endif
- .id = -1,
- .dev = {
- .platform_data = &rk29_irda_info,
- }
-};
-#endif
-
-#ifdef CONFIG_BU92747GUW_CIR
-#define BU92747_CIR_IRQ_PIN RK29_PIN5_PB0
-#define CIR_IRQ_PIN_IOMUX_NAME GPIO5B0_HSADCDATA3_NAME
-#define CIR_IRQ_PIN_IOMUX_VALUE GPIO5L_GPIO5B0
-static int cir_iomux_init(void)
-{
- if (CIR_IRQ_PIN_IOMUX_NAME)
- rk29_mux_api_set(CIR_IRQ_PIN_IOMUX_NAME, CIR_IRQ_PIN_IOMUX_VALUE);
- rk29_mux_api_set(GPIO5A7_HSADCDATA2_NAME, GPIO5L_GPIO5A7);
- return 0;
-}
-
-static struct bu92747guw_platform_data bu92747guw_pdata = {
- .intr_pin = BU92747_CIR_IRQ_PIN,
- .iomux_init = cir_iomux_init,
- .iomux_deinit = NULL,
- .cir_pwr_ctl = bu92747guw_power_ctl,
-};
-#endif
-#ifdef CONFIG_RK29_NEWTON
-struct rk29_newton_data rk29_newton_info = {
-};
-struct platform_device rk29_device_newton = {
- .name = "rk29_newton",
- .id = -1,
- .dev = {
- .platform_data = &rk29_newton_info,
- }
- };
-#endif
-#if defined (CONFIG_TOUCHSCREEN_FT5406)
-#define TOUCH_RESET_PIN RK29_PIN6_PC3
-#define TOUCH_INT_PIN RK29_PIN0_PA2
-int ft5406_init_platform_hw(void)
-{
- printk("ft5406_init_platform_hw\n");
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("ft5406_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("ift5406_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- mdelay(10);
- gpio_direction_input(TOUCH_INT_PIN);
- mdelay(10);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- msleep(300);
- return 0;
-}
-
-void ft5406_exit_platform_hw(void)
-{
- printk("ft5406_exit_platform_hw\n");
- gpio_free(TOUCH_RESET_PIN);
- gpio_free(TOUCH_INT_PIN);
-}
-
-int ft5406_platform_sleep(void)
-{
- printk("ft5406_platform_sleep\n");
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- return 0;
-}
-
-int ft5406_platform_wakeup(void)
-{
- printk("ft5406_platform_wakeup\n");
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- msleep(300);
- return 0;
-}
-
-struct ft5406_platform_data ft5406_info = {
-
- .init_platform_hw= ft5406_init_platform_hw,
- .exit_platform_hw= ft5406_exit_platform_hw,
- .platform_sleep = ft5406_platform_sleep,
- .platform_wakeup = ft5406_platform_wakeup,
-
-};
-#endif
-
-#if defined(CONFIG_TOUCHSCREEN_GT819)
-#define TOUCH_RESET_PIN RK29_PIN6_PC3
-#define TOUCH_INT_PIN RK29_PIN0_PA2
-int gt819_init_platform_hw(void)
-{
- printk("gt819_init_platform_hw\n");
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("gt819_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("gt819_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- mdelay(10);
-// gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
-// mdelay(10);
-// gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- gpio_direction_input(TOUCH_INT_PIN);
-// mdelay(10);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- msleep(300);
- return 0;
-}
-
-
-void gt819_exit_platform_hw(void)
-{
- printk("gt819_exit_platform_hw\n");
- gpio_free(TOUCH_RESET_PIN);
- gpio_free(TOUCH_INT_PIN);
-}
-
-int gt819_platform_sleep(void)
-{
- printk("gt819_platform_sleep\n");
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- return 0;
-}
-
-int gt819_platform_wakeup(void)
-{
- printk("gt819_platform_wakeup\n");
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- //msleep(5);
- //gpio_set_value(TOUCH_INT_PIN, GPIO_LOW);
- //msleep(20);
- //gpio_set_value(TOUCH_INT_PIN, GPIO_HIGH);
- return 0;
-}
-struct goodix_platform_data goodix_info = {
-
- .init_platform_hw= gt819_init_platform_hw,
- .exit_platform_hw= gt819_exit_platform_hw,
- .platform_sleep = gt819_platform_sleep,
- .platform_wakeup = gt819_platform_wakeup,
-
-};
-#endif
-
-
-#if defined (CONFIG_SND_SOC_CS42L52)
-
-int cs42l52_init_platform_hw()
-{
- printk("cs42l52_init_platform_hw\n");
- if(gpio_request(RK29_PIN6_PB6,NULL) != 0){
- gpio_free(RK29_PIN6_PB6);
- printk("cs42l52_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(RK29_PIN6_PB6, 0);
- gpio_set_value(RK29_PIN6_PB6,GPIO_HIGH);
- return 0;
-}
-struct cs42l52_platform_data cs42l52_info = {
-
- .init_platform_hw= cs42l52_init_platform_hw,
-
-};
-#endif
-#if defined (CONFIG_BATTERY_BQ27541)
-#define DC_CHECK_PIN RK29_PIN4_PA1
-#define LI_LION_BAT_NUM 1
-#define CHG_OK RK29_PIN4_PA3
-#define BAT_LOW RK29_PIN4_PA2
-
-static int bq27541_init_dc_check_pin(void){
- if(gpio_request(DC_CHECK_PIN,"dc_check") != 0){
- gpio_free(DC_CHECK_PIN);
- printk("bq27541 init dc check pin request error\n");
- return -EIO;
- }
- gpio_direction_input(DC_CHECK_PIN);
- return 0;
-}
-
-struct bq27541_platform_data bq27541_info = {
- .init_dc_check_pin = bq27541_init_dc_check_pin,
- .dc_check_pin = DC_CHECK_PIN,
- .bat_num = LI_LION_BAT_NUM,
- .chgok_check_pin = CHG_OK,
- .bat_check_pin = BAT_LOW,
-};
-#endif
-
-#ifdef CONFIG_BATTERY_RK29_ADC
-static struct rk29_adc_battery_platform_data rk29_adc_battery_platdata = {
- .dc_det_pin = RK29_PIN4_PA1,
- .batt_low_pin = RK29_PIN4_PA2,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = RK29_PIN4_PA3,
-
- .dc_det_level = GPIO_LOW,
- .charge_ok_level = GPIO_HIGH,
-};
-
-static struct platform_device rk29_device_adc_battery = {
- .name = "rk2918-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk29_adc_battery_platdata,
- },
-};
-#endif
-
-static struct android_pmem_platform_data android_pmem_pdata = {
- .name = "pmem",
- .start = PMEM_UI_BASE,
- .size = PMEM_UI_SIZE,
- .no_allocator = 1,
- .cached = 1,
-};
-
-static struct platform_device android_pmem_device = {
- .name = "android_pmem",
- .id = 0,
- .dev = {
- .platform_data = &android_pmem_pdata,
- },
-};
-
-
-static struct vpu_mem_platform_data vpu_mem_pdata = {
- .name = "vpu_mem",
- .start = PMEM_VPU_BASE,
- .size = PMEM_VPU_SIZE,
- .cached = 1,
-};
-
-static struct platform_device rk29_vpu_mem_device = {
- .name = "vpu_mem",
- .id = 2,
- .dev = {
- .platform_data = &vpu_mem_pdata,
- },
-};
-
-#if PMEM_SKYPE_SIZE > 0
-static struct android_pmem_platform_data android_pmem_skype_pdata = {
- .name = "pmem_skype",
- .start = PMEM_SKYPE_BASE,
- .size = PMEM_SKYPE_SIZE,
- .no_allocator = 0,
- .cached = 0,
-};
-
-static struct platform_device android_pmem_skype_device = {
- .name = "android_pmem",
- .id = 3,
- .dev = {
- .platform_data = &android_pmem_skype_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_ION
-static struct ion_platform_data rk29_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = 0,
- .name = "ui",
- .base = PMEM_UI_BASE,
- .size = PMEM_UI_SIZE,
- }
- },
-};
-
-static struct platform_device rk29_ion_device = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk29_ion_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_VIDEO_RK29XX_VOUT
-static struct platform_device rk29_v4l2_output_devce = {
- .name = "rk29_vout",
-};
-#endif
-/*HANNSTAR_P1003 touch*/
-#if defined (CONFIG_HANNSTAR_P1003)
-#define TOUCH_RESET_PIN RK29_PIN6_PC3
-#define TOUCH_INT_PIN RK29_PIN0_PA2
-
-int p1003_init_platform_hw(void)
-{
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_pull_updown(TOUCH_INT_PIN, 1);
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
-
- return 0;
-}
-
-
-struct p1003_platform_data p1003_info = {
- .model= 1003,
- .init_platform_hw= p1003_init_platform_hw,
-
-};
-#endif
-#if defined (CONFIG_EETI_EGALAX)
-#define TOUCH_RESET_PIN RK29_PIN6_PC3
-#define TOUCH_INT_PIN RK29_PIN0_PA2
-
-static int EETI_EGALAX_init_platform_hw(void)
-{
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_pull_updown(TOUCH_INT_PIN, 1);
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
-
- return 0;
-}
-
-
-static struct eeti_egalax_platform_data eeti_egalax_info = {
- .model= 1003,
- .init_platform_hw= EETI_EGALAX_init_platform_hw,
- .standby_pin = TOUCH_SCREEN_STANDBY_PIN,
- .standby_value = TOUCH_SCREEN_STANDBY_VALUE,
- .disp_on_pin = TOUCH_SCREEN_DISPLAY_PIN,
- .disp_on_value = TOUCH_SCREEN_DISPLAY_VALUE,
-};
-#endif
-
-#ifdef CONFIG_GS_KXTF9
-#include <linux/kxtf9.h>
-#define KXTF9_DEVICE_MAP 1
-#define KXTF9_MAP_X (KXTF9_DEVICE_MAP-1)%2
-#define KXTF9_MAP_Y KXTF9_DEVICE_MAP%2
-#define KXTF9_NEG_X (KXTF9_DEVICE_MAP/2)%2
-#define KXTF9_NEG_Y (KXTF9_DEVICE_MAP+1)/4
-#define KXTF9_NEG_Z (KXTF9_DEVICE_MAP-1)/4
-struct kxtf9_platform_data kxtf9_pdata = {
- .min_interval = 1,
- .poll_interval = 20,
- .g_range = KXTF9_G_2G,
- .axis_map_x = KXTF9_MAP_X,
- .axis_map_y = KXTF9_MAP_Y,
- .axis_map_z = 2,
- .negate_x = KXTF9_NEG_X,
- .negate_y = KXTF9_NEG_Y,
- .negate_z = KXTF9_NEG_Z,
- //.ctrl_regc_init = KXTF9_G_2G | ODR50F,
- //.ctrl_regb_init = ENABLE,
-};
-#endif /* CONFIG_GS_KXTF9 */
-
-
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN RK29_PIN0_PA3
-
-static int mma8452_init_platform_hw(void)
-{
-
- if(gpio_request(MMA8452_INT_PIN,NULL) != 0){
- gpio_free(MMA8452_INT_PIN);
- printk("mma8452_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_pull_updown(MMA8452_INT_PIN, 1);
- return 0;
-}
-
-
-static struct gsensor_platform_data mma8452_info = {
- .model= 8452,
- .swap_xy = 0,
- .swap_xyz = 1,
- .init_platform_hw= mma8452_init_platform_hw,
- .orientation = { -1, 0, 0, 0, 0, 1, 0, -1, 0},
-};
-#endif
-/*mpu3050*/
-#if defined (CONFIG_MPU_SENSORS_MPU3050)
-static struct mpu_platform_data mpu3050_data = {
- .int_config = 0x10,
- .orientation = { 1, 0, 0,0, 1, 0, 0, 0, 1 },
-};
-#endif
-
-/* accel */
-#if defined (CONFIG_MPU_SENSORS_KXTF9)
-static struct ext_slave_platform_data inv_mpu_kxtf9_data = {
- .bus = EXT_SLAVE_BUS_SECONDARY,
- .adapt_num = 0,
- .orientation = {1, 0, 0, 0, 1, 0, 0, 0, 1},
-};
-#endif
-
-/* compass */
-#if defined (CONFIG_MPU_SENSORS_AK8975)
-static struct ext_slave_platform_data inv_mpu_ak8975_data = {
- .bus = EXT_SLAVE_BUS_PRIMARY,
- .adapt_num = 0,
- .orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
-};
-#endif
-
-#if defined (CONFIG_BATTERY_BQ27510)
-#define DC_CHECK_PIN RK29_PIN4_PA1
-#define LI_LION_BAT_NUM 2
-static int bq27510_init_dc_check_pin(void){
- if(gpio_request(DC_CHECK_PIN,"dc_check") != 0){
- gpio_free(DC_CHECK_PIN);
- printk("bq27510 init dc check pin request error\n");
- return -EIO;
- }
- gpio_direction_input(DC_CHECK_PIN);
- return 0;
-}
-
-struct bq27510_platform_data bq27510_info = {
- .init_dc_check_pin = bq27510_init_dc_check_pin,
- .dc_check_pin = DC_CHECK_PIN,
- .bat_num = LI_LION_BAT_NUM,
-};
-#endif
-#ifdef CONFIG_SND_SOC_RK610
-static int rk610_codec_io_init(void)
-{
-//if need iomux.
-//Must not gpio_request
- return 0;
-}
-
-static struct rk610_codec_platform_data rk610_codec_pdata = {
- .spk_ctl_io = RK29_PIN6_PB6,
- .io_init = rk610_codec_io_init,
-};
-#endif
-/*************************************PMU ACT8891****************************************/
-
-#if defined (CONFIG_REGULATOR_ACT8891)
- /*dcdc mode*/
-/*act8891 in REGULATOR_MODE_STANDBY mode is said DCDC is in PMF mode is can save power,when in REGULATOR_MODE_NORMAL
-mode is said DCDC is in PWM mode , General default is in REGULATOR_MODE_STANDBY mode*/
- /*ldo mode */
-/*act8891 in REGULATOR_MODE_STANDBY mode is said LDO is in low power mode is can save power,when in REGULATOR_MODE_NORMAL
-mode is said DCDC is in nomal mode , General default is in REGULATOR_MODE_STANDBY mode*/
-/*set dcdc and ldo voltage by regulator_set_voltage()*/
-static struct act8891 *act8891;
-int act8891_set_init(struct act8891 *act8891)
-{
- int tmp = 0;
- struct regulator *act_ldo1,*act_ldo2,*act_ldo3,*act_ldo4;
- struct regulator *act_dcdc1,*act_dcdc2,*act_dcdc3;
-
- /*init ldo1*/
- act_ldo1 = regulator_get(NULL, "act_ldo1");
- regulator_enable(act_ldo1);
- regulator_set_voltage(act_ldo1,1800000,1800000);
- tmp = regulator_get_voltage(act_ldo1);
- regulator_set_mode(act_ldo1,REGULATOR_MODE_STANDBY);
- //regulator_set_mode(act_ldo1,REGULATOR_MODE_NORMAL);
- printk("***regulator_set_init: ldo1 vcc =%d\n",tmp);
- regulator_put(act_ldo1);
-
- /*init ldo2*/
- act_ldo2 = regulator_get(NULL, "act_ldo2");
- regulator_enable(act_ldo2);
- regulator_set_voltage(act_ldo2,1200000,1200000);
- tmp = regulator_get_voltage(act_ldo2);
- regulator_set_mode(act_ldo2,REGULATOR_MODE_STANDBY);
- //regulator_set_mode(act_ldo2,REGULATOR_MODE_NORMAL);
- printk("***regulator_set_init: ldo2 vcc =%d\n",tmp);
- regulator_put(act_ldo2);
-
- /*init ldo3*/
- act_ldo3 = regulator_get(NULL, "act_ldo3");
- regulator_enable(act_ldo3);
- regulator_set_voltage(act_ldo3,3300000,3300000);
- tmp = regulator_get_voltage(act_ldo3);
- regulator_set_mode(act_ldo3,REGULATOR_MODE_STANDBY);
- //regulator_set_mode(act_ldo3,REGULATOR_MODE_NORMAL);
- printk("***regulator_set_init: ldo3 vcc =%d\n",tmp);
- regulator_put(act_ldo3);
-
- /*init ldo4*/
- act_ldo4 = regulator_get(NULL, "act_ldo4");
- regulator_enable(act_ldo4);
- regulator_set_voltage(act_ldo4,2500000,2500000);
- tmp = regulator_get_voltage(act_ldo4);
- regulator_set_mode(act_ldo4,REGULATOR_MODE_STANDBY);
- //regulator_set_mode(act_ldo4,REGULATOR_MODE_NORMAL);
- printk("***regulator_set_init: ldo4 vcc =%d\n",tmp);
- regulator_put(act_ldo4);
-
- /*init dcdc1*/
- act_dcdc1 = regulator_get(NULL, "act_dcdc1");
- regulator_enable(act_dcdc1);
- regulator_set_voltage(act_dcdc1,3000000,3000000);
- tmp = regulator_get_voltage(act_dcdc1);
- regulator_set_mode(act_dcdc1,REGULATOR_MODE_STANDBY);
- //regulator_set_mode(act_dcdc1,REGULATOR_MODE_NORMAL);
- printk("***regulator_set_init: dcdc1 vcc =%d\n",tmp);
- regulator_put(act_dcdc1);
-
- /*init dcdc2*/
- act_dcdc2 = regulator_get(NULL, "act_dcdc2");
- regulator_enable(act_dcdc2);
- regulator_set_voltage(act_dcdc2,1500000,1500000);
- tmp = regulator_get_voltage(act_dcdc2);
- regulator_set_mode(act_dcdc2,REGULATOR_MODE_STANDBY);
- //regulator_set_mode(act_dcdc2,REGULATOR_MODE_NORMAL);
- printk("***regulator_set_init: dcdc2 vcc =%d\n",tmp);
- regulator_put(act_dcdc2);
-
- /*init dcdc3*/
- act_dcdc3 = regulator_get(NULL, "act_dcdc3");
- regulator_enable(act_dcdc3);
- regulator_set_voltage(act_dcdc3,1200000,1200000);
- tmp = regulator_get_voltage(act_dcdc3);
- regulator_set_mode(act_dcdc3,REGULATOR_MODE_STANDBY);
- //regulator_set_mode(act_dcdc3,REGULATOR_MODE_NORMAL);
- printk("***regulator_set_init: dcdc3 vcc =%d\n",tmp);
- regulator_put(act_dcdc3);
-
- return(0);
-}
-
-static struct regulator_consumer_supply act8891_ldo1_consumers[] = {
- {
- .supply = "act_ldo1",
- }
-};
-
-static struct regulator_init_data act8891_ldo1_data = {
- .constraints = {
- .name = "ACT_LDO1",
- .min_uV = 600000,
- .max_uV = 3900000,
- .apply_uV = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
- },
- .num_consumer_supplies = ARRAY_SIZE(act8891_ldo1_consumers),
- .consumer_supplies = act8891_ldo1_consumers,
-};
-
-/**/
-static struct regulator_consumer_supply act8891_ldo2_consumers[] = {
- {
- .supply = "act_ldo2",
- }
-};
-
-static struct regulator_init_data act8891_ldo2_data = {
- .constraints = {
- .name = "ACT_LDO2",
- .min_uV = 600000,
- .max_uV = 3900000,
- .apply_uV = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
- },
- .num_consumer_supplies = ARRAY_SIZE(act8891_ldo2_consumers),
- .consumer_supplies = act8891_ldo2_consumers,
-};
-
-/*ldo3 VCC_NAND WIFI/BT/FM_BCM4325*/
-static struct regulator_consumer_supply act8891_ldo3_consumers[] = {
- {
- .supply = "act_ldo3",
- }
-};
-
-static struct regulator_init_data act8891_ldo3_data = {
- .constraints = {
- .name = "ACT_LDO3",
- .min_uV = 600000,
- .max_uV = 3900000,
- .apply_uV = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
- },
- .num_consumer_supplies = ARRAY_SIZE(act8891_ldo3_consumers),
- .consumer_supplies = act8891_ldo3_consumers,
-};
-
-/*ldo4 VCCA CODEC_WM8994*/
-static struct regulator_consumer_supply act8891_ldo4_consumers[] = {
- {
- .supply = "act_ldo4",
- }
-};
-
-static struct regulator_init_data act8891_ldo4_data = {
- .constraints = {
- .name = "ACT_LDO4",
- .min_uV = 600000,
- .max_uV = 3900000,
- .apply_uV = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
- },
- .num_consumer_supplies = ARRAY_SIZE(act8891_ldo4_consumers),
- .consumer_supplies = act8891_ldo4_consumers,
-};
-/*buck1 vcc Core*/
-static struct regulator_consumer_supply act8891_dcdc1_consumers[] = {
- {
- .supply = "act_dcdc1",
- }
-};
-
-static struct regulator_init_data act8891_dcdc1_data = {
- .constraints = {
- .name = "ACT_DCDC1",
- .min_uV = 600000,
- .max_uV = 3900000,
- .apply_uV = 1,
- //.always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
- },
- .num_consumer_supplies = ARRAY_SIZE(act8891_dcdc1_consumers),
- .consumer_supplies = act8891_dcdc1_consumers
-};
-
-/*buck2 VDDDR MobileDDR VCC*/
-static struct regulator_consumer_supply act8891_dcdc2_consumers[] = {
- {
- .supply = "act_dcdc2",
- }
-};
-
-static struct regulator_init_data act8891_dcdc2_data = {
- .constraints = {
- .name = "ACT_DCDC2",
- .min_uV = 600000,
- .max_uV = 3900000,
- .apply_uV = 1,
- //.always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
- },
- .num_consumer_supplies = ARRAY_SIZE(act8891_dcdc2_consumers),
- .consumer_supplies = act8891_dcdc2_consumers
-};
-
-/*buck3 vdd Core*/
-static struct regulator_consumer_supply act8891_dcdc3_consumers[] = {
- {
- .supply = "act_dcdc3",
- }
-};
-
-static struct regulator_init_data act8891_dcdc3_data = {
- .constraints = {
- .name = "ACT_DCDC3",
- .min_uV = 600000,
- .max_uV = 3900000,
- .apply_uV = 1,
- //.always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
- },
- .num_consumer_supplies = ARRAY_SIZE(act8891_dcdc3_consumers),
- .consumer_supplies = act8891_dcdc3_consumers
-};
-
-struct act8891_regulator_subdev act8891_regulator_subdev_id[] = {
- {
- .id=0,
- .initdata=&act8891_ldo1_data,
- },
-
- {
- .id=1,
- .initdata=&act8891_ldo2_data,
- },
-
- {
- .id=2,
- .initdata=&act8891_ldo3_data,
- },
-
- {
- .id=3,
- .initdata=&act8891_ldo4_data,
- },
-
- {
- .id=4,
- .initdata=&act8891_dcdc1_data,
- },
-
- {
- .id=5,
- .initdata=&act8891_dcdc2_data,
- },
- {
- .id=6,
- .initdata=&act8891_dcdc3_data,
- },
-
-};
-
-struct act8891_platform_data act8891_data={
- .set_init=act8891_set_init,
- .num_regulators=7,
- .regulators=act8891_regulator_subdev_id,
-
-};
-#endif
-
-/*****************************************************************************************
- * i2c devices
- * author: kfx@rock-chips.com
-*****************************************************************************************/
-static int rk29_i2c0_io_init(void)
-{
-#ifdef CONFIG_RK29_I2C0_CONTROLLER
- rk29_mux_api_set(GPIO2B7_I2C0SCL_NAME, GPIO2L_I2C0_SCL);
- rk29_mux_api_set(GPIO2B6_I2C0SDA_NAME, GPIO2L_I2C0_SDA);
-#else
- rk29_mux_api_set(GPIO2B7_I2C0SCL_NAME, GPIO2L_GPIO2B7);
- rk29_mux_api_set(GPIO2B6_I2C0SDA_NAME, GPIO2L_GPIO2B6);
-#endif
- return 0;
-}
-
-static int rk29_i2c1_io_init(void)
-{
-#ifdef CONFIG_RK29_I2C1_CONTROLLER
- rk29_mux_api_set(GPIO1A7_I2C1SCL_NAME, GPIO1L_I2C1_SCL);
- rk29_mux_api_set(GPIO1A6_I2C1SDA_NAME, GPIO1L_I2C1_SDA);
-#else
- rk29_mux_api_set(GPIO1A7_I2C1SCL_NAME, GPIO1L_GPIO1A7);
- rk29_mux_api_set(GPIO1A6_I2C1SDA_NAME, GPIO1L_GPIO1A6);
-#endif
- return 0;
-}
-static int rk29_i2c2_io_init(void)
-{
-#ifdef CONFIG_RK29_I2C2_CONTROLLER
- rk29_mux_api_set(GPIO5D4_I2C2SCL_NAME, GPIO5H_I2C2_SCL);
- rk29_mux_api_set(GPIO5D3_I2C2SDA_NAME, GPIO5H_I2C2_SDA);
-#else
- rk29_mux_api_set(GPIO5D4_I2C2SCL_NAME, GPIO5H_GPIO5D4);
- rk29_mux_api_set(GPIO5D3_I2C2SDA_NAME, GPIO5H_GPIO5D3);
-#endif
- return 0;
-}
-
-static int rk29_i2c3_io_init(void)
-{
-#ifdef CONFIG_RK29_I2C3_CONTROLLER
- rk29_mux_api_set(GPIO2B5_UART3RTSN_I2C3SCL_NAME, GPIO2L_I2C3_SCL);
- rk29_mux_api_set(GPIO2B4_UART3CTSN_I2C3SDA_NAME, GPIO2L_I2C3_SDA);
-#else
- rk29_mux_api_set(GPIO2B5_UART3RTSN_I2C3SCL_NAME, GPIO2L_GPIO2B5);
- rk29_mux_api_set(GPIO2B4_UART3CTSN_I2C3SDA_NAME, GPIO2L_GPIO2B4);
-#endif
- return 0;
-}
-#ifdef CONFIG_RK29_I2C0_CONTROLLER
-struct rk29_i2c_platform_data default_i2c0_data = {
- .bus_num = 0,
- .flags = 0,
- .slave_addr = 0xff,
- .scl_rate = 400*1000,
- .mode = I2C_MODE_IRQ,
- .io_init = rk29_i2c0_io_init,
-};
-#else
-struct i2c_gpio_platform_data default_i2c0_data = {
- .sda_pin = RK29_PIN2_PB6,
- .scl_pin = RK29_PIN2_PB7,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(200),
- .bus_num = 0,
- .io_init = rk29_i2c0_io_init,
-};
-#endif
-#ifdef CONFIG_RK29_I2C1_CONTROLLER
-struct rk29_i2c_platform_data default_i2c1_data = {
- .bus_num = 1,
- .flags = 0,
- .slave_addr = 0xff,
- .scl_rate = 400*1000,
- .mode = I2C_MODE_IRQ,
- .io_init = rk29_i2c1_io_init,
-};
-#else
-struct i2c_gpio_platform_data default_i2c1_data = {
- .sda_pin = RK29_PIN1_PA6,
- .scl_pin = RK29_PIN1_PA7,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(200),
- .bus_num = 1,
- .io_init = rk29_i2c1_io_init,
-};
-#endif
-#ifdef CONFIG_RK29_I2C2_CONTROLLER
-struct rk29_i2c_platform_data default_i2c2_data = {
- .bus_num = 2,
- .flags = 0,
- .slave_addr = 0xff,
- .scl_rate = 400*1000,
- .mode = I2C_MODE_IRQ,
- .io_init = rk29_i2c2_io_init,
-};
-#else
-struct i2c_gpio_platform_data default_i2c2_data = {
- .sda_pin = RK29_PIN5_PD3,
- .scl_pin = RK29_PIN5_PD4,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(200),
- .bus_num = 2,
- .io_init = rk29_i2c2_io_init,
-};
-#endif
-#ifdef CONFIG_RK29_I2C3_CONTROLLER
-struct rk29_i2c_platform_data default_i2c3_data = {
- .bus_num = 3,
- .flags = 0,
- .slave_addr = 0xff,
- .scl_rate = 400*1000,
- .mode = I2C_MODE_IRQ,
- .io_init = rk29_i2c3_io_init,
-};
-#else
-struct i2c_gpio_platform_data default_i2c3_data = {
- .sda_pin = RK29_PIN5_PB5,
- .scl_pin = RK29_PIN5_PB4,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(200),
- .bus_num = 3,
- .io_init = rk29_i2c3_io_init,
-};
-#endif
-#ifdef CONFIG_I2C0_RK29
-static struct i2c_board_info __initdata board_i2c0_devices[] = {
-#if defined (CONFIG_RK1000_CONTROL)
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RT5621)
- {
- .type = "rt5621",
- .addr = 0x1a,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RT5631)
- {
- .type = "rt5631",
- .addr = 0x1a,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_WM8988)
- {
- .type = "wm8988",
- .addr = 0x1A,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_WM8900)
- {
- .type = "wm8900",
- .addr = 0x1A,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_BATTERY_STC3100)
- {
- .type = "stc3100",
- .addr = 0x70,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_BATTERY_BQ27510)
- {
- .type = "bq27510",
- .addr = 0x55,
- .flags = 0,
- .platform_data = &bq27510_info,
- },
-#endif
-#if defined (CONFIG_RTC_HYM8563)
- {
- .type = "rtc_hym8563",
- .addr = 0x51,
- .flags = 0,
- .irq = RK29_PIN0_PA1,
- },
-#endif
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1c,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8973)
- {
- .type = "ak8973",
- .addr = 0x1d,
- .flags = 0,
- .irq = RK29_PIN0_PA4,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK29_PIN0_PA4,
- },
-#endif
-#if defined (CONFIG_MPU_SENSORS_MPU3050)
- {
- .type = "mpu3050",
- .addr = 0x68,
- .flags = 0,
- .irq = RK29_PIN4_PC4,
- .platform_data = &mpu3050_data,
- },
-#endif
-#if defined (CONFIG_MPU_SENSORS_KXTF9)
- {
- .type = "kxtf9",
- .addr = 0x0f,
- .flags = 0,
- //.irq = RK29_PIN6_PC4,
- .platform_data = &inv_mpu_kxtf9_data,
- },
-#endif
-#if defined (CONFIG_MPU_SENSORS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- //.irq = RK29_PIN6_PC5,
- .platform_data = &inv_mpu_ak8975_data,
- },
-#endif
-
-#if defined (CONFIG_SND_SOC_CS42L52)
- {
- .type = "cs42l52",
- .addr = 0x4A,
- .flags = 0,
- .platform_data = &cs42l52_info,
- },
-#endif
-#if defined (CONFIG_RTC_M41T66)
- {
- .type = "rtc-M41T66",
- .addr = 0x68,
- .flags = 0,
- .irq = RK29_PIN0_PA1,
- },
-#endif
-};
-#endif
-#if defined (CONFIG_ANX7150)
-struct hdmi_platform_data anx7150_data = {
- //.io_init = anx7150_io_init,
-};
-#endif
-#ifdef CONFIG_I2C1_RK29
-static struct i2c_board_info __initdata board_i2c1_devices[] = {
-#if defined (CONFIG_RK1000_CONTROL1)
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_ANX7150)
- {
- .type = "anx7150",
- .addr = 0x39, //0x39, 0x3d
- .flags = 0,
- .irq = RK29_PIN1_PD7,
- .platform_data = &anx7150_data,
- },
-#endif
-#ifdef CONFIG_BU92747GUW_CIR
- {
- .type ="bu92747_cir",
- .addr = 0x77,
- .flags =0,
- .irq = BU92747_CIR_IRQ_PIN,
- .platform_data = &bu92747guw_pdata,
- },
-#endif
-#ifdef CONFIG_MFD_RK610
- {
- .type = "rk610_ctl",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#ifdef CONFIG_RK610_TVOUT
- {
- .type = "rk610_tvout",
- .addr = 0x42,
- .flags = 0,
- },
-#endif
-#ifdef CONFIG_RK610_HDMI
- {
- .type = "rk610_hdmi",
- .addr = 0x46,
- .flags = 0,
- .irq = RK29_PIN1_PD7,
- },
-#endif
-#ifdef CONFIG_SND_SOC_RK610
- {
- .type = "rk610_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- .platform_data = &rk610_codec_pdata,
- },
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C2_RK29
-static struct i2c_board_info __initdata board_i2c2_devices[] = {
-#if defined (CONFIG_HANNSTAR_P1003)
- {
- .type = "p1003_touch",
- .addr = 0x04,
- .flags = 0, //I2C_M_NEED_DELAY
- .irq = RK29_PIN0_PA2,
- .platform_data = &p1003_info,
- //.udelay = 100
- },
-#endif
-#if defined (CONFIG_EETI_EGALAX)
- {
- .type = "egalax_i2c",
- .addr = 0x04,
- .flags = 0,
- .irq = RK29_PIN0_PA2,
- .platform_data = &eeti_egalax_info,
- },
-#endif
-#if defined (CONFIG_TOUCHSCREEN_GT819)
- {
- .type = "Goodix-TS",
- .addr = 0x55,
- .flags =0,
- .irq =RK29_PIN0_PA2,
- .platform_data = &goodix_info,
- },
-#endif
-#if defined (CONFIG_TOUCHSCREEN_FT5406)
- {
- .type ="ft5x0x_ts",
- .addr = 0x38, //0x70,
- .flags =0,
- .irq =RK29_PIN0_PA2, // support goodix tp detect, 20110706
- .platform_data = &ft5406_info,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK29
-static struct i2c_board_info __initdata board_i2c3_devices[] = {
-#if defined (CONFIG_BATTERY_BQ27541)
- {
- .type = "bq27541",
- .addr = 0x55,
- .flags = 0,
- .platform_data = &bq27541_info,
- },
-#endif
-#if defined (CONFIG_REGULATOR_ACT8891)
- {
- .type = "act8891",
- .addr = 0x5b,
- .flags = 0,
- .platform_data=&act8891_data,
- },
-#endif
-
-};
-#endif
-
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#define CONFIG_SENSOR_POWER_IOCTL_USR 0
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_RESET_IOCTL_USR
-static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
-static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-#include "../../../drivers/media/video/rk29_camera.c"
-#endif
-/*****************************************************************************************
- * backlight devices
- * author: nzy@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- /*
- GPIO1B5_PWM0_NAME, GPIO1L_PWM0
- GPIO5D2_PWM1_UART1SIRIN_NAME, GPIO5H_PWM1
- GPIO2A3_SDMMC0WRITEPRT_PWM2_NAME, GPIO2L_PWM2
- GPIO1A5_EMMCPWREN_PWM3_NAME, GPIO1L_PWM3
- */
-
-#define PWM_ID 0
-#define PWM_MUX_NAME GPIO1B5_PWM0_NAME
-#define PWM_MUX_MODE GPIO1L_PWM0
-#define PWM_MUX_MODE_GPIO GPIO1L_GPIO1B5
-#define PWM_GPIO RK29_PIN1_PB5
-#define PWM_EFFECT_VALUE 1
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-//#define BL_EN_MUX_NAME GPIOF34_UART3_SEL_NAME
-//#define BL_EN_MUX_MODE IOMUXB_GPIO1_B34
-
-#define BL_EN_PIN RK29_PIN6_PD0
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
-
- rk29_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
- #ifdef LCD_DISP_ON_PIN
- // rk29_mux_api_set(BL_EN_MUX_NAME, BL_EN_MUX_MODE);
-
- ret = gpio_request(BL_EN_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(BL_EN_PIN);
- }
-
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
- #endif
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0;
- #ifdef LCD_DISP_ON_PIN
- gpio_free(BL_EN_PIN);
- #endif
- rk29_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
-
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret = 0;
- rk29_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- if (gpio_request(PWM_GPIO, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- gpio_direction_output(PWM_GPIO, GPIO_LOW);
- #ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, !BL_EN_VALUE);
- #endif
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- gpio_free(PWM_GPIO);
- rk29_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
-
- #ifdef LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, 1);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
- #endif
- return 0;
-}
-
-struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-#endif
-/*****************************************************************************************
-* pwm voltage regulator devices
-******************************************************************************************/
-#if defined (CONFIG_RK29_PWM_REGULATOR)
-
-#define REGULATOR_PWM_ID 2
-#define REGULATOR_PWM_MUX_NAME GPIO2A3_SDMMC0WRITEPRT_PWM2_NAME
-#define REGULATOR_PWM_MUX_MODE GPIO2L_PWM2
-#define REGULATOR_PWM_MUX_MODE_GPIO GPIO2L_GPIO2A3
-#define REGULATOR_PWM_GPIO RK29_PIN2_PA3
-
-static struct regulator_consumer_supply pwm_consumers[] = {
- {
- .supply = "vcore",
- }
-};
-
-static struct regulator_init_data rk29_pwm_regulator_data = {
- .constraints = {
- .name = "PWM2",
- .min_uV = 950000,
- .max_uV = 1400000,
- .apply_uV = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_consumers),
- .consumer_supplies = pwm_consumers,
-};
-
-static struct pwm_platform_data rk29_regulator_pwm_platform_data = {
- .pwm_id = REGULATOR_PWM_ID,
- .pwm_gpio = REGULATOR_PWM_GPIO,
- //.pwm_iomux_name[] = REGULATOR_PWM_MUX_NAME;
- .pwm_iomux_name = REGULATOR_PWM_MUX_NAME,
- .pwm_iomux_pwm = REGULATOR_PWM_MUX_MODE,
- .pwm_iomux_gpio = REGULATOR_PWM_MUX_MODE_GPIO,
- .init_data = &rk29_pwm_regulator_data,
-};
-
-static struct platform_device rk29_device_pwm_regulator = {
- .name = "pwm-voltage-regulator",
- .id = -1,
- .dev = {
- .platform_data = &rk29_regulator_pwm_platform_data,
- },
-};
-
-#endif
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
-#define SDMMC0_WRITE_PROTECT_PIN RK29_PIN6_PB0 //According to your own project to set the value of write-protect-pin.
-#endif
-
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
-#define SDMMC1_WRITE_PROTECT_PIN RK29_PIN6_PB0 //According to your own project to set the value of write-protect-pin.
-#endif
-
-/*****************************************************************************************
- * SDMMC devices
-*****************************************************************************************/
-#if !defined(CONFIG_SDMMC_RK29_OLD)
-static void rk29_sdmmc_gpio_open(int device_id, int on)
-{
- switch(device_id)
- {
- case 0://mmc0
- {
- #ifdef CONFIG_SDMMC0_RK29
- if(on)
- {
- gpio_direction_output(RK29_PIN1_PD0,GPIO_HIGH);//set mmc0-clk to high
- gpio_direction_output(RK29_PIN1_PD1,GPIO_HIGH);//set mmc0-cmd to high.
- gpio_direction_output(RK29_PIN1_PD2,GPIO_HIGH);//set mmc0-data0 to high.
- gpio_direction_output(RK29_PIN1_PD3,GPIO_HIGH);//set mmc0-data1 to high.
- gpio_direction_output(RK29_PIN1_PD4,GPIO_HIGH);//set mmc0-data2 to high.
- gpio_direction_output(RK29_PIN1_PD5,GPIO_HIGH);//set mmc0-data3 to high.
-
- mdelay(30);
- }
- else
- {
- rk29_mux_api_set(GPIO1D0_SDMMC0CLKOUT_NAME, GPIO1H_GPIO1_D0);
- gpio_request(RK29_PIN1_PD0, "mmc0-clk");
- gpio_direction_output(RK29_PIN1_PD0,GPIO_LOW);//set mmc0-clk to low.
-
- rk29_mux_api_set(GPIO1D1_SDMMC0CMD_NAME, GPIO1H_GPIO1_D1);
- gpio_request(RK29_PIN1_PD1, "mmc0-cmd");
- gpio_direction_output(RK29_PIN1_PD1,GPIO_LOW);//set mmc0-cmd to low.
-
- rk29_mux_api_set(GPIO1D2_SDMMC0DATA0_NAME, GPIO1H_GPIO1D2);
- gpio_request(RK29_PIN1_PD2, "mmc0-data0");
- gpio_direction_output(RK29_PIN1_PD2,GPIO_LOW);//set mmc0-data0 to low.
-
- rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_GPIO1D3);
- gpio_request(RK29_PIN1_PD3, "mmc0-data1");
- gpio_direction_output(RK29_PIN1_PD3,GPIO_LOW);//set mmc0-data1 to low.
-
- rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_GPIO1D4);
- gpio_request(RK29_PIN1_PD4, "mmc0-data2");
- gpio_direction_output(RK29_PIN1_PD4,GPIO_LOW);//set mmc0-data2 to low.
-
- rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_GPIO1D5);
- gpio_request(RK29_PIN1_PD5, "mmc0-data3");
- gpio_direction_output(RK29_PIN1_PD5,GPIO_LOW);//set mmc0-data3 to low.
-
- mdelay(30);
- }
- #endif
- }
- break;
-
- case 1://mmc1
- {
- #ifdef CONFIG_SDMMC1_RK29
- if(on)
- {
- gpio_direction_output(RK29_PIN1_PC7,GPIO_HIGH);//set mmc1-clk to high
- gpio_direction_output(RK29_PIN1_PC2,GPIO_HIGH);//set mmc1-cmd to high.
- gpio_direction_output(RK29_PIN1_PC3,GPIO_HIGH);//set mmc1-data0 to high.
- gpio_direction_output(RK29_PIN1_PC4,GPIO_HIGH);//set mmc1-data1 to high.
- gpio_direction_output(RK29_PIN1_PC5,GPIO_HIGH);//set mmc1-data2 to high.
- gpio_direction_output(RK29_PIN1_PC6,GPIO_HIGH);//set mmc1-data3 to high.
- mdelay(100);
- }
- else
- {
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_GPIO1C7);
- gpio_request(RK29_PIN1_PC7, "mmc1-clk");
- gpio_direction_output(RK29_PIN1_PC7,GPIO_LOW);//set mmc1-clk to low.
-
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_GPIO1C2);
- gpio_request(RK29_PIN1_PC2, "mmc1-cmd");
- gpio_direction_output(RK29_PIN1_PC2,GPIO_LOW);//set mmc1-cmd to low.
-
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_GPIO1C3);
- gpio_request(RK29_PIN1_PC3, "mmc1-data0");
- gpio_direction_output(RK29_PIN1_PC3,GPIO_LOW);//set mmc1-data0 to low.
-
- mdelay(100);
- }
- #endif
- }
- break;
-
- case 2: //mmc2
- break;
-
- default:
- break;
- }
-}
-
-static void rk29_sdmmc_set_iomux_mmc0(unsigned int bus_width)
-{
- switch (bus_width)
- {
-
- case 1://SDMMC_CTYPE_4BIT:
- {
- rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_SDMMC0_DATA1);
- rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_SDMMC0_DATA2);
- rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_SDMMC0_DATA3);
- }
- break;
-
- case 0x10000://SDMMC_CTYPE_8BIT:
- break;
- case 0xFFFF: //gpio_reset
- {
- rk29_mux_api_set(GPIO5D5_SDMMC0PWREN_NAME, GPIO5H_GPIO5D5);
- gpio_request(RK29_PIN5_PD5,"sdmmc-power");
- gpio_direction_output(RK29_PIN5_PD5,GPIO_HIGH); //power-off
-
- rk29_sdmmc_gpio_open(0, 0);
-
- gpio_direction_output(RK29_PIN5_PD5,GPIO_LOW); //power-on
-
- rk29_sdmmc_gpio_open(0, 1);
- }
- break;
-
- default: //case 0://SDMMC_CTYPE_1BIT:
- {
- rk29_mux_api_set(GPIO1D1_SDMMC0CMD_NAME, GPIO1H_SDMMC0_CMD);
- rk29_mux_api_set(GPIO1D0_SDMMC0CLKOUT_NAME, GPIO1H_SDMMC0_CLKOUT);
- rk29_mux_api_set(GPIO1D2_SDMMC0DATA0_NAME, GPIO1H_SDMMC0_DATA0);
-
- rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_GPIO1D3);
- gpio_request(RK29_PIN1_PD3, "mmc0-data1");
- gpio_direction_output(RK29_PIN1_PD3,GPIO_HIGH);
-
- rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_GPIO1D4);
- gpio_request(RK29_PIN1_PD4, "mmc0-data2");
- gpio_direction_output(RK29_PIN1_PD4,GPIO_HIGH);
-
- rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_GPIO1D5);
- gpio_request(RK29_PIN1_PD5, "mmc0-data3");
- gpio_direction_output(RK29_PIN1_PD5,GPIO_HIGH);
- }
- break;
- }
-}
-
-static void rk29_sdmmc_set_iomux_mmc1(unsigned int bus_width)
-{
-#if 0
- switch (bus_width)
- {
-
- case 1://SDMMC_CTYPE_4BIT:
- {
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);
- rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_SDMMC1_DATA1);
- rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_SDMMC1_DATA2);
- rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_SDMMC1_DATA3);
- }
- break;
-
- case 0x10000://SDMMC_CTYPE_8BIT:
- break;
- case 0xFFFF:
- {
- rk29_sdmmc_gpio_open(1, 0);
- rk29_sdmmc_gpio_open(1, 1);
- }
- break;
-
- default: //case 0://SDMMC_CTYPE_1BIT:
- {
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);
-
- rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_GPIO1C4);
- gpio_request(RK29_PIN1_PC4, "mmc1-data1");
- gpio_direction_output(RK29_PIN1_PC4,GPIO_HIGH);
-
- rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_GPIO1C5);
- gpio_request(RK29_PIN1_PC5, "mmc1-data2");
- gpio_direction_output(RK29_PIN1_PC5,GPIO_HIGH);
-
- rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_GPIO1C6);
- gpio_request(RK29_PIN1_PC6, "mmc1-data3");
- gpio_direction_output(RK29_PIN1_PC6,GPIO_HIGH);
-
- }
- break;
- }
-#else
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);
- rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_SDMMC1_DATA1);
- rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_SDMMC1_DATA2);
- rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_SDMMC1_DATA3);
-
-#endif
-}
-
-static void rk29_sdmmc_set_iomux_mmc2(unsigned int bus_width)
-{
- ;//
-}
-
-
-static void rk29_sdmmc_set_iomux(int device_id, unsigned int bus_width)
-{
- switch(device_id)
- {
- case 0:
- #ifdef CONFIG_SDMMC0_RK29
- rk29_sdmmc_set_iomux_mmc0(bus_width);
- #endif
- break;
- case 1:
- #ifdef CONFIG_SDMMC1_RK29
- rk29_sdmmc_set_iomux_mmc1(bus_width);
- #endif
- break;
- case 2:
- rk29_sdmmc_set_iomux_mmc2(bus_width);
- break;
- default:
- break;
- }
-}
-
-#endif
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
-static int rk29sdk_wifi_status(struct device *dev);
-static int rk29sdk_wifi_status_register(void (*callback)(int card_presend, void *dev_id), void *dev_id);
-#endif
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- rk29_mux_api_set(GPIO1D1_SDMMC0CMD_NAME, GPIO1H_SDMMC0_CMD);
- rk29_mux_api_set(GPIO1D0_SDMMC0CLKOUT_NAME, GPIO1H_SDMMC0_CLKOUT);
- rk29_mux_api_set(GPIO1D2_SDMMC0DATA0_NAME, GPIO1H_SDMMC0_DATA0);
- rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_SDMMC0_DATA1);
- rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_SDMMC0_DATA2);
- rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_SDMMC0_DATA3);
-
- rk29_mux_api_set(GPIO2A2_SDMMC0DETECTN_NAME, GPIO2L_GPIO2A2);
-
- rk29_mux_api_set(GPIO5D5_SDMMC0PWREN_NAME, GPIO5H_GPIO5D5); ///GPIO5H_SDMMC0_PWR_EN); ///GPIO5H_GPIO5D5);
- gpio_request(RK29_PIN5_PD5,"sdmmc");
-#if 0
- gpio_set_value(RK29_PIN5_PD5,GPIO_HIGH);
- mdelay(100);
- gpio_set_value(RK29_PIN5_PD5,GPIO_LOW);
-#else
- gpio_direction_output(RK29_PIN5_PD5,GPIO_LOW);
-#endif
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- rk29_mux_api_set(GPIO2A2_SDMMC0DETECTN_NAME, GPIO2L_SDMMC0_DETECT_N);//Modifyed by xbw.
-
- #if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN,"sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
- #endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail = (MMC_VDD_25_26|MMC_VDD_26_27|MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30|
- MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33|
- MMC_VDD_33_34|MMC_VDD_34_35| MMC_VDD_35_36),
- .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
- .detect_irq = RK29_PIN2_PA2, // INVALID_GPIO
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
-#else
- .write_prt = INVALID_GPIO,
-#endif
-};
-#endif
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);
- rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_SDMMC1_DATA1);
- rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_SDMMC1_DATA2);
- rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_SDMMC1_DATA3);
- //rk29_mux_api_set(GPIO1C0_UART0CTSN_SDMMC1DETECTN_NAME, GPIO1H_SDMMC1_DETECT_N);
-
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN,"sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-
-
-#define RK29SDK_WIFI_SDIO_CARD_DETECT_N RK29_PIN1_PD6
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail = (MMC_VDD_25_26|MMC_VDD_26_27|MMC_VDD_27_28|MMC_VDD_28_29|
- MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32|
- MMC_VDD_32_33|MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_SDIO_IRQ|
- MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-#if 0
- .detect_irq = RK29SDK_WIFI_SDIO_CARD_DETECT_N,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
-#else
-//for wifi develop board
- .detect_irq = INVALID_GPIO,
- .enable_sd_wakeup = 0,
-#endif
-
-};
-#endif ////endif--#ifdef CONFIG_SDMMC1_RK29
-
-
-int rk29sdk_wifi_power_state = 0;
-int rk29sdk_bt_power_state = 0;
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
-#define RK29SDK_WIFI_BT_GPIO_POWER_N RK29_PIN5_PD6
-#define RK29SDK_WIFI_GPIO_RESET_N RK29_PIN6_PC0
-
-static int rk29sdk_wifi_cd = 0; /* wifi virtual 'card detect' status */
-static void (*wifi_status_cb)(int card_present, void *dev_id);
-static void *wifi_status_cb_devid;
-
-static int rk29sdk_wifi_status(struct device *dev)
-{
- return rk29sdk_wifi_cd;
-}
-
-static int rk29sdk_wifi_status_register(void (*callback)(int card_present, void *dev_id), void *dev_id)
-{
- if(wifi_status_cb)
- return -EAGAIN;
- wifi_status_cb = callback;
- wifi_status_cb_devid = dev_id;
- return 0;
-}
-
-static int rk29sdk_wifi_bt_gpio_control_init(void)
-{
- if (gpio_request(RK29SDK_WIFI_BT_GPIO_POWER_N, "wifi_bt_power")) {
- pr_info("%s: request wifi_bt power gpio failed\n", __func__);
- return -1;
- }
-
- if (gpio_request(RK29SDK_WIFI_GPIO_RESET_N, "wifi reset")) {
- pr_info("%s: request wifi reset gpio failed\n", __func__);
- gpio_free(RK29SDK_WIFI_BT_GPIO_POWER_N);
- return -1;
- }
-
- gpio_direction_output(RK29SDK_WIFI_BT_GPIO_POWER_N, GPIO_LOW);
- gpio_direction_output(RK29SDK_WIFI_GPIO_RESET_N, GPIO_LOW);
-
- #if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
-
- rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_GPIO1C4);
- gpio_request(RK29_PIN1_PC4, "mmc1-data1");
- gpio_direction_output(RK29_PIN1_PC4,GPIO_LOW);//set mmc1-data1 to low.
-
- rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_GPIO1C5);
- gpio_request(RK29_PIN1_PC5, "mmc1-data2");
- gpio_direction_output(RK29_PIN1_PC5,GPIO_LOW);//set mmc1-data2 to low.
-
- rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_GPIO1C6);
- gpio_request(RK29_PIN1_PC6, "mmc1-data3");
- gpio_direction_output(RK29_PIN1_PC6,GPIO_LOW);//set mmc1-data3 to low.
-
- rk29_sdmmc_gpio_open(1, 0); //added by xbw at 2011-10-13
- #endif
- pr_info("%s: init finished\n",__func__);
-
- return 0;
-}
-
-static int rk29sdk_wifi_power(int on)
-{
- pr_info("%s: %d\n", __func__, on);
- if (on){
- gpio_set_value(RK29SDK_WIFI_BT_GPIO_POWER_N, GPIO_HIGH);
-
- #if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
- rk29_sdmmc_gpio_open(1, 1); //added by xbw at 2011-10-13
- #endif
-
- gpio_set_value(RK29SDK_WIFI_GPIO_RESET_N, GPIO_HIGH);
- mdelay(100);
- pr_info("wifi turn on power\n");
- }else{
- if (!rk29sdk_bt_power_state){
- gpio_set_value(RK29SDK_WIFI_BT_GPIO_POWER_N, GPIO_LOW);
-
- #if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
- rk29_sdmmc_gpio_open(1, 0); //added by xbw at 2011-10-13
- #endif
-
- mdelay(100);
- pr_info("wifi shut off power\n");
- }else
- {
- pr_info("wifi shouldn't shut off power, bt is using it!\n");
- }
- gpio_set_value(RK29SDK_WIFI_GPIO_RESET_N, GPIO_LOW);
-
- }
-
- rk29sdk_wifi_power_state = on;
- return 0;
-}
-
-static int rk29sdk_wifi_reset_state;
-static int rk29sdk_wifi_reset(int on)
-{
- pr_info("%s: %d\n", __func__, on);
- gpio_set_value(RK29SDK_WIFI_GPIO_RESET_N, on);
- mdelay(100);
- rk29sdk_wifi_reset_state = on;
- return 0;
-}
-
-int rk29sdk_wifi_set_carddetect(int val)
-{
- pr_info("%s:%d\n", __func__, val);
- rk29sdk_wifi_cd = val;
- if (wifi_status_cb){
- wifi_status_cb(val, wifi_status_cb_devid);
- }else {
- pr_warning("%s, nobody to notify\n", __func__);
- }
- return 0;
-}
-EXPORT_SYMBOL(rk29sdk_wifi_set_carddetect);
-
-static struct wifi_mem_prealloc wifi_mem_array[PREALLOC_WLAN_SEC_NUM] = {
- {NULL, (WLAN_SECTION_SIZE_0 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_1 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_2 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_3 + PREALLOC_WLAN_SECTION_HEADER)}
-};
-
-static void *rk29sdk_mem_prealloc(int section, unsigned long size)
-{
- if (section == PREALLOC_WLAN_SEC_NUM)
- return wlan_static_skb;
-
- if ((section < 0) || (section > PREALLOC_WLAN_SEC_NUM))
- return NULL;
-
- if (wifi_mem_array[section].size < size)
- return NULL;
-
- return wifi_mem_array[section].mem_ptr;
-}
-
-int __init rk29sdk_init_wifi_mem(void)
-{
- int i;
- int j;
-
- for (i = 0 ; i < WLAN_SKB_BUF_NUM ; i++) {
- wlan_static_skb[i] = dev_alloc_skb(
- ((i < (WLAN_SKB_BUF_NUM / 2)) ? 4096 : 8192));
-
- if (!wlan_static_skb[i])
- goto err_skb_alloc;
- }
-
- for (i = 0 ; i < PREALLOC_WLAN_SEC_NUM ; i++) {
- wifi_mem_array[i].mem_ptr =
- kmalloc(wifi_mem_array[i].size, GFP_KERNEL);
-
- if (!wifi_mem_array[i].mem_ptr)
- goto err_mem_alloc;
- }
- return 0;
-
-err_mem_alloc:
- pr_err("Failed to mem_alloc for WLAN\n");
- for (j = 0 ; j < i ; j++)
- kfree(wifi_mem_array[j].mem_ptr);
-
- i = WLAN_SKB_BUF_NUM;
-
-err_skb_alloc:
- pr_err("Failed to skb_alloc for WLAN\n");
- for (j = 0 ; j < i ; j++)
- dev_kfree_skb(wlan_static_skb[j]);
-
- return -ENOMEM;
-}
-
-static struct wifi_platform_data rk29sdk_wifi_control = {
- .set_power = rk29sdk_wifi_power,
- .set_reset = rk29sdk_wifi_reset,
- .set_carddetect = rk29sdk_wifi_set_carddetect,
- .mem_prealloc = rk29sdk_mem_prealloc,
-};
-static struct platform_device rk29sdk_wifi_device = {
- .name = "bcm4329_wlan",
- .id = 1,
- .dev = {
- .platform_data = &rk29sdk_wifi_control,
- },
-};
-#endif
-
-
-//#ifdef CONFIG_VIVANTE
-#define GPU_HIGH_CLOCK 552
-#define GPU_LOW_CLOCK (periph_pll_default / 1000000) /* same as general pll clock rate below */
-static struct resource resources_gpu[] = {
- [0] = {
- .name = "gpu_irq",
- .start = IRQ_GPU,
- .end = IRQ_GPU,
- .flags = IORESOURCE_IRQ,
- },
- [1] = {
- .name = "gpu_base",
- .start = RK29_GPU_PHYS,
- .end = RK29_GPU_PHYS + RK29_GPU_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "gpu_mem",
- .start = PMEM_GPU_BASE,
- .end = PMEM_GPU_BASE + PMEM_GPU_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [3] = {
- .name = "gpu_clk",
- .start = GPU_LOW_CLOCK,
- .end = GPU_HIGH_CLOCK,
- .flags = IORESOURCE_IO,
- },
-};
-static struct platform_device rk29_device_gpu = {
- .name = "galcore",
- .id = 0,
- .num_resources = ARRAY_SIZE(resources_gpu),
- .resource = resources_gpu,
-};
-//#endif
-
-#ifdef CONFIG_KEYS_RK29
-extern struct rk29_keys_platform_data rk29_keys_pdata;
-static struct platform_device rk29_device_keys = {
- .name = "rk29-keypad",
- .id = -1,
- .dev = {
- .platform_data = &rk29_keys_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
-struct gpio_led rk29_leds[] = {
- {
- .name = "rk29_red_led",
- .gpio = RK29_PIN4_PB2,
- .default_trigger = "timer",
- .active_low = 0,
- .retain_state_suspended = 1,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- },
- {
- .name = "rk29_green_led",
- .gpio = RK29_PIN4_PB1,
- .default_trigger = "timer",
- .active_low = 0,
- .retain_state_suspended = 1,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- },
- {
- .name = "rk29_blue_led",
- .gpio = RK29_PIN4_PB0,
- .default_trigger = "timer",
- .active_low = 0,
- .retain_state_suspended = 1,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- },
-};
-
-struct gpio_led_platform_data rk29_leds_pdata = {
- .leds = &rk29_leds,
- .num_leds = ARRAY_SIZE(rk29_leds),
-};
-
-struct platform_device rk29_device_gpio_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_leds_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_LEDS_NEWTON_PWM
-static struct led_newton_pwm rk29_pwm_leds[] = {
- {
- .name = "power_led",
- .pwm_id = 1,
- .pwm_gpio = RK29_PIN5_PD2,
- .pwm_iomux_name = GPIO5D2_PWM1_UART1SIRIN_NAME,
- .pwm_iomux_pwm = GPIO5H_PWM1,
- .pwm_iomux_gpio = GPIO5H_GPIO5D2,
- .freq = 1000,
- .period = 255,
- },
-};
-
-static struct led_newton_pwm_platform_data rk29_pwm_leds_pdata = {
- .leds = &rk29_pwm_leds,
- .num_leds = ARRAY_SIZE(rk29_pwm_leds),
-};
-
-static struct platform_device rk29_device_pwm_leds = {
- .name = "leds_newton_pwm",
- .id = -1,
- .dev = {
- .platform_data = &rk29_pwm_leds_pdata,
- },
-};
-
-#endif
-
-#ifdef CONFIG_BT
-// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
-static struct rfkill_rk_platform_data rfkill_rk_platdata = {
- .type = RFKILL_TYPE_BLUETOOTH,
-
- .poweron_gpio = { // BT_REG_ON
- .io = RK29_PIN5_PD6,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO5D6_SDMMC1PWREN_NAME,
- .fgpio = GPIO5H_GPIO5D6,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK29_PIN6_PC4, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = NULL,
- },
- },
-
- .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
- .io = RK29_PIN6_PC5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .gpio = {
- .io = INVALID_GPIO/*RK30_PIN6_PA2*/, // set io to INVALID_GPIO for disable it
- },
- },
-
- .rts_gpio = { // UART_RTS, enable or disable BT's data coming
- .io = RK29_PIN2_PA7, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = GPIO2A7_UART2RTSN_NAME,
- .fgpio = GPIO2L_GPIO2A7,
- .fmux = GPIO2L_UART2_RTS_N,
- },
- },
-};
-
-struct platform_device device_rfkill_rk = {
- .name = "rfkill_rk",
- .id = -1,
- .dev = {
- .platform_data = &rfkill_rk_platdata,
- },
-};
-#endif
-
-static void __init rk29_board_iomux_init(void)
-{
- #ifdef CONFIG_RK29_PWM_REGULATOR
- rk29_mux_api_set(REGULATOR_PWM_MUX_NAME,REGULATOR_PWM_MUX_MODE);
- #endif
-}
-
-static struct platform_device *devices[] __initdata = {
-
-#ifdef CONFIG_RK29_WATCHDOG
- &rk29_device_wdt,
-#endif
-
-#ifdef CONFIG_UART1_RK29
- &rk29_device_uart1,
-#endif
-#ifdef CONFIG_UART0_RK29
- &rk29_device_uart0,
-#endif
-#ifdef CONFIG_UART2_RK29
- &rk29_device_uart2,
-#endif
-#ifdef CONFIG_UART3_RK29
- &rk29_device_uart3,
-#endif
-
-#ifdef CONFIG_RK29_PWM_REGULATOR
- &rk29_device_pwm_regulator,
-#endif
-#ifdef CONFIG_SPIM0_RK29
- &rk29xx_device_spi0m,
-#endif
-#ifdef CONFIG_SPIM1_RK29
- &rk29xx_device_spi1m,
-#endif
-#ifdef CONFIG_ADC_RK29
- &rk29_device_adc,
-#endif
-#ifdef CONFIG_BATTERY_RK29_ADC
- &rk29_device_adc_battery,
-#endif
-#ifdef CONFIG_I2C0_RK29
- &rk29_device_i2c0,
-#endif
-#ifdef CONFIG_I2C1_RK29
- &rk29_device_i2c1,
-#endif
-#ifdef CONFIG_I2C2_RK29
- &rk29_device_i2c2,
-#endif
-#ifdef CONFIG_I2C3_RK29
- &rk29_device_i2c3,
-#endif
-
-#ifdef CONFIG_SND_RK29_SOC_I2S_2CH
- &rk29_device_iis_2ch,
-#endif
-#ifdef CONFIG_SND_RK29_SOC_I2S_8CH
- &rk29_device_iis_8ch,
-#endif
-
-#ifdef CONFIG_KEYS_RK29
- &rk29_device_keys,
-#endif
-#ifdef CONFIG_KEYS_RK29_NEWTON
- &rk29_device_keys,
-#endif
-#ifdef CONFIG_SDMMC0_RK29
- &rk29_device_sdmmc0,
-#endif
-#ifdef CONFIG_SDMMC1_RK29
- &rk29_device_sdmmc1,
-#endif
-
-#ifdef CONFIG_MTD_NAND_RK29XX
- &rk29xx_device_nand,
-#endif
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- &rk29sdk_wifi_device,
-#endif
-
-#ifdef CONFIG_MTD_NAND_RK29
- &rk29_device_nand,
-#endif
-
-#ifdef CONFIG_FB_RK29
- &rk29_device_fb,
- &rk29_device_dma_cpy,
-#endif
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- &rk29_device_backlight,
-#endif
-#ifdef CONFIG_BACKLIGHT_RK29_NEWTON_BL
- &rk29_device_backlight,
-#endif
-#ifdef CONFIG_RK29_VMAC
- &rk29_device_vmac,
-#endif
-//#ifdef CONFIG_VIVANTE
- &rk29_device_gpu,
-//#endif
-#ifdef CONFIG_VIDEO_RK29
- &rk29_device_camera, /* ddl@rock-chips.com : camera support */
- #if (CONFIG_SENSOR_IIC_ADDR_0 != 0x00)
- &rk29_soc_camera_pdrv_0,
- #endif
- #if (CONFIG_SENSOR_IIC_ADDR_1 != 0x00)
- &rk29_soc_camera_pdrv_1,
- #endif
- #if (PMEM_CAM_SIZE > 0)
- &android_pmem_cam_device,
- #endif
-#endif
-#if PMEM_SKYPE_SIZE > 0
- &android_pmem_skype_device,
-#endif
-#ifdef CONFIG_ION
- &rk29_ion_device,
-#endif
- &android_pmem_device,
- &rk29_vpu_mem_device,
-#ifdef CONFIG_USB20_OTG
- &rk29_device_usb20_otg,
-#endif
-#ifdef CONFIG_USB20_HOST
- &rk29_device_usb20_host,
-#endif
-#ifdef CONFIG_USB11_HOST
- &rk29_device_usb11_host,
-#endif
-#ifdef CONFIG_USB_ANDROID
- &android_usb_device,
- &usb_mass_storage_device,
-#endif
-#ifdef CONFIG_USB_ANDROID_RNDIS
- &rk29_device_rndis,
-#endif
-
-//#ifdef CONFIG_RK29_IPP
- &rk29_device_ipp,
-//#endif
-
-#ifdef CONFIG_VIDEO_RK29XX_VOUT
- &rk29_v4l2_output_devce,
-#endif
-#ifdef CONFIG_RK29_NEWTON
- &rk29_device_newton,
-#endif
-#ifdef CONFIG_RK_IRDA
- &irda_device,
-#endif
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
- &rk29_device_gpio_leds,
-#endif
-#ifdef CONFIG_LEDS_NEWTON_PWM
- &rk29_device_pwm_leds,
-#endif
-#ifdef CONFIG_SND_RK29_SOC_CS42L52
- &rk29_cs42l52_device,
-#endif
-#ifdef CONFIG_RFKILL_RK
- &device_rfkill_rk,
-#endif
-};
-
-/*****************************************************************************************
- * spi devices
- * author: cmc@rock-chips.com
- *****************************************************************************************/
-
-#define BIT_EMAC_SPEED (1 << 10)
-static int rk29_vmac_speed_switch(int speed)
-{
- printk("%s--speed=%d\n", __FUNCTION__, speed);
- if (10 == speed) {
- writel(readl(RK29_GRF_BASE + 0xbc) & (~BIT_EMAC_SPEED), RK29_GRF_BASE + 0xbc);
- } else {
- writel(readl(RK29_GRF_BASE + 0xbc) | BIT_EMAC_SPEED, RK29_GRF_BASE + 0xbc);
- }
-}
-
-static int rk29_vmac_register_set(void)
-{
- //config rk29 vmac as rmii, 100MHz
- u32 value= readl(RK29_GRF_BASE + 0xbc);
- value = (value & 0xfff7ff) | (0x400);
- writel(value, RK29_GRF_BASE + 0xbc);
- return 0;
-}
-
-static int rk29_rmii_io_init(void)
-{
- int err;
-
- //phy power gpio
- err = gpio_request(RK29_PIN6_PB0, "phy_power_en");
- if (err) {
- gpio_free(RK29_PIN6_PB0);
- printk("-------request RK29_PIN6_PB0 fail--------\n");
- return -1;
- }
- //phy power down
- gpio_direction_output(RK29_PIN6_PB0, GPIO_LOW);
- gpio_set_value(RK29_PIN6_PB0, GPIO_LOW);
-
- return 0;
-}
-
-static int rk29_rmii_io_deinit(void)
-{
- //phy power down
- gpio_direction_output(RK29_PIN6_PB0, GPIO_LOW);
- gpio_set_value(RK29_PIN6_PB0, GPIO_LOW);
- //free
- gpio_free(RK29_PIN6_PB0);
- return 0;
-}
-
-static int rk29_rmii_power_control(int enable)
-{
- if (enable) {
- //enable phy power
- gpio_direction_output(RK29_PIN6_PB0, GPIO_HIGH);
- gpio_set_value(RK29_PIN6_PB0, GPIO_HIGH);
- }
- else {
- gpio_direction_output(RK29_PIN6_PB0, GPIO_LOW);
- gpio_set_value(RK29_PIN6_PB0, GPIO_LOW);
- }
- return 0;
-}
-
-struct rk29_vmac_platform_data rk29_vmac_pdata = {
- .vmac_register_set = rk29_vmac_register_set,
- .rmii_io_init = rk29_rmii_io_init,
- .rmii_io_deinit = rk29_rmii_io_deinit,
- .rmii_power_control = rk29_rmii_power_control,
-};
-
-/*****************************************************************************************
- * spi devices
- * author: cmc@rock-chips.com
- *****************************************************************************************/
-#define SPI_CHIPSELECT_NUM 2
-static struct spi_cs_gpio rk29xx_spi0_cs_gpios[SPI_CHIPSELECT_NUM] = {
- {
- .name = "spi0 cs0",
- .cs_gpio = RK29_PIN2_PC1,
- .cs_iomux_name = GPIO2C1_SPI0CSN0_NAME,
- .cs_iomux_mode = GPIO2H_SPI0_CSN0,
- },
- {
- .name = "spi0 cs1",
- .cs_gpio = RK29_PIN1_PA4,
- .cs_iomux_name = GPIO1A4_EMMCWRITEPRT_SPI0CS1_NAME,//if no iomux,set it NULL
- .cs_iomux_mode = GPIO1L_SPI0_CSN1,
- }
-};
-
-static struct spi_cs_gpio rk29xx_spi1_cs_gpios[SPI_CHIPSELECT_NUM] = {
- {
- .name = "spi1 cs0",
- .cs_gpio = RK29_PIN2_PC5,
- .cs_iomux_name = GPIO2C5_SPI1CSN0_NAME,
- .cs_iomux_mode = GPIO2H_SPI1_CSN0,
- },
- {
- .name = "spi1 cs1",
- .cs_gpio = RK29_PIN1_PA3,
- .cs_iomux_name = GPIO1A3_EMMCDETECTN_SPI1CS1_NAME,//if no iomux,set it NULL
- .cs_iomux_mode = GPIO1L_SPI1_CSN1,
- }
-};
-
-static int spi_io_init(struct spi_cs_gpio *cs_gpios, int cs_num)
-{
-#if 1
- int i;
- if (cs_gpios) {
- for (i=0; i<cs_num; i++) {
- rk29_mux_api_set(cs_gpios[i].cs_iomux_name, cs_gpios[i].cs_iomux_mode);
- }
- }
-#endif
- return 0;
-}
-
-static int spi_io_deinit(struct spi_cs_gpio *cs_gpios, int cs_num)
-{
- return 0;
-}
-
-static int spi_io_fix_leakage_bug(void)
-{
-#if 0
- gpio_direction_output(RK29_PIN2_PC1, GPIO_LOW);
-#endif
- return 0;
-}
-
-static int spi_io_resume_leakage_bug(void)
-{
-#if 0
- gpio_direction_output(RK29_PIN2_PC1, GPIO_HIGH);
-#endif
- return 0;
-}
-
-struct rk29xx_spi_platform_data rk29xx_spi0_platdata = {
- .num_chipselect = SPI_CHIPSELECT_NUM,
- .chipselect_gpios = rk29xx_spi0_cs_gpios,
- .io_init = spi_io_init,
- .io_deinit = spi_io_deinit,
- .io_fix_leakage_bug = spi_io_fix_leakage_bug,
- .io_resume_leakage_bug = spi_io_resume_leakage_bug,
-};
-
-struct rk29xx_spi_platform_data rk29xx_spi1_platdata = {
- .num_chipselect = SPI_CHIPSELECT_NUM,
- .chipselect_gpios = rk29xx_spi1_cs_gpios,
- .io_init = spi_io_init,
- .io_deinit = spi_io_deinit,
- .io_fix_leakage_bug = spi_io_fix_leakage_bug,
- .io_resume_leakage_bug = spi_io_resume_leakage_bug,
-};
-
-/*****************************************************************************************
- * xpt2046 touch panel
- * author: cmc@rock-chips.com
- *****************************************************************************************/
-#define XPT2046_GPIO_INT RK29_PIN0_PA3
-#define DEBOUNCE_REPTIME 3
-
-#if defined(CONFIG_TOUCHSCREEN_XPT2046_320X480_SPI)
-static struct xpt2046_platform_data xpt2046_info = {
- .model = 2046,
- .keep_vref_on = 1,
- .swap_xy = 0,
- .x_min = 0,
- .x_max = 320,
- .y_min = 0,
- .y_max = 480,
- .debounce_max = 7,
- .debounce_rep = DEBOUNCE_REPTIME,
- .debounce_tol = 20,
- .gpio_pendown = XPT2046_GPIO_INT,
- .penirq_recheck_delay_usecs = 1,
-};
-#elif defined(CONFIG_TOUCHSCREEN_XPT2046_320X480_CBN_SPI)
-static struct xpt2046_platform_data xpt2046_info = {
- .model = 2046,
- .keep_vref_on = 1,
- .swap_xy = 0,
- .x_min = 0,
- .x_max = 320,
- .y_min = 0,
- .y_max = 480,
- .debounce_max = 7,
- .debounce_rep = DEBOUNCE_REPTIME,
- .debounce_tol = 20,
- .gpio_pendown = XPT2046_GPIO_INT,
- .penirq_recheck_delay_usecs = 1,
-};
-#elif defined(CONFIG_TOUCHSCREEN_XPT2046_SPI)
-static struct xpt2046_platform_data xpt2046_info = {
- .model = 2046,
- .keep_vref_on = 1,
- .swap_xy = 1,
- .x_min = 0,
- .x_max = 800,
- .y_min = 0,
- .y_max = 480,
- .debounce_max = 7,
- .debounce_rep = DEBOUNCE_REPTIME,
- .debounce_tol = 20,
- .gpio_pendown = XPT2046_GPIO_INT,
-
- .penirq_recheck_delay_usecs = 1,
-};
-#elif defined(CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI)
-static struct xpt2046_platform_data xpt2046_info = {
- .model = 2046,
- .keep_vref_on = 1,
- .swap_xy = 1,
- .x_min = 0,
- .x_max = 800,
- .y_min = 0,
- .y_max = 480,
- .debounce_max = 7,
- .debounce_rep = DEBOUNCE_REPTIME,
- .debounce_tol = 20,
- .gpio_pendown = XPT2046_GPIO_INT,
-
- .penirq_recheck_delay_usecs = 1,
-};
-#endif
-
-static struct spi_board_info board_spi_devices[] = {
-#if defined(CONFIG_TOUCHSCREEN_XPT2046_320X480_SPI) || defined(CONFIG_TOUCHSCREEN_XPT2046_320X480_CBN_SPI)\
- ||defined(CONFIG_TOUCHSCREEN_XPT2046_SPI) || defined(CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI)
- {
- .modalias = "xpt2046_ts",
- .chip_select = 0,
- .max_speed_hz = 125 * 1000 * 26,/* (max sample rate @ 3V) * (cmd + data + overhead) */
- .bus_num = 0,
- .irq = XPT2046_GPIO_INT,
- .platform_data = &xpt2046_info,
- },
-#endif
-};
-
-
-static void __init rk29_gic_init_irq(void)
-{
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38))
- gic_init(0, 32, (void __iomem *)RK29_GICPERI_BASE, (void __iomem *)RK29_GICCPU_BASE);
-#else
- gic_dist_init(0, (void __iomem *)RK29_GICPERI_BASE, 32);
- gic_cpu_init(0, (void __iomem *)RK29_GICCPU_BASE);
-#endif
-}
-
-static void __init machine_rk29_init_irq(void)
-{
- rk29_gic_init_irq();
- rk29_gpio_init();
-}
-
-static struct cpufreq_frequency_table freq_table[] = {
- { .index = 1200000, .frequency = 408000 },
- { .index = 1200000, .frequency = 816000 },
- { .index = 1300000, .frequency = 1008000 },
- { .frequency = CPUFREQ_TABLE_END },
-};
-
-static void __init machine_rk29_board_init(void)
-{
- rk29_board_iomux_init();
-
- board_power_init();
- board_update_cpufreq_table(freq_table);
-
- platform_add_devices(devices, ARRAY_SIZE(devices));
-#ifdef CONFIG_I2C0_RK29
- i2c_register_board_info(default_i2c0_data.bus_num, board_i2c0_devices,
- ARRAY_SIZE(board_i2c0_devices));
-#endif
-#ifdef CONFIG_I2C1_RK29
- i2c_register_board_info(default_i2c1_data.bus_num, board_i2c1_devices,
- ARRAY_SIZE(board_i2c1_devices));
-#endif
-#ifdef CONFIG_I2C2_RK29
- i2c_register_board_info(default_i2c2_data.bus_num, board_i2c2_devices,
- ARRAY_SIZE(board_i2c2_devices));
-#endif
-#ifdef CONFIG_I2C3_RK29
- i2c_register_board_info(default_i2c3_data.bus_num, board_i2c3_devices,
- ARRAY_SIZE(board_i2c3_devices));
-#endif
-
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- rk29sdk_wifi_bt_gpio_control_init();
- rk29sdk_init_wifi_mem();
-#endif
-
- board_usb_detect_init(RK29_PIN0_PA0);
-#if defined(CONFIG_RK_IRDA) || defined(CONFIG_BU92747GUW_CIR)
- smc0_init(NULL);
- bu92747guw_io_init();
-#endif
-
-}
-
-static void __init machine_rk29_fixup(struct machine_desc *desc, struct tag *tags,
- char **cmdline, struct meminfo *mi)
-{
- mi->nr_banks = 1;
- mi->bank[0].start = RK29_SDRAM_PHYS;
- mi->bank[0].size = LINUX_SIZE;
-#if SDRAM_SIZE > SZ_512M
- mi->nr_banks = 2;
- mi->bank[1].start = RK29_SDRAM_PHYS + SZ_512M;
- mi->bank[1].size = SDRAM_SIZE - SZ_512M;
-#endif
-}
-
-static void __init machine_rk29_mapio(void)
-{
- rk29_map_common_io();
- rk29_setup_early_printk();
- rk29_sram_init();
- rk29_clock_init(periph_pll_default);
- rk29_iomux_init();
- ddr_init(DDR_TYPE, DDR_FREQ);
-}
-
-MACHINE_START(RK29, "RK29board")
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 37))
- /* UART for LL DEBUG */
- .phys_io = RK29_UART1_PHYS & 0xfff00000,
- .io_pg_offst = ((RK29_UART1_BASE) >> 18) & 0xfffc,
-#endif
- .boot_params = RK29_SDRAM_PHYS + 0x88000,
- .fixup = machine_rk29_fixup,
- .map_io = machine_rk29_mapio,
- .init_irq = machine_rk29_init_irq,
- .init_machine = machine_rk29_board_init,
- .timer = &rk29_timer,
-MACHINE_END
+++ /dev/null
-#include <mach/key.h>
-#include <mach/gpio.h>
-#include <mach/board.h>
-
-#define EV_ENCALL KEY_F4
-#define EV_MENU KEY_F1
-
-#define PRESS_LEV_LOW 1
-#define PRESS_LEV_HIGH 0
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .gpio = RK29_PIN6_PA1,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .gpio = RK29_PIN6_PA2,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK29_PIN6_PA7,
- .active_low = PRESS_LEV_HIGH,
- .wakeup = 1,
- },
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = -1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
+++ /dev/null
-/* arch/arm/mach-rk29/board-rk29.c
- *
- * Copyright (C) 2010 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/android_pmem.h>
-#include <linux/usb/android_composite.h>
-#include <linux/i2c/tps65910.h>
-#include <linux/mpu.h>
-#include <linux/mpu3050.h>
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/iomux.h>
-#include <mach/gpio.h>
-#include <mach/irqs.h>
-#include <mach/rk29_iomap.h>
-#include <mach/board.h>
-#include <mach/rk29_nand.h>
-#include <mach/rk29_camera.h> /* ddl@rock-chips.com : camera support */
-#include <media/soc_camera.h> /* ddl@rock-chips.com : camera support */
-#include <mach/vpu_mem.h>
-#include <mach/sram.h>
-#include <mach/rk29_lightsensor.h>
-#include <mach/ddr.h>
-
-#include <linux/regulator/rk29-pwm-regulator.h>
-#include <linux/regulator/machine.h>
-
-#include <linux/mtd/nand.h>
-#include <linux/mtd/partitions.h>
-
-#include <linux/atmel_maxtouch.h>
-#include <linux/leds-att1272.h>
-
-#include "devices.h"
-#include "../../../drivers/input/touchscreen/xpt2046_cbn_ts.h"
-
-/*Below : /sys/class/timed_output */
-#include "../../../drivers/staging/android/timed_gpio.h"
-
-/* Set memory size of pmem */
-#ifdef CONFIG_RK29_MEM_SIZE_M
-#define SDRAM_SIZE (CONFIG_RK29_MEM_SIZE_M * SZ_1M)
-#else
-#define SDRAM_SIZE SZ_512M
-#endif
-#define PMEM_GPU_SIZE SZ_64M
-#define PMEM_UI_SIZE SZ_32M
-#define PMEM_VPU_SIZE SZ_64M
-#define PMEM_CAM_SIZE 0x01300000
-#ifdef CONFIG_VIDEO_RK29_WORK_IPP
-#define MEM_CAMIPP_SIZE SZ_8M
-#else
-#define MEM_CAMIPP_SIZE 0
-#endif
-#define MEM_FB_SIZE (3*SZ_2M)
-#ifdef CONFIG_FB_WORK_IPP
-#ifdef CONFIG_FB_SCALING_OSD_1080P
-#define MEM_FBIPP_SIZE SZ_16M //1920 x 1080 x 2 x 2 //RGB565 = x2;RGB888 = x4
-#else
-#define MEM_FBIPP_SIZE SZ_8M //1920 x 1080 x 2 x 2 //RGB565 = x2;RGB888 = x4
-#endif
-#else
-#define MEM_FBIPP_SIZE 0
-#endif
-#define PMEM_GPU_BASE ((u32)RK29_SDRAM_PHYS + SDRAM_SIZE - PMEM_GPU_SIZE)
-#define PMEM_UI_BASE (PMEM_GPU_BASE - PMEM_UI_SIZE)
-#define PMEM_VPU_BASE (PMEM_UI_BASE - PMEM_VPU_SIZE)
-#define PMEM_CAM_BASE (PMEM_VPU_BASE - PMEM_CAM_SIZE)
-#define MEM_CAMIPP_BASE (PMEM_CAM_BASE - MEM_CAMIPP_SIZE)
-#define MEM_FB_BASE (MEM_CAMIPP_BASE - MEM_FB_SIZE)
-#define MEM_FBIPP_BASE (MEM_FB_BASE - MEM_FBIPP_SIZE)
-#define LINUX_SIZE (MEM_FBIPP_BASE - RK29_SDRAM_PHYS)
-
-#define PREALLOC_WLAN_SEC_NUM 4
-#define PREALLOC_WLAN_BUF_NUM 160
-#define PREALLOC_WLAN_SECTION_HEADER 24
-
-#define WLAN_SECTION_SIZE_0 (PREALLOC_WLAN_BUF_NUM * 128)
-#define WLAN_SECTION_SIZE_1 (PREALLOC_WLAN_BUF_NUM * 128)
-#define WLAN_SECTION_SIZE_2 (PREALLOC_WLAN_BUF_NUM * 512)
-#define WLAN_SECTION_SIZE_3 (PREALLOC_WLAN_BUF_NUM * 1024)
-
-#define WLAN_SKB_BUF_NUM 16
-
-static struct sk_buff *wlan_static_skb[WLAN_SKB_BUF_NUM];
-
-struct wifi_mem_prealloc {
- void *mem_ptr;
- unsigned long size;
-};
-
-extern struct sys_timer rk29_timer;
-
-static int rk29_nand_io_init(void)
-{
- return 0;
-}
-
-struct rk29_nand_platform_data rk29_nand_data = {
- .width = 1, /* data bus width in bytes */
- .hw_ecc = 1, /* hw ecc 0: soft ecc */
- .num_flash = 1,
- .io_init = rk29_nand_io_init,
-};
-
-/*****************************************************************************************
-* touch screen devices
-* author: cf@rock-chips.com
-*****************************************************************************************/
-#define TOUCH_SCREEN_STANDBY_PIN INVALID_GPIO
-#define TOUCH_SCREEN_STANDBY_VALUE GPIO_HIGH
-#define TOUCH_SCREEN_DISPLAY_PIN INVALID_GPIO
-#define TOUCH_SCREEN_DISPLAY_VALUE GPIO_HIGH
-
-#ifdef CONFIG_FB_RK29
-/*****************************************************************************************
- * lcd devices
- * author: zyw@rock-chips.com
- *****************************************************************************************/
-//#ifdef CONFIG_LCD_TD043MGEA1
-#define LCD_TXD_PIN INVALID_GPIO
-#define LCD_CLK_PIN INVALID_GPIO
-#define LCD_CS_PIN INVALID_GPIO
-/*****************************************************************************************
-* frame buffe devices
-* author: zyw@rock-chips.com
-*****************************************************************************************/
-#define FB_ID 0
-#define FB_DISPLAY_ON_PIN INVALID_GPIO// RK29_PIN6_PD0
-#define FB_LCD_STANDBY_PIN RK29_PIN6_PD1
-#define FB_LCD_CABC_EN_PIN RK29_PIN6_PD2
-#define FB_MCU_FMK_PIN INVALID_GPIO
-
-#define FB_DISPLAY_ON_VALUE GPIO_HIGH
-#define FB_LCD_STANDBY_VALUE GPIO_HIGH
-
-//#endif
-static int rk29_lcd_io_init(void)
-{
- int ret = 0;
- return ret;
-}
-
-static int rk29_lcd_io_deinit(void)
-{
- int ret = 0;
- return ret;
-}
-
-static struct rk29lcd_info rk29_lcd_info = {
- .txd_pin = LCD_TXD_PIN,
- .clk_pin = LCD_CLK_PIN,
- .cs_pin = LCD_CS_PIN,
- .io_init = rk29_lcd_io_init,
- .io_deinit = rk29_lcd_io_deinit,
-};
-
-int rk29_fb_io_enable(void)
-{
- if(FB_DISPLAY_ON_PIN != INVALID_GPIO)
- {
- gpio_direction_output(FB_DISPLAY_ON_PIN, 0);
- gpio_set_value(FB_DISPLAY_ON_PIN, FB_DISPLAY_ON_VALUE);
- }
- if(FB_LCD_STANDBY_PIN != INVALID_GPIO)
- {
- gpio_direction_output(FB_LCD_STANDBY_PIN, 0);
- gpio_set_value(FB_LCD_STANDBY_PIN, FB_LCD_STANDBY_VALUE);
- }
-}
-
-int rk29_fb_io_disable(void)
-{
- if(FB_DISPLAY_ON_PIN != INVALID_GPIO)
- {
- gpio_direction_output(FB_DISPLAY_ON_PIN, 0);
- gpio_set_value(FB_DISPLAY_ON_PIN, !FB_DISPLAY_ON_VALUE);
- }
- if(FB_LCD_STANDBY_PIN != INVALID_GPIO)
- {
- gpio_direction_output(FB_LCD_STANDBY_PIN, 0);
- gpio_set_value(FB_LCD_STANDBY_PIN, !FB_LCD_STANDBY_VALUE);
- }
-}
-
-static int rk29_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
- if(fb_setting->mcu_fmk_en && (FB_MCU_FMK_PIN != INVALID_GPIO))
- {
- ret = gpio_request(FB_MCU_FMK_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(FB_MCU_FMK_PIN);
- printk(">>>>>> FB_MCU_FMK_PIN gpio_request err \n ");
- }
- gpio_direction_input(FB_MCU_FMK_PIN);
- }
- if(fb_setting->disp_on_en)
- {
- if(FB_DISPLAY_ON_PIN != INVALID_GPIO)
- {
- ret = gpio_request(FB_DISPLAY_ON_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(FB_DISPLAY_ON_PIN);
- printk(">>>>>> FB_DISPLAY_ON_PIN gpio_request err \n ");
- }
- }
- else
- {
- ret = gpio_request(TOUCH_SCREEN_DISPLAY_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(TOUCH_SCREEN_DISPLAY_PIN);
- printk(">>>>>> TOUCH_SCREEN_DISPLAY_PIN gpio_request err \n ");
- }
- gpio_direction_output(TOUCH_SCREEN_DISPLAY_PIN, 0);
- gpio_set_value(TOUCH_SCREEN_DISPLAY_PIN, TOUCH_SCREEN_DISPLAY_VALUE);
- }
- }
-
- if(fb_setting->disp_on_en)
- {
- if(FB_LCD_STANDBY_PIN != INVALID_GPIO)
- {
- ret = gpio_request(FB_LCD_STANDBY_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(FB_LCD_STANDBY_PIN);
- printk(">>>>>> FB_LCD_STANDBY_PIN gpio_request err \n ");
- }
- }
- else
- {
- ret = gpio_request(TOUCH_SCREEN_STANDBY_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(TOUCH_SCREEN_STANDBY_PIN);
- printk(">>>>>> TOUCH_SCREEN_STANDBY_PIN gpio_request err \n ");
- }
- gpio_direction_output(TOUCH_SCREEN_STANDBY_PIN, 0);
- gpio_set_value(TOUCH_SCREEN_STANDBY_PIN, TOUCH_SCREEN_STANDBY_VALUE);
- }
- }
-
- if(FB_LCD_CABC_EN_PIN != INVALID_GPIO)
- {
- ret = gpio_request(FB_LCD_CABC_EN_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(FB_LCD_CABC_EN_PIN);
- printk(">>>>>> FB_LCD_CABC_EN_PIN gpio_request err \n ");
- }
- gpio_direction_output(FB_LCD_CABC_EN_PIN, 0);
- gpio_set_value(FB_LCD_CABC_EN_PIN, GPIO_LOW);
- }
-
- rk29_fb_io_enable(); //enable it
-
- return ret;
-}
-
-
-static struct rk29fb_info rk29_fb_info = {
- .fb_id = FB_ID,
- .mcu_fmk_pin = FB_MCU_FMK_PIN,
- .lcd_info = &rk29_lcd_info,
- .io_init = rk29_fb_io_init,
- .io_enable = rk29_fb_io_enable,
- .io_disable = rk29_fb_io_disable,
-};
-
-/* rk29 fb resource */
-static struct resource rk29_fb_resource[] = {
- [0] = {
- .name = "lcdc reg",
- .start = RK29_LCDC_PHYS,
- .end = RK29_LCDC_PHYS + RK29_LCDC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc irq",
- .start = IRQ_LCDC,
- .end = IRQ_LCDC,
- .flags = IORESOURCE_IRQ,
- },
- [2] = {
- .name = "win1 buf",
- .start = MEM_FB_BASE,
- .end = MEM_FB_BASE + MEM_FB_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- #ifdef CONFIG_FB_WORK_IPP
- [3] = {
- .name = "win1 ipp buf",
- .start = MEM_FBIPP_BASE,
- .end = MEM_FBIPP_BASE + MEM_FBIPP_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- #endif
-};
-
-/*platform_device*/
-struct platform_device rk29_device_fb = {
- .name = "rk29-fb",
- .id = 4,
- .num_resources = ARRAY_SIZE(rk29_fb_resource),
- .resource = rk29_fb_resource,
- .dev = {
- .platform_data = &rk29_fb_info,
- }
-};
-
-struct platform_device rk29_device_dma_cpy = {
- .name = "dma_memcpy",
- .id = 4,
-
-};
-
-#endif
-
-static struct android_pmem_platform_data android_pmem_pdata = {
- .name = "pmem",
- .start = PMEM_UI_BASE,
- .size = PMEM_UI_SIZE,
- .no_allocator = 0,
- .cached = 1,
-};
-
-static struct platform_device android_pmem_device = {
- .name = "android_pmem",
- .id = 0,
- .dev = {
- .platform_data = &android_pmem_pdata,
- },
-};
-
-
-static struct android_pmem_platform_data android_pmem_cam_pdata = {
- .name = "pmem_cam",
- .start = PMEM_CAM_BASE,
- .size = PMEM_CAM_SIZE,
- .no_allocator = 1,
- .cached = 1,
-};
-
-static struct platform_device android_pmem_cam_device = {
- .name = "android_pmem",
- .id = 1,
- .dev = {
- .platform_data = &android_pmem_cam_pdata,
- },
-};
-
-
-static struct vpu_mem_platform_data vpu_mem_pdata = {
- .name = "vpu_mem",
- .start = PMEM_VPU_BASE,
- .size = PMEM_VPU_SIZE,
- .cached = 1,
-};
-
-static struct platform_device rk29_vpu_mem_device = {
- .name = "vpu_mem",
- .id = 2,
- .dev = {
- .platform_data = &vpu_mem_pdata,
- },
-};
-
-static struct platform_device rk29_v4l2_output_devce = {
- .name = "rk29_vout",
-};
-
-/*HANNSTAR_P1003 touch*/
-#if defined (CONFIG_HANNSTAR_P1003)
-#define TOUCH_RESET_PIN RK29_PIN6_PC3
-#define TOUCH_INT_PIN RK29_PIN0_PA2
-
-int p1003_init_platform_hw(void)
-{
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_pull_updown(TOUCH_INT_PIN, 1);
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
-
- return 0;
-}
-
-
-struct p1003_platform_data p1003_info = {
- .model= 1003,
- .init_platform_hw= p1003_init_platform_hw,
-
-};
-#endif
-#if defined (CONFIG_EETI_EGALAX)
-#define TOUCH_RESET_PIN RK29_PIN6_PC3
-#define TOUCH_INT_PIN RK29_PIN0_PA2
-
-static int EETI_EGALAX_init_platform_hw(void)
-{
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_pull_updown(TOUCH_INT_PIN, 1);
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
-
- return 0;
-}
-
-
-static struct eeti_egalax_platform_data eeti_egalax_info = {
- .model= 1003,
- .init_platform_hw= EETI_EGALAX_init_platform_hw,
-
-};
-#endif
-
-/*Atmel mxt224 touch*/
-#if defined (CONFIG_ATMEL_MXT224)
-#define TOUCH_RESET_PIN RK29_PIN6_PC3
-#define TOUCH_INT_PIN RK29_PIN0_PA2
-
-int mxt224_init_platform_hw(void)
-{
- if(gpio_request(TOUCH_RESET_PIN, "Touch_reset") != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("mxt224_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN, "Touch_int") != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("mxt224_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_pull_updown(TOUCH_INT_PIN, 1);
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- msleep(10);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- msleep(500);
- return 0;
-}
-
-u8 mxt_read_chg(void)
-{
- return 1;
-}
-
-struct mxt_platform_data mxt224_info = {
- .numtouch = 2,
- .init_platform_hw= mxt224_init_platform_hw,
- .read_chg = mxt_read_chg,
- .max_x = 4095,
- .max_y = 4095,
-};
-#endif
-
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN RK29_PIN0_PA3
-
-static int mma8452_init_platform_hw(void)
-{
-
- if(gpio_request(MMA8452_INT_PIN,NULL) != 0){
- gpio_free(MMA8452_INT_PIN);
- printk("mma8452_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_pull_updown(MMA8452_INT_PIN, 1);
- return 0;
-}
-
-
-static struct gsensor_platform_data mma8452_info = {
- .model= 8452,
- .swap_xy = 0,
- .init_platform_hw= mma8452_init_platform_hw,
-
-};
-#endif
-/*mpu3050*/
-#if defined (CONFIG_MPU_SENSORS_MPU3050)
-static struct mpu_platform_data mpu3050_data = {
- .int_config = 0x10,
- .orientation = { 1, 0, 0,0, 1, 0, 0, 0, 1 },
-};
-#endif
-
-/* accel */
-#if defined (CONFIG_MPU_SENSORS_KXTF9)
-static struct ext_slave_platform_data inv_mpu_kxtf9_data = {
- .bus = EXT_SLAVE_BUS_SECONDARY,
- .adapt_num = 0,
- .orientation = {1, 0, 0, 0, 1, 0, 0, 0, 1},
-};
-#endif
-
-/* compass */
-#if defined (CONFIG_MPU_SENSORS_AK8975)
-static struct ext_slave_platform_data inv_mpu_ak8975_data = {
- .bus = EXT_SLAVE_BUS_PRIMARY,
- .adapt_num = 0,
- .orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
-};
-#endif
-
-#if defined (CONFIG_BATTERY_BQ27510)
-
-#define DC_CHECK_PIN RK29_PIN4_PA1
-#define LI_LION_BAT_NUM 2
-static int bq27510_init_dc_check_pin(void)
-{
- if(gpio_request(DC_CHECK_PIN,"dc_check") != 0)
- {
- gpio_free(DC_CHECK_PIN);
- printk("bq27510 init dc check pin request error\n");
- return -EIO;
- }
- gpio_direction_input(DC_CHECK_PIN);
- return 0;
-}
-struct bq27510_platform_data bq27510_info =
-{
- .init_dc_check_pin = bq27510_init_dc_check_pin,
- .dc_check_pin = DC_CHECK_PIN,
- .bat_num = LI_LION_BAT_NUM,
-};
-
-#endif
-
-
-/*****************************************************************************************
-* TI TPS65910 voltage regulator devices
-******************************************************************************************/
-#if defined (CONFIG_TPS65910_CORE)
-/* VDD1 */
-static struct regulator_consumer_supply rk29_vdd1_supplies[] = {
- {
- .supply = "vcore", // set name vcore for all platform
- },
-};
-
-/* VDD1 DCDC */
-static struct regulator_init_data rk29_regulator_vdd1 = {
- .constraints = {
- .min_uV = 950000,
- .max_uV = 1400000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
- .always_on = true,
- .apply_uV = true,
- },
- .num_consumer_supplies = ARRAY_SIZE(rk29_vdd1_supplies),
- .consumer_supplies = rk29_vdd1_supplies,
-};
-
-/* VDD2 */
-static struct regulator_consumer_supply rk29_vdd2_supplies[] = {
- {
- .supply = "vdd2",
- },
-};
-
-/* VDD2 DCDC */
-static struct regulator_init_data rk29_regulator_vdd2 = {
- .constraints = {
- .min_uV = 1200000,
- .max_uV = 1200000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- .always_on = true,
- .apply_uV = true,
- },
- .num_consumer_supplies = ARRAY_SIZE(rk29_vdd2_supplies),
- .consumer_supplies = rk29_vdd2_supplies,
-};
-
-/* VIO */
-static struct regulator_consumer_supply rk29_vio_supplies[] = {
- {
- .supply = "vio",
- },
-};
-
-/* VIO LDO */
-static struct regulator_init_data rk29_regulator_vio = {
- .constraints = {
- .min_uV = 3300000,
- .max_uV = 3300000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- .always_on = true,
- .apply_uV = true,
- },
- .num_consumer_supplies = ARRAY_SIZE(rk29_vio_supplies),
- .consumer_supplies = rk29_vio_supplies,
-};
-
-/* VAUX1 */
-static struct regulator_consumer_supply rk29_vaux1_supplies[] = {
- {
- .supply = "vaux1",
- },
-};
-
-/* VAUX1 LDO */
-static struct regulator_init_data rk29_regulator_vaux1 = {
- .constraints = {
- .min_uV = 2800000,
- .max_uV = 2800000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- .apply_uV = true,
- },
- .num_consumer_supplies = ARRAY_SIZE(rk29_vaux1_supplies),
- .consumer_supplies = rk29_vaux1_supplies,
-};
-
-/* VAUX2 */
-static struct regulator_consumer_supply rk29_vaux2_supplies[] = {
- {
- .supply = "vaux2",
- },
-};
-
-/* VAUX2 LDO */
-static struct regulator_init_data rk29_regulator_vaux2 = {
- .constraints = {
- .min_uV = 2900000,
- .max_uV = 2900000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- .apply_uV = true,
- },
- .num_consumer_supplies = ARRAY_SIZE(rk29_vaux2_supplies),
- .consumer_supplies = rk29_vaux2_supplies,
-};
-
-/* VDAC */
-static struct regulator_consumer_supply rk29_vdac_supplies[] = {
- {
- .supply = "vdac",
- },
-};
-
-/* VDAC LDO */
-static struct regulator_init_data rk29_regulator_vdac = {
- .constraints = {
- .min_uV = 1800000,
- .max_uV = 1800000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- .apply_uV = true,
- },
- .num_consumer_supplies = ARRAY_SIZE(rk29_vdac_supplies),
- .consumer_supplies = rk29_vdac_supplies,
-};
-
-/* VAUX33 */
-static struct regulator_consumer_supply rk29_vaux33_supplies[] = {
- {
- .supply = "vaux33",
- },
-};
-
-/* VAUX33 LDO */
-static struct regulator_init_data rk29_regulator_vaux33 = {
- .constraints = {
- .min_uV = 3300000,
- .max_uV = 3300000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- .apply_uV = true,
- },
- .num_consumer_supplies = ARRAY_SIZE(rk29_vaux33_supplies),
- .consumer_supplies = rk29_vaux33_supplies,
-};
-
-/* VMMC */
-static struct regulator_consumer_supply rk29_vmmc_supplies[] = {
- {
- .supply = "vmmc",
- },
-};
-
-/* VMMC LDO */
-static struct regulator_init_data rk29_regulator_vmmc = {
- .constraints = {
- .min_uV = 3000000,
- .max_uV = 3000000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- .apply_uV = true,
- },
- .num_consumer_supplies = ARRAY_SIZE(rk29_vmmc_supplies),
- .consumer_supplies = rk29_vmmc_supplies,
-};
-
-/* VPLL */
-static struct regulator_consumer_supply rk29_vpll_supplies[] = {
- {
- .supply = "vpll",
- },
-};
-
-/* VPLL LDO */
-static struct regulator_init_data rk29_regulator_vpll = {
- .constraints = {
- .min_uV = 2500000,
- .max_uV = 2500000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- .always_on = true,
- .apply_uV = true,
- },
- .num_consumer_supplies = ARRAY_SIZE(rk29_vpll_supplies),
- .consumer_supplies = rk29_vpll_supplies,
-};
-
-/* VDIG1 */
-static struct regulator_consumer_supply rk29_vdig1_supplies[] = {
- {
- .supply = "vdig1",
- },
-};
-
-/* VDIG1 LDO */
-static struct regulator_init_data rk29_regulator_vdig1 = {
- .constraints = {
- .min_uV = 2700000,
- .max_uV = 2700000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- .apply_uV = true,
- },
- .num_consumer_supplies = ARRAY_SIZE(rk29_vdig1_supplies),
- .consumer_supplies = rk29_vdig1_supplies,
-};
-
-/* VDIG2 */
-static struct regulator_consumer_supply rk29_vdig2_supplies[] = {
- {
- .supply = "vdig2",
- },
-};
-
-/* VDIG2 LDO */
-static struct regulator_init_data rk29_regulator_vdig2 = {
- .constraints = {
- .min_uV = 1200000,
- .max_uV = 1200000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- .always_on = true,
- .apply_uV = true,
- },
- .num_consumer_supplies = ARRAY_SIZE(rk29_vdig2_supplies),
- .consumer_supplies = rk29_vdig2_supplies,
-};
-
-static int rk29_tps65910_config(struct tps65910_platform_data *pdata)
-{
- u8 val = 0;
- int i = 0;
- int err = -1;
-
-
- /* Configure TPS65910 for rk29 board needs */
- printk("rk29_tps65910_config: tps65910 init config.\n");
-
- err = tps65910_i2c_read_u8(TPS65910_I2C_ID0, &val, TPS65910_REG_DEVCTRL2);
- if (err) {
- printk(KERN_ERR "Unable to read TPS65910_REG_DEVCTRL2 reg\n");
- return -EIO;
- }
- /* Set sleep state active high and allow device turn-off after PWRON long press */
- val |= (TPS65910_DEV2_SLEEPSIG_POL | TPS65910_DEV2_PWON_LP_OFF);
-
- err = tps65910_i2c_write_u8(TPS65910_I2C_ID0, val,
- TPS65910_REG_DEVCTRL2);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_REG_DEVCTRL2 reg\n");
- return -EIO;
- }
-
- /* Set the maxinum load current */
- /* VDD1 */
- err = tps65910_i2c_read_u8(TPS65910_I2C_ID0, &val, TPS65910_REG_VDD1);
- if (err) {
- printk(KERN_ERR "Unable to read TPS65910_REG_VDD1 reg\n");
- return -EIO;
- }
-
- val |= (1<<5);
- err = tps65910_i2c_write_u8(TPS65910_I2C_ID0, val, TPS65910_REG_VDD1);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_REG_VDD1 reg\n");
- return -EIO;
- }
-
- /* VDD2 */
- err = tps65910_i2c_read_u8(TPS65910_I2C_ID0, &val, TPS65910_REG_VDD2);
- if (err) {
- printk(KERN_ERR "Unable to read TPS65910_REG_VDD2 reg\n");
- return -EIO;
- }
-
- val |= (1<<5);
- err = tps65910_i2c_write_u8(TPS65910_I2C_ID0, val, TPS65910_REG_VDD2);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_REG_VDD2 reg\n");
- return -EIO;
- }
-
- /* VIO */
- err = tps65910_i2c_read_u8(TPS65910_I2C_ID0, &val, TPS65910_REG_VIO);
- if (err) {
- printk(KERN_ERR "Unable to read TPS65910_REG_VIO reg\n");
- return -EIO;
- }
-
- val |= (1<<6);
- err = tps65910_i2c_write_u8(TPS65910_I2C_ID0, val, TPS65910_REG_VIO);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_REG_VIO reg\n");
- return -EIO;
- }
-
- /* Mask ALL interrupts */
- err = tps65910_i2c_write_u8(TPS65910_I2C_ID0, 0xFF,
- TPS65910_REG_INT_MSK);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_REG_INT_MSK reg\n");
- return -EIO;
- }
- err = tps65910_i2c_write_u8(TPS65910_I2C_ID0, 0x03,
- TPS65910_REG_INT_MSK2);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_REG_INT_MSK2 reg\n");
- return -EIO;
- }
-
- /* Set RTC Power, disable Smart Reflex in DEVCTRL_REG */
- val = 0;
- val |= (TPS65910_SR_CTL_I2C_SEL);
- err = tps65910_i2c_write_u8(TPS65910_I2C_ID0, val,
- TPS65910_REG_DEVCTRL);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_REG_DEVCTRL reg\n");
- return -EIO;
- }
-
- printk(KERN_INFO "TPS65910 Set default voltage.\n");
-#if 1
- /* VDIG1 Set the default voltage from 1800mV to 2700 mV for camera io */
- val = 0x01;
- val |= (0x03 << 2);
- err = tps65910_i2c_write_u8(TPS65910_I2C_ID0, val, TPS65910_REG_VDIG1);
- if (err) {
- printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
- \n", TPS65910_REG_VDIG1);
- return -EIO;
- }
-#endif
-
-#if 0
- /* VDD1 whitch suplies for core Set the default voltage: 1150 mV(47)*/
- val = 47;
- err = tps65910_i2c_write_u8(TPS65910_I2C_ID0, val, TPS65910_REG_VDD1_OP);
- if (err) {
- printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
- \n", TPS65910_REG_VDD1_OP);
- return -EIO;
- }
-#endif
-
-#if 1
- /* VDD2 whitch suplies for ddr3 Set the default voltage: 1087 * 1.25mV(41)*/
- val = 42;
- err = tps65910_i2c_write_u8(TPS65910_I2C_ID0, val, TPS65910_REG_VDD2_OP);
- if (err) {
- printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
- \n", TPS65910_REG_VDD2_OP);
- return -EIO;
- }
-#endif
-
- /* initilize all ISR work as NULL, specific driver will
- * assign function(s) later.
- */
- for (i = 0; i < TPS65910_MAX_IRQS; i++)
- pdata->handlers[i] = NULL;
-
- return 0;
-}
-
-struct tps65910_platform_data rk29_tps65910_data = {
- .irq_num = (unsigned)TPS65910_HOST_IRQ,
- .gpio = NULL,
- .vio = &rk29_regulator_vio,
- .vdd1 = &rk29_regulator_vdd1,
- .vdd2 = &rk29_regulator_vdd2,
- .vdd3 = NULL,
- .vdig1 = &rk29_regulator_vdig1,
- .vdig2 = &rk29_regulator_vdig2,
- .vaux33 = &rk29_regulator_vaux33,
- .vmmc = &rk29_regulator_vmmc,
- .vaux1 = &rk29_regulator_vaux1,
- .vaux2 = &rk29_regulator_vaux2,
- .vdac = &rk29_regulator_vdac,
- .vpll = &rk29_regulator_vpll,
- .board_tps65910_config = rk29_tps65910_config,
-};
-#endif /* CONFIG_TPS65910_CORE */
-
-#if defined (CONFIG_LEDS_ATT1272)
-struct att1272_led_platform_data att1272_data = {
- .name = "att1272",
- .en_gpio = RK29_PIN1_PB0,
- .flen_gpio = RK29_PIN1_PB1,
-};
-#endif
-
-/*****************************************************************************************
- * i2c devices
- * author: kfx@rock-chips.com
-*****************************************************************************************/
-static int rk29_i2c0_io_init(void)
-{
- rk29_mux_api_set(GPIO2B7_I2C0SCL_NAME, GPIO2L_I2C0_SCL);
- rk29_mux_api_set(GPIO2B6_I2C0SDA_NAME, GPIO2L_I2C0_SDA);
- return 0;
-}
-
-static int rk29_i2c1_io_init(void)
-{
- rk29_mux_api_set(GPIO1A7_I2C1SCL_NAME, GPIO1L_I2C1_SCL);
- rk29_mux_api_set(GPIO1A6_I2C1SDA_NAME, GPIO1L_I2C1_SDA);
- return 0;
-}
-static int rk29_i2c2_io_init(void)
-{
- rk29_mux_api_set(GPIO5D4_I2C2SCL_NAME, GPIO5H_I2C2_SCL);
- rk29_mux_api_set(GPIO5D3_I2C2SDA_NAME, GPIO5H_I2C2_SDA);
- return 0;
-}
-
-static int rk29_i2c3_io_init(void)
-{
- rk29_mux_api_set(GPIO2B5_UART3RTSN_I2C3SCL_NAME, GPIO2L_I2C3_SCL);
- rk29_mux_api_set(GPIO2B4_UART3CTSN_I2C3SDA_NAME, GPIO2L_I2C3_SDA);
- return 0;
-}
-
-struct rk29_i2c_platform_data default_i2c0_data = {
- .bus_num = 0,
- .flags = 0,
- .slave_addr = 0xff,
- .scl_rate = 400*1000,
- .mode = I2C_MODE_IRQ,
- .io_init = rk29_i2c0_io_init,
-};
-
-struct rk29_i2c_platform_data default_i2c1_data = {
- .bus_num = 1,
- .flags = 0,
- .slave_addr = 0xff,
- .scl_rate = 400*1000,
- .mode = I2C_MODE_IRQ,
- .io_init = rk29_i2c1_io_init,
-};
-
-struct rk29_i2c_platform_data default_i2c2_data = {
- .bus_num = 2,
- .flags = 0,
- .slave_addr = 0xff,
- .scl_rate = 400*1000,
- .mode = I2C_MODE_IRQ,
- .io_init = rk29_i2c2_io_init,
-};
-
-struct rk29_i2c_platform_data default_i2c3_data = {
- .bus_num = 3,
- .flags = 0,
- .slave_addr = 0xff,
- .scl_rate = 400*1000,
- .mode = I2C_MODE_POLL,
- .io_init = rk29_i2c3_io_init,
-};
-
-#ifdef CONFIG_I2C0_RK29
-static struct i2c_board_info __initdata board_i2c0_devices[] = {
-#if defined (CONFIG_RK1000_CONTROL)
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_WM8900)
- {
- .type = "wm8900",
- .addr = 0x1A,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_BATTERY_STC3100)
- {
- .type = "stc3100",
- .addr = 0x70,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_RTC_HYM8563)
- {
- .type = "rtc_hym8563",
- .addr = 0x51,
- .flags = 0,
- .irq = RK29_PIN0_PA1,
- },
-#endif
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1c,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_SENSORS_AK8973)
- {
- .type = "ak8973",
- .addr = 0x1d,
- .flags = 0,
- .irq = RK29_PIN0_PA4,
- },
-#endif
-#if defined (CONFIG_MPU_SENSORS_MPU3050)
- {
- .type = "mpu3050",
- .addr = 0x68,
- .flags = 0,
- .irq = RK29_PIN4_PC4,
- .platform_data = &mpu3050_data,
- },
-#endif
-#if defined (CONFIG_MPU_SENSORS_KXTF9)
- {
- .type = "kxtf9",
- .addr = 0x0f,
- .flags = 0,
- //.irq = RK29_PIN6_PC4,
- .platform_data = &inv_mpu_kxtf9_data,
- },
-#endif
-#if defined (CONFIG_MPU_SENSORS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- //.irq = RK29_PIN6_PC5,
- .platform_data = &inv_mpu_ak8975_data,
- },
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C1_RK29
-static struct i2c_board_info __initdata board_i2c1_devices[] = {
-#if defined (CONFIG_RK1000_CONTROL1)
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_ANX7150) || defined (CONFIG_ANX7150_NEW)
- {
- .type = "anx7150",
- .addr = 0x39, //0x39, 0x3d
- .flags = 0,
- .irq = RK29_PIN1_PD7,
- },
-#endif
-#if defined (CONFIG_ATMEL_MXT224)
- {
- .type = "maXTouch",
- .addr = 0x4B,
- .flags = 0,
- .irq = RK29_PIN0_PA2,
- .platform_data = &mxt224_info,
- },
-#endif
-
-#if defined (CONFIG_LEDS_ATT1272)
- {
- .type = "att1272",
- .addr = 0x37,
- .flags = 0,
- .irq = 0,
- .platform_data = &att1272_data,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C2_RK29
-static struct i2c_board_info __initdata board_i2c2_devices[] = {
-#if defined (CONFIG_HANNSTAR_P1003)
- {
- .type = "p1003_touch",
- .addr = 0x04,
- .flags = 0,
- .irq = RK29_PIN0_PA2,
- .platform_data = &p1003_info,
- },
-#endif
-#if defined (CONFIG_EETI_EGALAX)
- {
- .type = "egalax_i2c",
- .addr = 0x04,
- .flags = 0,
- .irq = RK29_PIN0_PA2,
- .platform_data = &eeti_egalax_info,
- },
-#endif
-#if defined (CONFIG_TPS65910_CORE)
- {
- .type = "tps659102",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &rk29_tps65910_data,
- },
-#endif
-#if defined (CONFIG_BATTERY_BQ27510)
-{
- .type = "bq27510",
- .addr = 0x55,
- .flags = 0,
- .platform_data = &bq27510_info,
-},
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK29
-static struct i2c_board_info __initdata board_i2c3_devices[] = {
-};
-#endif
-
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Begin ------------------------*/
-#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_MT9P111 /* back camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_0 0x78
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 1
-#define CONFIG_SENSOR_POWER_PIN_0 RK29_PIN5_PD7
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 RK29_PIN1_PB2
-#define CONFIG_SENSOR_FALSH_PIN_0 RK29_PIN1_PB1
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_H
-
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_S5K6AA /* front camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_1 0x78
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 1
-#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_1 RK29_PIN1_PB3
-#define CONFIG_SENSOR_POWERDN_PIN_1 RK29_PIN6_PB7
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_L
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-/*---------------- Camera Sensor Configuration End------------------------*/
-
-#define _CONS(a,b) a##b
-#define CONS(a,b) _CONS(a,b)
-
-#define __STR(x) #x
-#define _STR(x) __STR(x)
-#define STR(x) _STR(x)
-
-#define SENSOR_NAME_0 STR(CONFIG_SENSOR_0) /* back camera sensor */
-#define SENSOR_NAME_1 STR(CONFIG_SENSOR_1) /* front camera sensor */
-#define SENSOR_DEVICE_NAME_0 STR(CONS(CONFIG_SENSOR_0, _back))
-#define SENSOR_DEVICE_NAME_1 STR(CONS(CONFIG_SENSOR_1, _front))
-
-static int rk29_sensor_io_init(void);
-static int rk29_sensor_io_deinit(int sensor);
-static int rk29_sensor_ioctrl(struct device *dev,enum rk29camera_ioctrl_cmd cmd,int on);
-
-static struct rk29camera_platform_data rk29_camera_platform_data = {
- .io_init = rk29_sensor_io_init,
- .io_deinit = rk29_sensor_io_deinit,
- .sensor_ioctrl = rk29_sensor_ioctrl,
- .gpio_res = {
- {
- .gpio_reset = CONFIG_SENSOR_RESET_PIN_0,
- .gpio_power = CONFIG_SENSOR_POWER_PIN_0,
- .gpio_powerdown = CONFIG_SENSOR_POWERDN_PIN_0,
- .gpio_flash = CONFIG_SENSOR_FALSH_PIN_0,
- .gpio_flag = (CONFIG_SENSOR_POWERACTIVE_LEVEL_0|CONFIG_SENSOR_RESETACTIVE_LEVEL_0|CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0|CONFIG_SENSOR_FLASHACTIVE_LEVEL_0),
- .gpio_init = 0,
- .dev_name = SENSOR_DEVICE_NAME_0,
- }, {
- .gpio_reset = CONFIG_SENSOR_RESET_PIN_1,
- .gpio_power = CONFIG_SENSOR_POWER_PIN_1,
- .gpio_powerdown = CONFIG_SENSOR_POWERDN_PIN_1,
- .gpio_flash = CONFIG_SENSOR_FALSH_PIN_1,
- .gpio_flag = (CONFIG_SENSOR_POWERACTIVE_LEVEL_1|CONFIG_SENSOR_RESETACTIVE_LEVEL_1|CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1|CONFIG_SENSOR_FLASHACTIVE_LEVEL_1),
- .gpio_init = 0,
- .dev_name = SENSOR_DEVICE_NAME_1,
- }
- },
- #ifdef CONFIG_VIDEO_RK29_WORK_IPP
- .meminfo = {
- .name = "camera_ipp_mem",
- .start = MEM_CAMIPP_BASE,
- .size = MEM_CAMIPP_SIZE,
- }
- #endif
-};
-
-static int rk29_sensor_io_init(void)
-{
- int ret = 0, i;
- unsigned int camera_reset = INVALID_GPIO, camera_power = INVALID_GPIO;
- unsigned int camera_powerdown = INVALID_GPIO, camera_flash = INVALID_GPIO;
- unsigned int camera_ioflag;
-
- for (i=0; i<2; i++) {
- camera_reset = rk29_camera_platform_data.gpio_res[i].gpio_reset;
- camera_power = rk29_camera_platform_data.gpio_res[i].gpio_power;
- camera_powerdown = rk29_camera_platform_data.gpio_res[i].gpio_powerdown;
- camera_flash = rk29_camera_platform_data.gpio_res[i].gpio_flash;
- camera_ioflag = rk29_camera_platform_data.gpio_res[i].gpio_flag;
- rk29_camera_platform_data.gpio_res[i].gpio_init = 0;
-
- if (camera_power != INVALID_GPIO) {
- ret = gpio_request(camera_power, "camera power");
- if (ret)
- goto sensor_io_int_loop_end;
- rk29_camera_platform_data.gpio_res[i].gpio_init |= RK29_CAM_POWERACTIVE_MASK;
- gpio_set_value(camera_reset, (((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
- gpio_direction_output(camera_power, (((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
-
- //printk("\n%s....power pin(%d) init success(0x%x) \n",__FUNCTION__,camera_power,(((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
-
- }
-
- if (camera_reset != INVALID_GPIO) {
- ret = gpio_request(camera_reset, "camera reset");
- if (ret)
- goto sensor_io_int_loop_end;
- rk29_camera_platform_data.gpio_res[i].gpio_init |= RK29_CAM_RESETACTIVE_MASK;
- gpio_set_value(camera_reset, ((camera_ioflag&RK29_CAM_RESETACTIVE_MASK)>>RK29_CAM_RESETACTIVE_BITPOS));
- gpio_direction_output(camera_reset, ((camera_ioflag&RK29_CAM_RESETACTIVE_MASK)>>RK29_CAM_RESETACTIVE_BITPOS));
-
- //printk("\n%s....reset pin(%d) init success(0x%x)\n",__FUNCTION__,camera_reset,((camera_ioflag&RK29_CAM_RESETACTIVE_MASK)>>RK29_CAM_RESETACTIVE_BITPOS));
-
- }
-
- if (camera_powerdown != INVALID_GPIO) {
- ret = gpio_request(camera_powerdown, "camera powerdown");
- if (ret)
- goto sensor_io_int_loop_end;
- rk29_camera_platform_data.gpio_res[i].gpio_init |= RK29_CAM_POWERDNACTIVE_MASK;
- gpio_set_value(camera_powerdown, ((camera_ioflag&RK29_CAM_POWERDNACTIVE_MASK)>>RK29_CAM_POWERDNACTIVE_BITPOS));
- gpio_direction_output(camera_powerdown, ((camera_ioflag&RK29_CAM_POWERDNACTIVE_MASK)>>RK29_CAM_POWERDNACTIVE_BITPOS));
-
- //printk("\n%s....powerdown pin(%d) init success(0x%x) \n",__FUNCTION__,camera_powerdown,((camera_ioflag&RK29_CAM_POWERDNACTIVE_BITPOS)>>RK29_CAM_POWERDNACTIVE_BITPOS));
-
- }
-
- if (camera_flash != INVALID_GPIO) {
- ret = gpio_request(camera_flash, "camera flash");
- if (ret)
- goto sensor_io_int_loop_end;
- rk29_camera_platform_data.gpio_res[i].gpio_init |= RK29_CAM_FLASHACTIVE_MASK;
- /*lzg@rock-chips.com; to forbid to flash while powing on ;*/
-#if 0
- gpio_set_value(camera_flash, ((camera_ioflag&RK29_CAM_FLASHACTIVE_MASK)>>RK29_CAM_FLASHACTIVE_BITPOS));
- gpio_direction_output(camera_flash, ((camera_ioflag&RK29_CAM_FLASHACTIVE_MASK)>>RK29_CAM_FLASHACTIVE_BITPOS));
-#endif
- //printk("\n%s....flash pin(%d) init success(0x%x) \n",__FUNCTION__,camera_flash,((camera_ioflag&RK29_CAM_FLASHACTIVE_MASK)>>RK29_CAM_FLASHACTIVE_BITPOS));
-
- }
- continue;
-sensor_io_int_loop_end:
- rk29_sensor_io_deinit(i);
- continue;
- }
-
- return 0;
-}
-
-static int rk29_sensor_io_deinit(int sensor)
-{
- unsigned int camera_reset = INVALID_GPIO, camera_power = INVALID_GPIO;
- unsigned int camera_powerdown = INVALID_GPIO, camera_flash = INVALID_GPIO;
-
- camera_reset = rk29_camera_platform_data.gpio_res[sensor].gpio_reset;
- camera_power = rk29_camera_platform_data.gpio_res[sensor].gpio_power;
- camera_powerdown = rk29_camera_platform_data.gpio_res[sensor].gpio_powerdown;
- camera_flash = rk29_camera_platform_data.gpio_res[sensor].gpio_flash;
-
- if (rk29_camera_platform_data.gpio_res[sensor].gpio_init & RK29_CAM_POWERACTIVE_MASK) {
- if (camera_power != INVALID_GPIO) {
- gpio_direction_input(camera_power);
- gpio_free(camera_power);
- }
- }
-
- if (rk29_camera_platform_data.gpio_res[sensor].gpio_init & RK29_CAM_RESETACTIVE_MASK) {
- if (camera_reset != INVALID_GPIO) {
- gpio_direction_input(camera_reset);
- gpio_free(camera_reset);
- }
- }
-
- if (rk29_camera_platform_data.gpio_res[sensor].gpio_init & RK29_CAM_POWERDNACTIVE_MASK) {
- if (camera_powerdown != INVALID_GPIO) {
- gpio_direction_input(camera_powerdown);
- gpio_free(camera_powerdown);
- }
- }
-
- if (rk29_camera_platform_data.gpio_res[sensor].gpio_init & RK29_CAM_FLASHACTIVE_MASK) {
- if (camera_flash != INVALID_GPIO) {
- gpio_direction_input(camera_flash);
- gpio_free(camera_flash);
- }
- }
-
- rk29_camera_platform_data.gpio_res[sensor].gpio_init = 0;
- return 0;
-}
-static int rk29_sensor_ioctrl(struct device *dev,enum rk29camera_ioctrl_cmd cmd, int on)
-{
- unsigned int camera_power=INVALID_GPIO,camera_reset=INVALID_GPIO, camera_powerdown=INVALID_GPIO,camera_flash = INVALID_GPIO;
- unsigned int camera_ioflag,camera_io_init;
- int ret = RK29_CAM_IO_SUCCESS;
-
- if(rk29_camera_platform_data.gpio_res[0].dev_name && (strcmp(rk29_camera_platform_data.gpio_res[0].dev_name, dev_name(dev)) == 0)) {
- camera_power = rk29_camera_platform_data.gpio_res[0].gpio_power;
- camera_reset = rk29_camera_platform_data.gpio_res[0].gpio_reset;
- camera_powerdown = rk29_camera_platform_data.gpio_res[0].gpio_powerdown;
- camera_flash = rk29_camera_platform_data.gpio_res[0].gpio_flash;
- camera_ioflag = rk29_camera_platform_data.gpio_res[0].gpio_flag;
- camera_io_init = rk29_camera_platform_data.gpio_res[0].gpio_init;
- } else if (rk29_camera_platform_data.gpio_res[1].dev_name && (strcmp(rk29_camera_platform_data.gpio_res[1].dev_name, dev_name(dev)) == 0)) {
- camera_power = rk29_camera_platform_data.gpio_res[1].gpio_power;
- camera_reset = rk29_camera_platform_data.gpio_res[1].gpio_reset;
- camera_powerdown = rk29_camera_platform_data.gpio_res[1].gpio_powerdown;
- camera_flash = rk29_camera_platform_data.gpio_res[1].gpio_flash;
- camera_ioflag = rk29_camera_platform_data.gpio_res[1].gpio_flag;
- camera_io_init = rk29_camera_platform_data.gpio_res[1].gpio_init;
- }
-
- switch (cmd)
- {
- case Cam_Power:
- {
- if (camera_power != INVALID_GPIO) {
- if (camera_io_init & RK29_CAM_POWERACTIVE_MASK) {
- if (on) {
- gpio_set_value(camera_power, ((camera_ioflag&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
- //printk("\n%s..%s..PowerPin=%d ..PinLevel = %x \n",__FUNCTION__,dev_name(dev), camera_power, ((camera_ioflag&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
- msleep(10);
- } else {
- gpio_set_value(camera_power, (((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
- //printk("\n%s..%s..PowerPin=%d ..PinLevel = %x \n",__FUNCTION__,dev_name(dev), camera_power, (((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
- }
- } else {
- ret = RK29_CAM_EIO_REQUESTFAIL;
- printk("\n%s..%s..PowerPin=%d request failed!\n",__FUNCTION__,dev_name(dev),camera_reset);
- }
- } else {
- ret = RK29_CAM_EIO_INVALID;
- }
- break;
- }
- case Cam_Reset:
- {
- if (camera_reset != INVALID_GPIO) {
- if (camera_io_init & RK29_CAM_RESETACTIVE_MASK) {
- if (on) {
- gpio_set_value(camera_reset, ((camera_ioflag&RK29_CAM_RESETACTIVE_MASK)>>RK29_CAM_RESETACTIVE_BITPOS));
- //printk("\n%s..%s..ResetPin=%d ..PinLevel = %x \n",__FUNCTION__,dev_name(dev),camera_reset, ((camera_ioflag&RK29_CAM_RESETACTIVE_MASK)>>RK29_CAM_RESETACTIVE_BITPOS));
- } else {
- gpio_set_value(camera_reset,(((~camera_ioflag)&RK29_CAM_RESETACTIVE_MASK)>>RK29_CAM_RESETACTIVE_BITPOS));
- //printk("\n%s..%s..ResetPin= %d..PinLevel = %x \n",__FUNCTION__,dev_name(dev), camera_reset, (((~camera_ioflag)&RK29_CAM_RESETACTIVE_MASK)>>RK29_CAM_RESETACTIVE_BITPOS));
- }
- } else {
- ret = RK29_CAM_EIO_REQUESTFAIL;
- printk("\n%s..%s..ResetPin=%d request failed!\n",__FUNCTION__,dev_name(dev),camera_reset);
- }
- } else {
- ret = RK29_CAM_EIO_INVALID;
- }
- break;
- }
-
- case Cam_PowerDown:
- {
- if (camera_powerdown != INVALID_GPIO) {
- if (camera_io_init & RK29_CAM_POWERDNACTIVE_MASK) {
- if (on) {
- gpio_set_value(camera_powerdown, ((camera_ioflag&RK29_CAM_POWERDNACTIVE_MASK)>>RK29_CAM_POWERDNACTIVE_BITPOS));
- //printk("\n%s..%s..PowerDownPin=%d ..PinLevel = %x \n",__FUNCTION__,dev_name(dev),camera_powerdown, ((camera_ioflag&RK29_CAM_POWERDNACTIVE_MASK)>>RK29_CAM_POWERDNACTIVE_BITPOS));
- } else {
- gpio_set_value(camera_powerdown,(((~camera_ioflag)&RK29_CAM_POWERDNACTIVE_MASK)>>RK29_CAM_POWERDNACTIVE_BITPOS));
- //printk("\n%s..%s..PowerDownPin= %d..PinLevel = %x \n",__FUNCTION__,dev_name(dev), camera_powerdown, (((~camera_ioflag)&RK29_CAM_POWERDNACTIVE_MASK)>>RK29_CAM_POWERDNACTIVE_BITPOS));
- }
- } else {
- ret = RK29_CAM_EIO_REQUESTFAIL;
- printk("\n%s..%s..PowerDownPin=%d request failed!\n",__FUNCTION__,dev_name(dev),camera_powerdown);
- }
- } else {
- ret = RK29_CAM_EIO_INVALID;
- }
- break;
- }
-
- case Cam_Flash:
- {
- if (camera_flash != INVALID_GPIO) {
- if (camera_io_init & RK29_CAM_FLASHACTIVE_MASK) {
- switch (on)
- {
- case Flash_Off:
- {
- gpio_set_value(camera_flash,(((~camera_ioflag)&RK29_CAM_FLASHACTIVE_MASK)>>RK29_CAM_FLASHACTIVE_BITPOS));
- printk("\n%s..%s..FlashPin= %d..PinLevel = %x \n",__FUNCTION__,dev_name(dev), camera_flash, (((~camera_ioflag)&RK29_CAM_FLASHACTIVE_MASK)>>RK29_CAM_FLASHACTIVE_BITPOS));
- break;
- }
-
- case Flash_On:
- {
- gpio_set_value(camera_flash, ((camera_ioflag&RK29_CAM_FLASHACTIVE_MASK)>>RK29_CAM_FLASHACTIVE_BITPOS));
- printk("\n%s..%s..FlashPin=%d ..PinLevel = %x \n",__FUNCTION__,dev_name(dev),camera_flash, ((camera_ioflag&RK29_CAM_FLASHACTIVE_MASK)>>RK29_CAM_FLASHACTIVE_BITPOS));
- break;
- }
-
- case Flash_Torch:
- {
- gpio_set_value(camera_flash, ((camera_ioflag&RK29_CAM_FLASHACTIVE_MASK)>>RK29_CAM_FLASHACTIVE_BITPOS));
- printk("\n%s..%s..FlashPin=%d ..PinLevel = %x \n",__FUNCTION__,dev_name(dev),camera_flash, ((camera_ioflag&RK29_CAM_FLASHACTIVE_MASK)>>RK29_CAM_FLASHACTIVE_BITPOS));
- break;
- }
-
- default:
- {
- printk("\n%s..%s..Flash command(%d) is invalidate \n",__FUNCTION__,dev_name(dev),on);
- break;
- }
- }
- } else {
- ret = RK29_CAM_EIO_REQUESTFAIL;
- printk("\n%s..%s..FlashPin=%d request failed!\n",__FUNCTION__,dev_name(dev),camera_flash);
- }
- } else {
- ret = RK29_CAM_EIO_INVALID;
- }
- break;
- }
-
- default:
- {
- printk("%s cmd(0x%x) is unknown!\n",__FUNCTION__, cmd);
- break;
- }
- }
- return ret;
-}
-static int rk29_sensor_power(struct device *dev, int on)
-{
- rk29_sensor_ioctrl(dev,Cam_Power,on);
- return 0;
-}
-static int rk29_sensor_reset(struct device *dev)
-{
- rk29_sensor_ioctrl(dev,Cam_Reset,1);
- msleep(2);
- rk29_sensor_ioctrl(dev,Cam_Reset,0);
- return 0;
-}
-static int rk29_sensor_powerdown(struct device *dev, int on)
-{
- return rk29_sensor_ioctrl(dev,Cam_PowerDown,on);
-}
-#if (CONFIG_SENSOR_IIC_ADDR_0 != 0x00)
-static struct i2c_board_info rk29_i2c_cam_info_0[] = {
- {
- I2C_BOARD_INFO(SENSOR_NAME_0, CONFIG_SENSOR_IIC_ADDR_0>>1)
- },
-};
-
-static struct soc_camera_link rk29_iclink_0 = {
- .bus_id = RK29_CAM_PLATFORM_DEV_ID,
- .power = rk29_sensor_power,
- .powerdown = rk29_sensor_powerdown,
- .board_info = &rk29_i2c_cam_info_0[0],
- .i2c_adapter_id = CONFIG_SENSOR_IIC_ADAPTER_ID_0,
- .module_name = SENSOR_NAME_0,
-};
-
-/*platform_device : soc-camera need */
-static struct platform_device rk29_soc_camera_pdrv_0 = {
- .name = "soc-camera-pdrv",
- .id = 0,
- .dev = {
- .init_name = SENSOR_DEVICE_NAME_0,
- .platform_data = &rk29_iclink_0,
- },
-};
-#endif
-#if (CONFIG_SENSOR_IIC_ADDR_1 != 0x00)
-static struct i2c_board_info rk29_i2c_cam_info_1[] = {
- {
- I2C_BOARD_INFO(SENSOR_NAME_1, CONFIG_SENSOR_IIC_ADDR_1>>1)
- },
-};
-
-static struct soc_camera_link rk29_iclink_1 = {
- .bus_id = RK29_CAM_PLATFORM_DEV_ID,
- .power = rk29_sensor_power,
- .powerdown = rk29_sensor_powerdown,
- .board_info = &rk29_i2c_cam_info_1[0],
- .i2c_adapter_id = CONFIG_SENSOR_IIC_ADAPTER_ID_1,
- .module_name = SENSOR_NAME_1,
-};
-
-/*platform_device : soc-camera need */
-static struct platform_device rk29_soc_camera_pdrv_1 = {
- .name = "soc-camera-pdrv",
- .id = 1,
- .dev = {
- .init_name = SENSOR_DEVICE_NAME_1,
- .platform_data = &rk29_iclink_1,
- },
-};
-#endif
-
-static u64 rockchip_device_camera_dmamask = 0xffffffffUL;
-static struct resource rk29_camera_resource[] = {
- [0] = {
- .start = RK29_VIP_PHYS,
- .end = RK29_VIP_PHYS + RK29_VIP_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_VIP,
- .end = IRQ_VIP,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/*platform_device : */
-static struct platform_device rk29_device_camera = {
- .name = RK29_CAM_DRV_NAME,
- .id = RK29_CAM_PLATFORM_DEV_ID, /* This is used to put cameras on this interface */
- .num_resources = ARRAY_SIZE(rk29_camera_resource),
- .resource = rk29_camera_resource,
- .dev = {
- .dma_mask = &rockchip_device_camera_dmamask,
- .coherent_dma_mask = 0xffffffffUL,
- .platform_data = &rk29_camera_platform_data,
- }
-};
-#endif
-/*****************************************************************************************
- * backlight devices
- * author: nzy@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- /*
- GPIO1B5_PWM0_NAME, GPIO1L_PWM0
- GPIO5D2_PWM1_UART1SIRIN_NAME, GPIO5H_PWM1
- GPIO2A3_SDMMC0WRITEPRT_PWM2_NAME, GPIO2L_PWM2
- GPIO1A5_EMMCPWREN_PWM3_NAME, GPIO1L_PWM3
- */
-
-#define PWM_ID 0
-#define PWM_MUX_NAME GPIO1B5_PWM0_NAME
-#define PWM_MUX_MODE GPIO1L_PWM0
-#define PWM_MUX_MODE_GPIO GPIO1L_GPIO1B5
-#define PWM_GPIO RK29_PIN1_PB5
-#define PWM_EFFECT_VALUE 0
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-//#define BL_EN_MUX_NAME GPIOF34_UART3_SEL_NAME
-//#define BL_EN_MUX_MODE IOMUXB_GPIO1_B34
-
-#define BL_EN_PIN RK29_PIN6_PD0
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
-
- rk29_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
- #ifdef LCD_DISP_ON_PIN
- // rk29_mux_api_set(BL_EN_MUX_NAME, BL_EN_MUX_MODE);
-
- ret = gpio_request(BL_EN_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(BL_EN_PIN);
- }
-
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
- #endif
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0;
- #ifdef LCD_DISP_ON_PIN
- gpio_free(BL_EN_PIN);
- #endif
- rk29_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret = 0;
- rk29_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- if (ret = gpio_request(PWM_GPIO, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- gpio_direction_output(PWM_GPIO, GPIO_HIGH);
- #ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, !BL_EN_VALUE);
- #endif
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- gpio_free(PWM_GPIO);
- rk29_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
- #ifdef LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, 1);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
- #endif
- return 0;
-}
-
-struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-#endif
-
-#ifdef CONFIG_CM3202
-/**********************************
- * cm3202 lightsensor *
-**********************************/
-#define CM3202_SD RK29_PIN5_PA2
-static int cm3202_init_hw(void)
-{
- int ret;
- ret = gpio_request(CM3202_SD, "cm3202_sd");
- if (ret) {
- printk( "failed to request cm3202 SD GPIO%d\n",CM3202_SD);
- }
- gpio_pull_updown(CM3202_SD,GPIOPullDown);
- return ret;
-}
-
-static void cm3202_exit_hw(void)
-{
- gpio_free(CM3202_SD);
-}
-
-struct cm3202_platform_data cm3202_info = {
- .CM3202_SD_IOPIN = CM3202_SD,
- .DATA_ADC_CHN = 2,
- .init_platform_hw = cm3202_init_hw,
- .exit_platform_hw = cm3202_exit_hw,
-};
-
-struct platform_device cm3202_device = {
- .name = "lightsensor",
- .id = -1,
- .dev = {
- .platform_data = &cm3202_info,
- }
-};
-#endif
-
-#ifdef CONFIG_FIH_TOUCHKEY_LED
-#define FIH_TOUCHKEY_LED_PWM_ID 1
-#define FIH_TOUCHKEY_LED_PWM_MUX_NAME GPIO5D2_PWM1_UART1SIRIN_NAME
-#define FIH_TOUCHKEY_LED_PWM_MUX_MODE GPIO5H_PWM1
-#define FIH_TOUCHKEY_LED_PWM_MUX_MODE_GPIO GPIO5H_GPIO5D2
-#define FIH_TOUCHKEY_LED_PWM_GPIO RK29_PIN5_PD2
-#define FIH_TOUCHKEY_LED_PWM_EFFECT_VALUE 1
-
-static int fih_touchkey_led_io_init(void)
-{
- rk29_mux_api_set(FIH_TOUCHKEY_LED_PWM_MUX_NAME, FIH_TOUCHKEY_LED_PWM_MUX_MODE);
-}
-static int fih_touchkey_led_io_deinit(void)
-{
- rk29_mux_api_set(FIH_TOUCHKEY_LED_PWM_MUX_NAME, FIH_TOUCHKEY_LED_PWM_MUX_MODE_GPIO);
-}
-
-static int fih_touchkey_led_pwm_suspend(void)
-{
- int ret = 0;
- rk29_mux_api_set(FIH_TOUCHKEY_LED_PWM_MUX_NAME, FIH_TOUCHKEY_LED_PWM_MUX_MODE_GPIO);
- if (ret = gpio_request(FIH_TOUCHKEY_LED_PWM_GPIO, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- gpio_direction_output(FIH_TOUCHKEY_LED_PWM_GPIO, GPIO_LOW);
- return ret;
-}
-
-static int fih_touchkey_led_pwm_resume(void)
-{
- gpio_free(FIH_TOUCHKEY_LED_PWM_GPIO);
- rk29_mux_api_set(FIH_TOUCHKEY_LED_PWM_MUX_NAME, FIH_TOUCHKEY_LED_PWM_MUX_MODE);
- return 0;
-}
-
-struct rk29_bl_info fih_touchkey_led_info = {
- .pwm_id = FIH_TOUCHKEY_LED_PWM_ID,
- .bl_ref = FIH_TOUCHKEY_LED_PWM_EFFECT_VALUE,
- .io_init = fih_touchkey_led_io_init,
- .io_deinit = fih_touchkey_led_io_deinit,
- .pwm_suspend = fih_touchkey_led_pwm_suspend,
- .pwm_resume = fih_touchkey_led_pwm_resume,
-};
-#endif
-#ifdef CONFIG_FIH_TOUCHKEY_LED
-struct platform_device fih_touchkey_led = {
- .name = "fih_touchkey_led",
- .id = -1,
- .dev = {
- .platform_data = &fih_touchkey_led_info,
- }
-};
-#endif
-/*****************************************************************************************
-* pwm voltage regulator devices
-******************************************************************************************/
-#if defined (CONFIG_RK29_PWM_REGULATOR)
-
-#define REGULATOR_PWM_ID 2
-#define REGULATOR_PWM_MUX_NAME GPIO2A3_SDMMC0WRITEPRT_PWM2_NAME
-#define REGULATOR_PWM_MUX_MODE GPIO2L_PWM2
-#define REGULATOR_PWM_MUX_MODE_GPIO GPIO2L_GPIO2A3
-#define REGULATOR_PWM_GPIO RK29_PIN2_PA3
-
-static struct regulator_consumer_supply pwm_consumers[] = {
- {
- .supply = "vcore",
- }
-};
-
-static struct regulator_init_data rk29_pwm_regulator_data = {
- .constraints = {
- .name = "PWM2",
- .min_uV = 950000,
- .max_uV = 1400000,
- .apply_uV = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_consumers),
- .consumer_supplies = pwm_consumers,
-};
-
-static struct pwm_platform_data rk29_regulator_pwm_platform_data = {
- .pwm_id = REGULATOR_PWM_ID,
- .pwm_gpio = REGULATOR_PWM_GPIO,
- //.pwm_iomux_name[] = REGULATOR_PWM_MUX_NAME;
- .pwm_iomux_name = REGULATOR_PWM_MUX_NAME,
- .pwm_iomux_pwm = REGULATOR_PWM_MUX_MODE,
- .pwm_iomux_gpio = REGULATOR_PWM_MUX_MODE_GPIO,
- .init_data = &rk29_pwm_regulator_data,
-};
-
-static struct platform_device rk29_device_pwm_regulator = {
- .name = "pwm-voltage-regulator",
- .id = -1,
- .dev = {
- .platform_data = &rk29_regulator_pwm_platform_data,
- },
-};
-
-#endif
-
-
-/*****************************************************************************************
- * SDMMC devices
-*****************************************************************************************/
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
- rk29_mux_api_set(GPIO1D1_SDMMC0CMD_NAME, GPIO1H_SDMMC0_CMD);
- rk29_mux_api_set(GPIO1D0_SDMMC0CLKOUT_NAME, GPIO1H_SDMMC0_CLKOUT);
- rk29_mux_api_set(GPIO1D2_SDMMC0DATA0_NAME, GPIO1H_SDMMC0_DATA0);
- rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_SDMMC0_DATA1);
- rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_SDMMC0_DATA2);
- rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_SDMMC0_DATA3);
- rk29_mux_api_set(GPIO2A2_SDMMC0DETECTN_NAME, GPIO2L_GPIO2A2);
- rk29_mux_api_set(GPIO5D5_SDMMC0PWREN_NAME, GPIO5H_GPIO5D5); ///GPIO5H_SDMMC0_PWR_EN); ///GPIO5H_GPIO5D5);
- gpio_request(RK29_PIN5_PD5,"sdmmc");
-#if 0
- gpio_set_value(RK29_PIN5_PD5,GPIO_HIGH);
- mdelay(100);
- gpio_set_value(RK29_PIN5_PD5,GPIO_LOW);
-#else
- gpio_direction_output(RK29_PIN5_PD5,GPIO_LOW);
-#endif
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail = (MMC_VDD_25_26|MMC_VDD_26_27|MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30|
- MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33|
- MMC_VDD_33_34|MMC_VDD_34_35| MMC_VDD_35_36),
- .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
- .detect_irq = RK29_PIN2_PA2, // INVALID_GPIO
- .enable_sd_wakeup = 0,
-};
-#endif
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);
- rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_SDMMC1_DATA1);
- rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_SDMMC1_DATA2);
- rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_SDMMC1_DATA3);
- //rk29_mux_api_set(GPIO1C0_UART0CTSN_SDMMC1DETECTN_NAME, GPIO1H_SDMMC1_DETECT_N);
- return 0;
-}
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
-static int rk29sdk_wifi_status(struct device *dev);
-static int rk29sdk_wifi_status_register(void (*callback)(int card_presend, void *dev_id), void *dev_id);
-#endif
-
-#define RK29SDK_WIFI_SDIO_CARD_DETECT_N RK29_PIN1_PD6
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail = (MMC_VDD_25_26|MMC_VDD_26_27|MMC_VDD_27_28|MMC_VDD_28_29|
- MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32|
- MMC_VDD_32_33|MMC_VDD_33_34),
- .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_SDIO_IRQ|
- MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc1_cfg_gpio,
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-#if 0
- .detect_irq = RK29SDK_WIFI_SDIO_CARD_DETECT_N,
-#endif
-};
-#endif
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
-#define RK29SDK_WIFI_BT_GPIO_POWER_N RK29_PIN5_PD6
-#define RK29SDK_WIFI_GPIO_RESET_N RK29_PIN6_PC0
-#define RK29SDK_BT_GPIO_RESET_N RK29_PIN6_PC4
-
-static int rk29sdk_wifi_cd = 0; /* wifi virtual 'card detect' status */
-static void (*wifi_status_cb)(int card_present, void *dev_id);
-static void *wifi_status_cb_devid;
-int rk29sdk_wifi_power_state = 0;
-int rk29sdk_bt_power_state = 0;
-
-static int rk29sdk_wifi_status(struct device *dev)
-{
- return rk29sdk_wifi_cd;
-}
-
-static int rk29sdk_wifi_status_register(void (*callback)(int card_present, void *dev_id), void *dev_id)
-{
- if(wifi_status_cb)
- return -EAGAIN;
- wifi_status_cb = callback;
- wifi_status_cb_devid = dev_id;
- return 0;
-}
-
-static int rk29sdk_wifi_bt_gpio_control_init(void)
-{
- if (gpio_request(RK29SDK_WIFI_BT_GPIO_POWER_N, "wifi_bt_power")) {
- pr_info("%s: request wifi_bt power gpio failed\n", __func__);
- return -1;
- }
-
- if (gpio_request(RK29SDK_WIFI_GPIO_RESET_N, "wifi reset")) {
- pr_info("%s: request wifi reset gpio failed\n", __func__);
- gpio_free(RK29SDK_WIFI_BT_GPIO_POWER_N);
- return -1;
- }
-
- if (gpio_request(RK29SDK_BT_GPIO_RESET_N, "bt reset")) {
- pr_info("%s: request bt reset gpio failed\n", __func__);
- gpio_free(RK29SDK_WIFI_GPIO_RESET_N);
- return -1;
- }
-
- gpio_direction_output(RK29SDK_WIFI_BT_GPIO_POWER_N, GPIO_LOW);
- gpio_direction_output(RK29SDK_WIFI_GPIO_RESET_N, GPIO_LOW);
- gpio_direction_output(RK29SDK_BT_GPIO_RESET_N, GPIO_LOW);
-
- pr_info("%s: init finished\n",__func__);
-
- return 0;
-}
-
-static int rk29sdk_wifi_power(int on)
-{
- pr_info("%s: %d\n", __func__, on);
- if (on){
- gpio_set_value(RK29SDK_WIFI_BT_GPIO_POWER_N, GPIO_HIGH);
- gpio_set_value(RK29SDK_WIFI_GPIO_RESET_N, GPIO_HIGH);
- mdelay(100);
- pr_info("wifi turn on power\n");
- }else{
- if (!rk29sdk_bt_power_state){
- gpio_set_value(RK29SDK_WIFI_BT_GPIO_POWER_N, GPIO_LOW);
- mdelay(100);
- pr_info("wifi shut off power\n");
- }else
- {
- pr_info("wifi shouldn't shut off power, bt is using it!\n");
- }
- gpio_set_value(RK29SDK_WIFI_GPIO_RESET_N, GPIO_LOW);
-
- }
-
- rk29sdk_wifi_power_state = on;
- return 0;
-}
-
-static int rk29sdk_wifi_reset_state;
-static int rk29sdk_wifi_reset(int on)
-{
- pr_info("%s: %d\n", __func__, on);
- gpio_set_value(RK29SDK_WIFI_GPIO_RESET_N, on);
- mdelay(100);
- rk29sdk_wifi_reset_state = on;
- return 0;
-}
-
-int rk29sdk_wifi_set_carddetect(int val)
-{
- pr_info("%s:%d\n", __func__, val);
- rk29sdk_wifi_cd = val;
- if (wifi_status_cb){
- wifi_status_cb(val, wifi_status_cb_devid);
- }else {
- pr_warning("%s, nobody to notify\n", __func__);
- }
- return 0;
-}
-EXPORT_SYMBOL(rk29sdk_wifi_set_carddetect);
-
-static struct wifi_mem_prealloc wifi_mem_array[PREALLOC_WLAN_SEC_NUM] = {
- {NULL, (WLAN_SECTION_SIZE_0 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_1 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_2 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_3 + PREALLOC_WLAN_SECTION_HEADER)}
-};
-
-static void *rk29sdk_mem_prealloc(int section, unsigned long size)
-{
- if (section == PREALLOC_WLAN_SEC_NUM)
- return wlan_static_skb;
-
- if ((section < 0) || (section > PREALLOC_WLAN_SEC_NUM))
- return NULL;
-
- if (wifi_mem_array[section].size < size)
- return NULL;
-
- return wifi_mem_array[section].mem_ptr;
-}
-
-int __init rk29sdk_init_wifi_mem(void)
-{
- int i;
- int j;
-
- for (i = 0 ; i < WLAN_SKB_BUF_NUM ; i++) {
- wlan_static_skb[i] = dev_alloc_skb(
- ((i < (WLAN_SKB_BUF_NUM / 2)) ? 4096 : 8192));
-
- if (!wlan_static_skb[i])
- goto err_skb_alloc;
- }
-
- for (i = 0 ; i < PREALLOC_WLAN_SEC_NUM ; i++) {
- wifi_mem_array[i].mem_ptr =
- kmalloc(wifi_mem_array[i].size, GFP_KERNEL);
-
- if (!wifi_mem_array[i].mem_ptr)
- goto err_mem_alloc;
- }
- return 0;
-
-err_mem_alloc:
- pr_err("Failed to mem_alloc for WLAN\n");
- for (j = 0 ; j < i ; j++)
- kfree(wifi_mem_array[j].mem_ptr);
-
- i = WLAN_SKB_BUF_NUM;
-
-err_skb_alloc:
- pr_err("Failed to skb_alloc for WLAN\n");
- for (j = 0 ; j < i ; j++)
- dev_kfree_skb(wlan_static_skb[j]);
-
- return -ENOMEM;
-}
-
-static struct wifi_platform_data rk29sdk_wifi_control = {
- .set_power = rk29sdk_wifi_power,
- .set_reset = rk29sdk_wifi_reset,
- .set_carddetect = rk29sdk_wifi_set_carddetect,
- .mem_prealloc = rk29sdk_mem_prealloc,
-};
-static struct platform_device rk29sdk_wifi_device = {
- .name = "bcm4329_wlan",
- .id = 1,
- .dev = {
- .platform_data = &rk29sdk_wifi_control,
- },
-};
-#endif
-
-/* bluetooth rfkill device */
-static struct platform_device rk29sdk_rfkill = {
- .name = "rk29sdk_rfkill",
- .id = -1,
-};
-
-
-#ifdef CONFIG_VIVANTE
-static struct resource resources_gpu[] = {
- [0] = {
- .name = "gpu_irq",
- .start = IRQ_GPU,
- .end = IRQ_GPU,
- .flags = IORESOURCE_IRQ,
- },
- [1] = {
- .name = "gpu_base",
- .start = RK29_GPU_PHYS,
- .end = RK29_GPU_PHYS + RK29_GPU_SIZE,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "gpu_mem",
- .start = PMEM_GPU_BASE,
- .end = PMEM_GPU_BASE + PMEM_GPU_SIZE,
- .flags = IORESOURCE_MEM,
- },
-};
-static struct platform_device rk29_device_gpu = {
- .name = "galcore",
- .id = 0,
- .num_resources = ARRAY_SIZE(resources_gpu),
- .resource = resources_gpu,
-};
-#endif
-#ifdef CONFIG_KEYS_RK29
-extern struct rk29_keys_platform_data rk29_keys_pdata;
-static struct platform_device rk29_device_keys = {
- .name = "rk29-keypad",
- .id = -1,
- .dev = {
- .platform_data = &rk29_keys_pdata,
- },
-};
-#endif
-#if CONFIG_ANDROID_TIMED_GPIO
-static struct timed_gpio timed_gpios[] = {
- {
- .name = "vibrator",
- .gpio = RK29_PIN6_PD3,
- .max_timeout = 1000,
- .active_low = 0,
- .adjust_time =5, //adjust for diff product
- },
- {
- .name = "vibratorR",
- .gpio = RK29_PIN4_PD5,
- .max_timeout = 1000,
- .active_low = 0,
- .adjust_time =5, //adjust for diff product
-
- },
-};
-struct timed_gpio_platform_data rk29_vibrator_info = {
- .num_gpios = 2,
- .gpios = timed_gpios,
-};
-
-struct platform_device rk29_device_vibrator ={
- .name = "timed-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_vibrator_info,
- },
-
-};
-#endif
-static void __init rk29_board_iomux_init(void)
-{
- #ifdef CONFIG_RK29_PWM_REGULATOR
- rk29_mux_api_set(REGULATOR_PWM_MUX_NAME,REGULATOR_PWM_MUX_MODE);
- #endif
- #if defined (CONFIG_TPS65910_CORE)
- rk29_mux_api_set(GPIO4D32_CPUTRACEDATA32_NAME, GPIO4H_GPIO4D32);
- #endif
-}
-
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_UART1_RK29
- &rk29_device_uart1,
-#endif
-#ifdef CONFIG_UART0_RK29
- &rk29_device_uart0,
-#endif
-#ifdef CONFIG_UART2_RK29
- &rk29_device_uart2,
-#endif
-#ifdef CONFIG_UART3_RK29
- &rk29_device_uart3,
-#endif
-#ifdef CONFIG_RK29_PWM_REGULATOR
- &rk29_device_pwm_regulator,
-#endif
-#ifdef CONFIG_SPIM0_RK29
- &rk29xx_device_spi0m,
-#endif
-#ifdef CONFIG_SPIM1_RK29
- &rk29xx_device_spi1m,
-#endif
-#ifdef CONFIG_ADC_RK29
- &rk29_device_adc,
-#endif
-#ifdef CONFIG_I2C0_RK29
- &rk29_device_i2c0,
-#endif
-#ifdef CONFIG_I2C1_RK29
- &rk29_device_i2c1,
-#endif
-#ifdef CONFIG_I2C2_RK29
- &rk29_device_i2c2,
-#endif
-#ifdef CONFIG_I2C3_RK29
- &rk29_device_i2c3,
-#endif
-
-#ifdef CONFIG_SND_RK29_SOC_I2S_2CH
- &rk29_device_iis_2ch,
-#endif
-#ifdef CONFIG_SND_RK29_SOC_I2S_8CH
- &rk29_device_iis_8ch,
-#endif
-
-#ifdef CONFIG_KEYS_RK29
- &rk29_device_keys,
-#endif
-#ifdef CONFIG_SDMMC0_RK29
- &rk29_device_sdmmc0,
-#endif
-#ifdef CONFIG_SDMMC1_RK29
- &rk29_device_sdmmc1,
-#endif
-
-#ifdef CONFIG_CM3202
- &cm3202_device,
-#endif
-
-#ifdef CONFIG_MTD_NAND_RK29XX
- &rk29xx_device_nand,
-#endif
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- &rk29sdk_wifi_device,
-#endif
-
-#ifdef CONFIG_BT
- &rk29sdk_rfkill,
-#endif
-
-#ifdef CONFIG_MTD_NAND_RK29
- &rk29_device_nand,
-#endif
-
-#ifdef CONFIG_FB_RK29
- &rk29_device_fb,
- &rk29_device_dma_cpy,
-#endif
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- &rk29_device_backlight,
-#endif
-#ifdef CONFIG_RK29_VMAC
- &rk29_device_vmac,
-#endif
-#ifdef CONFIG_VIVANTE
- &rk29_device_gpu,
-#endif
-#ifdef CONFIG_VIDEO_RK29
- &rk29_device_camera, /* ddl@rock-chips.com : camera support */
- #if (CONFIG_SENSOR_IIC_ADDR_0 != 0x00)
- &rk29_soc_camera_pdrv_0,
- #endif
- #if (CONFIG_SENSOR_IIC_ADDR_1 != 0x00)
- &rk29_soc_camera_pdrv_1,
- #endif
- &android_pmem_cam_device,
-#endif
- &android_pmem_device,
- &rk29_vpu_mem_device,
-#ifdef CONFIG_USB20_OTG
- &rk29_device_usb20_otg,
-#endif
-#ifdef CONFIG_USB20_HOST
- &rk29_device_usb20_host,
-#endif
-#ifdef CONFIG_USB11_HOST
- &rk29_device_usb11_host,
-#endif
-#ifdef CONFIG_USB_ANDROID
- &android_usb_device,
- &usb_mass_storage_device,
-#endif
-#ifdef CONFIG_RK29_IPP
- &rk29_device_ipp,
-#endif
-#ifdef CONFIG_VIDEO_RK29XX_VOUT
- &rk29_v4l2_output_devce,
-#endif
-#ifdef CONFIG_ANDROID_TIMED_GPIO
- &rk29_device_vibrator,
-#endif
-#ifdef CONFIG_FIH_TOUCHKEY_LED
- &fih_touchkey_led,
-#endif
-};
-
-/*****************************************************************************************
- * spi devices
- * author: cmc@rock-chips.com
- *****************************************************************************************/
-static int rk29_vmac_register_set(void)
-{
- //config rk29 vmac as rmii, 100MHz
- u32 value= readl(RK29_GRF_BASE + 0xbc);
- value = (value & 0xfff7ff) | (0x400);
- writel(value, RK29_GRF_BASE + 0xbc);
- return 0;
-}
-
-static int rk29_rmii_io_init(void)
-{
- int err;
-
- //phy power gpio
- err = gpio_request(RK29_PIN6_PB0, "phy_power_en");
- if (err) {
- gpio_free(RK29_PIN6_PB0);
- printk("-------request RK29_PIN6_PB0 fail--------\n");
- return -1;
- }
- //phy power down
- gpio_direction_output(RK29_PIN6_PB0, GPIO_LOW);
- gpio_set_value(RK29_PIN6_PB0, GPIO_LOW);
-
- return 0;
-}
-
-static int rk29_rmii_io_deinit(void)
-{
- //phy power down
- gpio_direction_output(RK29_PIN6_PB0, GPIO_LOW);
- gpio_set_value(RK29_PIN6_PB0, GPIO_LOW);
- //free
- gpio_free(RK29_PIN6_PB0);
- return 0;
-}
-
-static int rk29_rmii_power_control(int enable)
-{
- if (enable) {
- //enable phy power
- gpio_direction_output(RK29_PIN6_PB0, GPIO_HIGH);
- gpio_set_value(RK29_PIN6_PB0, GPIO_HIGH);
- }
- else {
- gpio_direction_output(RK29_PIN6_PB0, GPIO_LOW);
- gpio_set_value(RK29_PIN6_PB0, GPIO_LOW);
- }
- return 0;
-}
-
-struct rk29_vmac_platform_data rk29_vmac_pdata = {
- .vmac_register_set = rk29_vmac_register_set,
- .rmii_io_init = rk29_rmii_io_init,
- .rmii_io_deinit = rk29_rmii_io_deinit,
- .rmii_power_control = rk29_rmii_power_control,
-};
-
-/*****************************************************************************************
- * spi devices
- * author: cmc@rock-chips.com
- *****************************************************************************************/
-#define SPI_CHIPSELECT_NUM 2
-static struct spi_cs_gpio rk29xx_spi0_cs_gpios[SPI_CHIPSELECT_NUM] = {
- {
- .name = "spi0 cs0",
- .cs_gpio = RK29_PIN2_PC1,
- .cs_iomux_name = GPIO2C1_SPI0CSN0_NAME,
- .cs_iomux_mode = GPIO2H_SPI0_CSN0,
- },
- {
- .name = "spi0 cs1",
- .cs_gpio = RK29_PIN1_PA4,
- .cs_iomux_name = GPIO1A4_EMMCWRITEPRT_SPI0CS1_NAME,//if no iomux,set it NULL
- .cs_iomux_mode = GPIO1L_SPI0_CSN1,
- }
-};
-
-static struct spi_cs_gpio rk29xx_spi1_cs_gpios[SPI_CHIPSELECT_NUM] = {
- {
- .name = "spi1 cs0",
- .cs_gpio = RK29_PIN2_PC5,
- .cs_iomux_name = GPIO2C5_SPI1CSN0_NAME,
- .cs_iomux_mode = GPIO2H_SPI1_CSN0,
- },
- {
- .name = "spi1 cs1",
- .cs_gpio = RK29_PIN1_PA3,
- .cs_iomux_name = GPIO1A3_EMMCDETECTN_SPI1CS1_NAME,//if no iomux,set it NULL
- .cs_iomux_mode = GPIO1L_SPI1_CSN1,
- }
-};
-
-static int spi_io_init(struct spi_cs_gpio *cs_gpios, int cs_num)
-{
-#if 1
- int i;
- if (cs_gpios) {
- for (i=0; i<cs_num; i++) {
- rk29_mux_api_set(cs_gpios[i].cs_iomux_name, cs_gpios[i].cs_iomux_mode);
- }
- }
-#endif
-
- return 0;
-}
-
-static int spi_io_deinit(struct spi_cs_gpio *cs_gpios, int cs_num)
-{
-
- return 0;
-}
-
-static int spi_io_fix_leakage_bug(void)
-{
-#if 0
- gpio_direction_output(RK29_PIN2_PC1, GPIO_LOW);
-#endif
- return 0;
-}
-
-static int spi_io_resume_leakage_bug(void)
-{
-#if 0
- gpio_direction_output(RK29_PIN2_PC1, GPIO_HIGH);
-#endif
- return 0;
-}
-
-struct rk29xx_spi_platform_data rk29xx_spi0_platdata = {
- .num_chipselect = SPI_CHIPSELECT_NUM,
- .chipselect_gpios = rk29xx_spi0_cs_gpios,
- .io_init = spi_io_init,
- .io_deinit = spi_io_deinit,
- .io_fix_leakage_bug = spi_io_fix_leakage_bug,
- .io_resume_leakage_bug = spi_io_resume_leakage_bug,
-};
-
-struct rk29xx_spi_platform_data rk29xx_spi1_platdata = {
- .num_chipselect = SPI_CHIPSELECT_NUM,
- .chipselect_gpios = rk29xx_spi1_cs_gpios,
- .io_init = spi_io_init,
- .io_deinit = spi_io_deinit,
- .io_fix_leakage_bug = spi_io_fix_leakage_bug,
- .io_resume_leakage_bug = spi_io_resume_leakage_bug,
-};
-
-/*****************************************************************************************
- * xpt2046 touch panel
- * author: cmc@rock-chips.com
- *****************************************************************************************/
-#define XPT2046_GPIO_INT RK29_PIN0_PA3
-#define DEBOUNCE_REPTIME 3
-
-#if defined(CONFIG_TOUCHSCREEN_XPT2046_320X480_SPI)
-static struct xpt2046_platform_data xpt2046_info = {
- .model = 2046,
- .keep_vref_on = 1,
- .swap_xy = 0,
- .x_min = 0,
- .x_max = 320,
- .y_min = 0,
- .y_max = 480,
- .debounce_max = 7,
- .debounce_rep = DEBOUNCE_REPTIME,
- .debounce_tol = 20,
- .gpio_pendown = XPT2046_GPIO_INT,
- .penirq_recheck_delay_usecs = 1,
-};
-#elif defined(CONFIG_TOUCHSCREEN_XPT2046_320X480_CBN_SPI)
-static struct xpt2046_platform_data xpt2046_info = {
- .model = 2046,
- .keep_vref_on = 1,
- .swap_xy = 0,
- .x_min = 0,
- .x_max = 320,
- .y_min = 0,
- .y_max = 480,
- .debounce_max = 7,
- .debounce_rep = DEBOUNCE_REPTIME,
- .debounce_tol = 20,
- .gpio_pendown = XPT2046_GPIO_INT,
- .penirq_recheck_delay_usecs = 1,
-};
-#elif defined(CONFIG_TOUCHSCREEN_XPT2046_SPI)
-static struct xpt2046_platform_data xpt2046_info = {
- .model = 2046,
- .keep_vref_on = 1,
- .swap_xy = 1,
- .x_min = 0,
- .x_max = 800,
- .y_min = 0,
- .y_max = 480,
- .debounce_max = 7,
- .debounce_rep = DEBOUNCE_REPTIME,
- .debounce_tol = 20,
- .gpio_pendown = XPT2046_GPIO_INT,
-
- .penirq_recheck_delay_usecs = 1,
-};
-#elif defined(CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI)
-static struct xpt2046_platform_data xpt2046_info = {
- .model = 2046,
- .keep_vref_on = 1,
- .swap_xy = 1,
- .x_min = 0,
- .x_max = 800,
- .y_min = 0,
- .y_max = 480,
- .debounce_max = 7,
- .debounce_rep = DEBOUNCE_REPTIME,
- .debounce_tol = 20,
- .gpio_pendown = XPT2046_GPIO_INT,
-
- .penirq_recheck_delay_usecs = 1,
-};
-#endif
-
-static struct spi_board_info board_spi_devices[] = {
-#if defined(CONFIG_TOUCHSCREEN_XPT2046_320X480_SPI) || defined(CONFIG_TOUCHSCREEN_XPT2046_320X480_CBN_SPI)\
- ||defined(CONFIG_TOUCHSCREEN_XPT2046_SPI) || defined(CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI)
- {
- .modalias = "xpt2046_ts",
- .chip_select = 0,
- .max_speed_hz = 125 * 1000 * 26,/* (max sample rate @ 3V) * (cmd + data + overhead) */
- .bus_num = 0,
- .irq = XPT2046_GPIO_INT,
- .platform_data = &xpt2046_info,
- },
-#endif
-};
-
-
-static void __init rk29_gic_init_irq(void)
-{
- gic_dist_init(0, (void __iomem *)RK29_GICPERI_BASE, 32);
- gic_cpu_init(0, (void __iomem *)RK29_GICCPU_BASE);
-}
-
-static void __init machine_rk29_init_irq(void)
-{
- rk29_gic_init_irq();
- rk29_gpio_init();
-}
-
-static void __init machine_rk29_board_init(void)
-{
- rk29_board_iomux_init();
-
- board_power_init();
-
- platform_add_devices(devices, ARRAY_SIZE(devices));
-#ifdef CONFIG_I2C0_RK29
- i2c_register_board_info(default_i2c0_data.bus_num, board_i2c0_devices,
- ARRAY_SIZE(board_i2c0_devices));
-#endif
-#ifdef CONFIG_I2C1_RK29
- i2c_register_board_info(default_i2c1_data.bus_num, board_i2c1_devices,
- ARRAY_SIZE(board_i2c1_devices));
-#endif
-#ifdef CONFIG_I2C2_RK29
- i2c_register_board_info(default_i2c2_data.bus_num, board_i2c2_devices,
- ARRAY_SIZE(board_i2c2_devices));
-#endif
-#ifdef CONFIG_I2C3_RK29
- i2c_register_board_info(default_i2c3_data.bus_num, board_i2c3_devices,
- ARRAY_SIZE(board_i2c3_devices));
-#endif
-
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- rk29sdk_wifi_bt_gpio_control_init();
- rk29sdk_init_wifi_mem();
-#endif
-
- board_usb_detect_init(RK29_PIN0_PA0);
-}
-
-static void __init machine_rk29_fixup(struct machine_desc *desc, struct tag *tags,
- char **cmdline, struct meminfo *mi)
-{
- mi->nr_banks = 1;
- mi->bank[0].start = RK29_SDRAM_PHYS;
- mi->bank[0].node = PHYS_TO_NID(RK29_SDRAM_PHYS);
- mi->bank[0].size = LINUX_SIZE;
-}
-
-static void __init machine_rk29_mapio(void)
-{
- rk29_map_common_io();
- rk29_setup_early_printk();
- rk29_sram_init();
- rk29_clock_init(periph_pll_288mhz);
- rk29_iomux_init();
- ddr_init(DDR_TYPE,DDR_FREQ); // DDR3_1333H, 400
-}
-
-MACHINE_START(RK29, "RK29board")
- /* UART for LL DEBUG */
- .phys_io = RK29_UART1_PHYS,
- .io_pg_offst = ((RK29_UART1_BASE) >> 18) & 0xfffc,
- .boot_params = RK29_SDRAM_PHYS + 0x88000,
- .fixup = machine_rk29_fixup,
- .map_io = machine_rk29_mapio,
- .init_irq = machine_rk29_init_irq,
- .init_machine = machine_rk29_board_init,
- .timer = &rk29_timer,
-MACHINE_END
+++ /dev/null
-/* arch/arm/mach-rk29/board-rk29.c
- *
- * Copyright (C) 2010 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/android_pmem.h>
-#ifdef CONFIG_USB_ANDROID
-#include <linux/usb/android_composite.h>
-#endif
-#include <linux/ion.h>
-
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/iomux.h>
-#include <mach/gpio.h>
-#include <mach/irqs.h>
-#include <mach/rk29_iomap.h>
-#include <mach/board.h>
-#include <mach/rk29_nand.h>
-#include <mach/rk29_camera.h> /* ddl@rock-chips.com : camera support */
-#include <media/soc_camera.h> /* ddl@rock-chips.com : camera support */
-#include <mach/vpu_mem.h>
-#include <mach/sram.h>
-#include <mach/ddr.h>
-#include <mach/cpufreq.h>
-#include <mach/rk29_smc.h>
-
-#include <linux/regulator/rk29-pwm-regulator.h>
-#include <linux/regulator/machine.h>
-
-#include <linux/regulator/act8891.h>
-
-#include <linux/mtd/nand.h>
-#include <linux/mtd/partitions.h>
-#include <linux/i2c-gpio.h>
-#include <linux/mpu.h>
-#include "devices.h"
-#include "../../../drivers/input/touchscreen/xpt2046_cbn_ts.h"
-
-#ifdef CONFIG_BU92747GUW_CIR
-#include "../../../drivers/cir/bu92747guw_cir.h"
-#endif
-#ifdef CONFIG_VIDEO_RK29
-#include <plat/rk_camera.h>
-/* Notes:
-
-Simple camera device registration:
-
- new_camera_device(sensor_name,\ // sensor name, it is equal to CONFIG_SENSOR_X
- face,\ // sensor face information, it can be back or front
- pwdn_io,\ // power down gpio configuration, it is equal to CONFIG_SENSOR_POWERDN_PIN_XX
- flash_attach,\ // sensor is attach flash or not
- mir,\ // sensor image mirror and flip control information
- i2c_chl,\ // i2c channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_IIC_ADAPTER_ID_X
- cif_chl) \ // cif channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_CIF_INDEX_X
-
-Comprehensive camera device registration:
-
- new_camera_device_ex(sensor_name,\
- face,\
- ori,\ // sensor orientation, it is equal to CONFIG_SENSOR_ORIENTATION_X
- pwr_io,\ // sensor power gpio configuration, it is equal to CONFIG_SENSOR_POWER_PIN_XX
- pwr_active,\ // sensor power active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- rst_io,\ // sensor reset gpio configuration, it is equal to CONFIG_SENSOR_RESET_PIN_XX
- rst_active,\ // sensor reset active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- pwdn_io,\
- pwdn_active,\ // sensor power down active level, is equal to CONFIG_SENSOR_POWERDNACTIVE_LEVEL_X
- flash_attach,\
- res,\ // sensor resolution, this is real resolution or resoltuion after interpolate
- mir,\
- i2c_chl,\
- i2c_spd,\ // i2c speed , 100000 = 100KHz
- i2c_addr,\ // the i2c slave device address for sensor
- cif_chl,\
- mclk)\ // sensor input clock rate, 24 or 48
-
-*/
-static struct rkcamera_platform_data new_camera[] = {
-#ifdef CONFIG_SOC_CAMERA_OV2655
- new_camera_device(RK29_CAM_SENSOR_OV2655,
- back,
- RK29_PIN5_PD7,
- 0,
- 0,
- 1,
- 0),
-#endif
-#ifdef CONFIG_SOC_CAMERA_OV9665
- new_camera_device(RK29_CAM_SENSOR_OV9665,
- front,
- RK29_PIN6_PB7,
- 0,
- 0,
- 1,
- 0),
-#endif
- new_camera_device(RK29_CAM_SENSOR_OV2655,
- front,
- RK29_PIN6_PB7,
- 0,
- 0,
- 1,
- 0),
- new_camera_device_end
-};
-/*---------------- Camera Sensor Macro Define Begin ------------------------*/
-/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
-#ifdef CONFIG_SOC_CAMERA_OV2655
-#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_OV2655 /* back camera sensor *//* back camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_0 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 1
-#define CONFIG_SENSOR_ORIENTATION_0 90
-#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 RK29_PIN5_PD7//RK29_PIN6_PB7
-#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_L
-#endif
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 12504
-#define CONFIG_SENSOR_240X160_FPS_FIXED_0 12504
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 12504
-#define CONFIG_SENSOR_CIF_FPS_FIXED_0 12504
-#define CONFIG_SENSOR_VGA_FPS_FIXED_0 12504
-#define CONFIG_SENSOR_480P_FPS_FIXED_0 12504
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 12504
-#define CONFIG_SENSOR_720P_FPS_FIXED_0 12504
-#ifdef CONFIG_SOC_CAMERA_OV9665
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_OV9665 /* front camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_1 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 1
-#define CONFIG_SENSOR_ORIENTATION_1 0
-#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_1 RK29_PIN6_PB7//RK29_PIN5_PD7
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-#endif
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_OV2655 /* back camera sensor *//* back camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_1 0x60
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 1
-#define CONFIG_SENSOR_ORIENTATION_1 270
-#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_1 RK29_PIN6_PB7//RK29_PIN6_PB7
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 12504
-#define CONFIG_SENSOR_240X160_FPS_FIXED_1 12504
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 12504
-#define CONFIG_SENSOR_CIF_FPS_FIXED_1 12504
-#define CONFIG_SENSOR_VGA_FPS_FIXED_1 12504
-#define CONFIG_SENSOR_480P_FPS_FIXED_1 12504
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 12504
-#define CONFIG_SENSOR_720P_FPS_FIXED_1 12504
-#endif //#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk29_camera.c"
-/*---------------- Camera Sensor Macro Define End ------------------------*/
-
-
-/* Set memory size of pmem */
-#ifdef CONFIG_RK29_MEM_SIZE_M
-#define SDRAM_SIZE (CONFIG_RK29_MEM_SIZE_M * SZ_1M)
-#else
-#define SDRAM_SIZE SZ_512M
-#endif
-#define PMEM_GPU_SIZE SZ_128M
-#define PMEM_UI_SIZE (68 * SZ_1M) /* 1280x800: 64M 1024x768: 48M ... */
-#define PMEM_VPU_SIZE SZ_64M
-#define PMEM_SKYPE_SIZE 0
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-#ifdef CONFIG_VIDEO_RK29_WORK_IPP
-#define MEM_CAMIPP_SIZE PMEM_CAMIPP_NECESSARY
-#else
-#define MEM_CAMIPP_SIZE 0
-#endif
-#define MEM_FB_SIZE (9*SZ_1M)
-#ifdef CONFIG_FB_WORK_IPP
-#ifdef CONFIG_FB_SCALING_OSD_1080P
-#define MEM_FBIPP_SIZE SZ_16M //1920 x 1080 x 2 x 2 //RGB565 = x2;RGB888 = x4
-#else
-#define MEM_FBIPP_SIZE SZ_8M //1920 x 1080 x 2 x 2 //RGB565 = x2;RGB888 = x4
-#endif
-#else
-#define MEM_FBIPP_SIZE 0
-#endif
-#if SDRAM_SIZE > SZ_512M
-#define PMEM_GPU_BASE (RK29_SDRAM_PHYS + SZ_512M - PMEM_GPU_SIZE)
-#else
-#define PMEM_GPU_BASE (RK29_SDRAM_PHYS + SDRAM_SIZE - PMEM_GPU_SIZE)
-#endif
-#define PMEM_UI_BASE (PMEM_GPU_BASE - PMEM_UI_SIZE)
-#define PMEM_VPU_BASE (PMEM_UI_BASE - PMEM_VPU_SIZE)
-#define PMEM_CAM_BASE (PMEM_VPU_BASE - PMEM_CAM_SIZE)
-#define MEM_CAMIPP_BASE (PMEM_CAM_BASE - MEM_CAMIPP_SIZE)
-#define MEM_FB_BASE (MEM_CAMIPP_BASE - MEM_FB_SIZE)
-#define MEM_FBIPP_BASE (MEM_FB_BASE - MEM_FBIPP_SIZE)
-#define PMEM_SKYPE_BASE (MEM_FBIPP_BASE - PMEM_SKYPE_SIZE)
-#define LINUX_SIZE (PMEM_SKYPE_BASE - RK29_SDRAM_PHYS)
-
-#define PREALLOC_WLAN_SEC_NUM 4
-#define PREALLOC_WLAN_BUF_NUM 160
-#define PREALLOC_WLAN_SECTION_HEADER 24
-
-#define WLAN_SECTION_SIZE_0 (PREALLOC_WLAN_BUF_NUM * 128)
-#define WLAN_SECTION_SIZE_1 (PREALLOC_WLAN_BUF_NUM * 128)
-#define WLAN_SECTION_SIZE_2 (PREALLOC_WLAN_BUF_NUM * 512)
-#define WLAN_SECTION_SIZE_3 (PREALLOC_WLAN_BUF_NUM * 1024)
-
-#define WLAN_SKB_BUF_NUM 16
-
-static struct sk_buff *wlan_static_skb[WLAN_SKB_BUF_NUM];
-
-struct wifi_mem_prealloc {
- void *mem_ptr;
- unsigned long size;
-};
-
-extern struct sys_timer rk29_timer;
-
-static int rk29_nand_io_init(void)
-{
- return 0;
-}
-
-struct rk29_nand_platform_data rk29_nand_data = {
- .width = 1, /* data bus width in bytes */
- .hw_ecc = 1, /* hw ecc 0: soft ecc */
- .num_flash = 1,
- .io_init = rk29_nand_io_init,
-};
-
-#define TOUCH_SCREEN_STANDBY_PIN INVALID_GPIO
-#define TOUCH_SCREEN_STANDBY_VALUE GPIO_HIGH
-#define TOUCH_SCREEN_DISPLAY_PIN INVALID_GPIO
-#define TOUCH_SCREEN_DISPLAY_VALUE GPIO_HIGH
-
-#ifdef CONFIG_FB_RK29
-/*****************************************************************************************
- * lcd devices
- * author: zyw@rock-chips.com
- *****************************************************************************************/
-//#ifdef CONFIG_LCD_TD043MGEA1
-#define LCD_TXD_PIN INVALID_GPIO
-#define LCD_CLK_PIN INVALID_GPIO
-#define LCD_CS_PIN INVALID_GPIO
-/*****************************************************************************************
-* frame buffe devices
-* author: zyw@rock-chips.com
-*****************************************************************************************/
-#define FB_ID 0
-#define FB_DISPLAY_ON_PIN RK29_PIN6_PD1
-#define FB_LCD_STANDBY_PIN INVALID_GPIO
-#define FB_LCD_CABC_EN_PIN RK29_PIN6_PD2
-#define FB_MCU_FMK_PIN INVALID_GPIO
-
-#define FB_DISPLAY_ON_VALUE GPIO_HIGH
-#define FB_LCD_STANDBY_VALUE GPIO_HIGH
-
-static int rk29_lcd_io_init(void)
-{
- int ret = 0;
- return ret;
-}
-
-static int rk29_lcd_io_deinit(void)
-{
- int ret = 0;
- return ret;
-}
-
-static struct rk29lcd_info rk29_lcd_info = {
- .txd_pin = LCD_TXD_PIN,
- .clk_pin = LCD_CLK_PIN,
- .cs_pin = LCD_CS_PIN,
- .io_init = rk29_lcd_io_init,
- .io_deinit = rk29_lcd_io_deinit,
-};
-
-int rk29_fb_io_enable(void)
-{
- if(FB_DISPLAY_ON_PIN != INVALID_GPIO)
- {
- gpio_direction_output(FB_DISPLAY_ON_PIN, 0);
- gpio_set_value(FB_DISPLAY_ON_PIN, FB_DISPLAY_ON_VALUE);
- }
- if(FB_LCD_STANDBY_PIN != INVALID_GPIO)
- {
- gpio_direction_output(FB_LCD_STANDBY_PIN, 0);
- gpio_set_value(FB_LCD_STANDBY_PIN, FB_LCD_STANDBY_VALUE);
- }
- return 0;
-}
-
-int rk29_fb_io_disable(void)
-{
- if(FB_DISPLAY_ON_PIN != INVALID_GPIO)
- {
- gpio_direction_output(FB_DISPLAY_ON_PIN, 0);
- gpio_set_value(FB_DISPLAY_ON_PIN, !FB_DISPLAY_ON_VALUE);
- }
- if(FB_LCD_STANDBY_PIN != INVALID_GPIO)
- {
- gpio_direction_output(FB_LCD_STANDBY_PIN, 0);
- gpio_set_value(FB_LCD_STANDBY_PIN, !FB_LCD_STANDBY_VALUE);
- }
- return 0;
-}
-
-static int rk29_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
- if(fb_setting->mcu_fmk_en && (FB_MCU_FMK_PIN != INVALID_GPIO))
- {
- ret = gpio_request(FB_MCU_FMK_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(FB_MCU_FMK_PIN);
- printk(">>>>>> FB_MCU_FMK_PIN gpio_request err \n ");
- }
- gpio_direction_input(FB_MCU_FMK_PIN);
- }
- if(fb_setting->disp_on_en)
- {
- if(FB_DISPLAY_ON_PIN != INVALID_GPIO)
- {
- ret = gpio_request(FB_DISPLAY_ON_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(FB_DISPLAY_ON_PIN);
- printk(">>>>>> FB_DISPLAY_ON_PIN gpio_request err \n ");
- }
- }
- else if (TOUCH_SCREEN_DISPLAY_PIN != INVALID_GPIO)
- {
- ret = gpio_request(TOUCH_SCREEN_DISPLAY_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(TOUCH_SCREEN_DISPLAY_PIN);
- printk(">>>>>> TOUCH_SCREEN_DISPLAY_PIN gpio_request err \n ");
- }
- gpio_direction_output(TOUCH_SCREEN_DISPLAY_PIN, 0);
- gpio_set_value(TOUCH_SCREEN_DISPLAY_PIN, TOUCH_SCREEN_DISPLAY_VALUE);
- }
- }
-
- if(fb_setting->disp_on_en)
- {
- if(FB_LCD_STANDBY_PIN != INVALID_GPIO)
- {
- ret = gpio_request(FB_LCD_STANDBY_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(FB_LCD_STANDBY_PIN);
- printk(">>>>>> FB_LCD_STANDBY_PIN gpio_request err \n ");
- }
- }
- else if (TOUCH_SCREEN_STANDBY_PIN != INVALID_GPIO)
- {
- ret = gpio_request(TOUCH_SCREEN_STANDBY_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(TOUCH_SCREEN_STANDBY_PIN);
- printk(">>>>>> TOUCH_SCREEN_STANDBY_PIN gpio_request err \n ");
- }
- gpio_direction_output(TOUCH_SCREEN_STANDBY_PIN, 0);
- gpio_set_value(TOUCH_SCREEN_STANDBY_PIN, TOUCH_SCREEN_STANDBY_VALUE);
- }
- }
-
- if(FB_LCD_CABC_EN_PIN != INVALID_GPIO)
- {
- ret = gpio_request(FB_LCD_CABC_EN_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(FB_LCD_CABC_EN_PIN);
- printk(">>>>>> FB_LCD_CABC_EN_PIN gpio_request err \n ");
- }
- gpio_direction_output(FB_LCD_CABC_EN_PIN, 0);
- gpio_set_value(FB_LCD_CABC_EN_PIN, GPIO_HIGH);
- }
-
- rk29_fb_io_enable(); //enable it
-
- return ret;
-}
-
-
-static struct rk29fb_info rk29_fb_info = {
- .fb_id = FB_ID,
- .mcu_fmk_pin = FB_MCU_FMK_PIN,
- .lcd_info = &rk29_lcd_info,
- .io_init = rk29_fb_io_init,
- .io_enable = rk29_fb_io_enable,
- .io_disable = rk29_fb_io_disable,
-};
-
-/* rk29 fb resource */
-static struct resource rk29_fb_resource[] = {
- [0] = {
- .name = "lcdc reg",
- .start = RK29_LCDC_PHYS,
- .end = RK29_LCDC_PHYS + RK29_LCDC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc irq",
- .start = IRQ_LCDC,
- .end = IRQ_LCDC,
- .flags = IORESOURCE_IRQ,
- },
- [2] = {
- .name = "win1 buf",
- .start = MEM_FB_BASE,
- .end = MEM_FB_BASE + MEM_FB_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- #ifdef CONFIG_FB_WORK_IPP
- [3] = {
- .name = "win1 ipp buf",
- .start = MEM_FBIPP_BASE,
- .end = MEM_FBIPP_BASE + MEM_FBIPP_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- #endif
-};
-
-/*platform_device*/
-struct platform_device rk29_device_fb = {
- .name = "rk29-fb",
- .id = 4,
- .num_resources = ARRAY_SIZE(rk29_fb_resource),
- .resource = rk29_fb_resource,
- .dev = {
- .platform_data = &rk29_fb_info,
- }
-};
-
-struct platform_device rk29_device_dma_cpy = {
- .name = "dma_memcpy",
- .id = 4,
-
-};
-
-#endif
-
-#if defined(CONFIG_RK29_GPIO_SUSPEND)
-static void key_gpio_pullupdown_enable(void)
-{
- gpio_pull_updown(RK29_PIN6_PA0, 0);
- gpio_pull_updown(RK29_PIN6_PA1, 0);
- gpio_pull_updown(RK29_PIN6_PA2, 0);
- gpio_pull_updown(RK29_PIN6_PA3, 0);
- gpio_pull_updown(RK29_PIN6_PA4, 0);
- gpio_pull_updown(RK29_PIN6_PA5, 0);
- gpio_pull_updown(RK29_PIN6_PA6, 0);
-}
-
-static void key_gpio_pullupdown_disable(void)
-{
- gpio_pull_updown(RK29_PIN6_PA0, 1);
- gpio_pull_updown(RK29_PIN6_PA1, 1);
- gpio_pull_updown(RK29_PIN6_PA2, 1);
- gpio_pull_updown(RK29_PIN6_PA3, 1);
- gpio_pull_updown(RK29_PIN6_PA4, 1);
- gpio_pull_updown(RK29_PIN6_PA5, 1);
- gpio_pull_updown(RK29_PIN6_PA6, 1);
-}
-
-void rk29_setgpio_suspend_board(void)
-{
- key_gpio_pullupdown_enable();
-}
-
-void rk29_setgpio_resume_board(void)
-{
- key_gpio_pullupdown_disable();
-}
-#endif
-
-#if defined(CONFIG_RK_IRDA) || defined(CONFIG_BU92747GUW_CIR)
-#define BU92747GUW_RESET_PIN RK29_PIN3_PD4// INVALID_GPIO //
-#define BU92747GUW_RESET_MUX_NAME GPIO3D4_HOSTWRN_NAME//NULL //
-#define BU92747GUW_RESET_MUX_MODE GPIO3H_GPIO3D4//NULL //
-
-#define BU92747GUW_PWDN_PIN RK29_PIN3_PD3//RK29_PIN5_PA7 //
-#define BU92747GUW_PWDN_MUX_NAME GPIO3D3_HOSTRDN_NAME//GPIO5A7_HSADCDATA2_NAME //
-#define BU92747GUW_PWDN_MUX_MODE GPIO3H_GPIO3D3//GPIO5L_GPIO5A7 //
-
-static int bu92747guw_io_init(void)
-{
- int ret;
-
- //reset pin
- if(BU92747GUW_RESET_MUX_NAME != NULL)
- {
- rk29_mux_api_set(BU92747GUW_RESET_MUX_NAME, BU92747GUW_RESET_MUX_MODE);
- }
- ret = gpio_request(BU92747GUW_RESET_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(BU92747GUW_RESET_PIN);
- printk(">>>>>> BU92747GUW_RESET_PIN gpio_request err \n ");
- }
- gpio_direction_output(BU92747GUW_RESET_PIN, GPIO_HIGH);
-
- //power down pin
- if(BU92747GUW_PWDN_MUX_NAME != NULL)
- {
- rk29_mux_api_set(BU92747GUW_PWDN_MUX_NAME, BU92747GUW_PWDN_MUX_MODE);
- }
- ret = gpio_request(BU92747GUW_PWDN_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(BU92747GUW_PWDN_PIN);
- printk(">>>>>> BU92747GUW_PWDN_PIN gpio_request err \n ");
- }
-
- //power down as default
- gpio_direction_output(BU92747GUW_PWDN_PIN, GPIO_LOW);
-
- return 0;
-}
-
-
-static int bu92747guw_io_deinit(void)
-{
- gpio_free(BU92747GUW_PWDN_PIN);
- gpio_free(BU92747GUW_RESET_PIN);
- return 0;
-}
-
-//power ctl func is share with irda and remote
-static int nPowerOnCount = 0;
-static DEFINE_MUTEX(bu92747_power_mutex);
-
-//1---power on; 0---power off
-static int bu92747guw_power_ctl(int enable)
-{
- printk("%s \n",__FUNCTION__);
-
- mutex_lock(&bu92747_power_mutex);
- if (enable) {
- nPowerOnCount++;
- if (nPowerOnCount == 1) {//power on first
- //smc0_init(NULL);
- gpio_set_value(BU92747GUW_PWDN_PIN, GPIO_HIGH);
- gpio_set_value(BU92747GUW_RESET_PIN, GPIO_LOW);
- mdelay(5);
- gpio_set_value(BU92747GUW_RESET_PIN, GPIO_HIGH);
- mdelay(5);
- }
- }
- else {
- nPowerOnCount--;
- if (nPowerOnCount <= 0) {//power down final
- nPowerOnCount = 0;
- //smc0_exit();
- gpio_set_value(BU92747GUW_PWDN_PIN, GPIO_LOW);
- }
- }
- mutex_unlock(&bu92747_power_mutex);
- return 0;
-}
-#endif
-
-#ifdef CONFIG_RK_IRDA
-#define IRDA_IRQ_PIN RK29_PIN5_PB2
-#define IRDA_IRQ_MUX_NAME GPIO5B2_HSADCDATA5_NAME
-#define IRDA_IRQ_MUX_MODE GPIO5L_GPIO5B2
-
-int irda_iomux_init(void)
-{
- int ret = 0;
-
- //irda irq pin
- if(IRDA_IRQ_MUX_NAME != NULL)
- {
- rk29_mux_api_set(IRDA_IRQ_MUX_NAME, IRDA_IRQ_MUX_MODE);
- }
- ret = gpio_request(IRDA_IRQ_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(IRDA_IRQ_PIN);
- printk(">>>>>> IRDA_IRQ_PIN gpio_request err \n ");
- }
- gpio_pull_updown(IRDA_IRQ_PIN, GPIO_HIGH);
- gpio_direction_input(IRDA_IRQ_PIN);
-
- return 0;
-}
-
-int irda_iomux_deinit(void)
-{
- gpio_free(IRDA_IRQ_PIN);
- return 0;
-}
-
-static struct irda_info rk29_irda_info = {
- .intr_pin = IRDA_IRQ_PIN,
- .iomux_init = irda_iomux_init,
- .iomux_deinit = irda_iomux_deinit,
- .irda_pwr_ctl = bu92747guw_power_ctl,
-};
-
-static struct platform_device irda_device = {
-#ifdef CONFIG_RK_IRDA_NET
- .name = "rk_irda",
-#else
- .name = "bu92747_irda",
-#endif
- .id = -1,
- .dev = {
- .platform_data = &rk29_irda_info,
- }
-};
-#endif
-
-#ifdef CONFIG_BU92747GUW_CIR
-#define BU92747_CIR_IRQ_PIN RK29_PIN5_PB0
-#define CIR_IRQ_PIN_IOMUX_NAME GPIO5B0_HSADCDATA3_NAME
-#define CIR_IRQ_PIN_IOMUX_VALUE GPIO5L_GPIO5B0
-static int cir_iomux_init(void)
-{
- if (CIR_IRQ_PIN_IOMUX_NAME)
- rk29_mux_api_set(CIR_IRQ_PIN_IOMUX_NAME, CIR_IRQ_PIN_IOMUX_VALUE);
- rk29_mux_api_set(GPIO5A7_HSADCDATA2_NAME, GPIO5L_GPIO5A7);
- return 0;
-}
-
-static struct bu92747guw_platform_data bu92747guw_pdata = {
- .intr_pin = BU92747_CIR_IRQ_PIN,
- .iomux_init = cir_iomux_init,
- .iomux_deinit = NULL,
- .cir_pwr_ctl = bu92747guw_power_ctl,
-};
-#endif
-#ifdef CONFIG_RK29_NEWTON
-struct rk29_newton_data rk29_newton_info = {
-};
-struct platform_device rk29_device_newton = {
- .name = "rk29_newton",
- .id = -1,
- .dev = {
- .platform_data = &rk29_newton_info,
- }
- };
-#endif
-#if defined (CONFIG_TOUCHSCREEN_FT5406)
-#define TOUCH_RESET_PIN RK29_PIN6_PC3
-#define TOUCH_INT_PIN RK29_PIN0_PA2
-int ft5406_init_platform_hw(void)
-{
- printk("ft5406_init_platform_hw\n");
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("ft5406_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("ift5406_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- mdelay(10);
- gpio_direction_input(TOUCH_INT_PIN);
- mdelay(10);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- msleep(300);
- return 0;
-}
-
-void ft5406_exit_platform_hw(void)
-{
- printk("ft5406_exit_platform_hw\n");
- gpio_free(TOUCH_RESET_PIN);
- gpio_free(TOUCH_INT_PIN);
-}
-
-int ft5406_platform_sleep(void)
-{
- printk("ft5406_platform_sleep\n");
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- return 0;
-}
-
-int ft5406_platform_wakeup(void)
-{
- printk("ft5406_platform_wakeup\n");
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- msleep(300);
- return 0;
-}
-
-struct ft5406_platform_data ft5406_info = {
-
- .init_platform_hw= ft5406_init_platform_hw,
- .exit_platform_hw= ft5406_exit_platform_hw,
- .platform_sleep = ft5406_platform_sleep,
- .platform_wakeup = ft5406_platform_wakeup,
-
-};
-#endif
-
-#if defined(CONFIG_TOUCHSCREEN_GT819)
-#define TOUCH_RESET_PIN RK29_PIN6_PC3
-#define TOUCH_INT_PIN RK29_PIN0_PA2
-int gt819_init_platform_hw(void)
-{
- printk("gt819_init_platform_hw\n");
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("gt819_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("gt819_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- mdelay(10);
-// gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
-// mdelay(10);
-// gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- gpio_direction_input(TOUCH_INT_PIN);
-// mdelay(10);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- msleep(300);
- return 0;
-}
-
-
-void gt819_exit_platform_hw(void)
-{
- printk("gt819_exit_platform_hw\n");
- gpio_free(TOUCH_RESET_PIN);
- gpio_free(TOUCH_INT_PIN);
-}
-
-int gt819_platform_sleep(void)
-{
- printk("gt819_platform_sleep\n");
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- return 0;
-}
-
-int gt819_platform_wakeup(void)
-{
- printk("gt819_platform_wakeup\n");
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- //msleep(5);
- //gpio_set_value(TOUCH_INT_PIN, GPIO_LOW);
- //msleep(20);
- //gpio_set_value(TOUCH_INT_PIN, GPIO_HIGH);
- return 0;
-}
-struct goodix_platform_data goodix_info = {
-
- .init_platform_hw= gt819_init_platform_hw,
- .exit_platform_hw= gt819_exit_platform_hw,
- .platform_sleep = gt819_platform_sleep,
- .platform_wakeup = gt819_platform_wakeup,
-
-};
-#endif
-
-/*goodix touch*/
-#if defined(CONFIG_TOUCHSCREEN_GT8XX)
-#define TOUCH_RESET_PIN RK29_PIN6_PC3
-#define TOUCH_PWR_PIN RK29_PIN5_PA1
-int goodix_init_platform_hw(void)
-{
- int ret;
- printk("goodix_init_platform_hw\n");
- ret = gpio_request(TOUCH_PWR_PIN, "goodix power pin");
- if(ret != 0){
- gpio_free(TOUCH_PWR_PIN);
- printk("goodix power error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_PWR_PIN, 0);
- gpio_set_value(TOUCH_PWR_PIN,GPIO_LOW);
- msleep(100);
- ret = gpio_request(TOUCH_RESET_PIN, "goodix reset pin");
- if(ret != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("goodix gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- msleep(10);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- msleep(500);
- return 0;
-}
-
-struct goodix_platform_data goodix_info = {
- .model= 8105,
- .irq_pin = RK29_PIN0_PA2,
- .rest_pin = TOUCH_RESET_PIN,
- .init_platform_hw = goodix_init_platform_hw,
-};
-#endif
-
-#if defined (CONFIG_SND_SOC_CS42L52)
-
-int cs42l52_init_platform_hw()
-{
- printk("cs42l52_init_platform_hw\n");
- if(gpio_request(RK29_PIN6_PB6,NULL) != 0){
- gpio_free(RK29_PIN6_PB6);
- printk("cs42l52_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(RK29_PIN6_PB6, 0);
- gpio_set_value(RK29_PIN6_PB6,GPIO_HIGH);
- return 0;
-}
-struct cs42l52_platform_data cs42l52_info = {
-
- .init_platform_hw= cs42l52_init_platform_hw,
-
-};
-#endif
-#if defined (CONFIG_BATTERY_BQ27541)
-#define DC_CHECK_PIN RK29_PIN4_PA1
-#define LI_LION_BAT_NUM 1
-#define CHG_OK RK29_PIN4_PA3
-#define BAT_LOW RK29_PIN4_PA2
-
-static int bq27541_init_dc_check_pin(void){
- if(gpio_request(DC_CHECK_PIN,"dc_check") != 0){
- gpio_free(DC_CHECK_PIN);
- printk("bq27541 init dc check pin request error\n");
- return -EIO;
- }
- gpio_direction_input(DC_CHECK_PIN);
- return 0;
-}
-
-struct bq27541_platform_data bq27541_info = {
- .init_dc_check_pin = bq27541_init_dc_check_pin,
- .dc_check_pin = DC_CHECK_PIN,
- .bat_num = LI_LION_BAT_NUM,
- .chgok_check_pin = CHG_OK,
- .bat_check_pin = BAT_LOW,
-};
-#endif
-static struct android_pmem_platform_data android_pmem_pdata = {
- .name = "pmem",
- .start = PMEM_UI_BASE,
- .size = PMEM_UI_SIZE,
- .no_allocator = 1,
- .cached = 1,
-};
-
-static struct platform_device android_pmem_device = {
- .name = "android_pmem",
- .id = 0,
- .dev = {
- .platform_data = &android_pmem_pdata,
- },
-};
-
-
-static struct vpu_mem_platform_data vpu_mem_pdata = {
- .name = "vpu_mem",
- .start = PMEM_VPU_BASE,
- .size = PMEM_VPU_SIZE,
- .cached = 1,
-};
-
-static struct platform_device rk29_vpu_mem_device = {
- .name = "vpu_mem",
- .id = 2,
- .dev = {
- .platform_data = &vpu_mem_pdata,
- },
-};
-
-#if PMEM_SKYPE_SIZE > 0
-static struct android_pmem_platform_data android_pmem_skype_pdata = {
- .name = "pmem_skype",
- .start = PMEM_SKYPE_BASE,
- .size = PMEM_SKYPE_SIZE,
- .no_allocator = 0,
- .cached = 0,
-};
-
-static struct platform_device android_pmem_skype_device = {
- .name = "android_pmem",
- .id = 3,
- .dev = {
- .platform_data = &android_pmem_skype_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_ION
-static struct ion_platform_data rk29_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = 0,
- .name = "ui",
- .base = PMEM_UI_BASE,
- .size = PMEM_UI_SIZE,
- }
- },
-};
-
-static struct platform_device rk29_ion_device = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk29_ion_pdata,
- },
-};
-#endif
-#ifdef CONFIG_VIDEO_RK29XX_VOUT
-static struct platform_device rk29_v4l2_output_devce = {
- .name = "rk29_vout",
-};
-#endif
-/*HANNSTAR_P1003 touch*/
-#if defined (CONFIG_HANNSTAR_P1003)
-#define TOUCH_RESET_PIN RK29_PIN6_PC3
-#define TOUCH_INT_PIN RK29_PIN0_PA2
-
-int p1003_init_platform_hw(void)
-{
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_pull_updown(TOUCH_INT_PIN, 1);
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
-
- return 0;
-}
-
-
-struct p1003_platform_data p1003_info = {
- .model= 1003,
- .init_platform_hw= p1003_init_platform_hw,
-
-};
-#endif
-#if defined (CONFIG_EETI_EGALAX)
-#define TOUCH_RESET_PIN RK29_PIN6_PC3
-#define TOUCH_INT_PIN RK29_PIN0_PA2
-
-static int EETI_EGALAX_init_platform_hw(void)
-{
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_pull_updown(TOUCH_INT_PIN, 1);
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
-
- return 0;
-}
-
-
-static struct eeti_egalax_platform_data eeti_egalax_info = {
- .model= 1003,
- .init_platform_hw= EETI_EGALAX_init_platform_hw,
- .standby_pin = TOUCH_SCREEN_STANDBY_PIN,
- .standby_value = TOUCH_SCREEN_STANDBY_VALUE,
- .disp_on_pin = TOUCH_SCREEN_DISPLAY_PIN,
- .disp_on_value = TOUCH_SCREEN_DISPLAY_VALUE,
-};
-#endif
-
-#ifdef CONFIG_GS_KXTF9
-#include <linux/kxtf9.h>
-#define KXTF9_DEVICE_MAP 1
-#define KXTF9_MAP_X (KXTF9_DEVICE_MAP-1)%2
-#define KXTF9_MAP_Y KXTF9_DEVICE_MAP%2
-#define KXTF9_NEG_X (KXTF9_DEVICE_MAP/2)%2
-#define KXTF9_NEG_Y (KXTF9_DEVICE_MAP+1)/4
-#define KXTF9_NEG_Z (KXTF9_DEVICE_MAP-1)/4
-struct kxtf9_platform_data kxtf9_pdata = {
- .min_interval = 1,
- .poll_interval = 20,
- .g_range = KXTF9_G_2G,
- .axis_map_x = KXTF9_MAP_X,
- .axis_map_y = KXTF9_MAP_Y,
- .axis_map_z = 2,
- .negate_x = KXTF9_NEG_X,
- .negate_y = KXTF9_NEG_Y,
- .negate_z = KXTF9_NEG_Z,
- //.ctrl_regc_init = KXTF9_G_2G | ODR50F,
- //.ctrl_regb_init = ENABLE,
-};
-#endif /* CONFIG_GS_KXTF9 */
-
-
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN RK29_PIN0_PA3
-static int mma8452_init_platform_hw(void)
-{
-
- if(gpio_request(MMA8452_INT_PIN,NULL) != 0){
- gpio_free(MMA8452_INT_PIN);
- printk("mma8452_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_pull_updown(MMA8452_INT_PIN, 1);
- return 0;
-}
-
-
-static struct gsensor_platform_data mma8452_info = {
- .model= 8452,
- .swap_xyz= 1,
- .swap_xy=0,
- .orientation ={1,0,0,0,0,-1,0,-1,0},
- .init_platform_hw= mma8452_init_platform_hw,
-
-};
-#endif
-/*mpu3050*/
-#if defined (CONFIG_MPU_SENSORS_MPU3050)
-static struct mpu_platform_data mpu3050_data = {
- .int_config = 0x10,
- .orientation = { 1, 0, 0,0, 1, 0, 0, 0, 1 },
-};
-#endif
-
-/* accel */
-#if defined (CONFIG_MPU_SENSORS_KXTF9)
-static struct ext_slave_platform_data inv_mpu_kxtf9_data = {
- .bus = EXT_SLAVE_BUS_SECONDARY,
- .adapt_num = 0,
- .orientation = {1, 0, 0, 0, 1, 0, 0, 0, 1},
-};
-#endif
-
-/* compass */
-#if defined (CONFIG_MPU_SENSORS_AK8975)
-static struct ext_slave_platform_data inv_mpu_ak8975_data = {
- .bus = EXT_SLAVE_BUS_PRIMARY,
- .adapt_num = 0,
- .orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
-};
-#endif
-
-#if defined (CONFIG_BATTERY_BQ27510)
-#define DC_CHECK_PIN RK29_PIN4_PA1
-#define LI_LION_BAT_NUM 2
-static int bq27510_init_dc_check_pin(void){
- if(gpio_request(DC_CHECK_PIN,"dc_check") != 0){
- gpio_free(DC_CHECK_PIN);
- printk("bq27510 init dc check pin request error\n");
- return -EIO;
- }
- gpio_direction_input(DC_CHECK_PIN);
- return 0;
-}
-
-struct bq27510_platform_data bq27510_info = {
- .init_dc_check_pin = bq27510_init_dc_check_pin,
- .dc_check_pin = DC_CHECK_PIN,
- .bat_num = LI_LION_BAT_NUM,
-};
-#endif
-
-#ifdef CONFIG_BATTERY_RK29_ADC
-static struct rk29_adc_battery_platform_data rk29_adc_battery_platdata = {
- .dc_det_pin = RK29_PIN4_PA1,
- .batt_low_pin = RK29_PIN4_PA2,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = RK29_PIN4_PA3,
-
- .dc_det_level = GPIO_LOW,
- .charge_ok_level = GPIO_HIGH,
-};
-
-static struct platform_device rk29_adc_device_battery = {
- .name = "rk2918-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk29_adc_battery_platdata,
- },
-};
-#endif
-
-/*************************************PMU ACT8891****************************************/
-
-#if defined (CONFIG_REGULATOR_ACT8891)
- /*dcdc mode*/
-/*act8891 in REGULATOR_MODE_STANDBY mode is said DCDC is in PMF mode is can save power,when in REGULATOR_MODE_NORMAL
-mode is said DCDC is in PWM mode , General default is in REGULATOR_MODE_STANDBY mode*/
- /*ldo mode */
-/*act8891 in REGULATOR_MODE_STANDBY mode is said LDO is in low power mode is can save power,when in REGULATOR_MODE_NORMAL
-mode is said DCDC is in nomal mode , General default is in REGULATOR_MODE_STANDBY mode*/
-/*set dcdc and ldo voltage by regulator_set_voltage()*/
-static struct act8891 *act8891;
-int act8891_set_init(struct act8891 *act8891)
-{
- int tmp = 0;
- struct regulator *act_ldo1,*act_ldo2,*act_ldo3,*act_ldo4;
- struct regulator *act_dcdc1,*act_dcdc2,*act_dcdc3;
-
- /*init ldo1*/
- act_ldo1 = regulator_get(NULL, "act_ldo1");
- regulator_enable(act_ldo1);
- regulator_set_voltage(act_ldo1,1800000,1800000);
- tmp = regulator_get_voltage(act_ldo1);
- regulator_set_mode(act_ldo1,REGULATOR_MODE_STANDBY);
- //regulator_set_mode(act_ldo1,REGULATOR_MODE_NORMAL);
- printk("***regulator_set_init: ldo1 vcc =%d\n",tmp);
- regulator_put(act_ldo1);
-
- /*init ldo2*/
- act_ldo2 = regulator_get(NULL, "act_ldo2");
- regulator_enable(act_ldo2);
- regulator_set_voltage(act_ldo2,1200000,1200000);
- tmp = regulator_get_voltage(act_ldo2);
- regulator_set_mode(act_ldo2,REGULATOR_MODE_STANDBY);
- //regulator_set_mode(act_ldo2,REGULATOR_MODE_NORMAL);
- printk("***regulator_set_init: ldo2 vcc =%d\n",tmp);
- regulator_put(act_ldo2);
-
- /*init ldo3*/
- act_ldo3 = regulator_get(NULL, "act_ldo3");
- regulator_enable(act_ldo3);
- regulator_set_voltage(act_ldo3,3300000,3300000);
- tmp = regulator_get_voltage(act_ldo3);
- regulator_set_mode(act_ldo3,REGULATOR_MODE_STANDBY);
- //regulator_set_mode(act_ldo3,REGULATOR_MODE_NORMAL);
- printk("***regulator_set_init: ldo3 vcc =%d\n",tmp);
- regulator_put(act_ldo3);
-
- /*init ldo4*/
- act_ldo4 = regulator_get(NULL, "act_ldo4");
- regulator_enable(act_ldo4);
- regulator_set_voltage(act_ldo4,2500000,2500000);
- tmp = regulator_get_voltage(act_ldo4);
- regulator_set_mode(act_ldo4,REGULATOR_MODE_STANDBY);
- //regulator_set_mode(act_ldo4,REGULATOR_MODE_NORMAL);
- printk("***regulator_set_init: ldo4 vcc =%d\n",tmp);
- regulator_put(act_ldo4);
-
- /*init dcdc1*/
- act_dcdc1 = regulator_get(NULL, "act_dcdc1");
- regulator_enable(act_dcdc1);
- regulator_set_voltage(act_dcdc1,3000000,3000000);
- tmp = regulator_get_voltage(act_dcdc1);
- regulator_set_mode(act_dcdc1,REGULATOR_MODE_STANDBY);
- //regulator_set_mode(act_dcdc1,REGULATOR_MODE_NORMAL);
- printk("***regulator_set_init: dcdc1 vcc =%d\n",tmp);
- regulator_put(act_dcdc1);
-
- /*init dcdc2*/
- act_dcdc2 = regulator_get(NULL, "act_dcdc2");
- regulator_enable(act_dcdc2);
- regulator_set_voltage(act_dcdc2,1500000,1500000);
- tmp = regulator_get_voltage(act_dcdc2);
- regulator_set_mode(act_dcdc2,REGULATOR_MODE_STANDBY);
- //regulator_set_mode(act_dcdc2,REGULATOR_MODE_NORMAL);
- printk("***regulator_set_init: dcdc2 vcc =%d\n",tmp);
- regulator_put(act_dcdc2);
-
- /*init dcdc3*/
- act_dcdc3 = regulator_get(NULL, "act_dcdc3");
- regulator_enable(act_dcdc3);
- regulator_set_voltage(act_dcdc3,1200000,1200000);
- tmp = regulator_get_voltage(act_dcdc3);
- regulator_set_mode(act_dcdc3,REGULATOR_MODE_STANDBY);
- //regulator_set_mode(act_dcdc3,REGULATOR_MODE_NORMAL);
- printk("***regulator_set_init: dcdc3 vcc =%d\n",tmp);
- regulator_put(act_dcdc3);
-
- return(0);
-}
-
-static struct regulator_consumer_supply act8891_ldo1_consumers[] = {
- {
- .supply = "act_ldo1",
- }
-};
-
-static struct regulator_init_data act8891_ldo1_data = {
- .constraints = {
- .name = "ACT_LDO1",
- .min_uV = 600000,
- .max_uV = 3900000,
- .apply_uV = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
- },
- .num_consumer_supplies = ARRAY_SIZE(act8891_ldo1_consumers),
- .consumer_supplies = act8891_ldo1_consumers,
-};
-
-/**/
-static struct regulator_consumer_supply act8891_ldo2_consumers[] = {
- {
- .supply = "act_ldo2",
- }
-};
-
-static struct regulator_init_data act8891_ldo2_data = {
- .constraints = {
- .name = "ACT_LDO2",
- .min_uV = 600000,
- .max_uV = 3900000,
- .apply_uV = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
- },
- .num_consumer_supplies = ARRAY_SIZE(act8891_ldo2_consumers),
- .consumer_supplies = act8891_ldo2_consumers,
-};
-
-/*ldo3 VCC_NAND WIFI/BT/FM_BCM4325*/
-static struct regulator_consumer_supply act8891_ldo3_consumers[] = {
- {
- .supply = "act_ldo3",
- }
-};
-
-static struct regulator_init_data act8891_ldo3_data = {
- .constraints = {
- .name = "ACT_LDO3",
- .min_uV = 600000,
- .max_uV = 3900000,
- .apply_uV = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
- },
- .num_consumer_supplies = ARRAY_SIZE(act8891_ldo3_consumers),
- .consumer_supplies = act8891_ldo3_consumers,
-};
-
-/*ldo4 VCCA CODEC_WM8994*/
-static struct regulator_consumer_supply act8891_ldo4_consumers[] = {
- {
- .supply = "act_ldo4",
- }
-};
-
-static struct regulator_init_data act8891_ldo4_data = {
- .constraints = {
- .name = "ACT_LDO4",
- .min_uV = 600000,
- .max_uV = 3900000,
- .apply_uV = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
- },
- .num_consumer_supplies = ARRAY_SIZE(act8891_ldo4_consumers),
- .consumer_supplies = act8891_ldo4_consumers,
-};
-/*buck1 vcc Core*/
-static struct regulator_consumer_supply act8891_dcdc1_consumers[] = {
- {
- .supply = "act_dcdc1",
- }
-};
-
-static struct regulator_init_data act8891_dcdc1_data = {
- .constraints = {
- .name = "ACT_DCDC1",
- .min_uV = 600000,
- .max_uV = 3900000,
- .apply_uV = 1,
- //.always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
- },
- .num_consumer_supplies = ARRAY_SIZE(act8891_dcdc1_consumers),
- .consumer_supplies = act8891_dcdc1_consumers
-};
-
-/*buck2 VDDDR MobileDDR VCC*/
-static struct regulator_consumer_supply act8891_dcdc2_consumers[] = {
- {
- .supply = "act_dcdc2",
- }
-};
-
-static struct regulator_init_data act8891_dcdc2_data = {
- .constraints = {
- .name = "ACT_DCDC2",
- .min_uV = 600000,
- .max_uV = 3900000,
- .apply_uV = 1,
- //.always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
- },
- .num_consumer_supplies = ARRAY_SIZE(act8891_dcdc2_consumers),
- .consumer_supplies = act8891_dcdc2_consumers
-};
-
-/*buck3 vdd Core*/
-static struct regulator_consumer_supply act8891_dcdc3_consumers[] = {
- {
- .supply = "act_dcdc3",
- }
-};
-
-static struct regulator_init_data act8891_dcdc3_data = {
- .constraints = {
- .name = "ACT_DCDC3",
- .min_uV = 600000,
- .max_uV = 3900000,
- .apply_uV = 1,
- //.always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
- },
- .num_consumer_supplies = ARRAY_SIZE(act8891_dcdc3_consumers),
- .consumer_supplies = act8891_dcdc3_consumers
-};
-
-struct act8891_regulator_subdev act8891_regulator_subdev_id[] = {
- {
- .id=0,
- .initdata=&act8891_ldo1_data,
- },
-
- {
- .id=1,
- .initdata=&act8891_ldo2_data,
- },
-
- {
- .id=2,
- .initdata=&act8891_ldo3_data,
- },
-
- {
- .id=3,
- .initdata=&act8891_ldo4_data,
- },
-
- {
- .id=4,
- .initdata=&act8891_dcdc1_data,
- },
-
- {
- .id=5,
- .initdata=&act8891_dcdc2_data,
- },
- {
- .id=6,
- .initdata=&act8891_dcdc3_data,
- },
-
-};
-
-struct act8891_platform_data act8891_data={
- .set_init=act8891_set_init,
- .num_regulators=7,
- .regulators=act8891_regulator_subdev_id,
-
-};
-#endif
-
-/*****************************************************************************************
- * i2c devices
- * author: kfx@rock-chips.com
-*****************************************************************************************/
-static int rk29_i2c0_io_init(void)
-{
-#ifdef CONFIG_RK29_I2C0_CONTROLLER
- rk29_mux_api_set(GPIO2B7_I2C0SCL_NAME, GPIO2L_I2C0_SCL);
- rk29_mux_api_set(GPIO2B6_I2C0SDA_NAME, GPIO2L_I2C0_SDA);
-#else
- rk29_mux_api_set(GPIO2B7_I2C0SCL_NAME, GPIO2L_GPIO2B7);
- rk29_mux_api_set(GPIO2B6_I2C0SDA_NAME, GPIO2L_GPIO2B6);
-#endif
- return 0;
-}
-
-static int rk29_i2c1_io_init(void)
-{
-#ifdef CONFIG_RK29_I2C1_CONTROLLER
- rk29_mux_api_set(GPIO1A7_I2C1SCL_NAME, GPIO1L_I2C1_SCL);
- rk29_mux_api_set(GPIO1A6_I2C1SDA_NAME, GPIO1L_I2C1_SDA);
-#else
- rk29_mux_api_set(GPIO1A7_I2C1SCL_NAME, GPIO1L_GPIO1A7);
- rk29_mux_api_set(GPIO1A6_I2C1SDA_NAME, GPIO1L_GPIO1A6);
-#endif
- return 0;
-}
-static int rk29_i2c2_io_init(void)
-{
-#ifdef CONFIG_RK29_I2C2_CONTROLLER
- rk29_mux_api_set(GPIO5D4_I2C2SCL_NAME, GPIO5H_I2C2_SCL);
- rk29_mux_api_set(GPIO5D3_I2C2SDA_NAME, GPIO5H_I2C2_SDA);
-#else
- rk29_mux_api_set(GPIO5D4_I2C2SCL_NAME, GPIO5H_GPIO5D4);
- rk29_mux_api_set(GPIO5D3_I2C2SDA_NAME, GPIO5H_GPIO5D3);
-#endif
- return 0;
-}
-
-static int rk29_i2c3_io_init(void)
-{
-#ifdef CONFIG_RK29_I2C3_CONTROLLER
- rk29_mux_api_set(GPIO2B5_UART3RTSN_I2C3SCL_NAME, GPIO2L_I2C3_SCL);
- rk29_mux_api_set(GPIO2B4_UART3CTSN_I2C3SDA_NAME, GPIO2L_I2C3_SDA);
-#else
- rk29_mux_api_set(GPIO2B5_UART3RTSN_I2C3SCL_NAME, GPIO2L_GPIO2B5);
- rk29_mux_api_set(GPIO2B4_UART3CTSN_I2C3SDA_NAME, GPIO2L_GPIO2B4);
-#endif
- return 0;
-}
-#ifdef CONFIG_RK29_I2C0_CONTROLLER
-struct rk29_i2c_platform_data default_i2c0_data = {
- .bus_num = 0,
- .flags = 0,
- .slave_addr = 0xff,
- .scl_rate = 400*1000,
- .mode = I2C_MODE_IRQ,
- .io_init = rk29_i2c0_io_init,
-};
-#else
-struct i2c_gpio_platform_data default_i2c0_data = {
- .sda_pin = RK29_PIN2_PB6,
- .scl_pin = RK29_PIN2_PB7,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(200),
- .bus_num = 0,
- .io_init = rk29_i2c0_io_init,
-};
-#endif
-#ifdef CONFIG_RK29_I2C1_CONTROLLER
-struct rk29_i2c_platform_data default_i2c1_data = {
- .bus_num = 1,
- .flags = 0,
- .slave_addr = 0xff,
- .scl_rate = 400*1000,
- .mode = I2C_MODE_IRQ,
- .io_init = rk29_i2c1_io_init,
-};
-#else
-struct i2c_gpio_platform_data default_i2c1_data = {
- .sda_pin = RK29_PIN1_PA6,
- .scl_pin = RK29_PIN1_PA7,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(200),
- .bus_num = 1,
- .io_init = rk29_i2c1_io_init,
-};
-#endif
-#ifdef CONFIG_RK29_I2C2_CONTROLLER
-struct rk29_i2c_platform_data default_i2c2_data = {
- .bus_num = 2,
- .flags = 0,
- .slave_addr = 0xff,
- .scl_rate = 400*1000,
- .mode = I2C_MODE_IRQ,
- .io_init = rk29_i2c2_io_init,
-};
-#else
-struct i2c_gpio_platform_data default_i2c2_data = {
- .sda_pin = RK29_PIN5_PD3,
- .scl_pin = RK29_PIN5_PD4,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(200),
- .bus_num = 2,
- .io_init = rk29_i2c2_io_init,
-};
-#endif
-#ifdef CONFIG_RK29_I2C3_CONTROLLER
-struct rk29_i2c_platform_data default_i2c3_data = {
- .bus_num = 3,
- .flags = 0,
- .slave_addr = 0xff,
- .scl_rate = 400*1000,
- .mode = I2C_MODE_IRQ,
- .io_init = rk29_i2c3_io_init,
-};
-#else
-struct i2c_gpio_platform_data default_i2c3_data = {
- .sda_pin = RK29_PIN5_PB5,
- .scl_pin = RK29_PIN5_PB4,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(200),
- .bus_num = 3,
- .io_init = rk29_i2c3_io_init,
-};
-#endif
-#ifdef CONFIG_I2C0_RK29
-static struct i2c_board_info __initdata board_i2c0_devices[] = {
-#if defined (CONFIG_RK1000_CONTROL)
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RT5621)
- {
- .type = "rt5621",
- .addr = 0x1a,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RT5631)
- {
- .type = "rt5631",
- .addr = 0x1a,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_WM8988)
- {
- .type = "wm8988",
- .addr = 0x1A,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_WM8900)
- {
- .type = "wm8900",
- .addr = 0x1A,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_BATTERY_STC3100)
- {
- .type = "stc3100",
- .addr = 0x70,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_BATTERY_BQ27510)
- {
- .type = "bq27510",
- .addr = 0x55,
- .flags = 0,
- .platform_data = &bq27510_info,
- },
-#endif
-#if defined (CONFIG_RTC_HYM8563)
- {
- .type = "rtc_hym8563",
- .addr = 0x51,
- .flags = 0,
- .irq = RK29_PIN0_PA1,
- },
-#endif
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1c,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8973)
- {
- .type = "ak8973",
- .addr = 0x1d,
- .flags = 0,
- .irq = RK29_PIN0_PA4,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK29_PIN0_PA4,
- },
-#endif
-#if defined (CONFIG_MPU_SENSORS_MPU3050)
- {
- .type = "mpu3050",
- .addr = 0x68,
- .flags = 0,
- .irq = RK29_PIN4_PC4,
- .platform_data = &mpu3050_data,
- },
-#endif
-#if defined (CONFIG_MPU_SENSORS_KXTF9)
- {
- .type = "kxtf9",
- .addr = 0x0f,
- .flags = 0,
- //.irq = RK29_PIN6_PC4,
- .platform_data = &inv_mpu_kxtf9_data,
- },
-#endif
-#if defined (CONFIG_MPU_SENSORS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- //.irq = RK29_PIN6_PC5,
- .platform_data = &inv_mpu_ak8975_data,
- },
-#endif
-
-#if defined (CONFIG_SND_SOC_CS42L52)
- {
- .type = "cs42l52",
- .addr = 0x4A,
- .flags = 0,
- .platform_data = &cs42l52_info,
- },
-#endif
-#if defined (CONFIG_RTC_M41T66)
- {
- .type = "rtc-M41T66",
- .addr = 0x68,
- .flags = 0,
- .irq = RK29_PIN0_PA1,
- },
-#endif
-};
-#endif
-#if defined (CONFIG_ANX7150)
-struct hdmi_platform_data anx7150_data = {
- //.io_init = anx7150_io_init,
-};
-#endif
-#ifdef CONFIG_I2C1_RK29
-static struct i2c_board_info __initdata board_i2c1_devices[] = {
-#if defined (CONFIG_RK1000_CONTROL1)
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_ANX7150)
- {
- .type = "anx7150",
- .addr = 0x39, //0x39, 0x3d
- .flags = 0,
- .irq = RK29_PIN1_PD7,
- .platform_data = &anx7150_data,
- },
-#endif
-#ifdef CONFIG_BU92747GUW_CIR
- {
- .type ="bu92747_cir",
- .addr = 0x77,
- .flags =0,
- .irq = BU92747_CIR_IRQ_PIN,
- .platform_data = &bu92747guw_pdata,
- },
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C2_RK29
-static struct i2c_board_info __initdata board_i2c2_devices[] = {
-#if defined (CONFIG_HANNSTAR_P1003)
- {
- .type = "p1003_touch",
- .addr = 0x04,
- .flags = 0, //I2C_M_NEED_DELAY
- .irq = RK29_PIN0_PA2,
- .platform_data = &p1003_info,
- //.udelay = 100
- },
-#endif
-#if defined (CONFIG_EETI_EGALAX)
- {
- .type = "egalax_i2c",
- .addr = 0x04,
- .flags = 0,
- .irq = RK29_PIN0_PA2,
- .platform_data = &eeti_egalax_info,
- },
-#endif
-#if defined (CONFIG_TOUCHSCREEN_GT8XX)
- {
- .type = "Goodix-TS",
- .addr = 0x55,
- .flags =0,
- .irq =RK29_PIN0_PA2,
- .platform_data = &goodix_info,
- },
-#endif
-#if defined (CONFIG_TOUCHSCREEN_FT5406)
- {
- .type ="ft5x0x_ts",
- .addr = 0x38, //0x70,
- .flags =0,
- .irq =RK29_PIN0_PA2, // support goodix tp detect, 20110706
- .platform_data = &ft5406_info,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK29
-static struct i2c_board_info __initdata board_i2c3_devices[] = {
-#if defined (CONFIG_BATTERY_BQ27541)
- {
- .type = "bq27541",
- .addr = 0x55,
- .flags = 0,
- .platform_data = &bq27541_info,
- },
-#endif
-#if defined (CONFIG_REGULATOR_ACT8891)
- {
- .type = "act8891",
- .addr = 0x5b,
- .flags = 0,
- .platform_data=&act8891_data,
- },
-#endif
-
-};
-#endif
-
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#define CONFIG_SENSOR_POWER_IOCTL_USR 0
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_RESET_IOCTL_USR
-static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
-static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-#include "../../../drivers/media/video/rk29_camera.c"
-#endif
-/*****************************************************************************************
- * backlight devices
- * author: nzy@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- /*
- GPIO1B5_PWM0_NAME, GPIO1L_PWM0
- GPIO5D2_PWM1_UART1SIRIN_NAME, GPIO5H_PWM1
- GPIO2A3_SDMMC0WRITEPRT_PWM2_NAME, GPIO2L_PWM2
- GPIO1A5_EMMCPWREN_PWM3_NAME, GPIO1L_PWM3
- */
-
-#define PWM_ID 0
-#define PWM_MUX_NAME GPIO1B5_PWM0_NAME
-#define PWM_MUX_MODE GPIO1L_PWM0
-#define PWM_MUX_MODE_GPIO GPIO1L_GPIO1B5
-#define PWM_GPIO RK29_PIN1_PB5
-#define PWM_EFFECT_VALUE 0
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-//#define BL_EN_MUX_NAME GPIOF34_UART3_SEL_NAME
-//#define BL_EN_MUX_MODE IOMUXB_GPIO1_B34
-
-#define BL_EN_PIN RK29_PIN6_PD0
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
-
- rk29_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
- #ifdef LCD_DISP_ON_PIN
- // rk29_mux_api_set(BL_EN_MUX_NAME, BL_EN_MUX_MODE);
-
- ret = gpio_request(BL_EN_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(BL_EN_PIN);
- }
-
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
- #endif
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0;
- #ifdef LCD_DISP_ON_PIN
- gpio_free(BL_EN_PIN);
- #endif
- rk29_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- gpio_free(PWM_GPIO);
- if (ret = gpio_request(PWM_GPIO, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- gpio_direction_output(PWM_GPIO, GPIO_HIGH);
- gpio_set_value(PWM_GPIO, GPIO_HIGH);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret = 0;
- rk29_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- if (gpio_request(PWM_GPIO, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- gpio_direction_output(PWM_GPIO, GPIO_LOW);
- #ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, !BL_EN_VALUE);
- #endif
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- gpio_free(PWM_GPIO);
- rk29_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
-
- #ifdef LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, 1);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
- #endif
- return 0;
-}
-
-struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
- .min_brightness = 30,
-};
-#endif
-/*****************************************************************************************
-* pwm voltage regulator devices
-******************************************************************************************/
-#if defined (CONFIG_RK29_PWM_REGULATOR)
-
-#define REGULATOR_PWM_ID 2
-#define REGULATOR_PWM_MUX_NAME GPIO2A3_SDMMC0WRITEPRT_PWM2_NAME
-#define REGULATOR_PWM_MUX_MODE GPIO2L_PWM2
-#define REGULATOR_PWM_MUX_MODE_GPIO GPIO2L_GPIO2A3
-#define REGULATOR_PWM_GPIO RK29_PIN2_PA3
-
-static struct regulator_consumer_supply pwm_consumers[] = {
- {
- .supply = "vcore",
- }
-};
-
-static struct regulator_init_data rk29_pwm_regulator_data = {
- .constraints = {
- .name = "PWM2",
- .min_uV = 950000,
- .max_uV = 1400000,
- .apply_uV = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_consumers),
- .consumer_supplies = pwm_consumers,
-};
-
-static struct pwm_platform_data rk29_regulator_pwm_platform_data = {
- .pwm_id = REGULATOR_PWM_ID,
- .pwm_gpio = REGULATOR_PWM_GPIO,
- //.pwm_iomux_name[] = REGULATOR_PWM_MUX_NAME;
- .pwm_iomux_name = REGULATOR_PWM_MUX_NAME,
- .pwm_iomux_pwm = REGULATOR_PWM_MUX_MODE,
- .pwm_iomux_gpio = REGULATOR_PWM_MUX_MODE_GPIO,
- .init_data = &rk29_pwm_regulator_data,
-};
-
-static struct platform_device rk29_device_pwm_regulator = {
- .name = "pwm-voltage-regulator",
- .id = -1,
- .dev = {
- .platform_data = &rk29_regulator_pwm_platform_data,
- },
-};
-
-#endif
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
-#define SDMMC0_WRITE_PROTECT_PIN RK29_PIN6_PB0 //According to your own project to set the value of write-protect-pin.
-#endif
-
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
-#define SDMMC1_WRITE_PROTECT_PIN RK29_PIN6_PB0 //According to your own project to set the value of write-protect-pin.
-#endif
-
-/*****************************************************************************************
- * SDMMC devices
-*****************************************************************************************/
-#if !defined(CONFIG_SDMMC_RK29_OLD)
-static void rk29_sdmmc_gpio_open(int device_id, int on)
-{
- switch(device_id)
- {
- case 0://mmc0
- {
- #ifdef CONFIG_SDMMC0_RK29
- if(on)
- {
- gpio_direction_output(RK29_PIN1_PD0,GPIO_HIGH);//set mmc0-clk to high
- gpio_direction_output(RK29_PIN1_PD1,GPIO_HIGH);//set mmc0-cmd to high.
- gpio_direction_output(RK29_PIN1_PD2,GPIO_HIGH);//set mmc0-data0 to high.
- gpio_direction_output(RK29_PIN1_PD3,GPIO_HIGH);//set mmc0-data1 to high.
- gpio_direction_output(RK29_PIN1_PD4,GPIO_HIGH);//set mmc0-data2 to high.
- gpio_direction_output(RK29_PIN1_PD5,GPIO_HIGH);//set mmc0-data3 to high.
-
- mdelay(30);
- }
- else
- {
- rk29_mux_api_set(GPIO1D0_SDMMC0CLKOUT_NAME, GPIO1H_GPIO1_D0);
- gpio_request(RK29_PIN1_PD0, "mmc0-clk");
- gpio_direction_output(RK29_PIN1_PD0,GPIO_LOW);//set mmc0-clk to low.
-
- rk29_mux_api_set(GPIO1D1_SDMMC0CMD_NAME, GPIO1H_GPIO1_D1);
- gpio_request(RK29_PIN1_PD1, "mmc0-cmd");
- gpio_direction_output(RK29_PIN1_PD1,GPIO_LOW);//set mmc0-cmd to low.
-
- rk29_mux_api_set(GPIO1D2_SDMMC0DATA0_NAME, GPIO1H_GPIO1D2);
- gpio_request(RK29_PIN1_PD2, "mmc0-data0");
- gpio_direction_output(RK29_PIN1_PD2,GPIO_LOW);//set mmc0-data0 to low.
-
- rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_GPIO1D3);
- gpio_request(RK29_PIN1_PD3, "mmc0-data1");
- gpio_direction_output(RK29_PIN1_PD3,GPIO_LOW);//set mmc0-data1 to low.
-
- rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_GPIO1D4);
- gpio_request(RK29_PIN1_PD4, "mmc0-data2");
- gpio_direction_output(RK29_PIN1_PD4,GPIO_LOW);//set mmc0-data2 to low.
-
- rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_GPIO1D5);
- gpio_request(RK29_PIN1_PD5, "mmc0-data3");
- gpio_direction_output(RK29_PIN1_PD5,GPIO_LOW);//set mmc0-data3 to low.
-
- mdelay(30);
- }
- #endif
- }
- break;
-
- case 1://mmc1
- {
- #ifdef CONFIG_SDMMC1_RK29
- if(on)
- {
- gpio_direction_output(RK29_PIN1_PC7,GPIO_HIGH);//set mmc1-clk to high
- gpio_direction_output(RK29_PIN1_PC2,GPIO_HIGH);//set mmc1-cmd to high.
- gpio_direction_output(RK29_PIN1_PC3,GPIO_HIGH);//set mmc1-data0 to high.
- gpio_direction_output(RK29_PIN1_PC4,GPIO_HIGH);//set mmc1-data1 to high.
- gpio_direction_output(RK29_PIN1_PC5,GPIO_HIGH);//set mmc1-data2 to high.
- gpio_direction_output(RK29_PIN1_PC6,GPIO_HIGH);//set mmc1-data3 to high.
- mdelay(100);
- }
- else
- {
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_GPIO1C7);
- gpio_request(RK29_PIN1_PC7, "mmc1-clk");
- gpio_direction_output(RK29_PIN1_PC7,GPIO_LOW);//set mmc1-clk to low.
-
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_GPIO1C2);
- gpio_request(RK29_PIN1_PC2, "mmc1-cmd");
- gpio_direction_output(RK29_PIN1_PC2,GPIO_LOW);//set mmc1-cmd to low.
-
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_GPIO1C3);
- gpio_request(RK29_PIN1_PC3, "mmc1-data0");
- gpio_direction_output(RK29_PIN1_PC3,GPIO_LOW);//set mmc1-data0 to low.
-
- mdelay(100);
- }
- #endif
- }
- break;
-
- case 2: //mmc2
- break;
-
- default:
- break;
- }
-}
-
-static void rk29_sdmmc_set_iomux_mmc0(unsigned int bus_width)
-{
- switch (bus_width)
- {
-
- case 1://SDMMC_CTYPE_4BIT:
- {
- rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_SDMMC0_DATA1);
- rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_SDMMC0_DATA2);
- rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_SDMMC0_DATA3);
- }
- break;
-
- case 0x10000://SDMMC_CTYPE_8BIT:
- break;
- case 0xFFFF: //gpio_reset
- {
- rk29_mux_api_set(GPIO5D5_SDMMC0PWREN_NAME, GPIO5H_GPIO5D5);
- gpio_request(RK29_PIN5_PD5,"sdmmc-power");
- gpio_direction_output(RK29_PIN5_PD5,GPIO_HIGH); //power-off
-
- rk29_sdmmc_gpio_open(0, 0);
-
- gpio_direction_output(RK29_PIN5_PD5,GPIO_LOW); //power-on
-
- rk29_sdmmc_gpio_open(0, 1);
- }
- break;
-
- default: //case 0://SDMMC_CTYPE_1BIT:
- {
- rk29_mux_api_set(GPIO1D1_SDMMC0CMD_NAME, GPIO1H_SDMMC0_CMD);
- rk29_mux_api_set(GPIO1D0_SDMMC0CLKOUT_NAME, GPIO1H_SDMMC0_CLKOUT);
- rk29_mux_api_set(GPIO1D2_SDMMC0DATA0_NAME, GPIO1H_SDMMC0_DATA0);
-
- rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_GPIO1D3);
- gpio_request(RK29_PIN1_PD3, "mmc0-data1");
- gpio_direction_output(RK29_PIN1_PD3,GPIO_HIGH);
-
- rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_GPIO1D4);
- gpio_request(RK29_PIN1_PD4, "mmc0-data2");
- gpio_direction_output(RK29_PIN1_PD4,GPIO_HIGH);
-
- rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_GPIO1D5);
- gpio_request(RK29_PIN1_PD5, "mmc0-data3");
- gpio_direction_output(RK29_PIN1_PD5,GPIO_HIGH);
- }
- break;
- }
-}
-
-static void rk29_sdmmc_set_iomux_mmc1(unsigned int bus_width)
-{
-#if 0
- switch (bus_width)
- {
-
- case 1://SDMMC_CTYPE_4BIT:
- {
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);
- rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_SDMMC1_DATA1);
- rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_SDMMC1_DATA2);
- rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_SDMMC1_DATA3);
- }
- break;
-
- case 0x10000://SDMMC_CTYPE_8BIT:
- break;
- case 0xFFFF:
- {
- rk29_sdmmc_gpio_open(1, 0);
- rk29_sdmmc_gpio_open(1, 1);
- }
- break;
-
- default: //case 0://SDMMC_CTYPE_1BIT:
- {
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);
-
- rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_GPIO1C4);
- gpio_request(RK29_PIN1_PC4, "mmc1-data1");
- gpio_direction_output(RK29_PIN1_PC4,GPIO_HIGH);
-
- rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_GPIO1C5);
- gpio_request(RK29_PIN1_PC5, "mmc1-data2");
- gpio_direction_output(RK29_PIN1_PC5,GPIO_HIGH);
-
- rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_GPIO1C6);
- gpio_request(RK29_PIN1_PC6, "mmc1-data3");
- gpio_direction_output(RK29_PIN1_PC6,GPIO_HIGH);
-
- }
- break;
- }
-#else
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);
- rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_SDMMC1_DATA1);
- rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_SDMMC1_DATA2);
- rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_SDMMC1_DATA3);
-
-#endif
-}
-
-static void rk29_sdmmc_set_iomux_mmc2(unsigned int bus_width)
-{
- ;//
-}
-
-
-static void rk29_sdmmc_set_iomux(int device_id, unsigned int bus_width)
-{
- switch(device_id)
- {
- case 0:
- #ifdef CONFIG_SDMMC0_RK29
- rk29_sdmmc_set_iomux_mmc0(bus_width);
- #endif
- break;
- case 1:
- #ifdef CONFIG_SDMMC1_RK29
- rk29_sdmmc_set_iomux_mmc1(bus_width);
- #endif
- break;
- case 2:
- rk29_sdmmc_set_iomux_mmc2(bus_width);
- break;
- default:
- break;
- }
-}
-
-#endif
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
-static int rk29sdk_wifi_status(struct device *dev);
-static int rk29sdk_wifi_status_register(void (*callback)(int card_presend, void *dev_id), void *dev_id);
-#endif
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- rk29_mux_api_set(GPIO1D1_SDMMC0CMD_NAME, GPIO1H_SDMMC0_CMD);
- rk29_mux_api_set(GPIO1D0_SDMMC0CLKOUT_NAME, GPIO1H_SDMMC0_CLKOUT);
- rk29_mux_api_set(GPIO1D2_SDMMC0DATA0_NAME, GPIO1H_SDMMC0_DATA0);
- rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_SDMMC0_DATA1);
- rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_SDMMC0_DATA2);
- rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_SDMMC0_DATA3);
-
- rk29_mux_api_set(GPIO2A2_SDMMC0DETECTN_NAME, GPIO2L_GPIO2A2);
-
- rk29_mux_api_set(GPIO5D5_SDMMC0PWREN_NAME, GPIO5H_GPIO5D5); ///GPIO5H_SDMMC0_PWR_EN); ///GPIO5H_GPIO5D5);
- gpio_request(RK29_PIN5_PD5,"sdmmc");
-#if 0
- gpio_set_value(RK29_PIN5_PD5,GPIO_HIGH);
- mdelay(100);
- gpio_set_value(RK29_PIN5_PD5,GPIO_LOW);
-#else
- gpio_direction_output(RK29_PIN5_PD5,GPIO_LOW);
-#endif
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- rk29_mux_api_set(GPIO2A2_SDMMC0DETECTN_NAME, GPIO2L_SDMMC0_DETECT_N);//Modifyed by xbw.
-
- #if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN,"sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
- #endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail = (MMC_VDD_25_26|MMC_VDD_26_27|MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30|
- MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33|
- MMC_VDD_33_34|MMC_VDD_34_35| MMC_VDD_35_36),
- .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
- .detect_irq = RK29_PIN2_PA2, // INVALID_GPIO
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
-#else
- .write_prt = INVALID_GPIO,
-#endif
-};
-#endif
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);
- rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_SDMMC1_DATA1);
- rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_SDMMC1_DATA2);
- rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_SDMMC1_DATA3);
- //rk29_mux_api_set(GPIO1C0_UART0CTSN_SDMMC1DETECTN_NAME, GPIO1H_SDMMC1_DETECT_N);
-
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN,"sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-
-
-#define RK29SDK_WIFI_SDIO_CARD_DETECT_N RK29_PIN1_PD6
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail = (MMC_VDD_25_26|MMC_VDD_26_27|MMC_VDD_27_28|MMC_VDD_28_29|
- MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32|
- MMC_VDD_32_33|MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_SDIO_IRQ|
- MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-#if 0
- .detect_irq = RK29SDK_WIFI_SDIO_CARD_DETECT_N,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
-#else
-//for wifi develop board
- .detect_irq = INVALID_GPIO,
- .enable_sd_wakeup = 0,
-#endif
-
-};
-#endif ////endif--#ifdef CONFIG_SDMMC1_RK29
-
-
-int rk29sdk_wifi_power_state = 0;
-int rk29sdk_bt_power_state = 0;
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
-#define RK29SDK_WIFI_BT_GPIO_POWER_N RK29_PIN5_PD6
-#define RK29SDK_WIFI_GPIO_RESET_N RK29_PIN6_PC0
-#define RK29SDK_BT_GPIO_RESET_N RK29_PIN6_PC4
-
-static int rk29sdk_wifi_cd = 0; /* wifi virtual 'card detect' status */
-static void (*wifi_status_cb)(int card_present, void *dev_id);
-static void *wifi_status_cb_devid;
-
-static int rk29sdk_wifi_status(struct device *dev)
-{
- return rk29sdk_wifi_cd;
-}
-
-static int rk29sdk_wifi_status_register(void (*callback)(int card_present, void *dev_id), void *dev_id)
-{
- if(wifi_status_cb)
- return -EAGAIN;
- wifi_status_cb = callback;
- wifi_status_cb_devid = dev_id;
- return 0;
-}
-
-static int rk29sdk_wifi_bt_gpio_control_init(void)
-{
- if (gpio_request(RK29SDK_WIFI_BT_GPIO_POWER_N, "wifi_bt_power")) {
- pr_info("%s: request wifi_bt power gpio failed\n", __func__);
- return -1;
- }
-
- if (gpio_request(RK29SDK_WIFI_GPIO_RESET_N, "wifi reset")) {
- pr_info("%s: request wifi reset gpio failed\n", __func__);
- gpio_free(RK29SDK_WIFI_BT_GPIO_POWER_N);
- return -1;
- }
-
- if (gpio_request(RK29SDK_BT_GPIO_RESET_N, "bt reset")) {
- pr_info("%s: request bt reset gpio failed\n", __func__);
- gpio_free(RK29SDK_WIFI_GPIO_RESET_N);
- return -1;
- }
-
- gpio_direction_output(RK29SDK_WIFI_BT_GPIO_POWER_N, GPIO_LOW);
- gpio_direction_output(RK29SDK_WIFI_GPIO_RESET_N, GPIO_LOW);
- gpio_direction_output(RK29SDK_BT_GPIO_RESET_N, GPIO_LOW);
-
- #if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
-
- rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_GPIO1C4);
- gpio_request(RK29_PIN1_PC4, "mmc1-data1");
- gpio_direction_output(RK29_PIN1_PC4,GPIO_LOW);//set mmc1-data1 to low.
-
- rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_GPIO1C5);
- gpio_request(RK29_PIN1_PC5, "mmc1-data2");
- gpio_direction_output(RK29_PIN1_PC5,GPIO_LOW);//set mmc1-data2 to low.
-
- rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_GPIO1C6);
- gpio_request(RK29_PIN1_PC6, "mmc1-data3");
- gpio_direction_output(RK29_PIN1_PC6,GPIO_LOW);//set mmc1-data3 to low.
-
- rk29_sdmmc_gpio_open(1, 0); //added by xbw at 2011-10-13
- #endif
- pr_info("%s: init finished\n",__func__);
-
- return 0;
-}
-
-static int rk29sdk_wifi_power(int on)
-{
- pr_info("%s: %d\n", __func__, on);
- if (on){
- gpio_set_value(RK29SDK_WIFI_BT_GPIO_POWER_N, GPIO_HIGH);
-
- #if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
- rk29_sdmmc_gpio_open(1, 1); //added by xbw at 2011-10-13
- #endif
-
- gpio_set_value(RK29SDK_WIFI_GPIO_RESET_N, GPIO_HIGH);
- mdelay(100);
- pr_info("wifi turn on power\n");
- }else{
- if (!rk29sdk_bt_power_state){
- gpio_set_value(RK29SDK_WIFI_BT_GPIO_POWER_N, GPIO_LOW);
-
- #if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
- rk29_sdmmc_gpio_open(1, 0); //added by xbw at 2011-10-13
- #endif
-
- mdelay(100);
- pr_info("wifi shut off power\n");
- }else
- {
- pr_info("wifi shouldn't shut off power, bt is using it!\n");
- }
- gpio_set_value(RK29SDK_WIFI_GPIO_RESET_N, GPIO_LOW);
-
- }
-
- rk29sdk_wifi_power_state = on;
- return 0;
-}
-
-static int rk29sdk_wifi_reset_state;
-static int rk29sdk_wifi_reset(int on)
-{
- pr_info("%s: %d\n", __func__, on);
- gpio_set_value(RK29SDK_WIFI_GPIO_RESET_N, on);
- mdelay(100);
- rk29sdk_wifi_reset_state = on;
- return 0;
-}
-
-int rk29sdk_wifi_set_carddetect(int val)
-{
- pr_info("%s:%d\n", __func__, val);
- rk29sdk_wifi_cd = val;
- if (wifi_status_cb){
- wifi_status_cb(val, wifi_status_cb_devid);
- }else {
- pr_warning("%s, nobody to notify\n", __func__);
- }
- return 0;
-}
-EXPORT_SYMBOL(rk29sdk_wifi_set_carddetect);
-
-static struct wifi_mem_prealloc wifi_mem_array[PREALLOC_WLAN_SEC_NUM] = {
- {NULL, (WLAN_SECTION_SIZE_0 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_1 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_2 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_3 + PREALLOC_WLAN_SECTION_HEADER)}
-};
-
-static void *rk29sdk_mem_prealloc(int section, unsigned long size)
-{
- if (section == PREALLOC_WLAN_SEC_NUM)
- return wlan_static_skb;
-
- if ((section < 0) || (section > PREALLOC_WLAN_SEC_NUM))
- return NULL;
-
- if (wifi_mem_array[section].size < size)
- return NULL;
-
- return wifi_mem_array[section].mem_ptr;
-}
-
-int __init rk29sdk_init_wifi_mem(void)
-{
- int i;
- int j;
-
- for (i = 0 ; i < WLAN_SKB_BUF_NUM ; i++) {
- wlan_static_skb[i] = dev_alloc_skb(
- ((i < (WLAN_SKB_BUF_NUM / 2)) ? 4096 : 8192));
-
- if (!wlan_static_skb[i])
- goto err_skb_alloc;
- }
-
- for (i = 0 ; i < PREALLOC_WLAN_SEC_NUM ; i++) {
- wifi_mem_array[i].mem_ptr =
- kmalloc(wifi_mem_array[i].size, GFP_KERNEL);
-
- if (!wifi_mem_array[i].mem_ptr)
- goto err_mem_alloc;
- }
- return 0;
-
-err_mem_alloc:
- pr_err("Failed to mem_alloc for WLAN\n");
- for (j = 0 ; j < i ; j++)
- kfree(wifi_mem_array[j].mem_ptr);
-
- i = WLAN_SKB_BUF_NUM;
-
-err_skb_alloc:
- pr_err("Failed to skb_alloc for WLAN\n");
- for (j = 0 ; j < i ; j++)
- dev_kfree_skb(wlan_static_skb[j]);
-
- return -ENOMEM;
-}
-
-static struct wifi_platform_data rk29sdk_wifi_control = {
- .set_power = rk29sdk_wifi_power,
- .set_reset = rk29sdk_wifi_reset,
- .set_carddetect = rk29sdk_wifi_set_carddetect,
- .mem_prealloc = rk29sdk_mem_prealloc,
-};
-static struct platform_device rk29sdk_wifi_device = {
- .name = "bcm4329_wlan",
- .id = 1,
- .dev = {
- .platform_data = &rk29sdk_wifi_control,
- },
-};
-#endif
-
-
-/* bluetooth rfkill device */
-static struct platform_device rk29sdk_rfkill = {
- .name = "rk29sdk_rfkill",
- .id = -1,
-};
-
-
-//#ifdef CONFIG_VIVANTE
-#define GPU_HIGH_CLOCK 552
-#define GPU_LOW_CLOCK (periph_pll_default / 1000000) /* same as general pll clock rate below */
-static struct resource resources_gpu[] = {
- [0] = {
- .name = "gpu_irq",
- .start = IRQ_GPU,
- .end = IRQ_GPU,
- .flags = IORESOURCE_IRQ,
- },
- [1] = {
- .name = "gpu_base",
- .start = RK29_GPU_PHYS,
- .end = RK29_GPU_PHYS + RK29_GPU_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "gpu_mem",
- .start = PMEM_GPU_BASE,
- .end = PMEM_GPU_BASE + PMEM_GPU_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [3] = {
- .name = "gpu_clk",
- .start = GPU_LOW_CLOCK,
- .end = GPU_HIGH_CLOCK,
- .flags = IORESOURCE_IO,
- },
-};
-static struct platform_device rk29_device_gpu = {
- .name = "galcore",
- .id = 0,
- .num_resources = ARRAY_SIZE(resources_gpu),
- .resource = resources_gpu,
-};
-//#endif
-
-#ifdef CONFIG_KEYS_RK29
-extern struct rk29_keys_platform_data rk29_keys_pdata;
-static struct platform_device rk29_device_keys = {
- .name = "rk29-keypad",
- .id = -1,
- .dev = {
- .platform_data = &rk29_keys_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
-struct gpio_led rk29_leds[] = {
- {
- .name = "rk29_red_led",
- .gpio = RK29_PIN4_PB2,
- .default_trigger = "timer",
- .active_low = 0,
- .retain_state_suspended = 1,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- },
- {
- .name = "rk29_green_led",
- .gpio = RK29_PIN4_PB1,
- .default_trigger = "timer",
- .active_low = 0,
- .retain_state_suspended = 1,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- },
- {
- .name = "rk29_blue_led",
- .gpio = RK29_PIN4_PB0,
- .default_trigger = "timer",
- .active_low = 0,
- .retain_state_suspended = 1,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- },
-};
-
-struct gpio_led_platform_data rk29_leds_pdata = {
- .leds = &rk29_leds,
- .num_leds = ARRAY_SIZE(rk29_leds),
-};
-
-struct platform_device rk29_device_gpio_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_leds_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_LEDS_NEWTON_PWM
-static struct led_newton_pwm rk29_pwm_leds[] = {
- {
- .name = "power_led",
- .pwm_id = 1,
- .pwm_gpio = RK29_PIN5_PD2,
- .pwm_iomux_name = GPIO5D2_PWM1_UART1SIRIN_NAME,
- .pwm_iomux_pwm = GPIO5H_PWM1,
- .pwm_iomux_gpio = GPIO5H_GPIO5D2,
- .freq = 1000,
- .period = 255,
- },
-};
-
-static struct led_newton_pwm_platform_data rk29_pwm_leds_pdata = {
- .leds = &rk29_pwm_leds,
- .num_leds = ARRAY_SIZE(rk29_pwm_leds),
-};
-
-static struct platform_device rk29_device_pwm_leds = {
- .name = "leds_newton_pwm",
- .id = -1,
- .dev = {
- .platform_data = &rk29_pwm_leds_pdata,
- },
-};
-
-#endif
-static void __init rk29_board_iomux_init(void)
-{
- #ifdef CONFIG_RK29_PWM_REGULATOR
- rk29_mux_api_set(REGULATOR_PWM_MUX_NAME,REGULATOR_PWM_MUX_MODE);
- #endif
-}
-
-static struct platform_device *devices[] __initdata = {
-
-#ifdef CONFIG_RK29_WATCHDOG
- &rk29_device_wdt,
-#endif
-
-#ifdef CONFIG_UART1_RK29
- &rk29_device_uart1,
-#endif
-#ifdef CONFIG_UART0_RK29
- &rk29_device_uart0,
-#endif
-#ifdef CONFIG_UART2_RK29
- &rk29_device_uart2,
-#endif
-#ifdef CONFIG_UART3_RK29
- &rk29_device_uart3,
-#endif
-
-#ifdef CONFIG_RK29_PWM_REGULATOR
- &rk29_device_pwm_regulator,
-#endif
-#ifdef CONFIG_SPIM0_RK29
- &rk29xx_device_spi0m,
-#endif
-#ifdef CONFIG_SPIM1_RK29
- &rk29xx_device_spi1m,
-#endif
-#ifdef CONFIG_ADC_RK29
- &rk29_device_adc,
-#endif
-#ifdef CONFIG_BATTERY_RK29_ADC
- &rk29_adc_device_battery,
-#endif
-#ifdef CONFIG_I2C0_RK29
- &rk29_device_i2c0,
-#endif
-#ifdef CONFIG_I2C1_RK29
- &rk29_device_i2c1,
-#endif
-#ifdef CONFIG_I2C2_RK29
- &rk29_device_i2c2,
-#endif
-#ifdef CONFIG_I2C3_RK29
- &rk29_device_i2c3,
-#endif
-
-#ifdef CONFIG_SND_RK29_SOC_I2S_2CH
- &rk29_device_iis_2ch,
-#endif
-#ifdef CONFIG_SND_RK29_SOC_I2S_8CH
- &rk29_device_iis_8ch,
-#endif
-
-#ifdef CONFIG_KEYS_RK29
- &rk29_device_keys,
-#endif
-#ifdef CONFIG_KEYS_RK29_NEWTON
- &rk29_device_keys,
-#endif
-#ifdef CONFIG_SDMMC0_RK29
- &rk29_device_sdmmc0,
-#endif
-#ifdef CONFIG_SDMMC1_RK29
- &rk29_device_sdmmc1,
-#endif
-
-#ifdef CONFIG_MTD_NAND_RK29XX
- &rk29xx_device_nand,
-#endif
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- &rk29sdk_wifi_device,
-#endif
-
-#ifdef CONFIG_BT
- &rk29sdk_rfkill,
-#endif
-
-#ifdef CONFIG_MTD_NAND_RK29
- &rk29_device_nand,
-#endif
-
-#ifdef CONFIG_FB_RK29
- &rk29_device_fb,
- &rk29_device_dma_cpy,
-#endif
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- &rk29_device_backlight,
-#endif
-#ifdef CONFIG_BACKLIGHT_RK29_NEWTON_BL
- &rk29_device_backlight,
-#endif
-#ifdef CONFIG_RK29_VMAC
- &rk29_device_vmac,
-#endif
-//#ifdef CONFIG_VIVANTE
- &rk29_device_gpu,
-//#endif
-#ifdef CONFIG_VIDEO_RK29
- &rk29_device_camera, /* ddl@rock-chips.com : camera support */
- #if (CONFIG_SENSOR_IIC_ADDR_0 != 0x00)
- &rk29_soc_camera_pdrv_0,
- #endif
- #if (CONFIG_SENSOR_IIC_ADDR_1 != 0x00)
- &rk29_soc_camera_pdrv_1,
- #endif
-
- #if (PMEM_CAM_SIZE > 0)
- &android_pmem_cam_device,
- #endif
-#endif
-#if PMEM_SKYPE_SIZE > 0
- &android_pmem_skype_device,
-#endif
-#ifdef CONFIG_ION
- &rk29_ion_device,
-#endif
- &android_pmem_device,
- &rk29_vpu_mem_device,
-#ifdef CONFIG_USB20_OTG
- &rk29_device_usb20_otg,
-#endif
-#ifdef CONFIG_USB20_HOST
- &rk29_device_usb20_host,
-#endif
-#ifdef CONFIG_USB11_HOST
- &rk29_device_usb11_host,
-#endif
-#ifdef CONFIG_USB_ANDROID
- &android_usb_device,
- &usb_mass_storage_device,
-#endif
-#ifdef CONFIG_USB_ANDROID_RNDIS
- &rk29_device_rndis,
-#endif
-//#ifdef CONFIG_RK29_IPP
- &rk29_device_ipp,
-//#endif
-#ifdef CONFIG_VIDEO_RK29XX_VOUT
- &rk29_v4l2_output_devce,
-#endif
-#ifdef CONFIG_RK29_NEWTON
- &rk29_device_newton,
-#endif
-#ifdef CONFIG_RK_IRDA
- &irda_device,
-#endif
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
- &rk29_device_gpio_leds,
-#endif
-#ifdef CONFIG_LEDS_NEWTON_PWM
- &rk29_device_pwm_leds,
-#endif
-#ifdef CONFIG_SND_RK29_SOC_CS42L52
- &rk29_cs42l52_device,
-#endif
-};
-
-/*****************************************************************************************
- * spi devices
- * author: cmc@rock-chips.com
- *****************************************************************************************/
-static int rk29_vmac_register_set(void)
-{
- //config rk29 vmac as rmii, 100MHz
- u32 value= readl(RK29_GRF_BASE + 0xbc);
- value = (value & 0xfff7ff) | (0x400);
- writel(value, RK29_GRF_BASE + 0xbc);
- return 0;
-}
-
-static int rk29_rmii_io_init(void)
-{
- int err;
-
- //phy power gpio
- err = gpio_request(RK29_PIN6_PB0, "phy_power_en");
- if (err) {
- gpio_free(RK29_PIN6_PB0);
- printk("-------request RK29_PIN6_PB0 fail--------\n");
- return -1;
- }
- //phy power down
- gpio_direction_output(RK29_PIN6_PB0, GPIO_LOW);
- gpio_set_value(RK29_PIN6_PB0, GPIO_LOW);
-
- return 0;
-}
-
-static int rk29_rmii_io_deinit(void)
-{
- //phy power down
- gpio_direction_output(RK29_PIN6_PB0, GPIO_LOW);
- gpio_set_value(RK29_PIN6_PB0, GPIO_LOW);
- //free
- gpio_free(RK29_PIN6_PB0);
- return 0;
-}
-
-static int rk29_rmii_power_control(int enable)
-{
- if (enable) {
- //enable phy power
- gpio_direction_output(RK29_PIN6_PB0, GPIO_HIGH);
- gpio_set_value(RK29_PIN6_PB0, GPIO_HIGH);
- }
- else {
- gpio_direction_output(RK29_PIN6_PB0, GPIO_LOW);
- gpio_set_value(RK29_PIN6_PB0, GPIO_LOW);
- }
- return 0;
-}
-
-struct rk29_vmac_platform_data rk29_vmac_pdata = {
- .vmac_register_set = rk29_vmac_register_set,
- .rmii_io_init = rk29_rmii_io_init,
- .rmii_io_deinit = rk29_rmii_io_deinit,
- .rmii_power_control = rk29_rmii_power_control,
-};
-
-/*****************************************************************************************
- * spi devices
- * author: cmc@rock-chips.com
- *****************************************************************************************/
-#define SPI_CHIPSELECT_NUM 2
-static struct spi_cs_gpio rk29xx_spi0_cs_gpios[SPI_CHIPSELECT_NUM] = {
- {
- .name = "spi0 cs0",
- .cs_gpio = RK29_PIN2_PC1,
- .cs_iomux_name = GPIO2C1_SPI0CSN0_NAME,
- .cs_iomux_mode = GPIO2H_SPI0_CSN0,
- },
- {
- .name = "spi0 cs1",
- .cs_gpio = RK29_PIN1_PA4,
- .cs_iomux_name = GPIO1A4_EMMCWRITEPRT_SPI0CS1_NAME,//if no iomux,set it NULL
- .cs_iomux_mode = GPIO1L_SPI0_CSN1,
- }
-};
-
-static struct spi_cs_gpio rk29xx_spi1_cs_gpios[SPI_CHIPSELECT_NUM] = {
- {
- .name = "spi1 cs0",
- .cs_gpio = RK29_PIN2_PC5,
- .cs_iomux_name = GPIO2C5_SPI1CSN0_NAME,
- .cs_iomux_mode = GPIO2H_SPI1_CSN0,
- },
- {
- .name = "spi1 cs1",
- .cs_gpio = RK29_PIN1_PA3,
- .cs_iomux_name = GPIO1A3_EMMCDETECTN_SPI1CS1_NAME,//if no iomux,set it NULL
- .cs_iomux_mode = GPIO1L_SPI1_CSN1,
- }
-};
-
-static int spi_io_init(struct spi_cs_gpio *cs_gpios, int cs_num)
-{
-#if 1
- int i;
- if (cs_gpios) {
- for (i=0; i<cs_num; i++) {
- rk29_mux_api_set(cs_gpios[i].cs_iomux_name, cs_gpios[i].cs_iomux_mode);
- }
- }
-#endif
- return 0;
-}
-
-static int spi_io_deinit(struct spi_cs_gpio *cs_gpios, int cs_num)
-{
- return 0;
-}
-
-static int spi_io_fix_leakage_bug(void)
-{
-#if 0
- gpio_direction_output(RK29_PIN2_PC1, GPIO_LOW);
-#endif
- return 0;
-}
-
-static int spi_io_resume_leakage_bug(void)
-{
-#if 0
- gpio_direction_output(RK29_PIN2_PC1, GPIO_HIGH);
-#endif
- return 0;
-}
-
-struct rk29xx_spi_platform_data rk29xx_spi0_platdata = {
- .num_chipselect = SPI_CHIPSELECT_NUM,
- .chipselect_gpios = rk29xx_spi0_cs_gpios,
- .io_init = spi_io_init,
- .io_deinit = spi_io_deinit,
- .io_fix_leakage_bug = spi_io_fix_leakage_bug,
- .io_resume_leakage_bug = spi_io_resume_leakage_bug,
-};
-
-struct rk29xx_spi_platform_data rk29xx_spi1_platdata = {
- .num_chipselect = SPI_CHIPSELECT_NUM,
- .chipselect_gpios = rk29xx_spi1_cs_gpios,
- .io_init = spi_io_init,
- .io_deinit = spi_io_deinit,
- .io_fix_leakage_bug = spi_io_fix_leakage_bug,
- .io_resume_leakage_bug = spi_io_resume_leakage_bug,
-};
-
-/*****************************************************************************************
- * xpt2046 touch panel
- * author: cmc@rock-chips.com
- *****************************************************************************************/
-#define XPT2046_GPIO_INT RK29_PIN0_PA3
-#define DEBOUNCE_REPTIME 3
-
-#if defined(CONFIG_TOUCHSCREEN_XPT2046_320X480_SPI)
-static struct xpt2046_platform_data xpt2046_info = {
- .model = 2046,
- .keep_vref_on = 1,
- .swap_xy = 0,
- .x_min = 0,
- .x_max = 320,
- .y_min = 0,
- .y_max = 480,
- .debounce_max = 7,
- .debounce_rep = DEBOUNCE_REPTIME,
- .debounce_tol = 20,
- .gpio_pendown = XPT2046_GPIO_INT,
- .penirq_recheck_delay_usecs = 1,
-};
-#elif defined(CONFIG_TOUCHSCREEN_XPT2046_320X480_CBN_SPI)
-static struct xpt2046_platform_data xpt2046_info = {
- .model = 2046,
- .keep_vref_on = 1,
- .swap_xy = 0,
- .x_min = 0,
- .x_max = 320,
- .y_min = 0,
- .y_max = 480,
- .debounce_max = 7,
- .debounce_rep = DEBOUNCE_REPTIME,
- .debounce_tol = 20,
- .gpio_pendown = XPT2046_GPIO_INT,
- .penirq_recheck_delay_usecs = 1,
-};
-#elif defined(CONFIG_TOUCHSCREEN_XPT2046_SPI)
-static struct xpt2046_platform_data xpt2046_info = {
- .model = 2046,
- .keep_vref_on = 1,
- .swap_xy = 1,
- .x_min = 0,
- .x_max = 800,
- .y_min = 0,
- .y_max = 480,
- .debounce_max = 7,
- .debounce_rep = DEBOUNCE_REPTIME,
- .debounce_tol = 20,
- .gpio_pendown = XPT2046_GPIO_INT,
-
- .penirq_recheck_delay_usecs = 1,
-};
-#elif defined(CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI)
-static struct xpt2046_platform_data xpt2046_info = {
- .model = 2046,
- .keep_vref_on = 1,
- .swap_xy = 1,
- .x_min = 0,
- .x_max = 800,
- .y_min = 0,
- .y_max = 480,
- .debounce_max = 7,
- .debounce_rep = DEBOUNCE_REPTIME,
- .debounce_tol = 20,
- .gpio_pendown = XPT2046_GPIO_INT,
-
- .penirq_recheck_delay_usecs = 1,
-};
-#endif
-
-static struct spi_board_info board_spi_devices[] = {
-#if defined(CONFIG_TOUCHSCREEN_XPT2046_320X480_SPI) || defined(CONFIG_TOUCHSCREEN_XPT2046_320X480_CBN_SPI)\
- ||defined(CONFIG_TOUCHSCREEN_XPT2046_SPI) || defined(CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI)
- {
- .modalias = "xpt2046_ts",
- .chip_select = 0,
- .max_speed_hz = 125 * 1000 * 26,/* (max sample rate @ 3V) * (cmd + data + overhead) */
- .bus_num = 0,
- .irq = XPT2046_GPIO_INT,
- .platform_data = &xpt2046_info,
- },
-#endif
-};
-
-
-static void __init rk29_gic_init_irq(void)
-{
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38))
- gic_init(0, 32, (void __iomem *)RK29_GICPERI_BASE, (void __iomem *)RK29_GICCPU_BASE);
-#else
- gic_dist_init(0, (void __iomem *)RK29_GICPERI_BASE, 32);
- gic_cpu_init(0, (void __iomem *)RK29_GICCPU_BASE);
-#endif
-}
-
-static void __init machine_rk29_init_irq(void)
-{
- rk29_gic_init_irq();
- rk29_gpio_init();
-}
-
-static struct cpufreq_frequency_table freq_table[] = {
- { .index = 1200000, .frequency = 408000 },
- { .index = 1250000, .frequency = 816000 },
- { .index = 1350000, .frequency = 1008000 },
- { .frequency = CPUFREQ_TABLE_END },
-};
-
-static void __init machine_rk29_board_init(void)
-{
- rk29_board_iomux_init();
-
- board_power_init();
- board_update_cpufreq_table(freq_table);
-
- platform_add_devices(devices, ARRAY_SIZE(devices));
-#ifdef CONFIG_I2C0_RK29
- i2c_register_board_info(default_i2c0_data.bus_num, board_i2c0_devices,
- ARRAY_SIZE(board_i2c0_devices));
-#endif
-#ifdef CONFIG_I2C1_RK29
- i2c_register_board_info(default_i2c1_data.bus_num, board_i2c1_devices,
- ARRAY_SIZE(board_i2c1_devices));
-#endif
-#ifdef CONFIG_I2C2_RK29
- i2c_register_board_info(default_i2c2_data.bus_num, board_i2c2_devices,
- ARRAY_SIZE(board_i2c2_devices));
-#endif
-#ifdef CONFIG_I2C3_RK29
- i2c_register_board_info(default_i2c3_data.bus_num, board_i2c3_devices,
- ARRAY_SIZE(board_i2c3_devices));
-#endif
-
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- rk29sdk_wifi_bt_gpio_control_init();
- rk29sdk_init_wifi_mem();
-#endif
-
- board_usb_detect_init(RK29_PIN0_PA0);
-#if defined(CONFIG_RK_IRDA) || defined(CONFIG_BU92747GUW_CIR)
- smc0_init(NULL);
- bu92747guw_io_init();
-#endif
-
-}
-
-static void __init machine_rk29_fixup(struct machine_desc *desc, struct tag *tags,
- char **cmdline, struct meminfo *mi)
-{
- mi->nr_banks = 1;
- mi->bank[0].start = RK29_SDRAM_PHYS;
- mi->bank[0].size = LINUX_SIZE;
-#if SDRAM_SIZE > SZ_512M
- mi->nr_banks = 2;
- mi->bank[1].start = RK29_SDRAM_PHYS + SZ_512M;
- mi->bank[1].size = SDRAM_SIZE - SZ_512M;
-#endif
-}
-
-static void __init machine_rk29_mapio(void)
-{
- rk29_map_common_io();
- rk29_setup_early_printk();
- rk29_sram_init();
- rk29_clock_init(periph_pll_default);
- rk29_iomux_init();
- ddr_init(DDR_TYPE, DDR_FREQ);
-}
-
-MACHINE_START(RK29, "RK29board")
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 37))
- /* UART for LL DEBUG */
- .phys_io = RK29_UART1_PHYS & 0xfff00000,
- .io_pg_offst = ((RK29_UART1_BASE) >> 18) & 0xfffc,
-#endif
- .boot_params = RK29_SDRAM_PHYS + 0x88000,
- .fixup = machine_rk29_fixup,
- .map_io = machine_rk29_mapio,
- .init_irq = machine_rk29_init_irq,
- .init_machine = machine_rk29_board_init,
- .timer = &rk29_timer,
-MACHINE_END
+++ /dev/null
-#include <mach/key.h>
-#include <mach/gpio.h>
-
-#define EV_ENCALL KEY_F4
-#define EV_MENU KEY_F1
-
-#define PRESS_LEV_LOW 1
-#define PRESS_LEV_HIGH 0
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "menu",
- .code = EV_MENU,
- .gpio = RK29_PIN6_PA0,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .gpio = RK29_PIN6_PA1,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .gpio = RK29_PIN6_PA2,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .gpio = RK29_PIN6_PA3,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "search",
- .code = KEY_SEARCH,
- .gpio = RK29_PIN6_PA4,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .gpio = RK29_PIN6_PA5,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "sensor",
- .code = KEY_CAMERA,
- .gpio = RK29_PIN6_PA6,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK29_PIN6_PA7,
- .active_low = PRESS_LEV_LOW,
- .wakeup = 1,
- },
-#if 0
- {
- .desc = "vol+",
- .code = KEY_VOLUMEDOWN,
- .adc_value = 95,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEUP,
- .adc_value = 249,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "menu",
- .code = EV_MENU,
- .adc_value = 406,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .code_long_press = KEY_F4,
- .adc_value = 561,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_ESC,
- .adc_value = 726,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "adkey6",
- .code = KEY_BACK,
- .code_long_press = EV_ENCALL,
- .adc_value = 899,
- .active_low = PRESS_LEV_LOW,
- },
-#endif
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = -1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
+++ /dev/null
-/*
- * Copyright (C) 2010 ROCKCHIP, Inc.
- * Author: roger_chen <cz@rock-chips.com>
- *
- * This program is the bluetooth device bcm4329's driver,
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/module.h>
-#include <linux/device.h>
-#include <linux/rfkill.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/interrupt.h>
-#include <linux/wakelock.h>
-#include <linux/fs.h>
-#include <asm/uaccess.h>
-#include <mach/gpio.h>
-#include <asm/irq.h>
-#include <mach/iomux.h>
-#include <linux/wakelock.h>
-#include <linux/timer.h>
-#include <mach/board.h>
-#if 0
-#define DBG(x...) printk(KERN_INFO x)
-#else
-#define DBG(x...)
-#endif
-
-#define BT_WAKE_HOST_SUPPORT 1
-
-struct bt_ctrl
-{
- struct rfkill *bt_rfk;
-#if BT_WAKE_HOST_SUPPORT
- struct timer_list tl;
- bool b_HostWake;
- struct wake_lock bt_wakelock;
-#endif
-};
-
-#define BT_GPIO_POWER RK29_PIN5_PD6
-#define IOMUX_BT_GPIO_POWER rk29_mux_api_set(GPIO5D6_SDMMC1PWREN_NAME, GPIO5H_GPIO5D6);
-#define BT_GPIO_RESET RK29_PIN6_PC7
-#define BT_GPIO_WAKE_UP RK29_PIN6_PD0
-#define BT_GPIO_WAKE_UP_HOST RK29_PIN4_PD4
-#define IOMUX_BT_GPIO_WAKE_UP_HOST() rk29_mux_api_set(GPIO4D4_CPUTRACECLK_NAME,GPIO4H_GPIO4D4);
-
-//bt cts paired to uart rts
-#define UART_RTS RK29_PIN2_PA7
-#define IOMUX_UART_RTS_GPIO rk29_mux_api_set(GPIO2A7_UART2RTSN_NAME, GPIO2L_GPIO2A7);
-#define IOMUX_UART_RTS rk29_mux_api_set(GPIO2A7_UART2RTSN_NAME, GPIO2L_UART2_RTS_N);
-
-#define BT_WAKE_LOCK_TIMEOUT 10 //s
-
-static const char bt_name[] = "bcm4329";
-extern int rk29sdk_bt_power_state;
-extern int rk29sdk_wifi_power_state;
-
-struct bt_ctrl gBtCtrl;
-
-#if BT_WAKE_HOST_SUPPORT
-void resetBtHostSleepTimer(void)
-{
- mod_timer(&(gBtCtrl.tl),jiffies + BT_WAKE_LOCK_TIMEOUT*HZ);//ÔÙÖØÐÂÉèÖó¬Ê±Öµ¡£
-}
-
-void btWakeupHostLock(void)
-{
- if(gBtCtrl.b_HostWake == false){
- DBG("*************************Lock\n");
-
- wake_lock(&(gBtCtrl.bt_wakelock));
- gBtCtrl.b_HostWake = true;
- }
-}
-
-void btWakeupHostUnlock(void)
-{
- if(gBtCtrl.b_HostWake == true){
- DBG("*************************UnLock\n");
- wake_unlock(&(gBtCtrl.bt_wakelock)); //ÈÃϵͳ˯Ãß
- gBtCtrl.b_HostWake = false;
- }
-}
-
-static void timer_hostSleep(unsigned long arg)
-{
- DBG("%s---b_HostWake=%d\n",__FUNCTION__,gBtCtrl.b_HostWake);
- btWakeupHostUnlock();
-}
-
-
-#ifdef CONFIG_PM
-static int bcm4329_rfkill_suspend(struct platform_device *pdev, pm_message_t state)
-{
- DBG("%s\n",__FUNCTION__);
-
- //To prevent uart to receive bt data when suspended
- IOMUX_UART_RTS_GPIO;
- gpio_request(UART_RTS, "uart_rts");
- gpio_direction_output(UART_RTS, 0);
- gpio_set_value(UART_RTS, GPIO_HIGH);
-
- return 0;
-}
-
-static int bcm4329_rfkill_resume(struct platform_device *pdev)
-{
- DBG("%s\n",__FUNCTION__);
-
- btWakeupHostLock();
- resetBtHostSleepTimer();
-
- gpio_set_value(UART_RTS, GPIO_LOW);
- IOMUX_UART_RTS;
-
- return 0;
-}
-#else
-#define bcm4329_rfkill_suspend NULL
-#define bcm4329_rfkill_resume NULL
-#endif
-
-static irqreturn_t bcm4329_wake_host_irq(int irq, void *dev)
-{
- DBG("%s\n",__FUNCTION__);
-
- btWakeupHostLock();
- resetBtHostSleepTimer();
- return IRQ_HANDLED;
-}
-#endif
-
-#ifdef CONFIG_BT_HCIBCM4325
-int bcm4325_sleep(int bSleep)
-{
- //printk("*************bt enter sleep***************\n");
- if (bSleep)
- gpio_set_value(BT_GPIO_WAKE_UP, GPIO_LOW); //low represent bt device may enter sleep
- else
- gpio_set_value(BT_GPIO_WAKE_UP, GPIO_HIGH); //high represent bt device must be awake
- //printk("sleep=%d\n",bSleep);
- return 0;
-}
-#endif
-
-static int bcm4329_set_block(void *data, bool blocked)
-{
- DBG("%s---blocked :%d\n", __FUNCTION__, blocked);
-
- IOMUX_BT_GPIO_POWER;
-
- if (false == blocked) {
- gpio_set_value(BT_GPIO_POWER, GPIO_HIGH); /* bt power on */
- gpio_set_value(BT_GPIO_RESET, GPIO_LOW);
- mdelay(200);
- gpio_set_value(BT_GPIO_RESET, GPIO_HIGH); /* bt reset deactive*/
- mdelay(200);
-
-#if BT_WAKE_HOST_SUPPORT
- btWakeupHostLock();
-#endif
- pr_info("bt turn on power\n");
- }
- else {
-#if BT_WAKE_HOST_SUPPORT
- btWakeupHostUnlock();
-#endif
- if (!rk29sdk_wifi_power_state) {
- gpio_set_value(BT_GPIO_POWER, GPIO_LOW); /* bt power off */
- mdelay(20);
- pr_info("bt shut off power\n");
- }else {
- pr_info("bt shouldn't shut off power, wifi is using it!\n");
- }
-
- gpio_set_value(BT_GPIO_RESET, GPIO_LOW); /* bt reset active*/
- mdelay(20);
- }
-
- rk29sdk_bt_power_state = !blocked;
- return 0;
-}
-
-
-static const struct rfkill_ops bcm4329_rfk_ops = {
- .set_block = bcm4329_set_block,
-};
-
-static int __devinit bcm4329_rfkill_probe(struct platform_device *pdev)
-{
- int rc = 0;
- bool default_state = true;
-
- DBG("Enter::%s,line=%d\n",__FUNCTION__,__LINE__);
-
- /* default to bluetooth off */
- bcm4329_set_block(NULL, default_state); /* blocked -> bt off */
-
- gBtCtrl.bt_rfk = rfkill_alloc(bt_name,
- NULL,
- RFKILL_TYPE_BLUETOOTH,
- &bcm4329_rfk_ops,
- NULL);
-
- if (!gBtCtrl.bt_rfk)
- {
- printk("fail to rfkill_allocate************\n");
- return -ENOMEM;
- }
-
- rfkill_set_states(gBtCtrl.bt_rfk, default_state, false);
-
- rc = rfkill_register(gBtCtrl.bt_rfk);
- if (rc)
- {
- printk("failed to rfkill_register,rc=0x%x\n",rc);
- rfkill_destroy(gBtCtrl.bt_rfk);
- }
-
- gpio_request(BT_GPIO_POWER, NULL);
- gpio_request(BT_GPIO_RESET, NULL);
- gpio_request(BT_GPIO_WAKE_UP, NULL);
-
-#if BT_WAKE_HOST_SUPPORT
- init_timer(&(gBtCtrl.tl));
- gBtCtrl.tl.expires = jiffies + BT_WAKE_LOCK_TIMEOUT*HZ;
- gBtCtrl.tl.function = timer_hostSleep;
- add_timer(&(gBtCtrl.tl));
- gBtCtrl.b_HostWake = false;
-
- wake_lock_init(&(gBtCtrl.bt_wakelock), WAKE_LOCK_SUSPEND, "bt_wake");
-
- rc = gpio_request(BT_GPIO_WAKE_UP_HOST, "bt_wake");
- if (rc) {
- printk("%s:failed to request RAHO_BT_WAKE_UP_HOST\n",__FUNCTION__);
- }
-
- IOMUX_BT_GPIO_WAKE_UP_HOST();
- gpio_pull_updown(BT_GPIO_WAKE_UP_HOST,GPIOPullUp);
- rc = request_irq(gpio_to_irq(BT_GPIO_WAKE_UP_HOST),bcm4329_wake_host_irq,IRQF_TRIGGER_FALLING,NULL,NULL);
- if(rc)
- {
- printk("%s:failed to request RAHO_BT_WAKE_UP_HOST irq\n",__FUNCTION__);
- gpio_free(BT_GPIO_WAKE_UP_HOST);
- }
- enable_irq_wake(gpio_to_irq(BT_GPIO_WAKE_UP_HOST)); // so RAHO_BT_WAKE_UP_HOST can wake up system
-
- printk(KERN_INFO "bcm4329 module has been initialized,rc=0x%x\n",rc);
- #endif
-
- return rc;
-
-
-}
-
-
-static int __devexit bcm4329_rfkill_remove(struct platform_device *pdev)
-{
- if (gBtCtrl.bt_rfk)
- rfkill_unregister(gBtCtrl.bt_rfk);
- gBtCtrl.bt_rfk = NULL;
-#if BT_WAKE_HOST_SUPPORT
- del_timer(&(gBtCtrl.tl));//ɾµô¶¨Ê±Æ÷
- btWakeupHostUnlock();
- wake_lock_destroy(&(gBtCtrl.bt_wakelock));
-#endif
- platform_set_drvdata(pdev, NULL);
-
- DBG("Enter::%s,line=%d\n",__FUNCTION__,__LINE__);
- return 0;
-}
-
-static struct platform_driver bcm4329_rfkill_driver = {
- .probe = bcm4329_rfkill_probe,
- .remove = __devexit_p(bcm4329_rfkill_remove),
- .driver = {
- .name = "rk29sdk_rfkill",
- .owner = THIS_MODULE,
- },
-#if BT_WAKE_HOST_SUPPORT
- .suspend = bcm4329_rfkill_suspend,
- .resume = bcm4329_rfkill_resume,
-#endif
-};
-
-/*
- * Module initialization
- */
-static int __init bcm4329_mod_init(void)
-{
- int ret;
- DBG("Enter::%s,line=%d\n",__FUNCTION__,__LINE__);
- ret = platform_driver_register(&bcm4329_rfkill_driver);
- printk("ret=0x%x\n", ret);
- return ret;
-}
-
-static void __exit bcm4329_mod_exit(void)
-{
- platform_driver_unregister(&bcm4329_rfkill_driver);
-}
-
-module_init(bcm4329_mod_init);
-module_exit(bcm4329_mod_exit);
-MODULE_DESCRIPTION("bcm4329 Bluetooth driver");
-MODULE_AUTHOR("roger_chen cz@rock-chips.com");
-MODULE_LICENSE("GPL");
-
+++ /dev/null
-/* arch/arm/mach-rk29/board-rk29-phonesdk.c
- *
- * Copyright (C) 2010 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/android_pmem.h>
-#include <linux/usb/android_composite.h>
-#include <linux/ion.h>
-
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/iomux.h>
-#include <mach/gpio.h>
-#include <mach/irqs.h>
-#include <mach/rk29_iomap.h>
-#include <mach/board.h>
-#include <mach/rk29_nand.h>
-#include <mach/rk29_camera.h> /* ddl@rock-chips.com : camera support */
-#include <media/soc_camera.h> /* ddl@rock-chips.com : camera support */
-#include <mach/vpu_mem.h>
-#include <mach/sram.h>
-#include <mach/ddr.h>
-#include <mach/cpufreq.h>
-
-#include <linux/regulator/rk29-pwm-regulator.h>
-#include <linux/regulator/machine.h>
-#include <linux/mfd/wm831x/pdata.h>
-#include <linux/mfd/wm831x/core.h>
-#include <linux/mfd/wm831x/gpio.h>
-
-#include <linux/regulator/fixed.h>
-#include <linux/mfd/wm8994/pdata.h>
-
-#include <linux/mtd/nand.h>
-#include <linux/mtd/partitions.h>
-#include <linux/i2c-gpio.h>
-#include <linux/mpu.h>
-#include "devices.h"
-
-
-#if defined(CONFIG_MTK23D)
-#include <linux/mtk23d.h>
-#endif
-
-#ifdef CONFIG_USE_GPIO_GENERATE_WAVE
-#include "../../../drivers/testcode/gpio_wave.h"
-#endif
-
-#include "../../../drivers/headset_observe/rk_headset.h"
-/*set touchscreen different type header*/
-#if defined(CONFIG_TOUCHSCREEN_XPT2046_NORMAL_SPI)
-#include "../../../drivers/input/touchscreen/xpt2046_ts.h"
-#elif defined(CONFIG_TOUCHSCREEN_XPT2046_TSLIB_SPI)
-#include "../../../drivers/input/touchscreen/xpt2046_tslib_ts.h"
-#elif defined(CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI)
-#include "../../../drivers/input/touchscreen/xpt2046_cbn_ts.h"
-#endif
-#include "../../../drivers/misc/gps/rk29_gps.h"
-#include "../../../drivers/tty/serial/sc8800.h"
-#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Macro Define Begin ------------------------*/
-/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
-#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_OV5642 /* back camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_0 0x78
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 1
-#define CONFIG_SENSOR_ORIENTATION_0 0
-#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 RK29_PIN6_PB7
-#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15
-#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15
-#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15
-#define CONFIG_SENSOR_720P_FPS_FIXED_0 30
-
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_OV2659 /* front camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_1 0x60
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 1
-#define CONFIG_SENSOR_ORIENTATION_1 0
-#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_1 RK29_PIN5_PD7
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15
-#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15
-#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15
-#define CONFIG_SENSOR_720P_FPS_FIXED_1 30
-
-#endif //#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk29_camera.c"
-/*---------------- Camera Sensor Macro Define End ------------------------*/
-
-
-/* Set memory size of pmem */
-#ifdef CONFIG_RK29_MEM_SIZE_M
-#define SDRAM_SIZE (CONFIG_RK29_MEM_SIZE_M * SZ_1M)
-#else
-#define SDRAM_SIZE SZ_512M
-#endif
-#define PMEM_GPU_SIZE SZ_16M
-#define PMEM_UI_SIZE SZ_32M
-#define PMEM_VPU_SIZE SZ_64M
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-#ifdef CONFIG_VIDEO_RK29_WORK_IPP
-#define MEM_CAMIPP_SIZE SZ_4M
-#else
-#define MEM_CAMIPP_SIZE 0
-#endif
-#define MEM_FB_SIZE (3*SZ_2M)
-#ifdef CONFIG_FB_WORK_IPP
-#ifdef CONFIG_FB_SCALING_OSD_1080P
-#define MEM_FBIPP_SIZE SZ_16M //1920 x 1080 x 2 x 2 //RGB565 = x2;RGB888 = x4
-#else
-#define MEM_FBIPP_SIZE SZ_8M //1920 x 1080 x 2 x 2 //RGB565 = x2;RGB888 = x4
-#endif
-#else
-#define MEM_FBIPP_SIZE 0
-#endif
-#if SDRAM_SIZE > SZ_512M
-#define PMEM_GPU_BASE (RK29_SDRAM_PHYS + SZ_512M - PMEM_GPU_SIZE)
-#else
-#define PMEM_GPU_BASE (RK29_SDRAM_PHYS + SDRAM_SIZE - PMEM_GPU_SIZE)
-#endif
-#define PMEM_UI_BASE (PMEM_GPU_BASE - PMEM_UI_SIZE)
-#define PMEM_VPU_BASE (PMEM_UI_BASE - PMEM_VPU_SIZE)
-#define PMEM_CAM_BASE (PMEM_VPU_BASE - PMEM_CAM_SIZE)
-#define MEM_CAMIPP_BASE (PMEM_CAM_BASE - MEM_CAMIPP_SIZE)
-#define MEM_FB_BASE (MEM_CAMIPP_BASE - MEM_FB_SIZE)
-#define MEM_FBIPP_BASE (MEM_FB_BASE - MEM_FBIPP_SIZE)
-#define LINUX_SIZE (MEM_FBIPP_BASE - RK29_SDRAM_PHYS)
-
-#define PREALLOC_WLAN_SEC_NUM 4
-#define PREALLOC_WLAN_BUF_NUM 160
-#define PREALLOC_WLAN_SECTION_HEADER 24
-
-#define WLAN_SECTION_SIZE_0 (PREALLOC_WLAN_BUF_NUM * 128)
-#define WLAN_SECTION_SIZE_1 (PREALLOC_WLAN_BUF_NUM * 128)
-#define WLAN_SECTION_SIZE_2 (PREALLOC_WLAN_BUF_NUM * 512)
-#define WLAN_SECTION_SIZE_3 (PREALLOC_WLAN_BUF_NUM * 1024)
-
-#define WLAN_SKB_BUF_NUM 16
-#define UNLOCK_SECURITY_KEY ~(0x1<<5)
-#define LOCK_SECURITY_KEY 0x00
-
-static struct sk_buff *wlan_static_skb[WLAN_SKB_BUF_NUM];
-
-struct wifi_mem_prealloc {
- void *mem_ptr;
- unsigned long size;
-};
-
-extern struct sys_timer rk29_timer;
-
-static int rk29_nand_io_init(void)
-{
- return 0;
-}
-
-struct rk29_nand_platform_data rk29_nand_data = {
- .width = 1, /* data bus width in bytes */
- .hw_ecc = 1, /* hw ecc 0: soft ecc */
- .num_flash = 1,
- .io_init = rk29_nand_io_init,
-};
-
-#ifdef CONFIG_FB_RK29
-/*****************************************************************************************
- * lcd devices
- * author: zyw@rock-chips.com
- *****************************************************************************************/
-//#ifdef CONFIG_LCD_TD043MGEA1
-#define LCD_RXD_PIN RK29_PIN2_PC7
-#define LCD_TXD_PIN RK29_PIN2_PC6
-#define LCD_CLK_PIN RK29_PIN2_PC4
-#define LCD_CS_PIN RK29_PIN2_PC5
-/*****************************************************************************************
-* frame buffer devices
-* author: zyw@rock-chips.com
-*****************************************************************************************/
-#define FB_ID 0
-#define FB_DISPLAY_ON_PIN INVALID_GPIO//RK29_PIN6_PD0
-#define FB_LCD_STANDBY_PIN INVALID_GPIO//RK29_PIN6_PD1
-#define FB_LCD_CABC_EN_PIN INVALID_GPIO//RK29_PIN6_PD2
-#define FB_MCU_FMK_PIN INVALID_GPIO
-
-#define FB_DISPLAY_ON_VALUE GPIO_HIGH
-#define FB_LCD_STANDBY_VALUE GPIO_HIGH
-
-//#endif
-static int rk29_lcd_io_init(void)
-{
- int ret = 0;
- //printk("rk29_lcd_io_init\n");
- //ret = gpio_request(LCD_RXD_PIN, NULL);
- ret = gpio_request(LCD_TXD_PIN, NULL);
- ret = gpio_request(LCD_CLK_PIN, NULL);
- ret = gpio_request(LCD_CS_PIN, NULL);
- //rk29_mux_api_set(GPIO2C7_SPI1RXD_NAME,GPIO2H_GPIO2C7);
- rk29_mux_api_set(GPIO2C6_SPI1TXD_NAME,GPIO2H_GPIO2C6);
- rk29_mux_api_set(GPIO2C5_SPI1CSN0_NAME,GPIO2H_GPIO2C5);
- rk29_mux_api_set(GPIO2C4_SPI1CLK_NAME,GPIO2H_GPIO2C4);
- return ret;
-}
-
-static int rk29_lcd_io_deinit(void)
-{
- int ret = 0;
- //printk("rk29_lcd_io_deinit\n");
- gpio_free(LCD_CS_PIN);
- gpio_free(LCD_CLK_PIN);
- gpio_free(LCD_TXD_PIN);
- //gpio_free(LCD_RXD_PIN);
- //rk29_mux_api_set(GPIO2C7_SPI1RXD_NAME,GPIO2H_SPI1_RXD);
- rk29_mux_api_set(GPIO2C6_SPI1TXD_NAME,GPIO2H_SPI1_TXD);
- rk29_mux_api_set(GPIO2C5_SPI1CSN0_NAME,GPIO2H_SPI1_CSN0);
- rk29_mux_api_set(GPIO2C4_SPI1CLK_NAME,GPIO2H_SPI1_CLK);
- return ret;
-}
-
-static struct rk29lcd_info rk29_lcd_info = {
- .txd_pin = LCD_TXD_PIN,
- .clk_pin = LCD_CLK_PIN,
- .cs_pin = LCD_CS_PIN,
- .io_init = rk29_lcd_io_init,
- .io_deinit = rk29_lcd_io_deinit,
-};
-
-int rk29_fb_io_enable(void)
-{
- if(FB_DISPLAY_ON_PIN != INVALID_GPIO)
- {
- gpio_direction_output(FB_DISPLAY_ON_PIN, 0);
- gpio_set_value(FB_DISPLAY_ON_PIN, FB_DISPLAY_ON_VALUE);
- }
- if(FB_LCD_STANDBY_PIN != INVALID_GPIO)
- {
- gpio_direction_output(FB_LCD_STANDBY_PIN, 0);
- gpio_set_value(FB_LCD_STANDBY_PIN, FB_LCD_STANDBY_VALUE);
- }
- return 0;
-}
-
-int rk29_fb_io_disable(void)
-{
- if(FB_DISPLAY_ON_PIN != INVALID_GPIO)
- {
- gpio_direction_output(FB_DISPLAY_ON_PIN, 0);
- gpio_set_value(FB_DISPLAY_ON_PIN, !FB_DISPLAY_ON_VALUE);
- }
- if(FB_LCD_STANDBY_PIN != INVALID_GPIO)
- {
- gpio_direction_output(FB_LCD_STANDBY_PIN, 0);
- gpio_set_value(FB_LCD_STANDBY_PIN, !FB_LCD_STANDBY_VALUE);
- }
- return 0;
-}
-
-static int rk29_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
- if(fb_setting->mcu_fmk_en && (FB_MCU_FMK_PIN != INVALID_GPIO))
- {
- ret = gpio_request(FB_MCU_FMK_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(FB_MCU_FMK_PIN);
- printk(">>>>>> FB_MCU_FMK_PIN gpio_request err \n ");
- }
- gpio_direction_input(FB_MCU_FMK_PIN);
- }
- if(fb_setting->disp_on_en && (FB_DISPLAY_ON_PIN != INVALID_GPIO))
- {
- ret = gpio_request(FB_DISPLAY_ON_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(FB_DISPLAY_ON_PIN);
- printk(">>>>>> FB_DISPLAY_ON_PIN gpio_request err \n ");
- }
- }
-
- if(fb_setting->disp_on_en && (FB_LCD_STANDBY_PIN != INVALID_GPIO))
- {
- ret = gpio_request(FB_LCD_STANDBY_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(FB_LCD_STANDBY_PIN);
- printk(">>>>>> FB_LCD_STANDBY_PIN gpio_request err \n ");
- }
- }
-
- if(FB_LCD_CABC_EN_PIN != INVALID_GPIO)
- {
- ret = gpio_request(FB_LCD_CABC_EN_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(FB_LCD_CABC_EN_PIN);
- printk(">>>>>> FB_LCD_CABC_EN_PIN gpio_request err \n ");
- }
- gpio_direction_output(FB_LCD_CABC_EN_PIN, 0);
- gpio_set_value(FB_LCD_CABC_EN_PIN, GPIO_LOW);
- }
- rk29_fb_io_enable(); //enable it
-
- return ret;
-}
-
-static struct rk29fb_info rk29_fb_info = {
- .fb_id = FB_ID,
- .mcu_fmk_pin = FB_MCU_FMK_PIN,
- .lcd_info = &rk29_lcd_info,
- .io_init = rk29_fb_io_init,
- .io_enable = rk29_fb_io_enable,
- .io_disable = rk29_fb_io_disable,
-};
-
-/* rk29 fb resource */
-static struct resource rk29_fb_resource[] = {
- [0] = {
- .name = "lcdc reg",
- .start = RK29_LCDC_PHYS,
- .end = RK29_LCDC_PHYS + RK29_LCDC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc irq",
- .start = IRQ_LCDC,
- .end = IRQ_LCDC,
- .flags = IORESOURCE_IRQ,
- },
- [2] = {
- .name = "win1 buf",
- .start = MEM_FB_BASE,
- .end = MEM_FB_BASE + MEM_FB_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- #ifdef CONFIG_FB_WORK_IPP
- [3] = {
- .name = "win1 ipp buf",
- .start = MEM_FBIPP_BASE,
- .end = MEM_FBIPP_BASE + MEM_FBIPP_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- #endif
-};
-
-/*platform_device*/
-struct platform_device rk29_device_fb = {
- .name = "rk29-fb",
- .id = 4,
- .num_resources = ARRAY_SIZE(rk29_fb_resource),
- .resource = rk29_fb_resource,
- .dev = {
- .platform_data = &rk29_fb_info,
- }
-};
-
-struct platform_device rk29_device_dma_cpy = {
- .name = "dma_memcpy",
- .id = 4,
-
-};
-
-#endif
-
-static struct android_pmem_platform_data android_pmem_pdata = {
- .name = "pmem",
- .start = PMEM_UI_BASE,
- .size = PMEM_UI_SIZE,
- .no_allocator = 1,
- .cached = 1,
-};
-
-static struct platform_device android_pmem_device = {
- .name = "android_pmem",
- .id = 0,
- .dev = {
- .platform_data = &android_pmem_pdata,
- },
-};
-
-
-static struct vpu_mem_platform_data vpu_mem_pdata = {
- .name = "vpu_mem",
- .start = PMEM_VPU_BASE,
- .size = PMEM_VPU_SIZE,
- .cached = 1,
-};
-
-static struct platform_device rk29_vpu_mem_device = {
- .name = "vpu_mem",
- .id = 2,
- .dev = {
- .platform_data = &vpu_mem_pdata,
- },
-};
-
-static struct platform_device rk29_v4l2_output_devce = {
- .name = "rk29_vout",
-};
-
-#ifdef CONFIG_ION
-static struct ion_platform_data rk29_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = 0,
- .name = "ui",
- .base = PMEM_UI_BASE,
- .size = PMEM_UI_SIZE,
- }
- },
-};
-
-static struct platform_device rk29_ion_device = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk29_ion_pdata,
- },
-};
-#endif
-
-
-/* HANNSTAR_P1003 touch I2C */
-#if defined (CONFIG_HANNSTAR_P1003)
-#define TOUCH_RESET_PIN RK29_PIN6_PC3
-#define TOUCH_INT_PIN RK29_PIN4_PD5
-
-int p1003_init_platform_hw(void)
-{
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_pull_updown(TOUCH_INT_PIN, 1);
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
-
- return 0;
-}
-
-
-struct p1003_platform_data p1003_info = {
- .model= 1003,
- .init_platform_hw= p1003_init_platform_hw,
-
-};
-#endif
-
-
-#if defined(CONFIG_TOUCHSCREEN_GT801_IIC)
-#include "../../../drivers/input/touchscreen/gt801_ts.h"
-#define GT801_GPIO_INT RK29_PIN4_PD5
-#define GT801_GPIO_RESET RK29_PIN6_PC3
-static struct gt801_platform_data gt801_info = {
- .model = 801,
- .swap_xy = 0,
- .x_min = 0,
- .x_max = 480,
- .y_min = 0,
- .y_max = 800,
- .gpio_reset = GT801_GPIO_RESET,
- .gpio_reset_active_low = 0,
- .gpio_pendown = GT801_GPIO_INT,
- .pendown_iomux_name = GPIO4D5_CPUTRACECTL_NAME,
- .resetpin_iomux_name = NULL,
- .pendown_iomux_mode = GPIO4H_GPIO4D5,
- .resetpin_iomux_mode = 0,
-};
-#endif
-
-
-#if defined(CONFIG_TOUCHSCREEN_GT818_IIC)
-#include "../../../drivers/input/touchscreen/gt818_ts.h"
-#define GT818_GPIO_INT RK29_PIN4_PD5
-#define GT818_GPIO_RESET RK29_PIN6_PC3
-static struct gt818_platform_data gt818_info = {
- .model = 818,
- .swap_xy = 0,
- .x_min = 0,
- .x_max = 480,
- .y_min = 0,
- .y_max = 800,
- .gpio_reset = GT818_GPIO_RESET,
- .gpio_reset_active_low = 0,
- .gpio_pendown = GT818_GPIO_INT,
- .pendown_iomux_name = GPIO4D5_CPUTRACECTL_NAME,
- .resetpin_iomux_name = NULL,
- .pendown_iomux_mode = GPIO4H_GPIO4D5,
- .resetpin_iomux_mode = 0,
-};
-#endif
-
-#if defined(CONFIG_TOUCHSCREEN_ILI2102_IIC)
-#include "../../../drivers/input/touchscreen/ili2102_ts.h"
-#define GT801_GPIO_INT RK29_PIN4_PD5
-#define GT801_GPIO_RESET RK29_PIN6_PC3
-static struct ili2102_platform_data ili2102_info = {
- .model = 2102,
- .swap_xy = 0,
- .x_min = 0,
- .x_max = 481,
- .y_min = 0,
- .y_max = 801,
- .gpio_reset = GT801_GPIO_RESET,
- .gpio_reset_active_low = 1,
- .gpio_pendown = GT801_GPIO_INT,
- .pendown_iomux_name = GPIO4D5_CPUTRACECTL_NAME,
- .resetpin_iomux_name = NULL,
- .pendown_iomux_mode = GPIO4H_GPIO4D5,
- .resetpin_iomux_mode = 0,
-};
-#endif
-
-/* EETI_EGALAX touch I2C */
-#if defined (CONFIG_EETI_EGALAX)
-#define TOUCH_RESET_PIN RK29_PIN6_PC3
-#define TOUCH_INT_PIN RK29_PIN4_PD5
-
-static int EETI_EGALAX_init_platform_hw(void)
-{
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_pull_updown(TOUCH_INT_PIN, 1);
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
-
- return 0;
-}
-
-
-static struct eeti_egalax_platform_data eeti_egalax_info = {
- .model= 1003,
- .init_platform_hw= EETI_EGALAX_init_platform_hw,
-
-};
-#endif
-
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN RK29_PIN6_PC4
-
-static int mma8452_init_platform_hw(void)
-{
-
- if(gpio_request(MMA8452_INT_PIN,NULL) != 0){
- gpio_free(MMA8452_INT_PIN);
- printk("mma8452_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_pull_updown(MMA8452_INT_PIN, 1);
- return 0;
-}
-
-
-static struct gsensor_platform_data mma8452_info = {
- .model= 8452,
- .swap_xy = 0,
- .init_platform_hw= mma8452_init_platform_hw,
-
-};
-#endif
-
-/*mpu3050*/
-#if defined (CONFIG_MPU_SENSORS_MPU3050)
-static struct mpu_platform_data mpu3050_data = {
- .int_config = 0x10,
- .orientation = { 1, 0, 0,0, 1, 0, 0, 0, 1 },
-};
-#endif
-
-/* accel */
-#if defined (CONFIG_MPU_SENSORS_KXTF9)
-static struct ext_slave_platform_data inv_mpu_kxtf9_data = {
- .bus = EXT_SLAVE_BUS_SECONDARY,
- .adapt_num = 0,
- .orientation = {1, 0, 0, 0, 1, 0, 0, 0, 1},
-};
-#endif
-
-/* compass */
-#if defined (CONFIG_MPU_SENSORS_AK8975)
-static struct ext_slave_platform_data inv_mpu_ak8975_data = {
- .bus = EXT_SLAVE_BUS_PRIMARY,
- .adapt_num = 0,
- .orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
-};
-#endif
-
-#if defined(CONFIG_GPIO_WM831X)
-struct rk29_gpio_expander_info wm831x_gpio_settinginfo[] = {
- {
- .gpio_num =WM831X_P01,// tp3
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
-
- {
- .gpio_num =WM831X_P02,//tp4
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P03,//tp2
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P04,//tp1
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P05,//tp1
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P06,//tp1
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P07,//tp1
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P08,//tp1
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P09,//tp1
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P10,//tp1
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P11,//tp1
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P12,
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
-};
-
-#endif
-
-
-
-#if defined(CONFIG_MFD_WM831X)
-static struct wm831x *gWm831x;
-int wm831x_pre_init(struct wm831x *parm)
-{
- int ret;
- printk("%s\n", __FUNCTION__);
- gWm831x = parm;
- //ILIM = 900ma
- ret = wm831x_reg_read(parm, WM831X_POWER_STATE) & 0xffff;
- wm831x_reg_write(parm, WM831X_POWER_STATE, (ret&0xfff8) | 0x04);
-
- //BATT_FET_ENA = 1
- wm831x_reg_write(parm,WM831X_SECURITY_KEY,0x9716); // unlock security key
- wm831x_set_bits(parm, WM831X_RESET_CONTROL,0x1000,0x1000);
- ret = wm831x_reg_read(parm, WM831X_RESET_CONTROL) & 0xffff&UNLOCK_SECURITY_KEY;// enternal reset active in sleep
- printk("%s:WM831X_RESET_CONTROL=0x%x\n",__FUNCTION__,ret);
- wm831x_reg_write(parm, WM831X_RESET_CONTROL, ret);
-
-
- wm831x_reg_write(parm,WM831X_SECURITY_KEY,LOCK_SECURITY_KEY); // lock securit
-
-#if 0
- wm831x_set_bits(parm, WM831X_LDO_ENABLE, (1 << 3), 0);
- wm831x_set_bits(parm, WM831X_LDO_ENABLE, (1 << 7), 0);
- printk("%s:disable ldo4 and ldo8 because they are enabled in uboot\n",__FUNCTION__);
-#endif
- return 0;
-}
-int wm831x_post_init(struct wm831x *parm)
-{
- struct regulator *dcdc;
- struct regulator *ldo;
-
- dcdc = regulator_get(NULL, "dcdc3"); // 1th IO
- regulator_set_voltage(dcdc,3000000,3000000);
- regulator_set_suspend_voltage(dcdc, 2800000);
- regulator_enable(dcdc);
- printk("%s set dcdc3=%dmV end\n", __FUNCTION__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo10"); // 1th modem IO
- regulator_set_voltage(ldo,3000000,3000000);
- regulator_set_suspend_voltage(ldo,3000000);
- regulator_enable(ldo);
- printk("%s set ldo10=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- dcdc = regulator_get(NULL, "dcdc2"); // 2th CORE
- regulator_set_voltage(dcdc,1300000,1300000);
- regulator_set_suspend_voltage(dcdc,1000000);
- regulator_enable(dcdc);
- printk("%s set dcdc2=%dmV end\n", __FUNCTION__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- dcdc = regulator_get(NULL, "dcdc1"); // 3th ddr
- regulator_set_voltage(dcdc,1800000,1800000);
- regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(dcdc);
- printk("%s set dcdc1=%dmV end\n", __FUNCTION__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo1"); // 3th nand
- regulator_set_voltage(ldo,1800000,1800000);
- regulator_set_suspend_voltage(ldo,1800000);
- regulator_enable(ldo);
- printk("%s set ldo1=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo4"); // 4th usb
- regulator_set_voltage(ldo,2500000,2500000);
- regulator_set_suspend_voltage(ldo,0000000);
- regulator_enable(ldo);
- printk("%s set ldo4=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo7"); // 5th usb
- regulator_set_voltage(ldo,3300000,3300000);
- regulator_set_suspend_voltage(ldo,3300000);
- regulator_enable(ldo);
- printk("%s set ldo7=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- dcdc = regulator_get(NULL, "dcdc4"); // backlight
- regulator_set_voltage(dcdc,20000000,20000000);
- regulator_set_suspend_voltage(dcdc, 20000000);
- regulator_enable(dcdc);
- printk("%s set dcdc4=%dmV end\n", __FUNCTION__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-#if 1
-
- ldo = regulator_get(NULL, "ldo2"); //lcd
- regulator_set_voltage(ldo,3000000,3000000);
- regulator_set_suspend_voltage(ldo,3000000);
- regulator_enable(ldo);
- printk("%s set ldo2=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
-
-
- ldo = regulator_get(NULL, "ldo5"); //tf
- regulator_set_voltage(ldo,3000000,3000000);
- regulator_set_suspend_voltage(ldo,3000000);
- regulator_enable(ldo);
- printk("%s set ldo5=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo6"); //camera
- regulator_set_voltage(ldo,1800000,1800000);
- regulator_set_suspend_voltage(ldo,1800000);
- regulator_enable(ldo);
- printk("%s set ldo6=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
-
-
-
-#if 0
- ldo = regulator_get(NULL, "ldo3"); //sram
- regulator_set_voltage(ldo,1800000,1800000);
- regulator_set_suspend_voltage(ldo,1800000);
- regulator_enable(ldo);
- printk("%s set ldo3=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
-
-
- ldo = regulator_get(NULL, "ldo8"); //cmmb
- regulator_set_voltage(ldo,1200000,1200000);
- regulator_set_suspend_voltage(ldo,1200000);
- regulator_enable(ldo);
- printk("%s set ldo8=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo9"); //cmmb
- regulator_set_voltage(ldo,3000000,3000000);
- regulator_set_suspend_voltage(ldo,3000000);
- regulator_enable(ldo);
- printk("%s set ldo9=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
-#endif
-
-#endif
-
- ldo = regulator_get(NULL, "ldo11");
- //regulator_enable(ldo);
- printk("%s set ldo11=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
-
-
- return 0;
-}
-
-extern void wm831x_enter_sleep(void);
-extern void wm831x_exit_sleep(void);
-
-void pmu_wm831x_set_suspend_voltage(void)
-{
-
-}
-EXPORT_SYMBOL_GPL(pmu_wm831x_set_suspend_voltage);
-
-void pmu_wm831x_set_resume_voltage(void)
-{
-
-}
-EXPORT_SYMBOL_GPL(pmu_wm831x_set_resume_voltage);
-
-int wm831x_last_deinit(struct wm831x *parm)
-{
- struct regulator* ldo;
-
- printk("%s\n", __FUNCTION__);
-
- ldo = regulator_get(NULL, "ldo1");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo2");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo3");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo4");
- //regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo5");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo6");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo7");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo8");
- //regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo9");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo10");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- return 0;
-}
-
-struct wm831x_backlight_pdata wm831x_backlight_platdata = {
- .isink = 1, /** ISINK to use, 1 or 2 */
- .max_uA = 19484, /** Maximum current to allow */
-};
-
-struct wm831x_backup_pdata wm831x_backup_platdata = {
- .charger_enable = 1,
- .no_constant_voltage = 0, /** Disable constant voltage charging */
- .vlim = 3100, /** Voltage limit in milivolts */
- .ilim = 300, /** Current limit in microamps */
-};
-
-struct wm831x_battery_pdata wm831x_battery_platdata = {
- .enable = 1, /** Enable charging */
- .fast_enable = 1, /** Enable fast charging */
- .off_mask = 1, /** Mask OFF while charging */
- .trickle_ilim = 200, /** Trickle charge current limit, in mA */
- .vsel = 4200, /** Target voltage, in mV */
- .eoc_iterm = 50, /** End of trickle charge current, in mA */
- .fast_ilim = 500, /** Fast charge current limit, in mA */
- .timeout = 480, /** Charge cycle timeout, in minutes */
- .syslo = 3300, /* syslo threshold, in mV*/
- .sysok = 3500, /* sysko threshold, in mV*/
-};
-
-struct wm831x_status_pdata wm831x_status_platdata[WM831X_MAX_STATUS] = {
- {
- .default_src = WM831X_STATUS_OTP,
- .name = "wm831x_status0",
- .default_trigger = "wm831x_otp",
- },
- {
- .default_src = WM831X_STATUS_POWER,
- .name = "wm831x_status1",
- .default_trigger = "wm831x_power",
- },
-};
-
-
-static struct regulator_consumer_supply dcdc1_consumers[] = {
- {
- .supply = "dcdc1",
- }
-};
-static struct regulator_consumer_supply dcdc2_consumers[] = {
- {
- .supply = "dcdc2",
- },
- {
- .supply = "vcore",
- }
-};
-static struct regulator_consumer_supply dcdc3_consumers[] = {
- {
- .supply = "dcdc3",
- }
-};
-static struct regulator_consumer_supply dcdc4_consumers[] = {
- {
- .supply = "dcdc4",
- }
-};
-static struct regulator_consumer_supply epe1_consumers[] = {
- {
- .supply = "epe1",
- }
-};
-static struct regulator_consumer_supply epe2_consumers[] = {
- {
- .supply = "epe2",
- }
-};
-static struct regulator_consumer_supply ldo1_consumers[] = {
- {
- .supply = "ldo1",
- }
-};
-static struct regulator_consumer_supply ldo2_consumers[] = {
- {
- .supply = "ldo2",
- }
-};
-static struct regulator_consumer_supply ldo3_consumers[] = {
- {
- .supply = "ldo3",
- }
-};
-static struct regulator_consumer_supply ldo4_consumers[] = {
- {
- .supply = "ldo4",
- }
-};
-static struct regulator_consumer_supply ldo5_consumers[] = {
- {
- .supply = "ldo5",
- }
-};
-static struct regulator_consumer_supply ldo6_consumers[] = {
- {
- .supply = "ldo6",
- }
-};
-static struct regulator_consumer_supply ldo7_consumers[] = {
- {
- .supply = "ldo7",
- }
-};
-static struct regulator_consumer_supply ldo8_consumers[] = {
- {
- .supply = "ldo8",
- }
-};
-static struct regulator_consumer_supply ldo9_consumers[] = {
- {
- .supply = "ldo9",
- }
-};
-static struct regulator_consumer_supply ldo10_consumers[] = {
- {
- .supply = "ldo10",
- }
-};
-static struct regulator_consumer_supply ldo11_consumers[] = {
- {
- .supply = "ldo11",
- }
-};
-static struct regulator_consumer_supply isink1_consumers[] = {
- {
- .supply = "isink1",
- }
-};
-static struct regulator_consumer_supply isink2_consumers[] = {
- {
- .supply = "isink2",
- }
-};
-
-struct regulator_init_data wm831x_regulator_init_dcdc[WM831X_MAX_DCDC] = {
- {
- .constraints = {
- .name = "DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000,//0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(dcdc1_consumers),
- .consumer_supplies = dcdc1_consumers,
- },
- {
- .constraints = {
- .name = "DCDC2",
- .min_uV = 600000,
- .max_uV = 1800000,//0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(dcdc2_consumers),
- .consumer_supplies = dcdc2_consumers,
- },
- {
- .constraints = {
- .name = "DCDC3",
- .min_uV = 850000,
- .max_uV = 3400000,//0.85-3.4V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(dcdc3_consumers),
- .consumer_supplies = dcdc3_consumers,
- },
- {
- .constraints = {
- .name = "DCDC4",
- .min_uV = 00000000,
- .max_uV = 30000000,//30V/40mA
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(dcdc4_consumers),
- .consumer_supplies = dcdc4_consumers,
- },
-
-};
-struct regulator_init_data wm831x_regulator_init_epe[WM831X_MAX_EPE] = {
- {
- .constraints = {
- .name = "EPE1",
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(epe1_consumers),
- .consumer_supplies = epe1_consumers,
- },
- {
- .constraints = {
- .name = "EPE2",
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(epe2_consumers),
- .consumer_supplies = epe2_consumers,
- },
-};
-
-struct regulator_init_data wm831x_regulator_init_ldo[WM831X_MAX_LDO] = {
- {
- .constraints = {
- .name = "LDO1",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo1_consumers),
- .consumer_supplies = ldo1_consumers,
- },
- {
- .constraints = {
- .name = "LDO2",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
- .consumer_supplies = ldo2_consumers,
- },
- {
- .constraints = {
- .name = "LDO3",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo3_consumers),
- .consumer_supplies = ldo3_consumers,
- },
- {
- .constraints = {
- .name = "LDO4",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo4_consumers),
- .consumer_supplies = ldo4_consumers,
- },
- {
- .constraints = {
- .name = "LDO5",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo5_consumers),
- .consumer_supplies = ldo5_consumers,
- },
- {
- .constraints = {
- .name = "LDO6",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo6_consumers),
- .consumer_supplies = ldo6_consumers,
- },
- {
- .constraints = {
- .name = "LDO7",
- .min_uV = 1000000,
- .max_uV = 3500000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo7_consumers),
- .consumer_supplies = ldo7_consumers,
- },
- {
- .constraints = {
- .name = "LDO8",
- .min_uV = 1000000,
- .max_uV = 3500000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo8_consumers),
- .consumer_supplies = ldo8_consumers,
- },
- {
- .constraints = {
- .name = "LDO9",
- .min_uV = 1000000,
- .max_uV = 3500000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo9_consumers),
- .consumer_supplies = ldo9_consumers,
- },
- {
- .constraints = {
- .name = "LDO10",
- .min_uV = 1000000,
- .max_uV = 3500000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo10_consumers),
- .consumer_supplies = ldo10_consumers,
- },
- {
- .constraints = {
- .name = "LDO11",
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo11_consumers),
- .consumer_supplies = ldo11_consumers,
- },
-};
-
-struct regulator_init_data wm831x_regulator_init_isink[WM831X_MAX_ISINK] = {
- {
- .constraints = {
- .name = "ISINK1",
- .min_uA = 00000,
- .max_uA = 40000,
- .always_on = true,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_CURRENT,
- },
- .num_consumer_supplies = ARRAY_SIZE(isink1_consumers),
- .consumer_supplies = isink1_consumers,
- },
- {
- .constraints = {
- .name = "ISINK2",
- .min_uA = 0000000,
- .max_uA = 0000000,
- .apply_uV = false,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_CURRENT,
- },
- .num_consumer_supplies = ARRAY_SIZE(isink2_consumers),
- .consumer_supplies = isink2_consumers,
- },
-};
-
-static int wm831x_checkrange(int start,int num,int val)
-{
- if((val<(start+num))&&(val>=start))
- return 0;
- else
- return -1;
-}
-
-static int wm831x_init_pin_type(struct wm831x *wm831x)
-{
-#if 1
- struct wm831x_pdata *pdata = wm831x->dev->platform_data;
- struct rk29_gpio_expander_info *wm831x_gpio_settinginfo;
- uint16_t offset = 0;
- uint16_t wm831x_settingpin_num = 0;
- uint16_t ret = 0;
- int i = 0;
-
- if(wm831x)
- {
- wm831x_gpio_settinginfo=pdata->settinginfo;
- if(wm831x_gpio_settinginfo)
- {
- wm831x_settingpin_num = pdata->settinginfolen;
- for(i=0;i<wm831x_settingpin_num;i++)
- {
- if(!wm831x_checkrange(pdata->gpio_base,pdata->gpio_pin_num,wm831x_gpio_settinginfo[i].gpio_num))
- {
- offset = wm831x_gpio_settinginfo[i].gpio_num - pdata->gpio_base;
-
- if(wm831x_gpio_settinginfo[i].pin_type==GPIO_IN)
- {
- wm831x_set_bits(wm831x,(WM831X_GPIO1_CONTROL+offset), WM831X_GPN_DIR_MASK|WM831X_GPN_TRI_MASK, 1<<WM831X_GPN_DIR_SHIFT|1<<WM831X_GPN_TRI_SHIFT);
- }
- else
- {
- wm831x_set_bits(wm831x,(WM831X_GPIO1_CONTROL+offset), WM831X_GPN_DIR_MASK|WM831X_GPN_TRI_MASK, 1<<WM831X_GPN_TRI_SHIFT);
- if(wm831x_gpio_settinginfo[i].pin_value==GPIO_HIGH)
- {
- wm831x_set_bits(wm831x, WM831X_GPIO_LEVEL, (1 << offset),(1 << offset));
- }
- else
- {
- wm831x_set_bits(wm831x, WM831X_GPIO_LEVEL, (1 << offset),(0 << offset));
- }
- }
-
- }
- }
- }
- }
-
- for(i=0;i<pdata->gpio_pin_num;i++)
- {
- wm831x_set_bits(wm831x,(WM831X_GPIO1_CONTROL+i),
- WM831X_GPN_PULL_MASK|WM831X_GPN_POL_MASK|WM831X_GPN_OD_MASK|WM831X_GPN_TRI_MASK,
- 1<<WM831X_GPN_POL_SHIFT|1<<WM831X_GPN_TRI_SHIFT);
- ret = wm831x_reg_read(wm831x, WM831X_GPIO1_CONTROL+i);
- printk("Gpio%d Pin Configuration = %x\n",i,ret);
- }
-#endif
- return 0;
-}
-
-/*
- * GPIO Buttons
- */
-#if defined(CONFIG_KEYBOARD_WM831X_GPIO)
-static struct wm831x_gpio_keys_button wm831x_gpio_buttons[] = {
-{
- .code = KEY_MEDIA,
- .gpio = TCA6424_P21,
- .active_low = 1,
- .desc = "media",
- .wakeup = 0,
- .debounce_interval = 120,
-},
-{
- .code= KEY_VOLUMEUP,
- .gpio= WM831X_P05,
- .active_low= 1,
- .desc= "volume_up",
- .wakeup= 0,
-},
-{
- .code= KEY_CAMERA,
- .gpio= WM831X_P06,
- .active_low= 1,
- .desc= "camera",
- .wakeup= 0,
-},
-{
- .code= KEY_VOLUMEDOWN,
- .gpio= WM831X_P07,
- .active_low= 1,
- .desc= "volume_down",
- .wakeup= 0,
-},
-{
- .code= KEY_END,
- .gpio= WM831X_P09,
- .active_low= 1,
- .desc= "enter",
- .wakeup= 0,
-},
-{
- .code= KEY_MENU,
- .gpio= WM831X_P10,
- .active_low= 1,
- .desc= "menu",
- .wakeup= 0,
-},
-{
- .code= KEY_SEND,
- .gpio= WM831X_P11,
- .active_low= 1,
- .desc= "esc",
- .wakeup= 0,
-},
-{
- .code= KEY_BACK,
- .gpio= WM831X_P12,
- .active_low= 1,
- .desc= "home",
- .wakeup= 0,
-},
-};
-
-struct wm831x_gpio_keys_pdata wm831x_gpio_keys_platdata = {
- .buttons = wm831x_gpio_buttons,
- .nbuttons = ARRAY_SIZE(wm831x_gpio_buttons),
-};
-
-#endif
-struct wm831x_pdata wm831x_platdata = {
- /** Called before subdevices are set up */
- .pre_init= wm831x_pre_init,
- /** Called after subdevices are set up */
- .post_init = wm831x_post_init,
- /** Called before subdevices are power down */
- .last_deinit = wm831x_last_deinit,
-
-#if defined(CONFIG_GPIO_WM831X)
- .gpio_base=WM831X_GPIO_EXPANDER_BASE,
- .gpio_pin_num=WM831X_TOTOL_GPIO_NUM,
- .settinginfo=wm831x_gpio_settinginfo,
- .settinginfolen=ARRAY_SIZE(wm831x_gpio_settinginfo),
- .pin_type_init = wm831x_init_pin_type,
- .irq_base= NR_AIC_IRQS + 7*NUM_GROUP,
-#endif
-
- .backlight = &wm831x_backlight_platdata,
-
- .backup = &wm831x_backup_platdata,
-
- .battery = &wm831x_battery_platdata,
- //.wm831x_touch_pdata = NULL,
- //.watchdog = NULL,
-
-#if defined(CONFIG_KEYBOARD_WM831X_GPIO)
- .gpio_keys = &wm831x_gpio_keys_platdata,
-#endif
-
- /** LED1 = 0 and so on */
- .status = {&wm831x_status_platdata[0], &wm831x_status_platdata[1]},
-
- /** DCDC1 = 0 and so on */
- .dcdc = {&wm831x_regulator_init_dcdc[0], &wm831x_regulator_init_dcdc[1], &wm831x_regulator_init_dcdc[2], &wm831x_regulator_init_dcdc[3]},
-
- /** EPE1 = 0 and so on */
- .epe = {&wm831x_regulator_init_epe[0], &wm831x_regulator_init_epe[1]},
-
- /** LDO1 = 0 and so on */
- .ldo = {&wm831x_regulator_init_ldo[0], &wm831x_regulator_init_ldo[1], &wm831x_regulator_init_ldo[2], &wm831x_regulator_init_ldo[3],
- &wm831x_regulator_init_ldo[4], &wm831x_regulator_init_ldo[5], &wm831x_regulator_init_ldo[6], &wm831x_regulator_init_ldo[7],
- &wm831x_regulator_init_ldo[8], &wm831x_regulator_init_ldo[9], &wm831x_regulator_init_ldo[10]},
-
- /** ISINK1 = 0 and so on*/
- .isink = {&wm831x_regulator_init_isink[0], &wm831x_regulator_init_isink[1]},
-};
-#endif
-
-#if defined(CONFIG_RK29_GPIO_SUSPEND)
-static void gpio_set_request(void)
-{
- gpio_request(RK29_PIN6_PA0, NULL);
- gpio_request(RK29_PIN6_PA1, NULL);
- gpio_request(RK29_PIN6_PA2, NULL);
- gpio_request(RK29_PIN6_PA3, NULL);
- gpio_request(RK29_PIN6_PA4, NULL);
- gpio_request(RK29_PIN6_PA5, NULL);
- gpio_request(RK29_PIN6_PA6, NULL);
-
- gpio_request(RK29_PIN2_PA5, NULL);
- gpio_request(RK29_PIN2_PA4, NULL);
- gpio_request(RK29_PIN2_PB0, NULL);
- gpio_request(RK29_PIN2_PB1, NULL);
- gpio_request(RK29_PIN2_PB2, NULL);
- gpio_request(RK29_PIN2_PB3, NULL);
-
- gpio_request(RK29_PIN1_PA4, NULL);
- gpio_request(RK29_PIN1_PA3, NULL);
-
- gpio_request(RK29_PIN2_PC7, NULL);
- gpio_request(RK29_PIN2_PC6, NULL);
- gpio_request(RK29_PIN2_PC5, NULL);
- gpio_request(RK29_PIN2_PC4, NULL);
- gpio_request(RK29_PIN2_PC3, NULL);
- gpio_request(RK29_PIN2_PC2, NULL);
- gpio_request(RK29_PIN2_PC1, NULL);
- gpio_request(RK29_PIN2_PC0, NULL);
-}
-
-static void gpio_set_free(void)
-{
- gpio_free(RK29_PIN6_PA0);
- gpio_free(RK29_PIN6_PA1);
- gpio_free(RK29_PIN6_PA2);
- gpio_free(RK29_PIN6_PA3);
- gpio_free(RK29_PIN6_PA4);
- gpio_free(RK29_PIN6_PA5);
- gpio_free(RK29_PIN6_PA6);
-
- gpio_free(RK29_PIN2_PA5);
- gpio_free(RK29_PIN2_PA4);
- gpio_free(RK29_PIN2_PB0);
- gpio_free(RK29_PIN2_PB1);
- gpio_free(RK29_PIN2_PB2);
- gpio_free(RK29_PIN2_PB3);
-
- gpio_free(RK29_PIN1_PA4);
- gpio_free(RK29_PIN1_PA3);
-
- gpio_free(RK29_PIN2_PC7);
- gpio_free(RK29_PIN2_PC6);
- gpio_free(RK29_PIN2_PC5);
- gpio_free(RK29_PIN2_PC4);
- gpio_free(RK29_PIN2_PC3);
- gpio_free(RK29_PIN2_PC2);
- gpio_free(RK29_PIN2_PC1);
- gpio_free(RK29_PIN2_PC0);
-}
-
-static void rk29_keygpio_suspend(void)
-{
- gpio_pull_updown(RK29_PIN6_PA0, 0);
- gpio_pull_updown(RK29_PIN6_PA1, 0);
- gpio_pull_updown(RK29_PIN6_PA2, 0);
- gpio_pull_updown(RK29_PIN6_PA3, 0);
- gpio_pull_updown(RK29_PIN6_PA4, 0);
- gpio_pull_updown(RK29_PIN6_PA5, 0);
- gpio_pull_updown(RK29_PIN6_PA6, 0);//key pullup/pulldown disable
-
- gpio_pull_updown(RK29_PIN2_PA4, 0);
- gpio_pull_updown(RK29_PIN2_PA5, 0);
- gpio_pull_updown(RK29_PIN2_PB0, 0);
- gpio_pull_updown(RK29_PIN2_PB1, 0);
- gpio_pull_updown(RK29_PIN2_PB2, 0);
- gpio_pull_updown(RK29_PIN2_PB3, 0);
-}
-
-static void rk29_keygpio_resume(void)
-{
- gpio_pull_updown(RK29_PIN6_PA0, 1);
- gpio_pull_updown(RK29_PIN6_PA1, 1);
- gpio_pull_updown(RK29_PIN6_PA2, 1);
- gpio_pull_updown(RK29_PIN6_PA3, 1);
- gpio_pull_updown(RK29_PIN6_PA4, 1);
- gpio_pull_updown(RK29_PIN6_PA5, 1);
- gpio_pull_updown(RK29_PIN6_PA6, 1);//key pullup/pulldown enable
-
- gpio_pull_updown(RK29_PIN2_PA4, 1);
- gpio_pull_updown(RK29_PIN2_PA5, 1);
- gpio_pull_updown(RK29_PIN2_PB0, 1);
- gpio_pull_updown(RK29_PIN2_PB1, 1);
- gpio_pull_updown(RK29_PIN2_PB2, 1);
- gpio_pull_updown(RK29_PIN2_PB3, 1);
-}
-
-static void spi_gpio_suspend(void)
-{
- rk29_mux_api_set(GPIO1A4_EMMCWRITEPRT_SPI0CS1_NAME,GPIO1L_GPIO1A4); //set iomux is gpio mode
- rk29_mux_api_set(GPIO1A3_EMMCDETECTN_SPI1CS1_NAME,GPIO1L_GPIO1A3);
-
- rk29_mux_api_set(GPIO2C7_SPI1RXD_NAME,GPIO2H_GPIO2C7);
- rk29_mux_api_set(GPIO2C6_SPI1TXD_NAME,GPIO2H_GPIO2C6);
- //rk29_mux_api_set(GPIO2C5_SPI1CSN0_NAME,GPIO2H_GPIO2C5);
- rk29_mux_api_set(GPIO2C4_SPI1CLK_NAME,GPIO2H_GPIO2C4);
- rk29_mux_api_set(GPIO2C3_SPI0RXD_NAME,GPIO2H_GPIO2C3);
- rk29_mux_api_set(GPIO2C2_SPI0TXD_NAME,GPIO2H_GPIO2C2);
- rk29_mux_api_set(GPIO2C1_SPI0CSN0_NAME,GPIO2H_GPIO2C1);
- rk29_mux_api_set(GPIO2C0_SPI0CLK_NAME,GPIO2H_GPIO2C0);
-
- gpio_direction_input(RK29_PIN1_PA4); //set gpio is input
- gpio_direction_input(RK29_PIN1_PA3);
- gpio_direction_input(RK29_PIN2_PC7);
- gpio_direction_input(RK29_PIN2_PC6);
- // gpio_direction_input(RK29_PIN2_PC5);
- gpio_direction_input(RK29_PIN2_PC4);
- gpio_direction_input(RK29_PIN2_PC3);
- gpio_direction_input(RK29_PIN2_PC2);
- gpio_direction_input(RK29_PIN2_PC1);
- gpio_direction_input(RK29_PIN2_PC0);
-
- gpio_pull_updown(RK29_PIN1_PA4, 0); //set gpio pullup/down disable
- gpio_pull_updown(RK29_PIN1_PA3, 0);
-
- gpio_pull_updown(RK29_PIN2_PC7, 0);
- gpio_pull_updown(RK29_PIN2_PC6, 0);
- //gpio_pull_updown(RK29_PIN2_PC5, 0);
- gpio_pull_updown(RK29_PIN2_PC4, 0);
- gpio_pull_updown(RK29_PIN2_PC3, 0);
- gpio_pull_updown(RK29_PIN2_PC2, 0);
- gpio_pull_updown(RK29_PIN2_PC1, 0);
- gpio_pull_updown(RK29_PIN2_PC0, 0);
-}
-
-static void spi_gpio_resume(void)
-{
- gpio_pull_updown(RK29_PIN1_PA4, 1); //set gpio pullup/down enable
- gpio_pull_updown(RK29_PIN1_PA3, 1);
-
- gpio_pull_updown(RK29_PIN2_PC7, 1);
- gpio_pull_updown(RK29_PIN2_PC6, 1);
- //gpio_pull_updown(RK29_PIN2_PC5, 1);
- gpio_pull_updown(RK29_PIN2_PC4, 1);
- gpio_pull_updown(RK29_PIN2_PC3, 1);
- gpio_pull_updown(RK29_PIN2_PC2, 1);
- gpio_pull_updown(RK29_PIN2_PC1, 1);
- gpio_pull_updown(RK29_PIN2_PC0, 1);
-
- rk29_mux_api_set(GPIO1A4_EMMCWRITEPRT_SPI0CS1_NAME,GPIO1L_SPI0_CSN1); //set iomux is spi mode
- rk29_mux_api_set(GPIO1A3_EMMCDETECTN_SPI1CS1_NAME,GPIO1L_SPI1_CSN1);
-
- rk29_mux_api_set(GPIO2C7_SPI1RXD_NAME,GPIO2H_SPI1_RXD);
- rk29_mux_api_set(GPIO2C6_SPI1TXD_NAME,GPIO2H_SPI1_TXD);
- //rk29_mux_api_set(GPIO2C5_SPI1CSN0_NAME,GPIO2H_SPI1_CSN0);
- rk29_mux_api_set(GPIO2C4_SPI1CLK_NAME, GPIO2H_SPI1_CLK);
- rk29_mux_api_set(GPIO2C3_SPI0RXD_NAME,GPIO2H_SPI0_RXD);
- rk29_mux_api_set(GPIO2C2_SPI0TXD_NAME,GPIO2H_SPI0_TXD);
- rk29_mux_api_set(GPIO2C1_SPI0CSN0_NAME,GPIO2H_SPI0_CSN0);
- rk29_mux_api_set(GPIO2C0_SPI0CLK_NAME,GPIO2H_SPI0_CLK);
-}
-
-void rk29_setgpio_suspend_board(void)
-{
- gpio_set_request();
- rk29_keygpio_suspend();
- spi_gpio_suspend();
- gpio_set_free();
-}
-
-void rk29_setgpio_resume_board(void)
-{
- gpio_set_request();
- rk29_keygpio_resume();
- spi_gpio_resume();
- gpio_set_free();
-}
-#endif
-
-#if defined(CONFIG_RK29_GPS)
-
-#define RK29_GPS_POWER_PIN RK29_PIN6_PB2
-#define RK29_GPS_RESET_PIN RK29_PIN6_PC1
-
-int rk29_gps_power_up(void)
-{
- printk("%s \n", __FUNCTION__);
-
- gpio_request(RK29_GPS_POWER_PIN, NULL);
- gpio_direction_output(RK29_GPS_POWER_PIN, GPIO_HIGH);
-
- return 0;
-}
-
-int rk29_gps_power_down(void)
-{
- printk("%s \n", __FUNCTION__);
-
- gpio_request(RK29_GPS_POWER_PIN, NULL);
- gpio_direction_output(RK29_GPS_POWER_PIN, GPIO_LOW);
-
- return 0;
-}
-
-int rk29_gps_reset_set(int level)
-{
- gpio_request(RK29_GPS_RESET_PIN, NULL);
- if (level)
- gpio_direction_output(RK29_GPS_RESET_PIN, GPIO_HIGH);
- else
- gpio_direction_output(RK29_GPS_RESET_PIN, GPIO_LOW);
-
- return 0;
-}
-
-struct rk29_gps_data rk29_gps_info = {
- .power_up = rk29_gps_power_up,
- .power_down = rk29_gps_power_down,
- .reset = rk29_gps_reset_set,
- .uart_id = 3,
-};
-
-struct platform_device rk29_device_gps = {
- .name = "rk29_gps",
- .id = -1,
- .dev = {
- .platform_data = &rk29_gps_info,
- }
- };
-#endif
-
-
-/*****************************************************************************************
- * wm8994 codec
- * author: qjb@rock-chips.com
- *****************************************************************************************/
-#if defined(CONFIG_MFD_WM8994)
-static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = {
- REGULATOR_SUPPLY("DBVDD", "5-001a"),
- REGULATOR_SUPPLY("AVDD2", "5-001a"),
- REGULATOR_SUPPLY("CPVDD", "5-001a"),
-};
-
-static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = {
- REGULATOR_SUPPLY("SPKVDD1", "5-001a"),
- REGULATOR_SUPPLY("SPKVDD2", "5-001a"),
-};
-
-static struct regulator_init_data wm8994_fixed_voltage0_init_data = {
- .constraints = {
- .always_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage0_supplies),
- .consumer_supplies = wm8994_fixed_voltage0_supplies,
-};
-
-static struct regulator_init_data wm8994_fixed_voltage1_init_data = {
- .constraints = {
- .always_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage1_supplies),
- .consumer_supplies = wm8994_fixed_voltage1_supplies,
-};
-
-static struct fixed_voltage_config wm8994_fixed_voltage0_config = {
- .supply_name = "VCC_1.8V_PDA",
- .microvolts = 1800000,
- .gpio = -EINVAL,
- .init_data = &wm8994_fixed_voltage0_init_data,
-};
-
-static struct fixed_voltage_config wm8994_fixed_voltage1_config = {
- .supply_name = "V_BAT",
- .microvolts = 3700000,
- .gpio = -EINVAL,
- .init_data = &wm8994_fixed_voltage1_init_data,
-};
-
-static struct platform_device wm8994_fixed_voltage0 = {
- .name = "reg-fixed-voltage",
- .id = 0,
- .dev = {
- .platform_data = &wm8994_fixed_voltage0_config,
- },
-};
-
-static struct platform_device wm8994_fixed_voltage1 = {
- .name = "reg-fixed-voltage",
- .id = 1,
- .dev = {
- .platform_data = &wm8994_fixed_voltage1_config,
- },
-};
-
-static struct regulator_consumer_supply wm8994_avdd1_supply =
- REGULATOR_SUPPLY("AVDD1", "5-001a");
-
-static struct regulator_consumer_supply wm8994_dcvdd_supply =
- REGULATOR_SUPPLY("DCVDD", "5-001a");
-
-
-
-static struct regulator_init_data wm8994_ldo1_data = {
- .constraints = {
- .name = "AVDD1_3.0V",
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = 1,
- .consumer_supplies = &wm8994_avdd1_supply,
-};
-
-static struct regulator_init_data wm8994_ldo2_data = {
- .constraints = {
- .name = "DCVDD_1.0V",
- },
- .num_consumer_supplies = 1,
- .consumer_supplies = &wm8994_dcvdd_supply,
-};
-
-static struct wm8994_pdata wm8994_platform_data = {
-#if defined (CONFIG_GPIO_WM8994)
- .gpio_base = WM8994_GPIO_EXPANDER_BASE,
- //Fill value to initialize the GPIO
-// .gpio_defaults ={},
- /* configure gpio1 function: 0x0001(Logic level input/output) */
-// .gpio_defaults[0] = 0x0001,
- /* configure gpio3/4/5/7 function for AIF2 voice */
- .gpio_defaults[2] = 0x2100,
- .gpio_defaults[3] = 0x2100,
- .gpio_defaults[4] = 0xA100,
-// .gpio_defaults[6] = 0x0100,
- /* configure gpio8/9/10/11 function for AIF3 BT */
- .gpio_defaults[7] = 0xA100,
- .gpio_defaults[8] = 0x2100,
- .gpio_defaults[9] = 0x2100,
- .gpio_defaults[10] = 0x2100,
-#endif
-
- .ldo[0] = { RK29_PIN5_PA1, NULL, &wm8994_ldo1_data }, /* XM0FRNB_2 */
- .ldo[1] = { 0, NULL, &wm8994_ldo2_data },
-
- .micdet_irq = 0,
- .irq_base = 0,
-};
-#endif
-
-#ifdef CONFIG_RK_HEADSET_DET
-#define HEADSET_GPIO RK29_PIN4_PD2
-struct rk_headset_pdata rk_headset_info = {
- .Headset_gpio = RK29_PIN4_PD2,
- .headset_in_type= HEADSET_IN_HIGH,
- .Hook_gpio = RK29_PIN4_PD1,//Detection Headset--Must be set
- .hook_key_code = KEY_MEDIA,
-};
-
-struct platform_device rk_device_headset = {
- .name = "rk_headsetdet",
- .id = 0,
- .dev = {
- .platform_data = &rk_headset_info,
- }
-};
-#endif
-
-#if defined(CONFIG_GS_L3G4200D)
-
-#include <linux/l3g4200d.h>
-#define L3G4200D_INT_PIN RK29_PIN5_PA3
-
-static int l3g4200d_init_platform_hw(void)
-{
- if (gpio_request(L3G4200D_INT_PIN, NULL) != 0) {
- gpio_free(L3G4200D_INT_PIN);
- printk("%s: request l3g4200d int pin error\n", __func__);
- return -EIO;
- }
- gpio_pull_updown(L3G4200D_INT_PIN, 1);
- return 0;
-}
-
-static struct l3g4200d_platform_data l3g4200d_info = {
- .fs_range = 1,
-
- .axis_map_x = 0,
- .axis_map_y = 1,
- .axis_map_z = 2,
-
- .negate_x = 1,
- .negate_y = 1,
- .negate_z = 0,
-
- .init = l3g4200d_init_platform_hw,
-};
-
-#endif
-
-/*****************************************************************************************
- * i2c devices
- * author: kfx@rock-chips.com
-*****************************************************************************************/
-static int rk29_i2c0_io_init(void)
-{
-#ifdef CONFIG_RK29_I2C0_CONTROLLER
- rk29_mux_api_set(GPIO2B7_I2C0SCL_NAME, GPIO2L_I2C0_SCL);
- rk29_mux_api_set(GPIO2B6_I2C0SDA_NAME, GPIO2L_I2C0_SDA);
-#else
- rk29_mux_api_set(GPIO2B7_I2C0SCL_NAME, GPIO2L_GPIO2B7);
- rk29_mux_api_set(GPIO2B6_I2C0SDA_NAME, GPIO2L_GPIO2B6);
-#endif
- return 0;
-}
-
-static int rk29_i2c1_io_init(void)
-{
-#ifdef CONFIG_RK29_I2C1_CONTROLLER
- rk29_mux_api_set(GPIO1A7_I2C1SCL_NAME, GPIO1L_I2C1_SCL);
- rk29_mux_api_set(GPIO1A6_I2C1SDA_NAME, GPIO1L_I2C1_SDA);
-#else
- rk29_mux_api_set(GPIO1A7_I2C1SCL_NAME, GPIO1L_GPIO1A7);
- rk29_mux_api_set(GPIO1A6_I2C1SDA_NAME, GPIO1L_GPIO1A6);
-#endif
- return 0;
-}
-static int rk29_i2c2_io_init(void)
-{
-#ifdef CONFIG_RK29_I2C2_CONTROLLER
- rk29_mux_api_set(GPIO5D4_I2C2SCL_NAME, GPIO5H_I2C2_SCL);
- rk29_mux_api_set(GPIO5D3_I2C2SDA_NAME, GPIO5H_I2C2_SDA);
-#else
- rk29_mux_api_set(GPIO5D4_I2C2SCL_NAME, GPIO5H_GPIO5D4);
- rk29_mux_api_set(GPIO5D3_I2C2SDA_NAME, GPIO5H_GPIO5D3);
-#endif
- return 0;
-}
-
-static int rk29_i2c3_io_init(void)
-{
-#ifdef CONFIG_RK29_I2C3_CONTROLLER
- rk29_mux_api_set(GPIO2B5_UART3RTSN_I2C3SCL_NAME, GPIO2L_I2C3_SCL);
- rk29_mux_api_set(GPIO2B4_UART3CTSN_I2C3SDA_NAME, GPIO2L_I2C3_SDA);
-#else
- rk29_mux_api_set(GPIO2B5_UART3RTSN_I2C3SCL_NAME, GPIO2L_GPIO2B5);
- rk29_mux_api_set(GPIO2B4_UART3CTSN_I2C3SDA_NAME, GPIO2L_GPIO2B4);
-#endif
- return 0;
-}
-#ifdef CONFIG_RK29_I2C0_CONTROLLER
-struct rk29_i2c_platform_data default_i2c0_data = {
- .bus_num = 0,
- .flags = 0,
- .slave_addr = 0xff,
- .scl_rate = 400*1000,
- .mode = I2C_MODE_IRQ,
- .io_init = rk29_i2c0_io_init,
-};
-#else
-struct i2c_gpio_platform_data default_i2c0_data = {
- .sda_pin = RK29_PIN2_PB6,
- .scl_pin = RK29_PIN2_PB7,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(200),
- .bus_num = 0,
- .io_init = rk29_i2c0_io_init,
-};
-#endif
-#ifdef CONFIG_RK29_I2C1_CONTROLLER
-struct rk29_i2c_platform_data default_i2c1_data = {
- .bus_num = 1,
- .flags = 0,
- .slave_addr = 0xff,
- .scl_rate = 400*1000,
- .mode = I2C_MODE_IRQ,
- .io_init = rk29_i2c1_io_init,
-};
-#else
-struct i2c_gpio_platform_data default_i2c1_data = {
- .sda_pin = RK29_PIN1_PA6,
- .scl_pin = RK29_PIN1_PA7,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(200),
- .bus_num = 1,
- .io_init = rk29_i2c1_io_init,
-};
-#endif
-#ifdef CONFIG_RK29_I2C2_CONTROLLER
-struct rk29_i2c_platform_data default_i2c2_data = {
- .bus_num = 2,
- .flags = 0,
- .slave_addr = 0xff,
- .scl_rate = 400*1000,
- .mode = I2C_MODE_IRQ,
- .io_init = rk29_i2c2_io_init,
-};
-#else
-struct i2c_gpio_platform_data default_i2c2_data = {
- .sda_pin = RK29_PIN5_PD3,
- .scl_pin = RK29_PIN5_PD4,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(200),
- .bus_num = 2,
- .io_init = rk29_i2c2_io_init,
-};
-#endif
-#ifdef CONFIG_RK29_I2C3_CONTROLLER
-struct rk29_i2c_platform_data default_i2c3_data = {
- .bus_num = 3,
- .flags = 0,
- .slave_addr = 0xff,
- .scl_rate = 400*1000,
- .mode = I2C_MODE_IRQ,
- .io_init = rk29_i2c3_io_init,
-};
-#else
-struct i2c_gpio_platform_data default_i2c3_data = {
- .sda_pin = RK29_PIN5_PB5,
- .scl_pin = RK29_PIN5_PB4,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(200),
- .bus_num = 3,
- .io_init = rk29_i2c3_io_init,
-};
-#endif
-
-#if defined (CONFIG_ANX7150)
-struct hdmi_platform_data anx7150_data = {
- //.io_init = anx7150_io_init,
-};
-#endif
-#ifdef CONFIG_I2C0_RK29
-static struct i2c_board_info __initdata board_i2c0_devices[] = {
-#if defined (CONFIG_RK1000_CONTROL)
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_WM8900)
- {
- .type = "wm8900",
- .addr = 0x1A,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_WM8994)
- {
- .type = "wm8994",
- .addr = 0x1a,
- .flags = 0,
- #if defined(CONFIG_MFD_WM8994)
- .platform_data = &wm8994_platform_data,
- #endif
- },
-#endif
-#if defined (CONFIG_BATTERY_STC3100)
- {
- .type = "stc3100",
- .addr = 0x70,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_BATTERY_BQ27510)
- {
- .type = "bq27510",
- .addr = 0x55,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_RTC_HYM8563)
- {
- .type = "rtc_hym8563",
- .addr = 0x51,
- .flags = 0,
- .irq = RK29_PIN0_PA1,
- },
-#endif
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1c,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8973)
- {
- .type = "ak8973",
- .addr = 0x1d,
- .flags = 0,
- .irq = RK29_PIN6_PC5,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK29_PIN6_PC5,
- },
-#endif
-#if defined (CONFIG_INPUT_LPSENSOR_ISL29028)
- {
- .type = "isl29028",
- .addr = 0x44,
- .flags = 0,
- .irq = RK29_PIN4_PD3,
- },
-#endif
-#if defined (CONFIG_ANX7150)
- {
- .type = "anx7150",
- .addr = 0x39, //0x39, 0x3d
- .flags = 0,
- .irq = RK29_PIN2_PA3,
- .platform_data = &anx7150_data,
- },
-#endif
-#if defined (CONFIG_GS_L3G4200D)
- {
- .type = "gs_l3g4200d",
- .addr = 0x69,
- .flags = 0,
- .irq = L3G4200D_INT_PIN,
- .platform_data = &l3g4200d_info,
- },
-#endif
-#if defined (CONFIG_MPU_SENSORS_MPU3050)
- {
- .type = "mpu3050",
- .addr = 0x68,
- .flags = 0,
- .irq = RK29_PIN4_PC4,
- .platform_data = &mpu3050_data,
- },
-#endif
-#if defined (CONFIG_MPU_SENSORS_KXTF9)
- {
- .type = "kxtf9",
- .addr = 0x0f,
- .flags = 0,
- .irq = RK29_PIN6_PC4,
- .platform_data = &inv_mpu_kxtf9_data,
- },
-#endif
-#if defined (CONFIG_MPU_SENSORS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK29_PIN6_PC5,
- .platform_data = &inv_mpu_ak8975_data,
- },
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C1_RK29
-static struct i2c_board_info __initdata board_i2c1_devices[] = {
-#if defined (CONFIG_RK1000_CONTROL1)
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C2_RK29
-static struct i2c_board_info __initdata board_i2c2_devices[] = {
-#if defined (CONFIG_TOUCHSCREEN_GT801_IIC)
-{
- .type = "gt801_ts",
- .addr = 0x55,
- .flags = 0,
- .irq = RK29_PIN4_PD5,
- .platform_data = >801_info,
-},
-#endif
-
-#if defined (CONFIG_TOUCHSCREEN_GT818_IIC)
-{
- .type = "gt818_ts",
- .addr = 0x5d,
- .flags = 0,
- .irq = RK29_PIN4_PD5,
- .platform_data = >818_info,
-},
-#endif
-
-#if defined (CONFIG_TOUCHSCREEN_ILI2102_IIC)
-{
- .type = "ili2102_ts",
- .addr = 0x41,
- .flags = I2C_M_NEED_DELAY,
- .udelay = 600,
- .irq = RK29_PIN4_PD5,
- .platform_data = &ili2102_info,
-},
-#endif
-
-#if defined (CONFIG_MFD_WM831X_I2C)
-{
- .type = "wm8310",
- .addr = 0x34,
- .flags = 0,
- .irq = RK29_PIN4_PD0,
- .platform_data = &wm831x_platdata,
-},
-#endif
-#if defined (CONFIG_HANNSTAR_P1003)
- {
- .type = "p1003_touch",
- .addr = 0x04,
- .flags = 0,
- .irq = RK29_PIN0_PA2,
- .platform_data = &p1003_info,
- },
-#endif
-#if defined (CONFIG_EETI_EGALAX)
- {
- .type = "egalax_i2c",
- .addr = 0x04,
- .flags = 0,
- .irq = RK29_PIN4_PD5,
- .platform_data = &eeti_egalax_info,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK29
-static struct i2c_board_info __initdata board_i2c3_devices[] = {
-};
-#endif
-
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#define CONFIG_SENSOR_POWER_IOCTL_USR 0
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_RESET_IOCTL_USR
-static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
-static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-#include "../../../drivers/media/video/rk29_camera.c"
-#endif
-
-/*****************************************************************************************
- * backlight devices
- * author: nzy@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- /*
- GPIO1B5_PWM0_NAME, GPIO1L_PWM0
- GPIO5D2_PWM1_UART1SIRIN_NAME, GPIO5H_PWM1
- GPIO2A3_SDMMC0WRITEPRT_PWM2_NAME, GPIO2L_PWM2
- GPIO1A5_EMMCPWREN_PWM3_NAME, GPIO1L_PWM3
- */
-
-#define PWM_ID 0
-#define PWM_MUX_NAME GPIO1B5_PWM0_NAME
-#define PWM_MUX_MODE GPIO1L_PWM0
-#define PWM_MUX_MODE_GPIO GPIO1L_GPIO1B5
-#define PWM_EFFECT_VALUE 1
-
-//#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-#define BL_EN_MUX_NAME GPIOF34_UART3_SEL_NAME
-#define BL_EN_MUX_MODE IOMUXB_GPIO1_B34
-
-#define BL_EN_PIN GPIO0L_GPIO0A5
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
-
- rk29_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
- #ifdef LCD_DISP_ON_PIN
- rk29_mux_api_set(BL_EN_MUX_NAME, BL_EN_MUX_MODE);
-
- ret = gpio_request(BL_EN_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(BL_EN_PIN);
- }
-
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
- #endif
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0;
- #ifdef LCD_DISP_ON_PIN
- gpio_free(BL_EN_PIN);
- #endif
- rk29_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- return ret;
-}
-struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
-};
-#endif
-/*****************************************************************************************
-* pwm voltage regulator devices
-******************************************************************************************/
-#if defined (CONFIG_RK29_PWM_REGULATOR)
-
-#define REGULATOR_PWM_ID 2
-#define REGULATOR_PWM_MUX_NAME GPIO2A3_SDMMC0WRITEPRT_PWM2_NAME
-#define REGULATOR_PWM_MUX_MODE GPIO2L_PWM2
-#define REGULATOR_PWM_MUX_MODE_GPIO GPIO2L_GPIO2A3
-#define REGULATOR_PWM_GPIO RK29_PIN2_PA3
-
-static struct regulator_consumer_supply pwm_consumers[] = {
- {
- .supply = "vcore",
- }
-};
-
-static struct regulator_init_data rk29_pwm_regulator_data = {
- .constraints = {
- .name = "PWM2",
- .min_uV = 950000,
- .max_uV = 1400000,
- .apply_uV = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_consumers),
- .consumer_supplies = pwm_consumers,
-};
-
-static struct pwm_platform_data rk29_regulator_pwm_platform_data = {
- .pwm_id = REGULATOR_PWM_ID,
- .pwm_gpio = REGULATOR_PWM_GPIO,
- //.pwm_iomux_name[] = REGULATOR_PWM_MUX_NAME;
- .pwm_iomux_name = REGULATOR_PWM_MUX_NAME,
- .pwm_iomux_pwm = REGULATOR_PWM_MUX_MODE,
- .pwm_iomux_gpio = REGULATOR_PWM_MUX_MODE_GPIO,
- .init_data = &rk29_pwm_regulator_data,
-};
-
-static struct platform_device rk29_device_pwm_regulator = {
- .name = "pwm-voltage-regulator",
- .id = -1,
- .dev = {
- .platform_data = &rk29_regulator_pwm_platform_data,
- },
-};
-
-#endif
-
-
-#if defined(CONFIG_MTK23D)
-static int mtk23d_io_init(void)
-{
-
- return 0;
-}
-
-static int mtk23d_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk2818_23d_data rk2818_23d_info = {
- .io_init = mtk23d_io_init,
- .io_deinit = mtk23d_io_deinit,
- .bp_power = RK29_PIN0_PA0,
- .bp_power_active_low = 0,
- .bp_reset = RK29_PIN0_PA1,
- .bp_reset_active_low = 1,
- .bp_statue = RK29_PIN0_PA2,//input high bp sleep;
- .ap_statue = RK29_PIN0_PA4,//output high ap sleep;
- .ap_bp_wakeup = RK29_PIN0_PA3, //output AP wake up BP used rising edge;
- .bp_ap_wakeup = 0,//input BP wake up AP
-};
-struct platform_device rk2818_device_mtk23d = {
- .name = "mtk23d",
- .id = -1,
- .dev = {
- .platform_data = &rk2818_23d_info,
- }
- };
-#endif
-
-/*****************************************************************************************
- * SDMMC devices
-*****************************************************************************************/
-#if !defined(CONFIG_SDMMC_RK29_OLD)
-static void rk29_sdmmc_gpio_open(int device_id, int on)
-{
- switch(device_id)
- {
- case 0://mmc0
- {
- #ifdef CONFIG_SDMMC0_RK29
- if(on)
- {
- gpio_direction_output(RK29_PIN1_PD0,GPIO_HIGH);//set mmc0-clk to high
- gpio_direction_output(RK29_PIN1_PD1,GPIO_HIGH);//set mmc0-cmd to high.
- gpio_direction_output(RK29_PIN1_PD2,GPIO_HIGH);//set mmc0-data0 to high.
- gpio_direction_output(RK29_PIN1_PD3,GPIO_HIGH);//set mmc0-data1 to high.
- gpio_direction_output(RK29_PIN1_PD4,GPIO_HIGH);//set mmc0-data2 to high.
- gpio_direction_output(RK29_PIN1_PD5,GPIO_HIGH);//set mmc0-data3 to high.
-
- mdelay(30);
- }
- else
- {
- rk29_mux_api_set(GPIO1D0_SDMMC0CLKOUT_NAME, GPIO1H_GPIO1_D0);
- gpio_request(RK29_PIN1_PD0, "mmc0-clk");
- gpio_direction_output(RK29_PIN1_PD0,GPIO_LOW);//set mmc0-clk to low.
-
- rk29_mux_api_set(GPIO1D1_SDMMC0CMD_NAME, GPIO1H_GPIO1_D1);
- gpio_request(RK29_PIN1_PD1, "mmc0-cmd");
- gpio_direction_output(RK29_PIN1_PD1,GPIO_LOW);//set mmc0-cmd to low.
-
- rk29_mux_api_set(GPIO1D2_SDMMC0DATA0_NAME, GPIO1H_GPIO1D2);
- gpio_request(RK29_PIN1_PD2, "mmc0-data0");
- gpio_direction_output(RK29_PIN1_PD2,GPIO_LOW);//set mmc0-data0 to low.
-
- rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_GPIO1D3);
- gpio_request(RK29_PIN1_PD3, "mmc0-data1");
- gpio_direction_output(RK29_PIN1_PD3,GPIO_LOW);//set mmc0-data1 to low.
-
- rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_GPIO1D4);
- gpio_request(RK29_PIN1_PD4, "mmc0-data2");
- gpio_direction_output(RK29_PIN1_PD4,GPIO_LOW);//set mmc0-data2 to low.
-
- rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_GPIO1D5);
- gpio_request(RK29_PIN1_PD5, "mmc0-data3");
- gpio_direction_output(RK29_PIN1_PD5,GPIO_LOW);//set mmc0-data3 to low.
-
- mdelay(30);
- }
- #endif
- }
- break;
-
- case 1://mmc1
- {
- #ifdef CONFIG_SDMMC1_RK29
- if(on)
- {
- gpio_direction_output(RK29_PIN1_PC7,GPIO_HIGH);//set mmc1-clk to high
- gpio_direction_output(RK29_PIN1_PC2,GPIO_HIGH);//set mmc1-cmd to high.
- gpio_direction_output(RK29_PIN1_PC3,GPIO_HIGH);//set mmc1-data0 to high.
- gpio_direction_output(RK29_PIN1_PC4,GPIO_HIGH);//set mmc1-data1 to high.
- gpio_direction_output(RK29_PIN1_PC5,GPIO_HIGH);//set mmc1-data2 to high.
- gpio_direction_output(RK29_PIN1_PC6,GPIO_HIGH);//set mmc1-data3 to high.
- mdelay(100);
- }
- else
- {
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_GPIO1C7);
- gpio_request(RK29_PIN1_PC7, "mmc1-clk");
- gpio_direction_output(RK29_PIN1_PC7,GPIO_LOW);//set mmc1-clk to low.
-
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_GPIO1C2);
- gpio_request(RK29_PIN1_PC2, "mmc1-cmd");
- gpio_direction_output(RK29_PIN1_PC2,GPIO_LOW);//set mmc1-cmd to low.
-
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_GPIO1C3);
- gpio_request(RK29_PIN1_PC3, "mmc1-data0");
- gpio_direction_output(RK29_PIN1_PC3,GPIO_LOW);//set mmc1-data0 to low.
-
- mdelay(100);
- }
- #endif
- }
- break;
-
- case 2: //mmc2
- break;
-
- default:
- break;
- }
-}
-
-
-static void rk29_sdmmc_set_iomux_mmc0(unsigned int bus_width)
-{
- switch (bus_width)
- {
-
- case 1://SDMMC_CTYPE_4BIT:
- {
- rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_SDMMC0_DATA1);
- rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_SDMMC0_DATA2);
- rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_SDMMC0_DATA3);
- }
- break;
-
- case 0x10000://SDMMC_CTYPE_8BIT:
- break;
- case 0xFFFF: //gpio_reset
- {
- rk29_mux_api_set(GPIO5D5_SDMMC0PWREN_NAME, GPIO5H_GPIO5D5);
- gpio_request(RK29_PIN5_PD5,"sdmmc-power");
- gpio_direction_output(RK29_PIN5_PD5,GPIO_HIGH); //power-off
-
- rk29_sdmmc_gpio_open(0, 0);
-
- gpio_direction_output(RK29_PIN5_PD5,GPIO_LOW); //power-on
-
- rk29_sdmmc_gpio_open(0, 1);
- }
- break;
-
- default: //case 0://SDMMC_CTYPE_1BIT:
- {
- rk29_mux_api_set(GPIO1D1_SDMMC0CMD_NAME, GPIO1H_SDMMC0_CMD);
- rk29_mux_api_set(GPIO1D0_SDMMC0CLKOUT_NAME, GPIO1H_SDMMC0_CLKOUT);
- rk29_mux_api_set(GPIO1D2_SDMMC0DATA0_NAME, GPIO1H_SDMMC0_DATA0);
-
- rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_GPIO1D3);
- gpio_request(RK29_PIN1_PD3, "mmc0-data1");
- gpio_direction_output(RK29_PIN1_PD3,GPIO_HIGH);
-
- rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_GPIO1D4);
- gpio_request(RK29_PIN1_PD4, "mmc0-data2");
- gpio_direction_output(RK29_PIN1_PD4,GPIO_HIGH);
-
- rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_GPIO1D5);
- gpio_request(RK29_PIN1_PD5, "mmc0-data3");
- gpio_direction_output(RK29_PIN1_PD5,GPIO_HIGH);
- }
- break;
- }
-}
-
-static void rk29_sdmmc_set_iomux_mmc1(unsigned int bus_width)
-{
-#if 0
- switch (bus_width)
- {
-
- case 1://SDMMC_CTYPE_4BIT:
- {
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);
- rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_SDMMC1_DATA1);
- rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_SDMMC1_DATA2);
- rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_SDMMC1_DATA3);
- }
- break;
-
- case 0x10000://SDMMC_CTYPE_8BIT:
- break;
- case 0xFFFF:
- {
- rk29_sdmmc_gpio_open(1, 0);
- rk29_sdmmc_gpio_open(1, 1);
- }
- break;
-
- default: //case 0://SDMMC_CTYPE_1BIT:
- {
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);
-
- rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_GPIO1C4);
- gpio_request(RK29_PIN1_PC4, "mmc1-data1");
- gpio_direction_output(RK29_PIN1_PC4,GPIO_HIGH);
-
- rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_GPIO1C5);
- gpio_request(RK29_PIN1_PC5, "mmc1-data2");
- gpio_direction_output(RK29_PIN1_PC5,GPIO_HIGH);
-
- rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_GPIO1C6);
- gpio_request(RK29_PIN1_PC6, "mmc1-data3");
- gpio_direction_output(RK29_PIN1_PC6,GPIO_HIGH);
-
- }
- break;
- }
-#else
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);
- rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_SDMMC1_DATA1);
- rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_SDMMC1_DATA2);
- rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_SDMMC1_DATA3);
-
-#endif
-}
-
-static void rk29_sdmmc_set_iomux_mmc2(unsigned int bus_width)
-{
- ;//
-}
-
-static void rk29_sdmmc_set_iomux(int device_id, unsigned int bus_width)
-{
- switch(device_id)
- {
- case 0:
- #ifdef CONFIG_SDMMC0_RK29
- rk29_sdmmc_set_iomux_mmc0(bus_width);
- #endif
- break;
- case 1:
- #ifdef CONFIG_SDMMC1_RK29
- rk29_sdmmc_set_iomux_mmc1(bus_width);
- #endif
- break;
- case 2:
- rk29_sdmmc_set_iomux_mmc2(bus_width);
- break;
- default:
- break;
- }
-}
-#endif
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
- rk29_mux_api_set(GPIO1D1_SDMMC0CMD_NAME, GPIO1H_SDMMC0_CMD);
- rk29_mux_api_set(GPIO1D0_SDMMC0CLKOUT_NAME, GPIO1H_SDMMC0_CLKOUT);
- rk29_mux_api_set(GPIO1D2_SDMMC0DATA0_NAME, GPIO1H_SDMMC0_DATA0);
- rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_SDMMC0_DATA1);
- rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_SDMMC0_DATA2);
- rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_SDMMC0_DATA3);
-#ifdef CONFIG_SDMMC_RK29_OLD
- rk29_mux_api_set(GPIO2A2_SDMMC0DETECTN_NAME, GPIO2L_GPIO2A2);
-#else
- rk29_mux_api_set(GPIO2A2_SDMMC0DETECTN_NAME, GPIO2L_SDMMC0_DETECT_N);//Modifyed by xbw.
-#endif
- rk29_mux_api_set(GPIO5D5_SDMMC0PWREN_NAME, GPIO5H_GPIO5D5); ///GPIO5H_SDMMC0_PWR_EN); ///GPIO5H_GPIO5D5);
- gpio_request(RK29_PIN5_PD5,"sdmmc");
- gpio_set_value(RK29_PIN5_PD5,GPIO_HIGH);
- mdelay(100);
- gpio_set_value(RK29_PIN5_PD5,GPIO_LOW);
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail = (MMC_VDD_25_26|MMC_VDD_26_27|MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30|
- MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33|
- MMC_VDD_33_34|MMC_VDD_34_35| MMC_VDD_35_36),
- .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
- .detect_irq = RK29_PIN2_PA2, // INVALID_GPIO
- .enable_sd_wakeup = 0,
-};
-#endif
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);
- rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_SDMMC1_DATA1);
- rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_SDMMC1_DATA2);
- rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_SDMMC1_DATA3);
- //rk29_mux_api_set(GPIO1C0_UART0CTSN_SDMMC1DETECTN_NAME, GPIO1H_SDMMC1_DETECT_N);
- return 0;
-}
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
-static int rk29sdk_wifi_status(struct device *dev);
-static int rk29sdk_wifi_status_register(void (*callback)(int card_presend, void *dev_id), void *dev_id);
-#endif
-
-#define RK29SDK_WIFI_SDIO_CARD_DETECT_N RK29_PIN1_PD6
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail = (MMC_VDD_25_26|MMC_VDD_26_27|MMC_VDD_27_28|MMC_VDD_28_29|
- MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32|
- MMC_VDD_32_33|MMC_VDD_33_34),
- .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_SDIO_IRQ|
- MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc1_cfg_gpio,
- .dma_name = "sdio",
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-#if 0
- .detect_irq = RK29SDK_WIFI_SDIO_CARD_DETECT_N,
-#endif
-};
-#endif
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
-#define RK29SDK_WIFI_BT_GPIO_POWER_N RK29_PIN5_PD6
-#define RK29SDK_WIFI_GPIO_RESET_N RK29_PIN6_PC0
-#define RK29SDK_BT_GPIO_RESET_N RK29_PIN6_PC7
-
-static int rk29sdk_wifi_cd = 0; /* wifi virtual 'card detect' status */
-static void (*wifi_status_cb)(int card_present, void *dev_id);
-static void *wifi_status_cb_devid;
-int rk29sdk_wifi_power_state = 0;
-int rk29sdk_bt_power_state = 0;
-
-static int rk29sdk_wifi_status(struct device *dev)
-{
- return rk29sdk_wifi_cd;
-}
-
-static int rk29sdk_wifi_status_register(void (*callback)(int card_present, void *dev_id), void *dev_id)
-{
- if(wifi_status_cb)
- return -EAGAIN;
- wifi_status_cb = callback;
- wifi_status_cb_devid = dev_id;
- return 0;
-}
-
-static int rk29sdk_wifi_bt_gpio_control_init(void)
-{
- if (gpio_request(RK29SDK_WIFI_BT_GPIO_POWER_N, "wifi_bt_power")) {
- pr_info("%s: request wifi_bt power gpio failed\n", __func__);
- return -1;
- }
-
- if (gpio_request(RK29SDK_WIFI_GPIO_RESET_N, "wifi reset")) {
- pr_info("%s: request wifi reset gpio failed\n", __func__);
- gpio_free(RK29SDK_WIFI_BT_GPIO_POWER_N);
- return -1;
- }
-
- if (gpio_request(RK29SDK_BT_GPIO_RESET_N, "bt reset")) {
- pr_info("%s: request bt reset gpio failed\n", __func__);
- gpio_free(RK29SDK_WIFI_GPIO_RESET_N);
- return -1;
- }
-
- gpio_direction_output(RK29SDK_WIFI_BT_GPIO_POWER_N, GPIO_LOW);
- gpio_direction_output(RK29SDK_WIFI_GPIO_RESET_N, GPIO_LOW);
- gpio_direction_output(RK29SDK_BT_GPIO_RESET_N, GPIO_LOW);
-
- pr_info("%s: init finished\n",__func__);
-
- return 0;
-}
-
-static int rk29sdk_wifi_power(int on)
-{
- pr_info("%s: %d\n", __func__, on);
- if (on){
- gpio_set_value(RK29SDK_WIFI_BT_GPIO_POWER_N, GPIO_HIGH);
- gpio_set_value(RK29SDK_WIFI_GPIO_RESET_N, GPIO_HIGH);
- mdelay(100);
- pr_info("wifi turn on power\n");
- }else{
- if (!rk29sdk_bt_power_state){
- gpio_set_value(RK29SDK_WIFI_BT_GPIO_POWER_N, GPIO_LOW);
- mdelay(100);
- pr_info("wifi shut off power\n");
- }else
- {
- pr_info("wifi shouldn't shut off power, bt is using it!\n");
- }
- gpio_set_value(RK29SDK_WIFI_GPIO_RESET_N, GPIO_LOW);
-
- }
-
- rk29sdk_wifi_power_state = on;
- return 0;
-}
-
-static int rk29sdk_wifi_reset_state;
-static int rk29sdk_wifi_reset(int on)
-{
- pr_info("%s: %d\n", __func__, on);
- gpio_set_value(RK29SDK_WIFI_GPIO_RESET_N, on);
- mdelay(100);
- rk29sdk_wifi_reset_state = on;
- return 0;
-}
-
-int rk29sdk_wifi_set_carddetect(int val)
-{
- pr_info("%s:%d\n", __func__, val);
- rk29sdk_wifi_cd = val;
- if (wifi_status_cb){
- wifi_status_cb(val, wifi_status_cb_devid);
- }else {
- pr_warning("%s, nobody to notify\n", __func__);
- }
- return 0;
-}
-EXPORT_SYMBOL(rk29sdk_wifi_set_carddetect);
-
-static struct wifi_mem_prealloc wifi_mem_array[PREALLOC_WLAN_SEC_NUM] = {
- {NULL, (WLAN_SECTION_SIZE_0 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_1 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_2 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_3 + PREALLOC_WLAN_SECTION_HEADER)}
-};
-
-static void *rk29sdk_mem_prealloc(int section, unsigned long size)
-{
- if (section == PREALLOC_WLAN_SEC_NUM)
- return wlan_static_skb;
-
- if ((section < 0) || (section > PREALLOC_WLAN_SEC_NUM))
- return NULL;
-
- if (wifi_mem_array[section].size < size)
- return NULL;
-
- return wifi_mem_array[section].mem_ptr;
-}
-
-int __init rk29sdk_init_wifi_mem(void)
-{
- int i;
- int j;
-
- for (i = 0 ; i < WLAN_SKB_BUF_NUM ; i++) {
- wlan_static_skb[i] = dev_alloc_skb(
- ((i < (WLAN_SKB_BUF_NUM / 2)) ? 4096 : 8192));
-
- if (!wlan_static_skb[i])
- goto err_skb_alloc;
- }
-
- for (i = 0 ; i < PREALLOC_WLAN_SEC_NUM ; i++) {
- wifi_mem_array[i].mem_ptr =
- kmalloc(wifi_mem_array[i].size, GFP_KERNEL);
-
- if (!wifi_mem_array[i].mem_ptr)
- goto err_mem_alloc;
- }
- return 0;
-
- err_mem_alloc:
- pr_err("Failed to mem_alloc for WLAN\n");
- for (j = 0 ; j < i ; j++)
- kfree(wifi_mem_array[j].mem_ptr);
-
- i = WLAN_SKB_BUF_NUM;
-
- err_skb_alloc:
- pr_err("Failed to skb_alloc for WLAN\n");
- for (j = 0 ; j < i ; j++)
- dev_kfree_skb(wlan_static_skb[j]);
-
- return -ENOMEM;
-}
-
-static struct wifi_platform_data rk29sdk_wifi_control = {
- .set_power = rk29sdk_wifi_power,
- .set_reset = rk29sdk_wifi_reset,
- .set_carddetect = rk29sdk_wifi_set_carddetect,
- .mem_prealloc = rk29sdk_mem_prealloc,
-};
-static struct platform_device rk29sdk_wifi_device = {
- .name = "bcm4329_wlan",
- .id = 1,
- .dev = {
- .platform_data = &rk29sdk_wifi_control,
- },
-};
-#endif
-
-
-/* bluetooth rfkill device */
-static struct platform_device rk29sdk_rfkill = {
- .name = "rk29sdk_rfkill",
- .id = -1,
-};
-
-
-#ifdef CONFIG_VIVANTE
-static struct resource resources_gpu[] = {
- [0] = {
- .name = "gpu_irq",
- .start = IRQ_GPU,
- .end = IRQ_GPU,
- .flags = IORESOURCE_IRQ,
- },
- [1] = {
- .name = "gpu_base",
- .start = RK29_GPU_PHYS,
- .end = RK29_GPU_PHYS + RK29_GPU_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "gpu_mem",
- .start = PMEM_GPU_BASE,
- .end = PMEM_GPU_BASE + PMEM_GPU_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-static struct platform_device rk29_device_gpu = {
- .name = "galcore",
- .id = 0,
- .num_resources = ARRAY_SIZE(resources_gpu),
- .resource = resources_gpu,
-};
-#endif
-#ifdef CONFIG_KEYS_RK29
-extern struct rk29_keys_platform_data rk29_keys_pdata;
-static struct platform_device rk29_device_keys = {
- .name = "rk29-keypad",
- .id = -1,
- .dev = {
- .platform_data = &rk29_keys_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_USE_GPIO_GENERATE_WAVE
-static struct gpio_wave_platform_data gpio_wave_pdata = {
- .gpio = RK29_PIN0_PA0,
- .Htime = 2000,
- .Ltime = 300,
- .Dvalue = GPIO_HIGH,
-};
-static struct platform_device gpio_wave_device = {
- .name = "gpio_wave",
- .id = -1,
- .dev = {
- .platform_data = &gpio_wave_pdata,
- },
-};
-#endif
-
-static void __init rk29_board_iomux_init(void)
-{
- int err;
-
-#ifdef CONFIG_UART1_RK29
- //disable uart1 pull down
- rk29_mux_api_set(GPIO2A5_UART1SOUT_NAME, GPIO2L_GPIO2A5);
- rk29_mux_api_set(GPIO2A4_UART1SIN_NAME, GPIO2L_GPIO2A4);
-
- gpio_request(RK29_PIN2_PA5, NULL);
- gpio_request(RK29_PIN2_PA4, NULL);
-
- gpio_pull_updown(RK29_PIN2_PA5, PullDisable);
- gpio_pull_updown(RK29_PIN2_PA4, PullDisable);
-
- rk29_mux_api_set(GPIO2A5_UART1SOUT_NAME, GPIO2L_UART1_SOUT);
- rk29_mux_api_set(GPIO2A4_UART1SIN_NAME, GPIO2L_UART1_SIN);
-
- gpio_free(RK29_PIN2_PA5);
- gpio_free(RK29_PIN2_PA4);
-#endif
- #ifdef CONFIG_RK29_PWM_REGULATOR
- rk29_mux_api_set(REGULATOR_PWM_MUX_NAME,REGULATOR_PWM_MUX_MODE);
- #endif
- rk29_mux_api_set(GPIO4C0_RMIICLKOUT_RMIICLKIN_NAME,GPIO4H_GPIO4C0);
-
-/****************************clock change********************************************/
- err = gpio_request(RK29_PIN4_PC0, "clk27M_control");
- if (err) {
- gpio_free(RK29_PIN4_PC0);
- printk("-------request RK29_PIN4_PC0 fail--------\n");
- return -1;
- }
- //phy power down
- gpio_direction_output(RK29_PIN4_PC0, GPIO_LOW);// 27M 32K
- gpio_set_value(RK29_PIN4_PC0, GPIO_LOW);
-
- rk29_mux_api_set(GPIO4C5_RMIICSRDVALID_MIIRXDVALID_NAME,GPIO4H_GPIO4C5);
-
- err = gpio_request(RK29_PIN4_PC5, "clk24M_control");
- if (err) {
- gpio_free(RK29_PIN4_PC5);
- printk("-------request RK29_PIN4_PC5 fail--------\n");
- return -1;
- }
- //phy power down
- gpio_direction_output(RK29_PIN4_PC5, GPIO_LOW);// control 24M
- gpio_set_value(RK29_PIN4_PC5, GPIO_LOW);
-/*******************************************************************/
-
-
-}
-
-// For phone,just a disk only, add by phc,20110816
-#ifdef CONFIG_USB_ANDROID
-struct usb_mass_storage_platform_data phone_mass_storage_pdata = {
- .nluns = 1,
- .vendor = "RockChip",
- .product = "rk29 sdk",
- .release = 0x0100,
-};
-
-//static
-struct platform_device phone_usb_mass_storage_device = {
- .name = "usb_mass_storage",
- .id = -1,
- .dev = {
- .platform_data = &phone_mass_storage_pdata,
- },
-};
-#endif
-
-
-static struct platform_device *devices[] __initdata = {
-
-#ifdef CONFIG_RK29_WATCHDOG
- &rk29_device_wdt,
-#endif
-
-#ifdef CONFIG_UART1_RK29
- &rk29_device_uart1,
-#endif
-#ifdef CONFIG_UART0_RK29
- &rk29_device_uart0,
-#endif
-#ifdef CONFIG_UART2_RK29
- &rk29_device_uart2,
-#endif
-#ifdef CONFIG_UART3_RK29
- &rk29_device_uart3,
-#endif
-
-#ifdef CONFIG_RK29_PWM_REGULATOR
- &rk29_device_pwm_regulator,
-#endif
-#ifdef CONFIG_SPIM0_RK29
- &rk29xx_device_spi0m,
-#endif
-#ifdef CONFIG_SPIM1_RK29
- &rk29xx_device_spi1m,
-#endif
-#ifdef CONFIG_ADC_RK29
- &rk29_device_adc,
-#endif
-#ifdef CONFIG_I2C0_RK29
- &rk29_device_i2c0,
-#endif
-#ifdef CONFIG_I2C1_RK29
- &rk29_device_i2c1,
-#endif
-#ifdef CONFIG_I2C2_RK29
- &rk29_device_i2c2,
-#endif
-#ifdef CONFIG_I2C3_RK29
- &rk29_device_i2c3,
-#endif
-
-#ifdef CONFIG_MFD_WM8994
- &wm8994_fixed_voltage0,
- &wm8994_fixed_voltage1,
-#endif
-
-#ifdef CONFIG_SND_RK29_SOC_I2S_2CH
- &rk29_device_iis_2ch,
-#endif
-#ifdef CONFIG_SND_RK29_SOC_I2S_8CH
- &rk29_device_iis_8ch,
-#endif
-
-#ifdef CONFIG_KEYS_RK29
- &rk29_device_keys,
-#endif
-#ifdef CONFIG_USE_GPIO_GENERATE_WAVE
- &gpio_wave_device,
-#endif
-#ifdef CONFIG_SDMMC0_RK29
- &rk29_device_sdmmc0,
-#endif
-#ifdef CONFIG_SDMMC1_RK29
- &rk29_device_sdmmc1,
-#endif
-
-#ifdef CONFIG_MTD_NAND_RK29XX
- &rk29xx_device_nand,
-#endif
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- &rk29sdk_wifi_device,
-#endif
-
-#ifdef CONFIG_BT
- &rk29sdk_rfkill,
-#endif
-
-#if defined(CONFIG_MTK23D)
- &rk2818_device_mtk23d,
-#endif
-
-#ifdef CONFIG_MTD_NAND_RK29
- &rk29_device_nand,
-#endif
-
-#ifdef CONFIG_FB_RK29
- &rk29_device_fb,
- &rk29_device_dma_cpy,
-#endif
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- &rk29_device_backlight,
-#endif
-#ifdef CONFIG_RK29_VMAC
- &rk29_device_vmac,
-#endif
-#ifdef CONFIG_VIVANTE
- &rk29_device_gpu,
-#endif
-#ifdef CONFIG_VIDEO_RK29
- &rk29_device_camera, /* ddl@rock-chips.com : camera support */
- #if (CONFIG_SENSOR_IIC_ADDR_0 != 0x00)
- &rk29_soc_camera_pdrv_0,
- #endif
- &rk29_soc_camera_pdrv_1,
- &android_pmem_cam_device,
-#endif
-#ifdef CONFIG_ION
- &rk29_ion_device,
-#endif
- &android_pmem_device,
- &rk29_vpu_mem_device,
-#ifdef CONFIG_USB20_OTG
- &rk29_device_usb20_otg,
-#endif
-#ifdef CONFIG_USB20_HOST
- &rk29_device_usb20_host,
-#endif
-#ifdef CONFIG_USB11_HOST
- &rk29_device_usb11_host,
-#endif
-#ifdef CONFIG_USB_ANDROID
- &android_usb_device,
- &phone_usb_mass_storage_device,
-#endif
-#ifdef CONFIG_RK29_IPP
- &rk29_device_ipp,
-#endif
-#ifdef CONFIG_VIDEO_RK29XX_VOUT
- &rk29_v4l2_output_devce,
-#endif
-#ifdef CONFIG_RK_HEADSET_DET
- &rk_device_headset,
-#endif
-#ifdef CONFIG_RK29_GPS
- &rk29_device_gps,
-#endif
-};
-
-#ifdef CONFIG_RK29_VMAC
-/*****************************************************************************************
- * vmac devices
- * author: lyx@rock-chips.com
- *****************************************************************************************/
-static int rk29_vmac_register_set(void)
-{
- //config rk29 vmac as rmii, 100MHz
- u32 value= readl(RK29_GRF_BASE + 0xbc);
- value = (value & 0xfff7ff) | (0x400);
- writel(value, RK29_GRF_BASE + 0xbc);
- return 0;
-}
-
-static int rk29_rmii_io_init(void)
-{
- int err;
-
- //phy power gpio
- err = gpio_request(RK29_PIN6_PB0, "phy_power_en");
- if (err) {
- gpio_free(RK29_PIN6_PB0);
- printk("-------request RK29_PIN6_PB0 fail--------\n");
- return -1;
- }
- //phy power down
- gpio_direction_output(RK29_PIN6_PB0, GPIO_LOW);
- gpio_set_value(RK29_PIN6_PB0, GPIO_LOW);
-
- return 0;
-}
-
-static int rk29_rmii_io_deinit(void)
-{
- //phy power down
- gpio_direction_output(RK29_PIN6_PB0, GPIO_LOW);
- gpio_set_value(RK29_PIN6_PB0, GPIO_LOW);
- //free
- gpio_free(RK29_PIN6_PB0);
- return 0;
-}
-
-static int rk29_rmii_power_control(int enable)
-{
- if (enable) {
- //enable phy power
- gpio_direction_output(RK29_PIN6_PB0, GPIO_HIGH);
- gpio_set_value(RK29_PIN6_PB0, GPIO_HIGH);
- }
- else {
- gpio_direction_output(RK29_PIN6_PB0, GPIO_LOW);
- gpio_set_value(RK29_PIN6_PB0, GPIO_LOW);
- }
- return 0;
-}
-
-struct rk29_vmac_platform_data rk29_vmac_pdata = {
- .vmac_register_set = rk29_vmac_register_set,
- .rmii_io_init = rk29_rmii_io_init,
- .rmii_io_deinit = rk29_rmii_io_deinit,
- .rmii_power_control = rk29_rmii_power_control,
-};
-#endif
-
-/*****************************************************************************************
- * spi devices
- * author: cmc@rock-chips.com
- *****************************************************************************************/
-#define SPI_CHIPSELECT_NUM 2
-static struct spi_cs_gpio rk29xx_spi0_cs_gpios[SPI_CHIPSELECT_NUM] = {
- {
- .name = "spi0 cs0",
- .cs_gpio = RK29_PIN2_PC1,
- .cs_iomux_name = GPIO2C1_SPI0CSN0_NAME,
- .cs_iomux_mode = GPIO2H_SPI0_CSN0,
- },
- {
- .name = "spi0 cs1",
- .cs_gpio = RK29_PIN1_PA4,
- .cs_iomux_name = GPIO1A4_EMMCWRITEPRT_SPI0CS1_NAME,//if no iomux,set it NULL
- .cs_iomux_mode = GPIO1L_SPI0_CSN1,
- }
-};
-
-static struct spi_cs_gpio rk29xx_spi1_cs_gpios[SPI_CHIPSELECT_NUM] = {
- {
- .name = "spi1 cs0",
- .cs_gpio = RK29_PIN2_PC5,
- .cs_iomux_name = GPIO2C5_SPI1CSN0_NAME,
- .cs_iomux_mode = GPIO2H_SPI1_CSN0,
- },
- {
- .name = "spi1 cs1",
- .cs_gpio = RK29_PIN1_PA3,
- .cs_iomux_name = GPIO1A3_EMMCDETECTN_SPI1CS1_NAME,//if no iomux,set it NULL
- .cs_iomux_mode = GPIO1L_SPI1_CSN1,
- }
-};
-
-static int spi_io_init(struct spi_cs_gpio *cs_gpios, int cs_num)
-{
-#if 1
- int i;
- if (cs_gpios) {
- for (i=0; i<cs_num; i++) {
- rk29_mux_api_set(cs_gpios[i].cs_iomux_name, cs_gpios[i].cs_iomux_mode);
- }
- }
-#endif
- return 0;
-}
-
-static int spi_io_deinit(struct spi_cs_gpio *cs_gpios, int cs_num)
-{
- return 0;
-}
-
-static int spi_io_fix_leakage_bug(void)
-{
-#if 0
- gpio_direction_output(RK29_PIN2_PC1, GPIO_LOW);
-#endif
- return 0;
-}
-
-static int spi_io_resume_leakage_bug(void)
-{
-#if 0
- gpio_direction_output(RK29_PIN2_PC1, GPIO_HIGH);
-#endif
- return 0;
-}
-
-struct rk29xx_spi_platform_data rk29xx_spi0_platdata = {
- .num_chipselect = SPI_CHIPSELECT_NUM,
- .chipselect_gpios = rk29xx_spi0_cs_gpios,
- .io_init = spi_io_init,
- .io_deinit = spi_io_deinit,
- .io_fix_leakage_bug = spi_io_fix_leakage_bug,
- .io_resume_leakage_bug = spi_io_resume_leakage_bug,
-};
-
-struct rk29xx_spi_platform_data rk29xx_spi1_platdata = {
- .num_chipselect = SPI_CHIPSELECT_NUM,
- .chipselect_gpios = rk29xx_spi1_cs_gpios,
- .io_init = spi_io_init,
- .io_deinit = spi_io_deinit,
- .io_fix_leakage_bug = spi_io_fix_leakage_bug,
- .io_resume_leakage_bug = spi_io_resume_leakage_bug,
-};
-
-/*****************************************************************************************
- * xpt2046 touch panel
- * author: hhb@rock-chips.com
- *****************************************************************************************/
-#if defined(CONFIG_TOUCHSCREEN_XPT2046_NORMAL_SPI) || defined(CONFIG_TOUCHSCREEN_XPT2046_TSLIB_SPI)
-#define XPT2046_GPIO_INT RK29_PIN4_PD5 //中断???#define DEBOUNCE_REPTIME 3
-
-static struct xpt2046_platform_data xpt2046_info = {
- .model = 2046,
- .keep_vref_on = 1,
- .swap_xy = 0,
- .debounce_max = 7,
- .debounce_rep = DEBOUNCE_REPTIME,
- .debounce_tol = 20,
- .gpio_pendown = XPT2046_GPIO_INT,
- .pendown_iomux_name = GPIO4D5_CPUTRACECTL_NAME,
- .pendown_iomux_mode = GPIO4H_GPIO4D5,
- .touch_virtualkey_length = 60,
- .penirq_recheck_delay_usecs = 1,
-#if defined(CONFIG_TOUCHSCREEN_480X800)
- .x_min = 0,
- .x_max = 480,
- .y_min = 0,
- .y_max = 800,
- .touch_ad_top = 3940,
- .touch_ad_bottom = 310,
- .touch_ad_left = 3772,
- .touch_ad_right = 340,
-#elif defined(CONFIG_TOUCHSCREEN_800X480)
- .x_min = 0,
- .x_max = 800,
- .y_min = 0,
- .y_max = 480,
- .touch_ad_top = 2447,
- .touch_ad_bottom = 207,
- .touch_ad_left = 5938,
- .touch_ad_right = 153,
-#elif defined(CONFIG_TOUCHSCREEN_320X480)
- .x_min = 0,
- .x_max = 320,
- .y_min = 0,
- .y_max = 480,
- .touch_ad_top = 3166,
- .touch_ad_bottom = 256,
- .touch_ad_left = 3658,
- .touch_ad_right = 380,
-#endif
-};
-#elif defined(CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI)
-static struct xpt2046_platform_data xpt2046_info = {
- .model = 2046,
- .keep_vref_on = 1,
- .swap_xy = 0,
- .debounce_max = 7,
- .debounce_rep = DEBOUNCE_REPTIME,
- .debounce_tol = 20,
- .gpio_pendown = XPT2046_GPIO_INT,
- .pendown_iomux_name = GPIO4D5_CPUTRACECTL_NAME,
- .pendown_iomux_mode = GPIO4H_GPIO4D5,
- .touch_virtualkey_length = 60,
- .penirq_recheck_delay_usecs = 1,
-
-#if defined(CONFIG_TOUCHSCREEN_480X800)
- .x_min = 0,
- .x_max = 480,
- .y_min = 0,
- .y_max = 800,
- .screen_x = { 70, 410, 70, 410, 240},
- .screen_y = { 50, 50, 740, 740, 400},
- .uncali_x_default = { 3267, 831, 3139, 715, 1845 },
- .uncali_y_default = { 3638, 3664, 564, 591, 2087 },
-#elif defined(CONFIG_TOUCHSCREEN_800X480)
- .x_min = 0,
- .x_max = 800,
- .y_min = 0,
- .y_max = 480,
- .screen_x[5] = { 50, 750, 50, 750, 400};
- .screen_y[5] = { 40, 40, 440, 440, 240};
- .uncali_x_default[5] = { 438, 565, 3507, 3631, 2105 };
- .uncali_y_default[5] = { 3756, 489, 3792, 534, 2159 };
-#elif defined(CONFIG_TOUCHSCREEN_320X480)
- .x_min = 0,
- .x_max = 320,
- .y_min = 0,
- .y_max = 480,
- .screen_x[5] = { 50, 270, 50, 270, 160};
- .screen_y[5] = { 40, 40, 440, 440, 240};
- .uncali_x_default[5] = { 812, 3341, 851, 3371, 2183 };
- .uncali_y_default[5] = { 442, 435, 3193, 3195, 2004 };
-#endif
-};
-#endif
-
-#if defined(CONFIG_SERIAL_SC8800)
-static struct plat_sc8800 sc8800_plat_data = {
- .slav_rts_pin = RK29_PIN4_PD4,
- .slav_rdy_pin = RK29_PIN4_PD1,
- .master_rts_pin = RK29_PIN4_PD2,
- .master_rdy_pin = RK29_PIN4_PD3,
- //.poll_time = 100,
-};
-#endif
-
-static struct spi_board_info board_spi_devices[] = {
-#if defined(CONFIG_TOUCHSCREEN_XPT2046_SPI)
- {
- .modalias = "xpt2046_ts",
- .chip_select = 0,// 2,
- .max_speed_hz = 125 * 1000 * 26,/* (max sample rate @ 3V) * (cmd + data + overhead) */
- .bus_num = 0,
- .irq = XPT2046_GPIO_INT,
- .platform_data = &xpt2046_info,
- },
-#endif
-
-#if defined(CONFIG_MFD_WM831X_SPI)
- {
- .modalias = "wm8310",
- .chip_select = 1,
- .max_speed_hz = 1*1000*1000,
- .bus_num = 1,
- .irq = RK29_PIN4_PD0,
- .platform_data = &wm831x_platdata,
- },
-#endif
-#if defined(CONFIG_SERIAL_SC8800)
- {
- .modalias = "sc8800",
- .bus_num = 0,
- .platform_data = &sc8800_plat_data,
- .max_speed_hz = 12*1000*1000,
- .chip_select = 0,
- },
-#endif
-};
-
-
-/**********************************************************************************************
- *
- * The virtual keys for android "back", "home", "menu", "search", these four keys are touch key
- * on the touch screen panel. (added by hhb@rock-chips.com 2011.03.31)
- *
- ***********************************************************************************************/
-static ssize_t rk29xx_virtual_keys_show(struct kobject *kobj,
- struct kobj_attribute *attr, char *buf)
-{
-#if (defined(CONFIG_TOUCHSCREEN_XPT2046_SPI) && defined(CONFIG_TOUCHSCREEN_480X800)) \
- || defined(CONFIG_TOUCHSCREEN_HX8520_IIC) || defined(CONFIG_TOUCHSCREEN_GT801_IIC)
- /* center: x: home: 50, menu: 184, back: 315, search 435, y: 830*/
- /* centerx;centery;width;height; */
- return sprintf(buf,
- __stringify(EV_KEY) ":" __stringify(KEY_BACK) ":315:815:120:50" //":50:830:98:50" //":210:796:98:50"
- ":" __stringify(EV_KEY) ":" __stringify(KEY_MENU) ":85:815:88:50" // ":184:830:120:50" // ":435:796:120:50"
- ":" __stringify(EV_KEY) ":" __stringify(KEY_HOMEPAGE) ":184:815:100:50" //":315:830:100:50" //":320:796:100:50"
- ":" __stringify(EV_KEY) ":" __stringify(KEY_SEARCH) ":435:815:88:50" //":50:815:98:50" // //":85:796:88:50"
- "\n");
-#endif
- return 0;
-}
-
-static struct kobj_attribute rk29xx_virtual_keys_attr = {
- .attr = {
-#if defined(CONFIG_TOUCHSCREEN_XPT2046_SPI)
- .name = "virtualkeys.xpt2046-touchscreen",
-#elif defined(CONFIG_TOUCHSCREEN_HX8520_IIC)
- .name = "virtualkeys.hx8520-touchscreen",
-#elif defined(CONFIG_TOUCHSCREEN_GT801_IIC)
- .name = "virtualkeys.gt801-touchscreen",
-#elif defined(CONFIG_TOUCHSCREEN_ILI2102_IIC)
- .name = "virtualkeys.ili2102-touchscreen",
-#else
- .name = "virtualkeys",
-#endif
- .mode = S_IRUGO,
- },
- .show = &rk29xx_virtual_keys_show,
-};
-
-static struct attribute *rk29xx_properties_attrs[] = {
- &rk29xx_virtual_keys_attr.attr,
- NULL
-};
-
-static struct attribute_group rk29xx_properties_attr_group = {
- .attrs = rk29xx_properties_attrs,
-};
-static int rk29xx_virtual_keys_init(void)
-{
- int ret;
- struct kobject *properties_kobj;
- printk("rk29xx_virtual_keys_init \n");
- properties_kobj = kobject_create_and_add("board_properties", NULL);
- if (properties_kobj)
- ret = sysfs_create_group(properties_kobj,
- &rk29xx_properties_attr_group);
- if (!properties_kobj || ret)
- {
- pr_err("failed to create board_properties\n");
- }
- return ret;
-}
-
-
-static void __init rk29_gic_init_irq(void)
-{
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38))
- gic_init(0, 32, (void __iomem *)RK29_GICPERI_BASE, (void __iomem *)RK29_GICCPU_BASE);
-#else
- gic_dist_init(0, (void __iomem *)RK29_GICPERI_BASE, 32);
- gic_cpu_init(0, (void __iomem *)RK29_GICCPU_BASE);
-#endif
-}
-
-static void __init machine_rk29_init_irq(void)
-{
- rk29_gic_init_irq();
- rk29_gpio_init();
-}
-
-#define POWER_ON_PIN RK29_PIN4_PA4
-
-static void rk29_pm_power_restart(void)
-{
- printk("%s,line=%d\n",__FUNCTION__,__LINE__);
- mdelay(2);
-#if defined(CONFIG_MFD_WM831X)
- wm831x_device_restart(gWm831x);
-#endif
-
-}
-
-static void rk29_pm_power_off(void)
-{
- printk(KERN_ERR "rk29_pm_power_off start...\n");
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
-#if defined(CONFIG_MFD_WM831X)
- if(wm831x_read_usb(gWm831x))
- rk29_pm_power_restart(); //if charging then restart
- else
- wm831x_device_shutdown(gWm831x);//else shutdown
-#endif
- while (1);
-}
-
-static struct cpufreq_frequency_table freq_table[] =
-{
- { .index = 1200000, .frequency = 408000 },
- { .index = 1200000, .frequency = 600000 },
- { .index = 1200000, .frequency = 816000 },
- { .index = 1350000, .frequency = 1008000 },
- { .frequency = CPUFREQ_TABLE_END },
-};
-
-static void __init machine_rk29_board_init(void)
-{
- rk29_board_iomux_init();
-
- gpio_request(POWER_ON_PIN,"poweronpin");
- gpio_set_value(POWER_ON_PIN, GPIO_HIGH);
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
- pm_power_off = rk29_pm_power_off;
- //arm_pm_restart = rk29_pm_power_restart;
-
- board_update_cpufreq_table(freq_table);
-
- platform_add_devices(devices, ARRAY_SIZE(devices));
-#ifdef CONFIG_I2C0_RK29
- i2c_register_board_info(default_i2c0_data.bus_num, board_i2c0_devices,
- ARRAY_SIZE(board_i2c0_devices));
-#endif
-#ifdef CONFIG_I2C1_RK29
- i2c_register_board_info(default_i2c1_data.bus_num, board_i2c1_devices,
- ARRAY_SIZE(board_i2c1_devices));
-#endif
-#ifdef CONFIG_I2C2_RK29
- i2c_register_board_info(default_i2c2_data.bus_num, board_i2c2_devices,
- ARRAY_SIZE(board_i2c2_devices));
-#endif
-#ifdef CONFIG_I2C3_RK29
- i2c_register_board_info(default_i2c3_data.bus_num, board_i2c3_devices,
- ARRAY_SIZE(board_i2c3_devices));
-#endif
-
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- rk29sdk_wifi_bt_gpio_control_init();
- rk29sdk_init_wifi_mem();
-#endif
-
-#if (defined(CONFIG_TOUCHSCREEN_XPT2046_SPI) && defined(CONFIG_TOUCHSCREEN_480X800)) \
- || defined(CONFIG_TOUCHSCREEN_HX8520_IIC) || defined(CONFIG_TOUCHSCREEN_GT801_IIC)
- rk29xx_virtual_keys_init();
-#endif
-
-}
-
-static void __init machine_rk29_fixup(struct machine_desc *desc, struct tag *tags,
- char **cmdline, struct meminfo *mi)
-{
- mi->nr_banks = 1;
- mi->bank[0].start = RK29_SDRAM_PHYS;
- mi->bank[0].size = LINUX_SIZE;
-#if SDRAM_SIZE > SZ_512M
- mi->nr_banks = 2;
- mi->bank[1].start = RK29_SDRAM_PHYS + SZ_512M;
- mi->bank[1].size = SDRAM_SIZE - SZ_512M;
-#endif
-}
-
-static void __init machine_rk29_mapio(void)
-{
- rk29_map_common_io();
- rk29_setup_early_printk();
- rk29_sram_init();
- rk29_clock_init2(periph_pll_96mhz, codec_pll_300mhz, false);
- rk29_iomux_init();
- ddr_init(DDR_TYPE, DDR_FREQ);
-}
-
-MACHINE_START(RK29, "RK29board")
- /* UART for LL DEBUG */
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 37))
- /* UART for LL DEBUG */
- .phys_io = RK29_UART1_PHYS & 0xfff00000,
- .io_pg_offst = ((RK29_UART1_BASE) >> 18) & 0xfffc,
-#endif
- .boot_params = RK29_SDRAM_PHYS + 0x88000,
- .fixup = machine_rk29_fixup,
- .map_io = machine_rk29_mapio,
- .init_irq = machine_rk29_init_irq,
- .init_machine = machine_rk29_board_init,
- .timer = &rk29_timer,
-MACHINE_END
+++ /dev/null
-#include <mach/key.h>
-#include <mach/gpio.h>
-
-#define EV_ENCALL KEY_F4
-#define EV_MENU KEY_F1
-
-#define PRESS_LEV_LOW 1
-#define PRESS_LEV_HIGH 0
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "menu",
- .code = EV_MENU,
- .gpio = RK29_PIN6_PA0,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .gpio = RK29_PIN6_PA1,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .gpio = RK29_PIN6_PA2,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .gpio = RK29_PIN6_PA3,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "search",
- .code = KEY_SEARCH,
- .gpio = RK29_PIN6_PA4,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .gpio = RK29_PIN6_PA5,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "sensor",
- .code = KEY_CAMERA,
- .gpio = RK29_PIN6_PA6,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK29_PIN6_PA7,
- .active_low = PRESS_LEV_LOW,
- .wakeup = 1,
- },
-#if 0
- {
- .desc = "vol+",
- .code = KEY_VOLUMEDOWN,
- .adc_value = 95,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEUP,
- .adc_value = 249,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "menu",
- .code = EV_MENU,
- .adc_value = 406,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .code_long_press = KEY_F4,
- .adc_value = 561,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_ESC,
- .adc_value = 726,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "adkey6",
- .code = KEY_BACK,
- .code_long_press = EV_ENCALL,
- .adc_value = 899,
- .active_low = PRESS_LEV_LOW,
- },
-#endif
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = -1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
+++ /dev/null
-/*
- * Copyright (C) 2010 ROCKCHIP, Inc.
- * Author: roger_chen <cz@rock-chips.com>
- *
- * This program is the bluetooth device bcm4329's driver,
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/module.h>
-#include <linux/device.h>
-#include <linux/rfkill.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/interrupt.h>
-#include <linux/wakelock.h>
-#include <linux/fs.h>
-#include <asm/uaccess.h>
-#include <mach/gpio.h>
-#include <asm/irq.h>
-#include <mach/iomux.h>
-#include <linux/wakelock.h>
-#include <linux/timer.h>
-#include <mach/board.h>
-#if 0
-#define DBG(x...) printk(KERN_INFO x)
-#else
-#define DBG(x...)
-#endif
-
-#define BT_WAKE_HOST_SUPPORT 1
-
-struct bt_ctrl
-{
- struct rfkill *bt_rfk;
-#if BT_WAKE_HOST_SUPPORT
- struct timer_list tl;
- bool b_HostWake;
- struct wake_lock bt_wakelock;
-#endif
-};
-
-#define BT_GPIO_POWER RK29_PIN5_PD6
-#define IOMUX_BT_GPIO_POWER rk29_mux_api_set(GPIO5D6_SDMMC1PWREN_NAME, GPIO5H_GPIO5D6);
-#define BT_GPIO_RESET RK29_PIN6_PC7
-#define BT_GPIO_WAKE_UP RK29_PIN6_PD0
-#define BT_GPIO_WAKE_UP_HOST RK29_PIN4_PA2
-//#define IOMUX_BT_GPIO_WAKE_UP_HOST() rk29_mux_api_set(GPIO4D4_CPUTRACECLK_NAME,GPIO4H_GPIO4D4);
-
-//bt cts paired to uart rts
-#define UART_RTS RK29_PIN2_PA7
-#define IOMUX_UART_RTS_GPIO rk29_mux_api_set(GPIO2A7_UART2RTSN_NAME, GPIO2L_GPIO2A7);
-#define IOMUX_UART_RTS rk29_mux_api_set(GPIO2A7_UART2RTSN_NAME, GPIO2L_UART2_RTS_N);
-
-#define BT_WAKE_LOCK_TIMEOUT 10 //s
-
-static const char bt_name[] = "bcm4329";
-extern int rk29sdk_bt_power_state;
-extern int rk29sdk_wifi_power_state;
-
-struct bt_ctrl gBtCtrl;
-
-#if BT_WAKE_HOST_SUPPORT
-void resetBtHostSleepTimer(void)
-{
- mod_timer(&(gBtCtrl.tl),jiffies + BT_WAKE_LOCK_TIMEOUT*HZ);//ÔÙÖØÐÂÉèÖó¬Ê±Öµ¡£
-}
-
-void btWakeupHostLock(void)
-{
- if(gBtCtrl.b_HostWake == false){
- DBG("*************************Lock\n");
-
- wake_lock(&(gBtCtrl.bt_wakelock));
- gBtCtrl.b_HostWake = true;
- }
-}
-
-void btWakeupHostUnlock(void)
-{
- if(gBtCtrl.b_HostWake == true){
- DBG("*************************UnLock\n");
- wake_unlock(&(gBtCtrl.bt_wakelock)); //ÈÃϵͳ˯Ãß
- gBtCtrl.b_HostWake = false;
- }
-}
-
-static void timer_hostSleep(unsigned long arg)
-{
- DBG("%s---b_HostWake=%d\n",__FUNCTION__,gBtCtrl.b_HostWake);
- btWakeupHostUnlock();
-}
-
-
-#ifdef CONFIG_PM
-static int bcm4329_rfkill_suspend(struct platform_device *pdev, pm_message_t state)
-{
- DBG("%s\n",__FUNCTION__);
-
- //To prevent uart to receive bt data when suspended
- IOMUX_UART_RTS_GPIO;
- gpio_request(UART_RTS, "uart_rts");
- gpio_direction_output(UART_RTS, 0);
- gpio_set_value(UART_RTS, GPIO_HIGH);
-
- return 0;
-}
-
-static int bcm4329_rfkill_resume(struct platform_device *pdev)
-{
- DBG("%s\n",__FUNCTION__);
-
- btWakeupHostLock();
- resetBtHostSleepTimer();
-
- gpio_set_value(UART_RTS, GPIO_LOW);
- IOMUX_UART_RTS;
-
- return 0;
-}
-#else
-#define bcm4329_rfkill_suspend NULL
-#define bcm4329_rfkill_resume NULL
-#endif
-
-static irqreturn_t bcm4329_wake_host_irq(int irq, void *dev)
-{
- DBG("%s\n",__FUNCTION__);
-
- btWakeupHostLock();
- resetBtHostSleepTimer();
- return IRQ_HANDLED;
-}
-#endif
-
-#ifdef CONFIG_BT_HCIBCM4325
-int bcm4325_sleep(int bSleep)
-{
- //printk("*************bt enter sleep***************\n");
- if (bSleep)
- gpio_set_value(BT_GPIO_WAKE_UP, GPIO_LOW); //low represent bt device may enter sleep
- else
- gpio_set_value(BT_GPIO_WAKE_UP, GPIO_HIGH); //high represent bt device must be awake
- //printk("sleep=%d\n",bSleep);
- return 0;
-}
-#endif
-
-static int bcm4329_set_block(void *data, bool blocked)
-{
- DBG("%s---blocked :%d\n", __FUNCTION__, blocked);
-
- IOMUX_BT_GPIO_POWER;
-
- if (false == blocked) {
- gpio_set_value(BT_GPIO_POWER, GPIO_HIGH); /* bt power on */
- gpio_set_value(BT_GPIO_RESET, GPIO_LOW);
- mdelay(200);
- gpio_set_value(BT_GPIO_RESET, GPIO_HIGH); /* bt reset deactive*/
- mdelay(200);
-
-#if BT_WAKE_HOST_SUPPORT
- btWakeupHostLock();
-#endif
- pr_info("bt turn on power\n");
- }
- else {
-#if BT_WAKE_HOST_SUPPORT
- btWakeupHostUnlock();
-#endif
- if (!rk29sdk_wifi_power_state) {
- gpio_set_value(BT_GPIO_POWER, GPIO_LOW); /* bt power off */
- mdelay(20);
- pr_info("bt shut off power\n");
- }else {
- pr_info("bt shouldn't shut off power, wifi is using it!\n");
- }
-
- gpio_set_value(BT_GPIO_RESET, GPIO_LOW); /* bt reset active*/
- mdelay(20);
- }
-
- rk29sdk_bt_power_state = !blocked;
- return 0;
-}
-
-
-static const struct rfkill_ops bcm4329_rfk_ops = {
- .set_block = bcm4329_set_block,
-};
-
-static int __devinit bcm4329_rfkill_probe(struct platform_device *pdev)
-{
- int rc = 0;
- bool default_state = true;
-
- DBG("Enter::%s,line=%d\n",__FUNCTION__,__LINE__);
-
- /* default to bluetooth off */
- bcm4329_set_block(NULL, default_state); /* blocked -> bt off */
-
- gBtCtrl.bt_rfk = rfkill_alloc(bt_name,
- NULL,
- RFKILL_TYPE_BLUETOOTH,
- &bcm4329_rfk_ops,
- NULL);
-
- if (!gBtCtrl.bt_rfk)
- {
- printk("fail to rfkill_allocate************\n");
- return -ENOMEM;
- }
-
- rfkill_set_states(gBtCtrl.bt_rfk, default_state, false);
-
- rc = rfkill_register(gBtCtrl.bt_rfk);
- if (rc)
- {
- printk("failed to rfkill_register,rc=0x%x\n",rc);
- rfkill_destroy(gBtCtrl.bt_rfk);
- }
-
- gpio_request(BT_GPIO_POWER, NULL);
- gpio_request(BT_GPIO_RESET, NULL);
- gpio_request(BT_GPIO_WAKE_UP, NULL);
-
-#if BT_WAKE_HOST_SUPPORT
- init_timer(&(gBtCtrl.tl));
- gBtCtrl.tl.expires = jiffies + BT_WAKE_LOCK_TIMEOUT*HZ;
- gBtCtrl.tl.function = timer_hostSleep;
- add_timer(&(gBtCtrl.tl));
- gBtCtrl.b_HostWake = false;
-
- wake_lock_init(&(gBtCtrl.bt_wakelock), WAKE_LOCK_SUSPEND, "bt_wake");
-
- rc = gpio_request(BT_GPIO_WAKE_UP_HOST, "bt_wake");
- if (rc) {
- printk("%s:failed to request RAHO_BT_WAKE_UP_HOST\n",__FUNCTION__);
- }
-
- //IOMUX_BT_GPIO_WAKE_UP_HOST();
- gpio_pull_updown(BT_GPIO_WAKE_UP_HOST,GPIOPullUp);
- rc = request_irq(gpio_to_irq(BT_GPIO_WAKE_UP_HOST),bcm4329_wake_host_irq,IRQF_TRIGGER_FALLING,NULL,NULL);
- if(rc)
- {
- printk("%s:failed to request RAHO_BT_WAKE_UP_HOST irq\n",__FUNCTION__);
- gpio_free(BT_GPIO_WAKE_UP_HOST);
- }
- enable_irq_wake(gpio_to_irq(BT_GPIO_WAKE_UP_HOST)); // so RAHO_BT_WAKE_UP_HOST can wake up system
-
- printk(KERN_INFO "bcm4329 module has been initialized,rc=0x%x\n",rc);
- #endif
-
- return rc;
-
-
-}
-
-
-static int __devexit bcm4329_rfkill_remove(struct platform_device *pdev)
-{
- if (gBtCtrl.bt_rfk)
- rfkill_unregister(gBtCtrl.bt_rfk);
- gBtCtrl.bt_rfk = NULL;
-#if BT_WAKE_HOST_SUPPORT
- del_timer(&(gBtCtrl.tl));//ɾµô¶¨Ê±Æ÷
- btWakeupHostUnlock();
- wake_lock_destroy(&(gBtCtrl.bt_wakelock));
-#endif
- platform_set_drvdata(pdev, NULL);
-
- DBG("Enter::%s,line=%d\n",__FUNCTION__,__LINE__);
- return 0;
-}
-
-static struct platform_driver bcm4329_rfkill_driver = {
- .probe = bcm4329_rfkill_probe,
- .remove = __devexit_p(bcm4329_rfkill_remove),
- .driver = {
- .name = "rk29sdk_rfkill",
- .owner = THIS_MODULE,
- },
-#if BT_WAKE_HOST_SUPPORT
- .suspend = bcm4329_rfkill_suspend,
- .resume = bcm4329_rfkill_resume,
-#endif
-};
-
-/*
- * Module initialization
- */
-static int __init bcm4329_mod_init(void)
-{
- int ret;
- DBG("Enter::%s,line=%d\n",__FUNCTION__,__LINE__);
- ret = platform_driver_register(&bcm4329_rfkill_driver);
- printk("ret=0x%x\n", ret);
- return ret;
-}
-
-static void __exit bcm4329_mod_exit(void)
-{
- platform_driver_unregister(&bcm4329_rfkill_driver);
-}
-
-module_init(bcm4329_mod_init);
-module_exit(bcm4329_mod_exit);
-MODULE_DESCRIPTION("bcm4329 Bluetooth driver");
-MODULE_AUTHOR("roger_chen cz@rock-chips.com");
-MODULE_LICENSE("GPL");
+++ /dev/null
-/* arch/arm/mach-rk29/board-rk29-td8801.c
- *
- * Copyright (C) 2010 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/android_pmem.h>
-#include <linux/usb/android_composite.h>
-#include <linux/ion.h>
-
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/iomux.h>
-#include <mach/gpio.h>
-#include <mach/irqs.h>
-#include <mach/rk29_iomap.h>
-#include <mach/board.h>
-#include <mach/rk29_nand.h>
-#include <mach/rk29_camera.h> /* ddl@rock-chips.com : camera support */
-#include <media/soc_camera.h> /* ddl@rock-chips.com : camera support */
-#include <mach/vpu_mem.h>
-#include <mach/sram.h>
-#include <mach/ddr.h>
-#include <mach/cpufreq.h>
-
-#include <linux/regulator/rk29-pwm-regulator.h>
-#include <linux/regulator/machine.h>
-#include <linux/mfd/wm831x/pdata.h>
-#include <linux/mfd/wm831x/core.h>
-#include <linux/mfd/wm831x/gpio.h>
-
-#include <linux/mtd/nand.h>
-#include <linux/mtd/partitions.h>
-#include <linux/i2c-gpio.h>
-#include <linux/mpu.h>
-#include "devices.h"
-
-#include <linux/regulator/fixed.h>
-#include <linux/mfd/wm8994/pdata.h>
-
-#if defined(CONFIG_TDSC8800)
-#include <linux/mtk23d.h>
-#endif
-
-#ifdef CONFIG_USE_GPIO_GENERATE_WAVE
-#include "../../../drivers/testcode/gpio_wave.h"
-#endif
-
-#include "../../../drivers/headset_observe/rk_headset.h"
-#include "../../../drivers/staging/android/timed_gpio.h"
-/*set touchscreen different type header*/
-#if defined(CONFIG_TOUCHSCREEN_XPT2046_NORMAL_SPI)
-#include "../../../drivers/input/touchscreen/xpt2046_ts.h"
-#elif defined(CONFIG_TOUCHSCREEN_XPT2046_TSLIB_SPI)
-#include "../../../drivers/input/touchscreen/xpt2046_tslib_ts.h"
-#elif defined(CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI)
-#include "../../../drivers/input/touchscreen/xpt2046_cbn_ts.h"
-#endif
-#include "../../../drivers/misc/gps/rk29_gps.h"
-#include "../../../drivers/tty/serial/sc8800.h"
-#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Macro Define Begin ------------------------*/
-/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
-#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_OV5640 /* back camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_0 0x78
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 3
-#define CONFIG_SENSOR_ORIENTATION_0 90
-#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 RK29_PIN6_PB7
-#define CONFIG_SENSOR_FALSH_PIN_0 RK29_PIN6_PB5
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_H
-#define CONFIG_SENSOR_TORCH_PIN_0 RK29_PIN4_PD1
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_0 20000
-
-
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_GC0309 /* front camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_1 0x42
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 3
-#define CONFIG_SENSOR_ORIENTATION_1 270
-#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_1 RK29_PIN5_PD7
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-#define CONFIG_SENSOR_TORCH_PIN_1 RK29_PIN4_PD1
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 17000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_1 17000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 17000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_1 17000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_1 17000
-#define CONFIG_SENSOR_480P_FPS_FIXED_1 17000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 17000
-#define CONFIG_SENSOR_720P_FPS_FIXED_1 17000
-
-#endif //#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk29_camera.c"
-/*---------------- Camera Sensor Macro Define End ------------------------*/
-
-
-#include "../../../drivers/cmmb/siano/smsspiphy.h"
-/* Set memory size of pmem */
-#ifdef CONFIG_RK29_MEM_SIZE_M
-#define SDRAM_SIZE (CONFIG_RK29_MEM_SIZE_M * SZ_1M)
-#else
-#define SDRAM_SIZE SZ_512M
-#endif
-#define PMEM_GPU_SIZE SZ_64M
-#define PMEM_UI_SIZE SZ_32M
-#define PMEM_VPU_SIZE SZ_64M
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-#ifdef CONFIG_VIDEO_RK29_WORK_IPP
-#define MEM_CAMIPP_SIZE PMEM_CAMIPP_NECESSARY
-#else
-#define MEM_CAMIPP_SIZE 0
-#endif
-#define MEM_FB_SIZE (3*SZ_2M)//(3*SZ_2M)
-#ifdef CONFIG_FB_WORK_IPP
-#define MEM_FBIPP_SIZE SZ_2M//SZ_8M //1920 x 1080 x 2 x 2 //RGB565 = x2;RGB888 = x4
-#else
-#define MEM_FBIPP_SIZE 0
-#endif
-#if SDRAM_SIZE > SZ_512M
-#define PMEM_GPU_BASE (RK29_SDRAM_PHYS + SZ_512M - PMEM_GPU_SIZE)
-#else
-#define PMEM_GPU_BASE (RK29_SDRAM_PHYS + SDRAM_SIZE - PMEM_GPU_SIZE)
-#endif
-#define PMEM_UI_BASE (PMEM_GPU_BASE - PMEM_UI_SIZE)
-#define PMEM_VPU_BASE (PMEM_UI_BASE - PMEM_VPU_SIZE)
-#define PMEM_CAM_BASE (PMEM_VPU_BASE - PMEM_CAM_SIZE)
-#define MEM_CAMIPP_BASE (PMEM_CAM_BASE - MEM_CAMIPP_SIZE)
-#define MEM_FB_BASE (MEM_CAMIPP_BASE - MEM_FB_SIZE)
-#define MEM_FBIPP_BASE (MEM_FB_BASE - MEM_FBIPP_SIZE)
-#define LINUX_SIZE (MEM_FBIPP_BASE - RK29_SDRAM_PHYS)
-
-#define PREALLOC_WLAN_SEC_NUM 4
-#define PREALLOC_WLAN_BUF_NUM 160
-#define PREALLOC_WLAN_SECTION_HEADER 24
-
-#define WLAN_SECTION_SIZE_0 (PREALLOC_WLAN_BUF_NUM * 128)
-#define WLAN_SECTION_SIZE_1 (PREALLOC_WLAN_BUF_NUM * 128)
-#define WLAN_SECTION_SIZE_2 (PREALLOC_WLAN_BUF_NUM * 512)
-#define WLAN_SECTION_SIZE_3 (PREALLOC_WLAN_BUF_NUM * 1024)
-
-#define WLAN_SKB_BUF_NUM 16
-#define UNLOCK_SECURITY_KEY ~(0x1<<5)
-#define LOCK_SECURITY_KEY 0x00
-
-static struct sk_buff *wlan_static_skb[WLAN_SKB_BUF_NUM];
-
-struct wifi_mem_prealloc {
- void *mem_ptr;
- unsigned long size;
-};
-
-extern struct sys_timer rk29_timer;
-
-static int rk29_nand_io_init(void)
-{
- return 0;
-}
-
-struct rk29_nand_platform_data rk29_nand_data = {
- .width = 1, /* data bus width in bytes */
- .hw_ecc = 1, /* hw ecc 0: soft ecc */
- .num_flash = 1,
- .io_init = rk29_nand_io_init,
-};
-
-#ifdef CONFIG_FB_RK29
-/*****************************************************************************************
- * lcd devices
- * author: zyw@rock-chips.com
- *****************************************************************************************/
-//#ifdef CONFIG_LCD_TD043MGEA1
-#define LCD_RXD_PIN RK29_PIN2_PC7
-#define LCD_TXD_PIN RK29_PIN3_PA1// RK29_PIN2_PC6
-#define LCD_CLK_PIN RK29_PIN3_PA2//RK29_PIN2_PC4
-#define LCD_CS_PIN RK29_PIN3_PA5//RK29_PIN2_PC5
-/*****************************************************************************************
-* frame buffer devices
-* author: zyw@rock-chips.com
-*****************************************************************************************/
-#define FB_ID 0
-#define FB_DISPLAY_ON_PIN INVALID_GPIO//RK29_PIN6_PD0
-#define FB_LCD_STANDBY_PIN INVALID_GPIO//RK29_PIN6_PD1
-#define FB_LCD_CABC_EN_PIN INVALID_GPIO//RK29_PIN6_PD2
-#define FB_MCU_FMK_PIN INVALID_GPIO
-
-#define FB_DISPLAY_ON_VALUE GPIO_HIGH
-#define FB_LCD_STANDBY_VALUE GPIO_HIGH
-
-//#endif
-static int rk29_lcd_io_init(void)
-{
- int ret = 0;
- //printk("rk29_lcd_io_init\n");
- //ret = gpio_request(LCD_RXD_PIN, NULL);
- ret = gpio_request(LCD_TXD_PIN, NULL);
- ret = gpio_request(LCD_CLK_PIN, NULL);
- ret = gpio_request(LCD_CS_PIN, NULL);
- //rk29_mux_api_set(GPIO2C7_SPI1RXD_NAME,GPIO2H_GPIO2C7);
- rk29_mux_api_set(GPIO3A1_I2S1SCLK_NAME,GPIO3L_GPIO3A1);
- rk29_mux_api_set(GPIO3A5_I2S1LRCKTX_NAME,GPIO3L_GPIO3A5);
- rk29_mux_api_set(GPIO3A2_I2S1LRCKRX_NAME,GPIO3L_GPIO3A2);
- return ret;
-}
-
-static int rk29_lcd_io_deinit(void)
-{
- int ret = 0;
- //printk("rk29_lcd_io_deinit\n");
- gpio_free(LCD_CS_PIN);
- gpio_free(LCD_CLK_PIN);
- gpio_free(LCD_TXD_PIN);
- //gpio_free(LCD_RXD_PIN);
- //rk29_mux_api_set(GPIO2C7_SPI1RXD_NAME,GPIO2H_SPI1_RXD);
- //rk29_mux_api_set(GPIO2C6_SPI1TXD_NAME,GPIO2H_SPI1_TXD);
- ///rk29_mux_api_set(GPIO2C5_SPI1CSN0_NAME,GPIO2H_SPI1_CSN0);
- //rk29_mux_api_set(GPIO2C4_SPI1CLK_NAME,GPIO2H_SPI1_CLK);
- rk29_mux_api_set(GPIO3A1_I2S1SCLK_NAME,GPIO3L_I2S1_SCLK);
- rk29_mux_api_set(GPIO3A5_I2S1LRCKTX_NAME,GPIO3L_I2S1_LRCK_TX);
- rk29_mux_api_set(GPIO3A2_I2S1LRCKRX_NAME,GPIO3L_I2S1_LRCK_RX);
- return ret;
-}
-
-static struct rk29lcd_info rk29_lcd_info = {
- .txd_pin = LCD_TXD_PIN,
- .clk_pin = LCD_CLK_PIN,
- .cs_pin = LCD_CS_PIN,
- .io_init = rk29_lcd_io_init,
- .io_deinit = rk29_lcd_io_deinit,
-};
-
-int rk29_fb_io_enable(void)
-{
- if(FB_DISPLAY_ON_PIN != INVALID_GPIO)
- {
- gpio_direction_output(FB_DISPLAY_ON_PIN, 0);
- gpio_set_value(FB_DISPLAY_ON_PIN, FB_DISPLAY_ON_VALUE);
- }
- if(FB_LCD_STANDBY_PIN != INVALID_GPIO)
- {
- gpio_direction_output(FB_LCD_STANDBY_PIN, 0);
- gpio_set_value(FB_LCD_STANDBY_PIN, FB_LCD_STANDBY_VALUE);
- }
- return 0;
-}
-
-int rk29_fb_io_disable(void)
-{
- if(FB_DISPLAY_ON_PIN != INVALID_GPIO)
- {
- gpio_direction_output(FB_DISPLAY_ON_PIN, 0);
- gpio_set_value(FB_DISPLAY_ON_PIN, !FB_DISPLAY_ON_VALUE);
- }
- if(FB_LCD_STANDBY_PIN != INVALID_GPIO)
- {
- gpio_direction_output(FB_LCD_STANDBY_PIN, 0);
- gpio_set_value(FB_LCD_STANDBY_PIN, !FB_LCD_STANDBY_VALUE);
- }
- return 0;
-}
-
-static int rk29_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
- if(fb_setting->mcu_fmk_en && (FB_MCU_FMK_PIN != INVALID_GPIO))
- {
- ret = gpio_request(FB_MCU_FMK_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(FB_MCU_FMK_PIN);
- printk(">>>>>> FB_MCU_FMK_PIN gpio_request err \n ");
- }
- gpio_direction_input(FB_MCU_FMK_PIN);
- }
- if(fb_setting->disp_on_en && (FB_DISPLAY_ON_PIN != INVALID_GPIO))
- {
- ret = gpio_request(FB_DISPLAY_ON_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(FB_DISPLAY_ON_PIN);
- printk(">>>>>> FB_DISPLAY_ON_PIN gpio_request err \n ");
- }
- }
-
- if(fb_setting->disp_on_en && (FB_LCD_STANDBY_PIN != INVALID_GPIO))
- {
- ret = gpio_request(FB_LCD_STANDBY_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(FB_LCD_STANDBY_PIN);
- printk(">>>>>> FB_LCD_STANDBY_PIN gpio_request err \n ");
- }
- }
-
- if(FB_LCD_CABC_EN_PIN != INVALID_GPIO)
- {
- ret = gpio_request(FB_LCD_CABC_EN_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(FB_LCD_CABC_EN_PIN);
- printk(">>>>>> FB_LCD_CABC_EN_PIN gpio_request err \n ");
- }
- gpio_direction_output(FB_LCD_CABC_EN_PIN, 0);
- gpio_set_value(FB_LCD_CABC_EN_PIN, GPIO_LOW);
- }
- rk29_fb_io_enable(); //enable it
-
- return ret;
-}
-
-static struct rk29fb_info rk29_fb_info = {
- .fb_id = FB_ID,
- .mcu_fmk_pin = FB_MCU_FMK_PIN,
- .lcd_info = &rk29_lcd_info,
- .io_init = rk29_fb_io_init,
- .io_enable = rk29_fb_io_enable,
- .io_disable = rk29_fb_io_disable,
-};
-
-/* rk29 fb resource */
-static struct resource rk29_fb_resource[] = {
- [0] = {
- .name = "lcdc reg",
- .start = RK29_LCDC_PHYS,
- .end = RK29_LCDC_PHYS + RK29_LCDC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc irq",
- .start = IRQ_LCDC,
- .end = IRQ_LCDC,
- .flags = IORESOURCE_IRQ,
- },
- [2] = {
- .name = "win1 buf",
- .start = MEM_FB_BASE,
- .end = MEM_FB_BASE + MEM_FB_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- #ifdef CONFIG_FB_WORK_IPP
- [3] = {
- .name = "win1 ipp buf",
- .start = MEM_FBIPP_BASE,
- .end = MEM_FBIPP_BASE + MEM_FBIPP_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- #endif
-};
-
-/*platform_device*/
-struct platform_device rk29_device_fb = {
- .name = "rk29-fb",
- .id = 4,
- .num_resources = ARRAY_SIZE(rk29_fb_resource),
- .resource = rk29_fb_resource,
- .dev = {
- .platform_data = &rk29_fb_info,
- }
-};
-
-struct platform_device rk29_device_dma_cpy = {
- .name = "dma_memcpy",
- .id = 4,
-
-};
-
-#endif
-
-static struct android_pmem_platform_data android_pmem_pdata = {
- .name = "pmem",
- .start = PMEM_UI_BASE,
- .size = PMEM_UI_SIZE,
- .no_allocator = 0,
- .cached = 1,
-};
-
-static struct platform_device android_pmem_device = {
- .name = "android_pmem",
- .id = 0,
- .dev = {
- .platform_data = &android_pmem_pdata,
- },
-};
-
-
-static struct vpu_mem_platform_data vpu_mem_pdata = {
- .name = "vpu_mem",
- .start = PMEM_VPU_BASE,
- .size = PMEM_VPU_SIZE,
- .cached = 1,
-};
-
-static struct platform_device rk29_vpu_mem_device = {
- .name = "vpu_mem",
- .id = 2,
- .dev = {
- .platform_data = &vpu_mem_pdata,
- },
-};
-
-static struct platform_device rk29_v4l2_output_devce = {
- .name = "rk29_vout",
-};
-
-#ifdef CONFIG_ION
-static struct ion_platform_data rk29_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = 0,
- .name = "ui",
- .base = PMEM_UI_BASE,
- .size = PMEM_UI_SIZE,
- }
- },
-};
-
-static struct platform_device rk29_ion_device = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk29_ion_pdata,
- },
-};
-#endif
-
-
-/* HANNSTAR_P1003 touch I2C */
-#if defined (CONFIG_HANNSTAR_P1003)
-#define TOUCH_RESET_PIN RK29_PIN6_PC3
-#define TOUCH_INT_PIN RK29_PIN4_PD5
-
-int p1003_init_platform_hw(void)
-{
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_pull_updown(TOUCH_INT_PIN, 1);
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
-
- return 0;
-}
-
-
-struct p1003_platform_data p1003_info = {
- .model= 1003,
- .init_platform_hw= p1003_init_platform_hw,
-
-};
-#endif
-
-
-#if defined(CONFIG_TOUCHSCREEN_GT801_IIC)
-#include "../../../drivers/input/touchscreen/gt801_ts.h"
-#define GT801_GPIO_INT RK29_PIN4_PD5
-#define GT801_GPIO_RESET RK29_PIN6_PC3
-static struct gt801_platform_data gt801_info = {
- .model = 801,
- .swap_xy = 0,
- .x_min = 0,
- .x_max = 480,
- .y_min = 0,
- .y_max = 800,
- .gpio_reset = GT801_GPIO_RESET,
- .gpio_reset_active_low = 0,
- .gpio_pendown = GT801_GPIO_INT,
- .pendown_iomux_name = GPIO4D5_CPUTRACECTL_NAME,
- .resetpin_iomux_name = NULL,
- .pendown_iomux_mode = GPIO4H_GPIO4D5,
- .resetpin_iomux_mode = 0,
-};
-#endif
-
-
-#if defined(CONFIG_TOUCHSCREEN_GT818_IIC)
-#include "../../../drivers/input/touchscreen/gt818_ts.h"
-#define GT818_GPIO_INT RK29_PIN4_PD5
-#define GT818_GPIO_RESET RK29_PIN6_PC3
-static struct gt818_platform_data gt818_info = {
- .model = 818,
- .swap_xy = 0,
- .x_min = 0,
- .x_max = 480,
- .y_min = 0,
- .y_max = 800,
- .gpio_reset = GT818_GPIO_RESET,
- .gpio_reset_active_low = 0,
- .gpio_pendown = GT818_GPIO_INT,
- .pendown_iomux_name = GPIO4D5_CPUTRACECTL_NAME,
- .resetpin_iomux_name = NULL,
- .pendown_iomux_mode = GPIO4H_GPIO4D5,
- .resetpin_iomux_mode = 0,
-};
-#endif
-
-#if defined(CONFIG_TOUCHSCREEN_ILI2102_IIC)
-#include "../../../drivers/input/touchscreen/ili2102_ts.h"
-#define GT801_GPIO_INT RK29_PIN4_PD5
-#define GT801_GPIO_RESET RK29_PIN6_PC3
-static struct ili2102_platform_data ili2102_info = {
- .model = 2102,
- .swap_xy = 0,
- .x_min = 0,
- .x_max = 481,
- .y_min = 0,
- .y_max = 801,
- .gpio_reset = GT801_GPIO_RESET,
- .gpio_reset_active_low = 1,
- .gpio_pendown = GT801_GPIO_INT,
- .pendown_iomux_name = GPIO4D5_CPUTRACECTL_NAME,
- .resetpin_iomux_name = NULL,
- .pendown_iomux_mode = GPIO4H_GPIO4D5,
- .resetpin_iomux_mode = 0,
-};
-#endif
-
-/* EETI_EGALAX touch I2C */
-#if defined (CONFIG_EETI_EGALAX)
-#define TOUCH_RESET_PIN RK29_PIN6_PC3
-#define TOUCH_INT_PIN RK29_PIN4_PD5
-
-static int EETI_EGALAX_init_platform_hw(void)
-{
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_pull_updown(TOUCH_INT_PIN, 1);
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
-
- return 0;
-}
-
-
-static struct eeti_egalax_platform_data eeti_egalax_info = {
- .model= 1003,
- .init_platform_hw= EETI_EGALAX_init_platform_hw,
-
-};
-
-#endif
-
-#if defined(CONFIG_TOUCHSCREEN_PIXCIR)
-#include "../../../drivers/input/touchscreen/pixcir_i2c_ts.h"
-static struct pixcir_platform_data pixcir_info = {
- .model = 801,
- .swap_xy = 0,
- .x_min = 0,
- .x_max = 480,
- .y_min = 0,
- .y_max = 800,
- .gpio_reset = RK29_PIN6_PC3,
- .gpio_reset_active_low = 1,
- .gpio_pendown = RK29_PIN4_PD5,
- .pendown_iomux_name = GPIO4D5_CPUTRACECTL_NAME,
- .resetpin_iomux_name = NULL,
- .pendown_iomux_mode = GPIO4H_GPIO4D5,
- .resetpin_iomux_mode = 0,
-};
-#endif
-
-#if defined(CONFIG_TOUCHSCREEN_FT5X0X)
-#include "../../../drivers/input/touchscreen/ft5x0x_ts.h"
-static struct ft5x0x_platform_data ft5x0x_info = {
- .model = 5000,
- .swap_xy = 0,
- .x_min = 0,
- .x_max = 480,
- .y_min = 0,
- .y_max = 800,
- .gpio_reset = RK29_PIN6_PC3,
- .gpio_reset_active_low = 1,
- .gpio_pendown = RK29_PIN4_PD5,
- .pendown_iomux_name = GPIO4D5_CPUTRACECTL_NAME,
- .resetpin_iomux_name = NULL,
- .pendown_iomux_mode = GPIO4H_GPIO4D5,
- .resetpin_iomux_mode = 0,
-};
-#endif
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN RK29_PIN6_PC4
-
-static int mma8452_init_platform_hw(void)
-{
-
- if(gpio_request(MMA8452_INT_PIN,NULL) != 0){
- gpio_free(MMA8452_INT_PIN);
- printk("mma8452_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_pull_updown(MMA8452_INT_PIN, 1);
- return 0;
-}
-
-
-static struct gsensor_platform_data mma8452_info = {
- .model= 8452,
- .swap_xy = 0,
- .init_platform_hw= mma8452_init_platform_hw,
-
-};
-#endif
-/*BMA023 gsensor*/
-#if defined (CONFIG_GS_BMA023)
-#define BMA023_INT_PIN RK29_PIN6_PC4
-
-static int bma023_init_platform_hw(void)
-{
-
- if(gpio_request(BMA023_INT_PIN,NULL) != 0){
- gpio_free(BMA023_INT_PIN);
- printk("bma023_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_pull_updown(BMA023_INT_PIN, 1);
- return 0;
-}
-
-
-static struct bma023_platform_data bma023_info = {
- .model= 023,
- .swap_xy = 0,
- .swap_xyz = 1,
- .orientation = {-1,0,0,
- 0,0,1,
- 0,-1,0},
- .init_platform_hw= bma023_init_platform_hw,
-
-};
-#endif
-
-#if defined (CONFIG_COMPASS_AK8975)
-static struct akm8975_platform_data akm8975_info =
-{
- .m_layout =
- {
- {
- {1, 0, 0 },
- {0, 1, 0 },
- {0, 0, 1 },
- },
-
- {
- {1, 0, 0 },
- {0, 1, 0 },
- {0, 0, 1 },
- },
-
- {
- {1, 0, 0 },
- {0, 1, 0 },
- {0, 0, 1 },
- },
-
- {
- {1, 0, 0 },
- {0, 1, 0 },
- {0, 0, 1 },
- },
- }
-
-};
-
-#endif
-
-
-/*mpu3050*/
-#if defined (CONFIG_MPU_SENSORS_MPU3050)
-static struct mpu_platform_data mpu3050_data = {
- .int_config = 0x10,
- .orientation = { 1, 0, 0,0, 1, 0, 0, 0, 1 },
-};
-#endif
-
-/* accel */
-#if defined (CONFIG_MPU_SENSORS_KXTF9)
-static struct ext_slave_platform_data inv_mpu_kxtf9_data = {
- .bus = EXT_SLAVE_BUS_SECONDARY,
- .adapt_num = 0,
- .orientation = {1, 0, 0, 0, 1, 0, 0, 0, 1},
-};
-#endif
-
-/* compass */
-#if defined (CONFIG_MPU_SENSORS_AK8975)
-static struct ext_slave_platform_data inv_mpu_ak8975_data = {
- .bus = EXT_SLAVE_BUS_PRIMARY,
- .adapt_num = 0,
- .orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
-};
-#endif
-
-#if defined(CONFIG_GPIO_WM831X)
-struct rk29_gpio_expander_info wm831x_gpio_settinginfo[] = {
- {
- .gpio_num =WM831X_P01,// tp3
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
-
- {
- .gpio_num =WM831X_P02,//tp4
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P03,//tp2
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P04,//tp1
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P05,//tp1
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P06,//tp1
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P07,//tp1
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P08,//tp1
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P09,//tp1
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P10,//tp1
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P11,//tp1
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P12,
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
-};
-
-#endif
-
-
-
-#if defined(CONFIG_MFD_WM831X)
-static struct wm831x *gWm831x;
-int wm831x_pre_init(struct wm831x *parm)
-{
- int ret;
- printk("%s\n", __FUNCTION__);
- gWm831x = parm;
- //ILIM = 900ma
- ret = wm831x_reg_read(parm, WM831X_POWER_STATE) & 0xffff;
- wm831x_reg_write(parm, WM831X_POWER_STATE, (ret&0xfff8) | 0x04);
-
- //BATT_FET_ENA = 1
- wm831x_reg_write(parm,WM831X_SECURITY_KEY,0x9716); // unlock security key
- wm831x_set_bits(parm, WM831X_RESET_CONTROL,0x1000,0x1000);
- ret = wm831x_reg_read(parm, WM831X_RESET_CONTROL) & 0xffff&UNLOCK_SECURITY_KEY;// enternal reset active in sleep
- printk("%s:WM831X_RESET_CONTROL=0x%x\n",__FUNCTION__,ret);
- wm831x_reg_write(parm, WM831X_RESET_CONTROL, ret);
-
-
- wm831x_reg_write(parm,WM831X_SECURITY_KEY,LOCK_SECURITY_KEY); // lock security key
-
-
-#if 0
- wm831x_set_bits(parm, WM831X_LDO_ENABLE, (1 << 3), 0);
- wm831x_set_bits(parm, WM831X_LDO_ENABLE, (1 << 7), 0);
- printk("%s:disable ldo4 and ldo8 because they are enabled in uboot\n",__FUNCTION__);
-#endif
- return 0;
-}
-void cmmb_io_set_for_pm(void);
-int wm831x_post_init(struct wm831x *parm)
-{
- struct regulator *dcdc;
- struct regulator *ldo;
-
- dcdc = regulator_get(NULL, "dcdc3"); // 1th IO
- regulator_set_voltage(dcdc,3000000,3000000);
- regulator_set_suspend_voltage(dcdc, 2800000);
- regulator_enable(dcdc);
- printk("%s set dcdc3=%dmV end\n", __FUNCTION__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo10"); // 1th modem IO
- regulator_set_voltage(ldo,2800000,2800000);
- regulator_set_suspend_voltage(ldo,2800000);
- regulator_enable(ldo);
- printk("%s set ldo10=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- dcdc = regulator_get(NULL, "dcdc2"); // 2th CORE
- regulator_set_voltage(dcdc,1300000,1300000);
- regulator_set_suspend_voltage(dcdc,1000000);
- regulator_enable(dcdc);
- printk("%s set dcdc2=%dmV end\n", __FUNCTION__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- dcdc = regulator_get(NULL, "dcdc1"); // 3th ddr
- regulator_set_voltage(dcdc,1800000,1800000);
- regulator_set_suspend_voltage(dcdc, 1800000);
- regulator_enable(dcdc);
- printk("%s set dcdc1=%dmV end\n", __FUNCTION__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo1"); // 3th nand
- regulator_set_voltage(ldo,1800000,1800000);
- regulator_set_suspend_voltage(ldo,1800000);
- regulator_enable(ldo);
- printk("%s set ldo1=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo4"); // 4th usb
- regulator_set_voltage(ldo,2500000,2500000);
- regulator_set_suspend_voltage(ldo,0000000);
- regulator_enable(ldo);
- printk("%s set ldo4=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo7"); // 5th usb
- regulator_set_voltage(ldo,3300000,3300000);
- regulator_set_suspend_voltage(ldo,3300000);
- regulator_enable(ldo);
- printk("%s set ldo7=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- dcdc = regulator_get(NULL, "dcdc4"); // backlight
- regulator_set_voltage(dcdc,20000000,20000000);
- regulator_set_suspend_voltage(dcdc, 20000000);
- regulator_enable(dcdc);
- printk("%s set dcdc4=%dmV end\n", __FUNCTION__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-#if 1
-
- ldo = regulator_get(NULL, "ldo2"); //lcd
- regulator_set_voltage(ldo,2800000,2800000);
- regulator_set_suspend_voltage(ldo,2800000);
- regulator_enable(ldo);
- printk("%s set ldo2=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
-
-
- ldo = regulator_get(NULL, "ldo5"); //tf
- regulator_set_voltage(ldo,3000000,3000000);
- regulator_set_suspend_voltage(ldo,3000000);
- regulator_enable(ldo);
- printk("%s set ldo5=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo6"); //camera
- regulator_set_voltage(ldo,2800000,2800000);
- regulator_set_suspend_voltage(ldo,2800000);
- regulator_enable(ldo);
- printk("%s set ldo6=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
-
-
-/*
- ldo = regulator_get(NULL, "ldo3"); //sram
- regulator_set_voltage(ldo,1800000,1800000);
- regulator_set_suspend_voltage(ldo,1800000);
- regulator_enable(ldo);
- printk("%s set ldo3=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo); */
-
-
-
-#endif
-
- ldo = regulator_get(NULL, "ldo11");
- //regulator_enable(ldo);
- printk("%s set ldo11=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
-
-#if defined(CONFIG_SMS_SPI_ROCKCHIP)
- cmmb_io_set_for_pm();
-#endif
-
- return 0;
-}
-
-extern void wm831x_enter_sleep(void);
-extern void wm831x_exit_sleep(void);
-
-void pmu_wm831x_set_suspend_voltage(void)
-{
-
-}
-EXPORT_SYMBOL_GPL(pmu_wm831x_set_suspend_voltage);
-
-void pmu_wm831x_set_resume_voltage(void)
-{
-
-}
-EXPORT_SYMBOL_GPL(pmu_wm831x_set_resume_voltage);
-
-int wm831x_last_deinit(struct wm831x *parm)
-{
- struct regulator* ldo;
-
- printk("%s\n", __FUNCTION__);
- ldo = regulator_get(NULL, "ldo1");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo2");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo3");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo4");
- //regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo5");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo6");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo7");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo8");
- //regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo9");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo10");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- return 0;
-}
-
-struct wm831x_backlight_pdata wm831x_backlight_platdata = {
- .isink = 1, /** ISINK to use, 1 or 2 */
- .max_uA = 19484, /** Maximum current to allow */
-};
-
-struct wm831x_backup_pdata wm831x_backup_platdata = {
- .charger_enable = 1,
- .no_constant_voltage = 0, /** Disable constant voltage charging */
- .vlim = 3100, /** Voltage limit in milivolts */
- .ilim = 300, /** Current limit in microamps */
-};
-
-struct wm831x_battery_pdata wm831x_battery_platdata = {
- .enable = 1, /** Enable charging */
- .fast_enable = 1, /** Enable fast charging */
- .off_mask = 1, /** Mask OFF while charging */
- .trickle_ilim = 200, /** Trickle charge current limit, in mA */
- .vsel = 4200, /** Target voltage, in mV */
- .eoc_iterm = 50, /** End of trickle charge current, in mA */
- .fast_ilim = 500, /** Fast charge current limit, in mA */
- .timeout = 480, /** Charge cycle timeout, in minutes */
- .syslo = 3500, /* syslo threshold, in mV*/
- .sysok = 3500, /* sysko threshold, in mV*/
-};
-
-struct wm831x_status_pdata wm831x_status_platdata[WM831X_MAX_STATUS] = {
- {
- .default_src = WM831X_STATUS_OTP,
- .name = "wm831x_status0",
- .default_trigger = "wm831x_otp",
- },
- {
- .default_src = WM831X_STATUS_POWER,
- .name = "wm831x_status1",
- .default_trigger = "wm831x_power",
- },
-};
-
-
-static struct regulator_consumer_supply dcdc1_consumers[] = {
- {
- .supply = "dcdc1",
- }
-};
-static struct regulator_consumer_supply dcdc2_consumers[] = {
- {
- .supply = "dcdc2",
- },
- {
- .supply = "vcore",
- }
-};
-static struct regulator_consumer_supply dcdc3_consumers[] = {
- {
- .supply = "dcdc3",
- }
-};
-static struct regulator_consumer_supply dcdc4_consumers[] = {
- {
- .supply = "dcdc4",
- }
-};
-static struct regulator_consumer_supply epe1_consumers[] = {
- {
- .supply = "epe1",
- }
-};
-static struct regulator_consumer_supply epe2_consumers[] = {
- {
- .supply = "epe2",
- }
-};
-static struct regulator_consumer_supply ldo1_consumers[] = {
- {
- .supply = "ldo1",
- }
-};
-static struct regulator_consumer_supply ldo2_consumers[] = {
- {
- .supply = "ldo2",
- }
-};
-static struct regulator_consumer_supply ldo3_consumers[] = {
- {
- .supply = "ldo3",
- }
-};
-static struct regulator_consumer_supply ldo4_consumers[] = {
- {
- .supply = "ldo4",
- }
-};
-static struct regulator_consumer_supply ldo5_consumers[] = {
- {
- .supply = "ldo5",
- }
-};
-static struct regulator_consumer_supply ldo6_consumers[] = {
- {
- .supply = "ldo6",
- }
-};
-static struct regulator_consumer_supply ldo7_consumers[] = {
- {
- .supply = "ldo7",
- }
-};
-static struct regulator_consumer_supply ldo8_consumers[] = {
- {
- .supply = "ldo8",
- }
-};
-static struct regulator_consumer_supply ldo9_consumers[] = {
- {
- .supply = "ldo9",
- }
-};
-static struct regulator_consumer_supply ldo10_consumers[] = {
- {
- .supply = "ldo10",
- }
-};
-static struct regulator_consumer_supply ldo11_consumers[] = {
- {
- .supply = "ldo11",
- }
-};
-static struct regulator_consumer_supply isink1_consumers[] = {
- {
- .supply = "isink1",
- }
-};
-static struct regulator_consumer_supply isink2_consumers[] = {
- {
- .supply = "isink2",
- }
-};
-
-struct regulator_init_data wm831x_regulator_init_dcdc[WM831X_MAX_DCDC] = {
- {
- .constraints = {
- .name = "DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000,//0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(dcdc1_consumers),
- .consumer_supplies = dcdc1_consumers,
- },
- {
- .constraints = {
- .name = "DCDC2",
- .min_uV = 600000,
- .max_uV = 1800000,//0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(dcdc2_consumers),
- .consumer_supplies = dcdc2_consumers,
- },
- {
- .constraints = {
- .name = "DCDC3",
- .min_uV = 850000,
- .max_uV = 3400000,//0.85-3.4V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(dcdc3_consumers),
- .consumer_supplies = dcdc3_consumers,
- },
- {
- .constraints = {
- .name = "DCDC4",
- .min_uV = 00000000,
- .max_uV = 30000000,//30V/40mA
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(dcdc4_consumers),
- .consumer_supplies = dcdc4_consumers,
- },
-
-};
-struct regulator_init_data wm831x_regulator_init_epe[WM831X_MAX_EPE] = {
- {
- .constraints = {
- .name = "EPE1",
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(epe1_consumers),
- .consumer_supplies = epe1_consumers,
- },
- {
- .constraints = {
- .name = "EPE2",
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(epe2_consumers),
- .consumer_supplies = epe2_consumers,
- },
-};
-
-struct regulator_init_data wm831x_regulator_init_ldo[WM831X_MAX_LDO] = {
- {
- .constraints = {
- .name = "LDO1",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo1_consumers),
- .consumer_supplies = ldo1_consumers,
- },
- {
- .constraints = {
- .name = "LDO2",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
- .consumer_supplies = ldo2_consumers,
- },
- {
- .constraints = {
- .name = "LDO3",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo3_consumers),
- .consumer_supplies = ldo3_consumers,
- },
- {
- .constraints = {
- .name = "LDO4",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo4_consumers),
- .consumer_supplies = ldo4_consumers,
- },
- {
- .constraints = {
- .name = "LDO5",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo5_consumers),
- .consumer_supplies = ldo5_consumers,
- },
- {
- .constraints = {
- .name = "LDO6",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo6_consumers),
- .consumer_supplies = ldo6_consumers,
- },
- {
- .constraints = {
- .name = "LDO7",
- .min_uV = 1000000,
- .max_uV = 3500000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo7_consumers),
- .consumer_supplies = ldo7_consumers,
- },
- {
- .constraints = {
- .name = "LDO8",
- .min_uV = 1000000,
- .max_uV = 3500000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo8_consumers),
- .consumer_supplies = ldo8_consumers,
- },
- {
- .constraints = {
- .name = "LDO9",
- .min_uV = 1000000,
- .max_uV = 3500000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo9_consumers),
- .consumer_supplies = ldo9_consumers,
- },
- {
- .constraints = {
- .name = "LDO10",
- .min_uV = 1000000,
- .max_uV = 3500000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo10_consumers),
- .consumer_supplies = ldo10_consumers,
- },
- {
- .constraints = {
- .name = "LDO11",
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo11_consumers),
- .consumer_supplies = ldo11_consumers,
- },
-};
-
-struct regulator_init_data wm831x_regulator_init_isink[WM831X_MAX_ISINK] = {
- {
- .constraints = {
- .name = "ISINK1",
- .min_uA = 00000,
- .max_uA = 40000,
- .always_on = true,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_CURRENT,
- },
- .num_consumer_supplies = ARRAY_SIZE(isink1_consumers),
- .consumer_supplies = isink1_consumers,
- },
- {
- .constraints = {
- .name = "ISINK2",
- .min_uA = 0000000,
- .max_uA = 0000000,
- .apply_uV = false,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_CURRENT,
- },
- .num_consumer_supplies = ARRAY_SIZE(isink2_consumers),
- .consumer_supplies = isink2_consumers,
- },
-};
-
-static int wm831x_checkrange(int start,int num,int val)
-{
- if((val<(start+num))&&(val>=start))
- return 0;
- else
- return -1;
-}
-
-static int wm831x_init_pin_type(struct wm831x *wm831x)
-{
-#if 1
- struct wm831x_pdata *pdata = wm831x->dev->platform_data;
- struct rk29_gpio_expander_info *wm831x_gpio_settinginfo;
- uint16_t offset = 0;
- uint16_t wm831x_settingpin_num = 0;
- uint16_t ret = 0;
- int i = 0;
-
- if(wm831x)
- {
- wm831x_gpio_settinginfo=pdata->settinginfo;
- if(wm831x_gpio_settinginfo)
- {
- wm831x_settingpin_num = pdata->settinginfolen;
- for(i=0;i<wm831x_settingpin_num;i++)
- {
- if(!wm831x_checkrange(pdata->gpio_base,pdata->gpio_pin_num,wm831x_gpio_settinginfo[i].gpio_num))
- {
- offset = wm831x_gpio_settinginfo[i].gpio_num - pdata->gpio_base;
-
- if(wm831x_gpio_settinginfo[i].pin_type==GPIO_IN)
- {
- wm831x_set_bits(wm831x,(WM831X_GPIO1_CONTROL+offset), WM831X_GPN_DIR_MASK|WM831X_GPN_TRI_MASK, 1<<WM831X_GPN_DIR_SHIFT|1<<WM831X_GPN_TRI_SHIFT);
- }
- else
- {
- wm831x_set_bits(wm831x,(WM831X_GPIO1_CONTROL+offset), WM831X_GPN_DIR_MASK|WM831X_GPN_TRI_MASK, 1<<WM831X_GPN_TRI_SHIFT);
- if(wm831x_gpio_settinginfo[i].pin_value==GPIO_HIGH)
- {
- wm831x_set_bits(wm831x, WM831X_GPIO_LEVEL, (1 << offset),(1 << offset));
- }
- else
- {
- wm831x_set_bits(wm831x, WM831X_GPIO_LEVEL, (1 << offset),(0 << offset));
- }
- }
-
- }
- }
- }
- }
-
- for(i=0;i<pdata->gpio_pin_num;i++)
- {
- wm831x_set_bits(wm831x,(WM831X_GPIO1_CONTROL+i),
- WM831X_GPN_PULL_MASK|WM831X_GPN_POL_MASK|WM831X_GPN_OD_MASK|WM831X_GPN_TRI_MASK,
- 1<<WM831X_GPN_POL_SHIFT|1<<WM831X_GPN_TRI_SHIFT);
- ret = wm831x_reg_read(wm831x, WM831X_GPIO1_CONTROL+i);
- printk("Gpio%d Pin Configuration = %x\n",i,ret);
- }
-#endif
- return 0;
-}
-
-/*
- * GPIO Buttons
- */
-#if defined(CONFIG_KEYBOARD_WM831X_GPIO)
-static struct wm831x_gpio_keys_button wm831x_gpio_buttons[] = {
-{
- .code = KEY_MEDIA,
- .gpio = TCA6424_P21,
- .active_low = 1,
- .desc = "media",
- .wakeup = 0,
- .debounce_interval = 120,
-},
-{
- .code= KEY_VOLUMEUP,
- .gpio= WM831X_P05,
- .active_low= 1,
- .desc= "volume_up",
- .wakeup= 0,
-},
-{
- .code= KEY_CAMERA,
- .gpio= WM831X_P06,
- .active_low= 1,
- .desc= "camera",
- .wakeup= 0,
-},
-{
- .code= KEY_VOLUMEDOWN,
- .gpio= WM831X_P07,
- .active_low= 1,
- .desc= "volume_down",
- .wakeup= 0,
-},
-{
- .code= KEY_END,
- .gpio= WM831X_P09,
- .active_low= 1,
- .desc= "enter",
- .wakeup= 0,
-},
-{
- .code= KEY_MENU,
- .gpio= WM831X_P10,
- .active_low= 1,
- .desc= "menu",
- .wakeup= 0,
-},
-{
- .code= KEY_SEND,
- .gpio= WM831X_P11,
- .active_low= 1,
- .desc= "esc",
- .wakeup= 0,
-},
-{
- .code= KEY_BACK,
- .gpio= WM831X_P12,
- .active_low= 1,
- .desc= "home",
- .wakeup= 0,
-},
-};
-
-struct wm831x_gpio_keys_pdata wm831x_gpio_keys_platdata = {
- .buttons = wm831x_gpio_buttons,
- .nbuttons = ARRAY_SIZE(wm831x_gpio_buttons),
-};
-
-#endif
-struct wm831x_pdata wm831x_platdata = {
- /** Called before subdevices are set up */
- .pre_init= wm831x_pre_init,
- /** Called after subdevices are set up */
- .post_init = wm831x_post_init,
- /** Called before subdevices are power down */
- .last_deinit = wm831x_last_deinit,
-
-#if defined(CONFIG_GPIO_WM831X)
- .gpio_base=WM831X_GPIO_EXPANDER_BASE,
- .gpio_pin_num=WM831X_TOTOL_GPIO_NUM,
- .settinginfo=wm831x_gpio_settinginfo,
- .settinginfolen=ARRAY_SIZE(wm831x_gpio_settinginfo),
- .pin_type_init = wm831x_init_pin_type,
- .irq_base= NR_AIC_IRQS + 7*NUM_GROUP,
-#endif
-
- .backlight = &wm831x_backlight_platdata,
-
- .backup = &wm831x_backup_platdata,
-
- .battery = &wm831x_battery_platdata,
- //.wm831x_touch_pdata = NULL,
- //.watchdog = NULL,
-
-#if defined(CONFIG_KEYBOARD_WM831X_GPIO)
- .gpio_keys = &wm831x_gpio_keys_platdata,
-#endif
-
- /** LED1 = 0 and so on */
- .status = {&wm831x_status_platdata[0], &wm831x_status_platdata[1]},
-
- /** DCDC1 = 0 and so on */
- .dcdc = {&wm831x_regulator_init_dcdc[0], &wm831x_regulator_init_dcdc[1], &wm831x_regulator_init_dcdc[2], &wm831x_regulator_init_dcdc[3]},
-
- /** EPE1 = 0 and so on */
- .epe = {&wm831x_regulator_init_epe[0], &wm831x_regulator_init_epe[1]},
-
- /** LDO1 = 0 and so on */
- .ldo = {&wm831x_regulator_init_ldo[0], &wm831x_regulator_init_ldo[1], &wm831x_regulator_init_ldo[2], &wm831x_regulator_init_ldo[3],
- &wm831x_regulator_init_ldo[4], &wm831x_regulator_init_ldo[5], &wm831x_regulator_init_ldo[6], &wm831x_regulator_init_ldo[7],
- &wm831x_regulator_init_ldo[8], &wm831x_regulator_init_ldo[9], &wm831x_regulator_init_ldo[10]},
-
- /** ISINK1 = 0 and so on*/
- .isink = {&wm831x_regulator_init_isink[0], &wm831x_regulator_init_isink[1]},
-};
-#endif
-
-
-
-#if defined(CONFIG_RK29_GPS)
-
-#define RK29_GPS_POWER_PIN RK29_PIN6_PB2
-#define RK29_GPS_RESET_PIN RK29_PIN6_PC1
-
-int rk29_gps_power_up(void)
-{
- printk("%s \n", __FUNCTION__);
-
- gpio_request(RK29_GPS_POWER_PIN, NULL);
- gpio_direction_output(RK29_GPS_POWER_PIN, GPIO_HIGH);
-
- return 0;
-}
-
-int rk29_gps_power_down(void)
-{
- printk("%s \n", __FUNCTION__);
-
- gpio_request(RK29_GPS_POWER_PIN, NULL);
- gpio_direction_output(RK29_GPS_POWER_PIN, GPIO_LOW);
-
- return 0;
-}
-
-int rk29_gps_reset_set(int level)
-{
- gpio_request(RK29_GPS_RESET_PIN, NULL);
- if (level)
- gpio_direction_output(RK29_GPS_RESET_PIN, GPIO_HIGH);
- else
- gpio_direction_output(RK29_GPS_RESET_PIN, GPIO_LOW);
-
- return 0;
-}
-
-struct rk29_gps_data rk29_gps_info = {
- .power_up = rk29_gps_power_up,
- .power_down = rk29_gps_power_down,
- .reset = rk29_gps_reset_set,
- .uart_id = 3,
-};
-
-struct platform_device rk29_device_gps = {
- .name = "rk29_gps",
- .id = -1,
- .dev = {
- .platform_data = &rk29_gps_info,
- }
- };
-#endif
-
-/*****************************************************************************************
- * wm8994 codec
- * author: qjb@rock-chips.com
- *****************************************************************************************/
-#if defined(CONFIG_MFD_WM8994)
-static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = {
- REGULATOR_SUPPLY("DBVDD", "5-001a"),
- REGULATOR_SUPPLY("AVDD2", "5-001a"),
- REGULATOR_SUPPLY("CPVDD", "5-001a"),
-};
-
-static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = {
- REGULATOR_SUPPLY("SPKVDD1", "5-001a"),
- REGULATOR_SUPPLY("SPKVDD2", "5-001a"),
-};
-
-static struct regulator_init_data wm8994_fixed_voltage0_init_data = {
- .constraints = {
- .always_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage0_supplies),
- .consumer_supplies = wm8994_fixed_voltage0_supplies,
-};
-
-static struct regulator_init_data wm8994_fixed_voltage1_init_data = {
- .constraints = {
- .always_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage1_supplies),
- .consumer_supplies = wm8994_fixed_voltage1_supplies,
-};
-
-static struct fixed_voltage_config wm8994_fixed_voltage0_config = {
- .supply_name = "VCC_1.8V_PDA",
- .microvolts = 1800000,
- .gpio = -EINVAL,
- .init_data = &wm8994_fixed_voltage0_init_data,
-};
-
-static struct fixed_voltage_config wm8994_fixed_voltage1_config = {
- .supply_name = "V_BAT",
- .microvolts = 3700000,
- .gpio = -EINVAL,
- .init_data = &wm8994_fixed_voltage1_init_data,
-};
-
-static struct platform_device wm8994_fixed_voltage0 = {
- .name = "reg-fixed-voltage",
- .id = 0,
- .dev = {
- .platform_data = &wm8994_fixed_voltage0_config,
- },
-};
-
-static struct platform_device wm8994_fixed_voltage1 = {
- .name = "reg-fixed-voltage",
- .id = 1,
- .dev = {
- .platform_data = &wm8994_fixed_voltage1_config,
- },
-};
-
-static struct regulator_consumer_supply wm8994_avdd1_supply =
- REGULATOR_SUPPLY("AVDD1", "5-001a");
-
-static struct regulator_consumer_supply wm8994_dcvdd_supply =
- REGULATOR_SUPPLY("DCVDD", "5-001a");
-
-
-
-static struct regulator_init_data wm8994_ldo1_data = {
- .constraints = {
- .name = "AVDD1_3.0V",
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = 1,
- .consumer_supplies = &wm8994_avdd1_supply,
-};
-
-static struct regulator_init_data wm8994_ldo2_data = {
- .constraints = {
- .name = "DCVDD_1.0V",
- },
- .num_consumer_supplies = 1,
- .consumer_supplies = &wm8994_dcvdd_supply,
-};
-
-static struct wm8994_pdata wm8994_platform_data = {
-#if defined (CONFIG_GPIO_WM8994)
- .gpio_base = WM8994_GPIO_EXPANDER_BASE,
- //Fill value to initialize the GPIO
-// .gpio_defaults ={},
- /* configure gpio1 function: 0x0001(Logic level input/output) */
-// .gpio_defaults[0] = 0x0001,
- /* configure gpio3/4/5/7 function for AIF2 voice */
- .gpio_defaults[2] = 0x2100,
- .gpio_defaults[3] = 0x2100,
- .gpio_defaults[4] = 0xA100,
-// .gpio_defaults[6] = 0x0100,
- /* configure gpio8/9/10/11 function for AIF3 BT */
- .gpio_defaults[7] = 0xA100,
- .gpio_defaults[8] = 0x2100,
- .gpio_defaults[9] = 0x2100,
- .gpio_defaults[10] = 0x2100,
-#endif
-
- .ldo[0] = { RK29_PIN5_PA1, NULL, &wm8994_ldo1_data }, /* XM0FRNB_2 */
- .ldo[1] = { 0, NULL, &wm8994_ldo2_data },
-
- .micdet_irq = 0,
- .irq_base = 0,
-
- .lineout1_diff = 1,
-// .BB_input_diff = 1,
-};
-#endif
-
-#ifdef CONFIG_RK_HEADSET_DET
-#define HEADSET_GPIO RK29_PIN4_PD2
-struct rk_headset_pdata rk_headset_info = {
- .Headset_gpio = RK29_PIN4_PD2,
- .headset_in_type= HEADSET_IN_HIGH,
- .Hook_gpio = RK29_PIN6_PB6,//Detection Headset--Must be set
- .hook_key_code = KEY_MEDIA,
-};
-
-struct platform_device rk_device_headset = {
- .name = "rk_headsetdet",
- .id = 0,
- .dev = {
- .platform_data = &rk_headset_info,
- }
-};
-#endif
-
-#if defined(CONFIG_GS_L3G4200D)
-
-#include <linux/l3g4200d.h>
-#define L3G4200D_INT_PIN RK29_PIN5_PA3
-
-static int l3g4200d_init_platform_hw(void)
-{
- if (gpio_request(L3G4200D_INT_PIN, NULL) != 0) {
- gpio_free(L3G4200D_INT_PIN);
- printk("%s: request l3g4200d int pin error\n", __func__);
- return -EIO;
- }
- gpio_pull_updown(L3G4200D_INT_PIN, 1);
- return 0;
-}
-
-static struct l3g4200d_platform_data l3g4200d_info = {
- .fs_range = 1,
-
- .axis_map_x = 0,
- .axis_map_y = 1,
- .axis_map_z = 2,
-
- .negate_x = 1,
- .negate_y = 1,
- .negate_z = 0,
-
- .init = l3g4200d_init_platform_hw,
-};
-
-#endif
-
-/*****************************************************************************************
- * i2c devices
- * author: kfx@rock-chips.com
-*****************************************************************************************/
-static int rk29_i2c0_io_init(void)
-{
-#ifdef CONFIG_RK29_I2C0_CONTROLLER
- rk29_mux_api_set(GPIO2B7_I2C0SCL_NAME, GPIO2L_I2C0_SCL);
- rk29_mux_api_set(GPIO2B6_I2C0SDA_NAME, GPIO2L_I2C0_SDA);
-#else
- rk29_mux_api_set(GPIO2B7_I2C0SCL_NAME, GPIO2L_GPIO2B7);
- rk29_mux_api_set(GPIO2B6_I2C0SDA_NAME, GPIO2L_GPIO2B6);
-#endif
- return 0;
-}
-
-static int rk29_i2c1_io_init(void)
-{
-#ifdef CONFIG_RK29_I2C1_CONTROLLER
- rk29_mux_api_set(GPIO1A7_I2C1SCL_NAME, GPIO1L_I2C1_SCL);
- rk29_mux_api_set(GPIO1A6_I2C1SDA_NAME, GPIO1L_I2C1_SDA);
-#else
- rk29_mux_api_set(GPIO1A7_I2C1SCL_NAME, GPIO1L_GPIO1A7);
- rk29_mux_api_set(GPIO1A6_I2C1SDA_NAME, GPIO1L_GPIO1A6);
-#endif
- return 0;
-}
-static int rk29_i2c2_io_init(void)
-{
-#ifdef CONFIG_RK29_I2C2_CONTROLLER
- rk29_mux_api_set(GPIO5D4_I2C2SCL_NAME, GPIO5H_I2C2_SCL);
- rk29_mux_api_set(GPIO5D3_I2C2SDA_NAME, GPIO5H_I2C2_SDA);
-#else
- rk29_mux_api_set(GPIO5D4_I2C2SCL_NAME, GPIO5H_GPIO5D4);
- rk29_mux_api_set(GPIO5D3_I2C2SDA_NAME, GPIO5H_GPIO5D3);
-#endif
- return 0;
-}
-
-static int rk29_i2c3_io_init(void)
-{
-#ifdef CONFIG_RK29_I2C3_CONTROLLER
- rk29_mux_api_set(GPIO2B5_UART3RTSN_I2C3SCL_NAME, GPIO2L_I2C3_SCL);
- rk29_mux_api_set(GPIO2B4_UART3CTSN_I2C3SDA_NAME, GPIO2L_I2C3_SDA);
-#else
- rk29_mux_api_set(GPIO2B5_UART3RTSN_I2C3SCL_NAME, GPIO2L_GPIO2B5);
- rk29_mux_api_set(GPIO2B4_UART3CTSN_I2C3SDA_NAME, GPIO2L_GPIO2B4);
-#endif
- return 0;
-}
-#ifdef CONFIG_RK29_I2C0_CONTROLLER
-struct rk29_i2c_platform_data default_i2c0_data = {
- .bus_num = 0,
- .flags = 0,
- .slave_addr = 0xff,
- .scl_rate = 400*1000,
- .mode = I2C_MODE_IRQ,
- .io_init = rk29_i2c0_io_init,
-};
-#else
-struct i2c_gpio_platform_data default_i2c0_data = {
- .sda_pin = RK29_PIN2_PB6,
- .scl_pin = RK29_PIN2_PB7,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(200),
- .bus_num = 0,
- .io_init = rk29_i2c0_io_init,
-};
-#endif
-#ifdef CONFIG_RK29_I2C1_CONTROLLER
-struct rk29_i2c_platform_data default_i2c1_data = {
- .bus_num = 1,
- .flags = 0,
- .slave_addr = 0xff,
- .scl_rate = 400*1000,
- .mode = I2C_MODE_IRQ,
- .io_init = rk29_i2c1_io_init,
-};
-#else
-struct i2c_gpio_platform_data default_i2c1_data = {
- .sda_pin = RK29_PIN1_PA6,
- .scl_pin = RK29_PIN1_PA7,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(200),
- .bus_num = 1,
- .io_init = rk29_i2c1_io_init,
-};
-#endif
-#ifdef CONFIG_RK29_I2C2_CONTROLLER
-struct rk29_i2c_platform_data default_i2c2_data = {
- .bus_num = 2,
- .flags = 0,
- .slave_addr = 0xff,
- .scl_rate = 400*1000,
- .mode = I2C_MODE_IRQ,
- .io_init = rk29_i2c2_io_init,
-};
-#else
-struct i2c_gpio_platform_data default_i2c2_data = {
- .sda_pin = RK29_PIN5_PD3,
- .scl_pin = RK29_PIN5_PD4,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(200),
- .bus_num = 2,
- .io_init = rk29_i2c2_io_init,
-};
-#endif
-#ifdef CONFIG_RK29_I2C3_CONTROLLER
-struct rk29_i2c_platform_data default_i2c3_data = {
- .bus_num = 3,
- .flags = 0,
- .slave_addr = 0xff,
- .scl_rate = 400*1000,
- .mode = I2C_MODE_IRQ,
- .io_init = rk29_i2c3_io_init,
-};
-#else
-struct i2c_gpio_platform_data default_i2c3_data = {
- .sda_pin = RK29_PIN5_PB5,
- .scl_pin = RK29_PIN5_PB4,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(200),
- .bus_num = 3,
- .io_init = rk29_i2c3_io_init,
-};
-#endif
-#ifdef CONFIG_I2C0_RK29
-static struct i2c_board_info __initdata board_i2c0_devices[] = {
-#if defined (CONFIG_RK1000_CONTROL)
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_WM8900)
- {
- .type = "wm8900",
- .addr = 0x1A,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_WM8994)
- {
- .type = "wm8994",
- .addr = 0x1a,
- .flags = 0,
- #if defined(CONFIG_MFD_WM8994)
- .platform_data = &wm8994_platform_data,
- #endif
- },
-#endif
-#if defined (CONFIG_BATTERY_STC3100)
- {
- .type = "stc3100",
- .addr = 0x70,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_BATTERY_BQ27510)
- {
- .type = "bq27510",
- .addr = 0x55,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_RTC_HYM8563)
- {
- .type = "rtc_hym8563",
- .addr = 0x51,
- .flags = 0,
- .irq = RK29_PIN0_PA1,
- },
-#endif
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1c,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_GS_BMA023)
- {
- .type = "bma150",
- .addr = 0x38,
- .flags = 0,
- .irq = BMA023_INT_PIN,
- .platform_data = &bma023_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8973)
- {
- .type = "ak8973",
- .addr = 0x1d,
- .flags = 0,
- .irq = RK29_PIN6_PC5,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK29_PIN6_PC5,
- .platform_data = &akm8975_info,
- },
-#endif
-#if defined (CONFIG_INPUT_LPSENSOR_ISL29028)
- {
- .type = "isl29028",
- .addr = 0x44,
- .flags = 0,
- .irq = RK29_PIN4_PD3,
- },
-#endif
-#if defined (CONFIG_INPUT_LPSENSOR_AL3006)
- {
- .type = "al3006",
- .addr = 0x1C, //sel = 0; if sel =1, then addr = 0x1D
- .flags = 0,
- .irq = RK29_PIN4_PD3,
- },
-#endif
-#if defined (CONFIG_ANX7150)
- {
- .type = "anx7150",
- .addr = 0x39, //0x39, 0x3d
- .flags = 0,
- .irq = RK29_PIN2_PA3,
- },
-#endif
-#if defined (CONFIG_GS_L3G4200D)
- {
- .type = "gs_l3g4200d",
- .addr = 0x69,
- .flags = 0,
- .irq = L3G4200D_INT_PIN,
- .platform_data = &l3g4200d_info,
- },
-#endif
-#if defined (CONFIG_MPU_SENSORS_MPU3050)
- {
- .type = "mpu3050",
- .addr = 0x68,
- .flags = 0,
- .irq = RK29_PIN4_PC4,
- .platform_data = &mpu3050_data,
- },
-#endif
-#if defined (CONFIG_MPU_SENSORS_KXTF9)
- {
- .type = "kxtf9",
- .addr = 0x0f,
- .flags = 0,
- //.irq = RK29_PIN6_PC4,
- .platform_data = &inv_mpu_kxtf9_data,
- },
-#endif
-#if defined (CONFIG_MPU_SENSORS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- //.irq = RK29_PIN6_PC5,
- .platform_data = &inv_mpu_ak8975_data,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C1_RK29
-static struct i2c_board_info __initdata board_i2c1_devices[] = {
-#if defined (CONFIG_RK1000_CONTROL1)
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_MFD_WM831X_I2C)
- {
- .type = "wm8310",
- .addr = 0x34,
- .flags = 0,
- .irq = RK29_PIN4_PD0,
- .platform_data = &wm831x_platdata,
- },
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C2_RK29
-static struct i2c_board_info __initdata board_i2c2_devices[] = {
-#if defined (CONFIG_TOUCHSCREEN_GT801_IIC)
-{
- .type = "gt801_ts",
- .addr = 0x55,
- .flags = 0,
- .irq = RK29_PIN4_PD5,
- .platform_data = >801_info,
-},
-#endif
-
-#if defined (CONFIG_TOUCHSCREEN_GT818_IIC)
-{
- .type = "gt818_ts",
- .addr = 0x5d,
- .flags = 0,
- .irq = RK29_PIN4_PD5,
- .platform_data = >818_info,
-},
-#endif
-
-#if defined (CONFIG_TOUCHSCREEN_ILI2102_IIC)
-{
- .type = "ili2102_ts",
- .addr = 0x41,
- .flags = I2C_M_NEED_DELAY,
- .udelay = 600,
- .irq = RK29_PIN4_PD5,
- .platform_data = &ili2102_info,
-},
-#endif
-#if defined (CONFIG_HANNSTAR_P1003)
- {
- .type = "p1003_touch",
- .addr = 0x04,
- .flags = 0,
- .irq = RK29_PIN0_PA2,
- .platform_data = &p1003_info,
- },
-#endif
-#if defined (CONFIG_EETI_EGALAX)
- {
- .type = "egalax_i2c",
- .addr = 0x04,
- .flags = 0,
- .irq = RK29_PIN4_PD5,
- .platform_data = &eeti_egalax_info,
- },
-#endif
-#if defined (CONFIG_TOUCHSCREEN_PIXCIR)
- {
- .type = "pixcir_ts",
- .addr = 0x5c,
- .flags = 0,
- .irq = RK29_PIN4_PD5,
- .platform_data = &pixcir_info,
- },
-#endif
-#if defined (CONFIG_TOUCHSCREEN_FT5X0X)
- {
- .type = "ft5x0x_ts",
- .addr = (0x70>>1),
- .flags = 0,
- .irq = RK29_PIN4_PD5,
- .platform_data = &ft5x0x_info,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK29
-static struct i2c_board_info __initdata board_i2c3_devices[] = {
- //I2c3 only for camera
-};
-#endif
-
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#define CONFIG_SENSOR_POWER_IOCTL_USR 0
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 1
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_RESET_IOCTL_USR
-static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
-static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- //#error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
- int ret;
- ret = gpio_request(RK29_PIN0_PD1, NULL);
- if(ret != 0)
- {
- gpio_free(RK29_PIN0_PD1);
- printk("sensor_flash_usr_cb error!!\n");
- return 0;
- }
- ret = gpio_request(RK29_PIN6_PB5, NULL);
- if(ret != 0)
- {
- gpio_free(RK29_PIN6_PB5);
- printk("sensor_flash_usr_cb error!!\n");
- return 0;
- }
- if(on) {
- gpio_direction_output(RK29_PIN0_PD1, GPIO_HIGH);
- gpio_set_value(RK29_PIN0_PD1, 1);
-
- gpio_direction_output(RK29_PIN6_PB5, GPIO_HIGH);
- gpio_set_value(RK29_PIN6_PB5, 1);
- }
- else
- {
- gpio_direction_output(RK29_PIN0_PD1, GPIO_HIGH);
- gpio_set_value(RK29_PIN0_PD1, 0);
-
- gpio_direction_output(RK29_PIN6_PB5, GPIO_HIGH);
- gpio_set_value(RK29_PIN6_PB5, 0);
- }
- gpio_free(RK29_PIN0_PD1);
- gpio_free(RK29_PIN6_PB5);
- return 0;
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-#include "../../../drivers/media/video/rk29_camera.c"
-#endif
-
-/*****************************************************************************************
- * backlight devices
- * author: nzy@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- /*
- GPIO1B5_PWM0_NAME, GPIO1L_PWM0
- GPIO5D2_PWM1_UART1SIRIN_NAME, GPIO5H_PWM1
- GPIO2A3_SDMMC0WRITEPRT_PWM2_NAME, GPIO2L_PWM2
- GPIO1A5_EMMCPWREN_PWM3_NAME, GPIO1L_PWM3
- */
-
-#define PWM_ID 0
-#define PWM_MUX_NAME GPIO1B5_PWM0_NAME
-#define PWM_MUX_MODE GPIO1L_PWM0
-#define PWM_MUX_MODE_GPIO GPIO1L_GPIO1B5
-#define PWM_EFFECT_VALUE 1
-
-//#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-#define BL_EN_MUX_NAME GPIOF34_UART3_SEL_NAME
-#define BL_EN_MUX_MODE IOMUXB_GPIO1_B34
-
-#define BL_EN_PIN GPIO0L_GPIO0A5
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
-
- rk29_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
- #ifdef LCD_DISP_ON_PIN
- rk29_mux_api_set(BL_EN_MUX_NAME, BL_EN_MUX_MODE);
-
- ret = gpio_request(BL_EN_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(BL_EN_PIN);
- }
-
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
- #endif
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0;
- #ifdef LCD_DISP_ON_PIN
- gpio_free(BL_EN_PIN);
- #endif
- rk29_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- return ret;
-}
-struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
-};
-#endif
-/*****************************************************************************************
-* pwm voltage regulator devices
-******************************************************************************************/
-#if defined (CONFIG_RK29_PWM_REGULATOR)
-
-#define REGULATOR_PWM_ID 2
-#define REGULATOR_PWM_MUX_NAME GPIO2A3_SDMMC0WRITEPRT_PWM2_NAME
-#define REGULATOR_PWM_MUX_MODE GPIO2L_PWM2
-#define REGULATOR_PWM_MUX_MODE_GPIO GPIO2L_GPIO2A3
-#define REGULATOR_PWM_GPIO RK29_PIN2_PA3
-
-static struct regulator_consumer_supply pwm_consumers[] = {
- {
- .supply = "vcore",
- }
-};
-
-static struct regulator_init_data rk29_pwm_regulator_data = {
- .constraints = {
- .name = "PWM2",
- .min_uV = 950000,
- .max_uV = 1400000,
- .apply_uV = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_consumers),
- .consumer_supplies = pwm_consumers,
-};
-
-static struct pwm_platform_data rk29_regulator_pwm_platform_data = {
- .pwm_id = REGULATOR_PWM_ID,
- .pwm_gpio = REGULATOR_PWM_GPIO,
- //.pwm_iomux_name[] = REGULATOR_PWM_MUX_NAME;
- .pwm_iomux_name = REGULATOR_PWM_MUX_NAME,
- .pwm_iomux_pwm = REGULATOR_PWM_MUX_MODE,
- .pwm_iomux_gpio = REGULATOR_PWM_MUX_MODE_GPIO,
- .init_data = &rk29_pwm_regulator_data,
-};
-
-static struct platform_device rk29_device_pwm_regulator = {
- .name = "pwm-voltage-regulator",
- .id = -1,
- .dev = {
- .platform_data = &rk29_regulator_pwm_platform_data,
- },
-};
-
-#endif
-#define POWER_ON_PIN RK29_PIN4_PA4
-#define BP_VOL_PIN RK29_PIN6_PD3
-
-#if defined(CONFIG_TDSC8800)
-
-static int tdsc8800_io_init(void)
-{
-
- return 0;
-}
-
-static int tdsc8800_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk2818_23d_data rk29_tdsc8800_info = {
- .io_init = tdsc8800_io_init,
- .io_deinit = tdsc8800_io_deinit,
- .bp_power = BP_VOL_PIN,
- .bp_power_active_low = 1,
-};
-struct platform_device rk29_device_tdsc8800 = {
- .name = "tdsc8800",
- .id = -1,
- .dev = {
- .platform_data = &rk29_tdsc8800_info,
- }
- };
-#endif
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
-#define SDMMC0_WRITE_PROTECT_PIN RK29_PIN2_PA3 //According to your own project to set the value of write-protect-pin.
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
-#define SDMMC1_WRITE_PROTECT_PIN RK29_PIN1_PC1 //According to your own project to set the value of write-protect-pin.
-#endif
-
-
-/*****************************************************************************************
- * SDMMC devices
-*****************************************************************************************/
-#if !defined(CONFIG_SDMMC_RK29_OLD)
-static void rk29_sdmmc_gpio_open(int device_id, int on)
-{
- switch(device_id)
- {
- case 0://mmc0
- {
- #ifdef CONFIG_SDMMC0_RK29
- if(on)
- {
- gpio_direction_output(RK29_PIN1_PD0,GPIO_HIGH);//set mmc0-clk to high
- gpio_direction_output(RK29_PIN1_PD1,GPIO_HIGH);//set mmc0-cmd to high.
- gpio_direction_output(RK29_PIN1_PD2,GPIO_HIGH);//set mmc0-data0 to high.
- gpio_direction_output(RK29_PIN1_PD3,GPIO_HIGH);//set mmc0-data1 to high.
- gpio_direction_output(RK29_PIN1_PD4,GPIO_HIGH);//set mmc0-data2 to high.
- gpio_direction_output(RK29_PIN1_PD5,GPIO_HIGH);//set mmc0-data3 to high.
-
- mdelay(30);
- }
- else
- {
- rk29_mux_api_set(GPIO1D0_SDMMC0CLKOUT_NAME, GPIO1H_GPIO1_D0);
- gpio_request(RK29_PIN1_PD0, "mmc0-clk");
- gpio_direction_output(RK29_PIN1_PD0,GPIO_LOW);//set mmc0-clk to low.
-
- rk29_mux_api_set(GPIO1D1_SDMMC0CMD_NAME, GPIO1H_GPIO1_D1);
- gpio_request(RK29_PIN1_PD1, "mmc0-cmd");
- gpio_direction_output(RK29_PIN1_PD1,GPIO_LOW);//set mmc0-cmd to low.
-
- rk29_mux_api_set(GPIO1D2_SDMMC0DATA0_NAME, GPIO1H_GPIO1D2);
- gpio_request(RK29_PIN1_PD2, "mmc0-data0");
- gpio_direction_output(RK29_PIN1_PD2,GPIO_LOW);//set mmc0-data0 to low.
-
- rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_GPIO1D3);
- gpio_request(RK29_PIN1_PD3, "mmc0-data1");
- gpio_direction_output(RK29_PIN1_PD3,GPIO_LOW);//set mmc0-data1 to low.
-
- rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_GPIO1D4);
- gpio_request(RK29_PIN1_PD4, "mmc0-data2");
- gpio_direction_output(RK29_PIN1_PD4,GPIO_LOW);//set mmc0-data2 to low.
-
- rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_GPIO1D5);
- gpio_request(RK29_PIN1_PD5, "mmc0-data3");
- gpio_direction_output(RK29_PIN1_PD5,GPIO_LOW);//set mmc0-data3 to low.
-
- mdelay(30);
- }
- #endif
- }
- break;
-
- case 1://mmc1
- {
- #ifdef CONFIG_SDMMC1_RK29
- if(on)
- {
- gpio_direction_output(RK29_PIN1_PC7,GPIO_HIGH);//set mmc1-clk to high
- gpio_direction_output(RK29_PIN1_PC2,GPIO_HIGH);//set mmc1-cmd to high.
- gpio_direction_output(RK29_PIN1_PC3,GPIO_HIGH);//set mmc1-data0 to high.
- gpio_direction_output(RK29_PIN1_PC4,GPIO_HIGH);//set mmc1-data1 to high.
- gpio_direction_output(RK29_PIN1_PC5,GPIO_HIGH);//set mmc1-data2 to high.
- gpio_direction_output(RK29_PIN1_PC6,GPIO_HIGH);//set mmc1-data3 to high.
- mdelay(100);
- }
- else
- {
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_GPIO1C7);
- gpio_request(RK29_PIN1_PC7, "mmc1-clk");
- gpio_direction_output(RK29_PIN1_PC7,GPIO_LOW);//set mmc1-clk to low.
-
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_GPIO1C2);
- gpio_request(RK29_PIN1_PC2, "mmc1-cmd");
- gpio_direction_output(RK29_PIN1_PC2,GPIO_LOW);//set mmc1-cmd to low.
-
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_GPIO1C3);
- gpio_request(RK29_PIN1_PC3, "mmc1-data0");
- gpio_direction_output(RK29_PIN1_PC3,GPIO_LOW);//set mmc1-data0 to low.
-
- mdelay(100);
- }
- #endif
- }
- break;
-
- case 2: //mmc2
- break;
-
- default:
- break;
- }
-}
-
-
-static void rk29_sdmmc_set_iomux_mmc0(unsigned int bus_width)
-{
- switch (bus_width)
- {
-
- case 1://SDMMC_CTYPE_4BIT:
- {
- rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_SDMMC0_DATA1);
- rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_SDMMC0_DATA2);
- rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_SDMMC0_DATA3);
- }
- break;
-
- case 0x10000://SDMMC_CTYPE_8BIT:
- break;
- case 0xFFFF: //gpio_reset
- {
- rk29_mux_api_set(GPIO5D5_SDMMC0PWREN_NAME, GPIO5H_GPIO5D5);
- gpio_request(RK29_PIN5_PD5,"sdmmc-power");
- gpio_direction_output(RK29_PIN5_PD5,GPIO_HIGH); //power-off
-
- rk29_sdmmc_gpio_open(0, 0);
-
- gpio_direction_output(RK29_PIN5_PD5,GPIO_LOW); //power-on
-
- rk29_sdmmc_gpio_open(0, 1);
- }
- break;
-
- default: //case 0://SDMMC_CTYPE_1BIT:
- {
- rk29_mux_api_set(GPIO1D1_SDMMC0CMD_NAME, GPIO1H_SDMMC0_CMD);
- rk29_mux_api_set(GPIO1D0_SDMMC0CLKOUT_NAME, GPIO1H_SDMMC0_CLKOUT);
- rk29_mux_api_set(GPIO1D2_SDMMC0DATA0_NAME, GPIO1H_SDMMC0_DATA0);
-
- rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_GPIO1D3);
- gpio_request(RK29_PIN1_PD3, "mmc0-data1");
- gpio_direction_output(RK29_PIN1_PD3,GPIO_HIGH);
-
- rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_GPIO1D4);
- gpio_request(RK29_PIN1_PD4, "mmc0-data2");
- gpio_direction_output(RK29_PIN1_PD4,GPIO_HIGH);
-
- rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_GPIO1D5);
- gpio_request(RK29_PIN1_PD5, "mmc0-data3");
- gpio_direction_output(RK29_PIN1_PD5,GPIO_HIGH);
- }
- break;
- }
-}
-
-static void rk29_sdmmc_set_iomux_mmc1(unsigned int bus_width)
-{
-#if 0
- switch (bus_width)
- {
-
- case 1://SDMMC_CTYPE_4BIT:
- {
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);
- rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_SDMMC1_DATA1);
- rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_SDMMC1_DATA2);
- rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_SDMMC1_DATA3);
- }
- break;
-
- case 0x10000://SDMMC_CTYPE_8BIT:
- break;
- case 0xFFFF:
- {
- rk29_sdmmc_gpio_open(1, 0);
- rk29_sdmmc_gpio_open(1, 1);
- }
- break;
-
- default: //case 0://SDMMC_CTYPE_1BIT:
- {
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);
-
- rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_GPIO1C4);
- gpio_request(RK29_PIN1_PC4, "mmc1-data1");
- gpio_direction_output(RK29_PIN1_PC4,GPIO_HIGH);
-
- rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_GPIO1C5);
- gpio_request(RK29_PIN1_PC5, "mmc1-data2");
- gpio_direction_output(RK29_PIN1_PC5,GPIO_HIGH);
-
- rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_GPIO1C6);
- gpio_request(RK29_PIN1_PC6, "mmc1-data3");
- gpio_direction_output(RK29_PIN1_PC6,GPIO_HIGH);
-
- }
- break;
- }
-#else
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);
- rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_SDMMC1_DATA1);
- rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_SDMMC1_DATA2);
- rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_SDMMC1_DATA3);
-
-#endif
-}
-
-static void rk29_sdmmc_set_iomux_mmc2(unsigned int bus_width)
-{
- ;//
-}
-
-static void rk29_sdmmc_set_iomux(int device_id, unsigned int bus_width)
-{
- switch(device_id)
- {
- case 0:
- #ifdef CONFIG_SDMMC0_RK29
- rk29_sdmmc_set_iomux_mmc0(bus_width);
- #endif
- break;
- case 1:
- #ifdef CONFIG_SDMMC1_RK29
- rk29_sdmmc_set_iomux_mmc1(bus_width);
- #endif
- break;
- case 2:
- rk29_sdmmc_set_iomux_mmc2(bus_width);
- break;
- default:
- break;
- }
-}
-#endif
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- rk29_mux_api_set(GPIO1D1_SDMMC0CMD_NAME, GPIO1H_SDMMC0_CMD);
- rk29_mux_api_set(GPIO1D0_SDMMC0CLKOUT_NAME, GPIO1H_SDMMC0_CLKOUT);
- rk29_mux_api_set(GPIO1D2_SDMMC0DATA0_NAME, GPIO1H_SDMMC0_DATA0);
- rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_SDMMC0_DATA1);
- rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_SDMMC0_DATA2);
- rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_SDMMC0_DATA3);
-
- rk29_mux_api_set(GPIO2A2_SDMMC0DETECTN_NAME, GPIO2L_GPIO2A2);
-
- rk29_mux_api_set(GPIO5D5_SDMMC0PWREN_NAME, GPIO5H_GPIO5D5); ///GPIO5H_SDMMC0_PWR_EN); ///GPIO5H_GPIO5D5);
- gpio_request(RK29_PIN5_PD5,"sdmmc");
-#if 0
- gpio_set_value(RK29_PIN5_PD5,GPIO_HIGH);
- mdelay(100);
- gpio_set_value(RK29_PIN5_PD5,GPIO_LOW);
-#else
- gpio_direction_output(RK29_PIN5_PD5,GPIO_LOW);
-#endif
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- rk29_mux_api_set(GPIO2A2_SDMMC0DETECTN_NAME, GPIO2L_SDMMC0_DETECT_N);//Modifyed by xbw.
-
- #if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN,"sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
- #endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail = (MMC_VDD_25_26|MMC_VDD_26_27|MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30|
- MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33|
- MMC_VDD_33_34|MMC_VDD_34_35| MMC_VDD_35_36),
- .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
- .detect_irq = INVALID_GPIO,
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
-#else
- .write_prt = INVALID_GPIO,
-#endif
-};
-#endif
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);
- rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_SDMMC1_DATA1);
- rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_SDMMC1_DATA2);
- rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_SDMMC1_DATA3);
- //rk29_mux_api_set(GPIO1C0_UART0CTSN_SDMMC1DETECTN_NAME, GPIO1H_SDMMC1_DETECT_N);
-
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN,"sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
-static int rk29sdk_wifi_status(struct device *dev);
-static int rk29sdk_wifi_status_register(void (*callback)(int card_presend, void *dev_id), void *dev_id);
-#endif
-
-#define RK29SDK_WIFI_SDIO_CARD_DETECT_N RK29_PIN1_PD6
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail = (MMC_VDD_25_26|MMC_VDD_26_27|MMC_VDD_27_28|MMC_VDD_28_29|
- MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32|
- MMC_VDD_32_33|MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_SDIO_IRQ|
- MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-#if 0
- .detect_irq = RK29SDK_WIFI_SDIO_CARD_DETECT_N,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
-#else
-//for wifi develop board
- .detect_irq = INVALID_GPIO,
- .enable_sd_wakeup = 0,
-#endif
-
-};
-#endif ////endif--#ifdef CONFIG_SDMMC1_RK29
-
-
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
-#define RK29SDK_WIFI_BT_GPIO_POWER_N RK29_PIN5_PD6
-#define RK29SDK_WIFI_GPIO_RESET_N RK29_PIN6_PC0
-#define RK29SDK_BT_GPIO_RESET_N RK29_PIN6_PC7
-
-static int rk29sdk_wifi_cd = 0; /* wifi virtual 'card detect' status */
-static void (*wifi_status_cb)(int card_present, void *dev_id);
-static void *wifi_status_cb_devid;
-int rk29sdk_wifi_power_state = 0;
-int rk29sdk_bt_power_state = 0;
-
-static int rk29sdk_wifi_status(struct device *dev)
-{
- return rk29sdk_wifi_cd;
-}
-
-static int rk29sdk_wifi_status_register(void (*callback)(int card_present, void *dev_id), void *dev_id)
-{
- if(wifi_status_cb)
- return -EAGAIN;
- wifi_status_cb = callback;
- wifi_status_cb_devid = dev_id;
- return 0;
-}
-
-static int rk29sdk_wifi_bt_gpio_control_init(void)
-{
- if (gpio_request(RK29SDK_WIFI_BT_GPIO_POWER_N, "wifi_bt_power")) {
- pr_info("%s: request wifi_bt power gpio failed\n", __func__);
- return -1;
- }
-
- if (gpio_request(RK29SDK_WIFI_GPIO_RESET_N, "wifi reset")) {
- pr_info("%s: request wifi reset gpio failed\n", __func__);
- gpio_free(RK29SDK_WIFI_BT_GPIO_POWER_N);
- return -1;
- }
-
- if (gpio_request(RK29SDK_BT_GPIO_RESET_N, "bt reset")) {
- pr_info("%s: request bt reset gpio failed\n", __func__);
- gpio_free(RK29SDK_WIFI_GPIO_RESET_N);
- return -1;
- }
-
- gpio_direction_output(RK29SDK_WIFI_BT_GPIO_POWER_N, GPIO_LOW);
- gpio_direction_output(RK29SDK_WIFI_GPIO_RESET_N, GPIO_LOW);
- gpio_direction_output(RK29SDK_BT_GPIO_RESET_N, GPIO_LOW);
-
- #if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
-
- rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_GPIO1C4);
- gpio_request(RK29_PIN1_PC4, "mmc1-data1");
- gpio_direction_output(RK29_PIN1_PC4,GPIO_LOW);//set mmc1-data1 to low.
-
- rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_GPIO1C5);
- gpio_request(RK29_PIN1_PC5, "mmc1-data2");
- gpio_direction_output(RK29_PIN1_PC5,GPIO_LOW);//set mmc1-data2 to low.
-
- rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_GPIO1C6);
- gpio_request(RK29_PIN1_PC6, "mmc1-data3");
- gpio_direction_output(RK29_PIN1_PC6,GPIO_LOW);//set mmc1-data3 to low.
-
- rk29_sdmmc_gpio_open(1, 0); //added by xbw at 2011-10-13
- #endif
- pr_info("%s: init finished\n",__func__);
-
- return 0;
-}
-
-static int rk29sdk_wifi_power(int on)
-{
- pr_info("%s: %d\n", __func__, on);
- if (on){
- gpio_set_value(RK29SDK_WIFI_BT_GPIO_POWER_N, GPIO_HIGH);
-
- #if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
- rk29_sdmmc_gpio_open(1, 1); //added by xbw at 2011-10-13
- #endif
-
- gpio_set_value(RK29SDK_WIFI_GPIO_RESET_N, GPIO_HIGH);
- mdelay(100);
- pr_info("wifi turn on power\n");
- }else{
- if (!rk29sdk_bt_power_state){
- gpio_set_value(RK29SDK_WIFI_BT_GPIO_POWER_N, GPIO_LOW);
-
- #if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
- rk29_sdmmc_gpio_open(1, 0); //added by xbw at 2011-10-13
- #endif
-
- mdelay(100);
- pr_info("wifi shut off power\n");
- }else
- {
- pr_info("wifi shouldn't shut off power, bt is using it!\n");
- }
- gpio_set_value(RK29SDK_WIFI_GPIO_RESET_N, GPIO_LOW);
-
- }
-
- rk29sdk_wifi_power_state = on;
- return 0;
-}
-
-static int rk29sdk_wifi_reset_state;
-static int rk29sdk_wifi_reset(int on)
-{
- pr_info("%s: %d\n", __func__, on);
- gpio_set_value(RK29SDK_WIFI_GPIO_RESET_N, on);
- mdelay(100);
- rk29sdk_wifi_reset_state = on;
- return 0;
-}
-
-int rk29sdk_wifi_set_carddetect(int val)
-{
- pr_info("%s:%d\n", __func__, val);
- rk29sdk_wifi_cd = val;
- if (wifi_status_cb){
- wifi_status_cb(val, wifi_status_cb_devid);
- }else {
- pr_warning("%s, nobody to notify\n", __func__);
- }
- return 0;
-}
-EXPORT_SYMBOL(rk29sdk_wifi_set_carddetect);
-
-static struct wifi_mem_prealloc wifi_mem_array[PREALLOC_WLAN_SEC_NUM] = {
- {NULL, (WLAN_SECTION_SIZE_0 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_1 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_2 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_3 + PREALLOC_WLAN_SECTION_HEADER)}
-};
-
-static void *rk29sdk_mem_prealloc(int section, unsigned long size)
-{
- if (section == PREALLOC_WLAN_SEC_NUM)
- return wlan_static_skb;
-
- if ((section < 0) || (section > PREALLOC_WLAN_SEC_NUM))
- return NULL;
-
- if (wifi_mem_array[section].size < size)
- return NULL;
-
- return wifi_mem_array[section].mem_ptr;
-}
-
-int __init rk29sdk_init_wifi_mem(void)
-{
- int i;
- int j;
-
- for (i = 0 ; i < WLAN_SKB_BUF_NUM ; i++) {
- wlan_static_skb[i] = dev_alloc_skb(
- ((i < (WLAN_SKB_BUF_NUM / 2)) ? 4096 : 8192));
-
- if (!wlan_static_skb[i])
- goto err_skb_alloc;
- }
-
- for (i = 0 ; i < PREALLOC_WLAN_SEC_NUM ; i++) {
- wifi_mem_array[i].mem_ptr =
- kmalloc(wifi_mem_array[i].size, GFP_KERNEL);
-
- if (!wifi_mem_array[i].mem_ptr)
- goto err_mem_alloc;
- }
- return 0;
-
- err_mem_alloc:
- pr_err("Failed to mem_alloc for WLAN\n");
- for (j = 0 ; j < i ; j++)
- kfree(wifi_mem_array[j].mem_ptr);
-
- i = WLAN_SKB_BUF_NUM;
-
- err_skb_alloc:
- pr_err("Failed to skb_alloc for WLAN\n");
- for (j = 0 ; j < i ; j++)
- dev_kfree_skb(wlan_static_skb[j]);
-
- return -ENOMEM;
-}
-
-static struct wifi_platform_data rk29sdk_wifi_control = {
- .set_power = rk29sdk_wifi_power,
- .set_reset = rk29sdk_wifi_reset,
- .set_carddetect = rk29sdk_wifi_set_carddetect,
- .mem_prealloc = rk29sdk_mem_prealloc,
-};
-static struct platform_device rk29sdk_wifi_device = {
- .name = "bcm4329_wlan",
- .id = 1,
- .dev = {
- .platform_data = &rk29sdk_wifi_control,
- },
-};
-#endif
-
-
-/* bluetooth rfkill device */
-static struct platform_device rk29sdk_rfkill = {
- .name = "rk29sdk_rfkill",
- .id = -1,
-};
-
-
-//#ifdef CONFIG_VIVANTE
-#define GPU_HIGH_CLOCK 552
-#define GPU_LOW_CLOCK (periph_pll_default / 1000000) /* same as */
-static struct resource resources_gpu[] = {
- [0] = {
- .name = "gpu_irq",
- .start = IRQ_GPU,
- .end = IRQ_GPU,
- .flags = IORESOURCE_IRQ,
- },
- [1] = {
- .name = "gpu_base",
- .start = RK29_GPU_PHYS,
- .end = RK29_GPU_PHYS + RK29_GPU_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "gpu_mem",
- .start = PMEM_GPU_BASE,
- .end = PMEM_GPU_BASE + PMEM_GPU_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [3] = {
- .name = "gpu_clk",
- .start = GPU_LOW_CLOCK,
- .end = GPU_HIGH_CLOCK,
- .flags = IORESOURCE_IO,
- },
-
-};
-static struct platform_device rk29_device_gpu = {
- .name = "galcore",
- .id = 0,
- .num_resources = ARRAY_SIZE(resources_gpu),
- .resource = resources_gpu,
-};
-//#endif
-#ifdef CONFIG_KEYS_RK29
-extern struct rk29_keys_platform_data rk29_keys_pdata;
-static struct platform_device rk29_device_keys = {
- .name = "rk29-keypad",
- .id = -1,
- .dev = {
- .platform_data = &rk29_keys_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_USE_GPIO_GENERATE_WAVE
-static struct gpio_wave_platform_data gpio_wave_pdata = {
- .gpio = RK29_PIN0_PA0,
- .Htime = 2000,
- .Ltime = 300,
- .Dvalue = GPIO_HIGH,
-};
-static struct platform_device gpio_wave_device = {
- .name = "gpio_wave",
- .id = -1,
- .dev = {
- .platform_data = &gpio_wave_pdata,
- },
-};
-#endif
-#if CONFIG_ANDROID_TIMED_GPIO
-static struct timed_gpio timed_gpios[] = {
- {
- .name = "vibrator",
- .gpio = RK29_PIN1_PB5,
- .max_timeout = 1000,
- .active_low = 0,
- .adjust_time =20, //adjust for diff product
- },
-};
-
-struct timed_gpio_platform_data rk29_vibrator_info = {
- .num_gpios = 1,
- .gpios = timed_gpios,
-};
-
-struct platform_device rk29_device_vibrator ={
- .name = "timed-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_vibrator_info,
- },
-
-};
-#endif
-#ifdef CONFIG_BUTTON_LIGHT
-static int rk29_buttonlight_io_init(void)
-{
- int ret = 0;
-
- return ret;
-}
-
-static int rk29_buttonlight_io_deinit(void)
-{
- int ret = 0;
- return ret;
-}
-struct rk29_button_light_info rk29_button_light_info = {
- .led_on_pin = RK29_PIN0_PA0,
- .led_on_level = 1,
- .io_init = rk29_buttonlight_io_init,
- .io_deinit = rk29_buttonlight_io_deinit,
-
-};
-#endif
-static void __init rk29_board_iomux_init(void)
-{
- int err;
- #ifdef CONFIG_UART1_RK29
- //disable uart1 pull down
- rk29_mux_api_set(GPIO2A5_UART1SOUT_NAME, GPIO2L_GPIO2A5);
- rk29_mux_api_set(GPIO2A4_UART1SIN_NAME, GPIO2L_GPIO2A4);
-
- gpio_request(RK29_PIN2_PA5, NULL);
- gpio_request(RK29_PIN2_PA4, NULL);
-
- gpio_pull_updown(RK29_PIN2_PA5, PullDisable);
- gpio_pull_updown(RK29_PIN2_PA4, PullDisable);
-
- rk29_mux_api_set(GPIO2A5_UART1SOUT_NAME, GPIO2L_UART1_SOUT);
- rk29_mux_api_set(GPIO2A4_UART1SIN_NAME, GPIO2L_UART1_SIN);
-
- gpio_free(RK29_PIN2_PA5);
- gpio_free(RK29_PIN2_PA4);
- #endif
- #if CONFIG_ANDROID_TIMED_GPIO
- rk29_mux_api_set(GPIO1B5_PWM0_NAME, GPIO1L_GPIO1B5);//for timed gpio
- #endif
- #ifdef CONFIG_RK29_PWM_REGULATOR
- rk29_mux_api_set(REGULATOR_PWM_MUX_NAME,REGULATOR_PWM_MUX_MODE);
- #endif
- rk29_mux_api_set(GPIO4C0_RMIICLKOUT_RMIICLKIN_NAME,GPIO4H_GPIO4C0);
-
-/****************************clock change********************************************/
- err = gpio_request(RK29_PIN4_PC0, "clk27M_control");
- if (err) {
- gpio_free(RK29_PIN4_PC0);
- printk("-------request RK29_PIN4_PC0 fail--------\n");
- return -1;
- }
- //phy power down
- gpio_direction_output(RK29_PIN4_PC0, GPIO_LOW);// 27M 32K
- gpio_set_value(RK29_PIN4_PC0, GPIO_LOW);
-
- rk29_mux_api_set(GPIO4C5_RMIICSRDVALID_MIIRXDVALID_NAME,GPIO4H_GPIO4C5);
-
- err = gpio_request(RK29_PIN4_PC5, "clk24M_control");
- if (err) {
- gpio_free(RK29_PIN4_PC5);
- printk("-------request RK29_PIN4_PC5 fail--------\n");
- return -1;
- }
- //phy power down
- gpio_direction_output(RK29_PIN4_PC5, GPIO_LOW);// control 24M
- gpio_set_value(RK29_PIN4_PC5, GPIO_LOW);
-/*******************************************************************/
-
-
-}
-
-// For phone,just a disk only, add by phc,20110816
-#ifdef CONFIG_USB_ANDROID
-struct usb_mass_storage_platform_data phone_mass_storage_pdata = {
- .nluns = 1,
- .vendor = "RockChip",
- .product = "rk29 sdk",
- .release = 0x0100,
-};
-
-//static
-struct platform_device phone_usb_mass_storage_device = {
- .name = "usb_mass_storage",
- .id = -1,
- .dev = {
- .platform_data = &phone_mass_storage_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_RK29_CHARGE_EARLYSUSPEND
-
-struct platform_device charge_lowerpower_device = {
- .name = "charge_lowerpower",
- .id = -1,
-};
-#endif
-
-static struct platform_device *devices[] __initdata = {
-
-#ifdef CONFIG_RK29_WATCHDOG
- &rk29_device_wdt,
-#endif
-
-#ifdef CONFIG_UART1_RK29
- &rk29_device_uart1,
-#endif
-#ifdef CONFIG_UART0_RK29
- &rk29_device_uart0,
-#endif
-#ifdef CONFIG_UART2_RK29
- &rk29_device_uart2,
-#endif
-#ifdef CONFIG_UART3_RK29
- &rk29_device_uart3,
-#endif
-
-#ifdef CONFIG_RK29_PWM_REGULATOR
- &rk29_device_pwm_regulator,
-#endif
-#ifdef CONFIG_SPIM0_RK29
- &rk29xx_device_spi0m,
-#endif
-#ifdef CONFIG_SPIM1_RK29
- &rk29xx_device_spi1m,
-#endif
-#ifdef CONFIG_ADC_RK29
- &rk29_device_adc,
-#endif
-#ifdef CONFIG_I2C0_RK29
- &rk29_device_i2c0,
-#endif
-#ifdef CONFIG_I2C1_RK29
- &rk29_device_i2c1,
-#endif
-#ifdef CONFIG_I2C2_RK29
- &rk29_device_i2c2,
-#endif
-#ifdef CONFIG_I2C3_RK29
- &rk29_device_i2c3,
-#endif
-
-#ifdef CONFIG_SND_RK29_SOC_I2S_2CH
- &rk29_device_iis_2ch,
-#endif
-#ifdef CONFIG_SND_RK29_SOC_I2S_8CH
- &rk29_device_iis_8ch,
-#endif
-
-#ifdef CONFIG_MFD_WM8994
- &wm8994_fixed_voltage0,
- &wm8994_fixed_voltage1,
-#endif
-
-#ifdef CONFIG_KEYS_RK29
- &rk29_device_keys,
-#endif
-#ifdef CONFIG_USE_GPIO_GENERATE_WAVE
- &gpio_wave_device,
-#endif
-#ifdef CONFIG_SDMMC0_RK29
- &rk29_device_sdmmc0,
-#endif
-#ifdef CONFIG_SDMMC1_RK29
- &rk29_device_sdmmc1,
-#endif
-
-#ifdef CONFIG_MTD_NAND_RK29XX
- &rk29xx_device_nand,
-#endif
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- &rk29sdk_wifi_device,
-#endif
-
-#ifdef CONFIG_BT
- &rk29sdk_rfkill,
-#endif
-
-#if defined(CONFIG_TDSC8800)
- &rk29_device_tdsc8800,
-#endif
-
-#ifdef CONFIG_MTD_NAND_RK29
- &rk29_device_nand,
-#endif
-
-#ifdef CONFIG_FB_RK29
- &rk29_device_fb,
- &rk29_device_dma_cpy,
-#endif
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- &rk29_device_backlight,
-#endif
-#ifdef CONFIG_BUTTON_LIGHT
- &rk29_device_buttonlight,
-#endif
-#ifdef CONFIG_RK29_VMAC
- &rk29_device_vmac,
-#endif
-//#ifdef CONFIG_VIVANTE
- &rk29_device_gpu,
-//#endif
-#ifdef CONFIG_VIDEO_RK29
- &rk29_device_camera, /* ddl@rock-chips.com : camera support */
- #if (CONFIG_SENSOR_IIC_ADDR_0 != 0x00)
- &rk29_soc_camera_pdrv_0,
- #endif
- &rk29_soc_camera_pdrv_1,
- &android_pmem_cam_device,
-#endif
-#ifdef CONFIG_ION
- &rk29_ion_device,
-#endif
- &android_pmem_device,
- &rk29_vpu_mem_device,
-#ifdef CONFIG_USB20_OTG
- &rk29_device_usb20_otg,
-#endif
-#ifdef CONFIG_USB20_HOST
- &rk29_device_usb20_host,
-#endif
-#ifdef CONFIG_USB11_HOST
- &rk29_device_usb11_host,
-#endif
-#ifdef CONFIG_USB_ANDROID
- &android_usb_device,
- &phone_usb_mass_storage_device,
-#endif
-#ifdef CONFIG_RK29_IPP
- &rk29_device_ipp,
-#endif
-#ifdef CONFIG_VIDEO_RK29XX_VOUT
- &rk29_v4l2_output_devce,
-#endif
-#ifdef CONFIG_RK_HEADSET_DET
- &rk_device_headset,
-#endif
-#ifdef CONFIG_RK29_GPS
- &rk29_device_gps,
-#endif
-#ifdef CONFIG_RK29_CHARGE_EARLYSUSPEND
- &charge_lowerpower_device,
-#endif
-#ifdef CONFIG_ANDROID_TIMED_GPIO
- &rk29_device_vibrator,
-#endif
-};
-
-#ifdef CONFIG_RK29_VMAC
-/*****************************************************************************************
- * vmac devices
- * author: lyx@rock-chips.com
- *****************************************************************************************/
-static int rk29_vmac_register_set(void)
-{
- //config rk29 vmac as rmii, 100MHz
- u32 value= readl(RK29_GRF_BASE + 0xbc);
- value = (value & 0xfff7ff) | (0x400);
- writel(value, RK29_GRF_BASE + 0xbc);
- return 0;
-}
-
-static int rk29_rmii_io_init(void)
-{
- int err;
-
- //phy power gpio
- err = gpio_request(RK29_PIN6_PB0, "phy_power_en");
- if (err) {
- gpio_free(RK29_PIN6_PB0);
- printk("-------request RK29_PIN6_PB0 fail--------\n");
- return -1;
- }
- //phy power down
- gpio_direction_output(RK29_PIN6_PB0, GPIO_LOW);
- gpio_set_value(RK29_PIN6_PB0, GPIO_LOW);
-
- return 0;
-}
-
-static int rk29_rmii_io_deinit(void)
-{
- //phy power down
- gpio_direction_output(RK29_PIN6_PB0, GPIO_LOW);
- gpio_set_value(RK29_PIN6_PB0, GPIO_LOW);
- //free
- gpio_free(RK29_PIN6_PB0);
- return 0;
-}
-
-static int rk29_rmii_power_control(int enable)
-{
- if (enable) {
- //enable phy power
- gpio_direction_output(RK29_PIN6_PB0, GPIO_HIGH);
- gpio_set_value(RK29_PIN6_PB0, GPIO_HIGH);
- }
- else {
- gpio_direction_output(RK29_PIN6_PB0, GPIO_LOW);
- gpio_set_value(RK29_PIN6_PB0, GPIO_LOW);
- }
- return 0;
-}
-
-struct rk29_vmac_platform_data rk29_vmac_pdata = {
- .vmac_register_set = rk29_vmac_register_set,
- .rmii_io_init = rk29_rmii_io_init,
- .rmii_io_deinit = rk29_rmii_io_deinit,
- .rmii_power_control = rk29_rmii_power_control,
-};
-#endif
-
-/*****************************************************************************************
- * spi devices
- * author: cmc@rock-chips.com
- *****************************************************************************************/
-#define SPI_CHIPSELECT_NUM 2
-static struct spi_cs_gpio rk29xx_spi0_cs_gpios[SPI_CHIPSELECT_NUM] = {
- {
- .name = "spi0 cs0",
- .cs_gpio = RK29_PIN2_PC1,
- .cs_iomux_name = GPIO2C1_SPI0CSN0_NAME,
- .cs_iomux_mode = GPIO2H_SPI0_CSN0,
- },
- {
- .name = "spi0 cs1",
- .cs_gpio = RK29_PIN1_PA4,
- .cs_iomux_name = GPIO1A4_EMMCWRITEPRT_SPI0CS1_NAME,//if no iomux,set it NULL
- .cs_iomux_mode = GPIO1L_SPI0_CSN1,
- }
-};
-
-static struct spi_cs_gpio rk29xx_spi1_cs_gpios[SPI_CHIPSELECT_NUM] = {
- {
- .name = "spi1 cs0",
- .cs_gpio = RK29_PIN2_PC5,
- .cs_iomux_name = GPIO2C5_SPI1CSN0_NAME,
- .cs_iomux_mode = GPIO2H_SPI1_CSN0,
- },
- {
- .name = "spi1 cs1",
- .cs_gpio = RK29_PIN1_PA3,
- .cs_iomux_name = GPIO1A3_EMMCDETECTN_SPI1CS1_NAME,//if no iomux,set it NULL
- .cs_iomux_mode = GPIO1L_SPI1_CSN1,
- }
-};
-
-static int spi_io_init(struct spi_cs_gpio *cs_gpios, int cs_num)
-{
-#if 1
- int i;
- if (cs_gpios) {
- for (i=0; i<cs_num; i++) {
- rk29_mux_api_set(cs_gpios[i].cs_iomux_name, cs_gpios[i].cs_iomux_mode);
- }
- }
-#endif
- return 0;
-}
-
-static int spi_io_deinit(struct spi_cs_gpio *cs_gpios, int cs_num)
-{
- return 0;
-}
-
-static int spi_io_fix_leakage_bug(void)
-{
-#if 0
- gpio_direction_output(RK29_PIN2_PC1, GPIO_LOW);
-#endif
- return 0;
-}
-
-static int spi_io_resume_leakage_bug(void)
-{
-#if 0
- gpio_direction_output(RK29_PIN2_PC1, GPIO_HIGH);
-#endif
- return 0;
-}
-
-struct rk29xx_spi_platform_data rk29xx_spi0_platdata = {
- .num_chipselect = SPI_CHIPSELECT_NUM,
- .chipselect_gpios = rk29xx_spi0_cs_gpios,
- .io_init = spi_io_init,
- .io_deinit = spi_io_deinit,
- .io_fix_leakage_bug = spi_io_fix_leakage_bug,
- .io_resume_leakage_bug = spi_io_resume_leakage_bug,
-};
-
-struct rk29xx_spi_platform_data rk29xx_spi1_platdata = {
- .num_chipselect = SPI_CHIPSELECT_NUM,
- .chipselect_gpios = rk29xx_spi1_cs_gpios,
- .io_init = spi_io_init,
- .io_deinit = spi_io_deinit,
- .io_fix_leakage_bug = spi_io_fix_leakage_bug,
- .io_resume_leakage_bug = spi_io_resume_leakage_bug,
-};
-
-/*****************************************************************************************
- * xpt2046 touch panel
- * author: hhb@rock-chips.com
- *****************************************************************************************/
-#if defined(CONFIG_TOUCHSCREEN_XPT2046_NORMAL_SPI) || defined(CONFIG_TOUCHSCREEN_XPT2046_TSLIB_SPI)
-#define XPT2046_GPIO_INT RK29_PIN4_PD5 //中断???#define DEBOUNCE_REPTIME 3
-
-static struct xpt2046_platform_data xpt2046_info = {
- .model = 2046,
- .keep_vref_on = 1,
- .swap_xy = 0,
- .debounce_max = 7,
- .debounce_rep = DEBOUNCE_REPTIME,
- .debounce_tol = 20,
- .gpio_pendown = XPT2046_GPIO_INT,
- .pendown_iomux_name = GPIO4D5_CPUTRACECTL_NAME,
- .pendown_iomux_mode = GPIO4H_GPIO4D5,
- .touch_virtualkey_length = 60,
- .penirq_recheck_delay_usecs = 1,
-#if defined(CONFIG_TOUCHSCREEN_480X800)
- .x_min = 0,
- .x_max = 480,
- .y_min = 0,
- .y_max = 800,
- .touch_ad_top = 3940,
- .touch_ad_bottom = 310,
- .touch_ad_left = 3772,
- .touch_ad_right = 340,
-#elif defined(CONFIG_TOUCHSCREEN_800X480)
- .x_min = 0,
- .x_max = 800,
- .y_min = 0,
- .y_max = 480,
- .touch_ad_top = 2447,
- .touch_ad_bottom = 207,
- .touch_ad_left = 5938,
- .touch_ad_right = 153,
-#elif defined(CONFIG_TOUCHSCREEN_320X480)
- .x_min = 0,
- .x_max = 320,
- .y_min = 0,
- .y_max = 480,
- .touch_ad_top = 3166,
- .touch_ad_bottom = 256,
- .touch_ad_left = 3658,
- .touch_ad_right = 380,
-#endif
-};
-#elif defined(CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI)
-static struct xpt2046_platform_data xpt2046_info = {
- .model = 2046,
- .keep_vref_on = 1,
- .swap_xy = 0,
- .debounce_max = 7,
- .debounce_rep = DEBOUNCE_REPTIME,
- .debounce_tol = 20,
- .gpio_pendown = XPT2046_GPIO_INT,
- .pendown_iomux_name = GPIO4D5_CPUTRACECTL_NAME,
- .pendown_iomux_mode = GPIO4H_GPIO4D5,
- .touch_virtualkey_length = 60,
- .penirq_recheck_delay_usecs = 1,
-
-#if defined(CONFIG_TOUCHSCREEN_480X800)
- .x_min = 0,
- .x_max = 480,
- .y_min = 0,
- .y_max = 800,
- .screen_x = { 70, 410, 70, 410, 240},
- .screen_y = { 50, 50, 740, 740, 400},
- .uncali_x_default = { 3267, 831, 3139, 715, 1845 },
- .uncali_y_default = { 3638, 3664, 564, 591, 2087 },
-#elif defined(CONFIG_TOUCHSCREEN_800X480)
- .x_min = 0,
- .x_max = 800,
- .y_min = 0,
- .y_max = 480,
- .screen_x[5] = { 50, 750, 50, 750, 400};
- .screen_y[5] = { 40, 40, 440, 440, 240};
- .uncali_x_default[5] = { 438, 565, 3507, 3631, 2105 };
- .uncali_y_default[5] = { 3756, 489, 3792, 534, 2159 };
-#elif defined(CONFIG_TOUCHSCREEN_320X480)
- .x_min = 0,
- .x_max = 320,
- .y_min = 0,
- .y_max = 480,
- .screen_x[5] = { 50, 270, 50, 270, 160};
- .screen_y[5] = { 40, 40, 440, 440, 240};
- .uncali_x_default[5] = { 812, 3341, 851, 3371, 2183 };
- .uncali_y_default[5] = { 442, 435, 3193, 3195, 2004 };
-#endif
-};
-#endif
-
-#if defined(CONFIG_RK29_SC8800)
-static int sc8800_io_init(void)
-{
- rk29_mux_api_set(GPIO1C1_UART0RTSN_SDMMC1WRITEPRT_NAME, GPIO1H_GPIO1C1);
- rk29_mux_api_set(GPIO1C0_UART0CTSN_SDMMC1DETECTN_NAME, GPIO1H_GPIO1C0);
- return 0;
-}
-
-static int sc8800_io_deinit(void)
-{
-
- return 0;
-}
-
-static struct plat_sc8800 sc8800_plat_data = {
- .slav_rts_pin = RK29_PIN1_PC1,
- .slav_rdy_pin = RK29_PIN0_PA3,
- .master_rts_pin = RK29_PIN1_PC0,
- .master_rdy_pin = RK29_PIN0_PA2,
- //.poll_time = 100,
- .io_init = sc8800_io_init,
- .io_deinit = sc8800_io_deinit,
-};
-#endif
-/*
-static struct rk29xx_spi_chip cmb_spi_chip = {
- .transfer_mode = rk29xx_SPI_FULL_DUPLEX,
-};
-*/
-/*****************************************************************************************
- * CMMB IO CONFIG
- * author: lby@rock-chips.com
- *****************************************************************************************/
-#if defined(CONFIG_SMS_SPI_ROCKCHIP)
-#define CMMB_1186_SPIIRQ RK29_PIN6_PD1
-void cmmb_io_init_mux(void)
-{
-// rk29_mux_api_set(GPIO1A4_EMMCWRITEPRT_SPI0CS1_NAME, GPIO1L_GPIO1A4);
-
-}
-void cmmb_io_set_for_pm(void)
-{
- printk("entering cmmb_io_set_for_pm\n");
- gpio_request(RK29_PIN6_PD2, NULL);//cmmb reset pin
- gpio_direction_output(RK29_PIN6_PD2,0);
- rk29_mux_api_set(GPIO1A3_EMMCDETECTN_SPI1CS1_NAME,GPIO1L_GPIO1A3);
- gpio_request(RK29_PIN1_PA3, NULL);//cmmb cs pin
- gpio_direction_input(RK29_PIN1_PA3);
- gpio_pull_updown(RK29_PIN1_PA3, 0);
-}
-
-void cmmb_power_on_by_wm831x(void)
-{
- struct regulator *ldo;
-
- printk("entering cmmb_power_on_by_wm831x\n");
-
- rk29_mux_api_set(GPIO1A3_EMMCDETECTN_SPI1CS1_NAME,GPIO1L_SPI0_CSN1);
- gpio_request(RK29_PIN6_PD2, NULL);
- gpio_direction_output(RK29_PIN6_PD2,0);
- mdelay(200);
-
- ldo = regulator_get(NULL, "ldo8"); //cmmb
- regulator_set_voltage(ldo,1200000,1200000);
- regulator_set_suspend_voltage(ldo,1200000);
- regulator_enable(ldo);
- printk("%s set ldo8=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo9"); //cmmb
- regulator_set_voltage(ldo,3000000,3000000);
- regulator_set_suspend_voltage(ldo,3000000);
- regulator_enable(ldo);
- printk("%s set ldo9=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
-
- mdelay(200);
- gpio_direction_output(RK29_PIN6_PD2,1);
-}
-
-void cmmb_power_down_by_wm831x(void)
-{
- struct regulator* ldo;
-
- printk("entering cmmb_power_down_by_wm831x\n");
-
- ldo = regulator_get(NULL, "ldo8");
- regulator_set_voltage(ldo,0,0);
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo9");
- regulator_set_voltage(ldo,0,0);
- regulator_disable(ldo);
- regulator_put(ldo);
-}
-
-static struct cmmb_io_def_s cmmb_io = {
- .cmmb_pw_en = INVALID_GPIO,
- .cmmb_pw_dwn = INVALID_GPIO,
- .cmmb_pw_rst = RK29_PIN6_PD2,
- .cmmb_irq = CMMB_1186_SPIIRQ,
- .io_init_mux = cmmb_io_init_mux,
- .cmmb_io_pm = cmmb_io_set_for_pm,
- .cmmb_power_on = cmmb_power_on_by_wm831x,
- .cmmb_power_down = cmmb_power_down_by_wm831x
-};
-#endif
-static struct spi_board_info board_spi_devices[] = {
-#if defined(CONFIG_TOUCHSCREEN_XPT2046_SPI)
- {
- .modalias = "xpt2046_ts",
- .chip_select = 0,// 2,
- .max_speed_hz = 125 * 1000 * 26,/* (max sample rate @ 3V) * (cmd + data + overhead) */
- .bus_num = 0,
- .irq = XPT2046_GPIO_INT,
- .platform_data = &xpt2046_info,
- },
-#endif
-
-#if defined(CONFIG_MFD_WM831X_SPI)
- {
- .modalias = "wm8310",
- .chip_select = 1,
- .max_speed_hz = 1*1000*1000,
- .bus_num = 1,
- .irq = RK29_PIN4_PD0,
- .platform_data = &wm831x_platdata,
- },
-#endif
-#if defined(CONFIG_RK29_SC8800)
- {
- .modalias = "sc8800",
- .bus_num = 0,
- .platform_data = &sc8800_plat_data,
- .max_speed_hz = 12*1000*1000,
- .chip_select = 0,
- },
-#endif
-
-#if defined(CONFIG_SMS_SPI_ROCKCHIP)
- {
- .modalias = "siano1186",
- .chip_select = 1,
- .max_speed_hz = 12*1000*1000,
- .bus_num = 1,
- .irq =CMMB_1186_SPIIRQ,
- //.controller_data = &cmb_spi_chip,
- .platform_data = &cmmb_io,
- },
-#endif
-};
-
-
-/**********************************************************************************************
- *
- * The virtual keys for android "back", "home", "menu", "search", these four keys are touch key
- * on the touch screen panel. (added by hhb@rock-chips.com 2011.03.31)
- *
- ***********************************************************************************************/
-static ssize_t rk29xx_virtual_keys_show(struct kobject *kobj,
- struct kobj_attribute *attr, char *buf)
-{
-#if (defined(CONFIG_TOUCHSCREEN_XPT2046_SPI) && defined(CONFIG_TOUCHSCREEN_480X800)) \
- || defined(CONFIG_TOUCHSCREEN_HX8520_IIC) || defined(CONFIG_TOUCHSCREEN_GT801_IIC)\
- || defined(CONFIG_TOUCHSCREEN_PIXCIR)
- /* center: x: home: 50, menu: 184, back: 315, search 435, y: 830*/
- /* centerx;centery;width;height; */
- return sprintf(buf,
- __stringify(EV_KEY) ":" __stringify(KEY_BACK) ":305:845:50:60"//":305:845:50:60" //":50:830:98:50" //":210:796:98:50"
- ":" __stringify(EV_KEY) ":" __stringify(KEY_MENU) ":165:845:50:60"//":165:845:50:60" // ":184:830:120:50" // ":435:796:120:50"
- ":" __stringify(EV_KEY) ":" __stringify(KEY_HOMEPAGE) ":25:845:120:60"//":25:845:50:60" //":315:830:100:50" //":320:796:100:50"
- ":" __stringify(EV_KEY) ":" __stringify(KEY_SEARCH) ":445:845:50:60"//":445:845:50:60" //":50:815:98:50" // //":85:796:88:50"
- "\n");
-#endif
-#if defined(CONFIG_TOUCHSCREEN_FT5X0X) || defined(CONFIG_TOUCHSCREEN_ILI2102_IIC)
- return sprintf(buf,
- __stringify(EV_KEY) ":" __stringify(KEY_BACK) ":305:875:60:60"//":305:845:50:60" //":50:830:98:50" //":210:796:98:50"
- ":" __stringify(EV_KEY) ":" __stringify(KEY_MENU) ":165:875:60:60"//":165:845:50:60" // ":184:830:120:50" // ":435:796:120:50"
- ":" __stringify(EV_KEY) ":" __stringify(KEY_HOMEPAGE) ":30:875:60:60"//":25:845:50:60" //":315:830:100:50" //":320:796:100:50"
- ":" __stringify(EV_KEY) ":" __stringify(KEY_SEARCH) ":445:875:60:60"//":445:845:50:60" //":50:815:98:50" // //":85:796:88:50"
- "\n");
-#endif
- return 0;
-}
-
-static struct kobj_attribute rk29xx_virtual_keys_attr = {
- .attr = {
-#if defined(CONFIG_TOUCHSCREEN_XPT2046_SPI)
- .name = "virtualkeys.xpt2046-touchscreen",
-#elif defined(CONFIG_TOUCHSCREEN_HX8520_IIC)
- .name = "virtualkeys.hx8520-touchscreen",
-#elif defined(CONFIG_TOUCHSCREEN_GT801_IIC)
- .name = "virtualkeys.gt801-touchscreen",
-#elif defined(CONFIG_TOUCHSCREEN_ILI2102_IIC)
- .name = "virtualkeys.ili2102-touchscreen",
-#elif defined(CONFIG_TOUCHSCREEN_FT5X0X)
- .name = "virtualkeys.ft5x0x_ts-touchscreen",
-#elif defined(CONFIG_TOUCHSCREEN_PIXCIR)
- .name = "virtualkeys.pixcir_ts-touchscreen",
-#else
- .name = "virtualkeys",
-#endif
- .mode = S_IRUGO,
- },
- .show = &rk29xx_virtual_keys_show,
-};
-
-static struct attribute *rk29xx_properties_attrs[] = {
- &rk29xx_virtual_keys_attr.attr,
- NULL
-};
-
-static struct attribute_group rk29xx_properties_attr_group = {
- .attrs = rk29xx_properties_attrs,
-};
-static int rk29xx_virtual_keys_init(void)
-{
- int ret;
- struct kobject *properties_kobj;
- printk("rk29xx_virtual_keys_init \n");
- properties_kobj = kobject_create_and_add("board_properties", NULL);
- if (properties_kobj)
- ret = sysfs_create_group(properties_kobj,
- &rk29xx_properties_attr_group);
- if (!properties_kobj || ret)
- {
- pr_err("failed to create board_properties\n");
- }
- return ret;
-}
-
-
-static void __init rk29_gic_init_irq(void)
-{
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38))
- gic_init(0, 32, (void __iomem *)RK29_GICPERI_BASE, (void __iomem *)RK29_GICCPU_BASE);
-#else
- gic_dist_init(0, (void __iomem *)RK29_GICPERI_BASE, 32);
- gic_cpu_init(0, (void __iomem *)RK29_GICCPU_BASE);
-#endif
-}
-
-static void __init machine_rk29_init_irq(void)
-{
- rk29_gic_init_irq();
- rk29_gpio_init();
-}
-
-
-
-static void rk29_pm_power_restart(void)
-{
- printk("%s,line=%d\n",__FUNCTION__,__LINE__);
- mdelay(2);
-#if defined(CONFIG_MFD_WM831X)
- wm831x_device_restart(gWm831x);
-#endif
-
-}
-
-static void rk29_pm_power_off(void)
-{
- printk(KERN_ERR "rk29_pm_power_off start...\n");
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
- gpio_direction_output(BP_VOL_PIN,GPIO_LOW);
-#if defined(CONFIG_MFD_WM831X)
- if(wm831x_read_usb(gWm831x))
- rk29_pm_power_restart(); //if charging then restart
- else
- wm831x_device_shutdown(gWm831x);//else shutdown
-#endif
- while (1);
-}
-
-static struct cpufreq_frequency_table freq_table[] =
-{
- { .index = 1100000, .frequency = 408000 },
- { .index = 1150000, .frequency = 600000 },
- { .index = 1200000, .frequency = 816000 },
-// { .index = 1300000, .frequency = 1008000 },
- { .frequency = CPUFREQ_TABLE_END },
-};
-
-static void __init machine_rk29_board_init(void)
-{
- rk29_board_iomux_init();
-
- gpio_request(POWER_ON_PIN,"poweronpin");
- gpio_set_value(POWER_ON_PIN, GPIO_HIGH);
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
- gpio_request(RK29_PIN0_PA0,NULL);
- gpio_direction_output(RK29_PIN0_PA0, 0);
-
- pm_power_off = rk29_pm_power_off;
- //arm_pm_restart = rk29_pm_power_restart;
-
- board_update_cpufreq_table(freq_table);
-
- platform_add_devices(devices, ARRAY_SIZE(devices));
-#ifdef CONFIG_I2C0_RK29
- i2c_register_board_info(default_i2c0_data.bus_num, board_i2c0_devices,
- ARRAY_SIZE(board_i2c0_devices));
-#endif
-#ifdef CONFIG_I2C1_RK29
- i2c_register_board_info(default_i2c1_data.bus_num, board_i2c1_devices,
- ARRAY_SIZE(board_i2c1_devices));
-#endif
-#ifdef CONFIG_I2C2_RK29
- i2c_register_board_info(default_i2c2_data.bus_num, board_i2c2_devices,
- ARRAY_SIZE(board_i2c2_devices));
-#endif
-#ifdef CONFIG_I2C3_RK29
- i2c_register_board_info(default_i2c3_data.bus_num, board_i2c3_devices,
- ARRAY_SIZE(board_i2c3_devices));
-#endif
-
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- rk29sdk_wifi_bt_gpio_control_init();
- rk29sdk_init_wifi_mem();
-#endif
-
- #if (defined(CONFIG_TOUCHSCREEN_XPT2046_SPI) && defined(CONFIG_TOUCHSCREEN_480X800)) \
- || defined(CONFIG_TOUCHSCREEN_HX8520_IIC) || defined(CONFIG_TOUCHSCREEN_GT801_IIC)\
- || defined(CONFIG_TOUCHSCREEN_PIXCIR) || defined(CONFIG_TOUCHSCREEN_FT5X0X)\
- || defined(CONFIG_TOUCHSCREEN_ILI2102_IIC)
- rk29xx_virtual_keys_init();
- #endif
-
-}
-
-static void __init machine_rk29_fixup(struct machine_desc *desc, struct tag *tags,
- char **cmdline, struct meminfo *mi)
-{
- mi->nr_banks = 1;
- mi->bank[0].start = RK29_SDRAM_PHYS;
- //mi->bank[0].node = PHYS_TO_NID(RK29_SDRAM_PHYS);
- mi->bank[0].size = LINUX_SIZE;
-#if SDRAM_SIZE > SZ_512M
- mi->nr_banks = 2;
- mi->bank[1].start = RK29_SDRAM_PHYS + SZ_512M;
- mi->bank[1].size = SDRAM_SIZE - SZ_512M;
-#endif
-}
-
-static void __init machine_rk29_mapio(void)
-{
- rk29_map_common_io();
- rk29_setup_early_printk();
- rk29_sram_init();
- rk29_clock_init2(periph_pll_96mhz, codec_pll_300mhz, false);
- rk29_iomux_init();
- ddr_init(DDR_TYPE, DDR_FREQ);
-}
-
-MACHINE_START(RK29, "RK29board")
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 37))
- /* UART for LL DEBUG */
- .phys_io = RK29_UART1_PHYS & 0xfff00000,
- .io_pg_offst = ((RK29_UART1_BASE) >> 18) & 0xfffc,
-#endif
- .boot_params = RK29_SDRAM_PHYS + 0x88000,
- .fixup = machine_rk29_fixup,
- .map_io = machine_rk29_mapio,
- .init_irq = machine_rk29_init_irq,
- .init_machine = machine_rk29_board_init,
- .timer = &rk29_timer,
-MACHINE_END
+++ /dev/null
-#include <mach/key.h>
-#include <mach/gpio.h>
-
-#define EV_ENCALL KEY_F4
-#define EV_MENU KEY_F1
-
-#define PRESS_LEV_LOW 1
-#define PRESS_LEV_HIGH 0
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "menu",
- .code = EV_MENU,
- .gpio = RK29_PIN6_PA0,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .gpio = RK29_PIN6_PA1,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .gpio = RK29_PIN6_PA2,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .gpio = RK29_PIN6_PA3,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "search",
- .code = KEY_SEARCH,
- .gpio = RK29_PIN6_PA4,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .gpio = RK29_PIN6_PA5,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "sensor",
- .code = KEY_CAMERA,
- .gpio = RK29_PIN6_PA6,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK29_PIN6_PA7,
- .active_low = PRESS_LEV_LOW,
- .wakeup = 1,
- },
-#if 0
- {
- .desc = "vol+",
- .code = KEY_VOLUMEDOWN,
- .adc_value = 95,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEUP,
- .adc_value = 249,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "menu",
- .code = EV_MENU,
- .adc_value = 406,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .code_long_press = KEY_F4,
- .adc_value = 561,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_ESC,
- .adc_value = 726,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "adkey6",
- .code = KEY_BACK,
- .code_long_press = EV_ENCALL,
- .adc_value = 899,
- .active_low = PRESS_LEV_LOW,
- },
-#endif
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = -1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
+++ /dev/null
-/*
- * Copyright (C) 2010 ROCKCHIP, Inc.
- * Author: roger_chen <cz@rock-chips.com>
- *
- * This program is the bluetooth device bcm4329's driver,
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/module.h>
-#include <linux/device.h>
-#include <linux/rfkill.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/interrupt.h>
-#include <linux/wakelock.h>
-#include <linux/fs.h>
-#include <asm/uaccess.h>
-#include <mach/gpio.h>
-#include <asm/irq.h>
-#include <mach/iomux.h>
-#include <linux/wakelock.h>
-#include <linux/timer.h>
-#include <mach/board.h>
-#if 0
-#define DBG(x...) printk(KERN_INFO x)
-#else
-#define DBG(x...)
-#endif
-
-#define BT_WAKE_HOST_SUPPORT 1
-
-struct bt_ctrl
-{
- struct rfkill *bt_rfk;
-#if BT_WAKE_HOST_SUPPORT
- struct timer_list tl;
- bool b_HostWake;
- struct wake_lock bt_wakelock;
-#endif
-};
-
-#define BT_GPIO_POWER RK29_PIN5_PD6
-#define IOMUX_BT_GPIO_POWER rk29_mux_api_set(GPIO5D6_SDMMC1PWREN_NAME, GPIO5H_GPIO5D6);
-#define BT_GPIO_RESET RK29_PIN6_PC7
-#define BT_GPIO_WAKE_UP RK29_PIN6_PD0
-#define BT_GPIO_WAKE_UP_HOST RK29_PIN4_PD4
-#define IOMUX_BT_GPIO_WAKE_UP_HOST() rk29_mux_api_set(GPIO4D4_CPUTRACECLK_NAME,GPIO4H_GPIO4D4);
-
-//bt cts paired to uart rts
-#define UART_RTS RK29_PIN2_PA7
-#define IOMUX_UART_RTS_GPIO rk29_mux_api_set(GPIO2A7_UART2RTSN_NAME, GPIO2L_GPIO2A7);
-#define IOMUX_UART_RTS rk29_mux_api_set(GPIO2A7_UART2RTSN_NAME, GPIO2L_UART2_RTS_N);
-
-#define BT_WAKE_LOCK_TIMEOUT 10 //s
-
-static const char bt_name[] = "bcm4329";
-extern int rk29sdk_bt_power_state;
-extern int rk29sdk_wifi_power_state;
-
-struct bt_ctrl gBtCtrl;
-
-#if BT_WAKE_HOST_SUPPORT
-void resetBtHostSleepTimer(void)
-{
- mod_timer(&(gBtCtrl.tl),jiffies + BT_WAKE_LOCK_TIMEOUT*HZ);//ÔÙÖØÐÂÉèÖó¬Ê±Öµ¡£
-}
-
-void btWakeupHostLock(void)
-{
- if(gBtCtrl.b_HostWake == false){
- DBG("*************************Lock\n");
-
- wake_lock(&(gBtCtrl.bt_wakelock));
- gBtCtrl.b_HostWake = true;
- }
-}
-
-void btWakeupHostUnlock(void)
-{
- if(gBtCtrl.b_HostWake == true){
- DBG("*************************UnLock\n");
- wake_unlock(&(gBtCtrl.bt_wakelock)); //ÈÃϵͳ˯Ãß
- gBtCtrl.b_HostWake = false;
- }
-}
-
-static void timer_hostSleep(unsigned long arg)
-{
- DBG("%s---b_HostWake=%d\n",__FUNCTION__,gBtCtrl.b_HostWake);
- btWakeupHostUnlock();
-}
-
-
-#ifdef CONFIG_PM
-static int bcm4329_rfkill_suspend(struct platform_device *pdev, pm_message_t state)
-{
- DBG("%s\n",__FUNCTION__);
-
- //To prevent uart to receive bt data when suspended
- IOMUX_UART_RTS_GPIO;
- gpio_request(UART_RTS, "uart_rts");
- gpio_direction_output(UART_RTS, 0);
- gpio_set_value(UART_RTS, GPIO_HIGH);
-
- return 0;
-}
-
-static int bcm4329_rfkill_resume(struct platform_device *pdev)
-{
- DBG("%s\n",__FUNCTION__);
-
- btWakeupHostLock();
- resetBtHostSleepTimer();
-
- gpio_set_value(UART_RTS, GPIO_LOW);
- IOMUX_UART_RTS;
-
- return 0;
-}
-#else
-#define bcm4329_rfkill_suspend NULL
-#define bcm4329_rfkill_resume NULL
-#endif
-
-static irqreturn_t bcm4329_wake_host_irq(int irq, void *dev)
-{
- DBG("%s\n",__FUNCTION__);
-
- btWakeupHostLock();
- resetBtHostSleepTimer();
- return IRQ_HANDLED;
-}
-#endif
-
-#ifdef CONFIG_BT_HCIBCM4325
-int bcm4325_sleep(int bSleep)
-{
- //printk("*************bt enter sleep***************\n");
- if (bSleep)
- gpio_set_value(BT_GPIO_WAKE_UP, GPIO_LOW); //low represent bt device may enter sleep
- else
- gpio_set_value(BT_GPIO_WAKE_UP, GPIO_HIGH); //high represent bt device must be awake
- //printk("sleep=%d\n",bSleep);
- return 0;
-}
-#endif
-
-static int bcm4329_set_block(void *data, bool blocked)
-{
- DBG("%s---blocked :%d\n", __FUNCTION__, blocked);
-
- IOMUX_BT_GPIO_POWER;
-
- if (false == blocked) {
- gpio_set_value(BT_GPIO_POWER, GPIO_HIGH); /* bt power on */
- gpio_set_value(BT_GPIO_RESET, GPIO_LOW);
- mdelay(200);
- gpio_set_value(BT_GPIO_RESET, GPIO_HIGH); /* bt reset deactive*/
- mdelay(200);
-
-#if BT_WAKE_HOST_SUPPORT
- btWakeupHostLock();
-#endif
- pr_info("bt turn on power\n");
- }
- else {
-#if BT_WAKE_HOST_SUPPORT
- btWakeupHostUnlock();
-#endif
- if (!rk29sdk_wifi_power_state) {
- gpio_set_value(BT_GPIO_POWER, GPIO_LOW); /* bt power off */
- mdelay(20);
- pr_info("bt shut off power\n");
- }else {
- pr_info("bt shouldn't shut off power, wifi is using it!\n");
- }
-
- gpio_set_value(BT_GPIO_RESET, GPIO_LOW); /* bt reset active*/
- mdelay(20);
- }
-
- rk29sdk_bt_power_state = !blocked;
- return 0;
-}
-
-
-static const struct rfkill_ops bcm4329_rfk_ops = {
- .set_block = bcm4329_set_block,
-};
-
-static int __devinit bcm4329_rfkill_probe(struct platform_device *pdev)
-{
- int rc = 0;
- bool default_state = true;
-
- DBG("Enter::%s,line=%d\n",__FUNCTION__,__LINE__);
-
- /* default to bluetooth off */
- bcm4329_set_block(NULL, default_state); /* blocked -> bt off */
-
- gBtCtrl.bt_rfk = rfkill_alloc(bt_name,
- NULL,
- RFKILL_TYPE_BLUETOOTH,
- &bcm4329_rfk_ops,
- NULL);
-
- if (!gBtCtrl.bt_rfk)
- {
- printk("fail to rfkill_allocate************\n");
- return -ENOMEM;
- }
-
- rfkill_set_states(gBtCtrl.bt_rfk, default_state, false);
-
- rc = rfkill_register(gBtCtrl.bt_rfk);
- if (rc)
- {
- printk("failed to rfkill_register,rc=0x%x\n",rc);
- rfkill_destroy(gBtCtrl.bt_rfk);
- }
-
- gpio_request(BT_GPIO_POWER, NULL);
- gpio_request(BT_GPIO_RESET, NULL);
- gpio_request(BT_GPIO_WAKE_UP, NULL);
-
-#if BT_WAKE_HOST_SUPPORT
- init_timer(&(gBtCtrl.tl));
- gBtCtrl.tl.expires = jiffies + BT_WAKE_LOCK_TIMEOUT*HZ;
- gBtCtrl.tl.function = timer_hostSleep;
- add_timer(&(gBtCtrl.tl));
- gBtCtrl.b_HostWake = false;
-
- wake_lock_init(&(gBtCtrl.bt_wakelock), WAKE_LOCK_SUSPEND, "bt_wake");
-
- rc = gpio_request(BT_GPIO_WAKE_UP_HOST, "bt_wake");
- if (rc) {
- printk("%s:failed to request RAHO_BT_WAKE_UP_HOST\n",__FUNCTION__);
- }
-
- IOMUX_BT_GPIO_WAKE_UP_HOST();
- gpio_pull_updown(BT_GPIO_WAKE_UP_HOST,GPIOPullUp);
- rc = request_irq(gpio_to_irq(BT_GPIO_WAKE_UP_HOST),bcm4329_wake_host_irq,IRQF_TRIGGER_FALLING,NULL,NULL);
- if(rc)
- {
- printk("%s:failed to request RAHO_BT_WAKE_UP_HOST irq\n",__FUNCTION__);
- gpio_free(BT_GPIO_WAKE_UP_HOST);
- }
- enable_irq_wake(gpio_to_irq(BT_GPIO_WAKE_UP_HOST)); // so RAHO_BT_WAKE_UP_HOST can wake up system
-
- printk(KERN_INFO "bcm4329 module has been initialized,rc=0x%x\n",rc);
- #endif
-
- return rc;
-
-
-}
-
-
-static int __devexit bcm4329_rfkill_remove(struct platform_device *pdev)
-{
- if (gBtCtrl.bt_rfk)
- rfkill_unregister(gBtCtrl.bt_rfk);
- gBtCtrl.bt_rfk = NULL;
-#if BT_WAKE_HOST_SUPPORT
- del_timer(&(gBtCtrl.tl));//ɾµô¶¨Ê±Æ÷
- btWakeupHostUnlock();
- wake_lock_destroy(&(gBtCtrl.bt_wakelock));
-#endif
- platform_set_drvdata(pdev, NULL);
-
- DBG("Enter::%s,line=%d\n",__FUNCTION__,__LINE__);
- return 0;
-}
-
-static struct platform_driver bcm4329_rfkill_driver = {
- .probe = bcm4329_rfkill_probe,
- .remove = __devexit_p(bcm4329_rfkill_remove),
- .driver = {
- .name = "rk29sdk_rfkill",
- .owner = THIS_MODULE,
- },
-#if BT_WAKE_HOST_SUPPORT
- .suspend = bcm4329_rfkill_suspend,
- .resume = bcm4329_rfkill_resume,
-#endif
-};
-
-/*
- * Module initialization
- */
-static int __init bcm4329_mod_init(void)
-{
- int ret;
- DBG("Enter::%s,line=%d\n",__FUNCTION__,__LINE__);
- ret = platform_driver_register(&bcm4329_rfkill_driver);
- printk("ret=0x%x\n", ret);
- return ret;
-}
-
-static void __exit bcm4329_mod_exit(void)
-{
- platform_driver_unregister(&bcm4329_rfkill_driver);
-}
-
-module_init(bcm4329_mod_init);
-module_exit(bcm4329_mod_exit);
-MODULE_DESCRIPTION("bcm4329 Bluetooth driver");
-MODULE_AUTHOR("roger_chen cz@rock-chips.com");
-MODULE_LICENSE("GPL");
-
+++ /dev/null
-/* arch/arm/mach-rk29/board-rk29-phonesdk.c
- *
- * Copyright (C) 2010 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/android_pmem.h>
-#include <linux/usb/android_composite.h>
-#include <linux/mpu.h>
-#include <linux/mpu3050.h>
-
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/iomux.h>
-#include <mach/gpio.h>
-#include <mach/irqs.h>
-#include <mach/rk29_iomap.h>
-#include <mach/board.h>
-#include <mach/rk29_nand.h>
-#include <mach/rk29_camera.h> /* ddl@rock-chips.com : camera support */
-#include <media/soc_camera.h> /* ddl@rock-chips.com : camera support */
-#include <mach/vpu_mem.h>
-#include <mach/sram.h>
-#include <mach/ddr.h>
-#include <mach/cpufreq.h>
-
-#include <linux/regulator/rk29-pwm-regulator.h>
-#include <linux/regulator/machine.h>
-#include <linux/mfd/wm831x/pdata.h>
-#include <linux/mfd/wm831x/core.h>
-#include <linux/mfd/wm831x/gpio.h>
-#include <linux/regulator/fixed.h>
-#include <linux/mfd/wm8994/pdata.h>
-
-#include <linux/mtd/nand.h>
-#include <linux/mtd/partitions.h>
-#include <linux/i2c-gpio.h>
-
-#include "devices.h"
-
-#if defined(CONFIG_MTK23D)
-#include <linux/mtk23d.h>
-#endif
-
-#include "../../../drivers/staging/android/timed_gpio.h"
-#include "../../../drivers/headset_observe/rk_headset.h"
-/*set touchscreen different type header*/
-#if defined(CONFIG_TOUCHSCREEN_XPT2046_NORMAL_SPI)
-#include "../../../drivers/input/touchscreen/xpt2046_ts.h"
-#elif defined(CONFIG_TOUCHSCREEN_XPT2046_TSLIB_SPI)
-#include "../../../drivers/input/touchscreen/xpt2046_tslib_ts.h"
-#elif defined(CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI)
-#include "../../../drivers/input/touchscreen/xpt2046_cbn_ts.h"
-#endif
-
-#include "../../../drivers/misc/gps/rk29_gps.h"
-#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Macro Define Begin ------------------------*/
-/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
-#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_OV5640 /* back camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_0 0x78
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 1
-#define CONFIG_SENSOR_ORIENTATION_0 0
-#define CONFIG_SENSOR_POWER_PIN_0 RK29_PIN5_PA0
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 RK29_PIN6_PB7
-#define CONFIG_SENSOR_FALSH_PIN_0 RK29_PIN6_PB5
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_H
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_H
-
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_OV7690 /* front camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_1 0x42
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 1
-#define CONFIG_SENSOR_ORIENTATION_1 0
-#define CONFIG_SENSOR_POWER_PIN_1 RK29_PIN5_PA0
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_1 RK29_PIN6_PB6
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_H
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-#endif //#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk29_camera.c"
-/*---------------- Camera Sensor Macro Define End ------------------------*/
-
-
-/* Set memory size of pmem */
-#ifdef CONFIG_RK29_MEM_SIZE_M
-#define SDRAM_SIZE (CONFIG_RK29_MEM_SIZE_M * SZ_1M)
-#else
-#define SDRAM_SIZE SZ_512M
-#endif
-#define PMEM_GPU_SIZE SZ_16M
-#define PMEM_UI_SIZE SZ_32M /* 1280x800: 64M 1024x768: 48M ... */
-#define PMEM_VPU_SIZE SZ_64M
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-#ifdef CONFIG_VIDEO_RK29_WORK_IPP
-#define MEM_CAMIPP_SIZE PMEM_CAMIPP_NECESSARY
-#else
-#define MEM_CAMIPP_SIZE 0
-#endif
-#define MEM_FB_SIZE (3*SZ_2M)
-#ifdef CONFIG_FB_WORK_IPP
-#define MEM_FBIPP_SIZE SZ_2M//SZ_8M //1920 x 1080 x 2 x 2 //RGB565 = x2;RGB888 = x4
-#else
-#define MEM_FBIPP_SIZE 0
-#endif
-#if SDRAM_SIZE > SZ_512M
-#define PMEM_GPU_BASE (RK29_SDRAM_PHYS + SZ_512M - PMEM_GPU_SIZE)
-#else
-#define PMEM_GPU_BASE (RK29_SDRAM_PHYS + SDRAM_SIZE - PMEM_GPU_SIZE)
-#endif
-#define PMEM_UI_BASE (PMEM_GPU_BASE - PMEM_UI_SIZE)
-#define PMEM_VPU_BASE (PMEM_UI_BASE - PMEM_VPU_SIZE)
-#define PMEM_CAM_BASE (PMEM_VPU_BASE - PMEM_CAM_SIZE)
-#define MEM_CAMIPP_BASE (PMEM_CAM_BASE - MEM_CAMIPP_SIZE)
-#define MEM_FB_BASE (MEM_CAMIPP_BASE - MEM_FB_SIZE)
-#define MEM_FBIPP_BASE (MEM_FB_BASE - MEM_FBIPP_SIZE)
-#define LINUX_SIZE (MEM_FBIPP_BASE - RK29_SDRAM_PHYS)
-
-#define PREALLOC_WLAN_SEC_NUM 4
-#define PREALLOC_WLAN_BUF_NUM 160
-#define PREALLOC_WLAN_SECTION_HEADER 24
-
-#define WLAN_SECTION_SIZE_0 (PREALLOC_WLAN_BUF_NUM * 128)
-#define WLAN_SECTION_SIZE_1 (PREALLOC_WLAN_BUF_NUM * 128)
-#define WLAN_SECTION_SIZE_2 (PREALLOC_WLAN_BUF_NUM * 512)
-#define WLAN_SECTION_SIZE_3 (PREALLOC_WLAN_BUF_NUM * 1024)
-
-#define WLAN_SKB_BUF_NUM 16
-#define UNLOCK_SECURITY_KEY ~(0x1<<5)
-#define LOCK_SECURITY_KEY 0x00
-
-static struct sk_buff *wlan_static_skb[WLAN_SKB_BUF_NUM];
-
-struct wifi_mem_prealloc {
- void *mem_ptr;
- unsigned long size;
-};
-
-extern struct sys_timer rk29_timer;
-
-static int rk29_nand_io_init(void)
-{
- return 0;
-}
-
-struct rk29_nand_platform_data rk29_nand_data = {
- .width = 1, /* data bus width in bytes */
- .hw_ecc = 1, /* hw ecc 0: soft ecc */
- .num_flash = 1,
- .io_init = rk29_nand_io_init,
-};
-
-#ifdef CONFIG_FB_RK29
-/*****************************************************************************************
- * lcd devices
- * author: zyw@rock-chips.com
- *****************************************************************************************/
-//#ifdef CONFIG_LCD_TD043MGEA1
-#define LCD_RXD_PIN RK29_PIN4_PC3
-#define LCD_TXD_PIN RK29_PIN4_PC7
-#define LCD_CLK_PIN RK29_PIN4_PC6
-#define LCD_CS_PIN RK29_PIN4_PC2
-/*****************************************************************************************
-* frame buffer devices
-* author: zyw@rock-chips.com
-*****************************************************************************************/
-#define FB_ID 0
-#define FB_DISPLAY_ON_PIN INVALID_GPIO//RK29_PIN6_PD0
-#define FB_LCD_STANDBY_PIN INVALID_GPIO//RK29_PIN6_PD1
-#define FB_LCD_CABC_EN_PIN INVALID_GPIO//RK29_PIN6_PD2
-#define FB_MCU_FMK_PIN INVALID_GPIO
-
-#define FB_DISPLAY_ON_VALUE GPIO_HIGH
-#define FB_LCD_STANDBY_VALUE GPIO_HIGH
-
-//#endif
-static int rk29_lcd_io_init(void)
-{
- int ret = 0;
-
- ret = gpio_request(LCD_TXD_PIN, NULL);
- ret = gpio_request(LCD_CLK_PIN, NULL);
- ret = gpio_request(LCD_CS_PIN, NULL);
- ret = gpio_request(RK29_PIN6_PC6, NULL);
-
- ret = gpio_request(RK29_PIN4_PC1, NULL);//RS
- gpio_direction_output(RK29_PIN4_PC1, 0);
- gpio_set_value(RK29_PIN4_PC1, GPIO_HIGH);
-
- rk29_mux_api_set(GPIO4C7_RMIIRXD0_MIIRXD0_NAME,GPIO4H_GPIO4C7);
- rk29_mux_api_set(GPIO4C6_RMIIRXD1_MIIRXD1_NAME,GPIO4H_GPIO4C6);
- rk29_mux_api_set(GPIO4C2_RMIITXD1_MIITXD1_NAME,GPIO4H_GPIO4C2);
- rk29_mux_api_set(GPIO4C1_RMIITXEN_MIITXEN_NAME,GPIO4H_GPIO4C1);
-
- return ret;
-}
-
-static int rk29_lcd_io_deinit(void)
-{
- int ret = 0;
- gpio_free(LCD_CS_PIN);
- gpio_free(LCD_CLK_PIN);
- gpio_free(LCD_TXD_PIN);
- gpio_free(RK29_PIN6_PC6);
- gpio_free(RK29_PIN4_PC1);
- rk29_mux_api_set(GPIO4C7_RMIIRXD0_MIIRXD0_NAME,GPIO4H_RMII_RXD0);
- rk29_mux_api_set(GPIO4C6_RMIIRXD1_MIIRXD1_NAME,GPIO4H_RMII_RXD1);
- rk29_mux_api_set(GPIO4C2_RMIITXD1_MIITXD1_NAME,GPIO4H_RMII_TXD1);
- return ret;
-}
-
-static struct rk29lcd_info rk29_lcd_info = {
- .txd_pin = LCD_TXD_PIN,
- .clk_pin = LCD_CLK_PIN,
- .cs_pin = LCD_CS_PIN,
- .io_init = rk29_lcd_io_init,
- .io_deinit = rk29_lcd_io_deinit,
-};
-
-int rk29_fb_io_enable(void)
-{
- if(FB_DISPLAY_ON_PIN != INVALID_GPIO)
- {
- gpio_direction_output(FB_DISPLAY_ON_PIN, 0);
- gpio_set_value(FB_DISPLAY_ON_PIN, FB_DISPLAY_ON_VALUE);
- }
- if(FB_LCD_STANDBY_PIN != INVALID_GPIO)
- {
- gpio_direction_output(FB_LCD_STANDBY_PIN, 0);
- gpio_set_value(FB_LCD_STANDBY_PIN, FB_LCD_STANDBY_VALUE);
- }
- return 0;
-}
-
-int rk29_fb_io_disable(void)
-{
- if(FB_DISPLAY_ON_PIN != INVALID_GPIO)
- {
- gpio_direction_output(FB_DISPLAY_ON_PIN, 0);
- gpio_set_value(FB_DISPLAY_ON_PIN, !FB_DISPLAY_ON_VALUE);
- }
- if(FB_LCD_STANDBY_PIN != INVALID_GPIO)
- {
- gpio_direction_output(FB_LCD_STANDBY_PIN, 0);
- gpio_set_value(FB_LCD_STANDBY_PIN, !FB_LCD_STANDBY_VALUE);
- }
- return 0;
-}
-
-static int rk29_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
- if(fb_setting->mcu_fmk_en && (FB_MCU_FMK_PIN != INVALID_GPIO))
- {
- ret = gpio_request(FB_MCU_FMK_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(FB_MCU_FMK_PIN);
- printk(">>>>>> FB_MCU_FMK_PIN gpio_request err \n ");
- }
- gpio_direction_input(FB_MCU_FMK_PIN);
- }
- if(fb_setting->disp_on_en && (FB_DISPLAY_ON_PIN != INVALID_GPIO))
- {
- ret = gpio_request(FB_DISPLAY_ON_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(FB_DISPLAY_ON_PIN);
- printk(">>>>>> FB_DISPLAY_ON_PIN gpio_request err \n ");
- }
- }
-
- if(fb_setting->disp_on_en && (FB_LCD_STANDBY_PIN != INVALID_GPIO))
- {
- ret = gpio_request(FB_LCD_STANDBY_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(FB_LCD_STANDBY_PIN);
- printk(">>>>>> FB_LCD_STANDBY_PIN gpio_request err \n ");
- }
- }
-
- if(FB_LCD_CABC_EN_PIN != INVALID_GPIO)
- {
- ret = gpio_request(FB_LCD_CABC_EN_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(FB_LCD_CABC_EN_PIN);
- printk(">>>>>> FB_LCD_CABC_EN_PIN gpio_request err \n ");
- }
- gpio_direction_output(FB_LCD_CABC_EN_PIN, 0);
- gpio_set_value(FB_LCD_CABC_EN_PIN, GPIO_LOW);
- }
- rk29_fb_io_enable(); //enable it
-
- return ret;
-}
-
-static struct rk29fb_info rk29_fb_info = {
- .fb_id = FB_ID,
- .mcu_fmk_pin = FB_MCU_FMK_PIN,
- .lcd_info = &rk29_lcd_info,
- .io_init = rk29_fb_io_init,
- .io_enable = rk29_fb_io_enable,
- .io_disable = rk29_fb_io_disable,
-};
-
-/* rk29 fb resource */
-static struct resource rk29_fb_resource[] = {
- [0] = {
- .name = "lcdc reg",
- .start = RK29_LCDC_PHYS,
- .end = RK29_LCDC_PHYS + RK29_LCDC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc irq",
- .start = IRQ_LCDC,
- .end = IRQ_LCDC,
- .flags = IORESOURCE_IRQ,
- },
- [2] = {
- .name = "win1 buf",
- .start = MEM_FB_BASE,
- .end = MEM_FB_BASE + MEM_FB_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- #ifdef CONFIG_FB_WORK_IPP
- [3] = {
- .name = "win1 ipp buf",
- .start = MEM_FBIPP_BASE,
- .end = MEM_FBIPP_BASE + MEM_FBIPP_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- #endif
-};
-
-/*platform_device*/
-struct platform_device rk29_device_fb = {
- .name = "rk29-fb",
- .id = 4,
- .num_resources = ARRAY_SIZE(rk29_fb_resource),
- .resource = rk29_fb_resource,
- .dev = {
- .platform_data = &rk29_fb_info,
- }
-};
-
-struct platform_device rk29_device_dma_cpy = {
- .name = "dma_memcpy",
- .id = 4,
-
-};
-
-#endif
-
-static struct android_pmem_platform_data android_pmem_pdata = {
- .name = "pmem",
- .start = PMEM_UI_BASE,
- .size = PMEM_UI_SIZE,
- .no_allocator = 1,
- .cached = 1,
-};
-
-static struct platform_device android_pmem_device = {
- .name = "android_pmem",
- .id = 0,
- .dev = {
- .platform_data = &android_pmem_pdata,
- },
-};
-
-
-
-static struct vpu_mem_platform_data vpu_mem_pdata = {
- .name = "vpu_mem",
- .start = PMEM_VPU_BASE,
- .size = PMEM_VPU_SIZE,
- .cached = 1,
-};
-
-static struct platform_device rk29_vpu_mem_device = {
- .name = "vpu_mem",
- .id = 2,
- .dev = {
- .platform_data = &vpu_mem_pdata,
- },
-};
-
-static struct platform_device rk29_v4l2_output_devce = {
- .name = "rk29_vout",
-};
-
-/*HANNSTAR_P1003 touch*/
-#if defined (CONFIG_HANNSTAR_P1003)
-#define TOUCH_RESET_PIN RK29_PIN6_PC3
-#define TOUCH_INT_PIN RK29_PIN4_PD5
-
-int p1003_init_platform_hw(void)
-{
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_pull_updown(TOUCH_INT_PIN, 1);
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
-
- return 0;
-}
-
-
-struct p1003_platform_data p1003_info = {
- .model= 1003,
- .init_platform_hw= p1003_init_platform_hw,
-
-};
-#endif
-
-#if defined (CONFIG_TOUCHSCREEN_GT801_IIC)
-#include "../../../drivers/input/touchscreen/gt801_ts.h"
-
-#define TOUCH_RESET_PIN RK29_PIN6_PC3
-#define TOUCH_INT_PIN RK29_PIN4_PD5
-
-int gt801_init_platform_hw(void)
-{
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("gt801_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("gt801_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_pull_updown(TOUCH_INT_PIN, 1);
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- mdelay(100);
-
- return 0;
-}
-
-
-static struct gt801_platform_data gt801_info = {
- .model= 801,
- .gpio_reset = TOUCH_RESET_PIN,
- .init_platform_hw = gt801_init_platform_hw,
-};
-#endif
-
-#if defined(CONFIG_TOUCHSCREEN_GT801_Z5)
-#include "../../../drivers/input/touchscreen/gt801_z5_ts.h"
-#define TOUCH_RESET_PIN RK29_PIN6_PC3
-#define TOUCH_INT_PIN RK29_PIN4_PD5
-
-int gt801_init_platform_hw(void)
-{
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("gt801_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("gt801_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_pull_updown(TOUCH_INT_PIN, 1);
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- mdelay(100);
- return 0;
-}
-
-
-static struct gt801_platform_data gt801_info = {
- .model= 801,
- .gpio_reset = TOUCH_RESET_PIN,
- .init_platform_hw= gt801_init_platform_hw,
-};
-#endif
-
-#if defined(CONFIG_TOUCHSCREEN_GT818_IIC)
-#include "../../../drivers/input/touchscreen/gt818_ts.h"
-#define GT818_GPIO_INT RK29_PIN4_PD5
-#define GT818_GPIO_RESET RK29_PIN6_PC3
-static struct gt818_platform_data gt818_info = {
- .model = 818,
- .swap_xy = 0,
- .x_min = 0,
- .x_max = 480,
- .y_min = 0,
- .y_max = 800,
- .gpio_reset = GT818_GPIO_RESET,
- .gpio_reset_active_low = 0,
- .gpio_pendown = GT818_GPIO_INT,
- .pendown_iomux_name = GPIO4D5_CPUTRACECTL_NAME,
- .resetpin_iomux_name = NULL,
- .pendown_iomux_mode = GPIO4H_GPIO4D5,
- .resetpin_iomux_mode = 0,
-};
-#endif
-
-#if defined(CONFIG_TOUCHSCREEN_FT5X0X_Z5) || defined (CONFIG_TOUCHSCREEN_FT5306)
-
-#define TOUCH_RESET_PIN RK29_PIN6_PC3
-#define TOUCH_INT_PIN RK29_PIN4_PD5
-int ft5406_init_platform_hw(void)
-{
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("ft5406_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("ift5406_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_pull_updown(TOUCH_INT_PIN, 0);
- gpio_direction_output(TOUCH_RESET_PIN, GPIO_HIGH);
- msleep(5);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- mdelay(5);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- return 0;
-}
-
-void ft5406_exit_platform_hw(void)
-{
- printk("ft5406_exit_platform_hw\n");
- gpio_free(TOUCH_RESET_PIN);
- gpio_free(TOUCH_INT_PIN);
-}
-
-int ft5406_platform_sleep(void)
-{
- //printk("ft5406_platform_sleep\n");
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- return 0;
-}
-
-int ft5406_platform_wakeup(void)
-{
- //printk("ft5406_platform_wakeup\n");
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- return 0;
-}
-
-struct ft5406_platform_data ft5406_info = {
-
- .init_platform_hw= ft5406_init_platform_hw,
- .exit_platform_hw= ft5406_exit_platform_hw,
- .platform_sleep = ft5406_platform_sleep,
- .platform_wakeup = ft5406_platform_wakeup,
-};
-
-#endif
-
-#if defined(CONFIG_TOUCHSCREEN_ILI2102_IIC)
-#include "../../../drivers/input/touchscreen/ili2102_ts.h"
-#define GT801_GPIO_INT RK29_PIN4_PD5
-#define GT801_GPIO_RESET RK29_PIN6_PC3
-static struct ili2102_platform_data ili2102_info = {
- .model = 2102,
- .swap_xy = 0,
- .x_min = 0,
- .x_max = 481,
- .y_min = 0,
- .y_max = 801,
- .gpio_reset = GT801_GPIO_RESET,
- .gpio_reset_active_low = 1,
- .gpio_pendown = GT801_GPIO_INT,
- .pendown_iomux_name = GPIO4D5_CPUTRACECTL_NAME,
- .resetpin_iomux_name = NULL,
- .pendown_iomux_mode = GPIO4H_GPIO4D5,
- .resetpin_iomux_mode = 0,
-};
-#endif
-
-/* EETI_EGALAX touch I2C */
-#if defined (CONFIG_EETI_EGALAX)
-#define TOUCH_RESET_PIN RK29_PIN6_PC3
-#define TOUCH_INT_PIN RK29_PIN4_PD5
-
-static int EETI_EGALAX_init_platform_hw(void)
-{
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_pull_updown(TOUCH_INT_PIN, 1);
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
-
- return 0;
-}
-
-
-static struct eeti_egalax_platform_data eeti_egalax_info = {
- .model= 1003,
- .init_platform_hw= EETI_EGALAX_init_platform_hw,
-
-};
-#endif
-
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN RK29_PIN6_PC4
-
-static int mma8452_init_platform_hw(void)
-{
-
- if(gpio_request(MMA8452_INT_PIN,NULL) != 0){
- gpio_free(MMA8452_INT_PIN);
- printk("mma8452_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_pull_updown(MMA8452_INT_PIN, 1);
- return 0;
-}
-
-
-static struct gsensor_platform_data mma8452_info = {
- .model= 8452,
- .swap_xy = 0,
- .init_platform_hw= mma8452_init_platform_hw,
-
-};
-#endif
-
-#if defined (CONFIG_MPU_SENSORS_MPU3050)
-/*mpu3050*/
-static struct mpu3050_platform_data mpu3050_data = {
- .int_config = 0x10,
- //.orientation = { 1, 0, 0,0, -1, 0,0, 0, 1 },
- .orientation = { 0, -1, 0,-1, 0, 0,0, 0, -1 },
- //.orientation = { -1, 0, 0,0, -1, 0,0, 0, -1 },
- //.orientation = { 0, 1, 0, -1, 0, 0, 0, 0, 1 },
- //.orientation = { 1, 0, 0,0, 1, 0, 0, 0, 1 },
- .level_shifter = 0,
-#if defined (CONFIG_MPU_SENSORS_KXTF9)
- .accel = {
-#ifdef CONFIG_MPU_SENSORS_MPU3050_MODULE
- .get_slave_descr = NULL ,
-#else
- .get_slave_descr = get_accel_slave_descr ,
-#endif
- .adapt_num = 0, // The i2c bus to which the mpu device is
- // connected
- //.irq = RK29_PIN6_PC4,
- .bus = EXT_SLAVE_BUS_SECONDARY, //The secondary I2C of MPU
- .address = 0x0f,
- //.orientation = { 1, 0, 0,0, 1, 0,0, 0, 1 },
- //.orientation = { 0, -1, 0,-1, 0, 0,0, 0, -1 },
- //.orientation = { 0, 1, 0,1, 0, 0,0, 0, -1 },
- //.orientation = { 0, 1 ,0, -1 ,0, 0, 0, 0, 1 },
- .orientation = {1, 0, 0, 0, 1, 0, 0, 0, 1},
- },
-#endif
-
-#if defined (CONFIG_MPU_SENSORS_MMA845X)
- .accel = {
-#ifdef CONFIG_MPU_SENSORS_MPU3050_MODULE
- .get_slave_descr = NULL ,
-#else
- .get_slave_descr = get_accel_slave_descr ,
-#endif
- .adapt_num = 0, // The i2c bus to which the mpu device is
- // connected
- //.irq = RK29_PIN6_PC4,
- .bus = EXT_SLAVE_BUS_SECONDARY, //The secondary I2C of MPU
- .address = 0x1c,
- //.orientation = { 1, 0, 0,0, 1, 0,0, 0, 1 },
- //.orientation = { 0, -1, 0,-1, 0, 0,0, 0, -1 },
- .orientation = { 0, 1, 0,1, 0, 0,0, 0, -1 },
- //.orientation = { 0, 1 ,0, -1 ,0, 0, 0, 0, 1 },
- },
-#endif
-
-#if defined (CONFIG_MPU_SENSORS_AK8975)
- .compass = {
-#ifdef CONFIG_MPU_SENSORS_MPU3050_MODULE
- .get_slave_descr = NULL,/*ak5883_get_slave_descr,*/
-#else
- .get_slave_descr = get_compass_slave_descr,
-#endif
- .adapt_num = 0, // The i2c bus to which the compass device is.
- // It can be difference with mpu
- // connected
- //.irq = RK29_PIN6_PC5,
- .bus = EXT_SLAVE_BUS_PRIMARY,
- .address = 0x0d,
- //.orientation = { -1, 0, 0,0, -1, 0,0, 0, 1 },
- //.orientation = { 0, -1, 0,-1, 0, 0,0, 0, -1 },
- //.orientation = { 0, 1, 0,1, 0, 0,0, 0, -1 },
- //.orientation = { 0, -1, 0, 1, 0, 0, 0, 0, 1 },
- //.orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
- .orientation = { 1, 0 ,0, 0 ,-1, 0, 0, 0, -1 },
- },
-};
-#endif
-#endif
-
-#if defined(CONFIG_GPIO_WM831X)
-struct rk29_gpio_expander_info wm831x_gpio_settinginfo[] = {
- {
- .gpio_num =WM831X_P01,// tp3
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
-
- {
- .gpio_num =WM831X_P02,//tp4
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P03,//tp2
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P04,//tp1
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P05,//tp1
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P06,//tp1
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P07,//tp1
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P08,//tp1
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P09,//tp1
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P10,//tp1
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P11,//tp1
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
- {
- .gpio_num =WM831X_P12,
- .pin_type = GPIO_OUT,
- .pin_value =GPIO_HIGH,
- },
-};
-
-#endif
-
-
-
-#if defined(CONFIG_MFD_WM831X)
-static struct wm831x *gWm831x;
-int wm831x_pre_init(struct wm831x *parm)
-{
- int ret;
- printk("%s\n", __FUNCTION__);
- gWm831x = parm;
- //ILIM = 900ma
- ret = wm831x_reg_read(parm, WM831X_POWER_STATE) & 0xffff;
- wm831x_reg_write(parm, WM831X_POWER_STATE, (ret&0xfff8) | 0x04);
-
- //BATT_FET_ENA = 1
- wm831x_reg_write(parm,WM831X_SECURITY_KEY,0x9716); // unlock security key
- wm831x_set_bits(parm, WM831X_RESET_CONTROL,0x1000,0x1000);
- ret = wm831x_reg_read(parm, WM831X_RESET_CONTROL) & 0xffff&UNLOCK_SECURITY_KEY;// enternal reset active in sleep
- printk("%s:WM831X_RESET_CONTROL=0x%x\n",__FUNCTION__,ret);
- wm831x_reg_write(parm, WM831X_RESET_CONTROL, ret);
-
-
- wm831x_reg_write(parm,WM831X_SECURITY_KEY,LOCK_SECURITY_KEY); // lock security key
-
-
-#if 0
- wm831x_set_bits(parm, WM831X_LDO_ENABLE, (1 << 3), 0);
- wm831x_set_bits(parm, WM831X_LDO_ENABLE, (1 << 7), 0);
- printk("%s:disable ldo4 and ldo8 because they are enabled in uboot\n",__FUNCTION__);
-#endif
- return 0;
-}
-int wm831x_post_init(struct wm831x *parm)
-{
- struct regulator *dcdc;
- struct regulator *ldo;
-
-
- dcdc = regulator_get(NULL, "dcdc3"); // 1th IO
- regulator_set_voltage(dcdc,3000000,3000000);
- regulator_set_suspend_voltage(dcdc, 2800000);
- regulator_enable(dcdc);
- printk("%s set dcdc3=%dmV end\n", __FUNCTION__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo10"); // 1th modem IO
- regulator_set_voltage(ldo,3000000,3000000);
- regulator_set_suspend_voltage(ldo,3000000);
- regulator_enable(ldo);
- printk("%s set ldo10=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- dcdc = regulator_get(NULL, "dcdc2"); // 2th CORE
- regulator_set_voltage(dcdc,1300000,1300000);
- regulator_set_suspend_voltage(dcdc,1000000);
- regulator_enable(dcdc);
- printk("%s set dcdc2=%dmV end\n", __FUNCTION__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- dcdc = regulator_get(NULL, "dcdc1"); // 3th ddr
- regulator_set_voltage(dcdc,1800000,1800000);
- regulator_set_suspend_voltage(dcdc,1800000);
- regulator_enable(dcdc);
- printk("%s set dcdc1=%dmV end\n", __FUNCTION__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo1"); // 3th nand
- regulator_set_voltage(ldo,1800000,1800000);
- regulator_set_suspend_voltage(ldo,1800000);
- regulator_enable(ldo);
- printk("%s set ldo1=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo4"); // 4th usb
- regulator_set_voltage(ldo,2500000,2500000);
- regulator_set_suspend_voltage(ldo,0000000);
- regulator_enable(ldo);
- printk("%s set ldo4=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo7"); // 5th usb
- regulator_set_voltage(ldo,3300000,3300000);
- regulator_set_suspend_voltage(ldo,3300000);
- regulator_enable(ldo);
- printk("%s set ldo7=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- dcdc = regulator_get(NULL, "dcdc4"); // backlight
- regulator_set_voltage(dcdc,20000000,16000000);
- regulator_set_suspend_voltage(dcdc, 16000000);
- regulator_enable(dcdc);
- printk("%s set dcdc4=%dmV end\n", __FUNCTION__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-#if 1
-
- ldo = regulator_get(NULL, "ldo2"); //lcd
- regulator_set_voltage(ldo,3000000,3000000);
- regulator_set_suspend_voltage(ldo,3000000);
- regulator_enable(ldo);
- printk("%s set ldo2=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
-
-
- ldo = regulator_get(NULL, "ldo5"); //tf
- regulator_set_voltage(ldo,3000000,3000000);
- regulator_set_suspend_voltage(ldo,3000000);
- regulator_enable(ldo);
- printk("%s set ldo5=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo6"); //camera
- regulator_set_voltage(ldo,2800000,2800000);
- regulator_set_suspend_voltage(ldo,2800000);
- regulator_enable(ldo);
- printk("%s set ldo6=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
-
-
-
-#if 1
-#if 0
- ldo = regulator_get(NULL, "ldo3"); //sram
- regulator_set_voltage(ldo,1800000,1800000);
- regulator_set_suspend_voltage(ldo,1800000);
- regulator_enable(ldo);
- printk("%s set ldo3=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
-#endif
-
- ldo = regulator_get(NULL, "ldo8"); //cmmb
- regulator_set_voltage(ldo,1200000,1200000);
- regulator_set_suspend_voltage(ldo,1200000);
- regulator_enable(ldo);
- printk("%s set ldo8=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo9"); //cmmb
- regulator_set_voltage(ldo,3000000,3000000);
- regulator_set_suspend_voltage(ldo,3000000);
- regulator_enable(ldo);
- printk("%s set ldo9=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
-#endif
-
-#endif
-
- ldo = regulator_get(NULL, "ldo11");
- //regulator_enable(ldo);
- printk("%s set ldo11=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
-
-
- return 0;
-}
-
-extern void wm831x_enter_sleep(void);
-extern void wm831x_exit_sleep(void);
-
-void pmu_wm831x_set_suspend_voltage(void)
-{
-
-}
-EXPORT_SYMBOL_GPL(pmu_wm831x_set_suspend_voltage);
-
-void pmu_wm831x_set_resume_voltage(void)
-{
-
-}
-EXPORT_SYMBOL_GPL(pmu_wm831x_set_resume_voltage);
-
-int wm831x_last_deinit(struct wm831x *parm)
-{
- struct regulator* ldo;
-
- printk("%s\n", __FUNCTION__);
-
- ldo = regulator_get(NULL, "ldo1");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo2");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo3");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo4");
- //regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo5");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo6");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo7");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo8");
- //regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo9");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo10");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- return 0;
-}
-
-struct wm831x_backlight_pdata wm831x_backlight_platdata = {
- .isink = 1, /** ISINK to use, 1 or 2 */
- .max_uA = 19484, /** Maximum current to allow */
-};
-
-struct wm831x_backup_pdata wm831x_backup_platdata = {
- .charger_enable = 1,
- .no_constant_voltage = 0, /** Disable constant voltage charging */
- .vlim = 3100, /** Voltage limit in milivolts */
- .ilim = 300, /** Current limit in microamps */
-};
-
-struct wm831x_battery_pdata wm831x_battery_platdata = {
- .enable = 1, /** Enable charging */
- .fast_enable = 1, /** Enable fast charging */
- .off_mask = 1, /** Mask OFF while charging */
- .trickle_ilim = 200, /** Trickle charge current limit, in mA */
- .vsel = 4200, /** Target voltage, in mV */
- .eoc_iterm = 50, /** End of trickle charge current, in mA */
- .fast_ilim = 600, /** Fast charge current limit, in mA */
- .timeout = 480, /** Charge cycle timeout, in minutes */
- .syslo = 3300, /* syslo threshold, in mV*/
- .sysok = 3500, /* sysko threshold, in mV*/
-};
-
-struct wm831x_status_pdata wm831x_status_platdata[WM831X_MAX_STATUS] = {
- {
- .default_src = WM831X_STATUS_OTP,
- .name = "wm831x_status0",
- .default_trigger = "wm831x_otp",
- },
- {
- .default_src = WM831X_STATUS_POWER,
- .name = "wm831x_status1",
- .default_trigger = "wm831x_power",
- },
-};
-
-
-static struct regulator_consumer_supply dcdc1_consumers[] = {
- {
- .supply = "dcdc1",
- }
-};
-static struct regulator_consumer_supply dcdc2_consumers[] = {
- {
- .supply = "dcdc2",
- },
- {
- .supply = "vcore",
- }
-};
-static struct regulator_consumer_supply dcdc3_consumers[] = {
- {
- .supply = "dcdc3",
- }
-};
-static struct regulator_consumer_supply dcdc4_consumers[] = {
- {
- .supply = "dcdc4",
- }
-};
-static struct regulator_consumer_supply epe1_consumers[] = {
- {
- .supply = "epe1",
- }
-};
-static struct regulator_consumer_supply epe2_consumers[] = {
- {
- .supply = "epe2",
- }
-};
-static struct regulator_consumer_supply ldo1_consumers[] = {
- {
- .supply = "ldo1",
- }
-};
-static struct regulator_consumer_supply ldo2_consumers[] = {
- {
- .supply = "ldo2",
- }
-};
-static struct regulator_consumer_supply ldo3_consumers[] = {
- {
- .supply = "ldo3",
- }
-};
-static struct regulator_consumer_supply ldo4_consumers[] = {
- {
- .supply = "ldo4",
- }
-};
-static struct regulator_consumer_supply ldo5_consumers[] = {
- {
- .supply = "ldo5",
- }
-};
-static struct regulator_consumer_supply ldo6_consumers[] = {
- {
- .supply = "ldo6",
- }
-};
-static struct regulator_consumer_supply ldo7_consumers[] = {
- {
- .supply = "ldo7",
- }
-};
-static struct regulator_consumer_supply ldo8_consumers[] = {
- {
- .supply = "ldo8",
- }
-};
-static struct regulator_consumer_supply ldo9_consumers[] = {
- {
- .supply = "ldo9",
- }
-};
-static struct regulator_consumer_supply ldo10_consumers[] = {
- {
- .supply = "ldo10",
- }
-};
-static struct regulator_consumer_supply ldo11_consumers[] = {
- {
- .supply = "ldo11",
- }
-};
-static struct regulator_consumer_supply isink1_consumers[] = {
- {
- .supply = "isink1",
- }
-};
-static struct regulator_consumer_supply isink2_consumers[] = {
- {
- .supply = "isink2",
- }
-};
-
-struct regulator_init_data wm831x_regulator_init_dcdc[WM831X_MAX_DCDC] = {
- {
- .constraints = {
- .name = "DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000,//0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(dcdc1_consumers),
- .consumer_supplies = dcdc1_consumers,
- },
- {
- .constraints = {
- .name = "DCDC2",
- .min_uV = 600000,
- .max_uV = 1800000,//0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(dcdc2_consumers),
- .consumer_supplies = dcdc2_consumers,
- },
- {
- .constraints = {
- .name = "DCDC3",
- .min_uV = 850000,
- .max_uV = 3400000,//0.85-3.4V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(dcdc3_consumers),
- .consumer_supplies = dcdc3_consumers,
- },
- {
- .constraints = {
- .name = "DCDC4",
- .min_uV = 00000000,
- .max_uV = 30000000,//30V/40mA
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(dcdc4_consumers),
- .consumer_supplies = dcdc4_consumers,
- },
-
-};
-struct regulator_init_data wm831x_regulator_init_epe[WM831X_MAX_EPE] = {
- {
- .constraints = {
- .name = "EPE1",
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(epe1_consumers),
- .consumer_supplies = epe1_consumers,
- },
- {
- .constraints = {
- .name = "EPE2",
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(epe2_consumers),
- .consumer_supplies = epe2_consumers,
- },
-};
-
-struct regulator_init_data wm831x_regulator_init_ldo[WM831X_MAX_LDO] = {
- {
- .constraints = {
- .name = "LDO1",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo1_consumers),
- .consumer_supplies = ldo1_consumers,
- },
- {
- .constraints = {
- .name = "LDO2",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
- .consumer_supplies = ldo2_consumers,
- },
- {
- .constraints = {
- .name = "LDO3",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo3_consumers),
- .consumer_supplies = ldo3_consumers,
- },
- {
- .constraints = {
- .name = "LDO4",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo4_consumers),
- .consumer_supplies = ldo4_consumers,
- },
- {
- .constraints = {
- .name = "LDO5",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo5_consumers),
- .consumer_supplies = ldo5_consumers,
- },
- {
- .constraints = {
- .name = "LDO6",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo6_consumers),
- .consumer_supplies = ldo6_consumers,
- },
- {
- .constraints = {
- .name = "LDO7",
- .min_uV = 1000000,
- .max_uV = 3500000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo7_consumers),
- .consumer_supplies = ldo7_consumers,
- },
- {
- .constraints = {
- .name = "LDO8",
- .min_uV = 1000000,
- .max_uV = 3500000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo8_consumers),
- .consumer_supplies = ldo8_consumers,
- },
- {
- .constraints = {
- .name = "LDO9",
- .min_uV = 1000000,
- .max_uV = 3500000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo9_consumers),
- .consumer_supplies = ldo9_consumers,
- },
- {
- .constraints = {
- .name = "LDO10",
- .min_uV = 1000000,
- .max_uV = 3500000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo10_consumers),
- .consumer_supplies = ldo10_consumers,
- },
- {
- .constraints = {
- .name = "LDO11",
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo11_consumers),
- .consumer_supplies = ldo11_consumers,
- },
-};
-
-struct regulator_init_data wm831x_regulator_init_isink[WM831X_MAX_ISINK] = {
- {
- .constraints = {
- .name = "ISINK1",
- .min_uA = 00000,
- .max_uA = 40000,
- .always_on = true,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_CURRENT,
- },
- .num_consumer_supplies = ARRAY_SIZE(isink1_consumers),
- .consumer_supplies = isink1_consumers,
- },
- {
- .constraints = {
- .name = "ISINK2",
- .min_uA = 0000000,
- .max_uA = 0000000,
- .apply_uV = false,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_CURRENT,
- },
- .num_consumer_supplies = ARRAY_SIZE(isink2_consumers),
- .consumer_supplies = isink2_consumers,
- },
-};
-
-static int wm831x_checkrange(int start,int num,int val)
-{
- if((val<(start+num))&&(val>=start))
- return 0;
- else
- return -1;
-}
-
-static int wm831x_init_pin_type(struct wm831x *wm831x)
-{
-#if 1
- struct wm831x_pdata *pdata = wm831x->dev->platform_data;
- struct rk29_gpio_expander_info *wm831x_gpio_settinginfo;
- uint16_t offset = 0;
- uint16_t wm831x_settingpin_num = 0;
- uint16_t ret = 0;
- int i = 0;
-
- if(wm831x)
- {
- wm831x_gpio_settinginfo=pdata->settinginfo;
- if(wm831x_gpio_settinginfo)
- {
- wm831x_settingpin_num = pdata->settinginfolen;
- for(i=0;i<wm831x_settingpin_num;i++)
- {
- if(!wm831x_checkrange(pdata->gpio_base,pdata->gpio_pin_num,wm831x_gpio_settinginfo[i].gpio_num))
- {
- offset = wm831x_gpio_settinginfo[i].gpio_num - pdata->gpio_base;
-
- if(wm831x_gpio_settinginfo[i].pin_type==GPIO_IN)
- {
- wm831x_set_bits(wm831x,(WM831X_GPIO1_CONTROL+offset), WM831X_GPN_DIR_MASK|WM831X_GPN_TRI_MASK, 1<<WM831X_GPN_DIR_SHIFT|1<<WM831X_GPN_TRI_SHIFT);
- }
- else
- {
- wm831x_set_bits(wm831x,(WM831X_GPIO1_CONTROL+offset), WM831X_GPN_DIR_MASK|WM831X_GPN_TRI_MASK, 1<<WM831X_GPN_TRI_SHIFT);
- if(wm831x_gpio_settinginfo[i].pin_value==GPIO_HIGH)
- {
- wm831x_set_bits(wm831x, WM831X_GPIO_LEVEL, (1 << offset),(1 << offset));
- }
- else
- {
- wm831x_set_bits(wm831x, WM831X_GPIO_LEVEL, (1 << offset),(0 << offset));
- }
- }
-
- }
- }
- }
- }
-
- for(i=0;i<pdata->gpio_pin_num;i++)
- {
- wm831x_set_bits(wm831x,(WM831X_GPIO1_CONTROL+i),
- WM831X_GPN_PULL_MASK|WM831X_GPN_POL_MASK|WM831X_GPN_OD_MASK|WM831X_GPN_TRI_MASK,
- 1<<WM831X_GPN_POL_SHIFT|1<<WM831X_GPN_TRI_SHIFT);
- ret = wm831x_reg_read(wm831x, WM831X_GPIO1_CONTROL+i);
- printk("Gpio%d Pin Configuration = %x\n",i,ret);
- }
-#endif
- return 0;
-}
-
-/*
- * GPIO Buttons
- */
-#if defined(CONFIG_KEYBOARD_WM831X_GPIO)
-static struct wm831x_gpio_keys_button wm831x_gpio_buttons[] = {
-{
- .code = KEY_MEDIA,
- .gpio = TCA6424_P21,
- .active_low = 1,
- .desc = "media",
- .wakeup = 0,
- .debounce_interval = 120,
-},
-{
- .code= KEY_VOLUMEUP,
- .gpio= WM831X_P05,
- .active_low= 1,
- .desc= "volume_up",
- .wakeup= 0,
-},
-{
- .code= KEY_CAMERA,
- .gpio= WM831X_P06,
- .active_low= 1,
- .desc= "camera",
- .wakeup= 0,
-},
-{
- .code= KEY_VOLUMEDOWN,
- .gpio= WM831X_P07,
- .active_low= 1,
- .desc= "volume_down",
- .wakeup= 0,
-},
-{
- .code= KEY_END,
- .gpio= WM831X_P09,
- .active_low= 1,
- .desc= "enter",
- .wakeup= 0,
-},
-{
- .code= KEY_MENU,
- .gpio= WM831X_P10,
- .active_low= 1,
- .desc= "menu",
- .wakeup= 0,
-},
-{
- .code= KEY_SEND,
- .gpio= WM831X_P11,
- .active_low= 1,
- .desc= "esc",
- .wakeup= 0,
-},
-{
- .code= KEY_BACK,
- .gpio= WM831X_P12,
- .active_low= 1,
- .desc= "home",
- .wakeup= 0,
-},
-};
-
-struct wm831x_gpio_keys_pdata wm831x_gpio_keys_platdata = {
- .buttons = wm831x_gpio_buttons,
- .nbuttons = ARRAY_SIZE(wm831x_gpio_buttons),
-};
-
-#endif
-struct wm831x_pdata wm831x_platdata = {
- /** Called before subdevices are set up */
- .pre_init= wm831x_pre_init,
- /** Called after subdevices are set up */
- .post_init = wm831x_post_init,
- /** Called before subdevices are power down */
- .last_deinit = wm831x_last_deinit,
-
-#if defined(CONFIG_GPIO_WM831X)
- .gpio_base=WM831X_GPIO_EXPANDER_BASE,
- .gpio_pin_num=WM831X_TOTOL_GPIO_NUM,
- .settinginfo=wm831x_gpio_settinginfo,
- .settinginfolen=ARRAY_SIZE(wm831x_gpio_settinginfo),
- .pin_type_init = wm831x_init_pin_type,
- .irq_base= NR_AIC_IRQS + 7*NUM_GROUP,
-#endif
-
- .backlight = &wm831x_backlight_platdata,
-
- .backup = &wm831x_backup_platdata,
-
- .battery = &wm831x_battery_platdata,
- //.wm831x_touch_pdata = NULL,
- //.watchdog = NULL,
-
-#if defined(CONFIG_KEYBOARD_WM831X_GPIO)
- .gpio_keys = &wm831x_gpio_keys_platdata,
-#endif
-
- /** LED1 = 0 and so on */
- .status = {&wm831x_status_platdata[0], &wm831x_status_platdata[1]},
-
- /** DCDC1 = 0 and so on */
- .dcdc = {&wm831x_regulator_init_dcdc[0], &wm831x_regulator_init_dcdc[1], &wm831x_regulator_init_dcdc[2], &wm831x_regulator_init_dcdc[3]},
-
- /** EPE1 = 0 and so on */
- .epe = {&wm831x_regulator_init_epe[0], &wm831x_regulator_init_epe[1]},
-
- /** LDO1 = 0 and so on */
- .ldo = {&wm831x_regulator_init_ldo[0], &wm831x_regulator_init_ldo[1], &wm831x_regulator_init_ldo[2], &wm831x_regulator_init_ldo[3],
- &wm831x_regulator_init_ldo[4], &wm831x_regulator_init_ldo[5], &wm831x_regulator_init_ldo[6], &wm831x_regulator_init_ldo[7],
- &wm831x_regulator_init_ldo[8], &wm831x_regulator_init_ldo[9], &wm831x_regulator_init_ldo[10]},
-
- /** ISINK1 = 0 and so on*/
- .isink = {&wm831x_regulator_init_isink[0], &wm831x_regulator_init_isink[1]},
-};
-#endif
-
-#if defined(CONFIG_RK29_GPIO_SUSPEND)
-static void gpio_set_request(void)
-{
- gpio_request(RK29_PIN6_PA0, NULL);
- gpio_request(RK29_PIN6_PA1, NULL);
- gpio_request(RK29_PIN6_PA2, NULL);
- gpio_request(RK29_PIN6_PA3, NULL);
- gpio_request(RK29_PIN6_PA4, NULL);
- gpio_request(RK29_PIN6_PA5, NULL);
- gpio_request(RK29_PIN6_PA6, NULL);
-
- gpio_request(RK29_PIN2_PA5, NULL);
- gpio_request(RK29_PIN2_PA4, NULL);
- gpio_request(RK29_PIN2_PB0, NULL);
- gpio_request(RK29_PIN2_PB1, NULL);
- gpio_request(RK29_PIN2_PB2, NULL);
- gpio_request(RK29_PIN2_PB3, NULL);
-
- gpio_request(RK29_PIN1_PA4, NULL);
- gpio_request(RK29_PIN1_PA3, NULL);
-
- gpio_request(RK29_PIN2_PC7, NULL);
- gpio_request(RK29_PIN2_PC6, NULL);
- gpio_request(RK29_PIN2_PC5, NULL);
- gpio_request(RK29_PIN2_PC4, NULL);
- gpio_request(RK29_PIN2_PC3, NULL);
- gpio_request(RK29_PIN2_PC2, NULL);
- gpio_request(RK29_PIN2_PC1, NULL);
- gpio_request(RK29_PIN2_PC0, NULL);
-}
-
-static void gpio_set_free(void)
-{
- gpio_free(RK29_PIN6_PA0);
- gpio_free(RK29_PIN6_PA1);
- gpio_free(RK29_PIN6_PA2);
- gpio_free(RK29_PIN6_PA3);
- gpio_free(RK29_PIN6_PA4);
- gpio_free(RK29_PIN6_PA5);
- gpio_free(RK29_PIN6_PA6);
-
- gpio_free(RK29_PIN2_PA5);
- gpio_free(RK29_PIN2_PA4);
- gpio_free(RK29_PIN2_PB0);
- gpio_free(RK29_PIN2_PB1);
- gpio_free(RK29_PIN2_PB2);
- gpio_free(RK29_PIN2_PB3);
-
- gpio_free(RK29_PIN1_PA4);
- gpio_free(RK29_PIN1_PA3);
-
- gpio_free(RK29_PIN2_PC7);
- gpio_free(RK29_PIN2_PC6);
- gpio_free(RK29_PIN2_PC5);
- gpio_free(RK29_PIN2_PC4);
- gpio_free(RK29_PIN2_PC3);
- gpio_free(RK29_PIN2_PC2);
- gpio_free(RK29_PIN2_PC1);
- gpio_free(RK29_PIN2_PC0);
-}
-
-static void rk29_keygpio_suspend(void)
-{
- gpio_pull_updown(RK29_PIN6_PA0, 0);
- gpio_pull_updown(RK29_PIN6_PA1, 0);
- gpio_pull_updown(RK29_PIN6_PA2, 0);
- gpio_pull_updown(RK29_PIN6_PA3, 0);
- gpio_pull_updown(RK29_PIN6_PA4, 0);
- gpio_pull_updown(RK29_PIN6_PA5, 0);
- gpio_pull_updown(RK29_PIN6_PA6, 0);//key pullup/pulldown disable
-
- gpio_pull_updown(RK29_PIN2_PA4, 0);
- gpio_pull_updown(RK29_PIN2_PA5, 0);
- gpio_pull_updown(RK29_PIN2_PB0, 0);
- gpio_pull_updown(RK29_PIN2_PB1, 0);
- gpio_pull_updown(RK29_PIN2_PB2, 0);
- gpio_pull_updown(RK29_PIN2_PB3, 0);
-}
-
-static void rk29_keygpio_resume(void)
-{
- gpio_pull_updown(RK29_PIN6_PA0, 1);
- gpio_pull_updown(RK29_PIN6_PA1, 1);
- gpio_pull_updown(RK29_PIN6_PA2, 1);
- gpio_pull_updown(RK29_PIN6_PA3, 1);
- gpio_pull_updown(RK29_PIN6_PA4, 1);
- gpio_pull_updown(RK29_PIN6_PA5, 1);
- gpio_pull_updown(RK29_PIN6_PA6, 1);//key pullup/pulldown enable
-
- gpio_pull_updown(RK29_PIN2_PA4, 1);
- gpio_pull_updown(RK29_PIN2_PA5, 1);
- gpio_pull_updown(RK29_PIN2_PB0, 1);
- gpio_pull_updown(RK29_PIN2_PB1, 1);
- gpio_pull_updown(RK29_PIN2_PB2, 1);
- gpio_pull_updown(RK29_PIN2_PB3, 1);
-}
-
-static void spi_gpio_suspend(void)
-{
- rk29_mux_api_set(GPIO1A4_EMMCWRITEPRT_SPI0CS1_NAME,GPIO1L_GPIO1A4); //set iomux is gpio mode
- rk29_mux_api_set(GPIO1A3_EMMCDETECTN_SPI1CS1_NAME,GPIO1L_GPIO1A3);
-
- rk29_mux_api_set(GPIO2C7_SPI1RXD_NAME,GPIO2H_GPIO2C7);
- rk29_mux_api_set(GPIO2C6_SPI1TXD_NAME,GPIO2H_GPIO2C6);
- //rk29_mux_api_set(GPIO2C5_SPI1CSN0_NAME,GPIO2H_GPIO2C5);
- rk29_mux_api_set(GPIO2C4_SPI1CLK_NAME,GPIO2H_GPIO2C4);
- rk29_mux_api_set(GPIO2C3_SPI0RXD_NAME,GPIO2H_GPIO2C3);
- rk29_mux_api_set(GPIO2C2_SPI0TXD_NAME,GPIO2H_GPIO2C2);
- rk29_mux_api_set(GPIO2C1_SPI0CSN0_NAME,GPIO2H_GPIO2C1);
- rk29_mux_api_set(GPIO2C0_SPI0CLK_NAME,GPIO2H_GPIO2C0);
-
- gpio_direction_input(RK29_PIN1_PA4); //set gpio is input
- gpio_direction_input(RK29_PIN1_PA3);
- gpio_direction_input(RK29_PIN2_PC7);
- gpio_direction_input(RK29_PIN2_PC6);
- // gpio_direction_input(RK29_PIN2_PC5);
- gpio_direction_input(RK29_PIN2_PC4);
- gpio_direction_input(RK29_PIN2_PC3);
- gpio_direction_input(RK29_PIN2_PC2);
- gpio_direction_input(RK29_PIN2_PC1);
- gpio_direction_input(RK29_PIN2_PC0);
-
- gpio_pull_updown(RK29_PIN1_PA4, 0); //set gpio pullup/down disable
- gpio_pull_updown(RK29_PIN1_PA3, 0);
-
- gpio_pull_updown(RK29_PIN2_PC7, 0);
- gpio_pull_updown(RK29_PIN2_PC6, 0);
- //gpio_pull_updown(RK29_PIN2_PC5, 0);
- gpio_pull_updown(RK29_PIN2_PC4, 0);
- gpio_pull_updown(RK29_PIN2_PC3, 0);
- gpio_pull_updown(RK29_PIN2_PC2, 0);
- gpio_pull_updown(RK29_PIN2_PC1, 0);
- gpio_pull_updown(RK29_PIN2_PC0, 0);
-}
-
-static void spi_gpio_resume(void)
-{
- gpio_pull_updown(RK29_PIN1_PA4, 1); //set gpio pullup/down enable
- gpio_pull_updown(RK29_PIN1_PA3, 1);
-
- gpio_pull_updown(RK29_PIN2_PC7, 1);
- gpio_pull_updown(RK29_PIN2_PC6, 1);
- //gpio_pull_updown(RK29_PIN2_PC5, 1);
- gpio_pull_updown(RK29_PIN2_PC4, 1);
- gpio_pull_updown(RK29_PIN2_PC3, 1);
- gpio_pull_updown(RK29_PIN2_PC2, 1);
- gpio_pull_updown(RK29_PIN2_PC1, 1);
- gpio_pull_updown(RK29_PIN2_PC0, 1);
-
- rk29_mux_api_set(GPIO1A4_EMMCWRITEPRT_SPI0CS1_NAME,GPIO1L_SPI0_CSN1); //set iomux is spi mode
- rk29_mux_api_set(GPIO1A3_EMMCDETECTN_SPI1CS1_NAME,GPIO1L_SPI1_CSN1);
-
- rk29_mux_api_set(GPIO2C7_SPI1RXD_NAME,GPIO2H_SPI1_RXD);
- rk29_mux_api_set(GPIO2C6_SPI1TXD_NAME,GPIO2H_SPI1_TXD);
- //rk29_mux_api_set(GPIO2C5_SPI1CSN0_NAME,GPIO2H_SPI1_CSN0);
- rk29_mux_api_set(GPIO2C4_SPI1CLK_NAME, GPIO2H_SPI1_CLK);
- rk29_mux_api_set(GPIO2C3_SPI0RXD_NAME,GPIO2H_SPI0_RXD);
- rk29_mux_api_set(GPIO2C2_SPI0TXD_NAME,GPIO2H_SPI0_TXD);
- rk29_mux_api_set(GPIO2C1_SPI0CSN0_NAME,GPIO2H_SPI0_CSN0);
- rk29_mux_api_set(GPIO2C0_SPI0CLK_NAME,GPIO2H_SPI0_CLK);
-}
-
-void rk29_setgpio_suspend_board(void)
-{
- gpio_set_request();
- rk29_keygpio_suspend();
- spi_gpio_suspend();
- gpio_set_free();
-}
-
-void rk29_setgpio_resume_board(void)
-{
- gpio_set_request();
- rk29_keygpio_resume();
- spi_gpio_resume();
- gpio_set_free();
-}
-#endif
-
-#if defined(CONFIG_RK29_GPS)
-
-#define RK29_GPS_POWER_PIN RK29_PIN6_PB2
-#define RK29_GPS_RESET_PIN RK29_PIN6_PA7//RK29_PIN6_PC1 //modif by zwx CONFIG_CSR_GPS_GSD4E
-
-int rk29_gps_power_up(void)
-{
- printk("%s \n", __FUNCTION__);
-
- gpio_request(RK29_GPS_POWER_PIN, NULL);
- gpio_direction_output(RK29_GPS_POWER_PIN, GPIO_HIGH);
-
- return 0;
-}
-
-int rk29_gps_power_down(void)
-{
- printk("%s \n", __FUNCTION__);
-
- gpio_request(RK29_GPS_POWER_PIN, NULL);
- gpio_direction_output(RK29_GPS_POWER_PIN, GPIO_LOW);
-
- return 0;
-}
-
-int rk29_gps_reset_set(int level)
-{
- gpio_request(RK29_GPS_RESET_PIN, NULL);
- if (level)
- gpio_direction_output(RK29_GPS_RESET_PIN, GPIO_HIGH);
- else
- gpio_direction_output(RK29_GPS_RESET_PIN, GPIO_LOW);
- return 0;
-}
-#ifdef CONFIG_CSR_GPS_GSD4E
-struct gps_rfkill_platform_data gps_rfkill_data=
-{
- .nshutdown_gpio=RK29_PIN6_PB2,
- .reset_gpio=RK29_PIN6_PA7,
-};
-static struct platform_device rk_csrgps_device={
-
- .name = "csr-gps",
- .id = -1,
- .dev = {
- .platform_data = &gps_rfkill_data,
- },
-};
-#else
-struct rk29_gps_data rk29_gps_info = {
- .power_up = rk29_gps_power_up,
- .power_down = rk29_gps_power_down,
- .reset = rk29_gps_reset_set,
- .uart_id = 3,
-};
-
-struct platform_device rk29_device_gps = {
- .name = "rk29_gps",
- .id = -1,
- .dev = {
- .platform_data = &rk29_gps_info,
- }
- };
-#endif
-#endif
-
-/*****************************************************************************************
- * wm8994 codec
- * author: qjb@rock-chips.com
- *****************************************************************************************/
-#if defined(CONFIG_MFD_WM8994)
-static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = {
- REGULATOR_SUPPLY("DBVDD", "5-001a"),
- REGULATOR_SUPPLY("AVDD2", "5-001a"),
- REGULATOR_SUPPLY("CPVDD", "5-001a"),
-};
-
-static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = {
- REGULATOR_SUPPLY("SPKVDD1", "5-001a"),
- REGULATOR_SUPPLY("SPKVDD2", "5-001a"),
-};
-
-static struct regulator_init_data wm8994_fixed_voltage0_init_data = {
- .constraints = {
- .always_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage0_supplies),
- .consumer_supplies = wm8994_fixed_voltage0_supplies,
-};
-
-static struct regulator_init_data wm8994_fixed_voltage1_init_data = {
- .constraints = {
- .always_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage1_supplies),
- .consumer_supplies = wm8994_fixed_voltage1_supplies,
-};
-
-static struct fixed_voltage_config wm8994_fixed_voltage0_config = {
- .supply_name = "VCC_1.8V_PDA",
- .microvolts = 1800000,
- .gpio = -EINVAL,
- .init_data = &wm8994_fixed_voltage0_init_data,
-};
-
-static struct fixed_voltage_config wm8994_fixed_voltage1_config = {
- .supply_name = "V_BAT",
- .microvolts = 3700000,
- .gpio = -EINVAL,
- .init_data = &wm8994_fixed_voltage1_init_data,
-};
-
-static struct platform_device wm8994_fixed_voltage0 = {
- .name = "reg-fixed-voltage",
- .id = 0,
- .dev = {
- .platform_data = &wm8994_fixed_voltage0_config,
- },
-};
-
-static struct platform_device wm8994_fixed_voltage1 = {
- .name = "reg-fixed-voltage",
- .id = 1,
- .dev = {
- .platform_data = &wm8994_fixed_voltage1_config,
- },
-};
-
-static struct regulator_consumer_supply wm8994_avdd1_supply =
- REGULATOR_SUPPLY("AVDD1", "5-001a");
-
-static struct regulator_consumer_supply wm8994_dcvdd_supply =
- REGULATOR_SUPPLY("DCVDD", "5-001a");
-
-
-
-static struct regulator_init_data wm8994_ldo1_data = {
- .constraints = {
- .name = "AVDD1_3.0V",
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = 1,
- .consumer_supplies = &wm8994_avdd1_supply,
-};
-
-static struct regulator_init_data wm8994_ldo2_data = {
- .constraints = {
- .name = "DCVDD_1.0V",
- },
- .num_consumer_supplies = 1,
- .consumer_supplies = &wm8994_dcvdd_supply,
-};
-
-static struct wm8994_pdata wm8994_platform_data = {
-#if defined (CONFIG_GPIO_WM8994)
- .gpio_base = WM8994_GPIO_EXPANDER_BASE,
- //Fill value to initialize the GPIO
-// .gpio_defaults ={},
- /* configure gpio1 function: 0x0001(Logic level input/output) */
-// .gpio_defaults[0] = 0x0001,
- /* configure gpio3/4/5/7 function for AIF2 voice */
- .gpio_defaults[2] = 0x2100,
- .gpio_defaults[3] = 0x2100,
- .gpio_defaults[4] = 0xA100,
-// .gpio_defaults[6] = 0x0100,
- /* configure gpio8/9/10/11 function for AIF3 BT */
- .gpio_defaults[7] = 0xA100,
- .gpio_defaults[8] = 0x2100,
- .gpio_defaults[9] = 0x2100,
- .gpio_defaults[10] = 0x2100,
-#endif
-
- .ldo[0] = { RK29_PIN5_PA1, NULL, &wm8994_ldo1_data }, /* XM0FRNB_2 */
- .ldo[1] = { 0, NULL, &wm8994_ldo2_data },
-
- .micdet_irq = 0,
- .irq_base = 0,
-};
-#endif
-
-#ifdef CONFIG_RK_HEADSET_DET
-#define HEADSET_GPIO RK29_PIN4_PD2
-struct rk_headset_pdata rk_headset_info = {
- .Headset_gpio = RK29_PIN4_PD2,
- .headset_in_type= HEADSET_IN_HIGH,
- .Hook_gpio = RK29_PIN4_PD1,//Detection Headset--Must be set
- .hook_key_code = KEY_MEDIA,
-};
-
-struct platform_device rk_device_headset = {
- .name = "rk_headsetdet",
- .id = 0,
- .dev = {
- .platform_data = &rk_headset_info,
- }
-};
-#endif
-
-#if defined(CONFIG_GS_L3G4200D)
-
-#include <linux/l3g4200d.h>
-#define L3G4200D_INT_PIN RK29_PIN5_PA3
-
-static int l3g4200d_init_platform_hw(void)
-{
- if (gpio_request(L3G4200D_INT_PIN, NULL) != 0) {
- gpio_free(L3G4200D_INT_PIN);
- printk("%s: request l3g4200d int pin error\n", __func__);
- return -EIO;
- }
- gpio_pull_updown(L3G4200D_INT_PIN, 1);
- return 0;
-}
-
-static struct l3g4200d_platform_data l3g4200d_info = {
- .fs_range = 1,
-
- .axis_map_x = 0,
- .axis_map_y = 1,
- .axis_map_z = 2,
-
- .negate_x = 1,
- .negate_y = 1,
- .negate_z = 0,
-
- .init = l3g4200d_init_platform_hw,
-};
-
-#endif
-
-/*****************************************************************************************
- * i2c devices
- * author: kfx@rock-chips.com
-*****************************************************************************************/
-static int rk29_i2c0_io_init(void)
-{
-#ifdef CONFIG_RK29_I2C0_CONTROLLER
- rk29_mux_api_set(GPIO2B7_I2C0SCL_NAME, GPIO2L_I2C0_SCL);
- rk29_mux_api_set(GPIO2B6_I2C0SDA_NAME, GPIO2L_I2C0_SDA);
-#else
- rk29_mux_api_set(GPIO2B7_I2C0SCL_NAME, GPIO2L_GPIO2B7);
- rk29_mux_api_set(GPIO2B6_I2C0SDA_NAME, GPIO2L_GPIO2B6);
-#endif
- return 0;
-}
-
-static int rk29_i2c1_io_init(void)
-{
-#ifdef CONFIG_RK29_I2C1_CONTROLLER
- rk29_mux_api_set(GPIO1A7_I2C1SCL_NAME, GPIO1L_I2C1_SCL);
- rk29_mux_api_set(GPIO1A6_I2C1SDA_NAME, GPIO1L_I2C1_SDA);
-#else
- rk29_mux_api_set(GPIO1A7_I2C1SCL_NAME, GPIO1L_GPIO1A7);
- rk29_mux_api_set(GPIO1A6_I2C1SDA_NAME, GPIO1L_GPIO1A6);
-#endif
- return 0;
-}
-static int rk29_i2c2_io_init(void)
-{
-#ifdef CONFIG_RK29_I2C2_CONTROLLER
- rk29_mux_api_set(GPIO5D4_I2C2SCL_NAME, GPIO5H_I2C2_SCL);
- rk29_mux_api_set(GPIO5D3_I2C2SDA_NAME, GPIO5H_I2C2_SDA);
-#else
- rk29_mux_api_set(GPIO5D4_I2C2SCL_NAME, GPIO5H_GPIO5D4);
- rk29_mux_api_set(GPIO5D3_I2C2SDA_NAME, GPIO5H_GPIO5D3);
-#endif
- return 0;
-}
-
-static int rk29_i2c3_io_init(void)
-{
-#ifdef CONFIG_RK29_I2C3_CONTROLLER
- rk29_mux_api_set(GPIO2B5_UART3RTSN_I2C3SCL_NAME, GPIO2L_I2C3_SCL);
- rk29_mux_api_set(GPIO2B4_UART3CTSN_I2C3SDA_NAME, GPIO2L_I2C3_SDA);
-#else
- rk29_mux_api_set(GPIO2B5_UART3RTSN_I2C3SCL_NAME, GPIO2L_GPIO2B5);
- rk29_mux_api_set(GPIO2B4_UART3CTSN_I2C3SDA_NAME, GPIO2L_GPIO2B4);
-#endif
- return 0;
-}
-#ifdef CONFIG_RK29_I2C0_CONTROLLER
-struct rk29_i2c_platform_data default_i2c0_data = {
- .bus_num = 0,
- .flags = 0,
- .slave_addr = 0xff,
- .scl_rate = 400*1000,
- .mode = I2C_MODE_IRQ,
- .io_init = rk29_i2c0_io_init,
-};
-#else
-struct i2c_gpio_platform_data default_i2c0_data = {
- .sda_pin = RK29_PIN2_PB6,
- .scl_pin = RK29_PIN2_PB7,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(200),
- .bus_num = 0,
- .io_init = rk29_i2c0_io_init,
-};
-#endif
-#ifdef CONFIG_RK29_I2C1_CONTROLLER
-struct rk29_i2c_platform_data default_i2c1_data = {
- .bus_num = 1,
- .flags = 0,
- .slave_addr = 0xff,
- .scl_rate = 400*1000,
- .mode = I2C_MODE_IRQ,
- .io_init = rk29_i2c1_io_init,
-};
-#else
-struct i2c_gpio_platform_data default_i2c1_data = {
- .sda_pin = RK29_PIN1_PA6,
- .scl_pin = RK29_PIN1_PA7,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(200),
- .bus_num = 1,
- .io_init = rk29_i2c1_io_init,
-};
-#endif
-#ifdef CONFIG_RK29_I2C2_CONTROLLER
-struct rk29_i2c_platform_data default_i2c2_data = {
- .bus_num = 2,
- .flags = 0,
- .slave_addr = 0xff,
- .scl_rate = 400*1000,
- .mode = I2C_MODE_IRQ,
- .io_init = rk29_i2c2_io_init,
-};
-#else
-struct i2c_gpio_platform_data default_i2c2_data = {
- .sda_pin = RK29_PIN5_PD3,
- .scl_pin = RK29_PIN5_PD4,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(200),
- .bus_num = 2,
- .io_init = rk29_i2c2_io_init,
-};
-#endif
-#ifdef CONFIG_RK29_I2C3_CONTROLLER
-struct rk29_i2c_platform_data default_i2c3_data = {
- .bus_num = 3,
- .flags = 0,
- .slave_addr = 0xff,
- .scl_rate = 400*1000,
- .mode = I2C_MODE_IRQ,
- .io_init = rk29_i2c3_io_init,
-};
-#else
-struct i2c_gpio_platform_data default_i2c3_data = {
- .sda_pin = RK29_PIN5_PB5,
- .scl_pin = RK29_PIN5_PB4,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(200),
- .bus_num = 3,
- .io_init = rk29_i2c3_io_init,
-};
-#endif
-#ifdef CONFIG_I2C0_RK29
-static struct i2c_board_info __initdata board_i2c0_devices[] = {
-#if defined (CONFIG_RK1000_CONTROL)
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_WM8900)
- {
- .type = "wm8900",
- .addr = 0x1A,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_WM8994)
- {
- .type = "wm8994",
- .addr = 0x1a,
- .flags = 0,
- #if defined(CONFIG_MFD_WM8994)
- .platform_data = &wm8994_platform_data,
- #endif
- },
-#endif
-#if defined (CONFIG_BATTERY_STC3100)
- {
- .type = "stc3100",
- .addr = 0x70,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_BATTERY_BQ27510)
- {
- .type = "bq27510",
- .addr = 0x55,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_RTC_HYM8563)
- {
- .type = "rtc_hym8563",
- .addr = 0x51,
- .flags = 0,
- .irq = RK29_PIN0_PA1,
- },
-#endif
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1c,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8973)
- {
- .type = "ak8973",
- .addr = 0x1d,
- .flags = 0,
- .irq = RK29_PIN6_PC5,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK29_PIN6_PC5,
- },
-#endif
-#if defined (CONFIG_INPUT_LPSENSOR_ISL29028)
- {
- .type = "isl29028",
- .addr = 0x44,
- .flags = 0,
- .irq = RK29_PIN4_PD3,
- },
-#endif
-#if defined (CONFIG_INPUT_LPSENSOR_APDS9900)
- {
- .type = "apds9900",
- .addr = 0x39,
- .flags = 0,
- .irq = RK29_PIN4_PD3,
- },
-#endif
-#if defined (CONFIG_ANX7150)
- {
- .type = "anx7150",
- .addr = 0x39, //0x39, 0x3d
- .flags = 0,
- .irq = RK29_PIN2_PA3,
- },
-#endif
-#if defined (CONFIG_GS_L3G4200D)
- {
- .type = "gs_l3g4200d",
- .addr = 0x69,
- .flags = 0,
- .irq = L3G4200D_INT_PIN,
- .platform_data = &l3g4200d_info,
- },
-#endif
-#if defined (CONFIG_MPU_SENSORS_MPU3050)
- {
- .type = "mpu3050",
- .addr = 0x68,
- .flags = 0,
- .irq = RK29_PIN4_PC4,
- .platform_data = &mpu3050_data,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C1_RK29
-static struct i2c_board_info __initdata board_i2c1_devices[] = {
-#if defined (CONFIG_RK1000_CONTROL1)
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C2_RK29
-static struct i2c_board_info __initdata board_i2c2_devices[] = {
-#if defined (CONFIG_TOUCHSCREEN_GT801_IIC) || defined (CONFIG_TOUCHSCREEN_GT801_Z5)
-{
- .type = "gt801_ts",
- .addr = 0x55,
- .flags = 0,
- .irq = RK29_PIN4_PD5,
- .platform_data = >801_info,
-},
-#endif
-#if defined (CONFIG_TOUCHSCREEN_GT818_IIC)
-{
- .type = "gt818_ts",
- .addr = 0x5d,
- .flags = 0,
- .irq = RK29_PIN4_PD5,
- .platform_data = >818_info,
-},
-#endif
-
-#if defined(CONFIG_TOUCHSCREEN_FT5X0X_Z5) || defined (CONFIG_TOUCHSCREEN_FT5306)
-{
- .type = "ft5x0x_ts",
- .addr =0x38 ,
- .flags = 0,
- .irq = RK29_PIN4_PD5,
- .platform_data = &ft5406_info,
-},
-#endif
-
-#if defined (CONFIG_TOUCHSCREEN_ILI2102_IIC)
-{
- .type = "ili2102_ts",
- .addr = 0x41,
- .flags = I2C_M_NEED_DELAY,
- .udelay = 600,
- .irq = RK29_PIN4_PD5,
- .platform_data = &ili2102_info,
-},
-#endif
-
-#if defined (CONFIG_MFD_WM831X_I2C)
-{
- .type = "wm8310",
- .addr = 0x34,
- .flags = 0,
- .irq = RK29_PIN4_PD0,
- .platform_data = &wm831x_platdata,
-},
-#endif
-#if defined (CONFIG_HANNSTAR_P1003)
- {
- .type = "p1003_touch",
- .addr = 0x04,
- .flags = 0,
- .irq = RK29_PIN0_PA2,
- .platform_data = &p1003_info,
- },
-#endif
-#if defined (CONFIG_EETI_EGALAX)
- {
- .type = "egalax_i2c",
- .addr = 0x04,
- .flags = 0,
- .irq = RK29_PIN4_PD5,
- .platform_data = &eeti_egalax_info,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK29
-static struct i2c_board_info __initdata board_i2c3_devices[] = {
-};
-#endif
-
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#define CONFIG_SENSOR_POWER_IOCTL_USR 0
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_RESET_IOCTL_USR
-static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
-static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-#include "../../../drivers/media/video/rk29_camera.c"
-#endif
-
-/*****************************************************************************************
- * backlight devices
- * author: nzy@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- /*
- GPIO1B5_PWM0_NAME, GPIO1L_PWM0
- GPIO5D2_PWM1_UART1SIRIN_NAME, GPIO5H_PWM1
- GPIO2A3_SDMMC0WRITEPRT_PWM2_NAME, GPIO2L_PWM2
- GPIO1A5_EMMCPWREN_PWM3_NAME, GPIO1L_PWM3
- */
-
-#define PWM_ID 0
-#define PWM_MUX_NAME GPIO1B5_PWM0_NAME
-#define PWM_MUX_MODE GPIO1L_PWM0
-#define PWM_MUX_MODE_GPIO GPIO1L_GPIO1B5
-#define PWM_EFFECT_VALUE 1
-
-//#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-#define BL_EN_MUX_NAME GPIOF34_UART3_SEL_NAME
-#define BL_EN_MUX_MODE IOMUXB_GPIO1_B34
-
-#define BL_EN_PIN GPIO0L_GPIO0A5
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
-
- rk29_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
- #ifdef LCD_DISP_ON_PIN
- rk29_mux_api_set(BL_EN_MUX_NAME, BL_EN_MUX_MODE);
-
- ret = gpio_request(BL_EN_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(BL_EN_PIN);
- }
-
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
- #endif
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0;
- #ifdef LCD_DISP_ON_PIN
- gpio_free(BL_EN_PIN);
- #endif
- rk29_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- return ret;
-}
-struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
-};
-#endif
-/*****************************************************************************************
-* pwm voltage regulator devices
-******************************************************************************************/
-#if defined (CONFIG_RK29_PWM_REGULATOR)
-
-#define REGULATOR_PWM_ID 2
-#define REGULATOR_PWM_MUX_NAME GPIO2A3_SDMMC0WRITEPRT_PWM2_NAME
-#define REGULATOR_PWM_MUX_MODE GPIO2L_PWM2
-#define REGULATOR_PWM_MUX_MODE_GPIO GPIO2L_GPIO2A3
-#define REGULATOR_PWM_GPIO RK29_PIN2_PA3
-
-static struct regulator_consumer_supply pwm_consumers[] = {
- {
- .supply = "vcore",
- }
-};
-
-static struct regulator_init_data rk29_pwm_regulator_data = {
- .constraints = {
- .name = "PWM2",
- .min_uV = 950000,
- .max_uV = 1400000,
- .apply_uV = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_consumers),
- .consumer_supplies = pwm_consumers,
-};
-
-static struct pwm_platform_data rk29_regulator_pwm_platform_data = {
- .pwm_id = REGULATOR_PWM_ID,
- .pwm_gpio = REGULATOR_PWM_GPIO,
- //.pwm_iomux_name[] = REGULATOR_PWM_MUX_NAME;
- .pwm_iomux_name = REGULATOR_PWM_MUX_NAME,
- .pwm_iomux_pwm = REGULATOR_PWM_MUX_MODE,
- .pwm_iomux_gpio = REGULATOR_PWM_MUX_MODE_GPIO,
- .init_data = &rk29_pwm_regulator_data,
-};
-
-static struct platform_device rk29_device_pwm_regulator = {
- .name = "pwm-voltage-regulator",
- .id = -1,
- .dev = {
- .platform_data = &rk29_regulator_pwm_platform_data,
- },
-};
-
-#endif
-
-
-#if defined(CONFIG_MTK23D)
-static int mtk23d_io_init(void)
-{
- return 0;
-}
-
-static int mtk23d_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk2818_23d_data rk2818_23d_info = {
- .io_init = mtk23d_io_init,
- .io_deinit = mtk23d_io_deinit,
- .bp_power = RK29_PIN6_PB0,
- .bp_power_active_low = 0,
- .bp_reset = RK29_PIN6_PB1,
- .bp_reset_active_low = 0,
- .bp_statue = RK29_PIN0_PA2,//input high bp sleep;
- .ap_statue = RK29_PIN0_PA3,//output high ap sleep;
- .ap_bp_wakeup = RK29_PIN0_PA0, //output AP wake up BP used rising edge;
- .bp_ap_wakeup = RK29_PIN0_PA4,//input BP wake up AP
-};
-struct platform_device rk2818_device_mtk23d = {
- .name = "mtk23d",
- .id = -1,
- .dev = {
- .platform_data = &rk2818_23d_info,
- }
- };
-#endif
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
-#define SDMMC0_WRITE_PROTECT_PIN RK29_PIN6_PB0 //According to your own project to set the value of write-protect-pin.
-#endif
-
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
-#define SDMMC1_WRITE_PROTECT_PIN RK29_PIN6_PB0 //According to your own project to set the value of write-protect-pin.
-#endif
-
-/*****************************************************************************************
- * SDMMC devices
-*****************************************************************************************/
-#if !defined(CONFIG_SDMMC_RK29_OLD)
-static void rk29_sdmmc_gpio_open(int device_id, int on)
-{
- switch(device_id)
- {
- case 0://mmc0
- {
- #ifdef CONFIG_SDMMC0_RK29
- if(on)
- {
- gpio_direction_output(RK29_PIN1_PD0,GPIO_HIGH);//set mmc0-clk to high
- gpio_direction_output(RK29_PIN1_PD1,GPIO_HIGH);//set mmc0-cmd to high.
- gpio_direction_output(RK29_PIN1_PD2,GPIO_HIGH);//set mmc0-data0 to high.
- gpio_direction_output(RK29_PIN1_PD3,GPIO_HIGH);//set mmc0-data1 to high.
- gpio_direction_output(RK29_PIN1_PD4,GPIO_HIGH);//set mmc0-data2 to high.
- gpio_direction_output(RK29_PIN1_PD5,GPIO_HIGH);//set mmc0-data3 to high.
-
- mdelay(30);
- }
- else
- {
- rk29_mux_api_set(GPIO1D0_SDMMC0CLKOUT_NAME, GPIO1H_GPIO1_D0);
- gpio_request(RK29_PIN1_PD0, "mmc0-clk");
- gpio_direction_output(RK29_PIN1_PD0,GPIO_LOW);//set mmc0-clk to low.
-
- rk29_mux_api_set(GPIO1D1_SDMMC0CMD_NAME, GPIO1H_GPIO1_D1);
- gpio_request(RK29_PIN1_PD1, "mmc0-cmd");
- gpio_direction_output(RK29_PIN1_PD1,GPIO_LOW);//set mmc0-cmd to low.
-
- rk29_mux_api_set(GPIO1D2_SDMMC0DATA0_NAME, GPIO1H_GPIO1D2);
- gpio_request(RK29_PIN1_PD2, "mmc0-data0");
- gpio_direction_output(RK29_PIN1_PD2,GPIO_LOW);//set mmc0-data0 to low.
-
- rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_GPIO1D3);
- gpio_request(RK29_PIN1_PD3, "mmc0-data1");
- gpio_direction_output(RK29_PIN1_PD3,GPIO_LOW);//set mmc0-data1 to low.
-
- rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_GPIO1D4);
- gpio_request(RK29_PIN1_PD4, "mmc0-data2");
- gpio_direction_output(RK29_PIN1_PD4,GPIO_LOW);//set mmc0-data2 to low.
-
- rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_GPIO1D5);
- gpio_request(RK29_PIN1_PD5, "mmc0-data3");
- gpio_direction_output(RK29_PIN1_PD5,GPIO_LOW);//set mmc0-data3 to low.
-
- mdelay(30);
- }
- #endif
- }
- break;
-
- case 1://mmc1
- {
- #ifdef CONFIG_SDMMC1_RK29
- if(on)
- {
- gpio_direction_output(RK29_PIN1_PC7,GPIO_HIGH);//set mmc1-clk to high
- gpio_direction_output(RK29_PIN1_PC2,GPIO_HIGH);//set mmc1-cmd to high.
- gpio_direction_output(RK29_PIN1_PC3,GPIO_HIGH);//set mmc1-data0 to high.
- gpio_direction_output(RK29_PIN1_PC4,GPIO_HIGH);//set mmc1-data1 to high.
- gpio_direction_output(RK29_PIN1_PC5,GPIO_HIGH);//set mmc1-data2 to high.
- gpio_direction_output(RK29_PIN1_PC6,GPIO_HIGH);//set mmc1-data3 to high.
- mdelay(100);
- }
- else
- {
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_GPIO1C7);
- gpio_request(RK29_PIN1_PC7, "mmc1-clk");
- gpio_direction_output(RK29_PIN1_PC7,GPIO_LOW);//set mmc1-clk to low.
-
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_GPIO1C2);
- gpio_request(RK29_PIN1_PC2, "mmc1-cmd");
- gpio_direction_output(RK29_PIN1_PC2,GPIO_LOW);//set mmc1-cmd to low.
-
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_GPIO1C3);
- gpio_request(RK29_PIN1_PC3, "mmc1-data0");
- gpio_direction_output(RK29_PIN1_PC3,GPIO_LOW);//set mmc1-data0 to low.
-
- mdelay(100);
- }
- #endif
- }
- break;
-
- case 2: //mmc2
- break;
-
- default:
- break;
- }
-}
-
-
-static void rk29_sdmmc_set_iomux_mmc0(unsigned int bus_width)
-{
- switch (bus_width)
- {
-
- case 1://SDMMC_CTYPE_4BIT:
- {
- rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_SDMMC0_DATA1);
- rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_SDMMC0_DATA2);
- rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_SDMMC0_DATA3);
- }
- break;
-
- case 0x10000://SDMMC_CTYPE_8BIT:
- break;
- case 0xFFFF: //gpio_reset
- {
- rk29_mux_api_set(GPIO5D5_SDMMC0PWREN_NAME, GPIO5H_GPIO5D5);
- gpio_request(RK29_PIN5_PD5,"sdmmc-power");
- gpio_direction_output(RK29_PIN5_PD5,GPIO_HIGH); //power-off
-
- rk29_sdmmc_gpio_open(0, 0);
-
- gpio_direction_output(RK29_PIN5_PD5,GPIO_LOW); //power-on
-
- rk29_sdmmc_gpio_open(0, 1);
- }
- break;
-
- default: //case 0://SDMMC_CTYPE_1BIT:
- {
- rk29_mux_api_set(GPIO1D1_SDMMC0CMD_NAME, GPIO1H_SDMMC0_CMD);
- rk29_mux_api_set(GPIO1D0_SDMMC0CLKOUT_NAME, GPIO1H_SDMMC0_CLKOUT);
- rk29_mux_api_set(GPIO1D2_SDMMC0DATA0_NAME, GPIO1H_SDMMC0_DATA0);
-
- rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_GPIO1D3);
- gpio_request(RK29_PIN1_PD3, "mmc0-data1");
- gpio_direction_output(RK29_PIN1_PD3,GPIO_HIGH);
-
- rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_GPIO1D4);
- gpio_request(RK29_PIN1_PD4, "mmc0-data2");
- gpio_direction_output(RK29_PIN1_PD4,GPIO_HIGH);
-
- rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_GPIO1D5);
- gpio_request(RK29_PIN1_PD5, "mmc0-data3");
- gpio_direction_output(RK29_PIN1_PD5,GPIO_HIGH);
- }
- break;
- }
-}
-
-static void rk29_sdmmc_set_iomux_mmc1(unsigned int bus_width)
-{
-#if 0
- switch (bus_width)
- {
-
- case 1://SDMMC_CTYPE_4BIT:
- {
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);
- rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_SDMMC1_DATA1);
- rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_SDMMC1_DATA2);
- rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_SDMMC1_DATA3);
- }
- break;
-
- case 0x10000://SDMMC_CTYPE_8BIT:
- break;
- case 0xFFFF:
- {
- rk29_sdmmc_gpio_open(1, 0);
- rk29_sdmmc_gpio_open(1, 1);
- }
- break;
-
- default: //case 0://SDMMC_CTYPE_1BIT:
- {
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);
-
- rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_GPIO1C4);
- gpio_request(RK29_PIN1_PC4, "mmc1-data1");
- gpio_direction_output(RK29_PIN1_PC4,GPIO_HIGH);
-
- rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_GPIO1C5);
- gpio_request(RK29_PIN1_PC5, "mmc1-data2");
- gpio_direction_output(RK29_PIN1_PC5,GPIO_HIGH);
-
- rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_GPIO1C6);
- gpio_request(RK29_PIN1_PC6, "mmc1-data3");
- gpio_direction_output(RK29_PIN1_PC6,GPIO_HIGH);
-
- }
- break;
- }
-#else
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);
- rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_SDMMC1_DATA1);
- rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_SDMMC1_DATA2);
- rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_SDMMC1_DATA3);
-
-#endif
-}
-
-static void rk29_sdmmc_set_iomux_mmc2(unsigned int bus_width)
-{
- ;//
-}
-
-static void rk29_sdmmc_set_iomux(int device_id, unsigned int bus_width)
-{
- switch(device_id)
- {
- case 0:
- #ifdef CONFIG_SDMMC0_RK29
- rk29_sdmmc_set_iomux_mmc0(bus_width);
- #endif
- break;
- case 1:
- #ifdef CONFIG_SDMMC1_RK29
- rk29_sdmmc_set_iomux_mmc1(bus_width);
- #endif
- break;
- case 2:
- rk29_sdmmc_set_iomux_mmc2(bus_width);
- break;
- default:
- break;
- }
-}
-
-#endif
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
-static int rk29sdk_wifi_status(struct device *dev);
-static int rk29sdk_wifi_status_register(void (*callback)(int card_presend, void *dev_id), void *dev_id);
-#endif
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- rk29_mux_api_set(GPIO1D1_SDMMC0CMD_NAME, GPIO1H_SDMMC0_CMD);
- rk29_mux_api_set(GPIO1D0_SDMMC0CLKOUT_NAME, GPIO1H_SDMMC0_CLKOUT);
- rk29_mux_api_set(GPIO1D2_SDMMC0DATA0_NAME, GPIO1H_SDMMC0_DATA0);
- rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_SDMMC0_DATA1);
- rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_SDMMC0_DATA2);
- rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_SDMMC0_DATA3);
-
- rk29_mux_api_set(GPIO2A2_SDMMC0DETECTN_NAME, GPIO2L_GPIO2A2);
-
- rk29_mux_api_set(GPIO5D5_SDMMC0PWREN_NAME, GPIO5H_GPIO5D5); ///GPIO5H_SDMMC0_PWR_EN); ///GPIO5H_GPIO5D5);
- gpio_request(RK29_PIN5_PD5,"sdmmc");
-#if 0
- gpio_set_value(RK29_PIN5_PD5,GPIO_HIGH);
- mdelay(100);
- gpio_set_value(RK29_PIN5_PD5,GPIO_LOW);
-#else
- gpio_direction_output(RK29_PIN5_PD5,GPIO_LOW);
-#endif
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- rk29_mux_api_set(GPIO2A2_SDMMC0DETECTN_NAME, GPIO2L_SDMMC0_DETECT_N);//Modifyed by xbw.
-
- #if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN,"sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
- #endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail = (MMC_VDD_25_26|MMC_VDD_26_27|MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30|
- MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33|
- MMC_VDD_33_34|MMC_VDD_34_35| MMC_VDD_35_36),
- .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
- .detect_irq = RK29_PIN2_PA2, // INVALID_GPIO
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
-#else
- .write_prt = INVALID_GPIO,
-#endif
-};
-#endif
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);
- rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_SDMMC1_DATA1);
- rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_SDMMC1_DATA2);
- rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_SDMMC1_DATA3);
- //rk29_mux_api_set(GPIO1C0_UART0CTSN_SDMMC1DETECTN_NAME, GPIO1H_SDMMC1_DETECT_N);
-
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN,"sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-
-
-#define RK29SDK_WIFI_SDIO_CARD_DETECT_N RK29_PIN1_PD6
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail = (MMC_VDD_25_26|MMC_VDD_26_27|MMC_VDD_27_28|MMC_VDD_28_29|
- MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32|
- MMC_VDD_32_33|MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_SDIO_IRQ|
- MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-#if 0
- .detect_irq = RK29SDK_WIFI_SDIO_CARD_DETECT_N,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
-#else
-//for wifi develop board
- .detect_irq = INVALID_GPIO,
- .enable_sd_wakeup = 0,
-#endif
-
-};
-#endif ////endif--#ifdef CONFIG_SDMMC1_RK29
-
-
-int rk29sdk_wifi_power_state = 0;
-int rk29sdk_bt_power_state = 0;
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
-#define RK29SDK_WIFI_BT_GPIO_POWER_N RK29_PIN5_PD6
-#define RK29SDK_WIFI_GPIO_RESET_N RK29_PIN6_PC0
-#define RK29SDK_BT_GPIO_RESET_N RK29_PIN6_PC7
-
-static int rk29sdk_wifi_cd = 0; /* wifi virtual 'card detect' status */
-static void (*wifi_status_cb)(int card_present, void *dev_id);
-static void *wifi_status_cb_devid;
-
-static int rk29sdk_wifi_status(struct device *dev)
-{
- return rk29sdk_wifi_cd;
-}
-
-static int rk29sdk_wifi_status_register(void (*callback)(int card_present, void *dev_id), void *dev_id)
-{
- if(wifi_status_cb)
- return -EAGAIN;
- wifi_status_cb = callback;
- wifi_status_cb_devid = dev_id;
- return 0;
-}
-
-static int rk29sdk_wifi_bt_gpio_control_init(void)
-{
- if (gpio_request(RK29SDK_WIFI_BT_GPIO_POWER_N, "wifi_bt_power")) {
- pr_info("%s: request wifi_bt power gpio failed\n", __func__);
- return -1;
- }
-
- if (gpio_request(RK29SDK_WIFI_GPIO_RESET_N, "wifi reset")) {
- pr_info("%s: request wifi reset gpio failed\n", __func__);
- gpio_free(RK29SDK_WIFI_BT_GPIO_POWER_N);
- return -1;
- }
-
- if (gpio_request(RK29SDK_BT_GPIO_RESET_N, "bt reset")) {
- pr_info("%s: request bt reset gpio failed\n", __func__);
- gpio_free(RK29SDK_WIFI_GPIO_RESET_N);
- return -1;
- }
-
- gpio_direction_output(RK29SDK_WIFI_BT_GPIO_POWER_N, GPIO_LOW);
- gpio_direction_output(RK29SDK_WIFI_GPIO_RESET_N, GPIO_LOW);
- gpio_direction_output(RK29SDK_BT_GPIO_RESET_N, GPIO_LOW);
-
- #if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
-
- rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_GPIO1C4);
- gpio_request(RK29_PIN1_PC4, "mmc1-data1");
- gpio_direction_output(RK29_PIN1_PC4,GPIO_LOW);//set mmc1-data1 to low.
-
- rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_GPIO1C5);
- gpio_request(RK29_PIN1_PC5, "mmc1-data2");
- gpio_direction_output(RK29_PIN1_PC5,GPIO_LOW);//set mmc1-data2 to low.
-
- rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_GPIO1C6);
- gpio_request(RK29_PIN1_PC6, "mmc1-data3");
- gpio_direction_output(RK29_PIN1_PC6,GPIO_LOW);//set mmc1-data3 to low.
-
- rk29_sdmmc_gpio_open(1, 0); //added by xbw at 2011-10-13
- #endif
- pr_info("%s: init finished\n",__func__);
-
- return 0;
-}
-
-static int rk29sdk_wifi_power(int on)
-{
- pr_info("%s: %d\n", __func__, on);
- if (on){
- gpio_set_value(RK29SDK_WIFI_BT_GPIO_POWER_N, GPIO_HIGH);
-
- #if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
- rk29_sdmmc_gpio_open(1, 1); //added by xbw at 2011-10-13
- #endif
-
- gpio_set_value(RK29SDK_WIFI_GPIO_RESET_N, GPIO_HIGH);
- mdelay(100);
- pr_info("wifi turn on power\n");
- }else{
- if (!rk29sdk_bt_power_state){
- gpio_set_value(RK29SDK_WIFI_BT_GPIO_POWER_N, GPIO_LOW);
-
- #if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
- rk29_sdmmc_gpio_open(1, 0); //added by xbw at 2011-10-13
- #endif
-
- mdelay(100);
- pr_info("wifi shut off power\n");
- }else
- {
- pr_info("wifi shouldn't shut off power, bt is using it!\n");
- }
- gpio_set_value(RK29SDK_WIFI_GPIO_RESET_N, GPIO_LOW);
-
- }
-
- rk29sdk_wifi_power_state = on;
- return 0;
-}
-
-static int rk29sdk_wifi_reset_state;
-static int rk29sdk_wifi_reset(int on)
-{
- pr_info("%s: %d\n", __func__, on);
- gpio_set_value(RK29SDK_WIFI_GPIO_RESET_N, on);
- mdelay(100);
- rk29sdk_wifi_reset_state = on;
- return 0;
-}
-
-int rk29sdk_wifi_set_carddetect(int val)
-{
- pr_info("%s:%d\n", __func__, val);
- rk29sdk_wifi_cd = val;
- if (wifi_status_cb){
- wifi_status_cb(val, wifi_status_cb_devid);
- }else {
- pr_warning("%s, nobody to notify\n", __func__);
- }
- return 0;
-}
-EXPORT_SYMBOL(rk29sdk_wifi_set_carddetect);
-
-static struct wifi_mem_prealloc wifi_mem_array[PREALLOC_WLAN_SEC_NUM] = {
- {NULL, (WLAN_SECTION_SIZE_0 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_1 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_2 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_3 + PREALLOC_WLAN_SECTION_HEADER)}
-};
-
-static void *rk29sdk_mem_prealloc(int section, unsigned long size)
-{
- if (section == PREALLOC_WLAN_SEC_NUM)
- return wlan_static_skb;
-
- if ((section < 0) || (section > PREALLOC_WLAN_SEC_NUM))
- return NULL;
-
- if (wifi_mem_array[section].size < size)
- return NULL;
-
- return wifi_mem_array[section].mem_ptr;
-}
-
-int __init rk29sdk_init_wifi_mem(void)
-{
- int i;
- int j;
-
- for (i = 0 ; i < WLAN_SKB_BUF_NUM ; i++) {
- wlan_static_skb[i] = dev_alloc_skb(
- ((i < (WLAN_SKB_BUF_NUM / 2)) ? 4096 : 8192));
-
- if (!wlan_static_skb[i])
- goto err_skb_alloc;
- }
-
- for (i = 0 ; i < PREALLOC_WLAN_SEC_NUM ; i++) {
- wifi_mem_array[i].mem_ptr =
- kmalloc(wifi_mem_array[i].size, GFP_KERNEL);
-
- if (!wifi_mem_array[i].mem_ptr)
- goto err_mem_alloc;
- }
- return 0;
-
-err_mem_alloc:
- pr_err("Failed to mem_alloc for WLAN\n");
- for (j = 0 ; j < i ; j++)
- kfree(wifi_mem_array[j].mem_ptr);
-
- i = WLAN_SKB_BUF_NUM;
-
-err_skb_alloc:
- pr_err("Failed to skb_alloc for WLAN\n");
- for (j = 0 ; j < i ; j++)
- dev_kfree_skb(wlan_static_skb[j]);
-
- return -ENOMEM;
-}
-
-static struct wifi_platform_data rk29sdk_wifi_control = {
- .set_power = rk29sdk_wifi_power,
- .set_reset = rk29sdk_wifi_reset,
- .set_carddetect = rk29sdk_wifi_set_carddetect,
- .mem_prealloc = rk29sdk_mem_prealloc,
-};
-static struct platform_device rk29sdk_wifi_device = {
- .name = "bcm4329_wlan",
- .id = 1,
- .dev = {
- .platform_data = &rk29sdk_wifi_control,
- },
-};
-#endif
-
-
-/* bluetooth rfkill device */
-static struct platform_device rk29sdk_rfkill = {
- .name = "rk29sdk_rfkill",
- .id = -1,
-};
-
-
-#ifdef CONFIG_VIVANTE
-static struct resource resources_gpu[] = {
- [0] = {
- .name = "gpu_irq",
- .start = IRQ_GPU,
- .end = IRQ_GPU,
- .flags = IORESOURCE_IRQ,
- },
- [1] = {
- .name = "gpu_base",
- .start = RK29_GPU_PHYS,
- .end = RK29_GPU_PHYS + RK29_GPU_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "gpu_mem",
- .start = PMEM_GPU_BASE,
- .end = PMEM_GPU_BASE + PMEM_GPU_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-static struct platform_device rk29_device_gpu = {
- .name = "galcore",
- .id = 0,
- .num_resources = ARRAY_SIZE(resources_gpu),
- .resource = resources_gpu,
-};
-#endif
-#ifdef CONFIG_KEYS_RK29
-extern struct rk29_keys_platform_data rk29_keys_pdata;
-static struct platform_device rk29_device_keys = {
- .name = "rk29-keypad",
- .id = -1,
- .dev = {
- .platform_data = &rk29_keys_pdata,
- },
-};
-#endif
-
-#if CONFIG_ANDROID_TIMED_GPIO
-static struct timed_gpio timed_gpios[] = {
- {
- .name = "vibrator",
- .gpio = RK29_PIN1_PB5,
- .max_timeout = 1000,
- .active_low = 0,
- .adjust_time =20, //adjust for diff product
- },
-};
-
-struct timed_gpio_platform_data rk29_vibrator_info = {
- .num_gpios = 1,
- .gpios = timed_gpios,
-};
-
-struct platform_device rk29_device_vibrator ={
- .name = "timed-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_vibrator_info,
- },
-
-};
-#endif
-
-static void __init rk29_board_iomux_init(void)
-{
- int err;
-
-#ifdef CONFIG_UART1_RK29
- //disable uart1 pull down
- rk29_mux_api_set(GPIO2A5_UART1SOUT_NAME, GPIO2L_GPIO2A5);
- rk29_mux_api_set(GPIO2A4_UART1SIN_NAME, GPIO2L_GPIO2A4);
-
- gpio_request(RK29_PIN2_PA5, NULL);
- gpio_request(RK29_PIN2_PA4, NULL);
-
- gpio_pull_updown(RK29_PIN2_PA5, PullDisable);
- gpio_pull_updown(RK29_PIN2_PA4, PullDisable);
-
- rk29_mux_api_set(GPIO2A5_UART1SOUT_NAME, GPIO2L_UART1_SOUT);
- rk29_mux_api_set(GPIO2A4_UART1SIN_NAME, GPIO2L_UART1_SIN);
-
- gpio_free(RK29_PIN2_PA5);
- gpio_free(RK29_PIN2_PA4);
-#endif
-
- #if CONFIG_ANDROID_TIMED_GPIO
- rk29_mux_api_set(GPIO1B5_PWM0_NAME, GPIO1L_GPIO1B5);//for timed gpio
- #endif
- #ifdef CONFIG_RK29_PWM_REGULATOR
- rk29_mux_api_set(REGULATOR_PWM_MUX_NAME,REGULATOR_PWM_MUX_MODE);
- #endif
- #ifdef CONFIG_RK_HEADSET_DET
- rk29_mux_api_set(GPIO3A6_SMCADDR14_HOSTDATA14_NAME,GPIO3L_GPIO3A6);
- #endif
-
- rk29_mux_api_set(GPIO4C0_RMIICLKOUT_RMIICLKIN_NAME,GPIO4H_GPIO4C0);
-
- err = gpio_request(RK29_PIN4_PC0, "clk27M_control");
- if (err) {
- gpio_free(RK29_PIN4_PC0);
- printk("-------request RK29_PIN4_PC0 fail--------\n");
- return -1;
- }
- //phy power down
-
- #if defined (CONFIG_RK29_WORKING_POWER_MANAGEMENT)
- gpio_direction_output(RK29_PIN4_PC0, GPIO_HIGH);
- gpio_set_value(RK29_PIN4_PC0, GPIO_HIGH);
- #else
- gpio_direction_output(RK29_PIN4_PC0, GPIO_LOW);
- gpio_set_value(RK29_PIN4_PC0, GPIO_LOW);
- #endif
-
- rk29_mux_api_set(GPIO4C5_RMIICSRDVALID_MIIRXDVALID_NAME,GPIO4H_GPIO4C5);
-
- err = gpio_request(RK29_PIN4_PC5, "clk24M_control");
- if (err) {
- gpio_free(RK29_PIN4_PC5);
- printk("-------request RK29_PIN4_PC5 fail--------\n");
- return -1;
- }
- //phy power down
- gpio_direction_output(RK29_PIN4_PC5, GPIO_LOW);
- gpio_set_value(RK29_PIN4_PC5, GPIO_LOW);
-}
-
-// For phone,just a disk only, add by phc,20110816
-#ifdef CONFIG_USB_ANDROID
-struct usb_mass_storage_platform_data phone_mass_storage_pdata = {
- .nluns = 1,
- .vendor = "RockChip",
- .product = "rk29 sdk",
- .release = 0x0100,
-};
-
-//static
-struct platform_device phone_usb_mass_storage_device = {
- .name = "usb_mass_storage",
- .id = -1,
- .dev = {
- .platform_data = &phone_mass_storage_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_RK29_CHARGE_EARLYSUSPEND
-
-struct platform_device charge_lowerpower_device = {
- .name = "charge_lowerpower",
- .id = -1,
-};
-#endif
-
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_UART1_RK29
- &rk29_device_uart1,
-#endif
-#ifdef CONFIG_UART0_RK29
- &rk29_device_uart0,
-#endif
-#ifdef CONFIG_UART2_RK29
- &rk29_device_uart2,
-#endif
-#ifdef CONFIG_UART3_RK29
- &rk29_device_uart3,
-#endif
-
-#ifdef CONFIG_RK29_PWM_REGULATOR
- &rk29_device_pwm_regulator,
-#endif
-#ifdef CONFIG_SPIM0_RK29
- &rk29xx_device_spi0m,
-#endif
-#ifdef CONFIG_SPIM1_RK29
- &rk29xx_device_spi1m,
-#endif
-#ifdef CONFIG_ADC_RK29
- &rk29_device_adc,
-#endif
-#ifdef CONFIG_I2C0_RK29
- &rk29_device_i2c0,
-#endif
-#ifdef CONFIG_I2C1_RK29
- &rk29_device_i2c1,
-#endif
-#ifdef CONFIG_I2C2_RK29
- &rk29_device_i2c2,
-#endif
-#ifdef CONFIG_I2C3_RK29
- &rk29_device_i2c3,
-#endif
-
-#ifdef CONFIG_MFD_WM8994
- &wm8994_fixed_voltage0,
- &wm8994_fixed_voltage1,
-#endif
-
-#ifdef CONFIG_SND_RK29_SOC_I2S_2CH
- &rk29_device_iis_2ch,
-#endif
-#ifdef CONFIG_SND_RK29_SOC_I2S_8CH
- &rk29_device_iis_8ch,
-#endif
-
-#ifdef CONFIG_KEYS_RK29
- &rk29_device_keys,
-#endif
-#ifdef CONFIG_SDMMC0_RK29
- &rk29_device_sdmmc0,
-#endif
-#ifdef CONFIG_SDMMC1_RK29
- &rk29_device_sdmmc1,
-#endif
-
-#ifdef CONFIG_MTD_NAND_RK29XX
- &rk29xx_device_nand,
-#endif
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- &rk29sdk_wifi_device,
-#endif
-
-#ifdef CONFIG_BT
- &rk29sdk_rfkill,
-#endif
-
-#if defined(CONFIG_MTK23D)
- &rk2818_device_mtk23d,
-#endif
-
-#ifdef CONFIG_MTD_NAND_RK29
- &rk29_device_nand,
-#endif
-
-#ifdef CONFIG_FB_RK29
- &rk29_device_fb,
- &rk29_device_dma_cpy,
-#endif
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- &rk29_device_backlight,
-#endif
-#ifdef CONFIG_RK29_VMAC
- &rk29_device_vmac,
-#endif
-#ifdef CONFIG_VIVANTE
- &rk29_device_gpu,
-#endif
-#ifdef CONFIG_VIDEO_RK29
- &rk29_device_camera, /* ddl@rock-chips.com : camera support */
- #if (CONFIG_SENSOR_IIC_ADDR_0 != 0x00)
- &rk29_soc_camera_pdrv_0,
- #endif
- &rk29_soc_camera_pdrv_1,
- &android_pmem_cam_device,
-#endif
- &android_pmem_device,
- &rk29_vpu_mem_device,
-#ifdef CONFIG_USB20_OTG
- &rk29_device_usb20_otg,
-#endif
-#ifdef CONFIG_USB20_HOST
- &rk29_device_usb20_host,
-#endif
-#ifdef CONFIG_USB11_HOST
- &rk29_device_usb11_host,
-#endif
-#ifdef CONFIG_USB_ANDROID
- &android_usb_device,
- &phone_usb_mass_storage_device,
-#endif
-#ifdef CONFIG_RK29_IPP
- &rk29_device_ipp,
-#endif
-#ifdef CONFIG_VIDEO_RK29XX_VOUT
- &rk29_v4l2_output_devce,
-#endif
-#ifdef CONFIG_RK_HEADSET_DET
- &rk_device_headset,
-#endif
-#ifdef CONFIG_RK29_GPS
- &rk29_device_gps,
-#endif
-#ifdef CONFIG_ANDROID_TIMED_GPIO
- &rk29_device_vibrator,
-#endif
-};
-
-#ifdef CONFIG_RK29_VMAC
-/*****************************************************************************************
- * vmac devices
- * author: lyx@rock-chips.com
- *****************************************************************************************/
-static int rk29_vmac_register_set(void)
-{
- //config rk29 vmac as rmii, 100MHz
- u32 value= readl(RK29_GRF_BASE + 0xbc);
- value = (value & 0xfff7ff) | (0x400);
- writel(value, RK29_GRF_BASE + 0xbc);
- return 0;
-}
-
-static int rk29_rmii_io_init(void)
-{
- int err;
-
- //phy power gpio
- err = gpio_request(RK29_PIN6_PB0, "phy_power_en");
- if (err) {
- gpio_free(RK29_PIN6_PB0);
- printk("-------request RK29_PIN6_PB0 fail--------\n");
- return -1;
- }
- //phy power down
- gpio_direction_output(RK29_PIN6_PB0, GPIO_LOW);
- gpio_set_value(RK29_PIN6_PB0, GPIO_LOW);
-
- return 0;
-}
-
-static int rk29_rmii_io_deinit(void)
-{
- //phy power down
- gpio_direction_output(RK29_PIN6_PB0, GPIO_LOW);
- gpio_set_value(RK29_PIN6_PB0, GPIO_LOW);
- //free
- gpio_free(RK29_PIN6_PB0);
- return 0;
-}
-
-static int rk29_rmii_power_control(int enable)
-{
- if (enable) {
- //enable phy power
- gpio_direction_output(RK29_PIN6_PB0, GPIO_HIGH);
- gpio_set_value(RK29_PIN6_PB0, GPIO_HIGH);
- }
- else {
- gpio_direction_output(RK29_PIN6_PB0, GPIO_LOW);
- gpio_set_value(RK29_PIN6_PB0, GPIO_LOW);
- }
- return 0;
-}
-
-struct rk29_vmac_platform_data rk29_vmac_pdata = {
- .vmac_register_set = rk29_vmac_register_set,
- .rmii_io_init = rk29_rmii_io_init,
- .rmii_io_deinit = rk29_rmii_io_deinit,
- .rmii_power_control = rk29_rmii_power_control,
-};
-#endif
-
-/*****************************************************************************************
- * spi devices
- * author: cmc@rock-chips.com
- *****************************************************************************************/
-#define SPI_CHIPSELECT_NUM 2
-static struct spi_cs_gpio rk29xx_spi0_cs_gpios[SPI_CHIPSELECT_NUM] = {
- {
- .name = "spi0 cs0",
- .cs_gpio = RK29_PIN2_PC1,
- .cs_iomux_name = GPIO2C1_SPI0CSN0_NAME,
- .cs_iomux_mode = GPIO2H_SPI0_CSN0,
- },
- {
- .name = "spi0 cs1",
- .cs_gpio = RK29_PIN1_PA4,
- .cs_iomux_name = GPIO1A4_EMMCWRITEPRT_SPI0CS1_NAME,//if no iomux,set it NULL
- .cs_iomux_mode = GPIO1L_SPI0_CSN1,
- }
-};
-
-static struct spi_cs_gpio rk29xx_spi1_cs_gpios[SPI_CHIPSELECT_NUM] = {
- {
- .name = "spi1 cs0",
- .cs_gpio = RK29_PIN2_PC5,
- .cs_iomux_name = GPIO2C5_SPI1CSN0_NAME,
- .cs_iomux_mode = GPIO2H_SPI1_CSN0,
- },
- {
- .name = "spi1 cs1",
- .cs_gpio = RK29_PIN1_PA3,
- .cs_iomux_name = GPIO1A3_EMMCDETECTN_SPI1CS1_NAME,//if no iomux,set it NULL
- .cs_iomux_mode = GPIO1L_SPI1_CSN1,
- }
-};
-
-static int spi_io_init(struct spi_cs_gpio *cs_gpios, int cs_num)
-{
-#if 1
- int i;
- if (cs_gpios) {
- for (i=0; i<cs_num; i++) {
- rk29_mux_api_set(cs_gpios[i].cs_iomux_name, cs_gpios[i].cs_iomux_mode);
- }
- }
-#endif
- return 0;
-}
-
-static int spi_io_deinit(struct spi_cs_gpio *cs_gpios, int cs_num)
-{
- return 0;
-}
-
-static int spi_io_fix_leakage_bug(void)
-{
-#if 0
- gpio_direction_output(RK29_PIN2_PC1, GPIO_LOW);
-#endif
- return 0;
-}
-
-static int spi_io_resume_leakage_bug(void)
-{
-#if 0
- gpio_direction_output(RK29_PIN2_PC1, GPIO_HIGH);
-#endif
- return 0;
-}
-
-struct rk29xx_spi_platform_data rk29xx_spi0_platdata = {
- .num_chipselect = SPI_CHIPSELECT_NUM,
- .chipselect_gpios = rk29xx_spi0_cs_gpios,
- .io_init = spi_io_init,
- .io_deinit = spi_io_deinit,
- .io_fix_leakage_bug = spi_io_fix_leakage_bug,
- .io_resume_leakage_bug = spi_io_resume_leakage_bug,
-};
-
-struct rk29xx_spi_platform_data rk29xx_spi1_platdata = {
- .num_chipselect = SPI_CHIPSELECT_NUM,
- .chipselect_gpios = rk29xx_spi1_cs_gpios,
- .io_init = spi_io_init,
- .io_deinit = spi_io_deinit,
- .io_fix_leakage_bug = spi_io_fix_leakage_bug,
- .io_resume_leakage_bug = spi_io_resume_leakage_bug,
-};
-
-
-/*****************************************************************************************
- * xpt2046 touch panel
- * author: hhb@rock-chips.com
- *****************************************************************************************/
-#if defined(CONFIG_TOUCHSCREEN_XPT2046_NORMAL_SPI) || defined(CONFIG_TOUCHSCREEN_XPT2046_TSLIB_SPI)
-#define XPT2046_GPIO_INT RK29_PIN4_PD5 //中断???#define DEBOUNCE_REPTIME 3
-
-static struct xpt2046_platform_data xpt2046_info = {
- .model = 2046,
- .keep_vref_on = 1,
- .swap_xy = 0,
- .debounce_max = 7,
- .debounce_rep = DEBOUNCE_REPTIME,
- .debounce_tol = 20,
- .gpio_pendown = XPT2046_GPIO_INT,
- .pendown_iomux_name = GPIO4D5_CPUTRACECTL_NAME,
- .pendown_iomux_mode = GPIO4H_GPIO4D5,
- .touch_virtualkey_length = 60,
- .penirq_recheck_delay_usecs = 1,
-#if defined(CONFIG_TOUCHSCREEN_480X800)
- .x_min = 0,
- .x_max = 480,
- .y_min = 0,
- .y_max = 800,
- .touch_ad_top = 3940,
- .touch_ad_bottom = 310,
- .touch_ad_left = 3772,
- .touch_ad_right = 340,
-#elif defined(CONFIG_TOUCHSCREEN_800X480)
- .x_min = 0,
- .x_max = 800,
- .y_min = 0,
- .y_max = 480,
- .touch_ad_top = 2447,
- .touch_ad_bottom = 207,
- .touch_ad_left = 5938,
- .touch_ad_right = 153,
-#elif defined(CONFIG_TOUCHSCREEN_320X480)
- .x_min = 0,
- .x_max = 320,
- .y_min = 0,
- .y_max = 480,
- .touch_ad_top = 3166,
- .touch_ad_bottom = 256,
- .touch_ad_left = 3658,
- .touch_ad_right = 380,
-#endif
-};
-#elif defined(CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI)
-static struct xpt2046_platform_data xpt2046_info = {
- .model = 2046,
- .keep_vref_on = 1,
- .swap_xy = 0,
- .debounce_max = 7,
- .debounce_rep = DEBOUNCE_REPTIME,
- .debounce_tol = 20,
- .gpio_pendown = XPT2046_GPIO_INT,
- .pendown_iomux_name = GPIO4D5_CPUTRACECTL_NAME,
- .pendown_iomux_mode = GPIO4H_GPIO4D5,
- .touch_virtualkey_length = 60,
- .penirq_recheck_delay_usecs = 1,
-
-#if defined(CONFIG_TOUCHSCREEN_480X800)
- .x_min = 0,
- .x_max = 480,
- .y_min = 0,
- .y_max = 800,
- .screen_x = { 70, 410, 70, 410, 240},
- .screen_y = { 50, 50, 740, 740, 400},
- .uncali_x_default = { 3267, 831, 3139, 715, 1845 },
- .uncali_y_default = { 3638, 3664, 564, 591, 2087 },
-#elif defined(CONFIG_TOUCHSCREEN_800X480)
- .x_min = 0,
- .x_max = 800,
- .y_min = 0,
- .y_max = 480,
- .screen_x[5] = { 50, 750, 50, 750, 400};
- .screen_y[5] = { 40, 40, 440, 440, 240};
- .uncali_x_default[5] = { 438, 565, 3507, 3631, 2105 };
- .uncali_y_default[5] = { 3756, 489, 3792, 534, 2159 };
-#elif defined(CONFIG_TOUCHSCREEN_320X480)
- .x_min = 0,
- .x_max = 320,
- .y_min = 0,
- .y_max = 480,
- .screen_x[5] = { 50, 270, 50, 270, 160};
- .screen_y[5] = { 40, 40, 440, 440, 240};
- .uncali_x_default[5] = { 812, 3341, 851, 3371, 2183 };
- .uncali_y_default[5] = { 442, 435, 3193, 3195, 2004 };
-#endif
-};
-#endif
-
-static struct spi_board_info board_spi_devices[] = {
-#if defined(CONFIG_TOUCHSCREEN_XPT2046_SPI)
- {
- .modalias = "xpt2046_ts",
- .chip_select = 0,// 2,
- .max_speed_hz = 125 * 1000 * 26,/* (max sample rate @ 3V) * (cmd + data + overhead) */
- .bus_num = 0,
- .irq = XPT2046_GPIO_INT,
- .platform_data = &xpt2046_info,
- },
-#endif
-
-#if defined(CONFIG_MFD_WM831X_SPI)
- {
- .modalias = "wm8310",
- .chip_select = 1,
- .max_speed_hz = 2*1000*1000,
- .bus_num = 1,
- .irq = RK29_PIN4_PD0,
- .platform_data = &wm831x_platdata,
- },
-#endif
-
-};
-
-
-/**********************************************************************************************
- *
- * The virtual keys for android "back", "home", "menu", "search", these four keys are touch key
- * on the touch screen panel. (added by hhb@rock-chips.com 2011.03.31)
- *
- ***********************************************************************************************/
-static ssize_t rk29xx_virtual_keys_show(struct kobject *kobj,
- struct kobj_attribute *attr, char *buf)
-{
-#if (defined(CONFIG_TOUCHSCREEN_XPT2046_SPI) && defined(CONFIG_TOUCHSCREEN_480X800)) \
- || defined(CONFIG_TOUCHSCREEN_HX8520_IIC) || defined(CONFIG_TOUCHSCREEN_GT801_IIC) \
- || defined (CONFIG_TOUCHSCREEN_GT801_Z5)
- /* center: x: home: 50, menu: 184, back: 315, search 435, y: 830*/
- /* centerx;centery;width;height; */
- return sprintf(buf,
- __stringify(EV_KEY) ":" __stringify(KEY_BACK) ":300:860:120:60"//":315:815:120:50" //":50:830:98:50" //":210:796:98:50"
- ":" __stringify(EV_KEY) ":" __stringify(KEY_MENU) ":60:860:120:60"//":85:815:88:50" // ":184:830:120:50" // ":435:796:120:50"
- ":" __stringify(EV_KEY) ":" __stringify(KEY_HOMEPAGE) ":180:860:120:60"//":184:815:100:50" //":315:830:100:50" //":320:796:100:50"
- ":" __stringify(EV_KEY) ":" __stringify(KEY_SEARCH) ":420:860:120:60"//":435:815:88:50" //":50:815:98:50" // //":85:796:88:50"
- "\n");
-
-#elif defined (CONFIG_TOUCHSCREEN_FT5306)
- return sprintf(buf,
- __stringify(EV_KEY) ":" __stringify(KEY_BACK) ":400:830:120:60"//":315:815:120:50" //":50:830:98:50" //":210:796:98:50"
- ":" __stringify(EV_KEY) ":" __stringify(KEY_MENU) ":80:830:120:60"//":85:815:88:50" // ":184:830:120:50" // ":435:796:120:50"
- ":" __stringify(EV_KEY) ":" __stringify(KEY_HOMEPAGE) ":240:830:120:60"//":184:815:100:50" //":315:830:100:50" //":320:796:100:50"
- "\n");
-#endif
- return 0;
-}
-
-static struct kobj_attribute rk29xx_virtual_keys_attr = {
- .attr = {
-#if defined(CONFIG_TOUCHSCREEN_XPT2046_SPI)
- .name = "virtualkeys.xpt2046-touchscreen",
-#elif defined(CONFIG_TOUCHSCREEN_HX8520_IIC)
- .name = "virtualkeys.hx8520-touchscreen",
-#elif defined(CONFIG_TOUCHSCREEN_GT801_IIC) || defined (CONFIG_TOUCHSCREEN_GT801_Z5)
- .name = "virtualkeys.gt801-touchscreen",
-#elif defined(CONFIG_TOUCHSCREEN_ILI2102_IIC)
- .name = "virtualkeys.ili2102-touchscreen",
-#elif defined (CONFIG_TOUCHSCREEN_FT5306)
- .name = "virtualkeys.ft5x0x_ts-touchscreen",
-#else
- .name = "virtualkeys",
-#endif
- .mode = S_IRUGO,
- },
- .show = &rk29xx_virtual_keys_show,
-};
-
-static struct attribute *rk29xx_properties_attrs[] = {
- &rk29xx_virtual_keys_attr.attr,
- NULL
-};
-
-static struct attribute_group rk29xx_properties_attr_group = {
- .attrs = rk29xx_properties_attrs,
-};
-static int rk29xx_virtual_keys_init(void)
-{
- int ret;
- struct kobject *properties_kobj;
- printk("rk29xx_virtual_keys_init \n");
- properties_kobj = kobject_create_and_add("board_properties", NULL);
- if (properties_kobj)
- ret = sysfs_create_group(properties_kobj,
- &rk29xx_properties_attr_group);
- if (!properties_kobj || ret)
- {
- pr_err("failed to create board_properties\n");
- }
- return ret;
-}
-
-
-static void __init rk29_gic_init_irq(void)
-{
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38))
- gic_init(0, 32, (void __iomem *)RK29_GICPERI_BASE, (void __iomem *)RK29_GICCPU_BASE);
-#else
- gic_dist_init(0, (void __iomem *)RK29_GICPERI_BASE, 32);
- gic_cpu_init(0, (void __iomem *)RK29_GICCPU_BASE);
-#endif
-}
-
-static void __init machine_rk29_init_irq(void)
-{
- rk29_gic_init_irq();
- rk29_gpio_init();
-}
-
-#define POWER_ON_PIN RK29_PIN4_PA4
-
-static void rk29_pm_power_restart(void)
-{
- printk("%s,line=%d\n",__FUNCTION__,__LINE__);
- mdelay(2);
-#if defined(CONFIG_MFD_WM831X)
- wm831x_device_restart(gWm831x);
-#endif
-
-}
-
-static void rk29_pm_power_off(void)
-{
- printk(KERN_ERR "rk29_pm_power_off start...\n");
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
-#if defined(CONFIG_MFD_WM831X)
- if(wm831x_read_usb(gWm831x))
- rk29_pm_power_restart(); //if charging then restart
- else
- wm831x_device_shutdown(gWm831x);//else shutdown
-#endif
- while (1);
-}
-
-
-static struct cpufreq_frequency_table freq_table[] =
-{
- { .index = 1100000, .frequency = 408000 },
- { .index = 1150000, .frequency = 600000 },
- { .index = 1200000, .frequency = 816000 },
- { .index = 1300000, .frequency = 1008000 },
- { .frequency = CPUFREQ_TABLE_END },
-};
-
-static void __init machine_rk29_board_init(void)
-{
- rk29_board_iomux_init();
-
- gpio_request(POWER_ON_PIN,"poweronpin");
- gpio_set_value(POWER_ON_PIN, GPIO_HIGH);
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
- pm_power_off = rk29_pm_power_off;
- //arm_pm_restart = rk29_pm_power_restart;
-
- board_update_cpufreq_table(freq_table);
-
- platform_add_devices(devices, ARRAY_SIZE(devices));
-#ifdef CONFIG_I2C0_RK29
- i2c_register_board_info(default_i2c0_data.bus_num, board_i2c0_devices,
- ARRAY_SIZE(board_i2c0_devices));
-#endif
-#ifdef CONFIG_I2C1_RK29
- i2c_register_board_info(default_i2c1_data.bus_num, board_i2c1_devices,
- ARRAY_SIZE(board_i2c1_devices));
-#endif
-#ifdef CONFIG_I2C2_RK29
- i2c_register_board_info(default_i2c2_data.bus_num, board_i2c2_devices,
- ARRAY_SIZE(board_i2c2_devices));
-#endif
-#ifdef CONFIG_I2C3_RK29
- i2c_register_board_info(default_i2c3_data.bus_num, board_i2c3_devices,
- ARRAY_SIZE(board_i2c3_devices));
-#endif
-
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- rk29sdk_wifi_bt_gpio_control_init();
- rk29sdk_init_wifi_mem();
-#endif
-
-#if (defined(CONFIG_TOUCHSCREEN_XPT2046_SPI) && defined(CONFIG_TOUCHSCREEN_480X800)) \
- || defined(CONFIG_TOUCHSCREEN_HX8520_IIC) || defined(CONFIG_TOUCHSCREEN_GT801_IIC) \
- || defined (CONFIG_TOUCHSCREEN_GT801_Z5) || defined (CONFIG_TOUCHSCREEN_FT5306)
- rk29xx_virtual_keys_init();
-#endif
-
-}
-
-static void __init machine_rk29_fixup(struct machine_desc *desc, struct tag *tags,
- char **cmdline, struct meminfo *mi)
-{
- mi->nr_banks = 1;
- mi->bank[0].start = RK29_SDRAM_PHYS;
- mi->bank[0].size = LINUX_SIZE;
-#if SDRAM_SIZE > SZ_512M
- mi->nr_banks = 2;
- mi->bank[1].start = RK29_SDRAM_PHYS + SZ_512M;
- mi->bank[1].size = SDRAM_SIZE - SZ_512M;
-#endif
-}
-
-static void __init machine_rk29_mapio(void)
-{
- rk29_map_common_io();
- rk29_setup_early_printk();
- rk29_sram_init();
- rk29_clock_init2(periph_pll_96mhz, codec_pll_300mhz, false);
- rk29_iomux_init();
- ddr_init(DDR_TYPE, DDR_FREQ);
-}
-
-MACHINE_START(RK29, "RK29board")
- /* UART for LL DEBUG */
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 37))
- /* UART for LL DEBUG */
- .phys_io = RK29_UART1_PHYS & 0xfff00000,
- .io_pg_offst = ((RK29_UART1_BASE) >> 18) & 0xfffc,
-#endif
- .boot_params = RK29_SDRAM_PHYS + 0x88000,
- .fixup = machine_rk29_fixup,
- .map_io = machine_rk29_mapio,
- .init_irq = machine_rk29_init_irq,
- .init_machine = machine_rk29_board_init,
- .timer = &rk29_timer,
-MACHINE_END
+++ /dev/null
-#include <mach/key.h>
-#include <mach/gpio.h>
-#include <mach/board.h>
-
-#define EV_ENCALL KEY_F4
-#define EV_MENU KEY_F1
-
-#define PRESS_LEV_LOW 1
-#define PRESS_LEV_HIGH 0
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "menu",
- .code = EV_MENU,
- .gpio = RK29_PIN6_PA4,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .gpio = RK29_PIN6_PA1,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .gpio = RK29_PIN6_PA2,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .gpio = RK29_PIN6_PA3,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .gpio = RK29_PIN6_PA0,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "sensor",
- .code = KEY_CAMERA,
- .gpio = RK29_PIN6_PA6,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK29_PIN6_PA7,
- .active_low = PRESS_LEV_LOW,
- //.code_long_press = EV_ENCALL,
- .wakeup = 1,
- },
-#if 0
- {
- .desc = "vol+",
- .code = KEY_VOLUMEDOWN,
- .adc_value = 95,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEUP,
- .adc_value = 249,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "menu",
- .code = EV_MENU,
- .adc_value = 406,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .code_long_press = KEY_F4,
- .adc_value = 561,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_ESC,
- .adc_value = 726,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "adkey6",
- .code = KEY_BACK,
- .code_long_press = EV_ENCALL,
- .adc_value = 899,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-#endif
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = -1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
+++ /dev/null
-#include <mach/key.h>
-#include <mach/gpio.h>
-#include <mach/board.h>
-
-#define EV_ENCALL KEY_F4
-#define EV_MENU KEY_F1
-
-#define PRESS_LEV_LOW 1
-#define PRESS_LEV_HIGH 0
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "menu",
- .code = EV_MENU,
- .gpio = RK29_PIN6_PA0,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .gpio = RK29_PIN6_PA1,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .gpio = RK29_PIN6_PA2,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .gpio = RK29_PIN6_PA3,
- .active_low = PRESS_LEV_LOW,
- },
- //{
- // .desc = "search",
- // .code = KEY_SEARCH,
- // .gpio = RK29_PIN6_PA4,
- // .active_low = PRESS_LEV_LOW,
- //},
- {
- .desc = "esc",
- .code = KEY_BACK,
- .gpio = RK29_PIN6_PA5,
- .active_low = PRESS_LEV_LOW,
- },
- //{
- // .desc = "sensor",
- // .code = KEY_CAMERA,
- // .gpio = RK29_PIN6_PA6,
- // .active_low = PRESS_LEV_LOW,
- //},
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK29_PIN6_PA7,
- .active_low = PRESS_LEV_LOW,
- //.code_long_press = EV_ENCALL,
- .wakeup = 1,
- },
-#if 0
- {
- .desc = "vol+",
- .code = KEY_VOLUMEDOWN,
- .adc_value = 95,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEUP,
- .adc_value = 249,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "menu",
- .code = EV_MENU,
- .adc_value = 406,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .code_long_press = KEY_F4,
- .adc_value = 561,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_ESC,
- .adc_value = 726,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "adkey6",
- .code = KEY_BACK,
- .code_long_press = EV_ENCALL,
- .adc_value = 899,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-#endif
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = -1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
+++ /dev/null
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/pm.h>
-
-#include <mach/rk29_iomap.h>
-#include <mach/gpio.h>
-#include <mach/cru.h>
-
-#define POWER_ON_PIN RK29_PIN4_PA4
-#define PLAY_ON_PIN RK29_PIN6_PA7
-
-static void rk29_pm_power_off(void)
-{
- int count = 0;
-
- local_irq_disable();
- local_fiq_disable();
-
- printk(KERN_ERR "rk29_pm_power_off start...\n");
-
- /* arm enter slow mode */
- cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_SLOW, CRU_MODE_CON);
- LOOP(LOOPS_PER_USEC);
-
- while (1) {
- /* shut down the power by GPIO. */
- if (gpio_get_value(POWER_ON_PIN) == GPIO_HIGH) {
- printk("POWER_ON_PIN is high\n");
- gpio_set_value(POWER_ON_PIN, GPIO_LOW);
- }
-
- LOOP(5 * LOOPS_PER_MSEC);
-
- /* only normal power off can restart system safely */
- if (system_state != SYSTEM_POWER_OFF)
- continue;
-
- if (gpio_get_value(PLAY_ON_PIN) != GPIO_HIGH) {
- if (!count)
- printk("PLAY_ON_PIN is low\n");
- if (50 == count) /* break if keep low about 250ms */
- break;
- count++;
- } else {
- count = 0;
- }
- }
-
- printk("system reboot\n");
- gpio_set_value(POWER_ON_PIN, GPIO_HIGH);
- system_state = SYSTEM_RESTART;
- arm_pm_restart(0, NULL);
-
- while (1);
-}
-
-int __init board_power_init(void)
-{
- gpio_request(POWER_ON_PIN, "poweronpin");
- gpio_set_value(POWER_ON_PIN, GPIO_HIGH);
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
- pm_power_off = rk29_pm_power_off;
-
- return 0;
-}
-
+++ /dev/null
-/*
- * Copyright (C) 2010 ROCKCHIP, Inc.
- * Author: roger_chen <cz@rock-chips.com>
- *
- * This program is the bluetooth device bcm4329's driver,
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/module.h>
-#include <linux/device.h>
-#include <linux/rfkill.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/interrupt.h>
-#include <linux/wakelock.h>
-#include <linux/fs.h>
-#include <asm/uaccess.h>
-#include <mach/gpio.h>
-#include <asm/irq.h>
-#include <mach/iomux.h>
-#include <linux/wakelock.h>
-#include <linux/timer.h>
-
-#if 0
-#define DBG(x...) printk(KERN_INFO x)
-#else
-#define DBG(x...)
-#endif
-
-#define BT_WAKE_HOST_SUPPORT 0
-
-struct bt_ctrl
-{
- struct rfkill *bt_rfk;
-#if BT_WAKE_HOST_SUPPORT
- struct timer_list tl;
- bool b_HostWake;
- struct wake_lock bt_wakelock;
-#endif
-};
-
-#define BT_GPIO_POWER RK29_PIN5_PD6
-#define IOMUX_BT_GPIO_POWER rk29_mux_api_set(GPIO5D6_SDMMC1PWREN_NAME, GPIO5H_GPIO5D6);
-#define BT_GPIO_RESET RK29_PIN6_PC4
-#define BT_GPIO_WAKE_UP RK29_PIN6_PC5
-#define BT_GPIO_WAKE_UP_HOST //RK2818_PIN_PA7
-#define IOMUX_BT_GPIO_WAKE_UP_HOST() //rk2818_mux_api_set(GPIOA7_FLASHCS3_SEL_NAME,0);
-
-#define BT_WAKE_LOCK_TIMEOUT 10 //s
-
-static const char bt_name[] = "bcm4329";
-extern int rk29sdk_bt_power_state;
-extern int rk29sdk_wifi_power_state;
-
-struct bt_ctrl gBtCtrl;
-
-#if BT_WAKE_HOST_SUPPORT
-void resetBtHostSleepTimer(void)
-{
- mod_timer(&(gBtCtrl.tl),jiffies + BT_WAKE_LOCK_TIMEOUT*HZ);//ÔÙÖØÐÂÉèÖó¬Ê±Öµ¡£
-}
-
-void btWakeupHostLock(void)
-{
- if(gBtCtrl.b_HostWake == false){
- DBG("*************************Lock\n");
- wake_lock(&(gBtCtrl.bt_wakelock));
- gBtCtrl.b_HostWake = true;
- }
-}
-
-void btWakeupHostUnlock(void)
-{
- if(gBtCtrl.b_HostWake == true){
- DBG("*************************UnLock\n");
- wake_unlock(&(gBtCtrl.bt_wakelock)); //ÈÃϵͳ˯Ãß
- gBtCtrl.b_HostWake = false;
- }
-}
-
-static void timer_hostSleep(unsigned long arg)
-{
- DBG("%s---b_HostWake=%d\n",__FUNCTION__,gBtCtrl.b_HostWake);
- btWakeupHostUnlock();
-}
-
-
-#ifdef CONFIG_PM
-static int bcm4329_rfkill_suspend(struct platform_device *pdev, pm_message_t state)
-{
- DBG("%s\n",__FUNCTION__);
- return 0;
-}
-
-static int bcm4329_rfkill_resume(struct platform_device *pdev)
-{
- DBG("%s\n",__FUNCTION__);
- btWakeupHostLock();
- resetBtHostSleepTimer();
- return 0;
-}
-#else
-#define bcm4329_rfkill_suspend NULL
-#define bcm4329_rfkill_resume NULL
-#endif
-
-static irqreturn_t bcm4329_wake_host_irq(int irq, void *dev)
-{
- btWakeupHostLock();
- resetBtHostSleepTimer();
- return IRQ_HANDLED;
-}
-#endif
-
-#ifdef CONFIG_BT_HCIBCM4325
-int bcm4325_sleep(int bSleep)
-{
- //printk("*************bt enter sleep***************\n");
- if (bSleep)
- gpio_set_value(BT_GPIO_WAKE_UP, GPIO_LOW); //low represent bt device may enter sleep
- else
- gpio_set_value(BT_GPIO_WAKE_UP, GPIO_HIGH); //high represent bt device must be awake
- //printk("sleep=%d\n",bSleep);
- return 0;
-}
-#endif
-
-static int bcm4329_set_block(void *data, bool blocked)
-{
- DBG("%s---blocked :%d\n", __FUNCTION__, blocked);
-
- IOMUX_BT_GPIO_POWER;
-
- if (false == blocked) {
- gpio_set_value(BT_GPIO_POWER, GPIO_HIGH); /* bt power on */
- gpio_set_value(BT_GPIO_RESET, GPIO_LOW);
- mdelay(20);
- gpio_set_value(BT_GPIO_RESET, GPIO_HIGH); /* bt reset deactive*/
- mdelay(20);
-
-#if BT_WAKE_HOST_SUPPORT
- btWakeupHostLock();
-#endif
- pr_info("bt turn on power\n");
- }
- else {
-#if BT_WAKE_HOST_SUPPORT
- btWakeupHostUnlock();
-#endif
- if (!rk29sdk_wifi_power_state) {
- gpio_set_value(BT_GPIO_POWER, GPIO_LOW); /* bt power off */
- mdelay(20);
- pr_info("bt shut off power\n");
- }else {
- pr_info("bt shouldn't shut off power, wifi is using it!\n");
- }
-
- gpio_set_value(BT_GPIO_RESET, GPIO_LOW); /* bt reset active*/
- mdelay(20);
- }
-
- rk29sdk_bt_power_state = !blocked;
- return 0;
-}
-
-
-static const struct rfkill_ops bcm4329_rfk_ops = {
- .set_block = bcm4329_set_block,
-};
-
-static int __devinit bcm4329_rfkill_probe(struct platform_device *pdev)
-{
- int rc = 0;
- bool default_state = true;
-
- DBG("Enter::%s,line=%d\n",__FUNCTION__,__LINE__);
-
- /* default to bluetooth off */
- bcm4329_set_block(NULL, default_state); /* blocked -> bt off */
-
- gBtCtrl.bt_rfk = rfkill_alloc(bt_name,
- NULL,
- RFKILL_TYPE_BLUETOOTH,
- &bcm4329_rfk_ops,
- NULL);
-
- if (!gBtCtrl.bt_rfk)
- {
- printk("fail to rfkill_allocate************\n");
- return -ENOMEM;
- }
-
- rfkill_set_states(gBtCtrl.bt_rfk, default_state, false);
-
- rc = rfkill_register(gBtCtrl.bt_rfk);
- if (rc)
- {
- printk("failed to rfkill_register,rc=0x%x\n",rc);
- rfkill_destroy(gBtCtrl.bt_rfk);
- }
-
- gpio_request(BT_GPIO_POWER, NULL);
- gpio_request(BT_GPIO_RESET, NULL);
- gpio_request(BT_GPIO_WAKE_UP, NULL);
-
-#if BT_WAKE_HOST_SUPPORT
- init_timer(&(gBtCtrl.tl));
- gBtCtrl.tl.expires = jiffies + BT_WAKE_LOCK_TIMEOUT*HZ;
- gBtCtrl.tl.function = timer_hostSleep;
- add_timer(&(gBtCtrl.tl));
- gBtCtrl.b_HostWake = false;
-
- wake_lock_init(&(gBtCtrl.bt_wakelock), WAKE_LOCK_SUSPEND, "bt_wake");
-
- rc = gpio_request(BT_GPIO_WAKE_UP_HOST, "bt_wake");
- if (rc) {
- printk("%s:failed to request RAHO_BT_WAKE_UP_HOST\n",__FUNCTION__);
- }
-
- IOMUX_BT_GPIO_WAKE_UP_HOST();
- gpio_pull_updown(BT_GPIO_WAKE_UP_HOST,GPIOPullUp);
- rc = request_irq(gpio_to_irq(BT_GPIO_WAKE_UP_HOST),bcm4329_wake_host_irq,IRQF_TRIGGER_FALLING,NULL,NULL);
- if(rc)
- {
- printk("%s:failed to request RAHO_BT_WAKE_UP_HOST irq\n",__FUNCTION__);
- gpio_free(BT_GPIO_WAKE_UP_HOST);
- }
- enable_irq_wake(gpio_to_irq(BT_GPIO_WAKE_UP_HOST)); // so RAHO_BT_WAKE_UP_HOST can wake up system
-
- printk(KERN_INFO "bcm4329 module has been initialized,rc=0x%x\n",rc);
- #endif
-
- return rc;
-
-
-}
-
-
-static int __devexit bcm4329_rfkill_remove(struct platform_device *pdev)
-{
- if (gBtCtrl.bt_rfk)
- rfkill_unregister(gBtCtrl.bt_rfk);
- gBtCtrl.bt_rfk = NULL;
-#if BT_WAKE_HOST_SUPPORT
- del_timer(&(gBtCtrl.tl));//ɾµô¶¨Ê±Æ÷
- btWakeupHostUnlock();
- wake_lock_destroy(&(gBtCtrl.bt_wakelock));
-#endif
- platform_set_drvdata(pdev, NULL);
-
- DBG("Enter::%s,line=%d\n",__FUNCTION__,__LINE__);
- return 0;
-}
-
-static struct platform_driver bcm4329_rfkill_driver = {
- .probe = bcm4329_rfkill_probe,
- .remove = __devexit_p(bcm4329_rfkill_remove),
- .driver = {
- .name = "rk29sdk_rfkill",
- .owner = THIS_MODULE,
- },
-#if BT_WAKE_HOST_SUPPORT
- .suspend = bcm4329_rfkill_suspend,
- .resume = bcm4329_rfkill_resume,
-#endif
-};
-
-/*
- * Module initialization
- */
-static int __init bcm4329_mod_init(void)
-{
- int ret;
- DBG("Enter::%s,line=%d\n",__FUNCTION__,__LINE__);
- ret = platform_driver_register(&bcm4329_rfkill_driver);
- printk("ret=0x%x\n", ret);
- return ret;
-}
-
-static void __exit bcm4329_mod_exit(void)
-{
- platform_driver_unregister(&bcm4329_rfkill_driver);
-}
-
-module_init(bcm4329_mod_init);
-module_exit(bcm4329_mod_exit);
-MODULE_DESCRIPTION("bcm4329 Bluetooth driver");
-MODULE_AUTHOR("roger_chen cz@rock-chips.com");
-MODULE_LICENSE("GPL");
-
+++ /dev/null
-/* arch/arm/mach-rk29/board-rk29.c
- *
- * Copyright (C) 2010 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/android_pmem.h>
-#ifdef CONFIG_USB_ANDROID
-#include <linux/usb/android_composite.h>
-#endif
-#include <linux/ion.h>
-
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/iomux.h>
-#include <mach/gpio.h>
-#include <mach/irqs.h>
-#include <mach/rk29_iomap.h>
-#include <mach/board.h>
-#include <mach/rk29_nand.h>
-#include <media/soc_camera.h> /* ddl@rock-chips.com : camera support */
-#include <mach/rk29_camera.h> /* ddl@rock-chips.com : camera support */
-#include <mach/vpu_mem.h>
-#include <mach/sram.h>
-#include <mach/ddr.h>
-#include <mach/cpufreq.h>
-#include <mach/rk29_smc.h>
-
-#include <linux/regulator/rk29-pwm-regulator.h>
-#include <linux/regulator/machine.h>
-
-
-#include <linux/regulator/fixed.h>
-#include <linux/mfd/wm8994/pdata.h>
-
-#include <linux/mtd/nand.h>
-#include <linux/mtd/partitions.h>
-#include <linux/i2c-gpio.h>
-
-
-#include "devices.h"
-#if defined(CONFIG_MU509)
-#include <linux/mu509.h>
-#endif
-#include "../../../drivers/input/touchscreen/xpt2046_cbn_ts.h"
-#include "../../../drivers/headset_observe/rk_headset.h"
-
-#include <linux/goodix_touch.h>
-
-#include <linux/mpu.h>
-#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Macro Define Begin ------------------------*/
-/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
-#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_OV5642 /* back camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_0 0x78
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 1
-#define CONFIG_SENSOR_ORIENTATION_0 90
-#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 RK29_PIN5_PD7
-#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000
-
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_OV2659 /* front camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_1 0x60
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 1
-#define CONFIG_SENSOR_ORIENTATION_1 270
-#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_1 RK29_PIN6_PB7
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000
-
-#endif //#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk29_camera.c"
-/*---------------- Camera Sensor Macro Define End ------------------------*/
-
-
-/* Set memory size of pmem */
-#ifdef CONFIG_RK29_MEM_SIZE_M
-#define SDRAM_SIZE (CONFIG_RK29_MEM_SIZE_M * SZ_1M)
-#else
-#define SDRAM_SIZE SZ_512M
-#endif
-
-#define PMEM_GPU_SIZE SZ_64M
-/*1280*800 : (32+64)M ,1024*768 : (26+48)M, 800*600 : (16+32)M, 800*480 : (12+32)M,*/
-#define PMEM_UI_SIZE (48 * SZ_1M)
-#define PMEM_VPU_SIZE SZ_64M
-#define PMEM_SKYPE_SIZE 0
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-#ifdef CONFIG_VIDEO_RK29_WORK_IPP
-#define MEM_CAMIPP_SIZE PMEM_CAMIPP_NECESSARY
-#else
-#define MEM_CAMIPP_SIZE 0
-#endif
-#define MEM_FB_SIZE (9*SZ_1M)
-#ifdef CONFIG_FB_WORK_IPP
-#ifdef CONFIG_FB_SCALING_OSD_1080P
-#define MEM_FBIPP_SIZE SZ_16M //1920 x 1080 x 2 x 2 //RGB565 = x2;RGB888 = x4
-#else
-#define MEM_FBIPP_SIZE SZ_8M //1920 x 1080 x 2 x 2 //RGB565 = x2;RGB888 = x4
-#endif
-#else
-#define MEM_FBIPP_SIZE 0
-#endif
-#if SDRAM_SIZE > SZ_512M
-#define PMEM_GPU_BASE (RK29_SDRAM_PHYS + SZ_512M - PMEM_GPU_SIZE)
-#else
-#define PMEM_GPU_BASE (RK29_SDRAM_PHYS + SDRAM_SIZE - PMEM_GPU_SIZE)
-#endif
-#define PMEM_UI_BASE (PMEM_GPU_BASE - PMEM_UI_SIZE)
-#define PMEM_VPU_BASE (PMEM_UI_BASE - PMEM_VPU_SIZE)
-#define PMEM_CAM_BASE (PMEM_VPU_BASE - PMEM_CAM_SIZE)
-#define MEM_CAMIPP_BASE (PMEM_CAM_BASE - MEM_CAMIPP_SIZE)
-#define MEM_FB_BASE (MEM_CAMIPP_BASE - MEM_FB_SIZE)
-#define MEM_FBIPP_BASE (MEM_FB_BASE - MEM_FBIPP_SIZE)
-#define PMEM_SKYPE_BASE (MEM_FBIPP_BASE - PMEM_SKYPE_SIZE)
-#define LINUX_SIZE (PMEM_SKYPE_BASE - RK29_SDRAM_PHYS)
-
-#define PREALLOC_WLAN_SEC_NUM 4
-#define PREALLOC_WLAN_BUF_NUM 160
-#define PREALLOC_WLAN_SECTION_HEADER 24
-
-#define WLAN_SECTION_SIZE_0 (PREALLOC_WLAN_BUF_NUM * 128)
-#define WLAN_SECTION_SIZE_1 (PREALLOC_WLAN_BUF_NUM * 128)
-#define WLAN_SECTION_SIZE_2 (PREALLOC_WLAN_BUF_NUM * 512)
-#define WLAN_SECTION_SIZE_3 (PREALLOC_WLAN_BUF_NUM * 1024)
-
-#define WLAN_SKB_BUF_NUM 16
-
-static struct sk_buff *wlan_static_skb[WLAN_SKB_BUF_NUM];
-
-struct wifi_mem_prealloc {
- void *mem_ptr;
- unsigned long size;
-};
-
-extern struct sys_timer rk29_timer;
-
-static int rk29_nand_io_init(void)
-{
- return 0;
-}
-
-struct rk29_nand_platform_data rk29_nand_data = {
- .width = 1, /* data bus width in bytes */
- .hw_ecc = 1, /* hw ecc 0: soft ecc */
- .num_flash = 1,
- .io_init = rk29_nand_io_init,
-};
-
-/*****************************************************************************************
-* touch screen devices
-* author: cf@rock-chips.com
-*****************************************************************************************/
-#define TOUCH_SCREEN_STANDBY_PIN INVALID_GPIO
-#define TOUCH_SCREEN_STANDBY_VALUE GPIO_HIGH
-#define TOUCH_SCREEN_DISPLAY_PIN INVALID_GPIO
-#define TOUCH_SCREEN_DISPLAY_VALUE GPIO_HIGH
-
-#ifdef CONFIG_FB_RK29
-/*****************************************************************************************
- * lcd devices
- * author: zyw@rock-chips.com
- *****************************************************************************************/
-#define LCD_TXD_PIN INVALID_GPIO
-#define LCD_CLK_PIN INVALID_GPIO
-#define LCD_CS_PIN INVALID_GPIO
-/*****************************************************************************************
-* frame buffer devices pin define
-* author: zyw@rock-chips.com
-*****************************************************************************************/
-#define FB_ID 0
-#define FB_DISPLAY_ON_PIN INVALID_GPIO// RK29_PIN6_PD0
-#define FB_LCD_STANDBY_PIN RK29_PIN6_PD1
-#define FB_LCD_CABC_EN_PIN RK29_PIN6_PD2
-#define FB_MCU_FMK_PIN INVALID_GPIO
-
-#define FB_DISPLAY_ON_VALUE GPIO_HIGH
-#define FB_LCD_STANDBY_VALUE GPIO_HIGH
-
-static int rk29_lcd_io_init(void)
-{
- int ret = 0;
- return ret;
-}
-
-static int rk29_lcd_io_deinit(void)
-{
- int ret = 0;
- return ret;
-}
-
-static struct rk29lcd_info rk29_lcd_info = {
- .txd_pin = LCD_TXD_PIN,
- .clk_pin = LCD_CLK_PIN,
- .cs_pin = LCD_CS_PIN,
- .io_init = rk29_lcd_io_init,
- .io_deinit = rk29_lcd_io_deinit,
-};
-
-int rk29_fb_io_enable(void)
-{
- if(FB_DISPLAY_ON_PIN != INVALID_GPIO)
- {
- gpio_direction_output(FB_DISPLAY_ON_PIN, 0);
- gpio_set_value(FB_DISPLAY_ON_PIN, FB_DISPLAY_ON_VALUE);
- }
- if(FB_LCD_STANDBY_PIN != INVALID_GPIO)
- {
- gpio_direction_output(FB_LCD_STANDBY_PIN, 0);
- gpio_set_value(FB_LCD_STANDBY_PIN, FB_LCD_STANDBY_VALUE);
- }
- return 0;
-}
-
-int rk29_fb_io_disable(void)
-{
- if(FB_DISPLAY_ON_PIN != INVALID_GPIO)
- {
- gpio_direction_output(FB_DISPLAY_ON_PIN, 0);
- gpio_set_value(FB_DISPLAY_ON_PIN, !FB_DISPLAY_ON_VALUE);
- }
- if(FB_LCD_STANDBY_PIN != INVALID_GPIO)
- {
- gpio_direction_output(FB_LCD_STANDBY_PIN, 0);
- gpio_set_value(FB_LCD_STANDBY_PIN, !FB_LCD_STANDBY_VALUE);
- }
- return 0;
-}
-
-static int rk29_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
- if(fb_setting->mcu_fmk_en && (FB_MCU_FMK_PIN != INVALID_GPIO))
- {
- ret = gpio_request(FB_MCU_FMK_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(FB_MCU_FMK_PIN);
- printk(">>>>>> FB_MCU_FMK_PIN gpio_request err \n ");
- }
- gpio_direction_input(FB_MCU_FMK_PIN);
- }
- if(fb_setting->disp_on_en)
- {
- if(FB_DISPLAY_ON_PIN != INVALID_GPIO)
- {
- ret = gpio_request(FB_DISPLAY_ON_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(FB_DISPLAY_ON_PIN);
- printk(">>>>>> FB_DISPLAY_ON_PIN gpio_request err \n ");
- }
- }
- else
- {
- ret = gpio_request(TOUCH_SCREEN_DISPLAY_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(TOUCH_SCREEN_DISPLAY_PIN);
- printk(">>>>>> TOUCH_SCREEN_DISPLAY_PIN gpio_request err \n ");
- }
- gpio_direction_output(TOUCH_SCREEN_DISPLAY_PIN, 0);
- gpio_set_value(TOUCH_SCREEN_DISPLAY_PIN, TOUCH_SCREEN_DISPLAY_VALUE);
- }
- }
-
- if(fb_setting->disp_on_en)
- {
- if(FB_LCD_STANDBY_PIN != INVALID_GPIO)
- {
- ret = gpio_request(FB_LCD_STANDBY_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(FB_LCD_STANDBY_PIN);
- printk(">>>>>> FB_LCD_STANDBY_PIN gpio_request err \n ");
- }
- }
- else
- {
- ret = gpio_request(TOUCH_SCREEN_STANDBY_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(TOUCH_SCREEN_STANDBY_PIN);
- printk(">>>>>> TOUCH_SCREEN_STANDBY_PIN gpio_request err \n ");
- }
- gpio_direction_output(TOUCH_SCREEN_STANDBY_PIN, 0);
- gpio_set_value(TOUCH_SCREEN_STANDBY_PIN, TOUCH_SCREEN_STANDBY_VALUE);
- }
- }
-
- if(FB_LCD_CABC_EN_PIN != INVALID_GPIO)
- {
- ret = gpio_request(FB_LCD_CABC_EN_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(FB_LCD_CABC_EN_PIN);
- printk(">>>>>> FB_LCD_CABC_EN_PIN gpio_request err \n ");
- }
- gpio_direction_output(FB_LCD_CABC_EN_PIN, 0);
- gpio_set_value(FB_LCD_CABC_EN_PIN, GPIO_LOW);
- }
-
- rk29_fb_io_enable(); //enable it
-
- return ret;
-}
-
-
-static struct rk29fb_info rk29_fb_info = {
- .fb_id = FB_ID,
- .mcu_fmk_pin = FB_MCU_FMK_PIN,
- .lcd_info = &rk29_lcd_info,
- .io_init = rk29_fb_io_init,
- .io_enable = rk29_fb_io_enable,
- .io_disable = rk29_fb_io_disable,
-};
-
-/* rk29 fb resource */
-static struct resource rk29_fb_resource[] = {
- [0] = {
- .name = "lcdc reg",
- .start = RK29_LCDC_PHYS,
- .end = RK29_LCDC_PHYS + RK29_LCDC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc irq",
- .start = IRQ_LCDC,
- .end = IRQ_LCDC,
- .flags = IORESOURCE_IRQ,
- },
- [2] = {
- .name = "win1 buf",
- .start = MEM_FB_BASE,
- .end = MEM_FB_BASE + MEM_FB_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- #ifdef CONFIG_FB_WORK_IPP
- [3] = {
- .name = "win1 ipp buf",
- .start = MEM_FBIPP_BASE,
- .end = MEM_FBIPP_BASE + MEM_FBIPP_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- #endif
-};
-
-/*platform_device*/
-struct platform_device rk29_device_fb = {
- .name = "rk29-fb",
- .id = 4,
- .num_resources = ARRAY_SIZE(rk29_fb_resource),
- .resource = rk29_fb_resource,
- .dev = {
- .platform_data = &rk29_fb_info,
- }
-};
-
-struct platform_device rk29_device_dma_cpy = {
- .name = "dma_memcpy",
- .id = 4,
-
-};
-
-#endif
-
-#if defined(CONFIG_RK29_GPIO_SUSPEND)
-static void key_gpio_pullupdown_enable(void)
-{
- gpio_pull_updown(RK29_PIN6_PA0, 0);
- gpio_pull_updown(RK29_PIN6_PA1, 0);
- gpio_pull_updown(RK29_PIN6_PA2, 0);
- gpio_pull_updown(RK29_PIN6_PA3, 0);
- gpio_pull_updown(RK29_PIN6_PA4, 0);
- gpio_pull_updown(RK29_PIN6_PA5, 0);
- gpio_pull_updown(RK29_PIN6_PA6, 0);
-}
-
-static void key_gpio_pullupdown_disable(void)
-{
- gpio_pull_updown(RK29_PIN6_PA0, 1);
- gpio_pull_updown(RK29_PIN6_PA1, 1);
- gpio_pull_updown(RK29_PIN6_PA2, 1);
- gpio_pull_updown(RK29_PIN6_PA3, 1);
- gpio_pull_updown(RK29_PIN6_PA4, 1);
- gpio_pull_updown(RK29_PIN6_PA5, 1);
- gpio_pull_updown(RK29_PIN6_PA6, 1);
-}
-
-void rk29_setgpio_suspend_board(void)
-{
- key_gpio_pullupdown_enable();
-}
-
-void rk29_setgpio_resume_board(void)
-{
- key_gpio_pullupdown_disable();
-}
-#endif
-static struct android_pmem_platform_data android_pmem_pdata = {
- .name = "pmem",
- .start = PMEM_UI_BASE,
- .size = PMEM_UI_SIZE,
- .no_allocator = 1,
- .cached = 1,
-};
-
-static struct platform_device android_pmem_device = {
- .name = "android_pmem",
- .id = 0,
- .dev = {
- .platform_data = &android_pmem_pdata,
- },
-};
-
-static struct vpu_mem_platform_data vpu_mem_pdata = {
- .name = "vpu_mem",
- .start = PMEM_VPU_BASE,
- .size = PMEM_VPU_SIZE,
- .cached = 1,
-};
-
-static struct platform_device rk29_vpu_mem_device = {
- .name = "vpu_mem",
- .id = 2,
- .dev = {
- .platform_data = &vpu_mem_pdata,
- },
-};
-
-#if PMEM_SKYPE_SIZE > 0
-static struct android_pmem_platform_data android_pmem_skype_pdata = {
- .name = "pmem_skype",
- .start = PMEM_SKYPE_BASE,
- .size = PMEM_SKYPE_SIZE,
- .no_allocator = 0,
- .cached = 0,
-};
-
-static struct platform_device android_pmem_skype_device = {
- .name = "android_pmem",
- .id = 3,
- .dev = {
- .platform_data = &android_pmem_skype_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_ION
-static struct ion_platform_data rk29_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = 0,
- .name = "ui",
- .base = PMEM_UI_BASE,
- .size = PMEM_UI_SIZE,
- }
- },
-};
-
-static struct platform_device rk29_ion_device = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk29_ion_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_VIDEO_RK29XX_VOUT
-static struct platform_device rk29_v4l2_output_devce = {
- .name = "rk29_vout",
-};
-#endif
-/*HANNSTAR_P1003 touch*/
-#if defined (CONFIG_HANNSTAR_P1003)
-#define TOUCH_RESET_PIN RK29_PIN6_PC3
-#define TOUCH_INT_PIN RK29_PIN0_PA2
-
-int p1003_init_platform_hw(void)
-{
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- gpio_free(TOUCH_RESET_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_pull_updown(TOUCH_INT_PIN, 1);
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
-
- return 0;
-}
-
-
-struct p1003_platform_data p1003_info = {
- .model= 1003,
- .init_platform_hw= p1003_init_platform_hw,
-
-};
-#endif
-#if defined (CONFIG_EETI_EGALAX)
-
-#define TOUCH_RESET_PIN RK29_PIN6_PC3
-#define TOUCH_INT_PIN RK29_PIN0_PA2
-
-static int EETI_EGALAX_init_platform_hw(void)
-{
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- gpio_free(TOUCH_RESET_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_pull_updown(TOUCH_INT_PIN, 1);
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
-
- return 0;
-}
-
-
-static struct eeti_egalax_platform_data eeti_egalax_info = {
- .model= 1003,
- .init_platform_hw= EETI_EGALAX_init_platform_hw,
- .standby_pin = TOUCH_SCREEN_STANDBY_PIN,
- .standby_value = TOUCH_SCREEN_STANDBY_VALUE,
- .disp_on_pin = TOUCH_SCREEN_DISPLAY_PIN,
- .disp_on_value = TOUCH_SCREEN_DISPLAY_VALUE,
-};
-
-#endif
-//tcl miaozh add
-/*Nas touch*/
-#if defined (CONFIG_TOUCHSCREEN_NAS)
-#define TOUCH_RESET_PIN RK29_PIN6_PC3
-#define TOUCH_INT_PIN RK29_PIN0_PA2
-void nas_reset(void)
-{
- msleep(5);
- gpio_pull_updown(TOUCH_INT_PIN, 1);
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- msleep(5);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- msleep(200);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
-}
-void nas_hold(void)
-{
- printk("nas_hold()\n");
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- msleep(5);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- msleep(30);
- }
-void nas_request_io(void)
-{
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("nas_init_platform_hw gpio_request error\n");
- return ;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- gpio_free(TOUCH_RESET_PIN);
- printk("nas_init_platform_hw gpio_request error\n");
- return;
- }
-}
-
-int nas_init_platform_hw(void)
-{
- printk("enter %s()\n", __FUNCTION__);
- //nas_request_io();
- //nas_reset();
- return 0;
-}
-
-
-struct nas_platform_data nas_info = {
- .model= 1003,
- .init_platform_hw= nas_init_platform_hw,
-
-};
-#endif
-
-#if defined (CONFIG_LAIBAO_TS)
-#define TOUCH_RESET_PIN RK29_PIN6_PC3
-#define TOUCH_INT_PIN RK29_PIN0_PA2
-#define TOUCH_PWR_PIN RK29_PIN2_PC3
-//TODO,shut down touch for power saving
-#define TOUCH_SHUTDOWN RK29_PIN4_PD5
-void laibao_reset(void)
-{
- msleep(5);
- gpio_pull_updown(TOUCH_INT_PIN, 1);
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- msleep(5);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- msleep(200);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
-}
-void laibao_hold(void)
-{
- printk("laibao_hold()\n");
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- msleep(5);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- msleep(30);
- }
-void laibao_request_io(void)
-{
- if(gpio_request(TOUCH_PWR_PIN,NULL) != 0){
- gpio_free(TOUCH_PWR_PIN);
- printk("laibao_request_io TOUCH_PWR_PIN error\n");
- return ;
- }
- gpio_direction_output(TOUCH_PWR_PIN, 0);
- gpio_set_value(TOUCH_PWR_PIN,GPIO_HIGH);
-
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- gpio_free(TOUCH_PWR_PIN);
- printk("laibao_request_io TOUCH_RESET_PIN error\n");
- return ;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- gpio_free(TOUCH_RESET_PIN);
- gpio_free(TOUCH_PWR_PIN);
- printk("laibao_request_io TOUCH_INT_PIN error\n");
- return ;
- }
-}
-
-int laibao_init_platform_hw(void)
-{
- printk("enter %s()\n", __FUNCTION__);
- laibao_request_io();
- laibao_reset();
-
- return 0;
-}
-
-
-struct laibao_platform_data laibao_info = {
- .model= 1003,
- .init_platform_hw= laibao_init_platform_hw,
- .pwr_pin = TOUCH_PWR_PIN,
- .pwr_on_value = GPIO_HIGH,
- .reset_pin = TOUCH_RESET_PIN,
- .reset_value=GPIO_HIGH,
-
-};
-#endif
-
-
-#if defined (CONFIG_D70_L3188A)
-struct goodix_i2c_rmi_platform_data d70_l3188a_info = {
- .shutdown_pin = RK29_PIN4_PD5,
- .irq_pin = RK29_PIN0_PA2,
-};
-#endif
-
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN RK29_PIN0_PA3
-
-static int mma8452_init_platform_hw(void)
-{
-
- if(gpio_request(MMA8452_INT_PIN,NULL) != 0){
- gpio_free(MMA8452_INT_PIN);
- printk("mma8452_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_pull_updown(MMA8452_INT_PIN, 1);
- return 0;
-}
-
-
-static struct gsensor_platform_data mma8452_info = {
- .model= 8452,
- .swap_xy = 0,
- .init_platform_hw= mma8452_init_platform_hw,
-
-};
-#endif
-
-#if defined (CONFIG_MPU_SENSORS_MPU3050)
-static struct mpu_platform_data mpu3050_data = {
- .int_config = 0x10,
- .orientation ={ 1, 0, 0, 0, 1, 0, 0, 0, -1 },
-};
-#endif
-/* accel */
-#if defined (CONFIG_MPU_SENSORS_BMA222)
-static struct ext_slave_platform_data inv_mpu_bma222_data = {
- .bus = EXT_SLAVE_BUS_SECONDARY,
- .adapt_num = 0,
- .orientation = { -1, 0, 0, 0, -1, 0, 0, 0, 1 },
-};
-#endif
-
-#if defined (CONFIG_BATTERY_BQ27510)
-#define DC_CHECK_PIN RK29_PIN4_PA1
-#define LI_LION_BAT_NUM 2
-static int bq27510_init_dc_check_pin(void){
- if(gpio_request(DC_CHECK_PIN,"dc_check") != 0){
- gpio_free(DC_CHECK_PIN);
- printk("bq27510 init dc check pin request error\n");
- return -EIO;
- }
- gpio_direction_input(DC_CHECK_PIN);
- return 0;
-}
-
-struct bq27510_platform_data bq27510_info = {
- .init_dc_check_pin = bq27510_init_dc_check_pin,
- .dc_check_pin = DC_CHECK_PIN,
- .bat_num = LI_LION_BAT_NUM,
-};
-#endif
-/*****************************************************************************************
- * wm8994 codec
- * author: qjb@rock-chips.com
- *****************************************************************************************/
-#if defined(CONFIG_MFD_WM8994)
-static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = {
- REGULATOR_SUPPLY("DBVDD", "5-001a"),
- REGULATOR_SUPPLY("AVDD2", "5-001a"),
- REGULATOR_SUPPLY("CPVDD", "5-001a"),
-};
-
-static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = {
- REGULATOR_SUPPLY("SPKVDD1", "5-001a"),
- REGULATOR_SUPPLY("SPKVDD2", "5-001a"),
-};
-
-static struct regulator_init_data wm8994_fixed_voltage0_init_data = {
- .constraints = {
- .always_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage0_supplies),
- .consumer_supplies = wm8994_fixed_voltage0_supplies,
-};
-
-static struct regulator_init_data wm8994_fixed_voltage1_init_data = {
- .constraints = {
- .always_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage1_supplies),
- .consumer_supplies = wm8994_fixed_voltage1_supplies,
-};
-
-static struct fixed_voltage_config wm8994_fixed_voltage0_config = {
- .supply_name = "VCC_1.8V_PDA",
- .microvolts = 1800000,
- .gpio = -EINVAL,
- .init_data = &wm8994_fixed_voltage0_init_data,
-};
-
-static struct fixed_voltage_config wm8994_fixed_voltage1_config = {
- .supply_name = "V_BAT",
- .microvolts = 3700000,
- .gpio = -EINVAL,
- .init_data = &wm8994_fixed_voltage1_init_data,
-};
-
-static struct platform_device wm8994_fixed_voltage0 = {
- .name = "reg-fixed-voltage",
- .id = 0,
- .dev = {
- .platform_data = &wm8994_fixed_voltage0_config,
- },
-};
-
-static struct platform_device wm8994_fixed_voltage1 = {
- .name = "reg-fixed-voltage",
- .id = 1,
- .dev = {
- .platform_data = &wm8994_fixed_voltage1_config,
- },
-};
-
-static struct regulator_consumer_supply wm8994_avdd1_supply =
- REGULATOR_SUPPLY("AVDD1", "5-001a");
-
-static struct regulator_consumer_supply wm8994_dcvdd_supply =
- REGULATOR_SUPPLY("DCVDD", "5-001a");
-
-
-
-static struct regulator_init_data wm8994_ldo1_data = {
- .constraints = {
- .name = "AVDD1_3.0V",
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = 1,
- .consumer_supplies = &wm8994_avdd1_supply,
-};
-
-static struct regulator_init_data wm8994_ldo2_data = {
- .constraints = {
- .name = "DCVDD_1.0V",
- },
- .num_consumer_supplies = 1,
- .consumer_supplies = &wm8994_dcvdd_supply,
-};
-
-static struct wm8994_pdata wm8994_platform_data = {
-#if defined (CONFIG_GPIO_WM8994)
- .gpio_base = WM8994_GPIO_EXPANDER_BASE,
- //Fill value to initialize the GPIO
-// .gpio_defaults ={},
- /* configure gpio1 function: 0x0001(Logic level input/output) */
-// .gpio_defaults[0] = 0x0001,
- /* configure gpio3/4/5/7 function for AIF2 voice */
- .gpio_defaults[2] = 0x2100,
- .gpio_defaults[3] = 0x2100,
- .gpio_defaults[4] = 0xA100,
-// .gpio_defaults[6] = 0x0100,
- /* configure gpio8/9/10/11 function for AIF3 BT */
- .gpio_defaults[7] = 0xA100,
- .gpio_defaults[8] = 0x2100,
- .gpio_defaults[9] = 0x2100,
- .gpio_defaults[10] = 0x2100,
-#endif
-
- .ldo[0] = { RK29_PIN5_PA1, NULL, &wm8994_ldo1_data }, /* XM0FRNB_2 */
- .ldo[1] = { 0, NULL, &wm8994_ldo2_data },
-
- .micdet_irq = 0,
- .irq_base = 0,
- .lineout1_diff = 1,
- .PA_control_pin=RK29_PIN6_PB6,
-
-};
-#endif
-
-#if defined (CONFIG_SND_SOC_RT5625_SPK_FORM_SPKOUT) || defined (CONFIG_SND_SOC_RT5625_SPK_FORM_HPOUT)
-
-//please define level value of power amp control
-#define POWER_AMP_ON 0
-#define POWER_AMP_OFF 1
-#define RT5625_POWER_AMP_PIN INVALID_GPIO //RK29_PIN6_PB6
-
-struct rt5625_platform_data rt5625_platform_data = {
- .spk_ctr_pin = RT5625_POWER_AMP_PIN,
- .spk_ctr_on = POWER_AMP_ON,
- .spk_ctr_off = POWER_AMP_OFF,
-};
-#endif
-
-#ifdef CONFIG_RK_HEADSET_DET
-
-struct rk_headset_pdata rk_headset_info = {
- .Headset_gpio = RK29_PIN4_PD2,
- .headset_in_type= HEADSET_IN_HIGH,
- .Hook_gpio = RK29_PIN4_PD1,//Detection Headset--Must be set
- .hook_key_code = KEY_MEDIA,
-};
-
-struct platform_device rk_device_headset = {
- .name = "rk_headsetdet",
- .id = 0,
- .dev = {
- .platform_data = &rk_headset_info,
- }
-};
-#endif
-
-#if defined (CONFIG_BATTERY_BQ27541)
-#define DC_CHECK_PIN RK29_PIN4_PA1
-#define LI_LION_BAT_NUM 2
-#define CHG_OK RK29_PIN4_PA3
-#define BAT_LOW RK29_PIN4_PA2
-static int bq27541_init_dc_check_pin(void){
- if(gpio_request(DC_CHECK_PIN,"dc_check") != 0){
- gpio_free(DC_CHECK_PIN);
- printk("bq27541 init dc check pin request error\n");
- return -EIO;
- }
- gpio_direction_input(DC_CHECK_PIN);
- return 0;
-}
-
-struct bq27541_platform_data bq27541_info = {
- .init_dc_check_pin = bq27541_init_dc_check_pin,
- .dc_check_pin = DC_CHECK_PIN,
- .bat_num = LI_LION_BAT_NUM,
- .chgok_check_pin = CHG_OK,
- .bat_check_pin = BAT_LOW,
-};
-#endif
-
-
-/*****************************************************************************************
- * i2c devices
- * author: kfx@rock-chips.com
-*****************************************************************************************/
-static int rk29_i2c0_io_init(void)
-{
-#ifdef CONFIG_RK29_I2C0_CONTROLLER
- rk29_mux_api_set(GPIO2B7_I2C0SCL_NAME, GPIO2L_I2C0_SCL);
- rk29_mux_api_set(GPIO2B6_I2C0SDA_NAME, GPIO2L_I2C0_SDA);
-#else
- rk29_mux_api_set(GPIO2B7_I2C0SCL_NAME, GPIO2L_GPIO2B7);
- rk29_mux_api_set(GPIO2B6_I2C0SDA_NAME, GPIO2L_GPIO2B6);
-#endif
- return 0;
-}
-
-static int rk29_i2c1_io_init(void)
-{
-#ifdef CONFIG_RK29_I2C1_CONTROLLER
- rk29_mux_api_set(GPIO1A7_I2C1SCL_NAME, GPIO1L_I2C1_SCL);
- rk29_mux_api_set(GPIO1A6_I2C1SDA_NAME, GPIO1L_I2C1_SDA);
-#else
- rk29_mux_api_set(GPIO1A7_I2C1SCL_NAME, GPIO1L_GPIO1A7);
- rk29_mux_api_set(GPIO1A6_I2C1SDA_NAME, GPIO1L_GPIO1A6);
-#endif
- return 0;
-}
-static int rk29_i2c2_io_init(void)
-{
-#ifdef CONFIG_RK29_I2C2_CONTROLLER
- rk29_mux_api_set(GPIO5D4_I2C2SCL_NAME, GPIO5H_I2C2_SCL);
- rk29_mux_api_set(GPIO5D3_I2C2SDA_NAME, GPIO5H_I2C2_SDA);
-#else
- rk29_mux_api_set(GPIO5D4_I2C2SCL_NAME, GPIO5H_GPIO5D4);
- rk29_mux_api_set(GPIO5D3_I2C2SDA_NAME, GPIO5H_GPIO5D3);
-#endif
- return 0;
-}
-
-static int rk29_i2c3_io_init(void)
-{
-#ifdef CONFIG_RK29_I2C3_CONTROLLER
- rk29_mux_api_set(GPIO2B5_UART3RTSN_I2C3SCL_NAME, GPIO2L_I2C3_SCL);
- rk29_mux_api_set(GPIO2B4_UART3CTSN_I2C3SDA_NAME, GPIO2L_I2C3_SDA);
-#else
- rk29_mux_api_set(GPIO2B5_UART3RTSN_I2C3SCL_NAME, GPIO2L_GPIO2B5);
- rk29_mux_api_set(GPIO2B4_UART3CTSN_I2C3SDA_NAME, GPIO2L_GPIO2B4);
-#endif
- return 0;
-}
-#ifdef CONFIG_RK29_I2C0_CONTROLLER
-struct rk29_i2c_platform_data default_i2c0_data = {
- .bus_num = 0,
- .flags = 0,
- .slave_addr = 0xff,
- .scl_rate = 400*1000,
- .mode = I2C_MODE_IRQ,
- .io_init = rk29_i2c0_io_init,
-};
-#else
-struct i2c_gpio_platform_data default_i2c0_data = {
- .sda_pin = RK29_PIN2_PB6,
- .scl_pin = RK29_PIN2_PB7,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(200),
- .bus_num = 0,
- .io_init = rk29_i2c0_io_init,
-};
-#endif
-#ifdef CONFIG_RK29_I2C1_CONTROLLER
-struct rk29_i2c_platform_data default_i2c1_data = {
- .bus_num = 1,
- .flags = 0,
- .slave_addr = 0xff,
- .scl_rate = 400*1000,
- .mode = I2C_MODE_IRQ,
- .io_init = rk29_i2c1_io_init,
-};
-#else
-struct i2c_gpio_platform_data default_i2c1_data = {
- .sda_pin = RK29_PIN1_PA6,
- .scl_pin = RK29_PIN1_PA7,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(200),
- .bus_num = 1,
- .io_init = rk29_i2c1_io_init,
-};
-#endif
-#ifdef CONFIG_RK29_I2C2_CONTROLLER
-struct rk29_i2c_platform_data default_i2c2_data = {
- .bus_num = 2,
- .flags = 0,
- .slave_addr = 0xff,
- .scl_rate = 400*1000,
- .mode = I2C_MODE_IRQ,
- .io_init = rk29_i2c2_io_init,
-};
-#else
-struct i2c_gpio_platform_data default_i2c2_data = {
- .sda_pin = RK29_PIN5_PD3,
- .scl_pin = RK29_PIN5_PD4,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(200),
- .bus_num = 2,
- .io_init = rk29_i2c2_io_init,
-};
-#endif
-#ifdef CONFIG_RK29_I2C3_CONTROLLER
-struct rk29_i2c_platform_data default_i2c3_data = {
- .bus_num = 3,
- .flags = 0,
- .slave_addr = 0xff,
- .scl_rate = 400*1000,
- .mode = I2C_MODE_IRQ,
- .io_init = rk29_i2c3_io_init,
-};
-#else
-struct i2c_gpio_platform_data default_i2c3_data = {
- .sda_pin = RK29_PIN5_PB5,
- .scl_pin = RK29_PIN5_PB4,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(200),
- .bus_num = 3,
- .io_init = rk29_i2c3_io_init,
-};
-#endif
-#ifdef CONFIG_I2C0_RK29
-static struct i2c_board_info __initdata board_i2c0_devices[] = {
-#if defined (CONFIG_RK1000_CONTROL)
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_alc5621)
- {
- .type = "ALC5621",
- .addr = 0x1a,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_alc5631)
- {
- .type = "rt5631",
- .addr = 0x1a,
- .flags = 0,
- },
-#endif
-
-//note: rt5625 support two hardware connect, select the right config
-
-#if defined (CONFIG_SND_SOC_RT5625_SPK_FORM_SPKOUT) || defined (CONFIG_SND_SOC_RT5625_SPK_FORM_HPOUT)
- {
- .type = "rt5625",
- .addr = 0x1e, //need check A1 pin,A1 pin is low,addr=0x1e,A1 pin is high,addr=0x1f.
- .flags = 0,
- .platform_data = &rt5625_platform_data,
- },
-#endif
-
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_WM8900)
- {
- .type = "wm8900",
- .addr = 0x1A,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_MFD_WM8994)
- {
- .type = "wm8994",
- .addr = 0x1A,
- .flags = 0,
- .platform_data = &wm8994_platform_data,
- },
-#endif
-#if defined (CONFIG_BATTERY_STC3100)
- {
- .type = "stc3100",
- .addr = 0x70,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_BATTERY_BQ27510)
- {
- .type = "bq27510",
- .addr = 0x55,
- .flags = 0,
- .platform_data = &bq27510_info,
- },
-#endif
-#if defined (CONFIG_RTC_HYM8563)
- {
- .type = "rtc_hym8563",
- .addr = 0x51,
- .flags = 0,
- .irq = RK29_PIN0_PA1,
- },
-#endif
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1c,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8973)
- {
- .type = "ak8973",
- .addr = 0x1d,
- .flags = 0,
- .irq = RK29_PIN0_PA4,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK29_PIN0_PA4,
- },
-#endif
-#if defined (CONFIG_MPU_SENSORS_BMA222)
- {
- .type = "bma222",
- .addr = 0x08,
- .flags = 0,
-// .irq = RK29_PIN0_PA3,
- .platform_data = &inv_mpu_bma222_data,
- },
-
-#endif
-/*mpu3050*/
-#if defined (CONFIG_MPU_SENSORS_MPU3050)
- {
- .type = "mpu3050",
- .addr = 0x68,
- .flags = 0,
- .irq = RK29_PIN5_PA3,
- .platform_data = &mpu3050_data,
- },
-#endif
-
-#if defined (CONFIG_BATTERY_BQ27541)
- {
- .type = "bq27541",
- .addr = 0x55,
- .flags = 0,
- .platform_data = &bq27541_info,
- },
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C1_RK29
-static struct i2c_board_info __initdata board_i2c1_devices[] = {
-#if defined (CONFIG_RK1000_CONTROL1)
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C2_RK29
-static struct i2c_board_info __initdata board_i2c2_devices[] = {
-#if defined (CONFIG_HANNSTAR_P1003)
- {
- .type = "p1003_touch",
- .addr = 0x04,
- .flags = 0, //I2C_M_NEED_DELAY
- .irq = RK29_PIN0_PA2,
- .platform_data = &p1003_info,
- //.udelay = 100
- },
-#endif
-#if defined (CONFIG_EETI_EGALAX)
- {
- .type = "egalax_i2c",
- .addr = 0x04,
- .flags = 0,
- .irq = RK29_PIN0_PA2,
- .platform_data = &eeti_egalax_info,
- },
-#endif
-//tcl miaozh add
-#if defined (CONFIG_TOUCHSCREEN_NAS)
- {
- .type = "nas_touch",
- .addr = (0x70>>1),
- .flags = 0, //I2C_M_NEED_DELAY
- .irq = RK29_PIN0_PA2,
- .platform_data = &nas_info,
- //.udelay = 100
- },
-#endif
-
-#if defined (CONFIG_LAIBAO_TS)
- {
- .type = "laibao_touch",
- .addr = (0x70>>1),
- .flags = 0,
- .irq = RK29_PIN0_PA2,//gpio_to_irq(RK29_PIN0_PA2),
- .platform_data = &laibao_info,
- },
-#endif
-
-#if defined (CONFIG_D70_L3188A)
- {
- .type = "goodix-ts",
- .addr = 0x55,
- .flags = 0,
- .irq = RK29_PIN0_PA2,
- .platform_data = &d70_l3188a_info,
- },
-#endif
-};
-#endif
-
-#define CONFIG_TDA998 1
-#if defined (CONFIG_TDA998)
-#define HDMI_V33_CTL RK29_PIN6_PD3 //3.3V power control
-#define HDMI_V5_CTL RK29_PIN4_PD0 //5V power control
-#define HDMI_DET_PIN RK29_PIN1_PD7 //DET PIN
-int tda998_io_init(void)
-{
- printk("enter tda998_io_init()\n");
- gpio_request(HDMI_V33_CTL, "hdmi pwr ctl 0");
- gpio_request(HDMI_V5_CTL, "hdmi v5 ctl 1");
- gpio_direction_output(HDMI_V33_CTL, GPIO_HIGH);
- gpio_direction_output(HDMI_V5_CTL, GPIO_HIGH);
- gpio_request(HDMI_DET_PIN, "hdmi det");
- gpio_direction_input(HDMI_DET_PIN);
- mdelay(10);
- return 0;
-}
-struct hdmi_platform_data tda998_data = {
- .io_init = tda998_io_init,
-};
-#endif
-
-
-#if defined (CONFIG_ANX7150)
-#define HDMI_V33_CTL RK29_PIN6_PD3 //3.3V power control
-#define HDMI_V5_CTL RK29_PIN4_PD0 //5V power control
-int anx7150_io_init(void)
-{
- gpio_request(HDMI_V33_CTL, "hdmi pwr ctl 0");
- gpio_request(HDMI_V5_CTL, "hdmi pwr ctl 1");
- gpio_direction_output(HDMI_V33_CTL, GPIO_HIGH);
- gpio_direction_output(HDMI_V5_CTL, GPIO_HIGH);
- //gpio_set_value(HDMI_VDD_CTL, GPIO_HIGH);
- mdelay(10);
- return 0;
-}
-struct hdmi_platform_data anx7150_data = {
- .io_init = anx7150_io_init,
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK29
-static struct i2c_board_info __initdata board_i2c3_devices[] = {
-#if defined (CONFIG_ANX7150) || defined (CONFIG_ANX7150_NEW)
- {
- .type = "anx7150",
- .addr = 0x39, //0x39, 0x3d
- .flags = 0,
- .irq = RK29_PIN1_PD7,
- .platform_data = &anx7150_data,
- },
-#endif
-
-#if defined (CONFIG_TDA998)
- {
- .type = "tda998X",
- .addr = (0x70>>1), //0x39, 0x3d
- .flags = 0,
- .irq = RK29_PIN1_PD7,
- .platform_data = &tda998_data,
- },
- {
- .type = "tda99Xcec",
- .addr = (0x34>>1), //0x39, 0x3d
- .flags = 0,
- .irq = RK29_PIN1_PD7,
- .platform_data = &tda998_data,
- },
-
-#endif
-
-
-};
-#endif
-
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#define CONFIG_SENSOR_POWER_IOCTL_USR 0
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_RESET_IOCTL_USR
-static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
-static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-#include "../../../drivers/media/video/rk29_camera.c"
-#endif
-/*****************************************************************************************
- * backlight devices
- * author: nzy@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- /*
- GPIO1B5_PWM0_NAME, GPIO1L_PWM0
- GPIO5D2_PWM1_UART1SIRIN_NAME, GPIO5H_PWM1
- GPIO2A3_SDMMC0WRITEPRT_PWM2_NAME, GPIO2L_PWM2
- GPIO1A5_EMMCPWREN_PWM3_NAME, GPIO1L_PWM3
- */
-
-#define PWM_ID 0
-#define PWM_MUX_NAME GPIO1B5_PWM0_NAME
-#define PWM_MUX_MODE GPIO1L_PWM0
-#define PWM_MUX_MODE_GPIO GPIO1L_GPIO1B5
-#define PWM_GPIO RK29_PIN1_PB5
-#define PWM_EFFECT_VALUE 1
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-//#define BL_EN_MUX_NAME GPIOF34_UART3_SEL_NAME
-//#define BL_EN_MUX_MODE IOMUXB_GPIO1_B34
-
-#define BL_EN_PIN RK29_PIN6_PD0
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
-
- rk29_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
- #ifdef LCD_DISP_ON_PIN
- // rk29_mux_api_set(BL_EN_MUX_NAME, BL_EN_MUX_MODE);
-
- ret = gpio_request(BL_EN_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(BL_EN_PIN);
- }
-
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
- #endif
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0;
- #ifdef LCD_DISP_ON_PIN
- gpio_free(BL_EN_PIN);
- #endif
- rk29_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret = 0;
- rk29_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- if (gpio_request(PWM_GPIO, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- gpio_direction_output(PWM_GPIO, GPIO_LOW);
- #if 0//def LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, !BL_EN_VALUE);
- #endif
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- gpio_free(PWM_GPIO);
- rk29_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
-
- #if 0//def LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, 1);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
- #endif
- return 0;
-}
-
-struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-#endif
-/*****************************************************************************************
-* pwm voltage regulator devices
-******************************************************************************************/
-#if defined (CONFIG_RK29_PWM_REGULATOR)
-
-#define REGULATOR_PWM_ID 2
-#define REGULATOR_PWM_MUX_NAME GPIO2A3_SDMMC0WRITEPRT_PWM2_NAME
-#define REGULATOR_PWM_MUX_MODE GPIO2L_PWM2
-#define REGULATOR_PWM_MUX_MODE_GPIO GPIO2L_GPIO2A3
-#define REGULATOR_PWM_GPIO RK29_PIN2_PA3
-
-static struct regulator_consumer_supply pwm_consumers[] = {
- {
- .supply = "vcore",
- }
-};
-
-static struct regulator_init_data rk29_pwm_regulator_data = {
- .constraints = {
- .name = "PWM2",
- .min_uV = 950000,
- .max_uV = 1400000,
- .apply_uV = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_consumers),
- .consumer_supplies = pwm_consumers,
-};
-
-static struct pwm_platform_data rk29_regulator_pwm_platform_data = {
- .pwm_id = REGULATOR_PWM_ID,
- .pwm_gpio = REGULATOR_PWM_GPIO,
- //.pwm_iomux_name[] = REGULATOR_PWM_MUX_NAME;
- .pwm_iomux_name = REGULATOR_PWM_MUX_NAME,
- .pwm_iomux_pwm = REGULATOR_PWM_MUX_MODE,
- .pwm_iomux_gpio = REGULATOR_PWM_MUX_MODE_GPIO,
- .init_data = &rk29_pwm_regulator_data,
-};
-
-static struct platform_device rk29_device_pwm_regulator = {
- .name = "pwm-voltage-regulator",
- .id = -1,
- .dev = {
- .platform_data = &rk29_regulator_pwm_platform_data,
- },
-};
-
-#endif
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
-#define SDMMC0_WRITE_PROTECT_PIN RK29_PIN6_PB0 //According to your own project to set the value of write-protect-pin.
-#endif
-
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
-#define SDMMC1_WRITE_PROTECT_PIN RK29_PIN6_PB0 //According to your own project to set the value of write-protect-pin.
-#endif
-
-/*****************************************************************************************
- * SDMMC devices
-*****************************************************************************************/
-#if !defined(CONFIG_SDMMC_RK29_OLD)
-static void rk29_sdmmc_gpio_open(int device_id, int on)
-{
- switch(device_id)
- {
- case 0://mmc0
- {
- #ifdef CONFIG_SDMMC0_RK29
- if(on)
- {
- gpio_direction_output(RK29_PIN1_PD0,GPIO_HIGH);//set mmc0-clk to high
- gpio_direction_output(RK29_PIN1_PD1,GPIO_HIGH);//set mmc0-cmd to high.
- gpio_direction_output(RK29_PIN1_PD2,GPIO_HIGH);//set mmc0-data0 to high.
- gpio_direction_output(RK29_PIN1_PD3,GPIO_HIGH);//set mmc0-data1 to high.
- gpio_direction_output(RK29_PIN1_PD4,GPIO_HIGH);//set mmc0-data2 to high.
- gpio_direction_output(RK29_PIN1_PD5,GPIO_HIGH);//set mmc0-data3 to high.
-
- mdelay(30);
- }
- else
- {
- rk29_mux_api_set(GPIO1D0_SDMMC0CLKOUT_NAME, GPIO1H_GPIO1_D0);
- gpio_request(RK29_PIN1_PD0, "mmc0-clk");
- gpio_direction_output(RK29_PIN1_PD0,GPIO_LOW);//set mmc0-clk to low.
-
- rk29_mux_api_set(GPIO1D1_SDMMC0CMD_NAME, GPIO1H_GPIO1_D1);
- gpio_request(RK29_PIN1_PD1, "mmc0-cmd");
- gpio_direction_output(RK29_PIN1_PD1,GPIO_LOW);//set mmc0-cmd to low.
-
- rk29_mux_api_set(GPIO1D2_SDMMC0DATA0_NAME, GPIO1H_GPIO1D2);
- gpio_request(RK29_PIN1_PD2, "mmc0-data0");
- gpio_direction_output(RK29_PIN1_PD2,GPIO_LOW);//set mmc0-data0 to low.
-
- rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_GPIO1D3);
- gpio_request(RK29_PIN1_PD3, "mmc0-data1");
- gpio_direction_output(RK29_PIN1_PD3,GPIO_LOW);//set mmc0-data1 to low.
-
- rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_GPIO1D4);
- gpio_request(RK29_PIN1_PD4, "mmc0-data2");
- gpio_direction_output(RK29_PIN1_PD4,GPIO_LOW);//set mmc0-data2 to low.
-
- rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_GPIO1D5);
- gpio_request(RK29_PIN1_PD5, "mmc0-data3");
- gpio_direction_output(RK29_PIN1_PD5,GPIO_LOW);//set mmc0-data3 to low.
-
- mdelay(30);
- }
- #endif
- }
- break;
-
- case 1://mmc1
- {
- #ifdef CONFIG_SDMMC1_RK29
- if(on)
- {
- gpio_direction_output(RK29_PIN1_PC7,GPIO_HIGH);//set mmc1-clk to high
- gpio_direction_output(RK29_PIN1_PC2,GPIO_HIGH);//set mmc1-cmd to high.
- gpio_direction_output(RK29_PIN1_PC3,GPIO_HIGH);//set mmc1-data0 to high.
- gpio_direction_output(RK29_PIN1_PC4,GPIO_HIGH);//set mmc1-data1 to high.
- gpio_direction_output(RK29_PIN1_PC5,GPIO_HIGH);//set mmc1-data2 to high.
- gpio_direction_output(RK29_PIN1_PC6,GPIO_HIGH);//set mmc1-data3 to high.
- mdelay(100);
- }
- else
- {
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_GPIO1C7);
- gpio_request(RK29_PIN1_PC7, "mmc1-clk");
- gpio_direction_output(RK29_PIN1_PC7,GPIO_LOW);//set mmc1-clk to low.
-
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_GPIO1C2);
- gpio_request(RK29_PIN1_PC2, "mmc1-cmd");
- gpio_direction_output(RK29_PIN1_PC2,GPIO_LOW);//set mmc1-cmd to low.
-
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_GPIO1C3);
- gpio_request(RK29_PIN1_PC3, "mmc1-data0");
- gpio_direction_output(RK29_PIN1_PC3,GPIO_LOW);//set mmc1-data0 to low.
-
- mdelay(100);
- }
- #endif
- }
- break;
-
- case 2: //mmc2
- break;
-
- default:
- break;
- }
-}
-
-static void rk29_sdmmc_set_iomux_mmc0(unsigned int bus_width)
-{
- switch (bus_width)
- {
-
- case 1://SDMMC_CTYPE_4BIT:
- {
- rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_SDMMC0_DATA1);
- rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_SDMMC0_DATA2);
- rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_SDMMC0_DATA3);
- }
- break;
-
- case 0x10000://SDMMC_CTYPE_8BIT:
- break;
- case 0xFFFF: //gpio_reset
- {
- rk29_mux_api_set(GPIO5D5_SDMMC0PWREN_NAME, GPIO5H_GPIO5D5);
- gpio_request(RK29_PIN5_PD5,"sdmmc-power");
- gpio_direction_output(RK29_PIN5_PD5,GPIO_HIGH); //power-off
-
- rk29_sdmmc_gpio_open(0, 0);
-
- gpio_direction_output(RK29_PIN5_PD5,GPIO_LOW); //power-on
-
- rk29_sdmmc_gpio_open(0, 1);
- }
- break;
-
- default: //case 0://SDMMC_CTYPE_1BIT:
- {
- rk29_mux_api_set(GPIO1D1_SDMMC0CMD_NAME, GPIO1H_SDMMC0_CMD);
- rk29_mux_api_set(GPIO1D0_SDMMC0CLKOUT_NAME, GPIO1H_SDMMC0_CLKOUT);
- rk29_mux_api_set(GPIO1D2_SDMMC0DATA0_NAME, GPIO1H_SDMMC0_DATA0);
-
- rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_GPIO1D3);
- gpio_request(RK29_PIN1_PD3, "mmc0-data1");
- gpio_direction_output(RK29_PIN1_PD3,GPIO_HIGH);
-
- rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_GPIO1D4);
- gpio_request(RK29_PIN1_PD4, "mmc0-data2");
- gpio_direction_output(RK29_PIN1_PD4,GPIO_HIGH);
-
- rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_GPIO1D5);
- gpio_request(RK29_PIN1_PD5, "mmc0-data3");
- gpio_direction_output(RK29_PIN1_PD5,GPIO_HIGH);
- }
- break;
- }
-}
-
-static void rk29_sdmmc_set_iomux_mmc1(unsigned int bus_width)
-{
-#if 0
- switch (bus_width)
- {
-
- case 1://SDMMC_CTYPE_4BIT:
- {
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);
- rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_SDMMC1_DATA1);
- rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_SDMMC1_DATA2);
- rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_SDMMC1_DATA3);
- }
- break;
-
- case 0x10000://SDMMC_CTYPE_8BIT:
- break;
- case 0xFFFF:
- {
- rk29_sdmmc_gpio_open(1, 0);
- rk29_sdmmc_gpio_open(1, 1);
- }
- break;
-
- default: //case 0://SDMMC_CTYPE_1BIT:
- {
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);
-
- rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_GPIO1C4);
- gpio_request(RK29_PIN1_PC4, "mmc1-data1");
- gpio_direction_output(RK29_PIN1_PC4,GPIO_HIGH);
-
- rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_GPIO1C5);
- gpio_request(RK29_PIN1_PC5, "mmc1-data2");
- gpio_direction_output(RK29_PIN1_PC5,GPIO_HIGH);
-
- rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_GPIO1C6);
- gpio_request(RK29_PIN1_PC6, "mmc1-data3");
- gpio_direction_output(RK29_PIN1_PC6,GPIO_HIGH);
-
- }
- break;
- }
-#else
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);
- rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_SDMMC1_DATA1);
- rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_SDMMC1_DATA2);
- rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_SDMMC1_DATA3);
-
-#endif
-}
-
-static void rk29_sdmmc_set_iomux_mmc2(unsigned int bus_width)
-{
- ;//
-}
-
-
-static void rk29_sdmmc_set_iomux(int device_id, unsigned int bus_width)
-{
- switch(device_id)
- {
- case 0:
- #ifdef CONFIG_SDMMC0_RK29
- rk29_sdmmc_set_iomux_mmc0(bus_width);
- #endif
- break;
- case 1:
- #ifdef CONFIG_SDMMC1_RK29
- rk29_sdmmc_set_iomux_mmc1(bus_width);
- #endif
- break;
- case 2:
- rk29_sdmmc_set_iomux_mmc2(bus_width);
- break;
- default:
- break;
- }
-}
-
-#endif
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
-static int rk29sdk_wifi_status(struct device *dev);
-static int rk29sdk_wifi_status_register(void (*callback)(int card_presend, void *dev_id), void *dev_id);
-#endif
-#if defined(CONFIG_MU509)
-static int mu509_io_init(void)
-{
-
- return 0;
-}
-
-static int mu509_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mu509_data rk29_mu509_info = {
- .io_init = mu509_io_init,
- .io_deinit = mu509_io_deinit,
- .modem_power_en = RK29_PIN6_PC2,
- .bp_power = RK29_PIN6_PB1,//RK29_PIN0_PB4,
- .bp_power_active_low = 1,
- .bp_reset = RK29_PIN6_PC7,//RK29_PIN0_PB3,
- .bp_reset_active_low = 1,
- .bp_wakeup_ap = RK29_PIN0_PA4,//RK29_PIN0_PC2,
- .ap_wakeup_bp = RK29_PIN2_PB3,//RK29_PIN0_PB0,
-};
-struct platform_device rk29_device_mu509 = {
- .name = "mu509",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mu509_info,
- }
- };
-#endif
-/*****************************************************************************************
- * SDMMC devices
-*****************************************************************************************/
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- rk29_mux_api_set(GPIO1D1_SDMMC0CMD_NAME, GPIO1H_SDMMC0_CMD);
- rk29_mux_api_set(GPIO1D0_SDMMC0CLKOUT_NAME, GPIO1H_SDMMC0_CLKOUT);
- rk29_mux_api_set(GPIO1D2_SDMMC0DATA0_NAME, GPIO1H_SDMMC0_DATA0);
- rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_SDMMC0_DATA1);
- rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_SDMMC0_DATA2);
- rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_SDMMC0_DATA3);
-
- rk29_mux_api_set(GPIO2A2_SDMMC0DETECTN_NAME, GPIO2L_GPIO2A2);
-
- rk29_mux_api_set(GPIO5D5_SDMMC0PWREN_NAME, GPIO5H_GPIO5D5); ///GPIO5H_SDMMC0_PWR_EN); ///GPIO5H_GPIO5D5);
- gpio_request(RK29_PIN5_PD5,"sdmmc");
-#if 0
- gpio_set_value(RK29_PIN5_PD5,GPIO_HIGH);
- mdelay(100);
- gpio_set_value(RK29_PIN5_PD5,GPIO_LOW);
-#else
- gpio_direction_output(RK29_PIN5_PD5,GPIO_LOW);
-#endif
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- rk29_mux_api_set(GPIO2A2_SDMMC0DETECTN_NAME, GPIO2L_SDMMC0_DETECT_N);//Modifyed by xbw.
-
- #if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN,"sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
- #endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail = (MMC_VDD_25_26|MMC_VDD_26_27|MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30|
- MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33|
- MMC_VDD_33_34|MMC_VDD_34_35| MMC_VDD_35_36),
- .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
- .detect_irq = RK29_PIN2_PA2, // INVALID_GPIO
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
-#else
- .write_prt = INVALID_GPIO,
-#endif
-};
-#endif
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);
- rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_SDMMC1_DATA1);
- rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_SDMMC1_DATA2);
- rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_SDMMC1_DATA3);
- //rk29_mux_api_set(GPIO1C0_UART0CTSN_SDMMC1DETECTN_NAME, GPIO1H_SDMMC1_DETECT_N);
-
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN,"sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-
-
-#define RK29SDK_WIFI_SDIO_CARD_DETECT_N RK29_PIN1_PD6
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail = (MMC_VDD_25_26|MMC_VDD_26_27|MMC_VDD_27_28|MMC_VDD_28_29|
- MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32|
- MMC_VDD_32_33|MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_SDIO_IRQ|
- MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-#if 0
- .detect_irq = RK29SDK_WIFI_SDIO_CARD_DETECT_N,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
-#else
-//for wifi develop board
- .detect_irq = INVALID_GPIO,
- .enable_sd_wakeup = 0,
-#endif
-
-};
-#endif ////endif--#ifdef CONFIG_SDMMC1_RK29
-
-
-int rk29sdk_wifi_power_state = 0;
-int rk29sdk_bt_power_state = 0;
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
-#define RK29SDK_WIFI_BT_GPIO_POWER_N RK29_PIN5_PD6
-#define RK29SDK_WIFI_GPIO_RESET_N RK29_PIN6_PC0
-#define RK29SDK_BT_GPIO_RESET_N RK29_PIN6_PC4
-
-static int rk29sdk_wifi_cd = 0; /* wifi virtual 'card detect' status */
-static void (*wifi_status_cb)(int card_present, void *dev_id);
-static void *wifi_status_cb_devid;
-
-static int rk29sdk_wifi_status(struct device *dev)
-{
- return rk29sdk_wifi_cd;
-}
-
-static int rk29sdk_wifi_status_register(void (*callback)(int card_present, void *dev_id), void *dev_id)
-{
- if(wifi_status_cb)
- return -EAGAIN;
- wifi_status_cb = callback;
- wifi_status_cb_devid = dev_id;
- return 0;
-}
-
-static int rk29sdk_wifi_bt_gpio_control_init(void)
-{
- if (gpio_request(RK29SDK_WIFI_BT_GPIO_POWER_N, "wifi_bt_power")) {
- pr_info("%s: request wifi_bt power gpio failed\n", __func__);
- return -1;
- }
-
- if (gpio_request(RK29SDK_WIFI_GPIO_RESET_N, "wifi reset")) {
- pr_info("%s: request wifi reset gpio failed\n", __func__);
- gpio_free(RK29SDK_WIFI_BT_GPIO_POWER_N);
- return -1;
- }
-
- if (gpio_request(RK29SDK_BT_GPIO_RESET_N, "bt reset")) {
- pr_info("%s: request bt reset gpio failed\n", __func__);
- gpio_free(RK29SDK_WIFI_GPIO_RESET_N);
- return -1;
- }
-
- gpio_direction_output(RK29SDK_WIFI_BT_GPIO_POWER_N, GPIO_LOW);
- gpio_direction_output(RK29SDK_WIFI_GPIO_RESET_N, GPIO_LOW);
- gpio_direction_output(RK29SDK_BT_GPIO_RESET_N, GPIO_LOW);
-
- #if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
-
- rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_GPIO1C4);
- gpio_request(RK29_PIN1_PC4, "mmc1-data1");
- gpio_direction_output(RK29_PIN1_PC4,GPIO_LOW);//set mmc1-data1 to low.
-
- rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_GPIO1C5);
- gpio_request(RK29_PIN1_PC5, "mmc1-data2");
- gpio_direction_output(RK29_PIN1_PC5,GPIO_LOW);//set mmc1-data2 to low.
-
- rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_GPIO1C6);
- gpio_request(RK29_PIN1_PC6, "mmc1-data3");
- gpio_direction_output(RK29_PIN1_PC6,GPIO_LOW);//set mmc1-data3 to low.
-
- rk29_sdmmc_gpio_open(1, 0); //added by xbw at 2011-10-13
- #endif
- pr_info("%s: init finished\n",__func__);
-
- return 0;
-}
-
-static int rk29sdk_wifi_power(int on)
-{
- pr_info("%s: %d\n", __func__, on);
- if (on){
- gpio_set_value(RK29SDK_WIFI_BT_GPIO_POWER_N, GPIO_HIGH);
-
- #if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
- rk29_sdmmc_gpio_open(1, 1); //added by xbw at 2011-10-13
- #endif
-
- gpio_set_value(RK29SDK_WIFI_GPIO_RESET_N, GPIO_HIGH);
- mdelay(100);
- pr_info("wifi turn on power\n");
- }else{
- if (!rk29sdk_bt_power_state){
- gpio_set_value(RK29SDK_WIFI_BT_GPIO_POWER_N, GPIO_LOW);
-
- #if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
- rk29_sdmmc_gpio_open(1, 0); //added by xbw at 2011-10-13
- #endif
-
- mdelay(100);
- pr_info("wifi shut off power\n");
- }else
- {
- pr_info("wifi shouldn't shut off power, bt is using it!\n");
- }
- gpio_set_value(RK29SDK_WIFI_GPIO_RESET_N, GPIO_LOW);
-
- }
-
- rk29sdk_wifi_power_state = on;
- return 0;
-}
-
-static int rk29sdk_wifi_reset_state;
-static int rk29sdk_wifi_reset(int on)
-{
- pr_info("%s: %d\n", __func__, on);
- gpio_set_value(RK29SDK_WIFI_GPIO_RESET_N, on);
- mdelay(100);
- rk29sdk_wifi_reset_state = on;
- return 0;
-}
-
-int rk29sdk_wifi_set_carddetect(int val)
-{
- pr_info("%s:%d\n", __func__, val);
- rk29sdk_wifi_cd = val;
- if (wifi_status_cb){
- wifi_status_cb(val, wifi_status_cb_devid);
- }else {
- pr_warning("%s, nobody to notify\n", __func__);
- }
- return 0;
-}
-EXPORT_SYMBOL(rk29sdk_wifi_set_carddetect);
-
-static struct wifi_mem_prealloc wifi_mem_array[PREALLOC_WLAN_SEC_NUM] = {
- {NULL, (WLAN_SECTION_SIZE_0 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_1 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_2 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_3 + PREALLOC_WLAN_SECTION_HEADER)}
-};
-
-static void *rk29sdk_mem_prealloc(int section, unsigned long size)
-{
- if (section == PREALLOC_WLAN_SEC_NUM)
- return wlan_static_skb;
-
- if ((section < 0) || (section > PREALLOC_WLAN_SEC_NUM))
- return NULL;
-
- if (wifi_mem_array[section].size < size)
- return NULL;
-
- return wifi_mem_array[section].mem_ptr;
-}
-
-int __init rk29sdk_init_wifi_mem(void)
-{
- int i;
- int j;
-
- for (i = 0 ; i < WLAN_SKB_BUF_NUM ; i++) {
- wlan_static_skb[i] = dev_alloc_skb(
- ((i < (WLAN_SKB_BUF_NUM / 2)) ? 4096 : 8192));
-
- if (!wlan_static_skb[i])
- goto err_skb_alloc;
- }
-
- for (i = 0 ; i < PREALLOC_WLAN_SEC_NUM ; i++) {
- wifi_mem_array[i].mem_ptr =
- kmalloc(wifi_mem_array[i].size, GFP_KERNEL);
-
- if (!wifi_mem_array[i].mem_ptr)
- goto err_mem_alloc;
- }
- return 0;
-
-err_mem_alloc:
- pr_err("Failed to mem_alloc for WLAN\n");
- for (j = 0 ; j < i ; j++)
- kfree(wifi_mem_array[j].mem_ptr);
-
- i = WLAN_SKB_BUF_NUM;
-
-err_skb_alloc:
- pr_err("Failed to skb_alloc for WLAN\n");
- for (j = 0 ; j < i ; j++)
- dev_kfree_skb(wlan_static_skb[j]);
-
- return -ENOMEM;
-}
-
-static struct wifi_platform_data rk29sdk_wifi_control = {
- .set_power = rk29sdk_wifi_power,
- .set_reset = rk29sdk_wifi_reset,
- .set_carddetect = rk29sdk_wifi_set_carddetect,
- .mem_prealloc = rk29sdk_mem_prealloc,
-};
-static struct platform_device rk29sdk_wifi_device = {
- .name = "bcm4329_wlan",
- .id = 1,
- .dev = {
- .platform_data = &rk29sdk_wifi_control,
- },
-};
-#endif
-
-
-/* bluetooth rfkill device */
-static struct platform_device rk29sdk_rfkill = {
- .name = "rk29sdk_rfkill",
- .id = -1,
-};
-
-
-#ifdef CONFIG_VIVANTE
-#define GPU_HIGH_CLOCK 552
-#define GPU_LOW_CLOCK (periph_pll_default / 1000000) /* same as general pll clock rate below */
-static struct resource resources_gpu[] = {
- [0] = {
- .name = "gpu_irq",
- .start = IRQ_GPU,
- .end = IRQ_GPU,
- .flags = IORESOURCE_IRQ,
- },
- [1] = {
- .name = "gpu_base",
- .start = RK29_GPU_PHYS,
- .end = RK29_GPU_PHYS + RK29_GPU_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "gpu_mem",
- .start = PMEM_GPU_BASE,
- .end = PMEM_GPU_BASE + PMEM_GPU_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [3] = {
- .name = "gpu_clk",
- .start = GPU_LOW_CLOCK,
- .end = GPU_HIGH_CLOCK,
- .flags = IORESOURCE_IO,
- },
-};
-static struct platform_device rk29_device_gpu = {
- .name = "galcore",
- .id = 0,
- .num_resources = ARRAY_SIZE(resources_gpu),
- .resource = resources_gpu,
-};
-#endif
-#ifdef CONFIG_KEYS_RK29
-extern struct rk29_keys_platform_data rk29_keys_pdata;
-static struct platform_device rk29_device_keys = {
- .name = "rk29-keypad",
- .id = -1,
- .dev = {
- .platform_data = &rk29_keys_pdata,
- },
-};
-#endif
-
-static void __init rk29_board_iomux_init(void)
-{
- int err;
-#ifdef CONFIG_RK29_PWM_REGULATOR
- rk29_mux_api_set(REGULATOR_PWM_MUX_NAME,REGULATOR_PWM_MUX_MODE);
-#endif
-
-#ifdef CONFIG_RK29_CLK_SWITCH_TO_32K
-/****************************clock change********************************************/
- err = gpio_request(RK29_PIN4_PC0, "clk27M_control");
- if (err) {
- gpio_free(RK29_PIN4_PC0);
- printk("-------request RK29_PIN4_PC0 fail--------\n");
- return -1;
- }
- //phy power down
- gpio_direction_output(RK29_PIN4_PC0, GPIO_LOW);// 27M 32K
- gpio_set_value(RK29_PIN4_PC0, GPIO_LOW);
-
- rk29_mux_api_set(GPIO4C5_RMIICSRDVALID_MIIRXDVALID_NAME,GPIO4H_GPIO4C5);
-
- err = gpio_request(RK29_PIN4_PC5, "clk24M_control");
- if (err) {
- gpio_free(RK29_PIN4_PC5);
- printk("-------request RK29_PIN4_PC5 fail--------\n");
- return -1;
- }
- //phy power down
- gpio_direction_output(RK29_PIN4_PC5, GPIO_LOW);// control 24M
- gpio_set_value(RK29_PIN4_PC5, GPIO_LOW);
-/*******************************************************************/
-#endif
-}
-
-static struct platform_device *devices[] __initdata = {
-
-#ifdef CONFIG_RK29_WATCHDOG
- &rk29_device_wdt,
-#endif
-
-#ifdef CONFIG_UART1_RK29
- &rk29_device_uart1,
-#endif
-#ifdef CONFIG_UART0_RK29
- &rk29_device_uart0,
-#endif
-#ifdef CONFIG_UART2_RK29
- &rk29_device_uart2,
-#endif
-#ifdef CONFIG_UART3_RK29
- &rk29_device_uart3,
-#endif
-
-#ifdef CONFIG_RK29_PWM_REGULATOR
- &rk29_device_pwm_regulator,
-#endif
-#ifdef CONFIG_SPIM0_RK29
- &rk29xx_device_spi0m,
-#endif
-#ifdef CONFIG_SPIM1_RK29
- &rk29xx_device_spi1m,
-#endif
-#ifdef CONFIG_ADC_RK29
- &rk29_device_adc,
-#endif
-#ifdef CONFIG_I2C0_RK29
- &rk29_device_i2c0,
-#endif
-#ifdef CONFIG_I2C1_RK29
- &rk29_device_i2c1,
-#endif
-#ifdef CONFIG_I2C2_RK29
- &rk29_device_i2c2,
-#endif
-#ifdef CONFIG_I2C3_RK29
- &rk29_device_i2c3,
-#endif
-
-#ifdef CONFIG_SND_RK29_SOC_I2S_2CH
- &rk29_device_iis_2ch,
-#endif
-#ifdef CONFIG_SND_RK29_SOC_I2S_8CH
- &rk29_device_iis_8ch,
-#endif
-
-#ifdef CONFIG_KEYS_RK29
- &rk29_device_keys,
-#endif
-#ifdef CONFIG_SDMMC0_RK29
- &rk29_device_sdmmc0,
-#endif
-#ifdef CONFIG_SDMMC1_RK29
- &rk29_device_sdmmc1,
-#endif
-
-#ifdef CONFIG_MTD_NAND_RK29XX
- &rk29xx_device_nand,
-#endif
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- &rk29sdk_wifi_device,
-#endif
-
-#ifdef CONFIG_BT
- &rk29sdk_rfkill,
-#endif
-
-#if defined(CONFIG_MU509)
- &rk29_device_mu509,
-#endif
-#ifdef CONFIG_MTD_NAND_RK29
- &rk29_device_nand,
-#endif
-
-#ifdef CONFIG_FB_RK29
- &rk29_device_fb,
- &rk29_device_dma_cpy,
-#endif
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- &rk29_device_backlight,
-#endif
-#ifdef CONFIG_RK29_VMAC
- &rk29_device_vmac,
-#endif
-#ifdef CONFIG_VIVANTE
- &rk29_device_gpu,
-#endif
-#ifdef CONFIG_VIDEO_RK29
- &rk29_device_camera, /* ddl@rock-chips.com : camera support */
- #if (CONFIG_SENSOR_IIC_ADDR_0 != 0x00)
- &rk29_soc_camera_pdrv_0,
- #endif
- &rk29_soc_camera_pdrv_1,
- &android_pmem_cam_device,
-#endif
-#if PMEM_SKYPE_SIZE > 0
- &android_pmem_skype_device,
-#endif
-#ifdef CONFIG_ION
- &rk29_ion_device,
-#endif
- &android_pmem_device,
- &rk29_vpu_mem_device,
-#ifdef CONFIG_USB20_OTG
- &rk29_device_usb20_otg,
-#endif
-#ifdef CONFIG_USB20_HOST
- &rk29_device_usb20_host,
-#endif
-#ifdef CONFIG_USB11_HOST
- &rk29_device_usb11_host,
-#endif
-#ifdef CONFIG_USB_ANDROID
- &android_usb_device,
- &usb_mass_storage_device,
-#endif
-#ifdef CONFIG_RK29_IPP
- &rk29_device_ipp,
-#endif
-#ifdef CONFIG_VIDEO_RK29XX_VOUT
- &rk29_v4l2_output_devce,
-#endif
-#ifdef CONFIG_RK_HEADSET_DET
- &rk_device_headset,
-#endif
-
-};
-
-/*****************************************************************************************
- * spi devices
- * author: cmc@rock-chips.com
- *****************************************************************************************/
-static int rk29_vmac_register_set(void)
-{
- //config rk29 vmac as rmii, 100MHz
- u32 value= readl(RK29_GRF_BASE + 0xbc);
- value = (value & 0xfff7ff) | (0x400);
- writel(value, RK29_GRF_BASE + 0xbc);
- return 0;
-}
-
-static int rk29_rmii_io_init(void)
-{
- int err;
-
- //phy power gpio
- err = gpio_request(RK29_PIN6_PB0, "phy_power_en");
- if (err) {
- gpio_free(RK29_PIN6_PB0);
- printk("-------request RK29_PIN6_PB0 fail--------\n");
- return -1;
- }
- //phy power down
- gpio_direction_output(RK29_PIN6_PB0, GPIO_LOW);
- gpio_set_value(RK29_PIN6_PB0, GPIO_LOW);
-
- return 0;
-}
-
-static int rk29_rmii_io_deinit(void)
-{
- //phy power down
- gpio_direction_output(RK29_PIN6_PB0, GPIO_LOW);
- gpio_set_value(RK29_PIN6_PB0, GPIO_LOW);
- //free
- gpio_free(RK29_PIN6_PB0);
- return 0;
-}
-
-static int rk29_rmii_power_control(int enable)
-{
- if (enable) {
- //enable phy power
- gpio_direction_output(RK29_PIN6_PB0, GPIO_HIGH);
- gpio_set_value(RK29_PIN6_PB0, GPIO_HIGH);
- }
- else {
- gpio_direction_output(RK29_PIN6_PB0, GPIO_LOW);
- gpio_set_value(RK29_PIN6_PB0, GPIO_LOW);
- }
- return 0;
-}
-
-struct rk29_vmac_platform_data rk29_vmac_pdata = {
- .vmac_register_set = rk29_vmac_register_set,
- .rmii_io_init = rk29_rmii_io_init,
- .rmii_io_deinit = rk29_rmii_io_deinit,
- .rmii_power_control = rk29_rmii_power_control,
-};
-
-/*****************************************************************************************
- * spi devices
- * author: cmc@rock-chips.com
- *****************************************************************************************/
-#define SPI_CHIPSELECT_NUM 2
-static struct spi_cs_gpio rk29xx_spi0_cs_gpios[SPI_CHIPSELECT_NUM] = {
- {
- .name = "spi0 cs0",
- .cs_gpio = RK29_PIN2_PC1,
- .cs_iomux_name = GPIO2C1_SPI0CSN0_NAME,
- .cs_iomux_mode = GPIO2H_SPI0_CSN0,
- },
- {
- .name = "spi0 cs1",
- .cs_gpio = RK29_PIN1_PA4,
- .cs_iomux_name = GPIO1A4_EMMCWRITEPRT_SPI0CS1_NAME,//if no iomux,set it NULL
- .cs_iomux_mode = GPIO1L_SPI0_CSN1,
- }
-};
-
-static struct spi_cs_gpio rk29xx_spi1_cs_gpios[SPI_CHIPSELECT_NUM] = {
- {
- .name = "spi1 cs0",
- .cs_gpio = RK29_PIN2_PC5,
- .cs_iomux_name = GPIO2C5_SPI1CSN0_NAME,
- .cs_iomux_mode = GPIO2H_SPI1_CSN0,
- },
- {
- .name = "spi1 cs1",
- .cs_gpio = RK29_PIN1_PA3,
- .cs_iomux_name = GPIO1A3_EMMCDETECTN_SPI1CS1_NAME,//if no iomux,set it NULL
- .cs_iomux_mode = GPIO1L_SPI1_CSN1,
- }
-};
-
-static int spi_io_init(struct spi_cs_gpio *cs_gpios, int cs_num)
-{
-#if 1
- int i;
- if (cs_gpios) {
- for (i=0; i<cs_num; i++) {
- rk29_mux_api_set(cs_gpios[i].cs_iomux_name, cs_gpios[i].cs_iomux_mode);
- }
- }
-#endif
- return 0;
-}
-
-static int spi_io_deinit(struct spi_cs_gpio *cs_gpios, int cs_num)
-{
- return 0;
-}
-
-static int spi_io_fix_leakage_bug(void)
-{
-#if 0
- gpio_direction_output(RK29_PIN2_PC1, GPIO_LOW);
-#endif
- return 0;
-}
-
-static int spi_io_resume_leakage_bug(void)
-{
-#if 0
- gpio_direction_output(RK29_PIN2_PC1, GPIO_HIGH);
-#endif
- return 0;
-}
-
-struct rk29xx_spi_platform_data rk29xx_spi0_platdata = {
- .num_chipselect = SPI_CHIPSELECT_NUM,
- .chipselect_gpios = rk29xx_spi0_cs_gpios,
- .io_init = spi_io_init,
- .io_deinit = spi_io_deinit,
- .io_fix_leakage_bug = spi_io_fix_leakage_bug,
- .io_resume_leakage_bug = spi_io_resume_leakage_bug,
-};
-
-struct rk29xx_spi_platform_data rk29xx_spi1_platdata = {
- .num_chipselect = SPI_CHIPSELECT_NUM,
- .chipselect_gpios = rk29xx_spi1_cs_gpios,
- .io_init = spi_io_init,
- .io_deinit = spi_io_deinit,
- .io_fix_leakage_bug = spi_io_fix_leakage_bug,
- .io_resume_leakage_bug = spi_io_resume_leakage_bug,
-};
-
-/*****************************************************************************************
- * xpt2046 touch panel
- * author: cmc@rock-chips.com
- *****************************************************************************************/
-#define XPT2046_GPIO_INT RK29_PIN0_PA3
-#define DEBOUNCE_REPTIME 3
-
-#if defined(CONFIG_TOUCHSCREEN_XPT2046_320X480_SPI)
-static struct xpt2046_platform_data xpt2046_info = {
- .model = 2046,
- .keep_vref_on = 1,
- .swap_xy = 0,
- .x_min = 0,
- .x_max = 320,
- .y_min = 0,
- .y_max = 480,
- .debounce_max = 7,
- .debounce_rep = DEBOUNCE_REPTIME,
- .debounce_tol = 20,
- .gpio_pendown = XPT2046_GPIO_INT,
- .penirq_recheck_delay_usecs = 1,
-};
-#elif defined(CONFIG_TOUCHSCREEN_XPT2046_320X480_CBN_SPI)
-static struct xpt2046_platform_data xpt2046_info = {
- .model = 2046,
- .keep_vref_on = 1,
- .swap_xy = 0,
- .x_min = 0,
- .x_max = 320,
- .y_min = 0,
- .y_max = 480,
- .debounce_max = 7,
- .debounce_rep = DEBOUNCE_REPTIME,
- .debounce_tol = 20,
- .gpio_pendown = XPT2046_GPIO_INT,
- .penirq_recheck_delay_usecs = 1,
-};
-#elif defined(CONFIG_TOUCHSCREEN_XPT2046_SPI)
-static struct xpt2046_platform_data xpt2046_info = {
- .model = 2046,
- .keep_vref_on = 1,
- .swap_xy = 1,
- .x_min = 0,
- .x_max = 800,
- .y_min = 0,
- .y_max = 480,
- .debounce_max = 7,
- .debounce_rep = DEBOUNCE_REPTIME,
- .debounce_tol = 20,
- .gpio_pendown = XPT2046_GPIO_INT,
-
- .penirq_recheck_delay_usecs = 1,
-};
-#elif defined(CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI)
-static struct xpt2046_platform_data xpt2046_info = {
- .model = 2046,
- .keep_vref_on = 1,
- .swap_xy = 1,
- .x_min = 0,
- .x_max = 800,
- .y_min = 0,
- .y_max = 480,
- .debounce_max = 7,
- .debounce_rep = DEBOUNCE_REPTIME,
- .debounce_tol = 20,
- .gpio_pendown = XPT2046_GPIO_INT,
-
- .penirq_recheck_delay_usecs = 1,
-};
-#endif
-
-static struct spi_board_info board_spi_devices[] = {
-#if defined(CONFIG_TOUCHSCREEN_XPT2046_320X480_SPI) || defined(CONFIG_TOUCHSCREEN_XPT2046_320X480_CBN_SPI)\
- ||defined(CONFIG_TOUCHSCREEN_XPT2046_SPI) || defined(CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI)
- {
- .modalias = "xpt2046_ts",
- .chip_select = 0,
- .max_speed_hz = 125 * 1000 * 26,/* (max sample rate @ 3V) * (cmd + data + overhead) */
- .bus_num = 0,
- .irq = XPT2046_GPIO_INT,
- .platform_data = &xpt2046_info,
- },
-#endif
-};
-
-
-static void __init rk29_gic_init_irq(void)
-{
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38))
- gic_init(0, 32, (void __iomem *)RK29_GICPERI_BASE, (void __iomem *)RK29_GICCPU_BASE);
-#else
- gic_dist_init(0, (void __iomem *)RK29_GICPERI_BASE, 32);
- gic_cpu_init(0, (void __iomem *)RK29_GICCPU_BASE);
-#endif
-}
-
-static void __init machine_rk29_init_irq(void)
-{
- rk29_gic_init_irq();
- rk29_gpio_init();
-}
-
-static struct cpufreq_frequency_table freq_table[] = {
- { .index = 1200000, .frequency = 408000 },
- { .index = 1200000, .frequency = 816000 },
- { .index = 1300000, .frequency = 1008000 },
- { .frequency = CPUFREQ_TABLE_END },
-};
-
-static void __init machine_rk29_board_init(void)
-{
- rk29_board_iomux_init();
-
- board_power_init();
- board_update_cpufreq_table(freq_table);
-
- platform_add_devices(devices, ARRAY_SIZE(devices));
-#ifdef CONFIG_I2C0_RK29
- i2c_register_board_info(default_i2c0_data.bus_num, board_i2c0_devices,
- ARRAY_SIZE(board_i2c0_devices));
-#endif
-#ifdef CONFIG_I2C1_RK29
- i2c_register_board_info(default_i2c1_data.bus_num, board_i2c1_devices,
- ARRAY_SIZE(board_i2c1_devices));
-#endif
-#ifdef CONFIG_I2C2_RK29
- i2c_register_board_info(default_i2c2_data.bus_num, board_i2c2_devices,
- ARRAY_SIZE(board_i2c2_devices));
-#endif
-#ifdef CONFIG_I2C3_RK29
- i2c_register_board_info(default_i2c3_data.bus_num, board_i2c3_devices,
- ARRAY_SIZE(board_i2c3_devices));
-#endif
-
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- rk29sdk_wifi_bt_gpio_control_init();
- rk29sdk_init_wifi_mem();
-#endif
-
- board_usb_detect_init(RK29_PIN0_PA0);
-}
-
-static void __init machine_rk29_fixup(struct machine_desc *desc, struct tag *tags,
- char **cmdline, struct meminfo *mi)
-{
- mi->nr_banks = 1;
- mi->bank[0].start = RK29_SDRAM_PHYS;
- mi->bank[0].size = LINUX_SIZE;
-#if SDRAM_SIZE > SZ_512M
- mi->nr_banks = 2;
- mi->bank[1].start = RK29_SDRAM_PHYS + SZ_512M;
- mi->bank[1].size = SDRAM_SIZE - SZ_512M;
-#endif
-}
-
-static void __init machine_rk29_mapio(void)
-{
- rk29_map_common_io();
- rk29_setup_early_printk();
- rk29_sram_init();
- rk29_clock_init(periph_pll_default);
- rk29_iomux_init();
- ddr_init(DDR_TYPE,DDR_FREQ); // DDR3_1333H, 400
-}
-
-MACHINE_START(RK29, "RK29board")
- /* UART for LL DEBUG */
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 37))
- /* UART for LL DEBUG */
- .phys_io = RK29_UART1_PHYS & 0xfff00000,
- .io_pg_offst = ((RK29_UART1_BASE) >> 18) & 0xfffc,
-#endif
- .boot_params = RK29_SDRAM_PHYS + 0x88000,
- .fixup = machine_rk29_fixup,
- .map_io = machine_rk29_mapio,
- .init_irq = machine_rk29_init_irq,
- .init_machine = machine_rk29_board_init,
- .timer = &rk29_timer,
-MACHINE_END
+++ /dev/null
-#include <mach/key.h>
-#include <mach/gpio.h>
-#include <mach/board.h>
-
-#define EV_ENCALL KEY_F4
-#define EV_MENU KEY_F1
-
-#define PRESS_LEV_LOW 1
-#define PRESS_LEV_HIGH 0
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "menu",
- .code = EV_MENU,
- .gpio = RK29_PIN6_PA0,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .gpio = RK29_PIN6_PA1,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .gpio = RK29_PIN6_PA2,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .gpio = RK29_PIN6_PA3,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "search",
- .code = KEY_SEARCH,
- .gpio = RK29_PIN6_PA4,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .gpio = RK29_PIN6_PA5,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "sensor",
- .code = KEY_CAMERA,
- .gpio = RK29_PIN6_PA6,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK29_PIN6_PA7,
- .active_low = PRESS_LEV_LOW,
- //.code_long_press = EV_ENCALL,
- .wakeup = 1,
- },
-#if 0
- {
- .desc = "vol+",
- .code = KEY_VOLUMEDOWN,
- .adc_value = 95,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEUP,
- .adc_value = 249,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "menu",
- .code = EV_MENU,
- .adc_value = 406,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .code_long_press = KEY_F4,
- .adc_value = 561,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_ESC,
- .adc_value = 726,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "adkey6",
- .code = KEY_BACK,
- .code_long_press = EV_ENCALL,
- .adc_value = 899,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-#endif
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = -1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
+++ /dev/null
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/pm.h>
-
-#include <mach/rk29_iomap.h>
-#include <mach/gpio.h>
-#include <mach/cru.h>
-
-#define POWER_ON_PIN RK29_PIN4_PA4
-#define PLAY_ON_PIN RK29_PIN6_PA7
-
-static void rk29_pm_power_off(void)
-{
- int count = 0;
-
- local_irq_disable();
- local_fiq_disable();
-
- printk(KERN_ERR "rk29_pm_power_off start...\n");
-
- /* arm enter slow mode */
- cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_SLOW, CRU_MODE_CON);
- LOOP(LOOPS_PER_USEC);
-
- while (1) {
- /* shut down the power by GPIO. */
- if (gpio_get_value(POWER_ON_PIN) == GPIO_HIGH) {
- printk("POWER_ON_PIN is high\n");
- gpio_set_value(POWER_ON_PIN, GPIO_LOW);
- }
-
- LOOP(5 * LOOPS_PER_MSEC);
-
- /* only normal power off can restart system safely */
- if (system_state != SYSTEM_POWER_OFF)
- continue;
-
- if (gpio_get_value(PLAY_ON_PIN) != GPIO_HIGH) {
- if (!count)
- printk("PLAY_ON_PIN is low\n");
- if (50 == count) /* break if keep low about 250ms */
- break;
- count++;
- } else {
- count = 0;
- }
- }
-
- printk("system reboot\n");
- gpio_set_value(POWER_ON_PIN, GPIO_HIGH);
- system_state = SYSTEM_RESTART;
- arm_pm_restart(0, NULL);
-
- while (1);
-}
-
-int __init board_power_init(void)
-{
- gpio_request(POWER_ON_PIN, "poweronpin");
- gpio_set_value(POWER_ON_PIN, GPIO_HIGH);
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
- pm_power_off = rk29_pm_power_off;
-
- return 0;
-}
-
+++ /dev/null
-/*
- * Copyright (C) 2010 ROCKCHIP, Inc.
- * Author: roger_chen <cz@rock-chips.com>
- *
- * This program is the bluetooth device bcm4329's driver,
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/module.h>
-#include <linux/device.h>
-#include <linux/rfkill.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/interrupt.h>
-#include <linux/wakelock.h>
-#include <linux/fs.h>
-#include <asm/uaccess.h>
-#include <mach/gpio.h>
-#include <asm/irq.h>
-#include <mach/iomux.h>
-#include <linux/wakelock.h>
-#include <linux/timer.h>
-#include <mach/board.h>
-
-#if 0
-#define DBG(x...) printk(KERN_INFO x)
-#else
-#define DBG(x...)
-#endif
-
-#ifdef CONFIG_BCM4329
-#define WIFI_BT_POWER_TOGGLE 1
-#else
-#define WIFI_BT_POWER_TOGGLE 0
-#endif
-
-#define BT_WAKE_LOCK_TIMEOUT 10 //s
-
-#define BT_AUTO_SLEEP_TIMEOUT 3
-
-/*
- * IO Configuration for RK29
- */
-#ifdef CONFIG_ARCH_RK29
-
-#define BT_WAKE_HOST_SUPPORT 0
-
-/* IO configuration */
-// BT power pin
-#define BT_GPIO_POWER RK29_PIN5_PD6
-#define IOMUX_BT_GPIO_POWER() rk29_mux_api_set(GPIO5D6_SDMMC1PWREN_NAME, GPIO5H_GPIO5D6);
-
-// BT reset pin
-#define BT_GPIO_RESET RK29_PIN6_PC4
-#define IOMUX_BT_GPIO_RESET()
-
-// BT wakeup pin
-#define BT_GPIO_WAKE_UP RK29_PIN6_PC5
-#define IOMUX_BT_GPIO_WAKE_UP()
-
-// BT wakeup host pin
-#define BT_GPIO_WAKE_UP_HOST
-#define IOMUX_BT_GPIO_WAKE_UP_HOST()
-
-//bt cts paired to uart rts
-#define UART_RTS RK29_PIN2_PA7
-#define IOMUX_UART_RTS_GPIO() rk29_mux_api_set(GPIO2A7_UART2RTSN_NAME, GPIO2L_GPIO2A7)
-#define IOMUX_UART_RTS() rk29_mux_api_set(GPIO2A7_UART2RTSN_NAME, GPIO2L_UART2_RTS_N)
-
-/*
- * IO Configuration for RK30
- */
-#elif defined (CONFIG_ARCH_RK30)
-
-#define BT_WAKE_HOST_SUPPORT 1
-
-/* IO configuration */
-// BT power pin
-#define BT_GPIO_POWER RK30_PIN3_PC7
-#define IOMUX_BT_GPIO_POWER() rk29_mux_api_set(GPIO3C7_SDMMC1WRITEPRT_NAME, GPIO3C_GPIO3C7);
-
-// BT reset pin
-#define BT_GPIO_RESET RK30_PIN3_PD1
-#define IOMUX_BT_GPIO_RESET() rk29_mux_api_set(GPIO3D1_SDMMC1BACKENDPWR_NAME, GPIO3D_GPIO3D1);
-
-// BT wakeup pin
-#define BT_GPIO_WAKE_UP RK30_PIN3_PC6
-#define IOMUX_BT_GPIO_WAKE_UP() rk29_mux_api_set(GPIO3C6_SDMMC1DETECTN_NAME, GPIO3C_GPIO3C6);
-
-// BT wakeup host pin
-#define BT_GPIO_WAKE_UP_HOST RK30_PIN6_PA7
-#define IOMUX_BT_GPIO_WAKE_UP_HOST()
-
-//bt cts paired to uart rts
-#define UART_RTS RK30_PIN1_PA3
-#define IOMUX_UART_RTS_GPIO() rk29_mux_api_set(GPIO1A3_UART0RTSN_NAME, GPIO1A_GPIO1A3)
-#define IOMUX_UART_RTS() rk29_mux_api_set(GPIO1A3_UART0RTSN_NAME, GPIO1A_UART0_RTS_N)
-
-#endif
-
-struct bt_ctrl
-{
- struct rfkill *bt_rfk;
-#if BT_WAKE_HOST_SUPPORT
- struct timer_list tl;
- bool b_HostWake;
- struct wake_lock bt_wakelock;
-#endif
-};
-
-static const char bt_name[] =
-#if defined(CONFIG_RKWIFI)
- #if defined(CONFIG_RKWIFI_26M)
- "rk903_26M"
- #else
- "rk903"
- #endif
-#elif defined(CONFIG_BCM4329)
- "bcm4329"
-#elif defined(CONFIG_MV8787)
- "mv8787"
-#else
- "bt_default"
-#endif
-;
-
-#if WIFI_BT_POWER_TOGGLE
-extern int rk29sdk_bt_power_state;
-extern int rk29sdk_wifi_power_state;
-#endif
-
-struct bt_ctrl gBtCtrl;
-struct timer_list bt_sleep_tl;
-
-
-#if BT_WAKE_HOST_SUPPORT
-void resetBtHostSleepTimer(void)
-{
- mod_timer(&(gBtCtrl.tl),jiffies + BT_WAKE_LOCK_TIMEOUT*HZ);//ÔÙÖØÐÂÉèÖó¬Ê±Öµ¡£
-}
-
-void btWakeupHostLock(void)
-{
- if(gBtCtrl.b_HostWake == false){
- DBG("*************************Lock\n");
- wake_lock(&(gBtCtrl.bt_wakelock));
- gBtCtrl.b_HostWake = true;
- }
-}
-
-void btWakeupHostUnlock(void)
-{
- if(gBtCtrl.b_HostWake == true){
- DBG("*************************UnLock\n");
- wake_unlock(&(gBtCtrl.bt_wakelock)); //ÈÃϵͳ˯Ãß
- gBtCtrl.b_HostWake = false;
- }
-}
-
-static void timer_hostSleep(unsigned long arg)
-{
- DBG("%s---b_HostWake=%d\n",__FUNCTION__,gBtCtrl.b_HostWake);
- btWakeupHostUnlock();
-}
-
-void bcm4325_sleep(unsigned long bSleep);
-
-#ifdef CONFIG_PM
-static void rfkill_do_wakeup(struct work_struct *work)
-{
- DBG("Enable UART_RTS\n");
- gpio_set_value(UART_RTS, GPIO_LOW);
- IOMUX_UART_RTS();
-}
-
-static DECLARE_DELAYED_WORK(wakeup_work, rfkill_do_wakeup);
-
-static int bcm4329_rfkill_suspend(struct platform_device *pdev, pm_message_t state)
-{
- DBG("%s\n",__FUNCTION__);
-
-#ifdef CONFIG_BT_AUTOSLEEP
- bcm4325_sleep(1);
-#endif
-
- DBG("Disable UART_RTS\n");
- //To prevent uart to receive bt data when suspended
- IOMUX_UART_RTS_GPIO();
- gpio_request(UART_RTS, "uart_rts");
- gpio_set_value(UART_RTS, GPIO_HIGH);
-
-#ifdef CONFIG_RFKILL_RESET
- extern void rfkill_set_block(struct rfkill *rfkill, bool blocked);
- rfkill_set_block(gBtCtrl.bt_rfk, true);
-#endif
-
- return 0;
-}
-
-static int bcm4329_rfkill_resume(struct platform_device *pdev)
-{
- DBG("%s\n",__FUNCTION__);
-
- DBG("delay 1s\n");
- schedule_delayed_work(&wakeup_work, HZ);
-
- return 0;
-}
-#else
-#define bcm4329_rfkill_suspend NULL
-#define bcm4329_rfkill_resume NULL
-#endif
-
-static irqreturn_t bcm4329_wake_host_irq(int irq, void *dev)
-{
- DBG("%s\n",__FUNCTION__);
-
- btWakeupHostLock();
- resetBtHostSleepTimer();
- return IRQ_HANDLED;
-}
-#endif
-
-void bcm4325_sleep(unsigned long bSleep)
-{
- DBG("*** bt sleep: %d ***\n", bSleep);
-#ifdef CONFIG_BT_AUTOSLEEP
- del_timer(&bt_sleep_tl);// cmy: È·±£ÔÚ»½ÐÑBTʱ£¬²»»áÒò´¥·¢bt_sleep_tl¶øÂíÉÏ˯Ãß
-#endif
-
- IOMUX_BT_GPIO_WAKE_UP();
- gpio_set_value(BT_GPIO_WAKE_UP, bSleep?GPIO_LOW:GPIO_HIGH);
-
-#ifdef CONFIG_BT_AUTOSLEEP
- if(!bSleep)
- mod_timer(&bt_sleep_tl, jiffies + BT_AUTO_SLEEP_TIMEOUT*HZ);//ÔÙÖØÐÂÉèÖó¬Ê±Öµ¡£
-#endif
-}
-
-static int bcm4329_set_block(void *data, bool blocked)
-{
- DBG("%s---blocked :%d\n", __FUNCTION__, blocked);
-
- IOMUX_BT_GPIO_POWER();
- IOMUX_BT_GPIO_RESET();
-
- if (false == blocked) {
- gpio_set_value(BT_GPIO_POWER, GPIO_HIGH); /* bt power on */
- mdelay(20);
-
- gpio_set_value(BT_GPIO_RESET, GPIO_LOW);
- mdelay(20);
- gpio_set_value(BT_GPIO_RESET, GPIO_HIGH); /* bt reset deactive*/
-
- mdelay(20);
- bcm4325_sleep(0); // ensure bt is wakeup
-
- pr_info("bt turn on power\n");
- } else {
-#if WIFI_BT_POWER_TOGGLE
- if (!rk29sdk_wifi_power_state) {
-#endif
- gpio_set_value(BT_GPIO_POWER, GPIO_LOW); /* bt power off */
- mdelay(20);
- pr_info("bt shut off power\n");
-#if WIFI_BT_POWER_TOGGLE
- }else {
- pr_info("bt shouldn't shut off power, wifi is using it!\n");
- }
-#endif
-
- gpio_set_value(BT_GPIO_RESET, GPIO_LOW); /* bt reset active*/
- mdelay(20);
- }
-
-#if WIFI_BT_POWER_TOGGLE
- rk29sdk_bt_power_state = !blocked;
-#endif
- return 0;
-}
-
-static const struct rfkill_ops bcm4329_rfk_ops = {
- .set_block = bcm4329_set_block,
-};
-
-static int __devinit bcm4329_rfkill_probe(struct platform_device *pdev)
-{
- int rc = 0;
- bool default_state = true;
-
- DBG("Enter::%s,line=%d\n",__FUNCTION__,__LINE__);
-
- /* default to bluetooth off */
- bcm4329_set_block(NULL, default_state); /* blocked -> bt off */
-
- gBtCtrl.bt_rfk = rfkill_alloc(bt_name,
- NULL,
- RFKILL_TYPE_BLUETOOTH,
- &bcm4329_rfk_ops,
- NULL);
-
- if (!gBtCtrl.bt_rfk)
- {
- printk("fail to rfkill_allocate************\n");
- return -ENOMEM;
- }
-
- rfkill_set_states(gBtCtrl.bt_rfk, default_state, false);
-
- rc = rfkill_register(gBtCtrl.bt_rfk);
- if (rc)
- {
- printk("failed to rfkill_register,rc=0x%x\n",rc);
- rfkill_destroy(gBtCtrl.bt_rfk);
- }
-
- gpio_request(BT_GPIO_POWER, NULL);
- gpio_request(BT_GPIO_RESET, NULL);
- gpio_request(BT_GPIO_WAKE_UP, NULL);
-
-#ifdef CONFIG_BT_AUTOSLEEP
- init_timer(&bt_sleep_tl);
- bt_sleep_tl.expires = 0;
- bt_sleep_tl.function = bcm4325_sleep;
- bt_sleep_tl.data = 1;
- add_timer(&bt_sleep_tl);
-#endif
-
-#if BT_WAKE_HOST_SUPPORT
- init_timer(&(gBtCtrl.tl));
- gBtCtrl.tl.expires = 0;
- gBtCtrl.tl.function = timer_hostSleep;
- add_timer(&(gBtCtrl.tl));
- gBtCtrl.b_HostWake = false;
-
- wake_lock_init(&(gBtCtrl.bt_wakelock), WAKE_LOCK_SUSPEND, "bt_wake");
-
- rc = gpio_request(BT_GPIO_WAKE_UP_HOST, "bt_wake");
- if (rc) {
- printk("%s:failed to request BT_WAKE_UP_HOST\n",__FUNCTION__);
- }
-
- IOMUX_BT_GPIO_WAKE_UP_HOST();
- gpio_pull_updown(BT_GPIO_WAKE_UP_HOST,GPIOPullUp);
- rc = request_irq(gpio_to_irq(BT_GPIO_WAKE_UP_HOST),bcm4329_wake_host_irq,IRQF_TRIGGER_FALLING,"bt_wake",NULL);
- if(rc)
- {
- printk("%s:failed to request BT_WAKE_UP_HOST irq\n",__FUNCTION__);
- gpio_free(BT_GPIO_WAKE_UP_HOST);
- }
- enable_irq_wake(gpio_to_irq(BT_GPIO_WAKE_UP_HOST)); // so BT_WAKE_UP_HOST can wake up system
-
- printk(KERN_INFO "bcm4329 module has been initialized,rc=0x%x\n",rc);
- #endif
-
- return rc;
-}
-
-
-static int __devexit bcm4329_rfkill_remove(struct platform_device *pdev)
-{
- if (gBtCtrl.bt_rfk)
- rfkill_unregister(gBtCtrl.bt_rfk);
- gBtCtrl.bt_rfk = NULL;
-#if BT_WAKE_HOST_SUPPORT
- del_timer(&(gBtCtrl.tl));//ɾµô¶¨Ê±Æ÷
- btWakeupHostUnlock();
- wake_lock_destroy(&(gBtCtrl.bt_wakelock));
-#endif
-#ifdef CONFIG_BT_AUTOSLEEP
- del_timer(&bt_sleep_tl);
-#endif
-
- platform_set_drvdata(pdev, NULL);
-
- DBG("Enter::%s,line=%d\n",__FUNCTION__,__LINE__);
- return 0;
-}
-
-static struct platform_driver bcm4329_rfkill_driver = {
- .probe = bcm4329_rfkill_probe,
- .remove = __devexit_p(bcm4329_rfkill_remove),
- .driver = {
- .name = "rk29sdk_rfkill",
- .owner = THIS_MODULE,
- },
-#if BT_WAKE_HOST_SUPPORT
- .suspend = bcm4329_rfkill_suspend,
- .resume = bcm4329_rfkill_resume,
-#endif
-};
-
-/*
- * Module initialization
- */
-static int __init bcm4329_mod_init(void)
-{
- int ret;
- DBG("Enter::%s,line=%d\n",__FUNCTION__,__LINE__);
- ret = platform_driver_register(&bcm4329_rfkill_driver);
- printk("ret=0x%x\n", ret);
- return ret;
-}
-
-static void __exit bcm4329_mod_exit(void)
-{
- platform_driver_unregister(&bcm4329_rfkill_driver);
-}
-
-module_init(bcm4329_mod_init);
-module_exit(bcm4329_mod_exit);
-MODULE_DESCRIPTION("bcm4329 Bluetooth driver");
-MODULE_AUTHOR("roger_chen cz@rock-chips.com, cmy@rock-chips.com");
-MODULE_LICENSE("GPL");
-
+++ /dev/null
-/* arch/arm/mach-rk29/board-rk29.c
- *
- * Copyright (C) 2010 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/android_pmem.h>
-#include <linux/usb/android_composite.h>
-
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/iomux.h>
-#include <mach/gpio.h>
-#include <mach/irqs.h>
-#include <mach/rk29_iomap.h>
-#include <mach/board.h>
-#include <mach/rk29_nand.h>
-#include <mach/rk29_camera.h> /* ddl@rock-chips.com : camera support */
-#include <media/soc_camera.h> /* ddl@rock-chips.com : camera support */
-#include <mach/vpu_mem.h>
-#include <mach/sram.h>
-#include <mach/ddr.h>
-#include <mach/cpufreq.h>
-#include <mach/rk29_smc.h>
-
-#include <linux/regulator/rk29-pwm-regulator.h>
-#include <linux/regulator/machine.h>
-
-#include <linux/mtd/nand.h>
-#include <linux/mtd/partitions.h>
-#include <linux/i2c-gpio.h>
-
-#include "devices.h"
-#include "../../../drivers/input/touchscreen/xpt2046_cbn_ts.h"
-
-#ifdef CONFIG_BU92747GUW_CIR
-#include "../../../drivers/cir/bu92747guw_cir.h"
-#endif
-#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Macro Define Begin ------------------------*/
-/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
-#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_OV5642 /* back camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_0 0x78
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 1
-#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 RK29_PIN6_PB7
-#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_OV2659 /* front camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_1 0x60
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 1
-#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_1 RK29_PIN5_PD7
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-#endif //#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk29_camera.c"
-/*---------------- Camera Sensor Macro Define End ------------------------*/
-
-
-/* Set memory size of pmem */
-#ifdef CONFIG_RK29_MEM_SIZE_M
-#define SDRAM_SIZE (CONFIG_RK29_MEM_SIZE_M * SZ_1M)
-#else
-#define SDRAM_SIZE SZ_512M
-#endif
-#define PMEM_GPU_SIZE SZ_16M
-#define PMEM_UI_SIZE (48 * SZ_1M) /* 1280x800: 64M 1024x768: 48M ... */
-#define PMEM_VPU_SIZE SZ_64M
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-#ifdef CONFIG_VIDEO_RK29_WORK_IPP
-#define MEM_CAMIPP_SIZE SZ_4M
-#else
-#define MEM_CAMIPP_SIZE 0
-#endif
-#define MEM_FB_SIZE (3*SZ_2M)
-#ifdef CONFIG_FB_WORK_IPP
-#ifdef CONFIG_FB_SCALING_OSD_1080P
-#define MEM_FBIPP_SIZE SZ_16M //1920 x 1080 x 2 x 2 //RGB565 = x2;RGB888 = x4
-#else
-#define MEM_FBIPP_SIZE SZ_8M //1920 x 1080 x 2 x 2 //RGB565 = x2;RGB888 = x4
-#endif
-#else
-#define MEM_FBIPP_SIZE 0
-#endif
-#if SDRAM_SIZE > SZ_512M
-#define PMEM_GPU_BASE (RK29_SDRAM_PHYS + SZ_512M - PMEM_GPU_SIZE)
-#else
-#define PMEM_GPU_BASE (RK29_SDRAM_PHYS + SDRAM_SIZE - PMEM_GPU_SIZE)
-#endif
-#define PMEM_UI_BASE (PMEM_GPU_BASE - PMEM_UI_SIZE)
-#define PMEM_VPU_BASE (PMEM_UI_BASE - PMEM_VPU_SIZE)
-#define PMEM_CAM_BASE (PMEM_VPU_BASE - PMEM_CAM_SIZE)
-#define MEM_CAMIPP_BASE (PMEM_CAM_BASE - MEM_CAMIPP_SIZE)
-#define MEM_FB_BASE (MEM_CAMIPP_BASE - MEM_FB_SIZE)
-#define MEM_FBIPP_BASE (MEM_FB_BASE - MEM_FBIPP_SIZE)
-#define LINUX_SIZE (MEM_FBIPP_BASE - RK29_SDRAM_PHYS)
-
-#define PREALLOC_WLAN_SEC_NUM 4
-#define PREALLOC_WLAN_BUF_NUM 160
-#define PREALLOC_WLAN_SECTION_HEADER 24
-
-#define WLAN_SECTION_SIZE_0 (PREALLOC_WLAN_BUF_NUM * 128)
-#define WLAN_SECTION_SIZE_1 (PREALLOC_WLAN_BUF_NUM * 128)
-#define WLAN_SECTION_SIZE_2 (PREALLOC_WLAN_BUF_NUM * 512)
-#define WLAN_SECTION_SIZE_3 (PREALLOC_WLAN_BUF_NUM * 1024)
-
-#define WLAN_SKB_BUF_NUM 16
-
-static struct sk_buff *wlan_static_skb[WLAN_SKB_BUF_NUM];
-
-struct wifi_mem_prealloc {
- void *mem_ptr;
- unsigned long size;
-};
-
-extern struct sys_timer rk29_timer;
-
-static int rk29_nand_io_init(void)
-{
- return 0;
-}
-
-struct rk29_nand_platform_data rk29_nand_data = {
- .width = 1, /* data bus width in bytes */
- .hw_ecc = 1, /* hw ecc 0: soft ecc */
- .num_flash = 1,
- .io_init = rk29_nand_io_init,
-};
-
-#define TOUCH_SCREEN_STANDBY_PIN INVALID_GPIO
-#define TOUCH_SCREEN_STANDBY_VALUE GPIO_HIGH
-#define TOUCH_SCREEN_DISPLAY_PIN INVALID_GPIO
-#define TOUCH_SCREEN_DISPLAY_VALUE GPIO_HIGH
-#ifdef CONFIG_FB_RK29
-/*****************************************************************************************
- * lcd devices
- * author: zyw@rock-chips.com
- *****************************************************************************************/
-#define LCD_TXD_PIN INVALID_GPIO
-#define LCD_CLK_PIN INVALID_GPIO
-#define LCD_CS_PIN INVALID_GPIO
-/*****************************************************************************************
-* frame buffer devices pin define
-* author: zyw@rock-chips.com
-*****************************************************************************************/
-#define FB_ID 0
-#define FB_DISPLAY_ON_PIN INVALID_GPIO// RK29_PIN6_PD0
-#define FB_LCD_STANDBY_PIN RK29_PIN6_PD1
-#define FB_LCD_CABC_EN_PIN RK29_PIN6_PD2
-#define FB_MCU_FMK_PIN INVALID_GPIO
-
-#define FB_DISPLAY_ON_VALUE GPIO_HIGH
-#define FB_LCD_STANDBY_VALUE GPIO_HIGH
-
-static int rk29_lcd_io_init(void)
-{
- int ret = 0;
- return ret;
-}
-
-static int rk29_lcd_io_deinit(void)
-{
- int ret = 0;
- return ret;
-}
-
-static struct rk29lcd_info rk29_lcd_info = {
- .txd_pin = LCD_TXD_PIN,
- .clk_pin = LCD_CLK_PIN,
- .cs_pin = LCD_CS_PIN,
- .io_init = rk29_lcd_io_init,
- .io_deinit = rk29_lcd_io_deinit,
-};
-
-int rk29_fb_io_enable(void)
-{
- if(FB_DISPLAY_ON_PIN != INVALID_GPIO)
- {
- gpio_direction_output(FB_DISPLAY_ON_PIN, 0);
- gpio_set_value(FB_DISPLAY_ON_PIN, FB_DISPLAY_ON_VALUE);
- }
- if(FB_LCD_STANDBY_PIN != INVALID_GPIO)
- {
- gpio_direction_output(FB_LCD_STANDBY_PIN, 0);
- gpio_set_value(FB_LCD_STANDBY_PIN, FB_LCD_STANDBY_VALUE);
- }
- return 0;
-}
-
-int rk29_fb_io_disable(void)
-{
- if(FB_DISPLAY_ON_PIN != INVALID_GPIO)
- {
- gpio_direction_output(FB_DISPLAY_ON_PIN, 0);
- gpio_set_value(FB_DISPLAY_ON_PIN, !FB_DISPLAY_ON_VALUE);
- }
- if(FB_LCD_STANDBY_PIN != INVALID_GPIO)
- {
- gpio_direction_output(FB_LCD_STANDBY_PIN, 0);
- gpio_set_value(FB_LCD_STANDBY_PIN, !FB_LCD_STANDBY_VALUE);
- }
- return 0;
-}
-
-static int rk29_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
- if(fb_setting->mcu_fmk_en && (FB_MCU_FMK_PIN != INVALID_GPIO))
- {
- ret = gpio_request(FB_MCU_FMK_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(FB_MCU_FMK_PIN);
- printk(">>>>>> FB_MCU_FMK_PIN gpio_request err \n ");
- }
- gpio_direction_input(FB_MCU_FMK_PIN);
- }
- if(fb_setting->disp_on_en)
- {
- if(FB_DISPLAY_ON_PIN != INVALID_GPIO)
- {
- ret = gpio_request(FB_DISPLAY_ON_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(FB_DISPLAY_ON_PIN);
- printk(">>>>>> FB_DISPLAY_ON_PIN gpio_request err \n ");
- }
- }
- else
- {
- ret = gpio_request(TOUCH_SCREEN_DISPLAY_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(TOUCH_SCREEN_DISPLAY_PIN);
- printk(">>>>>> TOUCH_SCREEN_DISPLAY_PIN gpio_request err \n ");
- }
- gpio_direction_output(TOUCH_SCREEN_DISPLAY_PIN, 0);
- gpio_set_value(TOUCH_SCREEN_DISPLAY_PIN, TOUCH_SCREEN_DISPLAY_VALUE);
- }
- }
-
- if(fb_setting->disp_on_en)
- {
- if(FB_LCD_STANDBY_PIN != INVALID_GPIO)
- {
- ret = gpio_request(FB_LCD_STANDBY_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(FB_LCD_STANDBY_PIN);
- printk(">>>>>> FB_LCD_STANDBY_PIN gpio_request err \n ");
- }
- }
- else
- {
- ret = gpio_request(TOUCH_SCREEN_STANDBY_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(TOUCH_SCREEN_STANDBY_PIN);
- printk(">>>>>> TOUCH_SCREEN_STANDBY_PIN gpio_request err \n ");
- }
- gpio_direction_output(TOUCH_SCREEN_STANDBY_PIN, 0);
- gpio_set_value(TOUCH_SCREEN_STANDBY_PIN, TOUCH_SCREEN_STANDBY_VALUE);
- }
- }
-
- if(FB_LCD_CABC_EN_PIN != INVALID_GPIO)
- {
- ret = gpio_request(FB_LCD_CABC_EN_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(FB_LCD_CABC_EN_PIN);
- printk(">>>>>> FB_LCD_CABC_EN_PIN gpio_request err \n ");
- }
- gpio_direction_output(FB_LCD_CABC_EN_PIN, 0);
- gpio_set_value(FB_LCD_CABC_EN_PIN, GPIO_LOW);
- }
-
- rk29_fb_io_enable(); //enable it
-
- return ret;
-}
-
-
-static struct rk29fb_info rk29_fb_info = {
- .fb_id = FB_ID,
- .mcu_fmk_pin = FB_MCU_FMK_PIN,
- .lcd_info = &rk29_lcd_info,
- .io_init = rk29_fb_io_init,
- .io_enable = rk29_fb_io_enable,
- .io_disable = rk29_fb_io_disable,
-};
-
-/* rk29 fb resource */
-static struct resource rk29_fb_resource[] = {
- [0] = {
- .name = "lcdc reg",
- .start = RK29_LCDC_PHYS,
- .end = RK29_LCDC_PHYS + RK29_LCDC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc irq",
- .start = IRQ_LCDC,
- .end = IRQ_LCDC,
- .flags = IORESOURCE_IRQ,
- },
- [2] = {
- .name = "win1 buf",
- .start = MEM_FB_BASE,
- .end = MEM_FB_BASE + MEM_FB_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- #ifdef CONFIG_FB_WORK_IPP
- [3] = {
- .name = "win1 ipp buf",
- .start = MEM_FBIPP_BASE,
- .end = MEM_FBIPP_BASE + MEM_FBIPP_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- #endif
-};
-
-/*platform_device*/
-struct platform_device rk29_device_fb = {
- .name = "rk29-fb",
- .id = 4,
- .num_resources = ARRAY_SIZE(rk29_fb_resource),
- .resource = rk29_fb_resource,
- .dev = {
- .platform_data = &rk29_fb_info,
- }
-};
-
-struct platform_device rk29_device_dma_cpy = {
- .name = "dma_memcpy",
- .id = 4,
-
-};
-
-#endif
-
-#if defined(CONFIG_RK_IRDA) || defined(CONFIG_BU92747GUW_CIR)
-#define BU92747GUW_RESET_PIN RK29_PIN3_PD4// INVALID_GPIO //
-#define BU92747GUW_RESET_MUX_NAME GPIO3D4_HOSTWRN_NAME//NULL //
-#define BU92747GUW_RESET_MUX_MODE GPIO3H_GPIO3D4//NULL //
-
-#define BU92747GUW_PWDN_PIN RK29_PIN3_PD3//RK29_PIN5_PA7 //
-#define BU92747GUW_PWDN_MUX_NAME GPIO3D3_HOSTRDN_NAME//GPIO5A7_HSADCDATA2_NAME //
-#define BU92747GUW_PWDN_MUX_MODE GPIO3H_GPIO3D3//GPIO5L_GPIO5A7 //
-
-static int bu92747guw_io_init(void)
-{
- int ret;
-
- //reset pin
- if(BU92747GUW_RESET_MUX_NAME != NULL)
- {
- rk29_mux_api_set(BU92747GUW_RESET_MUX_NAME, BU92747GUW_RESET_MUX_MODE);
- }
- ret = gpio_request(BU92747GUW_RESET_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(BU92747GUW_RESET_PIN);
- printk(">>>>>> BU92747GUW_RESET_PIN gpio_request err \n ");
- }
- gpio_direction_output(BU92747GUW_RESET_PIN, GPIO_HIGH);
-
- //power down pin
- if(BU92747GUW_PWDN_MUX_NAME != NULL)
- {
- rk29_mux_api_set(BU92747GUW_PWDN_MUX_NAME, BU92747GUW_PWDN_MUX_MODE);
- }
- ret = gpio_request(BU92747GUW_PWDN_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(BU92747GUW_PWDN_PIN);
- printk(">>>>>> BU92747GUW_PWDN_PIN gpio_request err \n ");
- }
-
- //power down as default
- gpio_direction_output(BU92747GUW_PWDN_PIN, GPIO_LOW);
-
- return 0;
-}
-
-
-static int bu92747guw_io_deinit(void)
-{
- gpio_free(BU92747GUW_PWDN_PIN);
- gpio_free(BU92747GUW_RESET_PIN);
- return 0;
-}
-
-//power ctl func is share with irda and remote
-static int nPowerOnCount = 0;
-static DEFINE_MUTEX(bu92747_power_mutex);
-
-//1---power on; 0---power off
-static int bu92747guw_power_ctl(int enable)
-{
- printk("%s \n",__FUNCTION__);
-
- mutex_lock(&bu92747_power_mutex);
- if (enable) {
- nPowerOnCount++;
- if (nPowerOnCount == 1) {//power on first
- //smc0_init(NULL);
- gpio_set_value(BU92747GUW_PWDN_PIN, GPIO_HIGH);
- gpio_set_value(BU92747GUW_RESET_PIN, GPIO_LOW);
- mdelay(5);
- gpio_set_value(BU92747GUW_RESET_PIN, GPIO_HIGH);
- mdelay(5);
- }
- }
- else {
- nPowerOnCount--;
- if (nPowerOnCount <= 0) {//power down final
- nPowerOnCount = 0;
- //smc0_exit();
- gpio_set_value(BU92747GUW_PWDN_PIN, GPIO_LOW);
- }
- }
- mutex_unlock(&bu92747_power_mutex);
- return 0;
-}
-#endif
-
-#ifdef CONFIG_RK_IRDA
-#define IRDA_IRQ_PIN RK29_PIN5_PB2
-#define IRDA_IRQ_MUX_NAME GPIO5B2_HSADCDATA5_NAME
-#define IRDA_IRQ_MUX_MODE GPIO5L_GPIO5B2
-
-int irda_iomux_init(void)
-{
- int ret = 0;
-
- //irda irq pin
- if(IRDA_IRQ_MUX_NAME != NULL)
- {
- rk29_mux_api_set(IRDA_IRQ_MUX_NAME, IRDA_IRQ_MUX_MODE);
- }
- ret = gpio_request(IRDA_IRQ_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(IRDA_IRQ_PIN);
- printk(">>>>>> IRDA_IRQ_PIN gpio_request err \n ");
- }
- gpio_pull_updown(IRDA_IRQ_PIN, GPIO_HIGH);
- gpio_direction_input(IRDA_IRQ_PIN);
-
- return 0;
-}
-
-int irda_iomux_deinit(void)
-{
- gpio_free(IRDA_IRQ_PIN);
- return 0;
-}
-
-static struct irda_info rk29_irda_info = {
- .intr_pin = IRDA_IRQ_PIN,
- .iomux_init = irda_iomux_init,
- .iomux_deinit = irda_iomux_deinit,
- .irda_pwr_ctl = bu92747guw_power_ctl,
-};
-
-static struct platform_device irda_device = {
-#ifdef CONFIG_RK_IRDA_NET
- .name = "rk_irda",
-#else
- .name = "bu92747_irda",
-#endif
- .id = -1,
- .dev = {
- .platform_data = &rk29_irda_info,
- }
-};
-#endif
-
-#ifdef CONFIG_BU92747GUW_CIR
-#define BU92747_CIR_IRQ_PIN RK29_PIN5_PB0
-#define CIR_IRQ_PIN_IOMUX_NAME GPIO5B0_HSADCDATA3_NAME
-#define CIR_IRQ_PIN_IOMUX_VALUE GPIO5L_GPIO5B0
-static int cir_iomux_init(void)
-{
- if (CIR_IRQ_PIN_IOMUX_NAME)
- rk29_mux_api_set(CIR_IRQ_PIN_IOMUX_NAME, CIR_IRQ_PIN_IOMUX_VALUE);
- rk29_mux_api_set(GPIO5A7_HSADCDATA2_NAME, GPIO5L_GPIO5A7);
- return 0;
-}
-
-static struct bu92747guw_platform_data bu92747guw_pdata = {
- .intr_pin = BU92747_CIR_IRQ_PIN,
- .iomux_init = cir_iomux_init,
- .iomux_deinit = NULL,
- .cir_pwr_ctl = bu92747guw_power_ctl,
-};
-#endif
-#ifdef CONFIG_RK29_NEWTON
-struct rk29_newton_data rk29_newton_info = {
-};
-struct platform_device rk29_device_newton = {
- .name = "rk29_newton",
- .id = -1,
- .dev = {
- .platform_data = &rk29_newton_info,
- }
- };
-#endif
-#if defined (CONFIG_TOUCHSCREEN_FT5406)
-#define TOUCH_RESET_PIN RK29_PIN6_PC3
-#define TOUCH_INT_PIN RK29_PIN0_PA2
-int ft5406_init_platform_hw(void)
-{
- printk("ft5406_init_platform_hw\n");
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("ft5406_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("ift5406_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- mdelay(10);
- gpio_direction_input(TOUCH_INT_PIN);
- mdelay(10);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- msleep(300);
- return 0;
-}
-
-void ft5406_exit_platform_hw(void)
-{
- printk("ft5406_exit_platform_hw\n");
- gpio_free(TOUCH_RESET_PIN);
- gpio_free(TOUCH_INT_PIN);
-}
-
-int ft5406_platform_sleep(void)
-{
- printk("ft5406_platform_sleep\n");
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- return 0;
-}
-
-int ft5406_platform_wakeup(void)
-{
- printk("ft5406_platform_wakeup\n");
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- msleep(300);
- return 0;
-}
-
-struct ft5406_platform_data ft5406_info = {
-
- .init_platform_hw= ft5406_init_platform_hw,
- .exit_platform_hw= ft5406_exit_platform_hw,
- .platform_sleep = ft5406_platform_sleep,
- .platform_wakeup = ft5406_platform_wakeup,
-
-};
-#endif
-
-#if defined(CONFIG_TOUCHSCREEN_GT819)
-#define TOUCH_RESET_PIN RK29_PIN6_PC3
-#define TOUCH_INT_PIN RK29_PIN0_PA2
-int gt819_init_platform_hw(void)
-{
- printk("gt819_init_platform_hw\n");
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("gt819_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("gt819_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- mdelay(10);
-// gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
-// mdelay(10);
-// gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- gpio_direction_input(TOUCH_INT_PIN);
-// mdelay(10);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- msleep(300);
- return 0;
-}
-
-
-void gt819_exit_platform_hw(void)
-{
- printk("gt819_exit_platform_hw\n");
- gpio_free(TOUCH_RESET_PIN);
- gpio_free(TOUCH_INT_PIN);
-}
-
-int gt819_platform_sleep(void)
-{
- printk("gt819_platform_sleep\n");
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- return 0;
-}
-
-int gt819_platform_wakeup(void)
-{
- printk("gt819_platform_wakeup\n");
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- //msleep(5);
- //gpio_set_value(TOUCH_INT_PIN, GPIO_LOW);
- //msleep(20);
- //gpio_set_value(TOUCH_INT_PIN, GPIO_HIGH);
- return 0;
-}
-struct goodix_platform_data goodix_info = {
-
- .init_platform_hw= gt819_init_platform_hw,
- .exit_platform_hw= gt819_exit_platform_hw,
- .platform_sleep = gt819_platform_sleep,
- .platform_wakeup = gt819_platform_wakeup,
-
-};
-#endif
-
-
-#if defined (CONFIG_SND_SOC_CS42L52)
-
-int cs42l52_init_platform_hw()
-{
- printk("cs42l52_init_platform_hw\n");
- if(gpio_request(RK29_PIN6_PB6,NULL) != 0){
- gpio_free(RK29_PIN6_PB6);
- printk("cs42l52_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(RK29_PIN6_PB6, 0);
- gpio_set_value(RK29_PIN6_PB6,GPIO_HIGH);
- return 0;
-}
-struct cs42l52_platform_data cs42l52_info = {
-
- .init_platform_hw= cs42l52_init_platform_hw,
-
-};
-#endif
-#if defined (CONFIG_BATTERY_BQ27541)
-#define DC_CHECK_PIN RK29_PIN4_PA1
-#define LI_LION_BAT_NUM 1
-#define CHG_OK RK29_PIN4_PA3
-#define BAT_LOW RK29_PIN4_PA2
-
-static int bq27541_init_dc_check_pin(void){
- if(gpio_request(DC_CHECK_PIN,"dc_check") != 0){
- gpio_free(DC_CHECK_PIN);
- printk("bq27541 init dc check pin request error\n");
- return -EIO;
- }
- gpio_direction_input(DC_CHECK_PIN);
- return 0;
-}
-
-struct bq27541_platform_data bq27541_info = {
- .init_dc_check_pin = bq27541_init_dc_check_pin,
- .dc_check_pin = DC_CHECK_PIN,
- .bat_num = LI_LION_BAT_NUM,
- .chgok_check_pin = CHG_OK,
- .bat_check_pin = BAT_LOW,
-};
-#endif
-static struct android_pmem_platform_data android_pmem_pdata = {
- .name = "pmem",
- .start = PMEM_UI_BASE,
- .size = PMEM_UI_SIZE,
- .no_allocator = 1,
- .cached = 1,
-};
-
-static struct platform_device android_pmem_device = {
- .name = "android_pmem",
- .id = 0,
- .dev = {
- .platform_data = &android_pmem_pdata,
- },
-};
-
-
-static struct vpu_mem_platform_data vpu_mem_pdata = {
- .name = "vpu_mem",
- .start = PMEM_VPU_BASE,
- .size = PMEM_VPU_SIZE,
- .cached = 1,
-};
-
-static struct platform_device rk29_vpu_mem_device = {
- .name = "vpu_mem",
- .id = 2,
- .dev = {
- .platform_data = &vpu_mem_pdata,
- },
-};
-#ifdef CONFIG_VIDEO_RK29XX_VOUT
-static struct platform_device rk29_v4l2_output_devce = {
- .name = "rk29_vout",
-};
-#endif
-/*HANNSTAR_P1003 touch*/
-#if defined (CONFIG_HANNSTAR_P1003)
-#define TOUCH_RESET_PIN RK29_PIN6_PC3
-#define TOUCH_INT_PIN RK29_PIN0_PA2
-
-int p1003_init_platform_hw(void)
-{
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_pull_updown(TOUCH_INT_PIN, 1);
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
-
- return 0;
-}
-
-
-struct p1003_platform_data p1003_info = {
- .model= 1003,
- .init_platform_hw= p1003_init_platform_hw,
-
-};
-#endif
-#if defined (CONFIG_EETI_EGALAX)
-#define TOUCH_RESET_PIN RK29_PIN6_PC3
-#define TOUCH_INT_PIN RK29_PIN0_PA2
-
-static int EETI_EGALAX_init_platform_hw(void)
-{
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_pull_updown(TOUCH_INT_PIN, 1);
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
-
- return 0;
-}
-
-
-static struct eeti_egalax_platform_data eeti_egalax_info = {
- .model= 1003,
- .init_platform_hw= EETI_EGALAX_init_platform_hw,
- .standby_pin = TOUCH_SCREEN_STANDBY_PIN,
- .standby_value = TOUCH_SCREEN_STANDBY_VALUE,
- .disp_on_pin = TOUCH_SCREEN_DISPLAY_PIN,
- .disp_on_value = TOUCH_SCREEN_DISPLAY_VALUE,
-};
-#endif
-
-#ifdef CONFIG_GS_KXTF9
-#include <linux/kxtf9.h>
-#define KXTF9_DEVICE_MAP 1
-#define KXTF9_MAP_X (KXTF9_DEVICE_MAP-1)%2
-#define KXTF9_MAP_Y KXTF9_DEVICE_MAP%2
-#define KXTF9_NEG_X (KXTF9_DEVICE_MAP/2)%2
-#define KXTF9_NEG_Y (KXTF9_DEVICE_MAP+1)/4
-#define KXTF9_NEG_Z (KXTF9_DEVICE_MAP-1)/4
-struct kxtf9_platform_data kxtf9_pdata = {
- .min_interval = 1,
- .poll_interval = 20,
- .g_range = KXTF9_G_2G,
- .axis_map_x = KXTF9_MAP_X,
- .axis_map_y = KXTF9_MAP_Y,
- .axis_map_z = 2,
- .negate_x = KXTF9_NEG_X,
- .negate_y = KXTF9_NEG_Y,
- .negate_z = KXTF9_NEG_Z,
- //.ctrl_regc_init = KXTF9_G_2G | ODR50F,
- //.ctrl_regb_init = ENABLE,
-};
-#endif /* CONFIG_GS_KXTF9 */
-
-
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN RK29_PIN0_PA3
-
-static int mma8452_init_platform_hw(void)
-{
-
- if(gpio_request(MMA8452_INT_PIN,NULL) != 0){
- gpio_free(MMA8452_INT_PIN);
- printk("mma8452_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_pull_updown(MMA8452_INT_PIN, 1);
- return 0;
-}
-
-
-static struct gsensor_platform_data mma8452_info = {
- .model= 8452,
- .swap_xy = 1,
- .init_platform_hw= mma8452_init_platform_hw,
-
-};
-#endif
-#if defined (CONFIG_MPU_SENSORS_MPU3050)
-/*mpu3050*/
-static struct mpu3050_platform_data mpu3050_data = {
- .int_config = 0x10,
- //.orientation = { 1, 0, 0,0, -1, 0,0, 0, 1 },
- //.orientation = { 0, 1, 0,-1, 0, 0,0, 0, -1 },
- //.orientation = { -1, 0, 0,0, -1, 0,0, 0, -1 },
- .orientation = { 0, 1, 0, -1, 0, 0, 0, 0, 1 },
- .level_shifter = 0,
-#if defined (CONFIG_MPU_SENSORS_KXTF9)
- .accel = {
-#ifdef CONFIG_MPU_SENSORS_MPU3050_MODULE
- .get_slave_descr = NULL ,
-#else
- .get_slave_descr = get_accel_slave_descr ,
-#endif
- .adapt_num = 0, // The i2c bus to which the mpu device is
- // connected
- //.irq = RK29_PIN0_PA3,
- .bus = EXT_SLAVE_BUS_SECONDARY, //The secondary I2C of MPU
- .address = 0x0f,
- //.orientation = { 1, 0, 0,0, 1, 0,0, 0, 1 },
- //.orientation = { 0, -1, 0,-1, 0, 0,0, 0, -1 },
- //.orientation = { 0, 1, 0,1, 0, 0,0, 0, -1 },
- .orientation = { 0, 1 ,0, -1 ,0, 0, 0, 0, 1 },
- },
-#endif
-#if defined (CONFIG_MPU_SENSORS_AK8975)
- .compass = {
-#ifdef CONFIG_MPU_SENSORS_MPU3050_MODULE
- .get_slave_descr = NULL,/*ak5883_get_slave_descr,*/
-#else
- .get_slave_descr = get_compass_slave_descr,
-#endif
- .adapt_num = 0, // The i2c bus to which the compass device is.
- // It can be difference with mpu
- // connected
- //.irq = RK29_PIN0_PA4,
- .bus = EXT_SLAVE_BUS_PRIMARY,
- .address = 0x0d,
- //.orientation = { -1, 0, 0,0, -1, 0,0, 0, 1 },
- //.orientation = { 0, -1, 0,-1, 0, 0,0, 0, -1 },
- //.orientation = { 0, 1, 0,1, 0, 0,0, 0, -1 },
- //.orientation = { 0, -1, 0, 1, 0, 0, 0, 0, 1 },
- .orientation = { 0, 1, 0, -1, 0, 0, 0, 0, 1 },
- },
-};
-#endif
-#endif
-#if defined (CONFIG_BATTERY_BQ27510)
-#define DC_CHECK_PIN RK29_PIN4_PA1
-#define LI_LION_BAT_NUM 2
-static int bq27510_init_dc_check_pin(void){
- if(gpio_request(DC_CHECK_PIN,"dc_check") != 0){
- gpio_free(DC_CHECK_PIN);
- printk("bq27510 init dc check pin request error\n");
- return -EIO;
- }
- gpio_direction_input(DC_CHECK_PIN);
- return 0;
-}
-
-struct bq27510_platform_data bq27510_info = {
- .init_dc_check_pin = bq27510_init_dc_check_pin,
- .dc_check_pin = DC_CHECK_PIN,
- .bat_num = LI_LION_BAT_NUM,
-};
-#endif
-
-
-/*****************************************************************************************
- * i2c devices
- * author: kfx@rock-chips.com
-*****************************************************************************************/
-static int rk29_i2c0_io_init(void)
-{
-#ifdef CONFIG_RK29_I2C0_CONTROLLER
- rk29_mux_api_set(GPIO2B7_I2C0SCL_NAME, GPIO2L_I2C0_SCL);
- rk29_mux_api_set(GPIO2B6_I2C0SDA_NAME, GPIO2L_I2C0_SDA);
-#else
- rk29_mux_api_set(GPIO2B7_I2C0SCL_NAME, GPIO2L_GPIO2B7);
- rk29_mux_api_set(GPIO2B6_I2C0SDA_NAME, GPIO2L_GPIO2B6);
-#endif
- return 0;
-}
-
-static int rk29_i2c1_io_init(void)
-{
-#ifdef CONFIG_RK29_I2C1_CONTROLLER
- rk29_mux_api_set(GPIO1A7_I2C1SCL_NAME, GPIO1L_I2C1_SCL);
- rk29_mux_api_set(GPIO1A6_I2C1SDA_NAME, GPIO1L_I2C1_SDA);
-#else
- rk29_mux_api_set(GPIO1A7_I2C1SCL_NAME, GPIO1L_GPIO1A7);
- rk29_mux_api_set(GPIO1A6_I2C1SDA_NAME, GPIO1L_GPIO1A6);
-#endif
- return 0;
-}
-static int rk29_i2c2_io_init(void)
-{
-#ifdef CONFIG_RK29_I2C2_CONTROLLER
- rk29_mux_api_set(GPIO5D4_I2C2SCL_NAME, GPIO5H_I2C2_SCL);
- rk29_mux_api_set(GPIO5D3_I2C2SDA_NAME, GPIO5H_I2C2_SDA);
-#else
- rk29_mux_api_set(GPIO5D4_I2C2SCL_NAME, GPIO5H_GPIO5D4);
- rk29_mux_api_set(GPIO5D3_I2C2SDA_NAME, GPIO5H_GPIO5D3);
-#endif
- return 0;
-}
-
-static int rk29_i2c3_io_init(void)
-{
-#ifdef CONFIG_RK29_I2C3_CONTROLLER
- rk29_mux_api_set(GPIO2B5_UART3RTSN_I2C3SCL_NAME, GPIO2L_I2C3_SCL);
- rk29_mux_api_set(GPIO2B4_UART3CTSN_I2C3SDA_NAME, GPIO2L_I2C3_SDA);
-#else
- rk29_mux_api_set(GPIO2B5_UART3RTSN_I2C3SCL_NAME, GPIO2L_GPIO2B5);
- rk29_mux_api_set(GPIO2B4_UART3CTSN_I2C3SDA_NAME, GPIO2L_GPIO2B4);
-#endif
- return 0;
-}
-#ifdef CONFIG_RK29_I2C0_CONTROLLER
-struct rk29_i2c_platform_data default_i2c0_data = {
- .bus_num = 0,
- .flags = 0,
- .slave_addr = 0xff,
- .scl_rate = 400*1000,
- .mode = I2C_MODE_IRQ,
- .io_init = rk29_i2c0_io_init,
-};
-#else
-struct i2c_gpio_platform_data default_i2c0_data = {
- .sda_pin = RK29_PIN2_PB6,
- .scl_pin = RK29_PIN2_PB7,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(200),
- .bus_num = 0,
- .io_init = rk29_i2c0_io_init,
-};
-#endif
-#ifdef CONFIG_RK29_I2C1_CONTROLLER
-struct rk29_i2c_platform_data default_i2c1_data = {
- .bus_num = 1,
- .flags = 0,
- .slave_addr = 0xff,
- .scl_rate = 400*1000,
- .mode = I2C_MODE_IRQ,
- .io_init = rk29_i2c1_io_init,
-};
-#else
-struct i2c_gpio_platform_data default_i2c1_data = {
- .sda_pin = RK29_PIN1_PA6,
- .scl_pin = RK29_PIN1_PA7,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(200),
- .bus_num = 1,
- .io_init = rk29_i2c1_io_init,
-};
-#endif
-#ifdef CONFIG_RK29_I2C2_CONTROLLER
-struct rk29_i2c_platform_data default_i2c2_data = {
- .bus_num = 2,
- .flags = 0,
- .slave_addr = 0xff,
- .scl_rate = 400*1000,
- .mode = I2C_MODE_IRQ,
- .io_init = rk29_i2c2_io_init,
-};
-#else
-struct i2c_gpio_platform_data default_i2c2_data = {
- .sda_pin = RK29_PIN5_PD3,
- .scl_pin = RK29_PIN5_PD4,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(200),
- .bus_num = 2,
- .io_init = rk29_i2c2_io_init,
-};
-#endif
-#ifdef CONFIG_RK29_I2C3_CONTROLLER
-struct rk29_i2c_platform_data default_i2c3_data = {
- .bus_num = 3,
- .flags = 0,
- .slave_addr = 0xff,
- .scl_rate = 400*1000,
- .mode = I2C_MODE_IRQ,
- .io_init = rk29_i2c3_io_init,
-};
-#else
-struct i2c_gpio_platform_data default_i2c3_data = {
- .sda_pin = RK29_PIN5_PB5,
- .scl_pin = RK29_PIN5_PB4,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(200),
- .bus_num = 3,
- .io_init = rk29_i2c3_io_init,
-};
-#endif
-#ifdef CONFIG_I2C0_RK29
-static struct i2c_board_info __initdata board_i2c0_devices[] = {
-#if defined (CONFIG_RK1000_CONTROL)
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_alc5621)
- {
- .type = "ALC5621",
- .addr = 0x1a,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_alc5631)
- {
- .type = "rt5631",
- .addr = 0x1a,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_WM8900)
- {
- .type = "wm8900",
- .addr = 0x1A,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_BATTERY_STC3100)
- {
- .type = "stc3100",
- .addr = 0x70,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_BATTERY_BQ27510)
- {
- .type = "bq27510",
- .addr = 0x55,
- .flags = 0,
- .platform_data = &bq27510_info,
- },
-#endif
-#if defined (CONFIG_RTC_HYM8563)
- {
- .type = "rtc_hym8563",
- .addr = 0x51,
- .flags = 0,
- .irq = RK29_PIN0_PA1,
- },
-#endif
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1c,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8973)
- {
- .type = "ak8973",
- .addr = 0x1d,
- .flags = 0,
- .irq = RK29_PIN0_PA4,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK29_PIN0_PA4,
- },
-#endif
-/*mpu3050*/
-#if defined (CONFIG_MPU_SENSORS_MPU3050)
- {
- .type = "mpu3050",
- .addr = 0x68,
- .flags = 0,
- .irq = RK29_PIN5_PA3,
- .platform_data = &mpu3050_data,
- },
-#endif
-#if defined (CONFIG_SND_SOC_CS42L52)
- {
- .type = "cs42l52",
- .addr = 0x4A,
- .flags = 0,
- .platform_data = &cs42l52_info,
- },
-#endif
-#if defined (CONFIG_RTC_M41T66)
- {
- .type = "rtc-M41T66",
- .addr = 0x68,
- .flags = 0,
- .irq = RK29_PIN0_PA1,
- },
-#endif
-};
-#endif
-#if defined (CONFIG_ANX7150)
-struct hdmi_platform_data anx7150_data = {
- //.io_init = anx7150_io_init,
-};
-#endif
-#ifdef CONFIG_I2C1_RK29
-static struct i2c_board_info __initdata board_i2c1_devices[] = {
-#if defined (CONFIG_RK1000_CONTROL1)
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_ANX7150)
- {
- .type = "anx7150",
- .addr = 0x39, //0x39, 0x3d
- .flags = 0,
- .irq = RK29_PIN1_PD7,
- .platform_data = &anx7150_data,
- },
-#endif
-#ifdef CONFIG_BU92747GUW_CIR
- {
- .type ="bu92747_cir",
- .addr = 0x77,
- .flags =0,
- .irq = BU92747_CIR_IRQ_PIN,
- .platform_data = &bu92747guw_pdata,
- },
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C2_RK29
-static struct i2c_board_info __initdata board_i2c2_devices[] = {
-#if defined (CONFIG_HANNSTAR_P1003)
- {
- .type = "p1003_touch",
- .addr = 0x04,
- .flags = 0, //I2C_M_NEED_DELAY
- .irq = RK29_PIN0_PA2,
- .platform_data = &p1003_info,
- //.udelay = 100
- },
-#endif
-#if defined (CONFIG_EETI_EGALAX)
- {
- .type = "egalax_i2c",
- .addr = 0x04,
- .flags = 0,
- .irq = RK29_PIN0_PA2,
- .platform_data = &eeti_egalax_info,
- },
-#endif
-#if defined (CONFIG_TOUCHSCREEN_GT819)
- {
- .type = "Goodix-TS",
- .addr = 0x55,
- .flags =0,
- .irq =RK29_PIN0_PA2,
- .platform_data = &goodix_info,
- },
-#endif
-#if defined (CONFIG_TOUCHSCREEN_FT5406)
- {
- .type ="ft5x0x_ts",
- .addr = 0x38, //0x70,
- .flags =0,
- .irq =RK29_PIN0_PA2, // support goodix tp detect, 20110706
- .platform_data = &ft5406_info,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK29
-static struct i2c_board_info __initdata board_i2c3_devices[] = {
-#if defined (CONFIG_BATTERY_BQ27541)
- {
- .type = "bq27541",
- .addr = 0x55,
- .flags = 0,
- .platform_data = &bq27541_info,
- },
-#endif
-};
-#endif
-
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#define CONFIG_SENSOR_POWER_IOCTL_USR 0
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_RESET_IOCTL_USR
-static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
-static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-#include "../../../drivers/media/video/rk29_camera.c"
-#endif
-/*****************************************************************************************
- * backlight devices
- * author: nzy@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- /*
- GPIO1B5_PWM0_NAME, GPIO1L_PWM0
- GPIO5D2_PWM1_UART1SIRIN_NAME, GPIO5H_PWM1
- GPIO2A3_SDMMC0WRITEPRT_PWM2_NAME, GPIO2L_PWM2
- GPIO1A5_EMMCPWREN_PWM3_NAME, GPIO1L_PWM3
- */
-
-#define PWM_ID 0
-#define PWM_MUX_NAME GPIO1B5_PWM0_NAME
-#define PWM_MUX_MODE GPIO1L_PWM0
-#define PWM_MUX_MODE_GPIO GPIO1L_GPIO1B5
-#define PWM_GPIO RK29_PIN1_PB5
-#define PWM_EFFECT_VALUE 1
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-//#define BL_EN_MUX_NAME GPIOF34_UART3_SEL_NAME
-//#define BL_EN_MUX_MODE IOMUXB_GPIO1_B34
-
-#define BL_EN_PIN RK29_PIN6_PD0
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
-
- rk29_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
- #ifdef LCD_DISP_ON_PIN
- // rk29_mux_api_set(BL_EN_MUX_NAME, BL_EN_MUX_MODE);
-
- ret = gpio_request(BL_EN_PIN, NULL);
- if(ret != 0)
- {
- gpio_free(BL_EN_PIN);
- }
-
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
- #endif
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0;
- #ifdef LCD_DISP_ON_PIN
- gpio_free(BL_EN_PIN);
- #endif
- rk29_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
-
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret = 0;
- rk29_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- if (gpio_request(PWM_GPIO, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- gpio_direction_output(PWM_GPIO, GPIO_LOW);
- #ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, !BL_EN_VALUE);
- #endif
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- gpio_free(PWM_GPIO);
- rk29_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
-
- #ifdef LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, 1);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
- #endif
- return 0;
-}
-
-struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-#endif
-/*****************************************************************************************
-* pwm voltage regulator devices
-******************************************************************************************/
-#if defined (CONFIG_RK29_PWM_REGULATOR)
-
-#define REGULATOR_PWM_ID 2
-#define REGULATOR_PWM_MUX_NAME GPIO2A3_SDMMC0WRITEPRT_PWM2_NAME
-#define REGULATOR_PWM_MUX_MODE GPIO2L_PWM2
-#define REGULATOR_PWM_MUX_MODE_GPIO GPIO2L_GPIO2A3
-#define REGULATOR_PWM_GPIO RK29_PIN2_PA3
-
-static struct regulator_consumer_supply pwm_consumers[] = {
- {
- .supply = "vcore",
- }
-};
-
-static struct regulator_init_data rk29_pwm_regulator_data = {
- .constraints = {
- .name = "PWM2",
- .min_uV = 950000,
- .max_uV = 1400000,
- .apply_uV = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_consumers),
- .consumer_supplies = pwm_consumers,
-};
-
-static struct pwm_platform_data rk29_regulator_pwm_platform_data = {
- .pwm_id = REGULATOR_PWM_ID,
- .pwm_gpio = REGULATOR_PWM_GPIO,
- //.pwm_iomux_name[] = REGULATOR_PWM_MUX_NAME;
- .pwm_iomux_name = REGULATOR_PWM_MUX_NAME,
- .pwm_iomux_pwm = REGULATOR_PWM_MUX_MODE,
- .pwm_iomux_gpio = REGULATOR_PWM_MUX_MODE_GPIO,
- .init_data = &rk29_pwm_regulator_data,
-};
-
-static struct platform_device rk29_device_pwm_regulator = {
- .name = "pwm-voltage-regulator",
- .id = -1,
- .dev = {
- .platform_data = &rk29_regulator_pwm_platform_data,
- },
-};
-
-#endif
-
-/*****************************************************************************************
- * SDMMC devices
-*****************************************************************************************/
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
- rk29_mux_api_set(GPIO1D1_SDMMC0CMD_NAME, GPIO1H_SDMMC0_CMD);
- rk29_mux_api_set(GPIO1D0_SDMMC0CLKOUT_NAME, GPIO1H_SDMMC0_CLKOUT);
- rk29_mux_api_set(GPIO1D2_SDMMC0DATA0_NAME, GPIO1H_SDMMC0_DATA0);
- rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_SDMMC0_DATA1);
- rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_SDMMC0_DATA2);
- rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_SDMMC0_DATA3);
-
-#ifdef CONFIG_SDMMC_RK29_OLD
- rk29_mux_api_set(GPIO2A2_SDMMC0DETECTN_NAME, GPIO2L_GPIO2A2);
-#else
- rk29_mux_api_set(GPIO2A2_SDMMC0DETECTN_NAME, GPIO2L_SDMMC0_DETECT_N);//Modifyed by xbw.
-#endif
-
- rk29_mux_api_set(GPIO5D5_SDMMC0PWREN_NAME, GPIO5H_GPIO5D5); ///GPIO5H_SDMMC0_PWR_EN); ///GPIO5H_GPIO5D5);
- gpio_request(RK29_PIN5_PD5,"sdmmc");
-#if 0
- gpio_set_value(RK29_PIN5_PD5,GPIO_HIGH);
- mdelay(100);
- gpio_set_value(RK29_PIN5_PD5,GPIO_LOW);
-#else
- gpio_direction_output(RK29_PIN5_PD5,GPIO_LOW);
-#endif
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail = (MMC_VDD_25_26|MMC_VDD_26_27|MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30|
- MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33|
- MMC_VDD_33_34|MMC_VDD_34_35| MMC_VDD_35_36),
- .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
- .detect_irq = RK29_PIN2_PA2, // INVALID_GPIO
- .enable_sd_wakeup = 0,
-};
-#endif
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
- rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);
- rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);
- rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);
- rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_SDMMC1_DATA1);
- rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_SDMMC1_DATA2);
- rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_SDMMC1_DATA3);
- //rk29_mux_api_set(GPIO1C0_UART0CTSN_SDMMC1DETECTN_NAME, GPIO1H_SDMMC1_DETECT_N);
- return 0;
-}
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
-static int rk29sdk_wifi_status(struct device *dev);
-static int rk29sdk_wifi_status_register(void (*callback)(int card_presend, void *dev_id), void *dev_id);
-#endif
-
-#define RK29SDK_WIFI_SDIO_CARD_DETECT_N RK29_PIN1_PD6
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail = (MMC_VDD_25_26|MMC_VDD_26_27|MMC_VDD_27_28|MMC_VDD_28_29|
- MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32|
- MMC_VDD_32_33|MMC_VDD_33_34),
- .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_SDIO_IRQ|
- MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc1_cfg_gpio,
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-#if 0
- .detect_irq = RK29SDK_WIFI_SDIO_CARD_DETECT_N,
-#endif
-};
-#endif
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
-#define RK29SDK_WIFI_BT_GPIO_POWER_N RK29_PIN5_PD6
-#define RK29SDK_WIFI_GPIO_RESET_N RK29_PIN6_PC0
-#define RK29SDK_BT_GPIO_RESET_N RK29_PIN6_PC4
-
-static int rk29sdk_wifi_cd = 0; /* wifi virtual 'card detect' status */
-static void (*wifi_status_cb)(int card_present, void *dev_id);
-static void *wifi_status_cb_devid;
-int rk29sdk_wifi_power_state = 0;
-int rk29sdk_bt_power_state = 0;
-
-static int rk29sdk_wifi_status(struct device *dev)
-{
- return rk29sdk_wifi_cd;
-}
-
-static int rk29sdk_wifi_status_register(void (*callback)(int card_present, void *dev_id), void *dev_id)
-{
- if(wifi_status_cb)
- return -EAGAIN;
- wifi_status_cb = callback;
- wifi_status_cb_devid = dev_id;
- return 0;
-}
-
-static int rk29sdk_wifi_bt_gpio_control_init(void)
-{
- if (gpio_request(RK29SDK_WIFI_BT_GPIO_POWER_N, "wifi_bt_power")) {
- pr_info("%s: request wifi_bt power gpio failed\n", __func__);
- return -1;
- }
-
- if (gpio_request(RK29SDK_WIFI_GPIO_RESET_N, "wifi reset")) {
- pr_info("%s: request wifi reset gpio failed\n", __func__);
- gpio_free(RK29SDK_WIFI_BT_GPIO_POWER_N);
- return -1;
- }
-
- if (gpio_request(RK29SDK_BT_GPIO_RESET_N, "bt reset")) {
- pr_info("%s: request bt reset gpio failed\n", __func__);
- gpio_free(RK29SDK_WIFI_GPIO_RESET_N);
- return -1;
- }
-
- gpio_direction_output(RK29SDK_WIFI_BT_GPIO_POWER_N, GPIO_LOW);
- gpio_direction_output(RK29SDK_WIFI_GPIO_RESET_N, GPIO_LOW);
- gpio_direction_output(RK29SDK_BT_GPIO_RESET_N, GPIO_LOW);
-
- pr_info("%s: init finished\n",__func__);
-
- return 0;
-}
-
-static int rk29sdk_wifi_power(int on)
-{
- pr_info("%s: %d\n", __func__, on);
- if (on){
- gpio_set_value(RK29SDK_WIFI_BT_GPIO_POWER_N, GPIO_HIGH);
- gpio_set_value(RK29SDK_WIFI_GPIO_RESET_N, GPIO_HIGH);
- mdelay(100);
- pr_info("wifi turn on power\n");
- }else{
- if (!rk29sdk_bt_power_state){
- gpio_set_value(RK29SDK_WIFI_BT_GPIO_POWER_N, GPIO_LOW);
- mdelay(100);
- pr_info("wifi shut off power\n");
- }else
- {
- pr_info("wifi shouldn't shut off power, bt is using it!\n");
- }
- gpio_set_value(RK29SDK_WIFI_GPIO_RESET_N, GPIO_LOW);
-
- }
-
- rk29sdk_wifi_power_state = on;
- return 0;
-}
-
-static int rk29sdk_wifi_reset_state;
-static int rk29sdk_wifi_reset(int on)
-{
- pr_info("%s: %d\n", __func__, on);
- gpio_set_value(RK29SDK_WIFI_GPIO_RESET_N, on);
- mdelay(100);
- rk29sdk_wifi_reset_state = on;
- return 0;
-}
-
-int rk29sdk_wifi_set_carddetect(int val)
-{
- pr_info("%s:%d\n", __func__, val);
- rk29sdk_wifi_cd = val;
- if (wifi_status_cb){
- wifi_status_cb(val, wifi_status_cb_devid);
- }else {
- pr_warning("%s, nobody to notify\n", __func__);
- }
- return 0;
-}
-EXPORT_SYMBOL(rk29sdk_wifi_set_carddetect);
-
-static struct wifi_mem_prealloc wifi_mem_array[PREALLOC_WLAN_SEC_NUM] = {
- {NULL, (WLAN_SECTION_SIZE_0 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_1 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_2 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_3 + PREALLOC_WLAN_SECTION_HEADER)}
-};
-
-static void *rk29sdk_mem_prealloc(int section, unsigned long size)
-{
- if (section == PREALLOC_WLAN_SEC_NUM)
- return wlan_static_skb;
-
- if ((section < 0) || (section > PREALLOC_WLAN_SEC_NUM))
- return NULL;
-
- if (wifi_mem_array[section].size < size)
- return NULL;
-
- return wifi_mem_array[section].mem_ptr;
-}
-
-int __init rk29sdk_init_wifi_mem(void)
-{
- int i;
- int j;
-
- for (i = 0 ; i < WLAN_SKB_BUF_NUM ; i++) {
- wlan_static_skb[i] = dev_alloc_skb(
- ((i < (WLAN_SKB_BUF_NUM / 2)) ? 4096 : 8192));
-
- if (!wlan_static_skb[i])
- goto err_skb_alloc;
- }
-
- for (i = 0 ; i < PREALLOC_WLAN_SEC_NUM ; i++) {
- wifi_mem_array[i].mem_ptr =
- kmalloc(wifi_mem_array[i].size, GFP_KERNEL);
-
- if (!wifi_mem_array[i].mem_ptr)
- goto err_mem_alloc;
- }
- return 0;
-
-err_mem_alloc:
- pr_err("Failed to mem_alloc for WLAN\n");
- for (j = 0 ; j < i ; j++)
- kfree(wifi_mem_array[j].mem_ptr);
-
- i = WLAN_SKB_BUF_NUM;
-
-err_skb_alloc:
- pr_err("Failed to skb_alloc for WLAN\n");
- for (j = 0 ; j < i ; j++)
- dev_kfree_skb(wlan_static_skb[j]);
-
- return -ENOMEM;
-}
-
-static struct wifi_platform_data rk29sdk_wifi_control = {
- .set_power = rk29sdk_wifi_power,
- .set_reset = rk29sdk_wifi_reset,
- .set_carddetect = rk29sdk_wifi_set_carddetect,
- .mem_prealloc = rk29sdk_mem_prealloc,
-};
-static struct platform_device rk29sdk_wifi_device = {
- .name = "bcm4329_wlan",
- .id = 1,
- .dev = {
- .platform_data = &rk29sdk_wifi_control,
- },
-};
-#endif
-
-
-/* bluetooth rfkill device */
-static struct platform_device rk29sdk_rfkill = {
- .name = "rk29sdk_rfkill",
- .id = -1,
-};
-
-
-#ifdef CONFIG_VIVANTE
-#define GPU_HIGH_CLOCK 552
-#define GPU_LOW_CLOCK (periph_pll_default / 1000000) /* same as general pll clock rate below */
-static struct resource resources_gpu[] = {
- [0] = {
- .name = "gpu_irq",
- .start = IRQ_GPU,
- .end = IRQ_GPU,
- .flags = IORESOURCE_IRQ,
- },
- [1] = {
- .name = "gpu_base",
- .start = RK29_GPU_PHYS,
- .end = RK29_GPU_PHYS + RK29_GPU_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "gpu_mem",
- .start = PMEM_GPU_BASE,
- .end = PMEM_GPU_BASE + PMEM_GPU_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [3] = {
- .name = "gpu_clk",
- .start = GPU_LOW_CLOCK,
- .end = GPU_HIGH_CLOCK,
- .flags = IORESOURCE_IO,
- },
-};
-static struct platform_device rk29_device_gpu = {
- .name = "galcore",
- .id = 0,
- .num_resources = ARRAY_SIZE(resources_gpu),
- .resource = resources_gpu,
-};
-#endif
-
-#ifdef CONFIG_KEYS_RK29
-extern struct rk29_keys_platform_data rk29_keys_pdata;
-static struct platform_device rk29_device_keys = {
- .name = "rk29-keypad",
- .id = -1,
- .dev = {
- .platform_data = &rk29_keys_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
-struct gpio_led rk29_leds[] = {
- {
- .name = "rk29_red_led",
- .gpio = RK29_PIN4_PB2,
- .default_trigger = "timer",
- .active_low = 0,
- .retain_state_suspended = 1,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- },
- {
- .name = "rk29_green_led",
- .gpio = RK29_PIN4_PB1,
- .default_trigger = "timer",
- .active_low = 0,
- .retain_state_suspended = 1,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- },
- {
- .name = "rk29_blue_led",
- .gpio = RK29_PIN4_PB0,
- .default_trigger = "timer",
- .active_low = 0,
- .retain_state_suspended = 1,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- },
-};
-
-struct gpio_led_platform_data rk29_leds_pdata = {
- .leds = &rk29_leds,
- .num_leds = ARRAY_SIZE(rk29_leds),
-};
-
-struct platform_device rk29_device_gpio_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_leds_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_LEDS_NEWTON_PWM
-static struct led_newton_pwm rk29_pwm_leds[] = {
- {
- .name = "power_led",
- .pwm_id = 1,
- .pwm_gpio = RK29_PIN5_PD2,
- .pwm_iomux_name = GPIO5D2_PWM1_UART1SIRIN_NAME,
- .pwm_iomux_pwm = GPIO5H_PWM1,
- .pwm_iomux_gpio = GPIO5H_GPIO5D2,
- .freq = 1000,
- .period = 255,
- },
-};
-
-static struct led_newton_pwm_platform_data rk29_pwm_leds_pdata = {
- .leds = &rk29_pwm_leds,
- .num_leds = ARRAY_SIZE(rk29_pwm_leds),
-};
-
-static struct platform_device rk29_device_pwm_leds = {
- .name = "leds_newton_pwm",
- .id = -1,
- .dev = {
- .platform_data = &rk29_pwm_leds_pdata,
- },
-};
-
-#endif
-static void __init rk29_board_iomux_init(void)
-{
- #ifdef CONFIG_RK29_PWM_REGULATOR
- rk29_mux_api_set(REGULATOR_PWM_MUX_NAME,REGULATOR_PWM_MUX_MODE);
- #endif
-}
-
-static struct platform_device *devices[] __initdata = {
-
-#ifdef CONFIG_RK29_WATCHDOG
- &rk29_device_wdt,
-#endif
-
-#ifdef CONFIG_UART1_RK29
- &rk29_device_uart1,
-#endif
-#ifdef CONFIG_UART0_RK29
- &rk29_device_uart0,
-#endif
-#ifdef CONFIG_UART2_RK29
- &rk29_device_uart2,
-#endif
-#ifdef CONFIG_UART3_RK29
- &rk29_device_uart3,
-#endif
-
-#ifdef CONFIG_RK29_PWM_REGULATOR
- &rk29_device_pwm_regulator,
-#endif
-#ifdef CONFIG_SPIM0_RK29
- &rk29xx_device_spi0m,
-#endif
-#ifdef CONFIG_SPIM1_RK29
- &rk29xx_device_spi1m,
-#endif
-#ifdef CONFIG_ADC_RK29
- &rk29_device_adc,
-#endif
-#ifdef CONFIG_I2C0_RK29
- &rk29_device_i2c0,
-#endif
-#ifdef CONFIG_I2C1_RK29
- &rk29_device_i2c1,
-#endif
-#ifdef CONFIG_I2C2_RK29
- &rk29_device_i2c2,
-#endif
-#ifdef CONFIG_I2C3_RK29
- &rk29_device_i2c3,
-#endif
-
-#ifdef CONFIG_SND_RK29_SOC_I2S_2CH
- &rk29_device_iis_2ch,
-#endif
-#ifdef CONFIG_SND_RK29_SOC_I2S_8CH
- &rk29_device_iis_8ch,
-#endif
-
-#ifdef CONFIG_KEYS_RK29
- &rk29_device_keys,
-#endif
-#ifdef CONFIG_KEYS_RK29_NEWTON
- &rk29_device_keys,
-#endif
-#ifdef CONFIG_SDMMC0_RK29
- &rk29_device_sdmmc0,
-#endif
-#ifdef CONFIG_SDMMC1_RK29
- &rk29_device_sdmmc1,
-#endif
-
-#ifdef CONFIG_MTD_NAND_RK29XX
- &rk29xx_device_nand,
-#endif
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- &rk29sdk_wifi_device,
-#endif
-
-#ifdef CONFIG_BT
- &rk29sdk_rfkill,
-#endif
-
-#ifdef CONFIG_MTD_NAND_RK29
- &rk29_device_nand,
-#endif
-
-#ifdef CONFIG_FB_RK29
- &rk29_device_fb,
- &rk29_device_dma_cpy,
-#endif
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- &rk29_device_backlight,
-#endif
-#ifdef CONFIG_BACKLIGHT_RK29_NEWTON_BL
- &rk29_device_backlight,
-#endif
-#ifdef CONFIG_RK29_VMAC
- &rk29_device_vmac,
-#endif
-#ifdef CONFIG_VIVANTE
- &rk29_device_gpu,
-#endif
-#ifdef CONFIG_VIDEO_RK29
- &rk29_device_camera, /* ddl@rock-chips.com : camera support */
- #if (CONFIG_SENSOR_IIC_ADDR_0 != 0x00)
- &rk29_soc_camera_pdrv_0,
- #endif
- &rk29_soc_camera_pdrv_1,
- &android_pmem_cam_device,
-#endif
- &android_pmem_device,
- &rk29_vpu_mem_device,
-#ifdef CONFIG_USB20_OTG
- &rk29_device_usb20_otg,
-#endif
-#ifdef CONFIG_USB20_HOST
- &rk29_device_usb20_host,
-#endif
-#ifdef CONFIG_USB11_HOST
- &rk29_device_usb11_host,
-#endif
-#ifdef CONFIG_USB_ANDROID
- &android_usb_device,
- &usb_mass_storage_device,
-#endif
-#ifdef CONFIG_USB_ANDROID_RNDIS
- &rk29_device_rndis,
-#endif
-#ifdef CONFIG_RK29_IPP
- &rk29_device_ipp,
-#endif
-#ifdef CONFIG_VIDEO_RK29XX_VOUT
- &rk29_v4l2_output_devce,
-#endif
-#ifdef CONFIG_RK29_NEWTON
- &rk29_device_newton,
-#endif
-#ifdef CONFIG_RK_IRDA
- &irda_device,
-#endif
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
- &rk29_device_gpio_leds,
-#endif
-#ifdef CONFIG_LEDS_NEWTON_PWM
- &rk29_device_pwm_leds,
-#endif
-#ifdef CONFIG_SND_RK29_SOC_CS42L52
- &rk29_cs42l52_device,
-#endif
-};
-
-/*****************************************************************************************
- * spi devices
- * author: cmc@rock-chips.com
- *****************************************************************************************/
-static int rk29_vmac_register_set(void)
-{
- //config rk29 vmac as rmii, 100MHz
- u32 value= readl(RK29_GRF_BASE + 0xbc);
- value = (value & 0xfff7ff) | (0x400);
- writel(value, RK29_GRF_BASE + 0xbc);
- return 0;
-}
-
-static int rk29_rmii_io_init(void)
-{
- int err;
-
- //phy power gpio
- err = gpio_request(RK29_PIN6_PB0, "phy_power_en");
- if (err) {
- gpio_free(RK29_PIN6_PB0);
- printk("-------request RK29_PIN6_PB0 fail--------\n");
- return -1;
- }
- //phy power down
- gpio_direction_output(RK29_PIN6_PB0, GPIO_LOW);
- gpio_set_value(RK29_PIN6_PB0, GPIO_LOW);
-
- return 0;
-}
-
-static int rk29_rmii_io_deinit(void)
-{
- //phy power down
- gpio_direction_output(RK29_PIN6_PB0, GPIO_LOW);
- gpio_set_value(RK29_PIN6_PB0, GPIO_LOW);
- //free
- gpio_free(RK29_PIN6_PB0);
- return 0;
-}
-
-static int rk29_rmii_power_control(int enable)
-{
- if (enable) {
- //enable phy power
- gpio_direction_output(RK29_PIN6_PB0, GPIO_HIGH);
- gpio_set_value(RK29_PIN6_PB0, GPIO_HIGH);
- }
- else {
- gpio_direction_output(RK29_PIN6_PB0, GPIO_LOW);
- gpio_set_value(RK29_PIN6_PB0, GPIO_LOW);
- }
- return 0;
-}
-
-struct rk29_vmac_platform_data rk29_vmac_pdata = {
- .vmac_register_set = rk29_vmac_register_set,
- .rmii_io_init = rk29_rmii_io_init,
- .rmii_io_deinit = rk29_rmii_io_deinit,
- .rmii_power_control = rk29_rmii_power_control,
-};
-
-/*****************************************************************************************
- * spi devices
- * author: cmc@rock-chips.com
- *****************************************************************************************/
-#define SPI_CHIPSELECT_NUM 2
-static struct spi_cs_gpio rk29xx_spi0_cs_gpios[SPI_CHIPSELECT_NUM] = {
- {
- .name = "spi0 cs0",
- .cs_gpio = RK29_PIN2_PC1,
- .cs_iomux_name = GPIO2C1_SPI0CSN0_NAME,
- .cs_iomux_mode = GPIO2H_SPI0_CSN0,
- },
- {
- .name = "spi0 cs1",
- .cs_gpio = RK29_PIN1_PA4,
- .cs_iomux_name = GPIO1A4_EMMCWRITEPRT_SPI0CS1_NAME,//if no iomux,set it NULL
- .cs_iomux_mode = GPIO1L_SPI0_CSN1,
- }
-};
-
-static struct spi_cs_gpio rk29xx_spi1_cs_gpios[SPI_CHIPSELECT_NUM] = {
- {
- .name = "spi1 cs0",
- .cs_gpio = RK29_PIN2_PC5,
- .cs_iomux_name = GPIO2C5_SPI1CSN0_NAME,
- .cs_iomux_mode = GPIO2H_SPI1_CSN0,
- },
- {
- .name = "spi1 cs1",
- .cs_gpio = RK29_PIN1_PA3,
- .cs_iomux_name = GPIO1A3_EMMCDETECTN_SPI1CS1_NAME,//if no iomux,set it NULL
- .cs_iomux_mode = GPIO1L_SPI1_CSN1,
- }
-};
-
-static int spi_io_init(struct spi_cs_gpio *cs_gpios, int cs_num)
-{
-#if 1
- int i;
- if (cs_gpios) {
- for (i=0; i<cs_num; i++) {
- rk29_mux_api_set(cs_gpios[i].cs_iomux_name, cs_gpios[i].cs_iomux_mode);
- }
- }
-#endif
- return 0;
-}
-
-static int spi_io_deinit(struct spi_cs_gpio *cs_gpios, int cs_num)
-{
- return 0;
-}
-
-static int spi_io_fix_leakage_bug(void)
-{
-#if 0
- gpio_direction_output(RK29_PIN2_PC1, GPIO_LOW);
-#endif
- return 0;
-}
-
-static int spi_io_resume_leakage_bug(void)
-{
-#if 0
- gpio_direction_output(RK29_PIN2_PC1, GPIO_HIGH);
-#endif
- return 0;
-}
-
-struct rk29xx_spi_platform_data rk29xx_spi0_platdata = {
- .num_chipselect = SPI_CHIPSELECT_NUM,
- .chipselect_gpios = rk29xx_spi0_cs_gpios,
- .io_init = spi_io_init,
- .io_deinit = spi_io_deinit,
- .io_fix_leakage_bug = spi_io_fix_leakage_bug,
- .io_resume_leakage_bug = spi_io_resume_leakage_bug,
-};
-
-struct rk29xx_spi_platform_data rk29xx_spi1_platdata = {
- .num_chipselect = SPI_CHIPSELECT_NUM,
- .chipselect_gpios = rk29xx_spi1_cs_gpios,
- .io_init = spi_io_init,
- .io_deinit = spi_io_deinit,
- .io_fix_leakage_bug = spi_io_fix_leakage_bug,
- .io_resume_leakage_bug = spi_io_resume_leakage_bug,
-};
-
-/*****************************************************************************************
- * xpt2046 touch panel
- * author: cmc@rock-chips.com
- *****************************************************************************************/
-#define XPT2046_GPIO_INT RK29_PIN0_PA3
-#define DEBOUNCE_REPTIME 3
-
-#if defined(CONFIG_TOUCHSCREEN_XPT2046_320X480_SPI)
-static struct xpt2046_platform_data xpt2046_info = {
- .model = 2046,
- .keep_vref_on = 1,
- .swap_xy = 0,
- .x_min = 0,
- .x_max = 320,
- .y_min = 0,
- .y_max = 480,
- .debounce_max = 7,
- .debounce_rep = DEBOUNCE_REPTIME,
- .debounce_tol = 20,
- .gpio_pendown = XPT2046_GPIO_INT,
- .penirq_recheck_delay_usecs = 1,
-};
-#elif defined(CONFIG_TOUCHSCREEN_XPT2046_320X480_CBN_SPI)
-static struct xpt2046_platform_data xpt2046_info = {
- .model = 2046,
- .keep_vref_on = 1,
- .swap_xy = 0,
- .x_min = 0,
- .x_max = 320,
- .y_min = 0,
- .y_max = 480,
- .debounce_max = 7,
- .debounce_rep = DEBOUNCE_REPTIME,
- .debounce_tol = 20,
- .gpio_pendown = XPT2046_GPIO_INT,
- .penirq_recheck_delay_usecs = 1,
-};
-#elif defined(CONFIG_TOUCHSCREEN_XPT2046_SPI)
-static struct xpt2046_platform_data xpt2046_info = {
- .model = 2046,
- .keep_vref_on = 1,
- .swap_xy = 1,
- .x_min = 0,
- .x_max = 800,
- .y_min = 0,
- .y_max = 480,
- .debounce_max = 7,
- .debounce_rep = DEBOUNCE_REPTIME,
- .debounce_tol = 20,
- .gpio_pendown = XPT2046_GPIO_INT,
-
- .penirq_recheck_delay_usecs = 1,
-};
-#elif defined(CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI)
-static struct xpt2046_platform_data xpt2046_info = {
- .model = 2046,
- .keep_vref_on = 1,
- .swap_xy = 1,
- .x_min = 0,
- .x_max = 800,
- .y_min = 0,
- .y_max = 480,
- .debounce_max = 7,
- .debounce_rep = DEBOUNCE_REPTIME,
- .debounce_tol = 20,
- .gpio_pendown = XPT2046_GPIO_INT,
-
- .penirq_recheck_delay_usecs = 1,
-};
-#endif
-
-static struct spi_board_info board_spi_devices[] = {
-#if defined(CONFIG_TOUCHSCREEN_XPT2046_320X480_SPI) || defined(CONFIG_TOUCHSCREEN_XPT2046_320X480_CBN_SPI)\
- ||defined(CONFIG_TOUCHSCREEN_XPT2046_SPI) || defined(CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI)
- {
- .modalias = "xpt2046_ts",
- .chip_select = 0,
- .max_speed_hz = 125 * 1000 * 26,/* (max sample rate @ 3V) * (cmd + data + overhead) */
- .bus_num = 0,
- .irq = XPT2046_GPIO_INT,
- .platform_data = &xpt2046_info,
- },
-#endif
-};
-
-
-static void __init rk29_gic_init_irq(void)
-{
- gic_dist_init(0, (void __iomem *)RK29_GICPERI_BASE, 32);
- gic_cpu_init(0, (void __iomem *)RK29_GICCPU_BASE);
-}
-
-static void __init machine_rk29_init_irq(void)
-{
- rk29_gic_init_irq();
- rk29_gpio_init();
-}
-
-static void __init machine_rk29_board_init(void)
-{
- rk29_board_iomux_init();
-
- board_power_init();
-
- platform_add_devices(devices, ARRAY_SIZE(devices));
-#ifdef CONFIG_I2C0_RK29
- i2c_register_board_info(default_i2c0_data.bus_num, board_i2c0_devices,
- ARRAY_SIZE(board_i2c0_devices));
-#endif
-#ifdef CONFIG_I2C1_RK29
- i2c_register_board_info(default_i2c1_data.bus_num, board_i2c1_devices,
- ARRAY_SIZE(board_i2c1_devices));
-#endif
-#ifdef CONFIG_I2C2_RK29
- i2c_register_board_info(default_i2c2_data.bus_num, board_i2c2_devices,
- ARRAY_SIZE(board_i2c2_devices));
-#endif
-#ifdef CONFIG_I2C3_RK29
- i2c_register_board_info(default_i2c3_data.bus_num, board_i2c3_devices,
- ARRAY_SIZE(board_i2c3_devices));
-#endif
-
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- rk29sdk_wifi_bt_gpio_control_init();
- rk29sdk_init_wifi_mem();
-#endif
-
- board_usb_detect_init(RK29_PIN0_PA0);
-#if defined(CONFIG_RK_IRDA) || defined(CONFIG_BU92747GUW_CIR)
- smc0_init(NULL);
- bu92747guw_io_init();
-#endif
-
-}
-
-static void __init machine_rk29_fixup(struct machine_desc *desc, struct tag *tags,
- char **cmdline, struct meminfo *mi)
-{
- mi->nr_banks = 1;
- mi->bank[0].start = RK29_SDRAM_PHYS;
- mi->bank[0].size = LINUX_SIZE;
-#if SDRAM_SIZE > SZ_512M
- mi->nr_banks = 2;
- mi->bank[1].start = RK29_SDRAM_PHYS + SZ_512M;
- mi->bank[1].size = SDRAM_SIZE - SZ_512M;
-#endif
-}
-
-static void __init machine_rk29_mapio(void)
-{
- rk29_map_common_io();
- rk29_setup_early_printk();
- rk29_sram_init();
- rk29_clock_init(periph_pll_default);
- rk29_iomux_init();
- ddr_init(DDR_TYPE,DDR_FREQ); // DDR3_1333H, 400
-}
-
-MACHINE_START(RK29, "RK29board")
- /* UART for LL DEBUG */
- .phys_io = RK29_UART1_PHYS & 0xfff00000,
- .io_pg_offst = ((RK29_UART1_BASE) >> 18) & 0xfffc,
- .boot_params = RK29_SDRAM_PHYS + 0x88000,
- .fixup = machine_rk29_fixup,
- .map_io = machine_rk29_mapio,
- .init_irq = machine_rk29_init_irq,
- .init_machine = machine_rk29_board_init,
- .timer = &rk29_timer,
-MACHINE_END
+++ /dev/null
-/* arch/arm/mach-rk29/clock.c
- *
- * Copyright (C) 2010, 2011 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-//#define DEBUG
-#define pr_fmt(fmt) "clock: %s: " fmt, __func__
-
-#include <linux/clk.h>
-#include <linux/debugfs.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/module.h>
-#include <linux/version.h>
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
-#include <linux/clkdev.h>
-#else
-#include <asm/clkdev.h>
-#endif
-#include <mach/rk29_iomap.h>
-#include <mach/cru.h>
-#include <mach/pmu.h>
-#include <mach/sram.h>
-#include <mach/board.h>
-#include <mach/clock.h>
-
-
-/* Clock flags */
-/* bit 0 is free */
-#define RATE_FIXED (1 << 1) /* Fixed clock rate */
-#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */
-#define IS_PD (1 << 2) /* Power Domain */
-
-#define regfile_readl(offset) readl(RK29_GRF_BASE + offset)
-#define pmu_readl(offset) readl(RK29_PMU_BASE + offset)
-
-#define MHZ (1000*1000)
-#define KHZ 1000
-
-struct clk {
- struct list_head node;
- const char *name;
- struct clk *parent;
- struct list_head children;
- struct list_head sibling; /* node for children */
- unsigned long rate;
- u32 flags;
- int (*mode)(struct clk *clk, int on);
- unsigned long (*recalc)(struct clk *); /* if null, follow parent */
- int (*set_rate)(struct clk *, unsigned long);
- long (*round_rate)(struct clk *, unsigned long);
- struct clk* (*get_parent)(struct clk *); /* get clk's parent from the hardware. default is clksel_get_parent if parents present */
- int (*set_parent)(struct clk *, struct clk *); /* default is clksel_set_parent if parents present */
- s16 usecount;
- u16 notifier_count;
- u8 gate_idx;
- u8 pll_idx;
- u8 clksel_con;
- u8 clksel_mask;
- u8 clksel_shift;
- u8 clksel_maxdiv;
- u8 clksel_parent_mask;
- u8 clksel_parent_shift;
- struct clk **parents;
-};
-
-static void clk_notify(struct clk *clk, unsigned long msg,
- unsigned long old_rate, unsigned long new_rate);
-static int clk_enable_nolock(struct clk *clk);
-static void clk_disable_nolock(struct clk *clk);
-static int clk_set_rate_nolock(struct clk *clk, unsigned long rate);
-static int clk_set_parent_nolock(struct clk *clk, struct clk *parent);
-static void __clk_reparent(struct clk *child, struct clk *parent);
-static void __propagate_rate(struct clk *tclk);
-static struct clk codec_pll_clk;
-static struct clk general_pll_clk;
-static bool has_xin27m = true;
-
-static unsigned long clksel_recalc_div(struct clk *clk)
-{
- u32 div = ((cru_readl(clk->clksel_con) >> clk->clksel_shift) & clk->clksel_mask) + 1;
- unsigned long rate = clk->parent->rate / div;
- pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, div);
- return rate;
-}
-
-static unsigned long clksel_recalc_shift(struct clk *clk)
-{
- u32 shift = (cru_readl(clk->clksel_con) >> clk->clksel_shift) & clk->clksel_mask;
- unsigned long rate = clk->parent->rate >> shift;
- pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
- return rate;
-}
-
-static unsigned long clksel_recalc_frac(struct clk *clk)
-{
- unsigned long rate;
- u64 rate64;
- u32 r = cru_readl(clk->clksel_con), numerator, denominator;
- if (r == 0) // FPGA ?
- return clk->parent->rate;
- numerator = r >> 16;
- denominator = r & 0xFFFF;
- rate64 = (u64)clk->parent->rate * numerator;
- do_div(rate64, denominator);
- rate = rate64;
- pr_debug("%s new clock rate is %lu (frac %u/%u)\n", clk->name, rate, numerator, denominator);
- return rate;
-}
-
-static int clksel_set_rate_div(struct clk *clk, unsigned long rate)
-{
- u32 div;
-
- for (div = 0; div <= clk->clksel_mask; div++) {
- u32 new_rate = clk->parent->rate / (div + 1);
- if (new_rate <= rate) {
- u32 v = cru_readl(clk->clksel_con);
- v &= ~((u32) clk->clksel_mask << clk->clksel_shift);
- v |= div << clk->clksel_shift;
- cru_writel(v, clk->clksel_con);
- clk->rate = new_rate;
- pr_debug("clksel_set_rate_div for clock %s to rate %ld (div %d)\n", clk->name, rate, div + 1);
- return 0;
- }
- }
-
- return -ENOENT;
-}
-
-static long clksel_round_rate_div_by_parent(struct clk *clk, unsigned long rate, struct clk *parent, unsigned long max_rate)
-{
- u32 div;
- unsigned long prev = ULONG_MAX, actual = parent->rate;
-
- if (max_rate < rate)
- max_rate = rate;
- for (div = 0; div <= clk->clksel_mask; div++) {
- actual = parent->rate / (div + 1);
- if (actual > max_rate)
- continue;
- if (actual > rate)
- prev = actual;
- if (actual && actual <= rate) {
- if ((prev - rate) <= (rate - actual)) {
- actual = prev;
- div--;
- }
- break;
- }
- }
- if (div > clk->clksel_mask)
- div = clk->clksel_mask;
- pr_debug("clock %s, target rate %ld, max rate %ld, rounded rate %ld (div %d)\n", clk->name, rate, max_rate, actual, div + 1);
-
- return actual;
-}
-
-#if 0
-static long clksel_round_rate_div(struct clk *clk, unsigned long rate)
-{
- return clksel_round_rate_div_by_parent(clk, rate, clk->parent, ULONG_MAX);
-}
-#endif
-
-static int clksel_set_rate_shift(struct clk *clk, unsigned long rate)
-{
- u32 shift;
-
- for (shift = 0; (1 << shift) <= clk->clksel_maxdiv; shift++) {
- u32 new_rate = clk->parent->rate >> shift;
- if (new_rate <= rate) {
- u32 v = cru_readl(clk->clksel_con);
- v &= ~((u32) clk->clksel_mask << clk->clksel_shift);
- v |= shift << clk->clksel_shift;
- cru_writel(v, clk->clksel_con);
- clk->rate = new_rate;
- pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n", clk->name, rate, shift);
- return 0;
- }
- }
-
- return -ENOENT;
-}
-
-static struct clk* clksel_get_parent(struct clk *clk)
-{
- return clk->parents[(cru_readl(clk->clksel_con) >> clk->clksel_parent_shift) & clk->clksel_parent_mask];
-}
-
-static int clksel_set_parent(struct clk *clk, struct clk *parent)
-{
- struct clk **p = clk->parents;
- u32 i;
-
- if (unlikely(!p))
- return -EINVAL;
- for (i = 0; (i <= clk->clksel_parent_mask) && *p; i++, p++) {
- u32 v;
- if (*p != parent)
- continue;
- v = cru_readl(clk->clksel_con);
- v &= ~((u32) clk->clksel_parent_mask << clk->clksel_parent_shift);
- v |= (i << clk->clksel_parent_shift);
- cru_writel(v, clk->clksel_con);
- return 0;
- }
- return -EINVAL;
-}
-
-/* Work around CRU_CLKGATE3_CON bit21~20 bug */
-volatile u32 cru_clkgate3_con_mirror;
-
-static int gate_mode(struct clk *clk, int on)
-{
- unsigned long flags;
- u32 reg;
- int idx = clk->gate_idx;
- u32 v;
-
- if (idx >= CLK_GATE_MAX)
- return -EINVAL;
-
- reg = CRU_CLKGATE0_CON;
- reg += (idx >> 5) << 2;
- idx &= 0x1F;
-
- /* ddr reconfig may change gate */
- local_irq_save(flags);
-
- if (reg == CRU_CLKGATE3_CON)
- v = cru_clkgate3_con_mirror;
- else
- v = cru_readl(reg);
-
- if (on)
- v &= ~(1 << idx); // clear bit
- else
- v |= (1 << idx); // set bit
-
- if (reg == CRU_CLKGATE3_CON)
- cru_clkgate3_con_mirror = v;
- cru_writel(v, reg);
-
- local_irq_restore(flags);
- return 0;
-}
-
-/* Work around CRU_SOFTRST0_CON bit29~27 bug */
-static volatile u32 cru_softrst0_con_mirror;
-
-void cru_set_soft_reset(enum cru_soft_reset idx, bool on)
-{
- unsigned long flags;
- u32 reg = CRU_SOFTRST0_CON + ((idx >> 5) << 2);
- u32 mask = 1 << (idx & 31);
- u32 v;
-
- if (idx >= SOFT_RST_MAX)
- return;
-
- local_irq_save(flags);
-
- if (reg == CRU_SOFTRST0_CON)
- v = cru_softrst0_con_mirror;
- else
- v = cru_readl(reg);
-
- if (on)
- v |= mask;
- else
- v &= ~mask;
-
- if (reg == CRU_SOFTRST0_CON)
- cru_softrst0_con_mirror = v;
- cru_writel(v, reg);
-
- local_irq_restore(flags);
-}
-EXPORT_SYMBOL(cru_set_soft_reset);
-
-static struct clk xin24m = {
- .name = "xin24m",
- .rate = 24 * MHZ,
- .flags = RATE_FIXED,
-};
-
-static struct clk clk_12m = {
- .name = "clk_12m",
- .rate = 12 * MHZ,
- .parent = &xin24m,
- .flags = RATE_FIXED,
-};
-
-static struct clk xin27m = {
- .name = "xin27m",
- .rate = 27 * MHZ,
- .flags = RATE_FIXED,
-};
-
-static struct clk otgphy0_clkin = {
- .name = "otgphy0_clkin",
- .rate = 480 * MHZ,
- .flags = RATE_FIXED,
-};
-
-static struct clk otgphy1_clkin = {
- .name = "otgphy1_clkin",
- .rate = 480 * MHZ,
- .flags = RATE_FIXED,
-};
-
-
-static noinline void delay_500ns(void)
-{
- udelay(1);
-}
-
-static noinline void delay_300us(void)
-{
- udelay(300);
-}
-
-#define GENERAL_PLL_IDX 0
-#define CODEC_PLL_IDX 1
-#define ARM_PLL_IDX 2
-#define DDR_PLL_IDX 3
-
-#define GRF_SOC_CON0 0xbc
-static void pll_wait_lock(int pll_idx)
-{
- u32 bit = 0x2000000u << pll_idx;
- int delay = 2400000;
- while (delay > 0) {
- if (regfile_readl(GRF_SOC_CON0) & bit)
- break;
- delay--;
- }
- if (delay == 0) {
- pr_warning("wait pll bit 0x%x time out!\n", bit);
- }
-}
-
-static unsigned long arm_pll_clk_recalc(struct clk *clk)
-{
- unsigned long rate;
-
- if ((cru_readl(CRU_MODE_CON) & CRU_CPU_MODE_MASK) == CRU_CPU_MODE_NORMAL) {
- u32 v = cru_readl(CRU_APLL_CON);
- u64 rate64 = (u64) clk->parent->rate * PLL_NF2(v);
- do_div(rate64, PLL_NR(v));
- rate = rate64 >> PLL_NO_SHIFT(v);
- pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF2(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
- } else {
- rate = clk->parent->rate;
- pr_debug("%s new clock rate is %ld (slow mode)\n", clk->name, rate);
- }
-
- return rate;
-}
-
-struct arm_pll_set {
- unsigned long rate;
- u32 apll_con;
- u32 clksel0_con;
- unsigned long lpj;
-};
-
-#define CORE_ACLK_11 (0 << 5)
-#define CORE_ACLK_21 (1 << 5)
-#define CORE_ACLK_31 (2 << 5)
-#define CORE_ACLK_41 (3 << 5)
-#define CORE_ACLK_81 (4 << 5)
-#define CORE_ACLK_MASK (7 << 5)
-
-#define ACLK_HCLK_11 (0 << 8)
-#define ACLK_HCLK_21 (1 << 8)
-#define ACLK_HCLK_41 (2 << 8)
-#define ACLK_HCLK_MASK (3 << 8)
-
-#define ACLK_PCLK_11 (0 << 10)
-#define ACLK_PCLK_21 (1 << 10)
-#define ACLK_PCLK_41 (2 << 10)
-#define ACLK_PCLK_81 (3 << 10)
-#define ACLK_PCLK_MASK (3 << 10)
-
-#define LPJ_600MHZ 2998368ULL
-static unsigned long lpj_gpll;
-
-#define ARM_PLL(_mhz, nr, nf, no, _axi_div, _ahb_div, _apb_div) \
-{ \
- .rate = _mhz * MHZ, \
- .apll_con = PLL_CLKR(nr) | PLL_CLKF(nf >> 1) | PLL_NO_##no, \
- .clksel0_con = CORE_ACLK_##_axi_div | ACLK_HCLK_##_ahb_div | ACLK_PCLK_##_apb_div, \
- .lpj = LPJ_600MHZ * _mhz / 600, \
-}
-
-static const struct arm_pll_set arm_pll[] = {
- // rate = 24 * NF / (NR * NO)
- // rate NR NF NO adiv hdiv pdiv
- ARM_PLL(1200, 1, 50, 1, 31, 21, 81),
- ARM_PLL(1176, 2, 98, 1, 31, 21, 81),
- ARM_PLL(1104, 1, 46, 1, 31, 21, 81),
- ARM_PLL(1008, 1, 42, 1, 21, 21, 81),
- ARM_PLL( 912, 1, 38, 1, 21, 21, 81),
- ARM_PLL( 888, 2, 74, 1, 21, 21, 81),
- ARM_PLL( 816, 1, 34, 1, 21, 21, 81),
- ARM_PLL( 696, 1, 58, 2, 21, 21, 81),
- ARM_PLL( 624, 1, 52, 2, 21, 21, 81),
- ARM_PLL( 600, 1, 50, 2, 21, 21, 81),
- ARM_PLL( 504, 1, 42, 2, 21, 21, 81),
- ARM_PLL( 408, 1, 34, 2, 21, 21, 81),
- ARM_PLL( 300, 1, 50, 4, 21, 21, 41),
- ARM_PLL( 204, 1, 34, 4, 21, 21, 41),
- ARM_PLL( 102, 1, 34, 8, 21, 21, 41),
- // last item, pll power down.
- ARM_PLL( 24, 1, 64, 8, 21, 21, 41),
-};
-
-#define CORE_PARENT_MASK (3 << 23)
-#define CORE_PARENT_ARM_PLL (0 << 23)
-#define CORE_PARENT_GENERAL_PLL (1 << 23)
-
-static const struct arm_pll_set* arm_pll_clk_get_best_pll_set(unsigned long rate)
-{
- const struct arm_pll_set *ps, *pt;
-
- /* find the arm_pll we want. */
- ps = pt = &arm_pll[0];
- while (1) {
- if (pt->rate == rate) {
- ps = pt;
- break;
- }
- // we are sorted, and ps->rate > pt->rate.
- if ((pt->rate > rate || (rate - pt->rate < ps->rate - rate)))
- ps = pt;
- if (pt->rate < rate || pt->rate == 24 * MHZ)
- break;
- pt++;
- }
-
- return ps;
-}
-
-static int arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
-{
- unsigned long flags;
- const struct arm_pll_set *ps;
- u32 clksel0_con;
- bool aclk_limit = rate & 1;
-
- rate &= ~1;
- ps = arm_pll_clk_get_best_pll_set(rate);
- clksel0_con = ps->clksel0_con;
-
- if (aclk_limit) {
- u32 aclk_div = clksel0_con & CORE_ACLK_MASK;
- if (rate > 408 * MHZ && aclk_div < CORE_ACLK_41)
- aclk_div = CORE_ACLK_41;
- clksel0_con = (clksel0_con & ~CORE_ACLK_MASK) | aclk_div;
- }
-
- if (ps->apll_con == cru_readl(CRU_APLL_CON)) {
- cru_writel((cru_readl(CRU_CLKSEL0_CON) & ~(CORE_ACLK_MASK | ACLK_HCLK_MASK | ACLK_PCLK_MASK)) | clksel0_con, CRU_CLKSEL0_CON);
- return 0;
- }
-
- local_irq_save(flags);
- /* make aclk safe & reparent to general pll */
- cru_writel((cru_readl(CRU_CLKSEL0_CON) & ~(CORE_PARENT_MASK | CORE_ACLK_MASK)) | CORE_PARENT_GENERAL_PLL | CORE_ACLK_21, CRU_CLKSEL0_CON);
- loops_per_jiffy = lpj_gpll;
-
- /* enter slow mode */
- cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_SLOW, CRU_MODE_CON);
-
- /* power down */
- cru_writel(cru_readl(CRU_APLL_CON) | PLL_PD, CRU_APLL_CON);
- local_irq_restore(flags);
-
- delay_500ns();
-
- cru_writel(ps->apll_con | PLL_PD, CRU_APLL_CON);
-
- delay_500ns();
-
- /* power up */
- cru_writel(ps->apll_con, CRU_APLL_CON);
-
- delay_300us();
- pll_wait_lock(ARM_PLL_IDX);
-
- local_irq_save(flags);
- /* enter normal mode */
- cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_NORMAL, CRU_MODE_CON);
-
- loops_per_jiffy = ps->lpj;
- /* reparent to arm pll & set aclk/hclk/pclk */
- cru_writel((cru_readl(CRU_CLKSEL0_CON) & ~(CORE_PARENT_MASK | CORE_ACLK_MASK | ACLK_HCLK_MASK | ACLK_PCLK_MASK)) | CORE_PARENT_ARM_PLL | clksel0_con, CRU_CLKSEL0_CON);
- local_irq_restore(flags);
-
- return 0;
-}
-
-static long arm_pll_clk_round_rate(struct clk *clk, unsigned long rate)
-{
- return arm_pll_clk_get_best_pll_set(rate)->rate;
-}
-
-static struct clk *arm_pll_parents[2] = { &xin24m, &xin27m };
-
-static struct clk arm_pll_clk = {
- .name = "arm_pll",
- .parent = &xin24m,
- .recalc = arm_pll_clk_recalc,
- .set_rate = arm_pll_clk_set_rate,
- .round_rate = arm_pll_clk_round_rate,
- .clksel_con = CRU_MODE_CON,
- .clksel_parent_mask = 1,
- .clksel_parent_shift = 8,
- .parents = arm_pll_parents,
-};
-
-static unsigned long ddr_pll_clk_recalc(struct clk *clk)
-{
- unsigned long rate;
-
- if ((cru_readl(CRU_MODE_CON) & CRU_DDR_MODE_MASK) == CRU_DDR_MODE_NORMAL) {
- u32 v = cru_readl(CRU_DPLL_CON);
- u64 rate64 = (u64) clk->parent->rate * PLL_NF(v);
- do_div(rate64, PLL_NR(v));
- rate = rate64 >> PLL_NO_SHIFT(v);
- pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
- } else {
- rate = clk->parent->rate;
- pr_debug("%s new clock rate is %ld (slow mode)\n", clk->name, rate);
- }
-
- return rate;
-}
-
-static int ddr_pll_clk_set_rate(struct clk *clk, unsigned long rate)
-{
- /* do nothing here */
- return 0;
-}
-
-static struct clk *ddr_pll_parents[4] = { &xin24m, &xin27m, &codec_pll_clk, &general_pll_clk };
-
-static struct clk ddr_pll_clk = {
- .name = "ddr_pll",
- .parent = &xin24m,
- .recalc = ddr_pll_clk_recalc,
- .set_rate = ddr_pll_clk_set_rate,
- .clksel_con = CRU_MODE_CON,
- .clksel_parent_mask = 3,
- .clksel_parent_shift = 13,
- .parents = ddr_pll_parents,
-};
-
-
-static int codec_pll_clk_mode(struct clk *clk, int on)
-{
- u32 cpll = cru_readl(CRU_CPLL_CON);
- if (on) {
- cru_writel(cpll & ~(PLL_PD | PLL_BYPASS), CRU_CPLL_CON);
- delay_300us();
- pll_wait_lock(CODEC_PLL_IDX);
- cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | CRU_CODEC_MODE_NORMAL, CRU_MODE_CON);
- } else {
- cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | CRU_CODEC_MODE_SLOW, CRU_MODE_CON);
- cru_writel(cpll | PLL_BYPASS, CRU_CPLL_CON);
- cru_writel(cpll | PLL_PD | PLL_BYPASS, CRU_CPLL_CON);
- delay_500ns();
- }
- return 0;
-}
-
-static unsigned long codec_pll_clk_recalc(struct clk *clk)
-{
- unsigned long rate;
- u32 v = cru_readl(CRU_CPLL_CON);
- u64 rate64 = (u64) clk->parent->rate * PLL_NF(v);
- do_div(rate64, PLL_NR(v));
- rate = rate64 >> PLL_NO_SHIFT(v);
- pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
- if ((cru_readl(CRU_MODE_CON) & CRU_CODEC_MODE_MASK) != CRU_CODEC_MODE_NORMAL)
- pr_debug("%s rate is %ld (slow mode) actually\n", clk->name, clk->parent->rate);
- return rate;
-}
-
-#define CODEC_PLL_PARENT_MASK (3 << 11)
-#define CODEC_PLL_PARENT_XIN24M (0 << 11)
-#define CODEC_PLL_PARENT_XIN27M (1 << 11)
-#define CODEC_PLL_PARENT_DDR_PLL (2 << 11)
-#define CODEC_PLL_PARENT_GENERAL_PLL (3 << 11)
-
-struct codec_pll_set {
- unsigned long rate;
- u32 pll_con;
- u32 parent_con;
-};
-
-#define CODEC_PLL(_khz, _parent, band, nr, nf, no) \
-{ \
- .rate = _khz * KHZ, \
- .pll_con = PLL_##band##_BAND | PLL_CLKR(nr) | PLL_CLKF(nf) | PLL_NO_##no, \
- .parent_con = CODEC_PLL_PARENT_XIN##_parent##M, \
-}
-
-static const struct codec_pll_set codec_pll[] = {
- // rate parent band NR NF NO
- CODEC_PLL(108000, 24, LOW, 1, 18, 4), // for TV
- CODEC_PLL(648000, 24, HIGH, 1, 27, 1),
- CODEC_PLL(148500, 27, LOW, 2, 88, 8), //change for jetta hdmi dclk jitter 20120322// for HDMI
- CODEC_PLL(297000, 27, LOW, 2, 88, 4), //change for jetta hdmi dclk jitter 20120322// for HDMI
- CODEC_PLL(445500, 27, LOW, 2, 33, 1),
- CODEC_PLL(594000, 27, HIGH, 1, 22, 1),
- CODEC_PLL(891000, 27, HIGH, 1, 33, 1),
- CODEC_PLL(300000, 24, LOW, 1, 25, 2), // for GPU
- CODEC_PLL(360000, 24, LOW, 1, 15, 1),
- CODEC_PLL(408000, 24, LOW, 1, 17, 1),
- CODEC_PLL(456000, 24, LOW, 1, 19, 1),
- CODEC_PLL(504000, 24, LOW, 1, 21, 1),
- CODEC_PLL(552000, 24, LOW, 1, 23, 1),
- CODEC_PLL(600000, 24, HIGH, 1, 25, 1),
-};
-
-static int codec_pll_clk_set_rate(struct clk *clk, unsigned long rate)
-{
- int i;
- u32 work_mode;
-
- const struct codec_pll_set *ps = NULL;
-
- for (i = 0; i < ARRAY_SIZE(codec_pll); i++) {
- if (codec_pll[i].rate == rate) {
- ps = &codec_pll[i];
- break;
- }
- }
- if (!ps)
- return -ENOENT;
-
- if (!has_xin27m && ps->parent_con == CODEC_PLL_PARENT_XIN27M)
- return -ENOENT;
-
- work_mode = cru_readl(CRU_MODE_CON) & CRU_CODEC_MODE_MASK;
-
- /* enter slow mode */
- cru_writel((cru_readl(CRU_MODE_CON) & ~(CRU_CODEC_MODE_MASK | CODEC_PLL_PARENT_MASK)) | CRU_CODEC_MODE_SLOW | ps->parent_con, CRU_MODE_CON);
-
- /* power down */
- cru_writel(cru_readl(CRU_CPLL_CON) | PLL_PD, CRU_CPLL_CON);
-
- delay_500ns();
-
- cru_writel(ps->pll_con | PLL_PD, CRU_CPLL_CON);
-
- delay_500ns();
-
- /* power up */
- cru_writel(ps->pll_con, CRU_CPLL_CON);
-
- delay_300us();
- pll_wait_lock(CODEC_PLL_IDX);
-
- /* enter normal mode */
- cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | work_mode, CRU_MODE_CON);
-
- clk_set_parent_nolock(clk, ps->parent_con == CODEC_PLL_PARENT_XIN24M ? &xin24m : &xin27m);
-
- return 0;
-}
-
-static struct clk *codec_pll_parents[4] = { &xin24m, &xin27m, &ddr_pll_clk, &general_pll_clk };
-
-static struct clk codec_pll_clk = {
- .name = "codec_pll",
- .parent = &xin24m,
- .mode = codec_pll_clk_mode,
- .recalc = codec_pll_clk_recalc,
- .set_rate = codec_pll_clk_set_rate,
- .clksel_con = CRU_MODE_CON,
- .clksel_parent_mask = 3,
- .clksel_parent_shift = 11,
- .parents = codec_pll_parents,
-};
-
-
-static unsigned long general_pll_clk_recalc(struct clk *clk)
-{
- unsigned long rate;
-
- if ((cru_readl(CRU_MODE_CON) & CRU_GENERAL_MODE_MASK) == CRU_GENERAL_MODE_NORMAL) {
- u32 v = cru_readl(CRU_GPLL_CON);
- u64 rate64 = (u64) clk->parent->rate * PLL_NF(v);
- do_div(rate64, PLL_NR(v));
- rate = rate64 >> PLL_NO_SHIFT(v);
- pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
- } else {
- rate = clk->parent->rate;
- pr_debug("%s new clock rate is %ld (slow mode)\n", clk->name, rate);
- }
-
- return rate;
-}
-
-static int general_pll_clk_set_rate(struct clk *clk, unsigned long rate)
-{
- u32 pll_con;
-
- switch (rate) {
- case 96 * MHZ:
- /* 96M: low-band, NR=1, NF=16, NO=4 */
- pll_con = PLL_LOW_BAND | PLL_CLKR(1) | PLL_CLKF(16) | PLL_NO_4;
- break;
- case 144*MHZ:
- /* 96M: low-band, NR=1, NF=16, NO=4 */
- pll_con = PLL_LOW_BAND | PLL_CLKR(1) | PLL_CLKF(24) | PLL_NO_4;
- break;
- case 288 * MHZ:
- /* 288M: low-band, NR=1, NF=24, NO=2 */
- pll_con = PLL_LOW_BAND | PLL_CLKR(1) | PLL_CLKF(24) | PLL_NO_2;
- break;
- case 300 * MHZ:
- /* 300M: low-band, NR=1, NF=25, NO=2 */
- pll_con = PLL_LOW_BAND | PLL_CLKR(1) | PLL_CLKF(25) | PLL_NO_2;
- break;
- case 624 * MHZ:
- /* 624M: high-band, NR=1, NF=26, NO=1 */
- pll_con = PLL_HIGH_BAND | PLL_CLKR(1) | PLL_CLKF(26) | PLL_NO_1;
- break;
- default:
- return -ENOENT;
- break;
- }
-
- /* enter slow mode */
- cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_GENERAL_MODE_MASK) | CRU_GENERAL_MODE_SLOW, CRU_MODE_CON);
-
- /* power down */
- cru_writel(cru_readl(CRU_GPLL_CON) | PLL_PD, CRU_GPLL_CON);
-
- delay_500ns();
-
- cru_writel(pll_con | PLL_PD, CRU_GPLL_CON);
-
- delay_500ns();
-
- /* power up */
- cru_writel(pll_con, CRU_GPLL_CON);
-
- delay_300us();
- pll_wait_lock(GENERAL_PLL_IDX);
-
- /* enter normal mode */
- cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_GENERAL_MODE_MASK) | CRU_GENERAL_MODE_NORMAL, CRU_MODE_CON);
-
- return 0;
-}
-
-static struct clk *general_pll_parents[4] = { &xin24m, &xin27m, &ddr_pll_clk, &codec_pll_clk };
-
-static struct clk general_pll_clk = {
- .name = "general_pll",
- .parent = &xin24m,
- .recalc = general_pll_clk_recalc,
- .set_rate = general_pll_clk_set_rate,
- .clksel_con = CRU_MODE_CON,
- .clksel_parent_mask = 3,
- .clksel_parent_shift = 9,
- .parents = general_pll_parents,
-};
-
-
-static struct clk *clk_core_parents[4] = { &arm_pll_clk, &general_pll_clk, &codec_pll_clk, &ddr_pll_clk };
-
-static struct clk clk_core = {
- .name = "core",
- .parent = &arm_pll_clk,
- .recalc = clksel_recalc_div,
- .clksel_con = CRU_CLKSEL0_CON,
- .clksel_mask = 0x1F,
- .clksel_shift = 0,
- .clksel_parent_mask = 3,
- .clksel_parent_shift = 23,
- .parents = clk_core_parents,
-};
-
-static unsigned long aclk_cpu_recalc(struct clk *clk)
-{
- unsigned long rate;
- u32 div = ((cru_readl(CRU_CLKSEL0_CON) >> 5) & 0x7) + 1;
-
- BUG_ON(div > 5);
- if (div >= 5)
- div = 8;
- rate = clk->parent->rate / div;
- pr_debug("%s new clock rate is %ld (div %d)\n", clk->name, rate, div);
-
- return rate;
-}
-
-static struct clk aclk_cpu = {
- .name = "aclk_cpu",
- .parent = &clk_core,
- .recalc = aclk_cpu_recalc,
-};
-
-static struct clk hclk_cpu = {
- .name = "hclk_cpu",
- .parent = &aclk_cpu,
- .recalc = clksel_recalc_shift,
- .set_rate = clksel_set_rate_shift,
- .clksel_con = CRU_CLKSEL0_CON,
- .clksel_mask = 3,
- .clksel_shift = 8,
- .clksel_maxdiv = 4,
-};
-
-static struct clk pclk_cpu = {
- .name = "pclk_cpu",
- .parent = &aclk_cpu,
- .recalc = clksel_recalc_shift,
- .set_rate = clksel_set_rate_shift,
- .clksel_con = CRU_CLKSEL0_CON,
- .clksel_mask = 3,
- .clksel_shift = 10,
- .clksel_maxdiv = 8,
-};
-
-static struct clk *aclk_periph_parents[4] = { &general_pll_clk, &arm_pll_clk, &ddr_pll_clk, &codec_pll_clk };
-
-static struct clk aclk_periph = {
- .name = "aclk_periph",
- .mode = gate_mode,
- .gate_idx = CLK_GATE_ACLK_PEIRPH,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_div,
- .clksel_con = CRU_CLKSEL0_CON,
- .clksel_mask = 0x1F,
- .clksel_shift = 14,
- .clksel_parent_mask = 3,
- .clksel_parent_shift = 12,
- .parents = aclk_periph_parents,
-};
-
-static struct clk pclk_periph = {
- .name = "pclk_periph",
- .mode = gate_mode,
- .gate_idx = CLK_GATE_PCLK_PEIRPH,
- .parent = &aclk_periph,
- .recalc = clksel_recalc_shift,
- .set_rate = clksel_set_rate_shift,
- .clksel_con = CRU_CLKSEL0_CON,
- .clksel_mask = 3,
- .clksel_shift = 19,
- .clksel_maxdiv = 8,
-};
-
-static struct clk hclk_periph = {
- .name = "hclk_periph",
- .mode = gate_mode,
- .gate_idx = CLK_GATE_HCLK_PEIRPH,
- .parent = &aclk_periph,
- .recalc = clksel_recalc_shift,
- .set_rate = clksel_set_rate_shift,
- .clksel_con = CRU_CLKSEL0_CON,
- .clksel_mask = 3,
- .clksel_shift = 21,
- .clksel_maxdiv = 4,
-};
-
-
-static unsigned long uhost_recalc(struct clk *clk)
-{
- unsigned long rate = clksel_recalc_div(clk);
- if (rate != 48 * MHZ) {
- clksel_set_rate_div(clk, 48 * MHZ);
- rate = clksel_recalc_div(clk);
- }
- return rate;
-}
-
-static struct clk *clk_uhost_parents[8] = { &general_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
-
-static struct clk clk_uhost = {
- .name = "uhost",
- .mode = gate_mode,
- .recalc = uhost_recalc,
- .set_rate = clksel_set_rate_div,
- .gate_idx = CLK_GATE_UHOST,
- .clksel_con = CRU_CLKSEL1_CON,
- .clksel_mask = 0x1F,
- .clksel_shift = 16,
- .clksel_parent_mask = 7,
- .clksel_parent_shift = 13,
- .parents = clk_uhost_parents,
-};
-
-static struct clk *clk_otgphy_parents[4] = { &xin24m, &clk_12m, &clk_uhost };
-
-static struct clk clk_otgphy0 = {
- .name = "otgphy0",
- .mode = gate_mode,
- .gate_idx = CLK_GATE_USBPHY0,
- .clksel_con = CRU_CLKSEL1_CON,
- .clksel_parent_mask = 3,
- .clksel_parent_shift = 9,
- .parents = clk_otgphy_parents,
-};
-
-static struct clk clk_otgphy1 = {
- .name = "otgphy1",
- .mode = gate_mode,
- .gate_idx = CLK_GATE_USBPHY1,
- .clksel_con = CRU_CLKSEL1_CON,
- .clksel_parent_mask = 3,
- .clksel_parent_shift = 11,
- .parents = clk_otgphy_parents,
-};
-
-
-static struct clk rmii_clkin = {
- .name = "rmii_clkin",
-};
-
-static struct clk *clk_mac_ref_div_parents[4] = { &arm_pll_clk, &general_pll_clk, &codec_pll_clk, &ddr_pll_clk };
-
-static struct clk clk_mac_ref_div = {
- .name = "mac_ref_div",
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_div,
- .clksel_con = CRU_CLKSEL1_CON,
- .clksel_mask = 0x1F,
- .clksel_shift = 23,
- .clksel_parent_mask = 3,
- .clksel_parent_shift = 21,
- .parents = clk_mac_ref_div_parents,
-};
-
-static struct clk *clk_mac_ref_parents[2] = { &clk_mac_ref_div, &rmii_clkin };
-
-static struct clk clk_mac_ref = {
- .name = "mac_ref",
- .mode = gate_mode,
- .gate_idx = CLK_GATE_MAC_REF,
- .clksel_con = CRU_CLKSEL1_CON,
- .clksel_parent_mask = 1,
- .clksel_parent_shift = 28,
- .parents = clk_mac_ref_parents,
-};
-
-
-static struct clk *clk_i2s_div_parents[8] = { &codec_pll_clk, &general_pll_clk, &arm_pll_clk, &ddr_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
-
-static struct clk clk_i2s0_div = {
- .name = "i2s0_div",
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_div,
- .clksel_con = CRU_CLKSEL2_CON,
- .clksel_mask = 0x1F,
- .clksel_shift = 3,
- .clksel_parent_mask = 7,
- .clksel_parent_shift = 0,
- .parents = clk_i2s_div_parents,
-};
-
-static struct clk clk_i2s1_div = {
- .name = "i2s1_div",
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_div,
- .clksel_con = CRU_CLKSEL2_CON,
- .clksel_mask = 0x1F,
- .clksel_shift = 13,
- .clksel_parent_mask = 7,
- .clksel_parent_shift = 10,
- .parents = clk_i2s_div_parents,
-};
-
-static struct clk clk_spdif_div = {
- .name = "spdif_div",
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_div,
- .clksel_con = CRU_CLKSEL2_CON,
- .clksel_mask = 0x1F,
- .clksel_shift = 23,
- .clksel_parent_mask = 7,
- .clksel_parent_shift = 20,
- .parents = clk_i2s_div_parents,
-};
-
-static u32 clk_gcd(u32 numerator, u32 denominator)
-{
- u32 a, b;
-
- if (!numerator || !denominator)
- return 0;
- if (numerator > denominator) {
- a = numerator;
- b = denominator;
- } else {
- a = denominator;
- b = numerator;
- }
- while (b != 0) {
- int r = b;
- b = a % b;
- a = r;
- }
-
- return a;
-}
-
-static int clk_i2s_frac_div_set_rate(struct clk *clk, unsigned long rate)
-{
- u32 numerator, denominator;
- u32 gcd;
-
- gcd = clk_gcd(rate, clk->parent->rate);
- pr_debug("i2s rate=%ld,parent=%ld,gcd=%d\n", rate, clk->parent->rate, gcd);
- if (!gcd) {
- pr_err("gcd=0, i2s frac div is not be supported\n");
- return -ENOENT;
- }
-
- numerator = rate / gcd;
- denominator = clk->parent->rate / gcd;
- pr_debug("i2s numerator=%d,denominator=%d,times=%d\n",
- numerator, denominator, denominator / numerator);
- if (numerator > 0xffff || denominator > 0xffff) {
- pr_err("i2s can't get a available nume and deno\n");
- return -ENOENT;
- }
-
- pr_debug("set clock %s to rate %ld (%d/%d)\n", clk->name, rate, numerator, denominator);
- cru_writel(numerator << 16 | denominator, clk->clksel_con);
-
- return 0;
-}
-
-static struct clk clk_i2s0_frac_div = {
- .name = "i2s0_frac_div",
- .parent = &clk_i2s0_div,
- .recalc = clksel_recalc_frac,
- .set_rate = clk_i2s_frac_div_set_rate,
- .clksel_con = CRU_CLKSEL3_CON,
-};
-
-static struct clk clk_i2s1_frac_div = {
- .name = "i2s1_frac_div",
- .parent = &clk_i2s1_div,
- .recalc = clksel_recalc_frac,
- .set_rate = clk_i2s_frac_div_set_rate,
- .clksel_con = CRU_CLKSEL4_CON,
-};
-
-static struct clk clk_spdif_frac_div = {
- .name = "spdif_frac_div",
- .parent = &clk_spdif_div,
- .recalc = clksel_recalc_frac,
- .set_rate = clk_i2s_frac_div_set_rate,
- .clksel_con = CRU_CLKSEL5_CON,
-};
-
-static int i2s_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret = 0;
- struct clk *parent;
-
- if (rate == 12 * MHZ) {
- parent = &clk_12m;
- } else {
- parent = clk->parents[1]; /* frac div */
- ret = clk_set_rate_nolock(parent, rate);
- if (ret)
- return ret;
- }
- if (clk->parent != parent)
- ret = clk_set_parent_nolock(clk, parent);
-
- return ret;
-}
-
-static struct clk *clk_i2s0_parents[4] = { &clk_i2s0_div, &clk_i2s0_frac_div, &clk_12m, &xin24m };
-
-static struct clk clk_i2s0 = {
- .name = "i2s0",
- .mode = gate_mode,
- .gate_idx = CLK_GATE_I2S0,
- .set_rate = i2s_set_rate,
- .clksel_con = CRU_CLKSEL2_CON,
- .clksel_parent_mask = 3,
- .clksel_parent_shift = 8,
- .parents = clk_i2s0_parents,
-};
-
-static struct clk *clk_i2s1_parents[4] = { &clk_i2s1_div, &clk_i2s1_frac_div, &clk_12m, &xin24m };
-
-static struct clk clk_i2s1 = {
- .name = "i2s1",
- .mode = gate_mode,
- .gate_idx = CLK_GATE_I2S1,
- .set_rate = i2s_set_rate,
- .clksel_con = CRU_CLKSEL2_CON,
- .clksel_parent_mask = 3,
- .clksel_parent_shift = 18,
- .parents = clk_i2s1_parents,
-};
-
-static struct clk *clk_spdif_parents[4] = { &clk_spdif_div, &clk_spdif_frac_div, &clk_12m, &xin24m };
-
-static struct clk clk_spdif = {
- .name = "spdif",
- .mode = gate_mode,
- .gate_idx = CLK_GATE_SPDIF,
- .set_rate = i2s_set_rate,
- .clksel_con = CRU_CLKSEL2_CON,
- .clksel_parent_mask = 3,
- .clksel_parent_shift = 28,
- .parents = clk_spdif_parents,
-};
-
-
-static struct clk *clk_spi_src_parents[4] = { &general_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk };
-
-static struct clk clk_spi_src = {
- .name = "spi_src",
- .clksel_con = CRU_CLKSEL6_CON,
- .clksel_parent_mask = 3,
- .clksel_parent_shift = 0,
- .parents = clk_spi_src_parents,
-};
-
-static struct clk clk_spi0 = {
- .name = "spi0",
- .parent = &clk_spi_src,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_div,
- .gate_idx = CLK_GATE_SPI0,
- .clksel_con = CRU_CLKSEL6_CON,
- .clksel_mask = 0x7F,
- .clksel_shift = 2,
-};
-
-static struct clk clk_spi1 = {
- .name = "spi1",
- .parent = &clk_spi_src,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_div,
- .gate_idx = CLK_GATE_SPI1,
- .clksel_con = CRU_CLKSEL6_CON,
- .clksel_mask = 0x7F,
- .clksel_shift = 11,
-};
-
-
-static struct clk clk_saradc = {
- .name = "saradc",
- .parent = &pclk_periph,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_div,
- .gate_idx = CLK_GATE_SARADC,
- .clksel_con = CRU_CLKSEL6_CON,
- .clksel_mask = 0xFF,
- .clksel_shift = 18,
-};
-
-
-static struct clk *clk_cpu_timer_parents[2] = { &pclk_cpu, &xin24m };
-
-static struct clk clk_timer0 = {
- .name = "timer0",
- .mode = gate_mode,
- .gate_idx = CLK_GATE_TIMER0,
- .clksel_con = CRU_CLKSEL6_CON,
- .clksel_parent_mask = 1,
- .clksel_parent_shift = 26,
- .parents = clk_cpu_timer_parents,
-};
-
-static struct clk clk_timer1 = {
- .name = "timer1",
- .mode = gate_mode,
- .gate_idx = CLK_GATE_TIMER1,
- .clksel_con = CRU_CLKSEL6_CON,
- .clksel_parent_mask = 1,
- .clksel_parent_shift = 27,
- .parents = clk_cpu_timer_parents,
-};
-
-static struct clk *clk_periph_timer_parents[2] = { &pclk_periph, &xin24m };
-
-static struct clk clk_timer2 = {
- .name = "timer2",
- .mode = gate_mode,
- .gate_idx = CLK_GATE_TIMER2,
- .clksel_con = CRU_CLKSEL6_CON,
- .clksel_parent_mask = 1,
- .clksel_parent_shift = 28,
- .parents = clk_periph_timer_parents,
-};
-
-static struct clk clk_timer3 = {
- .name = "timer3",
- .mode = gate_mode,
- .gate_idx = CLK_GATE_TIMER3,
- .clksel_con = CRU_CLKSEL6_CON,
- .clksel_parent_mask = 1,
- .clksel_parent_shift = 29,
- .parents = clk_periph_timer_parents,
-};
-
-
-static struct clk *clk_mmc_src_parents[4] = { &arm_pll_clk, &general_pll_clk, &codec_pll_clk, &ddr_pll_clk };
-
-static struct clk clk_mmc_src = {
- .name = "mmc_src",
- .clksel_con = CRU_CLKSEL7_CON,
- .clksel_parent_mask = 3,
- .clksel_parent_shift = 0,
- .parents = clk_mmc_src_parents,
-};
-
-static struct clk clk_mmc0 = {
- .name = "mmc0",
- .parent = &clk_mmc_src,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_div,
- .gate_idx = CLK_GATE_MMC0,
- .clksel_con = CRU_CLKSEL7_CON,
- .clksel_mask = 0x3F,
- .clksel_shift = 2,
-};
-
-static struct clk clk_mmc1 = {
- .name = "mmc1",
- .parent = &clk_mmc_src,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_div,
- .gate_idx = CLK_GATE_MMC1,
- .clksel_con = CRU_CLKSEL7_CON,
- .clksel_mask = 0x3F,
- .clksel_shift = 10,
-};
-
-static struct clk clk_emmc = {
- .name = "emmc",
- .parent = &clk_mmc_src,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_div,
- .gate_idx = CLK_GATE_EMMC,
- .clksel_con = CRU_CLKSEL7_CON,
- .clksel_mask = 0x3F,
- .clksel_shift = 18,
-};
-
-
-static struct clk *clk_ddr_parents[8] = { &ddr_pll_clk, &general_pll_clk, &codec_pll_clk, &arm_pll_clk };
-
-static struct clk clk_ddr = {
- .name = "ddr",
- .recalc = clksel_recalc_shift,
- .clksel_con = CRU_CLKSEL7_CON,
- .clksel_mask = 7,
- .clksel_shift = 26,
- .clksel_maxdiv = 32,
- .clksel_parent_mask = 3,
- .clksel_parent_shift = 24,
- .parents = clk_ddr_parents,
-};
-
-
-static int clk_uart_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret = 0;
- struct clk *parent;
- struct clk *clk_div = clk->parents[0];
-
- switch (rate) {
- case 24*MHZ: /* 1.5M/0.5M/50/75/150/200/300/600/1200/2400 */
- parent = clk->parents[2]; /* xin24m */
- break;
- case 19200*16:
- case 38400*16:
- case 57600*16:
- case 115200*16:
- case 230400*16:
- case 460800*16:
- case 576000*16:
- parent = clk->parents[1]; /* frac div */
- /* reset div to 1 */
- ret = clk_set_rate_nolock(clk_div, clk_div->parent->rate);
- if (ret)
- return ret;
- break;
- default:
- parent = clk_div;
- break;
- }
-
- if (parent->set_rate) {
- ret = clk_set_rate_nolock(parent, rate);
- if (ret)
- return ret;
- }
-
- if (clk->parent != parent)
- ret = clk_set_parent_nolock(clk, parent);
-
- return ret;
-}
-
-static int clk_uart_frac_div_set_rate(struct clk *clk, unsigned long rate)
-{
- u32 numerator, denominator;
- u32 gcd;
-
- gcd = clk_gcd(rate, clk->parent->rate);
- pr_debug("uart rate=%ld,parent=%ld,gcd=%d\n", rate, clk->parent->rate, gcd);
- if (!gcd) {
- pr_err("gcd=0, uart frac div is not be supported\n");
- return -ENOENT;
- }
-
- numerator = rate / gcd;
- denominator = clk->parent->rate / gcd;
- pr_debug("uart numerator=%d,denominator=%d,times=%d\n",
- numerator, denominator, denominator / numerator);
- if (numerator > 0xffff || denominator > 0xffff) {
- pr_err("uart_frac can't get a available nume and deno\n");
- return -ENOENT;
- }
-
- pr_debug("set clock %s to rate %ld (%d/%d)\n", clk->name, rate, numerator, denominator);
- cru_writel(numerator << 16 | denominator, clk->clksel_con);
-
- return 0;
-}
-
-static struct clk *clk_uart_src_parents[8] = { &general_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
-
-static struct clk clk_uart01_src = {
- .name = "uart01_src",
- .clksel_con = CRU_CLKSEL8_CON,
- .clksel_parent_mask = 7,
- .clksel_parent_shift = 0,
- .parents = clk_uart_src_parents,
-};
-
-static struct clk clk_uart0_div = {
- .name = "uart0_div",
- .parent = &clk_uart01_src,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_div,
- .clksel_con = CRU_CLKSEL8_CON,
- .clksel_mask = 0x3F,
- .clksel_shift = 3,
-};
-
-static struct clk clk_uart0_frac_div = {
- .name = "uart0_frac_div",
- .parent = &clk_uart0_div,
- .recalc = clksel_recalc_frac,
- .set_rate = clk_uart_frac_div_set_rate,
- .clksel_con = CRU_CLKSEL10_CON,
-};
-
-static struct clk *clk_uart0_parents[4] = { &clk_uart0_div, &clk_uart0_frac_div, &xin24m };
-
-static struct clk clk_uart0 = {
- .name = "uart0",
- .mode = gate_mode,
- .set_rate = clk_uart_set_rate,
- .gate_idx = CLK_GATE_UART0,
- .clksel_con = CRU_CLKSEL8_CON,
- .clksel_parent_mask = 3,
- .clksel_parent_shift = 9,
- .parents = clk_uart0_parents,
-};
-
-static struct clk clk_uart1_div = {
- .name = "uart1_div",
- .parent = &clk_uart01_src,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_div,
- .clksel_con = CRU_CLKSEL8_CON,
- .clksel_mask = 0x3F,
- .clksel_shift = 14,
-};
-
-static struct clk clk_uart1_frac_div = {
- .name = "uart1_frac_div",
- .parent = &clk_uart1_div,
- .recalc = clksel_recalc_frac,
- .set_rate = clk_uart_frac_div_set_rate,
- .clksel_con = CRU_CLKSEL11_CON,
-};
-
-static struct clk *clk_uart1_parents[4] = { &clk_uart1_div, &clk_uart1_frac_div, &xin24m };
-
-static struct clk clk_uart1 = {
- .name = "uart1",
- .mode = gate_mode,
- .set_rate = clk_uart_set_rate,
- .gate_idx = CLK_GATE_UART1,
- .clksel_con = CRU_CLKSEL8_CON,
- .clksel_parent_mask = 3,
- .clksel_parent_shift = 20,
- .parents = clk_uart1_parents,
-};
-
-static struct clk clk_uart23_src = {
- .name = "uart23_src",
- .clksel_con = CRU_CLKSEL9_CON,
- .clksel_parent_mask = 7,
- .clksel_parent_shift = 0,
- .parents = clk_uart_src_parents,
-};
-
-static struct clk clk_uart2_div = {
- .name = "uart2_div",
- .parent = &clk_uart23_src,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_div,
- .clksel_con = CRU_CLKSEL9_CON,
- .clksel_mask = 0x3F,
- .clksel_shift = 3,
-};
-
-static struct clk clk_uart2_frac_div = {
- .name = "uart2_frac_div",
- .parent = &clk_uart2_div,
- .recalc = clksel_recalc_frac,
- .set_rate = clk_uart_frac_div_set_rate,
- .clksel_con = CRU_CLKSEL12_CON,
-};
-
-static struct clk *clk_uart2_parents[4] = { &clk_uart2_div, &clk_uart2_frac_div, &xin24m };
-
-static struct clk clk_uart2 = {
- .name = "uart2",
- .mode = gate_mode,
- .set_rate = clk_uart_set_rate,
- .gate_idx = CLK_GATE_UART2,
- .clksel_con = CRU_CLKSEL9_CON,
- .clksel_parent_mask = 3,
- .clksel_parent_shift = 9,
- .parents = clk_uart2_parents,
-};
-
-static struct clk clk_uart3_div = {
- .name = "uart3_div",
- .parent = &clk_uart23_src,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_div,
- .clksel_con = CRU_CLKSEL9_CON,
- .clksel_mask = 0x3F,
- .clksel_shift = 14,
-};
-
-static struct clk clk_uart3_frac_div = {
- .name = "uart3_frac_div",
- .parent = &clk_uart3_div,
- .recalc = clksel_recalc_frac,
- .set_rate = clk_uart_frac_div_set_rate,
- .clksel_con = CRU_CLKSEL13_CON,
-};
-
-static struct clk *clk_uart3_parents[4] = { &clk_uart3_div, &clk_uart3_frac_div, &xin24m };
-
-static struct clk clk_uart3 = {
- .name = "uart3",
- .mode = gate_mode,
- .set_rate = clk_uart_set_rate,
- .gate_idx = CLK_GATE_UART3,
- .clksel_con = CRU_CLKSEL9_CON,
- .clksel_parent_mask = 3,
- .clksel_parent_shift = 20,
- .parents = clk_uart3_parents,
-};
-
-
-static struct clk *clk_hsadc_div_parents[8] = { &codec_pll_clk, &ddr_pll_clk, &general_pll_clk, &arm_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
-
-static struct clk clk_hsadc_div = {
- .name = "hsadc_div",
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_div,
- .clksel_con = CRU_CLKSEL14_CON,
- .clksel_mask = 0xFF,
- .clksel_shift = 10,
- .clksel_parent_mask = 7,
- .clksel_parent_shift = 7,
- .parents = clk_hsadc_div_parents,
-};
-
-static struct clk clk_hsadc_frac_div = {
- .name = "hsadc_frac_div",
- .parent = &clk_hsadc_div,
- .recalc = clksel_recalc_frac,
- .clksel_con = CRU_CLKSEL15_CON,
-};
-
-static struct clk *clk_demod_parents[4] = { &clk_hsadc_div, &clk_hsadc_frac_div, &xin27m };
-
-static struct clk clk_demod = {
- .name = "demod",
- .clksel_con = CRU_CLKSEL14_CON,
- .clksel_parent_mask = 3,
- .clksel_parent_shift = 18,
- .parents = clk_demod_parents,
-};
-
-static struct clk gpsclk = {
- .name = "gpsclk",
-};
-
-static struct clk *clk_hsadc_parents[2] = { &clk_demod, &gpsclk };
-
-static struct clk clk_hsadc = {
- .name = "hsadc",
- .mode = gate_mode,
- .gate_idx = CLK_GATE_HSADC,
- .clksel_con = CRU_CLKSEL14_CON,
- .clksel_parent_mask = 1,
- .clksel_parent_shift = 21,
- .parents = clk_hsadc_parents,
-};
-
-static unsigned long div2_recalc(struct clk *clk)
-{
- return clk->parent->rate >> 1;
-}
-
-static struct clk clk_hsadc_div2 = {
- .name = "hsadc_div2",
- .parent = &clk_demod,
- .recalc = div2_recalc,
-};
-
-static struct clk clk_hsadc_div2_inv = {
- .name = "hsadc_div2_inv",
- .parent = &clk_demod,
- .recalc = div2_recalc,
-};
-
-static struct clk *clk_hsadc_out_parents[2] = { &clk_hsadc_div2, &clk_hsadc_div2_inv };
-
-static struct clk clk_hsadc_out = {
- .name = "hsadc_out",
- .clksel_con = CRU_CLKSEL14_CON,
- .clksel_parent_mask = 1,
- .clksel_parent_shift = 20,
- .parents = clk_hsadc_out_parents,
-};
-
-
-static int dclk_lcdc_div_set_rate(struct clk *clk, unsigned long rate)
-{
- struct clk *parent;
-
- switch (rate) {
- case 27000 * KHZ:
- case 74250 * KHZ:
- case 148500 * KHZ:
- case 297 * MHZ:
- case 594 * MHZ:
- parent = &codec_pll_clk;
- break;
- default:
- parent = &general_pll_clk;
- break;
- }
- if (clk->parent != parent)
- clk_set_parent_nolock(clk, parent);
-
- return clksel_set_rate_div(clk, rate);
-}
-
-static struct clk *dclk_lcdc_div_parents[4] = { &codec_pll_clk, &ddr_pll_clk, &general_pll_clk, &arm_pll_clk };
-
-static struct clk dclk_lcdc_div = {
- .name = "dclk_lcdc_div",
- .recalc = clksel_recalc_div,
- .set_rate = dclk_lcdc_div_set_rate,
- .clksel_con = CRU_CLKSEL16_CON,
- .clksel_mask = 0xFF,
- .clksel_shift = 2,
- .clksel_parent_mask = 3,
- .clksel_parent_shift = 0,
- .parents = dclk_lcdc_div_parents,
-};
-
-static int dclk_lcdc_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret = 0;
- struct clk *parent;
-
- if (rate == 27 * MHZ && has_xin27m) {
- parent = &xin27m;
- } else {
- parent = &dclk_lcdc_div;
- ret = clk_set_rate_nolock(parent, rate);
- if (ret)
- return ret;
- }
- if (clk->parent != parent)
- ret = clk_set_parent_nolock(clk, parent);
-
- return ret;
-}
-
-static struct clk *dclk_lcdc_parents[2] = { &dclk_lcdc_div, &xin27m };
-
-static struct clk dclk_lcdc = {
- .name = "dclk_lcdc",
- .mode = gate_mode,
- .set_rate = dclk_lcdc_set_rate,
- .gate_idx = CLK_GATE_DCLK_LCDC,
- .clksel_con = CRU_CLKSEL16_CON,
- .clksel_parent_mask = 1,
- .clksel_parent_shift = 10,
- .parents = dclk_lcdc_parents,
-};
-
-static struct clk dclk_ebook = {
- .name = "dclk_ebook",
- .mode = gate_mode,
- .gate_idx = CLK_GATE_DCLK_EBOOK,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_div,
- .clksel_con = CRU_CLKSEL16_CON,
- .clksel_mask = 0x1F,
- .clksel_shift = 13,
- .clksel_parent_mask = 3,
- .clksel_parent_shift = 11,
- .parents = dclk_lcdc_div_parents,
-};
-
-static struct clk *aclk_lcdc_parents[4] = { &ddr_pll_clk, &codec_pll_clk, &general_pll_clk, &arm_pll_clk };
-
-static struct clk aclk_lcdc = {
- .name = "aclk_lcdc",
- .mode = gate_mode,
- .gate_idx = CLK_GATE_ACLK_LCDC,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_div,
- .clksel_con = CRU_CLKSEL16_CON,
- .clksel_mask = 0x1F,
- .clksel_shift = 20,
- .clksel_parent_mask = 3,
- .clksel_parent_shift = 18,
- .parents = aclk_lcdc_parents,
-};
-
-static struct clk hclk_lcdc = {
- .name = "hclk_lcdc",
- .mode = gate_mode,
- .gate_idx = CLK_GATE_HCLK_LCDC,
- .parent = &aclk_lcdc,
- .clksel_con = CRU_CLKSEL16_CON,
- .recalc = clksel_recalc_shift,
- .set_rate = clksel_set_rate_shift,
- .clksel_mask = 3,
- .clksel_shift = 25,
- .clksel_maxdiv = 4,
-};
-
-/* for vpu power on notify */
-static struct clk clk_vpu = {
- .name = "vpu",
-};
-
-static struct clk *xpu_parents[4] = { &general_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk };
-
-static struct clk aclk_vepu = {
- .name = "aclk_vepu",
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_div,
- .gate_idx = CLK_GATE_ACLK_VEPU,
- .clksel_con = CRU_CLKSEL17_CON,
- .clksel_mask = 0x1F,
- .clksel_shift = 2,
- .clksel_parent_mask = 3,
- .clksel_parent_shift = 0,
- .parents = xpu_parents,
-};
-
-static struct clk hclk_vepu = {
- .name = "hclk_vepu",
- .parent = &aclk_vepu,
- .mode = gate_mode,
- .recalc = clksel_recalc_shift,
- .set_rate = clksel_set_rate_shift,
- .gate_idx = CLK_GATE_HCLK_VEPU,
- .clksel_con = CRU_CLKSEL17_CON,
- .clksel_mask = 3,
- .clksel_shift = 28,
- .clksel_maxdiv = 4,
-};
-
-static struct clk aclk_vdpu = {
- .name = "aclk_vdpu",
- .parent = &general_pll_clk,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_div,
- .gate_idx = CLK_GATE_ACLK_VDPU,
- .clksel_con = CRU_CLKSEL17_CON,
- .clksel_mask = 0x1F,
- .clksel_shift = 9,
- .clksel_parent_mask = 3,
- .clksel_parent_shift = 7,
- .parents = xpu_parents,
-};
-
-static struct clk hclk_vdpu = {
- .name = "hclk_vdpu",
- .parent = &aclk_vdpu,
- .mode = gate_mode,
- .recalc = clksel_recalc_shift,
- .set_rate = clksel_set_rate_shift,
- .gate_idx = CLK_GATE_HCLK_VDPU,
- .clksel_con = CRU_CLKSEL17_CON,
- .clksel_mask = 3,
- .clksel_shift = 30,
- .clksel_maxdiv = 4,
-};
-
-static int clk_gpu_set_rate(struct clk *clk, unsigned long rate)
-{
- unsigned long max_rate = rate / 100 * 105; /* +5% */
- struct clk *parents[] = { &general_pll_clk, &codec_pll_clk, &ddr_pll_clk };
- int i;
- unsigned long best_rate = 0;
- struct clk *best_parent = clk->parent;
-
- for (i = 0; i < ARRAY_SIZE(parents); i++) {
- unsigned long new_rate = clksel_round_rate_div_by_parent(clk, rate, parents[i], max_rate);
- if (new_rate == rate) {
- best_rate = new_rate;
- best_parent = parents[i];
- break;
- }
- if (new_rate > max_rate)
- continue;
- if (new_rate > best_rate) {
- best_rate = new_rate;
- best_parent = parents[i];
- }
- }
- if (!best_rate)
- return -ENOENT;
- if (best_parent != clk->parent)
- clk_set_parent_nolock(clk, best_parent);
- return clksel_set_rate_div(clk, best_rate);
-}
-
-static struct clk clk_gpu = {
- .name = "gpu",
- .mode = gate_mode,
- .gate_idx = CLK_GATE_GPU,
- .recalc = clksel_recalc_div,
- .set_rate = clk_gpu_set_rate,
- .clksel_con = CRU_CLKSEL17_CON,
- .clksel_mask = 0x1F,
- .clksel_shift = 16,
- .clksel_parent_mask = 3,
- .clksel_parent_shift = 14,
- .parents = xpu_parents,
-};
-
-static struct clk aclk_gpu = {
- .name = "aclk_gpu",
- .mode = gate_mode,
- .gate_idx = CLK_GATE_ACLK_GPU,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_div,
- .clksel_con = CRU_CLKSEL17_CON,
- .clksel_mask = 0x1F,
- .clksel_shift = 23,
- .clksel_parent_mask = 3,
- .clksel_parent_shift = 21,
- .parents = xpu_parents,
-};
-
-
-static struct clk vip_clkin = {
- .name = "vip_clkin",
-};
-
-static struct clk *clk_vip_parents[4] = { &xin24m, &xin27m, &dclk_ebook };
-
-static struct clk clk_vip_out = {
- .name = "vip_out",
- .mode = gate_mode,
- .gate_idx = CLK_GATE_VIP_OUT,
- .clksel_con = CRU_CLKSEL1_CON,
- .clksel_parent_mask = 3,
- .clksel_parent_shift = 7,
- .parents = clk_vip_parents,
-};
-
-
-#define GATE_CLK(NAME,PARENT,ID) \
-static struct clk clk_##NAME = { \
- .name = #NAME, \
- .parent = &PARENT, \
- .mode = gate_mode, \
- .gate_idx = CLK_GATE_##ID, \
-}
-
-GATE_CLK(i2c0, pclk_cpu, I2C0);
-GATE_CLK(i2c1, pclk_periph, I2C1);
-GATE_CLK(i2c2, pclk_periph, I2C2);
-GATE_CLK(i2c3, pclk_periph, I2C3);
-
-GATE_CLK(gpio0, pclk_cpu, GPIO0);
-GATE_CLK(gpio1, pclk_periph, GPIO1);
-GATE_CLK(gpio2, pclk_periph, GPIO2);
-GATE_CLK(gpio3, pclk_periph, GPIO3);
-GATE_CLK(gpio4, pclk_cpu, GPIO4);
-GATE_CLK(gpio5, pclk_periph, GPIO5);
-GATE_CLK(gpio6, pclk_cpu, GPIO6);
-
-GATE_CLK(dma1, aclk_cpu, DMA1);
-GATE_CLK(dma2, aclk_periph, DMA2);
-
-GATE_CLK(gic, aclk_cpu, GIC);
-GATE_CLK(intmem, aclk_cpu, INTMEM);
-GATE_CLK(rom, hclk_cpu, ROM);
-GATE_CLK(ddr_phy, aclk_cpu, DDR_PHY);
-GATE_CLK(ddr_reg, aclk_cpu, DDR_REG);
-GATE_CLK(ddr_cpu, aclk_cpu, DDR_CPU);
-GATE_CLK(efuse, pclk_cpu, EFUSE);
-GATE_CLK(tzpc, pclk_cpu, TZPC);
-GATE_CLK(debug, pclk_cpu, DEBUG);
-GATE_CLK(tpiu, pclk_cpu, TPIU);
-GATE_CLK(rtc, pclk_cpu, RTC);
-GATE_CLK(pmu, pclk_cpu, PMU);
-GATE_CLK(grf, pclk_cpu, GRF);
-
-GATE_CLK(emem, hclk_periph, EMEM);
-GATE_CLK(hclk_usb_peri, hclk_periph, HCLK_USB_PERI);
-GATE_CLK(aclk_ddr_peri, aclk_periph, ACLK_DDR_PERI);
-GATE_CLK(aclk_cpu_peri, aclk_cpu, ACLK_CPU_PERI);
-GATE_CLK(aclk_smc, aclk_periph, ACLK_SMC);
-GATE_CLK(smc, pclk_periph, SMC);
-GATE_CLK(hclk_mac, hclk_periph, HCLK_MAC);
-GATE_CLK(mii_tx, hclk_periph, MII_TX);
-GATE_CLK(mii_rx, hclk_periph, MII_RX);
-GATE_CLK(hif, hclk_periph, HIF);
-GATE_CLK(nandc, hclk_periph, NANDC);
-GATE_CLK(hclk_hsadc, hclk_periph, HCLK_HSADC);
-GATE_CLK(usbotg0, hclk_periph, USBOTG0);
-GATE_CLK(usbotg1, hclk_periph, USBOTG1);
-GATE_CLK(hclk_uhost, hclk_periph, HCLK_UHOST);
-GATE_CLK(pid_filter, hclk_periph, PID_FILTER);
-
-GATE_CLK(vip_slave, hclk_lcdc, VIP_SLAVE);
-GATE_CLK(wdt, pclk_periph, WDT);
-GATE_CLK(pwm, pclk_periph, PWM);
-GATE_CLK(vip_bus, aclk_cpu, VIP_BUS);
-GATE_CLK(vip_matrix, clk_vip_bus, VIP_MATRIX);
-GATE_CLK(vip_input, vip_clkin, VIP_INPUT);
-GATE_CLK(jtag, aclk_cpu, JTAG);
-
-GATE_CLK(aclk_ddr_lcdc, aclk_lcdc, ACLK_DDR_LCDC);
-GATE_CLK(aclk_ipp, aclk_lcdc, ACLK_IPP);
-GATE_CLK(hclk_ipp, hclk_lcdc, HCLK_IPP);
-GATE_CLK(hclk_ebook, hclk_lcdc, HCLK_EBOOK);
-GATE_CLK(aclk_disp_matrix, aclk_lcdc, ACLK_DISP_MATRIX);
-GATE_CLK(hclk_disp_matrix, hclk_lcdc, HCLK_DISP_MATRIX);
-GATE_CLK(aclk_ddr_vepu, aclk_vepu, ACLK_DDR_VEPU);
-GATE_CLK(aclk_ddr_vdpu, aclk_vdpu, ACLK_DDR_VDPU);
-GATE_CLK(aclk_ddr_gpu, aclk_gpu, ACLK_DDR_GPU);
-GATE_CLK(hclk_gpu, hclk_cpu, HCLK_GPU);
-GATE_CLK(hclk_cpu_vcodec, hclk_cpu, HCLK_CPU_VCODEC);
-GATE_CLK(hclk_cpu_display, hclk_cpu, HCLK_CPU_DISPLAY);
-
-GATE_CLK(hclk_mmc0, hclk_periph, HCLK_MMC0);
-GATE_CLK(hclk_mmc1, hclk_periph, HCLK_MMC1);
-GATE_CLK(hclk_emmc, hclk_periph, HCLK_EMMC);
-
-
-static void __sramfunc pmu_set_power_domain_sram(enum pmu_power_domain pd, bool on)
-{
- if (on)
- writel(readl(RK29_PMU_BASE + PMU_PD_CON) & ~(1 << pd), RK29_PMU_BASE + PMU_PD_CON);
- else
- writel(readl(RK29_PMU_BASE + PMU_PD_CON) | (1 << pd), RK29_PMU_BASE + PMU_PD_CON);
- dsb();
-
- while (pmu_power_domain_is_on(pd) != on)
- ;
-}
-
-static noinline void do_pmu_set_power_domain(enum pmu_power_domain pd, bool on)
-{
- static unsigned long save_sp;
-
- DDR_SAVE_SP(save_sp);
- pmu_set_power_domain_sram(pd, on);
- DDR_RESTORE_SP(save_sp);
-}
-
-void pmu_set_power_domain(enum pmu_power_domain pd, bool on)
-{
- unsigned long flags;
-
- mdelay(10);
- local_irq_save(flags);
- do_pmu_set_power_domain(pd, on);
- local_irq_restore(flags);
- mdelay(10);
-}
-EXPORT_SYMBOL(pmu_set_power_domain);
-
-static int pd_vcodec_mode(struct clk *clk, int on)
-{
- if (on) {
- u32 gate;
-
- gate = cru_clkgate3_con_mirror;
- gate |= (1 << CLK_GATE_ACLK_DDR_VEPU % 32);
- gate &= ~((1 << CLK_GATE_ACLK_VEPU % 32)
- | (1 << CLK_GATE_HCLK_VEPU % 32)
- | (1 << CLK_GATE_HCLK_CPU_VCODEC % 32));
- cru_writel(gate, CRU_CLKGATE3_CON);
-
- pmu_set_power_domain(PD_VCODEC, true);
-
- cru_writel(cru_clkgate3_con_mirror, CRU_CLKGATE3_CON);
- } else {
- pmu_set_power_domain(PD_VCODEC, false);
- }
-
- return 0;
-}
-
-static struct clk pd_vcodec = {
- .name = "pd_vcodec",
- .flags = IS_PD,
- .mode = pd_vcodec_mode,
- .gate_idx = PD_VCODEC,
-};
-
-static int pd_display_mode(struct clk *clk, int on)
-{
-#if 0 /* display power domain is buggy, always keep it on. */
- if (on) {
- u32 gate, gate2;
-
- gate = cru_clkgate3_con_mirror;
- gate |= (1 << CLK_GATE_ACLK_DDR_LCDC % 32);
- gate &= ~((1 << CLK_GATE_HCLK_CPU_DISPLAY % 32)
- | (1 << CLK_GATE_HCLK_DISP_MATRIX % 32)
- | (1 << CLK_GATE_ACLK_DISP_MATRIX % 32)
- | (1 << CLK_GATE_DCLK_EBOOK % 32)
- | (1 << CLK_GATE_HCLK_EBOOK % 32)
- | (1 << CLK_GATE_HCLK_IPP % 32)
- | (1 << CLK_GATE_ACLK_IPP % 32)
- | (1 << CLK_GATE_DCLK_LCDC % 32)
- | (1 << CLK_GATE_HCLK_LCDC % 32)
- | (1 << CLK_GATE_ACLK_LCDC % 32));
- cru_writel(gate, CRU_CLKGATE3_CON);
-
- gate2 = cru_readl(CRU_CLKGATE2_CON);
- gate = gate2;
- gate &= ~((1 << CLK_GATE_VIP_OUT % 32)
- | (1 << CLK_GATE_VIP_SLAVE % 32)
- | (1 << CLK_GATE_VIP_MATRIX % 32)
- | (1 << CLK_GATE_VIP_BUS % 32));
- cru_writel(gate, CRU_CLKGATE2_CON);
-
- pmu_set_power_domain(PD_DISPLAY, true);
-
- cru_writel(gate2, CRU_CLKGATE2_CON);
- cru_writel(cru_clkgate3_con_mirror, CRU_CLKGATE3_CON);
- } else {
- pmu_set_power_domain(PD_DISPLAY, false);
- }
-#endif
-
- return 0;
-}
-
-static struct clk pd_display = {
- .name = "pd_display",
- .flags = IS_PD,
- .mode = pd_display_mode,
- .gate_idx = PD_DISPLAY,
-};
-
-static int pd_gpu_mode(struct clk *clk, int on)
-{
- if (on) {
- pmu_set_power_domain(PD_GPU, true);
- } else {
- pmu_set_power_domain(PD_GPU, false);
- }
-
- return 0;
-}
-
-static struct clk pd_gpu = {
- .name = "pd_gpu",
- .flags = IS_PD,
- .mode = pd_gpu_mode,
- .gate_idx = PD_GPU,
-};
-
-
-#define CLK(dev, con, ck) \
- { \
- .dev_id = dev, \
- .con_id = con, \
- .clk = ck, \
- }
-
-#define CLK1(name) \
- { \
- .dev_id = NULL, \
- .con_id = #name, \
- .clk = &clk_##name, \
- }
-
-static struct clk_lookup clks[] = {
- CLK(NULL, "xin24m", &xin24m),
- CLK(NULL, "xin27m", &xin27m),
- CLK(NULL, "otgphy0_clkin", &otgphy0_clkin),
- CLK(NULL, "otgphy1_clkin", &otgphy1_clkin),
- CLK(NULL, "gpsclk", &gpsclk),
- CLK(NULL, "vip_clkin", &vip_clkin),
-
- CLK1(12m),
- CLK(NULL, "arm_pll", &arm_pll_clk),
- CLK(NULL, "ddr_pll", &ddr_pll_clk),
- CLK(NULL, "codec_pll", &codec_pll_clk),
- CLK(NULL, "general_pll", &general_pll_clk),
-
- CLK1(core),
- CLK(NULL, "aclk_cpu", &aclk_cpu),
- CLK(NULL, "hclk_cpu", &hclk_cpu),
- CLK(NULL, "pclk_cpu", &pclk_cpu),
-
- CLK(NULL, "aclk_periph", &aclk_periph),
- CLK(NULL, "hclk_periph", &hclk_periph),
- CLK(NULL, "pclk_periph", &pclk_periph),
-
- CLK1(vip_out),
- CLK1(otgphy0),
- CLK1(otgphy1),
- CLK1(uhost),
- CLK1(mac_ref_div),
- CLK1(mac_ref),
-
- CLK("rk29_i2s.0", "i2s_div", &clk_i2s0_div),
- CLK("rk29_i2s.0", "i2s_frac_div", &clk_i2s0_frac_div),
- CLK("rk29_i2s.0", "i2s", &clk_i2s0),
- CLK("rk29_i2s.1", "i2s_div", &clk_i2s1_div),
- CLK("rk29_i2s.1", "i2s_frac_div", &clk_i2s1_frac_div),
- CLK("rk29_i2s.1", "i2s", &clk_i2s1),
- CLK(NULL, "spdif_div", &clk_spdif_div),
- CLK(NULL, "spdif_frac_div", &clk_spdif_frac_div),
- CLK(NULL, "spdif", &clk_spdif),
-
- CLK1(spi_src),
- CLK("rk29xx_spim.0", "spi", &clk_spi0),
- CLK("rk29xx_spim.1", "spi", &clk_spi1),
-
- CLK1(saradc),
- CLK1(timer0),
- CLK1(timer1),
- CLK1(timer2),
- CLK1(timer3),
-
- CLK1(mmc_src),
- CLK("rk29_sdmmc.0", "mmc", &clk_mmc0),
- CLK("rk29_sdmmc.0", "hclk_mmc", &clk_hclk_mmc0),
- CLK("rk29_sdmmc.1", "mmc", &clk_mmc1),
- CLK("rk29_sdmmc.1", "hclk_mmc", &clk_hclk_mmc1),
- CLK1(emmc),
- CLK1(hclk_emmc),
- CLK1(ddr),
-
- CLK1(uart01_src),
- CLK("rk29_serial.0", "uart", &clk_uart0),
- CLK("rk29_serial.0", "uart_div", &clk_uart0_div),
- CLK("rk29_serial.0", "uart_frac_div", &clk_uart0_frac_div),
- CLK("rk29_serial.1", "uart", &clk_uart1),
- CLK("rk29_serial.1", "uart_div", &clk_uart1_div),
- CLK("rk29_serial.1", "uart_frac_div", &clk_uart1_frac_div),
-
- CLK1(uart23_src),
- CLK("rk29_serial.2", "uart", &clk_uart2),
- CLK("rk29_serial.2", "uart_div", &clk_uart2_div),
- CLK("rk29_serial.2", "uart_frac_div", &clk_uart2_frac_div),
- CLK("rk29_serial.3", "uart", &clk_uart3),
- CLK("rk29_serial.3", "uart_div", &clk_uart3_div),
- CLK("rk29_serial.3", "uart_frac_div", &clk_uart3_frac_div),
-
- CLK1(hsadc_div),
- CLK1(hsadc_frac_div),
- CLK1(demod),
- CLK1(hsadc),
- CLK1(hsadc_div2),
- CLK1(hsadc_div2_inv),
- CLK1(hsadc_out),
-
- CLK(NULL, "dclk_lcdc_div", &dclk_lcdc_div),
- CLK(NULL, "dclk_lcdc", &dclk_lcdc),
- CLK(NULL, "dclk_ebook", &dclk_ebook),
- CLK(NULL, "aclk_lcdc", &aclk_lcdc),
- CLK(NULL, "hclk_lcdc", &hclk_lcdc),
-
- CLK1(vpu),
- CLK(NULL, "aclk_vepu", &aclk_vepu),
- CLK(NULL, "hclk_vepu", &hclk_vepu),
- CLK(NULL, "aclk_vdpu", &aclk_vdpu),
- CLK(NULL, "hclk_vdpu", &hclk_vdpu),
- CLK1(gpu),
- CLK(NULL, "aclk_gpu", &aclk_gpu),
-
- CLK("rk29_i2c.0", "i2c", &clk_i2c0),
- CLK("rk29_i2c.1", "i2c", &clk_i2c1),
- CLK("rk29_i2c.2", "i2c", &clk_i2c2),
- CLK("rk29_i2c.3", "i2c", &clk_i2c3),
-
- CLK1(gpio0),
- CLK1(gpio1),
- CLK1(gpio2),
- CLK1(gpio3),
- CLK1(gpio4),
- CLK1(gpio5),
- CLK1(gpio6),
-
- CLK1(dma1),
- CLK1(dma2),
-
- CLK1(gic),
- CLK1(intmem),
- CLK1(rom),
- CLK1(ddr_phy),
- CLK1(ddr_reg),
- CLK1(ddr_cpu),
- CLK1(efuse),
- CLK1(tzpc),
- CLK1(debug),
- CLK1(tpiu),
- CLK1(rtc),
- CLK1(pmu),
- CLK1(grf),
-
- CLK1(emem),
- CLK1(hclk_usb_peri),
- CLK1(aclk_ddr_peri),
- CLK1(aclk_cpu_peri),
- CLK1(aclk_smc),
- CLK1(smc),
- CLK1(hclk_mac),
- CLK1(mii_tx),
- CLK1(mii_rx),
- CLK1(hif),
- CLK1(nandc),
- CLK1(hclk_hsadc),
- CLK1(usbotg0),
- CLK1(usbotg1),
- CLK1(hclk_uhost),
- CLK1(pid_filter),
-
- CLK1(vip_slave),
- CLK1(wdt),
- CLK1(pwm),
- CLK1(vip_bus),
- CLK1(vip_matrix),
- CLK1(vip_input),
- CLK1(jtag),
-
- CLK1(aclk_ddr_lcdc),
- CLK1(aclk_ipp),
- CLK1(hclk_ipp),
- CLK1(hclk_ebook),
- CLK1(aclk_disp_matrix),
- CLK1(hclk_disp_matrix),
- CLK1(aclk_ddr_vepu),
- CLK1(aclk_ddr_vdpu),
- CLK1(aclk_ddr_gpu),
- CLK1(hclk_gpu),
- CLK1(hclk_cpu_vcodec),
- CLK1(hclk_cpu_display),
-
- CLK(NULL, "pd_vcodec", &pd_vcodec),
- CLK(NULL, "pd_display", &pd_display),
- CLK(NULL, "pd_gpu", &pd_gpu),
-};
-
-static LIST_HEAD(clocks);
-static DEFINE_MUTEX(clocks_mutex);
-static DEFINE_SPINLOCK(clockfw_lock);
-#define LOCK() do { WARN_ON(in_irq()); if (!irqs_disabled()) spin_lock_bh(&clockfw_lock); } while (0)
-#define UNLOCK() do { if (!irqs_disabled()) spin_unlock_bh(&clockfw_lock); } while (0)
-
-static int clk_enable_nolock(struct clk *clk)
-{
- int ret = 0;
-
- if (clk->usecount == 0) {
- if (clk->parent) {
- ret = clk_enable_nolock(clk->parent);
- if (ret)
- return ret;
- }
-
- if (clk->notifier_count)
- clk_notify(clk, CLK_PRE_ENABLE, clk->rate, clk->rate);
- if (clk->mode)
- ret = clk->mode(clk, 1);
- if (clk->notifier_count)
- clk_notify(clk, ret ? CLK_ABORT_ENABLE : CLK_POST_ENABLE, clk->rate, clk->rate);
- if (ret) {
- if (clk->parent)
- clk_disable_nolock(clk->parent);
- return ret;
- }
- pr_debug("%s enabled\n", clk->name);
- }
- clk->usecount++;
-
- return ret;
-}
-
-int clk_enable(struct clk *clk)
-{
- int ret = 0;
-
- if (clk == NULL || IS_ERR(clk))
- return -EINVAL;
-
- LOCK();
- ret = clk_enable_nolock(clk);
- UNLOCK();
-
- return ret;
-}
-EXPORT_SYMBOL(clk_enable);
-
-static void clk_disable_nolock(struct clk *clk)
-{
- if (clk->usecount == 0) {
- printk(KERN_ERR "Trying disable clock %s with 0 usecount\n", clk->name);
- WARN_ON(1);
- return;
- }
-
- if (--clk->usecount == 0) {
- int ret = 0;
- if (clk->notifier_count)
- clk_notify(clk, CLK_PRE_DISABLE, clk->rate, clk->rate);
- if (clk->mode)
- ret = clk->mode(clk, 0);
- if (clk->notifier_count)
- clk_notify(clk, ret ? CLK_ABORT_DISABLE : CLK_POST_DISABLE, clk->rate, clk->rate);
- pr_debug("%s disabled\n", clk->name);
- if (ret == 0 && clk->parent)
- clk_disable_nolock(clk->parent);
- }
-}
-
-void clk_disable(struct clk *clk)
-{
- if (clk == NULL || IS_ERR(clk))
- return;
-
- LOCK();
- clk_disable_nolock(clk);
- UNLOCK();
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
- if (clk == NULL || IS_ERR(clk))
- return 0;
-
- return clk->rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-/*-------------------------------------------------------------------------
- * Optional clock functions defined in include/linux/clk.h
- *-------------------------------------------------------------------------*/
-
-/* Given a clock and a rate apply a clock specific rounding function */
-static long clk_round_rate_nolock(struct clk *clk, unsigned long rate)
-{
- if (clk->round_rate)
- return clk->round_rate(clk, rate);
-
- if (clk->flags & RATE_FIXED)
- printk(KERN_ERR "clock: clk_round_rate called on fixed-rate clock %s\n", clk->name);
-
- return clk->rate;
-}
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
- long ret = 0;
-
- if (clk == NULL || IS_ERR(clk))
- return ret;
-
- LOCK();
- ret = clk_round_rate_nolock(clk, rate);
- UNLOCK();
-
- return ret;
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-static void __clk_recalc(struct clk *clk)
-{
- if (unlikely(clk->flags & RATE_FIXED))
- return;
- if (clk->recalc)
- clk->rate = clk->recalc(clk);
- else if (clk->parent)
- clk->rate = clk->parent->rate;
- pr_debug("%s new clock rate is %lu\n", clk->name, clk->rate);
-}
-
-static int clk_set_rate_nolock(struct clk *clk, unsigned long rate)
-{
- int ret;
- unsigned long old_rate;
-
- if (rate == clk->rate)
- return 0;
-
- pr_debug("set_rate for clock %s to rate %ld\n", clk->name, rate);
-
- if (clk->flags & CONFIG_PARTICIPANT)
- return -EINVAL;
-
- if (!clk->set_rate)
- return -EINVAL;
-
- old_rate = clk->rate;
- if (clk->notifier_count)
- clk_notify(clk, CLK_PRE_RATE_CHANGE, old_rate, rate);
-
- ret = clk->set_rate(clk, rate);
-
- if (ret == 0) {
- __clk_recalc(clk);
- __propagate_rate(clk);
- }
-
- if (clk->notifier_count)
- clk_notify(clk, ret ? CLK_ABORT_RATE_CHANGE : CLK_POST_RATE_CHANGE, old_rate, clk->rate);
-
- return ret;
-}
-
-/* Set the clock rate for a clock source */
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret = -EINVAL;
-
- if (clk == NULL || IS_ERR(clk))
- return ret;
-
- LOCK();
- ret = clk_set_rate_nolock(clk, rate);
- UNLOCK();
-
- return ret;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-static int clk_set_parent_nolock(struct clk *clk, struct clk *parent)
-{
- int ret;
- int enabled = clk->usecount > 0;
- struct clk *old_parent = clk->parent;
-
- if (clk->parent == parent)
- return 0;
-
- /* if clk is already enabled, enable new parent first and disable old parent later. */
- if (enabled)
- clk_enable_nolock(parent);
-
- if (clk->set_parent)
- ret = clk->set_parent(clk, parent);
- else
- ret = clksel_set_parent(clk, parent);
-
- if (ret == 0) {
- /* OK */
- __clk_reparent(clk, parent);
- __clk_recalc(clk);
- __propagate_rate(clk);
- if (enabled)
- clk_disable_nolock(old_parent);
- } else {
- if (enabled)
- clk_disable_nolock(parent);
- }
-
- return ret;
-}
-
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
- int ret = -EINVAL;
-
- if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent))
- return ret;
-
- if (clk->set_parent == NULL && clk->parents == NULL)
- return ret;
-
- LOCK();
- if (clk->usecount == 0)
- ret = clk_set_parent_nolock(clk, parent);
- else
- ret = -EBUSY;
- UNLOCK();
-
- return ret;
-}
-EXPORT_SYMBOL(clk_set_parent);
-
-struct clk *clk_get_parent(struct clk *clk)
-{
- return clk->parent;
-}
-EXPORT_SYMBOL(clk_get_parent);
-
-static void __clk_reparent(struct clk *child, struct clk *parent)
-{
- if (child->parent == parent)
- return;
- pr_debug("%s reparent to %s (was %s)\n", child->name, parent->name, ((child->parent) ? child->parent->name : "NULL"));
-
- list_del_init(&child->sibling);
- if (parent)
- list_add(&child->sibling, &parent->children);
- child->parent = parent;
-}
-
-/* Propagate rate to children */
-static void __propagate_rate(struct clk *tclk)
-{
- struct clk *clkp;
-
- list_for_each_entry(clkp, &tclk->children, sibling) {
- __clk_recalc(clkp);
- __propagate_rate(clkp);
- }
-}
-
-static LIST_HEAD(root_clks);
-
-/**
- * recalculate_root_clocks - recalculate and propagate all root clocks
- *
- * Recalculates all root clocks (clocks with no parent), which if the
- * clock's .recalc is set correctly, should also propagate their rates.
- * Called at init.
- */
-static void clk_recalculate_root_clocks_nolock(void)
-{
- struct clk *clkp;
-
- list_for_each_entry(clkp, &root_clks, sibling) {
- __clk_recalc(clkp);
- __propagate_rate(clkp);
- }
-}
-
-void clk_recalculate_root_clocks(void)
-{
- LOCK();
- clk_recalculate_root_clocks_nolock();
- UNLOCK();
-}
-
-
-/**
- * clk_preinit - initialize any fields in the struct clk before clk init
- * @clk: struct clk * to initialize
- *
- * Initialize any struct clk fields needed before normal clk initialization
- * can run. No return value.
- */
-static void clk_preinit(struct clk *clk)
-{
- INIT_LIST_HEAD(&clk->children);
-}
-
-static int clk_register(struct clk *clk)
-{
- if (clk == NULL || IS_ERR(clk))
- return -EINVAL;
-
- /*
- * trap out already registered clocks
- */
- if (clk->node.next || clk->node.prev)
- return 0;
-
- mutex_lock(&clocks_mutex);
-
- if (clk->get_parent)
- clk->parent = clk->get_parent(clk);
- else if (clk->parents)
- clk->parent = clksel_get_parent(clk);
-
- if (clk->parent)
- list_add(&clk->sibling, &clk->parent->children);
- else
- list_add(&clk->sibling, &root_clks);
-
- list_add(&clk->node, &clocks);
-
- mutex_unlock(&clocks_mutex);
-
- return 0;
-}
-
-static unsigned int __initdata armclk = 300 * MHZ;
-
-/*
- * You can override arm_clk rate with armclk= cmdline option.
- */
-static int __init armclk_setup(char *str)
-{
- get_option(&str, &armclk);
-
- if (!armclk)
- return 0;
-
- if (armclk < 10000)
- armclk *= MHZ;
-
- clk_set_rate_nolock(&arm_pll_clk, armclk);
- return 0;
-}
-early_param("armclk", armclk_setup);
-
-static void __init rk29_clock_common_init(unsigned long ppll_rate, unsigned long cpll_rate)
-{
- unsigned long aclk_p, hclk_p, pclk_p;
- struct clk *aclk_vepu_parent, *aclk_vdpu_parent, *aclk_gpu_parent;
-
- /* general pll */
- switch (ppll_rate) {
- case 96 * MHZ:
- aclk_p = 96 * MHZ;
- hclk_p = 48 * MHZ;
- pclk_p = 24 * MHZ;
- aclk_gpu_parent = aclk_vdpu_parent = aclk_vepu_parent = &codec_pll_clk;
- break;
- case 144 * MHZ:
- aclk_p = 144 * MHZ;
- hclk_p = 72 * MHZ;
- pclk_p = 36 * MHZ;
- aclk_gpu_parent = aclk_vdpu_parent = aclk_vepu_parent = &codec_pll_clk;
- break;
- default:
- ppll_rate = 288 * MHZ;
- case 288 * MHZ:
- case 300 * MHZ:
- aclk_p = ppll_rate / 2;
- hclk_p = ppll_rate / 2;
- pclk_p = ppll_rate / 8;
- aclk_gpu_parent = aclk_vdpu_parent = aclk_vepu_parent = &general_pll_clk;
- break;
- }
-
- clk_set_rate_nolock(&general_pll_clk, ppll_rate);
- lpj_gpll = div_u64(LPJ_600MHZ * general_pll_clk.rate, 600 * MHZ);
- clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
- clk_set_rate_nolock(&aclk_periph, aclk_p);
- clk_set_rate_nolock(&hclk_periph, hclk_p);
- clk_set_rate_nolock(&pclk_periph, pclk_p);
- clk_set_parent_nolock(&clk_uhost, &general_pll_clk);
- clk_set_rate_nolock(&clk_uhost, 48 * MHZ);
- if (clk_uhost.rate != 48 * MHZ)
- clk_set_parent_nolock(&clk_uhost, &otgphy1_clkin);
- clk_set_parent_nolock(&clk_i2s0_div, &general_pll_clk);
- clk_set_parent_nolock(&clk_i2s1_div, &general_pll_clk);
- clk_set_parent_nolock(&clk_spdif_div, &general_pll_clk);
- clk_set_parent_nolock(&clk_spi_src, &general_pll_clk);
- clk_set_rate_nolock(&clk_spi0, 40 * MHZ);
- clk_set_rate_nolock(&clk_spi1, 40 * MHZ);
- clk_set_parent_nolock(&clk_mmc_src, &general_pll_clk);
- clk_set_parent_nolock(&clk_uart01_src, &general_pll_clk);
- clk_set_parent_nolock(&clk_uart23_src, &general_pll_clk);
- clk_set_parent_nolock(&dclk_lcdc_div, &general_pll_clk);
- clk_set_parent_nolock(&clk_mac_ref_div, &general_pll_clk);
- clk_set_parent_nolock(&clk_hsadc_div, &general_pll_clk);
-
- /* codec pll */
- clk_set_rate_nolock(&codec_pll_clk, cpll_rate);
- clk_set_parent_nolock(&clk_gpu, &codec_pll_clk);
-
- /* ddr pll */
- clk_set_parent_nolock(&aclk_lcdc, &ddr_pll_clk);
-
- /* arm pll */
- clk_set_rate_nolock(&arm_pll_clk, armclk);
-
- /*you can choose clk parent form codec pll or periph pll for following logic*/
- clk_set_parent_nolock(&aclk_vepu, aclk_vepu_parent);
- clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
- clk_set_rate_nolock(&clk_aclk_ddr_vepu, 300 * MHZ);
- clk_set_rate_nolock(&hclk_vepu, 150 * MHZ);
- clk_set_parent_nolock(&aclk_vdpu, aclk_vdpu_parent);
- clk_set_parent_nolock(&aclk_gpu, aclk_gpu_parent);
- clk_set_rate_nolock(&aclk_gpu, 300 * MHZ);
-}
-
-static void __init clk_enable_init_clocks(void)
-{
- clk_enable_nolock(&hclk_cpu);
- clk_enable_nolock(&pclk_cpu);
- clk_enable_nolock(&hclk_periph);
- clk_enable_nolock(&pclk_periph);
- clk_enable_nolock(&clk_nandc);
- clk_enable_nolock(&clk_aclk_cpu_peri);
- clk_enable_nolock(&clk_aclk_ddr_peri);
- clk_enable_nolock(&clk_grf);
- clk_enable_nolock(&clk_pmu);
- clk_enable_nolock(&clk_ddr_cpu);
- clk_enable_nolock(&clk_ddr_reg);
- clk_enable_nolock(&clk_ddr_phy);
- clk_enable_nolock(&clk_gic);
- clk_enable_nolock(&clk_dma2);
- clk_enable_nolock(&clk_dma1);
- clk_enable_nolock(&clk_emem);
- clk_enable_nolock(&clk_intmem);
- clk_enable_nolock(&clk_debug);
- clk_enable_nolock(&clk_tpiu);
- clk_enable_nolock(&clk_jtag);
- clk_enable_nolock(&clk_uart1);
-}
-
-static int __init clk_disable_unused(void)
-{
- struct clk *ck;
-
- list_for_each_entry(ck, &clocks, node) {
- if (ck->usecount > 0 || ck->mode == NULL || (ck->flags & IS_PD))
- continue;
-
- LOCK();
- clk_enable_nolock(ck);
- clk_disable_nolock(ck);
- UNLOCK();
- }
-
- return 0;
-}
-
-void __init rk29_clock_init2(enum periph_pll ppll_rate, enum codec_pll cpll_rate, bool _has_xin27m)
-{
- struct clk_lookup *lk;
-
- has_xin27m = _has_xin27m;
-
- cru_clkgate3_con_mirror = cru_readl(CRU_CLKGATE3_CON);
- cru_softrst0_con_mirror = cru_readl(CRU_SOFTRST0_CON);
-
- for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++)
- clk_preinit(lk->clk);
-
- for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) {
- clkdev_add(lk);
- clk_register(lk->clk);
- }
-
- clk_recalculate_root_clocks_nolock();
-
- loops_per_jiffy = div_u64(LPJ_600MHZ * arm_pll_clk.rate, 600 * MHZ);
-
- /*
- * Only enable those clocks we will need, let the drivers
- * enable other clocks as necessary
- */
- clk_enable_init_clocks();
-
- /*
- * Disable any unused clocks left on by the bootloader
- */
- clk_disable_unused();
-
- rk29_clock_common_init(ppll_rate, cpll_rate);
-
- printk(KERN_INFO "Clocking rate (apll/dpll/cpll/gpll/core/aclk_cpu/hclk_cpu/pclk_cpu/aclk_periph/hclk_periph/pclk_periph): %ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld MHz",
- arm_pll_clk.rate / MHZ, ddr_pll_clk.rate / MHZ, codec_pll_clk.rate / MHZ, general_pll_clk.rate / MHZ, clk_core.rate / MHZ,
- aclk_cpu.rate / MHZ, hclk_cpu.rate / MHZ, pclk_cpu.rate / MHZ, aclk_periph.rate / MHZ, hclk_periph.rate / MHZ, pclk_periph.rate / MHZ);
- printk(KERN_CONT " (20110909)\n");
-
- preset_lpj = loops_per_jiffy;
-}
-
-void __init rk29_clock_init(enum periph_pll ppll_rate)
-{
- rk29_clock_init2(ppll_rate, codec_pll_297mhz, true);
-}
-
-#ifdef CONFIG_PROC_FS
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-
-static void dump_clock(struct seq_file *s, struct clk *clk, int deep)
-{
- struct clk* ck;
- int i;
- unsigned long rate = clk->rate;
-
- for (i = 0; i < deep; i++)
- seq_printf(s, " ");
-
- seq_printf(s, "%-11s ", clk->name);
-
- if (clk->flags & IS_PD) {
- seq_printf(s, "%s ", pmu_power_domain_is_on(clk->gate_idx) ? "on " : "off");
- }
-
- if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
- u32 reg;
- int idx = clk->gate_idx;
- u32 v;
-
- reg = CRU_CLKGATE0_CON;
- reg += (idx >> 5) << 2;
- idx &= 0x1F;
-
- if (reg == CRU_CLKGATE3_CON)
- v = cru_clkgate3_con_mirror & (1 << idx);
- else
- v = cru_readl(reg) & (1 << idx);
-
- seq_printf(s, "%s ", v ? "off" : "on ");
- }
-
- if (clk == &arm_pll_clk) {
- switch (cru_readl(CRU_MODE_CON) & CRU_CPU_MODE_MASK) {
- case CRU_CPU_MODE_SLOW: seq_printf(s, "slow "); break;
- case CRU_CPU_MODE_NORMAL: seq_printf(s, "normal "); break;
- case CRU_CPU_MODE_SLOW27: seq_printf(s, "slow27 "); break;
- }
- if (cru_readl(CRU_APLL_CON) & PLL_BYPASS) seq_printf(s, "bypass ");
- } else if (clk == &ddr_pll_clk) {
- switch (cru_readl(CRU_MODE_CON) & CRU_DDR_MODE_MASK) {
- case CRU_DDR_MODE_SLOW: seq_printf(s, "slow "); break;
- case CRU_DDR_MODE_NORMAL: seq_printf(s, "normal "); break;
- case CRU_DDR_MODE_SLOW27: seq_printf(s, "slow27 "); break;
- }
- if (cru_readl(CRU_DPLL_CON) & PLL_BYPASS) seq_printf(s, "bypass ");
- } else if (clk == &codec_pll_clk) {
- switch (cru_readl(CRU_MODE_CON) & CRU_CODEC_MODE_MASK) {
- case CRU_CODEC_MODE_SLOW: seq_printf(s, "slow "); break;
- case CRU_CODEC_MODE_NORMAL: seq_printf(s, "normal "); break;
- case CRU_CODEC_MODE_SLOW27: seq_printf(s, "slow27 "); break;
- }
- if (cru_readl(CRU_CPLL_CON) & PLL_BYPASS) seq_printf(s, "bypass ");
- } else if (clk == &general_pll_clk) {
- switch (cru_readl(CRU_MODE_CON) & CRU_GENERAL_MODE_MASK) {
- case CRU_GENERAL_MODE_SLOW: seq_printf(s, "slow "); break;
- case CRU_GENERAL_MODE_NORMAL: seq_printf(s, "normal "); break;
- case CRU_GENERAL_MODE_SLOW27: seq_printf(s, "slow27 "); break;
- }
- if (cru_readl(CRU_GPLL_CON) & PLL_BYPASS) seq_printf(s, "bypass ");
- } else if (clk == &clk_ddr) {
- rate = clk->recalc(clk);
- }
-
- if (rate >= MHZ) {
- if (rate % MHZ)
- seq_printf(s, "%ld.%06ld MHz", rate / MHZ, rate % MHZ);
- else
- seq_printf(s, "%ld MHz", rate / MHZ);
- } else if (rate >= KHZ) {
- if (rate % KHZ)
- seq_printf(s, "%ld.%03ld KHz", rate / KHZ, rate % KHZ);
- else
- seq_printf(s, "%ld KHz", rate / KHZ);
- } else {
- seq_printf(s, "%ld Hz", rate);
- }
-
- seq_printf(s, " usecount = %d", clk->usecount);
-
- if (clk->parent)
- seq_printf(s, " parent = %s", clk->parent->name);
-
- seq_printf(s, "\n");
-
- list_for_each_entry(ck, &clocks, node) {
- if (ck->parent == clk)
- dump_clock(s, ck, deep + 1);
- }
-}
-
-static int proc_clk_show(struct seq_file *s, void *v)
-{
- struct clk* clk;
-
- mutex_lock(&clocks_mutex);
- list_for_each_entry(clk, &clocks, node) {
- if (!clk->parent)
- dump_clock(s, clk, 0);
- }
- mutex_unlock(&clocks_mutex);
-
- seq_printf(s, "\nCRU Registers:\n");
- seq_printf(s, "APLL : 0x%08x\n", cru_readl(CRU_APLL_CON));
- seq_printf(s, "DPLL : 0x%08x\n", cru_readl(CRU_DPLL_CON));
- seq_printf(s, "CPLL : 0x%08x\n", cru_readl(CRU_CPLL_CON));
- seq_printf(s, "GPLL : 0x%08x\n", cru_readl(CRU_GPLL_CON));
- seq_printf(s, "MODE : 0x%08x\n", cru_readl(CRU_MODE_CON));
- seq_printf(s, "CLKSEL0 : 0x%08x\n", cru_readl(CRU_CLKSEL0_CON));
- seq_printf(s, "CLKSEL1 : 0x%08x\n", cru_readl(CRU_CLKSEL1_CON));
- seq_printf(s, "CLKSEL2 : 0x%08x\n", cru_readl(CRU_CLKSEL2_CON));
- seq_printf(s, "CLKSEL3 : 0x%08x\n", cru_readl(CRU_CLKSEL3_CON));
- seq_printf(s, "CLKSEL4 : 0x%08x\n", cru_readl(CRU_CLKSEL4_CON));
- seq_printf(s, "CLKSEL5 : 0x%08x\n", cru_readl(CRU_CLKSEL5_CON));
- seq_printf(s, "CLKSEL6 : 0x%08x\n", cru_readl(CRU_CLKSEL6_CON));
- seq_printf(s, "CLKSEL7 : 0x%08x\n", cru_readl(CRU_CLKSEL7_CON));
- seq_printf(s, "CLKSEL8 : 0x%08x\n", cru_readl(CRU_CLKSEL8_CON));
- seq_printf(s, "CLKSEL9 : 0x%08x\n", cru_readl(CRU_CLKSEL9_CON));
- seq_printf(s, "CLKSEL10 : 0x%08x\n", cru_readl(CRU_CLKSEL10_CON));
- seq_printf(s, "CLKSEL11 : 0x%08x\n", cru_readl(CRU_CLKSEL11_CON));
- seq_printf(s, "CLKSEL12 : 0x%08x\n", cru_readl(CRU_CLKSEL12_CON));
- seq_printf(s, "CLKSEL13 : 0x%08x\n", cru_readl(CRU_CLKSEL13_CON));
- seq_printf(s, "CLKSEL14 : 0x%08x\n", cru_readl(CRU_CLKSEL14_CON));
- seq_printf(s, "CLKSEL15 : 0x%08x\n", cru_readl(CRU_CLKSEL15_CON));
- seq_printf(s, "CLKSEL16 : 0x%08x\n", cru_readl(CRU_CLKSEL16_CON));
- seq_printf(s, "CLKSEL17 : 0x%08x\n", cru_readl(CRU_CLKSEL17_CON));
- seq_printf(s, "CLKGATE0 : 0x%08x\n", cru_readl(CRU_CLKGATE0_CON));
- seq_printf(s, "CLKGATE1 : 0x%08x\n", cru_readl(CRU_CLKGATE1_CON));
- seq_printf(s, "CLKGATE2 : 0x%08x\n", cru_readl(CRU_CLKGATE2_CON));
- seq_printf(s, "CLKGATE3 : 0x%08x\n", cru_readl(CRU_CLKGATE3_CON));
- seq_printf(s, "CLKGATE3M: 0x%08x\n", cru_clkgate3_con_mirror);
- seq_printf(s, "SOFTRST0 : 0x%08x\n", cru_readl(CRU_SOFTRST0_CON));
- seq_printf(s, "SOFTRST0M: 0x%08x\n", cru_softrst0_con_mirror);
- seq_printf(s, "SOFTRST1 : 0x%08x\n", cru_readl(CRU_SOFTRST1_CON));
- seq_printf(s, "SOFTRST2 : 0x%08x\n", cru_readl(CRU_SOFTRST2_CON));
-
- seq_printf(s, "\nPMU Registers:\n");
- seq_printf(s, "WAKEUP_EN0 : 0x%08x\n", pmu_readl(PMU_WAKEUP_EN0));
- seq_printf(s, "WAKEUP_EN1 : 0x%08x\n", pmu_readl(PMU_WAKEUP_EN1));
- seq_printf(s, "WAKEUP_EN2 : 0x%08x\n", pmu_readl(PMU_WAKEUP_EN2));
- seq_printf(s, "PD_CON : 0x%08x\n", pmu_readl(PMU_PD_CON));
- seq_printf(s, "MISC_CON : 0x%08x\n", pmu_readl(PMU_MISC_CON));
- seq_printf(s, "PLL_CNT : 0x%08x\n", pmu_readl(PMU_PLL_CNT));
- seq_printf(s, "PD_ST : 0x%08x\n", pmu_readl(PMU_PD_ST));
- seq_printf(s, "INT_ST : 0x%08x\n", pmu_readl(PMU_INT_ST));
-
- return 0;
-}
-
-static int proc_clk_open(struct inode *inode, struct file *file)
-{
- return single_open(file, proc_clk_show, NULL);
-}
-
-static const struct file_operations proc_clk_fops = {
- .open = proc_clk_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-static int __init clk_proc_init(void)
-{
- proc_create("clocks", 0, NULL, &proc_clk_fops);
- return 0;
-
-}
-late_initcall(clk_proc_init);
-#endif /* CONFIG_PROC_FS */
-
-/* Clk notifier implementation */
-
-/**
- * struct clk_notifier - associate a clk with a notifier
- * @clk: struct clk * to associate the notifier with
- * @notifier_head: a raw_notifier_head for this clk
- * @node: linked list pointers
- *
- * A list of struct clk_notifier is maintained by the notifier code.
- * An entry is created whenever code registers the first notifier on a
- * particular @clk. Future notifiers on that @clk are added to the
- * @notifier_head.
- */
-struct clk_notifier {
- struct clk *clk;
- struct raw_notifier_head notifier_head;
- struct list_head node;
-};
-
-static LIST_HEAD(clk_notifier_list);
-
-/**
- * _clk_free_notifier_chain - safely remove struct clk_notifier
- * @cn: struct clk_notifier *
- *
- * Removes the struct clk_notifier @cn from the clk_notifier_list and
- * frees it.
- */
-static void _clk_free_notifier_chain(struct clk_notifier *cn)
-{
- list_del(&cn->node);
- kfree(cn);
-}
-
-/**
- * clk_notify - call clk notifier chain
- * @clk: struct clk * that is changing rate
- * @msg: clk notifier type (i.e., CLK_POST_RATE_CHANGE; see mach/clock.h)
- * @old_rate: old rate
- * @new_rate: new rate
- *
- * Triggers a notifier call chain on the post-clk-rate-change notifier
- * for clock 'clk'. Passes a pointer to the struct clk and the
- * previous and current rates to the notifier callback. Intended to be
- * called by internal clock code only. No return value.
- */
-static void clk_notify(struct clk *clk, unsigned long msg,
- unsigned long old_rate, unsigned long new_rate)
-{
- struct clk_notifier *cn;
- struct clk_notifier_data cnd;
-
- cnd.clk = clk;
- cnd.old_rate = old_rate;
- cnd.new_rate = new_rate;
-
- UNLOCK();
- list_for_each_entry(cn, &clk_notifier_list, node) {
- if (cn->clk == clk) {
- pr_debug("%s msg %lu rate %lu -> %lu\n", clk->name, msg, old_rate, new_rate);
- raw_notifier_call_chain(&cn->notifier_head, msg, &cnd);
- break;
- }
- }
- LOCK();
-}
-
-/**
- * clk_notifier_register - add a clock parameter change notifier
- * @clk: struct clk * to watch
- * @nb: struct notifier_block * with callback info
- *
- * Request notification for changes to the clock 'clk'. This uses a
- * blocking notifier. Callback code must not call into the clock
- * framework, as clocks_mutex is held. Pre-notifier callbacks will be
- * passed the previous and new rate of the clock.
- *
- * clk_notifier_register() must be called from process
- * context. Returns -EINVAL if called with null arguments, -ENOMEM
- * upon allocation failure; otherwise, passes along the return value
- * of blocking_notifier_chain_register().
- */
-int clk_notifier_register(struct clk *clk, struct notifier_block *nb)
-{
- struct clk_notifier *cn = NULL, *cn_new = NULL;
- int r;
- struct clk *clkp;
-
- if (!clk || IS_ERR(clk) || !nb)
- return -EINVAL;
-
- mutex_lock(&clocks_mutex);
-
- list_for_each_entry(cn, &clk_notifier_list, node)
- if (cn->clk == clk)
- break;
-
- if (cn->clk != clk) {
- cn_new = kzalloc(sizeof(struct clk_notifier), GFP_KERNEL);
- if (!cn_new) {
- r = -ENOMEM;
- goto cnr_out;
- };
-
- cn_new->clk = clk;
- RAW_INIT_NOTIFIER_HEAD(&cn_new->notifier_head);
-
- list_add(&cn_new->node, &clk_notifier_list);
- cn = cn_new;
- }
-
- r = raw_notifier_chain_register(&cn->notifier_head, nb);
- if (!IS_ERR_VALUE(r)) {
- clkp = clk;
- do {
- clkp->notifier_count++;
- } while ((clkp = clkp->parent));
- } else {
- if (cn_new)
- _clk_free_notifier_chain(cn);
- }
-
-cnr_out:
- mutex_unlock(&clocks_mutex);
-
- return r;
-}
-EXPORT_SYMBOL(clk_notifier_register);
-
-/**
- * clk_notifier_unregister - remove a clock change notifier
- * @clk: struct clk *
- * @nb: struct notifier_block * with callback info
- *
- * Request no further notification for changes to clock 'clk'.
- * Returns -EINVAL if called with null arguments; otherwise, passes
- * along the return value of blocking_notifier_chain_unregister().
- */
-int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb)
-{
- struct clk_notifier *cn = NULL;
- struct clk *clkp;
- int r = -EINVAL;
-
- if (!clk || IS_ERR(clk) || !nb)
- return -EINVAL;
-
- mutex_lock(&clocks_mutex);
-
- list_for_each_entry(cn, &clk_notifier_list, node)
- if (cn->clk == clk)
- break;
-
- if (cn->clk != clk) {
- r = -ENOENT;
- goto cnu_out;
- };
-
- r = raw_notifier_chain_unregister(&cn->notifier_head, nb);
- if (!IS_ERR_VALUE(r)) {
- clkp = clk;
- do {
- clkp->notifier_count--;
- } while ((clkp = clkp->parent));
- }
-
- /*
- * XXX ugh, layering violation. There should be some
- * support in the notifier code for this.
- */
- if (!cn->notifier_head.head)
- _clk_free_notifier_chain(cn);
-
-cnu_out:
- mutex_unlock(&clocks_mutex);
-
- return r;
-}
-EXPORT_SYMBOL(clk_notifier_unregister);
-
+++ /dev/null
-/* arch/arm/mach-rk29/cpufreq.c
- *
- * Copyright (C) 2010, 2011 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/clk.h>
-#include <linux/cpufreq.h>
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/reboot.h>
-#include <linux/regulator/consumer.h>
-#include <linux/suspend.h>
-#include <linux/tick.h>
-#include <linux/workqueue.h>
-#include <mach/clock.h>
-#include <mach/cpufreq.h>
-#include <../../../drivers/video/rk29_fb.h>
-
-#define MHZ (1000*1000)
-
-static int no_cpufreq_access;
-
-static struct cpufreq_frequency_table default_freq_table[] = {
-// { .index = 1100000, .frequency = 24000 },
-// { .index = 1200000, .frequency = 204000 },
-// { .index = 1200000, .frequency = 300000 },
- { .index = 1200000, .frequency = 408000 },
-// { .index = 1200000, .frequency = 600000 },
- { .index = 1200000, .frequency = 816000 }, /* must enable, see SLEEP_FREQ above */
-// { .index = 1250000, .frequency = 1008000 },
-// { .index = 1300000, .frequency = 1104000 },
-// { .index = 1400000, .frequency = 1176000 },
-// { .index = 1400000, .frequency = 1200000 },
- { .frequency = CPUFREQ_TABLE_END },
-};
-static struct cpufreq_frequency_table *freq_table = default_freq_table;
-static struct clk *arm_clk;
-static struct clk *ddr_clk;
-static unsigned long ddr_max_rate;
-static DEFINE_MUTEX(mutex);
-
-#ifdef CONFIG_REGULATOR
-static struct regulator *vcore;
-static int vcore_uV;
-#define CONFIG_RK29_CPU_FREQ_LIMIT_BY_TEMP
-#endif
-
-static struct workqueue_struct *wq;
-
-#ifdef CONFIG_RK29_CPU_FREQ_LIMIT_BY_TEMP
-static bool limit = true;
-module_param(limit, bool, 0644);
-
-static int limit_secs = 30;
-module_param(limit_secs, int, 0644);
-
-static int limit_secs_1200 = 6;
-module_param(limit_secs_1200, int, 0644);
-
-static int limit_temp;
-module_param(limit_temp, int, 0444);
-
-#define LIMIT_AVG_VOLTAGE 1200000 /* vU */
-#else /* !CONFIG_RK29_CPU_FREQ_LIMIT_BY_TEMP */
-#define LIMIT_AVG_VOLTAGE 1400000 /* vU */
-#endif /* CONFIG_RK29_CPU_FREQ_LIMIT_BY_TEMP */
-
-enum {
- DEBUG_CHANGE = 1U << 0,
- DEBUG_TEMP = 1U << 1,
- DEBUG_DISP = 1U << 2,
-};
-static uint debug_mask = DEBUG_CHANGE;
-module_param(debug_mask, uint, 0644);
-#define dprintk(mask, fmt, ...) do { if (mask & debug_mask) printk(KERN_DEBUG "cpufreq: " fmt, ##__VA_ARGS__); } while (0)
-
-#define LIMIT_AVG_FREQ (816 * 1000) /* kHz */
-static unsigned int limit_avg_freq = LIMIT_AVG_FREQ;
-module_param(limit_avg_freq, uint, 0444);
-
-static int limit_avg_index = -1;
-
-static unsigned int limit_avg_voltage = LIMIT_AVG_VOLTAGE;
-static int rk29_cpufreq_set_limit_avg_voltage(const char *val, struct kernel_param *kp)
-{
- int err = param_set_uint(val, kp);
- if (!err) {
- board_update_cpufreq_table(freq_table);
- }
- return err;
-}
-module_param_call(limit_avg_voltage, rk29_cpufreq_set_limit_avg_voltage, param_get_uint, &limit_avg_voltage, 0644);
-
-#define CONFIG_RK29_CPU_FREQ_LIMIT_BY_DISP
-#ifdef CONFIG_RK29_CPU_FREQ_LIMIT_BY_DISP
-static bool limit_fb1_enabled;
-static bool limit_hdmi_enabled;
-static inline bool aclk_limit(void) { return limit_hdmi_enabled && limit_fb1_enabled; }
-module_param(limit_fb1_enabled, bool, 0644);
-module_param(limit_hdmi_enabled, bool, 0644);
-#else
-static inline bool aclk_limit(void) { return false; }
-#endif
-
-#if defined(CONFIG_RK29_CPU_FREQ_LIMIT_BY_DISP) || defined(CONFIG_RK29_CPU_FREQ_LIMIT_BY_TEMP)
-static unsigned int limit_max_freq;
-static int limit_index_816 = -1;
-static unsigned int limit_freq_816;
-static int limit_index_1008 = -1;
-static unsigned int limit_freq_1008;
-#endif
-
-static bool rk29_cpufreq_is_ondemand_policy(struct cpufreq_policy *policy)
-{
- char c = 0;
- if (policy && policy->governor)
- c = policy->governor->name[0];
- return (c == 'o' || c == 'i' || c == 'c');
-}
-
-static void board_do_update_cpufreq_table(struct cpufreq_frequency_table *table)
-{
- unsigned int i;
-
- limit_avg_freq = 0;
- limit_avg_index = -1;
-#if defined(CONFIG_RK29_CPU_FREQ_LIMIT_BY_DISP) || defined(CONFIG_RK29_CPU_FREQ_LIMIT_BY_TEMP)
- limit_max_freq = 0;
- limit_index_816 = -1;
- limit_freq_816 = 0;
- limit_index_1008 = -1;
- limit_freq_1008 = 0;
-#endif
-
- for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) {
- table[i].frequency = clk_round_rate(arm_clk, table[i].frequency * 1000) / 1000;
- if (table[i].index <= limit_avg_voltage && limit_avg_freq < table[i].frequency) {
- limit_avg_freq = table[i].frequency;
- limit_avg_index = i;
- }
-#if defined(CONFIG_RK29_CPU_FREQ_LIMIT_BY_DISP) || defined(CONFIG_RK29_CPU_FREQ_LIMIT_BY_TEMP)
- if (limit_max_freq < table[i].frequency)
- limit_max_freq = table[i].frequency;
- if (table[i].frequency <= 816000 &&
- (limit_index_816 < 0 ||
- (limit_index_816 >= 0 && table[limit_index_816].frequency < table[i].frequency)))
- limit_index_816 = i;
- if (table[i].frequency <= 1008000 &&
- (limit_index_1008 < 0 ||
- (limit_index_1008 >= 0 && table[limit_index_1008].frequency < table[i].frequency))) {
- limit_index_1008 = i;
- limit_freq_1008 = table[i].frequency;
- }
-#endif
- }
-
- if (!limit_avg_freq)
- limit_avg_freq = LIMIT_AVG_FREQ;
-}
-
-int board_update_cpufreq_table(struct cpufreq_frequency_table *table)
-{
- mutex_lock(&mutex);
- if (arm_clk) {
- board_do_update_cpufreq_table(table);
- }
- freq_table = table;
- mutex_unlock(&mutex);
- return 0;
-}
-
-static int rk29_cpufreq_verify(struct cpufreq_policy *policy)
-{
- return cpufreq_frequency_table_verify(policy, freq_table);
-}
-
-#ifdef CONFIG_RK29_CPU_FREQ_LIMIT_BY_TEMP
-static bool limit_vpu_enabled;
-static bool limit_gpu_enabled;
-static bool limit_gpu_high;
-module_param(limit_vpu_enabled, bool, 0644);
-module_param(limit_gpu_enabled, bool, 0644);
-module_param(limit_gpu_high, bool, 0644);
-static struct clk* clk_vpu;
-static struct clk* clk_gpu;
-#define GPU_LOW_RATE (300 * MHZ)
-static unsigned long limit_gpu_low_rate = GPU_LOW_RATE;
-module_param(limit_gpu_low_rate, ulong, 0644);
-
-#define TEMP_COEFF_IDLE -1000
-#define TEMP_COEFF_408 -325
-#define TEMP_COEFF_624 -202
-#define TEMP_COEFF_816 -78
-#define TEMP_COEFF_1008 325
-#define TEMP_COEFF_1200 1300
-#define WORK_DELAY HZ
-static void rk29_cpufreq_limit_by_temp(struct cpufreq_policy *policy, unsigned int relation, int *index)
-{
- int c, ms;
- ktime_t now;
- static ktime_t last = { .tv64 = 0 };
- cputime64_t wall;
- u64 idle_time_us;
- static u64 last_idle_time_us;
- int idle;
- unsigned int cur = policy->cur;
- int overheat_temp_1200, overheat_temp;
- int temp;
- int target_index;
- unsigned int target_freq;
- bool overheat;
-
- if (!limit || !rk29_cpufreq_is_ondemand_policy(policy) ||
- (limit_index_816 < 0) || (relation & MASK_FURTHER_CPUFREQ)) {
- limit_temp = 0;
- last.tv64 = 0;
- return;
- }
-
- idle_time_us = get_cpu_idle_time_us(0, &wall);
- now = ktime_get();
- if (!last.tv64) {
- last = now;
- last_idle_time_us = idle_time_us;
- return;
- }
-
- temp = limit_temp;
- idle = idle_time_us - last_idle_time_us;
- if (idle) {
- temp -= idle; // -1000
- last_idle_time_us = idle_time_us;
- }
-
- ms = div_u64(ktime_us_delta(now, last), 1000);
- dprintk(DEBUG_TEMP, "%d kHz (%d uV) elapsed %d ms idle %d us\n", cur, vcore_uV, ms, idle);
- last = now;
-
- if (cur <= 408 * 1000)
- c = TEMP_COEFF_408;
- else if (cur <= 624 * 1000)
- c = TEMP_COEFF_624;
- else if (cur <= 816 * 1000)
- c = TEMP_COEFF_816;
- else if (cur <= 1008 * 1000)
- c = TEMP_COEFF_1008;
- else
- c = TEMP_COEFF_1200;
- temp += c * ms;
-
- if (temp < 0)
- temp = 0;
-
- target_index = *index;
- target_freq = freq_table[target_index].frequency;
- overheat_temp = TEMP_COEFF_1008 * limit_secs * MSEC_PER_SEC;
- overheat_temp_1200 = TEMP_COEFF_1200 * limit_secs_1200 * MSEC_PER_SEC;
- overheat = false;
-
- if (temp >= overheat_temp && target_freq > limit_freq_816) {
- target_index = limit_index_816;
- overheat = true;
- } else if (target_freq > limit_freq_1008 && limit_freq_1008 > limit_freq_816 &&
- temp >= overheat_temp_1200 && temp < overheat_temp) {
- target_index = limit_index_1008;
- overheat = true;
- } else if (target_freq > 1008000 && (limit_vpu_enabled || (limit_gpu_enabled && limit_gpu_high))) {
- target_index = limit_index_1008;
- }
-
- dprintk(DEBUG_TEMP, "%d kHz c %d temp %d (%s) selected %d kHz\n", target_freq, c, temp, overheat ? "overheat" : "normal", freq_table[target_index].frequency);
- limit_temp = temp;
- *index = target_index;
-}
-#else
-#define rk29_cpufreq_limit_by_temp(...) do {} while (0)
-#endif
-
-#ifdef CONFIG_RK29_CPU_FREQ_LIMIT_BY_DISP
-static void rk29_cpufreq_limit_by_disp(int *index)
-{
- unsigned int frequency = freq_table[*index].frequency;
- int new_index = -1;
-
- if (!aclk_limit())
- return;
-
- if (ddr_max_rate < 492 * MHZ) {
- if (limit_index_816 >= 0 && frequency > 816000)
- new_index = limit_index_816;
- } else {
- if (limit_index_1008 >= 0 && frequency > 1008000)
- new_index = limit_index_1008;
- }
-
- if (new_index != -1) {
- dprintk(DEBUG_DISP, "old %d new %d\n", freq_table[*index].frequency, freq_table[new_index].frequency);
- *index = new_index;
- }
-}
-#else
-#define rk29_cpufreq_limit_by_disp(...) do {} while (0)
-#endif
-
-static int rk29_cpufreq_do_target(struct cpufreq_policy *policy, unsigned int target_freq, unsigned int relation)
-{
- int index;
- int new_vcore_uV;
- struct cpufreq_freqs freqs;
- const struct cpufreq_frequency_table *freq;
- int err = 0;
- bool force = relation & CPUFREQ_FORCE_CHANGE;
- unsigned long new_arm_rate;
-
- relation &= ~CPUFREQ_FORCE_CHANGE;
-
- if ((relation & ENABLE_FURTHER_CPUFREQ) &&
- (relation & DISABLE_FURTHER_CPUFREQ)) {
- /* Invalidate both if both marked */
- relation &= ~ENABLE_FURTHER_CPUFREQ;
- relation &= ~DISABLE_FURTHER_CPUFREQ;
- pr_err("denied marking FURTHER_CPUFREQ as both marked.\n");
- }
- if (relation & ENABLE_FURTHER_CPUFREQ)
- no_cpufreq_access--;
- if (no_cpufreq_access) {
-#ifdef CONFIG_PM_VERBOSE
- pr_err("denied access to %s as it is disabled temporarily\n", __func__);
-#endif
- return -EINVAL;
- }
- if (relation & DISABLE_FURTHER_CPUFREQ)
- no_cpufreq_access++;
-
- if (cpufreq_frequency_table_target(policy, freq_table, target_freq, relation & ~MASK_FURTHER_CPUFREQ, &index)) {
- pr_err("invalid target_freq: %d\n", target_freq);
- return -EINVAL;
- }
- rk29_cpufreq_limit_by_disp(&index);
- rk29_cpufreq_limit_by_temp(policy, relation, &index);
- freq = &freq_table[index];
-
- if (policy->cur == freq->frequency && !force)
- return 0;
-
- freqs.old = policy->cur;
- freqs.new = freq->frequency;
- freqs.cpu = 0;
- new_vcore_uV = freq->index;
- new_arm_rate = freqs.new * 1000;
- dprintk(DEBUG_CHANGE, "%d kHz r %d(%c) selected %d kHz (%d uV)\n",
- target_freq, relation, relation & CPUFREQ_RELATION_H ? 'H' : 'L',
- freq->frequency, new_vcore_uV);
-
-#ifdef CONFIG_REGULATOR
- if (vcore && freqs.new > freqs.old && vcore_uV != new_vcore_uV) {
- int err = regulator_set_voltage(vcore, new_vcore_uV, new_vcore_uV);
- if (err) {
- pr_err("fail to set vcore (%d uV) for %d kHz: %d\n",
- new_vcore_uV, freqs.new, err);
- return err;
- } else {
- vcore_uV = new_vcore_uV;
- }
- }
-#endif
-
- cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
- dprintk(DEBUG_CHANGE, "pre change\n");
- clk_set_rate(arm_clk, freqs.new * 1000 + aclk_limit());
- dprintk(DEBUG_CHANGE, "post change\n");
- freqs.new = clk_get_rate(arm_clk) / 1000;
- cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
-
-#ifdef CONFIG_REGULATOR
- if (vcore && freqs.new < freqs.old && vcore_uV != new_vcore_uV) {
- int err = regulator_set_voltage(vcore, new_vcore_uV, new_vcore_uV);
- if (err) {
- pr_err("fail to set vcore (%d uV) for %d kHz: %d\n",
- new_vcore_uV, freqs.new, err);
- } else {
- vcore_uV = new_vcore_uV;
- }
- }
-#endif
- dprintk(DEBUG_CHANGE, "got %d kHz\n", freqs.new);
-
- return err;
-}
-
-static int rk29_cpufreq_target(struct cpufreq_policy *policy, unsigned int target_freq, unsigned int relation)
-{
- int err;
-
- if (!policy || policy->cpu != 0)
- return -EINVAL;
-
- mutex_lock(&mutex);
- err = rk29_cpufreq_do_target(policy, target_freq, relation);
- mutex_unlock(&mutex);
-
- return err;
-}
-
-#ifdef CONFIG_RK29_CPU_FREQ_LIMIT_BY_TEMP
-static void rk29_cpufreq_limit_by_temp_work_func(struct work_struct *work);
-static DECLARE_DELAYED_WORK(rk29_cpufreq_limit_by_temp_work, rk29_cpufreq_limit_by_temp_work_func);
-
-static int rk29_cpufreq_notifier_policy(struct notifier_block *nb,
- unsigned long val, void *data)
-{
- struct cpufreq_policy *policy = data;
-
- if (val != CPUFREQ_NOTIFY)
- return 0;
-
- if (rk29_cpufreq_is_ondemand_policy(policy)) {
- dprintk(DEBUG_TEMP, "queue work\n");
- queue_delayed_work(wq, &rk29_cpufreq_limit_by_temp_work, WORK_DELAY);
- } else {
- dprintk(DEBUG_TEMP, "cancel work\n");
- cancel_delayed_work(&rk29_cpufreq_limit_by_temp_work);
- }
-
- return 0;
-}
-
-static struct notifier_block notifier_policy_block = {
- .notifier_call = rk29_cpufreq_notifier_policy
-};
-
-static void rk29_cpufreq_limit_by_temp_work_func(struct work_struct *work)
-{
- struct cpufreq_policy *policy = cpufreq_cpu_get(0);
-
- if (policy) {
- dprintk(DEBUG_TEMP, "check %d kHz\n", policy->cur);
- cpufreq_driver_target(policy, policy->cur, CPUFREQ_RELATION_L);
- cpufreq_cpu_put(policy);
- }
- queue_delayed_work(wq, &rk29_cpufreq_limit_by_temp_work, WORK_DELAY);
-}
-
-static int rk29_cpufreq_vpu_notifier_event(struct notifier_block *this,
- unsigned long event, void *ptr)
-{
- switch (event) {
- case CLK_PRE_ENABLE:
- limit_vpu_enabled = true;
- break;
- case CLK_ABORT_ENABLE:
- case CLK_POST_DISABLE:
- limit_vpu_enabled = false;
- break;
- default:
- return NOTIFY_OK;
- }
-
- if (limit_vpu_enabled) {
- struct cpufreq_policy *policy = cpufreq_cpu_get(0);
-
- if (policy) {
- dprintk(DEBUG_TEMP, "vpu on\n");
- cpufreq_driver_target(policy, policy->cur, CPUFREQ_RELATION_L);
- cpufreq_cpu_put(policy);
- }
- }
- return NOTIFY_OK;
-}
-
-static struct notifier_block rk29_cpufreq_vpu_notifier = {
- .notifier_call = rk29_cpufreq_vpu_notifier_event,
-};
-
-static int rk29_cpufreq_gpu_notifier_event(struct notifier_block *this,
- unsigned long event, void *ptr)
-{
- struct clk_notifier_data *cnd = ptr;
- bool gpu_high_old = limit_gpu_enabled && limit_gpu_high;
- bool gpu_high;
-
- switch (event) {
- case CLK_PRE_RATE_CHANGE:
- if (cnd->new_rate > limit_gpu_low_rate)
- limit_gpu_high = true;
- break;
- case CLK_ABORT_RATE_CHANGE:
- if (cnd->new_rate > limit_gpu_low_rate && cnd->old_rate <= limit_gpu_low_rate)
- limit_gpu_high = false;
- break;
- case CLK_POST_RATE_CHANGE:
- if (cnd->new_rate <= limit_gpu_low_rate)
- limit_gpu_high = false;
- break;
- case CLK_PRE_ENABLE:
- limit_gpu_enabled = true;
- break;
- case CLK_ABORT_ENABLE:
- case CLK_POST_DISABLE:
- limit_gpu_enabled = false;
- break;
- default:
- return NOTIFY_OK;
- }
-
- gpu_high = limit_gpu_enabled && limit_gpu_high;
- if (gpu_high_old != gpu_high && gpu_high) {
- struct cpufreq_policy *policy = cpufreq_cpu_get(0);
-
- if (policy) {
- dprintk(DEBUG_TEMP, "gpu high\n");
- cpufreq_driver_target(policy, policy->cur, CPUFREQ_RELATION_L);
- cpufreq_cpu_put(policy);
- }
- }
- return NOTIFY_OK;
-}
-
-static struct notifier_block rk29_cpufreq_gpu_notifier = {
- .notifier_call = rk29_cpufreq_gpu_notifier_event,
-};
-#endif
-
-#ifdef CONFIG_RK29_CPU_FREQ_LIMIT_BY_DISP
-static void rk29_cpufreq_limit_by_disp_work_func(struct work_struct *work)
-{
- struct cpufreq_policy *policy;
-
- policy = cpufreq_cpu_get(0);
- if (policy) {
- cpufreq_driver_target(policy, policy->cur, CPUFREQ_RELATION_L | CPUFREQ_FORCE_CHANGE);
- cpufreq_cpu_put(policy);
- }
-}
-
-static DECLARE_WORK(rk29_cpufreq_limit_by_disp_work, rk29_cpufreq_limit_by_disp_work_func);
-
-static int rk29_cpufreq_fb_notifier_event(struct notifier_block *this,
- unsigned long event, void *ptr)
-{
- switch (event) {
- case RK29FB_EVENT_HDMI_ON:
- limit_hdmi_enabled = true;
- break;
- case RK29FB_EVENT_HDMI_OFF:
- limit_hdmi_enabled = false;
- break;
- case RK29FB_EVENT_FB1_ON:
- limit_fb1_enabled = true;
- break;
- case RK29FB_EVENT_FB1_OFF:
- limit_fb1_enabled = false;
- break;
- }
-
- dprintk(DEBUG_DISP, "event: %lu aclk_limit: %d\n", event, aclk_limit());
- flush_work(&rk29_cpufreq_limit_by_disp_work);
- queue_work(wq, &rk29_cpufreq_limit_by_disp_work);
-
- return NOTIFY_OK;
-}
-
-static struct notifier_block rk29_cpufreq_fb_notifier = {
- .notifier_call = rk29_cpufreq_fb_notifier_event,
-};
-#endif
-
-static int rk29_cpufreq_init(struct cpufreq_policy *policy)
-{
- if (policy->cpu != 0)
- return -EINVAL;
-
- arm_clk = clk_get(NULL, "arm_pll");
- if (IS_ERR(arm_clk)) {
- int err = PTR_ERR(arm_clk);
- pr_err("fail to get arm_pll clk: %d\n", err);
- arm_clk = NULL;
- return err;
- }
-
- ddr_clk = clk_get(NULL, "ddr");
- if (IS_ERR(ddr_clk)) {
- int err = PTR_ERR(ddr_clk);
- pr_err("fail to get ddr clk: %d\n", err);
- ddr_clk = NULL;
- return err;
- }
- ddr_max_rate = clk_get_rate(ddr_clk);
-
-#ifdef CONFIG_REGULATOR
- vcore = regulator_get(NULL, "vcore");
- if (IS_ERR(vcore)) {
- pr_err("fail to get regulator vcore: %ld\n", PTR_ERR(vcore));
- vcore = NULL;
- }
-#endif
-
- board_update_cpufreq_table(freq_table); /* force update frequency */
- BUG_ON(cpufreq_frequency_table_cpuinfo(policy, freq_table));
- cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
- policy->cur = clk_get_rate(arm_clk) / 1000;
-
- policy->cpuinfo.transition_latency = 40 * NSEC_PER_USEC; // make default sampling_rate to 40000
-
- wq = create_singlethread_workqueue("rk29_cpufreqd");
- if (!wq) {
- pr_err("fail to create workqueue\n");
- return -ENOMEM;
- }
-
-#ifdef CONFIG_RK29_CPU_FREQ_LIMIT_BY_TEMP
- if (rk29_cpufreq_is_ondemand_policy(policy)) {
- dprintk(DEBUG_TEMP, "queue work\n");
- queue_delayed_work(wq, &rk29_cpufreq_limit_by_temp_work, WORK_DELAY);
- }
- cpufreq_register_notifier(¬ifier_policy_block, CPUFREQ_POLICY_NOTIFIER);
- if (limit_max_freq > 1008000) {
- clk_gpu = clk_get(NULL, "gpu");
- clk_vpu = clk_get(NULL, "vpu");
- clk_notifier_register(clk_gpu, &rk29_cpufreq_gpu_notifier);
- clk_notifier_register(clk_vpu, &rk29_cpufreq_vpu_notifier);
- }
-#endif
-#ifdef CONFIG_RK29_CPU_FREQ_LIMIT_BY_DISP
- rk29fb_register_notifier(&rk29_cpufreq_fb_notifier);
-#endif
- return 0;
-}
-
-static int rk29_cpufreq_exit(struct cpufreq_policy *policy)
-{
-#ifdef CONFIG_RK29_CPU_FREQ_LIMIT_BY_DISP
- rk29fb_unregister_notifier(&rk29_cpufreq_fb_notifier);
-#endif
-#ifdef CONFIG_RK29_CPU_FREQ_LIMIT_BY_TEMP
- if (limit_max_freq > 1008000) {
- clk_notifier_unregister(clk_gpu, &rk29_cpufreq_gpu_notifier);
- clk_notifier_unregister(clk_vpu, &rk29_cpufreq_vpu_notifier);
- clk_put(clk_gpu);
- clk_put(clk_vpu);
- }
- cpufreq_unregister_notifier(¬ifier_policy_block, CPUFREQ_POLICY_NOTIFIER);
- if (wq)
- cancel_delayed_work(&rk29_cpufreq_limit_by_temp_work);
-#endif
- if (wq) {
- flush_workqueue(wq);
- destroy_workqueue(wq);
- wq = NULL;
- }
-#ifdef CONFIG_REGULATOR
- if (vcore)
- regulator_put(vcore);
-#endif
- clk_put(ddr_clk);
- clk_put(arm_clk);
- return 0;
-}
-
-static struct freq_attr *rk29_cpufreq_attr[] = {
- &cpufreq_freq_attr_scaling_available_freqs,
- NULL,
-};
-
-static struct cpufreq_driver rk29_cpufreq_driver = {
- .flags = CPUFREQ_STICKY | CPUFREQ_CONST_LOOPS,
- .init = rk29_cpufreq_init,
- .exit = rk29_cpufreq_exit,
- .verify = rk29_cpufreq_verify,
- .target = rk29_cpufreq_target,
- .name = "rk29",
- .attr = rk29_cpufreq_attr,
-};
-
-static int rk29_cpufreq_pm_notifier_event(struct notifier_block *this,
- unsigned long event, void *ptr)
-{
- int ret = NOTIFY_DONE;
- struct cpufreq_policy *policy = cpufreq_cpu_get(0);
-
- if (!policy)
- return ret;
-
- if (!rk29_cpufreq_is_ondemand_policy(policy))
- goto out;
-
- switch (event) {
- case PM_SUSPEND_PREPARE:
- ret = cpufreq_driver_target(policy, limit_avg_freq, DISABLE_FURTHER_CPUFREQ | CPUFREQ_RELATION_H);
- if (ret < 0) {
- ret = NOTIFY_BAD;
- goto out;
- }
- ret = NOTIFY_OK;
- break;
- case PM_POST_RESTORE:
- case PM_POST_SUSPEND:
- cpufreq_driver_target(policy, limit_avg_freq, ENABLE_FURTHER_CPUFREQ | CPUFREQ_RELATION_H);
- ret = NOTIFY_OK;
- break;
- }
-out:
- cpufreq_cpu_put(policy);
- return ret;
-}
-
-static struct notifier_block rk29_cpufreq_pm_notifier = {
- .notifier_call = rk29_cpufreq_pm_notifier_event,
-};
-
-static int rk29_cpufreq_reboot_notifier_event(struct notifier_block *this,
- unsigned long event, void *ptr)
-{
- struct cpufreq_policy *policy = cpufreq_cpu_get(0);
-
- if (policy) {
- cpufreq_driver_target(policy, limit_avg_freq, DISABLE_FURTHER_CPUFREQ | CPUFREQ_RELATION_H);
- cpufreq_cpu_put(policy);
- }
-
- return NOTIFY_OK;
-}
-
-static struct notifier_block rk29_cpufreq_reboot_notifier = {
- .notifier_call = rk29_cpufreq_reboot_notifier_event,
-};
-
-static int __init rk29_cpufreq_register(void)
-{
- register_pm_notifier(&rk29_cpufreq_pm_notifier);
- register_reboot_notifier(&rk29_cpufreq_reboot_notifier);
-
- return cpufreq_register_driver(&rk29_cpufreq_driver);
-}
-
-device_initcall(rk29_cpufreq_register);
-
+++ /dev/null
-/*
- * arch/arm/mach-rk29/ddr.c
- *
- * Function Driver for DDR controller
- *
- * Copyright (C) 2011 Fuzhou Rockchip Electronics Co.,Ltd
- * Author:
- * hcy@rock-chips.com
- * yk@rock-chips.com
- *
- * v2.02
- * reset DRAM DLL at update_mr
- * adjust ZQCR0, MR0,MR1,MR2 for ODT and driver strengh
- *
- * v2.01
- * disable DFTCMP
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/irqflags.h>
-#include <linux/string.h>
-#include <linux/version.h>
-#include <linux/compiler.h>
-#include <linux/platform_device.h>
-#include <linux/time.h>
-#include <linux/hrtimer.h>
-#include <linux/earlysuspend.h>
-#include <linux/random.h>
-#include <linux/crc32.h>
-#include <linux/clk.h>
-
-#include <mach/rk29_iomap.h>
-#include <mach/memory.h>
-#include <mach/sram.h>
-#include <mach/ddr.h>
-
-#include <asm/delay.h>
-#include <asm/tlbflush.h>
-#include <asm/cacheflush.h>
-#include <asm/io.h>
-
-#define DDR_BYPASS_EN 1
-
-#define ddr_print(x...) printk( "DDR DEBUG: " x )
-
-//CCR; //Controller Configuration Register
-#define ECCEN (1)
-#define NOMRWR (1<<1)
-#define HOSTEN (1<<2)
-#define RRB (1<<13)
-#define DQSCFG (1<<14)
-#define DFTLM_NO (0<<15)
-#define DFTLM_90 (1<<15)
-#define DFTLM_180 (2<<15)
-#define DFTLM_270 (3<<15)
-#define DFTCMP (1<<17)
-#define FLUSH (1<<27)
-#define ITMRST (1<<28)
-#define IB (1<<29)
-#define DTT (1<<30)
-#define IT (1<<31)
-//DCR; //DRAM Configuration Register
-#define DDRII (0)
-#define DDR3 (1)
-#define Mobile_DDR (2)
-
-#define DIO_8 (1<<2)
-#define DIO_16 (2<<2)
-#define DIO_32 (3<<2)
-
-#define DSIZE_64Mb (0<<4)
-#define DSIZE_128Mb (1<<4)
-#define DSIZE_256Mb (2<<4)
-#define DSIZE_512Mb (3<<4)
-#define DSIZE_1Gb (4<<4)
-#define DSIZE_2Gb (5<<4)
-#define DSIZE_4Gb (6<<4)
-#define DSIZE_8Gb (7<<4)
-
-#define SIO(n) (((n)-1)<<7)
-#define PIO (1<<10)
-#define RANKS(n) ((((n)-1)&0x3)<<11)
-#define RNKALL (1<<13)
-
-#define AMAP_RBRC (0<<14) //rank,bank,row,column
-#define AMAP_RRBC (1<<14) //rank,row,bank,column
-#define AMAP_BRRC (2<<14) //bank,row,rank,column
-#define AMAP_FIX (3<<14) //Fixed address
-
-#define PDQ(n) (((n)&0x7)<<16)
-#define MPRDQ (1<<19)
-#define MVAR (1<<20)
-#define RDIMM (1<<21)
-#define DO_INIT (1<<24)
-#define EXE_RANK(n) (((n)&3)<<25)
-
-#define CMD_NOP (0<<27)
-#define CMD_ClockStop (1<<27)
-#define CMD_SelfRefresh (2<<27)
-#define CMD_Refresh (3<<27)
-#define CMD_DDR3_Reset (4<<27)
-#define CMD_PrechargeAll (5<<27)
-#define CMD_DeepPowerDown (6<<27)
-#define CMD_SDRAM_Mode_Exit (7<<27)
-#define CMD_SDRAM_ZQ_Calibration_Short (0xB<<27)
-#define CMD_SDRAM_ZQ_Calibration_Long (0xC<<27)
-#define CMD_PowerDown (0xE<<27)
-#define CMD_SDRAM_NOP (0xF<<27)
-
-#define EXE (1<<31)
-
-//IOCR; //IO Configuration Register
-#define DQ_ODT (1)
-#define DQS_ODT (1<<1)
-#define TESTEN (1<<2)
-#define DQ_RTT_DIS (0<<3)
-#define DQ_RTT_150 (1<<3)
-#define DQ_RTT_75 (2<<3)
-#define DQ_RTT_50 (3<<3)
-#define DQS_RTT_DIS (0<<5)
-#define DQS_RTT_150 (1<<5)
-#define DQS_RTT_75 (2<<5)
-#define DQS_RTT_50 (3<<5)
-#define DQ_DS_FULL (1<<7)
-#define DQ_DS_REDUCE (0<<7)
-#define DQS_DS_FULL (1<<8)
-#define DQS_DS_REDUCE (0<<8)
-#define ADD_DS_FULL (1<<9)
-#define ADD_DS_REDUCE (0<<9)
-#define CK_DS_FULL (1<<10)
-#define CK_DS_REDUCE (0<<10)
-
-#define AUTO_CMD_IOPD(n) (((n)&0x3)<<18)
-#define AUTO_DATA_IOPD(n) (((n)&0x3)<<22)
-#define RTTOH(n) (((n)&0x7)<<26)
-#define RTTOE (1<<29)
-#define DQRTT (1<<30)
-#define DQSRTT (1<<31)
-
-//CSR; //Controller Status Register
-#define DFTERR (1<<18)
-#define ECCERR (1<<19)
-#define DTERR (1<<20)
-#define DTIERR (1<<21)
-#define ECCSEC (1<<22)
-#define TQ (1<<23)
-
-//DRR; //DRAM Refresh Register
-#define TRFC(n) ((n)&0xFF)
-#define TRFPRD(n) (((n)&0xFFFF)<<8)
-#define RFBURST(n) ((((n)-1)&0xF)<<24)
-#define RD (1<<31)
-
-//TPR[3]; //SDRAM Timing Parameters Registers
-//TPR0
-#define TMRD(n) ((n)&0x3)
-#define TRTP(n) (((n)&0x7)<<2)
-#define TWTR(n) (((n)&0x7)<<5)
-#define TRP(n) (((n)&0xF)<<8)
-#define TRCD(n) (((n)&0xF)<<12)
-#define TRAS(n) (((n)&0x1F)<<16)
-#define TRRD(n) (((n)&0xF)<<21)
-#define TRC(n) (((n)&0x3F)<<25)
-#define TCCD (1<<31)
-//TPR1
-#define TAOND_2 (0)
-#define TAOND_3 (1)
-#define TAOND_4 (2)
-#define TAOND_5 (3)
-#define TRTW (1<<2)
-#define TFAW(n) (((n)&0x3F)<<3)
-#define TMOD(n) (((n)&0x3)<<9)
-#define TRTODT (1<<11)
-#define TRNKRTR(n) ((((n)-1)&0x3)<<12)
-#define TRNKWTW(n) (((n)&0x3)<<14)
-//TPR2
-#define TXS(n) ((n)&0x3FF)
-#define TXP(n) (((n)&0x1F)<<10)
-#define TCKE(n) (((n)&0xF)<<15)
-
-//DLLCR; //Global DLL Control Register
-//DLLCR09[10]; //DDR Control Register 0-9
-#define DD (1<<31)
-
-//RSLR[4]; //Rank System Latency Register 0-3
-#define SL(n,value) (((value)&0x7)<<((n)*3))
-
-//RDGR[4]; //Rank DQS Gating Register 0-3
-#define DQSSEL(n, value) (((value)&0x3)<<((n)*2))
-
-//DQTR[9]; //DQ Timing Register 0-8
-#define DQDLY_DQS(n, value) (((value)&0x3)<<((n)*4))
-#define DQDLY_DQSb(n, value) (((value)&0x3)<<(((n)*4)+2))
-
-//DQSTR; //DQS Timing Register
-//DQSBTR; //DQS_b Timing Register
-#define DQSDLY(n, value) (((value)&0x7)<<((n)*3))
-
-//ODTCR; //ODT Configuration Register
-#define RDODT(rank, value) (((value)&0xF)<<((rank)*4))
-#define WRODT(rank, value) (((value)&0xF)<<(((rank)*4)+16))
-
-//DTR[2]; //Data Training Register 0-1
-//DTAR; //Data Training Address Register
-#define DTCOL(col) ((col)&0xFFF)
-#define DTROW(row) (((row)&0xFFFF)<<12)
-#define DTBANK(bank) (((bank)&0x7)<<28)
-#define DTMPR (1<<31)
-
-//ZQCR[3]; //SDRAM ZQ Control Register and SDRAM ZQCS Control Register 0-2
-//ZQCR0
-#define ZQDATA(n) ((n)&0xFFFFF)
-#define ZPROG_OUT(n) (((n)&0xF)<<20)
-#define ZPROG_ODT(n) (((n)&0xF)<<24)
-#define ZQDEN (1<<28)
-#define ZQCLK (1<<29)
-#define NOICAL (1<<30)
-#define ZQCAL (1<<31)
-//ZQCR1
-#define ZQ_CALPRD(n) ((n)&0x7FFF)
-#define ZQ_CAL_EN (1<<31)
-//ZQCR2
-#define ZQCS_CALPRD(n) ((n)&0x7FFF)
-#define ZQCS_CAL_EN (1<<31)
-
-//ZQSR; //SDRAM ZQ Status Register
-//TPR3; //SDRAM Timing Parameters Register 3
-#define BL2 (0)
-#define BL4 (1)
-#define BL8 (2)
-#define BL16 (3)
-#define BLOTF_EN (1<<2)
-#define CL(n) (((n)&0xF)<<3)
-#define CWL(n) (((n)&0xF)<<7)
-#define WR(n) (((n)&0xF)<<11)
-#define AL(n) (((n)&0xF)<<15)
-
-//ALPMR; //Automatic Low Power Mode Register
-#define LPPERIOD_CLK_STOP(n) ((n)&0xFF)
-#define LPPERIOD_POWER_DOWN(n) (((n)&0xFF)<<8)
-#define AUTOCS (1<<25)
-#define AUTOPD (1<<26)
-
-//Reserved[0x7c-0x30];
-//MR; //Mode Register
-#define DDR_BL4 (2)
-#define DDR_BL8 (3)
-#define DDR_CL(n) (((n)&0x7)<<4)
-#define DDR2_WR(n) ((((n)-1)&0x7)<<9)
-
-//mr0 for ddr3
-#define DDR3_BL8 (0)
-#define DDR3_BC4_8 (1)
-#define DDR3_BC4 (2)
-#define DDR3_BL(n) (n)
-#define DDR3_CL(n) ((((n-4)&0x7)<<4)|(((n-4)&0x8)>>1))
-#define DDR3_MR0_CL(n) ((((n-4)&0x7)<<4)|(((n-4)&0x8)>>1))
-#define DDR3_MR0_WR(n) (((n)&0x7)<<9)
-#define DDR3_MR0_DLL_RESET (1<<8)
-#define DDR3_MR0_DLL_NOR (0<<8)
-
-//mr1 for ddr3
-#define DDR3_MR1_AL(n) ((n&0x7)<<3)
-#define DDR3_MR1_DIC(n) (((n&1)<<1)|((n&2)<<4))
-#define DDR3_MR1_RTT_NOM(n) (((n&1)<<2)|((n&2)<<5)|((n&4)<<7))
-
-//mr2 for ddr3
-#define DDR3_MR2_RTT_WR(n) ((n&0x3)<<9)
-#define DDR3_MR2_CWL(n) (((n-5)&0x7)<<3)
-
-//EMR; //Extended Mode Register
-#define DDR2_STR_FULL (0)
-#define DDR2_STR_REDUCE (1<<1)
-#define DDR2_AL(n) (((n)&0x7)<<3)
-#define DDR2_ODT_DIS (0)
-#define DDR2_ODT_150 (0x40)
-#define DDR2_ODT_75 (0x4)
-#define DDR2_ODT_50 (0x44)
-
-//EMR2; //Extended Mode Register 2
-//EMR3; //Extended Mode Register 3
-//y Management Unit Registers
-//HPCR[32]; //Host Port Configuration Register 0-31
-#define HPBL(n) ((n)&0xFF)
-#define HCBP (1<<8)
-#define HNPC (1<<9)
-
-//PQCR[8]; //Priority Queue Configuration Register 0-7
-#define TOUT(n) ((n)&0xFF)
-#define TOUT_MUL_1 (0<<8)
-#define TOUT_MUL_16 (1<<8)
-#define TOUT_MUL_64 (2<<8)
-#define TOUT_MUL_256 (3<<8)
-#define LPQS(n) (((n)&0x3)<<10)
-#define PQBL(n) (((n)&0xFF)<<12)
-#define SWAIT(n) (((n)&0x1F)<<20)
-#define INTRPT(n) (((n)&0x7)<<25)
-#define APQS (1<<28)
-
-#define PLL_CLKR(i) ((((i) - 1) & 0x1f) << 10)
-
-#define PLL_CLKF(i) ((((i) - 1) & 0x7f) << 3)
-
-#define PLL_CLKOD(i) (((i) & 0x03) << 1)
-
-//MMGCR; //Memory Manager General Configuration Register
-#define PORT0_NORMAL_PRIO (0)
-#define PORT0_HIGH_PRIO (2)
-
-/* DDR Controller register struct */
-typedef volatile struct DDR_REG_Tag
-{
- volatile unsigned int CCR; //Controller Configuration Register
- volatile unsigned int DCR; //DRAM Configuration Register
- volatile unsigned int IOCR; //IO Configuration Register
- volatile unsigned int CSR; //Controller Status Register
- volatile unsigned int DRR; //DRAM Refresh Register
- volatile unsigned int TPR[3]; //SDRAM Timing Parameters Registers
- volatile unsigned int DLLCR; //Global DLL Control Register
- volatile unsigned int DLLCR09[10]; //DDR Control Register 0-9
- volatile unsigned int RSLR[4]; //Rank System Latency Register 0-3
- volatile unsigned int RDGR[4]; //Rank DQS Gating Register 0-3
- volatile unsigned int DQTR[9]; //DQ Timing Register 0-8
- volatile unsigned int DQSTR; //DQS Timing Register
- volatile unsigned int DQSBTR; //DQS_b Timing Register
- volatile unsigned int ODTCR; //ODT Configuration Register
- volatile unsigned int DTR[2]; //Data Training Register 0-1
- volatile unsigned int DTAR; //Data Training Address Register
- volatile unsigned int ZQCR[3]; //SDRAM ZQ Control Register and SDRAM ZQCS Control Register 0-2
- volatile unsigned int ZQSR; //SDRAM ZQ Status Register
- volatile unsigned int TPR3; //SDRAM Timing Parameters Register 3
- volatile unsigned int ALPMR; //Automatic Low Power Mode Register
- volatile unsigned int Reserved[0x7c-0x30];
- volatile unsigned int MR; //Mode Register
- volatile unsigned int EMR; //Extended Mode Register
- volatile unsigned int EMR2; //Extended Mode Register 2
- volatile unsigned int EMR3; //Extended Mode Register 3
- //Memory Management Unit Registers
- volatile unsigned int HPCR[32]; //Host Port Configuration Register 0-31
- volatile unsigned int PQCR[8]; //Priority Queue Configuration Register 0-7
- volatile unsigned int MMGCR; //Memory Manager General Configuration Register
-}DDR_REG_T, *pDDR_REG_T;
-
-
-
-typedef struct DDR_CONFIG_Tag
-{
- unsigned int row;
- unsigned int bank;
- unsigned int col;
- unsigned int config;
-}DDR_CONFIG_T;
-
-typedef struct tagGPIO_IOMUX
-{
- volatile unsigned int GPIOL_IOMUX;
- volatile unsigned int GPIOH_IOMUX;
-}GPIO_IOMUX_T;
-
-//GRF Registers
-typedef volatile struct tagREG_FILE
-{
- volatile unsigned int GRF_GPIO_DIR[6];
- volatile unsigned int GRF_GPIO_DO[6];
- volatile unsigned int GRF_GPIO_EN[6];
- GPIO_IOMUX_T GRF_GPIO_IOMUX[6];
- volatile unsigned int GRF_GPIO_PULL[7];
- volatile unsigned int GRF_UOC_CON[2];
- volatile unsigned int GRF_USB_CON;
- volatile unsigned int GRF_CPU_CON[2];
- volatile unsigned int GRF_CPU_STATUS;
- volatile unsigned int GRF_MEM_CON;
- volatile unsigned int GRF_MEM_STATUS[3];
- volatile unsigned int GRF_SOC_CON[5];
- volatile unsigned int GRF_OS_REG[4];
-} REG_FILE, *pREG_FILE;
-
-//CRU Registers
-typedef volatile struct tagCRU_REG
-{
- volatile unsigned int CRU_APLL_CON;
- volatile unsigned int CRU_DPLL_CON;
- volatile unsigned int CRU_CPLL_CON;
- volatile unsigned int CRU_PPLL_CON;
- volatile unsigned int CRU_MODE_CON;
- volatile unsigned int CRU_CLKSEL_CON[18];
- volatile unsigned int CRU_CLKGATE_CON[4];
- volatile unsigned int CRU_SOFTRST_CON[3];
-} CRU_REG, *pCRU_REG;
-
-// controller base address
-#define pDDR_Reg ((pDDR_REG_T)RK29_DDRC_BASE)
-#define pGRF_Reg ((pREG_FILE)RK29_GRF_BASE)
-#define pSCU_Reg ((pCRU_REG)RK29_CRU_BASE)
-
-
-// save_sp must be static global variable
-
-static unsigned long save_sp;
-
-
-uint32_t ddrDataTraining[16];
-
-DDR_CONFIG_T ddrConfig[3][10] = {
- //row, bank, col, config
- {
- //DDR2
- // x16
- {15, 8, 10, (DIO_16 | DSIZE_4Gb)},
- {14, 8, 10, (DIO_16 | DSIZE_2Gb)},
- {13, 8, 10, (DIO_16 | DSIZE_1Gb)},
- {13, 4, 10, (DIO_16 | DSIZE_512Mb)},
- {13, 4, 9, (DIO_16 | DSIZE_256Mb)},
- // x8
- {16, 8, 10, (DIO_8 | DSIZE_4Gb)},
- {15, 8, 10, (DIO_8 | DSIZE_2Gb)},
- {14, 8, 10, (DIO_8 | DSIZE_1Gb)},
- {14, 4, 10, (DIO_8 | DSIZE_512Mb)},
- {13, 4, 10, (DIO_8 | DSIZE_256Mb)},
- },
- {
- //DDR3
- // x16
- {16, 8, 10, (DIO_16 | DSIZE_8Gb)},
- {15, 8, 10, (DIO_16 | DSIZE_4Gb)},
- {14, 8, 10, (DIO_16 | DSIZE_2Gb)},
- {13, 8, 10, (DIO_16 | DSIZE_1Gb)},
- {12, 8, 10, (DIO_16 | DSIZE_512Mb)},
- // x8
- {16, 8, 11, (DIO_8 | DSIZE_8Gb)},
- {16, 8, 10, (DIO_8 | DSIZE_4Gb)},
- {15, 8, 10, (DIO_8 | DSIZE_2Gb)},
- {14, 8, 10, (DIO_8 | DSIZE_1Gb)},
- {13, 8, 10, (DIO_8 | DSIZE_512Mb)},
- },
- {
- //mobile DDR
- // x32
- {14, 4, 10, (DIO_32 | DSIZE_2Gb)},
- {13, 4, 10, (DIO_32 | DSIZE_1Gb)},
- {13, 4, 9, (DIO_32 | DSIZE_512Mb)},
- {12, 4, 9, (DIO_32 | DSIZE_256Mb)},
- // x16
- {14, 4, 11, (DIO_16 | DSIZE_2Gb)},
- {14, 4, 10, (DIO_16 | DSIZE_1Gb)},
- {13, 4, 10, (DIO_16 | DSIZE_512Mb)},
- {13, 4, 9, (DIO_16 | DSIZE_256Mb)},
- {12, 4, 9, (DIO_16 | DSIZE_128Mb)},
- {0, 0, 0, 0},
- }
-};
-
-uint32_t __sramdata ddr3_cl_cwl[22][3]={
-/* 0~330 330~400 400~533 speed
-* tCK >3 2.5~3 1.875~2.5
-* cl<<16, cwl cl<<16, cwl cl<<16, cwl */
- {((5<<16)|5), ((5<<16)|5), 0 }, //DDR3_800D
- {((5<<16)|5), ((6<<16)|5), 0 }, //DDR3_800E
-
- {((5<<16)|5), ((5<<16)|5), ((6<<16)|6) }, //DDR3_1066E
- {((5<<16)|5), ((6<<16)|5), ((7<<16)|6) }, //DDR3_1066F
- {((5<<16)|5), ((6<<16)|5), ((8<<16)|6) }, //DDR3_1066G
-
- {((5<<16)|5), ((5<<16)|5), ((6<<16)|6) }, //DDR3_1333F
- {((5<<16)|5), ((5<<16)|5), ((7<<16)|6) }, //DDR3_1333G
- {((5<<16)|5), ((6<<16)|5), ((7<<16)|6) }, //DDR3_1333H
- {((5<<16)|5), ((6<<16)|5), ((8<<16)|6) }, //DDR3_1333J
-
- {((5<<16)|5), ((5<<16)|5), ((6<<16)|6) }, //DDR3_1600G
- {((5<<16)|5), ((5<<16)|5), ((6<<16)|6) }, //DDR3_1600H
- {((5<<16)|5), ((5<<16)|5), ((7<<16)|6) }, //DDR3_1600J
- {((5<<16)|5), ((6<<16)|5), ((7<<16)|6) }, //DDR3_1600K
-
- {((5<<16)|5), ((5<<16)|5), ((6<<16)|6) }, //DDR3_1866J
- {((5<<16)|5), ((5<<16)|5), ((7<<16)|6) }, //DDR3_1866K
- {((6<<16)|5), ((6<<16)|5), ((7<<16)|6) }, //DDR3_1866L
- {((6<<16)|5), ((6<<16)|5), ((8<<16)|6) }, //DDR3_1866M
-
- {((5<<16)|5), ((5<<16)|5), ((6<<16)|6) }, //DDR3_2133K
- {((5<<16)|5), ((5<<16)|5), ((6<<16)|6) }, //DDR3_2133L
- {((5<<16)|5), ((5<<16)|5), ((7<<16)|6) }, //DDR3_2133M
- {((6<<16)|5), ((6<<16)|5), ((7<<16)|6) }, //DDR3_2133N
-
- {((6<<16)|5), ((6<<16)|5), ((8<<16)|6) } //DDR3_DEFAULT
-
-};
-uint32_t __sramdata ddr3_tRC_tFAW[22]={
-/** tRC tFAW */
- ((50<<16)|50), //DDR3_800D
- ((53<<16)|50), //DDR3_800E
-
- ((49<<16)|50), //DDR3_1066E
- ((51<<16)|50), //DDR3_1066F
- ((53<<16)|50), //DDR3_1066G
-
- ((47<<16)|45), //DDR3_1333F
- ((48<<16)|45), //DDR3_1333G
- ((50<<16)|45), //DDR3_1333H
- ((51<<16)|45), //DDR3_1333J
-
- ((45<<16)|40), //DDR3_1600G
- ((47<<16)|40), //DDR3_1600H
- ((48<<16)|40), //DDR3_1600J
- ((49<<16)|40), //DDR3_1600K
-
- ((45<<16)|35), //DDR3_1866J
- ((46<<16)|35), //DDR3_1866K
- ((47<<16)|35), //DDR3_1866L
- ((48<<16)|35), //DDR3_1866M
-
- ((44<<16)|35), //DDR3_2133K
- ((45<<16)|35), //DDR3_2133L
- ((46<<16)|35), //DDR3_2133M
- ((47<<16)|35), //DDR3_2133N
-
- ((53<<16)|50) //DDR3_DEFAULT
-};
-static __sramdata uint32_t mem_type; // 0:DDR2, 1:DDR3, 2:LPDDR
-static __sramdata uint32_t ddr_type; // used for ddr3 only
-static __sramdata uint32_t capability; // one chip cs capability
-
-//DDR2
-static __sramdata uint32_t tRFC;
-static __sramdata uint32_t tRFPRD;
-static __sramdata uint32_t tRTP;
-static __sramdata uint32_t tWTR;
-static __sramdata uint32_t tRAS;
-static __sramdata uint32_t tRRD;
-static __sramdata uint32_t tRC;
-static __sramdata uint32_t tFAW;
-//Mobile-DDR
-static __sramdata uint32_t tXS;
-static __sramdata uint32_t tXP;
-//DDR3
-static __sramdata uint32_t tWR;
-static __sramdata uint32_t tWR_MR0;
-static __sramdata uint32_t cl;
-static __sramdata uint32_t cwl;
-
-static __sramdata uint32_t ddr_freq;
-static __sramdata volatile uint32_t ddr_stop;
-
-
-/****************************************************************************
-Internal sram us delay function
-Cpu highest frequency is 1.2 GHz
-1 cycle = 1/1.2 ns
-1 us = 1000 ns = 1000 * 1.2 cycles = 1200 cycles
-*****************************************************************************/
-static __sramdata uint32_t loops_per_us;
-
-#define LPJ_100MHZ 499728UL
-
-/*static*/ void __sramlocalfunc delayus(uint32_t us)
-{
- uint32_t count;
-
- count = loops_per_us*us;
- while(count--) // 3 cycles
- barrier();
-}
-
-static uint32_t __sramlocalfunc ddr_get_parameter(uint32_t nMHz)
-{
- uint32_t tmp;
- uint32_t tmp1;
- uint32_t ret = 0;
- if(nMHz>533)
- {
- ret = -1;
- goto out;
- }
- if(mem_type == DDR3)
- {
- if(ddr_type > DDR3_DEFAULT){
- ret = -1;
- goto out;
- }
-
- /*
- * tREFI, average periodic refresh interval, 7.8us max
- */
- tRFPRD = ((59*nMHz) >> 3) & 0x3FFF; // 62/8 = 7.75us
-
- if(capability <= 0x4000000) // 512Mb 90ns
- {
- tmp = (90*nMHz+999)/1000;
- }
- else if(capability <= 0x8000000) // 1Gb 110ns
- {
- tmp = (110*nMHz+999)/1000;
- }
- else if(capability <= 0x10000000) // 2Gb 160ns
- {
- tmp = (160*nMHz+999)/1000;
- }
- else if(capability <= 0x20000000) // 4Gb 300ns
- {
- tmp = (300*nMHz+999)/1000;
- }
- else // 8Gb 350ns
- {
- tmp = (350*nMHz+999)/1000;
- }
- /*
- * tRFC DRR[7:0]
- */
- if(tmp > 0xff)
- {
- ret = -3;
- goto out;
- }
- else
- tRFC = tmp;
-
- /*
- * tRTP = max(4nCK,7.5ns), TPR0[4:2], valid values are 2~6
- * tWTR = max(4nCK,7.5ns), TPR0[7:5], valid values are 1~6
- * clock must <533MHz, then tRTP=tWTR=4
- */
- tRTP = 4;
- tWTR = 4;
-
- /*
- * tRAS = 33/37.5~9*tREFI,
- * TPR0[20:16], valid values are 2~31
- */
- tRAS = (38*nMHz+999)/1000;
-
- /*
- * tRRD = max(4nCK, 7.5ns), DDR3-1066(1K), DDR3-1333(2K), DDR3-1600(2K)
- * max(4nCK, 10ns), DDR3-800(1K,2K), DDR3-1066(2K)
- * max(4nCK, 6ns), DDR3-1333(1K), DDR3-1600(1K)
- *
- * TPR0[24:21], valid values are 1~8
- */
- tRRD = (10*nMHz+999)/1000;
-
- /*
- * tRC TPR0[30:25], valid values are 2~42
- */
- tRC = ((ddr3_tRC_tFAW[ddr_type]>>16)*nMHz+999)/1000;
-
- /*
- * tFAW TPR1[8:3], valid values are 2~31
- */
- tFAW = ((ddr3_tRC_tFAW[ddr_type]&0x0ff)*nMHz+999)/1000;
-
- /*
- * tXS TPR2[9:0], valid values are 2~1023
- * MAX(tXS, tXSDLL) for DDR3, tXSDLL = tDLLK = 512CK
- */
- tXS = 512;
-
- /*
- * max(tXP, tXPDLL) for DDR3
- * tXP = max(3nCK, 7.5ns), DDR3-800, DDR3-1066
- * max(3nCK, 6ns), DDR3-1333, DDR3-1600, DDR3-1866, DDR3-2133
- * tXPDLL = max(10nCK, 24ns)
- * TPR2[14:10], valid values are 2~31
- */
- if(nMHz <= 330)
- {
- tmp = 0;
- tXP = 10;
- }
- else if(nMHz<=400)
- {
- tmp = 1;
- tXP = 10;
- }
- else // 533 MHz
- {
- tmp = 2;
- tXP = 13;
- }
-
- /*
- * tWR TPR3[14:11], valid values are 2~12, 15ns
- */
- tWR = (15*nMHz+999)/1000;
- if(tWR<9)
- tWR_MR0 = tWR - 4;
- else
- tWR_MR0 = tWR>>1;
-
- cl = ddr3_cl_cwl[ddr_type][tmp] >> 16;
- cwl = ddr3_cl_cwl[ddr_type][tmp] & 0x0ff;
- if(cl == 0)
- ret = -4;
- }
- else if(mem_type == DDRII)
- {
- /*
- * tREFI, average periodic refresh interval, 7.8us max
- */
- tRFPRD = ((59*nMHz) >> 3) & 0x3FFF; // 62/8 = 7.75us
-
- if(capability <= 0x2000000) // 256Mb
- {
- tmp = (75*nMHz/1000) + ((((75*nMHz)%1000) > 0) ? 1:0);
- }
- else if(capability <= 0x4000000) // 512Mb
- {
- tmp = (105*nMHz/1000) + ((((105*nMHz)%1000) > 0) ? 1:0);
- }
- else if(capability <= 0x8000000) // 1Gb
- {
- tmp = (128*nMHz/1000) + ((((128*nMHz)%1000) > 0) ? 1:0);
- }
- else if(capability <= 0x10000000) // 2Gb
- {
- tmp = (195*nMHz/1000) + ((((195*nMHz)%1000) > 0) ? 1:0);
- }
- else // 4Gb
- {
- tmp = (328*nMHz/1000) + ((((328*nMHz)%1000) > 0) ? 1:0);
- }
- //tRFC = 75ns(256Mb)/105ns(512Mb)/127.5ns(1Gb)/195ns(2Gb)/327.5ns(4Gb)
- tmp = (tmp > 0xFF) ? 0xFF : tmp;
- tRFC = tmp;
- // tRTP = 7.5ns
- tmp = (8*nMHz/1000) + ((((8*nMHz)%1000) > 0) ? 1:0);
- tmp = (tmp > 6) ? 6 : tmp;
- tmp = (tmp < 2) ? 2 : tmp;
- tRTP = tmp;
- //tWTR = 10ns(DDR2-400), 7.5ns (DDR2-533/667/800)
- if(nMHz <= 200)
- {
- tmp = (10*nMHz/1000) + ((((10*nMHz)%1000) > 0) ? 1:0);
- }
- else
- {
- tmp = (8*nMHz/1000) + ((((8*nMHz)%1000) > 0) ? 1:0);
- }
- tmp = (tmp > 6) ? 6 : tmp;
- tmp = (tmp < 1) ? 1 : tmp;
- tWTR = tmp;
- //tRAS_min = 45ns
- tmp = (45*nMHz/1000) + ((((45*nMHz)%1000) > 0) ? 1:0);
- tmp = (tmp > 31) ? 31 : tmp;
- tmp = (tmp < 2) ? 2 : tmp;
- tRAS = tmp;
- // tRRD = 10ns
- tmp = (10*nMHz/1000) + ((((10*nMHz)%1000) > 0) ? 1:0);
- tmp = (tmp > 8) ? 8 : tmp;
- tmp = (tmp < 1) ? 1 : tmp;
- tRRD = tmp;
- if(nMHz <= 200) //tRC = 65ns
- {
- tmp = (65*nMHz/1000) + ((((65*nMHz)%1000) > 0) ? 1:0);
- }
- else //tRC = 60ns
- {
- tmp = (60*nMHz/1000) + ((((60*nMHz)%1000) > 0) ? 1:0);
- }
- tmp = (tmp > 42) ? 42 : tmp;
- tmp = (tmp < 2) ? 2 : tmp;
- tRC = tmp;
- //tFAW = 50ns
- tmp = (50*nMHz/1000) + ((((50*nMHz)%1000) > 0) ? 1:0);
- tmp = (tmp > 31) ? 31 : tmp;
- tmp = (tmp < 2) ? 2 : tmp;
- tFAW = tmp;
- if(nMHz <= 333)
- {
- tXP = 7;
- }
- else
- {
- tXP = 8;
- }
- // don't need to modify tXS, tWR, tWR_MR0, cwl
-
- if(nMHz <= 266)
- {
- cl = 4;
- }
- else if((nMHz > 266) && (nMHz <= 333))
- {
- cl = 5;
- }
- else if((nMHz > 333) && (nMHz <= 400))
- {
- cl = 6;
- }
- else // > 400MHz
- {
- cl = 7;
- }
- cwl = cl -1;
- }
- else
- {
- /*
- * mobile DDR timing USE 3-3-3
- */
-
- /*
- * tREFI, average periodic refresh interval, 7.8us max
- */
- tRFPRD = ((59*nMHz) >> 3) & 0x3FFF; // 62/8 = 7.75us
-
- /*
- *tRFC = 80ns(128Mb,256Mb)
- * 110ns(512Mb)
- * 140ns(1Gb,2Gb)
- */
- if(capability <= 0x2000000) // 256Mb
- {
- tmp = (80*nMHz/1000) + ((((80*nMHz)%1000) > 0) ? 1:0);
- }
- else if(capability <= 0x4000000) // 512Mb
- {
- tmp = (110*nMHz/1000) + ((((110*nMHz)%1000) > 0) ? 1:0);
- }
- else // 1Gb,2Gb
- {
- tmp = (140*nMHz/1000) + ((((140*nMHz)%1000) > 0) ? 1:0);
- }
- tmp = (tmp > 0xFF) ? 0xFF : tmp;
- tRFC = tmp;
- /*
- * tWTR = 1 tCK(100MHz,133MHz)
- * 2 tCK(166MHz,185MHz)
- */
- if(nMHz < 133)
- {
- tWTR = 1;
- }
- else
- {
- tWTR = 2;
- }
- /*
- * tRAS = 50ns(100MHz)
- * 45ns(133MHz)
- * 42ns(166MHz)
- * 42ns(185MHz)
- * 40ns(200MHz)
- */
- if(nMHz<100)
- {
- tmp = (50*nMHz/1000) + ((((50*nMHz)%1000) > 0) ? 1:0);
- }
- else if(nMHz<133)
- {
- tmp = (45*nMHz/1000) + ((((45*nMHz)%1000) > 0) ? 1:0);
- }
- else if(nMHz<185)
- {
- tmp = (42*nMHz/1000) + ((((42*nMHz)%1000) > 0) ? 1:0);
- }
- else
- {
- tmp = (40*nMHz/1000) + ((((40*nMHz)%1000) > 0) ? 1:0);
- }
- tmp1 = tmp;
- tmp = (tmp > 31) ? 31 : tmp;
- tmp = (tmp < 2) ? 2 : tmp;
- tRAS = tmp;
- /*
- * tRC = tRAS + tRP
- */
- tmp1 += 3;
- tmp1 = (tmp1 > 42) ? 42 : tmp1;
- tmp1 = (tmp1 < 2) ? 2 : tmp1;
- tRC = tmp1;
- /*
- * tRRD = 15ns(100MHz)
- * 15ns(133MHz)
- * 12ns(166MHz)
- * 10.8ns(185MHz)
- * 10ns(200MHz)
- */
- if(nMHz<133)
- {
- tmp = (15*nMHz/1000) + ((((15*nMHz)%1000) > 0) ? 1:0);
- }
- else if(nMHz<166)
- {
- tmp = (12*nMHz/1000) + ((((12*nMHz)%1000) > 0) ? 1:0);
- }
- else if(nMHz<185)
- {
- tmp = (11*nMHz/1000) + ((((11*nMHz)%1000) > 0) ? 1:0);
- }
- else
- {
- tmp = (10*nMHz/1000) + ((((10*nMHz)%1000) > 0) ? 1:0);
- }
- tmp = (tmp > 8) ? 8 : tmp;
- tmp = (tmp < 1) ? 1 : tmp;
- tRRD = tmp;
- /*
- * tXS = tXSR = 200ns
- */
- tmp = (200*nMHz/1000) + ((((200*nMHz)%1000) > 0) ? 1:0);
- tmp = (tmp > 0x3FF) ? 0x3FF : tmp;
- tmp = (tmp < 2) ? 2 : tmp;
- tXS = tmp;
- /*
- * tXP = 25ns
- */
- tmp = (25*nMHz/1000) + ((((25*nMHz)%1000) > 0) ? 1:0);
- tmp = (tmp > 0x1F) ? 0x1F : tmp;
- tmp = (tmp < 2) ? 2 : tmp;
- tXP = tmp;
-
- /*
- * mobile DDR CL always = 3
- */
- cl = 3;
- }
-out:
- return ret;
-}
-static uint32_t __sramlocalfunc ddr_update_timing(void)
-{
- uint32_t value;
-
- pDDR_Reg->DRR = TRFC(tRFC) | TRFPRD(tRFPRD) | RFBURST(1);
- if(mem_type == DDR3)
- {
- value = pDDR_Reg->TPR[0];
- value &= ~((0x7<<2)|(0x7<<5)|(0x1F<<16)|(0xF<<21)|(0x3F<<25));
- pDDR_Reg->TPR[0] = value | TRTP(tRTP) | TWTR(tWTR) | TRAS(tRAS) | TRRD(tRRD) | TRC(tRC);
- value = pDDR_Reg->TPR[1];
- value &= ~(0x3F<<3);
- pDDR_Reg->TPR[1] = value | TFAW(tFAW);
- // ddr3 tCKE should be tCKESR=tCKE+1nCK
- pDDR_Reg->TPR[2] = TXS(tXS) | TXP(tXP) | TCKE(4);//0x198c8;//
- pDDR_Reg->ZQCR[0] = 0x10039d29;//(pDDR_Reg->ZQSR & (0x3FF)) | (0x6<<10) | (0x6<<15) | (0x1<<28);
- }
- else if(mem_type == DDRII)
- {
- value = pDDR_Reg->TPR[0];
- value &= ~((0x7<<2)|(0x7<<5)|(0x1F<<16)|(0xF<<21)|(0x3F<<25));
- pDDR_Reg->TPR[0] = value | TRTP(tRTP) | TWTR(tWTR) | TRAS(tRAS) | TRRD(tRRD) | TRC(tRC);
- value = pDDR_Reg->TPR[1];
- value &= ~(0x3F<<3);
- pDDR_Reg->TPR[1] = value | TFAW(tFAW);
- value = pDDR_Reg->TPR[2];
- value &= ~(0x1F<<10);
- pDDR_Reg->TPR[2] = value | TXP(tXP);
- }
- else
- {
- /*
- * mobile DDR timing USE 3-3-3
- */
- value = pDDR_Reg->TPR[0];
- value &= ~((0x7<<2)|(0x7<<5)|(0x1F<<16)|(0xF<<21)|(0x3F<<25));
- pDDR_Reg->TPR[0] = value | TRTP(2) | TWTR(tWTR) | TRAS(tRAS) | TRRD(tRRD) | TRC(tRC);
- pDDR_Reg->TPR[2] = TXS(tXS) | TXP(tXP) | TCKE(2);
- }
- return 0;
-}
-
-static uint32_t __sramlocalfunc ddr_update_mr(void)
-{
- uint32_t value;
- value = pDDR_Reg->TPR[0];
- value &= ~(0x0FF<<8);
- pDDR_Reg->TPR[0] = value | TRP(cl) | TRCD(cl);
- value = pDDR_Reg->TPR3;
- value &= ~((0xF<<3)|(0xF<<7)|(0xF<<11));
-
- if(mem_type == DDR3)
- {
- pDDR_Reg->TPR3 = value | CL(cl) | CWL(cwl) | WR(tWR);
- pDDR_Reg->MR = DDR3_BL8 | DDR3_CL(cl) | DDR3_MR0_DLL_RESET | DDR3_MR0_WR(tWR_MR0)/*15 ns*/;
- delayus(1);
- pDDR_Reg->MR = DDR3_BL8 | DDR3_CL(cl) | DDR3_MR0_WR(tWR_MR0)/*15 ns*/;
- delayus(1);
- /*
- * DIC:Output Driver Impedance Control,0, RZQ(240)/6
- * Rtt_Nom:2 RZQ(240)/2
- */
- pDDR_Reg->EMR = DDR3_MR1_DIC(0) | DDR3_MR1_AL(0) | DDR3_MR1_RTT_NOM(2);
- delayus(1);
- /* DDR3 :CWL=5
- * RTT_WR: 1, RZQ(240)/4
- */
- pDDR_Reg->EMR2 = DDR3_MR2_RTT_WR(1)|DDR3_MR2_CWL(cwl);
- delayus(1);
- pDDR_Reg->EMR3 = 0x0;
- }
- else if(mem_type == DDRII)
- {
- pDDR_Reg->TPR3 = value | CL(cl) | CWL(cwl) | WR(cl);
- //set mode register cl
- value = pDDR_Reg->MR;
- value &= ~((0x7<<4)|(0x7<<9));
- pDDR_Reg->MR = value | DDR_CL(cl) | DDR2_WR(cl);
- }
- else
- {
- /*
- * mobile DDR CL always = 3
- */
- }
- return 0;
-}
-static __sramdata uint32_t clkr;
-static __sramdata uint32_t clkf;
-static __sramdata uint32_t clkod;
-static __sramdata uint32_t pllband = 0;
-static uint32_t __sramlocalfunc ddr_set_pll(uint32_t nMHz, uint32_t set)
-{
- uint32_t ret = 0;
- uint32_t temp;
-
- if(nMHz == 24)
- {
- ret = 24;
- goto out;
- }
-
- if(!set)
- {
- pllband = 0;
- if (nMHz<38)
- {
- nMHz = 38;
- clkr = 1;
- clkod = 3;
- }
- else if(nMHz <= 75 )
- {
- clkr = 1;
- clkod = 3;
- }
- else if (nMHz <= 150)
- {
- clkr = 2;
- clkod = 2;
- }
- else if(nMHz <= 500)
- {
- clkr = 2;
- clkod = 1;
- }
- else
- {
- clkr = 2;
- clkod = 0;
- }
- pllband = (0x01u<<16);
- temp = nMHz*clkr*(1<<clkod);
- clkf = temp/24;
- //if(temp%24)
- // clkf += 1;
- ret = ((24*clkf)>>(clkr-1))>>clkod;
- }
- else
- {
- // ddr slow
- pSCU_Reg->CRU_MODE_CON &=~(0x3<<6);
-
- pSCU_Reg->CRU_DPLL_CON |= (0x1 << 15); //power down pll
- delayus(1); //delay at least 500ns
- pSCU_Reg->CRU_DPLL_CON = pllband | (0x1<<15) |(PLL_CLKR(clkr))|(PLL_CLKF(clkf))|(PLL_CLKOD(clkod));
-
- delayus(1); //delay at least 500ns
- pSCU_Reg->CRU_DPLL_CON &= ~(0x1<<15);
- delayus(500); // wait for DPLL stable
-
- // ddr pll normal
- pSCU_Reg->CRU_MODE_CON |= 0x1<<6;
-
- // ddr_pll_clk: clk_ddr=1:1
- temp = pSCU_Reg->CRU_CLKSEL_CON[7];
- temp &= ~(0x1F<<24);
- pSCU_Reg->CRU_CLKSEL_CON[7] = temp;
- delayus(1);
- }
-out:
- return ret;
-}
-
-
-void __sramlocalfunc ddr_selfrefresh_enter(void)
-{
- /* 1. disables all host ports
- 2. Flushes the MCTL pipelines (including current automatically-scheduled refreshes)
- 3. Disables automatic scheduling of refreshes
- 4. Issues a Precharge All command
- 5. Waits for tRP clocks (programmable in TPR0 register)
- 6. Issues a Self-Refresh command
- 7. Clears the self-clearing bit DCR.EXE and waits for Mode Exit command
- */
- pDDR_Reg->ALPMR &= ~(AUTOPD);
- pDDR_Reg->CCR &= ~HOSTEN; //disable host port
- pDDR_Reg->CCR |= FLUSH; //flush
- delayus(1);
- pDDR_Reg->DCR = (pDDR_Reg->DCR & (~((0x1<<24) | (0x1<<13) | (0xF<<27) | (0x1<<31)))) | ((0x1<<13) | (0x2<<27) | (0x1<<31)); //enter Self Refresh
- //delayus(10);
- do
- {
- delayus(1);
- }while(pDDR_Reg->DCR & (EXE));
-
- pDDR_Reg->ZQCR[0] = (0x1<<28)|(0x1<<15) | (0x1<<10) | (0x1<<5) | 0x1;
-
- pDDR_Reg->CCR |= ITMRST; //ITM reset
- pSCU_Reg->CRU_SOFTRST_CON[0] |= (0x1F<<19); //reset DLL
- delayus(1);
- pSCU_Reg->CRU_CLKGATE_CON[0] |= (0x1<<18); //close DDR PHY clock
- delayus(1);
- pDDR_Reg->DLLCR09[0] =0x80000000;
- pDDR_Reg->DLLCR09[9] =0x80000000;
- pDDR_Reg->DLLCR09[1] =0x80000000;
- pDDR_Reg->DLLCR09[2] =0x80000000;
- pDDR_Reg->DLLCR09[3] =0x80000000;
- dsb();
-}
-void __sramlocalfunc ddr_selfrefresh_exit(void)
-{
- /* 1. Exits self-refresh when a Mode-Exit command is received
- 2. Waits for tXS clocks (programmable in TPR2 register)
- 3. Issues a Refresh command
- 4. Waits for tRFC clocks (programmable in DRR)
- 5. Clears the self-clearing bit DCR.EXE
- 6. Re-enables all host ports
- */
- pSCU_Reg->CRU_CLKGATE_CON[0] &= ~(0x1<<18); //open DDR PHY clock
- delayus(1);
- pSCU_Reg->CRU_SOFTRST_CON[0] &= ~(0x1F<<19); //de-reset DLL
- delayus(10);
- pDDR_Reg->CCR &= ~ITMRST; //ITM reset
- delayus(5);
-
- pDDR_Reg->ZQCR[0] = 0x10039d29;
-
- pDDR_Reg->DCR = (pDDR_Reg->DCR & (~((0x1<<24) | (0x1<<13) | (0xF<<27) | (0x1<<31)))) | ((0x1<<13) | (0x7<<27) | (0x1<<31)); //exit
- delayus(10);
- ddr_update_mr();
- delayus(1);
-
-refresh:
- pDDR_Reg->CSR = 0x0;
- pDDR_Reg->DRR |= RD;
- delayus(1);
- pDDR_Reg->CCR |= DTT;
- dsb();
- delayus(10);
- do
- {
- delayus(1);
- }while(pGRF_Reg->GRF_MEM_STATUS[2] & 0x1); //wait init ok
-
- if(pDDR_Reg->CSR & 0x100000)
- {
- pDDR_Reg->CSR &= ~0x100000;
- goto refresh;
- }
- pDDR_Reg->DRR = TRFC(tRFC) | TRFPRD(tRFPRD) | RFBURST(8);
- delayus(10);
- pDDR_Reg->DRR = TRFC(tRFC) | TRFPRD(tRFPRD) | RFBURST(1);
- delayus(1);
- pDDR_Reg->ALPMR |= AUTOPD;
- pDDR_Reg->CCR |= FLUSH; //flush
- delayus(1);
- pDDR_Reg->CCR |= HOSTEN; //enable host port
-}
-
-uint32_t __sramfunc ddr_change_freq(uint32_t nMHz)
-{
- uint32_t ret;
- volatile u32 n;
- unsigned long flags;
- volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
- uint32_t regvalue = pSCU_Reg->CRU_APLL_CON;
- uint32_t freq;
-
- // freq = (Fin/NR)*NF/OD
- if((pSCU_Reg->CRU_MODE_CON&3) == 1) // CPLL Normal mode
- freq = 24 *((((regvalue>>3)&0x7f)+1)<<1) // NF = 2*(CLKF+1)
- /(((regvalue>>10)&0x1f)+1) // NR = CLKR+1
- *(2<<((regvalue>>1)&3)); // OD = 2^CLKOD
- else
- freq = 24;
-
- loops_per_us = LPJ_100MHZ*freq / 1000000;
-
- ret = ddr_set_pll(nMHz, 0);
- ddr_get_parameter(ret);
- /** 1. Make sure there is no host access */
- local_irq_save(flags);
- flush_cache_all();
- __cpuc_flush_kern_all();
- __cpuc_flush_user_all();
- local_flush_tlb_all();
- DDR_SAVE_SP(save_sp);
- n=temp[0];
- barrier();
- n=temp[1024];
- barrier();
- n=temp[1024*2];
- barrier();
- n=temp[1024*3];
- barrier();
- n= pDDR_Reg->CCR;
- n= pSCU_Reg->CRU_SOFTRST_CON[0];
- dsb();
-
- /** 2. ddr enter self-refresh mode or precharge power-down mode */
- ddr_selfrefresh_enter();
- delayus(10);
- /** 3. change frequence */
- ddr_set_pll(ret, 1);
- ddr_freq = ret;
- #if DDR_BYPASS_EN
- if(nMHz<100)
- {
- pDDR_Reg->DLLCR09[0] |= (0x1<<31);
- pDDR_Reg->DLLCR09[1] |= (0x1<<31);
- pDDR_Reg->DLLCR09[2] |= (0x1<<31);
- pDDR_Reg->DLLCR09[3] |= (0x1<<31);
- pDDR_Reg->DLLCR09[9] |= (0x1<<31);
- pDDR_Reg->DLLCR &= ~(0x1<<23);
- }
- else if(nMHz<=200)
- {
- pDDR_Reg->DLLCR09[0] |= (0x1<<31);
- pDDR_Reg->DLLCR09[1] |= (0x1<<31);
- pDDR_Reg->DLLCR09[2] |= (0x1<<31);
- pDDR_Reg->DLLCR09[3] |= (0x1<<31);
- pDDR_Reg->DLLCR09[9] |= (0x1<<31);
- pDDR_Reg->DLLCR |= (0x1<<23);
- }
- else
- {
- pDDR_Reg->DLLCR09[0] &= ~(0x1<<31);
- pDDR_Reg->DLLCR09[1] &= ~(0x1<<31);
- pDDR_Reg->DLLCR09[2] &= ~(0x1<<31);
- pDDR_Reg->DLLCR09[3] &= ~(0x1<<31);
- pDDR_Reg->DLLCR09[9] &= ~(0x1<<31);
- pDDR_Reg->DLLCR &= ~(0x1<<23);
- }
- #else
- pDDR_Reg->DLLCR09[0] &= ~(0x1<<31);
- pDDR_Reg->DLLCR09[1] &= ~(0x1<<31);
- pDDR_Reg->DLLCR09[2] &= ~(0x1<<31);
- pDDR_Reg->DLLCR09[3] &= ~(0x1<<31);
- pDDR_Reg->DLLCR09[9] &= ~(0x1<<31);
- pDDR_Reg->DLLCR &= ~(0x1<<23);
- #endif
-
- /** 4. update timing¶meter */
- ddr_update_timing();
-
- /** 5. Issues a Mode Exit command */
- ddr_selfrefresh_exit();
- dsb();
- DDR_RESTORE_SP(save_sp);
- local_irq_restore(flags);
- clk_set_rate(clk_get(NULL, "ddr_pll"), 0);
- return ret;
-}
-EXPORT_SYMBOL(ddr_change_freq);
-
-void __sramfunc ddr_suspend(void)
-{
- uint32_t n;
- volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
- uint32_t regvalue = pSCU_Reg->CRU_APLL_CON;
- uint32_t freq;
-
- // freq = (Fin/NR)*NF/OD
- if((pSCU_Reg->CRU_MODE_CON&3) == 1) // CPLL Normal mode
- freq = 24 *((((regvalue>>3)&0x7f)+1)<<1) // NF = 2*(CLKF+1)
- /(((regvalue>>10)&0x1f)+1) // NR = CLKR+1
- *(2<<((regvalue>>1)&3)); // OD = 2^CLKOD
- else
- freq = 24;
-
- loops_per_us = LPJ_100MHZ*freq / 1000000;
-
- /** 1. Make sure there is no host access */
- flush_cache_all();
- __cpuc_flush_kern_all();
- __cpuc_flush_user_all();
-
- n=temp[0];
- barrier();
- n=temp[1024];
- barrier();
- n=temp[1024*2];
- barrier();
- n=temp[1024*3];
- barrier();
- n= pDDR_Reg->CCR;
- n= pGRF_Reg->GRF_MEM_STATUS[2];
- n= pSCU_Reg->CRU_SOFTRST_CON[0];
- dsb();
-
- ddr_selfrefresh_enter();
-
- pSCU_Reg->CRU_CLKGATE_CON[3] |= (0x1<<16) //close DDR GPU AXI clock
- | (0x1<<13) //close DDR VDPU AXI clock
- | (0x1<<11) //close DDR VEPU AXI clock
- | (0x1<<1); //close DDR LCDC AXI clock
- pSCU_Reg->CRU_CLKGATE_CON[1] |= (0x1<<6); //close DDR PERIPH AXI clock
- pSCU_Reg->CRU_CLKGATE_CON[0] |= (0x1<<18); //close DDR PHY clock
-
- delayus(1);
- // ddr slow
- pSCU_Reg->CRU_MODE_CON &=~(0x3<<6);
- delayus(1);
- pSCU_Reg->CRU_DPLL_CON |= (0x1 << 15); //power down DPLL
- delayus(1); //delay at least 500ns
-
- #if DDR_BYPASS_EN
- pDDR_Reg->DLLCR09[0] |= (0x1<<31);
- pDDR_Reg->DLLCR09[1] |= (0x1<<31);
- pDDR_Reg->DLLCR09[2] |= (0x1<<31);
- pDDR_Reg->DLLCR09[3] |= (0x1<<31);
- pDDR_Reg->DLLCR09[9] |= (0x1<<31);
- pDDR_Reg->DLLCR &= ~(0x1<<23);
- #endif
-
-}
-EXPORT_SYMBOL(ddr_suspend);
-
-void __sramfunc ddr_resume(void)
-{
- uint32_t value;
-
- #if DDR_BYPASS_EN
- if(ddr_freq<100)
- {
- pDDR_Reg->DLLCR09[0] |= (0x1<<31);
- pDDR_Reg->DLLCR09[1] |= (0x1<<31);
- pDDR_Reg->DLLCR09[2] |= (0x1<<31);
- pDDR_Reg->DLLCR09[3] |= (0x1<<31);
- pDDR_Reg->DLLCR09[9] |= (0x1<<31);
- pDDR_Reg->DLLCR &= ~(0x1<<23);
- }
- else if(ddr_freq<=200)
- {
- pDDR_Reg->DLLCR09[0] |= (0x1<<31);
- pDDR_Reg->DLLCR09[1] |= (0x1<<31);
- pDDR_Reg->DLLCR09[2] |= (0x1<<31);
- pDDR_Reg->DLLCR09[3] |= (0x1<<31);
- pDDR_Reg->DLLCR09[9] |= (0x1<<31);
- pDDR_Reg->DLLCR |= (0x1<<23);
- }
- else
- {
- pDDR_Reg->DLLCR09[0] &= ~(0x1<<31);
- pDDR_Reg->DLLCR09[1] &= ~(0x1<<31);
- pDDR_Reg->DLLCR09[2] &= ~(0x1<<31);
- pDDR_Reg->DLLCR09[3] &= ~(0x1<<31);
- pDDR_Reg->DLLCR09[9] &= ~(0x1<<31);
- pDDR_Reg->DLLCR &= ~(0x1<<23);
- }
- delayus(1);
- #endif
-
- pSCU_Reg->CRU_DPLL_CON &= ~(0x1 << 15); //power on DPLL
- delayus(300); // Ëø¶¨pll
- do
- {
- delayus(3);
- }while(!(pGRF_Reg->GRF_SOC_CON[0] & (1<<28))); //wait pll lock
- // ddr pll normal
- value = pSCU_Reg->CRU_MODE_CON;
- value &=~(0x3<<6);
- value |= 0x1<<6;
- pSCU_Reg->CRU_MODE_CON = value;
- delayus(1);
- pSCU_Reg->CRU_CLKGATE_CON[3] &= ~((0x1<<16) //close DDR GPU AXI clock
- | (0x1<<13) //close DDR VDPU AXI clock
- | (0x1<<11) //close DDR VEPU AXI clock
- | (0x1<<1)); //close DDR LCDC AXI clock
- pSCU_Reg->CRU_CLKGATE_CON[1] &= ~(0x1<<6); //close DDR PERIPH AXI clock
- pSCU_Reg->CRU_CLKGATE_CON[0] &= ~(0x1<<18); //enable DDR PHY clock
- delayus(1);
-
- ddr_selfrefresh_exit();
- dsb();
-}
-EXPORT_SYMBOL(ddr_resume);
-
-static void inline ddr_change_host_priority(void)
-{
- /*
- DMC AXI host N priority
- 00:higheset priority
- 01:second high priority
- 10:third high priority
-
- GRF_MEM_CON[1:0]: CPU (host 0)
- [3:2]: PERI (host 1)
- [5:4]: DISPLAY (host 2)
- [7:6]: GPU (host 3)
- [9:8]: VCODEC (host 4)
- */
- if(mem_type == Mobile_DDR)
- pGRF_Reg->GRF_MEM_CON = (pGRF_Reg->GRF_MEM_CON & ~0x3FF) | ((2<<0)|(2<<2)|(0<<4)|(2<<6)|(2<<8));
- else
- pGRF_Reg->GRF_MEM_CON = (pGRF_Reg->GRF_MEM_CON & ~0x3FF) | ((2<<0)|(1<<2)|(0<<4)|(1<<6)|(2<<8));
-}
-
-typedef struct _dtt_cnt_t
-{
- uint32_t value;
- uint32_t time;
- uint32_t cnt;
-}dtt_cnt_t;
-
-int ddr_init(uint32_t dram_type, uint32_t freq)
-{
- volatile uint32_t value = 0;
- uint32_t addr;
- uint32_t bw;
- uint32_t col = 0;
- uint32_t row = 0;
- uint32_t bank = 0;
- uint32_t n;
-
- ddr_print("version 2.03 20120519 \n");
-
- mem_type = (pDDR_Reg->DCR & 0x3);
- ddr_type = dram_type;//DDR3_TYPE;//
- ddr_stop = 1;
-
- // caculate aglined physical address
- addr = __pa((unsigned long)ddrDataTraining);
- if(addr&0x1F)
- {
- addr += (32-(addr&0x1F));
- }
- addr -= 0x60000000;
- // caculate data width
- bw = ((((pDDR_Reg->DCR >> 7) & 0x7)+1)>>1);
- // find out col£¬row£¬bank
- for(n=0;n<10; n++)
- {
- if(ddrConfig[(pDDR_Reg->DCR & 0x3)][n].config == (pDDR_Reg->DCR & 0x7c))
- {
- col = ddrConfig[(pDDR_Reg->DCR & 0x3)][n].col;
- row = ddrConfig[(pDDR_Reg->DCR & 0x3)][n].row;
- bank = ddrConfig[(pDDR_Reg->DCR & 0x3)][n].bank;
- bank >>= 2; // 8=>3, 4=>2
- bank += 1;
- break;
- }
- }
- if(n == 10)
- {
- //ASSERT
- }
-
- // according different address mapping, caculate DTAR register value
- value = pDDR_Reg->DTAR;
- value &= ~(0x7FFFFFFF);
- switch(pDDR_Reg->DCR & (0x3<<14))
- {
- case AMAP_RBRC:
- value |= (addr>>bw) & ((0x1<<col)-1); // col
- value |= ((addr>>(bw+col)) & ((0x1<<row)-1)) << 12; // row
- value |= ((addr>>(bw+col+row)) & ((0x1<<bank)-1)) << 28; // bank
- break;
- case AMAP_RRBC:
- value |= (addr>>bw) & ((0x1<<col)-1); // col
- value |= ((addr>>(bw+col+bank)) & ((0x1<<row)-1)) << 12; // row
- value |= ((addr>>(bw+col)) & ((0x1<<bank)-1)) << 28; // bank
- break;
- case AMAP_BRRC:
- value |= (addr>>bw) & ((0x1<<col)-1); // col
- if((pDDR_Reg->DCR >> 11) & 0x3)
- {
- value |= ((addr>>(bw+col+1)) & ((0x1<<row)-1)) << 12; // row
- value |= ((addr>>(bw+col+row+1)) & ((0x1<<bank)-1)) << 28; // bank
- }
- else
- {
- value |= ((addr>>(bw+col)) & ((0x1<<row)-1)) << 12; // row
- value |= ((addr>>(bw+col+row)) & ((0x1<<bank)-1)) << 28; // bank
- }
- break;
- case AMAP_FIX: // can not support AMAP_FIX mode
- default:
- break;
- }
- pDDR_Reg->DTAR = value;
- pDDR_Reg->CCR &= ~(DFTCMP);
- pDDR_Reg->IOCR = AUTO_CMD_IOPD(3) | AUTO_DATA_IOPD(3) | DQ_ODT | DQS_ODT | DQRTT | DQSRTT;
-
- //pDDR_Reg->CCR |= DQSCFG;// passive windowing mode
-
- if((mem_type == DDRII) || (mem_type == DDR3))
- {
- pDDR_Reg->ALPMR = LPPERIOD_POWER_DOWN(0xFF) | AUTOPD;
- }
- else
- {
- pDDR_Reg->ALPMR = LPPERIOD_CLK_STOP(0xFF) | LPPERIOD_POWER_DOWN(0xFF) | AUTOCS | AUTOPD;
- }
- ddr_change_host_priority();
- //get capability per chip, not total size, used for calculate tRFC
- capability = 0x800000 << ((pDDR_Reg->DCR >> 4) & 0x7);
- value = ((((pDDR_Reg->DCR >> 7) & 0x7)+1) >> ((pDDR_Reg->DCR >> 2) & 0x3))+((pDDR_Reg->DCR >> 11) & 0x3);
- if(mem_type == DDR3)
- {
- ddr_print("DDR3 Device\n");
- }
- else if(mem_type == DDRII)
- {
- ddr_print("DDR2 Device\n");
- }
- else
- {
- ddr_print("LPDDR Device\n");
- }
- ddr_print("%d CS, ROW=%d, Bank=%d, COL=%d, Total Capability=%dMB\n",
- (((pDDR_Reg->DCR >> 11) & 0x3) + 1), \
- row, (0x1<<bank), col, \
- ((capability<<value)>>20));
-
-
- value = ddr_change_freq(freq);//DDR_FREQ
- ddr_print("init success!!! freq=%dMHz\n", value);
- ddr_print("CSR:0x%x, RSLR0:0x%x, RSLR1:0x%x, RDGR0:0x%x, RDGR1:0x%x\n",
- pDDR_Reg->CSR,
- pDDR_Reg->RSLR[0], pDDR_Reg->RSLR[1],
- pDDR_Reg->RDGR[0], pDDR_Reg->RDGR[1]);
- return 0;
-}
-EXPORT_SYMBOL(ddr_init);
-
-#ifdef CONFIG_DDR_RECONFIG
-#include "ddr_reconfig.c"
-#endif
+++ /dev/null
-static __sramdata uint32_t ddrreg[0x40];
-extern void local_flush_tlb_all(void);
-#if 1
-unsigned int __sramlocalfunc ddr_datatraining(int nMHz)
-{
- pDDR_Reg->CSR =0x0;
- pDDR_Reg->DRR |= RD;
- delayus(1);
- pDDR_Reg->CCR |= DTT;
- dsb();
- do{
- delayus(1);
- }while(pGRF_Reg->GRF_MEM_STATUS[2] &0x1);
-
- if(pDDR_Reg->CSR & 0x100000)
- while(1);
- pDDR_Reg->DRR &= ~RD;
- return 0;
-
-}
-
-void __sramlocalfunc ddrReg_Save(void)
-{
- int i=0;
-// pDDR_REG_T pDDR_Reg=((pDDR_REG_T)RK29_DDRC_BASE);
- for(i =0; i<0x30; i++)
- ddrreg[i] =*(unsigned long volatile *)(RK29_DDRC_BASE +i*4);
- ddrreg[3] =0;
- ddrreg[i++] =*(unsigned long volatile *)(RK29_DDRC_BASE +0x7c*4); //pDDR_Reg->MR;
- ddrreg[i++] =*(unsigned long volatile *)(RK29_DDRC_BASE +0x7d*4);
- ddrreg[i++] =*(unsigned long volatile *)(RK29_DDRC_BASE +0x7e*4);
- ddrreg[i++] =*(unsigned long volatile *)(RK29_DDRC_BASE +0x7f*4);
- //rest reg did not saved yet
-}
-void __sramlocalfunc ddrReg_Restore(void)
-{
- int i=0;
-// pDDR_REG_T pDDR_Reg=((pDDR_REG_T)RK29_DDRC_BASE);
- for(i =0; i<0x30; i++)
- *(unsigned long volatile *)(RK29_DDRC_BASE +i*4) =ddrreg[i];
- *(unsigned long volatile *)(RK29_DDRC_BASE +0x7c*4) =ddrreg[i++];
- *(unsigned long volatile *)(RK29_DDRC_BASE +0x7d*4) =ddrreg[i++];
- *(unsigned long volatile *)(RK29_DDRC_BASE +0x7e*4) =ddrreg[i++];
- *(unsigned long volatile *)(RK29_DDRC_BASE +0x7f*4) =ddrreg[i++];
- //rest reg did not saved yet
-}
-void __sramlocalfunc Delay10cyc(int count)
-{
- volatile int i;
-
- while(count--)
- {
- for (i=0; i<8; i++); //12*8+8=104cyc
- }
-}
-#define RECONFIG_DEBUG 0
-#if RECONFIG_DEBUG
-unsigned int __sramdata mem[42];
-unsigned int __sramdata maxtimeout =0;
-#endif
-unsigned int __sramdata gpu_suspended;
-unsigned int __sramdata gpu_power;
-unsigned int __sramdata gpu_clock;
-unsigned int __sramdata gpuctl;
-unsigned int __sramdata gpususpendcmd =0x7;
-unsigned int __sramdata currcmdbufadr;
-unsigned int __sramdata clksel17;
-unsigned int __sramdata cru_gatecon[4];
-unsigned int __sramdata i2sxfer;
-void __sramlocalfunc __ddr_reconfig(int mode)
-{
-#if 1
- int i, n, bakdatr;
- volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
-
-// __cpuc_flush_kern_all();
-// __cpuc_flush_user_all();
- local_flush_tlb_all();
- n=temp[0];
- barrier();
- n=temp[1024];
- barrier();
- n=temp[1024*2];
- barrier();
- n=temp[1024*3];
- barrier();
- n= pSCU_Reg->CRU_SOFTRST_CON[0];
-
- dsb();
- pDDR_Reg->DLLCR09[0] &=~0x3c000;
- pDDR_Reg->DLLCR09[1] &=~0x3c000;
- pDDR_Reg->DLLCR09[2] &=~0x3c000;
- pDDR_Reg->DLLCR09[3] &=~0x3c000;
- pDDR_Reg->DLLCR09[0] |=0x4000; //set 90-18
- pDDR_Reg->DLLCR09[1] |=0x4000;
- pDDR_Reg->DLLCR09[2] |=0x4000;
- pDDR_Reg->DLLCR09[3] |=0x4000;
-
- n=pGRF_Reg->GRF_OS_REG[2]; // *(unsigned long volatile *)(0xf50080d8);
-
- pDDR_Reg->CCR &= ~HOSTEN; //ddr3 400m 4us 4*6*rank+1;
-
- pDDR_Reg->DCR = (pDDR_Reg->DCR & (~((0x1<<24) | (0x1<<13) | (0xF<<27) | (0x1<<31)))) | ((0x1<<13) | (0x2<<27) | (0x1<<31)); //enter Self Refresh
- while(pDDR_Reg->DCR &(0x1<<31)); //may done soon
- ddrReg_Save();
-
-#if 1
-#if 1
- //DO_INT Must be cleared before ddrReg_Save
-
- pSCU_Reg->CRU_SOFTRST_CON[2] |= ((0x3<<15) | (0x3<<11) |(0x3<<8));
- pSCU_Reg->CRU_SOFTRST_CON[0] |= (0x7f<<18);
- dsb();
- Delay10cyc(100);
- pSCU_Reg->CRU_SOFTRST_CON[2] &= ~((0x3<<15) | (0x3<<11) | (0x3<<8));
-// if((mode >>12)&0xfff)
-// *(unsigned long volatile *)(0xf50080ac) =mode &0xfff;
-
- pDDR_Reg->PQCR[0] =0x0e03f000;
- pDDR_Reg->PQCR[1] =(mode ==0) ?0x0e000000 : 0x0e00f000;
-// pDDR_Reg->PQCR[2] =0x0e00f000;
- ddrReg_Restore();
- pDDR_Reg->MMGCR =((mode&0xf) ==0) ?0 : 2;
-
- pSCU_Reg->CRU_SOFTRST_CON[0] &=~(0x7F<<18);
- dsb();
- Delay10cyc(200); //need 1024 cycles, worst case assume ddr @200MHZ, cpu at @1GHZ, need 5120 cycles delay
-// if((pDDR_Reg->DRR) &0x0f000000)
-// while(1);
-#else
- cru_gatecon[0] =pSCU_Reg->CRU_CLKGATE_CON[0];
- cru_gatecon[1] =pSCU_Reg->CRU_CLKGATE_CON[1];
- cru_gatecon[3] =pSCU_Reg->CRU_CLKGATE_CON[3];
-
- pSCU_Reg->CRU_CLKGATE_CON[0] |=/*(2<<19)*/(3<<9);
- pSCU_Reg->CRU_CLKGATE_CON[1] |=(1<<6);
- pSCU_Reg->CRU_CLKGATE_CON[3] |=((1<<1) |(0xf<<10) |(0xf<<14));
- pSCU_Reg->CRU_SOFTRST_CON[2] |=(1<<9);// ((0x1<<15) | (0x3<<11) | (0x3<<8));
- dsb();
- Delay10cyc(100);
- pSCU_Reg->CRU_SOFTRST_CON[0] |= (0x7f<<18);
- Delay10cyc(100);
- pSCU_Reg->CRU_SOFTRST_CON[2] &= ~((0x1<<15) | (0x3<<11) | (0x3<<8));
- if((mode >>12)&0xfff)
- *(unsigned long volatile *)(0xf50080ac) =mode &0xfff;
-
- pDDR_Reg->PQCR[0] =0x0e03f000;
- pDDR_Reg->PQCR[1] =0x0e01f000;
- pDDR_Reg->PQCR[2] =0x0e00f000;
- ddrReg_Restore();
- pDDR_Reg->MMGCR =(mode ==0) ?0:2;
- dsb();
-
- pSCU_Reg->CRU_SOFTRST_CON[0] &=~(0x7F<<18);
- dsb();
- Delay10cyc(100);
- pSCU_Reg->CRU_CLKGATE_CON[0]=cru_gatecon[0];
- pSCU_Reg->CRU_CLKGATE_CON[1]=cru_gatecon[1];
- pSCU_Reg->CRU_CLKGATE_CON[3]=cru_gatecon[3];
- Delay10cyc(200); //need 1024 cycles, worst case assume ddr @200MHZ, cpu at @1GHZ, need 5120 cycles delay
-#endif
- pDDR_Reg->DCR |= DO_INIT;
- while(pGRF_Reg->GRF_MEM_STATUS[2] & 0x1) //wait init ok
- Delay10cyc(1);
- pDDR_Reg->DRR |=(1<<31);
- Delay10cyc(10);
- pDDR_Reg->CCR |= DTT; //ddr3 400m 4us 4*6*rank+1;
- Delay10cyc(100);
- while(pGRF_Reg->GRF_MEM_STATUS[2] & 0x1) //wait dtt ok
- Delay10cyc(1);
- if(pGRF_Reg->GRF_MEM_STATUS[2] & 0x2)
- while(1);
- pDDR_Reg->DRR &=~(1<<31);
- pDDR_Reg->DLLCR09[0] &=~0x3c000;
- pDDR_Reg->DLLCR09[1] &=~0x3c000;
- pDDR_Reg->DLLCR09[2] &=~0x3c000;
- pDDR_Reg->DLLCR09[3] &=~0x3c000;
- pDDR_Reg->DLLCR09[0] |=0x10000; //set 90+18
- pDDR_Reg->DLLCR09[1] |=0x10000;
- pDDR_Reg->DLLCR09[2] |=0x10000;
- pDDR_Reg->DLLCR09[3] |=0x10000;
- pDDR_Reg->DCR &=~DO_INIT;
- pDDR_Reg->CCR |= HOSTEN; //enable host port
- dsb();
-#endif
-#endif
-}
-
-unsigned int tmodelay1us(unsigned int tmo)
-{
- delayus(1);
- return tmo +1;
-}
-/**********************************
-*input mode
-*case mode
-*0 normal
-*1 cpu priority highest
-*2 cpu priority ualtra
- GRF_MEM_CON[1:0]: CPU (host 0)
- [3:2]: PERI (host 1)
- [5:4]: DISPLAY (host 2)
- [7:6]: GPU (host 3)
- [9:8]: VCODEC (host 4)
-***********************************/
-
-void/* inline*/ __sramfunc sram_printch(char byte);
-int ddr_reconfig(int mode)
-{
- int baklcdctrl;
- int count =0;
- int i;
- unsigned int ret =0;
- unsigned int con3save, flags;
- unsigned int tmo =0;
- mode &=0xf;
- if((pDDR_Reg->MMGCR ==0) &&(mode <2))
- {
- pDDR_Reg->PQCR[0] =(mode ==0) ?0x0e000000 : 0x0e00f000;
- pDDR_Reg->PQCR[1] =(mode ==0) ?0x0e000000 : 0x0e03f000;
- pDDR_Reg->PQCR[2] =(mode ==0) ?0x0e000000 : 0x0e00f000;
- pGRF_Reg->GRF_MEM_CON = (pGRF_Reg->GRF_MEM_CON & ~0x3FF)
- | ((mode ==0) ?((2<<0)|(1<<2)|(0<<4)|(1<<6)|(2<<8)):((0<<0)|(2<<2)|(1<<4)|(2<<6)|(2<<8)));
- return 1;
- }
- local_irq_save(flags);
- sram_printch('1');
-/* if(mode ==2)
- {
- tmp =*(unsigned long volatile *)(0xf50080bc);
- pDDR_Reg->PQCR[0] =0x0e03f000;
- pDDR_Reg->PQCR[1] =0x0e01f000;
- pDDR_Reg->PQCR[2] =0x0e00f000;
- pDDR_Reg->MMGCR =(mode ==0) ?0 : 2;
- }
-*/
-// asm volatile ("cpsid if");
- {
- __cpuc_flush_kern_all();
- __cpuc_flush_user_all();
- dsb();
- //some risk: if a common to lcdc is going, then a read form 0xf410c0000 may retrun an old val
- con3save =pSCU_Reg->CRU_CLKGATE_CON[3];
- pSCU_Reg->CRU_CLKGATE_CON[3] =con3save |(1<<3);
- pGRF_Reg->GRF_SOC_CON[0] |=(1<<0);
- {
- gpu_suspended =0;
- gpu_power =0;
- gpu_clock =0;
-
- if((*(unsigned long volatile *)(RK29_PMU_BASE +0x10) &0x40) ==0)
- {
- gpu_power =1;
- if((0xf<<14) !=(pSCU_Reg->CRU_CLKGATE_CON[3] &(0xf<<14)))
- {
- gpu_clock =1;
- if(*(unsigned long volatile *)(RK29_GPU_BASE +0x4) !=0x7fffffff)
- { //clock enable and not at idle
- gpu_suspended =1;
-#if 1
- #if 1
- int chktime =0;
- for(chktime =0; chktime<32; chktime++ )
- {
- if(*(unsigned long volatile *)(RK29_GPU_BASE +0x4) !=0x7ffffffe)
- { chktime =0;
- //
- if((tmo =tmodelay1us(tmo)) >10)
- #if 0 //RECONFIG_DEBUG
- while(1);
- #else
- goto ddr_reconfig_cancel;
- #endif
- }
- }
- #if RECONFIG_DEBUG
- if(tmo >maxtimeout)
- {
- maxtimeout =tmo;
- printk("maxtimout %d\n", maxtimeout);
- }
- #endif
- {
- unsigned int i,tmp;
- currcmdbufadr =*(unsigned long volatile *)(RK29_GPU_BASE +0x664);
- if((currcmdbufadr&0xfff0) ==0)
- for(i =0; i<6; i++)
- {
- tmp =*(unsigned long volatile *)(RK29_GPU_BASE +0x664);
- if(((tmp >currcmdbufadr) &&((tmp -currcmdbufadr) >0x10))
- ||((tmp <currcmdbufadr) &&((currcmdbufadr -tmp) >0x10)))
- {
- printk("gpu:cmdbuffer base reg read error 0x%x !=0x%x\n", tmp, currcmdbufadr);
- i =0;
- }
- else
- delayus(1);
- currcmdbufadr =tmp;
- }
- }
- #if 0
- for(i =0; i<0x1000; i++)
- {
- unsigned int tmp;
- if(currcmdbufadr >(tmp =*(unsigned long volatile *)(0xf4120664)))
- currcmdbufadr =tmp;
- }
- #else
- if(*(int *)(currcmdbufadr +0x60000000) !=0x380000c8) //0x60000000 assume VA =PA +0x60000000
- {
- currcmdbufadr -=8;
- if(*(int *)(currcmdbufadr +0x60000000) !=0x380000c8)
- {
- currcmdbufadr -=8;
- if(*(int *)(currcmdbufadr +0x60000000) !=0x380000c8)
- #if RECONFIG_DEBUG
- while(1);
- #else
- goto ddr_reconfig_cancel;
- #endif
- }
- }
- #endif
- #if 0 //RECONFIG_DEBUG
- if((currcmdbufadr &0xffffe000) !=0x736ce000)
- while(1);
- {
- int i;
- for(i =0; i<16; i++)
- mem[i] =*(int *)(currcmdbufadr +0x60000000 +(i-4)*4);
- }
-
- #endif
- #endif
-
- *(unsigned long volatile *)(RK29_GPU_BASE +0x658) =0x2;
- dsb();
- while(*(unsigned long volatile *)(RK29_GPU_BASE +0x4) !=0x7fffffff) delayus(1); //
-#else
- gpuctl =*(unsigned long volatile *)(RK29_GPU_BASE +0x0);
- *(unsigned long volatile *)(RK29_GPU_BASE +0x0) =gpususpendcmd;
- delayus(100);
-#endif
- }
- }
- }
- sram_printch('5');
- if(!(gpu_clock &gpu_power))
- {
- unsigned int tmoadd1ms =tmo +3000;
- sram_printch('c');
-// if(tmo==0)
- if(pGRF_Reg->GRF_OS_REG[3] ==0xff)
- while(1);
- pSCU_Reg->CRU_CLKGATE_CON[3] =(con3save |(1<<3)) &0xfffc3fff;
- clksel17 =pSCU_Reg->CRU_CLKSEL_CON[17];
- pSCU_Reg->CRU_CLKSEL_CON[17]&=~(3<<14);
- dsb();
- *(unsigned long volatile *)(RK29_PMU_BASE +0x10) &=~0x40;
- dsb();
- while((tmo =tmodelay1us(tmo)) <tmoadd1ms);
- pSCU_Reg->CRU_CLKGATE_CON[3] =(con3save |(1<<3)) &0xfffc3fff;
- }
- }
- sram_printch('6');
- //status check
- //3 VIP clock con2[22,18](0x20000064) VIPCTL[0](0x10108010) 0==stop
- while(((0)==(pSCU_Reg->CRU_CLKGATE_CON[2] &((0x1<<18)|(0x1<<22))))
- &&((0)!=(*(unsigned long volatile *)(RK29_VIP_BASE +0x10) &(1<<0))) &&((1)!=(*(unsigned long volatile *)(RK29_VIP_BASE +0x2c) &(1<<0))))
- if((tmo =tmodelay1us(tmo)) >20)
- #if RECONFIG_DEBUG
- // goto ddr_reconfig_cancel2;
- while(1);
- #else
- goto ddr_reconfig_cancel2;
- #endif
-
- sram_printch('7');
- //1 IPP clock_con3[5:4](0x20000068) INT_ST[6](0x10110010) 1 ==working
- if(((0)==(pSCU_Reg->CRU_CLKGATE_CON[3] &(0x3<<4))) &&
- ((0)!=(*(unsigned long volatile *)(RK29_IPP_BASE +0x10) &(1<<6))))
- if((tmo =tmodelay1us(tmo)) >200000)
- #if RECONFIG_DEBUG
- while(1);
- #else
- goto ddr_reconfig_cancel2;
- #endif
- sram_printch('8');
- //2 SDMA0 clock con0[10](0x2000005c) DSR[3:0](0x20180000) 0 ==stop
-
-// i2sxfer =*(unsigned long volatile *)(RK29_I2S0_BASE +0x28);
-// *(unsigned long volatile *)(RK29_I2S0_BASE +0x28) =0;
- while(((0)==(pSCU_Reg->CRU_CLKGATE_CON[0] &(0x1<<10)))
- &&(((0)!=(*(unsigned long volatile *)(RK29_SDMAC0_BASE +0x0) &(0xf<<0)))
- ||(((0)!=(*(unsigned long volatile *)(RK29_SDMAC0_BASE +0x100) &(0xf<<0)))/*&& ((0x27)!=(*(unsigned long volatile *)(RK29_SDMAC0_BASE +0x100) &(0xff<<0)))*/)
- ||((0)!=(*(unsigned long volatile *)(RK29_SDMAC0_BASE +0x108) &(0xf<<0)))
- ||((0)!=(*(unsigned long volatile *)(RK29_SDMAC0_BASE +0x110) &(0xf<<0)))
- ||((0)!=(*(unsigned long volatile *)(RK29_SDMAC0_BASE +0x118) &(0xf<<0)))))
- if((tmo =tmodelay1us(tmo)) >200000)
- #if RECONFIG_DEBUG
- while(1);
- #else
- goto ddr_reconfig_cancel2;
- #endif
- sram_printch('9');
- //2 DMA0 clock con0[9](0x2000005c) DSR[3:0](0x201C0000) 0 ==stop
- while(((0)==(pSCU_Reg->CRU_CLKGATE_CON[0] &(0x1<<9)))
- &&(((0)!=(*(unsigned long volatile *)(RK29_DMAC0_BASE +0x0) &(0xf<<0)))
- ||((0)!=(*(unsigned long volatile *)(RK29_DMAC0_BASE +0x100) &(0xf<<0)))
- ||((0)!=(*(unsigned long volatile *)(RK29_DMAC0_BASE +0x108) &(0xf<<0)))
- ||((0)!=(*(unsigned long volatile *)(RK29_DMAC0_BASE +0x110) &(0xf<<0)))
- ||((0)!=(*(unsigned long volatile *)(RK29_DMAC0_BASE +0x118) &(0xf<<0)))))
- if((tmo =tmodelay1us(tmo)) >200000)
- #if RECONFIG_DEBUG
- while(1);
- #else
- goto ddr_reconfig_cancel2;
- #endif
- sram_printch('a');
- //2 DMA1 clock con1[5](0x20000060) DSR[3:0](0x20078000) 0 ==stop
- while(((0)==(pSCU_Reg->CRU_CLKGATE_CON[1] &(0x1<<5)))
- &&(((0)!=(*(unsigned long volatile *)(RK29_DMAC1_BASE +0x0) &(0xf<<0)))
- ||((0)!=(*(unsigned long volatile *)(RK29_DMAC1_BASE +0x100) &(0xf<<0)))
- ||((0)!=(*(unsigned long volatile *)(RK29_DMAC1_BASE +0x108) &(0xf<<0)))
- ||((0)!=(*(unsigned long volatile *)(RK29_DMAC1_BASE +0x110) &(0xf<<0)))
- ||((0)!=(*(unsigned long volatile *)(RK29_DMAC1_BASE +0x118) &(0xf<<0)))))
- if((tmo =tmodelay1us(tmo)) >200000)
- #if RECONFIG_DEBUG
- while(1);
- #else
- goto ddr_reconfig_cancel2;
- #endif
- sram_printch('b');
-/*
- //4 USB
- if(((0)==(*(unsigned long volatile *)(0xf5000068) &(0x3<<4))) &&
- ((0)==(*(unsigned long volatile *)(0xf4110010) &(1<<6))))
- while(1);
-*/
- //5 VPU when select VDPU clk VDPU clock con2[19,13:12]else con2[18,11:10] (0x20000068) wreg[1](0x10104204) 0==stop
- //wreg24[0] 0==stop
- {
- int clkgatemask;
- clkgatemask =((0x1<<18)|(0x3<<10))<<((((pGRF_Reg->GRF_SOC_CON[0]))>>23) &1);
- if((0)==(pSCU_Reg->CRU_CLKGATE_CON[3] &clkgatemask))
- while((((0)!=(*(unsigned long volatile *)(RK29_VCODEC_BASE +0x204) &(1<<0)))
- &&((0)==(*(unsigned long volatile *)(RK29_VCODEC_BASE +0x204) &(1<<13)))) //until idle or buff_int
- ||((0)!=(*(unsigned long volatile *)(RK29_VCODEC_BASE +0x38) &(1<<0))))
- if((tmo =tmodelay1us(tmo)) >200000)
- #if RECONFIG_DEBUG
- while(1);
- #else
- goto ddr_reconfig_cancel2;
- #endif
- }
-// while(((0xf<<14)!=(pSCU_Reg->CRU_CLKGATE_CON[3] &(0xf<<14))) &&
-// (*(unsigned long volatile *)(0xf4120004) !=0x7fffffff));
- sram_printch('2');
-
- {
- static unsigned long save_sp;
-
- DDR_SAVE_SP(save_sp);
- {
- __ddr_reconfig(mode);
-
- }
- DDR_RESTORE_SP(save_sp);
- } // do_ddr_reconfig(mode);
-///////////////////////////////////////////////////////////
- sram_printch('3');
- ret =1;
-// *(unsigned long volatile *)(RK29_I2S0_BASE +0x28) =i2sxfer;
- if(gpu_suspended)
- {
-#if 1
- *(unsigned long volatile *)(RK29_GPU_BASE +0x654) =currcmdbufadr;
- *(unsigned long volatile *)(RK29_GPU_BASE +0x658) =0x10002;
- dsb();
- while(*(unsigned long volatile *)(RK29_GPU_BASE +0x4) !=0x7ffffffe);
- #if RECONFIG_DEBUG
- mem[34] =*(unsigned long volatile *)(RK29_GPU_BASE +0x660);
- mem[35] =*(unsigned long volatile *)(RK29_GPU_BASE +0x664);
- mem[36] =*(unsigned long volatile *)(RK29_GPU_BASE +0x668);
- mem[37] =*(unsigned long volatile *)(RK29_GPU_BASE +0x66c);
- {
- int i;
- for(i =0; i<16; i++)
- mem[i+16] =*(int *)(currcmdbufadr +0x60000000 +(i-4)*4);
- }
- mem[32] =currcmdbufadr;
- mem[33]++;
-// printk("reconfig 0x%x ,0x%x ,0x%x ,0x%x ,", *(unsigned int volatile *)(0xf4120660),
-// *(unsigned int volatile *)(0xf4120664),*(unsigned int volatile *)(0xf4120668),
-// *(unsigned int volatile *)(0xf412066c));
- #endif
-#else
- *(unsigned long volatile *)(RK29_GPU_BASE +0x0) =gpuctl;
-#endif
- }
-
- #if RECONFIG_DEBUG
- printk("clkgate =0x%x, 0x%x\n",pSCU_Reg->CRU_CLKGATE_CON[3],tmo);
- #endif
- count++;
-
-ddr_reconfig_cancel2:
- if(!gpu_clock )
- pSCU_Reg->CRU_CLKSEL_CON[17] =clksel17;
- if(!gpu_power)
- *(unsigned long volatile *)(RK29_PMU_BASE +0x10) |=0x40;
- dsb();
- #if RECONFIG_DEBUG
- if((gpu_power ==0) &&( 1 ==gpu_clock))
- while(1);
- #endif
-ddr_reconfig_cancel:
- pSCU_Reg->CRU_CLKGATE_CON[3] =con3save;
- pGRF_Reg->GRF_SOC_CON[0]&=~(1<<0);
- }
- local_irq_restore(flags);
- sram_printch('4');
- return ret;
-}
-#endif
-
-
-int rk29fb_irq_notify_ddr(void)
-{
- {
- int tmp;
- if(((tmp =*(unsigned long volatile *)(RK29_LCDC_BASE)) &(2<<10)) ==0) //win 0 blanked
- {
- if((tmp &(1<<10)) &&(((pDDR_Reg->MMGCR &(1<<1)) ==2) ||((pGRF_Reg->GRF_MEM_CON &0x3) ==0))) //has OSD and current ddr is supper priority
- ddr_reconfig(0);
- }
- else
- {
- if(((pDDR_Reg->MMGCR &(1<<1)) ==0) &&((pGRF_Reg->GRF_MEM_CON &0x3) ==2)) //current not supper priority
- {
- if((((tmp >>3) &0x7) <2) &&((tmp &(1<<10)) ==0)) //LCD is RGB format, has not OSD
- ddr_reconfig(1);
- }
- }
- }
-}
-
-//#include "ddr_test.c"
-
+++ /dev/null
-/* arch/arm/mach-rk29/ddrfreq.c
- *
- * Copyright (C) 2011 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <mach/clock.h>
-#include <mach/ddr.h>
-
-#define MHZ (1000*1000)
-
-enum {
- DEBUG_CHANGE = 1U << 0,
- DEBUG_EVENT = 1U << 1,
-};
-static uint debug_mask = DEBUG_CHANGE;
-module_param(debug_mask, uint, 0644);
-#define dprintk(mask, fmt, ...) do { if (mask & debug_mask) printk(KERN_DEBUG "ddrfreq: " fmt, ##__VA_ARGS__); } while (0)
-
-static struct clk *clk_ddr;
-static struct clk *ddr_pll_clk;
-static struct clk *aclk_lcdc;
-static bool ddr_pll_can_change;
-static bool aclk_lcdc_disabled;
-static bool disable_ddr_freq;
-module_param(ddr_pll_can_change, bool, 0644);
-module_param(aclk_lcdc_disabled, bool, 0644);
-module_param(disable_ddr_freq, bool, 0644);
-
-static unsigned long ddr_max_mhz;
-static unsigned long ddr_min_mhz = 96;
-static void rk29_ddrfreq_change_freq(void);
-static int rk29_ddrfreq_set_ddr_mhz(const char *val, struct kernel_param *kp)
-{
- int err = param_set_uint(val, kp);
- if (!err) {
- rk29_ddrfreq_change_freq();
- }
- return err;
-}
-module_param_call(ddr_max_mhz, rk29_ddrfreq_set_ddr_mhz, param_get_uint, &ddr_max_mhz, 0644);
-module_param_call(ddr_min_mhz, rk29_ddrfreq_set_ddr_mhz, param_get_uint, &ddr_min_mhz, 0644);
-
-static DEFINE_SPINLOCK(ddr_lock);
-
-static void rk29_ddrfreq_change_freq(void)
-{
- unsigned long ddr_rate, mhz;
-
- if (disable_ddr_freq)
- return;
-
- ddr_rate = clk_get_rate(clk_ddr);
- mhz = (ddr_pll_can_change && aclk_lcdc_disabled) ? ddr_min_mhz : ddr_max_mhz;
- if ((mhz * MHZ) != ddr_rate) {
- dprintk(DEBUG_CHANGE, "%lu -> %lu Hz\n", ddr_rate, mhz * MHZ);
- ddr_change_freq(mhz);
- dprintk(DEBUG_CHANGE, "got %lu Hz\n", clk_get_rate(clk_ddr));
- }
-}
-
-static int rk29_ddrfreq_ddr_pll_notifier_event(struct notifier_block *this,
- unsigned long event, void *ptr)
-{
- spin_lock_bh(&ddr_lock);
- switch (event) {
- case CLK_PRE_ENABLE:
- ddr_pll_can_change = false;
- break;
- case CLK_ABORT_ENABLE:
- case CLK_POST_DISABLE:
- ddr_pll_can_change = true;
- break;
- default:
- goto out;
- }
-
- if (!disable_ddr_freq) {
- dprintk(DEBUG_EVENT, "event: %lu ddr_pll_can_change: %d\n", event, ddr_pll_can_change);
- rk29_ddrfreq_change_freq();
- }
-out:
- spin_unlock_bh(&ddr_lock);
- return NOTIFY_OK;
-}
-
-static struct notifier_block rk29_ddrfreq_ddr_pll_notifier = {
- .notifier_call = rk29_ddrfreq_ddr_pll_notifier_event,
-};
-
-static int rk29_ddrfreq_aclk_lcdc_notifier_event(struct notifier_block *this,
- unsigned long event, void *ptr)
-{
- spin_lock_bh(&ddr_lock);
- switch (event) {
- case CLK_PRE_ENABLE:
- aclk_lcdc_disabled = false;
- break;
- case CLK_ABORT_ENABLE:
- case CLK_POST_DISABLE:
- aclk_lcdc_disabled = true;
- break;
- default:
- goto out;
- }
-
- if (!disable_ddr_freq) {
- dprintk(DEBUG_EVENT, "event: %lu aclk_lcdc_disabled: %d\n", event, aclk_lcdc_disabled);
- rk29_ddrfreq_change_freq();
- }
-out:
- spin_unlock_bh(&ddr_lock);
- return NOTIFY_OK;
-}
-
-static struct notifier_block rk29_ddrfreq_aclk_lcdc_notifier = {
- .notifier_call = rk29_ddrfreq_aclk_lcdc_notifier_event,
-};
-
-static int __init rk29_ddrfreq_init(void)
-{
- clk_ddr = clk_get(NULL, "ddr");
- if (IS_ERR(clk_ddr)) {
- int err = PTR_ERR(clk_ddr);
- pr_err("fail to get ddr clk: %d\n", err);
- clk_ddr = NULL;
- return err;
- }
-
- ddr_max_mhz = clk_get_rate(clk_ddr) / MHZ;
-
- ddr_pll_clk = clk_get(NULL, "ddr_pll");
- aclk_lcdc = clk_get(NULL, "aclk_lcdc");
-
- clk_notifier_register(ddr_pll_clk, &rk29_ddrfreq_ddr_pll_notifier);
- clk_notifier_register(aclk_lcdc, &rk29_ddrfreq_aclk_lcdc_notifier);
-
- printk("ddrfreq: version 1.0\n");
- return 0;
-}
-
-late_initcall(rk29_ddrfreq_init);
+++ /dev/null
-/* arch/arm/mach-rk29/devices.c
- *
- * Copyright (C) 2010 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/fs.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#ifdef CONFIG_USB_ANDROID
-#include <linux/usb/android_composite.h>
-#endif
-#include <linux/delay.h>
-#include <linux/dma-mapping.h>
-#include <asm/pmu.h>
-#include <mach/irqs.h>
-#include <mach/rk29_iomap.h>
-#include <mach/rk29-dma-pl330.h>
-#include <mach/rk29_camera.h> /* ddl@rock-chips.com : camera support */
-#include <mach/board.h>
-#include <mach/loader.h>
-#include "devices.h"
-
-#ifdef CONFIG_ADC_RK29
-static struct adc_platform_data rk30_adc_pdata = {
- .ref_volt = 2500, //2500mV
- .base_chn = -1,
-};
-static struct resource rk29_adc_resource[] = {
- {
- .start = IRQ_SARADC,
- .end = IRQ_SARADC,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK29_ADC_PHYS,
- .end = RK29_ADC_PHYS + RK29_ADC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-struct platform_device rk29_device_adc = {
- .name = "rk29-adc",
- .id = -1,
- .num_resources = ARRAY_SIZE(rk29_adc_resource),
- .resource = rk29_adc_resource,
- .dev = {
- .platform_data = &rk29_adc_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_RK29_VMAC
-static u64 eth_dmamask = DMA_BIT_MASK(32);
-static struct resource rk29_vmac_resource[] = {
- [0] = {
- .start = RK29_MAC_PHYS,
- .end = RK29_MAC_PHYS + RK29_MAC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_MAC,
- .end = IRQ_MAC,
- .flags = IORESOURCE_IRQ,
- }
-
-};
-
-struct platform_device rk29_device_vmac = {
- .name = "rk29 vmac",
- .id = 0,
- .dev = {
- .dma_mask = ð_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &rk29_vmac_pdata,
- },
- .num_resources = ARRAY_SIZE(rk29_vmac_resource),
- .resource = rk29_vmac_resource,
-};
-#endif
-
-#ifdef CONFIG_I2C_RK29
-#ifdef CONFIG_RK29_I2C0_CONTROLLER
-static struct resource resources_i2c0[] = {
- {
- .start = IRQ_I2C0,
- .end = IRQ_I2C0,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK29_I2C0_PHYS,
- .end = RK29_I2C0_PHYS + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-#endif
-#ifdef CONFIG_RK29_I2C1_CONTROLLER
-static struct resource resources_i2c1[] = {
- {
- .start = IRQ_I2C1,
- .end = IRQ_I2C1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK29_I2C1_PHYS,
- .end = RK29_I2C1_PHYS + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-#endif
-#ifdef CONFIG_RK29_I2C2_CONTROLLER
-static struct resource resources_i2c2[] = {
- {
- .start = IRQ_I2C2,
- .end = IRQ_I2C2,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK29_I2C2_PHYS,
- .end = RK29_I2C2_PHYS + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-#endif
-#ifdef CONFIG_RK29_I2C3_CONTROLLER
-static struct resource resources_i2c3[] = {
- {
- .start = IRQ_I2C3,
- .end = IRQ_I2C3,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK29_I2C3_PHYS,
- .end = RK29_I2C3_PHYS + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-#endif
-struct platform_device rk29_device_i2c0 = {
-#ifdef CONFIG_RK29_I2C0_CONTROLLER
- .name = "rk29_i2c",
- .id = 0,
- .num_resources = ARRAY_SIZE(resources_i2c0),
- .resource = resources_i2c0,
- .dev = {
- .platform_data = &default_i2c0_data,
- },
-#else
- .name = "i2c-gpio",
- .id = 0,
- .dev = {
- .platform_data = &default_i2c0_data,
- },
-#endif
-};
-struct platform_device rk29_device_i2c1 = {
-#ifdef CONFIG_RK29_I2C1_CONTROLLER
- .name = "rk29_i2c",
- .id = 1,
- .num_resources = ARRAY_SIZE(resources_i2c1),
- .resource = resources_i2c1,
- .dev = {
- .platform_data = &default_i2c1_data,
- },
-#else
- .name = "i2c-gpio",
- .id = 1,
- .dev = {
- .platform_data = &default_i2c1_data,
- },
-#endif
-};
-struct platform_device rk29_device_i2c2 = {
-#ifdef CONFIG_RK29_I2C2_CONTROLLER
- .name = "rk29_i2c",
- .id = 2,
- .num_resources = ARRAY_SIZE(resources_i2c2),
- .resource = resources_i2c2,
- .dev = {
- .platform_data = &default_i2c2_data,
- },
-#else
- .name = "i2c-gpio",
- .id = 2,
- .dev = {
- .platform_data = &default_i2c2_data,
- },
-#endif
-};
-struct platform_device rk29_device_i2c3 = {
-#ifdef CONFIG_RK29_I2C3_CONTROLLER
- .name = "rk29_i2c",
- .id = 3,
- .num_resources = ARRAY_SIZE(resources_i2c3),
- .resource = resources_i2c3,
- .dev = {
- .platform_data = &default_i2c3_data,
- },
-#else
- .name = "i2c-gpio",
- .id = 3,
- .dev = {
- .platform_data = &default_i2c3_data,
- },
-#endif
-};
-#endif
-
-/***********************************************************
-* backlight
-***************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-#endif
-
-#ifdef CONFIG_BUTTON_LIGHT
-struct platform_device rk29_device_buttonlight = {
- .name = "rk29_button_light",
- .id = -1,
- .dev = {
- .platform_data = &rk29_button_light_info,
- }
-};
-#endif
-#ifdef CONFIG_SDMMC0_RK29
-#ifndef CONFIG_EMMC_RK29
-static struct resource resources_sdmmc0[] = {
- {
- .start = IRQ_SDMMC,
- .end = IRQ_SDMMC,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK29_SDMMC0_PHYS,
- .end = RK29_SDMMC0_PHYS + RK29_SDMMC0_SIZE -1,
- .flags = IORESOURCE_MEM,
- }
-};
-#else
-static struct resource resources_sdmmc0[] = {
- {
- .start = IRQ_EMMC,
- .end = IRQ_EMMC,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK29_EMMC_PHYS,
- .end = RK29_EMMC_PHYS + RK29_EMMC_SIZE -1,
- .flags = IORESOURCE_MEM,
- }
-};
-#endif
-#endif
-#ifdef CONFIG_SDMMC1_RK29
-static struct resource resources_sdmmc1[] = {
- {
- .start = IRQ_SDIO,
- .end = IRQ_SDIO,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK29_SDMMC1_PHYS,
- .end = RK29_SDMMC1_PHYS + RK29_SDMMC1_SIZE -1,
- .flags = IORESOURCE_MEM,
- }
-};
-#endif
-/* sdmmc */
-#ifdef CONFIG_SDMMC0_RK29
-struct platform_device rk29_device_sdmmc0 = {
- .name = "rk29_sdmmc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resources_sdmmc0),
- .resource = resources_sdmmc0,
- .dev = {
- .platform_data = &default_sdmmc0_data,
- },
-};
-#endif
-#ifdef CONFIG_SDMMC1_RK29
-struct platform_device rk29_device_sdmmc1 = {
- .name = "rk29_sdmmc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resources_sdmmc1),
- .resource = resources_sdmmc1,
- .dev = {
- .platform_data = &default_sdmmc1_data,
- },
-};
-#endif
-
-/*
- * rk29 wdt device ADDED BY HHB@ROCK-CHIPS.COM
- */
-
-#ifdef CONFIG_RK29_WATCHDOG
-
-static struct resource resources_wdt[] = {
- {
- .start = IRQ_WDT,
- .end = IRQ_WDT,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK29_WDT_PHYS,
- .end = RK29_WDT_PHYS + RK29_WDT_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-struct platform_device rk29_device_wdt = {
- .name = "rk29-wdt",
- .id = 0,
- .num_resources = ARRAY_SIZE(resources_wdt),
- .resource = resources_wdt,
-};
-
-#endif
-
-
-/*
- * rk29 4 uarts device
- */
-#ifdef CONFIG_UART0_RK29
-static struct resource resources_uart0[] = {
- {
- .start = IRQ_UART0,
- .end = IRQ_UART0,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK29_UART0_PHYS,
- .end = RK29_UART0_PHYS + RK29_UART0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-#endif
-#ifdef CONFIG_UART1_RK29
-static struct resource resources_uart1[] = {
- {
- .start = IRQ_UART1,
- .end = IRQ_UART1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK29_UART1_PHYS,
- .end = RK29_UART1_PHYS + RK29_UART1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-#endif
-#ifdef CONFIG_UART2_RK29
-static struct resource resources_uart2[] = {
- {
- .start = IRQ_UART2,
- .end = IRQ_UART2,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK29_UART2_PHYS,
- .end = RK29_UART2_PHYS + RK29_UART2_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-#endif
-#ifdef CONFIG_UART3_RK29
-static struct resource resources_uart3[] = {
- {
- .start = IRQ_UART3,
- .end = IRQ_UART3,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK29_UART3_PHYS,
- .end = RK29_UART3_PHYS + RK29_UART3_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-#endif
-#ifdef CONFIG_UART0_RK29
-struct platform_device rk29_device_uart0 = {
- .name = "rk29_serial",
- .id = 0,
- .num_resources = ARRAY_SIZE(resources_uart0),
- .resource = resources_uart0,
-};
-#endif
-#ifdef CONFIG_UART1_RK29
-struct platform_device rk29_device_uart1 = {
- .name = "rk29_serial",
- .id = 1,
- .num_resources = ARRAY_SIZE(resources_uart1),
- .resource = resources_uart1,
-};
-#endif
-#ifdef CONFIG_UART2_RK29
-struct platform_device rk29_device_uart2 = {
- .name = "rk29_serial",
- .id = 2,
- .num_resources = ARRAY_SIZE(resources_uart2),
- .resource = resources_uart2,
-};
-#endif
-#ifdef CONFIG_UART3_RK29
-struct platform_device rk29_device_uart3 = {
- .name = "rk29_serial",
- .id = 3,
- .num_resources = ARRAY_SIZE(resources_uart3),
- .resource = resources_uart3,
-};
-#endif
-
-/*
- * rk29xx spi master device
- */
-static struct resource rk29_spi0_resources[] = {
- {
- .start = IRQ_SPI0,
- .end = IRQ_SPI0,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK29_SPI0_PHYS,
- .end = RK29_SPI0_PHYS + RK29_SPI0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DMACH_SPI0_TX,
- .end = DMACH_SPI0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = DMACH_SPI0_RX,
- .end = DMACH_SPI0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-struct platform_device rk29xx_device_spi0m = {
- .name = "rk29xx_spim",
- .id = 0,
- .num_resources = ARRAY_SIZE(rk29_spi0_resources),
- .resource = rk29_spi0_resources,
- .dev = {
- .platform_data = &rk29xx_spi0_platdata,
- },
-};
-
-static struct resource rk29_spi1_resources[] = {
- {
- .start = IRQ_SPI1,
- .end = IRQ_SPI1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK29_SPI1_PHYS,
- .end = RK29_SPI1_PHYS + RK29_SPI1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DMACH_SPI1_TX,
- .end = DMACH_SPI1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = DMACH_SPI1_RX,
- .end = DMACH_SPI1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-struct platform_device rk29xx_device_spi1m = {
- .name = "rk29xx_spim",
- .id = 1,
- .num_resources = ARRAY_SIZE(rk29_spi1_resources),
- .resource = rk29_spi1_resources,
- .dev = {
- .platform_data = &rk29xx_spi1_platdata,
- },
-};
-
-#if defined(CONFIG_MTD_NAND_RK29XX)
-static struct resource rk29xxnand_resources[] = {
- {
- .start = RK29_NANDC_PHYS,
- .end = RK29_NANDC_PHYS+RK29_NANDC_SIZE -1,
- .flags = IORESOURCE_MEM,
- }
-};
-
-struct platform_device rk29xx_device_nand = {
- .name = "rk29xxnand",
- .id = -1,
- .resource = rk29xxnand_resources,
- .num_resources= ARRAY_SIZE(rk29xxnand_resources),
- .dev = {
- .platform_data= &rk29_nand_data,
- },
-
-};
-#endif
-
-
-#if defined(CONFIG_MTD_NAND_RK29)
-static struct resource nand_resources[] = {
- {
- .start = RK29_NANDC_PHYS,
- .end = RK29_NANDC_PHYS+RK29_NANDC_SIZE -1,
- .flags = IORESOURCE_MEM,
- }
-};
-
-struct platform_device rk29_device_nand = {
- .name = "rk29-nand",
- .id = -1,
- .resource = nand_resources,
- .num_resources= ARRAY_SIZE(nand_resources),
- .dev = {
- .platform_data= &rk29_nand_data,
- },
-
-};
-#endif
-
-#if defined(CONFIG_SND_RK29_SOC_I2S)
-static struct resource rk29_iis_2ch_resource[] = {
- [0] = {
- .start = RK29_I2S_2CH_PHYS,
- .end = RK29_I2S_2CH_PHYS + RK29_I2S_2CH_SIZE -1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = DMACH_I2S_2CH_TX,
- .end = DMACH_I2S_2CH_TX,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = DMACH_I2S_2CH_RX,
- .end = DMACH_I2S_2CH_RX,
- .flags = IORESOURCE_DMA,
- },
- [3] = {
- .start = IRQ_I2S_2CH,
- .end = IRQ_I2S_2CH,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device rk29_device_iis_2ch = {
- .name = "rk29_i2s",
- .id = 1,
- .num_resources = ARRAY_SIZE(rk29_iis_2ch_resource),
- .resource = rk29_iis_2ch_resource,
-};
-
-static struct resource rk29_iis_8ch_resource[] = {
- [0] = {
- .start = RK29_I2S_8CH_PHYS,
- .end = RK29_I2S_8CH_PHYS + RK29_I2S_8CH_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = DMACH_I2S_8CH_TX,
- .end = DMACH_I2S_8CH_TX,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = DMACH_I2S_8CH_RX,
- .end = DMACH_I2S_8CH_RX,
- .flags = IORESOURCE_DMA,
- },
- [3] = {
- .start = IRQ_I2S_8CH,
- .end = IRQ_I2S_8CH,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device rk29_device_iis_8ch = {
- .name = "rk29_i2s",
- .id = 0,
- .num_resources = ARRAY_SIZE(rk29_iis_8ch_resource),
- .resource = rk29_iis_8ch_resource,
-};
-#endif
-
-static struct platform_device rk29_device_pcm = {
- .name = "rockchip-audio",
- .id = -1,
-};
-
-
-//#ifdef CONFIG_RK29_IPP
-/* rk29 ipp resource */
-static struct resource rk29_ipp_resource[] = {
- [0] = {
- .start = RK29_IPP_PHYS,
- .end = RK29_IPP_PHYS + RK29_IPP_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_IPP,
- .end = IRQ_IPP,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-/*platform_device*/
-//extern struct rk29ipp_info rk29_ipp_info;
-struct platform_device rk29_device_ipp = {
- .name = "rk29-ipp",
- .id = -1,
- .num_resources = ARRAY_SIZE(rk29_ipp_resource),
- .resource = rk29_ipp_resource,
-};
-//#endif
-
-
-#ifdef CONFIG_USB20_OTG
-/*DWC_OTG*/
-static struct resource usb20_otg_resource[] = {
- {
- .start = IRQ_USB_OTG0,
- .end = IRQ_USB_OTG0,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK29_USBOTG0_PHYS,
- .end = RK29_USBOTG0_PHYS + RK29_USBOTG0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
-};
-
-struct platform_device rk29_device_usb20_otg = {
- .name = "usb20_otg",
- .id = -1,
- .num_resources = ARRAY_SIZE(usb20_otg_resource),
- .resource = usb20_otg_resource,
-};
-#endif
-#ifdef CONFIG_USB_ANDROID
-
-static char *usb_functions_rockchip[] = {
- "usb_mass_storage",
-};
-
-static char *usb_functions_rockchip_adb[] = {
- "usb_mass_storage",
- "adb",
-};
-
-static char *usb_functions_rndis_rockchip[] = {
- "rndis",
- "usb_mass_storage",
-};
-
-static char *usb_functions_rndis_rockchip_adb[] = {
- "rndis",
- "usb_mass_storage",
- "adb",
-};
-
-#ifdef CONFIG_USB_ANDROID_DIAG
-static char *usb_functions_adb_diag[] = {
- "usb_mass_storage",
- "adb",
- "diag",
-};
-#endif
-
-static char *usb_functions_all[] = {
-#ifdef CONFIG_USB_ANDROID_RNDIS
- "rndis",
-#endif
- "usb_mass_storage",
-#ifdef CONFIG_USB_ANDROID_ADB
- "adb",
-#endif
-#ifdef CONFIG_USB_ANDROID_ACM
- "acm",
-#endif
-#ifdef CONFIG_USB_ANDROID_DIAG
- "diag",
-#endif
-};
-
-static struct android_usb_product usb_products[] = {
- {
- .product_id = 0x2910,//0x0c02,//0x4e11,
- .num_functions = ARRAY_SIZE(usb_functions_rockchip),
- .functions = usb_functions_rockchip,
- },
- {
- .product_id = 0x0c02,//0x0c02,//0x4e12,
- .num_functions = ARRAY_SIZE(usb_functions_rockchip_adb),
- .functions = usb_functions_rockchip_adb,
- },
- {
- .product_id = 0x4e13,
- .num_functions = ARRAY_SIZE(usb_functions_rndis_rockchip),
- .functions = usb_functions_rndis_rockchip,
- },
- {
- .product_id = 0x4e14,
- .num_functions = ARRAY_SIZE(usb_functions_rndis_rockchip_adb),
- .functions = usb_functions_rndis_rockchip_adb,
- },
-#ifdef CONFIG_USB_ANDROID_DIAG
- {
- .product_id = 0x4e17,
- .num_functions = ARRAY_SIZE(usb_functions_adb_diag),
- .functions = usb_functions_adb_diag,
- },
-#endif
-};
-/*
- * if anyone want to use adb driver of HTC G1,
- * please change vendor_id to 0x0bb4 and product_id to 0x0c02.
- */
-static struct android_usb_platform_data android_usb_pdata = {
- .vendor_id = 0x0bb4,//0x2207,//0x0bb4,//0x18d1,
- .product_id = 0x4e11,//0x2910,//0x4e11,
- .version = 0x0100,
- .product_name = "rk2918 sdk",
- .manufacturer_name = "RockChip",
- .num_products = ARRAY_SIZE(usb_products),
- .products = usb_products,
- .num_functions = ARRAY_SIZE(usb_functions_all),
- .functions = usb_functions_all,
-};
-
-//static
-struct platform_device android_usb_device = {
- .name = "android_usb",
- .id = -1,
- .dev = {
- .platform_data = &android_usb_pdata,
- },
-};
-
-/********************usb*********************/
-struct usb_mass_storage_platform_data mass_storage_pdata = {
- .nluns = 2,
- .vendor = "RockChip",
- .product = "rk29 sdk",
- .release = 0x0100,
-};
-
-//static
-struct platform_device usb_mass_storage_device = {
- .name = "usb_mass_storage",
- .id = -1,
- .dev = {
- .platform_data = &mass_storage_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_USB_ANDROID_RNDIS
-static struct usb_ether_platform_data rndis_pdata = {
- /* ethaddr is filled by board_serialno_setup */
- .ethaddr = {0xf0, 0xde, 0xf1, 0x42, 0xe8, 0x10},
- .vendorID = 0x22b8,// moto xt701 //0x2207,
- .vendorDescr = "RockChip",
-};
-
-struct platform_device rk29_device_rndis = {
- .name = "rndis",
- .id = -1,
- .dev = {
- .platform_data = &rndis_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_USB11_HOST
-static struct resource usb11_host_resource[] = {
- {
- .start = IRQ_USB_HOST,
- .end = IRQ_USB_HOST,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK29_USBHOST_PHYS,
- .end = RK29_USBHOST_PHYS + RK29_USBHOST_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
-};
-
-struct platform_device rk29_device_usb11_host = {
- .name = "usb11_host",
- .id = -1,
- .num_resources = ARRAY_SIZE(usb11_host_resource),
- .resource = usb11_host_resource,
-};
-#endif
-#ifdef CONFIG_USB20_HOST
-static struct resource usb20_host_resource[] = {
- {
- .start = IRQ_USB_OTG1,
- .end = IRQ_USB_OTG1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK29_USBOTG1_PHYS,
- .end = RK29_USBOTG1_PHYS + RK29_USBOTG1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
-};
-
-struct platform_device rk29_device_usb20_host = {
- .name = "usb20_host",
- .id = -1,
- .num_resources = ARRAY_SIZE(usb20_host_resource),
- .resource = usb20_host_resource,
-};
-#endif
-
-static struct resource rk29_pmu_resource = {
- .start = IRQ_A8IRQ3,
- .end = IRQ_A8IRQ3,
- .flags = IORESOURCE_IRQ,
-};
-
-struct platform_device rk29_device_pmu = {
- .name = "arm-pmu",
- .id = ARM_PMU_DEVICE_CPU,
- .num_resources = 1,
- .resource = &rk29_pmu_resource,
-};
-
-static int boot_mode;
-static int __init boot_mode_init(char *s)
-{
- if (!strcmp(s, "normal"))
- boot_mode = BOOT_MODE_NORMAL;
- else if (!strcmp(s, "factory2"))
- boot_mode = BOOT_MODE_FACTORY2;
- else if (!strcmp(s, "recovery"))
- boot_mode = BOOT_MODE_RECOVERY;
- else if (!strcmp(s, "charge"))
- boot_mode = BOOT_MODE_CHARGE;
- else if (!strcmp(s, "power_test"))
- boot_mode = BOOT_MODE_POWER_TEST;
- else if (!strcmp(s, "offmode_charging"))
- boot_mode = BOOT_MODE_OFFMODE_CHARGING;
-
- return 1;
-}
-__setup("androidboot.mode=", boot_mode_init);
-
-__init void rk29_boot_mode_init_by_register(void)
-{
- u32 flag = readl(RK29_TIMER0_BASE);
- if (flag == (SYS_KERNRL_REBOOT_FLAG | BOOT_RECOVER)) {
- boot_mode = BOOT_MODE_RECOVERY;
- } else if (strstr(boot_command_line, "(parameter)")) {
- boot_mode = BOOT_MODE_RECOVERY;
- } else {
- boot_mode = readl(RK29_GRF_BASE + 0xdc); // GRF_OS_REG3
- }
- if (boot_mode)
- printk("Boot mode: %d\n", boot_mode);
-}
-
-int board_boot_mode(void)
-{
- return boot_mode;
-}
-EXPORT_SYMBOL(board_boot_mode);
-
-static int __init rk29_init_devices(void)
-{
- platform_device_register(&rk29_device_pmu);
- platform_device_register(&rk29_device_pcm);
- return 0;
-}
-arch_initcall(rk29_init_devices);
+++ /dev/null
-/* /arch/arm/mach-rk29/devices.h
- *
- * Copyright (C) 2010 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ARCH_ARM_MACH_RK29_DEVICES_H
-#define __ARCH_ARM_MACH_RK29_DEVICES_H
-
-extern struct rk29_nand_platform_data rk29_nand_data;
-#ifdef CONFIG_RK29_I2C0_CONTROLLER
-extern struct rk29_i2c_platform_data default_i2c0_data;
-#else
-extern struct i2c_gpio_platform_data default_i2c0_data;
-#endif
-#ifdef CONFIG_RK29_I2C1_CONTROLLER
-extern struct rk29_i2c_platform_data default_i2c1_data;
-#else
-extern struct i2c_gpio_platform_data default_i2c1_data;
-#endif
-#ifdef CONFIG_RK29_I2C2_CONTROLLER
-extern struct rk29_i2c_platform_data default_i2c2_data;
-#else
-extern struct i2c_gpio_platform_data default_i2c2_data;
-#endif
-#ifdef CONFIG_RK29_I2C3_CONTROLLER
-extern struct rk29_i2c_platform_data default_i2c3_data;
-#else
-extern struct i2c_gpio_platform_data default_i2c3_data;
-#endif
-
-extern struct platform_device rk29_device_i2c0;
-extern struct platform_device rk29_device_i2c1;
-extern struct platform_device rk29_device_i2c2;
-extern struct platform_device rk29_device_i2c3;
-
-extern struct platform_device rk29_device_iis_2ch;
-extern struct platform_device rk29_device_iis_8ch;
-
-extern struct platform_device rk29_device_uart0;
-extern struct platform_device rk29_device_uart1;
-extern struct platform_device rk29_device_uart2;
-extern struct platform_device rk29_device_uart3;
-extern struct platform_device rk29xx_device_spi0m;
-extern struct platform_device rk29xx_device_spi1m;
-extern struct rk29xx_spi_platform_data rk29xx_spi0_platdata;
-extern struct rk29xx_spi_platform_data rk29xx_spi1_platdata;
-extern struct platform_device rk29_device_fb;
-extern struct platform_device rk29_device_dma_cpy;
-extern struct platform_device rk29_device_nand;
-extern struct platform_device rk29xx_device_nand;
-extern struct rk29_sdmmc_platform_data default_sdmmc0_data;
-extern struct rk29_sdmmc_platform_data default_sdmmc1_data;
-extern struct platform_device rk29_device_sdmmc0;
-extern struct platform_device rk29_device_sdmmc1;
-extern struct platform_device rk29_device_adc;
-extern struct platform_device rk29_device_vmac;
-extern struct rk29_bl_info rk29_bl_info;
-extern struct rk29_button_light_info rk29_button_light_info;
-extern struct platform_device rk29_device_backlight;
-extern struct platform_device rk29_device_buttonlight;
-extern struct platform_device rk29_device_usb20_otg;
-extern struct platform_device rk29_device_usb20_host;
-extern struct platform_device rk29_device_usb11_host;
-extern struct platform_device android_usb_device;
-extern struct usb_mass_storage_platform_data mass_storage_pdata;
-extern struct platform_device usb_mass_storage_device;
-extern struct platform_device rk29_device_rndis;
-extern struct platform_device rk29_device_vmac;
-extern struct rk29_vmac_platform_data rk29_vmac_pdata;
-extern struct platform_device rk29_device_ipp;
-extern struct platform_device rk29_device_wdt;
-extern struct platform_device rk29_device_pmu;
-
-#endif
+++ /dev/null
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-
-#include <mach/rk29_iomap.h>
-#include <mach/irqs.h>
-
-#include <mach/rk29-dma-pl330.h>
-
-static u64 dma_dmamask = DMA_BIT_MASK(32);
-
-static struct resource rk29_dmac0_resource[] = {
- [0] = {
- .start = RK29_SDMAC0_PHYS,//RK29_DMAC0_PHYS,
- .end = RK29_SDMAC0_PHYS + RK29_SDMAC0_SIZE -1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_DMAC0_0,
- .end = IRQ_DMAC0_0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct rk29_pl330_platdata rk29_dmac0_pdata = {
- .peri = {
- [0] = DMACH_UART0_TX,
- [1] = DMACH_UART0_RX,
- [2] = DMACH_I2S_8CH_TX,
- [3] = DMACH_I2S_8CH_RX,
- [4] = DMACH_I2S_2CH_TX,
- [5] = DMACH_I2S_2CH_RX,
- [6] = DMACH_SPDIF,
- [7] = DMACH_MAX,
- [8] = DMACH_MAX,
- [9] = DMACH_MAX,
- [10] = DMACH_MAX,
- [11] = DMACH_MAX,
- [12] = DMACH_MAX,
- [13] = DMACH_MAX,
- [14] = DMACH_MAX,
- [15] = DMACH_MAX,
- [16] = DMACH_MAX,
- [17] = DMACH_MAX,
- [18] = DMACH_MAX,
- [19] = DMACH_MAX,
- [20] = DMACH_MAX,
- [21] = DMACH_MAX,
- [22] = DMACH_MAX,
- [23] = DMACH_MAX,
- [24] = DMACH_MAX,
- [25] = DMACH_MAX,
- [26] = DMACH_MAX,
- [27] = DMACH_MAX,
- [28] = DMACH_MAX,
- [29] = DMACH_MAX,
- [30] = DMACH_MAX,
- [31] = DMACH_MAX,
- },
-};
-
-static struct platform_device rk29_device_dmac0 = {
- .name = "rk29-pl330",
- .id = 0,
- .num_resources = ARRAY_SIZE(rk29_dmac0_resource),
- .resource = rk29_dmac0_resource,
- .dev = {
- .dma_mask = &dma_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &rk29_dmac0_pdata,
- },
-};
-
-static struct resource rk29_dmac1_resource[] = {
- [0] = {
- .start = RK29_DMAC1_PHYS,
- .end = RK29_DMAC1_PHYS + RK29_DMAC1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_DMAC1_0,
- .end = IRQ_DMAC1_0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct rk29_pl330_platdata rk29_dmac1_pdata = {
- .peri = {
- [0] = DMACH_HSADC,
- [1] = DMACH_SDMMC,
- [2] = DMACH_SDIO,
- [3] = DMACH_EMMC,
- [4] = DMACH_UART1_TX,
- [5] = DMACH_UART1_RX,
- [6] = DMACH_UART2_TX,
- [7] = DMACH_UART2_RX,
- [8] = DMACH_UART3_TX,
- [9] = DMACH_UART3_RX,
- [10] = DMACH_SPI0_TX,
- [11] = DMACH_SPI0_RX,
- [12] = DMACH_SPI1_TX,
- [13] = DMACH_SPI1_RX,
- [14] = DMACH_PID_FILTER,
- [15] = DMACH_DMAC0_MEMTOMEM,
- [16] = DMACH_MAX,
- [17] = DMACH_MAX,
- [18] = DMACH_MAX,
- [19] = DMACH_MAX,
- [20] = DMACH_MAX,
- [21] = DMACH_MAX,
- [22] = DMACH_MAX,
- [23] = DMACH_MAX,
- [24] = DMACH_MAX,
- [25] = DMACH_MAX,
- [26] = DMACH_MAX,
- [27] = DMACH_MAX,
- [28] = DMACH_MAX,
- [29] = DMACH_MAX,
- [30] = DMACH_MAX,
- [31] = DMACH_MAX,
- },
-};
-
-static struct platform_device rk29_device_dmac1 = {
- .name = "rk29-pl330",
- .id = 1,
- .num_resources = ARRAY_SIZE(rk29_dmac1_resource),
- .resource = rk29_dmac1_resource,
- .dev = {
- .dma_mask = &dma_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &rk29_dmac1_pdata,
- },
-};
-
-static struct platform_device *rk29_dmacs[] __initdata = {
- &rk29_device_dmac0,
- &rk29_device_dmac1,
-};
-
-static int __init rk29_dma_init(void)
-{
- platform_add_devices(rk29_dmacs, ARRAY_SIZE(rk29_dmacs));
-
- return 0;
-}
-arch_initcall(rk29_dma_init);
+++ /dev/null
-#include <mach/rk29_iomap.h>
-#include <mach/board.h>
-#include <mach/sram.h>
-#include <mach/iomux.h>
-#include <mach/cru.h>
-#include <asm/io.h>
-#include <mach/gpio.h>
-
-#if defined(CONFIG_RK29_I2C_INSRAM)
-
-#define I2C_SPEED 200
-
-#if defined(CONFIG_MACH_RK29_TD8801_V2)
-/******************need set when you use i2c*************************/
-#define I2C_SADDR (0x34) /* slave address ,wm8310 addr is 0x34*/
-#define SRAM_I2C_CH 1 //CH==0, i2c0,CH==1, i2c1,CH==2, i2c2,CH==3, i2c3
-#define SRAM_I2C_ADDRBASE RK29_I2C1_BASE //RK29_I2C0_BASE\RK29_I2C2_BASE\RK29_I2C3_BASE
-#define I2C_SLAVE_ADDR_LEN 1 // 2:slav addr is 10bit ,1:slav addr is 7bit
-#define I2C_SLAVE_REG_LEN 2 // 2:slav reg addr is 16 bit ,1:is 8 bit
-#define SRAM_I2C_DATA_BYTE 2 //i2c transmission data is 1bit(8wei) or 2bit(16wei)
-#define GRF_GPIO_IOMUX GRF_GPIO1L_IOMUX
-/*ch=0:GRF_GPIO2L_IOMUX,ch=1:GRF_GPIO1L_IOMUX,ch=2:GRF_GPIO5H_IOMUX,ch=3:GRF_GPIO2L_IOMUX*/
-#define I2C_GRF_GPIO_IOMUX (~(0x03<<14))&(~(0x03<<12))|(0x01<<14)|(0x01<<12)
-/*CH=0:(~(0x03<<30))&(~(0x03<<28))|(0x01<<30)|(0x01<<28),CH=1:(~(0x03<<14))&(~(0x03<<12))|(0x01<<14)|(0x01<<12),
-CH=2:(~(0x03<<24))&(~(0x03<<22))|(0x01<<24)|(0x01<<22),CH=3:(~(0x03<<26))&(~(0x03<<24))|(0x02<<26)|(0x02<<24)*/
-/***************************************/
-#if defined(SRAM_I2C_CH)
-#define CRU_CLKGATE_ADDR CRU_CLKGATE2_CON
-#define CRU_CLKGATE_BIT SRAM_I2C_CH+11
-#else
-#define CRU_CLKGATE_ADDR CRU_CLKGATE0_CON
-#define CRU_CLKGATE_BIT 26
-#endif
-//#define SRAM_I2C_ADDRBASE (RK29_I2C##SRAM_I2C_CH##_BASE )
-
-#define I2C_SLAVE_TYPE (((I2C_SLAVE_ADDR_LEN-1)<<4)|((I2C_SLAVE_REG_LEN-1)))
-
-#define uint8 unsigned char
-#define uint16 unsigned short
-#define uint32 unsigned int
-uint32 __sramdata data[5];
-
-#define CRU_CLKGATE0_CON 0x54
-#define CRU_CLKGATE2_CON 0x64
-#define CRU_CLKGATE1_CON 0x60
-
-#define CRU_CLKSEL0_CON 0x14
-#define GRF_GPIO5H_IOMUX 0x74
-#define GRF_GPIO2L_IOMUX 0x58
-#define GRF_GPIO1L_IOMUX 0x50
-
-#define I2C_ARBITR_LOSE_STATUS (1<<7) // Arbitration lose STATUS
-#define I2C_RECE_INT_MACKP (1<<1) // Master ACK period interrupt status bit
-#define I2C_RECE_INT_MACK (1) // Master receives ACK interrupt status bit
-
-#define I2C_MTXR (0x0000) /* master transmit */
-#define I2C_MRXR (0x0004) /* master receive */
-
-#define I2C_IER (0x0014) /* interrupt enable control */
-#define I2C_ISR (0x0018) /* interrupt status, write 0 to clear */
-#define I2C_LCMR (0x001c) /* stop/start/resume command, write 1 to set */
-#define I2C_LSR (0x0020) /* i2c core status */
-#define I2C_CONR (0x0024) /* i2c config */
-#define I2C_OPR (0x0028) /* i2c core config */
-#define I2C_MASTER_TRAN_MODE (1<<3)
-#define I2C_MASTER_PORT_ENABLE (1<<2)
-#define I2C_CON_NACK (1 << 4)
-#define I2C_CON_ACK (0)
-#define I2C_LCMR_RESUME (1<<2)
-#define I2C_LCMR_STOP (1<<1)
-#define I2C_LCMR_START (1<<0)
-#define SRAM_I2C_WRITE (0x0ul)
-#define SRAM_I2C_READ (0x1ul)
-#define I2C_MASTER_RECE_MODE (0)
-#define I2C_CORE_ENABLE (1<<6)
-#define I2C_CORE_DISABLE (0)
-
-#define SRAM_I2C_CLK_ENABLE() writel((~0x000000085), RK29_CRU_BASE + CRU_CLKGATE1_CON);
-#define SRAM_I2C_CLK_DISABLE() writel(~0, RK29_CRU_BASE + CRU_CLKGATE1_CON);
-#define sram_i2c_set_mode() do{ writel(0x0,SRAM_I2C_ADDRBASE + I2C_ISR);writel(0x0, SRAM_I2C_ADDRBASE + I2C_IER);writel((readl(SRAM_I2C_ADDRBASE + I2C_CONR)&(~(0x1ul<<4)))|I2C_MASTER_TRAN_MODE|I2C_MASTER_PORT_ENABLE, SRAM_I2C_ADDRBASE + I2C_CONR);}while(0)
-#define sram_udelay(usecs,a) LOOP((usecs)*LOOPS_PER_USEC)
-
-void __sramfunc sram_i2c_start(void);
-void __sramfunc sram_i2c_stop(void);
-uint8 __sramfunc sram_i2c_wait_event(void);
-uint8 __sramfunc sram_i2c_send_data(uint8 buf, uint8 startbit);
-uint8 __sramfunc sram_i2c_read_data(uint8 *buf);
-uint8 __sramfunc sram_i2c_slaveAdr(uint16 I2CSlaveAddr, uint8 addressBit, uint8 read_or_write);
-
-void __sramfunc sram_printch(char byte);
-void __sramfunc print_Hex(unsigned int hex);
-
-
-void i2c_interface_ctr_reg_pread()
-{
- readl(SRAM_I2C_ADDRBASE);
- readl(RK29_CRU_BASE);
- readl(RK29_GRF_BASE);
- readl(RK29_GPIO0_BASE);
- readl(RK29_GPIO1_BASE);
- readl(RK29_GPIO2_BASE);
- readl(RK29_GPIO3_BASE);
- readl(RK29_GPIO4_BASE);
- readl(RK29_GPIO5_BASE);
- readl(RK29_GPIO6_BASE);
-}
-
-void __sramfunc sram_i2c_delay(int delay_time)
-{
- int n = 100 * delay_time;
- while(n--)
- {
- __asm__ __volatile__("");
- }
-}
-
-
-/*-------------------------------------------------------------------------------------------------------
-Name : sram_i2c_init
-Desc : initialize the necessary registers
-Params : channel-determine which I2C bus we used
-Return : none
-------------------------------------------------------------------------------------------------------*/
-void __sramfunc sram_i2c_init()
-{
-
- //enable cru_clkgate1 clock
- data[0] = readl(RK29_CRU_BASE + CRU_CLKGATE1_CON);
- writel(data[0]&(~0x00000085), RK29_CRU_BASE + CRU_CLKGATE1_CON);
- //set the pclk
- data[1] = readl(RK29_CRU_BASE + CRU_CLKSEL0_CON);
- writel(data[1]&(~(0x07 << 5))&(~(0x03 << 10)) | (0x03 << 10), RK29_CRU_BASE + CRU_CLKSEL0_CON);
- data[2] = readl(RK29_CRU_BASE + CRU_CLKGATE_ADDR);
- writel(data[2]&(~(0x01 << CRU_CLKGATE_BIT)), RK29_CRU_BASE + CRU_CLKGATE_ADDR);
- data[3] = readl(RK29_GRF_BASE + GRF_GPIO_IOMUX);
- writel(data[3]&I2C_GRF_GPIO_IOMUX, RK29_GRF_BASE + GRF_GPIO_IOMUX);
-
-
- //reset I2c-reg base
- data[4] = readl(SRAM_I2C_ADDRBASE + I2C_OPR);
- writel(data[4] | (0x1ul << 7), SRAM_I2C_ADDRBASE + I2C_OPR);
- sram_i2c_delay(10);
- writel(data[4]&(~(0x1ul << 7)), SRAM_I2C_ADDRBASE + I2C_OPR);
- writel(0x0, SRAM_I2C_ADDRBASE + I2C_LCMR);
- //disable arq
- writel(0x0, SRAM_I2C_ADDRBASE + I2C_IER);
- writel(data[4]&(~0x03f), SRAM_I2C_ADDRBASE + I2C_OPR);
- //enable i2c core
- writel(data[4] | I2C_CORE_ENABLE , SRAM_I2C_ADDRBASE + I2C_OPR);
-}
-
-
-/*-------------------------------------------------------------------------------------------------------
-Name : sram_i2c_deinit
-Desc : de-initialize the necessary registers
-Params : noe
-Return : none
-------------------------------------------------------------------------------------------------------*/
-void __sramfunc sram_i2c_deinit(void)
-{
- SRAM_I2C_CLK_ENABLE();
- //restore i2c opr reg
- writel(data[4], SRAM_I2C_ADDRBASE + I2C_OPR);
-
- //restore iomux reg
- writel(data[3], RK29_GRF_BASE + GRF_GPIO_IOMUX);
-
- //restore cru gate2
- writel(data[2], RK29_CRU_BASE + CRU_CLKGATE_ADDR);
-
- //restore scu clock reg
- writel(data[1], RK29_CRU_BASE + CRU_CLKSEL0_CON);
-
- //restore cru gate1
- writel(data[0], RK29_CRU_BASE + CRU_CLKGATE1_CON);
-}
-
-
-/*-------------------------------------------------------------------------------------------------------
-Name : sram_i2c_start
-Desc : start i2c
-Params : none
-Return : none
-------------------------------------------------------------------------------------------------------*/
-void __sramfunc sram_i2c_start(void)
-{
- writel(I2C_LCMR_START | I2C_LCMR_RESUME, SRAM_I2C_ADDRBASE + I2C_LCMR);
-}
-
-
-/*-------------------------------------------------------------------------------------------------------
-Name : sram_i2c_stop
-Desc : stop i2c
-Params : none
-Return : none
-------------------------------------------------------------------------------------------------------*/
-void __sramfunc sram_i2c_stop(void)
-{
- writel(I2C_LCMR_STOP | I2C_LCMR_RESUME, SRAM_I2C_ADDRBASE + I2C_LCMR);
-}
-
-
-/*-------------------------------------------------------------------------------------------------------
-Name : sram_i2c_wait_event
-Desc : wait the ack
-Params : none
-Return : success: return 0; fail: return 1
-------------------------------------------------------------------------------------------------------*/
-uint8 __sramfunc sram_i2c_wait_event(void)
-{
- unsigned int isr, waiteSendDelay = 3;
-
- isr = readl(SRAM_I2C_ADDRBASE + I2C_ISR);
-
- while (waiteSendDelay > 0)
- {
- if ((isr & I2C_ARBITR_LOSE_STATUS) != 0)
- {
- writel(0x0, SRAM_I2C_ADDRBASE + I2C_ISR);
- return 1;
- }
- if ((isr & I2C_RECE_INT_MACK) != 0)
- {
- break;
- }
- sram_i2c_delay(1);
- waiteSendDelay--;
- }
- writel(isr & (~0x1ul) , SRAM_I2C_ADDRBASE + I2C_ISR);
- return 0;
-}
-
-
-/*-------------------------------------------------------------------------------------------------------
-Name : sram_i2c_send_data
-Desc : send a byte data
-Params : buf: the data we need to send;
- startbit: startbit=1, send a start signal
- startbit=0, do not send a start signal
-Return : success: return 0; fail: return 1
-------------------------------------------------------------------------------------------------------*/
-uint8 __sramfunc sram_i2c_send_data(uint8 buf, uint8 startbit)
-{
- writel(buf, SRAM_I2C_ADDRBASE + I2C_MTXR);
- readl(SRAM_I2C_ADDRBASE + I2C_LCMR);
- if(startbit)
- {
- writel(I2C_LCMR_START | I2C_LCMR_RESUME, SRAM_I2C_ADDRBASE + I2C_LCMR);
- sram_i2c_delay(50);
- }
- else
- {
- writel(I2C_LCMR_RESUME, SRAM_I2C_ADDRBASE + I2C_LCMR);
- sram_i2c_delay(50);
- }
-
- if(sram_i2c_wait_event() != 0)
- return 1;
-
- return 0;
-}
-
-
-/*-------------------------------------------------------------------------------------------------------
-Name : sram_i2c_send_data
-Desc : receive a byte data
-Params : buf: save the data we received
-Return : success: return 0; fail: return 1
-------------------------------------------------------------------------------------------------------*/
-uint8 __sramfunc sram_i2c_read_data(uint8 *buf)
-{
- unsigned int ret;
- uint8 waitDelay = 3;
-
- ret = readl(SRAM_I2C_ADDRBASE + I2C_LCMR);
- writel(ret | I2C_LCMR_RESUME, SRAM_I2C_ADDRBASE + I2C_LCMR);
-
- while(waitDelay > 0)
- {
- ret = readl(SRAM_I2C_ADDRBASE + I2C_ISR);
- if((ret & I2C_ARBITR_LOSE_STATUS) != 0)
- return 1;
-
- if((ret & I2C_RECE_INT_MACKP) != 0)
- break;
-
- waitDelay--;
- }
-
- sram_i2c_delay(50);
- *buf = (uint8)readl(SRAM_I2C_ADDRBASE + I2C_MRXR);
- ret = readl(SRAM_I2C_ADDRBASE + I2C_ISR);
- writel(ret & (~(0x1 << 1)), SRAM_I2C_ADDRBASE + I2C_ISR);
- return 0;
-}
-
-
-/*-------------------------------------------------------------------------------------------------------
-Name : sram_i2c_slaveAdr
-Desc : send the slaveAddr in 10bit mode or in 7bit mode
-Params : I2CSlaveAddr: slave address
- addressbit: high 4bits determine 7 bits or 10 bits slave address锛沴ow 4bits determine 8 bits or 16 bits regAddress
- high 4bits==7, slave address is 7 bits
- high 4bits==10,slave address is 10 bits
- low 4bits==0, slave address is 8 bits
- low 4bits==1, slave address is 16 bits
- read_or_write: read a data or write a data from salve
-Return : sucess return 0, fail return 0
-------------------------------------------------------------------------------------------------------*/
-uint8 __sramfunc sram_i2c_slaveAdr(uint16 I2CSlaveAddr, uint8 addressBit, uint8 read_or_write)
-{
- uint8 retv = 1;
-
- if((addressBit & 0xf0) == 0x10) //10bit slave address
- {
- if(sram_i2c_send_data((I2CSlaveAddr >> 7) & 0x06 | 0xf0 | read_or_write, 1) != 0)
- goto STOP;
-
- sram_i2c_delay(50);
- if(sram_i2c_send_data((I2CSlaveAddr) & 0xff | read_or_write, 0) != 0)
- goto STOP;
- }
- else //7bit slave address
- {
- if(sram_i2c_send_data((I2CSlaveAddr << 1) | read_or_write, 1) != 0)
- goto STOP;
- }
-
- retv = 0;
-
-STOP:
- //sram_i2c_stop();
- return retv;
-}
-
-
-/*-------------------------------------------------------------------------------------------------------
-Name : sram_i2c_wirte
-Desc : conduct wirte operation
-Params : I2CSlaveAddr: slave address
- regAddr: slave register address
- *pdataBuff: data we want to write
- size: number of bytes
- addressbit: high 4bits determine 7 bits or 10 bits slave address锛沴ow 4bits determine 8 bits or 16 bits regAddress
- high 4bits==7, slave address is 7 bits
- high 4bits==10,slave address is 10 bits
- low 4bits==0, slave address is 8 bits
- low 4bits==1, slave address is 16 bits
-Return : success: return 0; fail: return 1
-------------------------------------------------------------------------------------------------------*/
-uint8 __sramfunc sram_i2c_write(uint16 I2CSlaveAddr, uint16 regAddr, void *pdataBuff, uint16 size, uint8 addressBit)
-{
- unsigned int ret;
- uint8 *pdata;
- uint8 bit_if16 = (addressBit & 0x0f) ? 0x2 : 0x1;
- uint8 retv = 1;
-
- pdata = (uint8 *) pdataBuff;
-
- sram_i2c_set_mode();
-
- sram_i2c_delay(50);
- if((retv = sram_i2c_slaveAdr(I2CSlaveAddr, addressBit, SRAM_I2C_WRITE)) != 0)
- goto STOP;
- sram_i2c_delay(50);
-
- do
- {
- bit_if16--;
- if (sram_i2c_send_data((regAddr >> (bit_if16 ? 8 : 0)) & 0xff, 0) != 0)
- goto STOP;
-
- }
- while(bit_if16);
-
- sram_i2c_delay(50);
-
- do
- {
- if (sram_i2c_send_data(*pdata, 0) != 0)
- goto STOP;
- sram_i2c_delay(50);
- pdata++;
- size--;
- }
- while (size);
-
- retv = 0;
- ret = readl( SRAM_I2C_ADDRBASE + I2C_CONR);
- writel(ret | I2C_CON_NACK, SRAM_I2C_ADDRBASE + I2C_CONR);
-
-STOP:
- sram_i2c_stop();
- return retv;
-}
-
-
-/*-------------------------------------------------------------------------------------------------------
-Name : sram_i2c_read
-Desc : conduct read operation
-Params : I2CSlaveAddr: slave address
- regAddr: slave register address
- *pdataBuff: save the data master received
- size: number of bytes
- addressbit: high 4bits determine 7 bits or 10 bits slave address锛沴ow 4bits determine 8 bits or 16 bits regAddress
- high 4bits==7, slave address is 7 bits
- high 4bits==10,slave address is 10 bits
- low 4bits==0, slave address is 8 bits
- low 4bits==1, slave address is 16 bits
- mode: mode=0, NORMALMODE
- mode=1, DIRECTMODE
-Return : success: return 0; fail: return 1
-------------------------------------------------------------------------------------------------------*/
-uint8 __sramfunc sram_i2c_read(uint16 I2CSlaveAddr, uint16 regAddr, void *pdataBuff, uint16 size, uint8 addressBit)
-{
- uint8 *pdata;
- unsigned int ret;
- uint8 bit_if16 = (addressBit & 0x0f) ? 0x2 : 0x1;
- uint8 retv = 1;
-
- pdata = (uint8 *)pdataBuff;
- sram_i2c_set_mode();
- //sram_i2c_delay(50);
-
- if((retv = sram_i2c_slaveAdr(I2CSlaveAddr, addressBit, SRAM_I2C_WRITE)) != 0)
- goto STOP;
- //sram_i2c_delay(50);
-
- do
- {
- bit_if16--;
- if (sram_i2c_send_data((regAddr >> (bit_if16 ? 8 : 0)) & 0xff, 0) != 0)
- goto STOP;
- }
- while(bit_if16);
-
- sram_i2c_delay(50);
-
- if((retv = sram_i2c_slaveAdr(I2CSlaveAddr, addressBit, SRAM_I2C_READ)) != 0)
- goto STOP;
-
- writel((ret&(~(0x1 << 3))) | I2C_MASTER_RECE_MODE | I2C_MASTER_PORT_ENABLE, SRAM_I2C_ADDRBASE + I2C_CONR);
- do
- {
- ret = readl(SRAM_I2C_ADDRBASE + I2C_CONR);
- if(size == 1)
- {
- if((sram_i2c_read_data(pdata)) != 0)
- goto STOP;
- writel(ret | I2C_CON_NACK, SRAM_I2C_ADDRBASE + I2C_CONR);
- }
- else
- {
- if((sram_i2c_read_data(pdata)) != 0)
- goto STOP;
- writel(ret & (~(0x1ul << 4)) | I2C_CON_ACK, SRAM_I2C_ADDRBASE + I2C_CONR);
- }
- //sram_i2c_delay(50);
- pdata++;
- size--;
- }
- while (size);
-
- retv = 0;
-
-STOP:
- sram_i2c_stop();
- return retv;
-}
-unsigned int __sramfunc rk29_suspend_voltage_set(unsigned int vol)
-{
- uint8 slaveaddr;
- uint16 slavereg;
- unsigned int ret, mask, addr;
- uint8 data[2];
-
- sram_i2c_init(); //init i2c device
- slaveaddr = I2C_SADDR; //slave device addr
- slavereg = 0x4003; // reg addr
-
- data[0] = 0x00; //clear i2c when read
- data[1] = 0x00;
- ret = sram_i2c_read(slaveaddr, slavereg, data, SRAM_I2C_DATA_BYTE, I2C_SLAVE_TYPE);
- // print_Hex(data[0]); //read data saved in data
- // print_Hex(data[1]); //read data saved in data
- //sram_printch('\n');
-
- data[0] |= (0x1<<6); //write data
- sram_i2c_write(slaveaddr, slavereg, data, SRAM_I2C_DATA_BYTE, I2C_SLAVE_TYPE);//wm831x enter sleep mode
- sram_i2c_delay(50);
-
- sram_i2c_deinit(); //deinit i2c device
-
-}
-
-void __sramfunc rk29_suspend_voltage_resume(unsigned int vol)
-{
- uint8 slaveaddr;
- uint16 slavereg;
- unsigned int ret, mask, addr;
- uint8 data[2];
-
- sram_i2c_init(); //init i2c device
- slaveaddr = I2C_SADDR; //slave device addr
- slavereg = 0x4003; // reg addr
-
- data[0] = 0x00; //clear i2c when read
- data[1] = 0x00;
- ret = sram_i2c_read(slaveaddr, slavereg, data, SRAM_I2C_DATA_BYTE, I2C_SLAVE_TYPE);
- // print_Hex(data[0]); //read data saved in data
- // print_Hex(data[1]); //read data saved in data
- // sram_printch('\n');
-
- data[0] &= ~(0x1<<6); //write data
- sram_i2c_write(slaveaddr, slavereg, data, SRAM_I2C_DATA_BYTE, I2C_SLAVE_TYPE);//wm831x exit sleep mode
- sram_i2c_delay(50);
-
- sram_i2c_deinit(); //deinit i2c device
- // To make the system time correct after resume from suspend
- sram_udelay(100000, 24);
-
-}
-
-#endif
-#endif
-
-
+++ /dev/null
-/* arch/arm/mach-rk29/include/mach/board.h
- *
- * Copyright (C) 2010 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __ASM_ARCH_RK29_BOARD_H
-#define __ASM_ARCH_RK29_BOARD_H
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-#include <linux/types.h>
-#include <linux/timer.h>
-#include <linux/notifier.h>
-#include <plat/board.h>
-
-struct led_newton_pwm {
- const char *name;
- unsigned int pwm_id;
- unsigned pwm_gpio;
- char* pwm_iomux_name;
- unsigned int pwm_iomux_pwm;
- unsigned int pwm_iomux_gpio;
- unsigned int freq;/**/
- unsigned int period;/*1-100*/
-};
-
-struct led_newton_pwm_platform_data {
- int num_leds;
- struct led_newton_pwm* leds;
-};
-
-struct hdmi_platform_data {
- u32 hdmi_on_pin;
- u32 hdmi_on_level;
- int (*io_init)(void);
- int (*io_deinit)(void);
-};
-
-/* adc battery */
-struct rk29_adc_battery_platform_data {
- int (*io_init)(void);
- int (*io_deinit)(void);
-
- int dc_det_pin;
- int batt_low_pin;
- int charge_ok_pin;
- int charge_set_pin;
-
- int dc_det_level;
- int batt_low_level;
- int charge_ok_level;
- int charge_set_level;
-};
-
-
-struct rk29_button_light_info{
- u32 led_on_pin;
- u32 led_on_level;
- int (*io_init)(void);
- int (*io_deinit)(void);
-};
-
-#define INVALID_GPIO -1
-
-
-#ifndef _LINUX_WLAN_PLAT_H_
-struct wifi_platform_data {
- int (*set_power)(int val);
- int (*set_reset)(int val);
- int (*set_carddetect)(int val);
- void *(*mem_prealloc)(int section, unsigned long size);
- int (*get_mac_addr)(unsigned char *buf);
-};
-#endif
-
-struct rk29_i2c_platform_data {
- int bus_num;
- unsigned int flags;
- unsigned int slave_addr;
- unsigned long scl_rate;
-#define I2C_MODE_IRQ 0
-#define I2C_MODE_POLL 1
- unsigned int mode:1;
- int (*io_init)(void);
- int (*io_deinit)(void);
-};
-
-struct bq27510_platform_data {
- int (*init_dc_check_pin)(void);
- unsigned int dc_check_pin;
- unsigned int bat_num;
-};
-
-struct bq27541_platform_data {
- int (*init_dc_check_pin)(void);
- unsigned int dc_check_pin;
- unsigned int bat_check_pin;
- unsigned int chgok_check_pin;
- unsigned int bat_num;
-};
-
-/*i2s*/
-struct rk29_i2s_platform_data {
- int (*io_init)(void);
- int (*io_deinit)(void);
-};
-
-/*p1003 touch */
-struct p1003_platform_data {
- u16 model;
-
- int (*get_pendown_state)(void);
- int (*init_platform_hw)(void);
- int (*p1003_platform_sleep)(void);
- int (*p1003_platform_wakeup)(void);
- void (*exit_platform_hw)(void);
-};
-struct eeti_egalax_platform_data{
- u16 model;
-
- int (*get_pendown_state)(void);
- int (*init_platform_hw)(void);
- int (*eeti_egalax_platform_sleep)(void);
- int (*eeti_egalax_platform_wakeup)(void);
- void (*exit_platform_hw)(void);
- int standby_pin;
- int standby_value;
- int disp_on_pin;
- int disp_on_value;
-
-};
-//added by zyw
-struct atmel_1386_platform_data {
- u8 numtouch; /* Number of touches to report */
- int (*init_platform_hw)(struct device *dev);
- void (*exit_platform_hw)(struct device *dev);
- int max_x; /* The default reported X range */
- int max_y; /* The default reported Y range */
- u8 (*valid_interrupt) (void);
- u8 (*read_chg) (void);
-};
-
-/*sintex touch*/
-struct sintek_platform_data {
- u16 model;
-
- int (*get_pendown_state)(void);
- int (*init_platform_hw)(void);
- int (*sintek_platform_sleep)(void);
- int (*sintek_platform_wakeup)(void);
- void (*exit_platform_hw)(void);
-};
-
-/*synaptics touch*/
-struct synaptics_platform_data {
- u16 model;
-
- int (*get_pendown_state)(void);
- int (*init_platform_hw)(void);
- int (*sintek_platform_sleep)(void);
- int (*sintek_platform_wakeup)(void);
- void (*exit_platform_hw)(void);
-};
-
-
-struct bma023_platform_data {
- u16 model;
- u16 swap_xy;
- u16 swap_xyz;
- signed char orientation[9];
- int (*get_pendown_state)(void);
- int (*init_platform_hw)(void);
- int (*mma8452_platform_sleep)(void);
- int (*mma8452_platform_wakeup)(void);
- void (*exit_platform_hw)(void);
-};
-
-struct cm3202_platform_data {
- int CM3202_SD_IOPIN;
- int DATA_ADC_CHN;
- int (*init_platform_hw)(void);
- void (*exit_platform_hw)(void);
-};
-
-/*it7260 touch */
-struct it7260_platform_data {
- int (*get_pendown_state)(void);
- int (*init_platform_hw)(void);
- int (*it7260_platform_sleep)(void);
- int (*it7260_platform_wakeup)(void);
- void (*exit_platform_hw)(void);
-};
-
-struct ft5406_platform_data {
- int (*get_pendown_state)(void);
- int (*init_platform_hw)(void);
- int (*platform_sleep)(void);
- int (*platform_wakeup)(void);
- void (*exit_platform_hw)(void);
-};
-
-
-struct cs42l52_platform_data {
- int (*get_pendown_state)(void);
- int (*init_platform_hw)(void);
- int (*platform_sleep)(void);
- int (*platform_wakeup)(void);
- void (*exit_platform_hw)(void);
-};
-
-struct rt5625_platform_data {
- int spk_ctr_pin;
- int spk_ctr_on;
- int spk_ctr_off;
-};
-
-//tcl miaozh add
-/*nas touch */
-struct nas_platform_data {
- u16 model;
-
- int (*get_pendown_state)(void);
- int (*init_platform_hw)(void);
- int (*nas_platform_sleep)(void);
- int (*nas_platform_wakeup)(void);
- void (*exit_platform_hw)(void);
-};
-
-
-struct laibao_platform_data {
- u16 model;
-
- int (*get_pendown_state)(void);
- int (*init_platform_hw)(void);
- int (*laibao_platform_sleep)(void);
- int (*laibao_platform_wakeup)(void);
- void (*exit_platform_hw)(void);
- int pwr_pin;
- int pwr_on_value;
- int reset_pin;
- int reset_value;
-};
-
-struct rk29_newton_data {
-};
-
-struct tca6424_platform_data {
- /* the first extern gpio number in all of gpio groups */
- unsigned int gpio_base;
- unsigned int gpio_pin_num;
- /* the first gpio irq number in all of irq source */
-
- unsigned int gpio_irq_start;
- unsigned int irq_pin_num; //number of interrupt
- unsigned int tca6424_irq_pin; //rk29 gpio
- unsigned int expand_port_group;
- unsigned int expand_port_pinnum;
- unsigned int rk_irq_mode;
- unsigned int rk_irq_gpio_pull_up_down;
-
- /* initial polarity inversion setting */
- uint16_t invert;
- struct rk29_gpio_expander_info *settinginfo;
- int settinginfolen;
- void *context; /* param to setup/teardown */
-
- int (*setup)(struct i2c_client *client,unsigned gpio, unsigned ngpio,void *context);
- int (*teardown)(struct i2c_client *client,unsigned gpio, unsigned ngpio,void *context);
- char **names;
- void (*reseti2cpin)(void);
-};
-
-void __init rk29_setup_early_printk(void);
-void __init rk29_map_common_io(void);
-void __init board_power_init(void);
-
-enum periph_pll {
- periph_pll_96mhz = 96000000, /* save more power */
- periph_pll_144mhz = 144000000,
- periph_pll_288mhz = 288000000, /* for USB 1.1 */
- periph_pll_300mhz = 300000000, /* for Ethernet */
-#if defined(CONFIG_RK29_VMAC) && defined(CONFIG_USB20_HOST_EN)
- periph_pll_default = periph_pll_300mhz,
-#else
- periph_pll_default = periph_pll_288mhz,
-#endif
-};
-
-enum codec_pll {
- codec_pll_297mhz = 297000000, /* for HDMI */
- codec_pll_300mhz = 300000000,
- codec_pll_504mhz = 504000000,
- codec_pll_552mhz = 552000000,
- codec_pll_594mhz = 594000000, /* for HDMI */
- codec_pll_600mhz = 600000000,
-};
-
-void __init rk29_clock_init(enum periph_pll ppll_rate); /* codec pll is 297MHz, has xin27m */
-void __init rk29_clock_init2(enum periph_pll ppll_rate, enum codec_pll cpll_rate, bool has_xin27m);
-
-#endif
+++ /dev/null
-#ifndef __MACH_CLKDEV_H
-#define __MACH_CLKDEV_H
-
-static inline int __clk_get(struct clk *clk)
-{
- return 1;
-}
-
-static inline void __clk_put(struct clk *clk)
-{
-}
-
-#endif
+++ /dev/null
-/* arch/arm/mach-rk29/include/mach/clock.h
- *
- * Copyright (C) 2011 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ASM_ARCH_RK29_CLOCK_H
-#define __ASM_ARCH_RK29_CLOCK_H
-
-/**
- * struct clk_notifier_data - rate data to pass to the notifier callback
- * @clk: struct clk * being changed
- * @old_rate: previous rate of this clock
- * @new_rate: new rate of this clock
- *
- * For a pre-notifier, old_rate is the clock's rate before this rate
- * change, and new_rate is what the rate will be in the future. For a
- * post-notifier, old_rate and new_rate are both set to the clock's
- * current rate (this was done to optimize the implementation).
- */
-struct clk_notifier_data {
- struct clk *clk;
- unsigned long old_rate;
- unsigned long new_rate;
-};
-
-/*
- * Clk notifier callback types
- *
- * Since the notifier is called with interrupts disabled, any actions
- * taken by callbacks must be extremely fast and lightweight.
- *
- * CLK_PRE_RATE_CHANGE - called after all callbacks have approved the
- * rate change, immediately before the clock rate is changed, to
- * indicate that the rate change will proceed. Drivers must
- * immediately terminate any operations that will be affected by
- * the rate change. Callbacks must always return NOTIFY_DONE.
- *
- * CLK_ABORT_RATE_CHANGE: called if the rate change failed for some
- * reason after CLK_PRE_RATE_CHANGE. In this case, all registered
- * notifiers on the clock will be called with
- * CLK_ABORT_RATE_CHANGE. Callbacks must always return
- * NOTIFY_DONE.
- *
- * CLK_POST_RATE_CHANGE - called after the clock rate change has
- * successfully completed. Callbacks must always return
- * NOTIFY_DONE.
- *
- */
-#define CLK_PRE_RATE_CHANGE 1
-#define CLK_POST_RATE_CHANGE 2
-#define CLK_ABORT_RATE_CHANGE 3
-
-#define CLK_PRE_ENABLE 4
-#define CLK_POST_ENABLE 5
-#define CLK_ABORT_ENABLE 6
-
-#define CLK_PRE_DISABLE 7
-#define CLK_POST_DISABLE 8
-#define CLK_ABORT_DISABLE 9
-
-struct notifier_block;
-
-extern int clk_notifier_register(struct clk *clk, struct notifier_block *nb);
-extern int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb);
-
-#endif
+++ /dev/null
-/* arch/arm/mach-rk29/include/mach/cpufreq.h
- *
- * Copyright (C) 2011 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ASM_ARCH_RK29_CPUFREQ_H
-#define __ASM_ARCH_RK29_CPUFREQ_H
-
-#include <linux/cpufreq.h>
-
-/* additional symantics for "relation" in cpufreq with pm */
-#define DISABLE_FURTHER_CPUFREQ 0x10
-#define ENABLE_FURTHER_CPUFREQ 0x20
-#define MASK_FURTHER_CPUFREQ 0x30
-/* With 0x00(NOCHANGE), it depends on the previous "further" status */
-#define CPUFREQ_FORCE_CHANGE 0x40
-
-#ifdef CONFIG_CPU_FREQ
-int board_update_cpufreq_table(struct cpufreq_frequency_table *table);
-#else
-static inline int board_update_cpufreq_table(struct cpufreq_frequency_table *table) { return 0; }
-#endif
-
-#endif
+++ /dev/null
-/* arch/arm/mach-rk29/include/mach/cru.h
- *
- * Copyright (C) 2010 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ASM_ARCH_RK29_CRU_H
-#define __ASM_ARCH_RK29_CRU_H
-
-enum cru_clk_gate
-{
- /* SCU CLK GATE 0 CON */
- CLK_GATE_CORE = 0,
- CLK_GATE_PCLK_CORE,
- CLK_GATE_ATCLK_CORE,
- CLK_GATE_ACLK_CPU,
- CLK_GATE_ACLK_CPU2,
- CLK_GATE_HCLK_CPU,
- CLK_GATE_HCLK_CPU_MATRIX1,
- CLK_GATE_PCLK_CPU,
- CLK_GATE_ATCLK_CPU,
- CLK_GATE_DMA1 = 10,
- CLK_GATE_GIC,
- CLK_GATE_INTMEM,
- CLK_GATE_ROM = 14,
- CLK_GATE_I2S0,
- CLK_GATE_I2S1,
- CLK_GATE_SPDIF,
- CLK_GATE_DDR_PHY,
- CLK_GATE_DDR_REG,
- CLK_GATE_DDR_CPU,
- CLK_GATE_EFUSE,
- CLK_GATE_TZPC,
- CLK_GATE_TIMER0,
- CLK_GATE_GPIO0,
- CLK_GATE_UART0,
- CLK_GATE_I2C0,
- CLK_GATE_DEBUG,
- CLK_GATE_TPIU,
- CLK_GATE_RTC,
- CLK_GATE_PMU,
- CLK_GATE_GRF,
-
- /* SCU CLK GATE 1 CON */
- CLK_GATE_ACLK_PEIRPH = 32,
- CLK_GATE_HCLK_PEIRPH,
- CLK_GATE_PCLK_PEIRPH,
- CLK_GATE_EMEM,
- CLK_GATE_HCLK_USB_PERI,
- CLK_GATE_DMA2,
- CLK_GATE_ACLK_DDR_PERI,
- CLK_GATE_ACLK_CPU_PERI,
- CLK_GATE_ACLK_SMC,
- CLK_GATE_SMC,
- CLK_GATE_HCLK_MAC = 43,
- CLK_GATE_MAC_REF,
- CLK_GATE_MII_TX,
- CLK_GATE_MII_RX,
- CLK_GATE_HIF,
- CLK_GATE_NANDC,
- CLK_GATE_HCLK_HSADC,
- CLK_GATE_HSADC,
- CLK_GATE_HCLK_MMC0,
- CLK_GATE_MMC0,
- CLK_GATE_HCLK_MMC1,
- CLK_GATE_MMC1,
- CLK_GATE_HCLK_EMMC,
- CLK_GATE_EMMC,
- CLK_GATE_USBOTG0,
- CLK_GATE_USBPHY0,
- CLK_GATE_USBOTG1,
- CLK_GATE_USBPHY1,
- CLK_GATE_HCLK_UHOST,
- CLK_GATE_UHOST,
- CLK_GATE_PID_FILTER,
-
- /* SCU CLK GATE 2 CON */
- CLK_GATE_UART1 = 64,
- CLK_GATE_UART2,
- CLK_GATE_UART3,
- CLK_GATE_TIMER1,
- CLK_GATE_TIMER2,
- CLK_GATE_TIMER3,
- CLK_GATE_GPIO1,
- CLK_GATE_GPIO2,
- CLK_GATE_GPIO3,
- CLK_GATE_GPIO4,
- CLK_GATE_GPIO5,
- CLK_GATE_GPIO6,
- CLK_GATE_I2C1,
- CLK_GATE_I2C2,
- CLK_GATE_I2C3,
- CLK_GATE_SPI0,
- CLK_GATE_SPI1,
- CLK_GATE_VIP_SLAVE = 82,
- CLK_GATE_WDT,
- CLK_GATE_SARADC,
- CLK_GATE_PWM,
- CLK_GATE_VIP_BUS,
- CLK_GATE_VIP_MATRIX,
- CLK_GATE_VIP_OUT,
- CLK_GATE_VIP_INPUT,
- CLK_GATE_JTAG,
-
- /* CRU CLK GATE 3 CON */
- CLK_GATE_ACLK_LCDC = 96,
- CLK_GATE_ACLK_DDR_LCDC,
- CLK_GATE_HCLK_LCDC,
- CLK_GATE_DCLK_LCDC,
- CLK_GATE_ACLK_IPP,
- CLK_GATE_HCLK_IPP,
- CLK_GATE_HCLK_EBOOK,
- CLK_GATE_DCLK_EBOOK,
- CLK_GATE_ACLK_DISP_MATRIX,
- CLK_GATE_HCLK_DISP_MATRIX,
- CLK_GATE_ACLK_VEPU,
- CLK_GATE_ACLK_DDR_VEPU,
- CLK_GATE_ACLK_VDPU,
- CLK_GATE_ACLK_DDR_VDPU,
- CLK_GATE_GPU,
- CLK_GATE_ACLK_GPU,
- CLK_GATE_ACLK_DDR_GPU,
- CLK_GATE_HCLK_GPU,
- CLK_GATE_HCLK_VEPU,
- CLK_GATE_HCLK_VDPU,
- CLK_GATE_HCLK_CPU_VCODEC,
- CLK_GATE_HCLK_CPU_DISPLAY,
-
- CLK_GATE_MAX,
-};
-
-enum cru_soft_reset {
- SOFT_RST_ARM_CORE = 0,
- SOFT_RST_CPU_SYSTEM_INTERCONNECT_1_AXI,
- SOFT_RST_CPU_SYSTEM_INTERCONNECT_1_AHB,
- SOFT_RST_CPU_SYSTEM_INTERCONNECT_1_APB,
- SOFT_RST_CPU_SYSTEM_INTERCONNECT_1_ATB,
- SOFT_RST_CPU_SYSTEM_INTERCONNECT_2,
- SOFT_RST_DMA0 = 7,
- SOFT_RST_GIC,
- SOFT_RST_INTERNAL_MEMORY,
- SOFT_RST_TZPC = 11,
- SOFT_RST_ROM,
- SOFT_RST_I2S0,
- SOFT_RST_I2S1,
- SOFT_RST_SPDIF,
- SOFT_RST_UART0,
- SOFT_RST_RTC,
- SOFT_RST_DDR_PHY,
- SOFT_RST_DDR_DLL_BYTE0,
- SOFT_RST_DDR_DLL_BYTE1,
- SOFT_RST_DDR_DLL_BYTE2,
- SOFT_RST_DDR_DLL_BYTE3,
- SOFT_RST_DDR_DLL_CMD,
- SOFT_RST_DDR_CONTROLLER,
- SOFT_RST_ARM_CORE_DEBUG,
- SOFT_RST_DAP_DBG,
- SOFT_RST_CPU_VODEC_A2A_AHB,
- SOFT_RST_CPU_DISPLAY_A2A_AHB,
- SOFT_RST_DAP_SYS,
-
- SOFT_RST_PERI_SYSTEM_INTERCONNECT_1_AXI = 32,
- SOFT_RST_PERI_SYSTEM_INTERCONNECT_1_AHB,
- SOFT_RST_PERI_SYSTEM_INTERCONNECT_1_APB,
- SOFT_RST_PERIPH_EMEM = 32 + 4,
- SOFT_RST_PERIPH_USB,
- SOFT_RST_DMA1,
- SOFT_RST_MAC,
- SOFT_RST_HIF,
- SOFT_RST_NANDC,
- SOFT_RST_SMC,
- SOFT_RST_HSADC = 32 + 12,
- SOFT_RST_SDMMC,
- SOFT_RST_SDIO,
- SOFT_RST_EMMC,
- SOFT_RST_USB_OTG_2_0_AHB_BUS,
- SOFT_RST_USB_OTG_2_0_PHY,
- SOFT_RST_USB_OTG_2_0_CONTROLLER,
- SOFT_RST_USB_HOST_2_0_AHB_BUS,
- SOFT_RST_USB_HOST_2_0_PHY,
- SOFT_RST_USB_HOST_2_0_CONTROLLER,
- SOFT_RST_UHOST,
- SOFT_RST_VIP,
- SOFT_RST_VIP_MATRIX_AHB,
- SOFT_RST_SPI0,
- SOFT_RST_SPI1,
- SOFT_RST_SARADC,
- SOFT_RST_UART1,
- SOFT_RST_UART2,
- SOFT_RST_UART3,
- SOFT_RST_PWM,
-
- SOFT_RST_DISPLAY_INTERCONNECTOR_AXI = 64,
- SOFT_RST_DISPLAY_INTERCONNECTOR_AHB,
- SOFT_RST_LCDC,
- SOFT_RST_IPP,
- SOFT_RST_EBC,
- SOFT_RST_GPU = 64 + 7,
- SOFT_RST_DDR_REG_PORT,
- SOFT_RST_DDR_CPU_PORT,
- SOFT_RST_PERIPH_USED_CPU_AXI,
- SOFT_RST_DDR_PERIPH_PORT,
- SOFT_RST_DDR_LCDC_PORT,
- SOFT_RST_DDR_VCODEC_PORT = 64 + 15,
- SOFT_RST_DDR_GPU_PORT,
- SOFT_RST_PID_FILTER_AHB,
- SOFT_RST_VCODEC_AXI_BUS,
- SOFT_RST_VCODEC_AHB_BUS,
- SOFT_RST_TIMER0,
- SOFT_RST_TIMER1,
- SOFT_RST_TIMER2,
- SOFT_RST_TIMER3,
-
- SOFT_RST_MAX,
-};
-
-/* CRU MODE CON */
-#define CRU_CPU_MODE_MASK (0x03u << 0)
-#define CRU_CPU_MODE_SLOW (0x00u << 0)
-#define CRU_CPU_MODE_NORMAL (0x01u << 0)
-#define CRU_CPU_MODE_SLOW27 (0x02u << 0)
-
-#define CRU_GENERAL_MODE_MASK (0x03u << 2)
-#define CRU_GENERAL_MODE_SLOW (0x00u << 2)
-#define CRU_GENERAL_MODE_NORMAL (0x01u << 2)
-#define CRU_GENERAL_MODE_SLOW27 (0x02u << 2)
-
-#define CRU_CODEC_MODE_MASK (0x03u << 4)
-#define CRU_CODEC_MODE_SLOW (0x00u << 4)
-#define CRU_CODEC_MODE_NORMAL (0x01u << 4)
-#define CRU_CODEC_MODE_SLOW27 (0x02u << 4)
-
-#define CRU_DDR_MODE_MASK (0x03u << 6)
-#define CRU_DDR_MODE_SLOW (0x00u << 6)
-#define CRU_DDR_MODE_NORMAL (0x01u << 6)
-#define CRU_DDR_MODE_SLOW27 (0x02u << 6)
-
-/* CRU PLL CON */
-#define PLL_HIGH_BAND (0x01 << 16)
-#define PLL_LOW_BAND (0x00 << 16)
-#define PLL_PD (0x01 << 15)
-
-#define PLL_CLKR(i) ((((i) - 1) & 0x1f) << 10)
-#define PLL_NR(v) ((((v) >> 10) & 0x1f) + 1)
-
-#define PLL_CLKF(i) ((((i) - 1) & 0x7f) << 3)
-#define PLL_NF(v) ((((v) >> 3) & 0x7f) + 1)
-#define PLL_NF2(v) (((((v) >> 3) & 0x7f) + 1) << 1)
-
-#define PLL_CLKOD(i) (((i) & 0x03) << 1)
-#define PLL_NO_1 PLL_CLKOD(0)
-#define PLL_NO_2 PLL_CLKOD(1)
-#define PLL_NO_4 PLL_CLKOD(2)
-#define PLL_NO_8 PLL_CLKOD(3)
-#define PLL_NO_SHIFT(v) (((v) >> 1) & 0x03)
-
-#define PLL_BYPASS (0x01)
-
-/* Register definitions */
-#define CRU_APLL_CON 0x00
-#define CRU_DPLL_CON 0x04
-#define CRU_CPLL_CON 0x08
-#define CRU_GPLL_CON 0x0c
-#define CRU_MODE_CON 0x10
-#define CRU_CLKSEL0_CON 0x14
-#define CRU_CLKSEL1_CON 0x18
-#define CRU_CLKSEL2_CON 0x1c
-#define CRU_CLKSEL3_CON 0x20
-#define CRU_CLKSEL4_CON 0x24
-#define CRU_CLKSEL5_CON 0x28
-#define CRU_CLKSEL6_CON 0x2c
-#define CRU_CLKSEL7_CON 0x30
-#define CRU_CLKSEL8_CON 0x34
-#define CRU_CLKSEL9_CON 0x38
-#define CRU_CLKSEL10_CON 0x3c
-#define CRU_CLKSEL11_CON 0x40
-#define CRU_CLKSEL12_CON 0x44
-#define CRU_CLKSEL13_CON 0x48
-#define CRU_CLKSEL14_CON 0x4c
-#define CRU_CLKSEL15_CON 0x50
-#define CRU_CLKSEL16_CON 0x54
-#define CRU_CLKSEL17_CON 0x58
-#define CRU_CLKGATE0_CON 0x5c
-#define CRU_CLKGATE1_CON 0x60
-#define CRU_CLKGATE2_CON 0x64
-#define CRU_CLKGATE3_CON 0x68
-#define CRU_SOFTRST0_CON 0x6c
-#define CRU_SOFTRST1_CON 0x70
-#define CRU_SOFTRST2_CON 0x74
-
-#define cru_readl(offset) readl(RK29_CRU_BASE + offset)
-#define cru_writel(v, offset) do { writel(v, RK29_CRU_BASE + offset); dsb(); } while (0)
-
-extern volatile u32 cru_clkgate3_con_mirror;
-void cru_set_soft_reset(enum cru_soft_reset idx, bool on);
-
-#define LOOPS_PER_USEC 13
-#define LOOPS_PER_MSEC 12000
-#define LOOP(loops) do { unsigned int i = loops; barrier(); while (--i) barrier(); } while (0)
-
-#endif
+++ /dev/null
-/* arch/arm/mach-rk29/include/mach/ddr.h
- *
- * Copyright (C) 2011 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ARCH_ARM_MACH_RK29_DDR_H
-#define __ARCH_ARM_MACH_RK29_DDR_H
-
-#include <linux/types.h>
-#include <mach/sram.h>
-
-#ifdef CONFIG_DDR_SDRAM_FREQ
-#define DDR_FREQ (CONFIG_DDR_SDRAM_FREQ)
-#else
-#define DDR_FREQ 400
-#endif
-
-#define DDR3_800D (0) // 5-5-5
-#define DDR3_800E (1) // 6-6-6
-#define DDR3_1066E (2) // 6-6-6
-#define DDR3_1066F (3) // 7-7-7
-#define DDR3_1066G (4) // 8-8-8
-#define DDR3_1333F (5) // 7-7-7
-#define DDR3_1333G (6) // 8-8-8
-#define DDR3_1333H (7) // 9-9-9
-#define DDR3_1333J (8) // 10-10-10
-#define DDR3_1600G (9) // 8-8-8
-#define DDR3_1600H (10) // 9-9-9
-#define DDR3_1600J (11) // 10-10-10
-#define DDR3_1600K (12) // 11-11-11
-#define DDR3_1866J (13) // 10-10-10
-#define DDR3_1866K (14) // 11-11-11
-#define DDR3_1866L (15) // 12-12-12
-#define DDR3_1866M (16) // 13-13-13
-#define DDR3_2133K (17) // 11-11-11
-#define DDR3_2133L (18) // 12-12-12
-#define DDR3_2133M (19) // 13-13-13
-#define DDR3_2133N (20) // 14-14-14
-#define DDR3_DEFAULT (21)
-#define DDR_DDRII (22)
-#define DDR_LPDDR (23)
-
-
-#ifdef CONFIG_DDR_TYPE_DDR3_800D
-#define DDR_TYPE DDR3_800D
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_800E
-#define DDR_TYPE DDR3_800E
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_1066E
-#define DDR_TYPE DDR3_1066E
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_1066F
-#define DDR_TYPE DDR3_1066F
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_1066G
-#define DDR_TYPE DDR3_1066G
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_1333F
-#define DDR_TYPE DDR3_1333F
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_1333G
-#define DDR_TYPE DDR3_1333G
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_1333H
-#define DDR_TYPE DDR3_1333H
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_1333J
-#define DDR_TYPE DDR3_1333J
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_1600G
-#define DDR_TYPE DDR3_1600G
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_1600H
-#define DDR_TYPE DDR3_1600H
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_1600J
-#define DDR_TYPE DDR3_1600J
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_1866J
-#define DDR_TYPE DDR3_1866J
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_1866K
-#define DDR_TYPE DDR3_1866K
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_1866L
-#define DDR_TYPE DDR3_1866L
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_1866M
-#define DDR_TYPE DDR3_1866M
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_2133K
-#define DDR_TYPE DDR3_2133K
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_2133L
-#define DDR_TYPE DDR3_2133L
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_2133M
-#define DDR_TYPE DDR3_2133M
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_2133N
-#define DDR_TYPE DDR3_2133N
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_DEFAULT
-#define DDR_TYPE DDR3_DEFAULT
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDRII
-#define DDR_TYPE DDR_DDRII
-#endif
-
-#ifdef CONFIG_DDR_TYPE_LPDDR
-#define DDR_TYPE DDR_LPDDR
-#endif
-
-void __sramfunc ddr_suspend(void);
-void __sramfunc ddr_resume(void);
-void __sramlocalfunc delayus(uint32_t us);
-uint32_t __sramfunc ddr_change_freq(uint32_t nMHz);
-int ddr_init(uint32_t dram_type, uint32_t freq);
-#ifdef CONFIG_DDR_RECONFIG
-int rk29fb_irq_notify_ddr(void);
-#else
-static inline int rk29fb_irq_notify_ddr(void) { return 0; }
-#endif
-
-
-#endif
+++ /dev/null
-/* arch/arm/mach-rk29/include/mach/debug-macro.S
- *
- * Copyright (C) 2010 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-/* pull in the relevant register and map files. */
-
-#include <linux/version.h>
-#include <mach/rk29_iomap.h>
-
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
- .macro addruart, rp, rv
- ldr \rp, = RK29_UART1_PHYS
- ldr \rv, = RK29_UART1_BASE
- .endm
-#else
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34))
- .macro addruart, rx, tmp
-#else
- .macro addruart, rx
-#endif
- mrc p15, 0, \rx, c1, c0
- tst \rx, #1
- ldreq \rx, = RK29_UART1_PHYS
- ldrne \rx, = RK29_UART1_BASE
- .endm
-#endif
-
-#define UART_SHIFT 2
-#include <asm/hardware/debug-8250.S>
+++ /dev/null
-#include <mach/rk29-dma-pl330.h>
+++ /dev/null
-/* arch/arm/plat-samsung/include/plat/dma.h
- *
- * Copyright (C) 2003-2006 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- *
- * Samsung rk29 DMA support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-enum rk29_dma_buffresult {
- RK29_RES_OK,
- RK29_RES_ERR,
- RK29_RES_ABORT
-};
-
-enum rk29_dmasrc {
- RK29_DMASRC_HW, /* source is memory */
- RK29_DMASRC_MEM, /* source is hardware */
- RK29_DMASRC_MEMTOMEM
-};
-
-/* enum rk29_chan_op
- *
- * operation codes passed to the DMA code by the user, and also used
- * to inform the current channel owner of any changes to the system state
-*/
-
-enum rk29_chan_op {
- RK29_DMAOP_START,
- RK29_DMAOP_STOP,
- RK29_DMAOP_PAUSE,
- RK29_DMAOP_RESUME,
- RK29_DMAOP_FLUSH,
- RK29_DMAOP_TIMEOUT, /* internal signal to handler */
- RK29_DMAOP_STARTED, /* indicate channel started */
-};
-
-struct rk29_dma_client {
- char *name;
-};
-
-/* rk29_dma_cbfn_t
- *
- * buffer callback routine type
-*/
-
-typedef void (*rk29_dma_cbfn_t)(void *buf, int size,
- enum rk29_dma_buffresult result);
-
-typedef int (*rk29_dma_opfn_t)(enum rk29_chan_op );
-
-
-
-/* rk29_dma_request
- *
- * request a dma channel exclusivley
-*/
-
-extern int rk29_dma_request(unsigned int channel,
- struct rk29_dma_client *, void *dev);
-
-
-/* rk29_dma_ctrl
- *
- * change the state of the dma channel
-*/
-
-extern int rk29_dma_ctrl(unsigned int channel, enum rk29_chan_op op);
-
-/* rk29_dma_setflags
- *
- * set the channel's flags to a given state
-*/
-
-extern int rk29_dma_setflags(unsigned int channel,
- unsigned int flags);
-
-/* rk29_dma_free
- *
- * free the dma channel (will also abort any outstanding operations)
-*/
-
-extern int rk29_dma_free(unsigned int channel, struct rk29_dma_client *);
-
-/* rk29_dma_enqueue
- *
- * place the given buffer onto the queue of operations for the channel.
- * The buffer must be allocated from dma coherent memory, or the Dcache/WB
- * drained before the buffer is given to the DMA system.
-*/
-
-extern int rk29_dma_enqueue(unsigned int channel, void *id,
- dma_addr_t data, int size);
-
-/* rk29_dma_config
- *
- * configure the dma channel
-*/
-
-extern int rk29_dma_config(unsigned int channel, int xferunit, int brst_len);
-
-/* rk29_dma_devconfig
- *
- * configure the device we're talking to
-*/
-
-extern int rk29_dma_devconfig(unsigned int channel,
- enum rk29_dmasrc source, unsigned long devaddr);
-
-/* rk29_dma_getposition
- *
- * get the position that the dma transfer is currently at
-*/
-
-extern int rk29_dma_getposition(unsigned int channel,
- dma_addr_t *src, dma_addr_t *dest);
-
-extern int rk29_dma_set_opfn(unsigned int, rk29_dma_opfn_t rtn);
-extern int rk29_dma_set_buffdone_fn(unsigned int, rk29_dma_cbfn_t rtn);
-
-
+++ /dev/null
-/* arch/arm/mach-rk29/include/mach/entry-macro.S
- *
- * Copyright (C) 2010 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include "irqs.h"
-#include "rk29_iomap.h"
-#include <asm/hardware/gic.h>
-
- .macro disable_fiq
- .endm
-
- .macro get_irqnr_preamble, base, tmp
- .endm
-
- .macro arch_ret_to_user, tmp1, tmp2
- .endm /*
- * The interrupt numbering scheme is defined in the
- * interrupt controller spec. To wit:
- *
- * Interrupts 0-15 are IPI
- * 16-28 are reserved
- * 29-31 are local. We allow 30 to be used for the watchdog.
- * 32-1020 are global
- * 1021-1022 are reserved
- * 1023 is "spurious" (no interrupt)
- *
- * For now, we ignore all local interrupts so only return an
- * interrupt if it's between 30 and 1020. The test_for_ipi
- * routine below will pick up on IPIs.
- * A simple read from the controller will tell us the number
- * of the highest priority enabled interrupt.
- * We then just need to check whether it is in the
- * valid range for an IRQ (30-1020 inclusive).
- */
- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
- ldr \base, =RK29_GICCPU_BASE
- ldr \irqstat, [\base, #GIC_CPU_INTACK]
-
- ldr \tmp, =1021
-
- bic \irqnr, \irqstat, #0x1c00
-
- cmp \irqnr, #31
- cmpcc \irqnr, \irqnr
- cmpne \irqnr, \tmp
- cmpcs \irqnr, \irqnr
- .endm
-
- /* We assume that irqstat (the raw value of the IRQ acknowledge
- * register) is preserved from the macro above.
- * If there is an IPI, we immediately signal end of interrupt
- * on the controller, since this requires the original irqstat
- * value which we won't easily be able to recreate later.
- */
-
- .macro test_for_ipi, irqnr, irqstat, base, tmp
- bic \irqnr, \irqstat, #0x1c00
- cmp \irqnr, #31
- it cc
- strcc \irqstat, [\base, #GIC_CPU_EOI]
- it cs
- cmpcs \irqnr, \irqnr
- .endm
-
- /* As above, this assumes that irqstat and base are preserved */
-
- .macro test_for_ltirq, irqnr, irqstat, base, tmp
- bic \irqnr, \irqstat, #0x1c00
- mov \tmp, #0
- cmp \irqnr, #31
- itt eq
- moveq \tmp, #1
- streq \irqstat, [\base, #GIC_CPU_EOI]
- cmp \tmp, #0
- .endm
-
- .macro irq_prio_table
- .endm
+++ /dev/null
-/* arch/arm/mach-rk29/include/mach/gpio.h
- *
- * Copyright (C) 2010 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __ARCH_ARM_MACH_RK29_GPIO_H
-#define __ARCH_ARM_MACH_RK29_GPIO_H
-
-#include <mach/irqs.h>
-
-typedef enum eGPIOPinLevel
-{
- GPIO_LOW=0,
- GPIO_HIGH
-}eGPIOPinLevel_t;
-
-typedef enum eGPIOPinDirection
-{
- GPIO_IN=0,
- GPIO_OUT
-}eGPIOPinDirection_t;
-
-typedef enum GPIOPullType {
- PullDisable = 0,
- PullEnable = 1,
- GPIONormal = PullDisable,
- GPIOPullUp = 1,
- GPIOPullDown = 2,
-}eGPIOPullType_t;
-
-typedef enum GPIOIntType {
- GPIOLevelLow=0,
- GPIOLevelHigh,
- GPIOEdgelFalling,
- GPIOEdgelRising
-}eGPIOIntType_t;
-
-//¶¨ÒåGPIOÏà¹Ø¼Ä´æÆ÷Æ«ÒƵØÖ·
-#define GPIO_SWPORT_DR 0x00
-#define GPIO_SWPORT_DDR 0x04
-#define GPIO_INTEN 0x30
-#define GPIO_INTMASK 0x34
-#define GPIO_INTTYPE_LEVEL 0x38
-#define GPIO_INT_POLARITY 0x3c
-#define GPIO_INT_STATUS 0x40
-#define GPIO_INT_RAWSTATUS 0x44
-#define GPIO_DEBOUNCE 0x48
-#define GPIO_PORTS_EOI 0x4c
-#define GPIO_EXT_PORT 0x50
-#define GPIO_LS_SYNC 0x60
-
-#define RK29_ID_GPIO0 0
-#define RK29_ID_GPIO1 1
-#define RK29_ID_GPIO2 2
-#define RK29_ID_GPIO3 3
-#define RK29_ID_GPIO4 4
-#define RK29_ID_GPIO5 5
-#define RK29_ID_GPIO6 6
-
-#define NUM_GROUP 32
-#define PIN_BASE NR_AIC_IRQS
-#define MAX_BANK 7
-
-#define RK29_TOTOL_GPIO_NUM (NUM_GROUP*MAX_BANK)
-
-#define SPI_FPGA_EXPANDER_BASE (PIN_BASE+RK29_TOTOL_GPIO_NUM)
-
-#if defined (CONFIG_SPI_FPGA_GPIO)
-#define GPIO_EXPANDER_BASE (PIN_BASE+RK29_TOTOL_GPIO_NUM+CONFIG_SPI_FPGA_GPIO_NUM)
-#else
-#define GPIO_EXPANDER_BASE (PIN_BASE+RK29_TOTOL_GPIO_NUM)
-#endif
-
-#if defined(CONFIG_IOEXTEND_TCA6424)
-#define TCA6424_TOTOL_GPIO_NUM 24
-#define TCA6424_TOTOL_GPIO_IRQ_NUM 24
-#define TCA6424_GPIO_EXPANDER_BASE GPIO_EXPANDER_BASE
-#else
-#define TCA6424_TOTOL_GPIO_NUM 0
-#define TCA6424_TOTOL_GPIO_IRQ_NUM 0
-#endif
-
-#if defined(CONFIG_GPIO_WM831X)
-#define WM831X_TOTOL_GPIO_NUM 12
-#define WM831X_GPIO_EXPANDER_BASE (GPIO_EXPANDER_BASE+TCA6424_TOTOL_GPIO_NUM)
-#else
-#define WM831X_TOTOL_GPIO_NUM 0
-#define WM831X_GPIO_EXPANDER_BASE (GPIO_EXPANDER_BASE+TCA6424_TOTOL_GPIO_NUM)
-#endif
-
-#if defined (CONFIG_GPIO_WM8994)
-#define CONFIG_GPIO_WM8994_NUM 11
-#define WM8994_GPIO_EXPANDER_BASE (GPIO_EXPANDER_BASE+WM831X_TOTOL_GPIO_NUM)
-#else
-#define CONFIG_GPIO_WM8994_NUM 0
-#endif
-
-//¶¨ÒåGPIOµÄPIN¿Ú×î´óÊýÄ¿¡£CONFIG_SPI_FPGA_GPIO_NUM±íʾFPGAµÄPIN½ÅÊý¡£
-#define ARCH_NR_GPIOS (PIN_BASE + RK29_TOTOL_GPIO_NUM + TCA6424_TOTOL_GPIO_NUM + WM831X_TOTOL_GPIO_NUM + CONFIG_SPI_FPGA_GPIO_NUM+CONFIG_GPIO_WM8994_NUM)
-
-
-#define RK29_PIN0_PA0 (0*NUM_GROUP + PIN_BASE + 0)
-#define RK29_PIN0_PA1 (0*NUM_GROUP + PIN_BASE + 1)
-#define RK29_PIN0_PA2 (0*NUM_GROUP + PIN_BASE + 2)
-#define RK29_PIN0_PA3 (0*NUM_GROUP + PIN_BASE + 3)
-#define RK29_PIN0_PA4 (0*NUM_GROUP + PIN_BASE + 4)
-#define RK29_PIN0_PA5 (0*NUM_GROUP + PIN_BASE + 5)
-#define RK29_PIN0_PA6 (0*NUM_GROUP + PIN_BASE + 6)
-#define RK29_PIN0_PA7 (0*NUM_GROUP + PIN_BASE + 7)
-#define RK29_PIN0_PB0 (0*NUM_GROUP + PIN_BASE + 8)
-#define RK29_PIN0_PB1 (0*NUM_GROUP + PIN_BASE + 9)
-#define RK29_PIN0_PB2 (0*NUM_GROUP + PIN_BASE + 10)
-#define RK29_PIN0_PB3 (0*NUM_GROUP + PIN_BASE + 11)
-#define RK29_PIN0_PB4 (0*NUM_GROUP + PIN_BASE + 12)
-#define RK29_PIN0_PB5 (0*NUM_GROUP + PIN_BASE + 13)
-#define RK29_PIN0_PB6 (0*NUM_GROUP + PIN_BASE + 14)
-#define RK29_PIN0_PB7 (0*NUM_GROUP + PIN_BASE + 15)
-#define RK29_PIN0_PC0 (0*NUM_GROUP + PIN_BASE + 16)
-#define RK29_PIN0_PC1 (0*NUM_GROUP + PIN_BASE + 17)
-#define RK29_PIN0_PC2 (0*NUM_GROUP + PIN_BASE + 18)
-#define RK29_PIN0_PC3 (0*NUM_GROUP + PIN_BASE + 19)
-#define RK29_PIN0_PC4 (0*NUM_GROUP + PIN_BASE + 20)
-#define RK29_PIN0_PC5 (0*NUM_GROUP + PIN_BASE + 21)
-#define RK29_PIN0_PC6 (0*NUM_GROUP + PIN_BASE + 22)
-#define RK29_PIN0_PC7 (0*NUM_GROUP + PIN_BASE + 23)
-#define RK29_PIN0_PD0 (0*NUM_GROUP + PIN_BASE + 24)
-#define RK29_PIN0_PD1 (0*NUM_GROUP + PIN_BASE + 25)
-#define RK29_PIN0_PD2 (0*NUM_GROUP + PIN_BASE + 26)
-#define RK29_PIN0_PD3 (0*NUM_GROUP + PIN_BASE + 27)
-#define RK29_PIN0_PD4 (0*NUM_GROUP + PIN_BASE + 28)
-#define RK29_PIN0_PD5 (0*NUM_GROUP + PIN_BASE + 29)
-#define RK29_PIN0_PD6 (0*NUM_GROUP + PIN_BASE + 30)
-#define RK29_PIN0_PD7 (0*NUM_GROUP + PIN_BASE + 31)
-
-#define RK29_PIN1_PA0 (1*NUM_GROUP + PIN_BASE + 0)
-#define RK29_PIN1_PA1 (1*NUM_GROUP + PIN_BASE + 1)
-#define RK29_PIN1_PA2 (1*NUM_GROUP + PIN_BASE + 2)
-#define RK29_PIN1_PA3 (1*NUM_GROUP + PIN_BASE + 3)
-#define RK29_PIN1_PA4 (1*NUM_GROUP + PIN_BASE + 4)
-#define RK29_PIN1_PA5 (1*NUM_GROUP + PIN_BASE + 5)
-#define RK29_PIN1_PA6 (1*NUM_GROUP + PIN_BASE + 6)
-#define RK29_PIN1_PA7 (1*NUM_GROUP + PIN_BASE + 7)
-#define RK29_PIN1_PB0 (1*NUM_GROUP + PIN_BASE + 8)
-#define RK29_PIN1_PB1 (1*NUM_GROUP + PIN_BASE + 9)
-#define RK29_PIN1_PB2 (1*NUM_GROUP + PIN_BASE + 10)
-#define RK29_PIN1_PB3 (1*NUM_GROUP + PIN_BASE + 11)
-#define RK29_PIN1_PB4 (1*NUM_GROUP + PIN_BASE + 12)
-#define RK29_PIN1_PB5 (1*NUM_GROUP + PIN_BASE + 13)
-#define RK29_PIN1_PB6 (1*NUM_GROUP + PIN_BASE + 14)
-#define RK29_PIN1_PB7 (1*NUM_GROUP + PIN_BASE + 15)
-#define RK29_PIN1_PC0 (1*NUM_GROUP + PIN_BASE + 16)
-#define RK29_PIN1_PC1 (1*NUM_GROUP + PIN_BASE + 17)
-#define RK29_PIN1_PC2 (1*NUM_GROUP + PIN_BASE + 18)
-#define RK29_PIN1_PC3 (1*NUM_GROUP + PIN_BASE + 19)
-#define RK29_PIN1_PC4 (1*NUM_GROUP + PIN_BASE + 20)
-#define RK29_PIN1_PC5 (1*NUM_GROUP + PIN_BASE + 21)
-#define RK29_PIN1_PC6 (1*NUM_GROUP + PIN_BASE + 22)
-#define RK29_PIN1_PC7 (1*NUM_GROUP + PIN_BASE + 23)
-#define RK29_PIN1_PD0 (1*NUM_GROUP + PIN_BASE + 24)
-#define RK29_PIN1_PD1 (1*NUM_GROUP + PIN_BASE + 25)
-#define RK29_PIN1_PD2 (1*NUM_GROUP + PIN_BASE + 26)
-#define RK29_PIN1_PD3 (1*NUM_GROUP + PIN_BASE + 27)
-#define RK29_PIN1_PD4 (1*NUM_GROUP + PIN_BASE + 28)
-#define RK29_PIN1_PD5 (1*NUM_GROUP + PIN_BASE + 29)
-#define RK29_PIN1_PD6 (1*NUM_GROUP + PIN_BASE + 30)
-#define RK29_PIN1_PD7 (1*NUM_GROUP + PIN_BASE + 31)
-
-#define RK29_PIN2_PA0 (2*NUM_GROUP + PIN_BASE + 0)
-#define RK29_PIN2_PA1 (2*NUM_GROUP + PIN_BASE + 1)
-#define RK29_PIN2_PA2 (2*NUM_GROUP + PIN_BASE + 2)
-#define RK29_PIN2_PA3 (2*NUM_GROUP + PIN_BASE + 3)
-#define RK29_PIN2_PA4 (2*NUM_GROUP + PIN_BASE + 4)
-#define RK29_PIN2_PA5 (2*NUM_GROUP + PIN_BASE + 5)
-#define RK29_PIN2_PA6 (2*NUM_GROUP + PIN_BASE + 6)
-#define RK29_PIN2_PA7 (2*NUM_GROUP + PIN_BASE + 7)
-#define RK29_PIN2_PB0 (2*NUM_GROUP + PIN_BASE + 8)
-#define RK29_PIN2_PB1 (2*NUM_GROUP + PIN_BASE + 9)
-#define RK29_PIN2_PB2 (2*NUM_GROUP + PIN_BASE + 10)
-#define RK29_PIN2_PB3 (2*NUM_GROUP + PIN_BASE + 11)
-#define RK29_PIN2_PB4 (2*NUM_GROUP + PIN_BASE + 12)
-#define RK29_PIN2_PB5 (2*NUM_GROUP + PIN_BASE + 13)
-#define RK29_PIN2_PB6 (2*NUM_GROUP + PIN_BASE + 14)
-#define RK29_PIN2_PB7 (2*NUM_GROUP + PIN_BASE + 15)
-#define RK29_PIN2_PC0 (2*NUM_GROUP + PIN_BASE + 16)
-#define RK29_PIN2_PC1 (2*NUM_GROUP + PIN_BASE + 17)
-#define RK29_PIN2_PC2 (2*NUM_GROUP + PIN_BASE + 18)
-#define RK29_PIN2_PC3 (2*NUM_GROUP + PIN_BASE + 19)
-#define RK29_PIN2_PC4 (2*NUM_GROUP + PIN_BASE + 20)
-#define RK29_PIN2_PC5 (2*NUM_GROUP + PIN_BASE + 21)
-#define RK29_PIN2_PC6 (2*NUM_GROUP + PIN_BASE + 22)
-#define RK29_PIN2_PC7 (2*NUM_GROUP + PIN_BASE + 23)
-#define RK29_PIN2_PD0 (2*NUM_GROUP + PIN_BASE + 24)
-#define RK29_PIN2_PD1 (2*NUM_GROUP + PIN_BASE + 25)
-#define RK29_PIN2_PD2 (2*NUM_GROUP + PIN_BASE + 26)
-#define RK29_PIN2_PD3 (2*NUM_GROUP + PIN_BASE + 27)
-#define RK29_PIN2_PD4 (2*NUM_GROUP + PIN_BASE + 28)
-#define RK29_PIN2_PD5 (2*NUM_GROUP + PIN_BASE + 29)
-#define RK29_PIN2_PD6 (2*NUM_GROUP + PIN_BASE + 30)
-#define RK29_PIN2_PD7 (2*NUM_GROUP + PIN_BASE + 31)
-
-#define RK29_PIN3_PA0 (3*NUM_GROUP + PIN_BASE + 0)
-#define RK29_PIN3_PA1 (3*NUM_GROUP + PIN_BASE + 1)
-#define RK29_PIN3_PA2 (3*NUM_GROUP + PIN_BASE + 2)
-#define RK29_PIN3_PA3 (3*NUM_GROUP + PIN_BASE + 3)
-#define RK29_PIN3_PA4 (3*NUM_GROUP + PIN_BASE + 4)
-#define RK29_PIN3_PA5 (3*NUM_GROUP + PIN_BASE + 5)
-#define RK29_PIN3_PA6 (3*NUM_GROUP + PIN_BASE + 6)
-#define RK29_PIN3_PA7 (3*NUM_GROUP + PIN_BASE + 7)
-#define RK29_PIN3_PB0 (3*NUM_GROUP + PIN_BASE + 8)
-#define RK29_PIN3_PB1 (3*NUM_GROUP + PIN_BASE + 9)
-#define RK29_PIN3_PB2 (3*NUM_GROUP + PIN_BASE + 10)
-#define RK29_PIN3_PB3 (3*NUM_GROUP + PIN_BASE + 11)
-#define RK29_PIN3_PB4 (3*NUM_GROUP + PIN_BASE + 12)
-#define RK29_PIN3_PB5 (3*NUM_GROUP + PIN_BASE + 13)
-#define RK29_PIN3_PB6 (3*NUM_GROUP + PIN_BASE + 14)
-#define RK29_PIN3_PB7 (3*NUM_GROUP + PIN_BASE + 15)
-#define RK29_PIN3_PC0 (3*NUM_GROUP + PIN_BASE + 16)
-#define RK29_PIN3_PC1 (3*NUM_GROUP + PIN_BASE + 17)
-#define RK29_PIN3_PC2 (3*NUM_GROUP + PIN_BASE + 18)
-#define RK29_PIN3_PC3 (3*NUM_GROUP + PIN_BASE + 19)
-#define RK29_PIN3_PC4 (3*NUM_GROUP + PIN_BASE + 20)
-#define RK29_PIN3_PC5 (3*NUM_GROUP + PIN_BASE + 21)
-#define RK29_PIN3_PC6 (3*NUM_GROUP + PIN_BASE + 22)
-#define RK29_PIN3_PC7 (3*NUM_GROUP + PIN_BASE + 23)
-#define RK29_PIN3_PD0 (3*NUM_GROUP + PIN_BASE + 24)
-#define RK29_PIN3_PD1 (3*NUM_GROUP + PIN_BASE + 25)
-#define RK29_PIN3_PD2 (3*NUM_GROUP + PIN_BASE + 26)
-#define RK29_PIN3_PD3 (3*NUM_GROUP + PIN_BASE + 27)
-#define RK29_PIN3_PD4 (3*NUM_GROUP + PIN_BASE + 28)
-#define RK29_PIN3_PD5 (3*NUM_GROUP + PIN_BASE + 29)
-#define RK29_PIN3_PD6 (3*NUM_GROUP + PIN_BASE + 30)
-#define RK29_PIN3_PD7 (3*NUM_GROUP + PIN_BASE + 31)
-
-#define RK29_PIN4_PA0 (4*NUM_GROUP + PIN_BASE + 0)
-#define RK29_PIN4_PA1 (4*NUM_GROUP + PIN_BASE + 1)
-#define RK29_PIN4_PA2 (4*NUM_GROUP + PIN_BASE + 2)
-#define RK29_PIN4_PA3 (4*NUM_GROUP + PIN_BASE + 3)
-#define RK29_PIN4_PA4 (4*NUM_GROUP + PIN_BASE + 4)
-#define RK29_PIN4_PA5 (4*NUM_GROUP + PIN_BASE + 5)
-#define RK29_PIN4_PA6 (4*NUM_GROUP + PIN_BASE + 6)
-#define RK29_PIN4_PA7 (4*NUM_GROUP + PIN_BASE + 7)
-#define RK29_PIN4_PB0 (4*NUM_GROUP + PIN_BASE + 8)
-#define RK29_PIN4_PB1 (4*NUM_GROUP + PIN_BASE + 9)
-#define RK29_PIN4_PB2 (4*NUM_GROUP + PIN_BASE + 10)
-#define RK29_PIN4_PB3 (4*NUM_GROUP + PIN_BASE + 11)
-#define RK29_PIN4_PB4 (4*NUM_GROUP + PIN_BASE + 12)
-#define RK29_PIN4_PB5 (4*NUM_GROUP + PIN_BASE + 13)
-#define RK29_PIN4_PB6 (4*NUM_GROUP + PIN_BASE + 14)
-#define RK29_PIN4_PB7 (4*NUM_GROUP + PIN_BASE + 15)
-#define RK29_PIN4_PC0 (4*NUM_GROUP + PIN_BASE + 16)
-#define RK29_PIN4_PC1 (4*NUM_GROUP + PIN_BASE + 17)
-#define RK29_PIN4_PC2 (4*NUM_GROUP + PIN_BASE + 18)
-#define RK29_PIN4_PC3 (4*NUM_GROUP + PIN_BASE + 19)
-#define RK29_PIN4_PC4 (4*NUM_GROUP + PIN_BASE + 20)
-#define RK29_PIN4_PC5 (4*NUM_GROUP + PIN_BASE + 21)
-#define RK29_PIN4_PC6 (4*NUM_GROUP + PIN_BASE + 22)
-#define RK29_PIN4_PC7 (4*NUM_GROUP + PIN_BASE + 23)
-#define RK29_PIN4_PD0 (4*NUM_GROUP + PIN_BASE + 24)
-#define RK29_PIN4_PD1 (4*NUM_GROUP + PIN_BASE + 25)
-#define RK29_PIN4_PD2 (4*NUM_GROUP + PIN_BASE + 26)
-#define RK29_PIN4_PD3 (4*NUM_GROUP + PIN_BASE + 27)
-#define RK29_PIN4_PD4 (4*NUM_GROUP + PIN_BASE + 28)
-#define RK29_PIN4_PD5 (4*NUM_GROUP + PIN_BASE + 29)
-#define RK29_PIN4_PD6 (4*NUM_GROUP + PIN_BASE + 30)
-#define RK29_PIN4_PD7 (4*NUM_GROUP + PIN_BASE + 31)
-
-#define RK29_PIN5_PA0 (5*NUM_GROUP + PIN_BASE + 0)
-#define RK29_PIN5_PA1 (5*NUM_GROUP + PIN_BASE + 1)
-#define RK29_PIN5_PA2 (5*NUM_GROUP + PIN_BASE + 2)
-#define RK29_PIN5_PA3 (5*NUM_GROUP + PIN_BASE + 3)
-#define RK29_PIN5_PA4 (5*NUM_GROUP + PIN_BASE + 4)
-#define RK29_PIN5_PA5 (5*NUM_GROUP + PIN_BASE + 5)
-#define RK29_PIN5_PA6 (5*NUM_GROUP + PIN_BASE + 6)
-#define RK29_PIN5_PA7 (5*NUM_GROUP + PIN_BASE + 7)
-#define RK29_PIN5_PB0 (5*NUM_GROUP + PIN_BASE + 8)
-#define RK29_PIN5_PB1 (5*NUM_GROUP + PIN_BASE + 9)
-#define RK29_PIN5_PB2 (5*NUM_GROUP + PIN_BASE + 10)
-#define RK29_PIN5_PB3 (5*NUM_GROUP + PIN_BASE + 11)
-#define RK29_PIN5_PB4 (5*NUM_GROUP + PIN_BASE + 12)
-#define RK29_PIN5_PB5 (5*NUM_GROUP + PIN_BASE + 13)
-#define RK29_PIN5_PB6 (5*NUM_GROUP + PIN_BASE + 14)
-#define RK29_PIN5_PB7 (5*NUM_GROUP + PIN_BASE + 15)
-#define RK29_PIN5_PC0 (5*NUM_GROUP + PIN_BASE + 16)
-#define RK29_PIN5_PC1 (5*NUM_GROUP + PIN_BASE + 17)
-#define RK29_PIN5_PC2 (5*NUM_GROUP + PIN_BASE + 18)
-#define RK29_PIN5_PC3 (5*NUM_GROUP + PIN_BASE + 19)
-#define RK29_PIN5_PC4 (5*NUM_GROUP + PIN_BASE + 20)
-#define RK29_PIN5_PC5 (5*NUM_GROUP + PIN_BASE + 21)
-#define RK29_PIN5_PC6 (5*NUM_GROUP + PIN_BASE + 22)
-#define RK29_PIN5_PC7 (5*NUM_GROUP + PIN_BASE + 23)
-#define RK29_PIN5_PD0 (5*NUM_GROUP + PIN_BASE + 24)
-#define RK29_PIN5_PD1 (5*NUM_GROUP + PIN_BASE + 25)
-#define RK29_PIN5_PD2 (5*NUM_GROUP + PIN_BASE + 26)
-#define RK29_PIN5_PD3 (5*NUM_GROUP + PIN_BASE + 27)
-#define RK29_PIN5_PD4 (5*NUM_GROUP + PIN_BASE + 28)
-#define RK29_PIN5_PD5 (5*NUM_GROUP + PIN_BASE + 29)
-#define RK29_PIN5_PD6 (5*NUM_GROUP + PIN_BASE + 30)
-#define RK29_PIN5_PD7 (5*NUM_GROUP + PIN_BASE + 31)
-
-#define RK29_PIN6_PA0 (6*NUM_GROUP + PIN_BASE + 0)
-#define RK29_PIN6_PA1 (6*NUM_GROUP + PIN_BASE + 1)
-#define RK29_PIN6_PA2 (6*NUM_GROUP + PIN_BASE + 2)
-#define RK29_PIN6_PA3 (6*NUM_GROUP + PIN_BASE + 3)
-#define RK29_PIN6_PA4 (6*NUM_GROUP + PIN_BASE + 4)
-#define RK29_PIN6_PA5 (6*NUM_GROUP + PIN_BASE + 5)
-#define RK29_PIN6_PA6 (6*NUM_GROUP + PIN_BASE + 6)
-#define RK29_PIN6_PA7 (6*NUM_GROUP + PIN_BASE + 7)
-#define RK29_PIN6_PB0 (6*NUM_GROUP + PIN_BASE + 8)
-#define RK29_PIN6_PB1 (6*NUM_GROUP + PIN_BASE + 9)
-#define RK29_PIN6_PB2 (6*NUM_GROUP + PIN_BASE + 10)
-#define RK29_PIN6_PB3 (6*NUM_GROUP + PIN_BASE + 11)
-#define RK29_PIN6_PB4 (6*NUM_GROUP + PIN_BASE + 12)
-#define RK29_PIN6_PB5 (6*NUM_GROUP + PIN_BASE + 13)
-#define RK29_PIN6_PB6 (6*NUM_GROUP + PIN_BASE + 14)
-#define RK29_PIN6_PB7 (6*NUM_GROUP + PIN_BASE + 15)
-#define RK29_PIN6_PC0 (6*NUM_GROUP + PIN_BASE + 16)
-#define RK29_PIN6_PC1 (6*NUM_GROUP + PIN_BASE + 17)
-#define RK29_PIN6_PC2 (6*NUM_GROUP + PIN_BASE + 18)
-#define RK29_PIN6_PC3 (6*NUM_GROUP + PIN_BASE + 19)
-#define RK29_PIN6_PC4 (6*NUM_GROUP + PIN_BASE + 20)
-#define RK29_PIN6_PC5 (6*NUM_GROUP + PIN_BASE + 21)
-#define RK29_PIN6_PC6 (6*NUM_GROUP + PIN_BASE + 22)
-#define RK29_PIN6_PC7 (6*NUM_GROUP + PIN_BASE + 23)
-#define RK29_PIN6_PD0 (6*NUM_GROUP + PIN_BASE + 24)
-#define RK29_PIN6_PD1 (6*NUM_GROUP + PIN_BASE + 25)
-#define RK29_PIN6_PD2 (6*NUM_GROUP + PIN_BASE + 26)
-#define RK29_PIN6_PD3 (6*NUM_GROUP + PIN_BASE + 27)
-#define RK29_PIN6_PD4 (6*NUM_GROUP + PIN_BASE + 28)
-#define RK29_PIN6_PD5 (6*NUM_GROUP + PIN_BASE + 29)
-#define RK29_PIN6_PD6 (6*NUM_GROUP + PIN_BASE + 30)
-#define RK29_PIN6_PD7 (6*NUM_GROUP + PIN_BASE + 31)
-
-#if defined(CONFIG_SPI_FPGA_GPIO)
-#define FPGA_PIO0_00 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 0)
-#define FPGA_PIO0_01 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 1)
-#define FPGA_PIO0_02 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 2)
-#define FPGA_PIO0_03 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 3)
-#define FPGA_PIO0_04 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 4)
-#define FPGA_PIO0_05 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 5)
-#define FPGA_PIO0_06 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 6)
-#define FPGA_PIO0_07 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 7)
-
-#define FPGA_PIO0_08 (SPI_FPGA_EXPANDER_BASE + 1*NUM_GROUP + 0)
-#define FPGA_PIO0_09 (SPI_FPGA_EXPANDER_BASE + 1*NUM_GROUP + 1)
-#define FPGA_PIO0_10 (SPI_FPGA_EXPANDER_BASE + 1*NUM_GROUP + 2)
-#define FPGA_PIO0_11 (SPI_FPGA_EXPANDER_BASE + 1*NUM_GROUP + 3)
-#define FPGA_PIO0_12 (SPI_FPGA_EXPANDER_BASE + 1*NUM_GROUP + 4)
-#define FPGA_PIO0_13 (SPI_FPGA_EXPANDER_BASE + 1*NUM_GROUP + 5)
-#define FPGA_PIO0_14 (SPI_FPGA_EXPANDER_BASE + 1*NUM_GROUP + 6)
-#define FPGA_PIO0_15 (SPI_FPGA_EXPANDER_BASE + 1*NUM_GROUP + 7)
-
-#define FPGA_PIO1_00 (SPI_FPGA_EXPANDER_BASE + 2*NUM_GROUP + 0)
-#define FPGA_PIO1_01 (SPI_FPGA_EXPANDER_BASE + 2*NUM_GROUP + 1)
-#define FPGA_PIO1_02 (SPI_FPGA_EXPANDER_BASE + 2*NUM_GROUP + 2)
-#define FPGA_PIO1_03 (SPI_FPGA_EXPANDER_BASE + 2*NUM_GROUP + 3)
-#define FPGA_PIO1_04 (SPI_FPGA_EXPANDER_BASE + 2*NUM_GROUP + 4)
-#define FPGA_PIO1_05 (SPI_FPGA_EXPANDER_BASE + 2*NUM_GROUP + 5)
-#define FPGA_PIO1_06 (SPI_FPGA_EXPANDER_BASE + 2*NUM_GROUP + 6)
-#define FPGA_PIO1_07 (SPI_FPGA_EXPANDER_BASE + 2*NUM_GROUP + 7)
-
-#define FPGA_PIO1_08 (SPI_FPGA_EXPANDER_BASE + 3*NUM_GROUP + 0)
-#define FPGA_PIO1_09 (SPI_FPGA_EXPANDER_BASE + 3*NUM_GROUP + 1)
-#define FPGA_PIO1_10 (SPI_FPGA_EXPANDER_BASE + 3*NUM_GROUP + 2)
-#define FPGA_PIO1_11 (SPI_FPGA_EXPANDER_BASE + 3*NUM_GROUP + 3)
-#define FPGA_PIO1_12 (SPI_FPGA_EXPANDER_BASE + 3*NUM_GROUP + 4)
-#define FPGA_PIO1_13 (SPI_FPGA_EXPANDER_BASE + 3*NUM_GROUP + 5)
-#define FPGA_PIO1_14 (SPI_FPGA_EXPANDER_BASE + 3*NUM_GROUP + 6)
-#define FPGA_PIO1_15 (SPI_FPGA_EXPANDER_BASE + 3*NUM_GROUP + 7)
-
-#define FPGA_PIO2_00 (SPI_FPGA_EXPANDER_BASE + 4*NUM_GROUP + 0)
-#define FPGA_PIO2_01 (SPI_FPGA_EXPANDER_BASE + 4*NUM_GROUP + 1)
-#define FPGA_PIO2_02 (SPI_FPGA_EXPANDER_BASE + 4*NUM_GROUP + 2)
-#define FPGA_PIO2_03 (SPI_FPGA_EXPANDER_BASE + 4*NUM_GROUP + 3)
-#define FPGA_PIO2_04 (SPI_FPGA_EXPANDER_BASE + 4*NUM_GROUP + 4)
-#define FPGA_PIO2_05 (SPI_FPGA_EXPANDER_BASE + 4*NUM_GROUP + 5)
-#define FPGA_PIO2_06 (SPI_FPGA_EXPANDER_BASE + 4*NUM_GROUP + 6)
-#define FPGA_PIO2_07 (SPI_FPGA_EXPANDER_BASE + 4*NUM_GROUP + 7)
-
-#define FPGA_PIO2_08 (SPI_FPGA_EXPANDER_BASE + 5*NUM_GROUP + 0)
-#define FPGA_PIO2_09 (SPI_FPGA_EXPANDER_BASE + 5*NUM_GROUP + 1)
-#define FPGA_PIO2_10 (SPI_FPGA_EXPANDER_BASE + 5*NUM_GROUP + 2)
-#define FPGA_PIO2_11 (SPI_FPGA_EXPANDER_BASE + 5*NUM_GROUP + 3)
-#define FPGA_PIO2_12 (SPI_FPGA_EXPANDER_BASE + 5*NUM_GROUP + 4)
-#define FPGA_PIO2_13 (SPI_FPGA_EXPANDER_BASE + 5*NUM_GROUP + 5)
-#define FPGA_PIO2_14 (SPI_FPGA_EXPANDER_BASE + 5*NUM_GROUP + 6)
-#define FPGA_PIO2_15 (SPI_FPGA_EXPANDER_BASE + 5*NUM_GROUP + 7)
-
-#define FPGA_PIO3_00 (SPI_FPGA_EXPANDER_BASE + 6*NUM_GROUP + 0)
-#define FPGA_PIO3_01 (SPI_FPGA_EXPANDER_BASE + 6*NUM_GROUP + 1)
-#define FPGA_PIO3_02 (SPI_FPGA_EXPANDER_BASE + 6*NUM_GROUP + 2)
-#define FPGA_PIO3_03 (SPI_FPGA_EXPANDER_BASE + 6*NUM_GROUP + 3)
-#define FPGA_PIO3_04 (SPI_FPGA_EXPANDER_BASE + 6*NUM_GROUP + 4)
-#define FPGA_PIO3_05 (SPI_FPGA_EXPANDER_BASE + 6*NUM_GROUP + 5)
-#define FPGA_PIO3_06 (SPI_FPGA_EXPANDER_BASE + 6*NUM_GROUP + 6)
-#define FPGA_PIO3_07 (SPI_FPGA_EXPANDER_BASE + 6*NUM_GROUP + 7)
-
-#define FPGA_PIO3_08 (SPI_FPGA_EXPANDER_BASE + 7*NUM_GROUP + 0)
-#define FPGA_PIO3_09 (SPI_FPGA_EXPANDER_BASE + 7*NUM_GROUP + 1)
-#define FPGA_PIO3_10 (SPI_FPGA_EXPANDER_BASE + 7*NUM_GROUP + 2)
-#define FPGA_PIO3_11 (SPI_FPGA_EXPANDER_BASE + 7*NUM_GROUP + 3)
-#define FPGA_PIO3_12 (SPI_FPGA_EXPANDER_BASE + 7*NUM_GROUP + 4)
-#define FPGA_PIO3_13 (SPI_FPGA_EXPANDER_BASE + 7*NUM_GROUP + 5)
-#define FPGA_PIO3_14 (SPI_FPGA_EXPANDER_BASE + 7*NUM_GROUP + 6)
-#define FPGA_PIO3_15 (SPI_FPGA_EXPANDER_BASE + 7*NUM_GROUP + 7)
-
-#define FPGA_PIO4_00 (SPI_FPGA_EXPANDER_BASE + 8*NUM_GROUP + 0)
-#define FPGA_PIO4_01 (SPI_FPGA_EXPANDER_BASE + 8*NUM_GROUP + 1)
-#define FPGA_PIO4_02 (SPI_FPGA_EXPANDER_BASE + 8*NUM_GROUP + 2)
-#define FPGA_PIO4_03 (SPI_FPGA_EXPANDER_BASE + 8*NUM_GROUP + 3)
-#define FPGA_PIO4_04 (SPI_FPGA_EXPANDER_BASE + 8*NUM_GROUP + 4)
-#define FPGA_PIO4_05 (SPI_FPGA_EXPANDER_BASE + 8*NUM_GROUP + 5)
-#define FPGA_PIO4_06 (SPI_FPGA_EXPANDER_BASE + 8*NUM_GROUP + 6)
-#define FPGA_PIO4_07 (SPI_FPGA_EXPANDER_BASE + 8*NUM_GROUP + 7)
-
-#define FPGA_PIO4_08 (SPI_FPGA_EXPANDER_BASE + 9*NUM_GROUP + 0)
-#define FPGA_PIO4_09 (SPI_FPGA_EXPANDER_BASE + 9*NUM_GROUP + 1)
-#define FPGA_PIO4_10 (SPI_FPGA_EXPANDER_BASE + 9*NUM_GROUP + 2)
-#define FPGA_PIO4_11 (SPI_FPGA_EXPANDER_BASE + 9*NUM_GROUP + 3)
-#define FPGA_PIO4_12 (SPI_FPGA_EXPANDER_BASE + 9*NUM_GROUP + 4)
-#define FPGA_PIO4_13 (SPI_FPGA_EXPANDER_BASE + 9*NUM_GROUP + 5)
-#define FPGA_PIO4_14 (SPI_FPGA_EXPANDER_BASE + 9*NUM_GROUP + 6)
-#define FPGA_PIO4_15 (SPI_FPGA_EXPANDER_BASE + 9*NUM_GROUP + 7)
-
-#define FPGA_PIO5_00 (SPI_FPGA_EXPANDER_BASE + 10*NUM_GROUP + 0)
-#define FPGA_PIO5_01 (SPI_FPGA_EXPANDER_BASE + 10*NUM_GROUP + 1)
-#define FPGA_PIO5_02 (SPI_FPGA_EXPANDER_BASE + 10*NUM_GROUP + 2)
-#define FPGA_PIO5_03 (SPI_FPGA_EXPANDER_BASE + 10*NUM_GROUP + 3)
-#define FPGA_PIO5_04 (SPI_FPGA_EXPANDER_BASE + 10*NUM_GROUP + 4)
-#define FPGA_PIO5_05 (SPI_FPGA_EXPANDER_BASE + 10*NUM_GROUP + 5)
-#define FPGA_PIO5_06 (SPI_FPGA_EXPANDER_BASE + 10*NUM_GROUP + 6)
-#define FPGA_PIO5_07 (SPI_FPGA_EXPANDER_BASE + 10*NUM_GROUP + 7)
-
-#define FPGA_PIO5_08 (SPI_FPGA_EXPANDER_BASE + 11*NUM_GROUP + 0)
-#define FPGA_PIO5_09 (SPI_FPGA_EXPANDER_BASE + 11*NUM_GROUP + 1)
-#define FPGA_PIO5_10 (SPI_FPGA_EXPANDER_BASE + 11*NUM_GROUP + 2)
-#define FPGA_PIO5_11 (SPI_FPGA_EXPANDER_BASE + 11*NUM_GROUP + 3)
-#define FPGA_PIO5_12 (SPI_FPGA_EXPANDER_BASE + 11*NUM_GROUP + 4)
-#define FPGA_PIO5_13 (SPI_FPGA_EXPANDER_BASE + 11*NUM_GROUP + 5)
-#define FPGA_PIO5_14 (SPI_FPGA_EXPANDER_BASE + 11*NUM_GROUP + 6)
-#define FPGA_PIO5_15 (SPI_FPGA_EXPANDER_BASE + 11*NUM_GROUP + 7)
-
-#endif
-
-#if defined(CONFIG_IOEXTEND_TCA6424)
-#define TCA6424_P00 (TCA6424_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 0)
-#define TCA6424_P01 (TCA6424_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 1)
-#define TCA6424_P02 (TCA6424_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 2)
-#define TCA6424_P03 (TCA6424_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 3)
-#define TCA6424_P04 (TCA6424_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 4)
-#define TCA6424_P05 (TCA6424_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 5)
-#define TCA6424_P06 (TCA6424_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 6)
-#define TCA6424_P07 (TCA6424_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 7)
-
-#define TCA6424_P10 (TCA6424_GPIO_EXPANDER_BASE + 1*NUM_GROUP + 0)
-#define TCA6424_P11 (TCA6424_GPIO_EXPANDER_BASE + 1*NUM_GROUP + 1)
-#define TCA6424_P12 (TCA6424_GPIO_EXPANDER_BASE + 1*NUM_GROUP + 2)
-#define TCA6424_P13 (TCA6424_GPIO_EXPANDER_BASE + 1*NUM_GROUP + 3)
-#define TCA6424_P14 (TCA6424_GPIO_EXPANDER_BASE + 1*NUM_GROUP + 4)
-#define TCA6424_P15 (TCA6424_GPIO_EXPANDER_BASE + 1*NUM_GROUP + 5)
-#define TCA6424_P16 (TCA6424_GPIO_EXPANDER_BASE + 1*NUM_GROUP + 6)
-#define TCA6424_P17 (TCA6424_GPIO_EXPANDER_BASE + 1*NUM_GROUP + 7)
-
-#define TCA6424_P20 (TCA6424_GPIO_EXPANDER_BASE + 2*NUM_GROUP + 0)
-#define TCA6424_P21 (TCA6424_GPIO_EXPANDER_BASE + 2*NUM_GROUP + 1)
-#define TCA6424_P22 (TCA6424_GPIO_EXPANDER_BASE + 2*NUM_GROUP + 2)
-#define TCA6424_P23 (TCA6424_GPIO_EXPANDER_BASE + 2*NUM_GROUP + 3)
-#define TCA6424_P24 (TCA6424_GPIO_EXPANDER_BASE + 2*NUM_GROUP + 4)
-#define TCA6424_P25 (TCA6424_GPIO_EXPANDER_BASE + 2*NUM_GROUP + 5)
-#define TCA6424_P26 (TCA6424_GPIO_EXPANDER_BASE + 2*NUM_GROUP + 6)
-#define TCA6424_P27 (TCA6424_GPIO_EXPANDER_BASE + 2*NUM_GROUP + 7)
-#endif
-
-#if defined(CONFIG_GPIO_WM831X)
-#define WM831X_P01 (WM831X_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 0)
-#define WM831X_P02 (WM831X_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 1)
-#define WM831X_P03 (WM831X_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 2)
-#define WM831X_P04 (WM831X_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 3)
-#define WM831X_P05 (WM831X_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 4)
-#define WM831X_P06 (WM831X_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 5)
-#define WM831X_P07 (WM831X_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 6)
-#define WM831X_P08 (WM831X_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 7)
-
-#define WM831X_P09 (WM831X_GPIO_EXPANDER_BASE + 1*NUM_GROUP + 0)
-#define WM831X_P10 (WM831X_GPIO_EXPANDER_BASE + 1*NUM_GROUP + 1)
-#define WM831X_P11 (WM831X_GPIO_EXPANDER_BASE + 1*NUM_GROUP + 2)
-#define WM831X_P12 (WM831X_GPIO_EXPANDER_BASE + 1*NUM_GROUP + 3)
-#endif
-
-#ifndef __ASSEMBLY__
-extern void __init rk29_gpio_init(void);
-/*-------------------------------------------------------------------------*/
-
-/* wrappers for "new style" GPIO calls. the old RK2818-specfic ones should
- * eventually be removed (along with this errno.h inclusion), and the
- * gpio request/free calls should probably be implemented.
- */
-
-#include <asm/errno.h>
-#include <asm-generic/gpio.h> /* cansleep wrappers */
-
-#define gpio_get_value __gpio_get_value
-#define gpio_set_value __gpio_set_value
-#define gpio_cansleep __gpio_cansleep
-
-static inline int gpio_to_irq(unsigned gpio)
-{
- return gpio - PIN_BASE + NR_AIC_IRQS;
-}
-
-static inline int irq_to_gpio(unsigned irq)
-{
- return irq - NR_AIC_IRQS + PIN_BASE;
-}
-
-#endif /* __ASSEMBLY__ */
-
-#endif
+++ /dev/null
-/* arch/arm/mach-rk29/include/mach/hardware.h
- *
- * Copyright (C) 2010 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ASM_ARCH_RK29_HARDWARE_H
-
-
-#ifndef __ASSEMBLY__
-# define __REG(x) (*((volatile u32 *)IO_ADDRESS(x)))
-
-# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y)))
-#endif
-
-#endif
+++ /dev/null
-/* arch/arm/mach-rk29/include/mach/io.h
- *
- * Copyright (C) 2010 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-#define __io(a) __typesafe_io(a)
-#define __mem_pci(a) (a)
-
-#include <mach/rk29_iomap.h>
-
-#endif
+++ /dev/null
-/*
- * arch/arm/mach-rk29/include/mach/iomux.h
- *
- *Copyright (C) 2010 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __RK29_IOMUX_H__
-#define __RK29_IOMUX_H__
-
-#include "rk29_iomap.h"
-///GPIO0L
-#define GPIO0L_GPIO0B7 0
-#define GPIO0L_EBC_GDOE 1
-#define GPIO0L_SMC_OE_N 2
-#define GPIO0L_GPIO0B6 0
-#define GPIO0L_EBC_SDSHR 1
-#define GPIO0L_SMC_BLS_N_1 2
-#define GPIO0L_HOST_INT 3
-#define GPIO0L_GPIO0B5 0
-#define GPIO0L_EBC_VCOM 1
-#define GPIO0L_SMC_BLS_N_0 2
-#define GPIO0L_GPIO0B4 0
-#define GPIO0L_EBC_BORDER1 1
-#define GPIO0L_SMC_WE_N 2
-#define GPIO0L_GPIO0B3 0
-#define GPIO0L_EBC_BORDER0 1
-#define GPIO0L_SMC_ADDR3 2
-#define GPIO0L_HOST_DATA3 3
-#define GPIO0L_GPIO0B2 0
-#define GPIO0L_EBC_SDCE2 1
-#define GPIO0L_SMC_ADDR2 2
-#define GPIO0L_HOST_DATA2 3
-#define GPIO0L_GPIO0B1 0
-#define GPIO0L_EBC_SDCE1 1
-#define GPIO0L_SMC_ADDR1 2
-#define GPIO0L_HOST_DATA1 3
-#define GPIO0L_GPIO0B0 0
-#define GPIO0L_EBC_SDCE0 1
-#define GPIO0L_SMC_ADDR0 2
-#define GPIO0L_HOST_DATA0 3
-#define GPIO0L_GPIO0A7 0
-#define GPIO0L_MII_MDCLK 1
-#define GPIO0L_GPIO0A6 0
-#define GPIO0L_MII_MD 1
-#define GPIO0L_GPIO0A5 0
-#define GPIO0L_FLASH_DQS 1
-
-///GPIO0H
-#define GPIO0H_GPIO0D7 0
-#define GPIO0H_FLASH_CSN6 1
-#define GPIO0H_GPIO0D6 0
-#define GPIO0H_FLASH_CSN5 1
-#define GPIO0H_GPIO0D5 0
-#define GPIO0H_FLASH_CSN4 1
-#define GPIO0H_GPIO0D4 0
-#define GPIO0H_FLASH_CSN3 1
-#define GPIO0H_GPIO0D3 0
-#define GPIO0H_FLASH_CSN2 1
-#define GPIO0H_GPIO0D2 0
-#define GPIO0H_FLASH_CSN1 1
-#define GPIO0H_GPIO0D1 0
-#define GPIO0H_EBC_GDCLK 1
-#define GPIO0H_SMC_ADDR4 2
-#define GPIO0H_HOST_DATA4 3
-#define GPIO0H_GPIO0D0 0
-#define GPIO0H_EBC_SDOE 1
-#define GPIO0H_SMC_ADV_N 2
-#define GPIO0H_GPIO0C7 0
-#define GPIO0H_EBC_SDCE5 1
-#define GPIO0H_SMC_DATA15 2
-#define GPIO0H_GPIO0C6 0
-#define GPIO0H_EBC_SDCE4 1
-#define GPIO0H_SMC_DATA14 2
-#define GPIO0H_GPIO0C5 0
-#define GPIO0H_EBC_SDCE3 1
-#define GPIO0H_SMC_DATA13 2
-#define GPIO0H_GPIO0C4 0
-#define GPIO0H_EBC_GDPWR2 1
-#define GPIO0H_SMC_DATA12 2
-#define GPIO0H_GPIO0C3 0
-#define GPIO0H_EBC_GDPWR1 1
-#define GPIO0H_SMC_DATA11 2
-#define GPIO0H_GPIO0C2 0
-#define GPIO0H_EBC_GDPWR0 1
-#define GPIO0H_SMC_DATA10 2
-#define GPIO0H_GPIO0C1 0
-#define GPIO0H_EBC_GDRL 1
-#define GPIO0H_SMC_DATA9 2
-#define GPIO0H_GPIO0C0 0
-#define GPIO0H_EBC_GDSP 1
-#define GPIO0H_SMC_DATA8 2
-
-///GPIO1L
-#define GPIO1L_GPIO1B7 0
-#define GPIO1L_UART0_SOUT 1
-#define GPIO1L_GPIO1B6 0
-#define GPIO1L_UART0_SIN 1
-#define GPIO1L_GPIO1B5 0
-#define GPIO1L_PWM0 1
-#define GPIO1L_GPIO1B4 0
-#define GPIO1L_VIP_CLKOUT 1
-#define GPIO1L_GPIO1B3 0
-#define GPIO1L_VIP_DATA3 1
-#define GPIO1L_GPIO1B2 0
-#define GPIO1L_VIP_DATA2 1
-#define GPIO1L_GPIO1B1 0
-#define GPIO1L_VIP_DATA1 1
-#define GPIO1L_GPIO1B0 0
-#define GPIO1L_VIP_DATA0 1
-#define GPIO1L_GPIO1A7 0
-#define GPIO1L_I2C1_SCL 1
-#define GPIO1L_GPIO1A6 0
-#define GPIO1L_I2C1_SDA 1
-#define GPIO1L_GPIO1A5 0
-#define GPIO1L_EMMC_PWR_EN 1
-#define GPIO1L_PWM3 2
-#define GPIO1L_GPIO1A4 0
-#define GPIO1L_EMMC_WRITE_PRT 1
-#define GPIO1L_SPI0_CSN1 2
-#define GPIO1L_GPIO1A3 0
-#define GPIO1L_EMMC_DETECT_N 1
-#define GPIO1L_SPI1_CSN1 2
-#define GPIO1L_GPIO1A2 0
-#define GPIO1L_SMC_CSN1 1
-#define GPIO1L_GPIO1A1 0
-#define GPIO1L_SMC_CSN0 1
-#define GPIO1L_GPIO1A0 0
-#define GPIO1L_FLASH_CS7 1
-#define GPIO1L_MDDR_TQ 2
-
-///GPIO1H
-#define GPIO1H_GPIO1D7 0
-#define GPIO1H_SDMMC0_DATA5 1
-#define GPIO1H_GPIO1D6 0
-#define GPIO1H_SDMMC0_DATA4 1
-#define GPIO1H_GPIO1D5 0
-#define GPIO1H_SDMMC0_DATA3 1
-#define GPIO1H_GPIO1D4 0
-#define GPIO1H_SDMMC0_DATA2 1
-#define GPIO1H_GPIO1D3 0
-#define GPIO1H_SDMMC0_DATA1 1
-#define GPIO1H_GPIO1D2 0
-#define GPIO1H_SDMMC0_DATA0 1
-#define GPIO1H_GPIO1_D1 0
-#define GPIO1H_SDMMC0_CMD 1
-#define GPIO1H_GPIO1_D0 0
-#define GPIO1H_SDMMC0_CLKOUT 1
-#define GPIO1H_GPIO1C7 0
-#define GPIO1H_SDMMC1_CLKOUT 1
-#define GPIO1H_GPIO1C6 0
-#define GPIO1H_SDMMC1_DATA3 1
-#define GPIO1H_GPIO1C5 0
-#define GPIO1H_SDMMC1_DATA2 1
-#define GPIO1H_GPIO1C4 0
-#define GPIO1H_SDMMC1_DATA1 1
-#define GPIO1H_GPIO1C3 0
-#define GPIO1H_SDMMC1_DATA0 1
-#define GPIO1H_GPIO1C2 0
-#define GPIO1H_SDMMC1_CMD 1
-#define GPIO1H_GPIO1C1 0
-#define GPIO1H_UART0_RTS_N 1
-#define GPIO1H_SDMMC1_WRITE_PRT 2
-#define GPIO1H_GPIO1C0 0
-#define GPIO1H_UART0_CTS_N 1
-#define GPIO1H_SDMMC1_DETECT_N 2
-
-///GPIO2L
-#define GPIO2L_GPIO2B7 0
-#define GPIO2L_I2C0_SCL 1
-#define GPIO2L_GPIO2B6 0
-#define GPIO2L_I2C0_SDA 1
-#define GPIO2L_GPIO2B5 0
-#define GPIO2L_UART3_RTS_N 1
-#define GPIO2L_I2C3_SCL 2
-#define GPIO2L_GPIO2B4 0
-#define GPIO2L_UART3_CTS_N 1
-#define GPIO2L_I2C3_SDA 2
-#define GPIO2L_GPIO2B3 0
-#define GPIO2L_UART3_SOUT 1
-#define GPIO2L_GPIO2B2 0
-#define GPIO2L_UART3_SIN 1
-#define GPIO2L_GPIO2B1 0
-#define GPIO2L_UART2_SOUT 1
-#define GPIO2L_GPIO2B0 0
-#define GPIO2L_UART2_SIN 1
-#define GPIO2L_GPIO2A7 0
-#define GPIO2L_UART2_RTS_N 1
-#define GPIO2L_GPIO2A6 0
-#define GPIO2L_UART2_CTS_N 1
-#define GPIO2L_GPIO2A5 0
-#define GPIO2L_UART1_SOUT 1
-#define GPIO2L_GPIO2A4 0
-#define GPIO2L_UART1_SIN 1
-#define GPIO2L_GPIO2A3 0
-#define GPIO2L_SDMMC0_WRITE_PRT 1
-#define GPIO2L_PWM2 2
-#define GPIO2L_UART1_SIR_OUT_N 3
-#define GPIO2L_GPIO2A2 0
-#define GPIO2L_SDMMC0_DETECT_N 1
-#define GPIO2L_GPIO2A1 0
-#define GPIO2L_SDMMC0_DATA7 1
-#define GPIO2L_GPIO2A0 0
-#define GPIO2L_SDMMC0_DATA6 1
-
-///GPIO2H
-#define GPIO2H_GPIO2D7 0
-#define GPIO2H_I2S0_SDO3 1
-#define GPIO2H_MII_TXD3 2
-#define GPIO2H_GPIO2D6 0
-#define GPIO2H_I2S0_SDO2 1
-#define GPIO2H_MII_TXD2 2
-#define GPIO2H_GPIO2D5 0
-#define GPIO2H_I2S0_SDO1 1
-#define GPIO2H_MII_RXD3 2
-#define GPIO2H_GPIO2D4 0
-#define GPIO2H_I2S0_SDO0 1
-#define GPIO2H_MII_RXD2 2
-#define GPIO2H_GPIO2D3 0
-#define GPIO2H_I2S0_SDI 1
-#define GPIO2H_MII_COL 2
-#define GPIO2H_GPIO2D2 0
-#define GPIO2H_I2S0_LRCK_RX 1
-#define GPIO2H_MII_TX_ERR 2
-#define GPIO2H_GPIO2D1 0
-#define GPIO2H_I2S0_SCLK 1
-#define GPIO2H_MII_CRS 2
-#define GPIO2H_GPIO2D0 0
-#define GPIO2H_I2S0_CLK 1
-#define GPIO2H_MII_RX_CLKIN 2
-#define GPIO2H_GPIO2C7 0
-#define GPIO2H_SPI1_RXD 1
-#define GPIO2H_GPIO2C6 0
-#define GPIO2H_SPI1_TXD 1
-#define GPIO2H_GPIO2C5 0
-#define GPIO2H_SPI1_CSN0 1
-#define GPIO2H_GPIO2C4 0
-#define GPIO2H_SPI1_CLK 1
-#define GPIO2H_GPIO2C3 0
-#define GPIO2H_SPI0_RXD 1
-#define GPIO2H_GPIO2C2 0
-#define GPIO2H_SPI0_TXD 1
-#define GPIO2H_GPIO2C1 0
-#define GPIO2H_SPI0_CSN0 1
-#define GPIO2H_GPIO2C0 0
-#define GPIO2H_SPI0_CLK 1
-
-///GPIO3L
-#define GPIO3L_GPIO3B7 0
-#define GPIO3L_EMMC_DATA5 1
-#define GPIO3L_GPIO3B6 0
-#define GPIO3L_EMMC_DATA4 1
-#define GPIO3L_GPIO3B5 0
-#define GPIO3L_EMMC_DATA3 1
-#define GPIO3L_GPIO3B4 0
-#define GPIO3L_EMMC_DATA2 1
-#define GPIO3L_GPIO3B3 0
-#define GPIO3L_EMMC_DATA1 1
-#define GPIO3L_GPIO3B2 0
-#define GPIO3L_EMMC_DATA0 1
-#define GPIO3L_GPIO3B1 0
-#define GPIO3L_EMMC_CMD 1
-#define GPIO3L_GPIO3B0 0
-#define GPIO3L_EMMC_CLKOUT 1
-#define GPIO3L_GPIO3A7 0
-#define GPIO3L_SMC_ADDR15 1
-#define GPIO3L_HOST_DATA15 2
-#define GPIO3L_GPIO3A6 0
-#define GPIO3L_SMC_ADDR14 1
-#define GPIO3L_HOST_DATA14 2
-#define GPIO3L_GPIO3A5 0
-#define GPIO3L_I2S1_LRCK_TX 1
-#define GPIO3L_GPIO3A4 0
-#define GPIO3L_I2S1_SDO 1
-#define GPIO3L_GPIO3A3 0
-#define GPIO3L_I2S1_SDI 1
-#define GPIO3L_GPIO3A2 0
-#define GPIO3L_I2S1_LRCK_RX 1
-#define GPIO3L_GPIO3A1 0
-#define GPIO3L_I2S1_SCLK 1
-#define GPIO3L_GPIO3A0 0
-#define GPIO3L_I2S1_CLK 1
-
-///GPIO3H
-#define GPIO3H_GPIO3D7 0
-#define GPIO3H_SMC_ADDR9 1
-#define GPIO3H_HOST_DATA9 2
-#define GPIO3H_GPIO3D6 0
-#define GPIO3H_SMC_ADDR8 1
-#define GPIO3H_HOST_DATA8 2
-#define GPIO3H_GPIO3D5 0
-#define GPIO3H_SMC_ADDR7 1
-#define GPIO3H_HOST_DATA7 2
-#define GPIO3H_GPIO3D4 0
-#define GPIO3H_HOST_WRN 1
-#define GPIO3H_GPIO3D3 0
-#define GPIO3H_HOST_RDN 1
-#define GPIO3H_GPIO3D2 0
-#define GPIO3H_HOST_CSN 1
-#define GPIO3H_GPIO3D1 0
-#define GPIO3H_SMC_ADDR19 1
-#define GPIO3H_HOST_ADDR1 2
-#define GPIO3H_GPIO3D0 0
-#define GPIO3H_SMC_ADDR18 1
-#define GPIO3H_HOST_ADDR0 2
-#define GPIO3H_GPIO3C7 0
-#define GPIO3H_SMC_ADDR17 1
-#define GPIO3H_HOST_DATA17 2
-#define GPIO3H_GPIO3C6 0
-#define GPIO3H_SMC_ADDR16 1
-#define GPIO3H_HOST_DATA16 2
-#define GPIO3H_GPIO3C5 0
-#define GPIO3H_SMC_ADDR12 1
-#define GPIO3H_HOST_DATA12 2
-#define GPIO3H_GPIO3C4 0
-#define GPIO3H_SMC_ADDR11 1
-#define GPIO3H_HOST_DATA11 2
-#define GPIO3H_GPIO3C3 0
-#define GPIO3H_SMC_ADDR10 1
-#define GPIO3H_HOST_DATA10 2
-#define GPIO3H_GPIO3C2 0
-#define GPIO3H_SMC_ADDR13 1
-#define GPIO3H_HOST_DATA13 2
-#define GPIO3H_GPIO3C1 0
-#define GPIO3H_EMMC_DATA7 1
-#define GPIO3H_GPIO3C0 0
-#define GPIO3H_EMMC_DATA6 1
-
-///GPIO4L
-#define GPIO4L_GPIO4B7 0
-#define GPIO4L_FLASH_DATA15 1
-#define GPIO4L_GPIO4B6 0
-#define GPIO4L_FLASH_DATA14 1
-#define GPIO4L_GPIO4B5 0
-#define GPIO4L_FLASH_DATA13 1
-#define GPIO4L_GPIO4B4 0
-#define GPIO4L_FLASH_DATA12 1
-#define GPIO4L_GPIO4B3 0
-#define GPIO4L_FLASH_DATA11 1
-#define GPIO4L_GPIO4B2 0
-#define GPIO4L_FLASH_DATA10 1
-#define GPIO4L_GPIO4B1 0
-#define GPIO4L_FLASH_DATA9 1
-#define GPIO4L_GPIO4B0 0
-#define GPIO4L_FLASH_DATA8 1
-#define GPIO4L_GPIO4A7 0
-#define GPIO4L_SPDIF_TX 1
-#define GPIO4L_GPIO4A6 0
-#define GPIO4L_OTG1_DRV_VBUS 1
-#define GPIO4L_GPIO4A5 0
-#define GPIO4L_OTG0_DRV_VBUS 1
-
-///GPIO4H
-#define GPIO4H_GPIO4D7 0
-#define GPIO4H_I2S0_LRCK_TX1 1
-#define GPIO4H_GPIO4D6 0
-#define GPIO4H_I2S0_LRCK_TX0 1
-#define GPIO4H_GPIO4D5 0
-#define GPIO4H_CPU_TRACE_CTL 1
-#define GPIO4H_GPIO4D4 0
-#define GPIO4H_CPU_TRACE_CLK 1
-#define GPIO4H_GPIO6C76 0
-#define GPIO4H_CPU_TRACE_DATA76 1
-#define GPIO4H_GPIO6C54 0
-#define GPIO4H_CPU_TRACE_DATA54 1
-#define GPIO4H_GPIO4D32 0
-#define GPIO4H_CPU_TRACE_DATA32 1
-#define GPIO4H_GPIO4D10 0
-#define GPIO4H_CPU_TRACE_DATA10 1
-#define GPIO4H_GPIO4C7 0
-#define GPIO4H_RMII_RXD0 1
-#define GPIO4H_MII_RXD0 2
-#define GPIO4H_GPIO4C6 0
-#define GPIO4H_RMII_RXD1 1
-#define GPIO4H_MII_RXD1 2
-#define GPIO4H_GPIO4C5 0
-#define GPIO4H_RMII_CSR_DVALID 1
-#define GPIO4H_MII_RXD_VALID 2
-#define GPIO4H_GPIO4C4 0
-#define GPIO4H_RMII_RX_ERR 1
-#define GPIO4H_MII_RX_ERR 2
-#define GPIO4H_GPIO4C3 0
-#define GPIO4H_RMII_TXD0 1
-#define GPIO4H_MII_TXD0 2
-#define GPIO4H_GPIO4C2 0
-#define GPIO4H_RMII_TXD1 1
-#define GPIO4H_MII_TXD1 2
-#define GPIO4H_GPIO4C1 0
-#define GPIO4H_RMII_TX_EN 1
-#define GPIO4H_MII_TX_EN 2
-#define GPIO4H_GPIO4C0 0
-#define GPIO4H_RMII_CLKOUT 1
-#define GPIO4H_RMII_CLKIN 2
-
-///GPIO5L
-#define GPIO5L_GPIO5B7 0
-#define GPIO5L_HSADC_CLKOUT 1
-#define GPIO5L_GPS_CLK 2
-#define GPIO5L_GPIO5B6 0
-#define GPIO5L_HSADC_DATA9 1
-#define GPIO5L_GPIO5B5 0
-#define GPIO5L_HSADC_DATA8 1
-#define GPIO5L_GPIO5B4 0
-#define GPIO5L_HSADC_DATA7 1
-#define GPIO5L_GPIO5B3 0
-#define GPIO5L_HSADC_DATA6 1
-#define GPIO5L_GPIO5B2 0
-#define GPIO5L_HSADC_DATA5 1
-#define GPIO5L_GPIO5B1 0
-#define GPIO5L_HSADC_DATA4 1
-#define GPIO5L_GPIO5B0 0
-#define GPIO5L_HSADC_DATA3 1
-#define GPIO5L_GPIO5A7 0
-#define GPIO5L_HSADC_DATA2 1
-#define GPIO5L_GPIO5A6 0
-#define GPIO5L_HSADC_DATA1 1
-#define GPIO5L_GPIO5A5 0
-#define GPIO5L_HSADC_DATA0 1
-#define GPIO5L_GPIO5A4 0
-#define GPIO5L_TS_SYNC 1
-#define GPIO5L_GPIO5A3 0
-#define GPIO5L_MII_TX_CLKIN 1
-
-///GPIO5H
-#define GPIO5H_GPIO5D6 0
-#define GPIO5H_SDMMC1_PWR_EN 1
-#define GPIO5H_GPIO5D5 0
-#define GPIO5H_SDMMC0_PWR_EN 1
-#define GPIO5H_GPIO5D4 0
-#define GPIO5H_I2C2_SCL 1
-#define GPIO5H_GPIO5D3 0
-#define GPIO5H_I2C2_SDA 1
-#define GPIO5H_GPIO5D2 0
-#define GPIO5H_PWM1 1
-#define GPIO5H_UART1_SIR_IN 2
-#define GPIO5H_GPIO5D1 0
-#define GPIO5H_EBC_SDCLK 1
-#define GPIO5H_SMC_ADDR6 2
-#define GPIO5H_HOST_DATA6 3
-#define GPIO5H_GPIO5D0 0
-#define GPIO5H_EBC_SDLE 1
-#define GPIO5H_SMC_ADDR5 2
-#define GPIO5H_HOST_DATA5 3
-#define GPIO5H_GPIO5C7 0
-#define GPIO5H_EBC_SDDO7 1
-#define GPIO5H_SMC_DATA7 2
-#define GPIO5H_GPIO5C6 0
-#define GPIO5H_EBC_SDDO6 1
-#define GPIO5H_SMC_DATA6 2
-#define GPIO5H_GPIO5C5 0
-#define GPIO5H_EBC_SDDO5 1
-#define GPIO5H_SMC_DATA5 2
-#define GPIO5H_GPIO5C4 0
-#define GPIO5H_EBC_SDDO4 1
-#define GPIO5H_SMC_DATA4 2
-#define GPIO5H_GPIO5C3 0
-#define GPIO5H_EBC_SDDO3 1
-#define GPIO5H_SMC_DATA3 2
-#define GPIO5H_GPIO5C2 0
-#define GPIO5H_EBC_SDDO2 1
-#define GPIO5H_SMC_DATA2 2
-#define GPIO5H_GPIO5C1 0
-#define GPIO5H_EBC_SDDO1 1
-#define GPIO5H_SMC_DATA1 2
-#define GPIO5H_GPIO5C0 0
-#define GPIO5H_EBC_SDDO0 1
-#define GPIO5H_SMC_DATA0 2
-
-#define DEFAULT 0
-#define INITIAL 1
-
-#define RK29_IOMUX_GPIO0L_CON RK29_GRF_BASE+0x48
-#define RK29_IOMUX_GPIO0H_CON RK29_GRF_BASE+0x4c
-#define RK29_IOMUX_GPIO1L_CON RK29_GRF_BASE+0x50
-#define RK29_IOMUX_GPIO1H_CON RK29_GRF_BASE+0x54
-#define RK29_IOMUX_GPIO2L_CON RK29_GRF_BASE+0x58
-#define RK29_IOMUX_GPIO2H_CON RK29_GRF_BASE+0x5c
-#define RK29_IOMUX_GPIO3L_CON RK29_GRF_BASE+0x60
-#define RK29_IOMUX_GPIO3H_CON RK29_GRF_BASE+0x64
-#define RK29_IOMUX_GPIO4L_CON RK29_GRF_BASE+0x68
-#define RK29_IOMUX_GPIO4H_CON RK29_GRF_BASE+0x6c
-#define RK29_IOMUX_GPIO5L_CON RK29_GRF_BASE+0x70
-#define RK29_IOMUX_GPIO5H_CON RK29_GRF_BASE+0x74
-
-///GPIO0L
-#define GPIO0B7_EBCGDOE_SMCOEN_NAME "gpio0b7_ebcgdoe_smcoen_name"
-#define GPIO0B6_EBCSDSHR_SMCBLSN1_HOSTINT_NAME "gpio0b6_ebcsdshr_smcblsn1_hostint_name"
-#define GPIO0B5_EBCVCOM_SMCBLSN0_NAME "gpio0b5_ebcvcom_smcblsn0_name"
-#define GPIO0B4_EBCBORDER1_SMCWEN_NAME "gpio0b4_ebcborder1_smcwen_name"
-#define GPIO0B3_EBCBORDER0_SMCADDR3_HOSTDATA3_NAME "gpio0b3_ebcborder0_smcaddr3_hostdata3_name"
-#define GPIO0B2_EBCSDCE2_SMCADDR2_HOSTDATA2_NAME "gpio0b2_ebcsdce2_smcaddr2_hostdata2_name"
-#define GPIO0B1_EBCSDCE1_SMCADDR1_HOSTDATA1_NAME "gpio0b1_ebcsdce1_smcaddr1_hostdata1_name"
-#define GPIO0B0_EBCSDCE0_SMCADDR0_HOSTDATA0_NAME "gpio0b0_ebcsdce0_smcaddr0_hostdata0_name"
-#define GPIO0A7_MIIMDCLK_NAME "gpio0a7_miimdclk_name"
-#define GPIO0A6_MIIMD_NAME "gpio0a6_miimd_name"
-#define GPIO0A5_FLASHDQS_NAME "gpio0a5_flashdqs_name"
-
-///GPIO0H
-#define GPIO0D7_FLASHCSN6_NAME "gpio0d7_flashcsn6_name"
-#define GPIO0D6_FLASHCSN5_NAME "gpio0d6_flashcsn5_name"
-#define GPIO0D5_FLASHCSN4_NAME "gpio0d5_flashcsn4_name"
-#define GPIO0D4_FLASHCSN3_NAME "gpio0d4_flashcsn3_name"
-#define GPIO0D3_FLASHCSN2_NAME "gpio0d3_flashcsn2_name"
-#define GPIO0D2_FLASHCSN1_NAME "gpio0d2_flashcsn1_name"
-#define GPIO0D1_EBCGDCLK_SMCADDR4_HOSTDATA4_NAME "gpio0d1_ebcgdclk_smcaddr4_hostdata4_name"
-#define GPIO0D0_EBCSDOE_SMCADVN_NAME "gpio0d0_ebcsdoe_smcadvn_name"
-#define GPIO0C7_EBCSDCE5_SMCDATA15_NAME "gpio0c7_ebcsdce5_smcdata15_name"
-#define GPIO0C6_EBCSDCE4_SMCDATA14_NAME "gpio0c6_ebcsdce4_smcdata14_name"
-#define GPIO0C5_EBCSDCE3_SMCDATA13_NAME "gpio0c5_ebcsdce3_smcdata13_name"
-#define GPIO0C4_EBCSDCE2_SMCDATA12_NAME "gpio0c4_ebcsdce2_smcdata12_name"
-#define GPIO0C3_EBCSDCE1_SMCDATA11_NAME "gpio0c3_ebcsdce1_smcdata11_name"
-#define GPIO0C2_EBCSDCE0_SMCDATA10_NAME "gpio0c2_ebcsdce0_smcdata10_name"
-#define GPIO0C1_EBCGDR1_SMCDATA9_NAME "gpio0c1_ebcgdr1_smcdata9_name"
-#define GPIO0C0_EBCGDSP_SMCDATA8_NAME "gpio0c0_ebcgdsp_smcdata8_name"
-
-///GPIO1L
-#define GPIO1B7_UART0SOUT_NAME "gpio1b7_uart0sout_name"
-#define GPIO1B6_UART0SIN_NAME "gpio1b6_uart0sin_name"
-#define GPIO1B5_PWM0_NAME "gpio1b5_pwm0_name"
-#define GPIO1B4_VIPCLKOUT_NAME "gpio1b4_vipclkout_name"
-#define GPIO1B3_VIPDATA3_NAME "gpio1b3_vipdata3_name"
-#define GPIO1B2_VIPDATA2_NAME "gpio1b2_vipdata2_name"
-#define GPIO1B1_VIPDATA1_NAME "gpio1b1_vipdata1_name"
-#define GPIO1B0_VIPDATA0_NAME "gpio1b0_vipdata0_name"
-#define GPIO1A7_I2C1SCL_NAME "gpio1a7_i2c1scl_name"
-#define GPIO1A6_I2C1SDA_NAME "gpio1a6_i2c1sda_name"
-#define GPIO1A5_EMMCPWREN_PWM3_NAME "gpio1a5_emmcpwren_pwm3_name"
-#define GPIO1A4_EMMCWRITEPRT_SPI0CS1_NAME "gpio1a4_emmcwriteprt_spi0cs1_name"
-#define GPIO1A3_EMMCDETECTN_SPI1CS1_NAME "gpio1a3_emmcdetectn_spi1cs1_name"
-#define GPIO1A2_SMCCSN1_NAME "gpio1a2_smccsn1_name"
-#define GPIO1A1_SMCCSN0_NAME "gpio1a1_smccsn0_name"
-#define GPIO1A0_FLASHCS7_MDDRTQ_NAME "gpio1a0_flashcs7_mddrtq_name"
-
-///GPIO1H
-#define GPIO1D7_SDMMC0DATA5_NAME "gpio1d7_sdmmc0data5_name"
-#define GPIO1D6_SDMMC0DATA4_NAME "gpio1d6_sdmmc0data4_name"
-#define GPIO1D5_SDMMC0DATA3_NAME "gpio1d5_sdmmc0data3_name"
-#define GPIO1D4_SDMMC0DATA2_NAME "gpio1d4_sdmmc0data2_name"
-#define GPIO1D3_SDMMC0DATA1_NAME "gpio1d3_sdmmc0data1_name"
-#define GPIO1D2_SDMMC0DATA0_NAME "gpio1d2_sdmmc0data0_name"
-#define GPIO1D1_SDMMC0CMD_NAME "gpio1d1_sdmmc0cmd_name"
-#define GPIO1D0_SDMMC0CLKOUT_NAME "gpio1d0_sdmmc0clkout_name"
-#define GPIO1C7_SDMMC1CLKOUT_NAME "gpio1c7_sdmmc1clkout_name"
-#define GPIO1C6_SDMMC1DATA3_NAME "gpio1c6_sdmmc1data3_name"
-#define GPIO1C5_SDMMC1DATA2_NAME "gpio1c5_sdmmc1data2_name"
-#define GPIO1C4_SDMMC1DATA1_NAME "gpio1c4_sdmmc1data1_name"
-#define GPIO1C3_SDMMC1DATA0_NAME "gpio1c3_sdmmc1data0_name"
-#define GPIO1C2_SDMMC1CMD_NAME "gpio1c2_sdmmc1cmd_name"
-#define GPIO1C1_UART0RTSN_SDMMC1WRITEPRT_NAME "gpio1c1_uart0rtsn_sdmmc1writeprt_name"
-#define GPIO1C0_UART0CTSN_SDMMC1DETECTN_NAME "gpio1c1_uart0ctsn_sdmmc1detectn_name"
-
-///GPIO2L
-#define GPIO2B7_I2C0SCL_NAME "gpio2b7_i2c0scl_name"
-#define GPIO2B6_I2C0SDA_NAME "gpio2b6_i2c0sda_name"
-#define GPIO2B5_UART3RTSN_I2C3SCL_NAME "gpio2b5_uart3rtsn_i2c3scl_name"
-#define GPIO2B4_UART3CTSN_I2C3SDA_NAME "gpio2b4_uart3ctsn_i2c3sda_name"
-#define GPIO2B3_UART3SOUT_NAME "gpio2b3_uart3sout_name"
-#define GPIO2B2_UART3SIN_NAME "gpio2b2_uart3sin_name"
-#define GPIO2B1_UART2SOUT_NAME "gpio2b1_uart2sout_name"
-#define GPIO2B0_UART2SIN_NAME "gpio2b0_uart2sin_name"
-#define GPIO2A7_UART2RTSN_NAME "gpio2a7_uart2rtsn_name"
-#define GPIO2A6_UART2CTSN_NAME "gpio2a6_uart2ctsn_name"
-#define GPIO2A5_UART1SOUT_NAME "gpio2a5_uart1sout_name"
-#define GPIO2A4_UART1SIN_NAME "gpio2a4_uart1sin_name"
-#define GPIO2A3_SDMMC0WRITEPRT_PWM2_NAME "gpio2a3_sdmmc0writeprt_pwm2_name"
-#define GPIO2A2_SDMMC0DETECTN_NAME "gpio2a2_sdmmc0detectn_name"
-#define GPIO2A1_SDMMC0DATA7_NAME "gpio2a1_sdmmc0data7_name"
-#define GPIO2A0_SDMMC0DATA6_NAME "gpio2a0_sdmmc0data6_name"
-
-///GPIO2H
-#define GPIO2D7_I2S0SDO3_MIITXD3_NAME "gpio2d7_i2s0sdo3_miitxd3_name"
-#define GPIO2D6_I2S0SDO2_MIITXD2_NAME "gpio2d6_i2s0sdo2_miitxd2_name"
-#define GPIO2D5_I2S0SDO1_MIIRXD3_NAME "gpio2d5_i2s0sdo1_miirxd3_name"
-#define GPIO2D4_I2S0SDO0_MIIRXD2_NAME "gpio2d4_i2s0sdo0_miirxd2_name"
-#define GPIO2D3_I2S0SDI_MIICOL_NAME "gpio2d3_i2s0sdi_miicol_name"
-#define GPIO2D2_I2S0LRCKRX_MIITXERR_NAME "gpio2d2_i2s0lrckrx_miitxerr_name"
-#define GPIO2D1_I2S0SCLK_MIICRS_NAME "gpio2d1_i2s0sclk_miicrs_name"
-#define GPIO2D0_I2S0CLK_MIIRXCLKIN_NAME "gpio2d0_i2s0clk_miirxclkin_name"
-#define GPIO2C7_SPI1RXD_NAME "gpio2c7_spi1rxd_name"
-#define GPIO2C6_SPI1TXD_NAME "gpio2c6_spi1txd_name"
-#define GPIO2C5_SPI1CSN0_NAME "gpio2c5_spi1csn0_name"
-#define GPIO2C4_SPI1CLK_NAME "gpio2c4_spi1clk_name"
-#define GPIO2C3_SPI0RXD_NAME "gpio2c3_spi0rxd_name"
-#define GPIO2C2_SPI0TXD_NAME "gpio2c2_spi0txd_name"
-#define GPIO2C1_SPI0CSN0_NAME "gpio2c1_spi0csn0_name"
-#define GPIO2C0_SPI0CLK_NAME "gpio2c0_spi0clk_name"
-
-///GPIO3L
-#define GPIO3B7_EMMCDATA5_NAME "gpio3b7_emmcdata5_name"
-#define GPIO3B6_EMMCDATA4_NAME "gpio3b6_emmcdata4_name"
-#define GPIO3B5_EMMCDATA3_NAME "gpio3b5_emmcdata3_name"
-#define GPIO3B4_EMMCDATA2_NAME "gpio3b4_emmcdata2_name"
-#define GPIO3B3_EMMCDATA1_NAME "gpio3b3_emmcdata1_name"
-#define GPIO3B2_EMMCDATA0_NAME "gpio3b2_emmcdata0_name"
-#define GPIO3B1_EMMCMD_NAME "gpio3b1_emmcmd_name"
-#define GPIO3B0_EMMCLKOUT_NAME "gpio3b0_emmclkout_name"
-#define GPIO3A7_SMCADDR15_HOSTDATA15_NAME "gpio3a7_smcaddr15_hostdata15_name"
-#define GPIO3A6_SMCADDR14_HOSTDATA14_NAME "gpio3a6_smcaddr14_hostdata14_name"
-#define GPIO3A5_I2S1LRCKTX_NAME "gpio3a5_i2s1lrcktx_name"
-#define GPIO3A4_I2S1SDO_NAME "gpio3a4_i2s1sdo_name"
-#define GPIO3A3_I2S1SDI_NAME "gpio3a3_i2s1sdi_name"
-#define GPIO3A2_I2S1LRCKRX_NAME "gpio3a2_i2s1lrckrx_name"
-#define GPIO3A1_I2S1SCLK_NAME "gpio3a1_i2s1sclk_name"
-#define GPIO3A0_I2S1CLK_NAME "gpio3a0_i2s1clk_name"
-
-///GPIO3H
-#define GPIO3D7_SMCADDR9_HOSTDATA9_NAME "gpio3d7_smcaddr9_hostdata9_name"
-#define GPIO3D6_SMCADDR8_HOSTDATA8_NAME "gpio3d6_smcaddr8_hostdata8_name"
-#define GPIO3D5_SMCADDR7_HOSTDATA7_NAME "gpio3d5_smcaddr7_hostdata7_name"
-#define GPIO3D4_HOSTWRN_NAME "gpio3d4_hostwrn_name"
-#define GPIO3D3_HOSTRDN_NAME "gpio3d4_hostwrn_name"
-#define GPIO3D2_HOSTCSN_NAME "gpio3d2_hostcsn_name"
-#define GPIO3D1_SMCADDR19_HOSTADDR1_NAME "gpio3d1_smcaddr19_hostaddr1_name"
-#define GPIO3D0_SMCADDR18_HOSTADDR0_NAME "gpio3d0_smcaddr18_hostaddr0_name"
-#define GPIO3C7_SMCADDR17_HOSTDATA17_NAME "gpio3c7_smcaddr17_hostdata17_name"
-#define GPIO3C6_SMCADDR16_HOSTDATA16_NAME "gpio3c6_smcaddr16_hostdata16_name"
-#define GPIO3C5_SMCADDR12_HOSTDATA12_NAME "gpio3c5_smcaddr12_hostdata12_name"
-#define GPIO3C4_SMCADDR11_HOSTDATA11_NAME "gpio3c4_smcaddr11_hostdata11_name"
-#define GPIO3C3_SMCADDR10_HOSTDATA10_NAME "gpio3c3_smcaddr10_hostdata10_name"
-#define GPIO3C2_SMCADDR13_HOSTDATA13_NAME "gpio3c2_smcaddr13_hostdata13_name"
-#define GPIO3C1_EMMCDATA7_NAME "gpio3c1_emmcdata7_name"
-#define GPIO3C0_EMMCDATA6_NAME "gpio3c0_emmcdata6_name"
-
-///GPIO4L
-#define GPIO4B7_FLASHDATA15_NAME "gpio4b7_flashdata15_name"
-#define GPIO4B6_FLASHDATA14_NAME "gpio4b6_flashdata14_name"
-#define GPIO4B5_FLASHDATA13_NAME "gpio4b5_flashdata13_name"
-#define GPIO4B4_FLASHDATA12_NAME "gpio4b4_flashdata12_name"
-#define GPIO4B3_FLASHDATA11_NAME "gpio4b3_flashdata11_name"
-#define GPIO4B2_FLASHDATA10_NAME "gpio4b2_flashdata10_name"
-#define GPIO4B1_FLASHDATA9_NAME "gpio4b1_flashdata9_name"
-#define GPIO4B0_FLASHDATA8_NAME "gpio4b0_flashdata8_name"
-#define GPIO4A7_SPDIFTX_NAME "gpio4a7_spdiftx_name"
-#define GPIO4A6_OTG1DRVVBUS_NAME "gpio4a6_otg1drvvbus_name"
-#define GPIO4A5_OTG0DRVVBUS_NAME "gpio4a5_otg0drvvbus_name"
-
-///GPIO4H
-#define GPIO4D7_I2S0LRCKTX1_NAME "gpio4d7_i2s0lrcktx1_name"
-#define GPIO4D6_I2S0LRCKTX0_NAME "gpio4d6_i2s0lrcktx0_name"
-#define GPIO4D5_CPUTRACECTL_NAME "gpio4d5_cputracectl_name"
-#define GPIO4D4_CPUTRACECLK_NAME "gpio4d4_cputraceclk_name"
-#define GPIO6C76_CPUTRACEDATA76_NAME "gpio6c76_cputracedata76_name"
-#define GPIO6C54_CPUTRACEDATA54_NAME "gpio6c54_cputracedata54_name"
-#define GPIO4D32_CPUTRACEDATA32_NAME "gpio4d32_cputracedata32_name"
-#define GPIO4D10_CPUTRACEDATA10_NAME "gpio4d10_cputracedata10_name"
-#define GPIO4C7_RMIIRXD0_MIIRXD0_NAME "gpio4c7_rmiirxd0_miirxd0_name"
-#define GPIO4C6_RMIIRXD1_MIIRXD1_NAME "gpio4c6_rmiirxd1_miirxd1_name"
-#define GPIO4C5_RMIICSRDVALID_MIIRXDVALID_NAME "gpio4c5_rmiicsrdvalid_miirxdvalid_name"
-#define GPIO4C4_RMIIRXERR_MIIRXERR_NAME "gpio4c4_rmiirxerr_miirxerr_name"
-#define GPIO4C3_RMIITXD0_MIITXD0_NAME "gpio4c3_rmiitxd0_miitxd0_name"
-#define GPIO4C2_RMIITXD1_MIITXD1_NAME "gpio4c2_rmiitxd1_miitxd1_name"
-#define GPIO4C1_RMIITXEN_MIITXEN_NAME "gpio4c1_rmiitxen_miitxen_name"
-#define GPIO4C0_RMIICLKOUT_RMIICLKIN_NAME "gpio4c0_rmiiclkout_rmiiclkin_name"
-
-///GPIO5L
-#define GPIO5B7_HSADCCLKOUTGPSCLK_NAME "gpio5b7_hsadcclkoutgpsclk_name"
-#define GPIO5B6_HSADCDATA9_NAME "gpio5b6_hsadcdata9_name"
-#define GPIO5B5_HSADCDATA8_NAME "gpio5b5_hsadcdata8_name"
-#define GPIO5B4_HSADCDATA7_NAME "gpio5b4_hsadcdata7_name"
-#define GPIO5B3_HSADCDATA6_NAME "gpio5b3_hsadcdata6_name"
-#define GPIO5B2_HSADCDATA5_NAME "gpio5b2_hsadcdata5_name"
-#define GPIO5B1_HSADCDATA4_NAME "gpio5b1_hsadcdata4_name"
-#define GPIO5B0_HSADCDATA3_NAME "gpio5b0_hsadcdata3_name"
-#define GPIO5A7_HSADCDATA2_NAME "gpio5a7_hsadcdata2_name"
-#define GPIO5A6_HSADCDATA1_NAME "gpio5a6_hsadcdata1_name"
-#define GPIO5A5_HSADCDATA0_NAME "gpio5a5_hsadcdata0_name"
-#define GPIO5A4_TSSYNC_NAME "gpio5a4_tssync_name"
-#define GPIO5A3_MIITXCLKIN_NAME "gpio5a3_miitxclkin_name"
-
-///GPIO5H
-#define GPIO5D6_SDMMC1PWREN_NAME "gpio5d6_sdmmc1pwren_name"
-#define GPIO5D5_SDMMC0PWREN_NAME "gpio5d5_sdmmc0pwren_name"
-#define GPIO5D4_I2C2SCL_NAME "gpio5d4_i2c2scl_name"
-#define GPIO5D3_I2C2SDA_NAME "gpio5d3_i2c2sda_name"
-#define GPIO5D2_PWM1_UART1SIRIN_NAME "gpio5d2_pwm1_uart1sirin_name"
-#define GPIO5D1_EBCSDCLK_SMCADDR6_HOSTDATA6_NAME "gpio5d1_ebcsdclk_smcaddr6_hostdata6_name"
-#define GPIO5D0_EBCSDLE_SMCADDR5_HOSTDATA5_NAME "gpio5d0_ebcsdle_smcaddr5_hostdata5_name"
-#define GPIO5C7_EBCSDDO7_SMCDATA7_NAME "gpio5c7_ebcsddo7_smcdata7_name"
-#define GPIO5C6_EBCSDDO6_SMCDATA6_NAME "gpio5c6_ebcsddo6_smcdata6_name"
-#define GPIO5C5_EBCSDDO5_SMCDATA5_NAME "gpio5c5_ebcsddo5_smcdata5_name"
-#define GPIO5C4_EBCSDDO4_SMCDATA4_NAME "gpio5c4_ebcsddo4_smcdata4_name"
-#define GPIO5C3_EBCSDDO3_SMCDATA3_NAME "gpio5c3_ebcsddo3_smcdata3_name"
-#define GPIO5C2_EBCSDDO2_SMCDATA2_NAME "gpio5c2_ebcsddo2_smcdata2_name"
-#define GPIO5C1_EBCSDDO1_SMCDATA1_NAME "gpio5c1_ebcsddo1_smcdata1_name"
-#define GPIO5C0_EBCSDDO0_SMCDATA0_NAME "gpio5c0_ebcsddo0_smcdata0_name"
-
-#define GRF_GPIO0_PULL 0x0078
-#define GRF_GPIO1_PULL 0x007C
-#define GRF_GPIO2_PULL 0x0080
-#define GRF_GPIO3_PULL 0x0084
-#define GRF_GPIO4_PULL 0x0088
-#define GRF_GPIO5_PULL 0x008C
-#define GRF_GPIO6_PULL 0x0090
-
-#define MUX_CFG(desc,reg,off,interl,mux_mode,bflags) \
-{ \
- .name = desc, \
- .offset = off, \
- .interleave = interl, \
- .mux_reg = RK29_IOMUX_##reg##_CON, \
- .mode = mux_mode, \
- .premode = mux_mode, \
- .flags = bflags, \
-},
-
-struct mux_config {
- char *name;
- const unsigned int offset;
- unsigned int mode;
- unsigned int premode;
- const unsigned int mux_reg;
- const unsigned int interleave;
- unsigned int flags;
-};
-
-extern int rk29_iomux_init(void);
-extern void rk29_mux_api_set(char *name, unsigned int mode);
-
-#endif
\ No newline at end of file
+++ /dev/null
-/* arch/arm/mach-rk29/include/mach/irqs.h
- *
- * Copyright (C) 2010 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-
-#ifndef __ARCH_ARM_MACH_RK29_IRQS_H
-#define __ARCH_ARM_MACH_RK29_IRQS_H
-
-#define RK29XX_IRQ(x) (x+32)
-
-#define IRQ_DMAC0_0 RK29XX_IRQ(0)
-#define IRQ_DMAC0_1 RK29XX_IRQ(1)
-#define IRQ_DMAC0_2 RK29XX_IRQ(2)
-#define IRQ_DMAC0_3 RK29XX_IRQ(3)
-
-#define IRQ_DMAC1_0 RK29XX_IRQ(4)
-#define IRQ_DMAC1_1 RK29XX_IRQ(5)
-#define IRQ_DMAC1_2 RK29XX_IRQ(6)
-#define IRQ_DMAC1_3 RK29XX_IRQ(7)
-#define IRQ_DMAC1_4 RK29XX_IRQ(8)
-
-#define IRQ_GPU RK29XX_IRQ(9)
-#define IRQ_VEPU RK29XX_IRQ(10)
-#define IRQ_VDPU RK29XX_IRQ(11)
-#define IRQ_VIP RK29XX_IRQ(12)
-#define IRQ_LCDC RK29XX_IRQ(13)
-#define IRQ_IPP RK29XX_IRQ(14)
-#define IRQ_EBC RK29XX_IRQ(15)
-#define IRQ_USB_OTG0 RK29XX_IRQ(16)
-#define IRQ_USB_OTG1 RK29XX_IRQ(17)
-#define IRQ_USB_HOST RK29XX_IRQ(18)
-#define IRQ_MAC RK29XX_IRQ(19)
-#define IRQ_HIF0 RK29XX_IRQ(20)
-#define IRQ_HIF1 RK29XX_IRQ(21)
-#define IRQ_HSADC_TSI RK29XX_IRQ(22)
-#define IRQ_SDMMC RK29XX_IRQ(23)
-#define IRQ_SDIO RK29XX_IRQ(24)
-#define IRQ_EMMC RK29XX_IRQ(25)
-#define IRQ_SARADC RK29XX_IRQ(26)
-#define IRQ_NANDC RK29XX_IRQ(27)
-#define IRQ_NANDC_RDY RK29XX_IRQ(28)
-#define IRQ_SMC RK29XX_IRQ(29)
-#define IRQ_PID_FILTER RK29XX_IRQ(30)
-#define IRQ_I2S_8CH RK29XX_IRQ(31)
-#define IRQ_I2S_2CH RK29XX_IRQ(32)
-#define IRQ_SPDIF RK29XX_IRQ(33)
-
-#define IRQ_UART0 RK29XX_IRQ(34)
-#define IRQ_UART1 RK29XX_IRQ(35)
-#define IRQ_UART2 RK29XX_IRQ(36)
-#define IRQ_UART3 RK29XX_IRQ(37)
-
-#define IRQ_SPI0 RK29XX_IRQ(38)
-#define IRQ_SPI1 RK29XX_IRQ(39)
-
-#define IRQ_I2C0 RK29XX_IRQ(40)
-#define IRQ_I2C1 RK29XX_IRQ(41)
-#define IRQ_I2C2 RK29XX_IRQ(42)
-#define IRQ_I2C3 RK29XX_IRQ(43)
-
-#define IRQ_TIMER0 RK29XX_IRQ(44)
-#define IRQ_TIMER1 RK29XX_IRQ(45)
-#define IRQ_TIMER2 RK29XX_IRQ(46)
-#define IRQ_TIMER3 RK29XX_IRQ(47)
-
-#define IRQ_PWM0 RK29XX_IRQ(48)
-#define IRQ_PWM1 RK29XX_IRQ(49)
-#define IRQ_PWM2 RK29XX_IRQ(50)
-#define IRQ_PWM3 RK29XX_IRQ(51)
-
-#define IRQ_WDT RK29XX_IRQ(52)
-#define IRQ_RTC RK29XX_IRQ(53)
-#define IRQ_PMU RK29XX_IRQ(54)
-
-#define IRQ_GPIO0 RK29XX_IRQ(55)
-#define IRQ_GPIO1 RK29XX_IRQ(56)
-#define IRQ_GPIO2 RK29XX_IRQ(57)
-#define IRQ_GPIO3 RK29XX_IRQ(58)
-#define IRQ_GPIO4 RK29XX_IRQ(59)
-#define IRQ_GPIO5 RK29XX_IRQ(60)
-#define IRQ_GPIO6 RK29XX_IRQ(61)
-
-#define IRQ_USB_AHB_ARB RK29XX_IRQ(62)
-#define IRQ_PERI_AHB_ARB RK29XX_IRQ(63)
-#define IRQ_A8IRQ0 RK29XX_IRQ(64)
-#define IRQ_A8IRQ1 RK29XX_IRQ(65)
-#define IRQ_A8IRQ2 RK29XX_IRQ(66)
-#define IRQ_A8IRQ3 RK29XX_IRQ(67)
-
-#define NR_AIC_IRQS (IRQ_A8IRQ3+1)
-#define NR_GPIO_IRQS (7*32)
-#define NR_BOARD_IRQS 64
-#define NR_IRQS (NR_AIC_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS)
-#endif
+++ /dev/null
-#include <plat/key.h>
+++ /dev/null
-/* arch/arm/mach-rk29/include/mach/loader.h
- *
- * Copyright (C) 2011 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __ASM_ARCH_RK29_LOADER_H
-#define __ASM_ARCH_RK29_LOADER_H
-
-#define SYS_LOADER_ERR_FLAG 0x1888AAFF
-#define SYS_LOADER_REBOOT_FLAG 0x5242C300 //high 24 bits is tag, low 8 bits is type
-#define SYS_KERNRL_REBOOT_FLAG 0xC3524200 //high 24 bits is tag, low 8 bits is type
-
-enum {
- BOOT_NORMAL = 0,
- BOOT_LOADER, /* enter loader rockusb mode */
- BOOT_MASKROM, /* enter maskrom rockusb mode*/
- BOOT_RECOVER, /* enter recover */
- BOOT_NORECOVER, /* do not enter recover */
- BOOT_WINCE, /* FOR OTHER SYSTEM */
- BOOT_WIPEDATA, /* enter recover and wipe data. */
- BOOT_WIPEALL, /* enter recover and wipe all data. */
- BOOT_CHECKIMG, /* check firmware img with backup part(in loader mode)*/
- BOOT_MAX /* MAX VALID BOOT TYPE.*/
-};
-
-#endif
+++ /dev/null
-/* arch/arm/mach-rk29/include/mach/memory.h
- *
- * Copyright (C) 2010 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ASM_ARCH_RK29_MEMORY_H
-#define __ASM_ARCH_RK29_MEMORY_H
-
-#include <asm/page.h>
-#include <asm/sizes.h>
-#include <linux/version.h>
-
-/* physical offset of RAM */
-#define PHYS_OFFSET UL(0x60000000)
-
-#define CONSISTENT_DMA_SIZE SZ_8M
-
-#if !defined(__ASSEMBLY__) && defined(CONFIG_ZONE_DMA)
-
-/*
- * Restrict DMA-able region to workaround silicon bug. The bug
- * restricts memory available for GPU hardware to be below 512M.
- */
-#define ARM_DMA_ZONE_SIZE SZ_512M
-
-static inline void
-__arch_adjust_zones(int node, unsigned long *zone_size, unsigned long *zhole_size)
-{
- unsigned long dma_size = ARM_DMA_ZONE_SIZE >> PAGE_SHIFT;
-
- if (node || (zone_size[0] <= dma_size))
- return;
-
- zone_size[1] = zone_size[0] - dma_size;
- zone_size[0] = dma_size;
- zhole_size[1] = zhole_size[0];
- zhole_size[0] = 0;
-}
-
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36))
-#define arch_adjust_zones(zone_size, zhole_size) __arch_adjust_zones(0, zone_size, zhole_size)
-#else
-#define arch_adjust_zones(node, zone_size, zhole_size) __arch_adjust_zones(node, zone_size, zhole_size)
-#endif
-
-#endif /* CONFIG_ZONE_DMA */
-
-/*
- * SRAM memory whereabouts
- */
-#define SRAM_CODE_OFFSET 0xFEF00000
-#define SRAM_CODE_END 0xFEF02FFF
-#define SRAM_DATA_OFFSET 0xFEF03000
-#define SRAM_DATA_END 0xFEF03FFF
-
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34))
-#define dmac_clean_range(start, end) dmac_map_area(start, end - start, DMA_TO_DEVICE)
-#define dmac_inv_range(start, end) dmac_unmap_area(start, end - start, DMA_FROM_DEVICE)
-#endif
-
-#endif
-
+++ /dev/null
-/*
- * Very simple (yet, for some reason, very effective) memory tester.
- * Originally by Simon Kirby <sim@stormix.com> <sim@neato.org>
- * Version 2 by Charles Cazabon <charlesc-memtester@pyropus.ca>
- * Version 3 not publicly released.
- * Version 4 rewrite:
- * Copyright (C) 2007-2009 Charles Cazabon <charlesc-memtester@pyropus.ca>
- * Licensed under the terms of the GNU General Public License version 2 (only).
- * See the file COPYING for details.
- *
- * This file contains the declarations for external variables from the main file.
- * See other comments in that file.
- *
- */
-
-
-/* extern declarations. */
-
-extern void memtester(void);
\ No newline at end of file
+++ /dev/null
-#ifndef PM_VOL_H\r
-#define PM_VOL_H\r
-\r
-\r
-#if defined(CONFIG_RK29_SPI_INSRAM)||defined(CONFIG_RK29_PWM_INSRAM)||defined(CONFIG_RK29_I2C_INSRAM)\r
-\r
-void interface_ctr_reg_pread(void);\r
-void i2c_interface_ctr_reg_pread(void);\r
-unsigned int __sramfunc rk29_suspend_voltage_set(unsigned int vol);\r
-void __sramfunc rk29_suspend_voltage_resume(unsigned int vol);\r
-\r
-#else\r
-\r
-#define interface_ctr_reg_pread()\r
-#define i2c_interface_ctr_reg_pread()\r
-static unsigned int __sramfunc rk29_suspend_voltage_set(unsigned int vol) { return 0; }\r
-#define rk29_suspend_voltage_resume(a)\r
-\r
-#endif\r
-\r
-#endif\r
+++ /dev/null
-/* arch/arm/mach-rk29/include/mach/pmu.h
- *
- * Copyright (C) 2010 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ARCH_ARM_MACH_RK29_PMU_H
-#define __ARCH_ARM_MACH_RK29_PMU_H
-
-#include <linux/irqflags.h>
-#include <asm/io.h>
-#include <mach/rk29_iomap.h>
-
-#define PMU_WAKEUP_EN0 0x00
-#define PMU_WAKEUP_EN1 0x04
-#define PMU_WAKEUP_EN2 0x08
-#define PMU_PD_CON 0x10
-#define PMU_MISC_CON 0x14
-#define PMU_PLL_CNT 0x18
-#define PMU_PD_ST 0x1c
-#define PMU_INT_ST 0x20
-
-enum pmu_power_domain {
- PD_ARM_CORE = 0,
- PD_NEON,
- PD_ETM_DBG,
- PD_L2_CACHE,
- PD_VCODEC,
- PD_DISPLAY,
- PD_GPU,
- PD_PERIPHERAL,
- PD_MINI,
-};
-
-static inline bool pmu_power_domain_is_on(enum pmu_power_domain pd)
-{
- return !(readl(RK29_PMU_BASE + PMU_PD_ST) & (1 << pd));
-}
-
-void pmu_set_power_domain(enum pmu_power_domain pd, bool on);
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2010 RockChip Electronics Co. Ltd.
- * ZhenFu Fang <fzf@rock-chips.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef __RK29_DMA_PL330_H_
-#define __RK29_DMA_PL330_H_
-
-#define RK29_DMAF_AUTOSTART (1 << 0)
-#define RK29_DMAF_CIRCULAR (1 << 1)
-
-/*
- * PL330 can assign any channel to communicate with
- * any of the peripherals attched to the DMAC.
- * For the sake of consistency across client drivers,
- * We keep the channel names unchanged and only add
- * missing peripherals are added.
- * Order is not important since rk29 PL330 API driver
- * use these just as IDs.
- */
-enum dma_ch {
- DMACH_UART0_TX,
- DMACH_UART0_RX,
- DMACH_I2S_8CH_TX,
- DMACH_I2S_8CH_RX,
- DMACH_I2S_2CH_TX,
- DMACH_I2S_2CH_RX,
- DMACH_SPDIF,
- DMACH_HSADC,
- DMACH_SDMMC,
- DMACH_SDIO,
- DMACH_EMMC,
- DMACH_UART1_TX,
- DMACH_UART1_RX,
- DMACH_UART2_TX,
- DMACH_UART2_RX,
- DMACH_UART3_TX,
- DMACH_UART3_RX,
- DMACH_SPI0_TX,
- DMACH_SPI0_RX,
- DMACH_SPI1_TX,
- DMACH_SPI1_RX,
- DMACH_PID_FILTER,
- DMACH_DMAC0_MEMTOMEM,
- /* END Marker, also used to denote a reserved channel */
- DMACH_MAX,
-};
-
-static inline bool rk29_dma_has_circular(void)
-{
- return true;
-}
-
-/*
- * Every PL330 DMAC has max 32 peripheral interfaces,
- * of which some may be not be really used in your
- * DMAC's configuration.
- * Populate this array of 32 peri i/fs with relevant
- * channel IDs for used peri i/f and DMACH_MAX for
- * those unused.
- *
- * The platforms just need to provide this info
- * to the rk29 DMA API driver for PL330.
- */
-struct rk29_pl330_platdata {
- enum dma_ch peri[32];
-};
-
-#include <mach/dma.h>
-
-#endif /* __RK29_DMA_PL330_H_ */
+++ /dev/null
-#include <plat/ipp.h>
+++ /dev/null
-/*
- camera.h - PXA camera driver header file
-
- Copyright (C) 2003, Intel Corporation
- Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-*/
-#ifndef __ASM_ARCH_CAMERA_RK29_H_
-
-#define __ASM_ARCH_CAMERA_RK29_H_
-#define RK29_CAM_DRV_NAME "rk29-camera"
-
-#include <plat/rk_camera.h>
-
-
-#define CONFIG_CAMERA_SCALE_CROP_MACHINE RK_CAM_SCALE_CROP_IPP
-
-#if (CONFIG_CAMERA_SCALE_CROP_MACHINE==RK_CAM_SCALE_CROP_ARM)
- #define CAMERA_SCALE_CROP_MACHINE "arm"
-#elif (CONFIG_CAMERA_SCALE_CROP_MACHINE==RK_CAM_SCALE_CROP_IPP)
- #define CAMERA_SCALE_CROP_MACHINE "ipp"
-#elif (CONFIG_CAMERA_SCALE_CROP_MACHINE==RK_CAM_SCALE_CROP_RGA)
- #define CAMERA_SCALE_CROP_MACHINE "rga"
-#elif (CONFIG_CAMERA_SCALE_CROP_MACHINE==RK_CAM_SCALE_CROP_PP)
- #define CAMERA_SCALE_CROP_MACHINE "pp"
-#endif
-
-#if (CONFIG_CAMERA_SCALE_CROP_MACHINE == RK_CAM_SCALE_CROP_ARM)
- #define CAMERA_VIDEOBUF_ARM_ACCESS 1
-#else
- #define CAMERA_VIDEOBUF_ARM_ACCESS 0
-#endif
-
-#endif
+++ /dev/null
-/* arch/arm/mach-rk29/include/mach/rk29_iomap.h
- *
- * Copyright (C) 2010 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ASM_ARCH_RK29_IOMAP_H
-#define __ASM_ARCH_RK29_IOMAP_H
-
-#include <asm/sizes.h>
-
-/*
- * RK29 IO memory map:
- *
- * Virt Phys Size What
- * ---------------------------------------------------------------------------
- * 10000000 1M CPU L1 AXI Interconnect
- * FEA00000 10100000 1200K
- * 10300000 1M Peri AXI Interconnect
- * FEC00000 10500000 16K NANDC
- * 11000000 1M SMC Bank0
- * 12000000 1M SMC Bank1
- * 15000000 1M CPU L2 AXI Interconnect
- * FED00000 20000000 640K APB
- * FEF00000 0 16K SRAM
- */
-
-#define RK29_ADDR_BASE0 0xFEA00000
-#define RK29_ADDR_BASE1 0xFED00000
-
-#define RK29_SDRAM_PHYS 0x60000000U
-#define RK29_AXI1_PHYS 0x10000000
-#define RK29_AXI0_PHYS 0x1012C000
-#define RK29_PERI_PHYS 0x10140000
-
-//CPU system AXI 1
-#define RK29_BOOTROM_PHYS 0x10100000
-#define RK29_BOOTROM_SIZE SZ_16K
-#define RK29_VCODEC_PHYS 0x10104000
-#define RK29_VCODEC_SIZE SZ_16K
-#define RK29_VCODEC_BASE (RK29_ADDR_BASE0+0x104000)
-#define RK29_VIP_PHYS 0x10108000
-#define RK29_VIP_SIZE SZ_16K
-#define RK29_VIP_BASE (RK29_ADDR_BASE0+0x108000)
-#define RK29_LCDC_PHYS 0x1010C000
-#define RK29_LCDC_SIZE SZ_16K
-#define RK29_LCDC_BASE (RK29_ADDR_BASE0+0x10C000)
-#define RK29_IPP_PHYS 0x10110000
-#define RK29_IPP_SIZE SZ_16K
-#define RK29_IPP_BASE (RK29_ADDR_BASE0+0x110000)
-#define RK29_EBC_PHYS 0x10114000
-#define RK29_EBC_SIZE SZ_16K
-#define RK29_I2S_8CH_PHYS 0x10118000
-#define RK29_I2S_8CH_SIZE SZ_16K
-#define RK29_I2S_2CH_PHYS 0x1011C000
-#define RK29_I2S_2CH_SIZE SZ_8K
-#define RK29_I2S0_BASE (RK29_ADDR_BASE0+0x11C000)
-#define RK29_SPDIF_PHYS 0x1011E000
-#define RK29_SPDIF_SIZE SZ_8K
-#define RK29_GPU_PHYS 0x10120000
-#define RK29_GPU_SIZE SZ_16K
-#define RK29_GPU_BASE (RK29_ADDR_BASE0+0x120000)
-#define RK29_DDRC_PHYS 0x10124000
-#define RK29_DDRC_BASE (RK29_ADDR_BASE0+0x124000)
-#define RK29_DDRC_SIZE SZ_16K
-
-//CPU system AXI 0
-#define RK29_GICCPU_PHYS 0x1012C000
-#define RK29_GICCPU_BASE (RK29_ADDR_BASE0+0x12C000)
-#define RK29_GICCPU_SIZE SZ_8K
-#define RK29_GICPERI_PHYS 0x1012E000
-#define RK29_GICPERI_BASE (RK29_ADDR_BASE0+0x12E000)
-#define RK29_GICPERI_SIZE SZ_8K
-#define RK29_CPU_AXI_BUS0_PHYS 0x15000000
-
-//peri system
-#define RK29_USBHOST_PHYS 0x10140000
-#define RK29_USBHOST_SIZE SZ_256K
-#define RK29_USBOTG0_PHYS 0x10180000
-#define RK29_USBOTG0_SIZE SZ_256K
-#define RK29_USBOTG1_PHYS 0x101c0000
-#define RK29_USBOTG1_SIZE SZ_256K
-#define RK29_MAC_PHYS 0x10204000
-#define RK29_MAC_SIZE SZ_16K
-#define RK29_HOSTIF_PHYS 0x1020C000
-#define RK29_HOSTIF_SIZE SZ_16K
-#define RK29_HSADC_PHYS 0x10210000
-#define RK29_HSADC_SIZE SZ_16K
-#define RK29_SDMMC0_PHYS 0x10214000
-#define RK29_SDMMC0_SIZE SZ_16K
-#define RK29_SDMMC1_PHYS 0x10218000
-#define RK29_SDMMC1_SIZE SZ_16K
-#define RK29_EMMC_PHYS 0x1021C000
-#define RK29_EMMC_SIZE SZ_16K
-#define RK29_PIDF_PHYS 0x10220000
-#define RK29_EMMC_SIZE SZ_16K
-#define RK29_ARBITER0_PHYS 0x10224000
-#define RK29_ARBITER0_SIZE SZ_16K
-#define RK29_ARBITER1_PHYS 0x10228000
-#define RK29_ARBITER1_SIZE SZ_16K
-#define RK29_PERI_AXI_BUS0_PHYS 0x10300000
-
-#define RK29_NANDC_PHYS 0x10500000
-#define RK29_NANDC_BASE 0xFEC00000
-#define RK29_NANDC_SIZE SZ_16K
-
-//CPU AXI 1 APB
-#define RK29_CRU_PHYS 0x20000000
-#define RK29_CRU_BASE RK29_ADDR_BASE1
-#define RK29_CRU_SIZE SZ_4K
-#define RK29_PMU_PHYS 0x20004000
-#define RK29_PMU_BASE (RK29_ADDR_BASE1 + 0x4000)
-#define RK29_PMU_SIZE SZ_4K
-#define RK29_GRF_BASE (RK29_ADDR_BASE1+0x8000)
-#define RK29_GRF_PHYS 0x20008000
-#define RK29_GRF_SIZE SZ_16K
-#define RK29_RTC_PHYS 0x2000C000
-#define RK29_RTC_SIZE SZ_16K
-#define RK29_EFUSE_PHYS 0x20010000
-#define RK29_EFUSE_SIZE SZ_16K
-#define RK29_TZPC_PHYS 0x20014000
-#define RK29_TZPC_SIZE SZ_16K
-#define RK29_SDMAC0_PHYS 0x20018000
-#define RK29_SDMAC0_SIZE SZ_16K
-#define RK29_SDMAC0_BASE (RK29_ADDR_BASE1+0x18000)
-#define RK29_DMAC0_PHYS 0x2001C000
-#define RK29_DMAC0_SIZE SZ_16K
-#define RK29_DMAC0_BASE (RK29_ADDR_BASE1+0x1C000)
-#define RK29_DEBUG_PHYS 0x20024000
-#define RK29_DEBUG_SIZE SZ_16K
-#define RK29_I2C0_PHYS 0x2002C000
-#define RK29_I2C0_BASE (RK29_ADDR_BASE1+0x2C000)
-#define RK29_I2C0_SIZE SZ_16K
-#define RK29_UART0_PHYS 0x20030000
-#define RK29_UART0_SIZE SZ_4K
-#define RK29_GPIO0_BASE (RK29_ADDR_BASE1+0x34000)
-#define RK29_GPIO0_PHYS 0x20034000
-#define RK29_GPIO0_SIZE SZ_16K
-#define RK29_TIMER0_BASE (RK29_ADDR_BASE1+0x38000)
-#define RK29_TIMER0_PHYS 0x20038000
-#define RK29_TIMER0_SIZE SZ_8K
-#define RK29_TIMER1_BASE (RK29_ADDR_BASE1+0x3A000)
-#define RK29_TIMER1_PHYS 0x2003A000
-#define RK29_TIMER1_SIZE SZ_8K
-#define RK29_GPIO4_BASE (RK29_ADDR_BASE1+0x3C000)
-#define RK29_GPIO4_PHYS 0x2003C000
-#define RK29_GPIO4_SIZE SZ_8K
-#define RK29_GPIO6_BASE (RK29_ADDR_BASE1+0x3E000)
-#define RK29_GPIO6_PHYS 0x2003E000
-#define RK29_GPIO6_SIZE SZ_8K
-
-//peri system APB
-#define RK29_TIMER2_BASE (RK29_ADDR_BASE1+0x44000)
-#define RK29_TIMER2_PHYS 0x20044000
-#define RK29_TIMER2_SIZE SZ_16K
-#define RK29_TIMER3_BASE (RK29_ADDR_BASE1+0x48000)
-#define RK29_TIMER3_PHYS 0x20048000
-#define RK29_TIMER3_SIZE SZ_16K
-#define RK29_WDT_PHYS 0x2004C000
-#define RK29_WDT_SIZE SZ_16K
-#define RK29_PWM_BASE (RK29_ADDR_BASE1+0x50000)
-#define RK29_PWM_PHYS 0x20050000
-#define RK29_PWM_SIZE SZ_16K
-#define RK29_I2C1_PHYS 0x20054000
-#define RK29_I2C1_BASE (RK29_ADDR_BASE1+0x54000)
-#define RK29_I2C1_SIZE SZ_16K
-#define RK29_I2C2_PHYS 0x20058000
-#define RK29_I2C2_BASE (RK29_ADDR_BASE1+0x58000)
-#define RK29_I2C2_SIZE SZ_16K
-#define RK29_I2C3_PHYS 0x2005C000
-#define RK29_I2C3_BASE (RK29_ADDR_BASE1+0x5c000)
-#define RK29_I2C3_SIZE SZ_16K
-#define RK29_UART1_PHYS 0x20060000
-#define RK29_UART1_BASE (RK29_ADDR_BASE1+0x60000)
-#define RK29_UART1_SIZE SZ_4K
-#define RK29_UART2_PHYS 0x20064000
-#define RK29_UART2_SIZE SZ_4K
-#define RK29_UART3_PHYS 0x20068000
-#define RK29_UART3_SIZE SZ_4K
-#define RK29_TIMER2_SIZE SZ_16K
-#define RK29_ADC_PHYS 0x2006C000
-#define RK29_ADC_SIZE SZ_16K
-#define RK29_SPI0_PHYS 0x20070000
-#define RK29_SPI0_BASE (RK29_ADDR_BASE1+0x70000)
-#define RK29_SPI0_SIZE SZ_16K
-#define RK29_SPI1_PHYS 0x20074000
-#define RK29_SPI1_BASE (RK29_ADDR_BASE1+0x74000)
-#define RK29_SPI1_SIZE SZ_16K
-#define RK29_DMAC1_PHYS 0x20078000
-#define RK29_DMAC1_SIZE SZ_16K
-#define RK29_DMAC1_BASE (RK29_ADDR_BASE1+0x78000)
-#define RK29_SMC_PHYS 0x2007C000
-#define RK29_SMC_SIZE SZ_16K
-#define RK29_GPIO1_BASE (RK29_ADDR_BASE1+0x80000)
-#define RK29_GPIO1_PHYS 0x20080000
-#define RK29_GPIO1_SIZE SZ_16K
-#define RK29_GPIO2_BASE (RK29_ADDR_BASE1+0x84000)
-#define RK29_GPIO2_PHYS 0x20084000
-#define RK29_GPIO2_SIZE SZ_16K
-#define RK29_GPIO3_BASE (RK29_ADDR_BASE1+0x88000)
-#define RK29_GPIO3_PHYS 0x20088000
-#define RK29_GPIO3_SIZE SZ_16K
-#define RK29_GPIO5_BASE (RK29_ADDR_BASE1+0x8C000)
-#define RK29_GPIO5_PHYS 0x2008C000
-#define RK29_GPIO5_SIZE SZ_16K
-#endif
+++ /dev/null
-#ifndef __RK29_LIGHTSENSOR_H__
-#define __RK29_LIGHTSENSOR_H__
-
-#include <linux/ioctl.h>
-
-
-#define STARTUP_LEV_LOW 0
-#define SHUTDOWN_LEV_HIGH 1
-
-#define LSR_GPIO RK29_PIN5_PA2
-#define LSR_IOCTL_NR_ENABLE 1
-#define LSR_IOCTL_NR_SETRATE 2
-#define LSR_IOCTL_NR_DEVNAME 3
-#define LSR_IOCTL_NR_SWICTH 4
-
-
-#define LSR_IOCTL_ENABLE _IOR('l', LSR_IOCTL_NR_ENABLE, unsigned long )
-#define LSR_IOCTL_SETRATE _IOR('l', LSR_IOCTL_NR_SETRATE, unsigned long )
-#define LSR_IOCTL_DEVNAME _IOR('l', LSR_IOCTL_NR_DEVNAME, unsigned long )
-#define LSR_IOCTL_SWICTH _IOR('l', LSR_IOCTL_NR_SWICTH, unsigned long )
-
-#define LSR_ON 0
-#define LSR_OFF 1
-#define LSR_NAME "rk29-lsr"
-
-#define RATE(x) (1000/(x))
-
-struct rk29_lsr_platform_data {
- int gpio;
- char *desc;
- int adc_chn;
- struct adc_client *client;
- struct timer_list timer;
- struct input_dev *input_dev;
- unsigned int delay_time;
- unsigned int rate;
- int oldresult;
- struct mutex lsr_mutex;
- int active_low;
- unsigned int lsr_state;
- unsigned int timer_on;
-};
-
-
-
-#endif
+++ /dev/null
-
-/*
- * arch/arm/mach-rk29/include/mach/rk29_nand.h
- *
- * Copyright (C) 2010 RockChip, Inc.
- * Author:
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ASM_ARCH_RK29_NAND_H
-#define __ASM_ARCH_RK29_NAND_H
-
-
-//BCHCTL¼Ä´æÆ÷
-#define BCH_WR 0x0002
-#define BCH_RST 0x0001
-//FLCTL¼Ä´æÆ÷
-#define FL_RDY (0x1<<20)
-#define FL_LBA_EN (0x1<<11)
-#define FL_COR_EN (0x1<<10)
-#define FL_INT_EN (0x1<<9)
-#define FL_INTCLR (0x1<<8)
-#define FL_STMOD (0x1<<7)
-#define FL_TRCNT (0x3<<5)
-#define FL_STADDR (0x1<<4)
-#define FL_BYPASS (0x1<<3)
-#define FL_START (0x1<<2)
-#define FL_RDN (0x1<<1)
-#define FL_RST (0x1<<0)
-//FMCTL¼Ä´æÆ÷
-#define FMC_WP (0x1<<8)
-#define FMC_FRDY (0x1<<9)
-#define FMC_FRDY_INT_EN (0x1<<10)
-#define FMC_FRDY_INT_CLR (0x1<<11)
-#define FMC_WIDTH_16 (0x1<<12)
-//FMWAIT¼Ä´æÆ÷
-#define FMW_RWCS_OFFSET 0
-#define FMW_RWPW_OFFSET 5
-#define FMW_RDY (0x1<<11)
-#define FMW_CSRW_OFFSET 12
-#define FMW_DLY_OFFSET 24//16
-
-struct rk29_nand_timing {
- unsigned int tCH; /* Enable signal hold time */
- unsigned int tCS; /* Enable signal setup time */
- unsigned int tWH; /* ND_nWE high duration */
- unsigned int tWP; /* ND_nWE pulse time */
- unsigned int tRH; /* ND_nRE high duration */
- unsigned int tRP; /* ND_nRE pulse width */
- unsigned int tR; /* ND_nWE high to ND_nRE low for read */
- unsigned int tWHR; /* ND_nWE high to ND_nRE low for status read */
- unsigned int tAR; /* ND_ALE low to ND_nRE low delay */
-};
-
-struct rk29_nand_cmdset {
- uint16_t read1;
- uint16_t read2;
- uint16_t program;
- uint16_t read_status;
- uint16_t read_id;
- uint16_t erase;
- uint16_t reset;
- uint16_t lock;
- uint16_t unlock;
- uint16_t lock_status;
-};
-
-typedef volatile struct tagCHIP_IF
-{
- uint32_t data;
- uint32_t addr;
- uint32_t cmd;
- uint32_t RESERVED[0x3d];
-}CHIP_IF, *pCHIP_IF;
-
-//NANDC Registers
-typedef volatile struct tagNANDC
-{
- volatile uint32_t FMCTL;
- volatile uint32_t FMWAIT;
- volatile uint32_t FLCTL;
- volatile uint32_t BCHCTL;
- volatile uint32_t MTRANS_CFG;
- volatile uint32_t MTRANS_SADDR0;
- volatile uint32_t MTRANS_SADDR1;
- volatile uint32_t MTRANS_STAT;
-
- volatile uint32_t BCHST[8];
- volatile uint32_t FLR1[(0x160-0x40)/4];
- volatile uint32_t NANDC_VER;
- volatile uint32_t FLR2[(0x200-0x164)/4];
- volatile uint32_t spare[0x200/4];
- volatile uint32_t RESERVED2[0x400/4];
- volatile CHIP_IF chip[8];
- volatile uint32_t buf[0x800/4];
-}NANDC, *pNANDC;
-
-
-struct rk29_nand_flash {
- const struct rk29_nand_timing *timing; /* NAND Flash timing */
- const struct rk29_nand_cmdset *cmdset;
-
- uint32_t page_per_block; /* Pages per block (PG_PER_BLK) */
- uint32_t page_size; /* Page size in bytes (PAGE_SZ) */
- uint32_t flash_width; /* Width of Flash memory (DWIDTH_M) */
- uint32_t num_blocks; /* Number of physical blocks in Flash */
- uint32_t chip_id;
-};
-
-struct rk29_nand_platform_data {
-
- int width; /* data bus width in bytes */
- int hw_ecc; /* 1:hw ecc, 0: soft ecc */
- struct mtd_partition *parts;
- unsigned int nr_parts;
- size_t num_flash;
- int (*io_init)(void);
- int (*io_deinit)(void);
-};
-
-
-#endif /* __ASM_ARCH_RK29_NAND_H */
-
+++ /dev/null
-\r
-#ifndef __DRIVER_IRDA_SMC_H\r
-#define __DRIVER_IRDA_SMC_H\r
-\r
-extern int smc0_init(u8 **base_addr);\r
-extern void smc0_exit(void);\r
-extern int smc0_write(u32 addr, u32 data);\r
-extern int smc0_read(u32 addr);\r
-extern int smc0_enable(int enable);\r
-#endif\r
-\r
+++ /dev/null
-#include <plat/sram.h>
+++ /dev/null
-/* arch/arm/mach-rk29/include/mach/system.h
- *
- * Copyright (C) 2010 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
- /***************
-* DEBUG
-****************/
-#define RESTART_DEBUG
-#ifdef RESTART_DEBUG
-#define restart_dbg(format, arg...) \
- printk("RESTART_DEBUG : " format "\n" , ## arg)
-#else
-#define restart_dbg(format, arg...) do {} while (0)
-#endif
-extern void rk29_arch_reset(int mode, const char *cmd);
-
-static inline void arch_reset(int mode, const char *cmd)
-{
-
- /*
- * debug trace
- */
- restart_dbg("%s->%s->%d->mode=%c cmd=%s",__FILE__,__FUNCTION__,__LINE__,mode,cmd);
-
- rk29_arch_reset(mode, cmd);
-}
-
-static inline void arch_idle(void)
-{
- cpu_do_idle();
-}
+++ /dev/null
-/* arch/arm/mach-rk29/include/mach/timex.h
- *
- * Copyright (C) 2010 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ASM_ARCH_RK29_TIMEX_H
-#define __ASM_ARCH_RK29_TIMEX_H
-
-#define CLOCK_TICK_RATE 1000000
-
-#endif
+++ /dev/null
-/* arch/arm/mach-rk29/include/mach/uncompress.h
- *
- * Copyright (C) 2010 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ASM_ARCH_RK29_UNCOMPRESS_H
-
-#include <linux/serial_reg.h>
-#include <mach/rk29_iomap.h>
-
-static volatile u32 *UART = (u32 *)RK29_UART1_PHYS;
-
-static void putc(int c)
-{
- while (!(UART[UART_LSR] & UART_LSR_THRE))
- barrier();
- UART[UART_TX] = c;
-}
-
-static inline void flush(void)
-{
-}
-
-static inline void arch_decomp_setup(void)
-{
-}
-
-static inline void arch_decomp_wdog(void)
-{
-}
-
-#endif
+++ /dev/null
-/* arch/arm/mach-rk29/include/mach/vmalloc.h
- *
- * Copyright (C) 2010 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ASM_ARCH_RK29_VMALLOC_H
-#define __ASM_ARCH_RK29_VMALLOC_H
-
-#define VMALLOC_END 0xFE800000
-
-#endif
-
+++ /dev/null
-/* arch/arm/mach-rk29/include/mach/vcodec.h
- *
- * Copyright (C) 2010 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ARCH_ARM_MACH_RK29_VPU_H
-#define __ARCH_ARM_MACH_RK29_VPU_H
-
-#include <linux/ioctl.h> /* needed for the _IOW etc stuff used later */
-
-#define VPU_IRQ_EVENT_DEC_BIT BIT(0)
-#define VPU_IRQ_EVENT_DEC_IRQ_BIT BIT(1)
-#define VPU_IRQ_EVENT_PP_IRQ_BIT BIT(2)
-#define VPU_IRQ_EVENT_ENC_BIT BIT(8)
-#define VPU_IRQ_EVENT_ENC_IRQ_BIT BIT(9)
-
-/*
- * Ioctl definitions
- */
-
-#define VPU_aclk_vepu 0
-#define VPU_hclk_vepu 1
-#define VPU_aclk_ddr_vepu 2
-#define VPU_hclk_cpu_vcodec 3
-
-/* Use 'k' as magic number */
-#define VPU_IOC_MAGIC 'k'
-
-#define VPU_IOC_CLOCK_ON _IOW(VPU_IOC_MAGIC, 1, unsigned long)
-#define VPU_IOC_CLOCK_OFF _IOW(VPU_IOC_MAGIC, 2, unsigned long)
-
-#define VPU_IOC_CLOCK_RESET _IOW(VPU_IOC_MAGIC, 3, unsigned long)
-#define VPU_IOC_CLOCK_UNRESET _IOW(VPU_IOC_MAGIC, 4, unsigned long)
-
-#define VPU_IOC_DOMAIN_ON _IO(VPU_IOC_MAGIC, 5)
-#define VPU_IOC_DOMAIN_OFF _IO(VPU_IOC_MAGIC, 6)
-
-#define VPU_IOC_TEST _IO(VPU_IOC_MAGIC, 7)
-
-#define VPU_IOC_WR_DEC _IOW(VPU_IOC_MAGIC, 8, unsigned long)
-#define VPU_IOC_WR_DEC_PP _IOW(VPU_IOC_MAGIC, 9, unsigned long)
-#define VPU_IOC_WR_ENC _IOW(VPU_IOC_MAGIC, 10, unsigned long)
-#define VPU_IOC_WR_PP _IOW(VPU_IOC_MAGIC, 11, unsigned long)
-
-#define VPU_IOC_RD_DEC _IOW(VPU_IOC_MAGIC, 12, unsigned long)
-#define VPU_IOC_RD_DEC_PP _IOW(VPU_IOC_MAGIC, 13, unsigned long)
-#define VPU_IOC_RD_ENC _IOW(VPU_IOC_MAGIC, 14, unsigned long)
-#define VPU_IOC_RD_PP _IOW(VPU_IOC_MAGIC, 15, unsigned long)
-
-#define VPU_IOC_CLS_IRQ _IOW(VPU_IOC_MAGIC, 16, unsigned long)
-
-#endif
+++ /dev/null
-/* arch/arm/mach-rk29/include/mach/vpu_mem.h
- *
- * Copyright (C) 2007 Google, Inc.
- * author: chenhengming chm@rock-chips.com
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ARCH_ARM_MACH_RK29_VPU_MEM_H
-#define __ARCH_ARM_MACH_RK29_VPU_MEM_H
-
-
-#define VPU_MEM_IOCTL_MAGIC 'p'
-#define VPU_MEM_GET_PHYS _IOW(VPU_MEM_IOCTL_MAGIC, 1, unsigned int)
-#define VPU_MEM_GET_TOTAL_SIZE _IOW(VPU_MEM_IOCTL_MAGIC, 2, unsigned int)
-#define VPU_MEM_ALLOCATE _IOW(VPU_MEM_IOCTL_MAGIC, 3, unsigned int)
-#define VPU_MEM_FREE _IOW(VPU_MEM_IOCTL_MAGIC, 4, unsigned int)
-#define VPU_MEM_CACHE_FLUSH _IOW(VPU_MEM_IOCTL_MAGIC, 5, unsigned int)
-#define VPU_MEM_DUPLICATE _IOW(VPU_MEM_IOCTL_MAGIC, 6, unsigned int)
-#define VPU_MEM_LINK _IOW(VPU_MEM_IOCTL_MAGIC, 7, unsigned int)
-#define VPU_MEM_CACHE_CLEAN _IOW(VPU_MEM_IOCTL_MAGIC, 8, unsigned int)
-#define VPU_MEM_CACHE_INVALID _IOW(VPU_MEM_IOCTL_MAGIC, 9, unsigned int)
-#define VPU_MEM_POOL_SET _IOW(VPU_MEM_IOCTL_MAGIC, 10, unsigned int)
-#define VPU_MEM_POOL_UNSET _IOW(VPU_MEM_IOCTL_MAGIC, 11, unsigned int)
-#define VPU_MEM_POOL_CHECK _IOW(VPU_MEM_IOCTL_MAGIC, 12, unsigned int)
-
-struct vpu_mem_platform_data
-{
- const char* name;
- /* starting physical address of memory region */
- unsigned long start;
- /* size of memory region */
- unsigned long size;
- /* set to indicate maps of this region should be cached, if a mix of
- * cached and uncached is desired, set this and open the device with
- * O_SYNC to get an uncached region */
- unsigned cached;
- /* The MSM7k has bits to enable a write buffer in the bus controller*/
- unsigned buffered;
-};
-
-#endif //__ARCH_ARM_MACH_RK29_VPU_MEM_H
-
+++ /dev/null
-/* arch/arm/mach-rk29/io.c
- *
- * Copyright (C) 2010 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-
-#include <asm/page.h>
-#include <mach/rk29_iomap.h>
-#include <asm/mach/map.h>
-#include <mach/board.h>
-
-#define RK29_DEVICE(name) { \
- .virtual = (unsigned long) RK29_##name##_BASE, \
- .pfn = __phys_to_pfn(RK29_##name##_PHYS), \
- .length = RK29_##name##_SIZE, \
- .type = MT_DEVICE_NONSHARED, \
- }
-
-static struct map_desc rk29_io_desc[] __initdata = {
- RK29_DEVICE(GICCPU),
- RK29_DEVICE(GICPERI),
- RK29_DEVICE(TIMER0),
- RK29_DEVICE(TIMER1),
- RK29_DEVICE(TIMER2),
- RK29_DEVICE(TIMER3),
- RK29_DEVICE(DDRC),
- RK29_DEVICE(UART1),
- RK29_DEVICE(PWM),
- RK29_DEVICE(GRF),
- RK29_DEVICE(CRU),
- RK29_DEVICE(PMU),
- RK29_DEVICE(GPIO0),
- RK29_DEVICE(GPIO1),
- RK29_DEVICE(GPIO2),
- RK29_DEVICE(GPIO3),
- RK29_DEVICE(GPIO4),
- RK29_DEVICE(GPIO5),
- RK29_DEVICE(GPIO6),
- RK29_DEVICE(NANDC),
- RK29_DEVICE(SPI0),
- RK29_DEVICE(SPI1),
- RK29_DEVICE(I2C0),
- RK29_DEVICE(I2C1),
- RK29_DEVICE(I2C2),
- RK29_DEVICE(I2C3),
- RK29_DEVICE(LCDC),
-#ifdef CONFIG_DDR_RECONFIG
- RK29_DEVICE(GPU),
- RK29_DEVICE(VCODEC),
- RK29_DEVICE(VIP),
- RK29_DEVICE(IPP),
- RK29_DEVICE(DMAC0),
- RK29_DEVICE(DMAC1),
- RK29_DEVICE(SDMAC0),
-#endif
-};
-
-extern void rk29_boot_mode_init_by_register(void);
-void __init rk29_map_common_io(void)
-{
- iotable_init(rk29_io_desc, ARRAY_SIZE(rk29_io_desc));
- rk29_boot_mode_init_by_register();
-}
+++ /dev/null
-/*
- * arch/arm/mach-rk29/iomux.c
- *
- *Copyright (C) 2010 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <asm/system.h>
-#include <asm/io.h>
-#include <linux/spinlock.h>
-
-#include <mach/rk29_iomap.h>
-#include <mach/iomux.h>
-
-
-static struct mux_config rk29_muxs[] = {
-/*
- * description mux mode mux mux
- * reg offset inter mode
- */
-///GPIO0L
-MUX_CFG(GPIO0B7_EBCGDOE_SMCOEN_NAME, GPIO0L, 30, 2, 0, DEFAULT)
-MUX_CFG(GPIO0B6_EBCSDSHR_SMCBLSN1_HOSTINT_NAME, GPIO0L, 28, 2, 0, DEFAULT)
-MUX_CFG(GPIO0B5_EBCVCOM_SMCBLSN0_NAME, GPIO0L, 26, 2, 0, DEFAULT)
-MUX_CFG(GPIO0B4_EBCBORDER1_SMCWEN_NAME, GPIO0L, 24, 2, 0, DEFAULT)
-MUX_CFG(GPIO0B3_EBCBORDER0_SMCADDR3_HOSTDATA3_NAME, GPIO0L, 22, 2, 0, DEFAULT)
-MUX_CFG(GPIO0B2_EBCSDCE2_SMCADDR2_HOSTDATA2_NAME, GPIO0L, 20, 2, 0, DEFAULT)
-MUX_CFG(GPIO0B1_EBCSDCE1_SMCADDR1_HOSTDATA1_NAME, GPIO0L, 18, 2, 0, DEFAULT)
-MUX_CFG(GPIO0B0_EBCSDCE0_SMCADDR0_HOSTDATA0_NAME, GPIO0L, 16, 2, 0, DEFAULT)
-MUX_CFG(GPIO0A7_MIIMDCLK_NAME, GPIO0L, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO0A6_MIIMD_NAME, GPIO0L, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO0A5_FLASHDQS_NAME, GPIO0L, 10, 2, 0, DEFAULT)
-///GPIO0H
-MUX_CFG(GPIO0D7_FLASHCSN6_NAME, GPIO0H, 30, 2, 0, DEFAULT)
-MUX_CFG(GPIO0D6_FLASHCSN5_NAME, GPIO0H, 28, 2, 0, DEFAULT)
-MUX_CFG(GPIO0D5_FLASHCSN4_NAME, GPIO0H, 26, 2, 0, DEFAULT)
-MUX_CFG(GPIO0D4_FLASHCSN3_NAME, GPIO0H, 24, 2, 0, DEFAULT)
-MUX_CFG(GPIO0D3_FLASHCSN2_NAME, GPIO0H, 22, 2, 0, DEFAULT)
-MUX_CFG(GPIO0D2_FLASHCSN1_NAME, GPIO0H, 20, 2, 0, DEFAULT)
-MUX_CFG(GPIO0D1_EBCGDCLK_SMCADDR4_HOSTDATA4_NAME, GPIO0H, 18, 2, 0, DEFAULT)
-MUX_CFG(GPIO0D0_EBCSDOE_SMCADVN_NAME, GPIO0H, 16, 2, 0, DEFAULT)
-MUX_CFG(GPIO0C7_EBCSDCE5_SMCDATA15_NAME, GPIO0H, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO0C6_EBCSDCE4_SMCDATA14_NAME, GPIO0H, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO0C5_EBCSDCE3_SMCDATA13_NAME, GPIO0H, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO0C4_EBCSDCE2_SMCDATA12_NAME, GPIO0H, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO0C3_EBCSDCE1_SMCDATA11_NAME, GPIO0H, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO0C2_EBCSDCE0_SMCDATA10_NAME, GPIO0H, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO0C1_EBCGDR1_SMCDATA9_NAME, GPIO0H, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO0C0_EBCGDSP_SMCDATA8_NAME, GPIO0H, 0, 2, 0, DEFAULT)
-///GPIO1L
-MUX_CFG(GPIO1B7_UART0SOUT_NAME, GPIO1L, 30, 2, 0, DEFAULT)
-MUX_CFG(GPIO1B6_UART0SIN_NAME, GPIO1L, 28, 2, 0, DEFAULT)
-MUX_CFG(GPIO1B5_PWM0_NAME, GPIO1L, 26, 2, 0, DEFAULT)
-MUX_CFG(GPIO1B4_VIPCLKOUT_NAME, GPIO1L, 24, 2, 0, DEFAULT)
-MUX_CFG(GPIO1B3_VIPDATA3_NAME, GPIO1L, 22, 2, 0, DEFAULT)
-MUX_CFG(GPIO1B2_VIPDATA2_NAME, GPIO1L, 20, 2, 0, DEFAULT)
-MUX_CFG(GPIO1B1_VIPDATA1_NAME, GPIO1L, 18, 2, 0, DEFAULT)
-MUX_CFG(GPIO1B0_VIPDATA0_NAME, GPIO1L, 16, 2, 0, DEFAULT)
-MUX_CFG(GPIO1A7_I2C1SCL_NAME, GPIO1L, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO1A6_I2C1SDA_NAME, GPIO1L, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO1A5_EMMCPWREN_PWM3_NAME, GPIO1L, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO1A4_EMMCWRITEPRT_SPI0CS1_NAME, GPIO1L, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO1A3_EMMCDETECTN_SPI1CS1_NAME, GPIO1L, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO1A2_SMCCSN1_NAME, GPIO1L, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO1A1_SMCCSN0_NAME, GPIO1L, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO1A0_FLASHCS7_MDDRTQ_NAME, GPIO1L, 0, 2, 0, DEFAULT)
-///GPIO1H
-MUX_CFG(GPIO1D7_SDMMC0DATA5_NAME, GPIO1H, 30, 2, 0, DEFAULT)
-MUX_CFG(GPIO1D6_SDMMC0DATA4_NAME, GPIO1H, 28, 2, 0, DEFAULT)
-MUX_CFG(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H, 26, 2, 0, DEFAULT)
-MUX_CFG(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H, 24, 2, 0, DEFAULT)
-MUX_CFG(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H, 22, 2, 0, DEFAULT)
-MUX_CFG(GPIO1D2_SDMMC0DATA0_NAME, GPIO1H, 20, 2, 0, DEFAULT)
-MUX_CFG(GPIO1D1_SDMMC0CMD_NAME, GPIO1H, 18, 2, 0, DEFAULT)
-MUX_CFG(GPIO1D0_SDMMC0CLKOUT_NAME, GPIO1H, 16, 2, 0, DEFAULT)
-MUX_CFG(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO1C2_SDMMC1CMD_NAME, GPIO1H, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO1C1_UART0RTSN_SDMMC1WRITEPRT_NAME, GPIO1H, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO1C0_UART0CTSN_SDMMC1DETECTN_NAME, GPIO1H, 0, 2, 0, DEFAULT)
-///GPIO2L
-MUX_CFG(GPIO2B7_I2C0SCL_NAME, GPIO2L, 30, 2, 0, DEFAULT)
-MUX_CFG(GPIO2B6_I2C0SDA_NAME, GPIO2L, 28, 2, 0, DEFAULT)
-MUX_CFG(GPIO2B5_UART3RTSN_I2C3SCL_NAME, GPIO2L, 26, 2, 0, DEFAULT)
-MUX_CFG(GPIO2B4_UART3CTSN_I2C3SDA_NAME, GPIO2L, 24, 2, 0, DEFAULT)
-MUX_CFG(GPIO2B3_UART3SOUT_NAME, GPIO2L, 22, 2, 0, DEFAULT)
-MUX_CFG(GPIO2B2_UART3SIN_NAME, GPIO2L, 20, 2, 0, DEFAULT)
-MUX_CFG(GPIO2B1_UART2SOUT_NAME, GPIO2L, 18, 2, 0, DEFAULT)
-MUX_CFG(GPIO2B0_UART2SIN_NAME, GPIO2L, 16, 2, 0, DEFAULT)
-MUX_CFG(GPIO2A7_UART2RTSN_NAME, GPIO2L, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO2A6_UART2CTSN_NAME, GPIO2L, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO2A5_UART1SOUT_NAME, GPIO2L, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO2A4_UART1SIN_NAME, GPIO2L, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO2A3_SDMMC0WRITEPRT_PWM2_NAME, GPIO2L, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO2A2_SDMMC0DETECTN_NAME, GPIO2L, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO2A1_SDMMC0DATA7_NAME, GPIO2L, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO2A0_SDMMC0DATA6_NAME, GPIO2L, 0, 2, 0, DEFAULT)
-///GPIO2H
-MUX_CFG(GPIO2D7_I2S0SDO3_MIITXD3_NAME, GPIO2H, 30, 2, 0, DEFAULT)
-MUX_CFG(GPIO2D6_I2S0SDO2_MIITXD2_NAME, GPIO2H, 28, 2, 0, DEFAULT)
-MUX_CFG(GPIO2D5_I2S0SDO1_MIIRXD3_NAME, GPIO2H, 26, 2, 0, DEFAULT)
-MUX_CFG(GPIO2D4_I2S0SDO0_MIIRXD2_NAME, GPIO2H, 24, 2, 0, DEFAULT)
-MUX_CFG(GPIO2D3_I2S0SDI_MIICOL_NAME, GPIO2H, 22, 2, 0, DEFAULT)
-MUX_CFG(GPIO2D2_I2S0LRCKRX_MIITXERR_NAME, GPIO2H, 20, 2, 0, DEFAULT)
-MUX_CFG(GPIO2D1_I2S0SCLK_MIICRS_NAME, GPIO2H, 18, 2, 0, DEFAULT)
-MUX_CFG(GPIO2D0_I2S0CLK_MIIRXCLKIN_NAME, GPIO2H, 16, 2, 0, DEFAULT)
-MUX_CFG(GPIO2C7_SPI1RXD_NAME, GPIO2H, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO2C6_SPI1TXD_NAME, GPIO2H, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO2C5_SPI1CSN0_NAME, GPIO2H, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO2C4_SPI1CLK_NAME, GPIO2H, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO2C3_SPI0RXD_NAME, GPIO2H, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO2C2_SPI0TXD_NAME, GPIO2H, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO2C1_SPI0CSN0_NAME, GPIO2H, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO2C0_SPI0CLK_NAME, GPIO2H, 0, 2, 0, DEFAULT)
-///GPIO3L
-MUX_CFG(GPIO3B7_EMMCDATA5_NAME, GPIO3L, 30, 2, 0, DEFAULT)
-MUX_CFG(GPIO3B6_EMMCDATA4_NAME, GPIO3L, 28, 2, 0, DEFAULT)
-MUX_CFG(GPIO3B5_EMMCDATA3_NAME, GPIO3L, 26, 2, 0, DEFAULT)
-MUX_CFG(GPIO3B4_EMMCDATA2_NAME, GPIO3L, 24, 2, 0, DEFAULT)
-MUX_CFG(GPIO3B3_EMMCDATA1_NAME, GPIO3L, 22, 2, 0, DEFAULT)
-MUX_CFG(GPIO3B2_EMMCDATA0_NAME, GPIO3L, 20, 2, 0, DEFAULT)
-MUX_CFG(GPIO3B1_EMMCMD_NAME, GPIO3L, 18, 2, 0, DEFAULT)
-MUX_CFG(GPIO3B0_EMMCLKOUT_NAME, GPIO3L, 16, 2, 0, DEFAULT)
-MUX_CFG(GPIO3A7_SMCADDR15_HOSTDATA15_NAME, GPIO3L, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO3A6_SMCADDR14_HOSTDATA14_NAME, GPIO3L, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO3A5_I2S1LRCKTX_NAME, GPIO3L, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO3A4_I2S1SDO_NAME, GPIO3L, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO3A3_I2S1SDI_NAME, GPIO3L, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO3A2_I2S1LRCKRX_NAME, GPIO3L, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO3A1_I2S1SCLK_NAME, GPIO3L, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO3A0_I2S1CLK_NAME, GPIO3L, 0, 2, 0, DEFAULT)
-///GPIO3H
-MUX_CFG(GPIO3D7_SMCADDR9_HOSTDATA9_NAME, GPIO3H, 30, 2, 0, DEFAULT)
-MUX_CFG(GPIO3D6_SMCADDR8_HOSTDATA8_NAME, GPIO3H, 28, 2, 0, DEFAULT)
-MUX_CFG(GPIO3D5_SMCADDR7_HOSTDATA7_NAME, GPIO3H, 26, 2, 0, DEFAULT)
-MUX_CFG(GPIO3D4_HOSTWRN_NAME, GPIO3H, 24, 2, 0, DEFAULT)
-MUX_CFG(GPIO3D3_HOSTRDN_NAME, GPIO3H, 22, 2, 0, DEFAULT)
-MUX_CFG(GPIO3D2_HOSTCSN_NAME, GPIO3H, 20, 2, 0, DEFAULT)
-MUX_CFG(GPIO3D1_SMCADDR19_HOSTADDR1_NAME, GPIO3H, 18, 2, 0, DEFAULT)
-MUX_CFG(GPIO3D0_SMCADDR18_HOSTADDR0_NAME, GPIO3H, 16, 2, 0, DEFAULT)
-MUX_CFG(GPIO3C7_SMCADDR17_HOSTDATA17_NAME, GPIO3H, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO3C6_SMCADDR16_HOSTDATA16_NAME, GPIO3H, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO3C5_SMCADDR12_HOSTDATA12_NAME, GPIO3H, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO3C4_SMCADDR11_HOSTDATA11_NAME, GPIO3H, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO3C3_SMCADDR10_HOSTDATA10_NAME, GPIO3H, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO3C2_SMCADDR13_HOSTDATA13_NAME, GPIO3H, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO3C1_EMMCDATA7_NAME, GPIO3H, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO3C0_EMMCDATA6_NAME, GPIO3H, 0, 2, 0, DEFAULT)
-///GPIO4L
-MUX_CFG(GPIO4B7_FLASHDATA15_NAME, GPIO4L, 30, 2, 0, DEFAULT)
-MUX_CFG(GPIO4B6_FLASHDATA14_NAME, GPIO4L, 28, 2, 0, DEFAULT)
-MUX_CFG(GPIO4B5_FLASHDATA13_NAME, GPIO4L, 26, 2, 0, DEFAULT)
-MUX_CFG(GPIO4B4_FLASHDATA12_NAME, GPIO4L, 24, 2, 0, DEFAULT)
-MUX_CFG(GPIO4B3_FLASHDATA11_NAME, GPIO4L, 22, 2, 0, DEFAULT)
-MUX_CFG(GPIO4B2_FLASHDATA10_NAME, GPIO4L, 20, 2, 0, DEFAULT)
-MUX_CFG(GPIO4B1_FLASHDATA9_NAME, GPIO4L, 18, 2, 0, DEFAULT)
-MUX_CFG(GPIO4B0_FLASHDATA8_NAME, GPIO4L, 16, 2, 0, DEFAULT)
-MUX_CFG(GPIO4A7_SPDIFTX_NAME, GPIO4L, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO4A6_OTG1DRVVBUS_NAME, GPIO4L, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO4A5_OTG0DRVVBUS_NAME, GPIO4L, 10, 2, 0, DEFAULT)
-///GPIO4H
-MUX_CFG(GPIO4D7_I2S0LRCKTX1_NAME, GPIO4H, 30, 2, 0, DEFAULT)
-MUX_CFG(GPIO4D6_I2S0LRCKTX0_NAME, GPIO4H, 28, 2, 0, DEFAULT)
-MUX_CFG(GPIO4D5_CPUTRACECTL_NAME, GPIO4H, 26, 2, 0, DEFAULT)
-MUX_CFG(GPIO4D4_CPUTRACECLK_NAME, GPIO4H, 24, 2, 0, DEFAULT)
-MUX_CFG(GPIO6C76_CPUTRACEDATA76_NAME, GPIO4H, 22, 2, 0, DEFAULT)
-MUX_CFG(GPIO6C54_CPUTRACEDATA54_NAME, GPIO4H, 20, 2, 0, DEFAULT)
-MUX_CFG(GPIO4D32_CPUTRACEDATA32_NAME, GPIO4H, 18, 2, 0, DEFAULT)
-MUX_CFG(GPIO4D10_CPUTRACEDATA10_NAME, GPIO4H, 16, 2, 0, DEFAULT)
-MUX_CFG(GPIO4C7_RMIIRXD0_MIIRXD0_NAME, GPIO4H, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO4C6_RMIIRXD1_MIIRXD1_NAME, GPIO4H, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO4C5_RMIICSRDVALID_MIIRXDVALID_NAME, GPIO4H, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO4C4_RMIIRXERR_MIIRXERR_NAME, GPIO4H, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO4C3_RMIITXD0_MIITXD0_NAME, GPIO4H, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO4C2_RMIITXD1_MIITXD1_NAME, GPIO4H, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO4C1_RMIITXEN_MIITXEN_NAME, GPIO4H, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO4C0_RMIICLKOUT_RMIICLKIN_NAME, GPIO4H, 0, 2, 0, DEFAULT)
-///GPIO5L
-MUX_CFG(GPIO5B7_HSADCCLKOUTGPSCLK_NAME, GPIO5L, 30, 2, 0, DEFAULT)
-MUX_CFG(GPIO5B6_HSADCDATA9_NAME, GPIO5L, 28, 2, 0, DEFAULT)
-MUX_CFG(GPIO5B5_HSADCDATA8_NAME, GPIO5L, 26, 2, 0, DEFAULT)
-MUX_CFG(GPIO5B4_HSADCDATA7_NAME, GPIO5L, 24, 2, 0, DEFAULT)
-MUX_CFG(GPIO5B3_HSADCDATA6_NAME, GPIO5L, 22, 2, 0, DEFAULT)
-MUX_CFG(GPIO5B2_HSADCDATA5_NAME, GPIO5L, 20, 2, 0, DEFAULT)
-MUX_CFG(GPIO5B1_HSADCDATA4_NAME, GPIO5L, 18, 2, 0, DEFAULT)
-MUX_CFG(GPIO5B0_HSADCDATA3_NAME, GPIO5L, 16, 2, 0, DEFAULT)
-MUX_CFG(GPIO5A7_HSADCDATA2_NAME, GPIO5L, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO5A6_HSADCDATA1_NAME, GPIO5L, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO5A5_HSADCDATA0_NAME, GPIO5L, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO5A4_TSSYNC_NAME, GPIO5L, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO5A3_MIITXCLKIN_NAME, GPIO5L, 6, 2, 0, DEFAULT)
-///GPIO5H
-MUX_CFG(GPIO5D6_SDMMC1PWREN_NAME, GPIO5H, 28, 2, 0, DEFAULT)
-MUX_CFG(GPIO5D5_SDMMC0PWREN_NAME, GPIO5H, 26, 2, 0, DEFAULT)
-MUX_CFG(GPIO5D4_I2C2SCL_NAME, GPIO5H, 24, 2, 0, DEFAULT)
-MUX_CFG(GPIO5D3_I2C2SDA_NAME, GPIO5H, 22, 2, 0, DEFAULT)
-MUX_CFG(GPIO5D2_PWM1_UART1SIRIN_NAME, GPIO5H, 20, 2, 0, DEFAULT)
-MUX_CFG(GPIO5D1_EBCSDCLK_SMCADDR6_HOSTDATA6_NAME, GPIO5H, 18, 2, 0, DEFAULT)
-MUX_CFG(GPIO5D0_EBCSDLE_SMCADDR5_HOSTDATA5_NAME, GPIO5H, 16, 2, 0, DEFAULT)
-MUX_CFG(GPIO5C7_EBCSDDO7_SMCDATA7_NAME, GPIO5H, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO5C6_EBCSDDO6_SMCDATA6_NAME, GPIO5H, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO5C5_EBCSDDO5_SMCDATA5_NAME, GPIO5H, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO5C4_EBCSDDO4_SMCDATA4_NAME, GPIO5H, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO5C3_EBCSDDO3_SMCDATA3_NAME, GPIO5H, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO5C2_EBCSDDO2_SMCDATA2_NAME, GPIO5H, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO5C1_EBCSDDO1_SMCDATA1_NAME, GPIO5H, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO5C0_EBCSDDO0_SMCDATA0_NAME, GPIO5H, 0, 2, 0, DEFAULT)
-};
-
-
-void rk29_mux_set(struct mux_config *cfg)
-{
- int regValue;
- int mask;
-
- mask = ((1<<(cfg->interleave))-1)<<cfg->offset;
- regValue = readl(cfg->mux_reg);
- regValue &=~mask;
- regValue |=(cfg->mode<<cfg->offset);
- #ifdef DEBUG_LHH
- printk("%s::regValue is %x,mask is %x\n",__FUNCTION__,regValue,mask);
- #endif
- writel(regValue,cfg->mux_reg);
-
- return;
-}
-
-int rk29_iomux_init(void)
-{
- int i;
- for(i=0;i<ARRAY_SIZE(rk29_muxs);i++)
- {
- if(rk29_muxs[i].flags != DEFAULT)
- rk29_mux_set(&rk29_muxs[i]);
- }
-
-#ifdef CONFIG_UART0_RK29
- rk29_mux_api_set(GPIO1B7_UART0SOUT_NAME, GPIO1L_UART0_SOUT);
- rk29_mux_api_set(GPIO1B6_UART0SIN_NAME, GPIO1L_UART0_SIN);
-#ifdef CONFIG_UART0_CTS_RTS_RK29
- rk29_mux_api_set(GPIO1C1_UART0RTSN_SDMMC1WRITEPRT_NAME, GPIO1H_UART0_RTS_N);
- rk29_mux_api_set(GPIO1C0_UART0CTSN_SDMMC1DETECTN_NAME, GPIO1H_UART0_CTS_N);
-#endif
-#endif
-#ifdef CONFIG_UART1_RK29
- rk29_mux_api_set(GPIO2A5_UART1SOUT_NAME, GPIO2L_UART1_SOUT);
- rk29_mux_api_set(GPIO2A4_UART1SIN_NAME, GPIO2L_UART1_SIN);
-#endif
-#ifdef CONFIG_UART2_RK29
- rk29_mux_api_set(GPIO2B1_UART2SOUT_NAME, GPIO2L_UART2_SOUT);
- rk29_mux_api_set(GPIO2B0_UART2SIN_NAME, GPIO2L_UART2_SIN);
-#ifdef CONFIG_UART2_CTS_RTS_RK29
- rk29_mux_api_set(GPIO2A7_UART2RTSN_NAME, GPIO2L_UART2_RTS_N);
- rk29_mux_api_set(GPIO2A6_UART2CTSN_NAME, GPIO2L_UART2_CTS_N);
-#endif
-#endif
-#ifdef CONFIG_UART3_RK29
- rk29_mux_api_set(GPIO2B3_UART3SOUT_NAME, GPIO2L_UART3_SOUT);
- rk29_mux_api_set(GPIO2B2_UART3SIN_NAME, GPIO2L_UART3_SIN);
-#ifdef CONFIG_UART3_CTS_RTS_RK29
- rk29_mux_api_set(GPIO2B5_UART3RTSN_I2C3SCL_NAME, GPIO2L_UART3_RTS_N);
- rk29_mux_api_set(GPIO2B4_UART3CTSN_I2C3SDA_NAME, GPIO2L_UART3_CTS_N);
-#endif
-#endif
-#ifdef CONFIG_SPIM0_RK29
- rk29_mux_api_set(GPIO2C0_SPI0CLK_NAME, GPIO2H_SPI0_CLK);
- rk29_mux_api_set(GPIO2C1_SPI0CSN0_NAME, GPIO2H_SPI0_CSN0);
- rk29_mux_api_set(GPIO2C2_SPI0TXD_NAME, GPIO2H_SPI0_TXD);
- rk29_mux_api_set(GPIO2C3_SPI0RXD_NAME, GPIO2H_SPI0_RXD);
-#endif
-#ifdef CONFIG_SPIM1_RK29
- rk29_mux_api_set(GPIO2C4_SPI1CLK_NAME, GPIO2H_SPI1_CLK);
- rk29_mux_api_set(GPIO2C5_SPI1CSN0_NAME, GPIO2H_SPI1_CSN0);
- rk29_mux_api_set(GPIO2C6_SPI1TXD_NAME, GPIO2H_SPI1_TXD);
- rk29_mux_api_set(GPIO2C7_SPI1RXD_NAME, GPIO2H_SPI1_RXD);
-#endif
-#ifdef CONFIG_RK29_VMAC
- rk29_mux_api_set(GPIO4C0_RMIICLKOUT_RMIICLKIN_NAME, GPIO4H_RMII_CLKOUT);
- rk29_mux_api_set(GPIO4C1_RMIITXEN_MIITXEN_NAME, GPIO4H_RMII_TX_EN);
- rk29_mux_api_set(GPIO4C2_RMIITXD1_MIITXD1_NAME, GPIO4H_RMII_TXD1);
- rk29_mux_api_set(GPIO4C3_RMIITXD0_MIITXD0_NAME, GPIO4H_RMII_TXD0);
- rk29_mux_api_set(GPIO4C4_RMIIRXERR_MIIRXERR_NAME, GPIO4H_RMII_RX_ERR);
- rk29_mux_api_set(GPIO4C5_RMIICSRDVALID_MIIRXDVALID_NAME, GPIO4H_RMII_CSR_DVALID);
- rk29_mux_api_set(GPIO4C6_RMIIRXD1_MIIRXD1_NAME, GPIO4H_RMII_RXD1);
- rk29_mux_api_set(GPIO4C7_RMIIRXD0_MIIRXD0_NAME, GPIO4H_RMII_RXD0);
-
- rk29_mux_api_set(GPIO0A7_MIIMDCLK_NAME, GPIO0L_MII_MDCLK);
- rk29_mux_api_set(GPIO0A6_MIIMD_NAME, GPIO0L_MII_MD);
-#endif
-
- return 0;
-}
-EXPORT_SYMBOL(rk29_iomux_init);
-/*
- *config iomux : input iomux name and iomux flags
- */
-void rk29_mux_api_set(char *name, unsigned int mode)
-{
- int i;
- if (!name) {
- return;
- }
- for(i=0;i<ARRAY_SIZE(rk29_muxs);i++)
- {
- if (!strcmp(rk29_muxs[i].name, name))
- {
- rk29_muxs[i].premode = rk29_muxs[i].mode;
- rk29_muxs[i].mode = mode;
- rk29_mux_set(&rk29_muxs[i]);
- break;
- }
- }
-}
-EXPORT_SYMBOL(rk29_mux_api_set);
-
-
+++ /dev/null
-#include <linux/module.h>\r
-#include <linux/dma-mapping.h>\r
-#include <linux/platform_device.h>\r
-#include <linux/irq.h>\r
-#include <linux/io.h>\r
-#include <linux/wait.h>\r
-#include <linux/sched.h>\r
-\r
-#include <mach/rk29_iomap.h>\r
-#include <mach/rk29-dma-pl330.h>\r
-#include <asm/uaccess.h>\r
-#include <asm/current.h>\r
-\r
-\r
-static DECLARE_WAIT_QUEUE_HEAD(wq);\r
-static int wq_condition = 0;\r
-//wait_queue_head_t dma_memcpy_wait;\r
-\r
-static struct rk29_dma_client rk29_dma_memcpy_client = {\r
- .name = "rk29-dma-memcpy",\r
-};\r
-\r
-\r
-struct Dma_MemToMem {\r
- int SrcAddr;\r
- int DstAddr;\r
- int MenSize;\r
-};\r
-\r
-\r
-static void rk29_dma_memcpy_callback(void *buf_id, int size, enum rk29_dma_buffresult result)\r
-{\r
- wq_condition = 1;\r
- wake_up_interruptible(&wq);\r
- //wake_up_interruptible(&dma_memcpy_wait);\r
-}\r
-\r
-//int slecount = 0;\r
-static ssize_t memcpy_dma_read(struct device *device,struct device_attribute *attr, char *argv)\r
-{\r
-\r
- return 0;\r
-}\r
-\r
-static ssize_t memcpy_dma_write(struct device *device, struct device_attribute *attr, const char *argv, size_t count)\r
-{\r
- int rt;\r
- struct Dma_MemToMem *DmaMemInfo = (struct Dma_MemToMem *)argv;\r
- \r
- rt = rk29_dma_devconfig(DMACH_DMAC0_MEMTOMEM, RK29_DMASRC_MEMTOMEM, DmaMemInfo->SrcAddr);\r
- rt = rk29_dma_enqueue(DMACH_DMAC0_MEMTOMEM, NULL, DmaMemInfo->DstAddr, DmaMemInfo->MenSize);\r
- rt = rk29_dma_ctrl(DMACH_DMAC0_MEMTOMEM, RK29_DMAOP_START); \r
- wait_event_interruptible_timeout(wq, wq_condition, 200);\r
- wq_condition = 0; \r
- //init_waitqueue_head(&dma_memcpy_wait);\r
- //interruptible_sleep_on(&dma_memcpy_wait);\r
- return 0;\r
-}\r
-\r
-static DEVICE_ATTR(dmamemcpy, S_IRUGO|S_IXUGO, memcpy_dma_read, memcpy_dma_write);\r
-\r
-\r
-static int __devinit dma_memcpy_probe(struct platform_device *pdev)\r
-{\r
- int ret;\r
- \r
- ret = device_create_file(&pdev->dev, &dev_attr_dmamemcpy);\r
- rk29_dma_request(DMACH_DMAC0_MEMTOMEM, &rk29_dma_memcpy_client, NULL); \r
- rk29_dma_config(DMACH_DMAC0_MEMTOMEM, 8, 16);\r
- rk29_dma_set_buffdone_fn(DMACH_DMAC0_MEMTOMEM, rk29_dma_memcpy_callback);\r
- if(ret)\r
- {\r
- printk(">> fb1 dsp win0 info device_create_file err\n");\r
- ret = -EINVAL;\r
- }\r
- // printk(">>>>>>>>>>>>>>>>>>>>> dam_test_probe ok>>>>>>>>>>>>>>>>>>>>>>>>"); \r
- return 0;\r
-}\r
-\r
-static int __devexit dma_memcpy_remove(struct platform_device *pdev)\r
-{\r
- device_remove_file(&pdev->dev, &dev_attr_dmamemcpy);\r
- \r
- return 0;\r
-}\r
-\r
-static struct platform_driver dma_mempcy_driver = {\r
- .driver = {\r
- .name = "dma_memcpy",\r
- .owner = THIS_MODULE, \r
- },\r
- .probe = dma_memcpy_probe,\r
- .remove = __devexit_p(dma_memcpy_remove),\r
-};\r
-\r
-\r
-static int __init dma_test_init(void)\r
-{\r
- return platform_driver_register(&dma_mempcy_driver);\r
-}\r
-\r
-static void __exit dma_test_exit(void)\r
-{\r
- platform_driver_unregister(&dma_mempcy_driver);\r
-}\r
-\r
-module_init(dma_test_init);\r
-module_exit(dma_test_exit);\r
-\r
-MODULE_DESCRIPTION("RK29 PL330 Dma Test Deiver");\r
-MODULE_LICENSE("GPL V2");\r
-MODULE_AUTHOR("ZhenFu Fang <fzf@rock-chips.com>");\r
-\r
-\r
-\r
-\r
+++ /dev/null
-/*
- * memtester version 4
- *
- * Very simple but very effective user-space memory tester.
- * Originally by Simon Kirby <sim@stormix.com> <sim@neato.org>
- * Version 2 by Charles Cazabon <charlesc-memtester@pyropus.ca>
- * Version 3 not publicly released.
- * Version 4 rewrite:
- * Copyright (C) 2007-2009 Charles Cazabon <charlesc-memtester@pyropus.ca>
- * Licensed under the terms of the GNU General Public License version 2 (only).
- * See the file COPYING for details.
- *
- */
-
-
-#include <linux/kernel.h>
-#include <linux/slab.h>
-
-#include "tests.h"
-
-
-#define EXIT_FAIL_NONSTARTER 0x01
-#define EXIT_FAIL_ADDRESSLINES 0x02
-#define EXIT_FAIL_OTHERTEST 0x04
-
-//#pragma arm section rwdata="DDR"
-useful_data_t useful_data={(2*1024*1024), 133, 333};
-//#pragma arm section
-
-struct test tests[17]
-= {
- #ifdef TEST_RANDOM
- { "Random Value", test_random_value },
- #endif
- #ifdef TEST_XOR
- { "Compare XOR", test_xor_comparison },
- #endif
- #ifdef TEST_SUB
- { "Compare SUB", test_sub_comparison },
- #endif
- #ifdef TEST_MUL
- { "Compare MUL", test_mul_comparison },
- #endif
- #ifdef TEST_DIV
- { "Compare DIV",test_div_comparison },
- #endif
- #ifdef TEST_OR
- { "Compare OR", test_or_comparison },
- #endif
- #ifdef TEST_AND
- { "Compare AND", test_and_comparison },
- #endif
- #ifdef TEST_SEQINC
- { "Sequential Increment", test_seqinc_comparison },
- #endif
- #ifdef TEST_SOLID_BIT
- { "Solid Bits", test_solidbits_comparison },
- #endif
- #ifdef TEST_BLOCK_SEQ
- { "Block Sequential", test_blockseq_comparison },
- #endif
- #ifdef TEST_CHECK_BOARD
- { "Checkerboard", test_checkerboard_comparison },
- #endif
- #ifdef TEST_BIT_SPREAD
- { "Bit Spread", test_bitspread_comparison },
- #endif
- #ifdef TEST_BIT_FLIP
- { "Bit Flip", test_bitflip_comparison },
- #endif
- #ifdef TEST_ONE
- { "Walking Ones", test_walkbits1_comparison },
- #endif
- #ifdef TEST_ZERO
- { "Walking Zeroes", test_walkbits0_comparison },
- #endif
- { NULL, NULL }
-};
-
-int exit_code = 0;
-
-int memtester(void) {
- ul loops, loop, i;
- size_t pagesize, wantraw, wantmb, wantbytes, wantbytes_orig, bufsize,
- halflen, count;
- ptrdiff_t pagesizemask;
- void volatile *buf, *aligned;
- ulv *bufa, *bufb;
- int memshift;
- ul cap;
-
-
-
- print("Copyright (C) 2009 Charles Cazabon.\n");
- print("Licensed under the GNU General Public License version 2 (only).\n");
- print("\n");
- pagesize = 1024;
- pagesizemask = (ptrdiff_t) ~(pagesize - 1);
- print("pagesizemask is 0x");
- print_Hex(pagesizemask);
- print("\n");
-
- if(useful_data.testCap == 0xFFFFFFFF)
- {
- cap = 0x800000 << (((pDDR_Reg->DCR >> 4) & 0x7)
- + ((((pDDR_Reg->DCR >> 7) & 0x7)+1) >> ((pDDR_Reg->DCR >> 2) & 0x3))
- + ((pDDR_Reg->DCR >> 11) & 0x3));
- }
- else if(useful_data.testCap == 0)
- {
- cap = (0x1 << 20);
- }
- else
- {
- cap = useful_data.testCap;
- }
-
- wantraw = cap>>20;
- memshift = 20; /* megabytes */
-
- wantbytes_orig = wantbytes = ((size_t) wantraw << memshift);
- wantmb = (wantbytes_orig >> 20);
-
- loops = 10;
-
- print("want ");
- print_Dec((ull) wantmb);
- print("MB (");
- print_Dec((ull) wantbytes);
- print(" bytes)\n");
- buf = NULL;
-
- buf = (void volatile *) kmalloc(wantbytes, GFP_KERNEL);
- // buf = (void volatile *)0x60000000;
- bufsize = wantbytes;
- aligned = buf;
-
- halflen = bufsize / 2;
- count = halflen / sizeof(ul);
- bufa = (ulv *) aligned;
- bufb = (ulv *) ((size_t) aligned + halflen);
-
- for(loop=1; ((!loops) || loop <= loops); loop++) {
- print("Loop ");
- print_Dec(loop);
- //if (loops) {
- // print_Dec(loops);
- //}
- print(":\n");
- print(" Stuck Address: ");
- if (!test_stuck_address(aligned, bufsize / sizeof(ul))) {
- print("ok\n");
- } else {
- exit_code |= EXIT_FAIL_ADDRESSLINES;
- goto error;
- }
- for (i=0;;i++) {
- if (!tests[i].name) break;
- print(" ");
- print(tests[i].name);
- print(": ");
- if (!tests[i].fp(bufa, bufb, count)) {
- print("ok\n");
- } else {
- exit_code |= EXIT_FAIL_OTHERTEST;
- goto error;
- }
- }
- print("\n");
- }
- kfree((const void *)buf);
- print("Done.\n");
- return 0;
-error:
- print("failed\n");
- return 1;
-}
+++ /dev/null
-#define DEBUG
-
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/pm.h>
-#include <linux/suspend.h>
-#include <linux/random.h>
-#include <linux/crc32.h>
-#include <linux/io.h>
-#include <linux/wakelock.h>
-#include <asm/tlbflush.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/rk29_iomap.h>
-#include <mach/cru.h>
-#include <mach/pmu.h>
-#include <mach/board.h>
-#include <mach/system.h>
-#include <mach/sram.h>
-#include <mach/gpio.h>
-#include <mach/ddr.h>
-#include <mach/memtester.h>
-#include <mach/iomux.h>
-#include <mach/pm-vol.h>
-
-#include <asm/vfp.h>
-
-#define grf_readl(offset) readl(RK29_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel(v, RK29_GRF_BASE + offset); readl(RK29_GRF_BASE + offset); } while (0)
-
-static unsigned long save_sp;
-
-static inline void delay_500ns(void)
-{
- LOOP(LOOPS_PER_USEC);
-}
-
-static inline void delay_300us(void)
-{
- LOOP(300 * LOOPS_PER_USEC);
-}
-
-#ifdef DEBUG
- void/* inline*/ __sramfunc sram_printch(char byte)
-{
- unsigned long flags;
- u32 gate1, gate2;
-
- local_irq_save(flags);
- gate1 = cru_readl(CRU_CLKGATE1_CON);
- gate2 = cru_readl(CRU_CLKGATE2_CON);
- cru_writel(gate1 & ~((1 << CLK_GATE_PCLK_PEIRPH % 32) | (1 << CLK_GATE_ACLK_PEIRPH % 32) | (1 << CLK_GATE_ACLK_CPU_PERI % 32)), CRU_CLKGATE1_CON);
- cru_writel(gate2 & ~(1 << CLK_GATE_UART1 % 32), CRU_CLKGATE2_CON);
- delay_500ns();
-
- writel(byte, RK29_UART1_BASE);
-
- /* loop check LSR[6], Transmitter Empty bit */
- while (!(readl(RK29_UART1_BASE + 0x14) & 0x40))
- barrier();
-
- cru_writel(gate2, CRU_CLKGATE2_CON);
- cru_writel(gate1, CRU_CLKGATE1_CON);
- local_irq_restore(flags);
- if (byte == '\n')
- sram_printch('\r');
-}
-
-void print(const char *s)
-{
- sram_printascii(s);
-}
-
-void __sramfunc print_Hex(unsigned int hex)
-{
- int i = 8;
- sram_printch('0');
- sram_printch('x');
- while (i--) {
- unsigned char c = (hex & 0xF0000000) >> 28;
- sram_printch(c < 0xa ? c + '0' : c - 0xa + 'a');
- hex <<= 4;
- }
-}
-
-void __sramfunc print_Dec (uint32_t n)
-{
- if (n >= 10)
- {
- print_Dec(n / 10);
- n %= 10;
- }
- sram_printch((char)(n + '0'));
-}
-
-void print_Dec_3(uint32_t value)
-{
- if(value<10)
- {
- print(" ");
- }
- else if(value<100)
- {
- print(" ");
- }
- else
- {
- }
- print_Dec(value);
-}
-
-#else
-static void inline sram_printch(char byte) {}
-static void inline sram_printascii(const char *s) {}
-static void inline printhex(unsigned int hex) {}
-#endif /* DEBUG */
-
-/*volatile __sramdata */int ddr_debug;
-module_param(ddr_debug, int, 0644);
-#if 1
-static int inline calc_crc32(u32 addr, size_t len)
-{
- return crc32_le(~0,(const unsigned char *)addr,len);
-}
-void __sramfunc ddr_testmode(void)
-{
- int32_t g_crc1,g_crc2;
- uint32_t nMHz;
- uint32_t n = 0;
- extern char _stext[], _etext[];
- if(ddr_debug == 1)
- {
- for (;;)
- {
- sram_printascii("change freq\n");
- g_crc1 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
- nMHz = 333 + random32();
- nMHz %= 490;
- if(nMHz < 100)
- nMHz = 100;
- nMHz = ddr_change_freq(nMHz);
- sram_printhex(nMHz);
- sram_printch(' ');
- sram_printhex(n++);
- sram_printch(' ');
- g_crc2 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
- if (g_crc1!=g_crc2)
- {
- sram_printascii("fail\n");
- }
- //ddr_print("check image crc32 success--crc value = 0x%x!, count:%d\n",g_crc1, n++);
- // sram_printascii("change freq success\n");
- }
- }
- else if(ddr_debug == 2)
- {
- for (;;)
- {
- sram_printch(' ');
- sram_printch('9');
- sram_printch('9');
- sram_printch('9');
- sram_printch(' ');
- g_crc1 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
- nMHz = (random32()>>13);// 16.7s max
- ddr_suspend();
- delayus(nMHz);
- ddr_resume();
- sram_printhex(nMHz);
- sram_printch(' ');
- sram_printhex(n++);
- g_crc2 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
- if (g_crc1!=g_crc2)
- {
- sram_printch(' ');
- sram_printch('f');
- sram_printch('a');
- sram_printch('i');
- sram_printch('l');
- }
- // ddr_print("check image crc32 fail!, count:%d\n", n++);
- // sram_printascii("self refresh fail\n");
- //else
- //ddr_print("check image crc32 success--crc value = 0x%x!, count:%d\n",g_crc1, n++);
- // sram_printascii("self refresh success\n");
- }
- }
- else if(ddr_debug == 3)
- {
- memtester();
- }
-}
-#else
-void __sramfunc ddr_testmode(void)
-{}
-
-#endif
-void __sramfunc pm_clk_switch_32k(void);
-
-void __sramfunc pm_wfi(void)
-{
- u32 clksel0;
- sram_printch('7');
- clksel0 = cru_readl(CRU_CLKSEL0_CON);
- /* set arm clk 24MHz/32 = 750KHz */
- cru_writel(clksel0 | 0x1F, CRU_CLKSEL0_CON);
-
- sram_printch('8');
- dsb();
- asm("wfi");
- sram_printch('8');
-
- /* resume arm clk */
- cru_writel(clksel0, CRU_CLKSEL0_CON);
- sram_printch('7');
-
-
-}
-
-static void __sramfunc rk29_sram_suspend(void)
-{
- u32 vol;
-
- if (ddr_debug == 2)
- ddr_testmode();
-
- sram_printch('5');
- ddr_suspend();
-
- sram_printch('6');
- vol=rk29_suspend_voltage_set(1000000);
-#ifdef CONFIG_RK29_CLK_SWITCH_TO_32K
- pm_clk_switch_32k();
-#else
- pm_wfi();
-#endif
- rk29_suspend_voltage_resume(vol);
- sram_printch('6');
-
- ddr_resume();
- sram_printch('5');
-}
-
-static void noinline rk29_suspend(void)
-{
- DDR_SAVE_SP(save_sp);
- rk29_sram_suspend();
- DDR_RESTORE_SP(save_sp);
-}
-
-static void dump_irq(void)
-{
- u32 irq_gpio = (readl(RK29_GICPERI_BASE + GIC_DIST_PENDING_SET + 8) >> 23) & 0x7F;
- printk("wakeup irq: %08x %08x %01x\n",
- readl(RK29_GICPERI_BASE + GIC_DIST_PENDING_SET + 4),
- readl(RK29_GICPERI_BASE + GIC_DIST_PENDING_SET + 8),
- readl(RK29_GICPERI_BASE + GIC_DIST_PENDING_SET + 12) & 0xf);
- if (irq_gpio & 1)
- printk("wakeup gpio0: %08x\n", readl(RK29_GPIO0_BASE + GPIO_INT_STATUS));
- if (irq_gpio & 2)
- printk("wakeup gpio1: %08x\n", readl(RK29_GPIO1_BASE + GPIO_INT_STATUS));
- if (irq_gpio & 4)
- printk("wakeup gpio2: %08x\n", readl(RK29_GPIO2_BASE + GPIO_INT_STATUS));
- if (irq_gpio & 8)
- printk("wakeup gpio3: %08x\n", readl(RK29_GPIO3_BASE + GPIO_INT_STATUS));
- if (irq_gpio & 0x10)
- printk("wakeup gpio4: %08x\n", readl(RK29_GPIO4_BASE + GPIO_INT_STATUS));
- if (irq_gpio & 0x20)
- printk("wakeup gpio5: %08x\n", readl(RK29_GPIO5_BASE + GPIO_INT_STATUS));
- if (irq_gpio & 0x40)
- printk("wakeup gpio6: %08x\n", readl(RK29_GPIO6_BASE + GPIO_INT_STATUS));
-}
-
-#define DUMP_GPIO_INTEN(ID) \
-do { \
- u32 en = readl(RK29_GPIO##ID##_BASE + GPIO_INTEN); \
- if (en) { \
- sram_printascii("GPIO" #ID "_INTEN: "); \
- sram_printhex(en); \
- sram_printch('\n'); \
- } \
-} while (0)
-
-static void dump_inten(void)
-{
- DUMP_GPIO_INTEN(0);
- DUMP_GPIO_INTEN(1);
- DUMP_GPIO_INTEN(2);
- DUMP_GPIO_INTEN(3);
- DUMP_GPIO_INTEN(4);
- DUMP_GPIO_INTEN(5);
- DUMP_GPIO_INTEN(6);
-}
-
-
-
-#define DUMP_GPIO_PULL(ID) \
-do { \
- u32 state = readl(RK29_GRF_BASE + GRF_GPIO0_PULL + (ID<<2)); \
- sram_printascii("GPIO" #ID "_PULL: "); \
- sram_printhex(state); \
- sram_printch('\n'); \
-} while (0)
-
-static void dump_io_pull(void)
-{
- DUMP_GPIO_PULL(0);
- DUMP_GPIO_PULL(1);
- DUMP_GPIO_PULL(2);
- DUMP_GPIO_PULL(3);
- DUMP_GPIO_PULL(4);
- DUMP_GPIO_PULL(5);
- DUMP_GPIO_PULL(6);
-}
-#ifdef CONFIG_RK29_NEON_POWERDOMAIN_SET
-/*******************************neon powermain***********************/
-#define pmu_read(offset) readl(RK29_PMU_BASE + (offset))
-#define pmu_write(offset, value) writel((value), RK29_PMU_BASE + (offset))
-#define PMU_PG_CON 0x10
-#define vfpreg(_vfp_) #_vfp_
-
-#define fmrx(_vfp_) ({ \
- u32 __v; \
- asm("mrc p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmrx %0, " #_vfp_ \
- : "=r" (__v) : : "cc"); \
- __v; \
- })
-
-#define fmxr(_vfp_,_var_) \
- asm("mcr p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmxr " #_vfp_ ", %0" \
- : : "r" (_var_) : "cc")
-extern void vfp_save_state(void *location, u32 fpexc);
-extern void vfp_load_state(void *location, u32 fpexc);
-// extern __sramdata u64 saveptr[33];
-static u32 saveptr[2][60]={};
-static void neon_powerdomain_off(void)
-{
- int ret,i=0;
- int *p;
- u32 fpexc;
- p=&saveptr[0][0];
-
-
- fpexc= fmrx(FPEXC); //get neon Logic gate
-
- fmxr(FPEXC, fpexc | FPEXC_EN); //open neon Logic gate
- for(i=0;i<36;i++){
- vfp_save_state(p,fpexc); //save neon reg,32 D reg,2 control reg
- p++;
- }
- fmxr(FPEXC, fpexc & ~FPEXC_EN); //close neon Logic gate
-
- ret=pmu_read(PMU_PG_CON); //get power domain state
- pmu_write(PMU_PG_CON,ret|(0x1<<1)); //powerdomain off neon
- printk("neon powerdomain is off\n");
-}
-static void neon_powerdomain_on(void)
-{
- int ret,i=0;
- int *p;
- unsigned int fpexc ;
- p=&saveptr[0][0];
-
- ret=pmu_read(PMU_PG_CON); //get power domain state
- pmu_write(PMU_PG_CON,ret&~(0x1<<1)); //powerdomain on neon
- mdelay(4);
-
- fpexc = fmrx(FPEXC); //get neon Logic gate
- fmxr(FPEXC, fpexc | FPEXC_EN); //open neon Logic gate
- for(i=0;i<36;i++){
- vfp_load_state(p,fpexc); //recovery neon reg, 32 D reg,2 control reg
- p++;
- }
- fmxr(FPEXC, fpexc | FPEXC_EN); //open neon Logic gate
- printk("neon powerdomain is on\n");
-}
-#endif
-/*******************************neon powermain***********************/
-
-void pm_gpio_suspend(void);
-void pm_gpio_resume(void);
-
-static int rk29_pm_enter(suspend_state_t state)
-{
- u32 apll, cpll, gpll, mode, clksel0;
- u32 clkgate[4];
-
- #ifdef CONFIG_RK29_NEON_POWERDOMAIN_SET
- neon_powerdomain_off();
- #endif
-
- // memory teseter
- if (ddr_debug != 2)
- ddr_testmode();
-
- // dump GPIO INTEN for debug
- dump_inten();
- // dump GPIO PULL state for debug
- //if you want to display the information, please enable the code.
-#if 0
- dump_io_pull();
-#endif
-
- sram_printch('0');
- flush_tlb_all();
- #if defined(CONFIG_RK29_SPI_INSRAM) || defined(CONFIG_RK29_PWM_INSRAM)
- interface_ctr_reg_pread();
- #endif
- #if defined(CONFIG_RK29_I2C_INSRAM)
- i2c_interface_ctr_reg_pread();
- #endif
-
- /* disable clock */
- clkgate[0] = cru_readl(CRU_CLKGATE0_CON);
- clkgate[1] = cru_readl(CRU_CLKGATE1_CON);
- clkgate[2] = cru_readl(CRU_CLKGATE2_CON);
- clkgate[3] = cru_clkgate3_con_mirror;
- cru_writel(~((1 << CLK_GATE_CORE)
- | (1 << CLK_GATE_ACLK_CPU)
- | (1 << CLK_GATE_ACLK_CPU2)
- | (1 << CLK_GATE_PCLK_CPU)
- | (1 << CLK_GATE_GIC)
- | (1 << CLK_GATE_INTMEM)
- | (1 << CLK_GATE_DDR_PHY)
- | (1 << CLK_GATE_DDR_REG)
- | (1 << CLK_GATE_DDR_CPU)
- | (1 << CLK_GATE_GPIO0)
- | (1 << CLK_GATE_RTC)
- | (1 << CLK_GATE_GRF)
-#ifdef CONFIG_RK29_JTAG
- | (1 << CLK_GATE_PCLK_CORE)
- | (1 << CLK_GATE_ATCLK_CORE)
- | (1 << CLK_GATE_ATCLK_CPU)
- | (1 << CLK_GATE_DEBUG)
- | (1 << CLK_GATE_TPIU)
-#endif
- ) | clkgate[0], CRU_CLKGATE0_CON);
-
-#ifdef CONFIG_PHONE_INCALL_IS_SUSPEND
-#if defined(CONFIG_SND_RK29_SOC_I2S_8CH)
- cru_writel(clkgate[0]&(~(1<<CLK_GATE_I2S0)),CRU_CLKGATE0_CON);
-#elif defined(CONFIG_SND_RK29_SOC_I2S_2CH)
- cru_writel(clkgate[0]&(~(1<<CLK_GATE_I2S1)),CRU_CLKGATE0_CON);
-#endif
-#endif
-
- cru_writel(~0, CRU_CLKGATE1_CON);
- cru_writel(~((1 << CLK_GATE_GPIO1 % 32)
- | (1 << CLK_GATE_GPIO2 % 32)
- | (1 << CLK_GATE_GPIO3 % 32)
- | (1 << CLK_GATE_GPIO4 % 32)
- | (1 << CLK_GATE_GPIO5 % 32)
- | (1 << CLK_GATE_GPIO6 % 32)
- | (1 << CLK_GATE_PWM % 32)
-#ifdef CONFIG_RK29_JTAG
- | (1 << CLK_GATE_JTAG % 32)
-#endif
- ) | clkgate[2], CRU_CLKGATE2_CON);
- cru_writel(~0, CRU_CLKGATE3_CON);
- sram_printch('1');
-
- mode = cru_readl(CRU_MODE_CON);
- clksel0 = cru_readl(CRU_CLKSEL0_CON);
-
- /* suspend arm pll */
- apll = cru_readl(CRU_APLL_CON);
- cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_SLOW, CRU_MODE_CON);
- cru_writel(apll | PLL_BYPASS, CRU_APLL_CON);
- cru_writel(apll | PLL_PD | PLL_BYPASS, CRU_APLL_CON);
- delay_500ns();
- /* set core = aclk_cpu = hclk_cpu = pclk_cpu = 24MHz */
- cru_writel(clksel0 & 0xFFFFF000, CRU_CLKSEL0_CON);
- sram_printch('2');
-
- /* suspend codec pll */
- cpll = cru_readl(CRU_CPLL_CON);
- cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | CRU_CODEC_MODE_SLOW, CRU_MODE_CON);
- cru_writel(cpll | PLL_BYPASS, CRU_CPLL_CON);
- cru_writel(cpll | PLL_PD | PLL_BYPASS, CRU_CPLL_CON);
- delay_500ns();
- sram_printch('3');
-
- /* suspend general pll */
- gpll = cru_readl(CRU_GPLL_CON);
- cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_GENERAL_MODE_MASK) | CRU_GENERAL_MODE_SLOW, CRU_MODE_CON);
- cru_writel(gpll | PLL_BYPASS, CRU_GPLL_CON);
- cru_writel(gpll | PLL_PD | PLL_BYPASS, CRU_GPLL_CON);
- delay_500ns();
- /* set aclk_periph = hclk_periph = pclk_periph = 24MHz */
- cru_writel(clksel0 & ~0x7FC000, CRU_CLKSEL0_CON);
-
- sram_printch('4');
- pm_gpio_suspend();
- rk29_suspend();
- pm_gpio_resume();
- sram_printch('4');
-
- /* resume general pll */
- cru_writel(gpll, CRU_GPLL_CON);
- delay_300us();
- /* restore aclk_periph/hclk_periph/pclk_periph */
- cru_writel(cru_readl(CRU_CLKSEL0_CON) | (clksel0 & 0x7FC000), CRU_CLKSEL0_CON);
- cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_GENERAL_MODE_MASK) | (mode & CRU_GENERAL_MODE_MASK), CRU_MODE_CON);
- sram_printch('3');
-
- /* resume codec pll */
- cru_writel(cpll, CRU_CPLL_CON);
- delay_300us();
- cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | (mode & CRU_CODEC_MODE_MASK), CRU_MODE_CON);
- sram_printch('2');
-
- /* resume arm pll */
- cru_writel(apll, CRU_APLL_CON);
- delay_300us();
- /* restore core/aclk_cpu/hclk_cpu/pclk_cpu */
- cru_writel(cru_readl(CRU_CLKSEL0_CON) | (clksel0 & 0xFFF), CRU_CLKSEL0_CON);
- cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | (mode & CRU_CPU_MODE_MASK), CRU_MODE_CON);
- sram_printch('1');
-
- /* enable clock */
- cru_writel(clkgate[0], CRU_CLKGATE0_CON);
- cru_writel(clkgate[1], CRU_CLKGATE1_CON);
- cru_writel(clkgate[2], CRU_CLKGATE2_CON);
- cru_writel(clkgate[3], CRU_CLKGATE3_CON);
- sram_printascii("0\n");
-
- dump_irq();
-
- #ifdef CONFIG_RK29_NEON_POWERDOMAIN_SET
- neon_powerdomain_on();
- #endif
-
- return 0;
-}
-
-static int rk29_pm_prepare(void)
-{
- /* disable entering rk29_idle() by disable_hlt() */
- disable_hlt();
- return 0;
-}
-
-static void rk29_pm_finish(void)
-{
- enable_hlt();
-}
-
-static struct platform_suspend_ops rk29_pm_ops = {
- .enter = rk29_pm_enter,
- .valid = suspend_valid_only_mem,
- .prepare = rk29_pm_prepare,
- .finish = rk29_pm_finish,
-};
-
-static void rk29_idle(void)
-{
- if (!need_resched()) {
- int allow_sleep = 1;
-#ifdef CONFIG_HAS_WAKELOCK
- allow_sleep = !has_wake_lock(WAKE_LOCK_IDLE);
-#endif
- if (allow_sleep) {
- u32 mode_con = cru_readl(CRU_MODE_CON);
- cru_writel((mode_con & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_SLOW, CRU_MODE_CON);
- arch_idle();
- cru_writel(mode_con, CRU_MODE_CON);
- } else {
- arch_idle();
- }
- }
- local_irq_enable();
-}
-
-static int __init rk29_pm_init(void)
-{
- suspend_set_ops(&rk29_pm_ops);
-
- /* set idle function */
- pm_idle = rk29_idle;
- ddr_debug = 0;
-
-#ifdef CONFIG_EARLYSUSPEND
- pm_set_vt_switch(0); /* disable vt switch while suspend */
-#endif
-
- return 0;
-}
-__initcall(rk29_pm_init);
+++ /dev/null
-
-#include <mach/rk29_iomap.h>
-#include <mach/board.h>
-#include <mach/sram.h>
-#include <asm/io.h>
-#include <mach/cru.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-
-#define pwm_write_reg(addr, val) __raw_writel(val, addr + (RK29_PWM_BASE + 2*0x10))
-#define pwm_read_reg(addr) __raw_readl(addr + (RK29_PWM_BASE + 2*0x10))
-#define cru_readl(offset) readl(RK29_CRU_BASE + offset)
-#define cru_writel(v, offset) do { writel(v, RK29_CRU_BASE + offset); dsb(); } while (0)
-
-void interface_ctr_reg_pread(void)
-{
- readl(RK29_PWM_BASE);
- readl(RK29_GRF_BASE);
-}
-static unsigned int __sramdata pwm_lrc,pwm_hrc;
-
-static void __sramfunc rk29_pwm_set_core_voltage(unsigned int uV)
-{
- u32 gate1;
-
- gate1 = cru_readl(CRU_CLKGATE1_CON);
- cru_writel(gate1 & ~((1 << CLK_GATE_PCLK_PEIRPH % 32) | (1 << CLK_GATE_ACLK_PEIRPH % 32) | (1 << CLK_GATE_ACLK_CPU_PERI % 32)), CRU_CLKGATE1_CON);
-
- /* iomux pwm2 */
- writel((readl(RK29_GRF_BASE + 0x58) & ~(0x3<<6)) | (0x2<<6), RK29_GRF_BASE + 0x58);
-
- if (uV) {
- pwm_lrc = pwm_read_reg(PWM_REG_LRC);
- pwm_hrc = pwm_read_reg(PWM_REG_HRC);
- }
-
- pwm_write_reg(PWM_REG_CTRL, PWM_DIV|PWM_RESET);
- if (uV == 1000000) {
- pwm_write_reg(PWM_REG_LRC, 12);
- pwm_write_reg(PWM_REG_HRC, 10);
- } else {
- pwm_write_reg(PWM_REG_LRC, pwm_lrc);
- pwm_write_reg(PWM_REG_HRC, pwm_hrc);
- }
- pwm_write_reg(PWM_REG_CNTR, 0);
- pwm_write_reg(PWM_REG_CTRL, PWM_DIV|PWM_ENABLE|PWM_TimeEN);
-
- LOOP(10 * 1000 * LOOPS_PER_USEC); /* delay 10ms */
-
- cru_writel(gate1, CRU_CLKGATE1_CON);
-}
-
-unsigned int __sramfunc rk29_suspend_voltage_set(unsigned int vol)
-{
-
- rk29_pwm_set_core_voltage(1000000);
- return 0;
-
-}
-void __sramfunc rk29_suspend_voltage_resume(unsigned int vol)
-{
- rk29_pwm_set_core_voltage(0);
-}
-
+++ /dev/null
-#include <linux/kernel.h>\r
-#include <linux/reboot.h>\r
-\r
-#include <asm/io.h>\r
-#include <asm/proc-fns.h>\r
-#include <asm/cacheflush.h>\r
-#include <asm/tlb.h>\r
-#include <asm/traps.h>\r
-#include <asm/sections.h>\r
-#include <asm/mach/arch.h>\r
-#include <asm/mach/map.h>\r
-#include <asm/stacktrace.h>\r
-\r
-#include <mach/rk29_iomap.h>\r
-#include <mach/cru.h>\r
-#include <mach/memory.h>\r
-#include <mach/sram.h>\r
-#include <mach/pmu.h>\r
-#include <mach/loader.h>\r
-#include <mach/board.h>\r
-\r
-#include <asm/delay.h>\r
-#include <asm/tlbflush.h>\r
-#include <asm/cacheflush.h>\r
-\r
-static void pwm2gpiodefault(void)\r
-{\r
- #define REG_FILE_BASE_ADDR RK29_GRF_BASE\r
- volatile unsigned int * pGRF_GPIO2L_IOMUX = (volatile unsigned int *)(REG_FILE_BASE_ADDR + 0x58);\r
- #define GPIO2_BASE_ADDR RK29_GPIO2_BASE\r
- volatile unsigned int *pGPIO2_DIR = (volatile unsigned int *)(GPIO2_BASE_ADDR + 0x4);\r
-\r
- // iomux pwm2 to gpio2_a[3]\r
- *pGRF_GPIO2L_IOMUX &= ~(0x3<<6);\r
- // set gpio to input\r
- *pGPIO2_DIR &= ~(0x1<<3);\r
-\r
- memset((void *)RK29_PWM_BASE, 0, 0x40);\r
-} \r
-\r
-#if 0\r
-extern void __rb( void* );\r
-static void rb( void )\r
-{\r
- void(*cb)(void* ) ;\r
- \r
- void * uart_base = (unsigned int *)ioremap( RK29_UART1_PHYS , RK29_UART1_SIZE );\r
- local_irq_disable();\r
- cb = (void(*)(void* ))__pa(__rb);\r
- __cpuc_flush_kern_all();\r
- __cpuc_flush_user_all();\r
- //printk("begin to jump to reboot,uart1 va=0x%p\n" , uart_base);\r
- //while(testflag); \r
- cb( uart_base );\r
-}\r
-#endif\r
-\r
-static volatile u32 __sramdata reboot_reason = 0;\r
-static void __sramfunc __noreturn rk29_rb_with_softreset(void)\r
-{\r
- u32 reg;\r
- u32 reason = __raw_readl((u32)&reboot_reason - SRAM_CODE_OFFSET + 0x10130000);\r
-\r
- asm volatile (\r
- "mrc p15, 0, %0, c1, c0, 0\n\t"\r
- "bic %0, %0, #(1 << 0) @disable MMU\n\t"\r
- "bic %0, %0, #(1 << 13) @set vector to 0x00000000\n\t"\r
- "bic %0, %0, #(1 << 12) @disable I CACHE\n\t"\r
- "bic %0, %0, #(1 << 2) @disable D DACHE\n\t"\r
- "bic %0, %0, #(1 << 11) @disable Branch prediction\n\t"\r
- "bic %0, %0, #(1 << 28) @disable TEX Remap\n\t"\r
- "mcr p15, 0, %0, c1, c0, 0\n\t"\r
- "mov %0, #0\n\t"\r
- "mcr p15, 0, %0, c8, c7, 0 @invalidate whole TLB\n\t"\r
- "mcr p15, 0, %0, c7, c5, 6 @invalidate BTC\n\t"\r
- "dsb\n\t"\r
- "isb\n\t"\r
- "b 1f\n\t"\r
- ".align 5\n\t"\r
- "1:\n\t"\r
- : "=r" (reg));\r
-\r
- writel(0x00019a00, RK29_CRU_PHYS + CRU_SOFTRST2_CON);\r
- dsb();\r
- LOOP(10 * LOOPS_PER_USEC);\r
-\r
- writel(0xffffffff, RK29_CRU_PHYS + CRU_SOFTRST2_CON);\r
- writel(0xffffffff, RK29_CRU_PHYS + CRU_SOFTRST1_CON);\r
- writel(0xd9fdfdc0, RK29_CRU_PHYS + CRU_SOFTRST0_CON);\r
- dsb();\r
-\r
- LOOP(100 * LOOPS_PER_USEC);\r
-\r
- writel(0, RK29_CRU_PHYS + CRU_SOFTRST0_CON);\r
- writel(0, RK29_CRU_PHYS + CRU_SOFTRST1_CON);\r
- writel(0x00019a00, RK29_CRU_PHYS + CRU_SOFTRST2_CON);\r
- dsb();\r
- LOOP(10 * LOOPS_PER_USEC);\r
- writel(0, RK29_CRU_PHYS + CRU_SOFTRST2_CON);\r
- dsb();\r
- LOOP(10 * LOOPS_PER_USEC);\r
-\r
- /* reset GRF_MEM_CON, else bootloader usb function may not work properly */\r
- writel(0, RK29_GRF_PHYS + 0xac);\r
- dsb();\r
-\r
- if (reason) {\r
- __raw_writel(0, RK29_TIMER0_PHYS + 0x8);\r
- __raw_writel(reason, RK29_TIMER0_PHYS + 0x0);\r
- }\r
-\r
- asm volatile (\r
- "b 1f\n\t"\r
- ".align 5\n\t"\r
- "1:\n\t"\r
- "dsb\n\t"\r
- "isb\n\t"\r
- "mov pc, #0");\r
-\r
- while (1);\r
-}\r
-\r
-void rk29_arch_reset(int mode, const char *cmd)\r
-{\r
- void (*rb2)(void);\r
- u32 boot_mode = BOOT_MODE_REBOOT;\r
-\r
- if (cmd) {\r
- if (!strcmp(cmd, "loader") || !strcmp(cmd, "bootloader")) {\r
- reboot_reason = SYS_LOADER_ERR_FLAG;\r
- } else if (!strcmp(cmd, "recovery")) {\r
- reboot_reason = SYS_LOADER_REBOOT_FLAG + BOOT_RECOVER;\r
- boot_mode = BOOT_MODE_RECOVERY;\r
- } else if (!strcmp(cmd, "charge")) {\r
- boot_mode = BOOT_MODE_CHARGE;\r
- }\r
- } else {\r
- if (system_state != SYSTEM_RESTART)\r
- boot_mode = BOOT_MODE_PANIC;\r
- }\r
- writel(boot_mode, RK29_GRF_BASE + 0xdc); // GRF_OS_REG3\r
-\r
- rb2 = (void(*)(void))((u32)rk29_rb_with_softreset - SRAM_CODE_OFFSET + 0x10130000);\r
-\r
- local_irq_disable();\r
- local_fiq_disable();\r
-\r
-#ifdef CONFIG_MACH_RK29SDK\r
- /* from panic? loop for debug */\r
- if (system_state != SYSTEM_RESTART) {\r
- printk("\nLoop for debug...\n");\r
- while (1);\r
- }\r
-#endif\r
-\r
- cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_SLOW, CRU_MODE_CON);\r
- LOOP(LOOPS_PER_USEC);\r
-\r
- pwm2gpiodefault();\r
-\r
- cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_GENERAL_MODE_MASK) | CRU_GENERAL_MODE_SLOW, CRU_MODE_CON);\r
- LOOP(LOOPS_PER_USEC);\r
-\r
- cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | CRU_CODEC_MODE_SLOW, CRU_MODE_CON);\r
- LOOP(LOOPS_PER_USEC);\r
-\r
- cru_writel(0, CRU_CLKGATE0_CON);\r
- cru_writel(0, CRU_CLKGATE1_CON);\r
- cru_writel(0, CRU_CLKGATE2_CON);\r
- cru_writel(0, CRU_CLKGATE3_CON);\r
- LOOP(LOOPS_PER_USEC);\r
-\r
- cru_writel(0, CRU_SOFTRST0_CON);\r
- cru_writel(0, CRU_SOFTRST1_CON);\r
- cru_writel(0, CRU_SOFTRST2_CON);\r
- LOOP(LOOPS_PER_USEC);\r
-\r
- cru_writel(1 << 16 | 1 << 13 | 1 << 11 | 1 << 1, CRU_CLKGATE3_CON);\r
- LOOP(LOOPS_PER_USEC);\r
-\r
- writel(readl(RK29_PMU_BASE + PMU_PD_CON) & ~(1 << PD_VCODEC), RK29_PMU_BASE + PMU_PD_CON);\r
- dsb();\r
- while (readl(RK29_PMU_BASE + PMU_PD_ST) & (1 << PD_VCODEC))\r
- ;\r
- LOOP(10 * LOOPS_PER_MSEC);\r
-\r
- writel(readl(RK29_PMU_BASE + PMU_PD_CON) & ~(1 << PD_DISPLAY), RK29_PMU_BASE + PMU_PD_CON);\r
- dsb();\r
- while (readl(RK29_PMU_BASE + PMU_PD_ST) & (1 << PD_DISPLAY))\r
- ;\r
- LOOP(10 * LOOPS_PER_MSEC);\r
-\r
- writel(readl(RK29_PMU_BASE + PMU_PD_CON) & ~(1 << PD_GPU), RK29_PMU_BASE + PMU_PD_CON);\r
- dsb();\r
- while (readl(RK29_PMU_BASE + PMU_PD_ST) & (1 << PD_GPU))\r
- ;\r
- LOOP(10 * LOOPS_PER_MSEC);\r
-\r
- cru_writel(0, CRU_CLKGATE3_CON);\r
- LOOP(LOOPS_PER_USEC);\r
-\r
- //SPI0 clock source = periph_pll_clk, SPI0 divider=8\r
- cru_writel((cru_readl(CRU_CLKSEL6_CON) & ~0x1FF) | (7 << 2), CRU_CLKSEL6_CON);\r
-\r
- //eMMC divider=0x17, SD/MMC0 clock source=arm_pll_clk\r
- cru_writel((cru_readl(CRU_CLKSEL7_CON) & ~(3 | (0x3f << 18))) | (0x17 << 18), CRU_CLKSEL7_CON);\r
-\r
- //UART1 clock divider=0, UART1 clk =24MHz , UART0 and UART1 clock source=periph_pll_clk\r
- cru_writel((cru_readl(CRU_CLKSEL8_CON) & ~(7 | (0x3f << 14) | (3 << 20))) | (2 << 20), CRU_CLKSEL8_CON);\r
-\r
- // remap bit control = 0, normal mode\r
- writel(readl(RK29_GRF_BASE + 0xc0) & ~(1 << 21), RK29_GRF_BASE + 0xc0);\r
- // emmc_and_boot_en control=0, normal mode\r
- writel(readl(RK29_GRF_BASE + 0xbc) & ~(1 << 9), RK29_GRF_BASE + 0xbc);\r
- dsb();\r
-\r
- writel(0, RK29_CPU_AXI_BUS0_PHYS);\r
- writel(0, RK29_AXI1_PHYS);\r
- dsb();\r
-\r
- // SDMMC_CLKSRC=0, clk_source=clock divider 0\r
- writel(0, RK29_EMMC_PHYS + 0x0c);\r
- // SDMMC_CTYPE=0, card_width=1 bit mode\r
- writel(0, RK29_EMMC_PHYS + 0x18);\r
- // SDMMC_BLKSIZ=0x200, Block size=512\r
- writel(0x200, RK29_EMMC_PHYS + 0x1c);\r
- dsb();\r
-\r
- __cpuc_flush_kern_all();\r
- __cpuc_flush_user_all();\r
- \r
- rb2();\r
-}\r
-\r
-\r
+++ /dev/null
-/* linux/arch/arm/plat-samsung/rk29-pl330.c
- *
- * Copyright (C) 2010 Samsung Electronics Co. Ltd.
- * Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/platform_device.h>
-
-#include <asm/hardware/pl330.h>
-
-#include <mach/rk29-dma-pl330.h>
-
-/**
- * struct rk29_pl330_dmac - Logical representation of a PL330 DMAC.
- * @busy_chan: Number of channels currently busy.
- * @peri: List of IDs of peripherals this DMAC can work with.
- * @node: To attach to the global list of DMACs.
- * @pi: PL330 configuration info for the DMAC.
- * @kmcache: Pool to quickly allocate xfers for all channels in the dmac.
- */
-struct rk29_pl330_dmac {
- unsigned busy_chan;
- enum dma_ch *peri;
- struct list_head node;
- struct pl330_info *pi;
- struct kmem_cache *kmcache;
-};
-
-/**
- * struct rk29_pl330_xfer - A request submitted by rk29 DMA clients.
- * @token: Xfer ID provided by the client.
- * @node: To attach to the list of xfers on a channel.
- * @px: Xfer for PL330 core.
- * @chan: Owner channel of this xfer.
- */
-struct rk29_pl330_xfer {
- void *token;
- struct list_head node;
- struct pl330_xfer px;
- struct rk29_pl330_chan *chan;
-};
-
-/**
- * struct rk29_pl330_chan - Logical channel to communicate with
- * a Physical peripheral.
- * @pl330_chan_id: Token of a hardware channel thread of PL330 DMAC.
- * NULL if the channel is available to be acquired.
- * @id: ID of the peripheral that this channel can communicate with.
- * @options: Options specified by the client.
- * @sdaddr: Address provided via rk29_dma_devconfig.
- * @node: To attach to the global list of channels.
- * @lrq: Pointer to the last submitted pl330_req to PL330 core.
- * @xfer_list: To manage list of xfers enqueued.
- * @req: Two requests to communicate with the PL330 engine.
- * @callback_fn: Callback function to the client.
- * @rqcfg: Channel configuration for the xfers.
- * @xfer_head: Pointer to the xfer to be next excecuted.
- * @dmac: Pointer to the DMAC that manages this channel, NULL if the
- * channel is available to be acquired.
- * @client: Client of this channel. NULL if the
- * channel is available to be acquired.
- */
-struct rk29_pl330_chan {
- void *pl330_chan_id;
- enum dma_ch id;
- unsigned int options;
- unsigned long sdaddr;
- struct list_head node;
- struct pl330_req *lrq;
- struct list_head xfer_list;
- struct pl330_req req[2];
- rk29_dma_cbfn_t callback_fn;
- struct pl330_reqcfg rqcfg;
- struct rk29_pl330_xfer *xfer_head;
- struct rk29_pl330_dmac *dmac;
- struct rk29_dma_client *client;
-};
-
-/* All DMACs in the platform */
-static LIST_HEAD(dmac_list);
-
-/* All channels to peripherals in the platform */
-static LIST_HEAD(chan_list);
-
-/*
- * Since we add resources(DMACs and Channels) to the global pool,
- * we need to guard access to the resources using a global lock
- */
-static DEFINE_SPINLOCK(res_lock);
-
-/* Returns the channel with ID 'id' in the chan_list */
-static struct rk29_pl330_chan *id_to_chan(const enum dma_ch id)
-{
- struct rk29_pl330_chan *ch;
-
- list_for_each_entry(ch, &chan_list, node)
- if (ch->id == id)
- return ch;
-
- return NULL;
-}
-
-/* Allocate a new channel with ID 'id' and add to chan_list */
-static void chan_add(const enum dma_ch id)
-{
- struct rk29_pl330_chan *ch = id_to_chan(id);
-
- /* Return if the channel already exists */
- if (ch)
- return;
-
- ch = kmalloc(sizeof(*ch), GFP_KERNEL);
- /* Return silently to work with other channels */
- if (!ch)
- return;
-
- ch->id = id;
- ch->dmac = NULL;
-
- list_add_tail(&ch->node, &chan_list);
-}
-
-/* If the channel is not yet acquired by any client */
-static bool chan_free(struct rk29_pl330_chan *ch)
-{
- if (!ch)
- return false;
-
- /* Channel points to some DMAC only when it's acquired */
- return ch->dmac ? false : true;
-}
-
-/*
- * Returns 0 is peripheral i/f is invalid or not present on the dmac.
- * Index + 1, otherwise.
- */
-static unsigned iface_of_dmac(struct rk29_pl330_dmac *dmac, enum dma_ch ch_id)
-{
- enum dma_ch *id = dmac->peri;
- int i;
-
- /* Discount invalid markers */
- if (ch_id == DMACH_MAX)
- return 0;
-
- for (i = 0; i < PL330_MAX_PERI; i++)
- if (id[i] == ch_id)
- return i + 1;
-
- return 0;
-}
-
-/* If all channel threads of the DMAC are busy */
-static inline bool dmac_busy(struct rk29_pl330_dmac *dmac)
-{
- struct pl330_info *pi = dmac->pi;
-
- return (dmac->busy_chan < pi->pcfg.num_chan) ? false : true;
-}
-
-/*
- * Returns the number of free channels that
- * can be handled by this dmac only.
- */
-static unsigned ch_onlyby_dmac(struct rk29_pl330_dmac *dmac)
-{
- enum dma_ch *id = dmac->peri;
- struct rk29_pl330_dmac *d;
- struct rk29_pl330_chan *ch;
- unsigned found, count = 0;
- enum dma_ch p;
- int i;
-
- for (i = 0; i < PL330_MAX_PERI; i++) {
- p = id[i];
- ch = id_to_chan(p);
-
- if (p == DMACH_MAX || !chan_free(ch))
- continue;
-
- found = 0;
- list_for_each_entry(d, &dmac_list, node) {
- if (d != dmac && iface_of_dmac(d, ch->id)) {
- found = 1;
- break;
- }
- }
- if (!found)
- count++;
- }
-
- return count;
-}
-
-/*
- * Measure of suitability of 'dmac' handling 'ch'
- *
- * 0 indicates 'dmac' can not handle 'ch' either
- * because it is not supported by the hardware or
- * because all dmac channels are currently busy.
- *
- * >0 vlaue indicates 'dmac' has the capability.
- * The bigger the value the more suitable the dmac.
- */
-#define MAX_SUIT UINT_MAX
-#define MIN_SUIT 0
-
-static unsigned suitablility(struct rk29_pl330_dmac *dmac,
- struct rk29_pl330_chan *ch)
-{
- struct pl330_info *pi = dmac->pi;
- enum dma_ch *id = dmac->peri;
- struct rk29_pl330_dmac *d;
- unsigned s;
- int i;
-
- s = MIN_SUIT;
- /* If all the DMAC channel threads are busy */
- if (dmac_busy(dmac))
- return s;
-
- for (i = 0; i < PL330_MAX_PERI; i++)
- if (id[i] == ch->id)
- break;
-
- /* If the 'dmac' can't talk to 'ch' */
- if (i == PL330_MAX_PERI)
- return s;
-
- s = MAX_SUIT;
- list_for_each_entry(d, &dmac_list, node) {
- /*
- * If some other dmac can talk to this
- * peri and has some channel free.
- */
- if (d != dmac && iface_of_dmac(d, ch->id) && !dmac_busy(d)) {
- s = 0;
- break;
- }
- }
- if (s)
- return s;
-
- s = 100;
-
- /* Good if free chans are more, bad otherwise */
- s += (pi->pcfg.num_chan - dmac->busy_chan) - ch_onlyby_dmac(dmac);
-
- return s;
-}
-
-/* More than one DMAC may have capability to transfer data with the
- * peripheral. This function assigns most suitable DMAC to manage the
- * channel and hence communicate with the peripheral.
- */
-static struct rk29_pl330_dmac *map_chan_to_dmac(struct rk29_pl330_chan *ch)
-{
- struct rk29_pl330_dmac *d, *dmac = NULL;
- unsigned sn, sl = MIN_SUIT;
-
- list_for_each_entry(d, &dmac_list, node) {
- sn = suitablility(d, ch);
-
- if (sn == MAX_SUIT)
- return d;
-
- if (sn > sl)
- dmac = d;
- }
-
- return dmac;
-}
-
-/* Acquire the channel for peripheral 'id' */
-static struct rk29_pl330_chan *chan_acquire(const enum dma_ch id)
-{
- struct rk29_pl330_chan *ch = id_to_chan(id);
- struct rk29_pl330_dmac *dmac;
-
- /* If the channel doesn't exist or is already acquired */
- if (!ch || !chan_free(ch)) {
- ch = NULL;
- goto acq_exit;
- }
-
- dmac = map_chan_to_dmac(ch);
- /* If couldn't map */
- if (!dmac) {
- ch = NULL;
- goto acq_exit;
- }
-
- dmac->busy_chan++;
- ch->dmac = dmac;
-
-acq_exit:
- return ch;
-}
-
-/* Delete xfer from the queue */
-static inline void del_from_queue(struct rk29_pl330_xfer *xfer)
-{
- struct rk29_pl330_xfer *t;
- struct rk29_pl330_chan *ch;
- int found;
-
- if (!xfer)
- return;
-
- ch = xfer->chan;
-
- /* Make sure xfer is in the queue */
- found = 0;
- list_for_each_entry(t, &ch->xfer_list, node)
- if (t == xfer) {
- found = 1;
- break;
- }
-
- if (!found)
- return;
-
- /* If xfer is last entry in the queue */
- if (xfer->node.next == &ch->xfer_list)
- t = list_entry(ch->xfer_list.next,
- struct rk29_pl330_xfer, node);
- else
- t = list_entry(xfer->node.next,
- struct rk29_pl330_xfer, node);
-
- /* If there was only one node left */
- if (t == xfer)
- ch->xfer_head = NULL;
- else if (ch->xfer_head == xfer)
- ch->xfer_head = t;
-
- list_del(&xfer->node);
-}
-
-/* Provides pointer to the next xfer in the queue.
- * If CIRCULAR option is set, the list is left intact,
- * otherwise the xfer is removed from the list.
- * Forced delete 'pluck' can be set to override the CIRCULAR option.
- */
-static struct rk29_pl330_xfer *get_from_queue(struct rk29_pl330_chan *ch,
- int pluck)
-{
- struct rk29_pl330_xfer *xfer = ch->xfer_head;
-
- if (!xfer)
- return NULL;
-
- /* If xfer is last entry in the queue */
- if (xfer->node.next == &ch->xfer_list)
- ch->xfer_head = list_entry(ch->xfer_list.next,
- struct rk29_pl330_xfer, node);
- else
- ch->xfer_head = list_entry(xfer->node.next,
- struct rk29_pl330_xfer, node);
-
- if (pluck || !(ch->options & RK29_DMAF_CIRCULAR))
- del_from_queue(xfer);
-
- return xfer;
-}
-
-static inline void add_to_queue(struct rk29_pl330_chan *ch,
- struct rk29_pl330_xfer *xfer, int front)
-{
- struct pl330_xfer *xt;
-
- /* If queue empty */
- if (ch->xfer_head == NULL)
- ch->xfer_head = xfer;
-
- xt = &ch->xfer_head->px;
- /* If the head already submitted (CIRCULAR head) */
- if (ch->options & RK29_DMAF_CIRCULAR &&
- (xt == ch->req[0].x || xt == ch->req[1].x))
- ch->xfer_head = xfer;
-
- /* If this is a resubmission, it should go at the head */
- if (front) {
- ch->xfer_head = xfer;
- list_add(&xfer->node, &ch->xfer_list);
- } else {
- list_add_tail(&xfer->node, &ch->xfer_list);
- }
-}
-
-static inline void _finish_off(struct rk29_pl330_xfer *xfer,
- enum rk29_dma_buffresult res, int ffree)
-{
- struct rk29_pl330_chan *ch;
-
- if (!xfer)
- return;
-
- ch = xfer->chan;
-
- /* Do callback */
-
- if (ch->callback_fn)
- ch->callback_fn(xfer->token, xfer->px.bytes, res);
-
- /* Force Free or if buffer is not needed anymore */
- if (ffree || !(ch->options & RK29_DMAF_CIRCULAR))
- kmem_cache_free(ch->dmac->kmcache, xfer);
-}
-
-static inline int rk29_pl330_submit(struct rk29_pl330_chan *ch,
- struct pl330_req *r)
-{
- struct rk29_pl330_xfer *xfer;
- int ret = 0;
-
- /* If already submitted */
- if (r->x)
- return 0;
-
- xfer = get_from_queue(ch, 0);
-
- if (xfer) {
- r->x = &xfer->px;
-
- /* Use max bandwidth for M<->M xfers */
- if (r->rqtype == MEMTOMEM) {
- struct pl330_info *pi = xfer->chan->dmac->pi;
- int burst = 1 << ch->rqcfg.brst_size;
- u32 bytes = r->x->bytes;
- int bl;
-
- bl = pi->pcfg.data_bus_width / 8;
- bl *= pi->pcfg.data_buf_dep;
- bl /= burst;
-
- /* src/dst_burst_len can't be more than 16 */
- if (bl > 16)
- bl = 16;
-
- while (bl > 1) {
- if (!(bytes % (bl * burst)))
- break;
- bl--;
- }
-
- ch->rqcfg.brst_len = bl;
- }else {
- if(ch->id == DMACH_EMMC)
- ch->rqcfg.brst_len = 16; //yk
- //else
- // ch->rqcfg.brst_len = 1;
- }
-
- ret = pl330_submit_req(ch->pl330_chan_id, r);
-
- /* If submission was successful */
- if (!ret) {
- ch->lrq = r; /* latest submitted req */
- return 0;
- }
-
- r->x = NULL;
-
- /* If both of the PL330 ping-pong buffers filled */
- if (ret == -EAGAIN) {
- dev_err(ch->dmac->pi->dev, "%s:%d!\n",
- __func__, __LINE__);
- /* Queue back again */
- add_to_queue(ch, xfer, 1);
- ret = 0;
- } else {
- dev_err(ch->dmac->pi->dev, "%s:%d!\n",
- __func__, __LINE__);
- _finish_off(xfer, RK29_RES_ERR, 0);
- }
- }
-
- return ret;
-}
-
-static void rk29_pl330_rq(struct rk29_pl330_chan *ch,
- struct pl330_req *r, enum pl330_op_err err)
-{
- unsigned long flags;
- struct rk29_pl330_xfer *xfer;
- struct pl330_xfer *xl = r->x;
- enum rk29_dma_buffresult res;
-
- spin_lock_irqsave(&res_lock, flags);
-
- r->x = NULL;
-
- rk29_pl330_submit(ch, r);
-
- spin_unlock_irqrestore(&res_lock, flags);
-
- /* Map result to rk29 DMA API */
- if (err == PL330_ERR_NONE)
- res = RK29_RES_OK;
- else if (err == PL330_ERR_ABORT)
- res = RK29_RES_ABORT;
- else
- res = RK29_RES_ERR;
-
- /* If last request had some xfer */
- if (xl) {
- xfer = container_of(xl, struct rk29_pl330_xfer, px);
- _finish_off(xfer, res, 0);
- } else {
- dev_info(ch->dmac->pi->dev, "%s:%d No Xfer?!\n",
- __func__, __LINE__);
- }
-}
-
-static void rk29_pl330_rq0(void *token, enum pl330_op_err err)
-{
- struct pl330_req *r = token;
- struct rk29_pl330_chan *ch = container_of(r,
- struct rk29_pl330_chan, req[0]);
- rk29_pl330_rq(ch, r, err);
-}
-
-static void rk29_pl330_rq1(void *token, enum pl330_op_err err)
-{
- struct pl330_req *r = token;
- struct rk29_pl330_chan *ch = container_of(r,
- struct rk29_pl330_chan, req[1]);
- rk29_pl330_rq(ch, r, err);
-}
-
-/* Release an acquired channel */
-static void chan_release(struct rk29_pl330_chan *ch)
-{
- struct rk29_pl330_dmac *dmac;
-
- if (chan_free(ch))
- return;
-
- dmac = ch->dmac;
- ch->dmac = NULL;
- dmac->busy_chan--;
-}
-
-int rk29_dma_ctrl(enum dma_ch id, enum rk29_chan_op op)
-{
- struct rk29_pl330_xfer *xfer;
- enum pl330_chan_op pl330op;
- struct rk29_pl330_chan *ch;
- unsigned long flags;
- int idx, ret;
-
- spin_lock_irqsave(&res_lock, flags);
-
- ch = id_to_chan(id);
-
- if (!ch || chan_free(ch)) {
- ret = -EINVAL;
- goto ctrl_exit;
- }
-
- switch (op) {
- case RK29_DMAOP_START:
- /* Make sure both reqs are enqueued */
- idx = (ch->lrq == &ch->req[0]) ? 1 : 0;
- rk29_pl330_submit(ch, &ch->req[idx]);
- rk29_pl330_submit(ch, &ch->req[1 - idx]);
- pl330op = PL330_OP_START;
- break;
-
- case RK29_DMAOP_STOP:
- pl330op = PL330_OP_ABORT;
- break;
-
- case RK29_DMAOP_FLUSH:
- pl330op = PL330_OP_FLUSH;
- break;
-
- case RK29_DMAOP_PAUSE:
- case RK29_DMAOP_RESUME:
- case RK29_DMAOP_TIMEOUT:
- case RK29_DMAOP_STARTED:
- spin_unlock_irqrestore(&res_lock, flags);
- return 0;
-
- default:
- spin_unlock_irqrestore(&res_lock, flags);
- return -EINVAL;
- }
-
- ret = pl330_chan_ctrl(ch->pl330_chan_id, pl330op);
-
- if (pl330op == PL330_OP_START) {
- spin_unlock_irqrestore(&res_lock, flags);
- return ret;
- }
-
- idx = (ch->lrq == &ch->req[0]) ? 1 : 0;
-
- /* Abort the current xfer */
- if (ch->req[idx].x) {
- xfer = container_of(ch->req[idx].x,
- struct rk29_pl330_xfer, px);
-
- /* Drop xfer during FLUSH */
- if (pl330op == PL330_OP_FLUSH)
- del_from_queue(xfer);
-
- ch->req[idx].x = NULL;
-
- spin_unlock_irqrestore(&res_lock, flags);
- _finish_off(xfer, RK29_RES_ABORT,
- pl330op == PL330_OP_FLUSH ? 1 : 0);
- spin_lock_irqsave(&res_lock, flags);
- }
-
- /* Flush the whole queue */
- if (pl330op == PL330_OP_FLUSH) {
-
- if (ch->req[1 - idx].x) {
- xfer = container_of(ch->req[1 - idx].x,
- struct rk29_pl330_xfer, px);
-
- del_from_queue(xfer);
-
- ch->req[1 - idx].x = NULL;
-
- spin_unlock_irqrestore(&res_lock, flags);
- _finish_off(xfer, RK29_RES_ABORT, 1);
- spin_lock_irqsave(&res_lock, flags);
- }
-
- /* Finish off the remaining in the queue */
- xfer = ch->xfer_head;
- while (xfer) {
-
- del_from_queue(xfer);
-
- spin_unlock_irqrestore(&res_lock, flags);
- _finish_off(xfer, RK29_RES_ABORT, 1);
- spin_lock_irqsave(&res_lock, flags);
-
- xfer = ch->xfer_head;
- }
- }
-
-ctrl_exit:
- spin_unlock_irqrestore(&res_lock, flags);
-
- return ret;
-}
-EXPORT_SYMBOL(rk29_dma_ctrl);
-
-int rk29_dma_enqueue(enum dma_ch id, void *token,
- dma_addr_t addr, int size)
-{
- struct rk29_pl330_chan *ch;
- struct rk29_pl330_xfer *xfer;
- unsigned long flags;
- int idx, ret = 0;
-
- spin_lock_irqsave(&res_lock, flags);
-
- ch = id_to_chan(id);
-
- /* Error if invalid or free channel */
- if (!ch || chan_free(ch)) {
- ret = -EINVAL;
- goto enq_exit;
- }
-
- /* Error if size is unaligned */
- if (ch->rqcfg.brst_size && size % (1 << ch->rqcfg.brst_size)) {
- ret = -EINVAL;
- goto enq_exit;
- }
-
- xfer = kmem_cache_alloc(ch->dmac->kmcache, GFP_ATOMIC);
- if (!xfer) {
- ret = -ENOMEM;
- goto enq_exit;
- }
-
- xfer->token = token;
- xfer->chan = ch;
- xfer->px.bytes = size;
- xfer->px.next = NULL; /* Single request */
-
- /* For rk29 DMA API, direction is always fixed for all xfers */
- if (ch->req[0].rqtype == MEMTODEV) {
- xfer->px.src_addr = addr;
- xfer->px.dst_addr = ch->sdaddr;
- } else {
- xfer->px.src_addr = ch->sdaddr;
- xfer->px.dst_addr = addr;
- }
-
- add_to_queue(ch, xfer, 0);
-
- /* Try submitting on either request */
- idx = (ch->lrq == &ch->req[0]) ? 1 : 0;
-
- if (!ch->req[idx].x)
- rk29_pl330_submit(ch, &ch->req[idx]);
- else
- rk29_pl330_submit(ch, &ch->req[1 - idx]);
-
- spin_unlock_irqrestore(&res_lock, flags);
-
- if (ch->options & RK29_DMAF_AUTOSTART)
- rk29_dma_ctrl(id, RK29_DMAOP_START);
-
- return 0;
-
-enq_exit:
- spin_unlock_irqrestore(&res_lock, flags);
-
- return ret;
-}
-EXPORT_SYMBOL(rk29_dma_enqueue);
-
-int rk29_dma_request(enum dma_ch id,
- struct rk29_dma_client *client,
- void *dev)
-{
- struct rk29_pl330_dmac *dmac;
- struct rk29_pl330_chan *ch;
- unsigned long flags;
- int ret = 0;
-
- spin_lock_irqsave(&res_lock, flags);
-
- ch = chan_acquire(id);
- if (!ch) {
- ret = -EBUSY;
- goto req_exit;
- }
-
- dmac = ch->dmac;
-
- ch->pl330_chan_id = pl330_request_channel(id, dmac->pi);
- if (!ch->pl330_chan_id) {
- chan_release(ch);
- ret = -EBUSY;
- goto req_exit;
- }
-
- ch->client = client;
- ch->options = 0; /* Clear any option */
- ch->callback_fn = NULL; /* Clear any callback */
- ch->lrq = NULL;
-
- ch->rqcfg.brst_size = 2; /* Default word size */
- ch->rqcfg.swap = SWAP_NO;
- ch->rqcfg.scctl = SCCTRL0; /* Noncacheable and nonbufferable */
- ch->rqcfg.dcctl = DCCTRL0; /* Noncacheable and nonbufferable */
- ch->rqcfg.privileged = 0;
- ch->rqcfg.insnaccess = 0;
-
- /* Set invalid direction */
- ch->req[0].rqtype = DEVTODEV;
- ch->req[1].rqtype = ch->req[0].rqtype;
-
- ch->req[0].cfg = &ch->rqcfg;
- ch->req[1].cfg = ch->req[0].cfg;
-
- ch->req[0].peri = iface_of_dmac(dmac, id) - 1; /* Original index */
- ch->req[1].peri = ch->req[0].peri;
-
- ch->req[0].token = &ch->req[0];
- ch->req[0].xfer_cb = rk29_pl330_rq0;
- ch->req[1].token = &ch->req[1];
- ch->req[1].xfer_cb = rk29_pl330_rq1;
-
- ch->req[0].x = NULL;
- ch->req[1].x = NULL;
-
- /* Reset xfer list */
- INIT_LIST_HEAD(&ch->xfer_list);
- ch->xfer_head = NULL;
-
-req_exit:
- spin_unlock_irqrestore(&res_lock, flags);
-
- return ret;
-}
-EXPORT_SYMBOL(rk29_dma_request);
-
-int rk29_dma_free(enum dma_ch id, struct rk29_dma_client *client)
-{
- struct rk29_pl330_chan *ch;
- struct rk29_pl330_xfer *xfer;
- unsigned long flags;
- int ret = 0;
- unsigned idx;
-
- spin_lock_irqsave(&res_lock, flags);
-
- ch = id_to_chan(id);
-
- if (!ch || chan_free(ch))
- goto free_exit;
-
- /* Refuse if someone else wanted to free the channel */
- if (ch->client != client) {
- ret = -EBUSY;
- goto free_exit;
- }
-
- /* Stop any active xfer, Flushe the queue and do callbacks */
- pl330_chan_ctrl(ch->pl330_chan_id, PL330_OP_FLUSH);
-
- /* Abort the submitted requests */
- idx = (ch->lrq == &ch->req[0]) ? 1 : 0;
-
- if (ch->req[idx].x) {
- xfer = container_of(ch->req[idx].x,
- struct rk29_pl330_xfer, px);
-
- ch->req[idx].x = NULL;
- del_from_queue(xfer);
-
- spin_unlock_irqrestore(&res_lock, flags);
- _finish_off(xfer, RK29_RES_ABORT, 1);
- spin_lock_irqsave(&res_lock, flags);
- }
-
- if (ch->req[1 - idx].x) {
- xfer = container_of(ch->req[1 - idx].x,
- struct rk29_pl330_xfer, px);
-
- ch->req[1 - idx].x = NULL;
- del_from_queue(xfer);
-
- spin_unlock_irqrestore(&res_lock, flags);
- _finish_off(xfer, RK29_RES_ABORT, 1);
- spin_lock_irqsave(&res_lock, flags);
- }
-
- /* Pluck and Abort the queued requests in order */
- do {
- xfer = get_from_queue(ch, 1);
-
- spin_unlock_irqrestore(&res_lock, flags);
- _finish_off(xfer, RK29_RES_ABORT, 1);
- spin_lock_irqsave(&res_lock, flags);
- } while (xfer);
-
- ch->client = NULL;
-
- pl330_release_channel(ch->pl330_chan_id);
-
- ch->pl330_chan_id = NULL;
-
- chan_release(ch);
-
-free_exit:
- spin_unlock_irqrestore(&res_lock, flags);
-
- return ret;
-}
-EXPORT_SYMBOL(rk29_dma_free);
-
-/**
-* yk@rk 20110622
-* config the burst length when dma init or brst_len change
-* every peripher has to determine burst width and length by its FIFO
-*
-* param:
-* id: dma request id
-* xferunit: burst width in byte
-* brst_len: burst length every transfer
-*/
-int rk29_dma_config(enum dma_ch id, int xferunit, int brst_len)
-{
- struct rk29_pl330_chan *ch;
- struct pl330_info *pi;
- unsigned long flags;
- int i, dbwidth, ret = 0;
-
- spin_lock_irqsave(&res_lock, flags);
-
- ch = id_to_chan(id);
-
- if (!ch || chan_free(ch)) {
- ret = -EINVAL;
- goto cfg_exit;
- }
-#if 0
- pi = ch->dmac->pi;
- dbwidth = pi->pcfg.data_bus_width / 8;
-
- /* Max size of xfer can be pcfg.data_bus_width */
- if (xferunit > dbwidth) {
- ret = -EINVAL;
- goto cfg_exit;
- }
-
- i = 0;
- while (xferunit != (1 << i))
- i++;
-
- /* If valid value */
- if (xferunit == (1 << i))
- ch->rqcfg.brst_size = i;
- else
- ret = -EINVAL;
-#else
- i = 0;
- while (xferunit != (1 << i))
- i++;
-
- if(xferunit > 8)
- goto cfg_exit;
- else
- ch->rqcfg.brst_size = i;
-
- if(brst_len > 16)
- goto cfg_exit;
- else
- ch->rqcfg.brst_len = brst_len;
-#endif
-cfg_exit:
- spin_unlock_irqrestore(&res_lock, flags);
-
- return ret;
-}
-EXPORT_SYMBOL(rk29_dma_config);
-
-/* Options that are supported by this driver */
-#define RK29_PL330_FLAGS (RK29_DMAF_CIRCULAR | RK29_DMAF_AUTOSTART)
-
-int rk29_dma_setflags(enum dma_ch id, unsigned int options)
-{
- struct rk29_pl330_chan *ch;
- unsigned long flags;
- int ret = 0;
-
- spin_lock_irqsave(&res_lock, flags);
-
- ch = id_to_chan(id);
-
- if (!ch || chan_free(ch) || options & ~(RK29_PL330_FLAGS))
- ret = -EINVAL;
- else
- ch->options = options;
-
- spin_unlock_irqrestore(&res_lock, flags);
-
- return 0;
-}
-EXPORT_SYMBOL(rk29_dma_setflags);
-
-int rk29_dma_set_buffdone_fn(enum dma_ch id, rk29_dma_cbfn_t rtn)
-{
- struct rk29_pl330_chan *ch;
- unsigned long flags;
- int ret = 0;
-
- spin_lock_irqsave(&res_lock, flags);
-
- ch = id_to_chan(id);
-
- if (!ch || chan_free(ch))
- ret = -EINVAL;
- else
- ch->callback_fn = rtn;
-
- spin_unlock_irqrestore(&res_lock, flags);
-
- return ret;
-}
-EXPORT_SYMBOL(rk29_dma_set_buffdone_fn);
-
-int rk29_dma_devconfig(enum dma_ch id, enum rk29_dmasrc source,
- unsigned long address)
-{
- struct rk29_pl330_chan *ch;
- unsigned long flags;
- int ret = 0;
-
- spin_lock_irqsave(&res_lock, flags);
-
- ch = id_to_chan(id);
-
- if (!ch || chan_free(ch)) {
- ret = -EINVAL;
- goto devcfg_exit;
- }
-
- switch (source) {
- case RK29_DMASRC_HW: /* P->M */
- ch->req[0].rqtype = DEVTOMEM;
- ch->req[1].rqtype = DEVTOMEM;
- ch->rqcfg.src_inc = 0;
- ch->rqcfg.dst_inc = 1;
- break;
- case RK29_DMASRC_MEM: /* M->P */
- ch->req[0].rqtype = MEMTODEV;
- ch->req[1].rqtype = MEMTODEV;
- ch->rqcfg.src_inc = 1;
- ch->rqcfg.dst_inc = 0;
- break;
- case RK29_DMASRC_MEMTOMEM:
- ch->req[0].rqtype = MEMTOMEM;
- ch->req[1].rqtype = MEMTOMEM;
- ch->rqcfg.src_inc = 1;
- ch->rqcfg.dst_inc = 1;
- break;
- default:
- ret = -EINVAL;
- goto devcfg_exit;
- }
-
- ch->sdaddr = address;
-
-devcfg_exit:
- spin_unlock_irqrestore(&res_lock, flags);
-
- return ret;
-}
-EXPORT_SYMBOL(rk29_dma_devconfig);
-
-int rk29_dma_getposition(enum dma_ch id, dma_addr_t *src, dma_addr_t *dst)
-{
- struct rk29_pl330_chan *ch = id_to_chan(id);
- struct pl330_chanstatus status;
- int ret;
-
- if (!ch || chan_free(ch))
- return -EINVAL;
-
- ret = pl330_chan_status(ch->pl330_chan_id, &status);
- if (ret < 0)
- return ret;
-
- *src = status.src_addr;
- *dst = status.dst_addr;
-
- return 0;
-}
-EXPORT_SYMBOL(rk29_dma_getposition);
-
-static irqreturn_t pl330_irq_handler(int irq, void *data)
-{
- if (pl330_update(data))
- return IRQ_HANDLED;
- else
- return IRQ_NONE;
-}
-
-static int pl330_probe(struct platform_device *pdev)
-{
- struct rk29_pl330_dmac *rk29_pl330_dmac;
- struct rk29_pl330_platdata *pl330pd;
- struct pl330_info *pl330_info;
- struct resource *res;
- int i, ret, irq;
-
- pl330pd = pdev->dev.platform_data;
-
- /* Can't do without the list of _32_ peripherals */
- if (!pl330pd || !pl330pd->peri) {
- dev_err(&pdev->dev, "platform data missing!\n");
- return -ENODEV;
- }
-
- pl330_info = kzalloc(sizeof(*pl330_info), GFP_KERNEL);
- if (!pl330_info)
- return -ENOMEM;
-
- pl330_info->pl330_data = NULL;
- pl330_info->dev = &pdev->dev;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res) {
- ret = -ENODEV;
- goto probe_err1;
- }
-
- request_mem_region(res->start, resource_size(res), pdev->name);
-
- pl330_info->base = ioremap(res->start, resource_size(res));
- if (!pl330_info->base) {
- ret = -ENXIO;
- goto probe_err2;
- }
-
- irq = platform_get_irq(pdev, 0);
- if (irq < 0) {
- ret = irq;
- goto probe_err3;
- }
-
- ret = request_irq(irq, pl330_irq_handler, 0,
- dev_name(&pdev->dev), pl330_info);
-
- if(pdev->id == 0){
- WARN_ON(request_irq(IRQ_DMAC0_1, pl330_irq_handler, 0,
- dev_name(&pdev->dev), pl330_info) < 0);
- WARN_ON(request_irq(IRQ_DMAC0_2, pl330_irq_handler, 0,
- dev_name(&pdev->dev), pl330_info) < 0);
- WARN_ON(request_irq(IRQ_DMAC0_3, pl330_irq_handler, 0,
- dev_name(&pdev->dev), pl330_info) < 0);
- }
-
- if(pdev->id == 1){
- WARN_ON(request_irq(IRQ_DMAC1_1, pl330_irq_handler, 0,
- dev_name(&pdev->dev), pl330_info) < 0);
- WARN_ON(request_irq(IRQ_DMAC1_2, pl330_irq_handler, 0,
- dev_name(&pdev->dev), pl330_info) < 0);
- WARN_ON(request_irq(IRQ_DMAC1_3, pl330_irq_handler, 0,
- dev_name(&pdev->dev), pl330_info) < 0);
- WARN_ON(request_irq(IRQ_DMAC1_4, pl330_irq_handler, 0,
- dev_name(&pdev->dev), pl330_info) < 0);
- }
-
- if (ret)
- goto probe_err4;
-
- ret = pl330_add(pl330_info);
- if (ret)
- goto probe_err5;
-
- /* Allocate a new DMAC */
- rk29_pl330_dmac = kmalloc(sizeof(*rk29_pl330_dmac), GFP_KERNEL);
- if (!rk29_pl330_dmac) {
- ret = -ENOMEM;
- goto probe_err6;
- }
-
- /* Hook the info */
- rk29_pl330_dmac->pi = pl330_info;
-
- /* No busy channels */
- rk29_pl330_dmac->busy_chan = 0;
-
- rk29_pl330_dmac->kmcache = kmem_cache_create(dev_name(&pdev->dev),
- sizeof(struct rk29_pl330_xfer), 0, 0, NULL);
-
- if (!rk29_pl330_dmac->kmcache) {
- ret = -ENOMEM;
- goto probe_err7;
- }
-
- /* Get the list of peripherals */
- rk29_pl330_dmac->peri = pl330pd->peri;
-
- /* Attach to the list of DMACs */
- list_add_tail(&rk29_pl330_dmac->node, &dmac_list);
-
- /* Create a channel for each peripheral in the DMAC
- * that is, if it doesn't already exist
- */
- for (i = 0; i < PL330_MAX_PERI; i++)
- if (rk29_pl330_dmac->peri[i] != DMACH_MAX)
- chan_add(rk29_pl330_dmac->peri[i]);
-
- printk(KERN_INFO
- "Loaded driver for PL330 DMAC-%d %s\n", pdev->id, pdev->name);
- printk(KERN_INFO
- "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
- pl330_info->pcfg.data_buf_dep,
- pl330_info->pcfg.data_bus_width / 8, pl330_info->pcfg.num_chan,
- pl330_info->pcfg.num_peri, pl330_info->pcfg.num_events);
-
- return 0;
-
-probe_err7:
- kfree(rk29_pl330_dmac);
-probe_err6:
- pl330_del(pl330_info);
-probe_err5:
- free_irq(irq, pl330_info);
-probe_err4:
-probe_err3:
- iounmap(pl330_info->base);
-probe_err2:
- release_mem_region(res->start, resource_size(res));
-probe_err1:
- kfree(pl330_info);
-
- return ret;
-}
-
-static int pl330_remove(struct platform_device *pdev)
-{
- struct rk29_pl330_dmac *dmac, *d;
- struct rk29_pl330_chan *ch;
- unsigned long flags;
- int del, found;
-
- if (!pdev->dev.platform_data)
- return -EINVAL;
-
- spin_lock_irqsave(&res_lock, flags);
-
- found = 0;
- list_for_each_entry(d, &dmac_list, node)
- if (d->pi->dev == &pdev->dev) {
- found = 1;
- break;
- }
-
- if (!found) {
- spin_unlock_irqrestore(&res_lock, flags);
- return 0;
- }
-
- dmac = d;
-
- /* Remove all Channels that are managed only by this DMAC */
- list_for_each_entry(ch, &chan_list, node) {
-
- /* Only channels that are handled by this DMAC */
- if (iface_of_dmac(dmac, ch->id))
- del = 1;
- else
- continue;
-
- /* Don't remove if some other DMAC has it too */
- list_for_each_entry(d, &dmac_list, node)
- if (d != dmac && iface_of_dmac(d, ch->id)) {
- del = 0;
- break;
- }
-
- if (del) {
- spin_unlock_irqrestore(&res_lock, flags);
- rk29_dma_free(ch->id, ch->client);
- spin_lock_irqsave(&res_lock, flags);
- list_del(&ch->node);
- kfree(ch);
- }
- }
-
- /* Remove the DMAC */
- list_del(&dmac->node);
- kfree(dmac);
-
- spin_unlock_irqrestore(&res_lock, flags);
-
- return 0;
-}
-
-static struct platform_driver pl330_driver = {
- .driver = {
- .owner = THIS_MODULE,
- .name = "rk29-pl330",
- },
- .probe = pl330_probe,
- .remove = pl330_remove,
-};
-
-static int __init pl330_init(void)
-{
- return platform_driver_register(&pl330_driver);
-}
-module_init(pl330_init);
-
-static void __exit pl330_exit(void)
-{
- platform_driver_unregister(&pl330_driver);
- return;
-}
-module_exit(pl330_exit);
-
-MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
-MODULE_DESCRIPTION("Driver for PL330 DMA Controller");
-MODULE_LICENSE("GPL");
+++ /dev/null
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/input.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/suspend.h>
-#include <linux/platform_device.h>
-#include <linux/workqueue.h>
-#include <linux/suspend.h>
-#include <linux/power_supply.h>
-#include <linux/earlysuspend.h>
-#include <mach/rk29_iomap.h>
-#include <linux/io.h>
-#include <mach/gpio.h>
-
-
-
-#define CHARGE_EARLYSUSPEND 0
-#define CHARGE_EARLYRESUME 1
-
-/******************************************************************/
-#ifdef CONFIG_RK29_CHARGE_EARLYSUSPEND
-
-static DEFINE_MUTEX(power_suspend_lock);
-
-static struct early_suspend charge_lowerpower = {
-
- .level = -0xff,
- .suspend = NULL,
- .resume = NULL,
-};
-
-
-void charge_earlysuspend_enter(int status) //xsf
-{
-
-#ifdef CONFIG_HAS_EARLYSUSPEND
-
- struct early_suspend *pos;
- struct early_suspend *earlysuspend_temp;
- struct list_head *list_head;
- struct list_head *list_temp;
-
-
- mutex_lock(&power_suspend_lock);
-
- earlysuspend_temp = &charge_lowerpower;
- list_head = earlysuspend_temp->link.prev;
-
- if(status == 0)
- {
- list_for_each_entry(pos, list_head, link)
- {
-// printk("earlysuspend-level = %d --\n", pos->level);
- if (pos->suspend != NULL)
- pos->suspend(pos);
- }
- }
-
- if(status == 1)
- {
- list_for_each_entry_reverse(pos, list_head, link)
- {
-// printk("earlysuspend-level = %d --\n", pos->level);
- if (pos->resume != NULL)
- pos->resume(pos);
- }
- }
-
- mutex_unlock(&power_suspend_lock);
-#endif
-
-}
-int rk29_charge_judge(void)
-{
- return readl(RK29_GPIO4_BASE + GPIO_INT_STATUS);
-
-}
-extern int rk29_pm_enter(suspend_state_t state);
-
-int charger_suspend(void)
-{
-
-#ifdef CONFIG_RK29_CHARGE_EARLYSUSPEND
-
- charge_earlysuspend_enter(0);
- while(1)
- {
- local_irq_disable();
- rk29_pm_enter(PM_SUSPEND_MEM);
-
- if((rk29_charge_judge() &&(0x01000000)))
- {
- local_irq_enable();
- break;
- }
- else
- local_irq_enable();
- }
- charge_earlysuspend_enter(1); //xsf
- return 0;
-#endif
-}
-
-
-
-static int __devinit charge_lowerpower_probe(struct platform_device *pdev)
-{
-
-
- printk("%s\n",__FUNCTION__);
-#ifdef CONFIG_HAS_EARLYSUSPEND
- register_early_suspend(&charge_lowerpower);//xsf
-#endif
-
-}
-
-static struct platform_driver charge_lowerpower_driver = {
- .probe = charge_lowerpower_probe,
- .driver = {
- .name = "charge_lowerpower",
- .owner = THIS_MODULE,
- },
-};
-
-static int __init charge_lowerpower_init(void)
-{
- return platform_driver_register(&charge_lowerpower_driver);
-}
-module_init(charge_lowerpower_init);
-
-static void __exit charge_lowerpower_exit(void)
-{
- platform_driver_unregister(&charge_lowerpower_driver);
-}
-module_exit(charge_lowerpower_exit);
-
-
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("xsf<xsf@rock-chips.com>");
-MODULE_DESCRIPTION("charger lowerpower");
-
-
-#endif
-/***************************************************************/
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+++ /dev/null
-/***************************************spi **************************************************/
-#include <mach/rk29_iomap.h>
-#include <mach/board.h>
-#include <mach/sram.h>
-#include <mach/iomux.h>
-#include <mach/cru.h>
-#include <asm/io.h>
-#include <mach/gpio.h>
-
-#include <asm/vfp.h>
-
-
-#define GRF_GPIO0_DIR 0x000
-#define GRF_GPIO1_DIR 0x004
-#define GRF_GPIO2_DIR 0x008
-#define GRF_GPIO3_DIR 0x00c
-#define GRF_GPIO4_DIR 0x010
-#define GRF_GPIO5_DIR 0x014
-
-
-#define GRF_GPIO0_DO 0x018
-#define GRF_GPIO1_DO 0x01c
-#define GRF_GPIO2_DO 0x020
-#define GRF_GPIO3_DO 0x024
-#define GRF_GPIO4_DO 0x028
-#define GRF_GPIO5_DO 0x02c
-
-#define GRF_GPIO0_EN 0x030
-#define GRF_GPIO1_EN 0x034
-#define GRF_GPIO2_EN 0x038
-#define GRF_GPIO3_EN 0x03c
-#define GRF_GPIO4_EN 0x040
-#define GRF_GPIO5_EN 0x044
-
-
-#define GRF_GPIO0L_IOMUX 0x048
-#define GRF_GPIO0H_IOMUX 0x04c
-#define GRF_GPIO1L_IOMUX 0x050
-#define GRF_GPIO1H_IOMUX 0x054
-#define GRF_GPIO2L_IOMUX 0x058
-#define GRF_GPIO2H_IOMUX 0x05c
-#define GRF_GPIO3L_IOMUX 0x060
-#define GRF_GPIO3H_IOMUX 0x064
-#define GRF_GPIO4L_IOMUX 0x068
-#define GRF_GPIO4H_IOMUX 0x06c
-#define GRF_GPIO5L_IOMUX 0x070
-#define GRF_GPIO5H_IOMUX 0x074
-
-typedef struct GPIO_IOMUX
-{
- unsigned int GPIOL_IOMUX;
- unsigned int GPIOH_IOMUX;
-}GPIO_IOMUX_PM;
-
-//GRF Registers
-typedef struct REG_FILE_GRF
-{
- unsigned int GRF_GPIO_DIR[6];
- unsigned int GRF_GPIO_DO[6];
- unsigned int GRF_GPIO_EN[6];
- GPIO_IOMUX_PM GRF_GPIO_IOMUX[6];
- unsigned int GRF_GPIO_PULL[7];
-} GRF_REG_SAVE;
-
-
-int __sramdata crumode;
- u32 __sramdata gpio2_pull,gpio6_pull;
-
-
-#if 1
-void __sramfunc sram_printch(char byte);
-void __sramfunc printhex(unsigned int hex);
-#define sram_printHX(a)
-#else
-#define sram_printch(a)
-#define sram_printHX(a)
-#endif
-
-#define grf_readl(offset) readl(RK29_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel(v, RK29_GRF_BASE + offset); readl(RK29_GRF_BASE + offset); } while (0)
-
-#define sram_udelay(usecs,a) LOOP((usecs)*LOOPS_PER_USEC)
-
-#if defined(CONFIG_RK29_SPI_INSRAM)
-
-#define SPI_KHZ (1000)
-#define SPI_MHZ (1000*1000)
-#define GPLL_SPEED (24*SPI_MHZ)
-#define SPI_SR_SPEED (2*SPI_MHZ)
-
-
-#if defined(CONFIG_MACH_RK29_A22)||defined(CONFIG_MACH_RK29_PHONESDK)||defined(CONFIG_MACH_RK29_TD8801_V2)
-
-#define SRAM_SPI_CH 1
-#define SRAM_SPI_CS 1
-#define SRAM_SPI_DATA_BYTE 2
-#define SRAM_SPI_ADDRBASE RK29_SPI1_BASE//RK29_SPI0_BASE
-#define SPI_SPEED (500*SPI_KHZ)
-//#elif defined()
-#else
-#define SRAM_SPI_CH 1
-#define SRAM_SPI_CS 1
-#define SRAM_SPI_DATA_BYTE 2
-#define SRAM_SPI_ADDRBASE RK29_SPI1_BASE//RK29_SPI0_BASE
-#define SPI_SPEED (500*SPI_KHZ)
-#endif
-
-#define SRAM_SPI_SR_DIV (GPLL_SPEED/SPI_SR_SPEED-1) //
-#define SRAM_SPI_DIV (SPI_SR_SPEED/SPI_SPEED)
-//#include <mach/spi_sram.h>
-
-#define SPIM_ENR 0x0008
-#define SPIM_SER 0x000C
-#define SPIM_CTRLR0 0x0000
-#define SPIM_BAUDR 0x0010
-#define SPIM_TXFTLR 0x0014
-#define SPIM_RXFLR 0x0020
-#define cs1 1
-#define cs0 0
-#define spi1 1
-#define spi0 0
-#define SPIM_SR 0x0024
-
-#define SPIM_IMR 0x002c
-#define SPIM_TXDR 0x400
-#define SPIM_RXDR 0x800
-/* Bit fields in rxflr, */
-#define RXFLR_MASK (0x3f)
-/* Bit fields in SR, 7 bits */
-#define SR_MASK 0x7f /* cover 7 bits */
-#define SR_BUSY (1 << 0)
-#define SR_TF_FULL (1 << 1)
-#define SR_TF_EMPT (1 << 2)
-#define SR_RF_EMPT (1 << 3)
-#define SR_RF_FULL (1 << 4)
-
-#define PM_GETGPIO_BASE(N) RK29_GPIO##N##_BASE
-#define PM_GPIO_DR 0
-#define PM_GPIO_DDR 0x4
-#define PM_GPIO_INTEN 0x30
-
-#define wm831x_RD_MSK (0x1<<15)
-#define wm831x_RD_VOID (0x7FFF)
-#define spi_ctr0_mask 0x1fffc3
-
-
-
-enum
-{
-GRF_IOM50=0,
-GRF_IOM5c,
-CLKGATE1,
-CLKGATE2,
-CLKSEL6,
-SPI_CTRLR0,
-SPI_BAUDR,
-SPI_SER,
-DATE_END,
-};
- static u32 __sramdata spi_data[DATE_END]={};
-
-#define sram_spi_dis() spi_writel(spi_readl(SPIM_ENR)&~(0x1<<0),SPIM_ENR)
-#define sram_spi_en() spi_writel(spi_readl(SPIM_ENR)|(0x1<<0),SPIM_ENR)
-#define sram_spi_cs_dis() spi_writel(spi_readl(SPIM_SER)&~0x3,SPIM_SER)
-#define sram_spi_cs_en() spi_writel((spi_readl(SPIM_SER)&~0x3)|(0x1<<SRAM_SPI_CS),SPIM_SER)
-#define sram_spi_busy() (spi_readl(SPIM_SR)&SR_BUSY)
-
-#define spi_readl(offset) readl(SRAM_SPI_ADDRBASE + offset)
-#define spi_writel(v, offset) writel(v, SRAM_SPI_ADDRBASE+ offset)
-
-
-#define SPI_GATE1_MASK 0xCF
-
-void interface_ctr_reg_pread(void)
-{
- unsigned int temp,temp2;
-
- temp=readl(RK29_CRU_BASE + CRU_CLKGATE1_CON);
- temp2=readl(RK29_CRU_BASE + CRU_CLKGATE2_CON);
-
- writel(temp&~(SPI_GATE1_MASK),RK29_CRU_BASE + CRU_CLKGATE1_CON);
- writel(temp2&~(1<<(15+SRAM_SPI_CH)),RK29_CRU_BASE + CRU_CLKGATE2_CON); //spi clock enable
-
- readl(SRAM_SPI_ADDRBASE);
-
- writel(temp2,RK29_CRU_BASE + CRU_CLKGATE2_CON);
- writel(temp,RK29_CRU_BASE + CRU_CLKGATE1_CON);
- readl(RK29_GPIO0_BASE);
- readl(RK29_GPIO1_BASE);
- readl(RK29_GPIO2_BASE);
- readl(RK29_GPIO3_BASE);
- readl(RK29_GPIO4_BASE);
- readl(RK29_GPIO5_BASE);
- readl(RK29_GPIO6_BASE);
-
-
-}
-
-
-static void __sramfunc sram_spi_deinit(void)
-{
- sram_spi_dis();
-
- spi_writel(spi_data[SPI_CTRLR0],SPIM_CTRLR0);
- spi_writel(spi_data[SPI_BAUDR],SPIM_BAUDR);
- spi_writel(spi_data[SPI_SER],SPIM_SER);
-
-
- writel(spi_data[GRF_IOM5c],RK29_GRF_BASE + 0x5c);
- writel(spi_data[GRF_IOM50],RK29_GRF_BASE +0x50);
-
- writel(spi_data[CLKSEL6], RK29_CRU_BASE + CRU_CLKSEL6_CON);
- writel(spi_data[CLKGATE2],RK29_CRU_BASE + CRU_CLKGATE2_CON);
- writel(spi_data[CLKGATE1],RK29_CRU_BASE + CRU_CLKGATE1_CON);
-}
-
-static void __sramfunc sram_spi_init(void)
-{
-
- //sram_printch('V');
- /***************prihp clk*******************/
- spi_data[CLKGATE1]=readl(RK29_CRU_BASE + CRU_CLKGATE1_CON);
- writel(spi_data[CLKGATE1]&~(SPI_GATE1_MASK),RK29_CRU_BASE + CRU_CLKGATE1_CON);
-
- /***************spi sr clk speed*******************/
- spi_data[CLKSEL6]=readl(RK29_CRU_BASE + CRU_CLKSEL6_CON);
- writel((spi_data[CLKSEL6]&~(0x7f<<(2+SRAM_SPI_CH*9)))|(SRAM_SPI_SR_DIV<<(2+SRAM_SPI_CH*9)),
- RK29_CRU_BASE + CRU_CLKSEL6_CON);//spi sr clk speed
-
-
- /***************spi clk enable*******************/
- spi_data[CLKGATE2]=readl(RK29_CRU_BASE + CRU_CLKGATE2_CON);
- writel(spi_data[CLKGATE2]&~(1<<(15+SRAM_SPI_CH)),RK29_CRU_BASE + CRU_CLKGATE2_CON);//spi clk enable
-
- /***************spi iomox*******************/
- spi_data[GRF_IOM50]=readl(RK29_GRF_BASE +0x50);
- spi_data[GRF_IOM5c]=readl(RK29_GRF_BASE +0x5c);
- if(SRAM_SPI_CS)
- writel((spi_data[GRF_IOM50]&~(0x3<<(8-2*SRAM_SPI_CH)))|(0x2<<(8-2*SRAM_SPI_CH)),RK29_GRF_BASE +0x50); //spi cs1 iomux
- else
- writel((spi_data[GRF_IOM5c]&~(0x3<<(2+8*SRAM_SPI_CH)))|(0x1<<(2+8*SRAM_SPI_CH)),RK29_GRF_BASE +0x5c); //spi cs0 iomux
-
- writel((spi_data[GRF_IOM5c]&~(0xf3<<(SRAM_SPI_CH*8)))
- |(0x51<<(SRAM_SPI_CH*8)),RK29_GRF_BASE +0x5c); //spi clk\txd\rxd iomux
-
-
- /***************spi ctr*******************/
-
- //spibase=spi_base[ch];
- //sram_spi_cs=cs;
-
- sram_spi_dis();// disable spi
-
- spi_data[SPI_CTRLR0] = spi_readl(SPIM_CTRLR0);
- spi_data[SPI_BAUDR] = spi_readl(SPIM_BAUDR);
- spi_writel((spi_data[SPI_CTRLR0]&~0x1fffc3)|0x1<<11|(SRAM_SPI_DATA_BYTE),SPIM_CTRLR0);//spi setting
- spi_writel((spi_data[SPI_BAUDR]&(~0xffff))|SRAM_SPI_DIV,SPIM_BAUDR);//setting spi speed
- spi_data[SPI_SER]=spi_readl(SPIM_SER);//spi cs
-
-}
-
-static void __sramfunc sram_spi_write(unsigned short add,unsigned short data)
-{
- sram_spi_cs_en();
- sram_udelay(10,24);
- sram_spi_en();
-
- spi_writel(add,SPIM_TXDR);
- spi_writel(data,SPIM_TXDR);
- //delay_test(100);
-
- sram_udelay(100,24);
-
- //while(sram_spi_busy())
- //{
- sram_udelay(1,24);
- //sram_printch('B');
- //}
-
- sram_spi_dis();
- sram_udelay(10,24);
- sram_spi_cs_dis();
-}
-
-static unsigned short __sramfunc sram_spi_read(unsigned short add,unsigned short data){
- unsigned short ret=-1,ret1;
-
- sram_spi_cs_en();
- sram_udelay(10,24);
- sram_spi_en();
-
- spi_writel(add,SPIM_TXDR);
- //delay_test(100);
- spi_writel(data,SPIM_TXDR);
-
- //while(sram_spi_busy())
- //{
- sram_udelay(1,24);
- //sram_printch('B');
- //}
-
- sram_udelay(100,24);
-
- ret1=spi_readl(SPIM_RXDR);
- ret=spi_readl(SPIM_RXDR);
-
- //while(sram_spi_busy())
- //{
- sram_udelay(1,24);
- //sram_printch('B');
- //}
-
- sram_spi_dis();
- sram_udelay(10,24);
- sram_spi_cs_dis();
- return ret;
-}
-
-
-unsigned int __sramfunc rk29_suspend_voltage_set(unsigned int vol)
-{
-#if 0 //test
- unsigned short addr_4003=0x4003,addr_405d=0x405d,
- addr_4059=0x4059,addr_405e=0x405e,addr_4063=0x4063;
- unsigned short data_4003,data_405d,
- data_405e,data_4059,data_4063;
-
- sram_printch('s');
- sram_spi_init();
- sram_printch('\n');
- sram_printch('M');
- data_4059=sram_spi_read(addr_4059|wm831x_RD_MSK,wm831x_RD_VOID);
- sram_printHX(data_4059);//dc1 sleep
-
- data_405e=sram_spi_read(addr_405e|wm831x_RD_MSK,wm831x_RD_VOID);
- sram_printHX(data_405e);//dc2 sleep
-
- data_4063=sram_spi_read(addr_4063|wm831x_RD_MSK,wm831x_RD_VOID);
- sram_printHX(data_405e);//dc3 sleep
-
-
-
- data_4003=sram_spi_read(addr_4003|wm831x_RD_MSK,wm831x_RD_VOID);
- sram_printHX(data_4003);//sleep ctr
-
-
-
-
-
- sram_printch('N');
-
- data_4059=(data_4059&~(0x7f))|0x68;
- sram_spi_write(addr_4059,data_4059);//dc1 sleep 3.0v
-
- data_405e=(data_405e&~(0x7f))|0x28;//1.2 0x38 / 1.0 0x28,1.3 0x40
- sram_spi_write(addr_405e,data_405e);//dc2 sleep
-
- data_4063=(data_4063&~(0x7f))|0x56;
- sram_spi_write(addr_4063,data_4063);//dc3 sleep 1.8V
-
-
-
- sram_printch('J');
- data_4003|=(0x1<<14);
- sram_spi_write(addr_4003,data_4003);// sleep
-
- sram_printch('L');
- data_4059=sram_spi_read(addr_4059|wm831x_RD_MSK,wm831x_RD_VOID);
- sram_printHX(data_4059);
-
- data_405e=sram_spi_read(addr_405e|wm831x_RD_MSK,wm831x_RD_VOID);
- sram_printHX(data_405e);
-
-
- data_4063=sram_spi_read(addr_4063|wm831x_RD_MSK,wm831x_RD_VOID);
- sram_printHX(data_4063);
-
- data_4003=sram_spi_read(addr_4003|wm831x_RD_MSK,wm831x_RD_VOID);
- sram_printHX(data_4003);
-
-
-
- sram_spi_deinit();
- #else
- unsigned short addr_4003=0x4003;
- unsigned short data_4003;
- sram_spi_init(); //iomux clk
- data_4003=sram_spi_read(addr_4003|wm831x_RD_MSK,wm831x_RD_VOID);
- //sram_printHX(data_4003);//sleep ctr
- //sram_printch('G');
- sram_spi_write(addr_4003,data_4003|(0x1<<14));// sleep
- data_4003=sram_spi_read(addr_4003|wm831x_RD_MSK,wm831x_RD_VOID);
- //sram_printHX(data_4003);//sleep ctr
- sram_spi_deinit();
- #endif
- return 0;
-}
-void __sramfunc rk29_suspend_voltage_resume(unsigned int vol)
-{
-
- unsigned short addr_4003=0x4003;
- unsigned short data_4003;
- sram_spi_init(); //iomux clk
-
- data_4003=sram_spi_read(addr_4003|wm831x_RD_MSK,wm831x_RD_VOID);
- //sram_printHX(data_4003);//sleep ctr
-
- //sram_printch('G');
- sram_spi_write(addr_4003,data_4003&~(0x1<<14));
-
- data_4003=sram_spi_read(addr_4003|wm831x_RD_MSK,wm831x_RD_VOID);
-
- //sram_printHX(data_4003);//sleep ctr
-
- sram_spi_deinit();
-
- sram_udelay(100000, 24);
-
-
-}
-#endif
-/*******************************************gpio*********************************************/
-#ifdef CONFIG_RK29_CLK_SWITCH_TO_32K
-#define PM_GETGPIO_BASE(N) RK29_GPIO##N##_BASE
-#define PM_GPIO_DR 0
-#define PM_GPIO_DDR 0x4
-#define PM_GPIO_INTEN 0x30
-__sramdata u32 pm_gpio_base[7]=
-{
-RK29_GPIO0_BASE,
-RK29_GPIO1_BASE,
-RK29_GPIO2_BASE,
-RK29_GPIO3_BASE,
-RK29_GPIO4_BASE,
-RK29_GPIO5_BASE,
-RK29_GPIO6_BASE
-};
-
-#define pm_gpio_out_low(gpio) pm_gpio_set((gpio),GPIO_OUT,GPIO_LOW)
-#define pm_gpio_out_high(gpio) pm_gpio_set((gpio),GPIO_OUT,GPIO_HIGH)
-
-void __sramfunc pm_gpio_set(unsigned gpio,eGPIOPinDirection_t direction,eGPIOPinLevel_t level)
-{
- unsigned group,pin,value;
-
- gpio -= PIN_BASE; //must add
- group=gpio/32;
- pin=gpio%32;
- if(group>6||pin>31)
- return;
-
- if(direction==GPIO_OUT)
- {
- value=readl(pm_gpio_base[group]+PM_GPIO_DDR);
- value|=0x1<<pin;
- writel(value,pm_gpio_base[group]+PM_GPIO_DDR);
-
- value=readl(pm_gpio_base[group]+PM_GPIO_DR);
-
- if(level==GPIO_HIGH)
- value|=0x1<<pin;
- else
- value&=~(0x1<<pin);
-
- writel(value,pm_gpio_base[group]+PM_GPIO_DR);
-
-
- }
- else
- {
- value=readl(pm_gpio_base[group]+PM_GPIO_DDR);
- value&=~(0x1<<pin);
- writel(value,pm_gpio_base[group]+PM_GPIO_DDR);
-
- }
-}
-#endif
-/*****************************************gpio ctr*********************************************/
-#if defined(CONFIG_RK29_GPIO_SUSPEND)
-
-static GRF_REG_SAVE pm_grf;
-
-
-static void pm_keygpio_prepare(void)
-{
- gpio6_pull = grf_readl(GRF_GPIO6_PULL);
- gpio2_pull = grf_readl(GRF_GPIO2_PULL);
-}
- void pm_keygpio_sdk_suspend(void)
-{
- pm_keygpio_prepare();
- grf_writel(gpio6_pull|0x7f,GRF_GPIO6_PULL);//key pullup/pulldown disable
- grf_writel(gpio2_pull|0x00000f30,GRF_GPIO2_PULL);
-}
- void pm_keygpio_sdk_resume(void)
-{
- grf_writel(gpio6_pull,GRF_GPIO6_PULL);//key pullup/pulldown enable
- grf_writel(gpio2_pull,GRF_GPIO2_PULL);
-}
- void pm_keygpio_a22_suspend(void)
-{
- pm_keygpio_prepare();
- grf_writel(gpio6_pull|0x7f,GRF_GPIO6_PULL);//key pullup/pulldown disable
- grf_writel(gpio2_pull|0x00000900,GRF_GPIO2_PULL);
-}
- void pm_keygpio_a22_resume(void)
-{
- grf_writel(gpio6_pull,GRF_GPIO6_PULL);//key pullup/pulldown enable
- grf_writel(gpio2_pull,GRF_GPIO2_PULL);
-}
-
-
-static void pm_spi_gpio_prepare(void)
-{
- pm_grf.GRF_GPIO_IOMUX[1].GPIOL_IOMUX = grf_readl(GRF_GPIO1L_IOMUX);
- pm_grf.GRF_GPIO_IOMUX[2].GPIOH_IOMUX = grf_readl(GRF_GPIO2H_IOMUX);
-
- pm_grf.GRF_GPIO_PULL[1] = grf_readl(GRF_GPIO1_PULL);
- pm_grf.GRF_GPIO_PULL[2] = grf_readl(GRF_GPIO2_PULL);
-
- pm_grf.GRF_GPIO_EN[1] = grf_readl(GRF_GPIO1_EN);
- pm_grf.GRF_GPIO_EN[2] = grf_readl(GRF_GPIO2_EN);
-}
-
- void pm_spi_gpio_suspend(void)
-{
- int io1L_iomux;
- int io2H_iomux;
- int io1_pull,io2_pull;
- int io1_en,io2_en;
-
- pm_spi_gpio_prepare();
-
- io1L_iomux = grf_readl(GRF_GPIO1L_IOMUX);
- io2H_iomux = grf_readl(GRF_GPIO2H_IOMUX);
-
- grf_writel(io1L_iomux&(~((0x03<<6)|(0x03 <<8))), GRF_GPIO1L_IOMUX);
- grf_writel(io2H_iomux&0xffff0000, GRF_GPIO2H_IOMUX);
-
- io1_pull = grf_readl(GRF_GPIO1_PULL);
- io2_pull = grf_readl(GRF_GPIO2_PULL);
-
- grf_writel(io1_pull|0x18,GRF_GPIO1_PULL);
- grf_writel(io2_pull|0x00ff0000,GRF_GPIO2_PULL);
-
- io1_en = grf_readl(GRF_GPIO1_EN);
- io2_en = grf_readl(GRF_GPIO2_EN);
-
- grf_writel(io1_en|0x18,GRF_GPIO1_EN);
- grf_writel(io2_en|0x00ff0000,GRF_GPIO2_EN);
-}
-
- void pm_spi_gpio_resume(void)
-{
- grf_writel(pm_grf.GRF_GPIO_EN[1],GRF_GPIO1_EN);
- grf_writel(pm_grf.GRF_GPIO_EN[2],GRF_GPIO2_EN);
- grf_writel(pm_grf.GRF_GPIO_PULL[1],GRF_GPIO1_PULL);
- grf_writel(pm_grf.GRF_GPIO_PULL[2],GRF_GPIO2_PULL);
-
- grf_writel(pm_grf.GRF_GPIO_IOMUX[1].GPIOL_IOMUX, GRF_GPIO1L_IOMUX);
- grf_writel(pm_grf.GRF_GPIO_IOMUX[2].GPIOH_IOMUX, GRF_GPIO2H_IOMUX);
-}
-
-void pm_gpio_suspend(void)
-{
- pm_spi_gpio_suspend(); // spi pullup/pulldown disable....
- #if defined(CONFIG_MACH_RK29_PHONESDK)
- { pm_keygpio_sdk_suspend();// key pullup/pulldown disable.....
- }
- #endif
- #if defined(CONFIG_MACH_RK29_A22)
- { pm_keygpio_a22_suspend();// key pullup/pulldown disable.....
- }
- #endif
-}
-void pm_gpio_resume(void)
-{
- pm_spi_gpio_resume(); // spi pullup/pulldown enable.....
- #if defined(CONFIG_MACH_RK29_PHONESDK)
- { pm_keygpio_sdk_resume();// key pullup/pulldown enable.....
- }
- #endif
- #if defined(CONFIG_MACH_RK29_A22)
- { pm_keygpio_a22_resume();// key pullup/pulldown enable.....
- }
- #endif
-}
-#else
-void pm_gpio_suspend(void)
-{}
-void pm_gpio_resume(void)
-{}
-#endif
-
-
-#ifdef CONFIG_RK29_CLK_SWITCH_TO_32K
-void __sramfunc pm_clk_switch_32k(void)
-{
- sram_printch('7');
-
- #ifndef CONFIG_MACH_RK29_A22
- pm_gpio_out_high(RK29_PIN4_PC0);
- #endif
- //sram_udelay(10,30);
-
- crumode=cru_readl(CRU_MODE_CON); //24M to 27M
- cru_writel((crumode&(~0x7fff))|0x2baa, CRU_MODE_CON);
- //sram_udelay(10,30);
-
-// pm_gpio_iomux(RK29_PIN4_PC5,0x0);// disable 24
- pm_gpio_out_high(RK29_PIN4_PC5);
-
- //sram_udelay(10,30);
- dsb();
- asm("wfi");
-
- pm_gpio_out_low(RK29_PIN4_PC5);//enable 24M
- sram_udelay(20,24); //the system clock is 32.768K
- cru_writel(crumode, CRU_MODE_CON); //externel clk 24M
-
- #ifndef CONFIG_MACH_RK29_A22
- pm_gpio_out_low(RK29_PIN4_PC0); //enable 27M
- #endif
- //sram_udelay(1000,27);
- sram_printch('7');
-
-
-}
-
-#else
-void __sramfunc pm_clk_switch(void)
-{
-
-}
-#endif
+++ /dev/null
-/*
- * Very simple but very effective user-space memory tester.
- * Originally by Simon Kirby <sim@stormix.com> <sim@neato.org>
- * Version 2 by Charles Cazabon <charlesc-memtester@pyropus.ca>
- * Version 3 not publicly released.
- * Version 4 rewrite:
- * Copyright (C) 2007-2009 Charles Cazabon <charlesc-memtester@pyropus.ca>
- * Licensed under the terms of the GNU General Public License version 2 (only).
- * See the file COPYING for details.
- *
- * This file contains the functions for the actual tests, called from the
- * main routine in memtester.c. See other comments in that file.
- *
- */
-
-#include "tests.h"
-
-char progress[] = "-\\|/";
-#define PROGRESSLEN 4
-#define PROGRESSOFTEN 2500
-
-int compare_regions(ulv *bufa, ulv *bufb, size_t count) {
- int r = 0;
- size_t i;
- ulv *p1 = bufa;
- ulv *p2 = bufb;
- int n=0;
-
- for (i = 0; i < count; i++, p1++, p2++) {
- if (*p1 != *p2) {
- {
- print("FAILURE: 0x");
- print_Hex((ul) *p1);
- print(" != 0x");
- print_Hex((ul) *p2);
- print(" at offset 0x");
- print_Hex((ul) i);
- print(".\n");
- }
- /* printf("Skipping to next test..."); */
- r = -1;
- n++;
- if(n>10)
- {
- break;
- }
- }
- }
- return r;
-}
-
-int compare_regions_reverse(ulv *bufa, ulv *bufb, size_t count) {
- int r = 0;
- size_t i;
- ulv *p1 = bufa;
- ulv *p2 = bufb;
- int n=0;
-
- for (i = 0; i < count; i++, p1++, p2++) {
- if (*p1 != ~(*p2)) {
- {
- print("FAILURE: 0x");
- print_Hex((ul) *p1);
- print(" != 0x");
- print_Hex((ul) *p2);
- print(" at offset 0x");
- print_Hex((ul) i);
- print(".\n");
- }
- /* printf("Skipping to next test..."); */
- r = -1;
- n++;
- if(n>10)
- {
- break;
- }
- }
- }
- return r;
-}
-
-int test_stuck_address(ulv *bufa, size_t count) {
- ulv *p1 = bufa;
- unsigned int j;
- size_t i;
-
- print(" ");
- for (j = 0; j < 16; j++) {
- print("\b\b\b\b\b\b\b\b\b\b\b");
- p1 = (ulv *) bufa;
- print("setting ");
- print_Dec_3(j);
- for (i = 0; i < count; i++) {
- *p1 = ((j + i) % 2) == 0 ? (ul) p1 : ~((ul) p1);
- *p1++;
- }
- print("\b\b\b\b\b\b\b\b\b\b\b");
- print("testing ");
- print_Dec_3(j);
- p1 = (ulv *) bufa;
- for (i = 0; i < count; i++, p1++) {
- if (*p1 != (((j + i) % 2) == 0 ? (ul) p1 : ~((ul) p1))) {
- {
- print("FAILURE: possible bad address line at offset 0x");
- print_Hex((ul) i);
- print(".\n");
- }
- print("Skipping to next test...\n");
- return -1;
- }
- }
- }
- print("\b\b\b\b\b\b\b\b\b\b\b \b\b\b\b\b\b\b\b\b\b\b");
- return 0;
-}
-
-#ifdef TEST_RANDOM
-int test_random_value(ulv *bufa, ulv *bufb, size_t count) {
- ulv *p1 = bufa;
- ulv *p2 = bufb;
- size_t i;
-
- for (i = 0; i < count; i++) {
- *p1++ = *p2++ = rand_ul();
- if (!(i % PROGRESSOFTEN)) {
- }
- }
- print("\b \b");
- return compare_regions(bufa, bufb, count);
-}
-#endif
-
-#ifdef TEST_XOR
-int test_xor_comparison(ulv *bufa, ulv *bufb, size_t count) {
- ulv *p1 = bufa;
- ulv *p2 = bufb;
- size_t i;
- ul q = rand_ul();
-
- for (i = 0; i < count; i++) {
- *p1++ ^= q;
- *p2++ ^= q;
- }
- return compare_regions(bufa, bufb, count);
-}
-#endif
-
-#ifdef TEST_SUB
-int test_sub_comparison(ulv *bufa, ulv *bufb, size_t count) {
- ulv *p1 = bufa;
- ulv *p2 = bufb;
- size_t i;
- ul q = rand_ul();
-
- for (i = 0; i < count; i++) {
- *p1++ -= q;
- *p2++ -= q;
- }
- return compare_regions(bufa, bufb, count);
-}
-#endif
-
-#ifdef TEST_MUL
-int test_mul_comparison(ulv *bufa, ulv *bufb, size_t count) {
- ulv *p1 = bufa;
- ulv *p2 = bufb;
- size_t i;
- ul q = rand_ul();
-
- for (i = 0; i < count; i++) {
- *p1++ *= q;
- *p2++ *= q;
- }
- return compare_regions(bufa, bufb, count);
-}
-#endif
-
-#ifdef TEST_DIV
-int test_div_comparison(ulv *bufa, ulv *bufb, size_t count) {
- ulv *p1 = bufa;
- ulv *p2 = bufb;
- size_t i;
- ul q = rand_ul();
-
- for (i = 0; i < count; i++) {
- if (!q) {
- q++;
- }
- *p1++ /= q;
- *p2++ /= q;
- }
- return compare_regions(bufa, bufb, count);
-}
-#endif
-
-#ifdef TEST_OR
-int test_or_comparison(ulv *bufa, ulv *bufb, size_t count) {
- ulv *p1 = bufa;
- ulv *p2 = bufb;
- size_t i;
- ul q = rand_ul();
-
- for (i = 0; i < count; i++) {
- *p1++ |= q;
- *p2++ |= q;
- }
- return compare_regions(bufa, bufb, count);
-}
-#endif
-
-#ifdef TEST_AND
-int test_and_comparison(ulv *bufa, ulv *bufb, size_t count) {
- ulv *p1 = bufa;
- ulv *p2 = bufb;
- size_t i;
- ul q = rand_ul();
-
- for (i = 0; i < count; i++) {
- *p1++ &= q;
- *p2++ &= q;
- }
- return compare_regions(bufa, bufb, count);
-}
-#endif
-
-#ifdef TEST_SEQINC
-int test_seqinc_comparison(ulv *bufa, ulv *bufb, size_t count) {
- ulv *p1 = bufa;
- ulv *p2 = bufb;
- size_t i;
- ul q = rand_ul();
- ul value;
-
- for (i = 0; i < count; i++) {
- value = (i+q);
- *p1++ = value;
- *p2++ = ~value;
- //*p1++ = *p2++ = (i + q);
- }
- return compare_regions_reverse(bufa, bufb, count);
-}
-#endif
-
-#ifdef TEST_SOLID_BIT
-int test_solidbits_comparison(ulv *bufa, ulv *bufb, size_t count) {
- ulv *p1 = bufa;
- ulv *p2 = bufb;
- unsigned int j;
- ul q;
- size_t i;
- ul value;
-
- print(" ");
- for (j = 0; j < 64; j++) {
- print("\b\b\b\b\b\b\b\b\b\b\b");
- q = (j % 2) == 0 ? UL_ONEBITS : 0;
- print("setting ");
- print_Dec_3(j);
- p1 = (ulv *) bufa;
- p2 = (ulv *) bufb;
- for (i = 0; i < count; i++) {
- value = (i % 2) == 0 ? q : ~q;
- *p1++ = value;
- *p2++ = ~value;
- //*p1++ = *p2++ = (i % 2) == 0 ? q : ~q;
- }
- print("\b\b\b\b\b\b\b\b\b\b\b");
- print("testing ");
- print_Dec_3(j);
- if (compare_regions_reverse(bufa, bufb, count)) {
- return -1;
- }
- }
- print("\b\b\b\b\b\b\b\b\b\b\b \b\b\b\b\b\b\b\b\b\b\b");
- return 0;
-}
-#endif
-
-#ifdef TEST_CHECK_BOARD
-int test_checkerboard_comparison(ulv *bufa, ulv *bufb, size_t count) {
- ulv *p1 = bufa;
- ulv *p2 = bufb;
- unsigned int j;
- ul q;
- size_t i;
- ul value;
-
- print(" ");
- for (j = 0; j < 64; j++) {
- print("\b\b\b\b\b\b\b\b\b\b\b");
- q = (j % 2) == 0 ? CHECKERBOARD1 : CHECKERBOARD2;
- print("setting ");
- print_Dec_3(j);
- p1 = (ulv *) bufa;
- p2 = (ulv *) bufb;
- for (i = 0; i < count; i++) {
- value = (i % 2) == 0 ? q : ~q;
- *p1++ = value;
- *p2++ = ~value;
- //*p1++ = *p2++ = (i % 2) == 0 ? q : ~q;
- }
- print("\b\b\b\b\b\b\b\b\b\b\b");
- print("testing ");
- print_Dec_3(j);
- if (compare_regions_reverse(bufa, bufb, count)) {
- return -1;
- }
- }
- print("\b\b\b\b\b\b\b\b\b\b\b \b\b\b\b\b\b\b\b\b\b\b");
- return 0;
-}
-#endif
-
-#ifdef TEST_BLOCK_SEQ
-int test_blockseq_comparison(ulv *bufa, ulv *bufb, size_t count) {
- ulv *p1 = bufa;
- ulv *p2 = bufb;
- unsigned int j;
- size_t i;
- ul value;
-
- print(" ");
- for (j = 0; j < 256; j++) {
- print("\b\b\b\b\b\b\b\b\b\b\b");
- p1 = (ulv *) bufa;
- p2 = (ulv *) bufb;
- print("setting ");
- print_Dec_3(j);
- for (i = 0; i < count; i++) {
- value = (ul) UL_BYTE(j);
- *p1++ = value;
- *p2++ = ~value;
- //*p1++ = *p2++ = (ul) UL_BYTE(j);
- }
- print("\b\b\b\b\b\b\b\b\b\b\b");
- print("testing ");
- print_Dec_3(j);
- if (compare_regions_reverse(bufa, bufb, count)) {
- return -1;
- }
- }
- print("\b\b\b\b\b\b\b\b\b\b\b \b\b\b\b\b\b\b\b\b\b\b");
- return 0;
-}
-#endif
-
-#ifdef TEST_ZERO
-int test_walkbits0_comparison(ulv *bufa, ulv *bufb, size_t count) {
- ulv *p1 = bufa;
- ulv *p2 = bufb;
- unsigned int j;
- size_t i;
- ul value;
-
- print(" ");
- for (j = 0; j < UL_LEN * 2; j++) {
- print("\b\b\b\b\b\b\b\b\b\b\b");
- p1 = (ulv *) bufa;
- p2 = (ulv *) bufb;
- print("setting ");
- print_Dec_3(j);
- for (i = 0; i < count; i++) {
- if (j < UL_LEN) { /* Walk it up. */
- //*p1++ = *p2++ = 0x00000001 << j;
- value = 0x00000001 << j;
- *p1++ = value;
- *p2++ = ~value;
- } else { /* Walk it back down. */
- //*p1++ = *p2++ = 0x00000001 << (UL_LEN * 2 - j - 1);
- value = 0x00000001 << (UL_LEN * 2 - j - 1);
- *p1++ = value;
- *p2++ = ~value;
- }
- }
- print("\b\b\b\b\b\b\b\b\b\b\b");
- print("testing ");
- print_Dec_3(j);
- if (compare_regions_reverse(bufa, bufb, count)) {
- return -1;
- }
- }
- print("\b\b\b\b\b\b\b\b\b\b\b \b\b\b\b\b\b\b\b\b\b\b");
- return 0;
-}
-#endif
-
-#ifdef TEST_ONE
-int test_walkbits1_comparison(ulv *bufa, ulv *bufb, size_t count) {
- ulv *p1 = bufa;
- ulv *p2 = bufb;
- unsigned int j;
- size_t i;
- ul value;
-
- print(" ");
- for (j = 0; j < UL_LEN * 2; j++) {
- print("\b\b\b\b\b\b\b\b\b\b\b");
- p1 = (ulv *) bufa;
- p2 = (ulv *) bufb;
- print("setting ");
- print_Dec_3(j);
- for (i = 0; i < count; i++) {
- if (j < UL_LEN) { /* Walk it up. */
- //*p1++ = *p2++ = UL_ONEBITS ^ (0x00000001 << j);
- value = UL_ONEBITS ^ (0x00000001 << j);
- *p1++ = value;
- *p2++ = ~value;
- } else { /* Walk it back down. */
- //*p1++ = *p2++ = UL_ONEBITS ^ (0x00000001 << (UL_LEN * 2 - j - 1));
- value = UL_ONEBITS ^ (0x00000001 << (UL_LEN * 2 - j - 1));
- *p1++ = value;
- *p2++ = ~value;
- }
- }
- print("\b\b\b\b\b\b\b\b\b\b\b");
- print("testing ");
- print_Dec_3(j);
- if (compare_regions_reverse(bufa, bufb, count)) {
- return -1;
- }
- }
- print("\b\b\b\b\b\b\b\b\b\b\b \b\b\b\b\b\b\b\b\b\b\b");
- return 0;
-}
-#endif
-
-#ifdef TEST_BIT_SPREAD
-int test_bitspread_comparison(ulv *bufa, ulv *bufb, size_t count) {
- ulv *p1 = bufa;
- ulv *p2 = bufb;
- unsigned int j;
- size_t i;
- ul value;
-
- print(" ");
- for (j = 0; j < UL_LEN * 2; j++) {
- print("\b\b\b\b\b\b\b\b\b\b\b");
- p1 = (ulv *) bufa;
- p2 = (ulv *) bufb;
- print("setting ");
- print_Dec_3(j);
- for (i = 0; i < count; i++) {
- if (j < UL_LEN) { /* Walk it up. */
- //*p1++ = *p2++ = (i % 2 == 0)
- // ? (0x00000001 << j) | (0x00000001 << (j + 2))
- // : UL_ONEBITS ^ ((0x00000001 << j)
- // | (0x00000001 << (j + 2)));
- value = (i % 2 == 0)
- ? (0x00000001 << j) | (0x00000001 << (j + 2))
- : UL_ONEBITS ^ ((0x00000001 << j)
- | (0x00000001 << (j + 2)));
- *p1++ = value;
- *p2++ = ~value;
- } else { /* Walk it back down. */
- //*p1++ = *p2++ = (i % 2 == 0)
- // ? (0x00000001 << (UL_LEN * 2 - 1 - j)) | (0x00000001 << (UL_LEN * 2 + 1 - j))
- // : UL_ONEBITS ^ (0x00000001 << (UL_LEN * 2 - 1 - j)
- // | (0x00000001 << (UL_LEN * 2 + 1 - j)));
- value = (i % 2 == 0)
- ? (0x00000001 << (UL_LEN * 2 - 1 - j)) | (0x00000001 << (UL_LEN * 2 + 1 - j))
- : UL_ONEBITS ^ (0x00000001 << (UL_LEN * 2 - 1 - j)
- | (0x00000001 << (UL_LEN * 2 + 1 - j)));
- *p1++ = value;
- *p2++ = ~value;
- }
- }
- print("\b\b\b\b\b\b\b\b\b\b\b");
- print("testing ");
- print_Dec_3(j);
- if (compare_regions_reverse(bufa, bufb, count)) {
- return -1;
- }
- }
- print("\b\b\b\b\b\b\b\b\b\b\b \b\b\b\b\b\b\b\b\b\b\b");
- return 0;
-}
-#endif
-
-#ifdef TEST_BIT_FLIP
-int test_bitflip_comparison(ulv *bufa, ulv *bufb, size_t count) {
- ulv *p1 = bufa;
- ulv *p2 = bufb;
- unsigned int j, k;
- ul q;
- size_t i;
- ul value;
-
- print(" ");
- for (k = 0; k < UL_LEN; k++) {
- q = 0x00000001 << k;
- for (j = 0; j < 8; j++) {
- print("\b\b\b\b\b\b\b\b\b\b\b");
- q = ~q;
- print("setting ");
- print_Dec_3(k * 8 + j);
- p1 = (ulv *) bufa;
- p2 = (ulv *) bufb;
- for (i = 0; i < count; i++) {
- //*p1++ = *p2++ = (i % 2) == 0 ? q : ~q;
- value = (i % 2) == 0 ? q : ~q;
- *p1++ = value;
- *p2++ = ~value;
- }
- print("\b\b\b\b\b\b\b\b\b\b\b");
- print("testing ");
- print_Dec_3(k * 8 + j);
- if (compare_regions_reverse(bufa, bufb, count)) {
- return -1;
- }
- }
- }
- print("\b\b\b\b\b\b\b\b\b\b\b \b\b\b\b\b\b\b\b\b\b\b");
- return 0;
-}
-#endif
+++ /dev/null
-/*
- * Very simple yet very effective memory tester.
- * Originally by Simon Kirby <sim@stormix.com> <sim@neato.org>
- * Version 2 by Charles Cazabon <charlesc-memtester@pyropus.ca>
- * Version 3 not publicly released.
- * Version 4 rewrite:
- * Copyright (C) 2007-2009 Charles Cazabon <charlesc-memtester@pyropus.ca>
- * Licensed under the terms of the GNU General Public License version 2 (only).
- * See the file COPYING for details.
- *
- * This file contains the declarations for the functions for the actual tests,
- * called from the main routine in memtester.c. See other comments in that
- * file.
- *
- */
-
-#include <linux/kernel.h>
-#include <mach/rk29_iomap.h>
-
-#include <linux/random.h>
-
-//#if (ULONG_MAX == 4294967295UL)
-#if 1
- #define rand_ul() random32()
- #define UL_ONEBITS 0xffffffff
- #define UL_LEN 32
- #define CHECKERBOARD1 0x55555555
- #define CHECKERBOARD2 0xaaaaaaaa
- #define UL_BYTE(x) ((x | x << 8 | x << 16 | x << 24))
-#elif (ULONG_MAX == 18446744073709551615ULL)
- #define rand64() (((ul) rand32()) << 32 | ((ul) rand32()))
- #define rand_ul() rand64()
- #define UL_ONEBITS 0xffffffffffffffffUL
- #define UL_LEN 64
- #define CHECKERBOARD1 0x5555555555555555
- #define CHECKERBOARD2 0xaaaaaaaaaaaaaaaa
- #define UL_BYTE(x) (((ul)x | (ul)x<<8 | (ul)x<<16 | (ul)x<<24 | (ul)x<<32 | (ul)x<<40 | (ul)x<<48 | (ul)x<<56))
-#else
- #error long on this platform is not 32 or 64 bits
-#endif
-
-#define TEST_ALL
-
-#ifdef TEST_ALL // TEST_ALLµÄʱºòÕâЩ¶¼²»¶¯
-#define TEST_RANDOM
-#define TEST_XOR
-#define TEST_SUB
-#define TEST_MUL
-#define TEST_DIV
-#define TEST_OR
-#define TEST_AND
-#define TEST_SEQINC
-#define TEST_SOLID_BIT
-#define TEST_BLOCK_SEQ
-#define TEST_CHECK_BOARD
-#define TEST_BIT_SPREAD
-#define TEST_BIT_FLIP
-#define TEST_ONE
-#define TEST_ZERO
-#else //ÕâЩÅäÖÃÓÃÓÚÔöɾ
-//#define TEST_RANDOM
-//#define TEST_XOR
-//#define TEST_SUB
-//#define TEST_MUL
-//#define TEST_DIV
-//#define TEST_OR
-//#define TEST_AND
-//#define TEST_SEQINC
-//#define TEST_SOLID_BIT
-//#define TEST_BLOCK_SEQ
-//#define TEST_CHECK_BOARD
-//#define TEST_BIT_SPREAD
-#define TEST_BIT_FLIP
-//#define TEST_ONE
-//#define TEST_ZERO
-#endif
-
-
-typedef unsigned long ul;
-typedef unsigned long long ull;
-typedef unsigned long volatile ulv;
-/* DDR Controller register struct */
-typedef volatile struct DDR_REG_Tag
-{
- volatile unsigned int CCR; //Controller Configuration Register
- volatile unsigned int DCR; //DRAM Configuration Register
- volatile unsigned int IOCR; //IO Configuration Register
- volatile unsigned int CSR; //Controller Status Register
- volatile unsigned int DRR; //DRAM Refresh Register
- volatile unsigned int TPR[3]; //SDRAM Timing Parameters Registers
- volatile unsigned int DLLCR; //Global DLL Control Register
- volatile unsigned int DLLCR09[10]; //DDR Control Register 0-9
- volatile unsigned int RSLR[4]; //Rank System Latency Register 0-3
- volatile unsigned int RDGR[4]; //Rank DQS Gating Register 0-3
- volatile unsigned int DQTR[9]; //DQ Timing Register 0-8
- volatile unsigned int DQSTR; //DQS Timing Register
- volatile unsigned int DQSBTR; //DQS_b Timing Register
- volatile unsigned int ODTCR; //ODT Configuration Register
- volatile unsigned int DTR[2]; //Data Training Register 0-1
- volatile unsigned int DTAR; //Data Training Address Register
- volatile unsigned int ZQCR[3]; //SDRAM ZQ Control Register and SDRAM ZQCS Control Register 0-2
- volatile unsigned int ZQSR; //SDRAM ZQ Status Register
- volatile unsigned int TPR3; //SDRAM Timing Parameters Register 3
- volatile unsigned int ALPMR; //Automatic Low Power Mode Register
- volatile unsigned int Reserved[0x7c-0x30];
- volatile unsigned int MR; //Mode Register
- volatile unsigned int EMR; //Extended Mode Register
- volatile unsigned int EMR2; //Extended Mode Register 2
- volatile unsigned int EMR3; //Extended Mode Register 3
- //Memory Management Unit Registers
- volatile unsigned int HPCR[32]; //Host Port Configuration Register 0-31
- volatile unsigned int PQCR[8]; //Priority Queue Configuration Register 0-7
- volatile unsigned int MMGCR; //Memory Manager General Configuration Register
-}DDR_REG_T, *pDDR_REG_T;
-
-typedef struct tagGPIO_IOMUX
-{
- volatile unsigned int GPIOL_IOMUX;
- volatile unsigned int GPIOH_IOMUX;
-}GPIO_IOMUX_T;
-
-//GRF Registers
-typedef volatile struct tagREG_FILE
-{
- volatile unsigned int GRF_GPIO_DIR[6];
- volatile unsigned int GRF_GPIO_DO[6];
- volatile unsigned int GRF_GPIO_EN[6];
- GPIO_IOMUX_T GRF_GPIO_IOMUX[6];
- volatile unsigned int GRF_GPIO_PULL[7];
- volatile unsigned int GRF_UOC_CON[2];
- volatile unsigned int GRF_USB_CON;
- volatile unsigned int GRF_CPU_CON[2];
- volatile unsigned int GRF_CPU_STATUS;
- volatile unsigned int GRF_MEM_CON;
- volatile unsigned int GRF_MEM_STATUS[3];
- volatile unsigned int GRF_SOC_CON[5];
- volatile unsigned int GRF_OS_REG[4];
-} REG_FILE, *pREG_FILE;
-
-//CRU Registers
-typedef volatile struct tagCRU_REG
-{
- volatile unsigned int CRU_APLL_CON;
- volatile unsigned int CRU_DPLL_CON;
- volatile unsigned int CRU_CPLL_CON;
- volatile unsigned int CRU_PPLL_CON;
- volatile unsigned int CRU_MODE_CON;
- volatile unsigned int CRU_CLKSEL_CON[18];
- volatile unsigned int CRU_CLKGATE_CON[4];
- volatile unsigned int CRU_SOFTRST_CON[3];
-} CRU_REG, *pCRU_REG;
-
-#define pDDR_Reg ((pDDR_REG_T)RK29_DDRC_BASE)
-#define pGRF_Reg ((pREG_FILE)RK29_GRF_BASE)
-#define pSCU_Reg ((pCRU_REG)RK29_CRU_BASE)
-
-struct test
-{
- char *name;
- int (*fp)(ulv *bufa, ulv *bufb, size_t count);
-};
-
-typedef struct useful_data_tag
-{
- unsigned int testCap; //²âÊÔµÄÈÝÁ¿
- unsigned int WriteFreq;
- unsigned int ReadFreq;
-}useful_data_t;
-extern void printascii(const char *s);
-extern void print_Dec(unsigned int n);
-extern void print_Hex(unsigned int hex);
-extern void print(const char *s);
-extern void print_Dec_3(unsigned int value);
-
-
-/* Function declaration. */
-
-int test_stuck_address(unsigned long volatile *bufa, size_t count);
-int test_random_value(unsigned long volatile *bufa, unsigned long volatile *bufb, size_t count);
-int test_xor_comparison(unsigned long volatile *bufa, unsigned long volatile *bufb, size_t count);
-int test_sub_comparison(unsigned long volatile *bufa, unsigned long volatile *bufb, size_t count);
-int test_mul_comparison(unsigned long volatile *bufa, unsigned long volatile *bufb, size_t count);
-int test_div_comparison(unsigned long volatile *bufa, unsigned long volatile *bufb, size_t count);
-int test_or_comparison(unsigned long volatile *bufa, unsigned long volatile *bufb, size_t count);
-int test_and_comparison(unsigned long volatile *bufa, unsigned long volatile *bufb, size_t count);
-int test_seqinc_comparison(unsigned long volatile *bufa, unsigned long volatile *bufb, size_t count);
-int test_solidbits_comparison(unsigned long volatile *bufa, unsigned long volatile *bufb, size_t count);
-int test_checkerboard_comparison(unsigned long volatile *bufa, unsigned long volatile *bufb, size_t count);
-int test_blockseq_comparison(unsigned long volatile *bufa, unsigned long volatile *bufb, size_t count);
-int test_walkbits0_comparison(unsigned long volatile *bufa, unsigned long volatile *bufb, size_t count);
-int test_walkbits1_comparison(unsigned long volatile *bufa, unsigned long volatile *bufb, size_t count);
-int test_bitspread_comparison(unsigned long volatile *bufa, unsigned long volatile *bufb, size_t count);
-int test_bitflip_comparison(unsigned long volatile *bufa, unsigned long volatile *bufb, size_t count);
-int test_simple_comparison(ulv *bufa, ulv *bufb, size_t count);
-
+++ /dev/null
-/* linux/arch/arm/mach-rk29/timer.c
- *
- * Copyright (C) 2010 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/init.h>
-#include <linux/time.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/clk.h>
-#include <linux/clockchips.h>
-#include <linux/io.h>
-
-#include <asm/sched_clock.h>
-#include <asm/mach/time.h>
-#include <mach/rk29_iomap.h>
-
-#define TIMER_LOAD_COUNT 0x0000
-#define TIMER_CUR_VALUE 0x0004
-#define TIMER_CONTROL_REG 0x0008
-#define TIMER_EOI 0x000C
-#define TIMER_INT_STATUS 0x0010
-
-#define TIMER_DISABLE 6
-#define TIMER_ENABLE 3
-#define TIMER_ENABLE_FREE_RUNNING 5
-
-static inline void timer_write(u32 n, u32 v, u32 offset)
-{
- u32 addr = RK29_TIMER2_BASE + 0x4000 * (n - 2) + offset;
- writel(v, addr);
- dsb();
-}
-
-static inline u32 timer_read(u32 n, u32 offset)
-{
- u32 addr = RK29_TIMER2_BASE + 0x4000 * (n - 2) + offset;
- return readl(addr);
-}
-
-#define RK_TIMER_ENABLE(n) timer_write(n, TIMER_ENABLE, TIMER_CONTROL_REG)
-#define RK_TIMER_ENABLE_FREE_RUNNING(n) timer_write(n, TIMER_ENABLE_FREE_RUNNING, TIMER_CONTROL_REG)
-#define RK_TIMER_DISABLE(n) timer_write(n, TIMER_DISABLE, TIMER_CONTROL_REG)
-
-#define RK_TIMER_SETCOUNT(n, count) timer_write(n, count, TIMER_LOAD_COUNT)
-#define RK_TIMER_GETCOUNT(n) timer_read(n, TIMER_LOAD_COUNT)
-
-#define RK_TIMER_READVALUE(n) timer_read(n, TIMER_CUR_VALUE)
-#define RK_TIMER_INT_CLEAR(n) timer_read(n, TIMER_EOI)
-
-#define RK_TIMER_INT_STATUS(n) timer_read(n, TIMER_INT_STATUS)
-
-#define TIMER_CLKEVT 2 /* timer2 */
-#define IRQ_NR_TIMER_CLKEVT IRQ_TIMER2
-#define TIMER_CLKEVT_NAME "timer2"
-
-#define TIMER_CLKSRC 3 /* timer3 */
-#define IRQ_NR_TIMER_CLKSRC IRQ_TIMER3
-#define TIMER_CLKSRC_NAME "timer3"
-
-static int rk29_timer_set_next_event(unsigned long cycles, struct clock_event_device *evt)
-{
- do {
- RK_TIMER_DISABLE(TIMER_CLKEVT);
- RK_TIMER_SETCOUNT(TIMER_CLKEVT, cycles);
- RK_TIMER_ENABLE(TIMER_CLKEVT);
- } while (RK_TIMER_READVALUE(TIMER_CLKEVT) > cycles);
- return 0;
-}
-
-static void rk29_timer_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
-{
- u32 count;
-
- switch (mode) {
- case CLOCK_EVT_MODE_PERIODIC:
- count = clk_get_rate(clk_get(NULL, TIMER_CLKEVT_NAME)) / HZ - 1;
- do {
- RK_TIMER_DISABLE(TIMER_CLKEVT);
- RK_TIMER_SETCOUNT(TIMER_CLKEVT, count);
- RK_TIMER_ENABLE(TIMER_CLKEVT);
- } while (RK_TIMER_READVALUE(TIMER_CLKEVT) > count);
- break;
- case CLOCK_EVT_MODE_RESUME:
- case CLOCK_EVT_MODE_ONESHOT:
- break;
- case CLOCK_EVT_MODE_UNUSED:
- case CLOCK_EVT_MODE_SHUTDOWN:
- RK_TIMER_DISABLE(TIMER_CLKEVT);
- break;
- }
-}
-
-static struct clock_event_device rk29_timer_clockevent = {
- .name = TIMER_CLKEVT_NAME,
- .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
- .rating = 200,
- .set_next_event = rk29_timer_set_next_event,
- .set_mode = rk29_timer_set_mode,
-};
-
-static irqreturn_t rk29_timer_clockevent_interrupt(int irq, void *dev_id)
-{
- struct clock_event_device *evt = dev_id;
-
- RK_TIMER_INT_CLEAR(TIMER_CLKEVT);
- if (evt->mode == CLOCK_EVT_MODE_ONESHOT)
- RK_TIMER_DISABLE(TIMER_CLKEVT);
-
- evt->event_handler(evt);
-
- return IRQ_HANDLED;
-}
-
-static struct irqaction rk29_timer_clockevent_irq = {
- .name = TIMER_CLKEVT_NAME,
- .flags = IRQF_DISABLED | IRQF_TIMER,
- .handler = rk29_timer_clockevent_interrupt,
- .irq = IRQ_NR_TIMER_CLKEVT,
- .dev_id = &rk29_timer_clockevent,
-};
-
-static __init int rk29_timer_init_clockevent(void)
-{
- struct clock_event_device *ce = &rk29_timer_clockevent;
- struct clk *clk = clk_get(NULL, TIMER_CLKEVT_NAME);
- struct clk *pclk_periph = clk_get(NULL, "pclk_periph");
-
- clk_set_parent(clk, pclk_periph);
- clk_enable(clk);
-
- RK_TIMER_DISABLE(TIMER_CLKEVT);
-
- setup_irq(rk29_timer_clockevent_irq.irq, &rk29_timer_clockevent_irq);
-
- clockevents_calc_mult_shift(ce, clk_get_rate(clk), 4);
- ce->max_delta_ns = clockevent_delta2ns(0xFFFFFFFFUL, ce);
- ce->min_delta_ns = clockevent_delta2ns(1, ce) + 1;
-
- ce->cpumask = cpumask_of(0);
-
- clockevents_register_device(ce);
-
- return 0;
-}
-
-static cycle_t rk29_timer_read(struct clocksource *cs)
-{
- return ~RK_TIMER_READVALUE(TIMER_CLKSRC);
-}
-
-#define MASK (u32)~0
-
-static struct clocksource rk29_timer_clocksource = {
- .name = TIMER_CLKSRC_NAME,
- .rating = 200,
- .read = rk29_timer_read,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-static void __init rk29_timer_init_clocksource(void)
-{
- static char err[] __initdata = KERN_ERR "%s: can't register clocksource!\n";
- struct clocksource *cs = &rk29_timer_clocksource;
- struct clk *clk = clk_get(NULL, TIMER_CLKSRC_NAME);
- struct clk *pclk_periph = clk_get(NULL, "pclk_periph");
-
- clk_set_parent(clk, pclk_periph);
- clk_enable(clk);
-
- RK_TIMER_DISABLE(TIMER_CLKSRC);
- RK_TIMER_SETCOUNT(TIMER_CLKSRC, 0xFFFFFFFF);
- RK_TIMER_ENABLE_FREE_RUNNING(TIMER_CLKSRC);
-
- clocksource_calc_mult_shift(cs, clk_get_rate(clk), 60);
- if (clocksource_register(cs))
- printk(err, cs->name);
-}
-
-static DEFINE_CLOCK_DATA(cd);
-
-unsigned long long notrace sched_clock(void)
-{
- u32 cyc = ~RK_TIMER_READVALUE(TIMER_CLKSRC);
- const struct clocksource *cs = &rk29_timer_clocksource;
- return cyc_to_fixed_sched_clock(&cd, cyc, MASK, cs->mult, cs->shift);
-}
-
-static void notrace rk29_update_sched_clock(void)
-{
- u32 cyc = ~RK_TIMER_READVALUE(TIMER_CLKSRC);
- update_sched_clock(&cd, cyc, MASK);
-}
-
-static void __init rk29_sched_clock_init(void)
-{
- init_sched_clock(&cd, rk29_update_sched_clock, 32,
- clk_get_rate(clk_get(NULL, TIMER_CLKSRC_NAME)));
-}
-
-static void __init rk29_timer_init(void)
-{
- rk29_timer_init_clocksource();
- rk29_timer_init_clockevent();
- rk29_sched_clock_init();
-}
-
-struct sys_timer rk29_timer = {
- .init = rk29_timer_init
-};
-
+++ /dev/null
-/* linux/arch/arm/mach-rk29/timer.c
- *
- * Copyright (C) 2010 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/init.h>
-#include <linux/time.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/clk.h>
-#include <linux/clockchips.h>
-#include <linux/io.h>
-
-#include <asm/sched_clock.h>
-#include <asm/mach/time.h>
-#include <mach/rk29_iomap.h>
-#include <mach/cru.h>
-
-#define TIMER_LOAD_COUNT 0x0000
-#define TIMER_CUR_VALUE 0x0004
-#define TIMER_CONTROL_REG 0x0008
-#define TIMER_EOI 0x000C
-#define TIMER_INT_STATUS 0x0010
-
-#define TIMER_DISABLE 6
-#define TIMER_ENABLE 3
-#define TIMER_ENABLE_FREE_RUNNING 5
-
-static inline void timer_write(u32 n, u32 v, u32 offset)
-{
- u32 addr = RK29_TIMER0_BASE + 0x2000 * n + offset;
- barrier();
- writel(v, addr);
- dsb();
- barrier();
-}
-
-static inline u32 timer_read(u32 n, u32 offset)
-{
- u32 addr = RK29_TIMER0_BASE + 0x2000 * n + offset;
- return readl(addr);
-}
-
-static inline void timer_clk(u32 n, bool enable)
-{
- u32 gate = n ? CLK_GATE_TIMER1 : CLK_GATE_TIMER0;
- u32 offset = CRU_CLKGATE0_CON + (gate / 32) * 4;
- u32 v = cru_readl(offset);
- if (enable)
- v &= ~(1 << (gate % 32));
- else
- v |= 1 << (gate % 32);
- barrier();
- cru_writel(v, offset);
- barrier();
-}
-
-#define RK_TIMER_ENABLE(n) do { timer_write(n, TIMER_ENABLE, TIMER_CONTROL_REG); timer_clk(n, true); } while (0)
-#define RK_TIMER_ENABLE_FREE_RUNNING(n) do { timer_write(n, TIMER_ENABLE_FREE_RUNNING, TIMER_CONTROL_REG); timer_clk(n, true); } while (0)
-#define RK_TIMER_DISABLE(n) do { timer_write(n, TIMER_DISABLE, TIMER_CONTROL_REG); timer_clk(n, false); } while (0)
-
-#define RK_TIMER_SETCOUNT(n, count) timer_write(n, count, TIMER_LOAD_COUNT)
-#define RK_TIMER_GETCOUNT(n) timer_read(n, TIMER_LOAD_COUNT)
-
-#define RK_TIMER_READVALUE(n) timer_read(n, TIMER_CUR_VALUE)
-#define RK_TIMER_INT_CLEAR(n) timer_read(n, TIMER_EOI)
-
-#define RK_TIMER_INT_STATUS(n) timer_read(n, TIMER_INT_STATUS)
-
-#define TIMER_CLKEVT 0 /* timer0 */
-#define IRQ_NR_TIMER_CLKEVT IRQ_TIMER0
-#define TIMER_CLKEVT_NAME "timer0"
-
-#define TIMER_CLKSRC 1 /* timer1 */
-#define IRQ_NR_TIMER_CLKSRC IRQ_TIMER1
-#define TIMER_CLKSRC_NAME "timer1"
-
-static int rk29_timer_set_next_event(unsigned long cycles, struct clock_event_device *evt)
-{
- do {
- RK_TIMER_DISABLE(TIMER_CLKEVT);
- RK_TIMER_SETCOUNT(TIMER_CLKEVT, cycles);
- RK_TIMER_ENABLE(TIMER_CLKEVT);
- } while (RK_TIMER_READVALUE(TIMER_CLKEVT) > cycles);
- return 0;
-}
-
-static void rk29_timer_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
-{
- switch (mode) {
- case CLOCK_EVT_MODE_PERIODIC:
- do {
- RK_TIMER_DISABLE(TIMER_CLKEVT);
- RK_TIMER_SETCOUNT(TIMER_CLKEVT, 24000000/HZ - 1);
- RK_TIMER_ENABLE(TIMER_CLKEVT);
- } while (RK_TIMER_READVALUE(TIMER_CLKEVT) > (24000000/HZ - 1));
- break;
- case CLOCK_EVT_MODE_RESUME:
- case CLOCK_EVT_MODE_ONESHOT:
- break;
- case CLOCK_EVT_MODE_UNUSED:
- case CLOCK_EVT_MODE_SHUTDOWN:
- RK_TIMER_DISABLE(TIMER_CLKEVT);
- break;
- }
-}
-
-static struct clock_event_device rk29_timer_clockevent = {
- .name = TIMER_CLKEVT_NAME,
- .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
- .shift = 32,
- .rating = 200,
- .set_next_event = rk29_timer_set_next_event,
- .set_mode = rk29_timer_set_mode,
-};
-
-static irqreturn_t rk29_timer_clockevent_interrupt(int irq, void *dev_id)
-{
- struct clock_event_device *evt = dev_id;
-
- RK_TIMER_INT_CLEAR(TIMER_CLKEVT);
- if (evt->mode == CLOCK_EVT_MODE_ONESHOT)
- RK_TIMER_DISABLE(TIMER_CLKEVT);
-
- evt->event_handler(evt);
-
- return IRQ_HANDLED;
-}
-
-static struct irqaction rk29_timer_clockevent_irq = {
- .name = TIMER_CLKEVT_NAME,
- .flags = IRQF_DISABLED | IRQF_TIMER,
- .handler = rk29_timer_clockevent_interrupt,
- .irq = IRQ_NR_TIMER_CLKEVT,
- .dev_id = &rk29_timer_clockevent,
-};
-
-static __init int rk29_timer_init_clockevent(void)
-{
- struct clock_event_device *ce = &rk29_timer_clockevent;
- struct clk *clk = clk_get(NULL, TIMER_CLKEVT_NAME);
- struct clk *xin24m = clk_get(NULL, "xin24m");
-
- clk_set_parent(clk, xin24m);
-
- RK_TIMER_DISABLE(TIMER_CLKEVT);
-
- setup_irq(rk29_timer_clockevent_irq.irq, &rk29_timer_clockevent_irq);
-
- ce->mult = div_sc(24000000, NSEC_PER_SEC, ce->shift);
- ce->max_delta_ns = clockevent_delta2ns(0xFFFFFFFFUL, ce);
- ce->min_delta_ns = clockevent_delta2ns(1, ce) + 1;
-
- ce->cpumask = cpumask_of(0);
-
- clockevents_register_device(ce);
-
- return 0;
-}
-
-static cycle_t rk29_timer_read(struct clocksource *cs)
-{
- return ~RK_TIMER_READVALUE(TIMER_CLKSRC);
-}
-
-/*
- * Constants generated by clocksource_hz2mult(24000000, 26).
- * This gives a resolution of about 41ns and a wrap period of about 178s.
- */
-#define MULT 2796202667u
-#define SHIFT 26
-#define MASK (u32)~0
-
-static struct clocksource rk29_timer_clocksource = {
- .name = TIMER_CLKSRC_NAME,
- .rating = 200,
- .read = rk29_timer_read,
- .mask = CLOCKSOURCE_MASK(32),
- .shift = SHIFT,
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-static void __init rk29_timer_init_clocksource(void)
-{
- static char err[] __initdata = KERN_ERR "%s: can't register clocksource!\n";
- struct clocksource *cs = &rk29_timer_clocksource;
- struct clk *clk = clk_get(NULL, TIMER_CLKSRC_NAME);
- struct clk *xin24m = clk_get(NULL, "xin24m");
-
- clk_set_parent(clk, xin24m);
-
- RK_TIMER_DISABLE(TIMER_CLKSRC);
- RK_TIMER_SETCOUNT(TIMER_CLKSRC, 0xFFFFFFFF);
- RK_TIMER_ENABLE_FREE_RUNNING(TIMER_CLKSRC);
-
- cs->mult = MULT;
- if (clocksource_register(cs))
- printk(err, cs->name);
-}
-
-static DEFINE_CLOCK_DATA(cd);
-
-unsigned long long notrace sched_clock(void)
-{
- u32 cyc = ~RK_TIMER_READVALUE(TIMER_CLKSRC);
- return cyc_to_fixed_sched_clock(&cd, cyc, MASK, MULT, SHIFT);
-}
-
-static void notrace rk29_update_sched_clock(void)
-{
- u32 cyc = ~RK_TIMER_READVALUE(TIMER_CLKSRC);
- update_sched_clock(&cd, cyc, MASK);
-}
-
-static void __init rk29_sched_clock_init(void)
-{
- init_fixed_sched_clock(&cd, rk29_update_sched_clock,
- 32, 24000000, MULT, SHIFT);
-}
-
-static void __init rk29_timer_init(void)
-{
- rk29_timer_init_clocksource();
- rk29_timer_init_clockevent();
- rk29_sched_clock_init();
-}
-
-struct sys_timer rk29_timer = {
- .init = rk29_timer_init
-};
-
+++ /dev/null
-#include <linux/module.h>\r
-#include <linux/file.h>\r
-#include <linux/fs.h>\r
-#include <linux/miscdevice.h>\r
-#include <linux/uaccess.h>\r
-#include "verifyID.h"\r
-\r
-\r
-\r
-static int verifyid_open(struct inode *inode, struct file *file)\r
-{\r
- int ret;\r
- ret = generic_file_open(inode, file);\r
- if (unlikely(ret))\r
- return ret;\r
- return 0;\r
-}\r
-\r
-static int verifyid_release(struct inode *ignored, struct file *file)\r
-{\r
-\r
- return 0;\r
-}\r
-\r
-static int GetChipTag(void)\r
-{\r
- unsigned long i;\r
- unsigned long value; \r
- value = read_XDATA32(RK29_GPIO6_BASE+0x4);\r
- printk("read gpio6+4 = 0x%x\n",value);\r
- write_XDATA32((RK29_GPIO6_BASE+0x4), (read_XDATA32(RK29_GPIO6_BASE+0x4)&(~(0x7ul<<28)))); // portD 4:6 input\r
- value = read_XDATA32(RK29_GPIO6_BASE+0x50); \r
- printk("read gpio6+0x50 = 0x%x\n",value);\r
- value = (value>>28)&0x07; \r
- \r
- return value;\r
-}\r
-static long verifyid_ioctl(struct file *file, unsigned int cmd, unsigned long arg)\r
-{\r
- long ret = -ENOTTY;\r
-\r
- switch (cmd) {\r
- case VERIFYID_GETID:\r
- ret=GetChipTag();\r
- *((unsigned long *)arg) = 1;\r
- break;\r
- }\r
-\r
- return ret;\r
-}\r
-\r
-static ssize_t verifyid_read(struct file *file, char __user *buf,\r
- size_t len, loff_t *pos)\r
-{\r
- long ret = GetChipTag();\r
- char *kb = {0x11,0x22,0x33,0x44};\r
- if(ret>0)\r
- //*buf = 0xf8;\r
- copy_to_user(buf,kb,1);\r
- return ret;\r
-}\r
-\r
-static struct file_operations verifyid_fops = {\r
- .owner = THIS_MODULE,\r
- .open = verifyid_open,\r
- .read = verifyid_read,\r
- .release = verifyid_release,\r
- .unlocked_ioctl = verifyid_ioctl,\r
- .compat_ioctl = verifyid_ioctl,\r
-};\r
-\r
-static struct miscdevice verifyid_misc = {\r
- .minor = MISC_DYNAMIC_MINOR,\r
- .name = "verifyid",\r
- .fops = &verifyid_fops,\r
-};\r
-\r
-static int __init verifyid_init(void)\r
-{\r
- int ret;\r
- ret = misc_register(&verifyid_misc);\r
- if (unlikely(ret)) {\r
- printk(KERN_ERR "verifyid: failed to register misc device!\n");\r
- return ret;\r
- }\r
- printk(KERN_INFO "verifyid: initialized\n");\r
-\r
- return 0;\r
-}\r
-\r
-static void __exit verifyid_exit(void)\r
-{\r
- int ret;\r
-\r
- ret = misc_deregister(&verifyid_misc);\r
- if (unlikely(ret))\r
- printk(KERN_ERR "verifyid: failed to unregister misc device!\n");\r
-\r
- printk(KERN_INFO "verifyid: unloaded\n");\r
-}\r
-\r
-module_init(verifyid_init);\r
-module_exit(verifyid_exit);\r
-\r
-MODULE_LICENSE("GPL");\r
-\r
+++ /dev/null
-/*\r
- */\r
-\r
-#ifndef _LINUX_VERIFYID_H\r
-#define _LINUX_VERIFYID_H\r
-#include <mach/rk29_iomap.h>\r
-\r
-\r
-#define VERIFYID_GETID 0x29\r
-#define write_XDATA32(address, value) (*((unsigned long volatile*)(address)) = value)\r
-#define read_XDATA32(address) (*((unsigned long volatile*)(address)))\r
-\r
-#endif /* _LINUX_VERIFYID_H */\r
-\r
+++ /dev/null
-/* arch/arm/mach-rk29/vpu_mem.c\r
- *\r
- * Copyright (C) 2010 ROCKCHIP, Inc.\r
- * author: chenhengming chm@rock-chips.com\r
- *\r
- * This software is licensed under the terms of the GNU General Public\r
- * License version 2, as published by the Free Software Foundation, and\r
- * may be copied, distributed, and modified under those terms.\r
- *\r
- * This program is distributed in the hope that it will be useful,\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- * GNU General Public License for more details.\r
- *\r
- */\r
-\r
-#include <linux/miscdevice.h>\r
-#include <linux/platform_device.h>\r
-#include <linux/fs.h>\r
-#include <linux/file.h>\r
-#include <linux/mm.h>\r
-#include <linux/list.h>\r
-#include <linux/debugfs.h>\r
-#include <linux/mempolicy.h>\r
-#include <linux/sched.h>\r
-#include <linux/dma-mapping.h>\r
-#include <asm/io.h>\r
-#include <asm/uaccess.h>\r
-#include <asm/cacheflush.h>\r
-\r
-#include <mach/vpu_mem.h>\r
-\r
-#define VPU_MEM_MIN_ALLOC PAGE_SIZE\r
-#define VPU_MEM_IS_PAGE_ALIGNED(addr) (!((addr) & (~PAGE_MASK)))\r
-\r
-#define VPU_MEM_DEBUG 0\r
-#define VPU_MEM_DEBUG_MSGS 0\r
-\r
-#if VPU_MEM_DEBUG_MSGS\r
-#define DLOG(fmt,args...) \\r
- do { printk(KERN_INFO "[%s:%s:%d] "fmt, __FILE__, __func__, __LINE__, \\r
- ##args); } \\r
- while (0)\r
-#else\r
-#define DLOG(x...) do {} while (0)\r
-#endif\r
-\r
-/**\r
- * struct for process session which connect to vpu_mem\r
- *\r
- * @author ChenHengming (2011-4-11)\r
- */\r
-typedef struct vpu_mem_session {\r
- /* a list of memory region used posted by current process */\r
- struct list_head list_used;\r
- struct list_head list_post;\r
- /* a linked list of data so we can access them for debugging */\r
- struct list_head list_session;\r
- /* a linked list of memory pool on current session */\r
- struct list_head list_pool;\r
- /* process id of teh mapping process */\r
- pid_t pid;\r
-} vdm_session;\r
-\r
-/**\r
- * session memory pool info\r
- */\r
-typedef struct vpu_mem_pool_info {\r
- struct list_head session_link; /* link to session use for search */\r
- struct list_head list_used; /* a linked list for used memory in the pool */\r
- vdm_session *session;\r
- int count_current;\r
- int count_target;\r
- int pfn;\r
-} vdm_pool;\r
-\r
-/**\r
- * session memory pool config input\r
- */\r
-typedef struct vpu_mem_pool_config {\r
- int size;\r
- unsigned int count;\r
-} vdm_pool_config;\r
-\r
-/**\r
- * global region info\r
- */\r
-typedef struct vpu_mem_region_info {\r
- struct list_head index_list; /* link to index list use for search */\r
- int used;\r
- int post;\r
- int index;\r
- int pfn;\r
-} vdm_region;\r
-\r
-/**\r
- * struct for region information\r
- * this struct should be modified with bitmap lock\r
- */\r
-typedef struct vpu_mem_link_info {\r
- struct list_head session_link; /* link to vpu_mem_session list */\r
- struct list_head status_link; /* link to vdm_info.status list use for search */\r
- struct list_head pool_link; /* link to vpu_mem_session pool list for search */\r
- vdm_region *region;\r
- vdm_pool *pool;\r
- union {\r
- int post;\r
- int used;\r
- int count;\r
- } ref;\r
- int *ref_ptr;\r
- int index;\r
- int pfn;\r
-} vdm_link;\r
-\r
-/**\r
- * struct for global vpu memory info\r
- */\r
-typedef struct vpu_mem_info {\r
- struct miscdevice dev;\r
- /* physical start address of the remaped vpu_mem space */\r
- unsigned long base;\r
- /* vitual start address of the remaped vpu_mem space */\r
- unsigned char __iomem *vbase;\r
- /* total size of the vpu_mem space */\r
- unsigned long size;\r
- /* number of entries in the vpu_mem space */\r
- unsigned long num_entries;\r
- /* indicates maps of this region should be cached, if a mix of\r
- * cached and uncached is desired, set this and open the device with\r
- * O_SYNC to get an uncached region */\r
- unsigned cached;\r
- unsigned buffered;\r
- /*\r
- * vdm_session init only store the free region but use a vdm_session for convenience\r
- */\r
- vdm_session status;\r
- struct list_head list_index; /* sort by index */\r
- struct list_head list_free; /* free region list */\r
- struct list_head list_session; /* session list */\r
- struct rw_semaphore rw_sem;\r
-} vdm_info;\r
-\r
-static vdm_info vpu_mem;\r
-static int vpu_mem_count;\r
-static int vpu_mem_over = 0;\r
-\r
-#define vdm_used (vpu_mem.status.list_used)\r
-#define vdm_post (vpu_mem.status.list_post)\r
-#define vdm_index (vpu_mem.list_index)\r
-#define vdm_free (vpu_mem.list_free)\r
-#define vdm_proc (vpu_mem.list_session)\r
-#define vdm_rwsem (vpu_mem.rw_sem)\r
-#define is_free_region(x) ((0 == (x)->used) && (0 == (x)->post))\r
-\r
-/**\r
- * vpu memory info dump:\r
- * first dump global info, then dump each session info\r
- *\r
- * @author ChenHengming (2011-4-20)\r
- */\r
-static void dump_status(void)\r
-{\r
- vdm_link *link, *tmp_link;\r
- vdm_pool *pool, *tmp_pool;\r
- vdm_region *region, *tmp_region;\r
- vdm_session *session, *tmp_session;\r
-\r
- printk("vpu mem status dump :\n\n");\r
-\r
- // °´ index ´òÓ¡È«²¿ region\r
- printk("region:\n");\r
- list_for_each_entry_safe(region, tmp_region, &vdm_index, index_list) {\r
- printk(" idx %6d pfn %6d used %3d post %3d\n",\r
- region->index, region->pfn, region->used, region->post);\r
- }\r
- printk("free :\n");\r
- list_for_each_entry_safe(link, tmp_link, &vdm_free, status_link) {\r
- printk(" idx %6d pfn %6d ref %3d\n",\r
- link->index, link->pfn, link->ref.used);\r
- }\r
- printk("used :\n");\r
- list_for_each_entry_safe(link, tmp_link, &vdm_used, status_link) {\r
- printk(" idx %6d pfn %6d used %3d\n",\r
- link->index, link->pfn, link->ref.used);\r
- }\r
- printk("post :\n");\r
- list_for_each_entry_safe(link, tmp_link, &vdm_post, status_link) {\r
- printk(" idx %6d pfn %6d post %3d\n",\r
- link->index, link->pfn, link->ref.post);\r
- }\r
-\r
- // ´òÓ¡ vpu_mem_info ÖеÄÈ«²¿ session µÄ region Õ¼ÓÃÇé¿ö\r
- list_for_each_entry_safe(session, tmp_session, &vdm_proc, list_session) {\r
- printk("pid: %d\n", session->pid);\r
-\r
- list_for_each_entry_safe(pool, tmp_pool, &session->list_pool, session_link) {\r
- printk("pool: pfn %6d target %3d current %2d\n",\r
- pool->pfn, pool->count_current, pool->count_target);\r
- }\r
- list_for_each_entry_safe(link, tmp_link, &session->list_used, session_link) {\r
- printk("used: idx %6d pfn %6d used %3d\n",\r
- link->index, link->pfn, link->ref.used);\r
- }\r
- list_for_each_entry_safe(link, tmp_link, &session->list_post, session_link) {\r
- printk("post: idx %6d pfn %6d post %3d\n",\r
- link->index, link->pfn, link->ref.post);\r
- }\r
- }\r
-}\r
-\r
-/**\r
- * find used link in a session\r
- *\r
- * @author ChenHengming (2011-4-18)\r
- *\r
- * @param session\r
- * @param index\r
- *\r
- * @return vdm_link*\r
- */\r
-static vdm_link *find_used_link(vdm_session *session, int index)\r
-{\r
- vdm_link *pos, *n;\r
-\r
- list_for_each_entry_safe(pos, n, &session->list_used, session_link) {\r
- if (index == pos->index) {\r
- DLOG("found index %d ptr %p\n", index, pos);\r
- return pos;\r
- }\r
- }\r
-\r
- return NULL;\r
-}\r
-\r
-/**\r
- * find post link from vpu_mem's vdm_post list\r
- *\r
- * @author ChenHengming (2011-4-18)\r
- *\r
- * @param index\r
- *\r
- * @return vdm_link*\r
- */\r
-static vdm_link *find_post_link(int index)\r
-{\r
- vdm_link *pos, *n;\r
-\r
- list_for_each_entry_safe(pos, n, &vdm_post, status_link) {\r
- if (index == pos->index) {\r
- return pos;\r
- }\r
- }\r
-\r
- return NULL;\r
-}\r
-\r
-/**\r
- * find free link from vpu_mem's vdm_free list\r
- *\r
- * @author Administrator (2011-4-19)\r
- *\r
- * @param index\r
- *\r
- * @return vdm_link*\r
- */\r
-static vdm_link *find_free_link(int index)\r
-{\r
- vdm_link *pos, *n;\r
-\r
- list_for_each_entry_safe(pos, n, &vdm_free, status_link) {\r
- if (index == pos->index) {\r
- return pos;\r
- }\r
- }\r
-\r
- return NULL;\r
-}\r
-\r
-static vdm_pool *find_pool_by_pfn(vdm_session *session, unsigned int pfn)\r
-{\r
- vdm_pool *pos, *n;\r
-\r
- list_for_each_entry_safe(pos, n, &session->list_pool, session_link) {\r
- if (pfn == pos->pfn) {\r
- return pos;\r
- }\r
- }\r
-\r
- return NULL;\r
-}\r
-\r
-static void vpu_mem_pool_add_link(vdm_pool *pool, vdm_link *link)\r
-{\r
- link->pool = pool;\r
- list_add_tail(&link->pool_link, &pool->list_used);\r
- pool->count_current++;\r
-}\r
-\r
-static void vpu_mem_pool_del_link(vdm_link *link)\r
-{\r
- vdm_pool *pool = link->pool;\r
- link->pool = NULL;\r
- list_del_init(&link->pool_link);\r
- pool->count_current--;\r
-}\r
-\r
-static void link_ref_inc(vdm_link *link)\r
-{\r
- link->ref.count++;\r
- if (link->ref_ptr) {\r
- *link->ref_ptr += 1;\r
- }\r
-}\r
-\r
-static void link_ref_dec(vdm_link *link)\r
-{\r
- link->ref.count--;\r
- if (link->ref_ptr) {\r
- *link->ref_ptr -= 1;\r
- }\r
-}\r
-\r
-/**\r
- * insert a region into the index list for search\r
- *\r
- * @author ChenHengming (2011-4-18)\r
- *\r
- * @param region\r
- *\r
- * @return int\r
- */\r
-static int _insert_region_index(vdm_region *region)\r
-{\r
- int index = region->index;\r
- int last = -1;\r
- int next;\r
- vdm_region *tmp, *n;\r
-\r
- if (list_empty(&vdm_index)) {\r
- DLOG("index list is empty, insert first region\n");\r
- list_add_tail(®ion->index_list, &vdm_index);\r
- return 0;\r
- }\r
-\r
- list_for_each_entry_safe(tmp, n, &vdm_index, index_list) {\r
- next = tmp->index;\r
- DLOG("insert index %d pfn %d last %d next %d ptr %p\n", index, region->pfn, last, next, tmp);\r
- if ((last < index) && (index < next)) {\r
- DLOG("Done\n");\r
- list_add_tail(®ion->index_list, &tmp->index_list);\r
- return 0;\r
- }\r
- last = next;\r
- }\r
-\r
- printk(KERN_ERR "_insert_region_by_index %d fail!\n", index);\r
- dump_status();\r
- return -1;\r
-}\r
-\r
-/**\r
- * insert a link into vdm_free list, indexed by vdm_link->index\r
- *\r
- * @author ChenHengming (2011-4-20)\r
- *\r
- * @param link\r
- */\r
-static void _insert_link_status_free(vdm_link *link)\r
-{\r
- int index = link->index;\r
- int last = -1;\r
- int next;\r
- vdm_link *tmp, *n;\r
-\r
- if (list_empty(&vdm_free)) {\r
- DLOG("free list is empty, list_add_tail first region\n");\r
- list_add_tail(&link->status_link, &vdm_free);\r
- return ;\r
- }\r
-\r
- list_for_each_entry_safe(tmp, n, &vdm_free, status_link) {\r
- next = tmp->index;\r
- if ((last < index) && (index < next)) {\r
- DLOG("list_add_tail index %d pfn %d last %d next %d ptr %p\n", index, link->pfn, last, next, tmp);\r
- list_add_tail(&link->status_link, &tmp->status_link);\r
- return ;\r
- }\r
- last = next;\r
- }\r
- list_add_tail(&link->status_link, &tmp->status_link);\r
- DLOG("list_add index %d pfn %d last %d ptr %p\n", index, link->pfn, last, tmp);\r
- return ;\r
-}\r
-\r
-static void _insert_link_status_post(vdm_link *link)\r
-{\r
- int index = link->index;\r
- int last = -1;\r
- int next;\r
- vdm_link *tmp, *n;\r
-\r
- if (list_empty(&vdm_post)) {\r
- DLOG("post list is empty, list_add_tail first region\n");\r
- list_add_tail(&link->status_link, &vdm_post);\r
- return ;\r
- }\r
-\r
- list_for_each_entry_safe(tmp, n, &vdm_post, status_link) {\r
- next = tmp->index;\r
- if ((last < index) && (index < next)) {\r
- DLOG("list_add_tail index %d pfn %d last %d next %d ptr %p\n", index, link->pfn, last, next, tmp);\r
- list_add_tail(&link->status_link, &tmp->status_link);\r
- return ;\r
- }\r
- last = next;\r
- }\r
-\r
- list_add_tail(&link->status_link, &tmp->status_link);\r
- DLOG("list_add index %d pfn %d last %d ptr %p\n", index, link->pfn, last, tmp);\r
- return ;\r
-}\r
-\r
-static void _insert_link_status_used(vdm_link *link)\r
-{\r
- int index = link->index;\r
- int last = -1;\r
- int next;\r
- vdm_link *tmp, *n;\r
-\r
- if (list_empty(&vdm_used)) {\r
- DLOG("used list is empty, list_add_tail first region\n");\r
- list_add_tail(&link->status_link, &vdm_used);\r
- return ;\r
- }\r
-\r
- list_for_each_entry_safe(tmp, n, &vdm_used, status_link) {\r
- next = tmp->index;\r
- if ((last < index) && (index < next)) {\r
- DLOG("list_add_tail index %d pfn %d last %d next %d ptr %p\n", index, link->pfn, last, next, tmp);\r
- list_add_tail(&link->status_link, &tmp->status_link);\r
- return ;\r
- }\r
- last = next;\r
- }\r
-\r
- list_add_tail(&link->status_link, &tmp->status_link);\r
- DLOG("list_add index %d pfn %d last %d ptr %p\n", index, link->pfn, last, tmp);\r
- return ;\r
-}\r
-\r
-static void _insert_link_session_used(vdm_link *link, vdm_session *session)\r
-{\r
- int index = link->index;\r
- int last = -1;\r
- int next;\r
- vdm_link *tmp, *n;\r
-\r
- if (list_empty(&session->list_used)) {\r
- DLOG("session used list is empty, list_add_tail first region\n");\r
- list_add_tail(&link->session_link, &session->list_used);\r
- return ;\r
- }\r
-\r
- list_for_each_entry_safe(tmp, n, &session->list_used, session_link) {\r
- next = tmp->index;\r
- if ((last < index) && (index < next)) {\r
- list_add_tail(&link->session_link, &tmp->session_link);\r
- DLOG("list_add_tail index %d pfn %d last %d next %d ptr %p\n", index, link->pfn, last, next, tmp);\r
- return ;\r
- }\r
- last = next;\r
- }\r
-\r
- list_add_tail(&link->session_link, &tmp->session_link);\r
- DLOG("list_add index %d pfn %d last %d ptr %p\n", index, link->pfn, last, tmp);\r
- return ;\r
-}\r
-\r
-static void _insert_link_session_post(vdm_link *link, vdm_session *session)\r
-{\r
- int index = link->index;\r
- int last = -1;\r
- int next;\r
- vdm_link *tmp, *n;\r
-\r
- if (list_empty(&session->list_post)) {\r
- DLOG("session post list is empty, list_add_tail first region\n");\r
- list_add_tail(&link->session_link, &session->list_post);\r
- return ;\r
- }\r
-\r
- list_for_each_entry_safe(tmp, n, &session->list_post, session_link) {\r
- next = tmp->index;\r
- if ((last < index) && (index < next)) {\r
- list_add_tail(&link->session_link, &tmp->session_link);\r
- DLOG("list_add_tail index %d pfn %d last %d next %d ptr %p\n", index, link->pfn, last, next, tmp);\r
- return ;\r
- }\r
- last = next;\r
- }\r
-\r
- list_add_tail(&link->session_link, &tmp->session_link);\r
- DLOG("list_add index %d pfn %d last %d ptr %p\n", index, link->pfn, last, tmp);\r
- return ;\r
-}\r
-\r
-static void _remove_free_region(vdm_region *region)\r
-{\r
- list_del_init(®ion->index_list);\r
- kfree(region);\r
-}\r
-\r
-static void _remove_free_link(vdm_link *link)\r
-{\r
- list_del_init(&link->session_link);\r
- list_del_init(&link->status_link);\r
- kfree(link);\r
-}\r
-\r
-static void _merge_two_region(vdm_region *dst, vdm_region *src)\r
-{\r
- vdm_link *dst_link = find_free_link(dst->index);\r
- vdm_link *src_link = find_free_link(src->index);\r
- dst->pfn += src->pfn;\r
- dst_link->pfn += src_link->pfn;\r
- _remove_free_link(src_link);\r
- _remove_free_region(src);\r
-}\r
-\r
-static void merge_free_region_and_link(vdm_region *region)\r
-{\r
- if (region->used || region->post) {\r
- printk(KERN_ALERT "try to merge unfree region!\n");\r
- return ;\r
- } else {\r
- vdm_region *neighbor;\r
- struct list_head *tmp = region->index_list.next;\r
- if (tmp != &vdm_index) {\r
- neighbor = (vdm_region *)list_entry(tmp, vdm_region, index_list);\r
- if (is_free_region(neighbor)) {\r
- DLOG("merge next\n");\r
- _merge_two_region(region, neighbor);\r
- }\r
- }\r
- tmp = region->index_list.prev;\r
- if (tmp != &vdm_index) {\r
- neighbor = (vdm_region *)list_entry(tmp, vdm_region, index_list);\r
- if (is_free_region(neighbor)) {\r
- DLOG("merge prev\n");\r
- _merge_two_region(neighbor, region);\r
- }\r
- }\r
- }\r
-}\r
-\r
-static void put_free_link(vdm_link *link)\r
-{\r
- if (link->pool) {\r
- vpu_mem_pool_del_link(link);\r
- }\r
- list_del_init(&link->session_link);\r
- list_del_init(&link->status_link);\r
- _insert_link_status_free(link);\r
-}\r
-\r
-static void put_used_link(vdm_link *link, vdm_session *session)\r
-{\r
- list_del_init(&link->session_link);\r
- list_del_init(&link->status_link);\r
- _insert_link_status_used(link);\r
- _insert_link_session_used(link, session);\r
- if (NULL == link->pool) {\r
- vdm_pool *pool = find_pool_by_pfn(session, link->pfn);\r
- if (pool) {\r
- vpu_mem_pool_add_link(pool, link);\r
- }\r
- }\r
-}\r
-\r
-static void put_post_link(vdm_link *link, vdm_session *session)\r
-{\r
- list_del_init(&link->session_link);\r
- list_del_init(&link->status_link);\r
- _insert_link_status_post(link);\r
- _insert_link_session_post(link, session);\r
- if (NULL == link->pool) {\r
- vdm_pool *pool = find_pool_by_pfn(session, link->pfn);\r
- if (pool) {\r
- vpu_mem_pool_add_link(pool, link);\r
- }\r
- }\r
-}\r
-\r
-/**\r
- * Create a link and a region by index and pfn at a same time,\r
- * and connect the link with the region\r
- *\r
- * @author ChenHengming (2011-4-20)\r
- *\r
- * @param index\r
- * @param pfn\r
- *\r
- * @return vdm_link*\r
- */\r
-static vdm_link *new_link_by_index(int index, int pfn)\r
-{\r
- vdm_region *region = (vdm_region *)kmalloc(sizeof(vdm_region), GFP_KERNEL);\r
- vdm_link *link = (vdm_link *)kmalloc(sizeof(vdm_link ), GFP_KERNEL);\r
-\r
- if ((NULL == region) || (NULL == link)) {\r
- printk(KERN_ALERT "can not kmalloc vdm_region and vdm_link in %s", __FUNCTION__);\r
- if (region) {\r
- kfree(region);\r
- }\r
- if (link) {\r
- kfree(link);\r
- }\r
- return NULL;\r
- }\r
-\r
- region->post = 0;\r
- region->used = 0;\r
- region->index = index;\r
- region->pfn = pfn;\r
-\r
- INIT_LIST_HEAD(®ion->index_list);\r
-\r
- link->ref.count = 0;\r
- link->ref_ptr = NULL;\r
- link->region = region;\r
- link->index = region->index;\r
- link->pfn = region->pfn;\r
- INIT_LIST_HEAD(&link->session_link);\r
- INIT_LIST_HEAD(&link->status_link);\r
- INIT_LIST_HEAD(&link->pool_link);\r
- link->pool = NULL;\r
-\r
- return link;\r
-}\r
-\r
-/**\r
- * Create a link from a already exist region and connect to the\r
- * region\r
- *\r
- * @author ChenHengming (2011-4-20)\r
- *\r
- * @param region\r
- *\r
- * @return vdm_link*\r
- */\r
-static vdm_link *new_link_by_region(vdm_region *region)\r
-{\r
- vdm_link *link = (vdm_link *)kmalloc(sizeof(vdm_link), GFP_KERNEL);\r
- if (NULL == link) {\r
- printk(KERN_ALERT "can not kmalloc vdm_region and vdm_link in %s", __FUNCTION__);\r
- return NULL;\r
- }\r
-\r
- link->ref.count = 0;\r
- link->ref_ptr = NULL;\r
- link->region = region;\r
- link->index = region->index;\r
- link->pfn = region->pfn;\r
- INIT_LIST_HEAD(&link->session_link);\r
- INIT_LIST_HEAD(&link->status_link);\r
- INIT_LIST_HEAD(&link->pool_link);\r
- link->pool = NULL;\r
-\r
- return link;\r
-}\r
-\r
-/**\r
- * Delete a link completely\r
- *\r
- * @author ChenHengming (2011-4-20)\r
- *\r
- * @param link\r
- */\r
-static void link_del(vdm_link *link)\r
-{\r
- if (link->pool) {\r
- vpu_mem_pool_del_link(link);\r
- }\r
- list_del_init(&link->session_link);\r
- list_del_init(&link->status_link);\r
- if (is_free_region(link->region) && NULL == find_free_link(link->index)) {\r
- put_free_link(link);\r
- merge_free_region_and_link(link->region);\r
- } else {\r
- kfree(link);\r
- }\r
-}\r
-\r
-/**\r
- * Called by malloc, check whether a free link can by used for a\r
- * len of pfn, if can then put a used link to status link\r
- *\r
- * @author ChenHengming (2011-4-20)\r
- *\r
- * @param link\r
- * @param session\r
- * @param pfn\r
- *\r
- * @return vdm_link*\r
- */\r
-static vdm_link *get_used_link_from_free_link(vdm_link *link, vdm_session *session, int pfn)\r
-{\r
- if (pfn > link->pfn) {\r
- return NULL;\r
- }\r
- if (pfn == link->pfn) {\r
- DLOG("pfn == link->pfn %d\n", pfn);\r
- link->ref.used = 1;\r
- link->region->used = 1;\r
- link->ref_ptr = &link->region->used;\r
- put_used_link(link, session);\r
- return link;\r
- } else {\r
- vdm_link *used = new_link_by_index(link->index, pfn);\r
- if (NULL == used)\r
- return NULL;\r
-\r
- link->index += pfn;\r
- link->pfn -= pfn;\r
- link->region->index += pfn;\r
- link->region->pfn -= pfn;\r
- used->ref.used = 1;\r
- used->region->used = 1;\r
- used->ref_ptr = &used->region->used;\r
-\r
- DLOG("used: index %d pfn %d ptr %p\n", used->index, used->pfn, used->region);\r
- if (_insert_region_index(used->region)) {\r
- printk(KERN_ALERT "fail to insert allocated region index %d pfn %d\n", used->index, used->pfn);\r
- link_del(used);\r
- link->index -= pfn;\r
- link->pfn += pfn;\r
- link->region->index -= pfn;\r
- link->region->pfn += pfn;\r
- _remove_free_region(used->region);\r
- _remove_free_link(used);\r
- return NULL;\r
- }\r
- put_used_link(used, session);\r
- return used;\r
- }\r
-}\r
-\r
-int is_vpu_mem_file(struct file *file)\r
-{\r
- if (unlikely(!file || !file->f_dentry || !file->f_dentry->d_inode))\r
- return 0;\r
- if (unlikely(file->f_dentry->d_inode->i_rdev !=\r
- MKDEV(MISC_MAJOR, vpu_mem.dev.minor)))\r
- return 0;\r
- return 1;\r
-}\r
-\r
-static long vpu_mem_allocate(struct file *file, unsigned int len)\r
-{\r
- vdm_link *free, *n;\r
- unsigned int pfn = (len + VPU_MEM_MIN_ALLOC - 1)/VPU_MEM_MIN_ALLOC;\r
- vdm_session *session = (vdm_session *)file->private_data;\r
-\r
- if (!is_vpu_mem_file(file)) {\r
- printk(KERN_INFO "allocate vpu_mem session from invalid file\n");\r
- return -ENODEV;\r
- }\r
-\r
- list_for_each_entry_safe(free, n, &vdm_free, status_link) {\r
- /* find match free buffer use it first */\r
- vdm_link *used = get_used_link_from_free_link(free, session, pfn);\r
- DLOG("search free buffer at index %d pfn %d for len %d\n", free->index, free->pfn, pfn);\r
- if (NULL == used) {\r
- continue;\r
- } else {\r
- DLOG("found buffer at index %d pfn %d for ptr %p\n", used->index, used->pfn, used);\r
- return used->index;\r
- }\r
- }\r
-\r
- if (!vpu_mem_over) {\r
- printk(KERN_INFO "vpu_mem: no space left to allocate!\n");\r
- dump_status();\r
- vpu_mem_over = 1;\r
- }\r
- return -1;\r
-}\r
-\r
-static int vpu_mem_free(struct file *file, int index)\r
-{\r
- vdm_session *session = (vdm_session *)file->private_data;\r
-\r
- if (!is_vpu_mem_file(file)) {\r
- printk(KERN_INFO "free vpu_mem session from invalid file.\n");\r
- return -ENODEV;\r
- }\r
-\r
- DLOG("searching for index %d\n", index);\r
- {\r
- vdm_link *link = find_used_link(session, index);\r
- if (NULL == link) {\r
- DLOG("no link of index %d searched\n", index);\r
- return -1;\r
- }\r
- link_ref_dec(link);\r
- if (0 == link->ref.used) {\r
- link_del(link);\r
- }\r
- }\r
- return 0;\r
-}\r
-\r
-static int vpu_mem_duplicate(struct file *file, int index)\r
-{\r
- vdm_session *session = (vdm_session *)file->private_data;\r
- /* caller should hold the write lock on vpu_mem_sem! */\r
- if (!is_vpu_mem_file(file)) {\r
- printk(KERN_INFO "duplicate vpu_mem session from invalid file.\n");\r
- return -ENODEV;\r
- }\r
-\r
- DLOG("duplicate index %d\n", index);\r
- {\r
- vdm_link *post = find_post_link(index);\r
- if (NULL == post) {\r
- vdm_link *used = find_used_link(session, index);\r
- if (NULL == used) {\r
- printk(KERN_ERR "try to duplicate unknown index %d\n", index);\r
- dump_status();\r
- return -1;\r
- }\r
- post = new_link_by_region(used->region);\r
- post->ref_ptr = &post->region->post;\r
- link_ref_inc(post);\r
- put_post_link(post, session);\r
- } else {\r
- DLOG("duplicate posted index %d\n", index);\r
- link_ref_inc(post);\r
- }\r
- }\r
-\r
- return 0;\r
-}\r
-\r
-static int vpu_mem_link(struct file *file, int index)\r
-{\r
- vdm_session *session = (vdm_session *)file->private_data;\r
-\r
- if (!is_vpu_mem_file(file)) {\r
- printk(KERN_INFO "link vpu_mem session from invalid file.\n");\r
- return -ENODEV;\r
- }\r
-\r
- DLOG("link index %d\n", index);\r
- {\r
- vdm_link *post = find_post_link(index);\r
- if (NULL == post) {\r
- printk(KERN_ERR "try to link unknown index %d\n", index);\r
- dump_status();\r
- return -1;\r
- } else {\r
- vdm_link *used = find_used_link(session, index);\r
- link_ref_dec(post);\r
-\r
- if (used) {\r
- if (0 == post->ref.post) {\r
- link_del(post);\r
- post = NULL;\r
- }\r
- } else {\r
- if (post->ref.post) {\r
- used = new_link_by_region(post->region);\r
- } else {\r
- used = post;\r
- post = NULL;\r
- }\r
- used->ref_ptr = &used->region->used;\r
- put_used_link(used, session);\r
- }\r
- link_ref_inc(used);\r
- }\r
- }\r
-\r
- return 0;\r
-}\r
-\r
-static int vpu_mem_pool_add(vdm_session *session, unsigned int pfn, unsigned int count)\r
-{\r
- vdm_link *link, *n;\r
- vdm_pool *pool = kmalloc(sizeof(vdm_pool), GFP_KERNEL);\r
- DLOG("vpu_mem_pool_add %p pfn %d count %d\n", pool, pfn, count);\r
- if (NULL == pool) {\r
- printk(KERN_ALERT "vpu_mem: unable to allocate memory for vpu_mem pool.");\r
- return -1;\r
- }\r
- INIT_LIST_HEAD(&pool->session_link);\r
- INIT_LIST_HEAD(&pool->list_used);\r
- pool->session = session;\r
- pool->pfn = pfn;\r
- pool->count_target = count;\r
- pool->count_current = 0;\r
-\r
- list_for_each_entry_safe(link, n, &session->list_used, session_link) {\r
- if (pfn == link->pfn && NULL == link->pool) {\r
- vpu_mem_pool_add_link(pool, link);\r
- }\r
- }\r
-\r
- list_add_tail(&pool->session_link, &session->list_pool);\r
-\r
- return 0;\r
-}\r
-\r
-static void vpu_mem_pool_del(vdm_pool *pool)\r
-{\r
- vdm_link *link, *n;\r
- DLOG("vpu_mem_pool_del %p\n", pool);\r
- list_for_each_entry_safe(link, n, &pool->list_used, pool_link) {\r
- vpu_mem_pool_del_link(link);\r
- }\r
- if (pool->count_current) {\r
- printk(KERN_ALERT "vpu_mem pool deleted by still %d link left.\n", pool->count_current);\r
- }\r
- list_del_init(&pool->session_link);\r
- pool->session = NULL;\r
- kfree(pool);\r
- return ;\r
-}\r
-\r
-static int vpu_mem_pool_set(struct file *file, unsigned int pfn, unsigned int count)\r
-{\r
- int ret = 0;\r
- vdm_session *session = (vdm_session *)file->private_data;\r
- vdm_pool *pool = find_pool_by_pfn(session, pfn);\r
- if (NULL == pool) {\r
- // no pool build pool first\r
- ret = vpu_mem_pool_add(session, pfn, count);\r
- } else {\r
- pool->count_target += count;\r
- }\r
- return ret;\r
-}\r
-\r
-static int vpu_mem_pool_unset(struct file *file, unsigned int pfn, unsigned int count)\r
-{\r
- int ret = 0;\r
- vdm_session *session = (vdm_session *)file->private_data;\r
- vdm_pool *pool = find_pool_by_pfn(session, pfn);\r
- if (pool) {\r
- pool->count_target -= count;\r
- if (pool->count_target <= 0) {\r
- if (pool->count_target) {\r
- printk(KERN_ALERT "vpu_mem pool unpaired set and unset with %d differ.", pool->count_target);\r
- }\r
- vpu_mem_pool_del(pool);\r
- }\r
- }\r
- return ret;\r
-}\r
-\r
-static int vpu_mem_pool_check(struct file *file, unsigned int pfn)\r
-{\r
- int ret = 0;\r
- vdm_session *session = (vdm_session *)file->private_data;\r
- vdm_pool *pool = find_pool_by_pfn(session, pfn);\r
- if (pool) {\r
- if (pool->count_current >= pool->count_target) {\r
- ret = 1;\r
- }\r
- DLOG("vpu_mem_pool_check pfn %u current %d target %d ret %d\n", pfn, pool->count_current, pool->count_target, ret);\r
- }\r
- return ret;\r
-}\r
-\r
-void vpu_mem_cache_opt(struct file *file, long index, unsigned int cmd)\r
-{\r
- vdm_session *session = (vdm_session *)file->private_data;\r
- void *start, *end;\r
-\r
- if (!is_vpu_mem_file(file)) {\r
- return;\r
- }\r
-\r
- if (!vpu_mem.cached || file->f_flags & O_SYNC)\r
- return;\r
-\r
- down_read(&vdm_rwsem);\r
- do {\r
- vdm_link *link = find_used_link(session, index);\r
- if (NULL == link) {\r
- pr_err("vpu_mem_cache_opt on non-exsist index %ld\n", index);\r
- break;\r
- }\r
- start = vpu_mem.vbase + index * VPU_MEM_MIN_ALLOC;\r
- end = start + link->pfn * VPU_MEM_MIN_ALLOC;;\r
- switch (cmd) {\r
- case VPU_MEM_CACHE_FLUSH : {\r
- dmac_flush_range(start, end);\r
- break;\r
- }\r
- case VPU_MEM_CACHE_CLEAN : {\r
- dmac_clean_range(start, end);\r
- break;\r
- }\r
- case VPU_MEM_CACHE_INVALID : {\r
- dmac_inv_range(start, end);\r
- break;\r
- }\r
- default :\r
- break;\r
- }\r
- } while (0);\r
- up_read(&vdm_rwsem);\r
-}\r
-\r
-static pgprot_t vpu_mem_phys_mem_access_prot(struct file *file, pgprot_t vma_prot)\r
-{\r
-#ifdef pgprot_noncached\r
- if (vpu_mem.cached == 0 || file->f_flags & O_SYNC)\r
- return pgprot_noncached(vma_prot);\r
-#endif\r
-#ifdef pgprot_ext_buffered\r
- else if (vpu_mem.buffered)\r
- return pgprot_ext_buffered(vma_prot);\r
-#endif\r
- return vma_prot;\r
-}\r
-\r
-static int vpu_mem_map_pfn_range(struct vm_area_struct *vma, unsigned long len)\r
-{\r
- DLOG("map len %lx\n", len);\r
- BUG_ON(!VPU_MEM_IS_PAGE_ALIGNED(vma->vm_start));\r
- BUG_ON(!VPU_MEM_IS_PAGE_ALIGNED(vma->vm_end));\r
- BUG_ON(!VPU_MEM_IS_PAGE_ALIGNED(len));\r
- if (io_remap_pfn_range(vma, vma->vm_start,\r
- vpu_mem.base >> PAGE_SHIFT,\r
- len, vma->vm_page_prot)) {\r
- return -EAGAIN;\r
- }\r
- return 0;\r
-}\r
-\r
-static int vpu_mem_open(struct inode *inode, struct file *file)\r
-{\r
- vdm_session *session;\r
- int ret = 0;\r
-\r
- DLOG("current %u file %p(%d)\n", current->pid, file, (int)file_count(file));\r
- /* setup file->private_data to indicate its unmapped */\r
- /* you can only open a vpu_mem device one time */\r
- if (file->private_data != NULL && file->private_data != &vpu_mem.dev)\r
- return -1;\r
- session = kmalloc(sizeof(vdm_session), GFP_KERNEL);\r
- if (!session) {\r
- printk(KERN_ALERT "vpu_mem: unable to allocate memory for vpu_mem metadata.");\r
- return -1;\r
- }\r
- session->pid = current->pid;\r
- INIT_LIST_HEAD(&session->list_post);\r
- INIT_LIST_HEAD(&session->list_used);\r
- INIT_LIST_HEAD(&session->list_pool);\r
-\r
- file->private_data = session;\r
-\r
- down_write(&vdm_rwsem);\r
- list_add_tail(&session->list_session, &vdm_proc);\r
- up_write(&vdm_rwsem);\r
- return ret;\r
-}\r
-\r
-static int vpu_mem_mmap(struct file *file, struct vm_area_struct *vma)\r
-{\r
- vdm_session *session;\r
- unsigned long vma_size = vma->vm_end - vma->vm_start;\r
- int ret = 0;\r
-\r
- if (vma->vm_pgoff || !VPU_MEM_IS_PAGE_ALIGNED(vma_size)) {\r
- printk(KERN_ALERT "vpu_mem: mmaps must be at offset zero, aligned"\r
- " and a multiple of pages_size.\n");\r
- return -EINVAL;\r
- }\r
-\r
- session = (vdm_session *)file->private_data;\r
-\r
- /* assert: vma_size must be the total size of the vpu_mem */\r
- if (vpu_mem.size != vma_size) {\r
- printk(KERN_WARNING "vpu_mem: mmap size [%lu] does not match"\r
- "size of backing region [%lu].\n", vma_size, vpu_mem.size);\r
- ret = -EINVAL;\r
- goto error;\r
- }\r
-\r
- vma->vm_pgoff = vpu_mem.base >> PAGE_SHIFT;\r
- vma->vm_page_prot = vpu_mem_phys_mem_access_prot(file, vma->vm_page_prot);\r
-\r
- if (vpu_mem_map_pfn_range(vma, vma_size)) {\r
- printk(KERN_INFO "vpu_mem: mmap failed in kernel!\n");\r
- ret = -EAGAIN;\r
- goto error;\r
- }\r
-\r
- session->pid = current->pid;\r
-\r
-error:\r
- return ret;\r
-}\r
-\r
-static int vpu_mem_release(struct inode *inode, struct file *file)\r
-{\r
- vdm_session *session = (vdm_session *)file->private_data;\r
-\r
- down_write(&vdm_rwsem);\r
- {\r
- vdm_link *link, *tmp_link;\r
- vdm_pool *pool, *tmp_pool;\r
- //unsigned long flags = current->flags;\r
- //printk("current->flags: %lx\n", flags);\r
- list_del(&session->list_session);\r
- file->private_data = NULL;\r
-\r
- list_for_each_entry_safe(pool, tmp_pool, &session->list_pool, session_link) {\r
- vpu_mem_pool_del(pool);\r
- }\r
-\r
- list_for_each_entry_safe(link, tmp_link, &session->list_post, session_link) {\r
- do {\r
- link_ref_dec(link);\r
- } while (link->ref.post);\r
- link_del(link);\r
- }\r
- list_for_each_entry_safe(link, tmp_link, &session->list_used, session_link) {\r
- do {\r
- link_ref_dec(link);\r
- } while (link->ref.used);\r
- link_del(link);\r
- }\r
- }\r
- up_write(&vdm_rwsem);\r
- kfree(session);\r
-\r
- return 0;\r
-}\r
-\r
-static long vpu_mem_ioctl(struct file *file, unsigned int cmd, unsigned long arg)\r
-{\r
- long index, ret = 0;\r
-\r
- switch (cmd) {\r
- case VPU_MEM_GET_PHYS: {\r
- DLOG("get_phys\n");\r
- printk(KERN_INFO "vpu_mem: request for physical address of vpu_mem region "\r
- "from process %d.\n", current->pid);\r
- if (copy_to_user((void __user *)arg, &vpu_mem.base, sizeof(vpu_mem.base)))\r
- return -EFAULT;\r
- } break;\r
- case VPU_MEM_GET_TOTAL_SIZE: {\r
- DLOG("get total size\n");\r
- if (copy_to_user((void __user *)arg, &vpu_mem.size, sizeof(vpu_mem.size)))\r
- return -EFAULT;\r
- } break;\r
- case VPU_MEM_ALLOCATE: {\r
- unsigned int size;\r
- DLOG("allocate\n");\r
- if (copy_from_user(&size, (void __user *)arg, sizeof(size)))\r
- return -EFAULT;\r
- down_write(&vdm_rwsem);\r
- ret = vpu_mem_allocate(file, size);\r
- up_write(&vdm_rwsem);\r
- DLOG("allocate at index %ld\n", ret);\r
- } break;\r
- case VPU_MEM_FREE: {\r
- DLOG("mem free\n");\r
- if (copy_from_user(&index, (void __user *)arg, sizeof(index)))\r
- return -EFAULT;\r
- if (index >= vpu_mem.size)\r
- return -EACCES;\r
- down_write(&vdm_rwsem);\r
- ret = vpu_mem_free(file, index);\r
- up_write(&vdm_rwsem);\r
- } break;\r
-\r
- case VPU_MEM_CACHE_FLUSH:\r
- case VPU_MEM_CACHE_CLEAN:\r
- case VPU_MEM_CACHE_INVALID: {\r
- DLOG("flush\n");\r
- if (copy_from_user(&index, (void __user *)arg, sizeof(index)))\r
- return -EFAULT;\r
- if (index < 0)\r
- return -EINVAL;\r
- vpu_mem_cache_opt(file, index, cmd);\r
- } break;\r
- case VPU_MEM_DUPLICATE: {\r
- DLOG("duplicate\n");\r
- if (copy_from_user(&index, (void __user *)arg, sizeof(index)))\r
- return -EFAULT;\r
- down_write(&vdm_rwsem);\r
- ret = vpu_mem_duplicate(file, index);\r
- up_write(&vdm_rwsem);\r
- } break;\r
-\r
- case VPU_MEM_LINK: {\r
- DLOG("link\n");\r
- if (copy_from_user(&index, (void __user *)arg, sizeof(index)))\r
- return -EFAULT;\r
- down_write(&vdm_rwsem);\r
- ret = vpu_mem_link(file, index);\r
- up_write(&vdm_rwsem);\r
- } break;\r
-\r
- case VPU_MEM_POOL_SET: {\r
- struct vpu_mem_pool_config config;\r
- DLOG("pool set\n");\r
- if (copy_from_user(&config, (void __user *)arg, sizeof(config)))\r
- return -EFAULT;\r
- config.size = (config.size + VPU_MEM_MIN_ALLOC - 1)/VPU_MEM_MIN_ALLOC;\r
- down_write(&vdm_rwsem);\r
- ret = vpu_mem_pool_set(file, config.size, config.count);\r
- up_write(&vdm_rwsem);\r
- } break;\r
-\r
- case VPU_MEM_POOL_UNSET: {\r
- struct vpu_mem_pool_config config;\r
- DLOG("pool unset\n");\r
- if (copy_from_user(&config, (void __user *)arg, sizeof(config)))\r
- return -EFAULT;\r
- config.size = (config.size + VPU_MEM_MIN_ALLOC - 1)/VPU_MEM_MIN_ALLOC;\r
- down_write(&vdm_rwsem);\r
- ret = vpu_mem_pool_unset(file, config.size, config.count);\r
- up_write(&vdm_rwsem);\r
- } break;\r
-\r
- case VPU_MEM_POOL_CHECK: {\r
- int pfn;\r
- if (copy_from_user(&pfn, (void __user *)arg, sizeof(int)))\r
- return -EFAULT;\r
- pfn = (pfn + VPU_MEM_MIN_ALLOC - 1)/VPU_MEM_MIN_ALLOC;\r
- DLOG("pool check\n");\r
- down_read(&vdm_rwsem);\r
- ret = vpu_mem_pool_check(file, pfn);\r
- up_read(&vdm_rwsem);\r
- } break;\r
-\r
- default:\r
- return -EINVAL;\r
- }\r
- return ret;\r
-}\r
-\r
-struct file_operations vpu_mem_fops = {\r
- .open = vpu_mem_open,\r
- .mmap = vpu_mem_mmap,\r
- .unlocked_ioctl = vpu_mem_ioctl,\r
- .release = vpu_mem_release,\r
-};\r
-\r
-#if VPU_MEM_DEBUG\r
-static ssize_t debug_open(struct inode *inode, struct file *file)\r
-{\r
- file->private_data = inode->i_private;\r
- return 0;\r
-}\r
-\r
-static ssize_t debug_read(struct file *file, char __user *buf, size_t count,\r
- loff_t *ppos)\r
-{\r
- vdm_region *region, *tmp_region;\r
- const int debug_bufmax = 4096;\r
- static char buffer[4096];\r
- int n = 0;\r
-\r
- DLOG("debug open\n");\r
- n = scnprintf(buffer, debug_bufmax,\r
- "pid #: mapped regions (offset, len, used, post) ...\n");\r
- down_read(&vdm_rwsem);\r
- list_for_each_entry_safe(region, tmp_region, &vdm_index, index_list) {\r
- n += scnprintf(buffer + n, debug_bufmax - n,\r
- "(%d,%d,%d,%d) ",\r
- region->index, region->pfn, region->used, region->post);\r
- }\r
- up_read(&vdm_rwsem);\r
- n++;\r
- buffer[n] = 0;\r
- return simple_read_from_buffer(buf, count, ppos, buffer, n);\r
-}\r
-\r
-static struct file_operations debug_fops = {\r
- .read = debug_read,\r
- .open = debug_open,\r
-};\r
-#endif\r
-\r
-int vpu_mem_setup(struct vpu_mem_platform_data *pdata)\r
-{\r
- vdm_link *tmp = NULL;\r
- int err = 0;\r
-\r
- if (vpu_mem_count) {\r
- printk(KERN_ALERT "Only one vpu_mem driver can be register!\n");\r
- goto err_cant_register_device;\r
- }\r
-\r
- memset(&vpu_mem, 0, sizeof(struct vpu_mem_info));\r
-\r
- vpu_mem.cached = pdata->cached;\r
- vpu_mem.buffered = pdata->buffered;\r
- vpu_mem.base = pdata->start;\r
- vpu_mem.size = pdata->size;\r
- init_rwsem(&vdm_rwsem);\r
- INIT_LIST_HEAD(&vdm_proc);\r
- INIT_LIST_HEAD(&vdm_used);\r
- INIT_LIST_HEAD(&vdm_post);\r
- INIT_LIST_HEAD(&vdm_free);\r
- INIT_LIST_HEAD(&vdm_index);\r
- vpu_mem.dev.name = pdata->name;\r
- vpu_mem.dev.minor = MISC_DYNAMIC_MINOR;\r
- vpu_mem.dev.fops = &vpu_mem_fops;\r
-\r
- err = misc_register(&vpu_mem.dev);\r
- if (err) {\r
- printk(KERN_ALERT "Unable to register vpu_mem driver!\n");\r
- goto err_cant_register_device;\r
- }\r
-\r
- vpu_mem.num_entries = vpu_mem.size / VPU_MEM_MIN_ALLOC;\r
-\r
- tmp = new_link_by_index(0, vpu_mem.num_entries);\r
- if (NULL == tmp) {\r
- printk(KERN_ALERT "init free region failed\n");\r
- goto err_no_mem_for_metadata;\r
- }\r
- put_free_link(tmp);\r
- _insert_region_index(tmp->region);\r
-\r
- if (vpu_mem.cached)\r
- vpu_mem.vbase = ioremap_cached(vpu_mem.base, vpu_mem.size);\r
- #ifdef ioremap_ext_buffered\r
- else if (vpu_mem.buffered)\r
- vpu_mem.vbase = ioremap_ext_buffered(vpu_mem.base, vpu_mem.size);\r
- #endif\r
- else\r
- vpu_mem.vbase = ioremap(vpu_mem.base, vpu_mem.size);\r
-\r
- if (vpu_mem.vbase == 0)\r
- goto error_cant_remap;\r
-\r
- #if VPU_MEM_DEBUG\r
- debugfs_create_file(pdata->name, S_IFREG | S_IRUGO, NULL, (void *)vpu_mem.dev.minor,\r
- &debug_fops);\r
- #endif\r
- printk("%s: %d initialized\n", pdata->name, vpu_mem.dev.minor);\r
- vpu_mem_count++;\r
- return 0;\r
-error_cant_remap:\r
- if (tmp) {\r
- kfree(tmp);\r
- }\r
-err_no_mem_for_metadata:\r
- misc_deregister(&vpu_mem.dev);\r
-err_cant_register_device:\r
- return -1;\r
-}\r
-\r
-static int vpu_mem_probe(struct platform_device *pdev)\r
-{\r
- struct vpu_mem_platform_data *pdata;\r
-\r
- if (!pdev || !pdev->dev.platform_data) {\r
- printk(KERN_ALERT "Unable to probe vpu_mem!\n");\r
- return -1;\r
- }\r
- pdata = pdev->dev.platform_data;\r
- return vpu_mem_setup(pdata);\r
-}\r
-\r
-static int vpu_mem_remove(struct platform_device *pdev)\r
-{\r
- if (!pdev || !pdev->dev.platform_data) {\r
- printk(KERN_ALERT "Unable to remove vpu_mem!\n");\r
- return -1;\r
- }\r
- if (vpu_mem_count) {\r
- misc_deregister(&vpu_mem.dev);\r
- vpu_mem_count--;\r
- } else {\r
- printk(KERN_ALERT "no vpu_mem to remove!\n");\r
- }\r
- return 0;\r
-}\r
-\r
-static struct platform_driver vpu_mem_driver = {\r
- .probe = vpu_mem_probe,\r
- .remove = vpu_mem_remove,\r
- .driver = { .name = "vpu_mem" }\r
-};\r
-\r
-static int __init vpu_mem_proc_init(void);\r
-static int __init vpu_mem_init(void)\r
-{\r
- vpu_mem_proc_init();\r
- return platform_driver_register(&vpu_mem_driver);\r
-}\r
-\r
-static void __exit vpu_mem_exit(void)\r
-{\r
- platform_driver_unregister(&vpu_mem_driver);\r
-}\r
-\r
-module_init(vpu_mem_init);\r
-module_exit(vpu_mem_exit);\r
-\r
-#ifdef CONFIG_PROC_FS\r
-#include <linux/proc_fs.h>\r
-#include <linux/seq_file.h>\r
-\r
-static int proc_vpu_mem_show(struct seq_file *s, void *v)\r
-{\r
- if (vpu_mem_count) {\r
- seq_printf(s, "vpu mem opened\n");\r
- } else {\r
- seq_printf(s, "vpu mem closed\n");\r
- return 0;\r
- }\r
-\r
- down_read(&vdm_rwsem);\r
- {\r
- vdm_link *link, *tmp_link;\r
- vdm_pool *pool, *tmp_pool;\r
- vdm_region *region, *tmp_region;\r
- vdm_session *session, *tmp_session;\r
- // °´ index ´òÓ¡È«²¿ region\r
- seq_printf(s, "index:\n");\r
- list_for_each_entry_safe(region, tmp_region, &vdm_index, index_list) {\r
- seq_printf(s, " idx %6d pfn %6d used %3d post %3d\n",\r
- region->index, region->pfn, region->used, region->post);\r
- }\r
- if (list_empty(&vdm_free)) {\r
- seq_printf(s, "free : empty\n");\r
- } else {\r
- seq_printf(s, "free :\n");\r
- list_for_each_entry_safe(link, tmp_link, &vdm_free, status_link) {\r
- seq_printf(s, " idx %6d pfn %6d used %3d post %3d\n",\r
- link->index, link->pfn, link->ref.used, link->ref.post);\r
- }\r
- }\r
- if (list_empty(&vdm_used)) {\r
- seq_printf(s, "used : empty\n");\r
- } else {\r
- seq_printf(s, "used :\n");\r
- list_for_each_entry_safe(link, tmp_link, &vdm_used, status_link) {\r
- seq_printf(s, " idx %6d pfn %6d used %3d post %3d\n",\r
- link->index, link->pfn, link->ref.used, link->ref.post);\r
- }\r
- }\r
- if (list_empty(&vdm_post)) {\r
- seq_printf(s, "post : empty\n");\r
- } else {\r
- seq_printf(s, "post :\n");\r
- list_for_each_entry_safe(link, tmp_link, &vdm_post, status_link) {\r
- seq_printf(s, " idx %6d pfn %6d used %3d post %3d\n",\r
- link->index, link->pfn, link->ref.used, link->ref.post);\r
- }\r
- }\r
-\r
- // ´òÓ¡ vpu_mem_info ÖеÄÈ«²¿ session µÄ region Õ¼ÓÃÇé¿ö\r
- list_for_each_entry_safe(session, tmp_session, &vdm_proc, list_session) {\r
- seq_printf(s, "\npid: %d\n", session->pid);\r
- if (list_empty(&session->list_pool)) {\r
- seq_printf(s, "pool : empty\n");\r
- } else {\r
- seq_printf(s, "pool :\n");\r
- list_for_each_entry_safe(pool, tmp_pool, &session->list_pool, session_link) {\r
- seq_printf(s, " pfn %6d target %3d current %2d\n",\r
- pool->pfn, pool->count_target, pool->count_current);\r
- }\r
- }\r
- if (list_empty(&session->list_used)) {\r
- seq_printf(s, "used : empty\n");\r
- } else {\r
- seq_printf(s, "used :\n");\r
- list_for_each_entry_safe(link, tmp_link, &session->list_used, session_link) {\r
- seq_printf(s, " idx %6d pfn %6d used %3d\n",\r
- link->index, link->pfn, link->ref.used);\r
- }\r
- }\r
- if (list_empty(&session->list_post)) {\r
- seq_printf(s, "post : empty\n");\r
- } else {\r
- seq_printf(s, "post :\n");\r
- list_for_each_entry_safe(link, tmp_link, &session->list_post, session_link) {\r
- seq_printf(s, " idx %6d pfn %6d post %3d\n",\r
- link->index, link->pfn, link->ref.post);\r
- }\r
- }\r
- }\r
- }\r
-\r
- up_read(&vdm_rwsem);\r
- return 0;\r
-}\r
-\r
-static int proc_vpu_mem_open(struct inode *inode, struct file *file)\r
-{\r
- return single_open(file, proc_vpu_mem_show, NULL);\r
-}\r
-\r
-static const struct file_operations proc_vpu_mem_fops = {\r
- .open = proc_vpu_mem_open,\r
- .read = seq_read,\r
- .llseek = seq_lseek,\r
- .release = single_release,\r
-};\r
-\r
-static int __init vpu_mem_proc_init(void)\r
-{\r
- proc_create("vpu_mem", 0, NULL, &proc_vpu_mem_fops);\r
- return 0;\r
-\r
-}\r
-#endif /* CONFIG_PROC_FS */\r
-\r
+++ /dev/null
-if ARCH_RK2928
-
-choice
- prompt "RK2928 Board Type"
- default MACH_RK2928_SDK
-
-config MACH_RK2928
- bool "RK2928 Board"
- select RK_CONFIG
-
-
-config MACH_RK2928_SDK
- bool "RK2928(BGA) SDK board"
-
-config MACH_RK2926_SDK
- bool "RK2926 SDK board"
-
- config MACH_RK2926_V86
- tristate "rk2926 v86 "
- depends on MACH_RK2926_SDK
-
-
-config MACH_RK2928_PHONEPAD
- bool "RK2928_PhonePad board"
-config MACH_RK2928_PHONEPAD_760
- bool "RK2928_PhonePad board 760"
-
-config MACH_RK2928_A720
- bool "RK2928 A720 board"
-
-config MACH_RK2928_TB
- bool "RK2928 top board"
-
-config MACH_RK2926_TB
- bool "RK2926 top board"
-
-config MACH_RK2928_FPGA
- bool "RK2928 FPGA board"
-
-endchoice
-
-endif
+++ /dev/null
-obj-y += common.o
-CFLAGS_common.o += -DTEXT_OFFSET=$(TEXT_OFFSET)
-obj-y += io.o
-obj-y += reset.o
-obj-y += timer.o
-obj-y += devices.o
-obj-y += iomux.o
-obj-y += ../plat-rk/clock.o
-obj-y += clock_data.o
-obj-y += ddr.o
-obj-$(CONFIG_CPU_FREQ) += cpufreq.o
-obj-$(CONFIG_DVFS) += dvfs.o
-obj-$(CONFIG_PM) += pm.o
-obj-$(CONFIG_RK30_I2C_INSRAM) += i2c_sram.o
-
-obj-y += board.o
-
-board-$(CONFIG_MACH_RK2928) := board-rk2928.o
-
-board-$(CONFIG_MACH_RK2928_SDK) := board-rk2928-sdk.o
-board-$(CONFIG_MACH_RK2926_SDK) := board-rk2926-sdk.o
-board-$(CONFIG_MACH_RK2928_PHONEPAD) := board-rk2928-phonepad.o
-board-$(CONFIG_MACH_RK2928_PHONEPAD_760) := board-rk2928-phonepad-760.o
-board-$(CONFIG_MACH_RK2928_A720) := board-rk2928-a720.o
-board-$(CONFIG_MACH_RK2928_TB) := board-rk2928-tb.o
-board-$(CONFIG_MACH_RK2926_TB) := board-rk2928-tb.o
-board-$(CONFIG_MACH_RK2928_FPGA) := board-rk2928-fpga.o
+++ /dev/null
- zreladdr-y := 0x60408000
-params_phys-y := 0x60088000
-initrd_phys-y := 0x60800000
+++ /dev/null
-#if defined(CONFIG_SC6610)
-#include <linux/sc6610.h>
-#endif
-#if defined(CONFIG_MODEM_SOUND)
-#include "../../../drivers/misc/modem_sound.h"
-#endif
-#include "../../../drivers/headset_observe/rk_headset.h"
-/****************** default paramter *********************/
-enum {
- DEF_AP_MDM = -1,
- DEF_AP_HAS_ALSA = -1,
- DEF_AP_MULTI_CARD = -1,
- DEF_AP_DATA_ONLY = -1,
-};
-enum {
- DEF_BP_PWR = 0x000003c2,
- DEF_BP_RST = -1,
- DEF_BP_WK_AP = 0x000003c3,
- DEF_AP_WK_BP = 0x000003c4,
- DEF_MDM_ASST = 0x000003c5,
-};
-enum {
- DEF_HD_IO = 0x000001b4,
- DEF_HK_IO = 0x000000d1,
-};
-enum {
- DEF_SPKCTL_IO = 0x000003d4,
-};
-enum {
- DEF_RDA_I2C = 0,
-};
-/*************************************************************/
-
-/* Android Parameter */
-static int ap_mdm = DEF_AP_MDM;
-module_param(ap_mdm, int, 0644);
-static int ap_has_alsa = DEF_AP_HAS_ALSA;
-module_param(ap_has_alsa, int, 0644);
-static int ap_multi_card = DEF_AP_MULTI_CARD;
-module_param(ap_multi_card, int, 0644);
-static int ap_data_only = DEF_AP_DATA_ONLY;
-module_param(ap_data_only, int, 0644);
-
-/* sc6610 */
-static int bp_pwr = DEF_BP_PWR;
-module_param(bp_pwr, int, 0644);
-static int bp_rst = DEF_BP_RST;
-module_param(bp_rst, int, 0644);
-static int bp_wk_ap = DEF_BP_WK_AP;
-module_param(bp_wk_ap, int, 0644);
-static int ap_wk_bp = DEF_AP_WK_BP;
-module_param(ap_wk_bp, int, 0644);
-static int mdm_asst = DEF_MDM_ASST;
-module_param(mdm_asst, int, 0644);
-int check_sc_param(void)
-{
- return 0;
-}
-/* headset */
-static int hd_io = DEF_HD_IO;
-module_param(hd_io, int, 0644);
-static int hk_io = DEF_HK_IO;
-module_param(hk_io, int, 0644);
-int check_hd_param(void)
-{
- return 0;
-}
-/* modem sound */
-static int spkctl_io = DEF_SPKCTL_IO;
-module_param(spkctl_io, int, 0644);
-int check_mdm_sound_param(void)
-{
- return 0;
-}
-/* rda5990 */
-static int rda_i2c = DEF_RDA_I2C;
-module_param(rda_i2c, int, 0644);
-int check_rda_param(void)
-{
- return 0;
-}
-
-#if defined(CONFIG_SC6610)
-static int sc6610_io_init(void)
-{
- return 0;
-}
-
-static int sc6610_io_deinit(void)
-{
- return 0;
-}
-
-struct rk29_sc6610_data rk29_sc6610_info = {
- .io_init = sc6610_io_init,
- .io_deinit = sc6610_io_deinit,
-};
-struct platform_device rk29_device_sc6610 = {
- .name = "SC6610",
- .id = -1,
- .dev = {
- .platform_data = &rk29_sc6610_info,
- }
- };
-
-static int __init sc_board_init(void)
-{
- if(check_sc_param() < 0)
- return -EINVAL;
-
- rk29_sc6610_info.bp_power = get_port_config(bp_pwr).gpio;
- rk29_sc6610_info.bp_reset = get_port_config(bp_rst).gpio;
- rk29_sc6610_info.bp_wakeup_ap = get_port_config(bp_wk_ap).gpio;
- rk29_sc6610_info.ap_wakeup_bp = get_port_config(ap_wk_bp).gpio;
- rk29_sc6610_info.modem_assert = get_port_config(mdm_asst).gpio;
-
- return 0;
-}
-#else
-static int __init sc_board_init(void)
-{
- return 0;
-}
-#endif
-#if defined (CONFIG_RK_HEADSET_DET) || defined (CONFIG_RK_HEADSET_IRQ_HOOK_ADC_DET)
-static int rk_headset_io_init(int gpio)
-{
- int ret;
- ret = gpio_request(gpio, "headset_io");
- if(ret)
- return ret;
-
-// rk30_mux_api_set(iomux_name, iomux_mode);
- gpio_pull_updown(gpio, PullDisable);
- gpio_direction_input(gpio);
- mdelay(50);
- return 0;
-};
-
-static int rk_hook_io_init(int gpio)
-{
- int ret;
- ret = gpio_request(gpio, "hook_io");
- if(ret)
- return ret;
-
-// rk30_mux_api_set(iomux_name, iomux_mode);
- gpio_pull_updown(gpio, PullDisable);
- gpio_direction_input(gpio);
- mdelay(50);
- return 0;
-};
-
-struct rk_headset_pdata rk_headset_info = {
- .Hook_down_type = HOOK_DOWN_HIGH,
- .headset_in_type = HEADSET_IN_HIGH,
- .hook_key_code = KEY_MEDIA,
- .headset_io_init = rk_headset_io_init,
- .hook_io_init = rk_hook_io_init,
-};
-struct platform_device rk_device_headset = {
- .name = "rk_headsetdet",
- .id = 0,
- .dev = {
- .platform_data = &rk_headset_info,
- }
-};
-
-static int __init hd_board_init(void)
-{
- if(check_hd_param() < 0)
- return -EINVAL;
-
- rk_headset_info.Headset_gpio = get_port_config(hd_io).gpio;
- rk_headset_info.Hook_gpio = get_port_config(hk_io).gpio;
- return 0;
-}
-#else
-static int __init hd_board_init(void)
-{
- return 0;
-}
-#endif
-
-
-#if defined(CONFIG_MODEM_SOUND)
-
-struct modem_sound_data modem_sound_info = {
-};
-
-struct platform_device modem_sound_device = {
- .name = "modem_sound",
- .id = -1,
- .dev = {
- .platform_data = &modem_sound_info,
- }
- };
-static int __init mdm_sound_board_init(void)
-{
- struct port_config port;
- if(check_mdm_sound_param() < 0)
- return -EINVAL;
- port = get_port_config(spkctl_io);
- modem_sound_info.spkctl_io = port.gpio;
- modem_sound_info.spkctl_active = !port.io.active_low;
- return 0;
-}
-#else
-static int __init mdm_sound_board_init(void)
-{
- return 0;
-}
-
-#endif
-#ifdef CONFIG_RDA5990
-#define RDA_WIFI_CORE_ADDR (0x13)
-#define RDA_WIFI_RF_ADDR (0x14) //correct add is 0x14
-#define RDA_BT_CORE_ADDR (0x15)
-#define RDA_BT_RF_ADDR (0x16)
-
-#define RDA_WIFI_RF_I2C_DEVNAME "rda_wifi_rf_i2c"
-#define RDA_WIFI_CORE_I2C_DEVNAME "rda_wifi_core_i2c"
-#define RDA_BT_RF_I2C_DEVNAME "rda_bt_rf_i2c"
-#define RDA_BT_CORE_I2C_DEVNAME "rda_bt_core_i2c"
-static struct i2c_board_info __initdata rda_info[] = {
- {
- .type = RDA_WIFI_CORE_I2C_DEVNAME,
- .addr = RDA_WIFI_CORE_ADDR,
- .flags = 0,
-
- },
- {
- .type = RDA_WIFI_RF_I2C_DEVNAME,
- .addr = RDA_WIFI_RF_ADDR,
- .flags = 0,
-
- },
- {
- .type = RDA_BT_CORE_I2C_DEVNAME,
- .addr = RDA_BT_CORE_ADDR,
- .flags = 0,
-
- },
- {
- .type = RDA_BT_RF_I2C_DEVNAME,
- .addr = RDA_BT_RF_ADDR,
- .flags = 0,
-
- },
-};
-static int __init rda_board_init(void)
-{
- int ret;
-
- ret = check_rda_param();
-
- if(ret < 0)
- return ret;
- i2c_register_board_info(rda_i2c, rda_info, ARRAY_SIZE(rda_info));
- return 0;
-}
-#else
-static int __init rda_board_init(void)
-{
- return 0;
-}
-#endif
-
-
-static struct platform_device *phonepad_devices[] __initdata = {
-#if defined(CONFIG_SC6610)
- &rk29_device_sc6610,
-#endif
-#if defined (CONFIG_RK_HEADSET_DET) || defined (CONFIG_RK_HEADSET_IRQ_HOOK_ADC_DET)
- &rk_device_headset,
-#endif
-#if defined (CONFIG_MODEM_SOUND)
- &modem_sound_device,
-#endif
-};
-static void __init phonepad_board_init(void)
-{
- sc_board_init();
- hd_board_init();
- mdm_sound_board_init();
- rda_board_init();
- platform_add_devices(phonepad_devices, ARRAY_SIZE(phonepad_devices));
-}
-
-
+++ /dev/null
-/* arch/arm/mach-rk2928/board-rk2928-fpga.c
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-#include <mach/dvfs.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <linux/fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/mfd/tps65910.h>
-#include <linux/regulator/act8931.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-#if defined(CONFIG_HDMI_RK30)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-
-#ifdef CONFIG_SND_SOC_RK2928
-#include "../../../sound/soc/codecs/rk2928_codec.h"
-#endif
-
-#include "board-rk2928-sdk-camera.c"
-#include "board-rk2928-sdk-key.c"
-
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-
-#ifdef CONFIG_THREE_FB_BUFFER
-#define RK30_FB0_MEM_SIZE 12*SZ_1M
-#else
-#define RK30_FB0_MEM_SIZE 8*SZ_1M
-#endif
-
-int __sramdata g_pmic_type = 0;
-
-#if defined(CONFIG_REGULATOR_ACT8931)
-extern int act8931_charge_det ;
-extern int act8931_charge_ok ;
-#endif
-
-#if defined(CONFIG_MACH_RK2926_V86)
-//#define V86_VERSION_1_0
-#define V86_VERSION_1_1
-#endif
-
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-#define PWM_ID 0
-#define PWM_MUX_NAME GPIO0D2_PWM_0_NAME
-#define PWM_MUX_MODE GPIO0D_PWM_0
-#define PWM_MUX_MODE_GPIO GPIO0D_GPIO0D2
-#define PWM_GPIO RK2928_PIN0_PD2
-#define PWM_EFFECT_VALUE 0
-
-#if defined(V86_VERSION_1_1)
-#define LCD_DISP_ON_PIN
-#endif
-
-#ifdef LCD_DISP_ON_PIN
-#if defined(V86_VERSION_1_1)
-#define BL_EN_PIN RK2928_PIN3_PC1
-#define BL_EN_VALUE GPIO_HIGH
-#define BL_EN_MUX_NAME GPIO3C1_OTG_DRVVBUS_NAME
-#define BL_EN_MUX_MODE GPIO3C_GPIO3C1
-#else
-#define BL_EN_PIN RK2928_PIN1_PB0
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
-#ifdef LCD_DISP_ON_PIN
- #if defined(V86_VERSION_1_1)
- rk30_mux_api_set(BL_EN_MUX_NAME, BL_EN_MUX_MODE);
- #endif
-
- ret = gpio_request(BL_EN_PIN, NULL);
- if (ret != 0) {
- gpio_free(BL_EN_PIN);
- }
-
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0;
-#ifdef LCD_DISP_ON_PIN
- gpio_set_value(BL_EN_PIN, !BL_EN_VALUE);
- gpio_free(BL_EN_PIN);
-#endif
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
-
- #if defined(V86_VERSION_1_0) || defined(V86_VERSION_1_1)
- #if defined(CONFIG_MFD_TPS65910)
- if(g_pmic_type == PMIC_TYPE_TPS65910)
- {
- gpio_direction_output(PWM_GPIO, GPIO_HIGH);
- }
- #endif
- #endif
-
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret = 0;
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- if (gpio_request(PWM_GPIO, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- #if defined(CONFIG_MFD_TPS65910)
- if (pmic_is_tps65910() )
- #if defined(V86_VERSION_1_0) || defined(V86_VERSION_1_1)
- gpio_direction_output(PWM_GPIO, GPIO_HIGH);
- #else
- gpio_direction_output(PWM_GPIO, GPIO_LOW);
- #endif
- #endif
- #if defined(CONFIG_REGULATOR_ACT8931)
- if (pmic_is_act8931() )
- gpio_direction_output(PWM_GPIO, GPIO_HIGH);
- #endif
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, !BL_EN_VALUE);
-#endif
-
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- gpio_free(PWM_GPIO);
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
-#ifdef LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, 1);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .min_brightness = 80,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-#if defined(V86_VERSION_1_0) || defined(V86_VERSION_1_1) //for v86 to modify flash lcd when startup
-static int __init set_pwm_gpio_high(void)
-{
- printk("%s, xhc", __func__);
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- if (gpio_request(PWM_GPIO, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- gpio_direction_output(PWM_GPIO, GPIO_HIGH);
- gpio_free(PWM_GPIO);
- return 0;
-}
-core_initcall(set_pwm_gpio_high);
-#endif
-
-#endif
-
-#ifdef CONFIG_FB_ROCKCHIP
-
-#define LCD_MUX_NAME GPIO0C2_UART0_RTSN_NAME
-#define LCD_GPIO_MODE GPIO0C_GPIO0C2
-
-#define LCD_EN RK2928_PIN1_PB3
-#define LCD_EN_VALUE GPIO_LOW
-
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
-
- rk30_mux_api_set(LCD_MUX_NAME, LCD_GPIO_MODE);
-
- ret = gpio_request(LCD_EN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_EN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_EN, LCD_EN_VALUE); //disable
- }
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
-
- #if 0//defined(CONFIG_REGULATOR_ACT8931)
- if (pmic_is_act8931() ){
- struct regulator *ldo;
- ldo = regulator_get(NULL, "act_ldo4"); //vcc_lcd
- regulator_disable(ldo);
- regulator_put(ldo);
- udelay(100);
- }
- #endif
-
- #if defined(V86_VERSION_1_0) || defined(V86_VERSION_1_1)
- msleep(30);
- #endif
-
- gpio_set_value(LCD_EN, !LCD_EN_VALUE);
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- #if 0//defined(CONFIG_REGULATOR_ACT8931)
- if (pmic_is_act8931() ){
- struct regulator *ldo;
- ldo = regulator_get(NULL, "act_ldo4"); //vcc_lcd
- regulator_enable(ldo);
- regulator_put(ldo);
- udelay(100);
- msleep(300); // wait for powering on LED circuit
- }
- #endif
-
- #if defined(V86_VERSION_1_0) || defined(V86_VERSION_1_1)
- msleep(100);
- #endif
-
- gpio_set_value(LCD_EN, LCD_EN_VALUE);
- return 0;
-}
-
-#if defined(CONFIG_LCDC_RK2928)
-struct rk29fb_info lcdc_screen_info = {
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-
-//LCDC
-#ifdef CONFIG_LCDC_RK2928
-static struct resource resource_lcdc[] = {
- [0] = {
- .name = "lcdc reg",
- .start = RK2928_LCDC_PHYS,
- .end = RK2928_LCDC_PHYS + RK2928_LCDC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc irq",
- .start = IRQ_LCDC,
- .end = IRQ_LCDC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc = {
- .name = "rk2928-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc),
- .resource = resource_lcdc,
- .dev = {
- .platform_data = &lcdc_screen_info,
- },
-};
-#endif
-
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-/*ft5x0x touchpad*/
-#if defined (CONFIG_TOUCHSCREEN_FT5X0X)
-
-#if defined(V86_VERSION_1_0) || defined(V86_VERSION_1_1)
-#define TOUCH_RESET_PIN INVALID_GPIO
-#else
-#define TOUCH_RESET_PIN RK2928_PIN0_PD3
-#endif
-#define TOUCH_EN_PIN NULL
-#define TOUCH_INT_PIN RK2928_PIN1_PB0
-
-static struct ts_hw_data ts_hw_info = {
- .reset_gpio = TOUCH_RESET_PIN,
-};
-#endif
-
-#if defined(CONFIG_TOUCHSCREEN_GT811_IIC)
-#define TOUCH_RESET_PIN INVALID_GPIO//RK2928_PIN0_PD3//RK2928_PIN1_PA3
-#define TOUCH_INT_PIN RK2928_PIN1_PB0
-int goodix_init_platform_hw(void)
-{
-
- //printk("ft5306_init_platform_hw\n");
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("ft5306_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("ift5306_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, GPIO_HIGH);
- mdelay(10);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- mdelay(10);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- msleep(300);
- return 0;
-
-}
-
-struct goodix_platform_data goodix_info = {
- .model = 8105,
- //.irq_pin = RK2928_PIN1_PB0,
- .rest_pin = TOUCH_RESET_PIN,
- .init_platform_hw = goodix_init_platform_hw,
-};
-#endif
-
-
-#if defined(CONFIG_TOUCHSCREEN_SITRONIX_A720)
-
-#if defined(V86_VERSION_1_1)
-#define TOUCH_RESET_PIN NULL
-#else
-#define TOUCH_RESET_PIN RK2928_PIN1_PA3
-#endif
-#define TOUCH_INT_PIN RK2928_PIN1_PB0
-
-int ft5306_init_platform_hw(void)
-{
-
- //printk("ft5306_init_platform_hw\n");
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("ft5306_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("ift5306_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, GPIO_HIGH);
- mdelay(10);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- mdelay(10);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- msleep(300);
- return 0;
-
-}
-#if defined(V86_VERSION_1_1)
-int sitronix_direction_otation( int *x,int *y )
-{
- *x = *x ;
- *y = 480 - *y ;
- return 1 ;
-}
-#endif
-struct ft5x0x_platform_data sitronix_info = {
- .model = 5007,
- .init_platform_hw= ft5306_init_platform_hw,
- #if defined(V86_VERSION_1_1)
- .direction_otation = sitronix_direction_otation ,
- #endif
-};
-#endif
-
-/*MMA7660 gsensor*/
-#if defined (CONFIG_GS_MMA7660)
-#define MMA7660_INT_PIN RK2928_PIN1_PB2
-
-static int mma7660_init_platform_hw(void)
-{
- rk30_mux_api_set(GPIO1B2_SPI_RXD_UART1_SIN_NAME, GPIO1B_GPIO1B2);
-
- return 0;
-}
-
-static struct sensor_platform_data mma7660_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma7660_init_platform_hw,
- #if defined(V86_VERSION_1_0) || defined(V86_VERSION_1_1)
- #if defined(V86_VERSION_1_0)
- .orientation = {1, 0, 0, 0, -1, 0, 0, 0, -1},
- #else if defined(V86_VERSION_1_1)
- .orientation = {0, 1, 0, 1, 0, 0, 0, 0, -1},
- #endif
- #else
- .orientation = {-1, 0, 0, 0, 1, 0, 0, 0, -1},
- #endif
-};
-#endif
-
-
-#if CONFIG_RK30_PWM_REGULATOR
-static int pwm_voltage_map[] = {
- 950000,975000,1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000, 1375000, 1400000
-};
-
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_core",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] =
-{
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
- .pwm_id = 1,
- #if defined(V86_VERSION_1_1)
- #else
- .pwm_gpio = RK2928_PIN0_PD3,
- #endif
- .pwm_iomux_name = GPIO0D3_PWM_1_NAME,
- .pwm_iomux_pwm = GPIO0D_PWM_1,
- .pwm_iomux_gpio = GPIO0D_GPIO0D3,
- .pwm_voltage = 1200000,
- .suspend_voltage = 1050000,
- .min_uV = 950000,
- .max_uV = 1400000,
- .coefficient = 504, //50.4%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-#endif
-
-/***********************************************************
-* usb wifi
-************************************************************/
-#if defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU)
-
-static void rkusb_wifi_power(int on) {
- struct regulator *ldo = NULL;
-
-#if defined(CONFIG_MFD_TPS65910)
- if (pmic_is_tps65910() )
- ldo = regulator_get(NULL, "vmmc"); //vccio_wl
-#endif
-#if defined(CONFIG_REGULATOR_ACT8931)
- if(pmic_is_act8931() )
- ldo = regulator_get(NULL, "act_ldo4"); //vccio_wl
-#endif
-
- if(on) {
- regulator_enable(ldo);
- printk("%s: vccio_wl enable\n", __func__);
- } else {
- printk("%s: vccio_wl disable\n", __func__);
- regulator_disable(ldo);
- }
-
- regulator_put(ldo);
- udelay(100);
-}
-
-#endif
-
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and SDIO.noted by xbw at 2012-03-05
-**************************************************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "board-rk2928-sdk-sdmmc.c"
-#endif
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- rk30_mux_api_set(GPIO3B1_SDMMC0CMD_NAME, GPIO3B_SDMMC0_CMD);
- rk30_mux_api_set(GPIO3B0_SDMMC0CLKOUT_NAME, GPIO3B_SDMMC0_CLKOUT);
- rk30_mux_api_set(GPIO3B2_SDMMC0DATA0_NAME, GPIO3B_SDMMC0_DATA0);
- rk30_mux_api_set(GPIO3B3_SDMMC0DATA1_NAME, GPIO3B_SDMMC0_DATA1);
- rk30_mux_api_set(GPIO3B4_SDMMC0DATA2_NAME, GPIO3B_SDMMC0_DATA2);
- rk30_mux_api_set(GPIO3B5_SDMMC0DATA3_NAME, GPIO3B_SDMMC0_DATA3);
-
- rk30_mux_api_set(GPIO3B6_SDMMC0DETECTN_NAME, GPIO3B_GPIO3B6);
-
- rk30_mux_api_set(GPIO3A7_SDMMC0PWREN_NAME, GPIO3A_GPIO3A7);
- gpio_request(RK30_PIN3_PA7, "sdmmc-power");
- gpio_direction_output(RK30_PIN3_PA7, GPIO_LOW);
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- #if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO);
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FMUX);
- #endif
-
- #if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
- #endif
-
-#endif
-
- return 0;
-}
-
-#if defined(CONFIG_MACH_RK2926_V86)
-int rk2926_v86_sd_vcc_reset(){
- struct regulator *vcc;
-
- vcc = regulator_get(NULL,"vmmc");
- if (vcc == NULL || IS_ERR(vcc) ){
- printk("%s get cif vaux33 ldo failed!\n",__func__);
- return -1 ;
- }
-
-
- printk("hj---->rk29_sdmmc_hw_init get vmmc regulator successfully \n\n\n");
- regulator_disable(vcc);
- mdelay(2000);
- regulator_enable(vcc);
-
-}
-#endif
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) && defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- .status = rk29sdk_wifi_mmc0_status,
- .register_status_notify = rk29sdk_wifi_mmc0_status_register,
-#endif
-
- .power_en = RK29SDK_SD_CARD_PWR_EN,
- .power_en_level = RK29SDK_SD_CARD_PWR_EN_LEVEL,
-
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC0_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-#if defined(CONFIG_MACH_RK2926_V86)
- .sd_vcc_reset = rk2926_v86_sd_vcc_reset ,
-#endif
-
- .det_pin_info = {
- .io = RK29SDK_SD_CARD_DETECT_N, //INVALID_GPIO,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- },
- },
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- rk30_mux_api_set(GPIO3C0_SMMC1CMD_NAME, GPIO3C_SMMC1_CMD);
- rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_NAME, GPIO3C_SDMMC1_CLKOUT);
- rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_NAME, GPIO3C_SDMMC1_DATA0);
- rk30_mux_api_set(GPIO3C2_SDMMC1DATA1_NAME, GPIO3C_SDMMC1_DATA1);
- rk30_mux_api_set(GPIO3C3_SDMMC1DATA2_NAME, GPIO3C_SDMMC1_DATA2);
- rk30_mux_api_set(GPIO3C4_SDMMC1DATA3_NAME, GPIO3C_SDMMC1_DATA3);
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC) || defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-
- #if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC1_WRITE_PROTECT_ENABLE_VALUE;
- #else
- .write_prt = INVALID_GPIO,
- #endif
-
- #if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
- .sdio_INT_gpio = RK29SDK_WIFI_SDIO_CARD_INT,
- #endif
-
- .det_pin_info = {
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .io = RK29SDK_SD_CARD_DETECT_N,
-#else
- .io = INVALID_GPIO,
-#endif
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- .fmux = GPIO3B_SDMMC0_DETECT_N,
- },
- },
-
- .enable_sd_wakeup = 0,
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-/**************************************************************************************************
- * the end of setting for SDMMC devices
-**************************************************************************************************/
-
-
-#ifdef CONFIG_SND_SOC_RK2928
-static int hpctl_io_init(void)
-{
- int ret = 0;
- return ret;
-}
-
-struct rk2928_codec_pdata rk2928_codec_pdata_info={
- .hpctl = INVALID_GPIO,
- .hpctl_io_init = hpctl_io_init,
-};
-
-static struct resource resources_acodec[] = {
- {
- .start = RK2928_ACODEC_PHYS,
- .end = RK2928_ACODEC_PHYS + RK2928_ACODEC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = RK2928_PIN1_PA0,
- .end = RK2928_PIN1_PA0,
- .flags = IORESOURCE_IO,
- },
-};
-
-static struct platform_device device_acodec = {
- .name = "rk2928-codec",
- .id = -1,
- .num_resources = ARRAY_SIZE(resources_acodec),
- .resource = resources_acodec,
- .dev = {
- .platform_data = &rk2928_codec_pdata_info,
- }
-};
-#endif
-
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
-#if defined(V86_VERSION_1_0) || defined(V86_VERSION_1_1)
-#define DC_DET_PIN RK2928_PIN1_PA5
-
-#if defined(V86_VERSION_1_1)
-static int tps65910_charge_ok;
-static irqreturn_t tps65910_gpio0_r_irq(int irq, void *irq_data);
-static irqreturn_t tps65910_gpio0_f_irq(int irq, void *irq_data);
-#endif
-
-int rk30_battery_adc_io_init(void){
- int ret = 0;
-
- //dc charge detect pin
- ret = gpio_request(DC_DET_PIN, NULL);
- if (ret) {
- printk("failed to request dc_det gpio\n");
- return ret ;
- }
-
- gpio_pull_updown(DC_DET_PIN, 0);//important
- ret = gpio_direction_input(DC_DET_PIN);
- if (ret) {
- printk("failed to set gpio dc_det input\n");
- return ret ;
- }
-
- #if defined(V86_VERSION_1_1)
- //ÉÏÉýÑØ
- //ret = request_irq(IRQ_BOARD_BASE+TPS65910_IRQ_GPIO_R, tps65910_gpio0_r_irq, IRQF_TRIGGER_RISING, "chg_ok", NULL);
- ret = request_threaded_irq( IRQ_BOARD_BASE +TPS65910_IRQ_GPIO_R,
- NULL, tps65910_gpio0_r_irq, IRQF_TRIGGER_RISING,
- "chg_ok", NULL);
- if (ret) {
- printk("failed to request_irq IRQ_BOARD_BASE +TPS65910_IRQ_GPIO_R , error = %d \n",ret);
- return ret ;
- }
- #endif
-
- return 0;
-
-}
-
-#if defined(V86_VERSION_1_1)
-static irqreturn_t tps65910_gpio0_r_irq(int irq, void *irq_data)//ÉÏÉýÑØÖжϺ¯Êý
-{
- //printk("-----------------chg_ok_det######### %s\n",__func__);
- tps65910_charge_ok = 1 ;
- int ret = request_threaded_irq( IRQ_BOARD_BASE +TPS65910_IRQ_GPIO_F,
- NULL, tps65910_gpio0_f_irq, IRQF_TRIGGER_RISING,
- "chg_no_ok", NULL);
-
- return IRQ_HANDLED;
-}
-
-static irqreturn_t tps65910_gpio0_f_irq(int irq, void *irq_data)//ϽµÑØÖжϺ¯Êý
-{
- //printk("-----------------chg_no_ok######### %s\n",__func__);
- tps65910_charge_ok = 0 ;
- int ret = request_threaded_irq( IRQ_BOARD_BASE +TPS65910_IRQ_GPIO_R,
- NULL, tps65910_gpio0_r_irq, IRQF_TRIGGER_RISING,
- "chg_ok", NULL);
-
- return IRQ_HANDLED;
-}
-
-#if defined(CONFIG_MFD_TPS65910)
-int rk30_battery_adc_charging_ok( ){
- //printk(">>>>>>>>>>return tps65910_charge_ok = %d \n",tps65910_charge_ok);
- if( gpio_get_value(DC_DET_PIN) == GPIO_LOW){
- if( tps65910_charge_ok ){
-
- return 1 ;
- }
- }
-
- return 0 ;
-}
-#endif
-#endif
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = DC_DET_PIN,//INVALID_GPIO,
- .batt_low_pin = INVALID_GPIO,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = INVALID_GPIO,//RK2928_PIN1_PA5,
- .dc_det_level = GPIO_LOW,
- .charge_ok_level = GPIO_HIGH,
-
- .io_init = rk30_battery_adc_io_init,
- #if defined(V86_VERSION_1_1)
- .charging_ok = rk30_battery_adc_charging_ok ,
- #endif
-
- .reference_voltage=3300,
- .pull_up_res = 200 ,
- .pull_down_res = 200 ,
-
- .charging_sleep = 0 ,
- .save_capacity = 1 ,
- .adc_channel =0 ,
-
-};
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-
-#else
-#define DC_DET_PIN RK2928_PIN1_PA5
-int rk30_battery_adc_io_init(void){
- int ret = 0;
-
- //dc charge detect pin
- ret = gpio_request(DC_DET_PIN, NULL);
- if (ret) {
- printk("failed to request dc_det gpio\n");
- return ret ;
- }
-
- gpio_pull_updown(DC_DET_PIN, 0);//important
- ret = gpio_direction_input(DC_DET_PIN);
- if (ret) {
- printk("failed to set gpio dc_det input\n");
- return ret ;
- }
-
- return 0;
-
-}
-#if defined(CONFIG_REGULATOR_ACT8931)
-int rk30_battery_adc_is_dc_charging( ){
- return act8931_charge_det ;
-}
-int rk30_battery_adc_charging_ok( ){
- return act8931_charge_ok ;
-}
-#endif
- static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = INVALID_GPIO,
- .batt_low_pin = INVALID_GPIO,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = INVALID_GPIO,
-
- //.io_init = rk30_battery_adc_io_init,
- #if defined(CONFIG_REGULATOR_ACT8931)
- .is_dc_charging = rk30_battery_adc_is_dc_charging,
- .charging_ok = rk30_battery_adc_charging_ok ,
- #endif
-
- .charging_sleep = 0 ,
- .save_capacity = 1 ,
- .adc_channel =0 ,
- };
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-#endif
-
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_FB_ROCKCHIP
- &device_fb,
-#endif
-#ifdef CONFIG_LCDC_RK2928
- &device_lcdc,
-#endif
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- &rk29_device_backlight,
-#endif
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_SND_SOC_RK2928
- &device_acodec,
-#endif
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
- &rk30_device_adc_battery,
-#endif
-};
-//i2c
-#ifdef CONFIG_I2C0_RK30
-#ifdef CONFIG_MFD_TPS65910
-#if defined(V86_VERSION_1_0) || defined(V86_VERSION_1_1)
-#define TPS65910_HOST_IRQ RK2928_PIN1_PB1
-#else
-#define TPS65910_HOST_IRQ RK2928_PIN1_PB2
-#endif
-#define PMU_POWER_SLEEP RK2928_PIN1_PA1
-
-static struct pmu_info tps65910_dcdc_info[] = {
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- #if defined(V86_VERSION_1_1)
- .name = "vdd_core", //ddr
- #else
- .name = "vdd2", //ddr
- #endif
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vio", //vcc_io
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
-
-};
-static struct pmu_info tps65910_ldo_info[] = {
- #if defined(CONFIG_MACH_RK2928_TB) || defined(CONFIG_MACH_RK2926_TB)
- {
- .name = "vpll", //vcc25
- .min_uv = 2500000,
- .max_uv = 2500000,
- },
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "vdac", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- #else
- {
- .name = "vpll", //vcc25
- .min_uv = 1000000,
- .max_uv = 2500000,
- },
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 1500000,
- .max_uv = 1500000,
- },
-
- {
- .name = "vdig2", //vdd11
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vaux1", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "vaux2", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vaux33", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vmmc", //
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- #endif
- };
-
-#include "board-rk2928-sdk-tps65910.c"
-#endif
-
-#ifdef CONFIG_REGULATOR_ACT8931
-#define ACT8931_HOST_IRQ RK2928_PIN1_PB1
-#if defined(CONFIG_MACH_RK2928_SDK)
-#define ACT8931_CHGSEL_PIN RK2928_PIN0_PD0
-#else
-#define ACT8931_CHGSEL_PIN RK2928_PIN1_PA1
-#endif
-
-static struct pmu_info act8931_dcdc_info[] = {
- {
- .name = "act_dcdc1", //vcc_io
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_dcdc2", //ddr
- .min_uv = 1500000,
- .max_uv = 1500000,
- },
- {
- .name = "vdd_cpu", //vdd_arm
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
-
-};
-static struct pmu_info act8931_ldo_info[] = {
- {
- .name = "act_ldo1", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "act_ldo2", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo3", //vcca30
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
- {
- .name = "act_ldo4", //vcc_wl
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
-};
-#include "board-rk2928-sdk-act8931.c"
-#endif
-
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-#if defined (CONFIG_REGULATOR_ACT8931)
- {
- .type = "act8931",
- .addr = 0x5b,
- .flags = 0,
- .irq = ACT8931_HOST_IRQ,
- .platform_data=&act8931_data,
- },
-#endif
-#if defined (CONFIG_RTC_HYM8563)
- {
- .type = "rtc_hym8563",
- .addr = 0x51,
- .flags = 0,
- .irq = RK2928_PIN1_PA5,
- },
-#endif
-};
-#endif
-
-int __sramdata gpio0d3_iomux,gpio0d3_do,gpio0d3_dir;
-
-#define gpio0_readl(offset) readl_relaxed(RK2928_GPIO0_BASE + offset)
-#define gpio0_writel(v, offset) do { writel_relaxed(v, RK2928_GPIO0_BASE + offset); dsb(); } while (0)
-
-void __sramfunc rk30_pwm_logic_suspend_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
-
- sram_udelay(10000);
- gpio0d3_iomux = readl_relaxed(GRF_GPIO0D_IOMUX);
- gpio0d3_do = gpio0_readl(GPIO_SWPORTA_DR);
- gpio0d3_dir = gpio0_readl(GPIO_SWPORTA_DDR);
-
- writel_relaxed((gpio0d3_iomux |(1<<22)) & (~(1<<6)), GRF_GPIO0D_IOMUX);
- gpio0_writel(gpio0d3_dir |(1<<27), GPIO_SWPORTA_DDR);
- gpio0_writel(gpio0d3_do |(1<<27), GPIO_SWPORTA_DR);
-#endif
-}
-void __sramfunc rk30_pwm_logic_resume_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- writel_relaxed((1<<22)|gpio0d3_iomux, GRF_GPIO0D_IOMUX);
- gpio0_writel(gpio0d3_dir, GPIO_SWPORTA_DDR);
- gpio0_writel(gpio0d3_do, GPIO_SWPORTA_DR);
- sram_udelay(10000);
-
-#endif
-
-}
-extern void pwm_suspend_voltage(void);
-extern void pwm_resume_voltage(void);
-void rk30_pwm_suspend_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_suspend_voltage();
-#endif
-}
-void rk30_pwm_resume_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_resume_voltage();
-#endif
-}
-
-u32 gpio1b_iomux,gpio1c_iomux, gpio1b_pull,gpio1d_pull,gpio1_ddr;
-
-#define gpio1_readl(offset) readl_relaxed(RK2928_GPIO1_BASE + offset)
-#define gpio1_writel(v, offset) do { writel_relaxed(v, RK2928_GPIO1_BASE + offset); dsb(); } while (0)
-#define grf_readl(offset) readl_relaxed(RK2928_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel_relaxed(v, RK2928_GRF_BASE + offset); dsb(); } while (0)
-
-void board_gpio_suspend(void) {
- gpio1b_iomux = readl_relaxed(GRF_GPIO1B_IOMUX);
- gpio1c_iomux = readl_relaxed(GRF_GPIO1C_IOMUX);
- writel_relaxed((0x1<< 30), GRF_GPIO1B_IOMUX);
- writel_relaxed((0x5 <<24) |(0x5 <<20)|(0x1 <<16), GRF_GPIO1C_IOMUX);
- gpio1b_pull = grf_readl(GRF_GPIO1L_PULL);
- gpio1d_pull = grf_readl(GRF_GPIO1H_PULL);
- grf_writel(gpio1b_pull |(0x1<<31)|(0x1 <<15),GRF_GPIO1L_PULL);
- grf_writel( gpio1d_pull | (0xf<<18) |(0x1<<16) |(0xf <<2)|(0x1 <<0),GRF_GPIO1H_PULL);
-
- gpio1_ddr = gpio1_readl(GPIO_SWPORTA_DDR);
- gpio1_writel(gpio1_ddr & (~((0x3 <<15) |(0xf <<18))),GPIO_SWPORTA_DDR);
-}
- void board_gpio_resume(void) {
- writel_relaxed(0xffff0000|gpio1b_iomux, GRF_GPIO1B_IOMUX);
- writel_relaxed(0xffff0000|gpio1c_iomux, GRF_GPIO1C_IOMUX);
- grf_writel( 0xffff0000|gpio1b_pull,GRF_GPIO1L_PULL);
- grf_writel( 0xffff0000|gpio1d_pull,GRF_GPIO1H_PULL);
-
- gpio1_writel(gpio1_ddr,GPIO_SWPORTA_DDR);
-}
-
-void __sramfunc board_pmu_suspend(void)
-{
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910() )
- board_pmu_tps65910_suspend();
- #endif
-}
-void __sramfunc board_pmu_resume(void)
-{
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910() )
- board_pmu_tps65910_resume();
- #endif
-}
-
-#ifdef CONFIG_I2C1_RK30
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_GS_MMA7660)
- {
- .type = "gs_mma7660",
- .addr = 0x4c,
- .flags = 0,
- .irq = MMA7660_INT_PIN,
- .platform_data = &mma7660_info,
- },
-#endif
-
-};
-#endif
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-#if defined (CONFIG_TOUCHSCREEN_SITRONIX_A720)
-{
- .type ="sitronix",
- .addr = 0x60,
- .flags = 0,
- .irq = TOUCH_INT_PIN,
- .platform_data = &sitronix_info,
-},
-#endif
-#if defined (CONFIG_TOUCHSCREEN_GT811_IIC)
- {
- .type = "gt811_ts",
- .addr = 0x5d,
- .flags = 0,
- .irq = TOUCH_INT_PIN,
- .platform_data = &goodix_info,
- },
-#endif
-#if defined (CONFIG_TOUCHSCREEN_FT5X0X)
- {
- .type = "ft5x0x_ts",
- .addr = 0x38,
- .flags = 0,
- .irq = TOUCH_INT_PIN,
- //.platform_data = &ft5x0x_info,
- .platform_data = &ts_hw_info,
- },
-#endif
-};
-#endif
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- //set iomux (gpio) here
-
- return 0;
-}
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(4, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-
-#define POWER_ON_PIN RK2928_PIN1_PA2 //power_hold
-static void rk2928_pm_power_off(void)
-{
- printk(KERN_ERR "rk2928_pm_power_off start...\n");
-
- #if defined(CONFIG_REGULATOR_ACT8931)
- if (pmic_is_act8931() ){
- if(act8931_charge_det)
- arm_pm_restart(0, NULL);
- act8931_device_shutdown();
- }
- #endif
-
- #if defined(CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910() )
- tps65910_device_shutdown();//tps65910 shutdown
- #endif
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
-
-};
-
-static void __init rk2928_board_init(void)
-{
- gpio_request(POWER_ON_PIN, "poweronpin");
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
- pm_power_off = rk2928_pm_power_off;
-
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- rk29sdk_wifi_bt_gpio_control_init();
-#endif
-}
-
-static void __init rk2928_reserve(void)
-{
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0", RK30_FB0_MEM_SIZE);
- resource_fb[0].end = resource_fb[0].start + RK30_FB0_MEM_SIZE - 1;
-#endif
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
- board_mem_reserved();
-}
-/**
- * dvfs_cpu_logic_table: table for arm and logic dvfs
- * @frequency : arm frequency
- * @cpu_volt : arm voltage depend on frequency
- * @logic_volt : logic voltage arm requests depend on frequency
- * comments : min arm/logic voltage
- */
-static struct dvfs_arm_table dvfs_cpu_logic_table[] = {
-#if 1
- {.frequency = 216 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1000 * 1000},
- {.frequency = 312 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1000 * 1000},
- {.frequency = 408 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1000 * 1000},
- {.frequency = 504 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1000 * 1000},
- {.frequency = 600 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1000 * 1000},
- {.frequency = 696 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1000 * 1000},
- {.frequency = 816 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1000 * 1000},
- {.frequency = 912 * 1000, .cpu_volt = 1450 * 1000, .logic_volt = 1000 * 1000},
- {.frequency = 1008 * 1000, .cpu_volt = 1500 * 1000, .logic_volt = 1000 * 1000},
-#else
- {.frequency = 216 * 1000, .cpu_volt = 850 * 1000, .logic_volt = 1000 * 1000},
- {.frequency = 312 * 1000, .cpu_volt = 900 * 1000, .logic_volt = 1000 * 1000},
- {.frequency = 408 * 1000, .cpu_volt = 950 * 1000, .logic_volt = 1000 * 1000},
- {.frequency = 504 * 1000, .cpu_volt = 1000 * 1000, .logic_volt = 1000 * 1000},
- {.frequency = 600 * 1000, .cpu_volt = 1100 * 1000, .logic_volt = 1000 * 1000},
- {.frequency = 696 * 1000, .cpu_volt = 1175 * 1000, .logic_volt = 1000 * 1000},
- {.frequency = 816 * 1000, .cpu_volt = 1250 * 1000, .logic_volt = 1000 * 1000},
- {.frequency = 912 * 1000, .cpu_volt = 1350 * 1000, .logic_volt = 1000 * 1000},
- {.frequency = 1008 * 1000, .cpu_volt = 1450 * 1000, .logic_volt = 1000 * 1000},
-#endif
-#if 0
- {.frequency = 1104 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 1200 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 1104 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 1248 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
-#endif
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- {.frequency = 266 * 1000, .index = 1100 * 1000},
- {.frequency = 400 * 1000, .index = 1275 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 300 * 1000, .index = 1100 * 1000},
- {.frequency = 400 * 1000, .index = 1100 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
-static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
-static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
-
-void __init board_clock_init(void)
-{
- rk2928_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
- dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
- printk("%s end\n", __func__);
-}
-
-
-MACHINE_START(RK2928, "RK2928board")
-.boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk2928_fixup,
- .reserve = &rk2928_reserve,
- .map_io = rk2928_map_io,
- .init_irq = rk2928_init_irq,
- .timer = &rk2928_timer,
- .init_machine = rk2928_board_init,
- MACHINE_END
+++ /dev/null
-#ifdef CONFIG_VIDEO_RK29
-#include <plat/rk_camera.h>
-/* Notes:
-
-Simple camera device registration:
-
- new_camera_device(sensor_name,\ // sensor name, it is equal to CONFIG_SENSOR_X
- face,\ // sensor face information, it can be back or front
- pwdn_io,\ // power down gpio configuration, it is equal to CONFIG_SENSOR_POWERDN_PIN_XX
- flash_attach,\ // sensor is attach flash or not
- mir,\ // sensor image mirror and flip control information
- i2c_chl,\ // i2c channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_IIC_ADAPTER_ID_X
- cif_chl) \ // cif channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_CIF_INDEX_X
-
-Comprehensive camera device registration:
-
- new_camera_device_ex(sensor_name,\
- face,\
- ori,\ // sensor orientation, it is equal to CONFIG_SENSOR_ORIENTATION_X
- pwr_io,\ // sensor power gpio configuration, it is equal to CONFIG_SENSOR_POWER_PIN_XX
- pwr_active,\ // sensor power active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- rst_io,\ // sensor reset gpio configuration, it is equal to CONFIG_SENSOR_RESET_PIN_XX
- rst_active,\ // sensor reset active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- pwdn_io,\
- pwdn_active,\ // sensor power down active level, is equal to CONFIG_SENSOR_POWERDNACTIVE_LEVEL_X
- flash_attach,\
- res,\ // sensor resolution, this is real resolution or resoltuion after interpolate
- mir,\
- i2c_chl,\
- i2c_spd,\ // i2c speed , 100000 = 100KHz
- i2c_addr,\ // the i2c slave device address for sensor
- cif_chl,\
- mclk)\ // sensor input clock rate, 24 or 48
-
-*/
-static struct rkcamera_platform_data new_camera[] = {
- new_camera_device(RK29_CAM_SENSOR_GC0308,
- front,
- RK2928_PIN3_PB3,
- 0,
- 0,
- 1,
- 0),
- new_camera_device_end
-};
-/*---------------- Camera Sensor Macro Define Begin ------------------------*/
-/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
-#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_OV5642 /* back camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_0 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 0
-#define CONFIG_SENSOR_CIF_INDEX_0 0
-#define CONFIG_SENSOR_ORIENTATION_0 90
-#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 INVALID_GPIO//RK2928_PIN3_PB3
-#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000
-
-#define CONFIG_SENSOR_01 RK29_CAM_SENSOR_OV5642 /* back camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_01 0x00
-#define CONFIG_SENSOR_CIF_INDEX_01 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 4
-#define CONFIG_SENSOR_ORIENTATION_01 90
-#define CONFIG_SENSOR_POWER_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_01 INVALID_GPIO//RK2928_PIN3_PB3
-#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_01 30000
-
-#define CONFIG_SENSOR_02 RK29_CAM_SENSOR_OV5640 /* back camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_02 0x00
-#define CONFIG_SENSOR_CIF_INDEX_02 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 4
-#define CONFIG_SENSOR_ORIENTATION_02 90
-#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_02 INVALID_GPIO//RK2928_PIN3_PB3
-#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000
-
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_GC0308 /* front camera sensor 0 */
-#define CONFIG_SENSOR_IIC_ADDR_1 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 1
-#define CONFIG_SENSOR_CIF_INDEX_1 0
-#define CONFIG_SENSOR_ORIENTATION_1 270
-#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_1 RK2928_PIN3_PB3
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000
-
-#define CONFIG_SENSOR_11 RK29_CAM_SENSOR_OV2659 /* front camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_11 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 3
-#define CONFIG_SENSOR_CIF_INDEX_11 0
-#define CONFIG_SENSOR_ORIENTATION_11 270
-#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_11 30000
-
-#define CONFIG_SENSOR_12 RK29_CAM_SENSOR_OV2659//RK29_CAM_SENSOR_OV2655 /* front camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_12 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 3
-#define CONFIG_SENSOR_CIF_INDEX_12 0
-#define CONFIG_SENSOR_ORIENTATION_12 270
-#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_12 30000
-
-
-#endif //#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk2928_camera.c"
-/*---------------- Camera Sensor Macro Define End ---------*/
-
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#define CONFIG_SENSOR_POWER_IOCTL_USR 0 //define this refer to your board layout
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
-
-static void rk_cif_power(int on)
-{
- struct regulator *ldo_18,*ldo_28;
- ldo_28 = regulator_get(NULL, "ldo7"); // vcc28_cif
- ldo_18 = regulator_get(NULL, "ldo1"); // vcc18_cif
- if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){
- printk("get cif ldo failed!\n");
- return;
- }
- if(on == 0){
- regulator_disable(ldo_28);
- regulator_put(ldo_28);
- regulator_disable(ldo_18);
- regulator_put(ldo_18);
- mdelay(500);
- }
- else{
- regulator_set_voltage(ldo_28, 2800000, 2800000);
- regulator_enable(ldo_28);
- // printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
- regulator_put(ldo_28);
-
- regulator_set_voltage(ldo_18, 1800000, 1800000);
- // regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(ldo_18);
- // printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
- regulator_put(ldo_18);
- }
-}
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- //#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
- rk_cif_power(on);
-}
-#endif
-
-#if CONFIG_SENSOR_RESET_IOCTL_USR
-static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
-static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-
-#if CONFIG_SENSOR_IIC_ADDR_0
-static struct reginfo_t rk_init_data_sensor_reg_0[] =
-{
- {0x0000, 0x00,0,0}
- };
-static struct reginfo_t rk_init_data_sensor_winseqreg_0[] ={
- {0x0000, 0x00,0,0}
- };
-#endif
-
-#if CONFIG_SENSOR_IIC_ADDR_1
-static struct reginfo_t rk_init_data_sensor_reg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_01
-static struct reginfo_t rk_init_data_sensor_reg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_02
-static struct reginfo_t rk_init_data_sensor_reg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_11
-static struct reginfo_t rk_init_data_sensor_reg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_12
-static struct reginfo_t rk_init_data_sensor_reg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] =
-{
- #if CONFIG_SENSOR_IIC_ADDR_0
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_0,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_1
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_1,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_01
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_01,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_02
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_02,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_11
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_11,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_12
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_12,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
-
- };
-#include "../../../drivers/media/video/rk2928_camera.c"
-
-#endif /* CONFIG_VIDEO_RK29 */
+++ /dev/null
-#include <mach/gpio.h>
-#include <plat/key.h>
-
-#define EV_ENCALL KEY_F4
-#define EV_MENU KEY_F1
-
-#define PRESS_LEV_LOW 1
-#define PRESS_LEV_HIGH 0
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK2928_PIN1_PA4,
- .active_low = PRESS_LEV_LOW,
- //.code_long_press = EV_ENCALL,
- .wakeup = 1,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .gpio = INVALID_GPIO,
- .adc_value = 1,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .gpio = INVALID_GPIO,
- .adc_value = 512,
- .active_low = PRESS_LEV_LOW,
- },
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = 1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
+++ /dev/null
-/* arch/arm/mach-rk2928/board-rk2928-fpga.c
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-#include <mach/dvfs.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <linux/fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/mfd/tps65910.h>
-#include <linux/regulator/act8931.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-#if defined(CONFIG_HDMI_RK30)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-
-#ifdef CONFIG_SND_SOC_RK2928
-#include "../../../sound/soc/codecs/rk2928_codec.h"
-#endif
-
-#include "board-rk2928-a720-camera.c"
-#include "board-rk2928-a720-key.c"
-
-#ifdef CONFIG_THREE_FB_BUFFER
-#define RK30_FB0_MEM_SIZE 12*SZ_1M
-#else
-#define RK30_FB0_MEM_SIZE 8*SZ_1M
-#endif
-
-int __sramdata g_pmic_type = 0;
-
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-#define PWM_ID 0
-#define PWM_MUX_NAME GPIO0D2_PWM_0_NAME
-#define PWM_MUX_MODE GPIO0D_PWM_0
-#define PWM_MUX_MODE_GPIO GPIO0D_GPIO0D2
-#define PWM_GPIO RK2928_PIN0_PD2
-#define PWM_EFFECT_VALUE 0
-
-#if defined(CONFIG_MACH_RK2926_M713)
-//#define LCD_DISP_ON_PIN
-#else
-#define LCD_DISP_ON_PIN
-#endif
-
-#ifdef LCD_DISP_ON_PIN
-
-#define BL_EN_PIN RK2928_PIN1_PB0
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
-#ifdef LCD_DISP_ON_PIN
- // rk30_mux_api_set(BL_EN_MUX_NAME, BL_EN_MUX_MODE);
-
- ret = gpio_request(BL_EN_PIN, NULL);
- if (ret != 0) {
- gpio_free(BL_EN_PIN);
- }
-
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0;
-#ifdef LCD_DISP_ON_PIN
- gpio_set_value(BL_EN_PIN, !BL_EN_VALUE);
- gpio_free(BL_EN_PIN);
-#endif
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret = 0;
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- if (gpio_request(PWM_GPIO, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- #if defined(CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- {
- gpio_direction_output(PWM_GPIO, GPIO_LOW);
- }
- #endif
- #if defined(CONFIG_REGULATOR_ACT8931)
- if(pmic_is_act8931())
- {
- gpio_direction_output(PWM_GPIO, GPIO_HIGH);
- }
- #endif
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, !BL_EN_VALUE);
-#endif
-
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- gpio_free(PWM_GPIO);
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
-#ifdef LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, 1);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .min_brightness = 80,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-#endif
-
-#ifdef CONFIG_FB_ROCKCHIP
-
-#define LCD_MUX_NAME GPIO0C2_UART0_RTSN_NAME
-#define LCD_GPIO_MODE GPIO0C_GPIO0C2
-
-#ifdef CONFIG_MACH_RK2926_M713
-#define LCD_EN RK2928_PIN1_PB3
-#else
-#define LCD_EN RK2928_PIN0_PC2
-#endif
-#define LCD_EN_VALUE GPIO_LOW
-
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
-
- rk30_mux_api_set(LCD_MUX_NAME, LCD_GPIO_MODE);
-
- ret = gpio_request(LCD_EN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_EN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_EN, LCD_EN_VALUE); //disable
- }
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
-
- #if 0//defined(CONFIG_REGULATOR_ACT8931)
- if(pmic_is_act8931())
- {
- struct regulator *ldo;
- ldo = regulator_get(NULL, "act_ldo4"); //vcc_lcd
- regulator_disable(ldo);
- regulator_put(ldo);
- udelay(100);
- }
- #endif
- gpio_set_value(LCD_EN, !LCD_EN_VALUE);
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- #if 0//defined(CONFIG_REGULATOR_ACT8931)
- if(pmic_is_act8931())
- {
- struct regulator *ldo;
- ldo = regulator_get(NULL, "act_ldo4"); //vcc_lcd
- regulator_enable(ldo);
- regulator_put(ldo);
- udelay(100);
- msleep(300); // wait for powering on LED circuit
- }
- #endif
-
- gpio_set_value(LCD_EN, LCD_EN_VALUE);
- return 0;
-}
-
-#if defined(CONFIG_LCDC_RK2928)
-struct rk29fb_info lcdc_screen_info = {
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-
-//LCDC
-#ifdef CONFIG_LCDC_RK2928
-static struct resource resource_lcdc[] = {
- [0] = {
- .name = "lcdc reg",
- .start = RK2928_LCDC_PHYS,
- .end = RK2928_LCDC_PHYS + RK2928_LCDC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc irq",
- .start = IRQ_LCDC,
- .end = IRQ_LCDC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc = {
- .name = "rk2928-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc),
- .resource = resource_lcdc,
- .dev = {
- .platform_data = &lcdc_screen_info,
- },
-};
-#endif
-
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-
-#if defined(CONFIG_TOUCHSCREEN_SITRONIX_A720)
-
-#define TOUCH_RESET_PIN RK2928_PIN1_PA3
-#ifdef CONFIG_MACH_RK2926_M713
-#define TOUCH_INT_PIN RK2928_PIN1_PB0
-#else
-#define TOUCH_INT_PIN RK2928_PIN1_PB3
-#endif
-int ft5306_init_platform_hw(void)
-{
-
- //printk("ft5306_init_platform_hw\n");
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("ft5306_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("ift5306_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, GPIO_HIGH);
- mdelay(10);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- mdelay(10);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- msleep(300);
- return 0;
-
-}
-
-struct ft5x0x_platform_data sitronix_info = {
- .model = 5007,
- .init_platform_hw= ft5306_init_platform_hw,
-};
-
-#endif
-
-
-/*MMA7660 gsensor*/
-#if defined (CONFIG_GS_MMA7660)
-#ifdef CONFIG_MACH_RK2926_M713
-#define MMA7660_INT_PIN RK2928_PIN1_PB2
-#else
-#define MMA7660_INT_PIN RK2928_PIN1_PB1
-#endif
-
-static int mma7660_init_platform_hw(void)
-{
-#ifdef CONFIG_MACH_RK2926_M713
- rk30_mux_api_set(GPIO1B2_SPI_RXD_UART1_SIN_NAME, GPIO1B_GPIO1B2);
-#else
- rk30_mux_api_set(GPIO1B1_SPI_TXD_UART1_SOUT_NAME, GPIO1B_GPIO1B1);
-#endif
-
- return 0;
-}
-
-static struct sensor_platform_data mma7660_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma7660_init_platform_hw,
- .orientation = {-1, 0, 0, 0, 1, 0, 0, 0, -1},
-};
-#endif
-
-
-#if CONFIG_RK30_PWM_REGULATOR
-static int pwm_voltage_map[] = {
- 950000,975000,1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000, 1375000, 1400000
-};
-
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_core",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] =
-{
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
-#ifdef CONFIG_MACH_RK2926_M713
- .pwm_id = 1,
- .pwm_gpio = RK2928_PIN0_PD3,
- .pwm_iomux_name = GPIO0D3_PWM_1_NAME,
- .pwm_iomux_pwm = GPIO0D_PWM_1,
- .pwm_iomux_gpio = GPIO0D_GPIO0D3,
-#else
- .pwm_id = 2,
- .pwm_gpio = RK2928_PIN0_PD4,
- .pwm_iomux_name = GPIO0D4_PWM_2_NAME,
- .pwm_iomux_pwm = GPIO0D_PWM_2,
- .pwm_iomux_gpio = GPIO0D_GPIO0D4,
-#endif
- .pwm_voltage = 1200000,
- .suspend_voltage = 1050000,
- .min_uV = 950000,
- .max_uV = 1400000,
- .coefficient = 504, //50.4%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-#endif
-
-/***********************************************************
-* usb wifi
-************************************************************/
-#if defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU)
-
-static void rkusb_wifi_power(int on) {
- struct regulator *ldo = NULL;
-
-#if defined(CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910()) {
- ldo = regulator_get(NULL, "vmmc"); //vccio_wl
- }
-#endif
-#if defined(CONFIG_REGULATOR_ACT8931)
- if(pmic_is_act8931()) {
- ldo = regulator_get(NULL, "act_ldo4"); //vccio_wl
- }
-#endif
-
- if(on) {
- regulator_enable(ldo);
- printk("%s: vccio_wl enable\n", __func__);
- } else {
- printk("%s: vccio_wl disable\n", __func__);
- regulator_disable(ldo);
- }
-
- regulator_put(ldo);
- udelay(100);
-}
-
-#endif
-
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and sdio.noted by xbw at 2012-03-05
-**************************************************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "board-rk2928-sdk-sdmmc.c"
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
-#define SDMMC0_WRITE_PROTECT_PIN RK2928_PIN1_PA7 //According to your own project to set the value of write-protect-pin.
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
-#define SDMMC1_WRITE_PROTECT_PIN RK2928_PIN0_PD5 //According to your own project to set the value of write-protect-pin.
-#endif
-
-#define RK29SDK_WIFI_SDIO_CARD_DETECT_N RK2928_PIN0_PB2
-
-#define RK29SDK_SD_CARD_DETECT_N RK2928_PIN2_PA7 //According to your own project to set the value of card-detect-pin.
-#define RK29SDK_SD_CARD_INSERT_LEVEL GPIO_LOW // set the voltage of insert-card. Please pay attention to the default setting.
-
-
-#endif //endif ---#ifdef CONFIG_SDMMC_RK29
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
-#if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- rk30_mux_api_set(GPIO1C1_MMC0_DETN_NAME, GPIO1C_GPIO1C1);
- // gpio_request(RK29SDK_SD_CARD_DETECT_N, "sd-detect");
- // gpio_direction_output(RK29SDK_SD_CARD_DETECT_N,GPIO_HIGH);//set mmc0-data1 to high.
-#else
- rk30_mux_api_set(GPIO1C1_MMC0_DETN_NAME, GPIO1C_MMC0_DETN);
-#endif
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- .detect_irq = RK29SDK_SD_CARD_DETECT_N,
- .insert_card_level = RK29SDK_SD_CARD_INSERT_LEVEL,
-#else
- .detect_irq = INVALID_GPIO,
-#endif
-
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
-#else
- .write_prt = INVALID_GPIO,
-#endif
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SND_SOC_RK2928
-static int hpctl_io_init(void)
-{
- int ret=0;
- return ret;
-}
-
-struct rk2928_codec_pdata rk2928_codec_pdata_info={
- .hpctl = INVALID_GPIO,
- .hpctl_io_init = hpctl_io_init,
-};
-
-static struct resource resources_acodec[] = {
- {
- .start = RK2928_ACODEC_PHYS,
- .end = RK2928_ACODEC_PHYS + RK2928_ACODEC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = RK2928_PIN1_PA0,
- .end = RK2928_PIN1_PA0,
- .flags = IORESOURCE_IO,
- },
-};
-
-static struct platform_device device_acodec = {
- .name = "rk2928-codec",
- .id = -1,
- .num_resources = ARRAY_SIZE(resources_acodec),
- .resource = resources_acodec,
- .dev = {
- .platform_data = &rk2928_codec_pdata_info,
- }
-};
-#endif
-
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = INVALID_GPIO,
- .batt_low_pin = INVALID_GPIO,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = INVALID_GPIO,
-};
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_FB_ROCKCHIP
- &device_fb,
-#endif
-#ifdef CONFIG_LCDC_RK2928
- &device_lcdc,
-#endif
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- &rk29_device_backlight,
-#endif
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_SND_SOC_RK2928
- &device_acodec,
-#endif
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
- &rk30_device_adc_battery,
-#endif
-};
-//i2c
-#ifdef CONFIG_I2C0_RK30
-#ifdef CONFIG_MFD_TPS65910
-#define TPS65910_HOST_IRQ RK2928_PIN1_PB2
-#define PMU_POWER_SLEEP RK2928_PIN1_PA1
-
-static struct pmu_info tps65910_dcdc_info[] = {
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vdd2", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vio", //vcc_io
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
-
-};
-static struct pmu_info tps65910_ldo_info[] = {
- #if defined(CONFIG_MACH_RK2928_TB) || defined(CONFIG_MACH_RK2926_TB)
- {
- .name = "vpll", //vcc25
- .min_uv = 2500000,
- .max_uv = 2500000,
- },
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "vdac", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- #else
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 1500000,
- .max_uv = 1500000,
- },
-
- {
- .name = "vdig2", //vdd11
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vaux1", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "vaux2", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vaux33", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vmmc", //
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- #endif
- };
-
-#include "board-rk2928-sdk-tps65910.c"
-#endif
-
-#ifdef CONFIG_REGULATOR_ACT8931
-#ifdef CONFIG_MACH_RK2926_M713
-#define ACT8931_HOST_IRQ RK2928_PIN1_PB1
-#else
-#define ACT8931_HOST_IRQ RK2928_PIN1_PB2
-#endif
-#if defined(CONFIG_MACH_RK2928_SDK)
-#define ACT8931_CHGSEL_PIN RK2928_PIN0_PD0
-#else
-#define ACT8931_CHGSEL_PIN RK2928_PIN1_PA1
-#endif
-
-static struct pmu_info act8931_dcdc_info[] = {
- {
- .name = "act_dcdc1", //vcc_io
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_dcdc2", //ddr
- .min_uv = 1500000,
- .max_uv = 1500000,
- },
- {
- .name = "vdd_cpu", //vdd_arm
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
-
-};
-static struct pmu_info act8931_ldo_info[] = {
- {
- .name = "act_ldo1", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "act_ldo2", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo3", //vcca30
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
- {
- .name = "act_ldo4", //vcc_wl
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
-};
-#include "board-rk2928-sdk-act8931.c"
-#endif
-
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-#if defined (CONFIG_REGULATOR_ACT8931)
- {
- .type = "act8931",
- .addr = 0x5b,
- .flags = 0,
- .irq = ACT8931_HOST_IRQ,
- .platform_data=&act8931_data,
- },
-#endif
-#ifdef CONFIG_MACH_RK2926_M713
-#if defined (CONFIG_RTC_HYM8563)
- {
- .type = "rtc_hym8563",
- .addr = 0x51,
- .flags = 0,
- .irq = RK2928_PIN1_PA5,
- },
-#endif
-#endif
-};
-#endif
-
-#ifdef CONFIG_MACH_RK2926_M713
-int __sramdata gpio0d3_iomux,gpio0d3_do,gpio0d3_dir;
-#else
-int __sramdata gpio0d4_iomux,gpio0d4_do,gpio0d4_dir;
-#endif
-
-#define gpio0_readl(offset) readl_relaxed(RK2928_GPIO0_BASE + offset)
-#define gpio0_writel(v, offset) do { writel_relaxed(v, RK2928_GPIO0_BASE + offset); dsb(); } while (0)
-
-void __sramfunc rk30_pwm_logic_suspend_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
-
-#ifdef CONFIG_MACH_RK2926_M713
- sram_udelay(10000);
- gpio0d3_iomux = readl_relaxed(GRF_GPIO0D_IOMUX);
- gpio0d3_do = gpio0_readl(GPIO_SWPORTA_DR);
- gpio0d3_dir = gpio0_readl(GPIO_SWPORTA_DDR);
-
- writel_relaxed((gpio0d3_iomux |(1<<22)) & (~(1<<6)), GRF_GPIO0D_IOMUX);
- gpio0_writel(gpio0d3_dir |(1<<27), GPIO_SWPORTA_DDR);
- gpio0_writel(gpio0d3_do |(1<<27), GPIO_SWPORTA_DR);
-#else
-// int gpio0d7_iomux,gpio0d7_do,gpio0d7_dir,gpio0d7_en;
- sram_udelay(10000);
- gpio0d4_iomux = readl_relaxed(GRF_GPIO0D_IOMUX);
- gpio0d4_do = gpio0_readl(GPIO_SWPORTA_DR);
- gpio0d4_dir = gpio0_readl(GPIO_SWPORTA_DDR);
-
- writel_relaxed((gpio0d4_iomux |(1<<24)) & (~(1<<8)), GRF_GPIO0D_IOMUX);
- gpio0_writel(gpio0d4_dir |(1<<28), GPIO_SWPORTA_DDR);
- gpio0_writel(gpio0d4_do |(1<<28), GPIO_SWPORTA_DR);
-#endif
-
-#endif
-}
-void __sramfunc rk30_pwm_logic_resume_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
-#ifdef CONFIG_MACH_RK2926_M713
- writel_relaxed((1<<22)|gpio0d3_iomux, GRF_GPIO0D_IOMUX);
- gpio0_writel(gpio0d3_dir, GPIO_SWPORTA_DDR);
- gpio0_writel(gpio0d3_do, GPIO_SWPORTA_DR);
- sram_udelay(10000);
-#else
- writel_relaxed((1<<24)|gpio0d4_iomux, GRF_GPIO0D_IOMUX);
- gpio0_writel(gpio0d4_dir, GPIO_SWPORTA_DDR);
- gpio0_writel(gpio0d4_do, GPIO_SWPORTA_DR);
- sram_udelay(10000);
-#endif
-
-#endif
-
-}
-extern void pwm_suspend_voltage(void);
-extern void pwm_resume_voltage(void);
-void rk30_pwm_suspend_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_suspend_voltage();
-#endif
-}
-void rk30_pwm_resume_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_resume_voltage();
-#endif
-}
-
-void __sramfunc board_pmu_suspend(void)
-{
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_suspend();
- #endif
-}
-void __sramfunc board_pmu_resume(void)
-{
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_resume();
- #endif
-}
-
-#ifdef CONFIG_I2C1_RK30
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_GS_MMA7660)
- {
- .type = "gs_mma7660",
- .addr = 0x4c,
- .flags = 0,
- .irq = MMA7660_INT_PIN,
- .platform_data = &mma7660_info,
- },
-#endif
-
-};
-#endif
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-#if defined (CONFIG_TOUCHSCREEN_SITRONIX_A720)
-{
- .type ="sitronix",
-#ifdef CONFIG_MACH_RK2926_M713
- .addr = 0x60,
-#else
- .addr = 0x38,
-#endif
- .flags = 0,
- .irq = TOUCH_INT_PIN,
- .platform_data = &sitronix_info,
-},
-#endif
-};
-#endif
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- //set iomux (gpio) here
-
- return 0;
-}
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(4, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-
-#define POWER_ON_PIN RK2928_PIN1_PA2 //power_hold
-#if defined(CONFIG_REGULATOR_ACT8931)
-extern int act8931_charge_det ;
-#endif
-static void rk2928_pm_power_off(void)
-{
- printk(KERN_ERR "rk2928_pm_power_off start...\n");
-
- #if defined(CONFIG_REGULATOR_ACT8931)
- if(pmic_is_act8931())
- {
- if(act8931_charge_det)
- arm_pm_restart(0, NULL);
- act8931_device_shutdown();
- }
- #endif
-
- #if defined(CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- {
- tps65910_device_shutdown();//tps65910 shutdown
- }
- #endif
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
-
-};
-
-static void __init rk2928_board_init(void)
-{
- gpio_request(POWER_ON_PIN, "poweronpin");
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
- pm_power_off = rk2928_pm_power_off;
-
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
-
-}
-
-static void __init rk2928_reserve(void)
-{
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0", RK30_FB0_MEM_SIZE);
- resource_fb[0].end = resource_fb[0].start + RK30_FB0_MEM_SIZE - 1;
-#endif
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
- board_mem_reserved();
-}
-/**
- * dvfs_cpu_logic_table: table for arm and logic dvfs
- * @frequency : arm frequency
- * @cpu_volt : arm voltage depend on frequency
- * @logic_volt : logic voltage arm requests depend on frequency
- * comments : min arm/logic voltage
- */
-static struct dvfs_arm_table dvfs_cpu_logic_table[] = {
-#if defined(CONFIG_MACH_RK2926_M713)
- {.frequency = 216 * 1000, .cpu_volt = 850 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 312 * 1000, .cpu_volt = 900 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 408 * 1000, .cpu_volt = 950 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 504 * 1000, .cpu_volt = 1000 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 600 * 1000, .cpu_volt = 1100 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 696 * 1000, .cpu_volt = 1175 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 816 * 1000, .cpu_volt = 1250 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 912 * 1000, .cpu_volt = 1350 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 1008 * 1000, .cpu_volt = 1450 * 1000, .logic_volt = 1200 * 1000},
-#else
- {.frequency = 216 * 1000, .cpu_volt = 850 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 312 * 1000, .cpu_volt = 900 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 408 * 1000, .cpu_volt = 975 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 504 * 1000, .cpu_volt = 1050 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 600 * 1000, .cpu_volt = 1150 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 696 * 1000, .cpu_volt = 1225 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 816 * 1000, .cpu_volt = 1325 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 912 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 1008 * 1000, .cpu_volt = 1475 * 1000, .logic_volt = 1200 * 1000},
-#endif
-#if 0
- {.frequency = 1104 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 1200 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 1104 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 1248 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
-#endif
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- {.frequency = 266 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1275 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1125 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
-static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
-static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
-
-void __init board_clock_init(void)
-{
- rk2928_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
- dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
- //dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
- printk("%s end\n", __func__);
-}
-
-
-MACHINE_START(RK2928, "RK2928board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk2928_fixup,
- .reserve = &rk2928_reserve,
- .map_io = rk2928_map_io,
- .init_irq = rk2928_init_irq,
- .timer = &rk2928_timer,
- .init_machine = rk2928_board_init,
-MACHINE_END
+++ /dev/null
-#include <mach/config.h>
-#ifdef CONFIG_VIDEO_RK29
-#include <plat/rk_camera.h>
-/* Notes:
-
-Simple camera device registration:
-
- new_camera_device(sensor_name,\ // sensor name, it is equal to CONFIG_SENSOR_X
- face,\ // sensor face information, it can be back or front
- pwdn_io,\ // power down gpio configuration, it is equal to CONFIG_SENSOR_POWERDN_PIN_XX
- flash_attach,\ // sensor is attach flash or not
- mir,\ // sensor image mirror and flip control information
- i2c_chl,\ // i2c channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_IIC_ADAPTER_ID_X
- cif_chl) \ // cif channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_CIF_INDEX_X
-
-Comprehensive camera device registration:
-
- new_camera_device_ex(sensor_name,\
- face,\
- ori,\ // sensor orientation, it is equal to CONFIG_SENSOR_ORIENTATION_X
- pwr_io,\ // sensor power gpio configuration, it is equal to CONFIG_SENSOR_POWER_PIN_XX
- pwr_active,\ // sensor power active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- rst_io,\ // sensor reset gpio configuration, it is equal to CONFIG_SENSOR_RESET_PIN_XX
- rst_active,\ // sensor reset active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- pwdn_io,\
- pwdn_active,\ // sensor power down active level, is equal to CONFIG_SENSOR_POWERDNACTIVE_LEVEL_X
- flash_attach,\
- res,\ // sensor resolution, this is real resolution or resoltuion after interpolate
- mir,\
- i2c_chl,\
- i2c_spd,\ // i2c speed , 100000 = 100KHz
- i2c_addr,\ // the i2c slave device address for sensor
- cif_chl,\
- mclk)\ // sensor input clock rate, 24 or 48
-
-*/
-static struct rkcamera_platform_data new_camera[] = {
- new_camera_device_end
-};
-/*---------------- Camera Sensor Macro Define Begin ------------------------*/
-/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
-#define CONFIG_SENSOR_0 BACK_SENSOR_0 /* back camera sensor 0 */
-#define CONFIG_SENSOR_IIC_ADDR_0 BACK_SENSOR_0_ADDR
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 0
-#define CONFIG_SENSOR_CIF_INDEX_0 0
-#define CONFIG_SENSOR_ORIENTATION_0 90
-#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000
-
-#define CONFIG_SENSOR_01 BACK_SENSOR_1 /* back camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_01 BACK_SENSOR_1_ADDR
-#define CONFIG_SENSOR_CIF_INDEX_01 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 0
-#define CONFIG_SENSOR_ORIENTATION_01 90
-#define CONFIG_SENSOR_POWER_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_01 30000
-
-#define CONFIG_SENSOR_02 BACK_SENSOR_2 /* back camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_02 BACK_SENSOR_2_ADDR
-#define CONFIG_SENSOR_CIF_INDEX_02 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 0
-#define CONFIG_SENSOR_ORIENTATION_02 90
-#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000
-
-#define CONFIG_SENSOR_1 FRONT_SENSOR_0 /* front camera sensor 0 */
-#define CONFIG_SENSOR_IIC_ADDR_1 FRONT_SENSOR_0_ADDR
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 0
-#define CONFIG_SENSOR_CIF_INDEX_1 0
-#define CONFIG_SENSOR_ORIENTATION_1 270
-#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000
-
-#define CONFIG_SENSOR_11 FRONT_SENSOR_1 /* front camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_11 FRONT_SENSOR_1_ADDR
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 0
-#define CONFIG_SENSOR_CIF_INDEX_11 0
-#define CONFIG_SENSOR_ORIENTATION_11 270
-#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_11 30000
-
-#define CONFIG_SENSOR_12 FRONT_SENSOR_2 /* front camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_12 FRONT_SENSOR_2_ADDR
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 0
-#define CONFIG_SENSOR_CIF_INDEX_12 0
-#define CONFIG_SENSOR_ORIENTATION_12 270
-#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_12 30000
-
-
-#endif //#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk2928_camera.c"
-/*---------------- Camera Sensor Macro Define End ---------*/
-
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#define CONFIG_SENSOR_POWER_IOCTL_USR 0 //define this refer to your board layout
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
-
-static void rk_cif_power(int on)
-{
- struct regulator *ldo_18,*ldo_28;
- ldo_28 = regulator_get(NULL, "ldo7"); // vcc28_cif
- ldo_18 = regulator_get(NULL, "ldo1"); // vcc18_cif
- if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){
- printk("get cif ldo failed!\n");
- return;
- }
- if(on == 0){
- while(regulator_is_enabled(ldo_28)>0)
- regulator_disable(ldo_28);
- regulator_put(ldo_28);
- while(regulator_is_enabled(ldo_18)>0)
- regulator_disable(ldo_18);
- regulator_put(ldo_18);
- mdelay(500);
- }
- else{
- regulator_set_voltage(ldo_28, 2800000, 2800000);
- regulator_enable(ldo_28);
- // printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
- regulator_put(ldo_28);
-
- regulator_set_voltage(ldo_18, 1800000, 1800000);
- // regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(ldo_18);
- // printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
- regulator_put(ldo_18);
- }
-}
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- //#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
- rk_cif_power(on);
-}
-#endif
-
-#if CONFIG_SENSOR_RESET_IOCTL_USR
-static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
-static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-
-#if CONFIG_SENSOR_IIC_ADDR_0
-static struct reginfo_t rk_init_data_sensor_reg_0[] =
-{
- {0x0000, 0x00,0,0}
- };
-static struct reginfo_t rk_init_data_sensor_winseqreg_0[] ={
- {0x0000, 0x00,0,0}
- };
-#endif
-
-#if CONFIG_SENSOR_IIC_ADDR_1
-static struct reginfo_t rk_init_data_sensor_reg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_01
-static struct reginfo_t rk_init_data_sensor_reg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_02
-static struct reginfo_t rk_init_data_sensor_reg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_11
-static struct reginfo_t rk_init_data_sensor_reg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_12
-static struct reginfo_t rk_init_data_sensor_reg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] =
-{
- #if CONFIG_SENSOR_IIC_ADDR_0
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_0,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_1
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_1,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_01
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_01,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_02
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_02,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_11
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_11,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_12
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_12,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
-
- };
-#include "../../../drivers/media/video/rk2928_camera.c"
-
-#endif /* CONFIG_VIDEO_RK29 */
-#ifdef CONFIG_RK_CONFIG
-static int __init cam_board_init(void)
-{
- int ret = check_cam_param();
-
- if(ret < 0)
- return ret;
-
- camera_set_platform_param(back_cam_id,back_cam_i2c,get_port_config(back_cam_pwr).gpio);
- camera_set_platform_param(front_cam_id,front_cam_i2c,get_port_config(front_cam_pwr).gpio);
-
- return ret;
-}
-#else
-static int __init cam_board_init(void)
-{
-
- return 0;
-}
-#endif
-
-
+++ /dev/null
-#if 1
-#define CONFIG_ERR(v, name) do { printk("%s: Invalid parameter: %s(%d)\n", __func__, (name), (v)); } while(0)
-#else
-#define CONFIG_ERR(v, name)
-#endif
-#include <mach/config.h>
-int __sramdata g_pmic_type = 0;
-
-struct pwm_io_config{
- int id;
- int gpio;
- char *mux_name;
- unsigned int io_mode;
- unsigned int pwm_mode;
-};
-static struct pwm_io_config pwm_cfg[] = {
- {
- .id = 0,
- .gpio = RK2928_PIN0_PD2,
- .mux_name = GPIO0D2_PWM_0_NAME,
- .io_mode = GPIO0D_GPIO0D2,
- .pwm_mode = GPIO0D_PWM_0,
- },
- {
- .id = 1,
- .gpio = RK2928_PIN0_PD3,
- .mux_name = GPIO0D3_PWM_1_NAME,
- .io_mode = GPIO0D_GPIO0D3,
- .pwm_mode = GPIO0D_PWM_1,
- },
- {
- .id = 2,
- .gpio = RK2928_PIN0_PD4,
- .mux_name = GPIO0D4_PWM_2_NAME,
- .io_mode = GPIO0D_GPIO0D4,
- .pwm_mode = GPIO0D_PWM_2,
- },
-};
-
-#define TPS65910_HOST_IRQ INVALID_GPIO
-static struct pmu_info tps65910_dcdc_info[] = {
- {.name = "vdd_cpu"},
- {.name = "vdd2"},
- {.name = "vdd3"},
- {.name = "vio"},
-};
-static struct pmu_info tps65910_ldo_info[] = {
- {.name = "vdig1"},
- {.name = "vdig2"},
- {.name = "vaux1"},
- {.name = "vaux2"},
- {.name = "vaux33"},
- {.name = "vmmc"},
- {.name = "vdac"},
- {.name = "vpll"},
-};
-static struct pmu_info act8931_dcdc_info[] = {
- {.name = "act_dcdc1"},
- {.name = "act_dcdc2"},
- {.name = "vdd_cpu"},
-};
-static struct pmu_info act8931_ldo_info[] = {
- {.name = "act_ldo1"},
- {.name = "act_ldo2"},
- {.name = "act_ldo3"},
- {.name = "act_ldo4"},
-};
-
-/*************************************** parameter ******************************************/
-/* keyboard */
-uint key_adc = DEF_KEY_ADC;
-module_param(key_adc, uint, 0644);
-uint key_val_size = 7;
-uint key_val[] = {DEF_PLAY_KEY, DEF_VOLDN_KEY, DEF_VOLUP_KEY, DEF_MENU_KEY, DEF_ESC_KEY, DEF_HOME_KEY, DEF_CAM_KEY};
-module_param_array(key_val, uint, &key_val_size, 0644);
-
-static inline int check_key_param(void)
-{
- return 0;
-}
-/* backlight */
-static uint bl_pwm = DEF_BL_PWM;
-module_param(bl_pwm, uint, 0644);
-static uint bl_ref = DEF_BL_REF;
-module_param(bl_ref, uint, 0644);
-static uint bl_min = DEF_BL_MIN;
-module_param(bl_min, uint, 0644);
-static int bl_en = DEF_BL_EN;
-module_param(bl_en, int, 0644);
-
-static inline int check_bl_param(void)
-{
- if(bl_pwm < 0 || bl_pwm >= ARRAY_SIZE(pwm_cfg)){
- CONFIG_ERR(bl_pwm, "bl_pwm");
- return -EINVAL;
- }
- if(bl_ref != 0 && bl_ref != 1){
- CONFIG_ERR(bl_ref, "bl_ref");
- return -EINVAL;
- }
- if(bl_min > 100){
- CONFIG_ERR(bl_min, "bl_min");
- return -EINVAL;
- }
- return 0;
-}
-/* usb */
-static int otg_drv = DEF_OTG_DRV;
-module_param(otg_drv, int, 0644);
-static int host_drv = DEF_HOST_DRV;
-module_param(host_drv, int, 0644);
-static inline int check_usb_param(void)
-{
- return 0;
-}
-int inline otg_drv_init(int on)
-{
- if(otg_drv == -1){
- return 0;
- }else if (get_port_config(otg_drv).gpio == RK2928_PIN3_PC1){
- rk30_mux_api_set(GPIO3C1_OTG_DRVVBUS_NAME, GPIO3C_OTG_DRVVBUS);
- return 0;
- }else
- return port_output_init(otg_drv, on, "otg_drv");
-}
-void inline otg_drv_on(void)
-{
- port_output_on(otg_drv);
-}
-void inline otg_drv_off(void)
-{
- port_output_off(otg_drv);
-}
-int inline host_drv_init(int on)
-{
- return port_output_init(host_drv, on, "host_drv");
-}
-void inline host_drv_on(void)
-{
- port_output_on(host_drv);
-}
-void inline host_drv_off(void)
-{
- port_output_off(host_drv);
-}
-/* lcd */
-static int lcd_cabc = DEF_LCD_CABC;
-module_param(lcd_cabc, int, 0644);
-static int lcd_en = DEF_LCD_EN;
-module_param(lcd_en, int, 0644);
-static int lcd_std = DEF_LCD_STD;
-module_param(lcd_std, int, 0644);
-
-static inline int check_lcd_param(void)
-{
- return 0;
-
-}
-
-/* gsensor */
-static int gs_type = DEF_GS_TYPE;
-module_param(gs_type, int, 0644);
-static int gs_i2c = DEF_GS_I2C;
-module_param(gs_i2c, int, 0644);
-static int gs_addr = DEF_GS_ADDR;
-module_param(gs_addr, int, 0644);
-static int gs_irq = DEF_GS_IRQ;
-module_param(gs_irq, int, 0644);
-static int gs_pwr = DEF_GS_PWR;
-module_param(gs_pwr, int, 0644);
-static int gs_orig[9] = DEF_GS_ORIG;
-module_param_array(gs_orig, int, NULL, 0644);
-
-static inline int check_gs_param(void)
-{
- int i;
-
- if(gs_type == GS_TYPE_NONE)
- return 0;
- if(gs_type < GS_TYPE_NONE || gs_type > GS_TYPE_MAX){
- CONFIG_ERR(gs_type, "gs_type");
- return -EINVAL;
- }
- if(gs_i2c < 0 || gs_i2c > 3){
- CONFIG_ERR(gs_i2c, "gs_i2c");
- return -EINVAL;
- }
- if(gs_addr < 0 || gs_addr > 0x7f){
- CONFIG_ERR(gs_i2c, "gs_addr");
- return -EINVAL;
- }
- for(i = 0; i < 9; i++){
- if(gs_orig[i] != 1 && gs_orig[i] != 0 && gs_orig[i] != -1){
- CONFIG_ERR(gs_orig[i], "gs_orig[x]");
- return -EINVAL;
- }
- }
- return 0;
-}
-/* lsensor */
-static int ls_type = DEF_LS_TYPE;
-module_param(ls_type, int, 0644);
-static int ls_i2c = DEF_LS_I2C;
-module_param(ls_i2c, int, 0644);
-static int ls_addr = DEF_LS_ADDR;
-module_param(ls_addr, int, 0644);
-static int ls_irq = DEF_LS_IRQ;
-module_param(ls_irq, int, 0644);
-static int ls_pwr = DEF_LS_PWR;
-module_param(ls_pwr, int, 0644);
-
-static inline int check_ls_param(void)
-{
- if(ls_type == LS_TYPE_NONE)
- return 0;
- if(ls_type < LS_TYPE_NONE || ls_type > LS_TYPE_MAX){
- CONFIG_ERR(ls_type, "ls_type");
- return -EINVAL;
- }
- if(ls_i2c < 0 || ls_i2c > 3){
- CONFIG_ERR(ls_i2c, "ls_i2c");
- return -EINVAL;
- }
- if(ls_addr < 0 || ls_addr > 0x7f){
- CONFIG_ERR(ls_i2c, "ls_addr");
- return -EINVAL;
- }
- return 0;
-}
-
-
-/* psensor */
-static int ps_type = DEF_PS_TYPE;
-module_param(ps_type, int, 0644);
-static int ps_i2c = DEF_PS_I2C;
-module_param(ps_i2c, int, 0644);
-static int ps_addr = DEF_PS_ADDR;
-module_param(ps_addr, int, 0644);
-static int ps_irq = DEF_PS_IRQ;
-module_param(ps_irq, int, 0644);
-static int ps_pwr = DEF_PS_PWR;
-module_param(ps_pwr, int, 0644);
-
-static inline int check_ps_param(void)
-{
- if(ps_type == PS_TYPE_NONE)
- return 0;
- if(ps_type < PS_TYPE_NONE || ps_type > PS_TYPE_MAX){
- CONFIG_ERR(ps_type, "ps_type");
- return -EINVAL;
- }
- if(ps_i2c < 0 || ps_i2c > 3){
- CONFIG_ERR(ps_i2c, "ps_i2c");
- return -EINVAL;
- }
- if(ps_addr < 0 || ps_addr > 0x7f){
- CONFIG_ERR(ps_i2c, "ps_addr");
- return -EINVAL;
- }
- return 0;
-}
-/* camera */
-static int front_cam_i2c = DEF_FRONT_CAM_I2C;
-module_param(front_cam_i2c, int, 0644);
-static int front_cam_id = DEF_FRONT_CAM_ID;
-module_param(front_cam_id, uint, 0644);
-static int front_cam_pwr = DEF_FRONT_CAM_PWR;
-module_param(front_cam_pwr, int, 0644);
-
-static int back_cam_i2c = DEF_BACK_CAM_I2C;
-module_param(back_cam_i2c, int, 0644);
-static int back_cam_id = DEF_BACK_CAM_ID;
-module_param(back_cam_id, uint, 0644);
-static int back_cam_pwr = DEF_BACK_CAM_PWR;
-module_param(back_cam_pwr, int, 0644);
-
-static inline int check_cam_param(void)
-{
- return 0;
-}
-
-/* pwm regulator */
-static int __sramdata reg_pwm = DEF_REG_PWM;
-module_param(reg_pwm, int, 0644);
-static inline int check_reg_pwm_param(void)
-{
- if(reg_pwm < 0 || reg_pwm >= ARRAY_SIZE(pwm_cfg)){
- CONFIG_ERR(reg_pwm, "reg_pwm");
- return -EINVAL;
- }
-
- return 0;
-}
-
-/* pmic */
-static uint pmic_type = DEF_PMIC_TYPE;
-module_param(pmic_type, uint, 0644);
-static __sramdata int pmic_slp = DEF_PMIC_SLP;
-module_param(pmic_slp, int, 0644);
-static int pmic_irq = DEF_PMIC_IRQ;
-module_param(pmic_irq, int, 0644);
-static int pmic_i2c = DEF_PMIC_I2C;
-module_param(pmic_i2c, int, 0644);
-static int pmic_addr = DEF_PMIC_ADDR;
-module_param(pmic_addr, int, 0644);
-
-static int tps65910_dcdc[] = DEF_TPS65910_DCDC;
-module_param_array(tps65910_dcdc, int, NULL, 0644);
-static int tps65910_ldo[] = DEF_TPS65910_LDO;
-module_param_array(tps65910_ldo, int, NULL, 0644);
-
-static int act8931_dcdc[] = DEF_ACT8931_DCDC;
-module_param_array(act8931_dcdc, int, NULL, 0644);
-static int act8931_ldo[] = DEF_ACT8931_LDO;
-module_param_array(act8931_ldo, int, NULL, 0644);
-
-static inline int check_pmic_param(void)
-{
- if(pmic_type <= PMIC_TYPE_WM8326 || pmic_type >= PMIC_TYPE_MAX){
- CONFIG_ERR(pmic_type, "pmic_type");
- return -EINVAL;
- }
- if(pmic_i2c < 0 || pmic_i2c > 3){
- CONFIG_ERR(pmic_i2c, "pmic_i2c");
- return -EINVAL;
- }
- if(pmic_addr < 0 || pmic_addr > 0x7f){
- CONFIG_ERR(pmic_i2c, "pmic_addr");
- return -EINVAL;
- }
-
- g_pmic_type = pmic_type;
-
- return 0;
-}
-int pmic_dcdc_set(int index, int on)
-{
- struct regulator *dcdc = NULL;
-
- if(index < 0)
- return -EINVAL;
-
- if(pmic_is_tps65910()) {
- dcdc = regulator_get(NULL, tps65910_dcdc_info[index].name);
- }
- if(pmic_is_act8931()) {
- dcdc = regulator_get(NULL, act8931_dcdc_info[index].name);
- }
- if(IS_ERR_OR_NULL(dcdc))
- return -EINVAL;
- if(on)
- regulator_enable(dcdc);
- else
- regulator_disable(dcdc);
- regulator_put(dcdc);
- return 0;
-
-}
-EXPORT_SYMBOL(pmic_dcdc_set);
-int pmic_ldo_set(int index, int on)
-{
- struct regulator *ldo = NULL;
-
- if(index < 0)
- return -EINVAL;
-
- if(pmic_is_tps65910()) {
- ldo = regulator_get(NULL, tps65910_ldo_info[index].name);
- }
- if(pmic_is_act8931()) {
- ldo = regulator_get(NULL, act8931_ldo_info[index].name);
- }
- if(IS_ERR_OR_NULL(ldo))
- return -EINVAL;
- if(on)
- regulator_enable(ldo);
- else
- regulator_disable(ldo);
- regulator_put(ldo);
- return 0;
-
-}
-EXPORT_SYMBOL(pmic_ldo_set);
-/* ion */
-static uint ion_size = DEF_ION_SIZE;
-module_param(ion_size, uint, 0644);
-
-static inline int check_ion_param(void)
-{
- return 0;
-}
-/* codec */
-static int spk_ctl = DEF_SPK_CTL;
-module_param(spk_ctl, int, 0644);
-static int hp_det = DEF_HP_DET;
-module_param(hp_det, int, 0644);
-static inline int check_codec_param(void)
-{
- return 0;
-}
-/* sdmmc */
-static int sd_det = -1;
-module_param(sd_det, int, 0644);
-static inline int check_sdmmc_param(void)
-{
- return 0;
-}
-/* wifi */
-static int wifi_rst = DEF_WIFI_RST;
-module_param(wifi_rst, int, 0644);
-static int wifi_pwr = DEF_WIFI_PWR;
-module_param(wifi_pwr, int, 0644);
-static uint wifi_type = DEF_WIFI_TYPE;
-module_param(wifi_type, uint, 0644);
-static int wifi_ldo = DEF_WIFI_LDO;
-module_param(wifi_ldo, int, 0644);
-static inline int check_wifi_param(void)
-{
- if(wifi_type != WIFI_NONE){
- if(wifi_type <= WIFI_USB_NONE || wifi_type >= WIFI_USB_MAX || wifi_type <= WIFI_SDIO_NONE || wifi_type >= WIFI_SDIO_MAX){
- CONFIG_ERR(wifi_type, "wifi_type");
- return -EINVAL;
- }
- }
-
- return 0;
-
-}
-/* rtc */
-static int rtc_i2c = DEF_RTC_I2C;
-module_param(rtc_i2c, int, 0644);
-static int rtc_addr = DEF_RTC_ADDR;
-module_param(rtc_addr, int, 0644);
-static int rtc_irq = DEF_RTC_IRQ;
-module_param(rtc_irq, int, 0644);
-static inline int check_rtc_param(void)
-{
- if(rtc_i2c < 0 || rtc_i2c > 3){
- CONFIG_ERR(rtc_i2c, "rtc_i2c");
- return -EINVAL;
- }
- if(rtc_addr < 0 || rtc_addr > 0x7f){
- CONFIG_ERR(rtc_i2c, "rtc_addr");
- return -EINVAL;
- }
- return 0;
-}
-
-/* charge */
-static int chg_adc = DEF_CHG_ADC;
-module_param(chg_adc, int, 0644);
-
-static int dc_det = DEF_DC_DET;
-module_param(dc_det, int, 0644);
-static int bat_low = DEF_BAT_LOW;
-module_param(bat_low, int, 0644);
-static int chg_ok = DEF_CHG_OK;
-module_param(chg_ok, int, 0644);
-static int chg_set = DEF_CHG_SET;
-module_param(chg_set, int, 0644);
-static int chg_sel = DEF_CHG_SEL;
-module_param(chg_sel, int, 0644);
-static inline int check_chg_param(void)
-{
- return 0;
-}
-
-/* dvfs */
-static struct dvfs_arm_table dvfs_cpu_logic_table[] = {
-//#if defined(RK2926_TB_DEFAULT_CONFIG)
-#if 1
- {.frequency = 216 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 312 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 408 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 504 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 600 * 1000, .cpu_volt = 1250 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 696 * 1000, .cpu_volt = 1350 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 816 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 912 * 1000, .cpu_volt = 1450 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 1008 * 1000,.cpu_volt = 1500 * 1000, .logic_volt = 1200 * 1000},
-#else
- { .frequency = 216 * 1000, .cpu_volt = 850 * 1000, .logic_volt = 1200 * 1000 },
- { .frequency = 312 * 1000, .cpu_volt = 900 * 1000, .logic_volt = 1200 * 1000 },
- { .frequency = 408 * 1000, .cpu_volt = 950 * 1000, .logic_volt = 1200 * 1000 },
- { .frequency = 504 * 1000, .cpu_volt = 1000 * 1000, .logic_volt = 1200 * 1000 },
- { .frequency = 600 * 1000, .cpu_volt = 1100 * 1000, .logic_volt = 1200 * 1000 },
- { .frequency = 696 * 1000, .cpu_volt = 1175 * 1000, .logic_volt = 1200 * 1000 },
- { .frequency = 816 * 1000, .cpu_volt = 1250 * 1000, .logic_volt = 1200 * 1000 },
- { .frequency = 912 * 1000, .cpu_volt = 1350 * 1000, .logic_volt = 1200 * 1000 },
- { .frequency =1008 * 1000, .cpu_volt = 1450 * 1000, .logic_volt = 1200 * 1000 },
-#endif
- { .frequency = CPUFREQ_TABLE_END },
-};
-static unsigned int dvfs_cpu_logic[ARRAY_SIZE(dvfs_cpu_logic_table) * 3];
-static unsigned int dvfs_cpu_logic_num;
-module_param_array(dvfs_cpu_logic, uint, &dvfs_cpu_logic_num, 0400);
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- { .frequency = 266 * 1000, .index = 1050 * 1000 },
- { .frequency = 400 * 1000, .index = 1275 * 1000 },
- { .frequency = CPUFREQ_TABLE_END },
-};
-static unsigned int dvfs_gpu[ARRAY_SIZE(dvfs_gpu_table) * 2];
-static unsigned int dvfs_gpu_num;
-module_param_array(dvfs_gpu, uint, &dvfs_gpu_num, 0400);
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1125 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-static unsigned int dvfs_ddr[ARRAY_SIZE(dvfs_ddr_table) * 2];
-static unsigned int dvfs_ddr_num;
-module_param_array(dvfs_ddr, uint, &dvfs_ddr_num, 0400);
-
-
-/* global */
-static int is_phonepad = DEF_IS_PHONEPAD;
-module_param(is_phonepad, int, 0644);
-static int pwr_on = DEF_PWR_ON;
-module_param(pwr_on, int, 0644);
-
-static inline int rk2928_power_on(void)
-{
- return port_output_init(pwr_on, 1, "pwr_on");
-}
-static inline void rk2928_power_off(void)
-{
- port_output_off(pwr_on);
- port_deinit(pwr_on);
-}
-
+++ /dev/null
-#include <mach/gpio.h>
-#include <plat/key.h>
-
-#define EV_ENCALL KEY_F4
-#define EV_MENU KEY_F1
-
-#define PRESS_LEV_LOW 1
-#define PRESS_LEV_HIGH 0
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "menu",
- .code = EV_MENU,
- .gpio = RK2928_PIN3_PB2,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .gpio = RK2928_PIN3_PB1,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .gpio = RK2928_PIN3_PB0,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .gpio = RK2928_PIN3_PB3,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .gpio = RK2928_PIN3_PB4,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "key6",
- .code = KEY_CAMERA,
- .gpio = RK2928_PIN3_PB5,
- .active_low = PRESS_LEV_LOW,
- },
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = -1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
+++ /dev/null
-/* arch/arm/mach-rk2928/board-rk2928-fpga.c
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <linux/fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-
-#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Macro Define Begin ------------------------*/
-/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
-#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_OV5642 /* back camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_0 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 4
-#define CONFIG_SENSOR_CIF_INDEX_0 0
-#define CONFIG_SENSOR_ORIENTATION_0 90
-#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 RK2928_PIN1_PD6
-#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000
-
-#define CONFIG_SENSOR_01 RK29_CAM_SENSOR_OV5642 /* back camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_01 0x00
-#define CONFIG_SENSOR_CIF_INDEX_01 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 4
-#define CONFIG_SENSOR_ORIENTATION_01 90
-#define CONFIG_SENSOR_POWER_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_01 RK2928_PIN1_PD6
-#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_01 30000
-
-#define CONFIG_SENSOR_02 RK29_CAM_SENSOR_OV5640 /* back camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_02 0x00
-#define CONFIG_SENSOR_CIF_INDEX_02 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 4
-#define CONFIG_SENSOR_ORIENTATION_02 90
-#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_02 RK2928_PIN1_PD6
-#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000
-
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_OV2659 /* front camera sensor 0 */
-#define CONFIG_SENSOR_IIC_ADDR_1 0x60
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 1
-#define CONFIG_SENSOR_CIF_INDEX_1 0
-#define CONFIG_SENSOR_ORIENTATION_1 270
-#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_1 RK2928_PIN1_PB7
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000
-
-#define CONFIG_SENSOR_11 RK29_CAM_SENSOR_OV2659 /* front camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_11 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 3
-#define CONFIG_SENSOR_CIF_INDEX_11 0
-#define CONFIG_SENSOR_ORIENTATION_11 270
-#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_11 INVALID_GPIO//RK30_PIN1_PB7
-#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_11 30000
-
-#define CONFIG_SENSOR_12 RK29_CAM_SENSOR_OV2659//RK29_CAM_SENSOR_OV2655 /* front camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_12 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 3
-#define CONFIG_SENSOR_CIF_INDEX_12 0
-#define CONFIG_SENSOR_ORIENTATION_12 270
-#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_12 INVALID_GPIO//RK30_PIN1_PB7
-#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_12 30000
-
-
-#endif //#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk2928_camera.c"
-/*---------------- Camera Sensor Macro Define End ---------*/
-
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#define CONFIG_SENSOR_POWER_IOCTL_USR 0 //define this refer to your board layout
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
-
-static void rk_cif_power(int on)
-{
- struct regulator *ldo_18,*ldo_28;
- ldo_28 = regulator_get(NULL, "ldo7"); // vcc28_cif
- ldo_18 = regulator_get(NULL, "ldo1"); // vcc18_cif
- if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){
- printk("get cif ldo failed!\n");
- return;
- }
- if(on == 0){
- regulator_disable(ldo_28);
- regulator_put(ldo_28);
- regulator_disable(ldo_18);
- regulator_put(ldo_18);
- mdelay(500);
- }
- else{
- regulator_set_voltage(ldo_28, 2800000, 2800000);
- regulator_enable(ldo_28);
- // printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
- regulator_put(ldo_28);
-
- regulator_set_voltage(ldo_18, 1800000, 1800000);
- // regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(ldo_18);
- // printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
- regulator_put(ldo_18);
- }
-}
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- //#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
- rk_cif_power(on);
-}
-#endif
-
-#if CONFIG_SENSOR_RESET_IOCTL_USR
-static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
-static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-
-#if CONFIG_SENSOR_IIC_ADDR_0
-static struct reginfo_t rk_init_data_sensor_reg_0[] =
-{
- {0x0000, 0x00,0,0}
- };
-static struct reginfo_t rk_init_data_sensor_winseqreg_0[] ={
- {0x0000, 0x00,0,0}
- };
-#endif
-
-#if CONFIG_SENSOR_IIC_ADDR_1
-static struct reginfo_t rk_init_data_sensor_reg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_01
-static struct reginfo_t rk_init_data_sensor_reg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_02
-static struct reginfo_t rk_init_data_sensor_reg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_11
-static struct reginfo_t rk_init_data_sensor_reg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_12
-static struct reginfo_t rk_init_data_sensor_reg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] =
-{
- #if CONFIG_SENSOR_IIC_ADDR_0
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_0,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_1
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_1,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_01
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_01,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_02
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_02,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_11
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_11,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_12
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_12,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
-
- };
-#include "../../../drivers/media/video/rk2928_camera.c"
-
-#endif /* CONFIG_VIDEO_RK29 */
-
-#include "board-rk2928-fpga-key.c"
-
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and sdio.noted by xbw at 2012-03-05
-**************************************************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "board-rk2928-sdk-sdmmc.c"
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
-#define SDMMC0_WRITE_PROTECT_PIN RK2928_PIN1_PA7 //According to your own project to set the value of write-protect-pin.
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
-#define SDMMC1_WRITE_PROTECT_PIN RK2928_PIN0_PD5 //According to your own project to set the value of write-protect-pin.
-#endif
-
-#define RK29SDK_WIFI_SDIO_CARD_DETECT_N RK2928_PIN0_PB2
-
-#endif //endif ---#ifdef CONFIG_SDMMC_RK29
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- rk30_mux_api_set(GPIO1B7_MMC0_CMD_NAME, GPIO1B_MMC0_CMD);
- rk30_mux_api_set(GPIO1C0_MMC0_CLKOUT_NAME, GPIO1C_MMC0_CLKOUT);
- rk30_mux_api_set(GPIO1C2_MMC0_D0_NAME, GPIO1C_MMC0_D0);
- rk30_mux_api_set(GPIO1C3_MMC0_D1_NAME, GPIO1C_MMC0_D1);
- rk30_mux_api_set(GPIO1C4_MMC0_D2_NAME, GPIO1C_MMC0_D2);
- rk30_mux_api_set(GPIO1C5_MMC0_D3_NAME, GPIO1C_MMC0_D3);
-
- rk30_mux_api_set(GPIO1C1_MMC0_DETN_NAME, GPIO1C_MMC0_DETN);
-
- rk30_mux_api_set(GPIO1B6_MMC0_PWREN_NAME, GPIO1B_MMC0_PWREN);
- gpio_request(RK30_PIN3_PA7, "sdmmc-power");
- gpio_direction_output(RK2928_PIN1_PB6, GPIO_LOW);
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- rk30_mux_api_set(GPIO1C1_MMC0_DETN_NAME, GPIO1C_MMC0_DETN);
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
- .detect_irq = RK2928_PIN1_PC1, // INVALID_GPIO
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
-#else
- .write_prt = INVALID_GPIO,
-#endif
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- rk30_mux_api_set(GPIO0B0_MMC1_CMD_NAME, GPIO0B_MMC1_CMD);
- rk30_mux_api_set(GPIO0B1_MMC1_CLKOUT_NAME, GPIO0B_MMC1_CLKOUT);
- rk30_mux_api_set(GPIO0B3_MMC1_D0_NAME, GPIO0B_MMC1_D0);
- rk30_mux_api_set(GPIO0B4_MMC1_D1_NAME, GPIO0B_MMC1_D1);
- rk30_mux_api_set(GPIO0B5_MMC1_D2_NAME, GPIO0B_MMC1_D2);
- rk30_mux_api_set(GPIO0B6_MMC1_D3_NAME, GPIO0B_MMC1_D3);
- //rk30_mux_api_set(GPIO0B2_MMC1_DETN_NAME, GPIO0B_MMC1_DETN);
-
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-#if 0
- .detect_irq = RK29SDK_WIFI_SDIO_CARD_DETECT_N,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
-#else
- .detect_irq = INVALID_GPIO,
- .enable_sd_wakeup = 0,
-#endif
-
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-/**************************************************************************************************
- * the end of setting for SDMMC devices
-**************************************************************************************************/
-
-
-
-#define RK2928_FB_MEM_SIZE 3*SZ_1M
-
-#ifdef CONFIG_FB_ROCKCHIP
-
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- return 0;
-}
-
-#if defined(CONFIG_LCDC_RK2928)
-struct rk29fb_info lcdc_screen_info = {
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-
-//i2c
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-};
-#endif
-#ifdef CONFIG_I2C1_RK30
-static struct i2c_board_info __initdata i2c1_info[] = {
-};
-#endif
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-};
-#endif
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(4, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-static struct spi_board_info board_spi_devices[] = {
-};
-
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (8 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
- &device_fb,
-#endif
-};
-
-static void __init rk2928_board_init(void)
-{
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
-}
-
-static void __init rk2928_reserve(void)
-{
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0", RK2928_FB_MEM_SIZE);
- resource_fb[0].end = resource_fb[0].start + RK2928_FB_MEM_SIZE - 1;
-#endif
- board_mem_reserved();
-}
-
-#include <linux/clkdev.h>
-
-struct clk {
- const char *name;
- unsigned long rate;
-};
-
-static struct clk xin24m = {
- .name = "xin24m",
- .rate = 24000000,
-};
-
-#define CLK(dev, con, ck) \
- { \
- .dev_id = dev, \
- .con_id = con, \
- .clk = ck, \
- }
-
-static struct clk_lookup clks[] = {
- CLK("rk30_i2c.0", "i2c", &xin24m),
- CLK("rk30_i2c.1", "i2c", &xin24m),
- CLK("rk30_i2c.2", "i2c", &xin24m),
- CLK("rk30_i2c.3", "i2c", &xin24m),
- CLK("rk29xx_spim.0", "spi", &xin24m),
- CLK("rk29xx_spim.1", "spi", &xin24m),
-
- CLK("rk_serial.0", "uart_div", &xin24m),
- CLK("rk_serial.0", "uart_frac_div", &xin24m),
- CLK("rk_serial.0", "uart", &xin24m),
- CLK("rk_serial.0", "pclk_uart", &xin24m),
- CLK("rk_serial.1", "uart_div", &xin24m),
- CLK("rk_serial.1", "uart_frac_div", &xin24m),
- CLK("rk_serial.1", "uart", &xin24m),
- CLK("rk_serial.1", "pclk_uart", &xin24m),
- CLK("rk_serial.2", "uart_div", &xin24m),
- CLK("rk_serial.2", "uart_frac_div", &xin24m),
- CLK("rk_serial.2", "uart", &xin24m),
- CLK("rk_serial.2", "pclk_uart", &xin24m),
-
- CLK("rk29_i2s.0", "i2s_div", &xin24m),
- CLK("rk29_i2s.0", "i2s_frac_div", &xin24m),
- CLK("rk29_i2s.0", "i2s", &xin24m),
- CLK("rk29_i2s.0", "hclk_i2s", &xin24m),
- CLK(NULL, "pd_lcdc0", &xin24m),
- CLK(NULL, "hclk_lcdc0", &xin24m),
- CLK(NULL, "aclk_lcdc0", &xin24m),
- CLK(NULL, "dclk_lcdc0", &xin24m),
-
- CLK(NULL, "pd_cif0", &xin24m),
- CLK(NULL, "aclk_cif0", &xin24m),
- CLK(NULL, "hclk_cif0", &xin24m),
- CLK(NULL, "cif0_in", &xin24m),
- CLK(NULL, "cif0_out", &xin24m),
-};
-
-void __init rk30_clock_init(void)
-{
- struct clk_lookup *lk;
-
- for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) {
- clkdev_add(lk);
- }
-}
-void __init board_clock_init(void)
-{
- rk30_clock_init();
-}
-
-int clk_enable(struct clk *clk)
-{
- return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
- return 24000000;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
- return 0;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
- return 0;
-}
-EXPORT_SYMBOL(clk_set_parent);
-
-MACHINE_START(RK2928, "RK2928board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk2928_fixup,
- .reserve = &rk2928_reserve,
- .map_io = rk2928_map_io,
- .init_irq = rk2928_init_irq,
- .timer = &rk2928_timer,
- .init_machine = rk2928_board_init,
-MACHINE_END
+++ /dev/null
-#include <mach/gpio.h>
-#include <plat/key.h>
-
-#define EV_ENCALL KEY_F4
-#define EV_MENU KEY_F1
-
-#define PRESS_LEV_LOW 1
-#define PRESS_LEV_HIGH 0
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "play",
- .code = KEY_POWER,
- .wakeup = 1,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- },
- {
- .desc = "menu",
- .code = EV_MENU,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- },
- {
- .desc = "camera",
- .code = KEY_CAMERA,
- },
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .chn = -1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-static int __init key_board_init(void)
-{
- int i;
- struct port_config port;
-
- for(i = 0; i < key_val_size; i++){
- if(key_val[i] & (1<<31)){
- key_button[i].adc_value = key_val[i] & 0xffff;
- key_button[i].gpio = INVALID_GPIO;
- }else{
- port = get_port_config(key_val[i]);
- key_button[i].gpio = port.gpio;
- key_button[i].active_low = port.io.active_low;
- }
- }
- rk29_keys_pdata.nbuttons = key_val_size;
- rk29_keys_pdata.chn = key_adc;
-
- return 0;
-}
-
+++ /dev/null
-#ifdef CONFIG_VIDEO_RK29
-#include <plat/rk_camera.h>
-/* Notes:
-
-Simple camera device registration:
-
- new_camera_device(sensor_name,\ // sensor name, it is equal to CONFIG_SENSOR_X
- face,\ // sensor face information, it can be back or front
- pwdn_io,\ // power down gpio configuration, it is equal to CONFIG_SENSOR_POWERDN_PIN_XX
- flash_attach,\ // sensor is attach flash or not
- mir,\ // sensor image mirror and flip control information
- i2c_chl,\ // i2c channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_IIC_ADAPTER_ID_X
- cif_chl) \ // cif channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_CIF_INDEX_X
-
-Comprehensive camera device registration:
-
- new_camera_device_ex(sensor_name,\
- face,\
- ori,\ // sensor orientation, it is equal to CONFIG_SENSOR_ORIENTATION_X
- pwr_io,\ // sensor power gpio configuration, it is equal to CONFIG_SENSOR_POWER_PIN_XX
- pwr_active,\ // sensor power active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- rst_io,\ // sensor reset gpio configuration, it is equal to CONFIG_SENSOR_RESET_PIN_XX
- rst_active,\ // sensor reset active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- pwdn_io,\
- pwdn_active,\ // sensor power down active level, is equal to CONFIG_SENSOR_POWERDNACTIVE_LEVEL_X
- flash_attach,\
- res,\ // sensor resolution, this is real resolution or resoltuion after interpolate
- mir,\
- i2c_chl,\
- i2c_spd,\ // i2c speed , 100000 = 100KHz
- i2c_addr,\ // the i2c slave device address for sensor
- cif_chl,\
- mclk)\ // sensor input clock rate, 24 or 48
-
-*/
-static struct rkcamera_platform_data new_camera[] = {
- new_camera_device(RK29_CAM_SENSOR_GC2035,
- back,
- RK2928_PIN3_PB3,
- 0,
- 0,
- 1,
- 0),
- new_camera_device(RK29_CAM_SENSOR_GC0308,
- front,
- RK2928_PIN3_PD7,
- 0,
- 0,
- 1,
- 0),
- new_camera_device(RK29_CAM_SENSOR_GC0329,
- front,
- RK2928_PIN3_PD7,
- 0,
- 0,
- 1,
- 0),
- new_camera_device_end
-};
-/*---------------- Camera Sensor Macro Define Begin ------------------------*/
-/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
-#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_GC2035 /* back camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_0 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 1
-#define CONFIG_SENSOR_CIF_INDEX_0 0
-#define CONFIG_SENSOR_ORIENTATION_0 90
-#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 RK2928_PIN3_PB3
-#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000
-
-#define CONFIG_SENSOR_01 RK29_CAM_SENSOR_OV5642 /* back camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_01 0x00
-#define CONFIG_SENSOR_CIF_INDEX_01 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 4
-#define CONFIG_SENSOR_ORIENTATION_01 90
-#define CONFIG_SENSOR_POWER_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_01 INVALID_GPIO//RK2928_PIN3_PB3
-#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_01 30000
-
-#define CONFIG_SENSOR_02 RK29_CAM_SENSOR_OV5640 /* back camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_02 0x00
-#define CONFIG_SENSOR_CIF_INDEX_02 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 4
-#define CONFIG_SENSOR_ORIENTATION_02 90
-#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_02 INVALID_GPIO//RK2928_PIN3_PB3
-#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000
-
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_GC0308 /* front camera sensor 0 */
-#define CONFIG_SENSOR_IIC_ADDR_1 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 1
-#define CONFIG_SENSOR_CIF_INDEX_1 0
-#define CONFIG_SENSOR_ORIENTATION_1 270
-#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_1 RK2928_PIN3_PD7
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000
-
-#define CONFIG_SENSOR_11 RK29_CAM_SENSOR_GC0329 /* front camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_11 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 1
-#define CONFIG_SENSOR_CIF_INDEX_11 0
-#define CONFIG_SENSOR_ORIENTATION_11 90
-#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_11 RK2928_PIN3_PD7
-#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_11 30000
-
-#define CONFIG_SENSOR_12 RK29_CAM_SENSOR_OV2659//RK29_CAM_SENSOR_OV2655 /* front camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_12 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 3
-#define CONFIG_SENSOR_CIF_INDEX_12 0
-#define CONFIG_SENSOR_ORIENTATION_12 270
-#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_12 30000
-
-
-#endif //#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk2928_camera.c"
-/*---------------- Camera Sensor Macro Define End ---------*/
-
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#define CONFIG_SENSOR_POWER_IOCTL_USR 1 //define this refer to your board layout
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
-
-static void rk_cif_power(int on)
-{
- struct regulator *ldo_18,*ldo_28;
- ldo_28 = regulator_get(NULL, "vaux1"); // vcc28_cif
- ldo_18 = regulator_get(NULL, "vdig1"); // vcc18_cif
- if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){
- printk("get cif ldo failed!\n");
- return;
- }
- if(on == 0){
- regulator_force_disable(ldo_28);
- regulator_put(ldo_28);
- regulator_force_disable(ldo_18);
- regulator_put(ldo_18);
- mdelay(500);
- }
- else{
- regulator_set_voltage(ldo_28, 2800000, 2800000);
- regulator_enable(ldo_28);
- // printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
- regulator_put(ldo_28);
-
- regulator_set_voltage(ldo_18, 1800000, 1800000);
- // regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(ldo_18);
- // printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
- regulator_put(ldo_18);
- }
-}
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- //#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
- rk_cif_power(on);
-}
-#endif
-
-#if CONFIG_SENSOR_RESET_IOCTL_USR
-static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
-static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-
-#if CONFIG_SENSOR_IIC_ADDR_0
-static struct reginfo_t rk_init_data_sensor_reg_0[] =
-{
- {0x0000, 0x00,0,0}
- };
-static struct reginfo_t rk_init_data_sensor_winseqreg_0[] ={
- {0x0000, 0x00,0,0}
- };
-#endif
-
-#if CONFIG_SENSOR_IIC_ADDR_1
-static struct reginfo_t rk_init_data_sensor_reg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_01
-static struct reginfo_t rk_init_data_sensor_reg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_02
-static struct reginfo_t rk_init_data_sensor_reg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_11
-static struct reginfo_t rk_init_data_sensor_reg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_12
-static struct reginfo_t rk_init_data_sensor_reg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] =
-{
- #if CONFIG_SENSOR_IIC_ADDR_0
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_0,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_1
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_1,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_01
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_01,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_02
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_02,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_11
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_11,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_12
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_12,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
-
- };
-#include "../../../drivers/media/video/rk2928_camera.c"
-
-#endif /* CONFIG_VIDEO_RK29 */
+++ /dev/null
-/* arch/arm/mach-rk2928/board-rk2928-fpga.c
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-#include <mach/dvfs.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <mach/config.h>
-#include <linux/fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/mfd/tps65910.h>
-#include <linux/regulator/act8931.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-#if defined(CONFIG_MODEM_SOUND)
-#include "../../../drivers/misc/modem_sound.h"
-#endif
-#if defined(CONFIG_HDMI_RK30)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-#include "../../../drivers/headset_observe/rk_headset.h"
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-#ifdef CONFIG_SND_SOC_RK2928
-#include "../../../sound/soc/codecs/rk2928_codec.h"
-#endif
-#ifdef CONFIG_TOUCHSCREEN_GT82X_IIC_760
-#include <linux/goodix_touch_82x.h>
-#endif
-
-#if defined(CONFIG_SC6610)
-#include <linux/sc6610.h>
-#endif
-
-#if defined(CONFIG_ANDROID_TIMED_GPIO)
-#include "../../../drivers/staging/android/timed_gpio.h"
-#endif
-#if defined (CONFIG_BP_AUTO)
-#include <linux/bp-auto.h>
-#endif
-#include "board-rk2928-phonepad-760-camera.c"
-#include "board-rk2928-phonepad-key.c"
-int __sramdata g_pmic_type = 0;
-
-#ifdef CONFIG_THREE_FB_BUFFER
-#define RK30_FB0_MEM_SIZE 12*SZ_1M
-#else
-#define RK30_FB0_MEM_SIZE 8*SZ_1M
-#endif
-
-/* Android Parameter */
-static int ap_mdm = BP_ID_M50;
-module_param(ap_mdm, int, 0644);
-static int ap_has_alsa = 0;
-module_param(ap_has_alsa, int, 0644);
-static int ap_multi_card = 0;
-module_param(ap_multi_card, int, 0644);
-static int ap_data_only = 1;
-module_param(ap_data_only, int, 0644);
-
-static int ap_has_earphone = 1;
-module_param(ap_has_earphone, int, 0644);
-
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-#define PWM_ID 0
-#define PWM_MUX_NAME GPIO0D2_PWM_0_NAME
-#define PWM_MUX_MODE GPIO0D_PWM_0
-#define PWM_MUX_MODE_GPIO GPIO0D_GPIO0D2
-#define PWM_GPIO RK2928_PIN0_PD2
-#define PWM_EFFECT_VALUE 0
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-#define BL_EN_MUX_NAME GPIO1A5_I2S_SDI_GPS_SIGN_NAME
-#define BL_EN_MUX_MODE GPIO1A_GPIO1A5
-#define BL_EN_PIN RK2928_PIN1_PA5
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
-#ifdef LCD_DISP_ON_PIN
- rk30_mux_api_set(BL_EN_MUX_NAME, BL_EN_MUX_MODE);
-
- ret = gpio_request(BL_EN_PIN, NULL);
- //if (ret != 0) {
- // gpio_free(BL_EN_PIN);
- //}
-
- gpio_direction_output(BL_EN_PIN, 0);
- mdelay(100);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0;
-#ifdef LCD_DISP_ON_PIN
- gpio_set_value(BL_EN_PIN, !BL_EN_VALUE);
- gpio_free(BL_EN_PIN);
-#endif
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret = 0;
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- if (gpio_request(PWM_GPIO, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- #if defined(CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- {
- gpio_direction_output(PWM_GPIO, GPIO_LOW);
- }
- #endif
- #if defined(CONFIG_REGULATOR_ACT8931)
- if(pmic_is_act8931())
- {
- gpio_direction_output(PWM_GPIO, GPIO_HIGH);
- }
- #endif
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, !BL_EN_VALUE);
-#endif
-
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- gpio_free(PWM_GPIO);
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
-#ifdef LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, 1);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .min_brightness = 15,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
- .pre_div = 20000,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-#endif
-#ifdef CONFIG_TOUCHSCREEN_GT82X_IIC_760
-#define TOUCH_ENABLE_PIN INVALID_GPIO
-#define TOUCH_RESET_PIN RK2928_PIN3_PD5
-#define TOUCH_INT_PIN RK2928_PIN3_PC7
-int goodix_init_platform_hw(void)
-{
- int ret;
-
-
-
-
- if (TOUCH_ENABLE_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_ENABLE_PIN, "goodix power pin");
- if (ret != 0) {
- gpio_free(TOUCH_ENABLE_PIN);
- printk("goodix power error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_ENABLE_PIN, 0);
- gpio_set_value(TOUCH_ENABLE_PIN, GPIO_LOW);
- msleep(100);
- }
-
- if (TOUCH_RESET_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_RESET_PIN, "goodix reset pin");
- if (ret != 0) {
- gpio_free(TOUCH_RESET_PIN);
- printk("goodix gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- gpio_set_value(TOUCH_RESET_PIN, GPIO_LOW);
- msleep(10);
- gpio_set_value(TOUCH_RESET_PIN, GPIO_HIGH);
- msleep(500);
- }
- return 0;
-}
-u8 ts82x_config_data[] = {
- 0x65,0x00,0x04,0x00,0x03,0x00,0x0A,0x0D,0x1E,0xE7,
- 0x32,0x03,0x08,0x10,0x48,0x42,0x42,0x20,0x00,0x01,
- 0x60,0x60,0x4B,0x6E,0x0E,0x0D,0x0C,0x0B,0x0A,0x09,
- 0x08,0x07,0x06,0x05,0x04,0x03,0x02,0x01,0x00,0x1D,
- 0x1C,0x1B,0x1A,0x19,0x18,0x17,0x16,0x15,0x14,0x13,
- 0x12,0x11,0x10,0x0F,0x50,0x00,0x00,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2B,0x00,0x00,
- 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x00
-};
-static struct goodix_i2c_rmi_platform_data ts82x_pdata = {
- .gpio_shutdown = TOUCH_ENABLE_PIN,
- .gpio_irq = TOUCH_INT_PIN,
- .gpio_reset = TOUCH_RESET_PIN,
- .irq_edge = 1, /* 0:rising edge, 1:falling edge */
-
- .ypol = 1,
- .swap_xy = 1,
- .xpol = 0,
- .xmax = 1024,
- .ymax = 600,
- .config_info_len =ARRAY_SIZE(ts82x_config_data),
- .config_info = ts82x_config_data,
- .init_platform_hw= goodix_init_platform_hw,
-};
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
-#define LCD_STB
-#ifdef LCD_STB
-#define LCD_STB_MUX_NAME GPIO1A3_I2S_LRCKTX_NAME
-#define LCD_STB_GPIO_MODE GPIO1A_GPIO1A3
-
-#define LCD_STB_EN RK2928_PIN1_PA3
-#define LCD_STB_EN_VALUE GPIO_HIGH
-#endif
-#define LCD_MUX_NAME GPIO0D4_PWM_2_NAME
-#define LCD_GPIO_MODE GPIO0D_GPIO0D4
-
-#define LCD_EN RK2928_PIN0_PD4
-#define LCD_EN_VALUE GPIO_LOW
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
-
- rk30_mux_api_set(LCD_MUX_NAME, LCD_GPIO_MODE);
- ret = gpio_request(LCD_EN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_EN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_EN, LCD_EN_VALUE); //disable
- }
- rk30_mux_api_set(LCD_STB_MUX_NAME, LCD_STB_GPIO_MODE);
- ret = gpio_request(LCD_STB_EN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_STB_EN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_STB_EN, LCD_STB_EN_VALUE); //disable
- }
-
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
- gpio_set_value(LCD_EN, !LCD_EN_VALUE);
- mdelay(50);
-#ifdef LCD_STB
- gpio_set_value(LCD_STB_EN,GPIO_LOW);
-#endif
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
-#ifdef LCD_STB
- gpio_set_value(LCD_STB_EN,GPIO_HIGH);
-#endif
- gpio_set_value(LCD_EN, LCD_EN_VALUE);
- mdelay(200);
- return 0;
-}
-
-#if defined(CONFIG_LCDC_RK2928)
-struct rk29fb_info lcdc_screen_info = {
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-
-//LCDC
-#ifdef CONFIG_LCDC_RK2928
-static struct resource resource_lcdc[] = {
- [0] = {
- .name = "lcdc reg",
- .start = RK2928_LCDC_PHYS,
- .end = RK2928_LCDC_PHYS + RK2928_LCDC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc irq",
- .start = IRQ_LCDC,
- .end = IRQ_LCDC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc = {
- .name = "rk2928-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc),
- .resource = resource_lcdc,
- .dev = {
- .platform_data = &lcdc_screen_info,
- },
-};
-#endif
-
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-#if CONFIG_ANDROID_TIMED_GPIO
-static struct timed_gpio timed_gpios[] = {
- {
- .name = "vibrator",
- .gpio = RK2928_PIN3_PD6,
- .max_timeout = 1000,
- .active_low = 0,
- .adjust_time =20, //adjust for diff product
- },
-};
-
-struct timed_gpio_platform_data rk29_vibrator_info = {
- .num_gpios = 1,
- .gpios = timed_gpios,
-};
-
-struct platform_device rk29_device_vibrator ={
- .name = "timed-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_vibrator_info,
- },
-
-};
-#endif
-
-
-#if defined (CONFIG_TP_760_TS)
-
-#define TOUCH_RESET_PIN RK2928_PIN3_PD5
-#define TOUCH_INT_PIN RK2928_PIN3_PC7
-int ft5306_init_platform_hw(void)
-{
-
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0)
- {
- gpio_free(TOUCH_RESET_PIN);
- printk("ft5306_init_platform_hw TOUCH_RESET_PIN error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0)
- {
- gpio_free(TOUCH_INT_PIN);
- printk("ift5306_init_platform_hw TOUCH_INT_PIN error\n");
- return -EIO;
- }
- gpio_direction_input(TOUCH_INT_PIN);
- gpio_direction_output(TOUCH_RESET_PIN, 1);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- msleep(50);
- msleep(300);
- return 0;
-
-}
-
-void ft5306_exit_platform_hw(void)
-{
- gpio_free(TOUCH_RESET_PIN);
- gpio_free(TOUCH_INT_PIN);
-}
-
-int ft5306_platform_sleep(void)
-{
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- return 0;
-}
-
-int ft5306_platform_wakeup(void)
-{
- //gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- //msleep(10);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- msleep(300);
- return 0;
-}
-
-struct ft5306_platform_data ft5306_info = {
- .irq_pin = TOUCH_INT_PIN,
- .rest_pin = TOUCH_RESET_PIN,
- .init_platform_hw= ft5306_init_platform_hw,
- .exit_platform_hw= ft5306_exit_platform_hw,
- .platform_sleep = ft5306_platform_sleep,
- .platform_wakeup = ft5306_platform_wakeup,
-
-};
-#endif
-
-#if defined(CONFIG_TOUCHSCREEN_BYD693X)
-
-#define TOUCH_RESET_PIN RK2928_PIN3_PD5
-#define TOUCH_INT_PIN RK2928_PIN3_PC7
-struct byd_platform_data byd693x_info = {
- .int_pin = TOUCH_INT_PIN,
- .rst_pin = TOUCH_RESET_PIN,
- .screen_max_x = 800,
- .screen_max_y = 480,
- .xpol = -1,
-};
-#endif
-
-/*MMA7660 gsensor*/
-#if defined (CONFIG_GS_MMA7660)
-#define MMA7660_INT_PIN RK2928_PIN3_PD1
-static int mma7660_init_platform_hw(void)
-{
- //rk30_mux_api_set(GPIO1B1_SPI_TXD_UART1_SOUT_NAME, GPIO1B_GPIO1B1);
-
- return 0;
-}
-
-static struct sensor_platform_data mma7660_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma7660_init_platform_hw,
- .orientation = {1, 0, 0, 0, -1,0, 0, 0, -1},
-};
-#endif
-
-
-#if defined (CONFIG_GS_KXTIK)
-#define KXTIK_INT_PIN RK2928_PIN3_PD1
-
-static struct sensor_platform_data kxtik_pdata = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 60,
- .orientation = {-1, 0, 0, 0, 0, -1, 0, 1, 0},
-};
-
-#endif /* CONFIG_GS_KXTIK*/
-
-#if defined (CONFIG_GS_MM3A310)
-#define MM3A310_INT_PIN RK2928_PIN3_PD1
-
-static struct sensor_platform_data mm3a310_pdata = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .orientation = {-1, 0, 0, 0, 0, -1, 0, 1, 0},
-};
-
-#endif /* CONFIG_GS_MM3A310*/
-
-
-#ifdef CONFIG_LS_AP321XX
-#define LS_AP321XX_INT_PIN RK2928_PIN0_PC6
-
-static struct sensor_platform_data ls_ap321xx_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 1,
- .poll_delay_ms = 500,
-};
-#endif
-#ifdef CONFIG_PS_AP321XX
-#define PS_AP321XX_INT_PIN RK2928_PIN0_PC6
-
-static struct sensor_platform_data ps_ap321xx_info = {
- .type = SENSOR_TYPE_PROXIMITY,
- .irq_enable = 1,
- .poll_delay_ms = 500,
-};
-#endif
-
-#if defined(CONFIG_BATTERY_RK30_ADC)||defined(CONFIG_BATTERY_RK30_ADC_FAC)
-#define CHARGE_OK_PIN RK2928_PIN3_PD2
-#define DC_DET_PIN RK2928_PIN3_PD3
-#define DC_CUR_SET_PIN RK2928_PIN1_PA0
-static int ac_current = -1;
-#define CHARING_CURRENT_500MA 0
-#define CHARING_CURRENT_1000MA 1
-int rk30_battery_adc_io_init(void){
- int ret = 0;
-
- //dc charge detect pin
- ret = gpio_request(DC_DET_PIN, NULL);
- if (ret) {
- printk("failed to request dc_det gpio\n");
- return ret ;
- }
-
- gpio_pull_updown(DC_DET_PIN, 1);//important
- ret = gpio_direction_input(DC_DET_PIN);
- if (ret) {
- printk("failed to set gpio dc_det input\n");
- return ret ;
- }
-
- //charge ok pin
- ret = gpio_request(CHARGE_OK_PIN, NULL);
- if (ret) {
- printk("failed to request charge_ok gpio\n");
- return ret ;
- }
-
- gpio_pull_updown(CHARGE_OK_PIN, 1);//important
- ret = gpio_direction_input(CHARGE_OK_PIN);
- if (ret) {
- printk("failed to set gpio charge_ok input\n");
- return ret ;
- }
-
- //charge current set pin
- ret = gpio_request(DC_CUR_SET_PIN, NULL);
- if (ret) {
- printk("failed to request DC_CUR_SET_PIN gpio\n");
- return ret ;
- }
-
- ret = gpio_direction_output(DC_CUR_SET_PIN, GPIO_LOW);//500ma
- if (ret) {
- printk("failed to set gpio DC_CUR_SET_PIN output\n");
- return ret ;
- }
- printk("charging: set charging current 500ma\n");
- ac_current = CHARING_CURRENT_500MA;
-
- gpio_request(BL_EN_PIN, NULL);
-
- return 0;
-
-}
-
-static int set_ac_charging_current(void)
-{
- if (gpio_get_value(BL_EN_PIN) && (ac_current==CHARING_CURRENT_1000MA)) {
- printk("charging: set charging current 500ma\n");
- gpio_set_value(DC_CUR_SET_PIN, GPIO_LOW);
- ac_current = CHARING_CURRENT_500MA;
- }
- else if (!gpio_get_value(BL_EN_PIN) && (ac_current==CHARING_CURRENT_500MA)) {
- printk("charging: set charging current 1000ma\n");
- gpio_set_value(DC_CUR_SET_PIN, GPIO_HIGH);
- ac_current = CHARING_CURRENT_1000MA;
- }
-}
-
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = DC_DET_PIN,
- .batt_low_pin = INVALID_GPIO,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = CHARGE_OK_PIN,
- .dc_det_level = GPIO_LOW, //
- .charge_ok_level = GPIO_HIGH,
- //.control_ac_charging_current = set_ac_charging_current,
- .save_capacity = 1,
- .is_reboot_charging = 1,
- .io_init = rk30_battery_adc_io_init,
-};
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-
-
-#if CONFIG_RK30_PWM_REGULATOR
-const static int pwm_voltage_map[] = {
- 1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000, 1375000, 1400000
-};
-
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_core",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] =
-{
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
- .pwm_id = 2,
- .pwm_gpio = RK2928_PIN0_PD4,
- .pwm_iomux_name = GPIO0D4_PWM_2_NAME,
- .pwm_iomux_pwm = GPIO0D_PWM_2,
- .pwm_iomux_gpio = GPIO0D_GPIO0D4,
- .pwm_voltage = 1200000,
- .suspend_voltage = 1050000,
- .min_uV = 1000000,
- .max_uV = 1400000,
- .coefficient = 504, //50.4%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-#endif
-
-/***********************************************************
-* usb wifi
-************************************************************/
-#if defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU) || defined(CONFIG_RT5370)
-#define WIFI_POWER_EN_MUX_NAME GPIO0B0_MMC1_CMD_NAME
-#define WIFI_POWER_EN_MUX_MODE GPIO0B_GPIO0B0
-#define WIFI_POWER_EN_PIN RK2928_PIN0_PB0
-#define WIFI_POWER_EN_VALUE GPIO_LOW
-static int rkusb_wifi_init = 0;
-static void rkusb_wifi_power_io_init(void)
-{
- int ret = 0;
-
- if(rkusb_wifi_init)
- return;
- rk30_mux_api_set(WIFI_POWER_EN_MUX_NAME, WIFI_POWER_EN_MUX_MODE);
-
- ret = gpio_request(WIFI_POWER_EN_PIN, NULL);
- if (ret != 0) {
- printk("rkusb_wifi_power_io_init fail!!!!!\n");
- gpio_free(WIFI_POWER_EN_PIN);
- }
-
- gpio_direction_output(WIFI_POWER_EN_PIN, 0);
- gpio_set_value(WIFI_POWER_EN_PIN, GPIO_HIGH);
- rkusb_wifi_init = 1;
-}
-static void rkusb_wifi_power(int on) {
-#if 0
- struct regulator *ldo = NULL;
-
-#if defined(CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910()) {
- ldo = regulator_get(NULL, "vmmc"); //vccio_wl
- }
-#endif
-#if defined(CONFIG_REGULATOR_ACT8931)
- if(pmic_is_act8931()) {
- ldo = regulator_get(NULL, "act_ldo4"); //vccio_wl
- }
-#endif
-
- if(on) {
- regulator_enable(ldo);
- printk("%s: vccio_wl enable\n", __func__);
- } else {
- printk("%s: vccio_wl disable\n", __func__);
- regulator_disable(ldo);
- }
-
- regulator_put(ldo);
- udelay(100);
-#else
- rkusb_wifi_power_io_init();
- if(on)
- {
- printk("usb wifi power on!!\n");
- gpio_set_value(WIFI_POWER_EN_PIN,GPIO_LOW);
- }
- else
- {
- printk("usb wifi power down!!\n");
- gpio_set_value(WIFI_POWER_EN_PIN,GPIO_HIGH);
- }
-#endif
-}
-
-#endif
-#if defined(CONFIG_MODEM_SOUND)
-struct modem_sound_data modem_sound_info = {
- .spkctl_io = RK2928_PIN3_PD4,
- .spkctl_active = GPIO_HIGH,
-};
-
-struct platform_device modem_sound_device = {
- .name = "modem_sound",
- .id = -1,
- .dev = {
- .platform_data = &modem_sound_info,
- }
- };
-#endif
-
-int rk2928_sd_vcc_reset(){
- struct regulator *vcc;
-
- vcc = regulator_get(NULL,"act_ldo4");
- if (vcc == NULL || IS_ERR(vcc) ){
- printk("%s get cif vaux33 ldo failed!\n",__func__);
- return -1 ;
- }
-
- printk("hj---->rk29_sdmmc_hw_init get vmmc regulator successfully \n\n\n");
- regulator_disable(vcc);
- mdelay(2000);
- regulator_enable(vcc);
-
-}
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and SDIO.noted by xbw at 2012-03-05
-**************************************************************************************************/
-
-#if defined CONFIG_RFKILL_RK
-// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
-static struct rfkill_rk_platform_data rfkill_rk_platdata = {
- .type = RFKILL_TYPE_BLUETOOTH,
- .poweron_gpio = { // BT_REG_ON
- .io = RK2928_PIN1_PA3,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK2928_PIN3_PD5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = NULL,
- },
- },
-
- .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
- .io = RK2928_PIN0_PC6, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .gpio = {
- .io = RK2928_PIN0_PC5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
- .iomux = {
- .name = NULL,
- },
- },
- },
-
- .rts_gpio = { // UART_RTS, enable or disable BT's data coming
- .io = RK2928_PIN0_PC3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = GPIO0C3_UART0_CTSN_NAME,
- .fgpio = GPIO0C_GPIO0C3,
- .fmux = GPIO0C_UART0_RTSN,//GPIO0C_UART0_CTSN,
- },
- },
-};
-
-static struct platform_device device_rfkill_rk = {
- .name = "rfkill_rk",
- .id = -1,
- .dev = {
- .platform_data = &rfkill_rk_platdata,
- },
-};
-#endif
-
-#if defined CONFIG_TCC_BT_DEV
-static struct tcc_bt_platform_data tcc_bt_platdata = {
-
- .power_gpio = { // ldoon
- .io = RK2928_PIN3_PC0,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .wake_host_gpio = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .io = RK2928_PIN0_PC5, // set io to INVALID_GPIO for disable it
- .enable = IRQF_TRIGGER_RISING,// set IRQF_TRIGGER_FALLING for falling, set IRQF_TRIGGER_RISING for rising
- .iomux = {
- .name = NULL,
- },
- },
-};
-
-static struct platform_device device_tcc_bt = {
- .name = "tcc_bt_dev",
- .id = -1,
- .dev = {
- .platform_data = &tcc_bt_platdata,
- },
-};
-#endif
-#ifdef CONFIG_SDMMC_RK29
-#include "board-rk2928-phonepad-sdmmc.c"
-#endif
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- rk30_mux_api_set(GPIO3B1_SDMMC0CMD_NAME, GPIO3B_SDMMC0_CMD);
- rk30_mux_api_set(GPIO3B0_SDMMC0CLKOUT_NAME, GPIO3B_SDMMC0_CLKOUT);
- rk30_mux_api_set(GPIO3B2_SDMMC0DATA0_NAME, GPIO3B_SDMMC0_DATA0);
- rk30_mux_api_set(GPIO3B3_SDMMC0DATA1_NAME, GPIO3B_SDMMC0_DATA1);
- rk30_mux_api_set(GPIO3B4_SDMMC0DATA2_NAME, GPIO3B_SDMMC0_DATA2);
- rk30_mux_api_set(GPIO3B5_SDMMC0DATA3_NAME, GPIO3B_SDMMC0_DATA3);
-
- rk30_mux_api_set(GPIO3B6_SDMMC0DETECTN_NAME, GPIO3B_GPIO3B6);
-
- rk30_mux_api_set(GPIO3A7_SDMMC0PWREN_NAME, GPIO3A_GPIO3A7);
- gpio_request(RK30_PIN3_PA7, "sdmmc-power");
- gpio_direction_output(RK30_PIN3_PA7, GPIO_LOW);
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- #if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO);
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FMUX);
- #endif
-
- #if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
- #endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) && defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- .status = rk29sdk_wifi_mmc0_status,
- .register_status_notify = rk29sdk_wifi_mmc0_status_register,
-#endif
-
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .power_en = RK29SDK_SD_CARD_PWR_EN,
- .power_en_level = RK29SDK_SD_CARD_PWR_EN_LEVEL,
-#else
- .power_en = INVALID_GPIO,
- .power_en_level = GPIO_LOW,
-#endif
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC0_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- .det_pin_info = {
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N, //INVALID_GPIO,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
- #endif
- },
-
- //.setpower = rk29_sdmmc_board_setpower,
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- rk30_mux_api_set(GPIO3C0_SMMC1CMD_NAME, GPIO3C_SMMC1_CMD);
- rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_NAME, GPIO3C_SDMMC1_CLKOUT);
- rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_NAME, GPIO3C_SDMMC1_DATA0);
- rk30_mux_api_set(GPIO3C2_SDMMC1DATA1_NAME, GPIO3C_SDMMC1_DATA1);
- rk30_mux_api_set(GPIO3C3_SDMMC1DATA2_NAME, GPIO3C_SDMMC1_DATA2);
- rk30_mux_api_set(GPIO3C4_SDMMC1DATA3_NAME, GPIO3C_SDMMC1_DATA3);
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC) || defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-
- #if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC1_WRITE_PROTECT_ENABLE_VALUE;
- #else
- .write_prt = INVALID_GPIO,
- #endif
-
- #if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
- .sdio_INT_gpio = RK29SDK_WIFI_SDIO_CARD_INT,
- #endif
-
- .det_pin_info = {
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- #else
- .io = INVALID_GPIO,
- #endif
-#else
- .io = INVALID_GPIO,
-#endif
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- },
-
- .enable_sd_wakeup = 0,
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-/**************************************************************************************************
- * the end of setting for SDMMC devices
-**************************************************************************************************/
-#if defined(CONFIG_MT5931_MT6622)
-static struct mt6622_platform_data mt6622_platdata = {
- .power_gpio = { // BT_REG_ON
- .io = RK2928_PIN3_PC2, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK2928_PIN0_PC6,
- .enable = GPIO_LOW,
- .iomux = {
- .name = NULL,
- },
- },
-
- .irq_gpio = {
- .io = RK2928_PIN3_PD3,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- }
-};
-
-static struct platform_device device_mt6622 = {
- .name = "mt6622",
- .id = -1,
- .dev = {
- .platform_data = &mt6622_platdata,
- },
-};
-#endif
-
-#if defined(CONFIG_SC6610)
-static int sc6610_io_init(void)
-{
-
- return 0;
-}
-
-static int sc6610_io_deinit(void)
-{
-
-
- return 0;
-}
-
-struct rk29_sc6610_data rk29_sc6610_info = {
- .io_init = sc6610_io_init,
- .io_deinit = sc6610_io_deinit,
- .bp_power = RK2928_PIN3_PC2,//RK29_PIN0_PB4,
- .bp_reset = INVALID_GPIO,//RK29_PIN0_PB3,
- .bp_wakeup_ap = RK2928_PIN3_PC3,//RK29_PIN0_PC2,
- .ap_wakeup_bp = RK2928_PIN3_PC4,//RK29_PIN0_PB0,
- .modem_assert = RK2928_PIN3_PC5,
-};
-struct platform_device rk29_device_sc6610 = {
- .name = "SC6610",
- .id = -1,
- .dev = {
- .platform_data = &rk29_sc6610_info,
- }
- };
-#endif
-
-#if defined(CONFIG_BP_AUTO)
-
-static int bp_io_deinit(void)
-{
-
- return 0;
-}
-
-static int bp_io_init(void)
-{
- rk30_mux_api_set(GPIO0D6_MMC1_PWREN_NAME, GPIO0D_GPIO0D6);//AP_STATUS
- rk30_mux_api_set(GPIO0B6_MMC1_D3_NAME, GPIO0B_GPIO0B6);//mdm_rst
- rk30_mux_api_set(GPIO0D0_UART2_RTSN_NAME, GPIO0D_GPIO0D0);//mdm_ready
- return 0;
-}
-
-static int bp_id_get(void)
-{
- return ap_mdm; //internally 3G modem ID, defined in include\linux\Bp-auto.h
-}
-struct bp_platform_data bp_auto_info = {
- .init_platform_hw = bp_io_init,
- .exit_platform_hw = bp_io_deinit,
- .get_bp_id = bp_id_get,
- .bp_power = RK2928_PIN3_PC2, // 3g_power
- .bp_en = BP_UNKNOW_DATA, // 3g_en
- .bp_reset = BP_UNKNOW_DATA,
- .ap_ready = BP_UNKNOW_DATA, //
- .bp_ready = BP_UNKNOW_DATA,
- .ap_wakeup_bp = RK2928_PIN3_PC4,
- .bp_wakeup_ap = RK2928_PIN3_PC3, //
- .bp_uart_en = BP_UNKNOW_DATA, //EINT9
- .bp_usb_en = BP_UNKNOW_DATA, //W_disable
- .bp_assert = RK2928_PIN3_PC5,
- .gpio_valid = 0, //if 1:gpio is define in bp_auto_info,if 0:is not use gpio in bp_auto_info
-
-};
-
-struct platform_device device_bp_auto = {
- .name = "bp-auto",
- .id = -1,
- .dev = {
- .platform_data = &bp_auto_info,
- }
- };
-#endif
-#if defined (CONFIG_RK_HEADSET_DET) || defined (CONFIG_RK_HEADSET_IRQ_HOOK_ADC_DET)
-static int rk_headset_io_init(int gpio, char *iomux_name, int iomux_mode)
-{
- int ret;
- ret = gpio_request(gpio, "headset_io");
- if(ret)
- return ret;
-
- rk30_mux_api_set(iomux_name, iomux_mode);
- gpio_pull_updown(gpio, PullDisable);
- gpio_direction_input(gpio);
- mdelay(50);
- return 0;
-};
-
-static int rk_hook_io_init(int gpio, char *iomux_name, int iomux_mode)
-{
- int ret;
- ret = gpio_request(gpio, "hook_io");
- if(ret)
- return ret;
-
- rk30_mux_api_set(iomux_name, iomux_mode);
- gpio_pull_updown(gpio, PullDisable);
- gpio_direction_input(gpio);
- mdelay(50);
- return 0;
-};
-
-struct rk_headset_pdata rk_headset_info = {
- .Headset_gpio = RK2928_PIN1_PB4,
- .Hook_gpio = RK2928_PIN0_PD1,
- .Hook_down_type = HOOK_DOWN_HIGH,
- .headset_in_type = HEADSET_IN_HIGH,
- .hook_key_code = KEY_MEDIA,
- .headset_gpio_info = {GPIO1B4_SPI_CSN1_NAME, GPIO1B_GPIO1B4},
- .headset_io_init = rk_headset_io_init,
- .hook_gpio_info = {GPIO0D1_UART2_CTSN_NAME, GPIO0D_GPIO0D1},
- .hook_io_init = rk_hook_io_init,
-};
-struct platform_device rk_device_headset = {
- .name = "rk_headsetdet",
- .id = 0,
- .dev = {
- .platform_data = &rk_headset_info,
- }
-};
-#endif
-#ifdef CONFIG_SND_SOC_RK2928
-#define HP_CTL_MUX_NAME GPIO1B6_MMC0_PWREN_NAME
-#define HP_CTL_MUX_MODE GPIO1B_GPIO1B6
-#define HP_CTL_IO_NAME RK2928_PIN1_PB6
-static int hpctl_io_init(void)
-{
- int ret=0;
-
- rk30_mux_api_set(HP_CTL_MUX_NAME, HP_CTL_MUX_MODE);
- ret = gpio_request(HP_CTL_IO_NAME, NULL);
- if (ret != 0) {
- gpio_free(HP_CTL_IO_NAME);
- printk("HP_CTL_IO requeset fail\n");
- }
- else
- {
- gpio_direction_output(HP_CTL_IO_NAME, GPIO_LOW);
- }
- return ret;
-}
-struct rk2928_codec_pdata rk2928_codec_pdata_info={
- .hpctl = HP_CTL_IO_NAME,
- .hpctl_io_init = hpctl_io_init,
-};
-static struct resource resources_acodec[] = {
- {
- .start = RK2928_ACODEC_PHYS,
- .end = RK2928_ACODEC_PHYS + RK2928_ACODEC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = RK2928_PIN3_PD4,
- .end = RK2928_PIN3_PD4,
- .flags = IORESOURCE_IO,
- },
-};
-
-static struct platform_device device_acodec = {
- .name = "rk2928-codec",
- .id = -1,
- .num_resources = ARRAY_SIZE(resources_acodec),
- .resource = resources_acodec,
- .dev = {
- .platform_data = &rk2928_codec_pdata_info,
- }
-};
-#endif
-
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_FB_ROCKCHIP
- &device_fb,
-#endif
-#ifdef CONFIG_LCDC_RK2928
- &device_lcdc,
-#endif
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- &rk29_device_backlight,
-#endif
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_SND_SOC_RK2928
- &device_acodec,
-#endif
-
-#if defined(CONFIG_BATTERY_RK30_ADC)||defined(CONFIG_BATTERY_RK30_ADC_FAC)
- &rk30_device_adc_battery,
-#endif
-#if defined(CONFIG_SC6610)
- &rk29_device_sc6610,
-
-#endif
-#if defined(CONFIG_BP_AUTO)
- &device_bp_auto,
-#endif
-#if defined (CONFIG_RK_HEADSET_DET) || defined (CONFIG_RK_HEADSET_IRQ_HOOK_ADC_DET)
- &rk_device_headset,
-#endif
-#if defined (CONFIG_MODEM_SOUND)
- &modem_sound_device,
-#endif
-#ifdef CONFIG_ANDROID_TIMED_GPIO
- &rk29_device_vibrator,
-#endif
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- &rk29sdk_wifi_device,
-#endif
-#ifdef CONFIG_MT5931_MT6622
- &device_mt6622,
-#endif
-#ifdef CONFIG_RFKILL_RK
- &device_rfkill_rk,
-#endif
-
-#ifdef CONFIG_TCC_BT_DEV
- &device_tcc_bt,
-#endif
-};
-//i2c
-#ifdef CONFIG_I2C0_RK30
-#ifdef CONFIG_MFD_TPS65910
-#define TPS65910_HOST_IRQ RK2928_PIN3_PC6
-#include "board-rk2928-phonepad-tps65910.c"
-#endif
-#ifdef CONFIG_REGULATOR_ACT8931
-#define ACT8931_HOST_IRQ RK2928_PIN1_PB2
-#include "board-rk2928-sdk-act8931.c"
-#endif
-
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-#if defined (CONFIG_REGULATOR_ACT8931)
- {
- .type = "act8931",
- .addr = 0x5b,
- .flags = 0,
- .irq = ACT8931_HOST_IRQ,
- .platform_data=&act8931_data,
- },
-#endif
-};
-#endif
-#ifdef CONFIG_MACH_RK2926_M713
-int __sramdata gpio0d3_iomux,gpio0d3_do,gpio0d3_dir;
-#else
-int __sramdata gpio0d4_iomux,gpio0d4_do,gpio0d4_dir;
-#endif
-
-#define gpio0_readl(offset) readl_relaxed(RK2928_GPIO0_BASE + offset)
-#define gpio0_writel(v, offset) do { writel_relaxed(v, RK2928_GPIO0_BASE + offset); dsb(); } while (0)
-
-void __sramfunc rk30_pwm_logic_suspend_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
-
-#ifdef CONFIG_MACH_RK2926_M713
- sram_udelay(10000);
- gpio0d3_iomux = readl_relaxed(GRF_GPIO0D_IOMUX);
- gpio0d3_do = gpio0_readl(GPIO_SWPORTA_DR);
- gpio0d3_dir = gpio0_readl(GPIO_SWPORTA_DDR);
-
- writel_relaxed((gpio0d3_iomux |(1<<22)) & (~(1<<6)), GRF_GPIO0D_IOMUX);
- gpio0_writel(gpio0d3_dir |(1<<27), GPIO_SWPORTA_DDR);
- gpio0_writel(gpio0d3_do |(1<<27), GPIO_SWPORTA_DR);
-#else
-// int gpio0d7_iomux,gpio0d7_do,gpio0d7_dir,gpio0d7_en;
- sram_udelay(10000);
- gpio0d4_iomux = readl_relaxed(GRF_GPIO0D_IOMUX);
- gpio0d4_do = gpio0_readl(GPIO_SWPORTA_DR);
- gpio0d4_dir = gpio0_readl(GPIO_SWPORTA_DDR);
-
- writel_relaxed((gpio0d4_iomux |(1<<24)) & (~(1<<8)), GRF_GPIO0D_IOMUX);
- gpio0_writel(gpio0d4_dir |(1<<28), GPIO_SWPORTA_DDR);
- gpio0_writel(gpio0d4_do |(1<<28), GPIO_SWPORTA_DR);
-#endif
-
-#endif
-}
-void __sramfunc rk30_pwm_logic_resume_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
-#ifdef CONFIG_MACH_RK2926_M713
- writel_relaxed((1<<22)|gpio0d3_iomux, GRF_GPIO0D_IOMUX);
- gpio0_writel(gpio0d3_dir, GPIO_SWPORTA_DDR);
- gpio0_writel(gpio0d3_do, GPIO_SWPORTA_DR);
- sram_udelay(10000);
-#else
- writel_relaxed((1<<24)|gpio0d4_iomux, GRF_GPIO0D_IOMUX);
- gpio0_writel(gpio0d4_dir, GPIO_SWPORTA_DDR);
- gpio0_writel(gpio0d4_do, GPIO_SWPORTA_DR);
- sram_udelay(10000);
- sram_udelay(10000);
- sram_udelay(10000);
-
-#endif
-
-#endif
-
-}
-extern void pwm_suspend_voltage(void);
-extern void pwm_resume_voltage(void);
-void rk30_pwm_suspend_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_suspend_voltage();
-#endif
-}
-void rk30_pwm_resume_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_resume_voltage();
-#endif
-}
-
-void __sramfunc board_pmu_suspend(void)
-{
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_suspend();
- #endif
-}
-void __sramfunc board_pmu_resume(void)
-{
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_resume();
- #endif
-}
-
-#ifdef CONFIG_I2C1_RK30
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_GS_MMA7660)
- {
- .type = "gs_mma7660",
- .addr = 0x4c,
- .flags = 0,
- .irq = MMA7660_INT_PIN,
- .platform_data = &mma7660_info,
- },
-#endif
-
-#if defined (CONFIG_GS_KXTIK)
- {
- .type = "gs_kxtik",
- .addr = 0x0F,
- .flags = 0,
- .platform_data = &kxtik_pdata,
- .irq = KXTIK_INT_PIN, // Replace with appropriate GPIO setup
- },
-#endif
-
-#if defined (CONFIG_GS_MM3A310)
- {
- .type = "gs_mm3a310",
- .addr = 0x27,
- .flags = 0,
- .platform_data = &mm3a310_pdata,
- .irq = MM3A310_INT_PIN, // Replace with appropriate GPIO setup
- },
-#endif
-
-#ifdef CONFIG_LS_AP321XX
- {
- .type = "ls_ap321xx",
- .addr = 0x1E,
- .flags = 0,
- .irq = LS_AP321XX_INT_PIN,
- .platform_data = &ls_ap321xx_info
- },
-#endif
-
-#ifdef CONFIG_PS_AP321XX
- {
- .type = "ps_ap321xx",
- .addr = 0x1E,
- .flags = 0,
- .irq = PS_AP321XX_INT_PIN,
- .platform_data = &ps_ap321xx_info
- },
-#endif
-
-#ifdef CONFIG_RDA5990
-#define RDA_WIFI_CORE_ADDR (0x13)
-#define RDA_WIFI_RF_ADDR (0x14) //correct add is 0x14
-#define RDA_BT_CORE_ADDR (0x15)
-#define RDA_BT_RF_ADDR (0x16)
-
-#define RDA_WIFI_RF_I2C_DEVNAME "rda_wifi_rf_i2c"
-#define RDA_WIFI_CORE_I2C_DEVNAME "rda_wifi_core_i2c"
-#define RDA_BT_RF_I2C_DEVNAME "rda_bt_rf_i2c"
-#define RDA_BT_CORE_I2C_DEVNAME "rda_bt_core_i2c"
- {
- .type = RDA_WIFI_CORE_I2C_DEVNAME,
- .addr = RDA_WIFI_CORE_ADDR,
- .flags = 0,
-
- },
-
- {
- .type = RDA_WIFI_RF_I2C_DEVNAME,
- .addr = RDA_WIFI_RF_ADDR,
- .flags = 0,
-
- },
- {
- .type = RDA_BT_CORE_I2C_DEVNAME,
- .addr = RDA_BT_CORE_ADDR,
- .flags = 0,
-
- },
- {
- .type = RDA_BT_RF_I2C_DEVNAME,
- .addr = RDA_BT_RF_ADDR,
- .flags = 0,
-
- },
-#endif
-
-};
-#endif
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-#if defined (CONFIG_TP_760_TS)
- {
- .type = "ft5x0x_ts",
- .addr = 0x38,
- .flags = 0,
- .irq = TOUCH_INT_PIN,
- .platform_data = &ft5306_info,
- },
-#endif
-#if defined(CONFIG_TOUCHSCREEN_BYD693X)
- {
- .type = "byd693x-ts",
- .addr = 0x52,
- .flags = 0,
- .irq = TOUCH_INT_PIN,
- .platform_data = &byd693x_info,
- },
-#endif
-#if defined(CONFIG_TOUCHSCREEN_GT82X_IIC_760)
- {
- .type = "Goodix-TS-82X",
- .addr = 0x5D,
- .flags = 0,
- .irq = RK2928_PIN3_PC7,
- .platform_data = &ts82x_pdata,
- },
-#endif
-
-};
-#endif
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- //set iomux (gpio) here
-
- return 0;
-}
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(4, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-
-#define POWER_ON_PIN RK2928_PIN1_PA2 //power_hold
-#if defined(CONFIG_REGULATOR_ACT8931)
-extern int act8931_charge_det ;
-#endif
-static void rk2928_pm_power_off(void)
-{
- printk(KERN_ERR "rk2928_pm_power_off start...\n");
- #if defined(CONFIG_REGULATOR_ACT8931)
- if(pmic_is_act8931())
- {
- #ifdef CONFIG_BATTERY_RK30_ADC_FAC
- if (gpio_get_value (rk30_adc_battery_platdata.dc_det_pin) == rk30_adc_battery_platdata.dc_det_level)//if(act8931_charge_det)
- arm_pm_restart(0, NULL);
- #endif
- act8931_device_shutdown();
- }
- #endif
-
- #if defined(CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- {
- tps65910_device_shutdown();//tps65910 shutdown
- }
- #endif
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
-
-};
-
-static void __init rk2928_board_init(void)
-{
- gpio_request(POWER_ON_PIN, "poweronpin");
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
- pm_power_off = rk2928_pm_power_off;
-
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- rk29sdk_wifi_bt_gpio_control_init();
-#endif
-}
-
-static void __init rk2928_reserve(void)
-{
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0", RK30_FB0_MEM_SIZE);
- resource_fb[0].end = resource_fb[0].start + RK30_FB0_MEM_SIZE - 1;
-#endif
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
- board_mem_reserved();
-}
-/**
- * dvfs_cpu_logic_table: table for arm and logic dvfs
- * @frequency : arm frequency
- * @cpu_volt : arm voltage depend on frequency
- * @logic_volt : logic voltage arm requests depend on frequency
- * comments : min arm/logic voltage
- */
-static struct dvfs_arm_table dvfs_cpu_logic_table[] = {
- {.frequency = 216 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 312 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 408 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 504 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 600 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 696 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 816 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 912 * 1000, .cpu_volt = 1450 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 1008 * 1000, .cpu_volt = 1500 * 1000, .logic_volt = 1200 * 1000},
-#if 0
- {.frequency = 1104 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 1200 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 1104 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 1248 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
-#endif
- {.frequency = CPUFREQ_TABLE_END},
-
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- {.frequency = 266 * 1000, .index = 1200 * 1000},
- {.frequency = 400 * 1000, .index = 1275 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 300 * 1000, .index = 1200 * 1000},
- {.frequency = 400 * 1000, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
-static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
-static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
-
-void __init board_clock_init(void)
-{
- rk2928_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
- dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
- printk("%s end\n", __func__);
-}
-
-
-MACHINE_START(RK2928, "RK2928board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk2928_fixup,
- .reserve = &rk2928_reserve,
- .map_io = rk2928_map_io,
- .init_irq = rk2928_init_irq,
- .timer = &rk2928_timer,
- .init_machine = rk2928_board_init,
-MACHINE_END
+++ /dev/null
-#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Macro Define Begin ------------------------*/
-/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
-#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_HM2057 /* back camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_0 0x48
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 1
-#define CONFIG_SENSOR_CIF_INDEX_0 0
-#define CONFIG_SENSOR_ORIENTATION_0 90
-#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 RK2928_PIN3_PB3
-#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000
-
-#define CONFIG_SENSOR_01 RK29_CAM_SENSOR_OV5642 /* back camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_01 0x00
-#define CONFIG_SENSOR_CIF_INDEX_01 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 4
-#define CONFIG_SENSOR_ORIENTATION_01 90
-#define CONFIG_SENSOR_POWER_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_01 INVALID_GPIO//RK2928_PIN3_PB3
-#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_01 30000
-
-#define CONFIG_SENSOR_02 RK29_CAM_SENSOR_OV5640 /* back camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_02 0x00
-#define CONFIG_SENSOR_CIF_INDEX_02 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 4
-#define CONFIG_SENSOR_ORIENTATION_02 90
-#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_02 INVALID_GPIO//RK2928_PIN3_PB3
-#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000
-
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_HI704 /* front camera sensor 0 */
-#define CONFIG_SENSOR_IIC_ADDR_1 0x60
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 1
-#define CONFIG_SENSOR_CIF_INDEX_1 0
-#define CONFIG_SENSOR_ORIENTATION_1 270
-#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_1 RK2928_PIN3_PB3
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000
-
-#define CONFIG_SENSOR_11 RK29_CAM_SENSOR_GC0329 /* front camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_11 0x62
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 1
-#define CONFIG_SENSOR_CIF_INDEX_11 0
-#define CONFIG_SENSOR_ORIENTATION_11 270
-#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_11 RK2928_PIN3_PD7
-#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_11 30000
-
-#define CONFIG_SENSOR_12 RK29_CAM_SENSOR_OV2659//RK29_CAM_SENSOR_OV2655 /* front camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_12 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 3
-#define CONFIG_SENSOR_CIF_INDEX_12 0
-#define CONFIG_SENSOR_ORIENTATION_12 270
-#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_12 30000
-
-
-#endif //#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk2928_camera.c"
-/*---------------- Camera Sensor Macro Define End ---------*/
-
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#define CONFIG_SENSOR_POWER_IOCTL_USR 0 //define this refer to your board layout
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
-
-static void rk_cif_power(int on)
-{
- struct regulator *ldo_18,*ldo_28;
- ldo_28 = regulator_get(NULL, "vaux1"); // vcc28_cif
- ldo_18 = regulator_get(NULL, "vdig1"); // vcc18_cif
- if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){
- printk("get cif ldo failed!\n");
- return;
- }
- if(on == 0){
- regulator_disable(ldo_28);
- regulator_put(ldo_28);
- regulator_disable(ldo_18);
- regulator_put(ldo_18);
- mdelay(500);
- }
- else{
- regulator_set_voltage(ldo_28, 2800000, 2800000);
- regulator_enable(ldo_28);
- // printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
- regulator_put(ldo_28);
-
- regulator_set_voltage(ldo_18, 1800000, 1800000);
- // regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(ldo_18);
- // printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
- regulator_put(ldo_18);
- }
-}
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- //#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
- rk_cif_power(on);
-}
-#endif
-
-#if CONFIG_SENSOR_RESET_IOCTL_USR
-static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
-static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-
-#if CONFIG_SENSOR_IIC_ADDR_0
-static struct reginfo_t rk_init_data_sensor_reg_0[] =
-{
- {0x0000, 0x00,0,0}
- };
-static struct reginfo_t rk_init_data_sensor_winseqreg_0[] ={
- {0x0000, 0x00,0,0}
- };
-#endif
-
-#if CONFIG_SENSOR_IIC_ADDR_1
-static struct reginfo_t rk_init_data_sensor_reg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_01
-static struct reginfo_t rk_init_data_sensor_reg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_02
-static struct reginfo_t rk_init_data_sensor_reg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_11
-static struct reginfo_t rk_init_data_sensor_reg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_12
-static struct reginfo_t rk_init_data_sensor_reg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] =
-{
- #if CONFIG_SENSOR_IIC_ADDR_0
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_0,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_1
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_1,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_01
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_01,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_02
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_02,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_11
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_11,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_12
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_12,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
-
- };
-#include "../../../drivers/media/video/rk2928_camera.c"
-
-#endif /* CONFIG_VIDEO_RK29 */
+++ /dev/null
-#include <mach/gpio.h>
-#include <plat/key.h>
-
-#define EV_ENCALL KEY_F4
-#define EV_MENU KEY_F1
-
-#define PRESS_LEV_LOW 1
-#define PRESS_LEV_HIGH 0
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK2928_PIN1_PA4,
- .active_low = PRESS_LEV_LOW,
- //.code_long_press = EV_ENCALL,
- .wakeup = 1,
- },
-#if defined(CONFIG_MACH_RK2928_PHONEPAD_760)
- {
- .desc = "vol+",
- .code = KEY_VOLUMEDOWN,
- .gpio = INVALID_GPIO,
- .adc_value = 1,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEUP,
- .gpio = INVALID_GPIO,
- .adc_value = 512,
- .active_low = PRESS_LEV_LOW,
- },
-#else
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .gpio = INVALID_GPIO,
- .adc_value = 1,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .gpio = INVALID_GPIO,
- .adc_value = 512,
- .active_low = PRESS_LEV_LOW,
- },
-
-#endif
-
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = 1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
+++ /dev/null
-/* arch/arm/mach-rk30/board-rk30-sdk-sdmmc.c
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * *
- * History:
- * ver1.0 add combo-wifi operateions. such as commit e049351a09c78db8a08aa5c49ce8eba0a3d6824e, at 2012-09-16
- * ver2.0 Unify all the file versions of board_xxxx_sdmmc.c, at 2012-11-05
- *
- * Content:
- * Part 1: define the gpio for SD-MMC-SDIO-Wifi functions according to your own projects.
- ***********************************************************************************
- * Please set the value according to your own project.
- ***********************************************************************************
- *
- * Part 2: define the gpio for the SDMMC controller. Based on the chip datasheet.
- ***********************************************************************************
- * Please do not change, each platform has a fixed set. !!!!!!!!!!!!!!!!!!
- * The system personnel will set the value depending on the specific arch datasheet,
- * such as RK29XX, RK30XX.
- * If you have any doubt, please consult BangWang Xie.
- ***********************************************************************************
- *
- *.Part 3: The various operations of the SDMMC-SDIO module
- ***********************************************************************************
- * Please do not change, each platform has a fixed set. !!!!!!!!!!!!!!!!!!
- * define the varaious operations for SDMMC module
- * Generally only the author of SDMMC module will modify this section.
- * If you have any doubt, please consult BangWang Xie.
- ***********************************************************************************
- *
- *.Part 4: The various operations of the Wifi-BT module
- ***********************************************************************************
- * Please do not change, each module has a fixed set. !!!!!!!!!!!!!!!!!!
- * define the varaious operations for Wifi module
- * Generally only the author of Wifi module will modify this section.
- * If you have any doubt, please consult BangWang Xie, Weiguo Hu, and Weilong Gao.
- ***********************************************************************************
- *
- */
-
-//1.Part 1: define the gpio for SD-MMC-SDIO-Wifi functions according to your own projects.
-
-/*************************************************************************
-* define the gpio for sd-sdio-wifi module
-*************************************************************************/
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
-#define SDMMC0_WRITE_PROTECT_PIN RK30_PIN3_PB2 //According to your own project to set the value of write-protect-pin.
-#define SDMMC0_WRITE_PROTECT_ENABLE_VALUE GPIO_HIGH
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
-#define SDMMC1_WRITE_PROTECT_PIN RK30_PIN3_PB3 //According to your own project to set the value of write-protect-pin.
-#define SDMMC1_WRITE_PROTECT_ENABLE_VALUE GPIO_HIGH
-#endif
-
-#if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
-#define RK29SDK_WIFI_SDIO_CARD_INT RK30_PIN3_PD2
-#endif
-
-//define the card-detect-pin.
-#if defined(CONFIG_ARCH_RK29)
-//refer to file /arch/arm/mach-rk29/include/mach/Iomux.h
-//define reset-pin
-#define RK29SDK_SD_CARD_DETECT_N RK29_PIN2_PA2 //According to your own project to set the value of card-detect-pin.
-#define RK29SDK_SD_CARD_INSERT_LEVEL GPIO_LOW // set the voltage of insert-card. Please pay attention to the default setting.
-#define RK29SDK_SD_CARD_DETECT_PIN_NAME GPIO2A2_SDMMC0DETECTN_NAME
-#define RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO GPIO2L_GPIO2A2
-#define RK29SDK_SD_CARD_DETECT_IOMUX_FMUX GPIO2L_SDMMC0_DETECT_N
-//define PowerEn-pin
-#define RK29SDK_SD_CARD_PWR_EN RK29_PIN5_PD5
-#define RK29SDK_SD_CARD_PWR_EN_LEVEL GPIO_LOW
-#define RK29SDK_SD_CARD_PWR_EN_PIN_NAME GPIO5D5_SDMMC0PWREN_NAME
-#define RK29SDK_SD_CARD_PWR_EN_IOMUX_FGPIO GPIO5H_GPIO5D5
-#define RK29SDK_SD_CARD_PWR_EN_IOMUX_FMUX GPIO5H_SDMMC0_PWR_EN
-
-#elif defined(CONFIG_ARCH_RK3066B)
-//refer to file /arch/arm/mach-rk30/include/mach/iomux-rk3066b.h
-//define reset-pin
-#define RK29SDK_SD_CARD_DETECT_N RK30_PIN3_PB0 //According to your own project to set the value of card-detect-pin.
-#define RK29SDK_SD_CARD_INSERT_LEVEL GPIO_LOW // set the voltage of insert-card. Please pay attention to the default setting.
-#define RK29SDK_SD_CARD_DETECT_PIN_NAME GPIO3B0_SDMMC0DETECTN_NAME
-#define RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO GPIO3B_GPIO3B0
-#define RK29SDK_SD_CARD_DETECT_IOMUX_FMUX GPIO3B_SDMMC0_DETECT_N
-//define PowerEn-pin
-#define RK29SDK_SD_CARD_PWR_EN RK30_PIN3_PA1
-#define RK29SDK_SD_CARD_PWR_EN_LEVEL GPIO_LOW
-#define RK29SDK_SD_CARD_PWR_EN_PIN_NAME GPIO3A1_SDMMC0PWREN_NAME
-#define RK29SDK_SD_CARD_PWR_EN_IOMUX_FGPIO GPIO3A_GPIO3A1
-#define RK29SDK_SD_CARD_PWR_EN_IOMUX_FMUX GPIO3A_SDMMC0PWREN
-
-#elif defined(CONFIG_ARCH_RK30)&& !defined(CONFIG_ARCH_RK3066B) //for RK30,RK3066 SDK
-//refer to file /arch/arm/mach-rk30/include/mach/Iomux.h
-//define reset-pin
-#define RK29SDK_SD_CARD_DETECT_N RK30_PIN3_PB6 //According to your own project to set the value of card-detect-pin.
-#define RK29SDK_SD_CARD_INSERT_LEVEL GPIO_LOW // set the voltage of insert-card. Please pay attention to the default setting.
-#define RK29SDK_SD_CARD_DETECT_PIN_NAME GPIO3B6_SDMMC0DETECTN_NAME
-#define RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO GPIO3B_GPIO3B6
-#define RK29SDK_SD_CARD_DETECT_IOMUX_FMUX GPIO3B_SDMMC0_DETECT_N
-//define PowerEn-pin
-#define RK29SDK_SD_CARD_PWR_EN RK30_PIN3_PA7
-#define RK29SDK_SD_CARD_PWR_EN_LEVEL GPIO_LOW
-#define RK29SDK_SD_CARD_PWR_EN_PIN_NAME GPIO3A7_SDMMC0PWREN_NAME
-#define RK29SDK_SD_CARD_PWR_EN_IOMUX_FGPIO GPIO3A_GPIO3A7
-#define RK29SDK_SD_CARD_PWR_EN_IOMUX_FMUX GPIO3A_SDMMC0_PWR_EN
-
-#elif defined(CONFIG_ARCH_RK2928)
-//refer to file ./arch/arm/mach-rk2928/include/mach/iomux.h
-//define reset-pin
- #if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO) && defined(CONFIG_MACH_RK2928_PHONEPAD) //for i30 no detect pin
- //use gpio-interupt to dectec card in RK2926. Please pay attention to modify the default setting.
- #define RK29SDK_SD_CARD_DETECT_N INVALID_GPIO //According to your own project to set the value of card-detect-pin.
- #define RK29SDK_SD_CARD_INSERT_LEVEL GPIO_LOW // set the voltage of insert-card. Please pay attention to the default setting.
- #define RK29SDK_SD_CARD_DETECT_PIN_NAME GPIO2A7_NAND_DPS_EMMC_CLKOUT_NAME
- #define RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO GPIO2A_GPIO2A7
- #define RK29SDK_SD_CARD_DETECT_IOMUX_FMUX GPIO2A_EMMC_CLKOUT
- #else
- #define RK29SDK_SD_CARD_DETECT_N RK2928_PIN1_PC1 //According to your own project to set the value of card-detect-pin.
- #define RK29SDK_SD_CARD_INSERT_LEVEL GPIO_LOW // set the voltage of insert-card. Please pay attention to the default setting.
- #define RK29SDK_SD_CARD_DETECT_PIN_NAME GPIO1C1_MMC0_DETN_NAME
- #define RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO GPIO1C_GPIO1C1
- #define RK29SDK_SD_CARD_DETECT_IOMUX_FMUX GPIO1C_MMC0_DETN
- #endif
-//define PowerEn-pin
- #define RK29SDK_SD_CARD_PWR_EN INVALID_GPIO
- //#define RK29SDK_SD_CARD_PWR_EN RK2928_PIN1_PB6
- #define RK29SDK_SD_CARD_PWR_EN_LEVEL GPIO_LOW
- //#define RK29SDK_SD_CARD_PWR_EN_PIN_NAME GPIO1B6_MMC0_PWREN_NAME
- //#define RK29SDK_SD_CARD_PWR_EN_IOMUX_FGPIO GPIO1B_GPIO1B6
- //#define RK29SDK_SD_CARD_PWR_EN_IOMUX_FMUX GPIO1B_MMC0_PWREN
- #endif
-
-static void rk29_sdmmc_board_setpower(struct device *dev, char *regulator_supply_name)
-{
-#if !defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO == RK29SDK_SD_CARD_PWR_EN)
- memset(regulator_supply_name, 0,4);
-#else
- //set the PMU-LDO-supply name to NULL, if you use gpio to control power on-off.
- memset(regulator_supply_name, 0,4);
-#endif
-}
-
-//
-// Define wifi module's power and reset gpio, and gpio sensitive level.
-// Please set the value according to your own project.
-//
-#if defined(CONFIG_ARCH_RK30) && !defined(CONFIG_ARCH_RK3066B) //for RK30,RK3066 SDK
- #define WIFI_HOST_WAKE RK30_PIN3_PD2
-
- #if defined(CONFIG_RK903) || defined(CONFIG_RK901) || defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU)
- //power
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- //reset
- #define RK30SDK_WIFI_GPIO_POWER_PIN_NAME GPIO3D0_SDMMC1PWREN_NAME
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO3D_GPIO3D0
-
- #elif defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319)
- //power
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_POWER_PIN_NAME GPIO3D0_SDMMC1PWREN_NAME
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO3D_GPIO3D0
- //reset
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_RESET_PIN_NAME GPIO3D1_SDMMC1BACKENDPWR_NAME
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FGPIO GPIO3D_GPIO3D1
-
- #elif defined(CONFIG_MT6620)
- #if !defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- #define USE_SDMMC_CONTROLLER_FOR_WIFI 1
-
- #if defined(CONFIG_MACH_RK30_PHONE_PAD) // define the gpio for MT6620 in RK30_PHONE_PAD project.
- #define COMBO_MODULE_MT6620_CDT 0 //- 1--use Cdtech chip; 0--unuse CDT chip
- //power, PMU_EN
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PC7
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_POWER_PIN_NAME GPIO3C7_SDMMC1WRITEPRT_NAME
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO3C_GPIO3C7
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FMUX GPIO3C_SDMMC1_WRITE_PRT
- //reset, DAIRST,SYSRST_B
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_RESET_PIN_NAME GPIO3D1_SDMMC1BACKENDPWR_NAME
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FGPIO GPIO3D_GPIO3D1
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FMUX GPIO3D_SDMMC1_BACKEND_PWR
- //VDDIO
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL RK30_PIN6_PB4
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_ENABLE_VALUE GPIO_HIGH
- //WIFI_INT_B
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN4_PD2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_PIN_NAME GPIO4D2_SMCDATA10_TRACEDATA10_NAME
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FGPIO GPIO4D_GPIO4D2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FMUX GPIO4D_SMC_DATA10
- //BGF_INT_B
- #define RK30SDK_WIFI_GPIO_BGF_INT_B RK30_PIN6_PA7
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_ENABLE_VALUE GPIO_HIGH
- //#define RK30SDK_WIFI_GPIO_BGF_INT_B_PIN_NAME GPIO3C6_SDMMC1DETECTN_NAME
- //#define RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FGPIO GPIO3C_GPIO3C6
- //#define RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FMUX GPIO3C_SDMMC1_DETECT_N
- //GPS_SYNC
- #define RK30SDK_WIFI_GPIO_GPS_SYNC RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_PIN_NAME GPIO3D0_SDMMC1PWREN_NAME
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FGPIO GPIO3D_GPIO3D0
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FMUX GPIO3D_SDMMC1_PWR_EN
-
- #elif defined(CONFIG_MACH_RK3066_M8000R) // define the gpio for MT6620 in CONFIG_MACH_RK3066_M8000R project.
- #define COMBO_MODULE_MT6620_CDT 1 //- 1--use Cdtech chip; 0--unuse CDT chip
- //power, PMU_EN
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PC7
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_POWER_PIN_NAME GPIO3C7_SDMMC1WRITEPRT_NAME
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO3C_GPIO3C7
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FMUX GPIO3C_SDMMC1_WRITE_PRT
- //reset, DAIRST,SYSRST_B
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_RESET_PIN_NAME GPIO3D1_SDMMC1BACKENDPWR_NAME
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FGPIO GPIO3D_GPIO3D1
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FMUX GPIO3D_SDMMC1_BACKEND_PWR
- //VDDIO
- #define RK30SDK_WIFI_GPIO_VCCIO_WL RK30_PIN0_PD2
- #define RK30SDK_WIFI_GPIO_VCCIO_WL_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_VCCIO_WL_PIN_NAME GPIO0D2_I2S22CHLRCKRX_SMCOEN_NAME
- #define RK30SDK_WIFI_GPIO_VCCIO_WL_IOMUX_FGPIO GPIO0D_GPIO0D2
- #define RK30SDK_WIFI_GPIO_VCCIO_WL_IOMUX_FMUX GPIO0D_I2S2_2CH_LRCK_RX
- //WIFI_INT_B
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_PIN_NAME GPIO3D2_SDMMC1INTN_NAME
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FGPIO GPIO3D_GPIO3D2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FMUX GPIO3D_SDMMC1_INT_N
- //BGF_INT_B
- #define RK30SDK_WIFI_GPIO_BGF_INT_B RK30_PIN6_PA7
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_ENABLE_VALUE GPIO_HIGH
- //#define RK30SDK_WIFI_GPIO_BGF_INT_B_PIN_NAME GPIO3C6_SDMMC1DETECTN_NAME
- //#define RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FGPIO GPIO3C_GPIO3C6
- // #define RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FMUX GPIO3C_SDMMC1_DETECT_N
- //GPS_SYNC
- #define RK30SDK_WIFI_GPIO_GPS_SYNC RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_PIN_NAME GPIO3D0_SDMMC1PWREN_NAME
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FGPIO GPIO3D_GPIO3D0
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FMUX GPIO3D_SDMMC1_PWR_EN
-
- #if COMBO_MODULE_MT6620_CDT
- //ANTSEL2
- //#define RK30SDK_WIFI_GPIO_ANTSEL2 RK30_PIN4_PD4
- //#define RK30SDK_WIFI_GPIO_ANTSEL2_ENABLE_VALUE GPIO_LOW //use 6620 in CDT chip, LOW--work; High--no work.
- //#define RK30SDK_WIFI_GPIO_ANTSEL2_PIN_NAME GPIO4D4_SMCDATA12_TRACEDATA12_NAME
- //#define RK30SDK_WIFI_GPIO_ANTSEL2_IOMUX_FGPIO GPIO4D_GPIO4D4
- //#define RK30SDK_WIFI_GPIO_ANTSEL2_IOMUX_FMUX GPIO4D_TRACE_DATA12
- //ANTSEL3
- //#define RK30SDK_WIFI_GPIO_ANTSEL3 RK30_PIN4_PD3
- //#define RK30SDK_WIFI_GPIO_ANTSEL3_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- //#define RK30SDK_WIFI_GPIO_ANTSEL3_PIN_NAME GPIO4D3_SMCDATA11_TRACEDATA11_NAME
- //#define RK30SDK_WIFI_GPIO_ANTSEL3_IOMUX_FGPIO GPIO4D_GPIO4D3
- //#define RK30SDK_WIFI_GPIO_ANTSEL3_IOMUX_FMUX GPIO4D_TRACE_DATA11
- //GPS_LAN
- //#define RK30SDK_WIFI_GPIO_GPS_LAN RK30_PIN4_PD6
- //#define RK30SDK_WIFI_GPIO_GPS_LAN_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- //#define RK30SDK_WIFI_GPIO_GPS_LAN_PIN_NAME GPIO4D6_SMCDATA14_TRACEDATA14_NAME
- //#define RK30SDK_WIFI_GPIO_GPS_LAN_IOMUX_FGPIO GPIO4D_GPIO4D6
- //#define RK30SDK_WIFI_GPIO_GPS_LAN_IOMUX_FMUX GPIO4D_TRACE_DATA14
- #endif // #if COMBO_MODULE_MT6620_CDT--#endif
-
- #elif defined(CONFIG_MACH_SKYWORTH_T10_SDK) // define the gpio for MT6620 in KYWORTH_T10 project.
- #define COMBO_MODULE_MT6620_CDT 0 //- 1--use Cdtech chip; 0--unuse CDT chip
- //power, PMU_EN
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_POWER_PIN_NAME GPIO3D0_SDMMC1PWREN_NAME
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO3D_GPIO3D0
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FMUX GPIO3D_SDMMC1_PWR_EN
- //reset, DAIRST,SYSRST_B
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_RESET_PIN_NAME GPIO3D1_SDMMC1BACKENDPWR_NAME
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FGPIO GPIO3D_GPIO3D1
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FMUX GPIO3D_SDMMC1_BACKEND_PWR
- //VDDIO
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL RK30_PIN6_PB4
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_ENABLE_VALUE GPIO_HIGH
- //WIFI_INT_B
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_PIN_NAME GPIO3D2_SDMMC1INTN_NAME
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FGPIO GPIO3D_GPIO3D2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FMUX GPIO3D_SDMMC1_INT_N
- //BGF_INT_B
- #define RK30SDK_WIFI_GPIO_BGF_INT_B RK30_PIN3_PC6
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_PIN_NAME GPIO3C6_SDMMC1DETECTN_NAME
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FGPIO GPIO3C_GPIO3C6
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FMUX GPIO3C_SDMMC1_DETECT_N
- //GPS_SYNC
- #define RK30SDK_WIFI_GPIO_GPS_SYNC RK30_PIN3_PC7
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_PIN_NAME GPIO3C7_SDMMC1WRITEPRT_NAME
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FGPIO GPIO3C_GPIO3C7
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FMUX GPIO3C_SDMMC1_WRITE_PRT
-
- #else //For exmpale, to define the gpio for MT6620 in RK30SDK project.
- #define COMBO_MODULE_MT6620_CDT 1 //- 1--use Cdtech chip; 0--unuse CDT chip
- //power
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_POWER_PIN_NAME GPIO3D0_SDMMC1PWREN_NAME
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO3D_GPIO3D0
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FMUX GPIO3D_SDMMC1_PWR_EN
- //reset
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_RESET_PIN_NAME GPIO3D1_SDMMC1BACKENDPWR_NAME
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FGPIO GPIO3D_GPIO3D1
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FMUX GPIO3D_SDMMC1_BACKEND_PWR
- //VDDIO
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL RK30_PIN0_PD2
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_ENABLE_VALUE GPIO_HIGH
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_PIN_NAME GPIO0D2_I2S22CHLRCKRX_SMCOEN_NAME
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_IOMUX_FGPIO GPIO0D_GPIO0D2
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_IOMUX_FMUX GPIO0D_I2S2_2CH_LRCK_RX
- //WIFI_INT_B
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_PIN_NAME GPIO3D2_SDMMC1INTN_NAME
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FGPIO GPIO3D_GPIO3D2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FMUX GPIO3D_SDMMC1_INT_N
- //BGF_INT_B
- #define RK30SDK_WIFI_GPIO_BGF_INT_B RK30_PIN3_PC6
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_PIN_NAME GPIO3C6_SDMMC1DETECTN_NAME
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FGPIO GPIO3C_GPIO3C6
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FMUX GPIO3C_SDMMC1_DETECT_N
- //GPS_SYNC
- #define RK30SDK_WIFI_GPIO_GPS_SYNC RK30_PIN3_PC7
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_PIN_NAME GPIO3C7_SDMMC1WRITEPRT_NAME
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FGPIO GPIO3C_GPIO3C7
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FMUX GPIO3C_SDMMC1_WRITE_PRT
-
- #if COMBO_MODULE_MT6620_CDT
- //ANTSEL2
- #define RK30SDK_WIFI_GPIO_ANTSEL2 RK30_PIN4_PD4
- #define RK30SDK_WIFI_GPIO_ANTSEL2_ENABLE_VALUE GPIO_LOW //use 6620 in CDT chip, LOW--work; High--no work.
- #define RK30SDK_WIFI_GPIO_ANTSEL2_PIN_NAME GPIO4D4_SMCDATA12_TRACEDATA12_NAME
- #define RK30SDK_WIFI_GPIO_ANTSEL2_IOMUX_FGPIO GPIO4D_GPIO4D4
- #define RK30SDK_WIFI_GPIO_ANTSEL2_IOMUX_FMUX GPIO4D_TRACE_DATA12
- //ANTSEL3
- #define RK30SDK_WIFI_GPIO_ANTSEL3 RK30_PIN4_PD3
- #define RK30SDK_WIFI_GPIO_ANTSEL3_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- #define RK30SDK_WIFI_GPIO_ANTSEL3_PIN_NAME GPIO4D3_SMCDATA11_TRACEDATA11_NAME
- #define RK30SDK_WIFI_GPIO_ANTSEL3_IOMUX_FGPIO GPIO4D_GPIO4D3
- #define RK30SDK_WIFI_GPIO_ANTSEL3_IOMUX_FMUX GPIO4D_TRACE_DATA11
- //GPS_LAN
- #define RK30SDK_WIFI_GPIO_GPS_LAN RK30_PIN4_PD6
- #define RK30SDK_WIFI_GPIO_GPS_LAN_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- #define RK30SDK_WIFI_GPIO_GPS_LAN_PIN_NAME GPIO4D6_SMCDATA14_TRACEDATA14_NAME
- #define RK30SDK_WIFI_GPIO_GPS_LAN_IOMUX_FGPIO GPIO4D_GPIO4D6
- //#define RK30SDK_WIFI_GPIO_GPS_LAN_IOMUX_FMUX GPIO4D_TRACE_DATA14
- #endif // #if COMBO_MODULE_MT6620_CDT--#endif
- #endif
- #endif// #endif --#if !defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- #endif
-#elif defined(CONFIG_ARCH_RK3066B)//refer to file /arch/arm/mach-rk30/include/mach/iomux-rk3066b.h
- #define WIFI_HOST_WAKE RK30_PIN3_PD2
-
- #if defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU)
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_POWER_PIN_NAME GPIO3D0_SDMMC1PWREN_MIIMD_NAME
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO3D_GPIO3D0
-
- #elif defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319) || defined(CONFIG_RK903) || defined(CONFIG_RK901)
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_POWER_PIN_NAME GPIO3D0_SDMMC1PWREN_MIIMD_NAME
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO3D_GPIO3D0
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN2_PA7
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_RESET_PIN_NAME GPIO2A7_LCDC1DATA7_SMCDATA7_TRACEDATA7_NAME
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FGPIO GPIO2A_GPIO2A7
- #endif
-#elif defined(CONFIG_ARCH_RK2928) //refer to file ./arch/arm/mach-rk2928/include/mach/iomux.h
-#define WIFI_HOST_WAKE RK2928_PIN3_PC0
-
- #if defined(CONFIG_RK903) || defined(CONFIG_RK901) || defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319)
- #define RK30SDK_WIFI_GPIO_POWER_N RK2928_PIN0_PD6
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_POWER_PIN_NAME GPIO0D6_MMC1_PWREN_NAME
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO0D_GPIO0D6
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK2928_PIN3_PC2
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_RESET_PIN_NAME GPIO3C2_SDMMC1DATA1_NAME
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FGPIO GPIO3C_GPIO3C2
-
- #elif defined(CONFIG_RDA5990)
- #define RK30SDK_WIFI_GPIO_POWER_N INVALID_GPIO
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- //#define RK30SDK_WIFI_GPIO_POWER_PIN_NAME GPIO0B6_MMC1_PWREN_NAME
- //#define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO0B_GPIO0B6
-
- #define RK30SDK_WIFI_GPIO_RESET_N INVALID_GPIO
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- //#define RK30SDK_WIFI_GPIO_RESET_PIN_NAME GPIO3C2_SDMMC1DATA1_NAME
- //#define RK30SDK_WIFI_GPIO_RESET_IOMUX_FGPIO GPIO3C_GPIO3C2
-
-
- #elif defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU) || defined(CONFIG_RT5370)
- #if defined(CONFIG_MACH_RK2926_V86)
- #define CONFIG_USB_WIFI_POWER_CONTROLED_BY_GPIO
- #define RK30SDK_WIFI_GPIO_POWER_N RK2928_PIN0_PD3
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_LOW
- #elif defined(CONFIG_MACH_RK2928_TR726)
- #define CONFIG_USB_WIFI_POWER_CONTROLED_BY_GPIO
- #define RK30SDK_WIFI_GPIO_POWER_N RK2928_PIN3_PD3
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_LOW
- #else
- #define RK30SDK_WIFI_GPIO_POWER_N RK2928_PIN0_PD6
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_LOW
- #endif
-
- #elif defined(CONFIG_MT5931) || defined(CONFIG_MT5931_MT6622)
- #define RK30SDK_WIFI_GPIO_POWER_N RK2928_PIN3_PD2
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK2928_PIN3_PD5
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
-
- #endif
-#endif
-
-
-//1. Part 2: to define the gpio for the SDMMC controller. Based on the chip datasheet.
-/*************************************************************************
-* define the gpio for SDMMC module on various platforms
-* Generally only system personnel will modify this part
-*************************************************************************/
-
-#if defined(CONFIG_ARCH_RK30)&& !defined(CONFIG_ARCH_RK3066B)//for RK30,RK3066 SDK
-/*
-* define the gpio for sdmmc0
-*/
-struct rksdmmc_gpio_board rksdmmc0_gpio_init = {
-
- .clk_gpio = {
- .io = RK30_PIN3_PB0,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3B0_SDMMC0CLKOUT_NAME,
- .fgpio = GPIO3B_GPIO3B0,
- .fmux = GPIO3B_SDMMC0_CLKOUT,
- },
- },
-
- .cmd_gpio = {
- .io = RK30_PIN3_PB1,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3B1_SDMMC0CMD_NAME,
- .fgpio = GPIO3B_GPIO3B1,
- .fmux = GPIO3B_SDMMC0_CMD,
- },
- },
-
- .data0_gpio = {
- .io = RK30_PIN3_PB2,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3B2_SDMMC0DATA0_NAME,
- .fgpio = GPIO3B_GPIO3B2,
- .fmux = GPIO3B_SDMMC0_DATA0,
- },
- },
-
- .data1_gpio = {
- .io = RK30_PIN3_PB3,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3B3_SDMMC0DATA1_NAME,
- .fgpio = GPIO3B_GPIO3B3,
- .fmux = GPIO3B_SDMMC0_DATA1,
- },
- },
-
- .data2_gpio = {
- .io = RK30_PIN3_PB4,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3B4_SDMMC0DATA2_NAME,
- .fgpio = GPIO3B_GPIO3B4,
- .fmux = GPIO3B_SDMMC0_DATA2,
- },
- },
-
- .data3_gpio = {
- .io = RK30_PIN3_PB5,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3B5_SDMMC0DATA3_NAME,
- .fgpio = GPIO3B_GPIO3B5,
- .fmux = GPIO3B_SDMMC0_DATA3,
- },
- },
-
- .power_en_gpio = {
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .io = RK29SDK_SD_CARD_PWR_EN,
- .enable = RK29SDK_SD_CARD_PWR_EN_LEVEL,
- #ifdef RK29SDK_SD_CARD_PWR_EN_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_PWR_EN_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_PWR_EN_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_PWR_EN_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_PWR_EN_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_PWR_EN_IOMUX_FMUX,
- #endif
- },
- #endif
-#else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-
- .detect_irq = {
-#if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
-#else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-};
-
-
-/*
-* define the gpio for sdmmc1
-*/
-static struct rksdmmc_gpio_board rksdmmc1_gpio_init = {
-
- .clk_gpio = {
- .io = RK30_PIN3_PC5,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C5_SDMMC1CLKOUT_NAME,
- .fgpio = GPIO3C_GPIO3C5,
- .fmux = GPIO3B_SDMMC0_CLKOUT,
- },
- },
-
- .cmd_gpio = {
- .io = RK30_PIN3_PC0,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C0_SMMC1CMD_NAME,
- .fgpio = GPIO3C_GPIO3C0,
- .fmux = GPIO3B_SDMMC0_CMD,
- },
- },
-
- .data0_gpio = {
- .io = RK30_PIN3_PC1,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C1_SDMMC1DATA0_NAME,
- .fgpio = GPIO3C_GPIO3C1,
- .fmux = GPIO3B_SDMMC0_DATA0,
- },
- },
-
- .data1_gpio = {
- .io = RK30_PIN3_PC2,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C2_SDMMC1DATA1_NAME,
- .fgpio = GPIO3C_GPIO3C2,
- .fmux = GPIO3B_SDMMC0_DATA1,
- },
- },
-
- .data2_gpio = {
- .io = RK30_PIN3_PC3,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C3_SDMMC1DATA2_NAME,
- .fgpio = GPIO3C_GPIO3C3,
- .fmux = GPIO3B_SDMMC0_DATA2,
- },
- },
-
- .data3_gpio = {
- .io = RK30_PIN3_PC4,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C4_SDMMC1DATA3_NAME,
- .fgpio = GPIO3C_GPIO3C4,
- .fmux = GPIO3B_SDMMC0_DATA3,
- },
- },
-};
- // ---end -#if defined(CONFIG_ARCH_RK30)
-
-#elif defined(CONFIG_ARCH_RK3066B)
-
-/*
-* define the gpio for sdmmc0
-*/
-static struct rksdmmc_gpio_board rksdmmc0_gpio_init = {
-
- .clk_gpio = {
- .io = RK30_PIN3_PB0,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3A2_SDMMC0CLKOUT_NAME,
- .fgpio = GPIO3A_GPIO3A2,
- .fmux = GPIO3A_SDMMC0CLKOUT,
- },
- },
-
- .cmd_gpio = {
- .io = RK30_PIN3_PB1,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3A3_SDMMC0CMD_NAME,
- .fgpio = GPIO3A_GPIO3A3,
- .fmux = GPIO3A_SDMMC0CMD,
- },
- },
-
- .data0_gpio = {
- .io = RK30_PIN3_PB2,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3A4_SDMMC0DATA0_NAME,
- .fgpio = GPIO3A_GPIO3A4,
- .fmux = GPIO3A_SDMMC0DATA0,
- },
- },
-
- .data1_gpio = {
- .io = RK30_PIN3_PB3,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3A5_SDMMC0DATA1_NAME,
- .fgpio = GPIO3A_GPIO3A5,
- .fmux = GPIO3A_SDMMC0DATA1,
- },
- },
-
- .data2_gpio = {
- .io = RK30_PIN3_PB4,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3A6_SDMMC0DATA2_NAME,
- .fgpio = GPIO3A_GPIO3A6,
- .fmux = GPIO3A_SDMMC0DATA2,
- },
- },
-
- .data3_gpio = {
- .io = RK30_PIN3_PB5,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3A7_SDMMC0DATA3_NAME,
- .fgpio = GPIO3A_GPIO3A7,
- .fmux = GPIO3A_SDMMC0DATA3,
- },
- },
-
-
- .power_en_gpio = {
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .io = RK29SDK_SD_CARD_PWR_EN,
- .enable = RK29SDK_SD_CARD_PWR_EN_LEVEL,
- #ifdef RK29SDK_SD_CARD_PWR_EN_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_PWR_EN_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_PWR_EN_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_PWR_EN_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_PWR_EN_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_PWR_EN_IOMUX_FMUX,
- #endif
- },
- #endif
-#else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-
- .detect_irq = {
-#if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
-#else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-
-};
-
-
-/*
-* define the gpio for sdmmc1
-*/
-static struct rksdmmc_gpio_board rksdmmc1_gpio_init = {
-
- .clk_gpio = {
- .io = RK30_PIN3_PC5,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C5_SDMMC1CLKOUT_RMIICLKOUT_RMIICLKIN_NAME,
- .fgpio = GPIO3C_GPIO3C5,
- .fmux = GPIO3C_SDMMC1CLKOUT,
- },
- },
-
- .cmd_gpio = {
- .io = RK30_PIN3_PC0,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C0_SDMMC1CMD_RMIITXEN_NAME,
- .fgpio = GPIO3C_GPIO3C0,
- .fmux = GPIO3C_SDMMC1CMD,
- },
- },
-
- .data0_gpio = {
- .io = RK30_PIN3_PC1,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C1_SDMMC1DATA0_RMIITXD1_NAME,
- .fgpio = GPIO3C_GPIO3C1,
- .fmux = GPIO3C_SDMMC1DATA0,
- },
- },
-
- .data1_gpio = {
- .io = RK30_PIN3_PC2,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C2_SDMMC1DATA1_RMIITXD0_NAME,
- .fgpio = GPIO3C_GPIO3C2,
- .fmux = GPIO3C_SDMMC1DATA1,
- },
- },
-
- .data2_gpio = {
- .io = RK30_PIN3_PC3,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C3_SDMMC1DATA2_RMIIRXD0_NAME,
- .fgpio = GPIO3C_GPIO3C3,
- .fmux = GPIO3C_SDMMC1DATA2,
- },
- },
-
- .data3_gpio = {
- .io = RK30_PIN3_PC4,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C4_SDMMC1DATA3_RMIIRXD1_NAME,
- .fgpio = GPIO3C_GPIO3C4,
- .fmux = GPIO3C_SDMMC1DATA3,
- },
- },
-};
-// ---end -#if defined(CONFIG_ARCH_RK3066B)
-
-#elif defined(CONFIG_ARCH_RK2928)
-/*
-* define the gpio for sdmmc0
-*/
-static struct rksdmmc_gpio_board rksdmmc0_gpio_init = {
-
- .clk_gpio = {
- .io = RK2928_PIN1_PC0,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO1C0_MMC0_CLKOUT_NAME,
- .fgpio = GPIO1C_GPIO1C0,
- .fmux = GPIO1C_MMC0_CLKOUT,
- },
- },
-
- .cmd_gpio = {
- .io = RK2928_PIN1_PC7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO1B7_MMC0_CMD_NAME,
- .fgpio = GPIO1B_GPIO1B7,
- .fmux = GPIO1B_MMC0_CMD,
- },
- },
-
- .data0_gpio = {
- .io = RK2928_PIN1_PC2,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO1C2_MMC0_D0_NAME,
- .fgpio = GPIO1C_GPIO1C2,
- .fmux = GPIO1C_MMC0_D0,
- },
- },
-
- .data1_gpio = {
- .io = RK2928_PIN1_PC3,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO1C3_MMC0_D1_NAME,
- .fgpio = GPIO1C_GPIO1C3,
- .fmux = GPIO1C_MMC0_D1,
- },
- },
-
- .data2_gpio = {
- .io = RK2928_PIN1_PC4,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO1C4_MMC0_D2_NAME,
- .fgpio = GPIO1C_GPIO1C4,
- .fmux = GPIO1C_MMC0_D2,
- },
- },
-
- .data3_gpio = {
- .io = RK2928_PIN1_PC5,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO1C5_MMC0_D3_NAME,
- .fgpio = GPIO1C_GPIO1C5,
- .fmux = GPIO1C_MMC0_D3,
- },
- },
-
-
- .power_en_gpio = {
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .io = RK29SDK_SD_CARD_PWR_EN,
- .enable = RK29SDK_SD_CARD_PWR_EN_LEVEL,
- #ifdef RK29SDK_SD_CARD_PWR_EN_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_PWR_EN_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_PWR_EN_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_PWR_EN_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_PWR_EN_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_PWR_EN_IOMUX_FMUX,
- #endif
- },
- #endif
-#else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-
- .detect_irq = {
-#if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
-#else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-};
-
-
-/*
-* define the gpio for sdmmc1
-*/
-static struct rksdmmc_gpio_board rksdmmc1_gpio_init = {
-
- .clk_gpio = {
- .io = RK2928_PIN0_PB1,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO0B1_MMC1_CLKOUT_NAME,
- .fgpio = GPIO0B_GPIO0B1,
- .fmux = GPIO0B_MMC1_CLKOUT,
- },
- },
-
- .cmd_gpio = {
- .io = RK2928_PIN0_PB0,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO0B0_MMC1_CMD_NAME,
- .fgpio = GPIO0B_GPIO0B0,
- .fmux = GPIO0B_MMC1_CMD,
- },
- },
-
- .data0_gpio = {
- .io = RK2928_PIN0_PB3,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO0B3_MMC1_D0_NAME,
- .fgpio = GPIO0B_GPIO0B3,
- .fmux = GPIO0B_MMC1_D0,
- },
- },
-
- .data1_gpio = {
- .io = RK2928_PIN0_PB4,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO0B4_MMC1_D1_NAME,
- .fgpio = GPIO0B_GPIO0B4,
- .fmux = GPIO0B_MMC1_D1,
- },
- },
-
- .data2_gpio = {
- .io = RK2928_PIN0_PB5,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO0B5_MMC1_D2_NAME,
- .fgpio = GPIO0B_GPIO0B5,
- .fmux = GPIO0B_MMC1_D2,
- },
- },
-
- .data3_gpio = {
- .io = RK2928_PIN0_PB6,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO0B6_MMC1_D3_NAME,
- .fgpio = GPIO0B_GPIO0B6,
- .fmux = GPIO0B_MMC1_D3,
- },
- },
-
-
-};
-// ---end -#if defined(CONFIG_ARCH_RK2928)
-#endif
-
-
-
-//1.Part 3: The various operations of the SDMMC-SDIO module
-/*************************************************************************
-* define the varaious operations for SDMMC module
-* Generally only the author of SDMMC module will modify this section.
-*************************************************************************/
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
-static void rk29_sdmmc_gpio_open(int device_id, int on)
-{
- switch(device_id)
- {
- case 0://mmc0
- {
- #ifdef CONFIG_SDMMC0_RK29
- if(on)
- {
- gpio_direction_output(rksdmmc0_gpio_init.clk_gpio.io, GPIO_HIGH);//set mmc0-clk to high
- gpio_direction_output(rksdmmc0_gpio_init.cmd_gpio.io, GPIO_HIGH);// set mmc0-cmd to high.
- gpio_direction_output(rksdmmc0_gpio_init.data0_gpio.io,GPIO_HIGH);//set mmc0-data0 to high.
- gpio_direction_output(rksdmmc0_gpio_init.data1_gpio.io,GPIO_HIGH);//set mmc0-data1 to high.
- gpio_direction_output(rksdmmc0_gpio_init.data2_gpio.io,GPIO_HIGH);//set mmc0-data2 to high.
- gpio_direction_output(rksdmmc0_gpio_init.data3_gpio.io,GPIO_HIGH);//set mmc0-data3 to high.
-
- mdelay(30);
- }
- else
- {
- rk30_mux_api_set(rksdmmc0_gpio_init.clk_gpio.iomux.name, rksdmmc0_gpio_init.clk_gpio.iomux.fgpio);
- gpio_request(rksdmmc0_gpio_init.clk_gpio.io, "mmc0-clk");
- gpio_direction_output(rksdmmc0_gpio_init.clk_gpio.io,GPIO_LOW);//set mmc0-clk to low.
-
- rk30_mux_api_set(rksdmmc0_gpio_init.cmd_gpio.iomux.name, rksdmmc0_gpio_init.cmd_gpio.iomux.fgpio);
- gpio_request(rksdmmc0_gpio_init.cmd_gpio.io, "mmc0-cmd");
- gpio_direction_output(rksdmmc0_gpio_init.cmd_gpio.io,GPIO_LOW);//set mmc0-cmd to low.
-
- rk30_mux_api_set(rksdmmc0_gpio_init.data0_gpio.iomux.name, rksdmmc0_gpio_init.data0_gpio.iomux.fgpio);
- gpio_request(rksdmmc0_gpio_init.data0_gpio.io, "mmc0-data0");
- gpio_direction_output(rksdmmc0_gpio_init.data0_gpio.io,GPIO_LOW);//set mmc0-data0 to low.
-
- rk30_mux_api_set(rksdmmc0_gpio_init.data1_gpio.iomux.name, rksdmmc0_gpio_init.data1_gpio.iomux.fgpio);
- gpio_request(rksdmmc0_gpio_init.data1_gpio.io, "mmc0-data1");
- gpio_direction_output(rksdmmc0_gpio_init.data1_gpio.io,GPIO_LOW);//set mmc0-data1 to low.
-
- rk30_mux_api_set(rksdmmc0_gpio_init.data2_gpio.iomux.name, rksdmmc0_gpio_init.data2_gpio.iomux.fgpio);
- gpio_request(rksdmmc0_gpio_init.data2_gpio.io, "mmc0-data2");
- gpio_direction_output(rksdmmc0_gpio_init.data2_gpio.io,GPIO_LOW);//set mmc0-data2 to low.
-
- rk30_mux_api_set(rksdmmc0_gpio_init.data3_gpio.iomux.name, rksdmmc0_gpio_init.data3_gpio.iomux.fgpio);
- gpio_request(rksdmmc0_gpio_init.data3_gpio.io, "mmc0-data3");
- gpio_direction_output(rksdmmc0_gpio_init.data3_gpio.io,GPIO_LOW);//set mmc0-data3 to low.
-
- mdelay(30);
- }
- #endif
- }
- break;
-
- case 1://mmc1
- {
- #ifdef CONFIG_SDMMC1_RK29
- if(on)
- {
- gpio_direction_output(rksdmmc1_gpio_init.clk_gpio.io,GPIO_HIGH);//set mmc1-clk to high
- gpio_direction_output(rksdmmc1_gpio_init.cmd_gpio.io,GPIO_HIGH);//set mmc1-cmd to high.
- gpio_direction_output(rksdmmc1_gpio_init.data0_gpio.io,GPIO_HIGH);//set mmc1-data0 to high.
- gpio_direction_output(rksdmmc1_gpio_init.data1_gpio.io,GPIO_HIGH);//set mmc1-data1 to high.
- gpio_direction_output(rksdmmc1_gpio_init.data2_gpio.io,GPIO_HIGH);//set mmc1-data2 to high.
- gpio_direction_output(rksdmmc1_gpio_init.data3_gpio.io,GPIO_HIGH);//set mmc1-data3 to high.
- mdelay(100);
- }
- else
- {
- rk30_mux_api_set(rksdmmc1_gpio_init.clk_gpio.iomux.name, rksdmmc1_gpio_init.clk_gpio.iomux.fgpio);
- gpio_request(rksdmmc1_gpio_init.clk_gpio.io, "mmc1-clk");
- gpio_direction_output(rksdmmc1_gpio_init.clk_gpio.io,GPIO_LOW);//set mmc1-clk to low.
-
- rk30_mux_api_set(rksdmmc1_gpio_init.cmd_gpio.iomux.name, rksdmmc1_gpio_init.cmd_gpio.iomux.fgpio);
- gpio_request(rksdmmc1_gpio_init.cmd_gpio.io, "mmc1-cmd");
- gpio_direction_output(rksdmmc1_gpio_init.cmd_gpio.io,GPIO_LOW);//set mmc1-cmd to low.
-
- rk30_mux_api_set(rksdmmc1_gpio_init.data0_gpio.iomux.name, rksdmmc1_gpio_init.data0_gpio.iomux.fgpio);
- gpio_request(rksdmmc1_gpio_init.data0_gpio.io, "mmc1-data0");
- gpio_direction_output(rksdmmc1_gpio_init.data0_gpio.io,GPIO_LOW);//set mmc1-data0 to low.
-
- rk29_mux_api_set(rksdmmc1_gpio_init.data1_gpio.iomux.name, rksdmmc1_gpio_init.data1_gpio.iomux.fgpio);
- gpio_request(rksdmmc1_gpio_init.data1_gpio.io, "mmc1-data1");
- gpio_direction_output(rksdmmc1_gpio_init.data1_gpio.io,GPIO_LOW);//set mmc1-data1 to low.
-
- rk29_mux_api_set(rksdmmc1_gpio_init.data2_gpio.iomux.name, rksdmmc1_gpio_init.data2_gpio.iomux.fgpio);
- gpio_request(rksdmmc1_gpio_init.data2_gpio.io, "mmc1-data2");
- gpio_direction_output(rksdmmc1_gpio_init.data2_gpio.io,GPIO_LOW);//set mmc1-data2 to low.
-
- rk29_mux_api_set(rksdmmc1_gpio_init.data3_gpio.iomux.name, rksdmmc1_gpio_init.data3_gpio.iomux.fgpio);
- gpio_request(rksdmmc1_gpio_init.data3_gpio.io, "mmc1-data3");
- gpio_direction_output(rksdmmc1_gpio_init.data3_gpio.io,GPIO_LOW);//set mmc1-data3 to low.
-
- mdelay(100);
- }
- #endif
- }
- break;
-
- case 2: //mmc2
- break;
-
- default:
- break;
- }
-}
-
-static void rk29_sdmmc_set_iomux_mmc0(unsigned int bus_width)
-{
- switch (bus_width)
- {
-
- case 1://SDMMC_CTYPE_4BIT:
- {
- rk30_mux_api_set(rksdmmc0_gpio_init.data1_gpio.iomux.name, rksdmmc0_gpio_init.data1_gpio.iomux.fmux);
- rk30_mux_api_set(rksdmmc0_gpio_init.data2_gpio.iomux.name, rksdmmc0_gpio_init.data2_gpio.iomux.fmux);
- rk30_mux_api_set(rksdmmc0_gpio_init.data3_gpio.iomux.name, rksdmmc0_gpio_init.data3_gpio.iomux.fmux);
- }
- break;
-
- case 0x10000://SDMMC_CTYPE_8BIT:
- break;
- case 0xFFFF: //gpio_reset
- {
- if (rksdmmc0_gpio_init.power_en_gpio.io == INVALID_GPIO)
- break;
- rk30_mux_api_set(rksdmmc0_gpio_init.power_en_gpio.iomux.name, rksdmmc0_gpio_init.power_en_gpio.iomux.fgpio);
- gpio_request(rksdmmc0_gpio_init.power_en_gpio.io,"sdmmc-power");
- gpio_direction_output(rksdmmc0_gpio_init.power_en_gpio.io, !(rksdmmc0_gpio_init.power_en_gpio.enable)); //power-off
-
- #if 0 //replace the power control into rk29_sdmmc_set_ios(); modifyed by xbw at 2012-08-12
- rk29_sdmmc_gpio_open(0, 0);
-
- gpio_direction_output(rksdmmc0_gpio_init.power_en_gpio.io, rksdmmc0_gpio_init.power_en_gpio.enable); //power-on
-
- rk29_sdmmc_gpio_open(0, 1);
- #endif
- }
- break;
-
- default: //case 0://SDMMC_CTYPE_1BIT:
- {
- rk30_mux_api_set(rksdmmc0_gpio_init.cmd_gpio.iomux.name, rksdmmc0_gpio_init.cmd_gpio.iomux.fmux);
- rk30_mux_api_set(rksdmmc0_gpio_init.clk_gpio.iomux.name, rksdmmc0_gpio_init.clk_gpio.iomux.fmux);
- rk30_mux_api_set(rksdmmc0_gpio_init.data0_gpio.iomux.name, rksdmmc0_gpio_init.data0_gpio.iomux.fmux);
-
- rk30_mux_api_set(rksdmmc0_gpio_init.data1_gpio.iomux.name, rksdmmc0_gpio_init.data1_gpio.iomux.fgpio);
- gpio_request(rksdmmc0_gpio_init.data1_gpio.io, "mmc0-data1");
- gpio_direction_output(rksdmmc0_gpio_init.data1_gpio.io,GPIO_HIGH);//set mmc0-data1 to high.
-
- rk30_mux_api_set(rksdmmc0_gpio_init.data2_gpio.iomux.name, rksdmmc0_gpio_init.data2_gpio.iomux.fgpio);
- gpio_request(rksdmmc0_gpio_init.data2_gpio.io, "mmc0-data2");
- gpio_direction_output(rksdmmc0_gpio_init.data2_gpio.io,GPIO_HIGH);//set mmc0-data2 to high.
-
- rk30_mux_api_set(rksdmmc0_gpio_init.data3_gpio.iomux.name, rksdmmc0_gpio_init.data3_gpio.iomux.fgpio);
- gpio_request(rksdmmc0_gpio_init.data3_gpio.io, "mmc0-data3");
- gpio_direction_output(rksdmmc0_gpio_init.data3_gpio.io,GPIO_HIGH);//set mmc0-data3 to high.
- }
- break;
- }
-}
-
-static void rk29_sdmmc_set_iomux_mmc1(unsigned int bus_width)
-{
- rk30_mux_api_set(rksdmmc1_gpio_init.cmd_gpio.iomux.name, rksdmmc1_gpio_init.cmd_gpio.iomux.fmux);
- rk30_mux_api_set(rksdmmc1_gpio_init.clk_gpio.iomux.name, rksdmmc1_gpio_init.clk_gpio.iomux.fmux);
- rk30_mux_api_set(rksdmmc1_gpio_init.data0_gpio.iomux.name, rksdmmc1_gpio_init.data0_gpio.iomux.fmux);
- rk30_mux_api_set(rksdmmc1_gpio_init.data1_gpio.iomux.name, rksdmmc1_gpio_init.data1_gpio.iomux.fmux);
- rk30_mux_api_set(rksdmmc1_gpio_init.data2_gpio.iomux.name, rksdmmc1_gpio_init.data2_gpio.iomux.fmux);
- rk30_mux_api_set(rksdmmc1_gpio_init.data3_gpio.iomux.name, rksdmmc1_gpio_init.data3_gpio.iomux.fmux);
-}
-
-static void rk29_sdmmc_set_iomux_mmc2(unsigned int bus_width)
-{
- ;//
-}
-
-static void rk29_sdmmc_set_iomux(int device_id, unsigned int bus_width)
-{
- switch(device_id)
- {
- case 0:
- #ifdef CONFIG_SDMMC0_RK29
- rk29_sdmmc_set_iomux_mmc0(bus_width);
- #endif
- break;
- case 1:
- #ifdef CONFIG_SDMMC1_RK29
- rk29_sdmmc_set_iomux_mmc1(bus_width);
- #endif
- break;
- case 2:
- rk29_sdmmc_set_iomux_mmc2(bus_width);
- break;
- default:
- break;
- }
-}
-
-#endif
-
-
-
-//1.Part 4: The various operations of the Wifi-BT module
-/*************************************************************************
-* define the varaious operations for Wifi module
-* Generally only the author of Wifi module will modify this section.
-*************************************************************************/
-
-static int rk29sdk_wifi_status(struct device *dev);
-static int rk29sdk_wifi_status_register(void (*callback)(int card_presend, void *dev_id), void *dev_id);
-
-#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
-static int rk29sdk_wifi_mmc0_status(struct device *dev);
-static int rk29sdk_wifi_mmc0_status_register(void (*callback)(int card_presend, void *dev_id), void *dev_id);
-static int rk29sdk_wifi_mmc0_cd = 0; /* wifi virtual 'card detect' status */
-static void (*wifi_mmc0_status_cb)(int card_present, void *dev_id);
-static void *wifi_mmc0_status_cb_devid;
-
-int rk29sdk_wifi_power_state = 0;
-int rk29sdk_bt_power_state = 0;
-
- #if defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- /////////////////////////////////////////////////////////////////////////////////////
- // set the gpio to develop wifi EVB if you select the macro of CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD
- #define USE_SDMMC_CONTROLLER_FOR_WIFI 0
- #define COMBO_MODULE_MT6620_CDT 0 //- 1--use Cdtech chip; 0--unuse CDT chip
- //power
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_POWER_PIN_NAME GPIO3D0_SDMMC1PWREN_NAME
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO3D_GPIO3D0
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FMUX GPIO3D_SDMMC1_PWR_EN
- //reset
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_RESET_PIN_NAME GPIO3D1_SDMMC1BACKENDPWR_NAME
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FGPIO GPIO3D_GPIO3D1
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FMUX GPIO3D_SDMMC1_BACKEND_PWR
- //VDDIO
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL RK30_PIN2_PC5
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_ENABLE_VALUE GPIO_HIGH
- //WIFI_INT_B
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_PIN_NAME GPIO3D2_SDMMC1INTN_NAME
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FGPIO GPIO3D_GPIO3D2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FMUX GPIO3D_SDMMC1_INT_N
- //BGF_INT_B
- #define RK30SDK_WIFI_GPIO_BGF_INT_B RK30_PIN3_PC6
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_PIN_NAME GPIO3C6_SDMMC1DETECTN_NAME
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FGPIO GPIO3C_GPIO3C6
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FMUX GPIO3C_SDMMC1_DETECT_N
- //GPS_SYNC
- #define RK30SDK_WIFI_GPIO_GPS_SYNC RK30_PIN3_PC7
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_PIN_NAME GPIO3C7_SDMMC1WRITEPRT_NAME
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FGPIO GPIO3C_GPIO3C7
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FMUX GPIO3C_SDMMC1_WRITE_PRT
-
- #if COMBO_MODULE_MT6620_CDT
- //ANTSEL2
- #define RK30SDK_WIFI_GPIO_ANTSEL2 RK30_PIN4_PD4
- #define RK30SDK_WIFI_GPIO_ANTSEL2_ENABLE_VALUE GPIO_LOW //use 6620 in CDT chip, LOW--work; High--no work.
- #define RK30SDK_WIFI_GPIO_ANTSEL2_PIN_NAME GPIO4D4_SMCDATA12_TRACEDATA12_NAME
- #define RK30SDK_WIFI_GPIO_ANTSEL2_IOMUX_FGPIO GPIO4D_GPIO4D4
- #define RK30SDK_WIFI_GPIO_ANTSEL2_IOMUX_FMUX GPIO4D_TRACE_DATA12
- //ANTSEL3
- #define RK30SDK_WIFI_GPIO_ANTSEL3 RK30_PIN4_PD3
- #define RK30SDK_WIFI_GPIO_ANTSEL3_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- #define RK30SDK_WIFI_GPIO_ANTSEL3_PIN_NAME GPIO4D3_SMCDATA11_TRACEDATA11_NAME
- #define RK30SDK_WIFI_GPIO_ANTSEL3_IOMUX_FGPIO GPIO4D_GPIO4D3
- #define RK30SDK_WIFI_GPIO_ANTSEL3_IOMUX_FMUX GPIO4D_TRACE_DATA11
- //GPS_LAN
- #define RK30SDK_WIFI_GPIO_GPS_LAN RK30_PIN4_PD6
- #define RK30SDK_WIFI_GPIO_GPS_LAN_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- #define RK30SDK_WIFI_GPIO_GPS_LAN_PIN_NAME GPIO4D6_SMCDATA14_TRACEDATA14_NAME
- #define RK30SDK_WIFI_GPIO_GPS_LAN_IOMUX_FGPIO GPIO4D_GPIO4D6
- #define RK30SDK_WIFI_GPIO_GPS_LAN_IOMUX_FMUX GPIO4D_TRACE_DATA14
- #endif // #if COMBO_MODULE_MT6620_CDT--#endif
-
- #endif // #if defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)---#endif
-#endif // #if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) ---#endif
-
-static int rk29sdk_wifi_cd = 0; /* wifi virtual 'card detect' status */
-static void (*wifi_status_cb)(int card_present, void *dev_id);
-static void *wifi_status_cb_devid;
-
-#if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
-#define RK29SDK_WIFI_SDIO_CARD_INT RK30SDK_WIFI_GPIO_WIFI_INT_B
-#endif
-
-struct rksdmmc_gpio_wifi_moudle rk_platform_wifi_gpio = {
- .power_n = {
- .io = RK30SDK_WIFI_GPIO_POWER_N,
- .enable = RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE,
- #ifdef RK30SDK_WIFI_GPIO_POWER_PIN_NAME
- .iomux = {
- .name = RK30SDK_WIFI_GPIO_POWER_PIN_NAME,
- .fgpio = RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO,
- #ifdef RK30SDK_WIFI_GPIO_POWER_IOMUX_FMUX
- .fmux = RK30SDK_WIFI_GPIO_POWER_IOMUX_FMUX,
- #endif
- },
- #endif
- },
-
- #ifdef RK30SDK_WIFI_GPIO_RESET_N
- .reset_n = {
- .io = RK30SDK_WIFI_GPIO_RESET_N,
- .enable = RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE,
- #ifdef RK30SDK_WIFI_GPIO_RESET_PIN_NAME
- .iomux = {
- .name = RK30SDK_WIFI_GPIO_RESET_PIN_NAME,
- .fgpio = RK30SDK_WIFI_GPIO_RESET_IOMUX_FGPIO,
- #ifdef RK30SDK_WIFI_GPIO_RESET_IOMUX_FMUX
- .fmux = RK30SDK_WIFI_GPIO_RESET_IOMUX_FMUX,
- #endif
- },
- #endif
- },
- #endif
-
- #ifdef RK30SDK_WIFI_GPIO_WIFI_INT_B
- .wifi_int_b = {
- .io = RK30SDK_WIFI_GPIO_WIFI_INT_B,
- .enable = RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE,
- #ifdef RK30SDK_WIFI_GPIO_WIFI_INT_B_PIN_NAME
- .iomux = {
- .name = RK30SDK_WIFI_GPIO_WIFI_INT_B_PIN_NAME,
- .fgpio = RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FGPIO,
- #ifdef RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FMUX
- .fmux = RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FMUX,
- #endif
- },
- #endif
- },
- #endif
-
- #ifdef RK30SDK_WIFI_GPIO_VCCIO_WL
- .vddio = {
- .io = RK30SDK_WIFI_GPIO_VCCIO_WL,
- .enable = RK30SDK_WIFI_GPIO_VCCIO_WL_ENABLE_VALUE,
- #ifdef RK30SDK_WIFI_GPIO_VCCIO_WL_PIN_NAME
- .iomux = {
- .name = RK30SDK_WIFI_GPIO_VCCIO_WL_PIN_NAME,
- .fgpio = RK30SDK_WIFI_GPIO_VCCIO_WL_IOMUX_FGPIO,
- #ifdef RK30SDK_WIFI_GPIO_VCCIO_WL_IOMUX_FMUX
- .fmux = RK30SDK_WIFI_GPIO_VCCIO_WL_IOMUX_FMUX,
- #endif
- },
- #endif
- },
- #endif
-
- #ifdef RK30SDK_WIFI_GPIO_BGF_INT_B
- .bgf_int_b = {
- .io = RK30SDK_WIFI_GPIO_BGF_INT_B,
- .enable = RK30SDK_WIFI_GPIO_BGF_INT_B_ENABLE_VALUE,
- #ifdef RK30SDK_WIFI_GPIO_BGF_INT_B_PIN_NAME
- .iomux = {
- .name = RK30SDK_WIFI_GPIO_BGF_INT_B_PIN_NAME,
- .fgpio = RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FGPIO,
- #ifdef RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FMUX
- .fmux = RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FMUX,
- #endif
- },
- #endif
- },
- #endif
-
- #ifdef RK30SDK_WIFI_GPIO_GPS_SYNC
- .gps_sync = {
- .io = RK30SDK_WIFI_GPIO_GPS_SYNC,
- .enable = RK30SDK_WIFI_GPIO_GPS_SYNC_ENABLE_VALUE,
- #ifdef RK30SDK_WIFI_GPIO_GPS_SYNC_PIN_NAME
- .iomux = {
- .name = RK30SDK_WIFI_GPIO_GPS_SYNC_PIN_NAME,
- .fgpio = RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FGPIO,
- #ifdef RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FMUX
- .fmux = RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FMUX,
- #endif
- },
- #endif
- },
- #endif
-
-#if COMBO_MODULE_MT6620_CDT
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL2
- .ANTSEL2 = {
- .io = RK30SDK_WIFI_GPIO_ANTSEL2,
- .enable = RK30SDK_WIFI_GPIO_ANTSEL2_ENABLE_VALUE,
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL2_PIN_NAME
- .iomux = {
- .name = RK30SDK_WIFI_GPIO_ANTSEL2_PIN_NAME,
- .fgpio = RK30SDK_WIFI_GPIO_ANTSEL2_IOMUX_FGPIO,
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL2_IOMUX_FMUX
- .fmux = RK30SDK_WIFI_GPIO_ANTSEL2_IOMUX_FMUX,
- #endif
- },
- #endif
- },
- #endif
-
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL3
- .ANTSEL3 = {
- .io = RK30SDK_WIFI_GPIO_ANTSEL3,
- .enable = RK30SDK_WIFI_GPIO_ANTSEL3_ENABLE_VALUE,
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL3_PIN_NAME
- .iomux = {
- .name = RK30SDK_WIFI_GPIO_ANTSEL3_PIN_NAME,
- .fgpio = RK30SDK_WIFI_GPIO_ANTSEL3_IOMUX_FGPIO,
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL3_IOMUX_FMUX
- .fmux = RK30SDK_WIFI_GPIO_ANTSEL3_IOMUX_FMUX,
- #endif
- },
- #endif
- },
- #endif
-
- #ifdef RK30SDK_WIFI_GPIO_GPS_LAN
- .GPS_LAN = {
- .io = RK30SDK_WIFI_GPIO_GPS_LAN,
- .enable = RK30SDK_WIFI_GPIO_GPS_LAN_ENABLE_VALUE,
- #ifdef RK30SDK_WIFI_GPIO_GPS_LAN_PIN_NAME
- .iomux = {
- .name = RK30SDK_WIFI_GPIO_GPS_LAN_PIN_NAME,
- .fgpio = RK30SDK_WIFI_GPIO_GPS_LAN_IOMUX_FGPIO,
- #ifdef RK30SDK_WIFI_GPIO_GPS_LAN_IOMUX_FMUX
- .fmux = RK30SDK_WIFI_GPIO_GPS_LAN_IOMUX_FMUX,
- #endif
- },
- #endif
- },
- #endif
-#endif // #if COMBO_MODULE_MT6620_CDT--#endif
-};
-
-
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
-#define PREALLOC_WLAN_SEC_NUM 4
-#define PREALLOC_WLAN_BUF_NUM 160
-#define PREALLOC_WLAN_SECTION_HEADER 24
-
-#define WLAN_SECTION_SIZE_0 (PREALLOC_WLAN_BUF_NUM * 128)
-#define WLAN_SECTION_SIZE_1 (PREALLOC_WLAN_BUF_NUM * 128)
-#define WLAN_SECTION_SIZE_2 (PREALLOC_WLAN_BUF_NUM * 512)
-#define WLAN_SECTION_SIZE_3 (PREALLOC_WLAN_BUF_NUM * 1024)
-
-#define WLAN_SKB_BUF_NUM 16
-
-static struct sk_buff *wlan_static_skb[WLAN_SKB_BUF_NUM];
-
-struct wifi_mem_prealloc {
- void *mem_ptr;
- unsigned long size;
-};
-
-static struct wifi_mem_prealloc wifi_mem_array[PREALLOC_WLAN_SEC_NUM] = {
- {NULL, (WLAN_SECTION_SIZE_0 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_1 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_2 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_3 + PREALLOC_WLAN_SECTION_HEADER)}
-};
-
-static void *rk29sdk_mem_prealloc(int section, unsigned long size)
-{
- if (section == PREALLOC_WLAN_SEC_NUM)
- return wlan_static_skb;
-
- if ((section < 0) || (section > PREALLOC_WLAN_SEC_NUM))
- return NULL;
-
- if (wifi_mem_array[section].size < size)
- return NULL;
-
- return wifi_mem_array[section].mem_ptr;
-}
-
-static int __init rk29sdk_init_wifi_mem(void)
-{
- int i;
- int j;
-
- for (i = 0 ; i < WLAN_SKB_BUF_NUM ; i++) {
- wlan_static_skb[i] = dev_alloc_skb(
- ((i < (WLAN_SKB_BUF_NUM / 2)) ? 4096 : 8192));
-
- if (!wlan_static_skb[i])
- goto err_skb_alloc;
- }
-
- for (i = 0 ; i < PREALLOC_WLAN_SEC_NUM ; i++) {
- wifi_mem_array[i].mem_ptr =
- kmalloc(wifi_mem_array[i].size, GFP_KERNEL);
-
- if (!wifi_mem_array[i].mem_ptr)
- goto err_mem_alloc;
- }
- return 0;
-
-err_mem_alloc:
- pr_err("Failed to mem_alloc for WLAN\n");
- for (j = 0 ; j < i ; j++)
- kfree(wifi_mem_array[j].mem_ptr);
-
- i = WLAN_SKB_BUF_NUM;
-
-err_skb_alloc:
- pr_err("Failed to skb_alloc for WLAN\n");
- for (j = 0 ; j < i ; j++)
- dev_kfree_skb(wlan_static_skb[j]);
-
- return -ENOMEM;
-}
-
-static int rk29sdk_wifi_status(struct device *dev)
-{
- return rk29sdk_wifi_cd;
-}
-
-static int rk29sdk_wifi_status_register(void (*callback)(int card_present, void *dev_id), void *dev_id)
-{
- if(wifi_status_cb)
- return -EAGAIN;
- wifi_status_cb = callback;
- wifi_status_cb_devid = dev_id;
- return 0;
-}
-
-#if defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU) || defined(CONFIG_RT5370)
-static int __init rk29sdk_wifi_bt_gpio_control_init(void)
-{
-#if defined(CONFIG_USB_WIFI_POWER_CONTROLED_BY_GPIO)
- if (gpio_request(rk_platform_wifi_gpio.power_n.io, "wifi_power")) {
- pr_info("%s: request wifi power gpio failed\n", __func__);
- return -1;
- }
- gpio_direction_output(rk_platform_wifi_gpio.power_n.io, !(rk_platform_wifi_gpio.power_n.enable) );
-#endif
- pr_info("%s: init finished\n",__func__);
- return 0;
-}
-#elif defined(CONFIG_RDA5990)
-static int __init rk29sdk_wifi_bt_gpio_control_init(void)
-{
- #if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
- rk29_sdmmc_gpio_open(1, 0); //added by xbw at 2011-10-13
- #endif
- pr_info("%s: init finished\n",__func__);
-
- return 0;
-}
-#else
-static int __init rk29sdk_wifi_bt_gpio_control_init(void)
-{
- rk29sdk_init_wifi_mem();
- rk29_mux_api_set(rk_platform_wifi_gpio.power_n.iomux.name, rk_platform_wifi_gpio.power_n.iomux.fgpio);
-
- if (gpio_request(rk_platform_wifi_gpio.power_n.io, "wifi_power")) {
- pr_info("%s: request wifi power gpio failed\n", __func__);
- return -1;
- }
-
-#ifdef RK30SDK_WIFI_GPIO_RESET_N
- if (gpio_request(rk_platform_wifi_gpio.reset_n.io, "wifi reset")) {
- pr_info("%s: request wifi reset gpio failed\n", __func__);
- gpio_free(rk_platform_wifi_gpio.reset_n.io);
- return -1;
- }
-#endif
-
- gpio_direction_output(rk_platform_wifi_gpio.power_n.io, !(rk_platform_wifi_gpio.power_n.enable) );
-
-#ifdef RK30SDK_WIFI_GPIO_RESET_N
- gpio_direction_output(rk_platform_wifi_gpio.reset_n.io, !(rk_platform_wifi_gpio.reset_n.enable) );
-#endif
-
- #if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
- rk29_sdmmc_gpio_open(1, 0); //added by xbw at 2011-10-13
- #endif
- pr_info("%s: init finished\n",__func__);
-
- return 0;
-}
-#endif
-
-#if defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU) || defined(CONFIG_RT5370)
-static int usbwifi_power_status = 1;
-int rk29sdk_wifi_power(int on)
-{
- pr_info("%s: %d\n", __func__, on);
- if (on){
- #if defined(CONFIG_USB_WIFI_POWER_CONTROLED_BY_GPIO)
- gpio_set_value(rk_platform_wifi_gpio.power_n.io, rk_platform_wifi_gpio.power_n.enable);
- mdelay(100);
- #else
- if(usbwifi_power_status == 1) {
- rkusb_wifi_power(0);
- mdelay(50);
- }
- rkusb_wifi_power(1);
- #endif
- usbwifi_power_status = 1;
- pr_info("wifi turn on power\n");
- }else{
- #if defined(CONFIG_USB_WIFI_POWER_CONTROLED_BY_GPIO)
- gpio_set_value(rk_platform_wifi_gpio.power_n.io, !(rk_platform_wifi_gpio.power_n.enable));
- mdelay(100);
- #else
- rkusb_wifi_power(0);
- #endif
- usbwifi_power_status = 0;
- pr_info("wifi shut off power\n");
- }
- return 0;
-}
-#elif defined(CONFIG_RDA5990)
-int rk29sdk_wifi_power(int on)
-{
- pr_info("%s: %d\n", __func__, on);
- if (on){
- mdelay(50);
-
- #if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
- rk29_sdmmc_gpio_open(1, 1); //added by xbw at 2011-10-13
- #endif
-
- mdelay(100);
- pr_info("wifi turn on power\n");
- }else{
- #if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
- rk29_sdmmc_gpio_open(1, 0); //added by xbw at 2011-10-13
- #endif
-
- mdelay(100);
- pr_info("wifi shut off power\n");
- }
-
- return 0;
-}
-
-#else
-int rk29sdk_wifi_power(int on)
-{
- pr_info("%s: %d\n", __func__, on);
- if (on){
- gpio_set_value(rk_platform_wifi_gpio.power_n.io, rk_platform_wifi_gpio.power_n.enable);
- mdelay(50);
-
- #if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
- rk29_sdmmc_gpio_open(1, 1); //added by xbw at 2011-10-13
- #endif
-
- #ifdef RK30SDK_WIFI_GPIO_RESET_N
- gpio_set_value(rk_platform_wifi_gpio.reset_n.io, rk_platform_wifi_gpio.reset_n.enable);
- #endif
- mdelay(100);
- pr_info("wifi turn on power\n");
- }else{
-// if (!rk29sdk_bt_power_state){
- gpio_set_value(rk_platform_wifi_gpio.power_n.io, !(rk_platform_wifi_gpio.power_n.enable));
- #if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
- rk29_sdmmc_gpio_open(1, 0); //added by xbw at 2011-10-13
- #endif
-
- mdelay(100);
- pr_info("wifi shut off power\n");
-// }else
-// {
-// pr_info("wifi shouldn't shut off power, bt is using it!\n");
-// }
-#ifdef RK30SDK_WIFI_GPIO_RESET_N
- gpio_set_value(rk_platform_wifi_gpio.reset_n.io, !(rk_platform_wifi_gpio.reset_n.enable));
-#endif
- }
-
-// rk29sdk_wifi_power_state = on;
- return 0;
-}
-#endif
-EXPORT_SYMBOL(rk29sdk_wifi_power);
-
-static int rk29sdk_wifi_reset_state;
-static int rk29sdk_wifi_reset(int on)
-{
- pr_info("%s: %d\n", __func__, on);
- //mdelay(100);
- rk29sdk_wifi_reset_state = on;
- return 0;
-}
-
-int rk29sdk_wifi_set_carddetect(int val)
-{
- pr_info("%s:%d\n", __func__, val);
- rk29sdk_wifi_cd = val;
- if (wifi_status_cb){
- wifi_status_cb(val, wifi_status_cb_devid);
- }else {
- pr_warning("%s, nobody to notify\n", __func__);
- }
- return 0;
-}
-EXPORT_SYMBOL(rk29sdk_wifi_set_carddetect);
-
-
-static struct resource resources[] = {
- {
- .start = WIFI_HOST_WAKE,
- .flags = IORESOURCE_IRQ,
- .name = "bcmdhd_wlan_irq",
- },
-};
- //#if defined(CONFIG_WIFI_CONTROL_FUNC)----#elif
-
-///////////////////////////////////////////////////////////////////////////////////
-#elif defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
-
-#define debug_combo_system 0
-
-int rk29sdk_wifi_combo_get_BGFgpio(void)
-{
- return rk_platform_wifi_gpio.bgf_int_b.io;
-}
-EXPORT_SYMBOL(rk29sdk_wifi_combo_get_BGFgpio);
-
-
-int rk29sdk_wifi_combo_get_GPS_SYNC_gpio(void)
-{
- return rk_platform_wifi_gpio.gps_sync.io;
-}
-EXPORT_SYMBOL(rk29sdk_wifi_combo_get_GPS_SYNC_gpio);
-
-
-static int rk29sdk_wifi_combo_module_gpio_init(void)
-{
- //VDDIO
- #ifdef RK30SDK_WIFI_GPIO_VCCIO_WL
- #ifdef RK30SDK_WIFI_GPIO_VCCIO_WL_PIN_NAME
- rk30_mux_api_set(rk_platform_wifi_gpio.vddio.iomux.name, rk_platform_wifi_gpio.vddio.iomux.fgpio);
- #endif
- gpio_request(rk_platform_wifi_gpio.vddio.io, "combo-VDDIO");
- gpio_direction_output(rk_platform_wifi_gpio.vddio.io, !(rk_platform_wifi_gpio.power_n.enable));
- #endif
-
- //BGF_INT_B
- #ifdef RK30SDK_WIFI_GPIO_BGF_INT_B_PIN_NAME
- rk30_mux_api_set(rk_platform_wifi_gpio.bgf_int_b.iomux.name, rk_platform_wifi_gpio.bgf_int_b.iomux.fgpio);
- #endif
- gpio_request(rk_platform_wifi_gpio.bgf_int_b.io, "combo-BGFINT");
- gpio_pull_updown(rk_platform_wifi_gpio.bgf_int_b.io, GPIOPullUp);
- gpio_direction_input(rk_platform_wifi_gpio.bgf_int_b.io);
-
- //WIFI_INT_B
- #ifdef RK30SDK_WIFI_GPIO_WIFI_INT_B_PIN_NAME
- rk30_mux_api_set(rk_platform_wifi_gpio.bgf_int_b.iomux.name, rk_platform_wifi_gpio.bgf_int_b.iomux.fgpio);
- #endif
- gpio_request(rk_platform_wifi_gpio.wifi_int_b.io, "combo-WIFIINT");
- gpio_pull_updown(rk_platform_wifi_gpio.wifi_int_b.io, GPIOPullUp);
- gpio_direction_input(rk_platform_wifi_gpio.wifi_int_b.io);
-
- //reset
- #ifdef RK30SDK_WIFI_GPIO_RESET_PIN_NAME
- rk30_mux_api_set(rk_platform_wifi_gpio.reset_n.iomux.name, rk_platform_wifi_gpio.reset_n.iomux.fgpio);
- #endif
- gpio_request(rk_platform_wifi_gpio.reset_n.io, "combo-RST");
- gpio_direction_output(rk_platform_wifi_gpio.reset_n.io, !(rk_platform_wifi_gpio.reset_n.enable));
-
- //power
- #ifdef RK30SDK_WIFI_GPIO_POWER_PIN_NAME
- rk30_mux_api_set(rk_platform_wifi_gpio.power_n.iomux.name, rk_platform_wifi_gpio.power_n.iomux.fgpio);
- #endif
- gpio_request(rk_platform_wifi_gpio.power_n.io, "combo-PMUEN");
- gpio_direction_output(rk_platform_wifi_gpio.power_n.io, !(rk_platform_wifi_gpio.power_n.enable));
-
- #if COMBO_MODULE_MT6620_CDT
- //ANTSEL2
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL2
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL2_PIN_NAME
- rk30_mux_api_set(rk_platform_wifi_gpio.ANTSEL2.iomux.name, rk_platform_wifi_gpio.ANTSEL2.iomux.fgpio);
- #endif
- gpio_request(rk_platform_wifi_gpio.ANTSEL2.io, "combo-ANTSEL2");
- gpio_direction_output(rk_platform_wifi_gpio.reset_n.io, rk_platform_wifi_gpio.ANTSEL2.enable);
- #endif
-
- //ANTSEL3
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL3
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL3_PIN_NAME
- rk30_mux_api_set(rk_platform_wifi_gpio.ANTSEL3.iomux.name, rk_platform_wifi_gpio.ANTSEL3.iomux.fgpio);
- #endif
- gpio_request(rk_platform_wifi_gpio.ANTSEL3.io, "combo-ANTSEL3");
- gpio_direction_output(rk_platform_wifi_gpio.ANTSEL3.io, rk_platform_wifi_gpio.ANTSEL3.enable);
- #endif
-
- //GPS_LAN
- #ifdef RK30SDK_WIFI_GPIO_GPS_LAN
- #ifdef RK30SDK_WIFI_GPIO_GPS_LAN_PIN_NAME
- rk30_mux_api_set(rk_platform_wifi_gpio.GPS_LAN.iomux.name, rk_platform_wifi_gpio.GPS_LAN.iomux.fgpio);
- #endif
- gpio_request(rk_platform_wifi_gpio.GPS_LAN.io, "combo-GPSLAN");
- gpio_direction_output(rk_platform_wifi_gpio.GPS_LAN.io, rk_platform_wifi_gpio.GPS_LAN.enable);
- #endif
-
- #endif//#if COMBO_MODULE_MT6620_CDT ---#endif
-
- return 0;
-}
-
-
-int rk29sdk_wifi_combo_module_power(int on)
-{
- if(on)
- {
- #ifdef RK30SDK_WIFI_GPIO_VCCIO_WL
- gpio_set_value(rk_platform_wifi_gpio.vddio.io, rk_platform_wifi_gpio.vddio.enable);
- mdelay(10);
- #endif
-
- gpio_set_value(rk_platform_wifi_gpio.power_n.io, rk_platform_wifi_gpio.power_n.enable);
- mdelay(10);
- pr_info("combo-module turn on power\n");
- }
- else
- {
- gpio_set_value(rk_platform_wifi_gpio.power_n.io, !(rk_platform_wifi_gpio.power_n.enable) );
- mdelay(10);
-
- #ifdef RK30SDK_WIFI_GPIO_VCCIO_WL
- gpio_set_value(rk_platform_wifi_gpio.vddio.io, !(rk_platform_wifi_gpio.vddio.enable));
- #endif
-
- pr_info("combo-module turn off power\n");
- }
- return 0;
-
-}
-EXPORT_SYMBOL(rk29sdk_wifi_combo_module_power);
-
-
-int rk29sdk_wifi_combo_module_reset(int on)
-{
- if(on)
- {
- gpio_set_value(rk_platform_wifi_gpio.reset_n.io, rk_platform_wifi_gpio.reset_n.enable);
- pr_info("combo-module reset out 1\n");
- }
- else
- {
- gpio_set_value(rk_platform_wifi_gpio.reset_n.io, !(rk_platform_wifi_gpio.reset_n.enable) );
- pr_info("combo-module reset out 0\n");
- }
-
- return 0;
-}
-EXPORT_SYMBOL(rk29sdk_wifi_combo_module_reset);
-
-
-static int rk29sdk_wifi_mmc0_status(struct device *dev)
-{
- return rk29sdk_wifi_mmc0_cd;
-}
-
-static int rk29sdk_wifi_mmc0_status_register(void (*callback)(int card_present, void *dev_id), void *dev_id)
-{
- if(wifi_mmc0_status_cb)
- return -EAGAIN;
- wifi_mmc0_status_cb = callback;
- wifi_mmc0_status_cb_devid = dev_id;
- return 0;
-}
-
-
-static int rk29sdk_wifi_status(struct device *dev)
-{
- return rk29sdk_wifi_cd;
-}
-
-static int rk29sdk_wifi_status_register(void (*callback)(int card_present, void *dev_id), void *dev_id)
-{
- if(wifi_status_cb)
- return -EAGAIN;
- wifi_status_cb = callback;
- wifi_status_cb_devid = dev_id;
- return 0;
-}
-
-int rk29sdk_wifi_power(int on)
-{
- pr_info("%s: %d\n", __func__, on);
- if (on){
-
- #if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
-
- #if defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- rk29_sdmmc_gpio_open(0, 1);
- #else
- rk29_sdmmc_gpio_open(1, 0);
- mdelay(10);
- rk29_sdmmc_gpio_open(1, 1);
- #endif
- #endif
-
- mdelay(100);
- pr_info("wifi turn on power\n");
- }
- else
- {
-#if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
- #if defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- rk29_sdmmc_gpio_open(0, 0);
- #else
- rk29_sdmmc_gpio_open(1, 0);
- #endif
-#endif
- mdelay(100);
- pr_info("wifi shut off power\n");
-
- }
-
- rk29sdk_wifi_power_state = on;
- return 0;
-
-}
-EXPORT_SYMBOL(rk29sdk_wifi_power);
-
-
-int rk29sdk_wifi_reset(int on)
-{
- return 0;
-}
-EXPORT_SYMBOL(rk29sdk_wifi_reset);
-
-
-#if defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
-int rk29sdk_wifi_set_carddetect(int val)
-{
- pr_info("%s:%d\n", __func__, val);
- rk29sdk_wifi_mmc0_cd = val;
- if (wifi_mmc0_status_cb){
- wifi_mmc0_status_cb(val, wifi_mmc0_status_cb_devid);
- }else {
- pr_warning("%s,in mmc0 nobody to notify\n", __func__);
- }
- return 0;
-}
-
-#else
-int rk29sdk_wifi_set_carddetect(int val)
-{
- pr_info("%s:%d\n", __func__, val);
- rk29sdk_wifi_cd = val;
- if (wifi_status_cb){
- wifi_status_cb(val, wifi_status_cb_devid);
- }else {
- pr_warning("%s,in mmc1 nobody to notify\n", __func__);
- }
- return 0;
-}
-#endif
-
-EXPORT_SYMBOL(rk29sdk_wifi_set_carddetect);
-
-///////////////////////////////////////////////////////////////////////////////////
-#endif //#if defined(CONFIG_WIFI_CONTROL_FUNC)---#elif defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) --#endif
-
-
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC)
-static struct wifi_platform_data rk29sdk_wifi_control = {
- .set_power = rk29sdk_wifi_power,
- .set_reset = rk29sdk_wifi_reset,
- .set_carddetect = rk29sdk_wifi_set_carddetect,
- .mem_prealloc = rk29sdk_mem_prealloc,
-};
-
-static struct platform_device rk29sdk_wifi_device = {
- .name = "bcmdhd_wlan",
- .id = 1,
- .num_resources = ARRAY_SIZE(resources),
- .resource = resources,
- .dev = {
- .platform_data = &rk29sdk_wifi_control,
- },
-};
-
-#elif defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
-
- #if debug_combo_system
- static struct combo_module_platform_data rk29sdk_combo_module_control = {
- .set_power = rk29sdk_wifi_combo_module_power,
- .set_reset = rk29sdk_wifi_combo_module_reset,
- };
-
- static struct platform_device rk29sdk_combo_module_device = {
- .name = "combo-system",
- .id = 1,
- .dev = {
- .platform_data = &rk29sdk_combo_module_control,
- },
- };
- #endif
-
-static struct wifi_platform_data rk29sdk_wifi_control = {
- .set_power = rk29sdk_wifi_power,
- .set_reset = rk29sdk_wifi_reset,
- .set_carddetect = rk29sdk_wifi_set_carddetect,
-};
-
-static struct platform_device rk29sdk_wifi_device = {
- .name = "combo-wifi",
- .id = 1,
- .dev = {
- .platform_data = &rk29sdk_wifi_control,
- },
-};
-
-#endif
-
-
+++ /dev/null
-#include <linux/regulator/machine.h>
-#include <linux/i2c/twl.h>
-#include <linux/mfd/tps65910.h>
-#include <mach/sram.h>
-#include <linux/platform_device.h>
-
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#define PMU_POWER_SLEEP RK2928_PIN1_PA1
-#ifdef CONFIG_MFD_TPS65910
-
-extern int platform_device_register(struct platform_device *pdev);
-
-int tps65910_pre_init(struct tps65910 *tps65910){
-
- int val = 0;
- int i = 0;
- int err = -1;
-
- printk("%s,line=%d\n", __func__,__LINE__);
-#ifdef CONFIG_RK_CONFIG
- if(sram_gpio_init(get_port_config(pmic_slp).gpio, &pmic_sleep) < 0){
- printk(KERN_ERR "sram_gpio_init failed\n");
- return -EINVAL;
- }
- if(port_output_init(pmic_slp, 0, "pmic_slp") < 0){
- printk(KERN_ERR "port_output_init failed\n");
- return -EINVAL;
- }
-#else
- if(sram_gpio_init(PMU_POWER_SLEEP, &pmic_sleep) < 0){
- printk(KERN_ERR "sram_gpio_init failed\n");
- return -EINVAL;
- }
-// GPIO1A1_I2S_SCLK_NAME
- rk30_mux_api_set(GPIO1A1_I2S_SCLK_NAME, 0);
-
- gpio_request(PMU_POWER_SLEEP, "NULL");
- gpio_direction_output(PMU_POWER_SLEEP, GPIO_LOW);
-#endif
-
- val = tps65910_reg_read(tps65910, TPS65910_DEVCTRL2);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_DEVCTRL2 reg\n");
- return val;
- }
- /* Set sleep state active high and allow device turn-off after PWRON long press */
- val |= (DEVCTRL2_SLEEPSIG_POL_MASK | DEVCTRL2_PWON_LP_OFF_MASK);
-
- err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL2, val);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_DEVCTRL2 reg\n");
- return err;
- }
- #if 1
- /* set PSKIP=0 */
- val = tps65910_reg_read(tps65910, TPS65910_DCDCCTRL);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
- return val;
- }
-
- val &= ~DEVCTRL_DEV_OFF_MASK;
- val &= ~DEVCTRL_DEV_SLP_MASK;
- err = tps65910_reg_write(tps65910, TPS65910_DCDCCTRL, val);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_DCDCCTRL reg\n");
- return err;
- }
- #endif
- /* Set the maxinum load current */
- /* VDD1 */
- val = tps65910_reg_read(tps65910, TPS65910_VDD1);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_VDD1 reg\n");
- return val;
- }
-
- val |= (1<<5); //when 1: 1.5 A
- val |= (0x07<<2); //TSTEP[2:0] = 111 : 2.5 mV/|¨¬s(sampling 3 Mhz/5)
- err = tps65910_reg_write(tps65910, TPS65910_VDD1, val);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_VDD1 reg\n");
- return err;
- }
-
- /* VDD2 */
- val = tps65910_reg_read(tps65910, TPS65910_VDD2);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_VDD2 reg\n");
- return val;
- }
-
- val |= (1<<5); //when 1: 1.5 A
- err = tps65910_reg_write(tps65910, TPS65910_VDD2, val);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_VDD2 reg\n");
- return err;
- }
-
- /* VIO */
- val = tps65910_reg_read(tps65910, TPS65910_VIO);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_VIO reg\n");
- return -EIO;
- }
-
- val |= (1<<6); //when 01: 1.0 A
- err = tps65910_reg_write(tps65910, TPS65910_VIO, val);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_VIO reg\n");
- return err;
- }
- #if 1
- /* Mask ALL interrupts */
- err = tps65910_reg_write(tps65910,TPS65910_INT_MSK, 0xFF);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_INT_MSK reg\n");
- return err;
- }
-
- err = tps65910_reg_write(tps65910, TPS65910_INT_MSK2, 0x03);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_INT_MSK2 reg\n");
- return err;
- }
-
- /* Set RTC Power, disable Smart Reflex in DEVCTRL_REG */
- #if 1
- val = 0;
- val |= (DEVCTRL_SR_CTL_I2C_SEL_MASK);
- err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL, val);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_DEVCTRL reg\n");
- return err;
- }
- printk(KERN_INFO "TPS65910 Set default voltage.\n");
- #endif
- #if 0
- //read sleep control register for debug
- for(i=0; i<6; i++)
- {
- err = tps65910_reg_read(tps65910, &val, TPS65910_DEVCTRL+i);
- if (err) {
- printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
- return -EIO;
- }
- else
- printk("%s.......is 0x%04x\n",__FUNCTION__,val);
- }
- #endif
-
- #if 1
- //sleep control register
- /*set func when in sleep mode */
- val = tps65910_reg_read(tps65910, TPS65910_DEVCTRL);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
- return val;
- }
-
- val |= (1 << 1);
- err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL, val);
- if (err) {
- printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
- \n", TPS65910_VDIG1);
- return err;
- }
-
- /* open ldo when in sleep mode */
- val = tps65910_reg_read(tps65910, TPS65910_SLEEP_KEEP_LDO_ON);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
- return val;
- }
-
- val &= 0;
- err = tps65910_reg_write(tps65910, TPS65910_SLEEP_KEEP_LDO_ON, val);
- if (err) {
- printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
- \n", TPS65910_VDIG1);
- return err;
- }
-
- /*set dc mode when in sleep mode */
- val = tps65910_reg_read(tps65910, TPS65910_SLEEP_KEEP_RES_ON);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
- return val;
- }
-
- val |= 0xff;
- err = tps65910_reg_write(tps65910, TPS65910_SLEEP_KEEP_RES_ON, val);
- if (err) {
- printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
- \n", TPS65910_VDIG1);
- return err;
- }
-
- /*close ldo when in sleep mode */
- val = tps65910_reg_read(tps65910, TPS65910_SLEEP_SET_LDO_OFF);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
- return val;
- }
-
- val |= 0x90;
- //val |= 0x00;
- err = tps65910_reg_write(tps65910, TPS65910_SLEEP_SET_LDO_OFF, val);
- if (err) {
- printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
- \n", TPS65910_VDIG1);
- return err;
- }
-
- #endif
- #if 0
- //read sleep control register for debug
- for(i=0; i<6; i++)
- {
- err = tps65910_reg_read(tps65910, &val, TPS65910_DEVCTRL+i);
- if (err) {
- printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
- return -EIO;
- }
- else
- printk("%s.......is 0x%4x\n",__FUNCTION__,val);
- }
- #endif
- #endif
-
- printk("%s,line=%d\n", __func__,__LINE__);
- return 0;
-
-}
-
-
-int tps65910_post_init(struct tps65910 *tps65910)
-{
- struct regulator *dcdc;
- struct regulator *ldo;
- int i = 0;
- printk("%s,line=%d\n", __func__,__LINE__);
-
-#ifndef CONFIG_RK_CONFIG
- g_pmic_type = PMIC_TYPE_TPS65910;
-#endif
- printk("%s:g_pmic_type=%d\n",__func__,g_pmic_type);
-
- #ifdef CONFIG_RK30_PWM_REGULATOR
- platform_device_register(&pwm_regulator_device[0]);
- #endif
-
- dcdc = regulator_get(NULL, "vio"); //vcc_io
- regulator_set_voltage(dcdc, 3300000, 3300000);
- regulator_enable(dcdc);
- printk("%s set vio vcc_io=%dmV end\n", __func__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-#if defined(CONFIG_MACH_RK2928_TB) || defined(CONFIG_MACH_RK2926_TB) || defined(CONFIG_MACH_RK2926_V86)
- ldo = regulator_get(NULL, "vpll"); // vcc25
- regulator_set_voltage(ldo, 2500000, 2500000);
- regulator_enable(ldo);
- printk("%s set vpll vcc25=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-#endif
- ldo = regulator_get(NULL, "vdig2"); // vdd12
- regulator_set_voltage(ldo, 1200000, 1200000);
- regulator_enable(ldo);
- printk("%s set vdig2 vdd12=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "vaux33"); //vcc_tp
- regulator_set_voltage(ldo, 3300000, 3300000);
- regulator_enable(ldo);
- printk("%s set vaux33 vcc_tp=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- dcdc = regulator_get(NULL, "vdd_cpu"); //vdd_cpu
- regulator_set_voltage(dcdc, 1200000, 1200000);
- regulator_enable(dcdc);
- printk("%s set vdd1 vdd_cpu=%dmV end\n", __func__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- dcdc = regulator_get(NULL, "vdd2"); //vcc_ddr
- regulator_set_voltage(dcdc, 1200000, 1200000); // 1.5*4/5 = 1.2 and Vout=1.5v
- regulator_enable(dcdc);
- printk("%s set vdd2 vcc_ddr=%dmV end\n", __func__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- ldo = regulator_get(NULL, "vdig1"); //vcc18_cif
- regulator_set_voltage(ldo, 1800000, 1800000);
- regulator_enable(ldo);
- printk("%s set vdig1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- dcdc = regulator_get(NULL, "vaux1"); //vcc28_cif
- regulator_set_voltage(dcdc,2800000,2800000);
- regulator_enable(dcdc);
- printk("%s set vaux1 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- ldo = regulator_get(NULL, "vaux2"); //vcca33
- regulator_set_voltage(ldo, 3300000, 3300000);
- regulator_enable(ldo);
- printk("%s set vaux2 vcca33=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-#if defined(CONFIG_MACH_RK2928_TB) || defined(CONFIG_MACH_RK2926_TB)
- ldo = regulator_get(NULL, "vdac"); // vccio_wl
- regulator_set_voltage(ldo,1800000,1800000);
- regulator_enable(ldo);
- printk("%s set vdac vccio_wl=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-#endif
- ldo = regulator_get(NULL, "vmmc"); //vccio_wl
- regulator_set_voltage(ldo,3300000,3300000);
- regulator_enable(ldo);
- printk("%s set vmmc vccio_wl=%dmV end\n", __func__, regulator_get_voltage(ldo));
-#if defined(CONFIG_MACH_RK2928_TB) || defined(CONFIG_MACH_RK2926_TB) || defined(CONFIG_MACH_RK2926_V86) || defined(CONFIG_MACH_RK2928_PHONEPAD_760)
- //do not disable vccio wl
-#else
- regulator_disable(ldo); //for i30 sdcard used vcc_io so must close
-#endif
- regulator_put(ldo);
- udelay(100);
-
- printk("%s,line=%d END\n", __func__,__LINE__);
-
- return 0;
-}
-static struct regulator_consumer_supply tps65910_smps1_supply[] = {
- {
- .supply = "vdd1",
- },
- {
- .supply = "vdd_cpu",
- },
-};
-static struct regulator_consumer_supply tps65910_smps2_supply[] = {
- {
- .supply = "vdd2",
- },
- {
- .supply = "vdd_core",
- },
-
-};
-static struct regulator_consumer_supply tps65910_smps3_supply[] = {
- {
- .supply = "vdd3",
- },
-};
-static struct regulator_consumer_supply tps65910_smps4_supply[] = {
- {
- .supply = "vio",
- },
-};
-static struct regulator_consumer_supply tps65910_ldo1_supply[] = {
- {
- .supply = "vdig1",
- },
-};
-static struct regulator_consumer_supply tps65910_ldo2_supply[] = {
- {
- .supply = "vdig2",
- },
-};
-
-static struct regulator_consumer_supply tps65910_ldo3_supply[] = {
- {
- .supply = "vaux1",
- },
-};
-static struct regulator_consumer_supply tps65910_ldo4_supply[] = {
- {
- .supply = "vaux2",
- },
-};
-static struct regulator_consumer_supply tps65910_ldo5_supply[] = {
- {
- .supply = "vaux33",
- },
-};
-static struct regulator_consumer_supply tps65910_ldo6_supply[] = {
- {
- .supply = "vmmc",
- },
-};
-static struct regulator_consumer_supply tps65910_ldo7_supply[] = {
- {
- .supply = "vdac",
- },
-};
-
-static struct regulator_consumer_supply tps65910_ldo8_supply[] = {
- {
- .supply = "vpll",
- },
-};
-
-static struct regulator_init_data tps65910_smps1 = {
- .constraints = {
- .name = "VDD1",
- .min_uV = 600000,
- .max_uV = 1500000,
- .apply_uV = 1,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_smps1_supply),
- .consumer_supplies = tps65910_smps1_supply,
-};
-
-/* */
-static struct regulator_init_data tps65910_smps2 = {
- .constraints = {
- .name = "VDD2",
- .min_uV = 600000,
- .max_uV = 1500000,
- .apply_uV = 1,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_smps2_supply),
- .consumer_supplies = tps65910_smps2_supply,
-};
-
-/* */
-static struct regulator_init_data tps65910_smps3 = {
- .constraints = {
- .name = "VDD3",
- .min_uV = 1000000,
- .max_uV = 1400000,
- .apply_uV = 1,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_smps3_supply),
- .consumer_supplies = tps65910_smps3_supply,
-};
-
-static struct regulator_init_data tps65910_smps4 = {
- .constraints = {
- .name = "VIO",
- .min_uV = 1800000,
- .max_uV = 3300000,
- .apply_uV = 1,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_smps4_supply),
- .consumer_supplies = tps65910_smps4_supply,
-};
-static struct regulator_init_data tps65910_ldo1 = {
- .constraints = {
- .name = "VDIG1",
- .min_uV = 1200000,
- .max_uV = 2700000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo1_supply),
- .consumer_supplies = tps65910_ldo1_supply,
-};
-
-/* */
-static struct regulator_init_data tps65910_ldo2 = {
- .constraints = {
- .name = "VDIG2",
- .min_uV = 1000000,
- .max_uV = 1800000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo2_supply),
- .consumer_supplies = tps65910_ldo2_supply,
-};
-
-/* */
-static struct regulator_init_data tps65910_ldo3 = {
- .constraints = {
- .name = "VAUX1",
- .min_uV = 1800000,
- .max_uV = 3300000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo3_supply),
- .consumer_supplies = tps65910_ldo3_supply,
-};
-
-/* */
-static struct regulator_init_data tps65910_ldo4 = {
- .constraints = {
- .name = "VAUX2",
- .min_uV = 1800000,
- .max_uV = 3300000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo4_supply),
- .consumer_supplies = tps65910_ldo4_supply,
-};
-
-/* */
-static struct regulator_init_data tps65910_ldo5 = {
- .constraints = {
- .name = "VAUX33",
- .min_uV = 1800000,
- .max_uV = 3300000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo5_supply),
- .consumer_supplies = tps65910_ldo5_supply,
-};
-
-/* */
-static struct regulator_init_data tps65910_ldo6 = {
- .constraints = {
- .name = "VMMC",
- .min_uV = 1800000,
- .max_uV = 3300000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo6_supply),
- .consumer_supplies = tps65910_ldo6_supply,
-};
-
-/* */
-static struct regulator_init_data tps65910_ldo7 = {
- .constraints = {
- .name = "VDAC",
- .min_uV = 1800000,
- .max_uV = 2850000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo7_supply),
- .consumer_supplies = tps65910_ldo7_supply,
-};
-
-/* */
-static struct regulator_init_data tps65910_ldo8 = {
- .constraints = {
- .name = "VPLL",
- .min_uV = 1000000,
- .max_uV = 2500000,
- .apply_uV = 1,
- #if defined(CONFIG_MACH_RK2926_V86)
- #else
- .always_on = 1,
- #endif
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo8_supply),
- .consumer_supplies = tps65910_ldo8_supply,
-};
-void __sramfunc board_pmu_tps65910_suspend(void)
-{
-// sram_udelay(100);
- sram_gpio_set_value(pmic_sleep, GPIO_HIGH);
-}
-void __sramfunc board_pmu_tps65910_resume(void)
-{
- sram_gpio_set_value(pmic_sleep, GPIO_LOW);
- sram_udelay(2000);
-}
-static struct tps65910_board tps65910_data = {
- .irq = (unsigned)TPS65910_HOST_IRQ,
- .irq_base = IRQ_BOARD_BASE,
- .gpio_base = TPS65910_GPIO_EXPANDER_BASE,
-
- .pre_init = tps65910_pre_init,
- .post_init = tps65910_post_init,
-
- //TPS65910_NUM_REGS = 13
- // Regulators
- .tps65910_pmic_init_data[TPS65910_REG_VRTC] = NULL,
- .tps65910_pmic_init_data[TPS65910_REG_VIO] = &tps65910_smps4,
- .tps65910_pmic_init_data[TPS65910_REG_VDD1] = &tps65910_smps1,
- .tps65910_pmic_init_data[TPS65910_REG_VDD2] = &tps65910_smps2,
- .tps65910_pmic_init_data[TPS65910_REG_VDD3] = &tps65910_smps3,
- .tps65910_pmic_init_data[TPS65910_REG_VDIG1] = &tps65910_ldo1,
- .tps65910_pmic_init_data[TPS65910_REG_VDIG2] = &tps65910_ldo2,
- .tps65910_pmic_init_data[TPS65910_REG_VPLL] = &tps65910_ldo8,
- .tps65910_pmic_init_data[TPS65910_REG_VDAC] = &tps65910_ldo7,
- .tps65910_pmic_init_data[TPS65910_REG_VAUX1] = &tps65910_ldo3,
- .tps65910_pmic_init_data[TPS65910_REG_VAUX2] = &tps65910_ldo4,
- .tps65910_pmic_init_data[TPS65910_REG_VAUX33] = &tps65910_ldo5,
- .tps65910_pmic_init_data[TPS65910_REG_VMMC] = &tps65910_ldo6,
-
-
-};
-
-#endif
-
+++ /dev/null
-/* arch/arm/mach-rk2928/board-rk2928-fpga.c
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-#include <mach/dvfs.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <linux/fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/mfd/tps65910.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-#if defined(CONFIG_MODEM_SOUND)
-#include "../../../drivers/misc/modem_sound.h"
-#endif
-#if defined(CONFIG_HDMI_RK30)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-#include "../../../drivers/headset_observe/rk_headset.h"
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-
-#if defined(CONFIG_SC6610)
-#include <linux/sc6610.h>
-#endif
-
-#include "board-rk2928-phonepad-camera.c"
-#include "board-rk2928-phonepad-key.c"
-
-#ifdef CONFIG_THREE_FB_BUFFER
-#define RK30_FB0_MEM_SIZE 12*SZ_1M
-#else
-#define RK30_FB0_MEM_SIZE 8*SZ_1M
-#endif
-
-int __sramdata g_pmic_type = 0;
-
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-#define PWM_ID 0
-#define PWM_MUX_NAME GPIO0D2_PWM_0_NAME
-#define PWM_MUX_MODE GPIO0D_PWM_0
-#define PWM_MUX_MODE_GPIO GPIO0D_GPIO0D2
-#define PWM_GPIO RK2928_PIN0_PD2
-#define PWM_EFFECT_VALUE 1
-
-//#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-
-#define BL_EN_PIN RK2928_PIN1_PB0
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
-#ifdef LCD_DISP_ON_PIN
- // rk30_mux_api_set(BL_EN_MUX_NAME, BL_EN_MUX_MODE);
-
- ret = gpio_request(BL_EN_PIN, NULL);
- if (ret != 0) {
- gpio_free(BL_EN_PIN);
- }
-
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0;
-#ifdef LCD_DISP_ON_PIN
- gpio_set_value(BL_EN_PIN, !BL_EN_VALUE);
- gpio_free(BL_EN_PIN);
-#endif
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret = 0;
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- if (gpio_request(PWM_GPIO, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- gpio_direction_output(PWM_GPIO, GPIO_LOW);
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, !BL_EN_VALUE);
-#endif
-
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- gpio_free(PWM_GPIO);
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
-#ifdef LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, 1);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .min_brightness = 80,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-#endif
-
-#ifdef CONFIG_FB_ROCKCHIP
-
-#define LCD_MUX_NAME GPIO0C3_UART0_CTSN_NAME
-#define LCD_GPIO_MODE GPIO0C_GPIO0C3
-
-#define LCD_EN RK2928_PIN0_PC3
-#define LCD_EN_VALUE GPIO_LOW
-
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
-
- rk30_mux_api_set(LCD_MUX_NAME, LCD_GPIO_MODE);
- ret = gpio_request(LCD_EN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_EN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_EN, LCD_EN_VALUE); //disable
- }
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
- gpio_set_value(LCD_EN, !LCD_EN_VALUE);
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- gpio_set_value(LCD_EN, LCD_EN_VALUE);
- return 0;
-}
-
-#if defined(CONFIG_LCDC_RK2928)
-struct rk29fb_info lcdc_screen_info = {
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-
-//LCDC
-#ifdef CONFIG_LCDC_RK2928
-static struct resource resource_lcdc[] = {
- [0] = {
- .name = "lcdc reg",
- .start = RK2928_LCDC_PHYS,
- .end = RK2928_LCDC_PHYS + RK2928_LCDC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc irq",
- .start = IRQ_LCDC,
- .end = IRQ_LCDC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc = {
- .name = "rk2928-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc),
- .resource = resource_lcdc,
- .dev = {
- .platform_data = &lcdc_screen_info,
- },
-};
-#endif
-
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-
-#if defined (CONFIG_TOUCHSCREEN_I30)
-#define TOUCH_RESET_PIN RK2928_PIN3_PD5
-#define TOUCH_INT_PIN RK2928_PIN3_PC7
-int ft5306_init_platform_hw(void)
-{
- struct regulator *ldo;
-// printk("ft5306_init_platform_hw\n");
-
- ldo = regulator_get(NULL, "vaux33");
- regulator_disable(ldo);
-
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0)
- {
- gpio_free(TOUCH_RESET_PIN);
- printk("ft5306_init_platform_hw TOUCH_RESET_PIN error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0)
- {
- gpio_free(TOUCH_INT_PIN);
- printk("ift5306_init_platform_hw TOUCH_INT_PIN error\n");
- return -EIO;
- }
- gpio_direction_input(TOUCH_INT_PIN);
- gpio_direction_output(TOUCH_RESET_PIN, 1);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- msleep(50);
- regulator_enable(ldo);
- regulator_put(ldo);
- msleep(300);
- return 0;
-
-}
-
-void ft5306_exit_platform_hw(void)
-{
-// printk("ft5306_exit_platform_hw\n");
- gpio_free(TOUCH_RESET_PIN);
- gpio_free(TOUCH_INT_PIN);
-}
-
-int ft5306_platform_sleep(void)
-{
-#if 0
- struct regulator *ldo;
- ldo = regulator_get(NULL, "ldo9");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- printk("ft5306_platform_sleep\n");
-#endif
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- return 0;
-}
-
-int ft5306_platform_wakeup(void)
-{
-#if 0
- struct regulator *ldo;
- ldo = regulator_get(NULL, "ldo9");
- regulator_set_voltage(ldo, 3300000, 3300000);
- regulator_enable(ldo);
- regulator_put(ldo);
-
- printk("ft5306_platform_wakeup\n");
-#endif
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- msleep(300);
- return 0;
-}
-
-struct ft5306_platform_data ft5306_info = {
- .irq_pin = TOUCH_INT_PIN,
- .rest_pin = TOUCH_RESET_PIN,
- .init_platform_hw= ft5306_init_platform_hw,
- .exit_platform_hw= ft5306_exit_platform_hw,
- .platform_sleep = ft5306_platform_sleep,
- .platform_wakeup = ft5306_platform_wakeup,
-
-};
-#endif
-
-#if defined(CONFIG_TOUCHSCREEN_BYD693X)
-
-#define TOUCH_RESET_PIN RK2928_PIN3_PD5
-#define TOUCH_INT_PIN RK2928_PIN3_PC7
-struct byd_platform_data byd693x_info = {
- .int_pin = TOUCH_INT_PIN,
- .rst_pin = TOUCH_RESET_PIN,
- .screen_max_x = 800,
- .screen_max_y = 480,
- .xpol = -1,
-};
-#endif
-
-/*MMA7660 gsensor*/
-#if defined (CONFIG_GS_MMA7660)
-#define MMA7660_INT_PIN RK2928_PIN1_PB1
-
-static int mma7660_init_platform_hw(void)
-{
- rk30_mux_api_set(GPIO1B1_SPI_TXD_UART1_SOUT_NAME, GPIO1B_GPIO1B1);
-
- return 0;
-}
-
-static struct sensor_platform_data mma7660_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma7660_init_platform_hw,
- .orientation = {-1, 0, 0, 0, 0, -1, 0, 1, 0},
-};
-#endif
-
-
-#if defined (CONFIG_GS_KXTIK)
-#define KXTIK_INT_PIN RK2928_PIN3_PD1
-
-static struct sensor_platform_data kxtik_pdata = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .orientation = {-1, 0, 0, 0, 0, -1, 0, 1, 0},
-};
-
-#endif /* CONFIG_GS_KXTIK*/
-
-#ifdef CONFIG_LS_AP321XX
-#define LS_AP321XX_INT_PIN RK2928_PIN0_PC6
-
-static struct sensor_platform_data ls_ap321xx_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 1,
- .poll_delay_ms = 500,
-};
-#endif
-#ifdef CONFIG_PS_AP321XX
-#define PS_AP321XX_INT_PIN RK2928_PIN0_PC6
-
-static struct sensor_platform_data ps_ap321xx_info = {
- .type = SENSOR_TYPE_PROXIMITY,
- .irq_enable = 1,
- .poll_delay_ms = 500,
-};
-#endif
-
-#if defined(CONFIG_BATTERY_RK30_ADC)||defined(CONFIG_BATTERY_RK30_ADC_FAC)
-#define CHARGE_OK_PIN RK2928_PIN1_PA0
-#define DC_DET_PIN RK2928_PIN1_PA5
-int rk30_battery_adc_io_init(void){
- int ret = 0;
-
- //dc charge detect pin
- ret = gpio_request(DC_DET_PIN, NULL);
- if (ret) {
- printk("failed to request dc_det gpio\n");
- return ret ;
- }
-
- gpio_pull_updown(DC_DET_PIN, 0);//important
- ret = gpio_direction_input(DC_DET_PIN);
- if (ret) {
- printk("failed to set gpio dc_det input\n");
- return ret ;
- }
-
- //charge ok pin
- ret = gpio_request(CHARGE_OK_PIN, NULL);
- if (ret) {
- printk("failed to request charge_ok gpio\n");
- return ret ;
- }
-
- gpio_pull_updown(CHARGE_OK_PIN, 1);//important
- ret = gpio_direction_input(CHARGE_OK_PIN);
- if (ret) {
- printk("failed to set gpio charge_ok input\n");
- return ret ;
- }
-
- return 0;
-
-}
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = RK2928_PIN1_PA5,
- .batt_low_pin = INVALID_GPIO,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = RK2928_PIN1_PA0,
- .dc_det_level = GPIO_LOW, //
- .charge_ok_level = GPIO_HIGH,
-
- .io_init = rk30_battery_adc_io_init,
-};
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-
-
-#if CONFIG_RK30_PWM_REGULATOR
-const static int pwm_voltage_map[] = {
- 950000,975000,1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000, 1375000, 1400000
-};
-
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_core",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] =
-{
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
- .pwm_id = 2,
- .pwm_gpio = RK2928_PIN0_PD4,
- .pwm_iomux_name = GPIO0D4_PWM_2_NAME,
- .pwm_iomux_pwm = GPIO0D_PWM_2,
- .pwm_iomux_gpio = GPIO0D_GPIO0D4,
- .pwm_voltage = 1200000,
- .suspend_voltage = 1050000,
- .min_uV = 950000,
- .max_uV = 1400000,
- .coefficient = 504, //50.4%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-#endif
-
-#if defined(CONFIG_MODEM_SOUND)
-
-struct modem_sound_data modem_sound_info = {
- .spkctl_io = RK2928_PIN3_PD4,
- .spkctl_active = GPIO_HIGH,
-};
-
-struct platform_device modem_sound_device = {
- .name = "modem_sound",
- .id = -1,
- .dev = {
- .platform_data = &modem_sound_info,
- }
- };
-#endif
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and sdio.noted by xbw at 2012-03-05
-**************************************************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "board-rk2928-phonepad-sdmmc.c"
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
-#define SDMMC0_WRITE_PROTECT_PIN RK2928_PIN1_PA7 //According to your own project to set the value of write-protect-pin.
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
-#define SDMMC1_WRITE_PROTECT_PIN RK2928_PIN0_PD5 //According to your own project to set the value of write-protect-pin.
-#endif
-
-#define RK29SDK_WIFI_SDIO_CARD_DETECT_N RK2928_PIN0_PB2
-
-#endif //endif ---#ifdef CONFIG_SDMMC_RK29
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- rk30_mux_api_set(GPIO1C1_MMC0_DETN_NAME, GPIO1C_MMC0_DETN);
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
- .detect_irq = INVALID_GPIO,
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
-#else
- .write_prt = INVALID_GPIO,
-#endif
-};
-#endif // CONFIG_SDMMC0_RK29
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- rk30_mux_api_set(GPIO0B0_MMC1_CMD_NAME, GPIO0B_MMC1_CMD);
- rk30_mux_api_set(GPIO0B1_MMC1_CLKOUT_NAME, GPIO0B_MMC1_CLKOUT);
- rk30_mux_api_set(GPIO0B3_MMC1_D0_NAME, GPIO0B_MMC1_D0);
- rk30_mux_api_set(GPIO0B4_MMC1_D1_NAME, GPIO0B_MMC1_D1);
- rk30_mux_api_set(GPIO0B5_MMC1_D2_NAME, GPIO0B_MMC1_D2);
- rk30_mux_api_set(GPIO0B6_MMC1_D3_NAME, GPIO0B_MMC1_D3);
- //rk30_mux_api_set(GPIO0B2_MMC1_DETN_NAME, GPIO0B_MMC1_DETN);
-
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-#if 1
- .detect_irq = INVALID_GPIO,//RK29SDK_WIFI_SDIO_CARD_DETECT_N,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
-#else
- .detect_irq = INVALID_GPIO,
- .enable_sd_wakeup = 0,
-#endif
-
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-#if defined(CONFIG_SC6610)
-static int sc6610_io_init(void)
-{
-
- return 0;
-}
-
-static int sc6610_io_deinit(void)
-{
-
-
- return 0;
-}
-
-struct rk29_sc6610_data rk29_sc6610_info = {
- .io_init = sc6610_io_init,
- .io_deinit = sc6610_io_deinit,
- .bp_power = RK2928_PIN3_PC2,//RK29_PIN0_PB4,
- .bp_reset = INVALID_GPIO,//RK29_PIN0_PB3,
- .bp_wakeup_ap = RK2928_PIN3_PC3,//RK29_PIN0_PC2,
- .ap_wakeup_bp = RK2928_PIN3_PC4,//RK29_PIN0_PB0,
- .modem_assert = RK2928_PIN3_PC5,
-};
-struct platform_device rk29_device_sc6610 = {
- .name = "SC6610",
- .id = -1,
- .dev = {
- .platform_data = &rk29_sc6610_info,
- }
- };
-#endif
-#if defined (CONFIG_RK_HEADSET_DET) || defined (CONFIG_RK_HEADSET_IRQ_HOOK_ADC_DET)
-static int rk_headset_io_init(int gpio)
-{
- int ret;
- ret = gpio_request(gpio, "headset_io");
- if(ret)
- return ret;
-
- rk30_mux_api_set(GPIO1B4_SPI_CSN1_NAME, GPIO1B_GPIO1B4);
- gpio_pull_updown(gpio, PullDisable);
- gpio_direction_input(gpio);
- mdelay(50);
- return 0;
-};
-
-static int rk_hook_io_init(int gpio)
-{
- int ret;
- ret = gpio_request(gpio, "hook_io");
- if(ret)
- return ret;
-
- rk30_mux_api_set(GPIO0D1_UART2_CTSN_NAME, GPIO0D_GPIO0D1);
- gpio_pull_updown(gpio, PullDisable);
- gpio_direction_input(gpio);
- mdelay(50);
- return 0;
-};
-
-struct rk_headset_pdata rk_headset_info = {
- .Headset_gpio = RK2928_PIN1_PB4,
- .Hook_gpio = RK2928_PIN0_PD1,
- .Hook_down_type = HOOK_DOWN_HIGH,
- .headset_in_type = HEADSET_IN_HIGH,
- .hook_key_code = KEY_MEDIA,
- .headset_io_init = rk_headset_io_init,
- .hook_io_init = rk_hook_io_init,
-};
-struct platform_device rk_device_headset = {
- .name = "rk_headsetdet",
- .id = 0,
- .dev = {
- .platform_data = &rk_headset_info,
- }
-};
-#endif
-#ifdef CONFIG_SND_SOC_RK2928
-static struct resource resources_acodec[] = {
- {
- .start = RK2928_ACODEC_PHYS,
- .end = RK2928_ACODEC_PHYS + RK2928_ACODEC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = RK2928_PIN3_PD4,
- .end = RK2928_PIN3_PD4,
- .flags = IORESOURCE_IO,
- },
-};
-
-static struct platform_device device_acodec = {
- .name = "rk2928-codec",
- .id = -1,
- .num_resources = ARRAY_SIZE(resources_acodec),
- .resource = resources_acodec,
-};
-#endif
-
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_FB_ROCKCHIP
- &device_fb,
-#endif
-#ifdef CONFIG_LCDC_RK2928
- &device_lcdc,
-#endif
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- &rk29_device_backlight,
-#endif
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_SND_SOC_RK2928
- &device_acodec,
-#endif
-
-#if defined(CONFIG_BATTERY_RK30_ADC)||defined(CONFIG_BATTERY_RK30_ADC_FAC)
- &rk30_device_adc_battery,
-#endif
-#if defined(CONFIG_SC6610)
- &rk29_device_sc6610,
-
-#endif
-#if defined (CONFIG_RK_HEADSET_DET) || defined (CONFIG_RK_HEADSET_IRQ_HOOK_ADC_DET)
- &rk_device_headset,
-#endif
-#if defined (CONFIG_MODEM_SOUND)
- &modem_sound_device,
-#endif
-};
-//i2c
-#ifdef CONFIG_I2C0_RK30
-#ifdef CONFIG_MFD_TPS65910
-#define TPS65910_HOST_IRQ RK2928_PIN3_PC6
-#define PMU_POWER_SLEEP RK2928_PIN1_PA1
-
-static struct pmu_info tps65910_dcdc_info[] = {
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vdd2", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vio", //vcc_io
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
-
-};
-static struct pmu_info tps65910_ldo_info[] = {
- #if defined(CONFIG_MACH_RK2928_TB) || defined(CONFIG_MACH_RK2926_TB)
- {
- .name = "vpll", //vcc25
- .min_uv = 2500000,
- .max_uv = 2500000,
- },
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "vdac", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- #else
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 1500000,
- .max_uv = 1500000,
- },
-
- {
- .name = "vdig2", //vdd11
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vaux1", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "vaux2", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vaux33", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vmmc", //
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- #endif
- };
-
-#include "board-rk2928-sdk-tps65910.c"
-#endif
-
-#ifdef CONFIG_REGULATOR_ACT8931
-
-#if defined(CONFIG_MACH_RK2928_SDK)
-#define ACT8931_CHGSEL_PIN RK2928_PIN0_PD0
-#else
-#define ACT8931_CHGSEL_PIN RK2928_PIN1_PA1
-#endif
-
-static struct pmu_info act8931_dcdc_info[] = {
- {
- .name = "act_dcdc1", //vcc_io
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_dcdc2", //ddr
- .min_uv = 1500000,
- .max_uv = 1500000,
- },
- {
- .name = "vdd_cpu", //vdd_arm
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
-
-};
-static struct pmu_info act8931_ldo_info[] = {
- {
- .name = "act_ldo1", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "act_ldo2", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo3", //vcca30
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
- {
- .name = "act_ldo4", //vcc_wl
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
-};
-#include "board-rk2928-sdk-act8931.c"
-#endif
-
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-#if defined (CONFIG_REGULATOR_ACT8931)
- {
- .type = "act8931",
- .addr = 0x5b,
- .flags = 0,
- .platform_data=&act8931_data,
- },
-#endif
-};
-#endif
-#ifdef CONFIG_I2C1_RK30
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_GS_MMA7660)
- {
- .type = "gs_mma7660",
- .addr = 0x4c,
- .flags = 0,
- .irq = MMA7660_INT_PIN,
- .platform_data = &mma7660_info,
- },
-#endif
-
-
-#if defined (CONFIG_GS_KXTIK)
- {
- .type = "gs_kxtik",
- .addr = 0x0F,
- .flags = 0,
- .platform_data = &kxtik_pdata,
- .irq = KXTIK_INT_PIN, // Replace with appropriate GPIO setup
- },
-#endif
-
-#ifdef CONFIG_LS_AP321XX
- {
- .type = "ls_ap321xx",
- .addr = 0x1E,
- .flags = 0,
- .irq = LS_AP321XX_INT_PIN,
- .platform_data = &ls_ap321xx_info
- },
-#endif
-
-#ifdef CONFIG_PS_AP321XX
- {
- .type = "ps_ap321xx",
- .addr = 0x1E,
- .flags = 0,
- .irq = PS_AP321XX_INT_PIN,
- .platform_data = &ps_ap321xx_info
- },
-#endif
-
-#ifdef CONFIG_RDA5990
-#define RDA_WIFI_CORE_ADDR (0x13)
-#define RDA_WIFI_RF_ADDR (0x14) //correct add is 0x14
-#define RDA_BT_CORE_ADDR (0x15)
-#define RDA_BT_RF_ADDR (0x16)
-
-#define RDA_WIFI_RF_I2C_DEVNAME "rda_wifi_rf_i2c"
-#define RDA_WIFI_CORE_I2C_DEVNAME "rda_wifi_core_i2c"
-#define RDA_BT_RF_I2C_DEVNAME "rda_bt_rf_i2c"
-#define RDA_BT_CORE_I2C_DEVNAME "rda_bt_core_i2c"
- {
- .type = RDA_WIFI_CORE_I2C_DEVNAME,
- .addr = RDA_WIFI_CORE_ADDR,
- .flags = 0,
-
- },
-
- {
- .type = RDA_WIFI_RF_I2C_DEVNAME,
- .addr = RDA_WIFI_RF_ADDR,
- .flags = 0,
-
- },
- {
- .type = RDA_BT_CORE_I2C_DEVNAME,
- .addr = RDA_BT_CORE_ADDR,
- .flags = 0,
-
- },
- {
- .type = RDA_BT_RF_I2C_DEVNAME,
- .addr = RDA_BT_RF_ADDR,
- .flags = 0,
-
- },
-#endif
-
-};
-#endif
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-#if defined (CONFIG_TOUCHSCREEN_I30)
- {
- .type = "ft5x0x_ts",
- .addr = 0x38,
- .flags = 0,
- .irq = TOUCH_INT_PIN,
- .platform_data = &ft5306_info,
- },
-#endif
-#if defined(CONFIG_TOUCHSCREEN_BYD693X)
- {
- .type = "byd693x-ts",
- .addr = 0x52,
- .flags = 0,
- .irq = TOUCH_INT_PIN,
- .platform_data = &byd693x_info,
- },
-#endif
-};
-#endif
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- //set iomux (gpio) here
-
- return 0;
-}
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(4, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-
-#define POWER_ON_PIN RK2928_PIN1_PA2 //power_hold
-static void rk2928_pm_power_off(void)
-{
- printk(KERN_ERR "rk2928_pm_power_off start...\n");
-
- #if defined(CONFIG_MFD_TPS65910)
- tps65910_device_shutdown();//tps65910 shutdown
- #endif
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
-
-};
-
-static void __init rk2928_board_init(void)
-{
- gpio_request(POWER_ON_PIN, "poweronpin");
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
- gpio_free(POWER_ON_PIN);
-
- pm_power_off = rk2928_pm_power_off;
-
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
-
-}
-
-static void __init rk2928_reserve(void)
-{
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0", RK30_FB0_MEM_SIZE);
- resource_fb[0].end = resource_fb[0].start + RK30_FB0_MEM_SIZE - 1;
-#endif
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
- board_mem_reserved();
-}
-/**
- * dvfs_cpu_logic_table: table for arm and logic dvfs
- * @frequency : arm frequency
- * @cpu_volt : arm voltage depend on frequency
- * @logic_volt : logic voltage arm requests depend on frequency
- * comments : min arm/logic voltage
- */
-static struct dvfs_arm_table dvfs_cpu_logic_table[] = {
- {.frequency = 216 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 312 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 408 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 504 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 600 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 696 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 816 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
- //{.frequency = 912 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
- //{.frequency = 1008 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
-#if 0
- {.frequency = 1104 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 1200 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 1104 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 1248 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
-#endif
- //{.frequency = 1000 * 1000, .cpu_volt = 1225 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- {.frequency = 266 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1275 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1125 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
-static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
-static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
-
-void __init board_clock_init(void)
-{
- rk2928_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
- dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
- //dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
- printk("%s end\n", __func__);
-}
-
-
-MACHINE_START(RK2928, "RK2928board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk2928_fixup,
- .reserve = &rk2928_reserve,
- .map_io = rk2928_map_io,
- .init_irq = rk2928_init_irq,
- .timer = &rk2928_timer,
- .init_machine = rk2928_board_init,
-MACHINE_END
+++ /dev/null
-#include <linux/regulator/machine.h>
-#include <linux/regulator/act8931.h>
-#include <mach/sram.h>
-#include <linux/platform_device.h>
-
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <mach/board.h>
-
-#ifdef CONFIG_REGULATOR_ACT8931
-
-#define ACT8931_CHGSEL_VALUE GPIO_HIGH /* Declined to 20% current */
-
-extern int platform_device_register(struct platform_device *pdev);
-
-static int act8931_set_init(struct act8931 *act8931)
-{
- struct regulator *dcdc;
- struct regulator *ldo;
- int i = 0;
- printk("%s,line=%d\n", __func__,__LINE__);
-
-#ifndef CONFIG_RK_CONFIG
- g_pmic_type = PMIC_TYPE_ACT8931;
-#endif
- printk("%s:g_pmic_type=%d\n",__func__,g_pmic_type);
-
- #ifdef CONFIG_RK30_PWM_REGULATOR
- platform_device_register(&pwm_regulator_device[0]);
- #endif
-
- for(i = 0; i < ARRAY_SIZE(act8931_dcdc_info); i++)
- {
-
- if(act8931_dcdc_info[i].min_uv == 0 && act8931_dcdc_info[i].max_uv == 0)
- continue;
- dcdc =regulator_get(NULL, act8931_dcdc_info[i].name);
- regulator_set_voltage(dcdc, act8931_dcdc_info[i].min_uv, act8931_dcdc_info[i].max_uv);
- regulator_enable(dcdc);
- printk("%s %s =%dmV end\n", __func__,act8931_dcdc_info[i].name, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
- }
-
- for(i = 0; i < ARRAY_SIZE(act8931_ldo_info); i++)
- {
- if(act8931_ldo_info[i].min_uv == 0 && act8931_ldo_info[i].max_uv == 0)
- continue;
- ldo =regulator_get(NULL, act8931_ldo_info[i].name);
- regulator_set_voltage(ldo, act8931_ldo_info[i].min_uv, act8931_ldo_info[i].max_uv);
- regulator_enable(ldo);
- printk("%s %s =%dmV end\n", __func__,act8931_ldo_info[i].name, regulator_get_voltage(ldo));
- regulator_put(ldo);
- }
-
- printk("%s,line=%d END\n", __func__,__LINE__);
-
- return 0;
-}
-
-static struct regulator_consumer_supply act8931_buck1_supply[] = {
- {
- .supply = "act_dcdc1",
- },
-
-};
-static struct regulator_consumer_supply act8931_buck2_supply[] = {
- {
- .supply = "act_dcdc2",
- },
-
-};
-static struct regulator_consumer_supply act8931_buck3_supply[] = {
- {
- .supply = "act_dcdc3",
- },
- {
- .supply = "vdd_cpu",
- },
-};
-
-static struct regulator_consumer_supply act8931_ldo1_supply[] = {
- {
- .supply = "act_ldo1",
- },
-};
-static struct regulator_consumer_supply act8931_ldo2_supply[] = {
- {
- .supply = "act_ldo2",
- },
-};
-
-static struct regulator_consumer_supply act8931_ldo3_supply[] = {
- {
- .supply = "act_ldo3",
- },
-};
-static struct regulator_consumer_supply act8931_ldo4_supply[] = {
- {
- .supply = "act_ldo4",
- },
-};
-
-static struct regulator_init_data act8931_buck1 = {
- .constraints = {
- .name = "ACT_DCDC1",
- .min_uV = 600000,
- .max_uV = 3900000,
- .apply_uV = 1,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(act8931_buck1_supply),
- .consumer_supplies = act8931_buck1_supply,
-};
-
-/* */
-static struct regulator_init_data act8931_buck2 = {
- .constraints = {
- .name = "ACT_DCDC2",
- .min_uV = 600000,
- .max_uV = 3900000,
- .apply_uV = 1,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(act8931_buck2_supply),
- .consumer_supplies = act8931_buck2_supply,
-};
-
-/* */
-static struct regulator_init_data act8931_buck3 = {
- .constraints = {
- .name = "ACT_DCDC3",
- .min_uV = 600000,
- .max_uV = 3900000,
- .apply_uV = 1,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(act8931_buck3_supply),
- .consumer_supplies = act8931_buck3_supply,
-};
-
-static struct regulator_init_data act8931_ldo1 = {
- .constraints = {
- .name = "ACT_LDO1",
- .min_uV = 600000,
- .max_uV = 3900000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(act8931_ldo1_supply),
- .consumer_supplies = act8931_ldo1_supply,
-};
-
-/* */
-static struct regulator_init_data act8931_ldo2 = {
- .constraints = {
- .name = "ACT_LDO2",
- .min_uV = 600000,
- .max_uV = 3900000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(act8931_ldo2_supply),
- .consumer_supplies = act8931_ldo2_supply,
-};
-
-/* */
-static struct regulator_init_data act8931_ldo3 = {
- .constraints = {
- .name = "ACT_LDO3",
- .min_uV = 600000,
- .max_uV = 3900000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(act8931_ldo3_supply),
- .consumer_supplies = act8931_ldo3_supply,
-};
-
-/* */
-static struct regulator_init_data act8931_ldo4 = {
- .constraints = {
- .name = "ACT_LDO4",
- .min_uV = 600000,
- .max_uV = 3900000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(act8931_ldo4_supply),
- .consumer_supplies = act8931_ldo4_supply,
-};
-
-static struct act8931_regulator_subdev act8931_regulator_subdev_id[] = {
- {
- .id=0,
- .initdata=&act8931_ldo1,
- },
-
- {
- .id=1,
- .initdata=&act8931_ldo2,
- },
-
- {
- .id=2,
- .initdata=&act8931_ldo3,
- },
-
- {
- .id=3,
- .initdata=&act8931_ldo4,
- },
-
- {
- .id=4,
- .initdata=&act8931_buck1,
- },
-
- {
- .id=5,
- .initdata=&act8931_buck2,
- },
- {
- .id=6,
- .initdata=&act8931_buck3,
- },
-
-};
-
-static struct act8931_platform_data act8931_data={
- .set_init=act8931_set_init,
- .num_regulators=7,
- .regulators=act8931_regulator_subdev_id,
-};
-
-#ifdef CONFIG_HAS_EARLYSUSPEND
-void act8931_early_suspend(struct early_suspend *h)
-{
-#if CONFIG_RK_CONFIG
- port_output_off(chg_sel);
-#else
- gpio_direction_output(ACT8931_CHGSEL_PIN, !ACT8931_CHGSEL_VALUE);
-#endif
-}
-
-void act8931_late_resume(struct early_suspend *h)
-{
-#if CONFIG_RK_CONFIG
- port_output_on(chg_sel);
-#else
- gpio_direction_output(ACT8931_CHGSEL_PIN, ACT8931_CHGSEL_VALUE);
-#endif
-}
-#endif
-
-#endif
-
+++ /dev/null
-#ifdef CONFIG_VIDEO_RK29
-#include <plat/rk_camera.h>
-/* Notes:
-
-Simple camera device registration:
-
- new_camera_device(sensor_name,\ // sensor name, it is equal to CONFIG_SENSOR_X
- face,\ // sensor face information, it can be back or front
- pwdn_io,\ // power down gpio configuration, it is equal to CONFIG_SENSOR_POWERDN_PIN_XX
- flash_attach,\ // sensor is attach flash or not
- mir,\ // sensor image mirror and flip control information
- i2c_chl,\ // i2c channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_IIC_ADAPTER_ID_X
- cif_chl) \ // cif channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_CIF_INDEX_X
-
-Comprehensive camera device registration:
-
- new_camera_device_ex(sensor_name,\
- face,\
- ori,\ // sensor orientation, it is equal to CONFIG_SENSOR_ORIENTATION_X
- pwr_io,\ // sensor power gpio configuration, it is equal to CONFIG_SENSOR_POWER_PIN_XX
- pwr_active,\ // sensor power active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- rst_io,\ // sensor reset gpio configuration, it is equal to CONFIG_SENSOR_RESET_PIN_XX
- rst_active,\ // sensor reset active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- pwdn_io,\
- pwdn_active,\ // sensor power down active level, is equal to CONFIG_SENSOR_POWERDNACTIVE_LEVEL_X
- flash_attach,\
- res,\ // sensor resolution, this is real resolution or resoltuion after interpolate
- mir,\
- i2c_chl,\
- i2c_spd,\ // i2c speed , 100000 = 100KHz
- i2c_addr,\ // the i2c slave device address for sensor
- cif_chl,\
- mclk)\ // sensor input clock rate, 24 or 48
-
-*/
-static struct rkcamera_platform_data new_camera[] = {
-#if defined(CONFIG_MACH_RK2928_SDK)
- new_camera_device(RK29_CAM_SENSOR_GC0308,
- front,
- RK2928_PIN3_PD7,
- 0,
- 0,
- 1,
- 0),
-#else
- new_camera_device(RK29_CAM_SENSOR_GC0308,
- front,
- RK2928_PIN3_PB3,
- 0,
- 0,
- 1,
- 0),
-#endif
- new_camera_device_end
-};
-/*---------------- Camera Sensor Macro Define Begin ------------------------*/
-/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
-#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_OV5642 /* back camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_0 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 0
-#define CONFIG_SENSOR_CIF_INDEX_0 0
-#define CONFIG_SENSOR_ORIENTATION_0 90
-#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 INVALID_GPIO//RK2928_PIN3_PB3
-#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000
-
-#define CONFIG_SENSOR_01 RK29_CAM_SENSOR_OV5642 /* back camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_01 0x00
-#define CONFIG_SENSOR_CIF_INDEX_01 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 4
-#define CONFIG_SENSOR_ORIENTATION_01 90
-#define CONFIG_SENSOR_POWER_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_01 INVALID_GPIO//RK2928_PIN3_PB3
-#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_01 30000
-
-#define CONFIG_SENSOR_02 RK29_CAM_SENSOR_OV5640 /* back camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_02 0x00
-#define CONFIG_SENSOR_CIF_INDEX_02 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 4
-#define CONFIG_SENSOR_ORIENTATION_02 90
-#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_02 INVALID_GPIO//RK2928_PIN3_PB3
-#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000
-
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_GC0308 /* front camera sensor 0 */
-#define CONFIG_SENSOR_IIC_ADDR_1 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 1
-#define CONFIG_SENSOR_CIF_INDEX_1 0
-#define CONFIG_SENSOR_ORIENTATION_1 270
-#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-
-#if defined(CONFIG_MACH_RK2928_SDK)
-#define CONFIG_SENSOR_POWERDN_PIN_1 RK2928_PIN3_PD7
-#else
-#define CONFIG_SENSOR_POWERDN_PIN_1 RK2928_PIN3_PB3
-#endif
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000
-
-#define CONFIG_SENSOR_11 RK29_CAM_SENSOR_OV2659 /* front camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_11 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 3
-#define CONFIG_SENSOR_CIF_INDEX_11 0
-#define CONFIG_SENSOR_ORIENTATION_11 270
-#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_11 30000
-
-#define CONFIG_SENSOR_12 RK29_CAM_SENSOR_OV2659//RK29_CAM_SENSOR_OV2655 /* front camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_12 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 3
-#define CONFIG_SENSOR_CIF_INDEX_12 0
-#define CONFIG_SENSOR_ORIENTATION_12 270
-#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_12 30000
-
-
-#endif //#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk2928_camera.c"
-/*---------------- Camera Sensor Macro Define End ---------*/
-
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#if defined(CONFIG_MACH_RK2926_V86)
-#define CAMERA_NAME "sp2518_back"
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_PMU 1
-#define CONFIG_SENSOR_POWER_IOCTL_USR 1
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 1
-#else
-#define CONFIG_SENSOR_POWER_IOCTL_USR 0 //define this refer to your board layout
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#endif
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
-
-static void rk_cif_power(int on)
-{
- struct regulator *ldo_18,*ldo_28;
-
- #if defined(CONFIG_MACH_RK2926_V86)
- ldo_28 = regulator_get(NULL, "vaux1"); // vcc28_cif
- ldo_18 = regulator_get(NULL, "vdig1"); // vcc18_cif
- #else
- ldo_28 = regulator_get(NULL, "ldo7"); // vcc28_cif
- ldo_18 = regulator_get(NULL, "ldo1"); // vcc18_cif
- #endif
- if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){
- printk("get cif ldo failed!\n");
- return;
- }
- if(on == 0){
- while(regulator_is_enabled(ldo_28)>0)
- regulator_disable(ldo_28);
- regulator_put(ldo_28);
- while(regulator_is_enabled(ldo_18)>0)
- regulator_disable(ldo_18);
- regulator_put(ldo_18);
- mdelay(500);
- }
- else{
- regulator_set_voltage(ldo_28, 2800000, 2800000);
- regulator_enable(ldo_28);
- // printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
- regulator_put(ldo_28);
-
- regulator_set_voltage(ldo_18, 1800000, 1800000);
- // regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(ldo_18);
- // printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
- regulator_put(ldo_18);
- }
-}
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- //#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
- rk_cif_power(on);
-}
-#endif
-
-#if CONFIG_SENSOR_RESET_IOCTL_USR
-static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
-static void rk_cif_powerdowen(int on)
-{
- struct regulator *ldo_28;
- ldo_28 = regulator_get(NULL, "vpll"); // vcc28_cif
- if (ldo_28 == NULL || IS_ERR(ldo_28) ){
- printk("get cif vpll ldo failed!\n");
- return;
- }
-
- if( CONFIG_SENSOR_POWERDNACTIVE_LEVEL_PMU ) {
- if(on == 0){//enable camera
- regulator_set_voltage(ldo_28, 2500000, 2500000);
- regulator_enable(ldo_28);
- printk(" %s set vpll vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
- regulator_put(ldo_28);
- }else{//disable camera
- while(regulator_is_enabled(ldo_28)>0){
- int a = regulator_disable(ldo_28);
- }
- regulator_put(ldo_28);
- mdelay(500);
- }
- }else{
-
- if(on == 1){//enable camera
- regulator_set_voltage(ldo_28, 2500000, 2500000);
- regulator_enable(ldo_28);
- printk(" %s set vpll vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
- regulator_put(ldo_28);
- }else{//disable camera
- while(regulator_is_enabled(ldo_28)>0){
- regulator_disable(ldo_28);
- }
- regulator_put(ldo_28);
- mdelay(500);
- }
- }
-}
-static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #if defined(CONFIG_MACH_RK2926_V86)
- int ret = 0;
- if(strcmp(res->dev_name,CAMERA_NAME)==0)//"sp2518_back") == 0)
- {
- //Èç¹ûΪpmu¿ØÖƵÄÒý½Å£¬"ov5642_front_1" ¸ù¾Ý sensorÃû×Ö £¬Ç°ºóÖà £¬ sensorÐòºÅÈ·¶¨
- //¾ßÌåpmu¿ØÖƲÙ×÷£¬¿É²Î¿¼ÎļþĩβµÄ²Î¿¼´úÂë
- printk("%s.............pwm power\n",__FUNCTION__);
- rk_cif_powerdowen(on);
- }else{ //gpio¿ØÖƵIJÙ×÷
- int camera_powerdown = res->gpio_powerdown;
- int camera_ioflag = res->gpio_flag;
- int camera_io_init = res->gpio_init; // int ret = 0;
- if (camera_powerdown != INVALID_GPIO) {
- if (camera_io_init & RK29_CAM_POWERDNACTIVE_MASK) {
- if (on) {
- gpio_set_value(camera_powerdown, ((camera_ioflag&RK29_CAM_POWERDNACTIVE_MASK)>>RK29_CAM_POWERDNACTIVE_BITPOS));
- printk("%s..%s..PowerDownPin=%d ..PinLevel = %x \n",__FUNCTION__,res->dev_name,camera_powerdown, ((camera_ioflag&RK29_CAM_POWERDNACTIVE_MASK)>>RK29_CAM_POWERDNACTIVE_BITPOS));
- } else {
- gpio_set_value(camera_powerdown,(((~camera_ioflag)&RK29_CAM_POWERDNACTIVE_MASK)>>RK29_CAM_POWERDNACTIVE_BITPOS));
- printk("%s..%s..PowerDownPin= %d..PinLevel = %x \n",__FUNCTION__,res->dev_name, camera_powerdown, (((~camera_ioflag)&RK29_CAM_POWERDNACTIVE_MASK)>>RK29_CAM_POWERDNACTIVE_BITPOS));
- }
- } else { ret = RK29_CAM_EIO_REQUESTFAIL;
- printk("%s..%s..PowerDownPin=%d request failed!\n",__FUNCTION__,res->dev_name,camera_powerdown); }
- } else {
- ret = RK29_CAM_EIO_INVALID;
- }
- }
- return ret;
- #else
- #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
- #endif
-}
-#endif
-
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-
-#if CONFIG_SENSOR_IIC_ADDR_0
-static struct reginfo_t rk_init_data_sensor_reg_0[] =
-{
- {0x0000, 0x00,0,0}
- };
-static struct reginfo_t rk_init_data_sensor_winseqreg_0[] ={
- {0x0000, 0x00,0,0}
- };
-#endif
-
-#if CONFIG_SENSOR_IIC_ADDR_1
-static struct reginfo_t rk_init_data_sensor_reg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_01
-static struct reginfo_t rk_init_data_sensor_reg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_02
-static struct reginfo_t rk_init_data_sensor_reg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_11
-static struct reginfo_t rk_init_data_sensor_reg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_12
-static struct reginfo_t rk_init_data_sensor_reg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] =
-{
- #if CONFIG_SENSOR_IIC_ADDR_0
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_0,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_1
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_1,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_01
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_01,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_02
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_02,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_11
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_11,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_12
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_12,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
-
- };
-#include "../../../drivers/media/video/rk2928_camera.c"
-
-#endif /* CONFIG_VIDEO_RK29 */
+++ /dev/null
-#include <mach/gpio.h>
-#include <plat/key.h>
-
-#define EV_ENCALL KEY_F4
-#define EV_MENU KEY_F1
-
-#define PRESS_LEV_LOW 1
-#define PRESS_LEV_HIGH 0
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "play",
- .code = KEY_POWER,
- #if defined(CONFIG_MACH_RK2928_SDK)
- .gpio = RK2928_PIN0_PD1,
- #else
- .gpio = RK2928_PIN1_PA4,
- #endif
- .active_low = PRESS_LEV_LOW,
- //.code_long_press = EV_ENCALL,
- .wakeup = 1,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .gpio = INVALID_GPIO,
- .adc_value = 1,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .gpio = INVALID_GPIO,
- .adc_value = 512,
- .active_low = PRESS_LEV_LOW,
- },
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = 1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
+++ /dev/null
-/* arch/arm/mach-rk30/board-rk30-sdk-sdmmc.c
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * *
- * History:
- * ver1.0 add combo-wifi operateions. such as commit e049351a09c78db8a08aa5c49ce8eba0a3d6824e, at 2012-09-16
- * ver2.0 Unify all the file versions of board_xxxx_sdmmc.c, at 2012-11-05
- *
- * Content:
- * Part 1: define the gpio for SD-MMC-SDIO-Wifi functions according to your own projects.
- ***********************************************************************************
- * Please set the value according to your own project.
- ***********************************************************************************
- *
- * Part 2: define the gpio for the SDMMC controller. Based on the chip datasheet.
- ***********************************************************************************
- * Please do not change, each platform has a fixed set. !!!!!!!!!!!!!!!!!!
- * The system personnel will set the value depending on the specific arch datasheet,
- * such as RK29XX, RK30XX.
- * If you have any doubt, please consult BangWang Xie.
- ***********************************************************************************
- *
- *.Part 3: The various operations of the SDMMC-SDIO module
- ***********************************************************************************
- * Please do not change, each platform has a fixed set. !!!!!!!!!!!!!!!!!!
- * define the varaious operations for SDMMC module
- * Generally only the author of SDMMC module will modify this section.
- * If you have any doubt, please consult BangWang Xie.
- ***********************************************************************************
- *
- *.Part 4: The various operations of the Wifi-BT module
- ***********************************************************************************
- * Please do not change, each module has a fixed set. !!!!!!!!!!!!!!!!!!
- * define the varaious operations for Wifi module
- * Generally only the author of Wifi module will modify this section.
- * If you have any doubt, please consult BangWang Xie, Weiguo Hu, and Weilong Gao.
- ***********************************************************************************
- *
- */
-
-//1.Part 1: define the gpio for SD-MMC-SDIO-Wifi functions according to your own projects.
-
-/*************************************************************************
-* define the gpio for sd-sdio-wifi module
-*************************************************************************/
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
-#define SDMMC0_WRITE_PROTECT_PIN RK30_PIN3_PB2 //According to your own project to set the value of write-protect-pin.
-#define SDMMC0_WRITE_PROTECT_ENABLE_VALUE GPIO_HIGH
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
-#define SDMMC1_WRITE_PROTECT_PIN RK30_PIN3_PB3 //According to your own project to set the value of write-protect-pin.
-#define SDMMC1_WRITE_PROTECT_ENABLE_VALUE GPIO_HIGH
-#endif
-
-#if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
-#define RK29SDK_WIFI_SDIO_CARD_INT RK30_PIN3_PD2
-#endif
-
-//define the card-detect-pin.
-#if defined(CONFIG_ARCH_RK29)
-//refer to file /arch/arm/mach-rk29/include/mach/Iomux.h
-//define reset-pin
-#define RK29SDK_SD_CARD_DETECT_N RK29_PIN2_PA2 //According to your own project to set the value of card-detect-pin.
-#define RK29SDK_SD_CARD_INSERT_LEVEL GPIO_LOW // set the voltage of insert-card. Please pay attention to the default setting.
-#define RK29SDK_SD_CARD_DETECT_PIN_NAME GPIO2A2_SDMMC0DETECTN_NAME
-#define RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO GPIO2L_GPIO2A2
-#define RK29SDK_SD_CARD_DETECT_IOMUX_FMUX GPIO2L_SDMMC0_DETECT_N
-
-#elif defined(CONFIG_ARCH_RK3066B)
-//refer to file /arch/arm/mach-rk30/include/mach/iomux-rk3066b.h
-//define reset-pin
-#define RK29SDK_SD_CARD_DETECT_N RK30_PIN3_PB0 //According to your own project to set the value of card-detect-pin.
-#define RK29SDK_SD_CARD_INSERT_LEVEL GPIO_LOW // set the voltage of insert-card. Please pay attention to the default setting.
-#define RK29SDK_SD_CARD_DETECT_PIN_NAME GPIO3B0_SDMMC0DETECTN_NAME
-#define RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO GPIO3B_GPIO3B0
-#define RK29SDK_SD_CARD_DETECT_IOMUX_FMUX GPIO3B_SDMMC0_DETECT_N
-
-#elif defined(CONFIG_ARCH_RK30)
-//refer to file /arch/arm/mach-rk30/include/mach/Iomux.h
-//define reset-pin
-#define RK29SDK_SD_CARD_DETECT_N RK30_PIN3_PB6 //According to your own project to set the value of card-detect-pin.
-#define RK29SDK_SD_CARD_INSERT_LEVEL GPIO_LOW // set the voltage of insert-card. Please pay attention to the default setting.
-#define RK29SDK_SD_CARD_DETECT_PIN_NAME GPIO3B6_SDMMC0DETECTN_NAME
-#define RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO GPIO3B_GPIO3B6
-#define RK29SDK_SD_CARD_DETECT_IOMUX_FMUX GPIO3B_SDMMC0_DETECT_N
-
-#elif defined(CONFIG_ARCH_RK2928)
-//refer to file ./arch/arm/mach-rk2928/include/mach/iomux.h
-//define reset-pin
- #if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- //use gpio-interupt to dectec card in RK2926. Please pay attention to modify the default setting.
- #define RK29SDK_SD_CARD_DETECT_N RK2928_PIN2_PA7 //According to your own project to set the value of card-detect-pin.
- #define RK29SDK_SD_CARD_INSERT_LEVEL GPIO_LOW // set the voltage of insert-card. Please pay attention to the default setting.
- #define RK29SDK_SD_CARD_DETECT_PIN_NAME GPIO2A7_NAND_DPS_EMMC_CLKOUT_NAME
- #define RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO GPIO2A_GPIO2A7
- #define RK29SDK_SD_CARD_DETECT_IOMUX_FMUX GPIO2A_EMMC_CLKOUT
- #else
- #define RK29SDK_SD_CARD_DETECT_N RK2928_PIN1_PC1 //According to your own project to set the value of card-detect-pin.
- #define RK29SDK_SD_CARD_INSERT_LEVEL GPIO_LOW // set the voltage of insert-card. Please pay attention to the default setting.
- #define RK29SDK_SD_CARD_DETECT_PIN_NAME GPIO1C1_MMC0_DETN_NAME
- #define RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO GPIO1C_GPIO1C1
- #define RK29SDK_SD_CARD_DETECT_IOMUX_FMUX GPIO1C_MMC0_DETN
- #endif
-#endif
-
-
-//
-// Define wifi module's power and reset gpio, and gpio sensitive level.
-// Please set the value according to your own project.
-//
-#if defined(CONFIG_ARCH_RK30) // refer to file /arch/arm/mach-rk30/include/mach/Iomux.h
- #define WIFI_HOST_WAKE RK30_PIN3_PD2
-
- #if defined(CONFIG_RK903) || defined(CONFIG_RK901) || defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU)
- //power
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- //reset
- #define RK30SDK_WIFI_GPIO_POWER_PIN_NAME GPIO3D0_SDMMC1PWREN_NAME
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO3D_GPIO3D0
-
- #elif defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319)
- //power
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_POWER_PIN_NAME GPIO3D0_SDMMC1PWREN_NAME
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO3D_GPIO3D0
- //reset
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_RESET_PIN_NAME GPIO3D1_SDMMC1BACKENDPWR_NAME
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FGPIO GPIO3D_GPIO3D1
-
- #elif defined(CONFIG_MT6620)
- #if !defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- #define USE_SDMMC_CONTROLLER_FOR_WIFI 1
-
- #if defined(CONFIG_MACH_RK30_PHONE_PAD) // define the gpio for MT6620 in RK30_PHONE_PAD project.
- #define COMBO_MODULE_MT6620_CDT 0 //- 1--use Cdtech chip; 0--unuse CDT chip
- //power, PMU_EN
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PC7
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_POWER_PIN_NAME GPIO3C7_SDMMC1WRITEPRT_NAME
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO3C_GPIO3C7
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FMUX GPIO3C_SDMMC1_WRITE_PRT
- //reset, DAIRST,SYSRST_B
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_RESET_PIN_NAME GPIO3D1_SDMMC1BACKENDPWR_NAME
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FGPIO GPIO3D_GPIO3D1
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FMUX GPIO3D_SDMMC1_BACKEND_PWR
- //VDDIO
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL RK30_PIN6_PB4
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_ENABLE_VALUE GPIO_HIGH
- //WIFI_INT_B
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN4_PD2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_PIN_NAME GPIO4D2_SMCDATA10_TRACEDATA10_NAME
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FGPIO GPIO4D_GPIO4D2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FMUX GPIO4D_SMC_DATA10
- //BGF_INT_B
- #define RK30SDK_WIFI_GPIO_BGF_INT_B RK30_PIN6_PA7
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_ENABLE_VALUE GPIO_HIGH
- //#define RK30SDK_WIFI_GPIO_BGF_INT_B_PIN_NAME GPIO3C6_SDMMC1DETECTN_NAME
- //#define RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FGPIO GPIO3C_GPIO3C6
- //#define RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FMUX GPIO3C_SDMMC1_DETECT_N
- //GPS_SYNC
- #define RK30SDK_WIFI_GPIO_GPS_SYNC RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_PIN_NAME GPIO3D0_SDMMC1PWREN_NAME
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FGPIO GPIO3D_GPIO3D0
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FMUX GPIO3D_SDMMC1_PWR_EN
-
- #elif defined(CONFIG_MACH_RK3066_M8000R) // define the gpio for MT6620 in CONFIG_MACH_RK3066_M8000R project.
- #define COMBO_MODULE_MT6620_CDT 1 //- 1--use Cdtech chip; 0--unuse CDT chip
- //power, PMU_EN
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PC7
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_POWER_PIN_NAME GPIO3C7_SDMMC1WRITEPRT_NAME
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO3C_GPIO3C7
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FMUX GPIO3C_SDMMC1_WRITE_PRT
- //reset, DAIRST,SYSRST_B
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_RESET_PIN_NAME GPIO3D1_SDMMC1BACKENDPWR_NAME
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FGPIO GPIO3D_GPIO3D1
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FMUX GPIO3D_SDMMC1_BACKEND_PWR
- //VDDIO
- #define RK30SDK_WIFI_GPIO_VCCIO_WL RK30_PIN0_PD2
- #define RK30SDK_WIFI_GPIO_VCCIO_WL_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_VCCIO_WL_PIN_NAME GPIO0D2_I2S22CHLRCKRX_SMCOEN_NAME
- #define RK30SDK_WIFI_GPIO_VCCIO_WL_IOMUX_FGPIO GPIO0D_GPIO0D2
- #define RK30SDK_WIFI_GPIO_VCCIO_WL_IOMUX_FMUX GPIO0D_I2S2_2CH_LRCK_RX
- //WIFI_INT_B
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_PIN_NAME GPIO3D2_SDMMC1INTN_NAME
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FGPIO GPIO3D_GPIO3D2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FMUX GPIO3D_SDMMC1_INT_N
- //BGF_INT_B
- #define RK30SDK_WIFI_GPIO_BGF_INT_B RK30_PIN6_PA7
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_ENABLE_VALUE GPIO_HIGH
- //#define RK30SDK_WIFI_GPIO_BGF_INT_B_PIN_NAME GPIO3C6_SDMMC1DETECTN_NAME
- //#define RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FGPIO GPIO3C_GPIO3C6
- // #define RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FMUX GPIO3C_SDMMC1_DETECT_N
- //GPS_SYNC
- #define RK30SDK_WIFI_GPIO_GPS_SYNC RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_PIN_NAME GPIO3D0_SDMMC1PWREN_NAME
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FGPIO GPIO3D_GPIO3D0
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FMUX GPIO3D_SDMMC1_PWR_EN
-
- #if COMBO_MODULE_MT6620_CDT
- //ANTSEL2
- //#define RK30SDK_WIFI_GPIO_ANTSEL2 RK30_PIN4_PD4
- //#define RK30SDK_WIFI_GPIO_ANTSEL2_ENABLE_VALUE GPIO_LOW //use 6620 in CDT chip, LOW--work; High--no work.
- //#define RK30SDK_WIFI_GPIO_ANTSEL2_PIN_NAME GPIO4D4_SMCDATA12_TRACEDATA12_NAME
- //#define RK30SDK_WIFI_GPIO_ANTSEL2_IOMUX_FGPIO GPIO4D_GPIO4D4
- //#define RK30SDK_WIFI_GPIO_ANTSEL2_IOMUX_FMUX GPIO4D_TRACE_DATA12
- //ANTSEL3
- //#define RK30SDK_WIFI_GPIO_ANTSEL3 RK30_PIN4_PD3
- //#define RK30SDK_WIFI_GPIO_ANTSEL3_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- //#define RK30SDK_WIFI_GPIO_ANTSEL3_PIN_NAME GPIO4D3_SMCDATA11_TRACEDATA11_NAME
- //#define RK30SDK_WIFI_GPIO_ANTSEL3_IOMUX_FGPIO GPIO4D_GPIO4D3
- //#define RK30SDK_WIFI_GPIO_ANTSEL3_IOMUX_FMUX GPIO4D_TRACE_DATA11
- //GPS_LAN
- //#define RK30SDK_WIFI_GPIO_GPS_LAN RK30_PIN4_PD6
- //#define RK30SDK_WIFI_GPIO_GPS_LAN_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- //#define RK30SDK_WIFI_GPIO_GPS_LAN_PIN_NAME GPIO4D6_SMCDATA14_TRACEDATA14_NAME
- //#define RK30SDK_WIFI_GPIO_GPS_LAN_IOMUX_FGPIO GPIO4D_GPIO4D6
- //#define RK30SDK_WIFI_GPIO_GPS_LAN_IOMUX_FMUX GPIO4D_TRACE_DATA14
- #endif // #if COMBO_MODULE_MT6620_CDT--#endif
-
- #elif defined(CONFIG_MACH_SKYWORTH_T10_SDK) // define the gpio for MT6620 in KYWORTH_T10 project.
- #define COMBO_MODULE_MT6620_CDT 0 //- 1--use Cdtech chip; 0--unuse CDT chip
- //power, PMU_EN
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_POWER_PIN_NAME GPIO3D0_SDMMC1PWREN_NAME
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO3D_GPIO3D0
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FMUX GPIO3D_SDMMC1_PWR_EN
- //reset, DAIRST,SYSRST_B
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_RESET_PIN_NAME GPIO3D1_SDMMC1BACKENDPWR_NAME
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FGPIO GPIO3D_GPIO3D1
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FMUX GPIO3D_SDMMC1_BACKEND_PWR
- //VDDIO
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL RK30_PIN6_PB4
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_ENABLE_VALUE GPIO_HIGH
- //WIFI_INT_B
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_PIN_NAME GPIO3D2_SDMMC1INTN_NAME
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FGPIO GPIO3D_GPIO3D2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FMUX GPIO3D_SDMMC1_INT_N
- //BGF_INT_B
- #define RK30SDK_WIFI_GPIO_BGF_INT_B RK30_PIN3_PC6
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_PIN_NAME GPIO3C6_SDMMC1DETECTN_NAME
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FGPIO GPIO3C_GPIO3C6
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FMUX GPIO3C_SDMMC1_DETECT_N
- //GPS_SYNC
- #define RK30SDK_WIFI_GPIO_GPS_SYNC RK30_PIN3_PC7
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_PIN_NAME GPIO3C7_SDMMC1WRITEPRT_NAME
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FGPIO GPIO3C_GPIO3C7
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FMUX GPIO3C_SDMMC1_WRITE_PRT
-
- #else //For exmpale, to define the gpio for MT6620 in RK30SDK project.
- #define COMBO_MODULE_MT6620_CDT 1 //- 1--use Cdtech chip; 0--unuse CDT chip
- //power
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_POWER_PIN_NAME GPIO3D0_SDMMC1PWREN_NAME
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO3D_GPIO3D0
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FMUX GPIO3D_SDMMC1_PWR_EN
- //reset
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_RESET_PIN_NAME GPIO3D1_SDMMC1BACKENDPWR_NAME
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FGPIO GPIO3D_GPIO3D1
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FMUX GPIO3D_SDMMC1_BACKEND_PWR
- //VDDIO
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL RK30_PIN0_PD2
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_ENABLE_VALUE GPIO_HIGH
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_PIN_NAME GPIO0D2_I2S22CHLRCKRX_SMCOEN_NAME
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_IOMUX_FGPIO GPIO0D_GPIO0D2
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_IOMUX_FMUX GPIO0D_I2S2_2CH_LRCK_RX
- //WIFI_INT_B
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_PIN_NAME GPIO3D2_SDMMC1INTN_NAME
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FGPIO GPIO3D_GPIO3D2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FMUX GPIO3D_SDMMC1_INT_N
- //BGF_INT_B
- #define RK30SDK_WIFI_GPIO_BGF_INT_B RK30_PIN3_PC6
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_PIN_NAME GPIO3C6_SDMMC1DETECTN_NAME
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FGPIO GPIO3C_GPIO3C6
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FMUX GPIO3C_SDMMC1_DETECT_N
- //GPS_SYNC
- #define RK30SDK_WIFI_GPIO_GPS_SYNC RK30_PIN3_PC7
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_PIN_NAME GPIO3C7_SDMMC1WRITEPRT_NAME
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FGPIO GPIO3C_GPIO3C7
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FMUX GPIO3C_SDMMC1_WRITE_PRT
-
- #if COMBO_MODULE_MT6620_CDT
- //ANTSEL2
- #define RK30SDK_WIFI_GPIO_ANTSEL2 RK30_PIN4_PD4
- #define RK30SDK_WIFI_GPIO_ANTSEL2_ENABLE_VALUE GPIO_LOW //use 6620 in CDT chip, LOW--work; High--no work.
- #define RK30SDK_WIFI_GPIO_ANTSEL2_PIN_NAME GPIO4D4_SMCDATA12_TRACEDATA12_NAME
- #define RK30SDK_WIFI_GPIO_ANTSEL2_IOMUX_FGPIO GPIO4D_GPIO4D4
- #define RK30SDK_WIFI_GPIO_ANTSEL2_IOMUX_FMUX GPIO4D_TRACE_DATA12
- //ANTSEL3
- #define RK30SDK_WIFI_GPIO_ANTSEL3 RK30_PIN4_PD3
- #define RK30SDK_WIFI_GPIO_ANTSEL3_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- #define RK30SDK_WIFI_GPIO_ANTSEL3_PIN_NAME GPIO4D3_SMCDATA11_TRACEDATA11_NAME
- #define RK30SDK_WIFI_GPIO_ANTSEL3_IOMUX_FGPIO GPIO4D_GPIO4D3
- #define RK30SDK_WIFI_GPIO_ANTSEL3_IOMUX_FMUX GPIO4D_TRACE_DATA11
- //GPS_LAN
- #define RK30SDK_WIFI_GPIO_GPS_LAN RK30_PIN4_PD6
- #define RK30SDK_WIFI_GPIO_GPS_LAN_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- #define RK30SDK_WIFI_GPIO_GPS_LAN_PIN_NAME GPIO4D6_SMCDATA14_TRACEDATA14_NAME
- #define RK30SDK_WIFI_GPIO_GPS_LAN_IOMUX_FGPIO GPIO4D_GPIO4D6
- //#define RK30SDK_WIFI_GPIO_GPS_LAN_IOMUX_FMUX GPIO4D_TRACE_DATA14
- #endif // #if COMBO_MODULE_MT6620_CDT--#endif
- #endif
- #endif// #endif --#if !defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- #endif
-#elif defined(CONFIG_ARCH_RK3066B)//refer to file /arch/arm/mach-rk30/include/mach/iomux-rk3066b.h
- #define WIFI_HOST_WAKE RK30_PIN3_PD2
-
- #if defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU)
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_POWER_PIN_NAME GPIO3D0_SDMMC1PWREN_NAME
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO3D_GPIO3D0
-
- #elif defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319) || defined(CONFIG_RK903) || defined(CONFIG_RK901)
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_POWER_PIN_NAME GPIO3D0_SDMMC1PWREN_NAME
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO3D_GPIO3D0
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN2_PA7
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_RESET_PIN_NAME GPIO2A7_LCDC1DATA7_SMCADDR11_NAME
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FGPIO GPIO2A_GPIO2A7
- #endif
-#elif defined(CONFIG_ARCH_RK2928) //refer to file ./arch/arm/mach-rk2928/include/mach/iomux.h
- #define WIFI_HOST_WAKE RK2928_PIN3_PC0
-
- #if defined(CONFIG_RK903) || defined(CONFIG_RK901) || defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319)
- #define RK30SDK_WIFI_GPIO_POWER_N RK2928_PIN0_PD6
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- //#define RK30SDK_WIFI_GPIO_POWER_PIN_NAME GPIO0D6_MMC1_PWREN_NAME
- //#define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO0D_GPIO0D6
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK2928_PIN3_PC2
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- //#define RK30SDK_WIFI_GPIO_RESET_PIN_NAME GPIO3C2_SDMMC1DATA1_NAME
- //#define RK30SDK_WIFI_GPIO_RESET_IOMUX_FGPIO GPIO3C_GPIO3C2
-
- #elif defined(CONFIG_RDA5990)
- #define RK30SDK_WIFI_GPIO_POWER_N RK2928_PIN0_PD6
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- //#define RK30SDK_WIFI_GPIO_POWER_PIN_NAME GPIO0D6_MMC1_PWREN_NAME
- //#define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO0D_GPIO0D6
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK2928_PIN3_PC2
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- //#define RK30SDK_WIFI_GPIO_RESET_PIN_NAME GPIO3C2_SDMMC1DATA1_NAME
- //#define RK30SDK_WIFI_GPIO_RESET_IOMUX_FGPIO GPIO3C_GPIO3C2
-
-
- #elif defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU) || defined(CONFIG_RT5370)
- #if defined(CONFIG_MACH_RK2926_V86)
- #define CONFIG_USB_WIFI_POWER_CONTROLED_BY_GPIO
- #define RK30SDK_WIFI_GPIO_POWER_N RK2928_PIN0_PD3
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_LOW
- #elif defined(CONFIG_MACH_RK2928_TR726)
- #define CONFIG_USB_WIFI_POWER_CONTROLED_BY_GPIO
- #define RK30SDK_WIFI_GPIO_POWER_N RK2928_PIN3_PD3
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_LOW
- #else
- #define RK30SDK_WIFI_GPIO_POWER_N RK2928_PIN0_PD6
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_LOW
- #endif
-
- #elif defined(CONFIG_MT5931) || defined(CONFIG_MT5931_MT6622)
- #define RK30SDK_WIFI_GPIO_POWER_N RK2928_PIN3_PD2
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK2928_PIN3_PD5
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
-
- #endif
-#endif
-
-
-//1. Part 2: to define the gpio for the SDMMC controller. Based on the chip datasheet.
-/*************************************************************************
-* define the gpio for SDMMC module on various platforms
-* Generally only system personnel will modify this part
-*************************************************************************/
-#if defined(CONFIG_ARCH_RK29)
-//refer to file /arch/arm/mach-rk29/include/mach/Iomux.h
-//define PowerEn-pin
-#define RK29SDK_SD_CARD_PWR_EN RK29_PIN5_PD5
-#define RK29SDK_SD_CARD_PWR_EN_LEVEL GPIO_LOW
-#define RK29SDK_SD_CARD_PWR_EN_PIN_NAME GPIO5D5_SDMMC0PWREN_NAME
-#define RK29SDK_SD_CARD_PWR_EN_IOMUX_FGPIO GPIO5H_GPIO5D5
-#define RK29SDK_SD_CARD_PWR_EN_IOMUX_FMUX GPIO5H_SDMMC0_PWR_EN
-
-#elif defined(CONFIG_ARCH_RK3066B)
-//refer to file /arch/arm/mach-rk30/include/mach/iomux-rk3066b.h
-//define PowerEn-pin
-#define RK29SDK_SD_CARD_PWR_EN RK30_PIN3_PA1
-#define RK29SDK_SD_CARD_PWR_EN_LEVEL GPIO_LOW
-#define RK29SDK_SD_CARD_PWR_EN_PIN_NAME GPIO3A1_SDMMC0PWREN_NAME
-#define RK29SDK_SD_CARD_PWR_EN_IOMUX_FGPIO GPIO3A_GPIO3A1
-#define RK29SDK_SD_CARD_PWR_EN_IOMUX_FMUX GPIO3A_SDMMC0PWREN
-
-#elif defined(CONFIG_ARCH_RK30)
-//refer to file /arch/arm/mach-rk30/include/mach/Iomux.h
-//define PowerEn-pin
-#define RK29SDK_SD_CARD_PWR_EN RK30_PIN3_PA7
-#define RK29SDK_SD_CARD_PWR_EN_LEVEL GPIO_LOW
-#define RK29SDK_SD_CARD_PWR_EN_PIN_NAME GPIO3A7_SDMMC0PWREN_NAME
-#define RK29SDK_SD_CARD_PWR_EN_IOMUX_FGPIO GPIO3A_GPIO3A7
-#define RK29SDK_SD_CARD_PWR_EN_IOMUX_FMUX GPIO3A_SDMMC0_PWR_EN
-
-#elif defined(CONFIG_ARCH_RK2928)
-//refer to file ./arch/arm/mach-rk2928/include/mach/iomux.h
-//define PowerEn-pin
-#define RK29SDK_SD_CARD_PWR_EN RK2928_PIN1_PB6
-#define RK29SDK_SD_CARD_PWR_EN_LEVEL GPIO_LOW
-#define RK29SDK_SD_CARD_PWR_EN_PIN_NAME GPIO1B6_MMC0_PWREN_NAME
-#define RK29SDK_SD_CARD_PWR_EN_IOMUX_FGPIO GPIO1B_GPIO1B6
-#define RK29SDK_SD_CARD_PWR_EN_IOMUX_FMUX GPIO1B_MMC0_PWREN
-
-#endif
-
-#if defined(CONFIG_ARCH_RK30)
-/*
-* define the gpio for sdmmc0
-*/
-struct rksdmmc_gpio_board rksdmmc0_gpio_init = {
-
- .clk_gpio = {
- .io = RK30_PIN3_PB0,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3B0_SDMMC0CLKOUT_NAME,
- .fgpio = GPIO3B_GPIO3B0,
- .fmux = GPIO3B_SDMMC0_CLKOUT,
- },
- },
-
- .cmd_gpio = {
- .io = RK30_PIN3_PB1,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3B1_SDMMC0CMD_NAME,
- .fgpio = GPIO3B_GPIO3B1,
- .fmux = GPIO3B_SDMMC0_CMD,
- },
- },
-
- .data0_gpio = {
- .io = RK30_PIN3_PB2,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3B2_SDMMC0DATA0_NAME,
- .fgpio = GPIO3B_GPIO3B2,
- .fmux = GPIO3B_SDMMC0_DATA0,
- },
- },
-
- .data1_gpio = {
- .io = RK30_PIN3_PB3,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3B3_SDMMC0DATA1_NAME,
- .fgpio = GPIO3B_GPIO3B3,
- .fmux = GPIO3B_SDMMC0_DATA1,
- },
- },
-
- .data2_gpio = {
- .io = RK30_PIN3_PB4,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3B4_SDMMC0DATA2_NAME,
- .fgpio = GPIO3B_GPIO3B4,
- .fmux = GPIO3B_SDMMC0_DATA2,
- },
- },
-
- .data3_gpio = {
- .io = RK30_PIN3_PB5,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3B5_SDMMC0DATA3_NAME,
- .fgpio = GPIO3B_GPIO3B5,
- .fmux = GPIO3B_SDMMC0_DATA3,
- },
- },
-
- .power_en_gpio = {
- .io = RK29SDK_SD_CARD_PWR_EN,
- .enable = RK29SDK_SD_CARD_PWR_EN_LEVEL,
- .iomux = {
- .name = RK29SDK_SD_CARD_PWR_EN_PIN_NAME,
- .fgpio = RK29SDK_SD_CARD_PWR_EN_IOMUX_FGPIO,
- .fmux = RK29SDK_SD_CARD_PWR_EN_IOMUX_FMUX,
- },
- },
-
- .detect_irq = {
- .io = RK29SDK_SD_CARD_DETECT_N,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- },
- },
-};
-
-
-/*
-* define the gpio for sdmmc1
-*/
-static struct rksdmmc_gpio_board rksdmmc1_gpio_init = {
-
- .clk_gpio = {
- .io = RK30_PIN3_PC5,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C5_SDMMC1CLKOUT_NAME,
- .fgpio = GPIO3C_GPIO3C5,
- .fmux = GPIO3B_SDMMC0_CLKOUT,
- },
- },
-
- .cmd_gpio = {
- .io = RK30_PIN3_PC0,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C0_SMMC1CMD_NAME,
- .fgpio = GPIO3C_GPIO3C0,
- .fmux = GPIO3B_SDMMC0_CMD,
- },
- },
-
- .data0_gpio = {
- .io = RK30_PIN3_PC1,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C1_SDMMC1DATA0_NAME,
- .fgpio = GPIO3C_GPIO3C1,
- .fmux = GPIO3B_SDMMC0_DATA0,
- },
- },
-
- .data1_gpio = {
- .io = RK30_PIN3_PC2,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C2_SDMMC1DATA1_NAME,
- .fgpio = GPIO3C_GPIO3C2,
- .fmux = GPIO3B_SDMMC0_DATA1,
- },
- },
-
- .data2_gpio = {
- .io = RK30_PIN3_PC3,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C3_SDMMC1DATA2_NAME,
- .fgpio = GPIO3C_GPIO3C3,
- .fmux = GPIO3B_SDMMC0_DATA2,
- },
- },
-
- .data3_gpio = {
- .io = RK30_PIN3_PC4,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C4_SDMMC1DATA3_NAME,
- .fgpio = GPIO3C_GPIO3C4,
- .fmux = GPIO3B_SDMMC0_DATA3,
- },
- },
-};
- // ---end -#if defined(CONFIG_ARCH_RK30)
-
-#elif defined(CONFIG_ARCH_RK3066B)
-
-/*
-* define the gpio for sdmmc0
-*/
-static struct rksdmmc_gpio_board rksdmmc0_gpio_init = {
-
- .clk_gpio = {
- .io = RK30_PIN3_PB0,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3A2_SDMMC0CLKOUT_NAME,
- .fgpio = GPIO3A_GPIO3A2,
- .fmux = GPIO3A_SDMMC0CLKOUT,
- },
- },
-
- .cmd_gpio = {
- .io = RK30_PIN3_PB1,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3A3_SDMMC0CMD_NAME,
- .fgpio = GPIO3A_GPIO3A3,
- .fmux = GPIO3A_SDMMC0CMD,
- },
- },
-
- .data0_gpio = {
- .io = RK30_PIN3_PB2,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3A4_SDMMC0DATA0_NAME,
- .fgpio = GPIO3A_GPIO3A4,
- .fmux = GPIO3A_SDMMC0DATA0,
- },
- },
-
- .data1_gpio = {
- .io = RK30_PIN3_PB3,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3A5_SDMMC0DATA1_NAME,
- .fgpio = GPIO3A_GPIO3A5,
- .fmux = GPIO3A_SDMMC0DATA1,
- },
- },
-
- .data2_gpio = {
- .io = RK30_PIN3_PB4,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3A6_SDMMC0DATA2_NAME,
- .fgpio = GPIO3A_GPIO3A6,
- .fmux = GPIO3A_SDMMC0DATA2,
- },
- },
-
- .data3_gpio = {
- .io = RK30_PIN3_PB5,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3A7_SDMMC0DATA3_NAME,
- .fgpio = GPIO3A_GPIO3A7,
- .fmux = GPIO3A_SDMMC0DATA3,
- },
- },
-
- .power_en_gpio = {
- .io = RK29SDK_SD_CARD_PWR_EN,
- .enable = RK29SDK_SD_CARD_PWR_EN_LEVEL,
- .iomux = {
- .name = RK29SDK_SD_CARD_PWR_EN_PIN_NAME,
- .fgpio = RK29SDK_SD_CARD_PWR_EN_IOMUX_FGPIO,
- .fmux = RK29SDK_SD_CARD_PWR_EN_IOMUX_FMUX,
- },
- },
-
- .detect_irq = {
- .io = RK29SDK_SD_CARD_DETECT_N,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- },
- },
-};
-
-
-/*
-* define the gpio for sdmmc1
-*/
-static struct rksdmmc_gpio_board rksdmmc1_gpio_init = {
-
- .clk_gpio = {
- .io = RK30_PIN3_PC5,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C5_SDMMC1CLKOUT_RMIICLKOUT_RMIICLKIN_NAME,
- .fgpio = GPIO3C_GPIO3C5,
- .fmux = GPIO3C_SDMMC1CLKOUT,
- },
- },
-
- .cmd_gpio = {
- .io = RK30_PIN3_PC0,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C0_SDMMC1CMD_RMIITXEN_NAME,
- .fgpio = GPIO3C_GPIO3C0,
- .fmux = GPIO3C_SDMMC1CMD,
- },
- },
-
- .data0_gpio = {
- .io = RK30_PIN3_PC1,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C1_SDMMC1DATA0_RMIITXD1_NAME,
- .fgpio = GPIO3C_GPIO3C1,
- .fmux = GPIO3C_SDMMC1DATA0,
- },
- },
-
- .data1_gpio = {
- .io = RK30_PIN3_PC2,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C2_SDMMC1DATA1_RMIITXD0_NAME,
- .fgpio = GPIO3C_GPIO3C2,
- .fmux = GPIO3C_SDMMC1DATA1,
- },
- },
-
- .data2_gpio = {
- .io = RK30_PIN3_PC3,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C3_SDMMC1DATA2_RMIIRXD0_NAME,
- .fgpio = GPIO3C_GPIO3C3,
- .fmux = GPIO3C_SDMMC1DATA2,
- },
- },
-
- .data3_gpio = {
- .io = RK30_PIN3_PC4,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C4_SDMMC1DATA3_RMIIRXD1_NAME,
- .fgpio = GPIO3C_GPIO3C4,
- .fmux = GPIO3C_SDMMC1DATA3,
- },
- },
-};
-// ---end -#if defined(CONFIG_ARCH_RK3066B)
-
-#elif defined(CONFIG_ARCH_RK2928)
-/*
-* define the gpio for sdmmc0
-*/
-static struct rksdmmc_gpio_board rksdmmc0_gpio_init = {
-
- .clk_gpio = {
- .io = RK2928_PIN1_PC0,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO1C0_MMC0_CLKOUT_NAME,
- .fgpio = GPIO1C_GPIO1C0,
- .fmux = GPIO1C_MMC0_CLKOUT,
- },
- },
-
- .cmd_gpio = {
- .io = RK2928_PIN1_PC7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO1B7_MMC0_CMD_NAME,
- .fgpio = GPIO1B_GPIO1B7,
- .fmux = GPIO1B_MMC0_CMD,
- },
- },
-
- .data0_gpio = {
- .io = RK2928_PIN1_PC2,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO1C2_MMC0_D0_NAME,
- .fgpio = GPIO1C_GPIO1C2,
- .fmux = GPIO1C_MMC0_D0,
- },
- },
-
- .data1_gpio = {
- .io = RK2928_PIN1_PC3,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO1C3_MMC0_D1_NAME,
- .fgpio = GPIO1C_GPIO1C3,
- .fmux = GPIO1C_MMC0_D1,
- },
- },
-
- .data2_gpio = {
- .io = RK2928_PIN1_PC4,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO1C4_MMC0_D2_NAME,
- .fgpio = GPIO1C_GPIO1C4,
- .fmux = GPIO1C_MMC0_D2,
- },
- },
-
- .data3_gpio = {
- .io = RK2928_PIN1_PC5,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO1C5_MMC0_D3_NAME,
- .fgpio = GPIO1C_GPIO1C5,
- .fmux = GPIO1C_MMC0_D3,
- },
- },
-
- .power_en_gpio = {
- .io = RK29SDK_SD_CARD_PWR_EN,
- .enable = RK29SDK_SD_CARD_PWR_EN_LEVEL,
- .iomux = {
- .name = RK29SDK_SD_CARD_PWR_EN_PIN_NAME,
- .fgpio = RK29SDK_SD_CARD_PWR_EN_IOMUX_FGPIO,
- .fmux = RK29SDK_SD_CARD_PWR_EN_IOMUX_FMUX,
- },
- },
-
- .detect_irq = {
- .io = RK29SDK_SD_CARD_DETECT_N,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- },
- },
-
-};
-
-
-/*
-* define the gpio for sdmmc1
-*/
-static struct rksdmmc_gpio_board rksdmmc1_gpio_init = {
-
- .clk_gpio = {
- .io = RK2928_PIN0_PB1,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO0B1_MMC1_CLKOUT_NAME,
- .fgpio = GPIO0B_GPIO0B1,
- .fmux = GPIO0B_MMC1_CLKOUT,
- },
- },
-
- .cmd_gpio = {
- .io = RK2928_PIN0_PB0,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO0B0_MMC1_CMD_NAME,
- .fgpio = GPIO0B_GPIO0B0,
- .fmux = GPIO0B_MMC1_CMD,
- },
- },
-
- .data0_gpio = {
- .io = RK2928_PIN0_PB3,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO0B3_MMC1_D0_NAME,
- .fgpio = GPIO0B_GPIO0B3,
- .fmux = GPIO0B_MMC1_D0,
- },
- },
-
- .data1_gpio = {
- .io = RK2928_PIN0_PB4,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO0B4_MMC1_D1_NAME,
- .fgpio = GPIO0B_GPIO0B4,
- .fmux = GPIO0B_MMC1_D1,
- },
- },
-
- .data2_gpio = {
- .io = RK2928_PIN0_PB5,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO0B5_MMC1_D2_NAME,
- .fgpio = GPIO0B_GPIO0B5,
- .fmux = GPIO0B_MMC1_D2,
- },
- },
-
- .data3_gpio = {
- .io = RK2928_PIN0_PB6,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO0B6_MMC1_D3_NAME,
- .fgpio = GPIO0B_GPIO0B6,
- .fmux = GPIO0B_MMC1_D3,
- },
- },
-
-
-};
-// ---end -#if defined(CONFIG_ARCH_RK2928)
-#endif
-
-
-
-//1.Part 3: The various operations of the SDMMC-SDIO module
-/*************************************************************************
-* define the varaious operations for SDMMC module
-* Generally only the author of SDMMC module will modify this section.
-*************************************************************************/
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
-//static void rk29_sdmmc_gpio_open(int device_id, int on)
-void rk29_sdmmc_gpio_open(int device_id, int on)
-{
- switch(device_id)
- {
- case 0://mmc0
- {
- #ifdef CONFIG_SDMMC0_RK29
- if(on)
- {
- gpio_direction_output(rksdmmc0_gpio_init.clk_gpio.io, GPIO_HIGH);//set mmc0-clk to high
- gpio_direction_output(rksdmmc0_gpio_init.cmd_gpio.io, GPIO_HIGH);// set mmc0-cmd to high.
- gpio_direction_output(rksdmmc0_gpio_init.data0_gpio.io,GPIO_HIGH);//set mmc0-data0 to high.
- gpio_direction_output(rksdmmc0_gpio_init.data1_gpio.io,GPIO_HIGH);//set mmc0-data1 to high.
- gpio_direction_output(rksdmmc0_gpio_init.data2_gpio.io,GPIO_HIGH);//set mmc0-data2 to high.
- gpio_direction_output(rksdmmc0_gpio_init.data3_gpio.io,GPIO_HIGH);//set mmc0-data3 to high.
-
- mdelay(30);
- }
- else
- {
- rk30_mux_api_set(rksdmmc0_gpio_init.clk_gpio.iomux.name, rksdmmc0_gpio_init.clk_gpio.iomux.fgpio);
- gpio_request(rksdmmc0_gpio_init.clk_gpio.io, "mmc0-clk");
- gpio_direction_output(rksdmmc0_gpio_init.clk_gpio.io,GPIO_LOW);//set mmc0-clk to low.
-
- rk30_mux_api_set(rksdmmc0_gpio_init.cmd_gpio.iomux.name, rksdmmc0_gpio_init.cmd_gpio.iomux.fgpio);
- gpio_request(rksdmmc0_gpio_init.cmd_gpio.io, "mmc0-cmd");
- gpio_direction_output(rksdmmc0_gpio_init.cmd_gpio.io,GPIO_LOW);//set mmc0-cmd to low.
-
- rk30_mux_api_set(rksdmmc0_gpio_init.data0_gpio.iomux.name, rksdmmc0_gpio_init.data0_gpio.iomux.fgpio);
- gpio_request(rksdmmc0_gpio_init.data0_gpio.io, "mmc0-data0");
- gpio_direction_output(rksdmmc0_gpio_init.data0_gpio.io,GPIO_LOW);//set mmc0-data0 to low.
-
- rk30_mux_api_set(rksdmmc0_gpio_init.data1_gpio.iomux.name, rksdmmc0_gpio_init.data1_gpio.iomux.fgpio);
- gpio_request(rksdmmc0_gpio_init.data1_gpio.io, "mmc0-data1");
- gpio_direction_output(rksdmmc0_gpio_init.data1_gpio.io,GPIO_LOW);//set mmc0-data1 to low.
-
- rk30_mux_api_set(rksdmmc0_gpio_init.data2_gpio.iomux.name, rksdmmc0_gpio_init.data2_gpio.iomux.fgpio);
- gpio_request(rksdmmc0_gpio_init.data2_gpio.io, "mmc0-data2");
- gpio_direction_output(rksdmmc0_gpio_init.data2_gpio.io,GPIO_LOW);//set mmc0-data2 to low.
-
- rk30_mux_api_set(rksdmmc0_gpio_init.data3_gpio.iomux.name, rksdmmc0_gpio_init.data3_gpio.iomux.fgpio);
- gpio_request(rksdmmc0_gpio_init.data3_gpio.io, "mmc0-data3");
- gpio_direction_output(rksdmmc0_gpio_init.data3_gpio.io,GPIO_LOW);//set mmc0-data3 to low.
-
- mdelay(30);
- }
- #endif
- }
- break;
-
- case 1://mmc1
- {
- #ifdef CONFIG_SDMMC1_RK29
- if(on)
- {
- gpio_direction_output(rksdmmc1_gpio_init.clk_gpio.io,GPIO_HIGH);//set mmc1-clk to high
- gpio_direction_output(rksdmmc1_gpio_init.cmd_gpio.io,GPIO_HIGH);//set mmc1-cmd to high.
- gpio_direction_output(rksdmmc1_gpio_init.data0_gpio.io,GPIO_HIGH);//set mmc1-data0 to high.
- gpio_direction_output(rksdmmc1_gpio_init.data1_gpio.io,GPIO_HIGH);//set mmc1-data1 to high.
- gpio_direction_output(rksdmmc1_gpio_init.data2_gpio.io,GPIO_HIGH);//set mmc1-data2 to high.
- gpio_direction_output(rksdmmc1_gpio_init.data3_gpio.io,GPIO_HIGH);//set mmc1-data3 to high.
- mdelay(100);
- }
- else
- {
- rk30_mux_api_set(rksdmmc1_gpio_init.clk_gpio.iomux.name, rksdmmc1_gpio_init.clk_gpio.iomux.fgpio);
- gpio_request(rksdmmc1_gpio_init.clk_gpio.io, "mmc1-clk");
- gpio_direction_output(rksdmmc1_gpio_init.clk_gpio.io,GPIO_LOW);//set mmc1-clk to low.
-
- rk30_mux_api_set(rksdmmc1_gpio_init.cmd_gpio.iomux.name, rksdmmc1_gpio_init.cmd_gpio.iomux.fgpio);
- gpio_request(rksdmmc1_gpio_init.cmd_gpio.io, "mmc1-cmd");
- gpio_direction_output(rksdmmc1_gpio_init.cmd_gpio.io,GPIO_LOW);//set mmc1-cmd to low.
-
- rk30_mux_api_set(rksdmmc1_gpio_init.data0_gpio.iomux.name, rksdmmc1_gpio_init.data0_gpio.iomux.fgpio);
- gpio_request(rksdmmc1_gpio_init.data0_gpio.io, "mmc1-data0");
- gpio_direction_output(rksdmmc1_gpio_init.data0_gpio.io,GPIO_LOW);//set mmc1-data0 to low.
-
- rk29_mux_api_set(rksdmmc1_gpio_init.data1_gpio.iomux.name, rksdmmc1_gpio_init.data1_gpio.iomux.fgpio);
- gpio_request(rksdmmc1_gpio_init.data1_gpio.io, "mmc1-data1");
- gpio_direction_output(rksdmmc1_gpio_init.data1_gpio.io,GPIO_LOW);//set mmc1-data1 to low.
-
- rk29_mux_api_set(rksdmmc1_gpio_init.data2_gpio.iomux.name, rksdmmc1_gpio_init.data2_gpio.iomux.fgpio);
- gpio_request(rksdmmc1_gpio_init.data2_gpio.io, "mmc1-data2");
- gpio_direction_output(rksdmmc1_gpio_init.data2_gpio.io,GPIO_LOW);//set mmc1-data2 to low.
-
- rk29_mux_api_set(rksdmmc1_gpio_init.data3_gpio.iomux.name, rksdmmc1_gpio_init.data3_gpio.iomux.fgpio);
- gpio_request(rksdmmc1_gpio_init.data3_gpio.io, "mmc1-data3");
- gpio_direction_output(rksdmmc1_gpio_init.data3_gpio.io,GPIO_LOW);//set mmc1-data3 to low.
-
- mdelay(100);
- }
- #endif
- }
- break;
-
- case 2: //mmc2
- break;
-
- default:
- break;
- }
-}
-
-static void rk29_sdmmc_set_iomux_mmc0(unsigned int bus_width)
-{
- switch (bus_width)
- {
-
- case 1://SDMMC_CTYPE_4BIT:
- {
- rk30_mux_api_set(rksdmmc0_gpio_init.data1_gpio.iomux.name, rksdmmc0_gpio_init.data1_gpio.iomux.fmux);
- rk30_mux_api_set(rksdmmc0_gpio_init.data2_gpio.iomux.name, rksdmmc0_gpio_init.data2_gpio.iomux.fmux);
- rk30_mux_api_set(rksdmmc0_gpio_init.data3_gpio.iomux.name, rksdmmc0_gpio_init.data3_gpio.iomux.fmux);
- }
- break;
-
- case 0x10000://SDMMC_CTYPE_8BIT:
- break;
- case 0xFFFF: //gpio_reset
- {
- rk30_mux_api_set(rksdmmc0_gpio_init.power_en_gpio.iomux.name, rksdmmc0_gpio_init.power_en_gpio.iomux.fgpio);
- gpio_request(rksdmmc0_gpio_init.power_en_gpio.io,"sdmmc-power");
- gpio_direction_output(rksdmmc0_gpio_init.power_en_gpio.io, !(rksdmmc0_gpio_init.power_en_gpio.enable)); //power-off
-
- #if 0 //replace the power control into rk29_sdmmc_set_ios(); modifyed by xbw at 2012-08-12
- rk29_sdmmc_gpio_open(0, 0);
-
- gpio_direction_output(rksdmmc0_gpio_init.power_en_gpio.io, rksdmmc0_gpio_init.power_en_gpio.enable); //power-on
-
- rk29_sdmmc_gpio_open(0, 1);
- #endif
- }
- break;
-
- default: //case 0://SDMMC_CTYPE_1BIT:
- {
- rk30_mux_api_set(rksdmmc0_gpio_init.cmd_gpio.iomux.name, rksdmmc0_gpio_init.cmd_gpio.iomux.fmux);
- rk30_mux_api_set(rksdmmc0_gpio_init.clk_gpio.iomux.name, rksdmmc0_gpio_init.clk_gpio.iomux.fmux);
- rk30_mux_api_set(rksdmmc0_gpio_init.data0_gpio.iomux.name, rksdmmc0_gpio_init.data0_gpio.iomux.fmux);
-
- rk30_mux_api_set(rksdmmc0_gpio_init.data1_gpio.iomux.name, rksdmmc0_gpio_init.data1_gpio.iomux.fgpio);
- gpio_request(rksdmmc0_gpio_init.data1_gpio.io, "mmc0-data1");
- gpio_direction_output(rksdmmc0_gpio_init.data1_gpio.io,GPIO_HIGH);//set mmc0-data1 to high.
-
- rk30_mux_api_set(rksdmmc0_gpio_init.data2_gpio.iomux.name, rksdmmc0_gpio_init.data2_gpio.iomux.fgpio);
- gpio_request(rksdmmc0_gpio_init.data2_gpio.io, "mmc0-data2");
- gpio_direction_output(rksdmmc0_gpio_init.data2_gpio.io,GPIO_HIGH);//set mmc0-data2 to high.
-
- rk30_mux_api_set(rksdmmc0_gpio_init.data3_gpio.iomux.name, rksdmmc0_gpio_init.data3_gpio.iomux.fgpio);
- gpio_request(rksdmmc0_gpio_init.data3_gpio.io, "mmc0-data3");
- gpio_direction_output(rksdmmc0_gpio_init.data3_gpio.io,GPIO_HIGH);//set mmc0-data3 to high.
- }
- break;
- }
-}
-
-static void rk29_sdmmc_set_iomux_mmc1(unsigned int bus_width)
-{
- rk30_mux_api_set(rksdmmc1_gpio_init.cmd_gpio.iomux.name, rksdmmc1_gpio_init.cmd_gpio.iomux.fmux);
- rk30_mux_api_set(rksdmmc1_gpio_init.clk_gpio.iomux.name, rksdmmc1_gpio_init.clk_gpio.iomux.fmux);
- rk30_mux_api_set(rksdmmc1_gpio_init.data0_gpio.iomux.name, rksdmmc1_gpio_init.data0_gpio.iomux.fmux);
- rk30_mux_api_set(rksdmmc1_gpio_init.data1_gpio.iomux.name, rksdmmc1_gpio_init.data1_gpio.iomux.fmux);
- rk30_mux_api_set(rksdmmc1_gpio_init.data2_gpio.iomux.name, rksdmmc1_gpio_init.data2_gpio.iomux.fmux);
- rk30_mux_api_set(rksdmmc1_gpio_init.data3_gpio.iomux.name, rksdmmc1_gpio_init.data3_gpio.iomux.fmux);
-}
-
-static void rk29_sdmmc_set_iomux_mmc2(unsigned int bus_width)
-{
- ;//
-}
-
-static void rk29_sdmmc_set_iomux(int device_id, unsigned int bus_width)
-{
- switch(device_id)
- {
- case 0:
- #ifdef CONFIG_SDMMC0_RK29
- rk29_sdmmc_set_iomux_mmc0(bus_width);
- #endif
- break;
- case 1:
- #ifdef CONFIG_SDMMC1_RK29
- rk29_sdmmc_set_iomux_mmc1(bus_width);
- #endif
- break;
- case 2:
- rk29_sdmmc_set_iomux_mmc2(bus_width);
- break;
- default:
- break;
- }
-}
-
-#endif
-
-
-
-//1.Part 4: The various operations of the Wifi-BT module
-/*************************************************************************
-* define the varaious operations for Wifi module
-* Generally only the author of Wifi module will modify this section.
-*************************************************************************/
-
-static int rk29sdk_wifi_status(struct device *dev);
-static int rk29sdk_wifi_status_register(void (*callback)(int card_presend, void *dev_id), void *dev_id);
-
-#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
-static int rk29sdk_wifi_mmc0_status(struct device *dev);
-static int rk29sdk_wifi_mmc0_status_register(void (*callback)(int card_presend, void *dev_id), void *dev_id);
-static int rk29sdk_wifi_mmc0_cd = 0; /* wifi virtual 'card detect' status */
-static void (*wifi_mmc0_status_cb)(int card_present, void *dev_id);
-static void *wifi_mmc0_status_cb_devid;
-
-int rk29sdk_wifi_power_state = 0;
-int rk29sdk_bt_power_state = 0;
-
- #if defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- /////////////////////////////////////////////////////////////////////////////////////
- // set the gpio to develop wifi EVB if you select the macro of CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD
- #define USE_SDMMC_CONTROLLER_FOR_WIFI 0
- #define COMBO_MODULE_MT6620_CDT 0 //- 1--use Cdtech chip; 0--unuse CDT chip
- //power
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_POWER_PIN_NAME GPIO3D0_SDMMC1PWREN_NAME
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO3D_GPIO3D0
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FMUX GPIO3D_SDMMC1_PWR_EN
- //reset
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_RESET_PIN_NAME GPIO3D1_SDMMC1BACKENDPWR_NAME
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FGPIO GPIO3D_GPIO3D1
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FMUX GPIO3D_SDMMC1_BACKEND_PWR
- //VDDIO
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL RK30_PIN2_PC5
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_ENABLE_VALUE GPIO_HIGH
- //WIFI_INT_B
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_PIN_NAME GPIO3D2_SDMMC1INTN_NAME
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FGPIO GPIO3D_GPIO3D2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FMUX GPIO3D_SDMMC1_INT_N
- //BGF_INT_B
- #define RK30SDK_WIFI_GPIO_BGF_INT_B RK30_PIN3_PC6
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_PIN_NAME GPIO3C6_SDMMC1DETECTN_NAME
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FGPIO GPIO3C_GPIO3C6
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FMUX GPIO3C_SDMMC1_DETECT_N
- //GPS_SYNC
- #define RK30SDK_WIFI_GPIO_GPS_SYNC RK30_PIN3_PC7
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_PIN_NAME GPIO3C7_SDMMC1WRITEPRT_NAME
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FGPIO GPIO3C_GPIO3C7
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FMUX GPIO3C_SDMMC1_WRITE_PRT
-
- #if COMBO_MODULE_MT6620_CDT
- //ANTSEL2
- #define RK30SDK_WIFI_GPIO_ANTSEL2 RK30_PIN4_PD4
- #define RK30SDK_WIFI_GPIO_ANTSEL2_ENABLE_VALUE GPIO_LOW //use 6620 in CDT chip, LOW--work; High--no work.
- #define RK30SDK_WIFI_GPIO_ANTSEL2_PIN_NAME GPIO4D4_SMCDATA12_TRACEDATA12_NAME
- #define RK30SDK_WIFI_GPIO_ANTSEL2_IOMUX_FGPIO GPIO4D_GPIO4D4
- #define RK30SDK_WIFI_GPIO_ANTSEL2_IOMUX_FMUX GPIO4D_TRACE_DATA12
- //ANTSEL3
- #define RK30SDK_WIFI_GPIO_ANTSEL3 RK30_PIN4_PD3
- #define RK30SDK_WIFI_GPIO_ANTSEL3_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- #define RK30SDK_WIFI_GPIO_ANTSEL3_PIN_NAME GPIO4D3_SMCDATA11_TRACEDATA11_NAME
- #define RK30SDK_WIFI_GPIO_ANTSEL3_IOMUX_FGPIO GPIO4D_GPIO4D3
- #define RK30SDK_WIFI_GPIO_ANTSEL3_IOMUX_FMUX GPIO4D_TRACE_DATA11
- //GPS_LAN
- #define RK30SDK_WIFI_GPIO_GPS_LAN RK30_PIN4_PD6
- #define RK30SDK_WIFI_GPIO_GPS_LAN_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- #define RK30SDK_WIFI_GPIO_GPS_LAN_PIN_NAME GPIO4D6_SMCDATA14_TRACEDATA14_NAME
- #define RK30SDK_WIFI_GPIO_GPS_LAN_IOMUX_FGPIO GPIO4D_GPIO4D6
- #define RK30SDK_WIFI_GPIO_GPS_LAN_IOMUX_FMUX GPIO4D_TRACE_DATA14
- #endif // #if COMBO_MODULE_MT6620_CDT--#endif
-
- #endif // #if defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)---#endif
-#endif // #if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) ---#endif
-
-static int rk29sdk_wifi_cd = 0; /* wifi virtual 'card detect' status */
-static void (*wifi_status_cb)(int card_present, void *dev_id);
-static void *wifi_status_cb_devid;
-
-#if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
-#define RK29SDK_WIFI_SDIO_CARD_INT RK30SDK_WIFI_GPIO_WIFI_INT_B
-#endif
-
-struct rksdmmc_gpio_wifi_moudle rk_platform_wifi_gpio = {
- .power_n = {
- .io = RK30SDK_WIFI_GPIO_POWER_N,
- .enable = RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE,
- #ifdef RK30SDK_WIFI_GPIO_POWER_PIN_NAME
- .iomux = {
- .name = RK30SDK_WIFI_GPIO_POWER_PIN_NAME,
- .fgpio = RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO,
- #ifdef RK30SDK_WIFI_GPIO_POWER_IOMUX_FMUX
- .fmux = RK30SDK_WIFI_GPIO_POWER_IOMUX_FMUX,
- #endif
- },
- #endif
- },
-
- #ifdef RK30SDK_WIFI_GPIO_RESET_N
- .reset_n = {
- .io = RK30SDK_WIFI_GPIO_RESET_N,
- .enable = RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE,
- #ifdef RK30SDK_WIFI_GPIO_RESET_PIN_NAME
- .iomux = {
- .name = RK30SDK_WIFI_GPIO_RESET_PIN_NAME,
- .fgpio = RK30SDK_WIFI_GPIO_RESET_IOMUX_FGPIO,
- #ifdef RK30SDK_WIFI_GPIO_RESET_IOMUX_FMUX
- .fmux = RK30SDK_WIFI_GPIO_RESET_IOMUX_FMUX,
- #endif
- },
- #endif
- },
- #endif
-
- #ifdef RK30SDK_WIFI_GPIO_WIFI_INT_B
- .wifi_int_b = {
- .io = RK30SDK_WIFI_GPIO_WIFI_INT_B,
- .enable = RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE,
- #ifdef RK30SDK_WIFI_GPIO_WIFI_INT_B_PIN_NAME
- .iomux = {
- .name = RK30SDK_WIFI_GPIO_WIFI_INT_B_PIN_NAME,
- .fgpio = RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FGPIO,
- #ifdef RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FMUX
- .fmux = RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FMUX,
- #endif
- },
- #endif
- },
- #endif
-
- #ifdef RK30SDK_WIFI_GPIO_VCCIO_WL
- .vddio = {
- .io = RK30SDK_WIFI_GPIO_VCCIO_WL,
- .enable = RK30SDK_WIFI_GPIO_VCCIO_WL_ENABLE_VALUE,
- #ifdef RK30SDK_WIFI_GPIO_VCCIO_WL_PIN_NAME
- .iomux = {
- .name = RK30SDK_WIFI_GPIO_VCCIO_WL_PIN_NAME,
- .fgpio = RK30SDK_WIFI_GPIO_VCCIO_WL_IOMUX_FGPIO,
- #ifdef RK30SDK_WIFI_GPIO_VCCIO_WL_IOMUX_FMUX
- .fmux = RK30SDK_WIFI_GPIO_VCCIO_WL_IOMUX_FMUX,
- #endif
- },
- #endif
- },
- #endif
-
- #ifdef RK30SDK_WIFI_GPIO_BGF_INT_B
- .bgf_int_b = {
- .io = RK30SDK_WIFI_GPIO_BGF_INT_B,
- .enable = RK30SDK_WIFI_GPIO_BGF_INT_B_ENABLE_VALUE,
- #ifdef RK30SDK_WIFI_GPIO_BGF_INT_B_PIN_NAME
- .iomux = {
- .name = RK30SDK_WIFI_GPIO_BGF_INT_B_PIN_NAME,
- .fgpio = RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FGPIO,
- #ifdef RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FMUX
- .fmux = RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FMUX,
- #endif
- },
- #endif
- },
- #endif
-
- #ifdef RK30SDK_WIFI_GPIO_GPS_SYNC
- .gps_sync = {
- .io = RK30SDK_WIFI_GPIO_GPS_SYNC,
- .enable = RK30SDK_WIFI_GPIO_GPS_SYNC_ENABLE_VALUE,
- #ifdef RK30SDK_WIFI_GPIO_GPS_SYNC_PIN_NAME
- .iomux = {
- .name = RK30SDK_WIFI_GPIO_GPS_SYNC_PIN_NAME,
- .fgpio = RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FGPIO,
- #ifdef RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FMUX
- .fmux = RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FMUX,
- #endif
- },
- #endif
- },
- #endif
-
-#if COMBO_MODULE_MT6620_CDT
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL2
- .ANTSEL2 = {
- .io = RK30SDK_WIFI_GPIO_ANTSEL2,
- .enable = RK30SDK_WIFI_GPIO_ANTSEL2_ENABLE_VALUE,
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL2_PIN_NAME
- .iomux = {
- .name = RK30SDK_WIFI_GPIO_ANTSEL2_PIN_NAME,
- .fgpio = RK30SDK_WIFI_GPIO_ANTSEL2_IOMUX_FGPIO,
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL2_IOMUX_FMUX
- .fmux = RK30SDK_WIFI_GPIO_ANTSEL2_IOMUX_FMUX,
- #endif
- },
- #endif
- },
- #endif
-
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL3
- .ANTSEL3 = {
- .io = RK30SDK_WIFI_GPIO_ANTSEL3,
- .enable = RK30SDK_WIFI_GPIO_ANTSEL3_ENABLE_VALUE,
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL3_PIN_NAME
- .iomux = {
- .name = RK30SDK_WIFI_GPIO_ANTSEL3_PIN_NAME,
- .fgpio = RK30SDK_WIFI_GPIO_ANTSEL3_IOMUX_FGPIO,
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL3_IOMUX_FMUX
- .fmux = RK30SDK_WIFI_GPIO_ANTSEL3_IOMUX_FMUX,
- #endif
- },
- #endif
- },
- #endif
-
- #ifdef RK30SDK_WIFI_GPIO_GPS_LAN
- .GPS_LAN = {
- .io = RK30SDK_WIFI_GPIO_GPS_LAN,
- .enable = RK30SDK_WIFI_GPIO_GPS_LAN_ENABLE_VALUE,
- #ifdef RK30SDK_WIFI_GPIO_GPS_LAN_PIN_NAME
- .iomux = {
- .name = RK30SDK_WIFI_GPIO_GPS_LAN_PIN_NAME,
- .fgpio = RK30SDK_WIFI_GPIO_GPS_LAN_IOMUX_FGPIO,
- #ifdef RK30SDK_WIFI_GPIO_GPS_LAN_IOMUX_FMUX
- .fmux = RK30SDK_WIFI_GPIO_GPS_LAN_IOMUX_FMUX,
- #endif
- },
- #endif
- },
- #endif
-#endif // #if COMBO_MODULE_MT6620_CDT--#endif
-};
-
-
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
-#define PREALLOC_WLAN_SEC_NUM 4
-#define PREALLOC_WLAN_BUF_NUM 160
-#define PREALLOC_WLAN_SECTION_HEADER 24
-
-#define WLAN_SECTION_SIZE_0 (PREALLOC_WLAN_BUF_NUM * 128)
-#define WLAN_SECTION_SIZE_1 (PREALLOC_WLAN_BUF_NUM * 128)
-#define WLAN_SECTION_SIZE_2 (PREALLOC_WLAN_BUF_NUM * 512)
-#define WLAN_SECTION_SIZE_3 (PREALLOC_WLAN_BUF_NUM * 1024)
-
-#define WLAN_SKB_BUF_NUM 16
-
-static struct sk_buff *wlan_static_skb[WLAN_SKB_BUF_NUM];
-
-struct wifi_mem_prealloc {
- void *mem_ptr;
- unsigned long size;
-};
-
-static struct wifi_mem_prealloc wifi_mem_array[PREALLOC_WLAN_SEC_NUM] = {
- {NULL, (WLAN_SECTION_SIZE_0 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_1 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_2 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_3 + PREALLOC_WLAN_SECTION_HEADER)}
-};
-
-static void *rk29sdk_mem_prealloc(int section, unsigned long size)
-{
- if (section == PREALLOC_WLAN_SEC_NUM)
- return wlan_static_skb;
-
- if ((section < 0) || (section > PREALLOC_WLAN_SEC_NUM))
- return NULL;
-
- if (wifi_mem_array[section].size < size)
- return NULL;
-
- return wifi_mem_array[section].mem_ptr;
-}
-
-static int __init rk29sdk_init_wifi_mem(void)
-{
- int i;
- int j;
-
- for (i = 0 ; i < WLAN_SKB_BUF_NUM ; i++) {
- wlan_static_skb[i] = dev_alloc_skb(
- ((i < (WLAN_SKB_BUF_NUM / 2)) ? 4096 : 8192));
-
- if (!wlan_static_skb[i])
- goto err_skb_alloc;
- }
-
- for (i = 0 ; i < PREALLOC_WLAN_SEC_NUM ; i++) {
- wifi_mem_array[i].mem_ptr =
- kmalloc(wifi_mem_array[i].size, GFP_KERNEL);
-
- if (!wifi_mem_array[i].mem_ptr)
- goto err_mem_alloc;
- }
- return 0;
-
-err_mem_alloc:
- pr_err("Failed to mem_alloc for WLAN\n");
- for (j = 0 ; j < i ; j++)
- kfree(wifi_mem_array[j].mem_ptr);
-
- i = WLAN_SKB_BUF_NUM;
-
-err_skb_alloc:
- pr_err("Failed to skb_alloc for WLAN\n");
- for (j = 0 ; j < i ; j++)
- dev_kfree_skb(wlan_static_skb[j]);
-
- return -ENOMEM;
-}
-
-static int rk29sdk_wifi_status(struct device *dev)
-{
- return rk29sdk_wifi_cd;
-}
-
-static int rk29sdk_wifi_status_register(void (*callback)(int card_present, void *dev_id), void *dev_id)
-{
- if(wifi_status_cb)
- return -EAGAIN;
- wifi_status_cb = callback;
- wifi_status_cb_devid = dev_id;
- return 0;
-}
-
-#if defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU) || defined(CONFIG_RT5370)
-static int __init rk29sdk_wifi_bt_gpio_control_init(void)
-{
-#if defined(CONFIG_USB_WIFI_POWER_CONTROLED_BY_GPIO)
- if (gpio_request(rk_platform_wifi_gpio.power_n.io, "wifi_power")) {
- pr_info("%s: request wifi power gpio failed\n", __func__);
- return -1;
- }
- gpio_direction_output(rk_platform_wifi_gpio.power_n.io, !(rk_platform_wifi_gpio.power_n.enable) );
-#endif
- pr_info("%s: init finished\n",__func__);
- return 0;
-}
-#else
-static int __init rk29sdk_wifi_bt_gpio_control_init(void)
-{
- rk29sdk_init_wifi_mem();
- rk29_mux_api_set(rk_platform_wifi_gpio.power_n.iomux.name, rk_platform_wifi_gpio.power_n.iomux.fgpio);
-
- if (rk_platform_wifi_gpio.power_n.io != INVALID_GPIO) {
- if (gpio_request(rk_platform_wifi_gpio.power_n.io, "wifi_power")) {
- pr_info("%s: request wifi power gpio failed\n", __func__);
- return -1;
- }
- }
-
-#ifdef RK30SDK_WIFI_GPIO_RESET_N
- if (rk_platform_wifi_gpio.reset_n.io != INVALID_GPIO) {
- if (gpio_request(rk_platform_wifi_gpio.reset_n.io, "wifi reset")) {
- pr_info("%s: request wifi reset gpio failed\n", __func__);
- gpio_free(rk_platform_wifi_gpio.power_n.io);
- return -1;
- }
- }
-#endif
-
- if (rk_platform_wifi_gpio.power_n.io != INVALID_GPIO)
- gpio_direction_output(rk_platform_wifi_gpio.power_n.io, !(rk_platform_wifi_gpio.power_n.enable) );
-
-#ifdef RK30SDK_WIFI_GPIO_RESET_N
- if (rk_platform_wifi_gpio.reset_n.io != INVALID_GPIO)
- gpio_direction_output(rk_platform_wifi_gpio.reset_n.io, !(rk_platform_wifi_gpio.reset_n.enable) );
-#endif
-
- #if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
- rk29_sdmmc_gpio_open(1, 0); //added by xbw at 2011-10-13
- #endif
- pr_info("%s: init finished\n",__func__);
-
- return 0;
-}
-#endif
-
-#if defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU) || defined(CONFIG_RT5370)
-static int usbwifi_power_status = 1;
-int rk29sdk_wifi_power(int on)
-{
- pr_info("%s: %d\n", __func__, on);
- if (on){
- #if defined(CONFIG_USB_WIFI_POWER_CONTROLED_BY_GPIO)
- gpio_set_value(rk_platform_wifi_gpio.power_n.io, rk_platform_wifi_gpio.power_n.enable);
- mdelay(100);
- #else
- if(usbwifi_power_status == 1) {
- rkusb_wifi_power(0);
- mdelay(50);
- }
- rkusb_wifi_power(1);
- #endif
- usbwifi_power_status = 1;
- pr_info("wifi turn on power\n");
- }else{
- #if defined(CONFIG_USB_WIFI_POWER_CONTROLED_BY_GPIO)
- gpio_set_value(rk_platform_wifi_gpio.power_n.io, !(rk_platform_wifi_gpio.power_n.enable));
- mdelay(100);
- #else
- rkusb_wifi_power(0);
- #endif
- usbwifi_power_status = 0;
- pr_info("wifi shut off power\n");
- }
- return 0;
-}
-#else
-int rk29sdk_wifi_power(int on)
-{
- pr_info("%s: %d\n", __func__, on);
- if (on){
- gpio_set_value(rk_platform_wifi_gpio.power_n.io, rk_platform_wifi_gpio.power_n.enable);
- mdelay(50);
-
- #if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
- rk29_sdmmc_gpio_open(1, 1); //added by xbw at 2011-10-13
- #endif
-
- #ifdef RK30SDK_WIFI_GPIO_RESET_N
- if (rk_platform_wifi_gpio.reset_n.io != INVALID_GPIO)
- gpio_set_value(rk_platform_wifi_gpio.reset_n.io, rk_platform_wifi_gpio.reset_n.enable);
- #endif
- mdelay(100);
- pr_info("wifi turn on power\n");
- }else{
-// if (!rk29sdk_bt_power_state){
- gpio_set_value(rk_platform_wifi_gpio.power_n.io, !(rk_platform_wifi_gpio.power_n.enable));
-
- #if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
- rk29_sdmmc_gpio_open(1, 0); //added by xbw at 2011-10-13
- #endif
-
- mdelay(100);
- pr_info("wifi shut off power\n");
-// }else
-// {
-// pr_info("wifi shouldn't shut off power, bt is using it!\n");
-// }
-#ifdef RK30SDK_WIFI_GPIO_RESET_N
- if (rk_platform_wifi_gpio.reset_n.io != INVALID_GPIO)
- gpio_set_value(rk_platform_wifi_gpio.reset_n.io, !(rk_platform_wifi_gpio.reset_n.enable));
-#endif
- }
-
-// rk29sdk_wifi_power_state = on;
- return 0;
-}
-#endif
-EXPORT_SYMBOL(rk29sdk_wifi_power);
-
-static int rk29sdk_wifi_reset_state;
-static int rk29sdk_wifi_reset(int on)
-{
- pr_info("%s: %d\n", __func__, on);
- //mdelay(100);
- rk29sdk_wifi_reset_state = on;
- return 0;
-}
-
-int rk29sdk_wifi_set_carddetect(int val)
-{
- pr_info("%s:%d\n", __func__, val);
- rk29sdk_wifi_cd = val;
- if (wifi_status_cb){
- wifi_status_cb(val, wifi_status_cb_devid);
- }else {
- pr_warning("%s, nobody to notify\n", __func__);
- }
- return 0;
-}
-EXPORT_SYMBOL(rk29sdk_wifi_set_carddetect);
-
-
-static struct resource resources[] = {
- {
- .start = WIFI_HOST_WAKE,
- .flags = IORESOURCE_IRQ,
- .name = "bcmdhd_wlan_irq",
- },
-};
- //#if defined(CONFIG_WIFI_CONTROL_FUNC)----#elif
-
-///////////////////////////////////////////////////////////////////////////////////
-#elif defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
-
-#define debug_combo_system 0
-
-int rk29sdk_wifi_combo_get_BGFgpio(void)
-{
- return rk_platform_wifi_gpio.bgf_int_b.io;
-}
-EXPORT_SYMBOL(rk29sdk_wifi_combo_get_BGFgpio);
-
-
-int rk29sdk_wifi_combo_get_GPS_SYNC_gpio(void)
-{
- return rk_platform_wifi_gpio.gps_sync.io;
-}
-EXPORT_SYMBOL(rk29sdk_wifi_combo_get_GPS_SYNC_gpio);
-
-
-static int rk29sdk_wifi_combo_module_gpio_init(void)
-{
- //VDDIO
- #ifdef RK30SDK_WIFI_GPIO_VCCIO_WL
- #ifdef RK30SDK_WIFI_GPIO_VCCIO_WL_PIN_NAME
- rk30_mux_api_set(rk_platform_wifi_gpio.vddio.iomux.name, rk_platform_wifi_gpio.vddio.iomux.fgpio);
- #endif
- gpio_request(rk_platform_wifi_gpio.vddio.io, "combo-VDDIO");
- gpio_direction_output(rk_platform_wifi_gpio.vddio.io, !(rk_platform_wifi_gpio.power_n.enable));
- #endif
-
- //BGF_INT_B
- #ifdef RK30SDK_WIFI_GPIO_BGF_INT_B_PIN_NAME
- rk30_mux_api_set(rk_platform_wifi_gpio.bgf_int_b.iomux.name, rk_platform_wifi_gpio.bgf_int_b.iomux.fgpio);
- #endif
- gpio_request(rk_platform_wifi_gpio.bgf_int_b.io, "combo-BGFINT");
- gpio_pull_updown(rk_platform_wifi_gpio.bgf_int_b.io, GPIOPullUp);
- gpio_direction_input(rk_platform_wifi_gpio.bgf_int_b.io);
-
- //WIFI_INT_B
- #ifdef RK30SDK_WIFI_GPIO_WIFI_INT_B_PIN_NAME
- rk30_mux_api_set(rk_platform_wifi_gpio.bgf_int_b.iomux.name, rk_platform_wifi_gpio.bgf_int_b.iomux.fgpio);
- #endif
- gpio_request(rk_platform_wifi_gpio.wifi_int_b.io, "combo-WIFIINT");
- gpio_pull_updown(rk_platform_wifi_gpio.wifi_int_b.io, GPIOPullUp);
- gpio_direction_input(rk_platform_wifi_gpio.wifi_int_b.io);
-
- //reset
- #ifdef RK30SDK_WIFI_GPIO_RESET_PIN_NAME
- rk30_mux_api_set(rk_platform_wifi_gpio.reset_n.iomux.name, rk_platform_wifi_gpio.reset_n.iomux.fgpio);
- #endif
- gpio_request(rk_platform_wifi_gpio.reset_n.io, "combo-RST");
- gpio_direction_output(rk_platform_wifi_gpio.reset_n.io, !(rk_platform_wifi_gpio.reset_n.enable));
-
- //power
- #ifdef RK30SDK_WIFI_GPIO_POWER_PIN_NAME
- rk30_mux_api_set(rk_platform_wifi_gpio.power_n.iomux.name, rk_platform_wifi_gpio.power_n.iomux.fgpio);
- #endif
- gpio_request(rk_platform_wifi_gpio.power_n.io, "combo-PMUEN");
- gpio_direction_output(rk_platform_wifi_gpio.power_n.io, !(rk_platform_wifi_gpio.power_n.enable));
-
- #if COMBO_MODULE_MT6620_CDT
- //ANTSEL2
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL2
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL2_PIN_NAME
- rk30_mux_api_set(rk_platform_wifi_gpio.ANTSEL2.iomux.name, rk_platform_wifi_gpio.ANTSEL2.iomux.fgpio);
- #endif
- gpio_request(rk_platform_wifi_gpio.ANTSEL2.io, "combo-ANTSEL2");
- gpio_direction_output(rk_platform_wifi_gpio.reset_n.io, rk_platform_wifi_gpio.ANTSEL2.enable);
- #endif
-
- //ANTSEL3
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL3
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL3_PIN_NAME
- rk30_mux_api_set(rk_platform_wifi_gpio.ANTSEL3.iomux.name, rk_platform_wifi_gpio.ANTSEL3.iomux.fgpio);
- #endif
- gpio_request(rk_platform_wifi_gpio.ANTSEL3.io, "combo-ANTSEL3");
- gpio_direction_output(rk_platform_wifi_gpio.ANTSEL3.io, rk_platform_wifi_gpio.ANTSEL3.enable);
- #endif
-
- //GPS_LAN
- #ifdef RK30SDK_WIFI_GPIO_GPS_LAN
- #ifdef RK30SDK_WIFI_GPIO_GPS_LAN_PIN_NAME
- rk30_mux_api_set(rk_platform_wifi_gpio.GPS_LAN.iomux.name, rk_platform_wifi_gpio.GPS_LAN.iomux.fgpio);
- #endif
- gpio_request(rk_platform_wifi_gpio.GPS_LAN.io, "combo-GPSLAN");
- gpio_direction_output(rk_platform_wifi_gpio.GPS_LAN.io, rk_platform_wifi_gpio.GPS_LAN.enable);
- #endif
-
- #endif//#if COMBO_MODULE_MT6620_CDT ---#endif
-
- return 0;
-}
-
-
-int rk29sdk_wifi_combo_module_power(int on)
-{
- if(on)
- {
- #ifdef RK30SDK_WIFI_GPIO_VCCIO_WL
- gpio_set_value(rk_platform_wifi_gpio.vddio.io, rk_platform_wifi_gpio.vddio.enable);
- mdelay(10);
- #endif
-
- gpio_set_value(rk_platform_wifi_gpio.power_n.io, rk_platform_wifi_gpio.power_n.enable);
- mdelay(10);
- pr_info("combo-module turn on power\n");
- }
- else
- {
- gpio_set_value(rk_platform_wifi_gpio.power_n.io, !(rk_platform_wifi_gpio.power_n.enable) );
- mdelay(10);
-
- #ifdef RK30SDK_WIFI_GPIO_VCCIO_WL
- gpio_set_value(rk_platform_wifi_gpio.vddio.io, !(rk_platform_wifi_gpio.vddio.enable));
- #endif
-
- pr_info("combo-module turn off power\n");
- }
- return 0;
-
-}
-EXPORT_SYMBOL(rk29sdk_wifi_combo_module_power);
-
-
-int rk29sdk_wifi_combo_module_reset(int on)
-{
- if(on)
- {
- gpio_set_value(rk_platform_wifi_gpio.reset_n.io, rk_platform_wifi_gpio.reset_n.enable);
- pr_info("combo-module reset out 1\n");
- }
- else
- {
- gpio_set_value(rk_platform_wifi_gpio.reset_n.io, !(rk_platform_wifi_gpio.reset_n.enable) );
- pr_info("combo-module reset out 0\n");
- }
-
- return 0;
-}
-EXPORT_SYMBOL(rk29sdk_wifi_combo_module_reset);
-
-
-static int rk29sdk_wifi_mmc0_status(struct device *dev)
-{
- return rk29sdk_wifi_mmc0_cd;
-}
-
-static int rk29sdk_wifi_mmc0_status_register(void (*callback)(int card_present, void *dev_id), void *dev_id)
-{
- if(wifi_mmc0_status_cb)
- return -EAGAIN;
- wifi_mmc0_status_cb = callback;
- wifi_mmc0_status_cb_devid = dev_id;
- return 0;
-}
-
-
-static int rk29sdk_wifi_status(struct device *dev)
-{
- return rk29sdk_wifi_cd;
-}
-
-static int rk29sdk_wifi_status_register(void (*callback)(int card_present, void *dev_id), void *dev_id)
-{
- if(wifi_status_cb)
- return -EAGAIN;
- wifi_status_cb = callback;
- wifi_status_cb_devid = dev_id;
- return 0;
-}
-
-int rk29sdk_wifi_power(int on)
-{
- pr_info("%s: %d\n", __func__, on);
- if (on){
-
- #if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
-
- #if defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- rk29_sdmmc_gpio_open(0, 1);
- #else
- rk29_sdmmc_gpio_open(1, 0);
- mdelay(10);
- rk29_sdmmc_gpio_open(1, 1);
- #endif
- #endif
-
- mdelay(100);
- pr_info("wifi turn on power\n");
- }
- else
- {
-#if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
- #if defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- rk29_sdmmc_gpio_open(0, 0);
- #else
- rk29_sdmmc_gpio_open(1, 0);
- #endif
-#endif
- mdelay(100);
- pr_info("wifi shut off power\n");
-
- }
-
- rk29sdk_wifi_power_state = on;
- return 0;
-
-}
-EXPORT_SYMBOL(rk29sdk_wifi_power);
-
-
-int rk29sdk_wifi_reset(int on)
-{
- return 0;
-}
-EXPORT_SYMBOL(rk29sdk_wifi_reset);
-
-
-#if defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
-int rk29sdk_wifi_set_carddetect(int val)
-{
- pr_info("%s:%d\n", __func__, val);
- rk29sdk_wifi_mmc0_cd = val;
- if (wifi_mmc0_status_cb){
- wifi_mmc0_status_cb(val, wifi_mmc0_status_cb_devid);
- }else {
- pr_warning("%s,in mmc0 nobody to notify\n", __func__);
- }
- return 0;
-}
-
-#else
-int rk29sdk_wifi_set_carddetect(int val)
-{
- pr_info("%s:%d\n", __func__, val);
- rk29sdk_wifi_cd = val;
- if (wifi_status_cb){
- wifi_status_cb(val, wifi_status_cb_devid);
- }else {
- pr_warning("%s,in mmc1 nobody to notify\n", __func__);
- }
- return 0;
-}
-#endif
-
-EXPORT_SYMBOL(rk29sdk_wifi_set_carddetect);
-
-///////////////////////////////////////////////////////////////////////////////////
-#endif //#if defined(CONFIG_WIFI_CONTROL_FUNC)---#elif defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) --#endif
-
-
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC)
-static struct wifi_platform_data rk29sdk_wifi_control = {
- .set_power = rk29sdk_wifi_power,
- .set_reset = rk29sdk_wifi_reset,
- .set_carddetect = rk29sdk_wifi_set_carddetect,
- .mem_prealloc = rk29sdk_mem_prealloc,
-};
-
-static struct platform_device rk29sdk_wifi_device = {
- .name = "bcmdhd_wlan",
- .id = 1,
- .num_resources = ARRAY_SIZE(resources),
- .resource = resources,
- .dev = {
- .platform_data = &rk29sdk_wifi_control,
- },
-};
-
-#elif defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
-
- #if debug_combo_system
- static struct combo_module_platform_data rk29sdk_combo_module_control = {
- .set_power = rk29sdk_wifi_combo_module_power,
- .set_reset = rk29sdk_wifi_combo_module_reset,
- };
-
- static struct platform_device rk29sdk_combo_module_device = {
- .name = "combo-system",
- .id = 1,
- .dev = {
- .platform_data = &rk29sdk_combo_module_control,
- },
- };
- #endif
-
-static struct wifi_platform_data rk29sdk_wifi_control = {
- .set_power = rk29sdk_wifi_power,
- .set_reset = rk29sdk_wifi_reset,
- .set_carddetect = rk29sdk_wifi_set_carddetect,
-};
-
-static struct platform_device rk29sdk_wifi_device = {
- .name = "combo-wifi",
- .id = 1,
- .dev = {
- .platform_data = &rk29sdk_wifi_control,
- },
-};
-
-#endif
-
-
+++ /dev/null
-#include <linux/regulator/machine.h>
-#include <linux/i2c/twl.h>
-#include <linux/mfd/tps65910.h>
-#include <mach/sram.h>
-#include <linux/platform_device.h>
-
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-
-#ifdef CONFIG_MFD_TPS65910
-
-extern int platform_device_register(struct platform_device *pdev);
-
-int tps65910_pre_init(struct tps65910 *tps65910){
-
- int val = 0;
- int i = 0;
- int err = -1;
-
- printk("%s,line=%d\n", __func__,__LINE__);
-#ifdef CONFIG_RK_CONFIG
- if(sram_gpio_init(get_port_config(pmic_slp).gpio, &pmic_sleep) < 0){
- printk(KERN_ERR "sram_gpio_init failed\n");
- return -EINVAL;
- }
- if(port_output_init(pmic_slp, 0, "pmic_slp") < 0){
- printk(KERN_ERR "port_output_init failed\n");
- return -EINVAL;
- }
-#else
- if(sram_gpio_init(PMU_POWER_SLEEP, &pmic_sleep) < 0){
- printk(KERN_ERR "sram_gpio_init failed\n");
- return -EINVAL;
- }
-
- gpio_request(PMU_POWER_SLEEP, "NULL");
- gpio_direction_output(PMU_POWER_SLEEP, GPIO_LOW);
-#endif
-
- val = tps65910_reg_read(tps65910, TPS65910_DEVCTRL2);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_DEVCTRL2 reg\n");
- return val;
- }
- /* Set sleep state active high and allow device turn-off after PWRON long press */
- val |= (DEVCTRL2_SLEEPSIG_POL_MASK | DEVCTRL2_PWON_LP_OFF_MASK);
-
- err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL2, val);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_DEVCTRL2 reg\n");
- return err;
- }
- #if 1
- /* set PSKIP=0 */
- val = tps65910_reg_read(tps65910, TPS65910_DCDCCTRL);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
- return val;
- }
-
- val &= ~DEVCTRL_DEV_OFF_MASK;
- val &= ~DEVCTRL_DEV_SLP_MASK;
- err = tps65910_reg_write(tps65910, TPS65910_DCDCCTRL, val);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_DCDCCTRL reg\n");
- return err;
- }
- #endif
- /* Set the maxinum load current */
- /* VDD1 */
- val = tps65910_reg_read(tps65910, TPS65910_VDD1);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_VDD1 reg\n");
- return val;
- }
-
- val |= (1<<5); //when 1: 1.5 A
- val |= (0x07<<2); //TSTEP[2:0] = 111 : 2.5 mV/|¨¬s(sampling 3 Mhz/5)
- err = tps65910_reg_write(tps65910, TPS65910_VDD1, val);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_VDD1 reg\n");
- return err;
- }
-
- /* VDD2 */
- val = tps65910_reg_read(tps65910, TPS65910_VDD2);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_VDD2 reg\n");
- return val;
- }
-
- val |= (1<<5); //when 1: 1.5 A
- err = tps65910_reg_write(tps65910, TPS65910_VDD2, val);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_VDD2 reg\n");
- return err;
- }
-
- /* VIO */
- val = tps65910_reg_read(tps65910, TPS65910_VIO);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_VIO reg\n");
- return -EIO;
- }
-
- val |= (1<<6); //when 01: 1.0 A
- err = tps65910_reg_write(tps65910, TPS65910_VIO, val);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_VIO reg\n");
- return err;
- }
- #if 1
- /* Mask ALL interrupts */
- err = tps65910_reg_write(tps65910,TPS65910_INT_MSK, 0xFF);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_INT_MSK reg\n");
- return err;
- }
-
- err = tps65910_reg_write(tps65910, TPS65910_INT_MSK2, 0x03);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_INT_MSK2 reg\n");
- return err;
- }
-
- /* Set RTC Power, disable Smart Reflex in DEVCTRL_REG */
- #if 1
- val = 0;
- val |= (DEVCTRL_SR_CTL_I2C_SEL_MASK);
- err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL, val);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_DEVCTRL reg\n");
- return err;
- }
- printk(KERN_INFO "TPS65910 Set default voltage.\n");
- #endif
- #if 0
- //read sleep control register for debug
- for(i=0; i<6; i++)
- {
- err = tps65910_reg_read(tps65910, &val, TPS65910_DEVCTRL+i);
- if (err) {
- printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
- return -EIO;
- }
- else
- printk("%s.......is 0x%04x\n",__FUNCTION__,val);
- }
- #endif
-
- #if 1
- //sleep control register
- /*set func when in sleep mode */
- val = tps65910_reg_read(tps65910, TPS65910_DEVCTRL);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
- return val;
- }
-
- val |= (1 << 1);
- err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL, val);
- if (err) {
- printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
- \n", TPS65910_VDIG1);
- return err;
- }
-
- /* open ldo when in sleep mode */
- val = tps65910_reg_read(tps65910, TPS65910_SLEEP_KEEP_LDO_ON);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
- return val;
- }
-
- val &= 0;
- err = tps65910_reg_write(tps65910, TPS65910_SLEEP_KEEP_LDO_ON, val);
- if (err) {
- printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
- \n", TPS65910_VDIG1);
- return err;
- }
-
- /*set dc mode when in sleep mode */
- val = tps65910_reg_read(tps65910, TPS65910_SLEEP_KEEP_RES_ON);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
- return val;
- }
-
- val |= 0xff;
- val &= ~(0x07); //set vdd1 vdd2 vio in pfm mode when in sleep
- err = tps65910_reg_write(tps65910, TPS65910_SLEEP_KEEP_RES_ON, val);
- if (err) {
- printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
- \n", TPS65910_VDIG1);
- return err;
- }
-
- /*close ldo when in sleep mode */
- val = tps65910_reg_read(tps65910, TPS65910_SLEEP_SET_LDO_OFF);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
- return val;
- }
-
- val |= 0x8B;
- err = tps65910_reg_write(tps65910, TPS65910_SLEEP_SET_LDO_OFF, val);
- if (err) {
- printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
- \n", TPS65910_VDIG1);
- return err;
- }
-
- #endif
- #if 0
- //read sleep control register for debug
- for(i=0; i<6; i++)
- {
- err = tps65910_reg_read(tps65910, &val, TPS65910_DEVCTRL+i);
- if (err) {
- printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
- return -EIO;
- }
- else
- printk("%s.......is 0x%4x\n",__FUNCTION__,val);
- }
- #endif
- #endif
-
- /**********************set arm in pwm ****************/
- val = tps65910_reg_read(tps65910, TPS65910_DCDCCTRL);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
- return val;
- }
-
- val &= ~(1<<4);
- err = tps65910_reg_write(tps65910, TPS65910_DCDCCTRL, val);
- if (err) {
- printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
- \n", TPS65910_VDIG1);
- return err;
- }
- /************************************************/
-
- printk("%s,line=%d\n", __func__,__LINE__);
- return 0;
-
-}
-
-int tps65910_post_init(struct tps65910 *tps65910)
-{
- struct regulator *dcdc;
- struct regulator *ldo;
- int i = 0;
- printk("%s,line=%d\n", __func__,__LINE__);
-
-#ifndef CONFIG_RK_CONFIG
- g_pmic_type = PMIC_TYPE_TPS65910;
-#endif
- printk("%s:g_pmic_type=%d\n",__func__,g_pmic_type);
-
- #ifdef CONFIG_RK30_PWM_REGULATOR
- platform_device_register(&pwm_regulator_device[0]);
- #endif
-
- for(i = 0; i < ARRAY_SIZE(tps65910_dcdc_info); i++)
- {
- if(tps65910_dcdc_info[i].min_uv == 0 && tps65910_dcdc_info[i].max_uv == 0)
- continue;
- dcdc =regulator_get(NULL, tps65910_dcdc_info[i].name);
- regulator_set_voltage(dcdc, tps65910_dcdc_info[i].min_uv, tps65910_dcdc_info[i].max_uv);
- regulator_enable(dcdc);
- printk("%s %s =%dmV end\n", __func__,tps65910_dcdc_info[i].name, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
- }
-
- for(i = 0; i < ARRAY_SIZE(tps65910_ldo_info); i++)
- {
- if(tps65910_ldo_info[i].min_uv == 0 && tps65910_ldo_info[i].max_uv == 0)
- continue;
- ldo =regulator_get(NULL, tps65910_ldo_info[i].name);
- regulator_set_voltage(ldo, tps65910_ldo_info[i].min_uv, tps65910_ldo_info[i].max_uv);
- regulator_enable(ldo);
- printk("%s %s =%dmV end\n", __func__,tps65910_ldo_info[i].name, regulator_get_voltage(ldo));
- regulator_put(ldo);
- }
-
- printk("%s,line=%d END\n", __func__,__LINE__);
-
- return 0;
-}
-static struct regulator_consumer_supply tps65910_smps1_supply[] = {
- {
- .supply = "vdd1",
- },
- {
- .supply = "vdd_cpu",
- },
-};
-static struct regulator_consumer_supply tps65910_smps2_supply[] = {
- {
- .supply = "vdd2",
- },
- #if defined(CONFIG_MACH_RK2926_V86)
- {
- .supply = "vdd_core",
- },
- #endif
-
-};
-static struct regulator_consumer_supply tps65910_smps3_supply[] = {
- {
- .supply = "vdd3",
- },
-};
-static struct regulator_consumer_supply tps65910_smps4_supply[] = {
- {
- .supply = "vio",
- },
-};
-static struct regulator_consumer_supply tps65910_ldo1_supply[] = {
- {
- .supply = "vdig1",
- },
-};
-static struct regulator_consumer_supply tps65910_ldo2_supply[] = {
- {
- .supply = "vdig2",
- },
-};
-
-static struct regulator_consumer_supply tps65910_ldo3_supply[] = {
- {
- .supply = "vaux1",
- },
-};
-static struct regulator_consumer_supply tps65910_ldo4_supply[] = {
- {
- .supply = "vaux2",
- },
-};
-static struct regulator_consumer_supply tps65910_ldo5_supply[] = {
- {
- .supply = "vaux33",
- },
-};
-static struct regulator_consumer_supply tps65910_ldo6_supply[] = {
- {
- .supply = "vmmc",
- },
-};
-static struct regulator_consumer_supply tps65910_ldo7_supply[] = {
- {
- .supply = "vdac",
- },
-};
-
-static struct regulator_consumer_supply tps65910_ldo8_supply[] = {
- {
- .supply = "vpll",
- },
-};
-
-static struct regulator_init_data tps65910_smps1 = {
- .constraints = {
- .name = "VDD1",
- .min_uV = 600000,
- .max_uV = 1500000,
- .apply_uV = 1,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_smps1_supply),
- .consumer_supplies = tps65910_smps1_supply,
-};
-
-/* */
-static struct regulator_init_data tps65910_smps2 = {
- .constraints = {
- .name = "VDD2",
- .min_uV = 600000,
- .max_uV = 1500000,
- .apply_uV = 1,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_smps2_supply),
- .consumer_supplies = tps65910_smps2_supply,
-};
-
-/* */
-static struct regulator_init_data tps65910_smps3 = {
- .constraints = {
- .name = "VDD3",
- .min_uV = 1000000,
- .max_uV = 1400000,
- .apply_uV = 1,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_smps3_supply),
- .consumer_supplies = tps65910_smps3_supply,
-};
-
-static struct regulator_init_data tps65910_smps4 = {
- .constraints = {
- .name = "VIO",
- .min_uV = 1800000,
- .max_uV = 3300000,
- .apply_uV = 1,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_smps4_supply),
- .consumer_supplies = tps65910_smps4_supply,
-};
-static struct regulator_init_data tps65910_ldo1 = {
- .constraints = {
- .name = "VDIG1",
- .min_uV = 1200000,
- .max_uV = 2700000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo1_supply),
- .consumer_supplies = tps65910_ldo1_supply,
-};
-
-/* */
-static struct regulator_init_data tps65910_ldo2 = {
- .constraints = {
- .name = "VDIG2",
- .min_uV = 1000000,
- .max_uV = 1800000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo2_supply),
- .consumer_supplies = tps65910_ldo2_supply,
-};
-
-/* */
-static struct regulator_init_data tps65910_ldo3 = {
- .constraints = {
- .name = "VAUX1",
- .min_uV = 1800000,
- .max_uV = 3300000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo3_supply),
- .consumer_supplies = tps65910_ldo3_supply,
-};
-
-/* */
-static struct regulator_init_data tps65910_ldo4 = {
- .constraints = {
- .name = "VAUX2",
- .min_uV = 1800000,
- .max_uV = 3300000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo4_supply),
- .consumer_supplies = tps65910_ldo4_supply,
-};
-
-/* */
-static struct regulator_init_data tps65910_ldo5 = {
- .constraints = {
- .name = "VAUX33",
- .min_uV = 1800000,
- .max_uV = 3300000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo5_supply),
- .consumer_supplies = tps65910_ldo5_supply,
-};
-
-/* */
-static struct regulator_init_data tps65910_ldo6 = {
- .constraints = {
- .name = "VMMC",
- .min_uV = 1800000,
- .max_uV = 3300000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo6_supply),
- .consumer_supplies = tps65910_ldo6_supply,
-};
-
-/* */
-static struct regulator_init_data tps65910_ldo7 = {
- .constraints = {
- .name = "VDAC",
- .min_uV = 1800000,
- .max_uV = 2850000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo7_supply),
- .consumer_supplies = tps65910_ldo7_supply,
-};
-
-/* */
-static struct regulator_init_data tps65910_ldo8 = {
- .constraints = {
- .name = "VPLL",
- .min_uV = 1000000,
- .max_uV = 2500000,
- .apply_uV = 1,
- #if defined(CONFIG_MACH_RK2926_V86)
- #else
- .always_on = 1,
- #endif
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo8_supply),
- .consumer_supplies = tps65910_ldo8_supply,
-};
-void __sramfunc board_pmu_tps65910_suspend(void)
-{
- sram_gpio_set_value(pmic_sleep, GPIO_HIGH);
-}
-void __sramfunc board_pmu_tps65910_resume(void)
-{
- sram_gpio_set_value(pmic_sleep, GPIO_LOW);
- sram_udelay(2000);
-}
-static struct tps65910_board tps65910_data = {
- .irq = (unsigned)TPS65910_HOST_IRQ,
- .irq_base = IRQ_BOARD_BASE,
- .gpio_base = TPS65910_GPIO_EXPANDER_BASE,
-
- .pre_init = tps65910_pre_init,
- .post_init = tps65910_post_init,
-
- //TPS65910_NUM_REGS = 13
- // Regulators
- .tps65910_pmic_init_data[TPS65910_REG_VRTC] = NULL,
- .tps65910_pmic_init_data[TPS65910_REG_VIO] = &tps65910_smps4,
- .tps65910_pmic_init_data[TPS65910_REG_VDD1] = &tps65910_smps1,
- .tps65910_pmic_init_data[TPS65910_REG_VDD2] = &tps65910_smps2,
- .tps65910_pmic_init_data[TPS65910_REG_VDD3] = &tps65910_smps3,
- .tps65910_pmic_init_data[TPS65910_REG_VDIG1] = &tps65910_ldo1,
- .tps65910_pmic_init_data[TPS65910_REG_VDIG2] = &tps65910_ldo2,
- .tps65910_pmic_init_data[TPS65910_REG_VPLL] = &tps65910_ldo8,
- .tps65910_pmic_init_data[TPS65910_REG_VDAC] = &tps65910_ldo7,
- .tps65910_pmic_init_data[TPS65910_REG_VAUX1] = &tps65910_ldo3,
- .tps65910_pmic_init_data[TPS65910_REG_VAUX2] = &tps65910_ldo4,
- .tps65910_pmic_init_data[TPS65910_REG_VAUX33] = &tps65910_ldo5,
- .tps65910_pmic_init_data[TPS65910_REG_VMMC] = &tps65910_ldo6,
-
-
-};
-
-#endif
-
+++ /dev/null
-/* arch/arm/mach-rk2928/board-rk2928-fpga.c
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-#include <mach/dvfs.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <linux/fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/mfd/tps65910.h>
-#include <linux/regulator/act8931.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-#if defined(CONFIG_HDMI_RK30)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-
-#ifdef CONFIG_SND_SOC_RK2928
-#include "../../../sound/soc/codecs/rk2928_codec.h"
-#endif
-
-#include "board-rk2928-sdk-camera.c"
-#include "board-rk2928-sdk-key.c"
-
-int __sramdata g_pmic_type = 0;
-
-#ifdef CONFIG_THREE_FB_BUFFER
-#define RK30_FB0_MEM_SIZE 12*SZ_1M
-#else
-#define RK30_FB0_MEM_SIZE 8*SZ_1M
-#endif
-
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-#define PWM_ID 0
-#define PWM_MUX_NAME GPIO0D2_PWM_0_NAME
-#define PWM_MUX_MODE GPIO0D_PWM_0
-#define PWM_MUX_MODE_GPIO GPIO0D_GPIO0D2
-#define PWM_GPIO RK2928_PIN0_PD2
-#define PWM_EFFECT_VALUE 0
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-
-#define BL_EN_PIN RK2928_PIN3_PC5
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
-#ifdef LCD_DISP_ON_PIN
- // rk30_mux_api_set(BL_EN_MUX_NAME, BL_EN_MUX_MODE);
-
- ret = gpio_request(BL_EN_PIN, NULL);
- if (ret != 0) {
- gpio_free(BL_EN_PIN);
- }
-
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0;
-#ifdef LCD_DISP_ON_PIN
- gpio_set_value(BL_EN_PIN, !BL_EN_VALUE);
- gpio_free(BL_EN_PIN);
-#endif
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret = 0;
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- if (gpio_request(PWM_GPIO, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- #if defined(CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- {
- gpio_direction_output(PWM_GPIO, GPIO_LOW);
- }
- #endif
- #if defined(CONFIG_REGULATOR_ACT8931)
- if(pmic_is_act8931())
- {
- gpio_direction_output(PWM_GPIO, GPIO_HIGH);
- }
- #endif
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, !BL_EN_VALUE);
-#endif
-
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- gpio_free(PWM_GPIO);
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
-#ifdef LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, 1);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .min_brightness = 80,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-#endif
-
-#ifdef CONFIG_FB_ROCKCHIP
-
-#define LCD_MUX_NAME GPIO0C2_UART0_RTSN_NAME
-#define LCD_GPIO_MODE GPIO0C_GPIO0C2
-
-#define LCD_EN RK2928_PIN3_PB3
-#define LCD_EN_VALUE GPIO_LOW
-
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
-
- // rk30_mux_api_set(LCD_MUX_NAME, LCD_GPIO_MODE);
-
- ret = gpio_request(LCD_EN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_EN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_EN, LCD_EN_VALUE); //disable
- }
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
-
- #if 0//defined(CONFIG_REGULATOR_ACT8931)
- if(pmic_is_act8931())
- {
- struct regulator *ldo;
- ldo = regulator_get(NULL, "act_ldo4"); //vcc_lcd
- regulator_disable(ldo);
- regulator_put(ldo);
- udelay(100);
- }
- #endif
- gpio_set_value(LCD_EN, !LCD_EN_VALUE);
- msleep(50);
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- #if 0//defined(CONFIG_REGULATOR_ACT8931)
- if(pmic_is_act8931())
- {
- struct regulator *ldo;
- ldo = regulator_get(NULL, "act_ldo4"); //vcc_lcd
- regulator_enable(ldo);
- regulator_put(ldo);
- udelay(100);
- msleep(300); // wait for powering on LED circuit
- }
- #endif
-
- gpio_set_value(LCD_EN, LCD_EN_VALUE);
- msleep(50);
- return 0;
-}
-
-#if defined(CONFIG_LCDC_RK2928)
-struct rk29fb_info lcdc_screen_info = {
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-
-//LCDC
-#ifdef CONFIG_LCDC_RK2928
-static struct resource resource_lcdc[] = {
- [0] = {
- .name = "lcdc reg",
- .start = RK2928_LCDC_PHYS,
- .end = RK2928_LCDC_PHYS + RK2928_LCDC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc irq",
- .start = IRQ_LCDC,
- .end = IRQ_LCDC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc = {
- .name = "rk2928-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc),
- .resource = resource_lcdc,
- .dev = {
- .platform_data = &lcdc_screen_info,
- },
-};
-#endif
-
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-#if defined (CONFIG_TOUCHSCREEN_GT811_IIC)
-#define TOUCH_RESET_PIN RK2928_PIN3_PC3
-#define TOUCH_INT_PIN RK2928_PIN3_PC7
-int gt811_init_platform_hw(void)
-{
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("gt811_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("gt811_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_pull_updown(TOUCH_INT_PIN, 1);
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- mdelay(100);
-
- return 0;
-}
-
-
-static struct goodix_platform_data gt811_info = {
- .model= 811,
- .rest_pin = TOUCH_RESET_PIN,
- .init_platform_hw= gt811_init_platform_hw,
-
-};
-#endif
-
-#if defined(CONFIG_TOUCHSCREEN_SITRONIX_A720)
-
-#define TOUCH_RESET_PIN RK2928_PIN1_PA3
-#define TOUCH_INT_PIN RK2928_PIN1_PB3
-int ft5306_init_platform_hw(void)
-{
-
- //printk("ft5306_init_platform_hw\n");
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("ft5306_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("ift5306_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, GPIO_HIGH);
- mdelay(10);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- mdelay(10);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- msleep(300);
- return 0;
-
-}
-
-struct ft5x0x_platform_data sitronix_info = {
- .model = 5007,
- .init_platform_hw= ft5306_init_platform_hw,
-};
-#endif
-
-
-
-/*MMA7660 gsensor*/
-#if defined (CONFIG_GS_MMA7660)
-#define MMA7660_INT_PIN RK2928_PIN3_PD1
-
-static int mma7660_init_platform_hw(void)
-{
- rk30_mux_api_set(GPIO1B1_SPI_TXD_UART1_SOUT_NAME, GPIO1B_GPIO1B1);
-
- return 0;
-}
-
-static struct sensor_platform_data mma7660_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma7660_init_platform_hw,
- .orientation = {-1, 0, 0, 0, -1, 0, 0, 0, 1},
-};
-#endif
-
-#if defined (CONFIG_GS_MXC6225)
-#define MXC6225_INT_PIN RK2928_PIN3_PD1
-
-static int mxc6225_init_platform_hw(void)
-{
- rk30_mux_api_set(GPIO1B1_SPI_TXD_UART1_SOUT_NAME, GPIO1B_GPIO1B1);
- return 0;
-}
-
-static struct sensor_platform_data mxc6225_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 0,
- .poll_delay_ms = 30,
- .init_platform_hw = mxc6225_init_platform_hw,
- .orientation = { 0, 0, 0, 1, 0, 0, 0, 1, 0 },
-};
-#endif
-
-#if CONFIG_RK30_PWM_REGULATOR
-static int pwm_voltage_map[] = {
- 950000,975000,1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000, 1375000, 1400000
-};
-
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_core",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] =
-{
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
- .pwm_id = 2,
- .pwm_gpio = RK2928_PIN0_PD4,
- .pwm_iomux_name = GPIO0D4_PWM_2_NAME,
- .pwm_iomux_pwm = GPIO0D_PWM_2,
- .pwm_iomux_gpio = GPIO0D_GPIO0D4,
- .pwm_voltage = 1200000,
- .suspend_voltage = 1050000,
- .min_uV = 950000,
- .max_uV = 1400000,
- .coefficient = 504, //50.4%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-#endif
-
-/***********************************************************
-* usb wifi
-************************************************************/
-#if defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU) || defined(CONFIG_RT5370)
-
-static void rkusb_wifi_power(int on) {
- struct regulator *ldo = NULL;
-
-#if defined(CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910()) {
- ldo = regulator_get(NULL, "vmmc"); //vccio_wl
- }
-#endif
-#if defined(CONFIG_REGULATOR_ACT8931)
- if(pmic_is_act8931()) {
- ldo = regulator_get(NULL, "act_ldo4"); //vccio_wl
- }
-#endif
-
- if(on) {
- regulator_enable(ldo);
- printk("%s: vccio_wl enable\n", __func__);
- } else {
- printk("%s: vccio_wl disable\n", __func__);
- regulator_disable(ldo);
- }
-
- regulator_put(ldo);
- udelay(100);
-}
-
-#endif
-
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and SDIO.noted by xbw at 2012-03-05
-**************************************************************************************************/
-
-#ifdef CONFIG_RFKILL_RK
-// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
-static struct rfkill_rk_platform_data rfkill_rk_platdata = {
- .type = RFKILL_TYPE_BLUETOOTH,
- .poweron_gpio = { // BT_REG_ON
- .io = RK2928_PIN1_PA3,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK2928_PIN3_PD5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = NULL,
- },
- },
-
- .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
- .io = RK2928_PIN0_PC6, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .gpio = {
- .io = RK2928_PIN0_PC5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
- .iomux = {
- .name = NULL,
- },
- },
- },
-
- .rts_gpio = { // UART_RTS, enable or disable BT's data coming
- .io = RK2928_PIN0_PC2, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = GPIO0C2_UART0_RTSN_NAME,
- .fgpio = GPIO0C_GPIO0C3,
- .fmux = GPIO0C_UART0_RTSN,//GPIO0C_UART0_CTSN,
- },
- },
-};
-
-static struct platform_device device_rfkill_rk = {
- .name = "rfkill_rk",
- .id = -1,
- .dev = {
- .platform_data = &rfkill_rk_platdata,
- },
-};
-#endif
-
-#ifdef CONFIG_SDMMC_RK29
-#include "board-rk2928-sdk-sdmmc.c"
-#endif
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- rk30_mux_api_set(GPIO3B1_SDMMC0CMD_NAME, GPIO3B_SDMMC0_CMD);
- rk30_mux_api_set(GPIO3B0_SDMMC0CLKOUT_NAME, GPIO3B_SDMMC0_CLKOUT);
- rk30_mux_api_set(GPIO3B2_SDMMC0DATA0_NAME, GPIO3B_SDMMC0_DATA0);
- rk30_mux_api_set(GPIO3B3_SDMMC0DATA1_NAME, GPIO3B_SDMMC0_DATA1);
- rk30_mux_api_set(GPIO3B4_SDMMC0DATA2_NAME, GPIO3B_SDMMC0_DATA2);
- rk30_mux_api_set(GPIO3B5_SDMMC0DATA3_NAME, GPIO3B_SDMMC0_DATA3);
-
- rk30_mux_api_set(GPIO3B6_SDMMC0DETECTN_NAME, GPIO3B_GPIO3B6);
-
- rk30_mux_api_set(GPIO3A7_SDMMC0PWREN_NAME, GPIO3A_GPIO3A7);
- gpio_request(RK30_PIN3_PA7, "sdmmc-power");
- gpio_direction_output(RK30_PIN3_PA7, GPIO_LOW);
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- #if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO);
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FMUX);
- #endif
-
- #if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
- #endif
-
-#endif
-
- return 0;
-}
-
-int rk2928_sd_vcc_reset(){
- struct regulator *vcc;
-
- vcc = regulator_get(NULL,"act_ldo4");
- if (vcc == NULL || IS_ERR(vcc) ){
- printk("%s get cif vaux33 ldo failed!\n",__func__);
- return -1 ;
- }
-
- printk("hj---->rk29_sdmmc_hw_init get vmmc regulator successfully \n\n\n");
- regulator_disable(vcc);
- mdelay(2000);
- regulator_enable(vcc);
-
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) && defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- .status = rk29sdk_wifi_mmc0_status,
- .register_status_notify = rk29sdk_wifi_mmc0_status_register,
-#endif
-
- .power_en = RK29SDK_SD_CARD_PWR_EN,
- .power_en_level = RK29SDK_SD_CARD_PWR_EN_LEVEL,
-
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC0_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
- .sd_vcc_reset = rk2928_sd_vcc_reset ,
-
- .det_pin_info = {
- .io = RK29SDK_SD_CARD_DETECT_N, //INVALID_GPIO,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- },
- },
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- rk30_mux_api_set(GPIO3C0_SMMC1CMD_NAME, GPIO3C_SMMC1_CMD);
- rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_NAME, GPIO3C_SDMMC1_CLKOUT);
- rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_NAME, GPIO3C_SDMMC1_DATA0);
- rk30_mux_api_set(GPIO3C2_SDMMC1DATA1_NAME, GPIO3C_SDMMC1_DATA1);
- rk30_mux_api_set(GPIO3C3_SDMMC1DATA2_NAME, GPIO3C_SDMMC1_DATA2);
- rk30_mux_api_set(GPIO3C4_SDMMC1DATA3_NAME, GPIO3C_SDMMC1_DATA3);
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC) || defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-
- #if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC1_WRITE_PROTECT_ENABLE_VALUE;
- #else
- .write_prt = INVALID_GPIO,
- #endif
-
- #if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
- .sdio_INT_gpio = RK29SDK_WIFI_SDIO_CARD_INT,
- #endif
-
- .det_pin_info = {
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .io = RK29SDK_SD_CARD_DETECT_N,
-#else
- .io = INVALID_GPIO,
-#endif
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- },
- },
-
- .enable_sd_wakeup = 0,
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-/**************************************************************************************************
- * the end of setting for SDMMC devices
-**************************************************************************************************/
-
-#if defined(CONFIG_MT5931_MT6622)
-static struct mt6622_platform_data mt6622_platdata = {
- .power_gpio = { // BT_REG_ON
- .io = RK2928_PIN3_PC2, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK2928_PIN0_PC6,
- .enable = GPIO_LOW,
- .iomux = {
- .name = NULL,
- },
- },
-
- .irq_gpio = {
- .io = RK2928_PIN3_PD3,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- }
-};
-
-static struct platform_device device_mt6622 = {
- .name = "mt6622",
- .id = -1,
- .dev = {
- .platform_data = &mt6622_platdata,
- },
-};
-#endif
-
-#ifdef CONFIG_SND_SOC_RK2928
-static int hpctl_io_init(void)
-{
- int ret = 0;
- return ret;
-}
-
-struct rk2928_codec_pdata rk2928_codec_pdata_info={
- .hpctl = INVALID_GPIO,
- .hpctl_io_init = hpctl_io_init,
-};
-
-static struct resource resources_acodec[] = {
- {
- .start = RK2928_ACODEC_PHYS,
- .end = RK2928_ACODEC_PHYS + RK2928_ACODEC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = RK2928_PIN3_PD4,
- .end = RK2928_PIN3_PD4,
- .flags = IORESOURCE_IO,
- },
-};
-
-static struct platform_device device_acodec = {
- .name = "rk2928-codec",
- .id = -1,
- .num_resources = ARRAY_SIZE(resources_acodec),
- .resource = resources_acodec,
- .dev = {
- .platform_data = &rk2928_codec_pdata_info,
- }
-};
-#endif
-
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = RK2928_PIN1_PB4,//INVALID_GPIO,
- .batt_low_pin = INVALID_GPIO,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = RK2928_PIN1_PA0,
- .dc_det_level = GPIO_LOW,
- .charge_ok_level = GPIO_HIGH,
-
- .charging_sleep = 0 ,
- .save_capacity = 1 ,
- .adc_channel =0 ,
-
-};
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_FB_ROCKCHIP
- &device_fb,
-#endif
-#ifdef CONFIG_LCDC_RK2928
- &device_lcdc,
-#endif
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- &rk29_device_backlight,
-#endif
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_SND_SOC_RK2928
- &device_acodec,
-#endif
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
- &rk30_device_adc_battery,
-#endif
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- &rk29sdk_wifi_device,
-#endif
-#ifdef CONFIG_MT5931_MT6622
- &device_mt6622,
-#endif
-#ifdef CONFIG_RFKILL_RK
- &device_rfkill_rk,
-#endif
-};
-//i2c
-#ifdef CONFIG_I2C0_RK30
-#ifdef CONFIG_MFD_TPS65910
-#define TPS65910_HOST_IRQ RK2928_PIN1_PB2
-#define PMU_POWER_SLEEP RK2928_PIN0_PD0
-
-static struct pmu_info tps65910_dcdc_info[] = {
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vdd2", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vio", //vcc_io
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
-
-};
-static struct pmu_info tps65910_ldo_info[] = {
- #if defined(CONFIG_MACH_RK2928_TB) || defined(CONFIG_MACH_RK2926_TB)
- {
- .name = "vpll", //vcc25
- .min_uv = 2500000,
- .max_uv = 2500000,
- },
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "vdac", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- #else
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 1500000,
- .max_uv = 1500000,
- },
-
- {
- .name = "vdig2", //vdd11
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vaux1", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "vaux2", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vaux33", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vmmc", //
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- #endif
- };
-
-#include "board-rk2928-sdk-tps65910.c"
-#endif
-
-#ifdef CONFIG_REGULATOR_ACT8931
-#define ACT8931_HOST_IRQ RK2928_PIN3_PC6
-
-#if defined(CONFIG_MACH_RK2928_SDK)
-#define ACT8931_CHGSEL_PIN RK2928_PIN0_PD0
-#else
-#define ACT8931_CHGSEL_PIN RK2928_PIN1_PA1
-#endif
-
-static struct pmu_info act8931_dcdc_info[] = {
- {
- .name = "act_dcdc1", //vcc_io
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_dcdc2", //ddr
- .min_uv = 1500000,
- .max_uv = 1500000,
- },
- {
- .name = "vdd_cpu", //vdd_arm
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
-
-};
-static struct pmu_info act8931_ldo_info[] = {
- {
- .name = "act_ldo1", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "act_ldo2", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo3", //vcca30
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
- {
- .name = "act_ldo4", //vcc_wl
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
-};
-#include "board-rk2928-sdk-act8931.c"
-#endif
-
-
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-#if defined (CONFIG_REGULATOR_ACT8931)
- {
- .type = "act8931",
- .addr = 0x5b,
- .flags = 0,
- .irq = ACT8931_HOST_IRQ,
- .platform_data=&act8931_data,
- },
-#endif
-#ifdef CONFIG_MACH_RK2926_M713
-#if defined (CONFIG_RTC_HYM8563)
- {
- .type = "rtc_hym8563",
- .addr = 0x51,
- .flags = 0,
- .irq = RK2928_PIN1_PA5,
- },
-#endif
-#endif
-};
-#endif
-
-int __sramdata gpio0d4_iomux,gpio0d4_do,gpio0d4_dir;
-
-#define gpio0_readl(offset) readl_relaxed(RK2928_GPIO0_BASE + offset)
-#define gpio0_writel(v, offset) do { writel_relaxed(v, RK2928_GPIO0_BASE + offset); dsb(); } while (0)
-
-void __sramfunc rk30_pwm_logic_suspend_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
-
-// int gpio0d7_iomux,gpio0d7_do,gpio0d7_dir,gpio0d7_en;
- sram_udelay(10000);
- gpio0d4_iomux = readl_relaxed(GRF_GPIO0D_IOMUX);
- gpio0d4_do = gpio0_readl(GPIO_SWPORTA_DR);
- gpio0d4_dir = gpio0_readl(GPIO_SWPORTA_DDR);
-
- writel_relaxed((gpio0d4_iomux |(1<<24)) & (~(1<<8)), GRF_GPIO0D_IOMUX);
- gpio0_writel(gpio0d4_dir |(1<<28), GPIO_SWPORTA_DDR);
- gpio0_writel(gpio0d4_do |(1<<28), GPIO_SWPORTA_DR);
-
-#endif
-}
-void __sramfunc rk30_pwm_logic_resume_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- writel_relaxed((1<<24)|gpio0d4_iomux, GRF_GPIO0D_IOMUX);
- gpio0_writel(gpio0d4_dir, GPIO_SWPORTA_DDR);
- gpio0_writel(gpio0d4_do, GPIO_SWPORTA_DR);
- sram_udelay(10000);
-
-#endif
-
-}
-extern void pwm_suspend_voltage(void);
-extern void pwm_resume_voltage(void);
-void rk30_pwm_suspend_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_suspend_voltage();
-#endif
-}
-void rk30_pwm_resume_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_resume_voltage();
-#endif
-}
-
-void __sramfunc board_pmu_suspend(void)
-{
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_suspend();
- #endif
-}
-void __sramfunc board_pmu_resume(void)
-{
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_resume();
- #endif
-}
-
-#ifdef CONFIG_I2C1_RK30
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_GS_MMA7660)
- {
- .type = "gs_mma7660",
- .addr = 0x4c,
- .flags = 0,
- .irq = MMA7660_INT_PIN,
- .platform_data = &mma7660_info,
- },
-#endif
-#if defined (CONFIG_GS_MXC6225)
- {
- .type = "gs_mxc6225",
- .addr = 0x15,
- .flags = 0,
- .irq = MXC6225_INT_PIN,
- .platform_data = &mxc6225_info,
- },
-#endif
-};
-#endif
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-
-#if defined (CONFIG_TOUCHSCREEN_GT811_IIC)
- {
- .type = "gt811_ts",
- .addr = 0x5d,
- .flags = 0,
- .irq = TOUCH_INT_PIN,
- .platform_data = >811_info,
- },
-#endif
-
-#if defined (CONFIG_TOUCHSCREEN_SITRONIX_A720)
-{
- .type ="sitronix",
- .addr = 0x60,
- .flags = 0,
- .irq = TOUCH_INT_PIN,
- .platform_data = &sitronix_info,
-},
-#endif
-};
-#endif
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- //set iomux (gpio) here
-
- return 0;
-}
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(4, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-
-#define POWER_ON_PIN RK2928_PIN1_PA1 //power_hold
-#if defined(CONFIG_REGULATOR_ACT8931)
-extern int act8931_charge_det ;
-#endif
-static void rk2928_pm_power_off(void)
-{
- printk(KERN_ERR "rk2928_pm_power_off start...\n");
-
- #if defined(CONFIG_REGULATOR_ACT8931)
- if(pmic_is_act8931())
- {
- #ifdef CONFIG_BATTERY_RK30_ADC_FAC
- if (gpio_get_value (rk30_adc_battery_platdata.dc_det_pin) == rk30_adc_battery_platdata.dc_det_level)//if(act8931_charge_det)
- arm_pm_restart(0, NULL);
- #endif
- act8931_device_shutdown();
- }
- #endif
-
- #if defined(CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- {
- tps65910_device_shutdown();//tps65910 shutdown
- }
- #endif
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
-
-};
-
-static void __init rk2928_board_init(void)
-{
- gpio_request(POWER_ON_PIN, "poweronpin");
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
- pm_power_off = rk2928_pm_power_off;
-
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- rk29sdk_wifi_bt_gpio_control_init();
-#endif
-}
-
-static void __init rk2928_reserve(void)
-{
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0", RK30_FB0_MEM_SIZE);
- resource_fb[0].end = resource_fb[0].start + RK30_FB0_MEM_SIZE - 1;
-#endif
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
- board_mem_reserved();
-}
-/**
- * dvfs_cpu_logic_table: table for arm and logic dvfs
- * @frequency : arm frequency
- * @cpu_volt : arm voltage depend on frequency
- * @logic_volt : logic voltage arm requests depend on frequency
- * comments : min arm/logic voltage
- */
-static struct dvfs_arm_table dvfs_cpu_logic_table[] = {
- {.frequency = 216 * 1000, .cpu_volt = 850 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 312 * 1000, .cpu_volt = 900 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 408 * 1000, .cpu_volt = 950 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 504 * 1000, .cpu_volt = 1000 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 600 * 1000, .cpu_volt = 1100 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 696 * 1000, .cpu_volt = 1175 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 816 * 1000, .cpu_volt = 1250 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 912 * 1000, .cpu_volt = 1350 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 1008 * 1000, .cpu_volt = 1450 * 1000, .logic_volt = 1200 * 1000},
-#if 0
- {.frequency = 1104 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 1200 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 1104 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 1248 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
-#endif
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- {.frequency = 266 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1275 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1125 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
-static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
-static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
-
-void __init board_clock_init(void)
-{
- rk2928_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
- dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
- //dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
- printk("%s end\n", __func__);
-}
-
-
-MACHINE_START(RK2928, "RK2928board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk2928_fixup,
- .reserve = &rk2928_reserve,
- .map_io = rk2928_map_io,
- .init_irq = rk2928_init_irq,
- .timer = &rk2928_timer,
- .init_machine = rk2928_board_init,
-MACHINE_END
+++ /dev/null
-#ifdef CONFIG_VIDEO_RK29
-#include <plat/rk_camera.h>
-/* Notes:
-
-Simple camera device registration:
-
- new_camera_device(sensor_name,\ // sensor name, it is equal to CONFIG_SENSOR_X
- face,\ // sensor face information, it can be back or front
- pwdn_io,\ // power down gpio configuration, it is equal to CONFIG_SENSOR_POWERDN_PIN_XX
- flash_attach,\ // sensor is attach flash or not
- mir,\ // sensor image mirror and flip control information
- i2c_chl,\ // i2c channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_IIC_ADAPTER_ID_X
- cif_chl) \ // cif channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_CIF_INDEX_X
-
-Comprehensive camera device registration:
-
- new_camera_device_ex(sensor_name,\
- face,\
- ori,\ // sensor orientation, it is equal to CONFIG_SENSOR_ORIENTATION_X
- pwr_io,\ // sensor power gpio configuration, it is equal to CONFIG_SENSOR_POWER_PIN_XX
- pwr_active,\ // sensor power active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- rst_io,\ // sensor reset gpio configuration, it is equal to CONFIG_SENSOR_RESET_PIN_XX
- rst_active,\ // sensor reset active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- pwdn_io,\
- pwdn_active,\ // sensor power down active level, is equal to CONFIG_SENSOR_POWERDNACTIVE_LEVEL_X
- flash_attach,\
- res,\ // sensor resolution, this is real resolution or resoltuion after interpolate
- mir,\
- i2c_chl,\
- i2c_spd,\ // i2c speed , 100000 = 100KHz
- i2c_addr,\ // the i2c slave device address for sensor
- cif_chl,\
- mclk)\ // sensor input clock rate, 24 or 48
-
-*/
-static struct rkcamera_platform_data new_camera[] = {
- new_camera_device(RK29_CAM_SENSOR_OV5642,
- back,
- RK2928_PIN3_PB3,
- 0,
- 0,
- 0,
- 0),
- new_camera_device_end
-};
-/*---------------- Camera Sensor Macro Define Begin ------------------------*/
-/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
-#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_OV5642 /* back camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_0 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 0
-#define CONFIG_SENSOR_CIF_INDEX_0 0
-#define CONFIG_SENSOR_ORIENTATION_0 90
-#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 RK2928_PIN3_PB3
-#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000
-
-#define CONFIG_SENSOR_01 RK29_CAM_SENSOR_OV5642 /* back camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_01 0x00
-#define CONFIG_SENSOR_CIF_INDEX_01 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 4
-#define CONFIG_SENSOR_ORIENTATION_01 90
-#define CONFIG_SENSOR_POWER_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_01 RK2928_PIN3_PB3
-#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_01 30000
-
-#define CONFIG_SENSOR_02 RK29_CAM_SENSOR_OV5640 /* back camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_02 0x00
-#define CONFIG_SENSOR_CIF_INDEX_02 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 4
-#define CONFIG_SENSOR_ORIENTATION_02 90
-#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_02 RK2928_PIN3_PB3
-#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000
-
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_OV2659 /* front camera sensor 0 */
-#define CONFIG_SENSOR_IIC_ADDR_1 0// 0x60
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 3
-#define CONFIG_SENSOR_CIF_INDEX_1 0
-#define CONFIG_SENSOR_ORIENTATION_1 270
-#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_1 RK2928_PIN3_PB3
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000
-
-#define CONFIG_SENSOR_11 RK29_CAM_SENSOR_OV2659 /* front camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_11 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 3
-#define CONFIG_SENSOR_CIF_INDEX_11 0
-#define CONFIG_SENSOR_ORIENTATION_11 270
-#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_11 30000
-
-#define CONFIG_SENSOR_12 RK29_CAM_SENSOR_OV2659//RK29_CAM_SENSOR_OV2655 /* front camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_12 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 3
-#define CONFIG_SENSOR_CIF_INDEX_12 0
-#define CONFIG_SENSOR_ORIENTATION_12 270
-#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_12 30000
-
-
-#endif //#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk2928_camera.c"
-/*---------------- Camera Sensor Macro Define End ---------*/
-
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#define CONFIG_SENSOR_POWER_IOCTL_USR 0 //define this refer to your board layout
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
-
-static void rk_cif_power(int on)
-{
- struct regulator *ldo_18,*ldo_28;
- ldo_28 = regulator_get(NULL, "ldo7"); // vcc28_cif
- ldo_18 = regulator_get(NULL, "ldo1"); // vcc18_cif
- if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){
- printk("get cif ldo failed!\n");
- return;
- }
- if(on == 0){
- regulator_disable(ldo_28);
- regulator_put(ldo_28);
- regulator_disable(ldo_18);
- regulator_put(ldo_18);
- mdelay(500);
- }
- else{
- regulator_set_voltage(ldo_28, 2800000, 2800000);
- regulator_enable(ldo_28);
- // printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
- regulator_put(ldo_28);
-
- regulator_set_voltage(ldo_18, 1800000, 1800000);
- // regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(ldo_18);
- // printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
- regulator_put(ldo_18);
- }
-}
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- //#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
- rk_cif_power(on);
-}
-#endif
-
-#if CONFIG_SENSOR_RESET_IOCTL_USR
-static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
-static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-
-#if CONFIG_SENSOR_IIC_ADDR_0
-static struct reginfo_t rk_init_data_sensor_reg_0[] =
-{
- {0x0000, 0x00,0,0}
- };
-static struct reginfo_t rk_init_data_sensor_winseqreg_0[] ={
- {0x0000, 0x00,0,0}
- };
-#endif
-
-#if CONFIG_SENSOR_IIC_ADDR_1
-static struct reginfo_t rk_init_data_sensor_reg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_01
-static struct reginfo_t rk_init_data_sensor_reg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_02
-static struct reginfo_t rk_init_data_sensor_reg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_11
-static struct reginfo_t rk_init_data_sensor_reg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_12
-static struct reginfo_t rk_init_data_sensor_reg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] =
-{
- #if CONFIG_SENSOR_IIC_ADDR_0
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_0,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_1
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_1,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_01
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_01,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_02
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_02,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_11
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_11,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_12
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_12,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
-
- };
-#include "../../../drivers/media/video/rk2928_camera.c"
-
-#endif /* CONFIG_VIDEO_RK29 */
+++ /dev/null
-#include <mach/gpio.h>
-#include <plat/key.h>
-
-#define EV_ENCALL KEY_F4
-#define EV_MENU KEY_F1
-
-#define PRESS_LEV_LOW 1
-#define PRESS_LEV_HIGH 0
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- #if defined(CONFIG_MACH_RK2928_TB)
- .gpio = RK2928_PIN0_PD1,
- #elif defined(CONFIG_MACH_RK2926_TB)
- .gpio = RK2928_PIN2_PB6,
- #endif
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "play",
- .code = KEY_POWER,
- #if defined(CONFIG_MACH_RK2928_TB)
- .gpio = RK2928_PIN3_PC5,
- #elif defined(CONFIG_MACH_RK2926_TB)
- .gpio = RK2928_PIN1_PA4,
- #endif
- .active_low = PRESS_LEV_LOW,
- //.code_long_press = EV_ENCALL,
- .wakeup = 1,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .adc_value = 1,
- .gpio = INVALID_GPIO,
- //.gpio = RK2928_PIN0_PD0,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "menu",
- .code = EV_MENU,
- .adc_value = 135,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .adc_value = 550,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .adc_value = 334,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "camera",
- .code = KEY_CAMERA,
- .adc_value = 700,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = 1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
+++ /dev/null
-/* arch/arm/mach-rk2928/board-rk2928-fpga.c
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-#include <mach/dvfs.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <linux/fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/mfd/tps65910.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-#if defined(CONFIG_HDMI_RK30)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-
-#ifdef CONFIG_SND_SOC_RK2928
-#include "../../../sound/soc/codecs/rk2928_codec.h"
-#endif
-
-#if defined(CONFIG_GPS_RK)
-#include "../../../drivers/misc/gps/rk_gps/rk_gps.h"
-#endif
-
-//#define RK2928L_TB_OLD
-
-
-int __sramdata g_pmic_type = 0;
-
-#include "board-rk2928-tb-camera.c"
-#include "board-rk2928-tb-key.c"
-
-#if defined (CONFIG_EETI_EGALAX)
-#if defined (CONFIG_MACH_RK2928_TB)
-#define TOUCH_RESET_PIN RK2928_PIN3_PC3
-#define TOUCH_INT_PIN RK2928_PIN3_PC7
-#elif defined (CONFIG_MACH_RK2926_TB)
-#if defined (RK2928L_TB_OLD)
-#define TOUCH_RESET_PIN RK2928_PIN1_PA3
-#define TOUCH_INT_PIN RK2928_PIN1_PB3
-#else
-#define TOUCH_RESET_PIN RK2928_PIN2_PB0
-#define TOUCH_INT_PIN RK2928_PIN1_PB0
-#endif
-#endif
-
-
-static int EETI_EGALAX_init_platform_hw(void)
-{
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("p1003_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_pull_updown(TOUCH_INT_PIN, 1);
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
-
- return 0;
-}
-
-
-static struct eeti_egalax_platform_data eeti_egalax_info = {
- .model= 1003,
- .init_platform_hw= EETI_EGALAX_init_platform_hw,
- .standby_pin = INVALID_GPIO,
- //.standby_value = GPIO_HIGH,
- .disp_on_pin = INVALID_GPIO,
- //.disp_on_value = GPIO_HIGH,
-};
-#endif
-
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-#define PWM_ID 0
-#define PWM_MUX_NAME GPIO0D2_PWM_0_NAME
-#define PWM_MUX_MODE GPIO0D_PWM_0
-#define PWM_MUX_MODE_GPIO GPIO0D_GPIO0D2
-#define PWM_GPIO RK2928_PIN0_PD2
-#define PWM_EFFECT_VALUE 1
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-#if defined(CONFIG_MACH_RK2928_TB)
-#define BL_EN_PIN RK2928_PIN3_PC4
-#define BL_EN_VALUE GPIO_HIGH
-#elif defined(CONFIG_MACH_RK2926_TB)
-#if defined(RK2928L_TB_OLD)
-#define BL_EN_PIN RK2928_PIN1_PB0
-#define BL_EN_VALUE GPIO_HIGH
-#else
-#define BL_EN_PIN RK2928_PIN2_PC1
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-#endif
-
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
-#ifdef LCD_DISP_ON_PIN
- // rk30_mux_api_set(BL_EN_MUX_NAME, BL_EN_MUX_MODE);
-
- ret = gpio_request(BL_EN_PIN, NULL);
- if (ret != 0) {
- gpio_free(BL_EN_PIN);
- }
-
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0;
-#ifdef LCD_DISP_ON_PIN
- gpio_free(BL_EN_PIN);
-#endif
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret = 0;
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- if (gpio_request(PWM_GPIO, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- gpio_direction_output(PWM_GPIO, GPIO_LOW);
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, !BL_EN_VALUE);
-#endif
-
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- gpio_free(PWM_GPIO);
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
-#ifdef LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, 1);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-#endif
-
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-
-static int mma8452_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data mma8452_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma8452_init_platform_hw,
- .orientation = {-1, 0, 0, 0, -1, 0, 0, 0, 1},
-};
-#endif
-
-#ifdef CONFIG_FB_ROCKCHIP
-
-#if defined (CONFIG_MACH_RK2928_TB)
-#define LCD_CABC_EN RK2928_PIN2_PD1
-#define LCD_CABC_EN_VALUE GPIO_HIGH
-#elif defined (CONFIG_MACH_RK2926_TB)
-#define LCD_CABC_EN RK2928_PIN2_PC3
-#define LCD_CABC_EN_VALUE GPIO_HIGH
-#endif
-
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
-
-#if defined (CONFIG_MACH_RK2926_TB)
-#endif
-
- ret = gpio_request(LCD_CABC_EN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_CABC_EN);
- printk(KERN_ERR "request lcd cabc en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_CABC_EN, !LCD_CABC_EN_VALUE); //disable
- }
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- return 0;
-}
-
-#if defined(CONFIG_LCDC_RK2928)
-struct rk29fb_info lcdc_screen_info = {
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-
-//LCDC
-#ifdef CONFIG_LCDC_RK2928
-static struct resource resource_lcdc[] = {
- [0] = {
- .name = "lcdc reg",
- .start = RK2928_LCDC_PHYS,
- .end = RK2928_LCDC_PHYS + RK2928_LCDC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc irq",
- .start = IRQ_LCDC,
- .end = IRQ_LCDC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc = {
- .name = "rk2928-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc),
- .resource = resource_lcdc,
- .dev = {
- .platform_data = &lcdc_screen_info,
- },
-};
-#endif
-
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_RK30_PWM_REGULATOR
-const static int pwm_voltage_map[] = {
- 950000,975000,1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000, 1375000, 1400000
-};
-
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_core",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] =
-{
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
-#if defined (CONFIG_MACH_RK2928_TB)
- .pwm_id = 2,
- .pwm_gpio = RK2928_PIN0_PD4,
- .pwm_iomux_name = GPIO0D4_PWM_2_NAME,
- .pwm_iomux_pwm = GPIO0D_PWM_2,
- .pwm_iomux_gpio = GPIO0D_GPIO0D4,
-#elif defined (CONFIG_MACH_RK2926_TB)
- .pwm_id = 1,
- .pwm_gpio = RK2928_PIN0_PD3,
- .pwm_iomux_name = GPIO0D3_PWM_1_NAME,
- .pwm_iomux_pwm = GPIO0D_PWM_1,
- .pwm_iomux_gpio = GPIO0D_GPIO0D3,
-#endif
- .pwm_voltage = 1200000,
- .suspend_voltage = 1050000,
- .min_uV = 950000,
- .max_uV = 1400000,
- .coefficient = 504, //50.4%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-#endif
-
-/***********************************************************
-* usb wifi
-************************************************************/
-#if defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU)
-
-static void rkusb_wifi_power(int on) {
-#if 0
- struct regulator *ldo = NULL;
-
-#if defined(CONFIG_MFD_TPS65910)
- if (pmic_is_tps65910() )
- ldo = regulator_get(NULL, "vmmc"); //vccio_wl
-#endif
-#if defined(CONFIG_REGULATOR_ACT8931)
- if(pmic_is_act8931() )
- ldo = regulator_get(NULL, "act_ldo4"); //vccio_wl
-#endif
-
- if(on) {
- regulator_enable(ldo);
- printk("%s: vccio_wl enable\n", __func__);
- } else {
- printk("%s: vccio_wl disable\n", __func__);
- regulator_disable(ldo);
- }
-
- regulator_put(ldo);
- udelay(100);
-#endif
-}
-
-#endif
-
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and sdio.noted by xbw at 2012-03-05
-**************************************************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "board-rk2928-sdk-sdmmc.c"
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
-#define SDMMC0_WRITE_PROTECT_PIN RK2928_PIN1_PA7 //According to your own project to set the value of write-protect-pin.
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
-#define SDMMC1_WRITE_PROTECT_PIN RK2928_PIN0_PD5 //According to your own project to set the value of write-protect-pin.
-#endif
-
-#define RK29SDK_WIFI_SDIO_CARD_DETECT_N RK2928_PIN0_PB2
-
-#define RK29SDK_SD_CARD_DETECT_N RK2928_PIN2_PA7 //According to your own project to set the value of card-detect-pin.
-#define RK29SDK_SD_CARD_INSERT_LEVEL GPIO_LOW // set the voltage of insert-card. Please pay attention to the default setting.
-
-
-#endif //endif ---#ifdef CONFIG_SDMMC_RK29
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
-#if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- rk30_mux_api_set(GPIO1C1_MMC0_DETN_NAME, GPIO1C_GPIO1C1);
- // gpio_request(RK29SDK_SD_CARD_DETECT_N, "sd-detect");
- // gpio_direction_output(RK29SDK_SD_CARD_DETECT_N,GPIO_HIGH);//set mmc0-data1 to high.
-#else
- rk30_mux_api_set(GPIO1C1_MMC0_DETN_NAME, GPIO1C_MMC0_DETN);
-#endif
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- .detect_irq = RK29SDK_SD_CARD_DETECT_N,
- .insert_card_level = RK29SDK_SD_CARD_INSERT_LEVEL,
-#else
- .detect_irq = RK2928_PIN1_PC1, //INVALID_GPIO,
-#endif
- .enable_sd_wakeup = 0,
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
-#else
- .write_prt = INVALID_GPIO,
-#endif
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- rk30_mux_api_set(GPIO0B0_MMC1_CMD_NAME, GPIO0B_MMC1_CMD);
- rk30_mux_api_set(GPIO0B1_MMC1_CLKOUT_NAME, GPIO0B_MMC1_CLKOUT);
- rk30_mux_api_set(GPIO0B3_MMC1_D0_NAME, GPIO0B_MMC1_D0);
- rk30_mux_api_set(GPIO0B4_MMC1_D1_NAME, GPIO0B_MMC1_D1);
- rk30_mux_api_set(GPIO0B5_MMC1_D2_NAME, GPIO0B_MMC1_D2);
- rk30_mux_api_set(GPIO0B6_MMC1_D3_NAME, GPIO0B_MMC1_D3);
- //rk30_mux_api_set(GPIO0B2_MMC1_DETN_NAME, GPIO0B_MMC1_DETN);
-
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-#if 0
- .detect_irq = RK29SDK_WIFI_SDIO_CARD_DETECT_N,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
-#else
- .detect_irq = INVALID_GPIO,
- .enable_sd_wakeup = 0,
-#endif
-
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-/**************************************************************************************************
- * the end of setting for SDMMC devices
-**************************************************************************************************/
-
-
-
-#ifdef CONFIG_RFKILL_RK
-// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
-static struct rfkill_rk_platform_data rfkill_rk_platdata = {
-#if defined (CONFIG_MACH_RK2928_TB)
- .type = RFKILL_TYPE_BLUETOOTH,
-
- .poweron_gpio = { // BT_REG_ON
- .io = INVALID_GPIO,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK2928_PIN3_PD5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = NULL,
- },
- },
-
- .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
- .io = RK2928_PIN0_PC6, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .gpio = {
- .io = RK2928_PIN0_PC5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
- .iomux = {
- .name = NULL,
- },
- },
- },
-
- .rts_gpio = { // UART_RTS, enable or disable BT's data coming
- .io = RK2928_PIN0_PC3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = GPIO0C3_UART0_CTSN_NAME,
- .fgpio = GPIO0C_GPIO0C3,
- .fmux = GPIO0C_UART0_CTSN,
- },
- },
-#endif
-};
-
-static struct platform_device device_rfkill_rk = {
- .name = "rfkill_rk",
- .id = -1,
- .dev = {
- .platform_data = &rfkill_rk_platdata,
- },
-};
-#endif
-
-#ifdef CONFIG_SND_SOC_RK2928
-static int hpctl_io_init(void)
-{
- int ret=0;
- return ret;
-}
-
-struct rk2928_codec_pdata rk2928_codec_pdata_info={
- .hpctl = INVALID_GPIO,
- .hpctl_io_init = hpctl_io_init,
-};
-
-static struct resource resources_acodec[] = {
- {
- .start = RK2928_ACODEC_PHYS,
- .end = RK2928_ACODEC_PHYS + RK2928_ACODEC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- #if defined (CONFIG_MACH_RK2928_TB)
- .start = RK2928_PIN3_PD4,
- .end = RK2928_PIN3_PD4,
- #elif defined (CONFIG_MACH_RK2926_TB)
- .start = RK2928_PIN1_PA0,
- .end = RK2928_PIN1_PA0,
- #endif
- .flags = IORESOURCE_IO,
- },
-};
-
-static struct platform_device device_acodec = {
- .name = "rk2928-codec",
- .id = -1,
- .num_resources = ARRAY_SIZE(resources_acodec),
- .resource = resources_acodec,
- .dev = {
- .platform_data = &rk2928_codec_pdata_info,
- }
-};
-#endif
-
-#if defined(CONFIG_GPS_RK)
-int rk_gps_io_init(void)
-{
- printk("%s \n", __FUNCTION__);
- rk30_mux_api_set(GPIO1B1_SPI_TXD_UART1_SOUT_NAME, GPIO1B_GPIO1B1);//VCC_EN
- gpio_request(RK2928_PIN1_PB1, NULL);
- gpio_direction_output(RK2928_PIN1_PB1, GPIO_LOW);
-
- rk30_mux_api_set(GPIO1A2_I2S_LRCKRX_GPS_CLK_NAME, GPIO1A_GPS_CLK);//GPS_CLK
- rk30_mux_api_set(GPIO1A4_I2S_SDO_GPS_MAG_NAME, GPIO1A_GPS_MAG);//GPS_MAG
- rk30_mux_api_set(GPIO1A5_I2S_SDI_GPS_SIGN_NAME, GPIO1A_GPS_SIGN);//GPS_SIGN
-
- rk30_mux_api_set(GPIO1B0_SPI_CLK_UART1_CTSN_NAME, GPIO1B_GPIO1B0);//SPI_CLK
- gpio_request(RK2928_PIN1_PB0, NULL);
- gpio_direction_output(RK2928_PIN1_PB0, GPIO_LOW);
-
- rk30_mux_api_set(GPIO1B2_SPI_RXD_UART1_SIN_NAME, GPIO1B_GPIO1B2);//SPI_MOSI
- gpio_request(RK2928_PIN1_PB2, NULL);
- gpio_direction_output(RK2928_PIN1_PB2, GPIO_LOW);
-
- rk30_mux_api_set(GPIO1B3_SPI_CSN0_UART1_RTSN_NAME, GPIO1B_GPIO1B3);//SPI_CS
- gpio_request(RK2928_PIN1_PB3, NULL);
- gpio_direction_output(RK2928_PIN1_PB3, GPIO_LOW);
- return 0;
-}
-int rk_gps_power_up(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_power_down(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_reset_set(int level)
-{
- return 0;
-}
-int rk_enable_hclk_gps(void)
-{
- printk("%s \n", __FUNCTION__);
- clk_enable(clk_get(NULL, "aclk_gps"));
- return 0;
-}
-int rk_disable_hclk_gps(void)
-{
- printk("%s \n", __FUNCTION__);
- clk_disable(clk_get(NULL, "aclk_gps"));
- return 0;
-}
-struct rk_gps_data rk_gps_info = {
- .io_init = rk_gps_io_init,
- .power_up = rk_gps_power_up,
- .power_down = rk_gps_power_down,
- .reset = rk_gps_reset_set,
- .enable_hclk_gps = rk_enable_hclk_gps,
- .disable_hclk_gps = rk_disable_hclk_gps,
- .GpsSign = RK2928_PIN1_PA5,
- .GpsMag = RK2928_PIN1_PA4, //GPIO index
- .GpsClk = RK2928_PIN1_PA2, //GPIO index
- .GpsVCCEn = RK2928_PIN1_PB1, //GPIO index
- .GpsSpi_CSO = RK2928_PIN1_PB3, //GPIO index
- .GpsSpiClk = RK2928_PIN1_PB0, //GPIO index
- .GpsSpiMOSI = RK2928_PIN1_PB2, //GPIO index
- .GpsIrq = IRQ_GPS,
- .GpsSpiEn = 1,
- .GpsAdcCh = 2,
- .u32GpsPhyAddr = RK2928_GPS_PHYS,
- .u32GpsPhySize = RK2928_GPS_SIZE,
-};
-
-struct platform_device rk_device_gps = {
- .name = "gps_hv5820b",
- .id = -1,
- .dev = {
- .platform_data = &rk_gps_info,
- }
- };
-#endif
-
-
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_FB_ROCKCHIP
- &device_fb,
-#endif
-#ifdef CONFIG_LCDC_RK2928
- &device_lcdc,
-#endif
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- &rk29_device_backlight,
-#endif
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- &rk29sdk_wifi_device,
-#endif
-#ifdef CONFIG_RFKILL_RK
- &device_rfkill_rk,
-#endif
-#ifdef CONFIG_SND_SOC_RK2928
- &device_acodec,
-#endif
-#ifdef CONFIG_GPS_RK
- &rk_device_gps,
-#endif
-
-};
-//i2c
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1d,
- .flags = 0,
- #if defined(CONFIG_MACH_RK2928_TB)
- .irq = RK2928_PIN3_PD1,
- #elif defined(CONFIG_MACH_RK2926_TB)
- #if defined(RK2928L_TB_OLD)
- .irq = RK2928_PIN1_PB1,
- #else
- .irq = RK2928_PIN1_PB2,
- #endif
- #endif
- .platform_data = &mma8452_info,
- },
-#endif
-};
-#endif
-#ifdef CONFIG_I2C1_RK30
-#ifdef CONFIG_MFD_TPS65910
-#if defined(CONFIG_MACH_RK2928_TB)
-#define TPS65910_HOST_IRQ RK2928_PIN3_PC6
-#elif defined(CONFIG_MACH_RK2926_TB)
-#if defined(CONFIG_MACH_RK2926_TB)
-#define TPS65910_HOST_IRQ RK2928_PIN1_PB2
-#else
-#define TPS65910_HOST_IRQ RK2928_PIN1_PB1
-#endif
-#endif
-#define PMU_POWER_SLEEP RK2928_PIN1_PA1
-
-static struct pmu_info tps65910_dcdc_info[] = {
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vdd2", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vio", //vcc_io
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
-
-};
-static struct pmu_info tps65910_ldo_info[] = {
- #if defined(CONFIG_MACH_RK2928_TB) || defined(CONFIG_MACH_RK2926_TB)
- {
- .name = "vpll", //vcc25
- .min_uv = 2500000,
- .max_uv = 2500000,
- },
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "vdac", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- #else
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 1500000,
- .max_uv = 1500000,
- },
-
- {
- .name = "vdig2", //vdd11
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vaux1", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "vaux2", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vaux33", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vmmc", //
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- #endif
- };
-
-#include "board-rk2928-sdk-tps65910.c"
-#endif
-
-static struct i2c_board_info __initdata i2c1_info[] = {
-
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-
-};
-#endif
-
-void __sramfunc board_pmu_suspend(void)
-{
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910() )
- board_pmu_tps65910_suspend();
- #endif
-}
-void __sramfunc board_pmu_resume(void)
-{
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910() )
- board_pmu_tps65910_resume();
- #endif
-}
-
-
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-#if defined (CONFIG_EETI_EGALAX)
- {
- .type = "egalax_i2c",
- .addr = 0x04,
- .flags = 0,
- .irq = TOUCH_INT_PIN,
- .platform_data = &eeti_egalax_info,
- },
-#endif
-};
-#endif
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- //set iomux (gpio) here
-
- return 0;
-}
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(4, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-#if defined (CONFIG_MACH_RK2928_TB)
-#define POWER_ON_PIN RK2928_PIN1_PB4 //power_hold
-#elif defined (CONFIG_MACH_RK2926_TB)
-#define POWER_ON_PIN RK2928_PIN1_PA2 //power_hold
-#endif
-static void rk2928_pm_power_off(void)
-{
- printk(KERN_ERR "rk2928_pm_power_off start...\n");
-
- #if defined(CONFIG_MFD_TPS65910)
- tps65910_device_shutdown();//tps65910 shutdown
- #endif
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
-
-};
-
-static void __init rk2928_board_init(void)
-{
- gpio_request(POWER_ON_PIN, "poweronpin");
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
- gpio_free(POWER_ON_PIN);
-
- pm_power_off = rk2928_pm_power_off;
-
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- rk29sdk_wifi_bt_gpio_control_init();
-#endif
-}
-
-static void __init rk2928_reserve(void)
-{
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0", get_fb_size());
- resource_fb[0].end = resource_fb[0].start + get_fb_size()- 1;
-#endif
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
-
-#ifdef CONFIG_GPS_RK
- //it must be more than 8MB
- rk_gps_info.u32MemoryPhyAddr = board_mem_reserve_add("gps", SZ_8M);
-#endif
-
- board_mem_reserved();
-}
-/**
- * dvfs_cpu_logic_table: table for arm and logic dvfs
- * @frequency : arm frequency
- * @cpu_volt : arm voltage depend on frequency
- * @logic_volt : logic voltage arm requests depend on frequency
- * comments : min arm/logic voltage
- */
-static struct dvfs_arm_table dvfs_cpu_logic_table[] = {
- {.frequency = 216 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 312 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 408 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 504 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 600 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 696 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 816 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
- //{.frequency = 912 * 1000, .cpu_volt = 1450 * 1000, .logic_volt = 1200 * 1000},
- //{.frequency = 1008 * 1000, .cpu_volt = 1500 * 1000, .logic_volt = 1200 * 1000},
-#if 0
- {.frequency = 1104 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 1200 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 1104 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 1248 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},
-#endif
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- {.frequency = 266 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1275 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 1050 * 1000},
- {.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = 1050 * 1000},
- {.frequency = 400 * 1000 + DDR_FREQ_NORMAL, .index = 1125 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
-static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
-static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
-
-void __init board_clock_init(void)
-{
- rk2928_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
- dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
- //dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
- printk("%s end\n", __func__);
-}
-
-
-MACHINE_START(RK2928, "RK2928board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk2928_fixup,
- .reserve = &rk2928_reserve,
- .map_io = rk2928_map_io,
- .init_irq = rk2928_init_irq,
- .timer = &rk2928_timer,
- .init_machine = rk2928_board_init,
-MACHINE_END
+++ /dev/null
-/* arch/arm/mach-rk2928/board-rk2928.c
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-#include <mach/dvfs.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <linux/fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/mfd/tps65910.h>
-#include <linux/regulator/act8931.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-
-#include "board-rk2928-config.c"
-#include "board-phonepad.c"
-
-#if defined(CONFIG_HDMI_RK30)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-
-#include "board-rk2928-camera.c"
-#include "board-rk2928-key.c"
-
-
-#ifdef CONFIG_THREE_FB_BUFFER
-#define RK30_FB0_MEM_SIZE 12*SZ_1M
-#else
-#define RK30_FB0_MEM_SIZE 8*SZ_1M
-#endif
-
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
- struct pwm_io_config *cfg = &pwm_cfg[bl_pwm];
-
- ret = gpio_request(cfg->gpio, "bl_pwm");
- if(ret < 0){
- printk("%s: request gpio(bl_pwm) failed\n", __func__);
- return ret;
- }
- rk30_mux_api_set(cfg->mux_name, cfg->pwm_mode);
-
- if(bl_en == -1)
- return 0;
- ret = port_output_init(bl_en, 0, "bl_en");
- if(ret < 0){
- printk("%s: port output init faild\n", __func__);
- return ret;
- }
- port_output_on(bl_en);
-
- return 0;
-}
-static int rk29_backlight_io_deinit(void)
-{
- struct pwm_io_config *cfg = &pwm_cfg[bl_pwm];
-
- port_output_off(bl_en);
- if(bl_en != -1)
- port_deinit(bl_en);
- rk30_mux_api_set(cfg->mux_name, cfg->io_mode);
- gpio_free(cfg->gpio);
-
- return 0;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- struct pwm_io_config *cfg = &pwm_cfg[bl_pwm];
-
- rk30_mux_api_set(cfg->mux_name, cfg->io_mode);
-
- if(bl_ref)
- gpio_direction_output(cfg->gpio, GPIO_LOW);
- else
- gpio_direction_output(cfg->gpio, GPIO_HIGH);
-
- port_output_off(bl_en);
-
- return 0;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- struct pwm_io_config *cfg = &pwm_cfg[bl_pwm];
-
- rk30_mux_api_set(cfg->mux_name, cfg->pwm_mode);
- msleep(30);
- port_output_on(bl_en);
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-static int __init bl_board_init(void)
-{
- int ret = check_bl_param();
-
- if(ret < 0)
- return ret;
-
- rk29_bl_info.pwm_id = bl_pwm;
- rk29_bl_info.bl_ref = bl_ref;
- rk29_bl_info.min_brightness = bl_min;
-
- return 0;
-}
-
-#else
-static int __init bl_board_init(void)
-{
- return 0;
-}
-#endif
-
-#ifdef CONFIG_FB_ROCKCHIP
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
-
- if(lcd_cabc != -1){
- ret = port_output_init(lcd_cabc, 0, "lcd_cabc");
- if(ret < 0)
- printk("%s: port output init faild\n", __func__);
- }
- if(lcd_en == -1)
- return 0;
- ret = port_output_init(lcd_en, 1, "lcd_en");
- if(ret < 0)
- printk("%s: port output init faild\n", __func__);
-
- return ret;
-}
-static int rk_fb_io_disable(void)
-{
- if(lcd_en != -1)
- port_output_off(lcd_en);
-
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- if(lcd_en != -1)
- port_output_on(lcd_en);
- return 0;
-}
-
-#if defined(CONFIG_LCDC_RK2928)
-struct rk29fb_info lcdc_screen_info = {
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-
-static int __init lcd_board_init(void)
-{
- return check_lcd_param();
-}
-#else
-static int __init lcd_board_init(void)
-{
- return 0;
-}
-#endif
-
-//LCDC
-#ifdef CONFIG_LCDC_RK2928
-static struct resource resource_lcdc[] = {
- [0] = {
- .name = "lcdc reg",
- .start = RK2928_LCDC_PHYS,
- .end = RK2928_LCDC_PHYS + RK2928_LCDC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc irq",
- .start = IRQ_LCDC,
- .end = IRQ_LCDC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc = {
- .name = "rk2928-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc),
- .resource = resource_lcdc,
- .dev = {
- .platform_data = &lcdc_screen_info,
- },
-};
-#endif
-
-#ifdef CONFIG_ION
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-static int __init ion_board_init(void)
-{
- int ret = check_ion_param();
-
- if(ret < 0)
- return ret;
- rk30_ion_pdata.heaps[0].size = ion_size;
-
- return 0;
-}
-#else
-static int __init ion_board_init(void)
-{
- return 0;
-}
-#endif
-
-#if CONFIG_RK30_PWM_REGULATOR
-static int pwm_voltage_map[] = {
- 950000,975000,1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000, 1375000, 1400000
-};
-
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_core",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] =
-{
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
- .pwm_voltage = 1200000,
- .suspend_voltage = 1050000,
- .min_uV = 950000,
- .max_uV = 1400000,
- .coefficient = 504, //50.4%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-
-static int __init pwm_reg_board_init(void)
-{
- struct pwm_io_config *cfg;
- int ret = check_reg_pwm_param();
-
- if(ret < 0)
- return ret;
-
- cfg = &pwm_cfg[reg_pwm];
- pwm_regulator_info[0].pwm_id = reg_pwm;
- pwm_regulator_info[0].pwm_iomux_name = cfg->mux_name;
- pwm_regulator_info[0].pwm_iomux_pwm = cfg->pwm_mode;
- pwm_regulator_info[0].pwm_iomux_gpio = cfg->io_mode;
- pwm_regulator_info[0].pwm_gpio = cfg->gpio;
-
- return 0;
-}
-#else
-static int __init pwm_reg_board_init(void)
-{
- return 0;
-}
-#endif
-/***********************************************************
-* usb wifi
-************************************************************/
-#if defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU)
-static void rkusb_wifi_power(int on) {
-
- pmic_ldo_set(wifi_ldo, on);
- udelay(100);
-}
-#endif
-
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and sdio.noted by xbw at 2012-03-05
-**************************************************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "board-rk2928-sdk-sdmmc.c"
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
-#define SDMMC0_WRITE_PROTECT_PIN RK2928_PIN1_PA7 //According to your own project to set the value of write-protect-pin.
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
-#define SDMMC1_WRITE_PROTECT_PIN RK2928_PIN0_PD5 //According to your own project to set the value of write-protect-pin.
-#endif
-
-#define RK29SDK_WIFI_SDIO_CARD_DETECT_N RK2928_PIN0_PB2
-
-#define RK29SDK_SD_CARD_DETECT_N RK2928_PIN2_PA7 //According to your own project to set the value of card-detect-pin.
-#define RK29SDK_SD_CARD_INSERT_LEVEL GPIO_LOW // set the voltage of insert-card. Please pay attention to the default setting.
-
-
-#endif //endif ---#ifdef CONFIG_SDMMC_RK29
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
-#if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- rk30_mux_api_set(GPIO1C1_MMC0_DETN_NAME, GPIO1C_GPIO1C1);
- // gpio_request(RK29SDK_SD_CARD_DETECT_N, "sd-detect");
- // gpio_direction_output(RK29SDK_SD_CARD_DETECT_N,GPIO_HIGH);//set mmc0-data1 to high.
-#else
- rk30_mux_api_set(GPIO1C1_MMC0_DETN_NAME, GPIO1C_MMC0_DETN);
-#endif
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- .detect_irq = RK29SDK_SD_CARD_DETECT_N,
- .insert_card_level = RK29SDK_SD_CARD_INSERT_LEVEL,
-#else
- .detect_irq = INVALID_GPIO,
-#endif
-
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
-#else
- .write_prt = INVALID_GPIO,
-#endif
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
-static int __init sdmmc_board_init(void)
-{
- struct port_config port;
- int ret = check_sdmmc_param();
-
- if(ret < 0)
- return ret;
- if(sd_det == -1)
- return 0;
- port = get_port_config(sd_det);
-
- default_sdmmc0_data.detect_irq = port.gpio;
- default_sdmmc0_data.insert_card_level = !port.io.active_low;
- return 0;
-}
-#else
-static int __init sdmmc_board_init(void)
-{
- return 0;
-}
-#endif
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- rk30_mux_api_set(GPIO0B0_MMC1_CMD_NAME, GPIO0B_MMC1_CMD);
- rk30_mux_api_set(GPIO0B1_MMC1_CLKOUT_NAME, GPIO0B_MMC1_CLKOUT);
- rk30_mux_api_set(GPIO0B3_MMC1_D0_NAME, GPIO0B_MMC1_D0);
- rk30_mux_api_set(GPIO0B4_MMC1_D1_NAME, GPIO0B_MMC1_D1);
- rk30_mux_api_set(GPIO0B5_MMC1_D2_NAME, GPIO0B_MMC1_D2);
- rk30_mux_api_set(GPIO0B6_MMC1_D3_NAME, GPIO0B_MMC1_D3);
- //rk30_mux_api_set(GPIO0B2_MMC1_DETN_NAME, GPIO0B_MMC1_DETN);
-
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-#if 1
- .detect_irq = INVALID_GPIO,//RK29SDK_WIFI_SDIO_CARD_DETECT_N,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
-#else
- .detect_irq = INVALID_GPIO,
- .enable_sd_wakeup = 0,
-#endif
-
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-#ifdef CONFIG_SND_SOC_RK2928
-static struct resource resources_acodec[] = {
- {
- .start = RK2928_ACODEC_PHYS,
- .end = RK2928_ACODEC_PHYS + RK2928_ACODEC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .flags = IORESOURCE_IO,
- },
-};
-
-static struct platform_device device_acodec = {
- .name = "rk2928-codec",
- .id = -1,
- .num_resources = ARRAY_SIZE(resources_acodec),
- .resource = resources_acodec,
-};
-
-static int __init codec_board_init(void)
-{
- int gpio;
- int ret = check_codec_param();
-
- if(ret < 0)
- return ret;
- gpio = get_port_config(spk_ctl).gpio;
- resources_acodec[1].start = gpio;
- resources_acodec[1].end = gpio;
- return 0;
-}
-#else
-static int __init codec_board_init(void)
-{
- return 0;
-}
-#endif
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
-#if defined(CONFIG_REGULATOR_ACT8931)
-extern int act8931_charge_det;
-extern int act8931_charge_ok;
-
-int rk30_battery_adc_io_init(void){
- int ret = 0;
-
- if(dc_det != -1){
- ret = port_input_init(dc_det, "dc_det");
- if (ret) {
- printk("%s: port(%d) input init faild\n", __func__, dc_det);
- return ret ;
- }
- }
- if(chg_ok != -1){
- ret = port_input_init(chg_ok, "chg_ok");
- if (ret) {
- printk("%s: port(%d) input init faild\n", __func__, chg_ok);
- return ret ;
- }
- }
-
- return 0;
-}
-
-int rk30_battery_adc_is_dc_charging(void)
-{
- return act8931_charge_det;
-}
-int rk30_battery_adc_charging_ok(void)
-{
- return act8931_charge_ok;
-}
-#endif
-
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = INVALID_GPIO,
- .batt_low_pin = INVALID_GPIO,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = INVALID_GPIO,
- .io_init = rk30_battery_adc_io_init,
- .charging_sleep = 0 ,
- .save_capacity = 1 ,
-};
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-static int __init chg_board_init(void)
-{
- int ret = check_chg_param();
- if(ret < 0)
- return ret;
- rk30_adc_battery_platdata.adc_channel = chg_adc;
- if(dc_det != -1){
- rk30_adc_battery_platdata.dc_det_pin = get_port_config(dc_det).gpio;
- rk30_adc_battery_platdata.dc_det_level = !get_port_config(dc_det).io.active_low;
- }
- if(bat_low != -1){
- rk30_adc_battery_platdata.batt_low_pin = get_port_config(bat_low).gpio;
- rk30_adc_battery_platdata.batt_low_level = !get_port_config(bat_low).io.active_low;
- }
- if(chg_ok != -1){
- rk30_adc_battery_platdata.charge_ok_pin = get_port_config(chg_ok).gpio;
- rk30_adc_battery_platdata.charge_ok_level = !get_port_config(chg_ok).io.active_low;
- }
- if(chg_set != -1){
- rk30_adc_battery_platdata.charge_set_pin = get_port_config(chg_set).gpio;
- rk30_adc_battery_platdata.charge_set_level = !get_port_config(chg_set).io.active_low;
- }
- if(pmic_is_act8931()){
- rk30_adc_battery_platdata.is_dc_charging = rk30_battery_adc_is_dc_charging;
- rk30_adc_battery_platdata.charging_ok = rk30_battery_adc_charging_ok;
- };
-
- return 0;
-}
-#else
-static int __init chg_board_init(void)
-{
- return 0;
-}
-#endif
-
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_FB_ROCKCHIP
- &device_fb,
-#endif
-#ifdef CONFIG_LCDC_RK2928
- &device_lcdc,
-#endif
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- &rk29_device_backlight,
-#endif
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_SND_SOC_RK2928
- &device_acodec,
-#endif
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
- &rk30_device_adc_battery,
-#endif
-};
-#if defined (CONFIG_MFD_TPS65910) && defined (CONFIG_REGULATOR_ACT8931)
-#include "board-rk2928-sdk-tps65910.c"
-#include "board-rk2928-sdk-act8931.c"
-static struct i2c_board_info __initdata pmic_info = {
- .flags = 0,
-};
-static int __init pmic_board_init(void)
-{
- int ret = 0, i;
- struct port_config port;
-
- ret = check_pmic_param();
- if(ret < 0)
- return ret;
- if(pmic_irq != -1){
- port = get_port_config(pmic_irq);
- pmic_info.irq = port.gpio;
- }
- if(pmic_is_tps65910()){
- strcpy(pmic_info.type, "tps65910");
- pmic_info.platform_data = &tps65910_data;
-
- tps65910_data.irq = port.gpio;
- for(i = 0; i < ARRAY_SIZE(tps65910_dcdc_info); i++){
- tps65910_dcdc_info[i].min_uv = tps65910_dcdc[2*i];
- tps65910_dcdc_info[i].max_uv = tps65910_dcdc[2*i + 1];
- }
- for(i = 0; i < ARRAY_SIZE(tps65910_ldo_info); i++){
- tps65910_ldo_info[i].min_uv = tps65910_ldo[2*i];
- tps65910_ldo_info[i].max_uv = tps65910_ldo[2*i + 1];
- }
- }
- if(pmic_is_act8931()){
- strcpy(pmic_info.type, "act8931");
- pmic_info.platform_data = &act8931_data;
- for(i = 0; i < ARRAY_SIZE(act8931_dcdc_info); i++){
- act8931_dcdc_info[i].min_uv = act8931_dcdc[2*i];
- act8931_dcdc_info[i].max_uv = act8931_dcdc[2*i + 1];
- }
- for(i = 0; i < ARRAY_SIZE(act8931_ldo_info); i++){
- act8931_ldo_info[i].min_uv = act8931_ldo[2*i];
- act8931_ldo_info[i].max_uv = act8931_ldo[2*i + 1];
- }
- }
- pmic_info.addr = pmic_addr;
- i2c_register_board_info(pmic_i2c, &pmic_info, 1);
-
- return 0;
-}
-#else
-static int __init pmic_board_init(void)
-{
- return 0;
-}
-#endif
-
-#define GPIO_SWPORTA_DR 0x0000
-#define GPIO_SWPORTA_DDR 0x0004
-#define PWM_MUX_REG (GRF_GPIO0D_IOMUX)
-#define PWM_DDR_REG (RK2928_GPIO0_BASE + GPIO_SWPORTA_DDR)
-#define PWM_DR_REG (RK2928_GPIO0_BASE + GPIO_SWPORTA_DR)
-
-#define mux_set_gpio_mode(id) do { writel_relaxed( 1 << (20 + (id) * 2), PWM_MUX_REG); dsb(); } while (0)
-#define mux_set_pwm_mode(id) do { writel_relaxed( (1 << (20 + (id) * 2)) | (1 << (4 + (id) * 2)), PWM_MUX_REG); dsb(); } while (0)
-
-#define pwm_output_high(id) do {\
- writel_relaxed(readl_relaxed(PWM_DDR_REG) | (1 << (26 + (id))), PWM_DDR_REG); \
- writel_relaxed(readl_relaxed(PWM_DR_REG) | (1 << (26 + (id))), PWM_DR_REG); \
- dsb(); \
- } while (0)
-
-void __sramfunc rk30_pwm_logic_suspend_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
-
- sram_udelay(10000);
- mux_set_gpio_mode(reg_pwm);
- pwm_output_high(reg_pwm);
-#endif
-}
-void __sramfunc rk30_pwm_logic_resume_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- mux_set_pwm_mode(reg_pwm);
- sram_udelay(10000);
-#endif
-}
-
-extern void pwm_suspend_voltage(void);
-extern void pwm_resume_voltage(void);
-void rk30_pwm_suspend_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_suspend_voltage();
-#endif
-}
-void rk30_pwm_resume_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_resume_voltage();
-#endif
-}
-
-//i2c
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-};
-#endif
-#ifdef CONFIG_I2C1_RK30
-static struct i2c_board_info __initdata i2c1_info[] = {
-};
-#endif
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-};
-#endif
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- //set iomux (gpio) here
-
- return 0;
-}
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(4, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-
-/**************** gsensor ****************/
-// kxtik
-#if defined (CONFIG_GS_KXTIK)
-static int kxtik_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data kxtik_data = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = kxtik_init_platform_hw,
-};
-struct i2c_board_info __initdata kxtik_info = {
- .type = "gs_kxtik",
- .flags = 0,
- .platform_data = &kxtik_data,
-};
-#endif
-#if defined (CONFIG_GS_MMA8452)
-static int mma8452_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data mma8452_data = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma8452_init_platform_hw,
-};
-struct i2c_board_info __initdata mma8452_info = {
- .type = "gs_mma8452",
- .flags = 0,
- .platform_data = &mma8452_data,
-};
-#endif
-#if defined (CONFIG_GS_MMA7660)
-static int mma7660_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data mma7660_data = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma7660_init_platform_hw,
-};
-struct i2c_board_info __initdata mma7660_info = {
- .type = "gs_mma7660",
- .flags = 0,
- .platform_data = &mma7660_data,
-};
-#endif
-static int __init gs_board_init(void)
-{
- int i;
- struct port_config port;
- int ret = check_gs_param();
-
- if(ret < 0)
- return ret;
- port = get_port_config(gs_irq);
- //kxtik
-#if defined (CONFIG_GS_KXTIK)
- if(gs_type == GS_TYPE_KXTIK){
- kxtik_info.irq = port.gpio;
- kxtik_info.addr = gs_addr;
- for(i = 0; i < 9; i++)
- kxtik_data.orientation[i] = gs_orig[i];
- i2c_register_board_info(gs_i2c, &kxtik_info, 1);
- }
-#endif
- //mma7660
-#if defined (CONFIG_GS_MMA7660)
- if(gs_type == GS_TYPE_MMA7660){
- mma7660_info.irq = port.gpio;
- mma7660_info.addr = gs_addr;
- for(i = 0; i < 9; i++)
- mma7660_data.orientation[i] = gs_orig[i];
- i2c_register_board_info(gs_i2c, &mma7660_info, 1);
- }
-#endif
-#if defined (CONFIG_GS_MMA8452)
- if(gs_type == GS_TYPE_MMA8452){
- mma8452_info.irq = port.gpio;
- mma8452_info.addr = gs_addr;
- for(i = 0; i < 9; i++)
- mma8452_data.orientation[i] = gs_orig[i];
- i2c_register_board_info(gs_i2c, &mma8452_info, 1);
- }
-#endif
-
- return 0;
-}
-#ifdef CONFIG_LS_AP321XX
-static struct sensor_platform_data ls_ap321xx_data = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 1,
- .poll_delay_ms = 500,
-};
-struct i2c_board_info __initdata ls_ap321xx_info = {
- .type = "ls_ap321xx",
- .flags = 0,
- .platform_data = &ls_ap321xx_data,
-};
-#endif
-static int __init ls_board_init(void)
-{
- struct port_config port;
- int ret = check_ls_param();
-
- if(ret < 0)
- return ret;
- port = get_port_config(ls_irq);
- //ap321xx
-#if defined(CONFIG_LS_AP321XX)
- if(ls_type == LS_TYPE_AP321XX){
- ls_ap321xx_info.irq = port.gpio;
- ls_ap321xx_info.addr = ls_addr;
- i2c_register_board_info(ls_i2c, &ls_ap321xx_info, 1);
- }
-#endif
- return 0;
-}
-
-
-#ifdef CONFIG_PS_AP321XX
-static struct sensor_platform_data ps_ap321xx_data = {
- .type = SENSOR_TYPE_PROXIMITY,
- .irq_enable = 1,
- .poll_delay_ms = 500,
-};
-struct i2c_board_info __initdata ps_ap321xx_info = {
- .type = "ps_ap321xx",
- .flags = 0,
- .platform_data = &ps_ap321xx_data,
-};
-#endif
-static int __init ps_board_init(void)
-{
- struct port_config port;
- int ret = check_ps_param();
-
- if(ret < 0)
- return ret;
- port = get_port_config(ps_irq);
- //ap321xx
-#if defined(CONFIG_PS_AP321XX)
- if(ps_type == PS_TYPE_AP321XX){
- ps_ap321xx_info.irq = port.gpio;
- ps_ap321xx_info.addr = ps_addr;
- i2c_register_board_info(ps_i2c, &ps_ap321xx_info, 1);
- }
-#endif
- return 0;
-}
-
-
-#if defined (CONFIG_RTC_HYM8563)
-struct i2c_board_info __initdata rtc_info = {
- .type = "rtc_hym8563",
- .flags = 0,
-};
-static int __init rtc_board_init(void)
-{
- struct port_config port;
- int ret;
-
- if(pmic_is_tps65910())
- return 0;
-
- ret = check_rtc_param();
- if(ret < 0)
- return ret;
- port = get_port_config(rtc_irq);
- rtc_info.irq = port.gpio;
- rtc_info.addr = rtc_addr;
- i2c_register_board_info(rtc_i2c, &rtc_info, 1);
-
- return 0;
-}
-#else
-static int __init rtc_board_init(void)
-{
- return 0;
-}
-#endif
-
-static int __init rk2928_config_init(void)
-{
- int ret = 0;
-
- ret = pmic_board_init();
- if(ret < 0)
- return ret;
- ret = key_board_init();
- if(ret < 0)
- return ret;
- ret = bl_board_init();
- if(ret < 0)
- return ret;
- ret = lcd_board_init();
- if(ret < 0)
- return ret;
- ret = ion_board_init();
- if(ret < 0)
- return ret;
- ret = pwm_reg_board_init();
- if(ret < 0)
- return ret;
- ret = gs_board_init();
- if(ret < 0)
- return ret;
- ret = ls_board_init();
- if(ret < 0)
- return ret;
- ret = cam_board_init();
- if(ret < 0)
- return ret;
- ret = ps_board_init();
- if(ret < 0)
- return ret;
- ret = rtc_board_init();
- if(ret < 0)
- return ret;
- ret = codec_board_init();
- if(ret < 0)
- return ret;
- ret = sdmmc_board_init();
- if(ret < 0)
- return ret;
- ret = chg_board_init();
- if(ret < 0)
- return ret;
- return 0;
-}
-#if defined(CONFIG_REGULATOR_ACT8931)
-extern int act8931_charge_det;
-#endif
-static void rk2928_pm_power_off(void)
-{
- printk(KERN_ERR "rk2928_pm_power_off start...\n");
- #if defined(CONFIG_REGULATOR_ACT8931)
- if(pmic_is_act8931())
- {
- if(act8931_charge_det)
- arm_pm_restart(0, NULL);
- }
- #endif
-
- #if defined(CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- {
- tps65910_device_shutdown();//tps65910 shutdown
- }
- #endif
- rk2928_power_off();
-
-};
-
-/**
- * dvfs_cpu_logic_table: table for arm and logic dvfs
- * @frequency : arm frequency
- * @cpu_volt : arm voltage depend on frequency
- * @logic_volt : logic voltage arm requests depend on frequency
- * comments : min arm/logic voltage
- */
-#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
-static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
-static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
-
-static noinline __init void board_init_dvfs(void)
-{
- unsigned i, j;
-
- for (i = 0, j = 0; (i + 2) < dvfs_cpu_logic_num && j < (ARRAY_SIZE(dvfs_cpu_logic_table) - 1); i += 3, j++) {
- dvfs_cpu_logic_table[j].frequency = dvfs_cpu_logic[i + 0] * 1000;
- dvfs_cpu_logic_table[j].cpu_volt = dvfs_cpu_logic[i + 1] * 1000;
- dvfs_cpu_logic_table[j].logic_volt = dvfs_cpu_logic[i + 2] * 1000;
- }
- if (j > 0) {
- dvfs_cpu_logic_table[j].frequency = CPUFREQ_TABLE_END;
- }
- dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
-
- for (i = 0, j = 0; (i + 1) < dvfs_gpu_num && j < (ARRAY_SIZE(dvfs_gpu_table) - 1); i += 2, j++) {
- dvfs_gpu_table[j].frequency = dvfs_gpu[i + 0] * 1000;
- dvfs_gpu_table[j].index = dvfs_gpu[i + 1] * 1000;
- }
- if (j > 0) {
- dvfs_gpu_table[j].frequency = CPUFREQ_TABLE_END;
- }
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
-
-#if 0
- for (i = 0, j = 0; (i + 1) < dvfs_ddr_num && j < (ARRAY_SIZE(dvfs_ddr_table) - 1); i += 2, j++) {
- dvfs_ddr_table[j].frequency = dvfs_ddr[i + 0] * 1000;
- dvfs_ddr_table[j].index = dvfs_ddr[i + 1] * 1000;
- }
- if (j > 0) {
- dvfs_ddr_table[j].frequency = CPUFREQ_TABLE_END;
- }
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
-#endif
-}
-
-static void __init rk2928_board_init(void)
-{
- rk2928_power_on();
- rk2928_config_init();
-
- pm_power_off = rk2928_pm_power_off;
-
- board_init_dvfs();
-
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- if(is_phonepad)
- phonepad_board_init();
-}
-static void __init rk2928_reserve(void)
-{
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ion_size);
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0", RK30_FB0_MEM_SIZE);
- resource_fb[0].end = resource_fb[0].start + RK30_FB0_MEM_SIZE - 1;
-#endif
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
- board_mem_reserved();
-}
-
-void __init board_clock_init(void)
-{
- rk2928_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
-}
-
-MACHINE_START(RK2928, "RK2928board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk2928_fixup,
- .reserve = rk2928_reserve,
- .map_io = rk2928_map_io,
- .init_irq = rk2928_init_irq,
- .timer = &rk2928_timer,
- .init_machine = rk2928_board_init,
-MACHINE_END
+++ /dev/null
-/* arch/arm/mach-rk2928/clock_data.c
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/hardirq.h>
-#include <mach/cru.h>
-#include <mach/iomux.h>
-#include <mach/clock.h>
-#include <mach/dvfs.h>
-//#include <mach/pmu.h>
-#include <mach/ddr.h>
-
-#define MHZ (1000 * 1000)
-#define KHZ (1000)
-#define CLK_LOOPS_JIFFY_REF 11996091ULL
-#define CLK_LOOPS_RATE_REF (1200) //Mhz
-#define CLK_LOOPS_RECALC(new_rate) div_u64(CLK_LOOPS_JIFFY_REF*(new_rate),CLK_LOOPS_RATE_REF*MHZ)
-#define LPJ_24M (CLK_LOOPS_JIFFY_REF * 24) / CLK_LOOPS_RATE_REF
-
-
-struct apll_clk_set {
- unsigned long rate;
- u32 pllcon0;
- u32 pllcon1;
- u32 pllcon2; //nb=bwadj+1;0:11;nb=nf/2
- u32 clksel0;
- u32 clksel1;
- u32 rst_dly;//us
- unsigned long lpj; //loop per jeffise
-};
-
-struct pll_clk_set {
- unsigned long rate;
- u32 pllcon0;
- u32 pllcon1;
- u32 pllcon2; //nb=bwadj+1;0:11;nb=nf/2
- u32 rst_dly;//us
-};
-#if 0
-#define CLKDATA_DBG(fmt, args...) printk(KERN_DEBUG "CLKDATA_DBG:\t"fmt, ##args)
-#define CLKDATA_LOG(fmt, args...) printk(KERN_INFO "CLKDATA_LOG:\t"fmt, ##args)
-#else
-#define CLKDATA_DBG(fmt, args...) do {} while(0)
-#define CLKDATA_LOG(fmt, args...) do {} while(0)
-#endif
-#define CLKDATA_ERR(fmt, args...) printk(KERN_ERR "CLKDATA_ERR:\t"fmt, ##args)
-#define CLKDATA_WARNNING(fmt, args...) printk("CLKDATA_WANNING:\t"fmt, ##args)
-
-#define cru_readl(offset) readl_relaxed(RK2928_CRU_BASE + offset)
-#define cru_writel(v, offset) do { writel_relaxed(v, RK2928_CRU_BASE + offset); dsb(); } while (0)
-
-#define rk_clock_udelay(a) udelay(a);
-
-#define PLLS_IN_NORM(pll_id) \
- (((cru_readl(CRU_MODE_CON) & PLL_MODE_MSK(pll_id)) == (PLL_MODE_NORM(pll_id) & PLL_MODE_MSK(pll_id)))\
- && !(cru_readl(PLL_CONS(pll_id, 0)) & PLL_BYPASS))
-
-#define get_cru_bits(con, mask, shift)\
- ((cru_readl((con)) >> (shift)) & (mask))
-
-#define CRU_DIV_SET(mask, shift, max) \
- .div_mask = (mask),\
-.div_shift = (shift),\
-.div_max = (max)
-
-#define CRU_SRC_SET(mask, shift ) \
- .src_mask = (mask),\
-.src_shift = (shift)
-
-#define CRU_PARENTS_SET(parents_array) \
- .parents = (parents_array),\
-.parents_num = ARRAY_SIZE((parents_array))
-
-#define get_cru_bits(con,mask,shift)\
- ((cru_readl((con)) >> (shift)) & (mask))
-
-#define set_cru_bits_w_msk(val,mask,shift,con)\
- cru_writel(((mask)<<(shift+16))|((val)<<(shift)),(con))
-#define regfile_readl(offset) readl_relaxed(RK2928_GRF_BASE + offset)
-#define regfile_writel(v, offset) do { writel_relaxed(v, RK2928_GRF_BASE + offset); dsb(); } while (0)
-#define cru_writel_frac(v,offset) cru_writel((v),(offset))
-/*******************PLL CON0 BITS***************************/
-#define SET_PLL_DATA(_pll_id,_table) \
-{\
- .id=(_pll_id),\
- .table=(_table),\
-}
-
-#define GATE_CLK(NAME,PARENT,ID) \
- static struct clk clk_##NAME = { \
- .name = #NAME, \
- .parent = &PARENT, \
- .mode = gate_mode, \
- .gate_idx = CLK_GATE_##ID, \
- }
-
-//FIXME
-//lpj
-#define _APLL_SET_CLKS(_mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac, \
- _periph_div, _aclk_core_div, _axi_div, _apb_div, _ahb_div) \
-{ \
- .rate = (_mhz) * MHZ, \
- .pllcon0 = PLL_SET_POSTDIV1(_postdiv1) | PLL_SET_FBDIV(_fbdiv), \
- .pllcon1 = PLL_SET_DSMPD(_dsmpd) | PLL_SET_POSTDIV2(_postdiv2) | PLL_SET_REFDIV(_refdiv), \
- .pllcon2 = PLL_SET_FRAC(_frac), \
- .clksel1 = ACLK_CORE_DIV(RATIO_##_aclk_core_div) | CLK_CORE_PERI_DIV(RATIO_##_periph_div), \
- .lpj = (CLK_LOOPS_JIFFY_REF * _mhz) / CLK_LOOPS_RATE_REF, \
- .rst_dly = 0,\
-}
-
-static const struct apll_clk_set apll_clks[] = {
- _APLL_SET_CLKS(1248, 1, 52, 1, 1, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS(1200, 1, 50, 1, 1, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS(1104, 1, 46, 1, 1, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS(1008, 1, 42, 1, 1, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS( 912, 1, 38, 1, 1, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS( 816, 1, 34, 1, 1, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS( 696, 1, 29, 1, 1, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS( 600, 1, 25, 1, 1, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS( 504, 1, 21, 1, 1, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS( 408, 1, 17, 1, 1, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS( 312, 1, 52, 2, 2, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS( 216, 1, 36, 2, 2, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS( 0, 1, 0, 1, 1, 1, 0, 41, 21, 41, 21, 21),
-};
-
-#define _PLL_SET_CLKS(_mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac) \
-{ \
- .rate = (_mhz) * KHZ, \
- .pllcon0 = PLL_SET_POSTDIV1(_postdiv1) | PLL_SET_FBDIV(_fbdiv), \
- .pllcon1 = PLL_SET_DSMPD(_dsmpd) | PLL_SET_POSTDIV2(_postdiv2) | PLL_SET_REFDIV(_refdiv), \
- .pllcon2 = PLL_SET_FRAC(_frac), \
-}
-static const struct pll_clk_set cpll_clks[] = {
- _PLL_SET_CLKS(798000, 4, 133, 1, 1, 1, 0),
- _PLL_SET_CLKS(1064000, 3, 133, 1, 1, 1, 0),
-};
-
-static const struct pll_clk_set gpll_clks[] = {
- _PLL_SET_CLKS(297000, 2, 99, 4, 1, 1, 0),
-};
-
-static u32 clk_gcd(u32 numerator, u32 denominator)
-{
- u32 a, b;
-
- if (!numerator || !denominator)
- return 0;
-
- if (numerator > denominator) {
- a = numerator;
- b = denominator;
- } else {
- a = denominator;
- b = numerator;
- }
-
- while (b != 0) {
- int r = b;
- b = a % b;
- a = r;
- }
-
- return a;
-}
-
-static int frac_div_get_seting(unsigned long rate_out,unsigned long rate,
- u32 *numerator,u32 *denominator)
-{
- u32 gcd_vl;
- gcd_vl = clk_gcd(rate, rate_out);
- CLKDATA_DBG("frac_get_seting rate=%lu,parent=%lu,gcd=%d\n",rate_out,rate, gcd_vl);
-
- if (!gcd_vl) {
- CLKDATA_ERR("gcd=0, i2s frac div is not be supported\n");
- return -ENOENT;
- }
-
- *numerator = rate_out / gcd_vl;
- *denominator = rate/ gcd_vl;
-
- CLKDATA_DBG("frac_get_seting numerator=%d,denominator=%d,times=%d\n",
- *numerator, *denominator, *denominator / *numerator);
-
- if (*numerator > 0xffff || *denominator > 0xffff||
- (*denominator/(*numerator))<20) {
- CLKDATA_ERR("can't get a available nume and deno\n");
- return -ENOENT;
- }
-
- return 0;
-
-}
-/************************option functions*****************/
-/************************clk recalc div rate**************/
-
-//for free div
-static unsigned long clksel_recalc_div(struct clk *clk)
-{
- u32 div = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
- unsigned long rate = clk->parent->rate / div;
-
- CLKDATA_DBG("ENTER %s clk=%s\n", __func__, clk->name);
- CLKDATA_DBG("%s new clock rate is %lu (div %u)\n", clk->name, rate, div);
- return rate;
-}
-
-//for div 2^n
-static unsigned long clksel_recalc_shift(struct clk *clk)
-{
- u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift);
- unsigned long rate = clk->parent->rate >> shift;
- CLKDATA_DBG("ENTER %s clk=%s\n", __func__, clk->name);
- CLKDATA_DBG("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
- return rate;
-}
-
-//for rate equal to parent
-static unsigned long clksel_recalc_equal_parent(struct clk *clk)
-{
- unsigned long rate = clk->parent->rate;
- CLKDATA_DBG("ENTER %s clk=%s\n", __func__, clk->name);
- CLKDATA_DBG("%s new clock rate is %lu (equal to parent)\n", clk->name, rate);
-
- return rate;
-}
-
-//for Fixed divide ratio
-static unsigned long clksel_recalc_fixed_div2(struct clk *clk)
-{
- unsigned long rate = clk->parent->rate >> 1;
- CLKDATA_DBG("ENTER %s clk=%s\n", __func__, clk->name);
- CLKDATA_DBG("%s new clock rate is %lu (div %u)\n", clk->name, rate, 2);
-
- return rate;
-}
-
-static unsigned long clksel_recalc_fixed_div4(struct clk *clk)
-{
- unsigned long rate = clk->parent->rate >> 2;
- CLKDATA_DBG("ENTER %s clk=%s\n", __func__, clk->name);
- CLKDATA_DBG("%s new clock rate is %lu (div %u)\n", clk->name, rate, 4);
-
- return rate;
-}
-
-static unsigned long clksel_recalc_frac(struct clk *clk)
-{
- unsigned long rate;
- u64 rate64;
- u32 r = cru_readl(clk->clksel_con), numerator, denominator;
- CLKDATA_DBG("ENTER %s clk=%s\n", __func__, clk->name);
- if (r == 0) // FPGA ?
- return clk->parent->rate;
- numerator = r >> 16;
- denominator = r & 0xFFFF;
- rate64 = (u64)clk->parent->rate * numerator;
- do_div(rate64, denominator);
- rate = rate64;
- CLKDATA_DBG("%s new clock rate is %lu (frac %u/%u)\n", clk->name, rate, numerator, denominator);
- return rate;
-}
-
-#define FRAC_MODE 0
-static unsigned long pll_clk_recalc(u8 pll_id, unsigned long parent_rate)
-{
- unsigned long rate;
- unsigned int dsmp = 0;
- u64 rate64 = 0, frac_rate64 = 0;
- dsmp = PLL_GET_DSMPD(cru_readl(PLL_CONS(pll_id, 1)));
-
- if (PLLS_IN_NORM(pll_id)) {
- u32 pll_con0 = cru_readl(PLL_CONS(pll_id, 0));
- u32 pll_con1 = cru_readl(PLL_CONS(pll_id, 1));
- u32 pll_con2 = cru_readl(PLL_CONS(pll_id, 2));
- //integer mode
- rate64 = (u64)parent_rate * PLL_GET_FBDIV(pll_con0);
- do_div(rate64, PLL_GET_REFDIV(pll_con1));
-
- if (FRAC_MODE == dsmp) {
- //fractional mode
- frac_rate64 = (u64)parent_rate * PLL_GET_FRAC(pll_con2);
- do_div(frac_rate64, PLL_GET_REFDIV(pll_con1));
- rate64 += frac_rate64 >> 24;
- CLKDATA_DBG("%s id=%d frac_rate=%llu(%08x/2^24) by pass mode\n",
- __func__, pll_id, frac_rate64 >> 24, PLL_GET_FRAC(pll_con2));
- }
- do_div(rate64, PLL_GET_POSTDIV1(pll_con0));
- do_div(rate64, PLL_GET_POSTDIV2(pll_con1));
-
- rate = rate64;
- } else {
- rate = parent_rate;
- CLKDATA_DBG("pll_clk_recalc id=%d rate=%lu by pass mode\n", pll_id, rate);
- }
- return rate;
-}
-
-static unsigned long plls_clk_recalc(struct clk *clk)
-{
- return pll_clk_recalc(clk->pll->id, clk->parent->rate);
-}
-
-/************************clk set rate*********************************/
-static int clksel_set_rate_freediv(struct clk *clk, unsigned long rate)
-{
- u32 div = 0;
-
- for (div = 0; div < clk->div_max; div++) {
- u32 new_rate = clk->parent->rate / (div + 1);
- if (new_rate <= rate) {
- set_cru_bits_w_msk(div,clk->div_mask,clk->div_shift,clk->clksel_con);
- //clk->rate = new_rate;
- CLKDATA_DBG("clksel_set_rate_freediv for clock %s to rate %ld (div %d)\n", clk->name, rate, div + 1);
- return 0;
- }
- if (div == clk->div_max - 1) {
- CLKDATA_WARNNING("%s clk=%s, div=%u, rate=%lu, new_rate=%u\n",
- __func__, clk->name, div, rate, new_rate);
- set_cru_bits_w_msk(div,clk->div_mask,clk->div_shift,clk->clksel_con);
- return 0;
- }
- }
- return -ENOENT;
-}
-
-//for div 1 2 4 2^n
-static int clksel_set_rate_shift(struct clk *clk, unsigned long rate)
-{
- u32 shift;
- for (shift = 0; (1 << shift) < clk->div_max; shift++) {
- u32 new_rate = clk->parent->rate >> shift;
- if (new_rate <= rate) {
- set_cru_bits_w_msk(shift,clk->div_mask,clk->div_shift,clk->clksel_con);
- clk->rate = new_rate;
- CLKDATA_DBG("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n", clk->name, rate, shift);
- return 0;
- }
- }
- return -ENOENT;
-}
-#if 0
-//for div 2 4 2^n
-static int clksel_set_rate_shift_2(struct clk *clk, unsigned long rate)
-{
- u32 shift;
-
- for (shift = 1; (1 << shift) < clk->div_max; shift++) {
- u32 new_rate = clk->parent->rate >> shift;
- if (new_rate <= rate) {
- set_cru_bits_w_msk(shift-1,clk->div_mask,clk->div_shift,clk->clksel_con);
- clk->rate = new_rate;
- CLKDATA_DBG("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n", clk->name, rate, shift);
- return 0;
- }
- }
- return -ENOENT;
-}
-#endif
-//for div 1 2 4 2*n
-static int clksel_set_rate_even(struct clk *clk, unsigned long rate)
-{
- u32 div = 0, new_rate = 0;
- for (div = 1; div < clk->div_max; div++) {
- if (div >= 3 && div % 2 != 0)
- continue;
- new_rate = clk->parent->rate / div;
- if (new_rate <= rate) {
- set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
- clk->rate = new_rate;
- pr_debug("%s for clock %s to rate %ld (even div = %d)\n",
- __func__, clk->name, rate, div);
- return 0;
- }
- }
- return -ENOENT;
-}
-
-static u32 clk_get_freediv(unsigned long rate_out, unsigned long rate ,u32 div_max)
-{
- u32 div;
- unsigned long new_rate;
- for (div = 0; div <div_max; div++) {
- new_rate = rate / (div + 1);
- if (new_rate <= rate_out) {
- return div+1;
- }
- }
- return div_max?div_max:1;
-}
-struct clk *get_freediv_parents_div(struct clk *clk,unsigned long rate,u32 *div_out)
-{
- u32 div[2]={0,0};
- unsigned long new_rate[2]={0,0};
- u32 i;
-
- if(clk->rate==rate)
- return clk->parent;
- for(i=0;i<2;i++)
- {
- div[i]=clk_get_freediv(rate,clk->parents[i]->rate,clk->div_max);
- new_rate[i] = clk->parents[i]->rate/div[i];
- if(new_rate[i]==rate)
- {
- *div_out=div[i];
- return clk->parents[i];
- }
- }
- if(new_rate[0]<new_rate[1])
- i=1;
- else
- i=0;
- *div_out=div[i];
- return clk->parents[i];
-}
-
-static int clkset_rate_freediv_autosel_parents(struct clk *clk, unsigned long rate)
-{
- struct clk *p_clk;
- u32 div,old_div;
- int ret=0;
- if(clk->rate==rate)
- return 0;
- p_clk=get_freediv_parents_div(clk,rate,&div);
-
- if(!p_clk)
- return -ENOENT;
-
- CLKDATA_DBG("%s %lu,form %s\n",clk->name,rate,p_clk->name);
- if (clk->parent != p_clk)
- {
- old_div=CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con),clk->div_shift,clk->div_mask)+1;
-
- if(div>old_div)
- {
- set_cru_bits_w_msk(div-1,clk->div_mask,clk->div_shift,clk->clksel_con);
- }
- ret=clk_set_parent_nolock(clk,p_clk);
- if(ret)
- {
- CLKDATA_ERR("%s can't set %lu,reparent err\n",clk->name,rate);
- return -ENOENT;
- }
- }
- //set div
- set_cru_bits_w_msk(div-1,clk->div_mask,clk->div_shift,clk->clksel_con);
- return 0;
-}
-#if 0
-//rate==div rate //hdmi
-static int clk_freediv_autosel_parents_set_fixed_rate(struct clk *clk, unsigned long rate)
-{
- struct clk *p_clk;
- u32 div,old_div;
- int ret;
- p_clk=get_freediv_parents_div(clk,rate,&div);
-
- if(!p_clk)
- return -ENOENT;
-
- if((p_clk->rate/div)!=rate||(p_clk->rate%div))
- return -ENOENT;
-
- if (clk->parent != p_clk)
- {
- old_div=CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con),
- clk->div_shift,clk->div_mask)+1;
- if(div>old_div)
- {
- set_cru_bits_w_msk(div-1,clk->div_mask,clk->div_shift,clk->clksel_con);
- }
- ret=clk_set_parent_nolock(clk,p_clk);
- if (ret)
- {
- CLKDATA_DBG("%s can't get rate%lu,reparent err\n",clk->name,rate);
- return ret;
- }
- }
- //set div
- set_cru_bits_w_msk(div-1,clk->div_mask,clk->div_shift,clk->clksel_con);
- return 0;
-}
-#endif
-/************************round functions*****************/
-static long clksel_freediv_round_rate(struct clk *clk, unsigned long rate)
-{
- return clk->parent->rate/clk_get_freediv(rate,clk->parent->rate,clk->div_max);
-}
-
-static long clk_freediv_round_autosel_parents_rate(struct clk *clk, unsigned long rate)
-{
- u32 div;
- struct clk *p_clk;
- if(clk->rate == rate)
- return clk->rate;
- p_clk=get_freediv_parents_div(clk,rate,&div);
- if(!p_clk)
- return 0;
- return p_clk->rate/div;
-}
-
-static const struct apll_clk_set* apll_clk_get_best_pll_set(unsigned long rate,
- struct apll_clk_set *tables)
-{
- const struct apll_clk_set *ps, *pt;
-
- /* find the arm_pll we want. */
- ps = pt = tables;
- while (pt->rate) {
- if (pt->rate == rate) {
- ps = pt;
- break;
- }
- // we are sorted, and ps->rate > pt->rate.
- if ((pt->rate > rate || (rate - pt->rate < ps->rate - rate)))
- ps = pt;
- if (pt->rate < rate)
- break;
- pt++;
- }
- //CLKDATA_DBG("arm pll best rate=%lu\n",ps->rate);
- return ps;
-}
-static long apll_clk_round_rate(struct clk *clk, unsigned long rate)
-{
- return apll_clk_get_best_pll_set(rate, clk->pll->table)->rate;
-}
-
-/************************others functions*****************/
-static void pll_wait_lock(int pll_idx)
-{
- u32 pll_state[4]={1,0,2,3};
- u32 bit = 0x10u << pll_state[pll_idx];
- int delay = 24000000;
- while (delay > 0) {
- if ((cru_readl(PLL_CONS(pll_idx, 1)) & (0x1 << PLL_LOCK_SHIFT))) {
- //CLKDATA_DBG("%s %08x\n", __func__, cru_readl(PLL_CONS(pll_idx, 1)) & (0x1 << PLL_LOCK_SHIFT));
- //CLKDATA_DBG("%s ! %08x\n", __func__, !(cru_readl(PLL_CONS(pll_idx, 1)) & (0x1 << PLL_LOCK_SHIFT)));
- break;
- }
- delay--;
- }
- if (delay == 0) {
- CLKDATA_ERR("wait pll bit 0x%x time out!\n", bit);
- while(1);
- }
-}
-
-static int pll_clk_mode(struct clk *clk, int on)
-{
- u8 pll_id = clk->pll->id;
- // FIXME here 500 must be changed
- u32 dly = 1500;
-
- CLKDATA_DBG("pll_mode %s(%d)\n", clk->name, on);
- //FIXME
- if (on) {
- cru_writel(CRU_W_MSK_SETBIT(PLL_PWR_ON, PLL_BYPASS_SHIFT), PLL_CONS(pll_id, 0));
- rk_clock_udelay(dly);
- pll_wait_lock(pll_id);
- cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
- } else {
- cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
- cru_writel(CRU_W_MSK_SETBIT(PLL_PWR_DN, PLL_BYPASS_SHIFT), PLL_CONS(pll_id, 0));
- }
- return 0;
-}
-static struct clk* clksel_get_parent(struct clk *clk)
-{
- return clk->parents[(cru_readl(clk->clksel_con) >> clk->src_shift) & clk->src_mask];
-}
-static int clksel_set_parent(struct clk *clk, struct clk *parent)
-{
- u32 i;
- if (unlikely(!clk->parents))
- return -EINVAL;
- for (i = 0; (i <clk->parents_num); i++) {
- if (clk->parents[i]!= parent)
- continue;
- set_cru_bits_w_msk(i,clk->src_mask,clk->src_shift,clk->clksel_con);
- return 0;
- }
- return -EINVAL;
-}
-
-static int gate_mode(struct clk *clk, int on)
-{
- int idx = clk->gate_idx;
- CLKDATA_DBG("ENTER %s clk=%s, on=%d\n", __func__, clk->name, on);
- if (idx >= CLK_GATE_MAX)
- return -EINVAL;
- if(on) {
- cru_writel(CLK_GATE_W_MSK(idx) | CLK_UN_GATE(idx), CLK_GATE_CLKID_CONS(idx));
- } else {
- cru_writel(CLK_GATE_W_MSK(idx) | CLK_GATE(idx), CLK_GATE_CLKID_CONS(idx));
- }
- return 0;
-}
-#define PLL_INT_MODE 1
-#define PLL_FRAC_MODE 0
-
-#define rk2928_clock_udelay(a) udelay(a);
-static int pll_clk_set_rate(struct pll_clk_set *clk_set, u8 pll_id)
-{
- //enter slowmode
- cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
-
- cru_writel(clk_set->pllcon0, PLL_CONS(pll_id,0));
- cru_writel(clk_set->pllcon1, PLL_CONS(pll_id,1));
- cru_writel(clk_set->pllcon2, PLL_CONS(pll_id,2));
-
- CLKDATA_DBG("id=%d,pllcon0%08x\n", pll_id, cru_readl(PLL_CONS(pll_id,0)));
- CLKDATA_DBG("id=%d,pllcon1%08x\n", pll_id, cru_readl(PLL_CONS(pll_id,1)));
- CLKDATA_DBG("id=%d,pllcon2%08x\n", pll_id, cru_readl(PLL_CONS(pll_id,2)));
- //rk2928_clock_udelay(5);
-
- //wating lock state
- rk2928_clock_udelay(clk_set->rst_dly);
- pll_wait_lock(pll_id);
-
- //return form slow
- cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
-
- return 0;
-}
-#define PLL_FREF_MIN (183*KHZ)
-#define PLL_FREF_MAX (1500*MHZ)
-
-#define PLL_FVCO_MIN (300*MHZ)
-#define PLL_FVCO_MAX (1500*MHZ)
-
-#define PLL_FOUT_MIN (18750*KHZ)
-#define PLL_FOUT_MAX (1500*MHZ)
-
-#define PLL_NF_MAX (4096)
-#define PLL_NR_MAX (64)
-#define PLL_NO_MAX (16)
-
-static int pll_clk_check_legality(unsigned long fin_hz,unsigned long fout_hz,
- u32 refdiv, u32 fbdiv, u32 postdiv1, u32 postdiv2)
-{
- fin_hz /= MHZ;
- if (fin_hz < 1 || fin_hz > 800) {
- CLKDATA_ERR("%s fbdiv out of [1, 800]MHz\n", __func__);
- return -1;
- }
-
- if (fbdiv < 16 || fbdiv > 1600) {
- CLKDATA_ERR("%s fbdiv out of [16, 1600]MHz\n", __func__);
- return -1;
- }
-
- if (fin_hz / refdiv < 1 || fin_hz / refdiv > 40) {
- CLKDATA_ERR("%s fin / refdiv out of [1, 40]MHz\n", __func__);
- return -1;
- }
-
- if (fin_hz * fbdiv / refdiv < 400 || fin_hz * fbdiv / refdiv > 1600) {
- CLKDATA_ERR("%s fin_hz * fbdiv / refdiv out of [400, 1600]MHz\n", __func__);
- return -1;
- }
-
- if (fin_hz * fbdiv / refdiv / postdiv1 / postdiv2 < 8
- || fin_hz * fbdiv / refdiv / postdiv1 / postdiv2 > 1600) {
- CLKDATA_ERR("%s fin_hz * fbdiv / refdiv / postdiv1 / postdiv2 out of [8, 1600]MHz\n", __func__);
- return -1;
- }
-
-}
-
-static int pll_clk_check_legality_frac(unsigned long fin_hz,unsigned long fout_hz,
- u32 refdiv, u32 fbdiv, u32 postdiv1, u32 postdiv2, u32 frac)
-{
- fin_hz /= MHZ;
- if (fin_hz < 10 || fin_hz > 800) {
- CLKDATA_ERR("%s fin_hz out of [10, 800]MHz\n", __func__);
- return -1;
- }
- if (fbdiv < 19 || fbdiv > 160) {
- CLKDATA_ERR("%s fbdiv out of [19, 160]MHz\n", __func__);
- return -1;
- }
-
- if (fin_hz / refdiv < 1 || fin_hz / refdiv > 40) {
- CLKDATA_ERR("%s fin / refdiv out of [1, 40]MHz\n", __func__);
- return -1;
- }
-
- if (fin_hz * fbdiv / refdiv < 400 || fin_hz * fbdiv / refdiv > 1600) {
- CLKDATA_ERR("%s fin_hz * fbdiv / refdiv out of [400, 1600]MHz\n", __func__);
- return -1;
- }
-
- if (fin_hz * fbdiv / refdiv / postdiv1 / postdiv2 < 8
- || fin_hz * fbdiv / refdiv / postdiv1 / postdiv2 > 1600) {
- CLKDATA_ERR("%s fin_hz * fbdiv / refdiv / postdiv1 / postdiv2 out of [8, 1600]MHz\n", __func__);
- return -1;
- }
-
-}
-static int pll_clk_get_set(unsigned long fin_hz,unsigned long fout_hz,
- u32 *refdiv, u32 *fbdiv, u32 *postdiv1, u32 *postdiv2, u32 *frac)
-{
- // FIXME set postdiv1/2 always 1
- u32 gcd;
- u64 fin_64, frac_64;
- u32 f_frac;
- if(!fin_hz || !fout_hz || fout_hz == fin_hz)
- return -1;
-
- if (fin_hz / MHZ * MHZ == fin_hz && fout_hz /MHZ * MHZ == fout_hz) {
- fin_hz /= MHZ;
- fout_hz /= MHZ;
- gcd = clk_gcd(fin_hz, fout_hz);
- *refdiv = fin_hz / gcd;
- *fbdiv = fout_hz / gcd;
- *postdiv1 = 1;
- *postdiv2 = 1;
-
- *frac = 0;
-
- CLKDATA_DBG("fin=%lu,fout=%lu,gcd=%u,refdiv=%u,fbdiv=%u,postdiv1=%u,postdiv2=%u,frac=%u\n",
- fin_hz, fout_hz, gcd, *refdiv, *fbdiv, *postdiv1, *postdiv2, *frac);
- } else {
- CLKDATA_DBG("******frac div running, fin_hz=%lu, fout_hz=%lu, fin_mhz=%lu, fout_mhz=%lu\n",
- fin_hz, fout_hz, fin_hz / MHZ * MHZ, fout_hz / MHZ * MHZ);
- gcd = clk_gcd(fin_hz / MHZ, fout_hz / MHZ);
- *refdiv = fin_hz / MHZ / gcd;
- *fbdiv = fout_hz / MHZ / gcd;
- *postdiv1 = 1;
- *postdiv2 = 1;
-
- *frac = 0;
-
- f_frac = (fout_hz % MHZ);
- fin_64 = fin_hz;
- do_div(fin_64, (u64)*refdiv);
- frac_64 = (u64)f_frac << 24;
- do_div(frac_64, fin_64);
- *frac = (u32) frac_64;
- CLKDATA_DBG("frac_64=%llx, frac=%u\n", frac_64, *frac);
- }
- return 0;
-}
-static int pll_set_con(u8 id, u32 refdiv, u32 fbdiv, u32 postdiv1, u32 postdiv2, u32 frac)
-{
- struct pll_clk_set temp_clk_set;
- temp_clk_set.pllcon0 = PLL_SET_FBDIV(fbdiv) | PLL_SET_POSTDIV1(postdiv1);
- temp_clk_set.pllcon1 = PLL_SET_REFDIV(refdiv) | PLL_SET_POSTDIV2(postdiv2);
- if (frac != 0) {
- temp_clk_set.pllcon1 |= PLL_SET_DSMPD(0);
- } else {
- temp_clk_set.pllcon1 |= PLL_SET_DSMPD(1);
- }
- temp_clk_set.pllcon2 = PLL_SET_FRAC(frac);
- temp_clk_set.rst_dly = 0;
- CLKDATA_DBG("setting....\n");
- return pll_clk_set_rate(&temp_clk_set, id);
-}
-static int apll_clk_set_rate(struct clk *clk, unsigned long rate)
-{
- unsigned long flags;
- struct _pll_data *pll_data=clk->pll;
- struct apll_clk_set *clk_set=(struct apll_clk_set*)pll_data->table;
-
- u32 fin_hz, fout_hz;
- u32 refdiv, fbdiv, postdiv1, postdiv2, frac;
- u8 pll_id = pll_data->id;
-
- fin_hz = clk->parent->rate;
- fout_hz = rate;
-
- while(clk_set->rate) {
- if (clk_set->rate == rate) {
- break;
- }
- clk_set++;
- }
-
- CLKDATA_DBG("%s %s %lu\n", __func__, clk->name, rate);
- CLKDATA_DBG("pllcon0 %08x\n", cru_readl(PLL_CONS(0,0)));
- CLKDATA_DBG("pllcon1 %08x\n", cru_readl(PLL_CONS(0,1)));
- CLKDATA_DBG("pllcon2 %08x\n", cru_readl(PLL_CONS(0,2)));
- //CLKDATA_DBG("pllcon3 %08x\n", cru_readl(PLL_CONS(0,3)));
- CLKDATA_DBG("clksel0 %08x\n", cru_readl(CRU_CLKSELS_CON(0)));
- CLKDATA_DBG("clksel1 %08x\n", cru_readl(CRU_CLKSELS_CON(1)));
- if(clk_set->rate==rate) {
- CLKDATA_DBG("apll get a rate\n");
-
- //enter slowmode
- local_irq_save(flags);
- cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
- loops_per_jiffy = LPJ_24M;
-
- cru_writel(clk_set->pllcon0, PLL_CONS(pll_id,0));
- cru_writel(clk_set->pllcon1, PLL_CONS(pll_id,1));
- cru_writel(clk_set->pllcon2, PLL_CONS(pll_id,2));
- cru_writel(clk_set->clksel0, CRU_CLKSELS_CON(0));
- cru_writel(clk_set->clksel1, CRU_CLKSELS_CON(1));
- //local_irq_restore(flags);
-
- CLKDATA_DBG("pllcon0 %08x\n", cru_readl(PLL_CONS(0,0)));
- CLKDATA_DBG("pllcon1 %08x\n", cru_readl(PLL_CONS(0,1)));
- CLKDATA_DBG("pllcon2 %08x\n", cru_readl(PLL_CONS(0,2)));
- CLKDATA_DBG("pllcon3 %08x\n", cru_readl(PLL_CONS(0,3)));
- CLKDATA_DBG("clksel0 %08x\n", cru_readl(CRU_CLKSELS_CON(0)));
- CLKDATA_DBG("clksel1 %08x\n", cru_readl(CRU_CLKSELS_CON(1)));
- //rk2928_clock_udelay(5);
-
- //wating lock state
- rk2928_clock_udelay(clk_set->rst_dly);
- pll_wait_lock(pll_id);
-
- //return form slow
- //local_irq_save(flags);
- cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
- loops_per_jiffy = clk_set->lpj;
- local_irq_restore(flags);
- } else {
- // FIXME
- pll_clk_get_set(clk->parent->rate, rate, &refdiv, &fbdiv, &postdiv1, &postdiv2, &frac);
- pll_set_con(clk->pll->id, refdiv, fbdiv, postdiv1, postdiv2, frac);
- }
-
- CLKDATA_DBG("setting OK\n");
- return 0;
-}
-
-static int dpll_clk_set_rate(struct clk *clk, unsigned long rate)
-{
- // FIXME do nothing here
- CLKDATA_DBG("setting OK\n");
- return 0;
-}
-
-static int cpll_clk_set_rate(struct clk *clk, unsigned long rate)
-{
- // FIXME
- struct _pll_data *pll_data=clk->pll;
- struct pll_clk_set *clk_set=(struct pll_clk_set*)pll_data->table;
-
- unsigned long fin_hz, fout_hz;
- u32 refdiv, fbdiv, postdiv1, postdiv2, frac;
- fin_hz = clk->parent->rate;
- fout_hz = rate;
-
- while(clk_set->rate) {
- if (clk_set->rate == rate) {
- break;
- }
- clk_set++;
- }
-
- if(clk_set->rate==rate) {
- CLKDATA_DBG("cpll get a rate\n");
- pll_clk_set_rate(clk_set, pll_data->id);
-
- } else {
- CLKDATA_DBG("cpll get auto calc a rate\n");
- if(pll_clk_get_set(clk->parent->rate, rate, &refdiv, &fbdiv, &postdiv1, &postdiv2, &frac) != 0) {
- pr_err("cpll auto set rate error\n");
- return -ENOENT;
- }
- CLKDATA_DBG("%s get fin=%lu, fout=%lu, rate=%lu, refdiv=%u, fbdiv=%u, postdiv1=%u, postdiv2=%u",
- __func__, fin_hz, fout_hz, rate, refdiv, fbdiv, postdiv1, postdiv2);
- pll_set_con(pll_data->id, refdiv, fbdiv, postdiv1, postdiv2, frac);
-
- }
-
- CLKDATA_DBG("setting OK\n");
- return 0;
-}
-
-static int gpll_clk_set_rate(struct clk *clk, unsigned long rate)
-{
- // FIXME
- struct _pll_data *pll_data=clk->pll;
- struct pll_clk_set *clk_set=(struct pll_clk_set*)pll_data->table;
-
- CLKDATA_DBG("******%s\n", __func__);
- while(clk_set->rate)
- {
- CLKDATA_DBG("******%s clk_set->rate=%lu\n", __func__, clk_set->rate);
- if (clk_set->rate == rate) {
- break;
- }
- clk_set++;
- }
- if(clk_set->rate== rate)
- {
- pll_clk_set_rate(clk_set,pll_data->id);
- //lpj_gpll = CLK_LOOPS_RECALC(rate);
- }
- else
- {
- CLKDATA_ERR("gpll is no corresponding rate=%lu\n", rate);
- return -1;
- }
- CLKDATA_DBG("******%s end\n", __func__);
-
- return 0;
-}
-
-/**********************pll datas*************************/
-static u32 rk2928_clock_flags = 0;
-static struct _pll_data apll_data = SET_PLL_DATA(APLL_ID, (void *)apll_clks);
-static struct _pll_data dpll_data = SET_PLL_DATA(DPLL_ID, NULL);
-static struct _pll_data cpll_data = SET_PLL_DATA(CPLL_ID, (void *)cpll_clks);
-static struct _pll_data gpll_data = SET_PLL_DATA(GPLL_ID, (void *)gpll_clks);
-/*********************************************************/
-/************************clocks***************************/
-/*********************************************************/
-
-static struct clk xin24m = {
- .name = "xin24m",
- .rate = 24 * MHZ,
- .flags = RATE_FIXED,
-};
-
-static struct clk clk_12m = {
- .name = "clk_12m",
- .parent = &xin24m,
- .rate = 12 * MHZ,
- .flags = RATE_FIXED,
-};
-/************************plls***********************/
-static struct clk arm_pll_clk = {
- .name = "arm_pll",
- .parent = &xin24m,
- .mode = pll_clk_mode,
- .recalc = plls_clk_recalc,
- .set_rate = apll_clk_set_rate,
- .round_rate = apll_clk_round_rate,
- .pll = &apll_data,
-};
-
-static struct clk ddr_pll_clk = {
- .name = "ddr_pll",
- .parent = &xin24m,
- .mode = pll_clk_mode,
- .recalc = plls_clk_recalc,
- .set_rate = dpll_clk_set_rate,
- .pll = &dpll_data,
-};
-
-static struct clk codec_pll_clk = {
- .name = "codec_pll",
- .parent = &xin24m,
- .mode = pll_clk_mode,
- .recalc = plls_clk_recalc,
- .set_rate = cpll_clk_set_rate,
- .pll = &cpll_data,
-};
-
-static struct clk general_pll_clk = {
- .name = "general_pll",
- .parent = &xin24m,
- .mode = pll_clk_mode,
- .gate_idx = CLK_GATE_CPU_GPLL,
- .recalc = plls_clk_recalc,
- .set_rate = gpll_clk_set_rate,
- .pll = &gpll_data,
-};
-#define SELECT_FROM_2PLLS_GC {&general_pll_clk, &codec_pll_clk}
-#define SELECT_FROM_2PLLS_CG {&codec_pll_clk, &general_pll_clk}
-/*********ddr******/
-static int ddr_clk_set_rate(struct clk *c, unsigned long rate)
-{
- // need to do nothing
- return 0;
-}
-
-static long ddr_clk_round_rate(struct clk *clk, unsigned long rate)
-{
- return ddr_set_pll(rate / MHZ, 0) * MHZ;
-}
-static unsigned long ddr_clk_recalc_rate(struct clk *clk)
-{
- unsigned long rate = clk->parent->recalc(clk->parent) >> 1;
- return rate;
-}
-
-
-static struct clk clk_ddrphy2x = {
- .name = "ddrphy2x",
- .parent = &ddr_pll_clk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_DDRPHY_SRC,
- .recalc = clksel_recalc_shift,
- //.set_rate = ddr_clk_set_rate,
- .clksel_con = CRU_CLKSELS_CON(26),
-};
-
-static struct clk clk_ddrc = {
- .name = "ddrc",
- .parent = &clk_ddrphy2x,
- .set_rate = ddr_clk_set_rate,
- .recalc = ddr_clk_recalc_rate,
- .round_rate = ddr_clk_round_rate,
- //.recalc = clksel_recalc_fixed_div2,
-};
-
-static struct clk clk_ddrphy = {
- .name = "ddrphy",
- .parent = &clk_ddrphy2x,
- .recalc = clksel_recalc_fixed_div2,
-};
-
-/****************core*******************/
-#if 0
-static unsigned long core_clk_get_rate(struct clk *c)
-{
- u32 div=(get_cru_bits(c->clksel_con,c->div_mask,c->div_shift)+1);
- //c->parent->rate=c->parent->recalc(c->parent);
- return c->parent->rate/div;
-}
-#endif
-static long core_clk_round_rate(struct clk *clk, unsigned long rate)
-{
- u32 div=(get_cru_bits(clk->clksel_con,clk->div_mask,clk->div_shift)+1);
- return clk_round_rate_nolock(clk->parent,rate)/div;
-}
-
-static int core_clksel_set_parent(struct clk *clk, struct clk *new_prt)
-{
- // FIXME
- u32 temp_div;
- struct clk *old_prt;
-
- if(clk->parent==new_prt)
- return 0;
- if (unlikely(!clk->parents))
- return -EINVAL;
- CLKDATA_DBG("%s,reparent %s\n",clk->name,new_prt->name);
- //arm
- old_prt=clk->parent;
-
- if(clk->parents[0]==new_prt)
- {
- new_prt->set_rate(new_prt,300*MHZ);
- set_cru_bits_w_msk(0,clk->div_mask,clk->div_shift,clk->clksel_con);
- }
- else if(clk->parents[1]==new_prt)
- {
-
- if(new_prt->rate>old_prt->rate)
- {
- temp_div=clk_get_freediv(old_prt->rate,new_prt->rate,clk->div_max);
- set_cru_bits_w_msk(temp_div-1,clk->div_mask,clk->div_shift,clk->clksel_con);
- }
- set_cru_bits_w_msk(1,clk->src_mask,clk->src_shift,clk->clksel_con);
- new_prt->set_rate(new_prt,300*MHZ);
- }
- else
- return -1;
-
- return 0;
-}
-
-static struct clk *clk_core_pre_parents[2] = {&arm_pll_clk, &general_pll_clk};
-// this clk is cpu?
-static int arm_core_clk_set_rate(struct clk *c, unsigned long rate)
-{
- int ret;
- //set arm pll div 1
- //set_cru_bits_w_msk(0,c->div_mask,c->div_shift,c->clksel_con);
-
- CLKDATA_DBG("change clk pll %s to %lu\n",c->name,rate);
- ret = clk_set_rate_nolock(c->parent, rate);
- if (ret) {
- CLKDATA_ERR("Failed to change clk pll %s to %lu\n",c->name,rate);
- return ret;
- }
- CLKDATA_DBG("change clk pll %s to %lu OK\n",c->name,rate);
- return 0;
-}
-static struct clk clk_core_pre = {
- //.name = "cpu",
- .name = "core_pre",
- .parent = &arm_pll_clk,
- .recalc = clksel_recalc_div,
- .set_rate = arm_core_clk_set_rate,
- .round_rate = core_clk_round_rate,
- .set_parent = core_clksel_set_parent,
-
- .clksel_con = CRU_CLKSELS_CON(0),
- CRU_DIV_SET(A9_CORE_DIV_MASK, A9_CORE_DIV_SHIFT, 32),
- CRU_SRC_SET(0x1, CORE_CLK_PLL_SEL_SHIFT),
- CRU_PARENTS_SET(clk_core_pre_parents),
-};
-
-static struct clk clk_core_periph = {
- .name = "core_periph",
- .parent = &clk_core_pre,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_CORE_PERIPH,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(1),
- CRU_DIV_SET(CORE_PERIPH_DIV_MASK, CORE_PERIPH_DIV_SHIFT, 16),
-};
-
-static struct clk clken_core_periph = {
- .name = "core_periph_en",
- .parent = &clk_core_periph,
- .recalc = clksel_recalc_equal_parent,
-};
-
-static struct clk clk_l2c = {
- .name = "l2c",
- .parent = &clk_core_pre,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_CLK_L2C,
-};
-
-static struct clk aclk_core_pre = {
- .name = "aclk_core_pre",
- .parent = &clk_core_pre,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_ACLK_CORE,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(1),
- CRU_DIV_SET(ACLK_CORE_DIV_MASK, ACLK_CORE_DIV_SHIFT, 2),
-};
-
-/****************cpu*******************/
-
-static struct clk *clk_cpu_div_parents[] = {&arm_pll_clk, &general_pll_clk};
-/*seperate because of gating*/
-static struct clk clk_cpu_div = {
- .name = "cpu_div",
- .parent = &general_pll_clk,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(0),
- CRU_DIV_SET(ACLK_CPU_DIV_MASK, ACLK_CPU_DIV_SHIFT, 32),
- CRU_SRC_SET(0x1, CPU_CLK_PLL_SEL_SHIFT),
- CRU_PARENTS_SET(clk_cpu_div_parents),
-};
-static struct clk aclk_cpu_pre = {
- .name = "aclk_cpu_pre",
- .parent = &clk_cpu_div,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_ACLK_CPU,
- .recalc = clksel_recalc_equal_parent,
-};
-static struct clk hclk_cpu_pre = {
- .name = "hclk_cpu_pre",
- .parent = &clk_cpu_div,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_HCLK_CPU,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(1),
- CRU_DIV_SET(HCLK_CPU_DIV_MASK, HCLK_CPU_DIV_SHIFT, 4),
-};
-static struct clk pclk_cpu_pre = {
- .name = "pclk_cpu_pre",
- .parent = &clk_cpu_div,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_PCLK_CPU,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(1),
- CRU_DIV_SET(PCLK_CPU_DIV_MASK, PCLK_CPU_DIV_SHIFT, 8),
-};
-/****************vcodec*******************/
-static struct clk *clk_aclk_vepu_parents[] = SELECT_FROM_2PLLS_CG;
-static struct clk *clk_aclk_vdpu_parents[] = SELECT_FROM_2PLLS_CG;
-static struct clk aclk_vepu = {
- .name = "aclk_vepu",
- .parent = &codec_pll_clk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_ACLK_VEPU_SRC,
- .recalc = clksel_recalc_div,
- .clksel_con = CRU_CLKSELS_CON(32),
- .set_rate = clkset_rate_freediv_autosel_parents,
- .round_rate = clk_freediv_round_autosel_parents_rate,
- CRU_DIV_SET(0x1f, 0, 32),
- CRU_SRC_SET(0x1, 7),
- CRU_PARENTS_SET(clk_aclk_vepu_parents),
-};
-static struct clk aclk_vdpu = {
- .name = "aclk_vdpu",
- .parent = &clk_cpu_div,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_ACLK_VDPU_SRC,
- .recalc = clksel_recalc_div,
- .set_rate = clkset_rate_freediv_autosel_parents,
- .round_rate = clk_freediv_round_autosel_parents_rate,
- .clksel_con = CRU_CLKSELS_CON(32),
- CRU_DIV_SET(0x1f, 8, 32),
- CRU_SRC_SET(0x1, 15),
- CRU_PARENTS_SET(clk_aclk_vdpu_parents),
-};
-static struct clk hclk_vepu = {
- .name = "hclk_vepu",
- .parent = &aclk_vepu,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_HCLK_VEPU,
- .recalc = clksel_recalc_fixed_div4,
-};
-static struct clk hclk_vdpu = {
- .name = "hclk_vdpu",
- .parent = &aclk_vdpu,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_HCLK_VDPU,
- .recalc = clksel_recalc_fixed_div4,
-};
-
-/****************vio*******************/
-// name: lcdc0_aclk
-static struct clk *clk_aclk_vio_pre_parents[] = SELECT_FROM_2PLLS_CG;
-static struct clk aclk_vio_pre = {
- .name = "aclk_vio_pre",
- .parent = &general_pll_clk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_ACLK_VIO_SRC,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(31),
- CRU_DIV_SET(0x1f, 0, 32),
- CRU_SRC_SET(0x1, 7),
- CRU_PARENTS_SET(clk_aclk_vio_pre_parents),
-};
-static struct clk hclk_vio_pre = {
- .name = "hclk_vio_pre",
- .parent = &aclk_vio_pre,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_HCLK_VIO_PRE,
- .recalc = clksel_recalc_fixed_div4,
-};
-
-/****************periph*******************/
-static struct clk *peri_aclk_parents[] = SELECT_FROM_2PLLS_GC;
-static struct clk peri_aclk = {
- .name = "peri_aclk",
- .parent = &general_pll_clk,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_PERIPH_SRC,
- .clksel_con = CRU_CLKSELS_CON(10),
- CRU_DIV_SET(PERI_ACLK_DIV_MASK, PERI_ACLK_DIV_SHIFT, 32),
- CRU_SRC_SET(0x1, PERI_PLL_SEL_SHIFT),
- CRU_PARENTS_SET(peri_aclk_parents),
-};
-
-static struct clk peri_hclk = {
- .name = "peri_hclk",
- .parent = &peri_aclk,
- .recalc = clksel_recalc_shift,
- .set_rate = clksel_set_rate_shift,
- .clksel_con = CRU_CLKSELS_CON(10),
- CRU_DIV_SET(PERI_HCLK_DIV_MASK, PERI_HCLK_DIV_SHIFT, 8),
-};
-
-static struct clk peri_pclk = {
- .name = "peri_pclk",
- .parent = &peri_aclk,
- .recalc = clksel_recalc_shift,
- .set_rate = clksel_set_rate_shift,
- .clksel_con = CRU_CLKSELS_CON(10),
- CRU_DIV_SET(PERI_PCLK_DIV_MASK, PERI_PCLK_DIV_SHIFT, 4),
-};
-
-static struct clk aclk_periph_pre = {
- .name = "aclk_periph_pre",
- .parent = &peri_aclk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_ACLK_PERIPH,
- .recalc = clksel_recalc_equal_parent,
-};
-
-static struct clk hclk_periph_pre = {
- .name = "hclk_periph_pre",
- .parent = &peri_hclk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_HCLK_PERIPH,
- .recalc = clksel_recalc_equal_parent,
-};
-
-static struct clk pclk_periph_pre = {
- .name = "pclk_periph_pre",
- .parent = &peri_pclk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_PCLK_PERIPH,
- .recalc = clksel_recalc_equal_parent,
-};
-/****************timer*******************/
-static struct clk *clk_timer0_parents[] = {&xin24m, &peri_pclk};
-static struct clk *clk_timer1_parents[] = {&xin24m, &peri_pclk};
-static struct clk clk_timer0 = {
- .name = "timer0",
- .parent = &xin24m,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_TIMER0,
- .recalc = clksel_recalc_equal_parent,
- .clksel_con = CRU_CLKSELS_CON(2),
- CRU_SRC_SET(0x1, 4),
- CRU_PARENTS_SET(clk_timer0_parents),
-};
-static struct clk clk_timer1 = {
- .name = "timer1",
- .parent = &xin24m,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_TIMER1,
- .recalc = clksel_recalc_equal_parent,
- .clksel_con = CRU_CLKSELS_CON(2),
- CRU_SRC_SET(0x1, 5),
- CRU_PARENTS_SET(clk_timer1_parents),
-};
-/****************spi*******************/
-static struct clk clk_spi = {
- .name = "spi",
- .parent = &peri_pclk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_SPI0_SRC,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(25),
- CRU_DIV_SET(0x7f, 0, 128),
-};
-/****************sdmmc*******************/
-static struct clk *clk_sdmmc0_parents[] = SELECT_FROM_2PLLS_CG;
-static struct clk clk_sdmmc0 = {
- .name = "sdmmc0",
- .parent = &general_pll_clk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_MMC0_SRC,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_even,
- .clksel_con = CRU_CLKSELS_CON(11),
- CRU_SRC_SET(0x1, 6),
- CRU_DIV_SET(0x3f,0,64),
- CRU_PARENTS_SET(clk_sdmmc0_parents),
-};
-#if 0
-static struct clk clk_sdmmc0_sample = {
- .name = "sdmmc0_sample",
- .parent = &general_pll_clk,
- .recalc = ,
- //.set_rate = ,
- .clksel_con = ,
- CRU_DIV_SET(,,),
-};
-static struct clk clk_sdmmc0_drv = {
- .name = "sdmmc0_drv",
- .parent = &clk_sdmmc0,
- .recalc = ,
- //.set_rate = ,
- .clksel_con = ,
- CRU_DIV_SET(,,),
-};
-#endif
-/****************sdio*******************/
-static struct clk *clk_sdio_parents[] = SELECT_FROM_2PLLS_CG;
-static struct clk clk_sdio = {
- .name = "sdio",
- .parent = &general_pll_clk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_SDIO_SRC,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_even,
- .clksel_con = CRU_CLKSELS_CON(12),
- CRU_SRC_SET(0x1, 6),
- CRU_DIV_SET(0x3f,0,64),
- CRU_PARENTS_SET(clk_sdio_parents),
-};
-#if 0
-static struct clk clk_sdio_sample = {
- .name = "sdio_sample",
- .parent = &general_pll_clk,
- .recalc = ,
- //.set_rate = ,
- .clksel_con = ,
- CRU_DIV_SET(,,),
-};
-static struct clk clk_sdio_drv = {
- .name = "sdio_drv",
- .parent = &clk_sdio,
- .recalc = ,
- //.set_rate = ,
- .clksel_con = ,
- CRU_DIV_SET(,,),
-};
-#endif
-/****************emmc*******************/
-static struct clk *clk_emmc_parents[] = SELECT_FROM_2PLLS_CG;
-static struct clk clk_emmc = {
- .name = "emmc",
- .parent = &general_pll_clk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_EMMC_SRC,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con =CRU_CLKSELS_CON(12),
- CRU_SRC_SET(0x1, 7),
- CRU_DIV_SET(0x3f,8,64),
- CRU_PARENTS_SET(clk_emmc_parents),
-};
-#if 0
-static struct clk clk_emmc_sample = {
- .name = "emmc_sample",
- .parent = &general_pll_clk,
- .recalc = ,
- //.set_rate = ,
- .clksel_con = ,
- CRU_DIV_SET(,,),
-};
-static struct clk clk_emmc_drv = {
- .name = "emmc_drv",
- .parent = &clk_emmc,
- .recalc = ,
- //.set_rate = ,
- .clksel_con = ,
- CRU_DIV_SET(,,),
-};
-#endif
-/****************lcdc*******************/
-// DO NOT USE ARM_PLL
-static int sclk_lcdc_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret = 0;
- struct clk *parent;
-
- CLKDATA_DBG("enter %s clk=%s, rate=%lu\n", __func__, clk->name, rate);
- parent = clk->parent;
- ret = clk_set_rate_nolock(parent, rate);
- set_cru_bits_w_msk(0, clk->div_mask, clk->div_shift, clk->clksel_con);
- return ret;
-}
-static struct clk *dclk_lcdc_parents[] = {&codec_pll_clk, &general_pll_clk};
-static struct clk dclk_lcdc = {
- .name = "dclk_lcdc",
- .parent = &general_pll_clk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_DCLK_LCDC0_SRC,
- .recalc = clksel_recalc_div,
- //.set_rate = clkset_rate_freediv_autosel_parents,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(27),
- CRU_DIV_SET(0xff, 8, 256),
- CRU_SRC_SET(0x3, 0),
- CRU_PARENTS_SET(dclk_lcdc_parents),
-};
-static struct clk *sclk_lcdc_parents[] = SELECT_FROM_2PLLS_CG;
-static struct clk sclk_lcdc = {
- .name = "sclk_lcdc",
- .parent = &general_pll_clk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_SCLK_LCDC_SRC,
- .recalc = clksel_recalc_div,
- //.set_rate = clkset_rate_freediv_autosel_parents,
- .set_rate = sclk_lcdc_set_rate,
- .clksel_con = CRU_CLKSELS_CON(28),
- CRU_DIV_SET(0xff, 8, 256),
- CRU_SRC_SET(0x1, 0),
- CRU_PARENTS_SET(sclk_lcdc_parents),
-};
-/****************gps*******************/
-#if 0
-static struct clk hclk_gps_parents = SELECT_FROM_2PLLS_CG;
-static struct clk hclk_gps = {
- .name = "hclk_gps",
- .parent = &general_pll_clk,
- .recalc = ,
- //.set_rate = ,
- .clksel_con = ,
- CRU_DIV_SET(,,),
-};
-#endif
-/****************camera*******************/
-static int cif_out_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret = 0;
- struct clk *parent;
-
- if (rate == 24 * MHZ) {
- parent =clk->parents[1];
- } else {
- parent=clk->parents[0];
- ret = clk_set_rate_nolock(parent, rate);
- if (ret)
- return ret;
- }
- if (clk->parent != parent)
- ret = clk_set_parent_nolock(clk, parent);
-
- return ret;
-}
-static struct clk *clk_cif_out_div_parents[] = SELECT_FROM_2PLLS_CG;
-static struct clk clk_cif_out_div = {
- .name = "cif_out_div",
- .parent = &general_pll_clk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_CIF_OUT_SRC,
- .recalc = clksel_recalc_div,
- //.set_rate = clkset_rate_freediv_autosel_parents,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(29),
- CRU_SRC_SET(0x1, 0),
- CRU_DIV_SET(0x1f, 1, 32),
- CRU_PARENTS_SET(clk_cif_out_div_parents),
-};
-static struct clk *clk_cif_out_parents[] = {&clk_cif_out_div, &xin24m};
-static struct clk clk_cif_out = {
- .name = "cif0_out",
- .parent = &clk_cif_out_div,
- .set_rate = cif_out_set_rate,
- .clksel_con = CRU_CLKSELS_CON(29),
- CRU_SRC_SET(0x1, 7),
- CRU_PARENTS_SET(clk_cif_out_parents),
-};
-
-/*External clock*/
-static struct clk pclkin_cif0 = {
- .name = "pclkin_cif0",
- .mode = gate_mode,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_PCLKIN_CIF,
-};
-
-static struct clk inv_cif0 = {
- .name = "inv_cif0",
- .parent = &pclkin_cif0,
-};
-
-static struct clk *cif0_in_parents[] = {&pclkin_cif0, &inv_cif0};
-static struct clk cif0_in = {
- .name = "cif0_in",
- .parent = &pclkin_cif0,
- .clksel_con = CRU_CLKSELS_CON(30),
- CRU_SRC_SET(0x1, 8),
- CRU_PARENTS_SET(cif0_in_parents),
-};
-
-/****************i2s*******************/
-#define I2S_SRC_DIV (0x0)
-#define I2S_SRC_FRAC (0x1)
-#define I2S_SRC_12M (0x2)
-
-static int i2s_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret = -EINVAL;
- struct clk *parent;
-
- if (rate == clk->parents[I2S_SRC_12M]->rate){
- parent = clk->parents[I2S_SRC_12M];
- }else if((long)clk_round_rate_nolock(clk->parents[I2S_SRC_DIV],rate)==rate)
- {
- parent = clk->parents[I2S_SRC_DIV];
- }
- else
- {
- parent =clk->parents[I2S_SRC_FRAC];
- }
-
- CLKDATA_DBG("%s %s set rate=%lu parent %s(old %s)\n",
- __func__, clk->name,rate,parent->name,clk->parent->name);
-
- if(parent!=clk->parents[I2S_SRC_12M])
- {
- ret = clk_set_rate_nolock(parent,rate);//div 1:1
- if (ret)
- {
- CLKDATA_DBG("%s set rate%lu err\n",clk->name,rate);
- return ret;
- }
- }
-
- if (clk->parent != parent)
- {
- ret = clk_set_parent_nolock(clk, parent);
- if (ret)
- {
- CLKDATA_DBG("%s can't get rate%lu,reparent err\n",clk->name,rate);
- return ret;
- }
- }
-
- return ret;
-};
-static struct clk *clk_i2s_div_parents[] = SELECT_FROM_2PLLS_GC;
-static struct clk clk_i2s_pll = {
- .name = "i2s_pll",
- .parent = &general_pll_clk,
- .clksel_con = CRU_CLKSELS_CON(2),
- CRU_SRC_SET(0x1,15),
- CRU_PARENTS_SET(clk_i2s_div_parents),
-};
-static int i2s_fracdiv_set_rate(struct clk *clk, unsigned long rate)
-{
- u32 numerator, denominator;
- int i = 10;
- //clk_i2s_div->clk_i2s_pll->gpll/cpll
- //clk->parent->parent
- if(frac_div_get_seting(rate,clk->parent->parent->rate,
- &numerator,&denominator)==0)
- {
- clk_set_rate_nolock(clk->parent,clk->parent->parent->rate);//PLL:DIV 1:
- //cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
- while (i--) {
- cru_writel_frac((numerator - 1) << 16 | denominator, clk->clksel_con);
- msleep(1);
- cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
- msleep(1);
- }
-
- CLKDATA_DBG("%s set rate=%lu,is ok\n",clk->name,rate);
- }
- else
- {
- CLKDATA_DBG("clk_frac_div can't get rate=%lu,%s\n",rate,clk->name);
- return -ENOENT;
- }
- return 0;
-}
-
-
-static struct clk clk_i2s_div = {
- .name = "i2s_div",
- .parent = &clk_i2s_pll,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_I2S_SRC,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- //.round_rate = clksel_freediv_round_rate,
- .clksel_con = CRU_CLKSELS_CON(3),
- CRU_DIV_SET(0x7f, 0, 64),
-};
-static struct clk clk_i2s_frac_div = {
- .name = "i2s_frac_div",
- .parent = &clk_i2s_div,
- .recalc = clksel_recalc_frac,
- .set_rate = i2s_fracdiv_set_rate,
- //.round_rate = clksel_freediv_round_rate,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_I2S_FRAC_SRC,
- .clksel_con = CRU_CLKSELS_CON(7),
-};
-
-static struct clk *clk_i2s_parents[] = {&clk_i2s_div, &clk_i2s_frac_div, &clk_12m};
-static struct clk clk_i2s = {
- .name = "i2s",
- .parent = &clk_i2s_div,
- .set_rate = i2s_set_rate,
- .clksel_con = CRU_CLKSELS_CON(3),
- CRU_SRC_SET(0x3, 8),
- CRU_PARENTS_SET(clk_i2s_parents),
-};
-
-/****************otgphy*******************/
-#if 0
-static struct clk clk_otgphy0 = {
- .name = "otgphy0",
- .parent = &clk_12m,
- .recalc = ,
- //.set_rate = ,
- .clksel_con = ,
- CRU_DIV_SET(,,),
-};
-static struct clk clk_otgphy1 = {
- .name = "otgphy1",
- .parent = &clk_12m,
- .recalc = ,
- //.set_rate = ,
- .clksel_con = ,
- CRU_DIV_SET(,,),
-};
-#endif
-GATE_CLK(otgphy0, clk_12m, OTGPHY0);
-GATE_CLK(otgphy1, clk_12m, OTGPHY1);
-/****************saradc*******************/
-static struct clk clk_saradc = {
- .name = "saradc",
- .parent = &xin24m,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_SARADC_SRC,
- .clksel_con = CRU_CLKSELS_CON(24),
- CRU_DIV_SET(0xff,8,256),
-};
-/****************gpu_pre*******************/
-// name: gpu_aclk
-static struct clk *clk_gpu_pre_parents[] = SELECT_FROM_2PLLS_CG;
-static struct clk clk_gpu_pre = {
- //.name = "gpu",
- .name = "gpu_pre",
- .parent = &general_pll_clk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_GPU_PRE,
- .recalc = clksel_recalc_div,
- .set_rate = clkset_rate_freediv_autosel_parents,
- //.set_rate = clksel_set_rate_freediv,
- .round_rate = clk_freediv_round_autosel_parents_rate,
- .clksel_con = CRU_CLKSELS_CON(34),
- CRU_SRC_SET(0x1, 8),
- CRU_DIV_SET(0x1f, 0, 32),
- CRU_PARENTS_SET(clk_gpu_pre_parents),
-};
-/****************uart*******************/
-static int clk_uart_fracdiv_set_rate(struct clk *clk, unsigned long rate)
-{
- u32 numerator, denominator;
- //clk_uart0_div->clk_uart_pll->gpll/cpll
- //clk->parent->parent
- if(frac_div_get_seting(rate,clk->parent->parent->rate,
- &numerator,&denominator)==0)
- {
- clk_set_rate_nolock(clk->parent,clk->parent->parent->rate);//PLL:DIV 1:
-
- cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
-
- CLKDATA_DBG("%s set rate=%lu,is ok\n",clk->name,rate);
- }
- else
- {
- CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n",rate,clk->name);
- return -ENOENT;
- }
- return 0;
-}
-#define UART_SRC_DIV 0
-#define UART_SRC_FRAC 1
-#define UART_SRC_24M 2
-static int clk_uart_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret = 0;
- struct clk *parent;
-
- if(rate==clk->parents[UART_SRC_24M]->rate)//24m
- {
- parent = clk->parents[UART_SRC_24M];
- }
- else if((long)clk_round_rate_nolock(clk->parents[UART_SRC_DIV], rate)==rate)
- {
- parent = clk->parents[UART_SRC_DIV];
- }
- else
- {
- parent = clk->parents[UART_SRC_FRAC];
- }
-
-
-
- CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
- clk->name,rate,parent->name,clk->parent->name);
-
-
- if(parent!=clk->parents[UART_SRC_24M])
- {
- ret = clk_set_rate_nolock(parent,rate);
- if (ret)
- {
- CLKDATA_DBG("%s set rate%lu err\n",clk->name,rate);
- return ret;
- }
- }
-
- if (clk->parent != parent)
- {
- ret = clk_set_parent_nolock(clk, parent);
- if (ret)
- {
- CLKDATA_DBG("%s can't get rate%lu,reparent err\n",clk->name,rate);
- return ret;
- }
- }
-
-
- return ret;
-}
-
-
-static struct clk *clk_uart_pll_src_parents[] = SELECT_FROM_2PLLS_GC;
-static struct clk clk_uart_pll = {
- .name = "uart_pll",
- .parent = &general_pll_clk,
- .clksel_con = CRU_CLKSELS_CON(12),
- CRU_SRC_SET(0x1, 15),
- CRU_PARENTS_SET(clk_uart_pll_src_parents),
-};
-static struct clk clk_uart0_div = {
- .name = "uart0_div",
- .parent = &clk_uart_pll,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_UART0_SRC,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .round_rate = clksel_freediv_round_rate,
- .clksel_con = CRU_CLKSELS_CON(13),
- CRU_DIV_SET(0x7f, 0, 64),
-};
-static struct clk clk_uart1_div = {
- .name = "uart1_div",
- .parent = &clk_uart_pll,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_UART1_SRC,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .round_rate = clksel_freediv_round_rate,
- .clksel_con = CRU_CLKSELS_CON(14),
- CRU_DIV_SET(0x7f, 0, 64),
-};
-static struct clk clk_uart2_div = {
- .name = "uart2_div",
- .parent = &clk_uart_pll,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_UART2_SRC,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .round_rate = clksel_freediv_round_rate,
- .clksel_con = CRU_CLKSELS_CON(15),
- CRU_DIV_SET(0x7f, 0, 64),
-};
-static struct clk clk_uart0_frac_div = {
- .name = "uart0_frac_div",
- .parent = &clk_uart0_div,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_UART0_FRAC_SRC,
- .recalc = clksel_recalc_frac,
- .set_rate = clk_uart_fracdiv_set_rate,
- .clksel_con = CRU_CLKSELS_CON(17),
-};
-static struct clk clk_uart1_frac_div = {
- .name = "uart1_frac_div",
- .parent = &clk_uart1_div,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_UART1_FRAC_SRC,
- .recalc = clksel_recalc_frac,
- .set_rate = clk_uart_fracdiv_set_rate,
- .clksel_con = CRU_CLKSELS_CON(18),
-};
-static struct clk clk_uart2_frac_div = {
- .name = "uart2_frac_div",
- .parent = &clk_uart2_div,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_UART2_FRAC_SRC,
- .recalc = clksel_recalc_frac,
- .set_rate = clk_uart_fracdiv_set_rate,
- .clksel_con = CRU_CLKSELS_CON(19),
-};
-
-static struct clk *clk_uart0_parents[] = {&clk_uart0_div, &clk_uart0_frac_div, &xin24m};
-static struct clk *clk_uart1_parents[] = {&clk_uart1_div, &clk_uart1_frac_div, &xin24m};
-static struct clk *clk_uart2_parents[] = {&clk_uart2_div, &clk_uart2_frac_div, &xin24m};
-static struct clk clk_uart0= {
- .name = "uart0",
- .parent = &xin24m,
- .set_rate = clk_uart_set_rate,
- .clksel_con = CRU_CLKSELS_CON(13),
- CRU_SRC_SET(0x3, 8),
- CRU_PARENTS_SET(clk_uart0_parents),
-};
-static struct clk clk_uart1= {
- .name = "uart1",
- .parent = &xin24m,
- .set_rate = clk_uart_set_rate,
- .clksel_con = CRU_CLKSELS_CON(14),
- CRU_SRC_SET(0x3, 8),
- CRU_PARENTS_SET(clk_uart1_parents),
-};
-static struct clk clk_uart2= {
- .name = "uart2",
- .parent = &xin24m,
- .set_rate = clk_uart_set_rate,
- .clksel_con = CRU_CLKSELS_CON(15),
- CRU_SRC_SET(0x3, 8),
- CRU_PARENTS_SET(clk_uart2_parents),
-};
-/****************sub clock---pre*******************/
-/*************************aclk_cpu***********************/
-GATE_CLK(aclk_intmem, aclk_cpu_pre, ACLK_INTMEM);
-GATE_CLK(aclk_strc_sys, aclk_cpu_pre, ACLK_STRC_SYS);
-
-/*************************hclk_cpu***********************/
-//FIXME
-//GATE_CLK(hclk_cpubus, hclk_cpu_pre, HCLK_CPUBUS);
-GATE_CLK(hclk_rom, hclk_cpu_pre, HCLK_ROM);
-
-/*************************pclk_cpu***********************/
-//FIXME
-GATE_CLK(pclk_hdmi, pclk_cpu_pre, PCLK_HDMI);
-GATE_CLK(pclk_ddrupctl, pclk_cpu_pre, PCLK_DDRUPCTL);
-GATE_CLK(pclk_grf, pclk_cpu_pre, PCLK_GRF);
-GATE_CLK(pclk_acodec, pclk_cpu_pre, PCLK_ACODEC);
-
-/*************************aclk_periph********************/
-GATE_CLK(aclk_dma2, aclk_periph_pre, ACLK_DMAC2);
-GATE_CLK(aclk_peri_niu, aclk_periph_pre, ACLK_PERI_NIU);
-GATE_CLK(aclk_cpu_peri, aclk_periph_pre, ACLK_CPU_PERI);
-GATE_CLK(aclk_peri_axi_matrix, aclk_periph_pre, ACLK_PERI_AXI_MATRIX);
-GATE_CLK(aclk_gps, aclk_periph_pre, ACLK_GPS);
-
-/*************************hclk_periph***********************/
-GATE_CLK(hclk_peri_axi_matrix, hclk_periph_pre, HCLK_PERI_AXI_MATRIX);
-GATE_CLK(hclk_peri_ahb_arbi, hclk_periph_pre, HCLK_PERI_ARBI);
-GATE_CLK(nandc, hclk_periph_pre, HCLK_NANDC);
-GATE_CLK(hclk_usb_peri, hclk_periph_pre, HCLK_USB_PERI);
-GATE_CLK(hclk_otg0, clk_hclk_usb_peri, HCLK_OTG0); // is not parent in clk tree, but when hclk_otg0/1 open,
-GATE_CLK(hclk_otg1, clk_hclk_usb_peri, HCLK_OTG1); // must open hclk_usb_peri
-GATE_CLK(hclk_i2s, hclk_periph_pre, HCLK_I2S);
-GATE_CLK(hclk_sdmmc0, hclk_periph_pre, HCLK_SDMMC0);
-GATE_CLK(hclk_sdio, hclk_periph_pre, HCLK_SDIO);
-GATE_CLK(hclk_emmc, hclk_periph_pre, HCLK_EMMC);
-
-/*************************pclk_periph***********************/
-GATE_CLK(pclk_peri_axi_matrix, pclk_periph_pre, PCLK_PERI_AXI_MATRIX);
-GATE_CLK(pclk_pwm01, pclk_periph_pre, PCLK_PWM01);
-GATE_CLK(pclk_wdt, pclk_periph_pre, PCLK_WDT);
-GATE_CLK(pclk_spi0, pclk_periph_pre, PCLK_SPI0);
-GATE_CLK(pclk_uart0, pclk_periph_pre, PCLK_UART0);
-GATE_CLK(pclk_uart1, pclk_periph_pre, PCLK_UART1);
-GATE_CLK(pclk_uart2, pclk_periph_pre, PCLK_UART2);
-GATE_CLK(pclk_i2c0, pclk_periph_pre, PCLK_I2C0);
-GATE_CLK(pclk_i2c1, pclk_periph_pre, PCLK_I2C1);
-GATE_CLK(pclk_i2c2, pclk_periph_pre, PCLK_I2C2);
-GATE_CLK(pclk_i2c3, pclk_periph_pre, PCLK_I2C3);
-GATE_CLK(pclk_timer0, pclk_periph_pre, PCLK_TIMER0);
-GATE_CLK(pclk_timer1, pclk_periph_pre, PCLK_TIMER1);
-GATE_CLK(gpio0, pclk_periph_pre, PCLK_GPIO0);
-GATE_CLK(gpio1, pclk_periph_pre, PCLK_GPIO1);
-GATE_CLK(gpio2, pclk_periph_pre, PCLK_GPIO2);
-GATE_CLK(gpio3, pclk_periph_pre, PCLK_GPIO3);
-GATE_CLK(pclk_saradc, pclk_periph_pre, PCLK_SARADC);
-GATE_CLK(pclk_efuse, pclk_periph_pre, PCLK_EFUSE);
-
-/*************************aclk_vio***********************/
-GATE_CLK(aclk_vio0, aclk_vio_pre, ACLK_VIO0);
-GATE_CLK(aclk_lcdc0, aclk_vio_pre, ACLK_LCDC0);
-GATE_CLK(aclk_cif0, aclk_vio_pre, ACLK_CIF);
-GATE_CLK(aclk_rga, aclk_vio_pre, ACLK_RGA);
-
-/*************************hclk_vio***********************/
-GATE_CLK(hclk_lcdc0, hclk_vio_pre, HCLK_LCDC0);
-GATE_CLK(hclk_cif0, hclk_vio_pre, HCLK_CIF);
-GATE_CLK(hclk_rga, hclk_vio_pre, HCLK_RGA);
-GATE_CLK(hclk_vio_bus, hclk_vio_pre, HCLK_VIO_BUS);
-
-/* Power domain, not exist in fact*/
-enum pmu_power_domain {
- PD_A9_0 = 0,
- PD_A9_1,
- PD_ALIVE,
- PD_RTC,
- PD_SCU,
- PD_CPU,
- PD_PERI = 6,
- PD_VIO,
- PD_VIDEO,
- PD_VCODEC = PD_VIDEO,
- PD_GPU,
- PD_DBG,
-};
-
-static int pm_off_mode(struct clk *clk, int on)
-{
- return 0;
-}
-static struct clk pd_peri = {
- .name = "pd_peri",
- .flags = IS_PD,
- .mode = pm_off_mode,
- .gate_idx = PD_PERI,
-};
-
-static int pd_display_mode(struct clk *clk, int on)
-{
- return 0;
-}
-
-static struct clk pd_display = {
- .name = "pd_display",
- .flags = IS_PD,
- .mode = pd_display_mode,
- .gate_idx = PD_VIO,
-};
-
-static struct clk pd_lcdc0 = {
- .parent = &pd_display,
- .name = "pd_lcdc0",
-};
-static struct clk pd_lcdc1 = {
- .parent = &pd_display,
- .name = "pd_lcdc1",
-};
-static struct clk pd_cif0 = {
- .parent = &pd_display,
- .name = "pd_cif0",
-};
-static struct clk pd_cif1 = {
- .parent = &pd_display,
- .name = "pd_cif1",
-};
-static struct clk pd_rga = {
- .parent = &pd_display,
- .name = "pd_rga",
-};
-static struct clk pd_ipp = {
- .parent = &pd_display,
- .name = "pd_ipp",
-};
-static int pd_video_mode(struct clk *clk, int on)
-{
- return 0;
-}
-
-static struct clk pd_video = {
- .name = "pd_video",
- .flags = IS_PD,
- .mode = pd_video_mode,
- .gate_idx = PD_VIDEO,
-};
-
-static int pd_gpu_mode(struct clk *clk, int on)
-{
- return 0;
-}
-
-static struct clk pd_gpu = {
- .name = "pd_gpu",
- .flags = IS_PD,
- .mode = pd_gpu_mode,
- .gate_idx = PD_GPU,
-};
-static struct clk pd_dbg = {
- .name = "pd_dbg",
- .flags = IS_PD,
- .mode = pm_off_mode,
- .gate_idx = PD_DBG,
-};
-
-#define PD_CLK(name) \
-{\
- .dev_id = NULL,\
- .con_id = #name,\
- .clk = &name,\
-}
-/* Power domain END, not exist in fact*/
-
-#define CLK(dev, con, ck) \
-{\
- .dev_id = dev,\
- .con_id = con,\
- .clk = ck,\
-}
-
-#define CLK_GATE_NODEV(name) \
-{\
- .dev_id = NULL,\
- .con_id = #name,\
- .clk = &clk_##name,\
-}
-
-static struct clk_lookup clks[] = {
- CLK(NULL, "xin24m", &xin24m),
- CLK(NULL, "xin12m", &clk_12m),
-
- CLK(NULL, "arm_pll", &arm_pll_clk),
- CLK(NULL, "ddr_pll", &ddr_pll_clk),
- CLK(NULL, "codec_pll", &codec_pll_clk),
- CLK(NULL, "general_pll", &general_pll_clk),
-
- CLK(NULL, "ddrphy2x", &clk_ddrphy2x),
- CLK(NULL, "ddrphy", &clk_ddrphy),
- CLK(NULL, "ddr", &clk_ddrc),
-
- CLK(NULL, "cpu", &clk_core_pre),
- CLK(NULL, "core_periph", &clk_core_periph),
- CLK(NULL, "core_periph_en", &clken_core_periph),
- CLK(NULL, "l2c", &clk_l2c),
- CLK(NULL, "aclk_core_pre", &aclk_core_pre),
-
- CLK(NULL, "cpu_div", &clk_cpu_div),
- CLK(NULL, "aclk_cpu_pre", &aclk_cpu_pre),
- CLK(NULL, "pclk_cpu_pre", &pclk_cpu_pre),
- CLK(NULL, "hclk_cpu_pre", &hclk_cpu_pre),
-
- CLK(NULL, "aclk_vepu", &aclk_vepu),
- CLK(NULL, "aclk_vdpu", &aclk_vdpu),
- CLK(NULL, "hclk_vepu", &hclk_vepu),
- CLK(NULL, "hclk_vdpu", &hclk_vdpu),
-
- CLK(NULL, "aclk_vio_pre", &aclk_vio_pre),
- CLK(NULL, "hclk_vio_pre", &hclk_vio_pre),
-
- CLK(NULL, "peri_aclk", &peri_aclk),
- CLK(NULL, "peri_pclk", &peri_pclk),
- CLK(NULL, "peri_hclk", &peri_hclk),
-
- CLK(NULL, "timer0", &clk_timer0),
- CLK(NULL, "timer1", &clk_timer1),
-
- CLK("rk29xx_spim.0", "spi", &clk_spi),
-
- CLK("rk29_sdmmc.0", "mmc", &clk_sdmmc0),
- //CLK("rk29_sdmmc.0", "mmc_sample", &clk_sdmmc0_sample),
- //CLK("rk29_sdmmc.0", "mmc_drv", &clk_sdmmc0_drv),
-
- CLK("rk29_sdmmc.1", "mmc", &clk_sdio),
- //CLK("rk29_sdmmc.1", "mmc_sample", &clk_sdio_sample),
- //CLK("rk29_sdmmc.1", "mmc_drv", &clk_sdio_drv),
-
- CLK(NULL, "emmc", &clk_emmc),
- //CLK(NULL, "emmc_sample", &clk_emmc_sample),
- //CLK(NULL, "emmc_drv", &clk_emmc_drv),
-
- CLK(NULL, "dclk_lcdc0", &dclk_lcdc),
- CLK(NULL, "sclk_lcdc0", &sclk_lcdc),
- //FIXME
- //CLK(NULL, "hclk_gps", &hclk_gps),
-
- CLK(NULL, "cif0_out_div", &clk_cif_out_div),
- CLK(NULL, "cif0_out", &clk_cif_out),
- CLK(NULL, "pclkin_cif0", &pclkin_cif0),
- CLK(NULL, "inv_cif0", &inv_cif0),
- CLK(NULL, "cif0_in", &cif0_in),
-
- CLK(NULL, "i2s_pll", &clk_i2s_pll),
- CLK("rk29_i2s.0", "i2s_div", &clk_i2s_div),
- CLK("rk29_i2s.0", "i2s_frac_div", &clk_i2s_frac_div),
- CLK("rk29_i2s.0", "i2s", &clk_i2s),
-
- CLK(NULL, "otgphy0", &clk_otgphy0),
- CLK(NULL, "otgphy1", &clk_otgphy1),
- CLK(NULL, "saradc", &clk_saradc),
- CLK(NULL, "gpu", &clk_gpu_pre),
-
- CLK(NULL, "uart_pll", &clk_uart_pll),
- CLK("rk_serial.0", "uart_div", &clk_uart0_div),
- CLK("rk_serial.1", "uart_div", &clk_uart1_div),
- CLK("rk_serial.2", "uart_div", &clk_uart2_div),
- CLK("rk_serial.0", "uart_frac_div", &clk_uart0_frac_div),
- CLK("rk_serial.1", "uart_frac_div", &clk_uart1_frac_div),
- CLK("rk_serial.2", "uart_frac_div", &clk_uart2_frac_div),
- CLK("rk_serial.0", "uart", &clk_uart0),
- CLK("rk_serial.1", "uart", &clk_uart1),
- CLK("rk_serial.2", "uart", &clk_uart2),
-
- CLK(NULL, "aclk_periph_pre", &aclk_periph_pre),
- CLK(NULL, "hclk_periph_pre", &hclk_periph_pre),
- CLK(NULL, "pclk_periph_pre", &pclk_periph_pre),
-
- /*********fixed clock ******/
- CLK_GATE_NODEV(aclk_intmem),
- CLK_GATE_NODEV(aclk_strc_sys),
-
- //FIXME
- //CLK_GATE_NODEV(hclk_cpubus),
- CLK_GATE_NODEV(hclk_rom),
-
- //FIXME
- CLK_GATE_NODEV(pclk_hdmi),
- CLK_GATE_NODEV(pclk_ddrupctl),
- CLK_GATE_NODEV(pclk_grf),
- CLK_GATE_NODEV(pclk_acodec),
-
- CLK_GATE_NODEV(aclk_dma2),
- CLK_GATE_NODEV(aclk_peri_niu),
- CLK_GATE_NODEV(aclk_cpu_peri),
- CLK_GATE_NODEV(aclk_peri_axi_matrix),
- CLK_GATE_NODEV(aclk_gps),
-
- CLK_GATE_NODEV(hclk_peri_axi_matrix),
- CLK_GATE_NODEV(hclk_peri_ahb_arbi),
- CLK_GATE_NODEV(nandc),
- CLK_GATE_NODEV(hclk_usb_peri),
- CLK_GATE_NODEV(hclk_otg0),
- CLK_GATE_NODEV(hclk_otg1),
- CLK_GATE_NODEV(hclk_i2s),
- CLK("rk29_sdmmc.0", "hclk_mmc", &clk_hclk_sdmmc0),
- CLK("rk29_sdmmc.1", "hclk_mmc", &clk_hclk_sdio),
- CLK(NULL, "hclk_emmc", &clk_hclk_emmc),
-
- CLK_GATE_NODEV(pclk_peri_axi_matrix),
- CLK(NULL, "pwm01", &clk_pclk_pwm01),
- CLK_GATE_NODEV(pclk_wdt),
- CLK("rk29xx_spim.0", "pclk_spi", &clk_pclk_spi0),
- CLK("rk_serial.0", "pclk_uart", &clk_pclk_uart0),
- CLK("rk_serial.1", "pclk_uart", &clk_pclk_uart1),
- CLK("rk_serial.2", "pclk_uart", &clk_pclk_uart2),
- CLK("rk30_i2c.0", "i2c", &clk_pclk_i2c0),
- CLK("rk30_i2c.1", "i2c", &clk_pclk_i2c1),
- CLK("rk30_i2c.2", "i2c", &clk_pclk_i2c2),
- CLK("rk30_i2c.3", "i2c", &clk_pclk_i2c3),
- CLK_GATE_NODEV(pclk_timer0),
- CLK_GATE_NODEV(pclk_timer1),
- CLK_GATE_NODEV(gpio0),
- CLK_GATE_NODEV(gpio1),
- CLK_GATE_NODEV(gpio2),
- CLK_GATE_NODEV(gpio3),
- CLK_GATE_NODEV(pclk_saradc),
- CLK_GATE_NODEV(pclk_efuse),
-
- CLK_GATE_NODEV(aclk_vio0),
- CLK_GATE_NODEV(aclk_lcdc0),
- CLK_GATE_NODEV(aclk_cif0),
- CLK_GATE_NODEV(aclk_rga),
-
- CLK_GATE_NODEV(hclk_lcdc0),
- CLK_GATE_NODEV(hclk_cif0),
- CLK_GATE_NODEV(hclk_rga),
- CLK_GATE_NODEV(hclk_vio_bus),
-
- /* Power domain, not exist in fact*/
- PD_CLK(pd_peri),
- PD_CLK(pd_display),
- PD_CLK(pd_video),
- PD_CLK(pd_lcdc0),
- PD_CLK(pd_lcdc1),
- PD_CLK(pd_cif0),
- PD_CLK(pd_cif1),
- PD_CLK(pd_rga),
- PD_CLK(pd_ipp),
- PD_CLK(pd_video),
- PD_CLK(pd_gpu),
- PD_CLK(pd_dbg),
-
-};
-
-static void __init rk30_init_enable_clocks(void)
-{
- CLKDATA_DBG("ENTER %s\n", __func__);
- // core
- clk_enable_nolock(&clk_core_pre);
- clk_enable_nolock(&clk_core_periph);
- clk_enable_nolock(&clken_core_periph);
- clk_enable_nolock(&clk_l2c);
- clk_enable_nolock(&aclk_core_pre);
-
- // logic
- clk_enable_nolock(&aclk_cpu_pre);
- clk_enable_nolock(&hclk_cpu_pre);
- clk_enable_nolock(&pclk_cpu_pre);
-
- // ddr
- clk_enable_nolock(&clk_ddrc);
- clk_enable_nolock(&clk_ddrphy);
- clk_enable_nolock(&clk_ddrphy2x);
-
- clk_enable_nolock(&aclk_periph_pre);
- clk_enable_nolock(&pclk_periph_pre);
- clk_enable_nolock(&hclk_periph_pre);
-
- // others
- clk_enable_nolock(&clk_aclk_vio0);
- clk_enable_nolock(&clk_pclk_pwm01);
- clk_enable_nolock(&clk_hclk_otg0);
- clk_enable_nolock(&clk_hclk_otg1);
-
-#if CONFIG_RK_DEBUG_UART == 0
- clk_enable_nolock(&clk_uart0);
- clk_enable_nolock(&clk_pclk_uart0);
-
-#elif CONFIG_RK_DEBUG_UART == 1
- clk_enable_nolock(&clk_uart1);
- clk_enable_nolock(&clk_pclk_uart1);
-
-#elif CONFIG_RK_DEBUG_UART == 2
- clk_enable_nolock(&clk_uart2);
- clk_enable_nolock(&clk_pclk_uart2);
-#endif
-
- /*************************aclk_cpu***********************/
- clk_enable_nolock(&clk_aclk_intmem);
- clk_enable_nolock(&clk_aclk_strc_sys);
-
- /*************************hclk_cpu***********************/
- clk_enable_nolock(&clk_hclk_rom);
-
- /*************************pclk_cpu***********************/
- clk_enable_nolock(&clk_pclk_ddrupctl);
- clk_enable_nolock(&clk_pclk_grf);
-
- /*************************aclk_periph***********************/
- clk_enable_nolock(&clk_aclk_dma2);
- clk_enable_nolock(&clk_aclk_peri_niu);
- clk_enable_nolock(&clk_aclk_cpu_peri);
- clk_enable_nolock(&clk_aclk_peri_axi_matrix);
-
- /*************************hclk_periph***********************/
- clk_enable_nolock(&clk_hclk_peri_axi_matrix);
- clk_enable_nolock(&clk_hclk_peri_ahb_arbi);
- clk_enable_nolock(&clk_nandc);
-
- /*************************pclk_periph***********************/
- clk_enable_nolock(&clk_pclk_peri_axi_matrix);
- /*************************hclk_vio***********************/
- clk_enable_nolock(&clk_hclk_vio_bus);
-}
-
-
-static void rk_dump_clock(struct clk *clk, int deep, const struct list_head *root_clocks)
-{
- struct clk *ck;
- int i;
- unsigned long rate = clk->rate;
- for (i = 0; i < deep; i++)
- printk(" ");
-
- printk("%-11s ", clk->name);
- if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
- int idx = clk->gate_idx;
- u32 v;
- v = cru_readl(CLK_GATE_CLKID_CONS(idx)) & ((0x1) << (idx % 16));
- printk("%s ", v ? "off" : "on ");
- }
-
- if (clk->pll) {
- u32 pll_mode;
- u32 pll_id = clk->pll->id;
- pll_mode = cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id);
- if (pll_mode == (PLL_MODE_SLOW(pll_id) & PLL_MODE_MSK(pll_id)))
- printk("slow ");
- else if (pll_mode == (PLL_MODE_NORM(pll_id) & PLL_MODE_MSK(pll_id)))
- printk("normal ");
- //else if (pll_mode == (PLL_MODE_DEEP(pll_id) & PLL_MODE_MSK(pll_id)))
- // printk("deep ");
-
- if(cru_readl(PLL_CONS(pll_id, 3)) & PLL_BYPASS)
- printk("bypass ");
- } else if(clk == &clk_ddrc) {
- rate = clk->recalc(clk);
- }
-
- if (rate >= MHZ) {
- if (rate % MHZ)
- printk("%ld.%06ld MHz", rate / MHZ, rate % MHZ);
- else
- printk("%ld MHz", rate / MHZ);
- } else if (rate >= KHZ) {
- if (rate % KHZ)
- printk("%ld.%03ld KHz", rate / KHZ, rate % KHZ);
- else
- printk("%ld KHz", rate / KHZ);
- } else {
- printk("%ld Hz", rate);
- }
-
- printk(" usecount = %d", clk->usecount);
-
- if (clk->parent)
- printk(" parent = %s", clk->parent->name);
-
- printk("\n");
-
- list_for_each_entry(ck, root_clocks, node) {
- if (ck->parent == clk)
- rk_dump_clock(ck, deep + 1, root_clocks);
- }
-}
-
-#if 1
-extern struct list_head *get_rk_clocks_head(void);
-
-void rk_dump_clock_info(void)
-{
- struct clk* clk;
- list_for_each_entry(clk, get_rk_clocks_head(), node) {
- if (!clk->parent)
- rk_dump_clock(clk, 0,get_rk_clocks_head());
- }
-}
-#endif
-
-#ifdef CONFIG_PROC_FS
-static void dump_clock(struct seq_file *s, struct clk *clk, int deep,const struct list_head *root_clocks)
-{
- struct clk* ck;
- int i;
- unsigned long rate = clk->rate;
- //CLKDATA_DBG("dump_clock %s\n",clk->name);
- for (i = 0; i < deep; i++)
- seq_printf(s, " ");
-
- seq_printf(s, "%-11s ", clk->name);
-
- if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
- int idx = clk->gate_idx;
- u32 v;
- v = cru_readl(CLK_GATE_CLKID_CONS(idx))&((0x1)<<(idx%16));
- seq_printf(s, "%s ", v ? "off" : "on ");
- }
-
- if (clk->pll)
- {
- u32 pll_mode;
- u32 pll_id=clk->pll->id;
- pll_mode=cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id);
- if (pll_mode == (PLL_MODE_SLOW(pll_id) & PLL_MODE_MSK(pll_id)))
- seq_printf(s, "slow ");
- else if (pll_mode == (PLL_MODE_NORM(pll_id) & PLL_MODE_MSK(pll_id)))
- seq_printf(s, "normal ");
- if(cru_readl(PLL_CONS(pll_id,3)) & PLL_BYPASS)
- seq_printf(s, "bypass ");
- }
- else if(clk == &ddr_pll_clk) {
- rate = clk->recalc(clk);
- }
-
- if (rate >= MHZ) {
- if (rate % MHZ)
- seq_printf(s, "%ld.%06ld MHz", rate / MHZ, rate % MHZ);
- else
- seq_printf(s, "%ld MHz", rate / MHZ);
- } else if (rate >= KHZ) {
- if (rate % KHZ)
- seq_printf(s, "%ld.%03ld KHz", rate / KHZ, rate % KHZ);
- else
- seq_printf(s, "%ld KHz", rate / KHZ);
- } else {
- seq_printf(s, "%ld Hz", rate);
- }
-
- seq_printf(s, " usecount = %d", clk->usecount);
-
- if (clk->parent)
- seq_printf(s, " parent = %s", clk->parent->name);
-
- seq_printf(s, "\n");
-
- list_for_each_entry(ck, root_clocks, node) {
- if (ck->parent == clk)
- dump_clock(s, ck, deep + 1,root_clocks);
- }
-}
-
-static void dump_regs(struct seq_file *s)
-{
- int i=0;
- seq_printf(s, "\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
- seq_printf(s, "\nPLLRegisters:\n");
- for(i=0;i<END_PLL_ID;i++)
- {
- seq_printf(s,"pll%d :cons:%x,%x,%x,%x\n",i,
- cru_readl(PLL_CONS(i,0)),
- cru_readl(PLL_CONS(i,1)),
- cru_readl(PLL_CONS(i,2)),
- cru_readl(PLL_CONS(i,3))
- );
- }
- seq_printf(s, "MODE :%x\n", cru_readl(CRU_MODE_CON));
-
- for(i=0;i<CRU_CLKSELS_CON_CNT;i++)
- {
- seq_printf(s,"CLKSEL%d :%x\n",i,cru_readl(CRU_CLKSELS_CON(i)));
- }
- for(i=0;i<CRU_CLKGATES_CON_CNT;i++)
- {
- seq_printf(s,"CLKGATE%d :%x\n",i,cru_readl(CRU_CLKGATES_CON(i)));
- }
- seq_printf(s,"GLB_SRST_FST:%x\n",cru_readl(CRU_GLB_SRST_FST));
- seq_printf(s,"GLB_SRST_SND:%x\n",cru_readl(CRU_GLB_SRST_SND));
-
- for(i=0;i<CRU_SOFTRSTS_CON_CNT;i++)
- {
- seq_printf(s,"CLKGATE%d :%x\n",i,cru_readl(CRU_SOFTRSTS_CON(i)));
- }
- seq_printf(s,"CRU MISC :%x\n",cru_readl(CRU_MISC_CON));
- seq_printf(s,"GLB_CNT_TH :%x\n",cru_readl(CRU_GLB_CNT_TH));
-
-}
-
-void rk30_clk_dump_regs(void)
-{
- int i=0;
- CLKDATA_DBG("\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
- CLKDATA_DBG("\nPLLRegisters:\n");
- for(i=0;i<END_PLL_ID;i++)
- {
- CLKDATA_DBG("pll%d :cons:%x,%x,%x,%x\n",i,
- cru_readl(PLL_CONS(i,0)),
- cru_readl(PLL_CONS(i,1)),
- cru_readl(PLL_CONS(i,2)),
- cru_readl(PLL_CONS(i,3))
- );
- }
- CLKDATA_DBG("MODE :%x\n", cru_readl(CRU_MODE_CON));
-
- for(i=0;i<CRU_CLKSELS_CON_CNT;i++)
- {
- CLKDATA_DBG("CLKSEL%d :%x\n",i,cru_readl(CRU_CLKSELS_CON(i)));
- }
- for(i=0;i<CRU_CLKGATES_CON_CNT;i++)
- {
- CLKDATA_DBG("CLKGATE%d :%x\n",i,cru_readl(CRU_CLKGATES_CON(i)));
- }
- CLKDATA_DBG("GLB_SRST_FST:%x\n",cru_readl(CRU_GLB_SRST_FST));
- CLKDATA_DBG("GLB_SRST_SND:%x\n",cru_readl(CRU_GLB_SRST_SND));
-
- for(i=0;i<CRU_SOFTRSTS_CON_CNT;i++)
- {
- CLKDATA_DBG("SOFTRST%d :%x\n",i,cru_readl(CRU_SOFTRSTS_CON(i)));
- }
- CLKDATA_DBG("CRU MISC :%x\n",cru_readl(CRU_MISC_CON));
- CLKDATA_DBG("GLB_CNT_TH :%x\n",cru_readl(CRU_GLB_CNT_TH));
-
-}
-
-static struct clk def_ops_clk={
- .get_parent=clksel_get_parent,
- .set_parent=clksel_set_parent,
-};
-#ifdef CONFIG_PROC_FS
-static void dump_clock(struct seq_file *s, struct clk *clk, int deep,const struct list_head *root_clocks);
-struct clk_dump_ops dump_ops={
- .dump_clk=dump_clock,
- .dump_regs=dump_regs,
-};
-#endif
-#endif
-
-static void periph_clk_set_init(void)
-{
- unsigned long aclk_p, hclk_p, pclk_p;
- unsigned long gpll_rate=general_pll_clk.rate;
- //aclk 148.5
-
- /* general pll */
- switch (gpll_rate) {
- case 148500* KHZ:
- aclk_p = 148500*KHZ;
- hclk_p = aclk_p>>1;
- pclk_p = aclk_p>>2;
- break;
- case 1188*MHZ:
- aclk_p = aclk_p>>3;// 0
- hclk_p = aclk_p>>1;
- pclk_p = aclk_p>>2;
-
- case 297 * MHZ:
- aclk_p = gpll_rate>>0;
- hclk_p = aclk_p>>1;
- pclk_p = aclk_p>>1;
- break;
-
- case 300 * MHZ:
- aclk_p = gpll_rate>>1;
- hclk_p = aclk_p>>0;
- pclk_p = aclk_p>>1;
- break;
- default:
- aclk_p = 150 * MHZ;
- hclk_p = 150 * MHZ;
- pclk_p = 75 * MHZ;
- break;
- }
- clk_set_parent_nolock(&peri_aclk, &general_pll_clk);
- clk_set_rate_nolock(&peri_aclk, aclk_p);
- clk_set_rate_nolock(&peri_hclk, hclk_p);
- clk_set_rate_nolock(&peri_pclk, pclk_p);
-}
-
-static void cpu_axi_init(void)
-{
- unsigned long aclk_cpu_rate, hclk_cpu_rate, pclk_cpu_rate;
- unsigned long gpll_rate = general_pll_clk.rate;
-
- switch (gpll_rate) {
- case 297 * MHZ:
- aclk_cpu_rate = gpll_rate >> 0;
- hclk_cpu_rate = aclk_cpu_rate >> 1;
- pclk_cpu_rate = aclk_cpu_rate >> 2;
- break;
-
- default:
- aclk_cpu_rate = 150 * MHZ;
- hclk_cpu_rate = 150 * MHZ;
- pclk_cpu_rate = 75 * MHZ;
- break;
- }
-
- clk_set_parent_nolock(&clk_cpu_div, &general_pll_clk);
- clk_set_rate_nolock(&clk_cpu_div, gpll_rate);
- clk_set_rate_nolock(&aclk_cpu_pre, aclk_cpu_rate);
- clk_set_rate_nolock(&hclk_cpu_pre, hclk_cpu_rate);
- clk_set_rate_nolock(&pclk_cpu_pre, pclk_cpu_rate);
-}
-
-#define CLK_FLG_MAX_I2S_12288KHZ (1<<1)
-#define CLK_FLG_MAX_I2S_22579_2KHZ (1<<2)
-#define CLK_FLG_MAX_I2S_24576KHZ (1<<3)
-#define CLK_FLG_MAX_I2S_49152KHZ (1<<4)
-
-void rk2928_clock_common_i2s_init(void)
-{
- unsigned long i2s_rate;
- //struct clk *max_clk,*min_clk;
- //20 times
- if(rk2928_clock_flags & CLK_FLG_MAX_I2S_49152KHZ) {
- i2s_rate = 49152000;
-
- } else if(rk2928_clock_flags & CLK_FLG_MAX_I2S_24576KHZ) {
- i2s_rate = 24576000;
-
- } else if(rk2928_clock_flags & CLK_FLG_MAX_I2S_22579_2KHZ) {
- i2s_rate = 22579000;
-
- } else if(rk2928_clock_flags & CLK_FLG_MAX_I2S_12288KHZ) {
- i2s_rate = 12288000;
-
- } else {
- i2s_rate = 49152000;
- }
-
- if(((i2s_rate * 20) <= codec_pll_clk.rate)
- || !(codec_pll_clk.rate % i2s_rate)) {
- clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
-
- } else if(((i2s_rate * 20) <= general_pll_clk.rate)
- || !(general_pll_clk.rate % i2s_rate)) {
- clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
-
- } else {
- if(general_pll_clk.rate > codec_pll_clk.rate)
- clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
- else
- clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
- }
-
-}
-static void __init rk2928_clock_common_init(unsigned long gpll_rate,unsigned long cpll_rate)
-{
-
- //general
- clk_set_rate_nolock(&general_pll_clk, gpll_rate);
- //code pll
- clk_set_rate_nolock(&codec_pll_clk, cpll_rate);
-
- cpu_axi_init();
-
- clk_set_rate_nolock(&clk_core_pre, 600 * MHZ);
-
- //periph clk
- periph_clk_set_init();
-
- //i2s
- rk2928_clock_common_i2s_init();
-
- // spi
- clk_set_rate_nolock(&clk_spi, clk_spi.parent->rate);
-
- // uart
-#if 0
- clk_set_parent_nolock(&clk_uart_pll, &codec_pll_clk);
-#else
- clk_set_parent_nolock(&clk_uart_pll, &general_pll_clk);
-#endif
- //mac
- // FIXME
-#if 0
- if(!(gpll_rate%(50*MHZ)))
- clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
- else if(!(ddr_pll_clk.rate%(50*MHZ)))
- clk_set_parent_nolock(&clk_mac_pll_div, &ddr_pll_clk);
- else
- CRU_PRINTK_ERR("mac can't get 50mhz\n");
- //hsadc
- //auto pll sel
- //clk_set_parent_nolock(&clk_hsadc_pll_div, &general_pll_clk);
-
- //lcdc1 hdmi
- //clk_set_parent_nolock(&dclk_lcdc1_div, &general_pll_clk);
-
- //lcdc0 lcd auto sel pll
- //clk_set_parent_nolock(&dclk_lcdc0_div, &general_pll_clk);
-#endif
-
- //cif
- clk_set_parent_nolock(&clk_cif_out_div, &general_pll_clk);
-
- // FIXME yxj this plase cause display unusual
- //clk_set_parent_nolock(&aclk_vio_pre, &general_pll_clk);
-
- //axi lcdc auto sel
- //clk_set_parent_nolock(&aclk_lcdc0, &general_pll_clk);
- //clk_set_parent_nolock(&aclk_lcdc1, &general_pll_clk);
- // FIXME
-
- clk_set_rate_nolock(&aclk_vio_pre, 300*MHZ);
- //axi vepu auto sel
- clk_set_parent_nolock(&aclk_vepu, &codec_pll_clk);
- clk_set_parent_nolock(&aclk_vdpu, &codec_pll_clk);
-
- clk_set_rate_nolock(&aclk_vepu, 200*MHZ);
- clk_set_rate_nolock(&aclk_vdpu, 200*MHZ);
- //gpu auto sel
- //clk_set_parent_nolock(&clk_gpu_pre, &general_pll_clk);
- clk_set_rate_nolock(&clk_gpu_pre, 133 * MHZ);
-
- clk_set_parent_nolock(&clk_sdmmc0, &general_pll_clk);
- clk_set_parent_nolock(&clk_sdio, &general_pll_clk);
- clk_set_parent_nolock(&clk_emmc, &general_pll_clk);
- clk_set_parent_nolock(&dclk_lcdc, &general_pll_clk);
-
- clk_set_rate_nolock(&clk_sdmmc0, 24750000);
- clk_set_rate_nolock(&clk_sdio, 24750000);
-}
-void __init _rk2928_clock_data_init(unsigned long gpll,unsigned long cpll,int flags)
-{
- struct clk_lookup *clk;
- clk_register_dump_ops(&dump_ops);
- clk_register_default_ops_clk(&def_ops_clk);
-
- rk2928_clock_flags = flags;
-
- CLKDATA_DBG("%s total %d clks\n", __func__, ARRAY_SIZE(clks));
- for (clk = clks; clk < clks + ARRAY_SIZE(clks); clk++) {
- CLKDATA_DBG("%s add dev_id=%s, con_id=%s\n",
- __func__, clk->dev_id ? clk->dev_id : "NULL", clk->con_id ? clk->con_id : "NULL");
- clkdev_add(clk);
- clk_register(clk->clk);
- }
-
- CLKDATA_DBG("clk_recalculate_root_clocks_nolock\n");
- clk_recalculate_root_clocks_nolock();
-#if 0
- // print loader config
- rk_dump_clock_info();
- while(1);
-#endif
- loops_per_jiffy = CLK_LOOPS_RECALC(arm_pll_clk.rate);
-
- /*
- * Only enable those clocks we will need, let the drivers
- * enable other clocks as necessary
- */
- rk30_init_enable_clocks();
- /*
- * Disable any unused clocks left on by the bootloader
- */
- clk_disable_unused();
-
- CLKDATA_DBG("rk2928_clock_common_init, gpll=%lu, cpll=%lu\n", gpll, cpll);
- rk2928_clock_common_init(gpll, cpll);
- preset_lpj = loops_per_jiffy;
-
- CLKDATA_DBG("%s clks init finish\n", __func__);
-}
-
-int rk292x_dvfs_init(void);
-void __init rk2928_clock_data_init(unsigned long gpll,unsigned long cpll,u32 flags)
-{
- printk("%s version: 2012-8-14\n", __func__);
- _rk2928_clock_data_init(gpll,cpll,flags);
- rk292x_dvfs_init();
-}
-
+++ /dev/null
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-
-#include <asm/pgtable-hwdef.h>
-#include <asm/hardware/gic.h>
-#include <asm/mach/arch.h>
-#include <asm/hardware/cache-l2x0.h>
-
-#include <plat/sram.h>
-#include <mach/board.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <mach/fiq.h>
-#include <mach/loader.h>
-#include <mach/ddr.h>
-#include <mach/cpu.h>
-#include <mach/debug_uart.h>
-
-static void __init rk2928_cpu_axi_init(void)
-{
- writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x0088); // cpu0
- writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x0188); // cpu1r
- writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x0388); // cpu1w
- writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x4008); // peri
- writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x5008); // gpu
- writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x6008); // vpu
- writel_relaxed(0xa, RK2928_CPU_AXI_BUS_BASE + 0x7188); // lcdc
- writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x7208); // cif
- writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x7288); // rga
- writel_relaxed(0x3f, RK2928_CPU_AXI_BUS_BASE + 0x0014); // memory scheduler read latency
- dsb();
-}
-
-#define L2_LY_SP_OFF (0)
-#define L2_LY_SP_MSK (0x7)
-
-#define L2_LY_RD_OFF (4)
-#define L2_LY_RD_MSK (0x7)
-
-#define L2_LY_WR_OFF (8)
-#define L2_LY_WR_MSK (0x7)
-#define L2_LY_SET(ly,off) (((ly)-1)<<(off))
-
-static void __init rk2928_l2_cache_init(void)
-{
-#ifdef CONFIG_CACHE_L2X0
- u32 aux_ctrl, aux_ctrl_mask;
-
- writel_relaxed(L2_LY_SET(1,L2_LY_SP_OFF)
- |L2_LY_SET(1,L2_LY_RD_OFF)
- |L2_LY_SET(1,L2_LY_WR_OFF), RK2928_L2C_BASE + L2X0_TAG_LATENCY_CTRL);
- writel_relaxed(L2_LY_SET(2,L2_LY_SP_OFF)
- |L2_LY_SET(3,L2_LY_RD_OFF)
- |L2_LY_SET(1,L2_LY_WR_OFF), RK2928_L2C_BASE + L2X0_DATA_LATENCY_CTRL);
-
- /* L2X0 Prefetch Control */
- writel_relaxed(0x30000000, RK2928_L2C_BASE + L2X0_PREFETCH_CTRL);
-
- /* L2X0 Power Control */
- writel_relaxed(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, RK2928_L2C_BASE + L2X0_POWER_CTRL);
-
- aux_ctrl = (
-// (1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) | // 16-way
- (0x1 << 25) | // Round-robin cache replacement policy
- (0x1 << 0) | // Full Line of Zero Enable
- (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
-// (0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | // 32KB way-size
- (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
- (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
- (0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT) );
-
- aux_ctrl_mask = ~(
-// (1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) | // 16-way
- (0x1 << 25) | // Cache replacement policy
- (0x1 << 0) | // Full Line of Zero Enable
- (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
-// (0x7 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | // 32KB way-size
- (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
- (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
- (0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT) );
-
- l2x0_init(RK2928_L2C_BASE, aux_ctrl, aux_ctrl_mask);
-#endif
-}
-
-static int boot_mode;
-static void __init rk2928_boot_mode_init(void)
-{
- u32 boot_flag = (readl_relaxed(RK2928_GRF_BASE + GRF_OS_REG4) | (readl_relaxed(RK2928_GRF_BASE + GRF_OS_REG5) << 16)) - SYS_KERNRL_REBOOT_FLAG;
- boot_mode = readl_relaxed(RK2928_GRF_BASE + GRF_OS_REG6);
-
- if (boot_flag == BOOT_RECOVER) {
- boot_mode = BOOT_MODE_RECOVERY;
- }
- if (boot_mode || boot_flag)
- printk("Boot mode: %d flag: %d\n", boot_mode, boot_flag);
-}
-
-int board_boot_mode(void)
-{
- return boot_mode;
-}
-EXPORT_SYMBOL(board_boot_mode);
-
-void __init rk2928_init_irq(void)
-{
- gic_init(0, IRQ_LOCALTIMER, GIC_DIST_BASE, GIC_CPU_BASE);
-#ifdef CONFIG_FIQ
- rk_fiq_init();
-#endif
- rk30_gpio_init();
- soc_gpio_init();
-}
-
-static unsigned int __initdata ddr_freq = DDR_FREQ;
-static int __init ddr_freq_setup(char *str)
-{
- get_option(&str, &ddr_freq);
- return 0;
-}
-early_param("ddr_freq", ddr_freq_setup);
-
-void __init rk2928_map_io(void)
-{
- rk2928_map_common_io();
-#ifdef DEBUG_UART_BASE
-#ifdef CONFIG_RK_USB_UART
- writel_relaxed(0x04000000, RK2928_GRF_BASE + GRF_UOC1_CON4);
- if(!(readl_relaxed(RK2928_GRF_BASE + 0x014c) & (1<<10)))//detect id
- {
- writel_relaxed(0x34000000, RK2928_GRF_BASE + GRF_UOC1_CON4);
- }
- else
- {
- if(!(readl_relaxed(RK2928_GRF_BASE + 0x014c) & (1<<7)))//detect vbus
- {
- writel_relaxed(0x10001000, RK2928_GRF_BASE + GRF_UOC0_CON0);
- writel_relaxed(0x007f0055, RK2928_GRF_BASE + GRF_UOC0_CON5);
- writel_relaxed(0x34003000, RK2928_GRF_BASE + GRF_UOC1_CON4);
- }
- else
- {
- writel_relaxed(0x34000000, RK2928_GRF_BASE + GRF_UOC1_CON4);
- }
- }
-#else
- writel_relaxed(0x34000000, RK2928_GRF_BASE + GRF_UOC1_CON4);
-#endif
- writel_relaxed(0x07, DEBUG_UART_BASE + 0x88);
- writel_relaxed(0x07, DEBUG_UART_BASE + 0x88);
- writel_relaxed(0x00, DEBUG_UART_BASE + 0x04);
- writel_relaxed(0x83, DEBUG_UART_BASE + 0x0c);
- writel_relaxed(0x0d, DEBUG_UART_BASE + 0x00);
- writel_relaxed(0x00, DEBUG_UART_BASE + 0x04);
- writel_relaxed(0x03, DEBUG_UART_BASE + 0x0c);
-#endif
- rk29_setup_early_printk();
- rk2928_cpu_axi_init();
- rk29_sram_init();
- board_clock_init();
- rk2928_l2_cache_init();
- ddr_init(DDR_TYPE, ddr_freq);
-// clk_disable_unused();
- rk2928_iomux_init();
- rk2928_boot_mode_init();
-}
-
-static __init u32 rk2928_get_ddr_size(void)
-{
-#ifdef CONFIG_MACH_RK2928_FPGA
- return SZ_64M;
-#else
- u32 size;
- u32 v[1], a[1];
- u32 pgtbl = PAGE_OFFSET + TEXT_OFFSET - 0x4000;
- u32 flag = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ;
-
- a[0] = pgtbl + (((u32)RK2928_GRF_BASE >> 20) << 2);
- v[0] = readl_relaxed(a[0]);
- writel_relaxed(flag | ((RK2928_GRF_PHYS >> 20) << 20), a[0]);
-
- size = ddr_get_cap();
-
- writel_relaxed(v[0], a[0]);
-
- return size;
-#endif
-}
-
-void __init rk2928_fixup(struct machine_desc *desc, struct tag *tags,
- char **cmdline, struct meminfo *mi)
-{
- mi->nr_banks = 1;
- mi->bank[0].start = PLAT_PHYS_OFFSET;
- mi->bank[0].size = rk2928_get_ddr_size();
-}
-
+++ /dev/null
-/*
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-//#define DEBUG 1
-#define pr_fmt(fmt) "cpufreq: " fmt
-#include <linux/clk.h>
-#include <linux/cpufreq.h>
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/reboot.h>
-#include <linux/suspend.h>
-#include <linux/tick.h>
-#include <linux/workqueue.h>
-#include <asm/smp_plat.h>
-#include <asm/cpu.h>
-#include <mach/dvfs.h>
-#include <linux/delay.h>
-#include <linux/regulator/consumer.h>
-#include <linux/fs.h>
-#include <linux/string.h>
-#include <linux/earlysuspend.h>
-#include <asm/unistd.h>
-#include <asm/uaccess.h>
-#include <mach/ddr.h>
-#ifdef DEBUG
-#define FREQ_PRINTK_DBG(fmt, args...) pr_debug(fmt, ## args)
-#define FREQ_PRINTK_LOG(fmt, args...) pr_debug(fmt, ## args)
-#else
-#define FREQ_PRINTK_DBG(fmt, args...) do {} while(0)
-#define FREQ_PRINTK_LOG(fmt, args...) do {} while(0)
-#endif
-#define FREQ_PRINTK_ERR(fmt, args...) pr_err(fmt, ## args)
-
-/* Frequency table index must be sequential starting at 0 */
-static struct cpufreq_frequency_table default_freq_table[] = {
- {.frequency = 816 * 1000, .index = 1100 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table *freq_table = default_freq_table;
-static unsigned int max_freq = -1;
-
-/*********************************************************/
-
-/* additional symantics for "relation" in cpufreq with pm */
-#define DISABLE_FURTHER_CPUFREQ 0x10
-#define ENABLE_FURTHER_CPUFREQ 0x20
-#define MASK_FURTHER_CPUFREQ 0x30
-/* With 0x00(NOCHANGE), it depends on the previous "further" status */
-static int no_cpufreq_access;
-static unsigned int suspend_freq = 600 * 1000;
-static unsigned int reboot_freq = 816 * 1000;
-
-static struct workqueue_struct *freq_wq;
-static struct clk *cpu_clk;
-static struct clk *cpu_pll;
-static struct clk *cpu_gpll;
-
-
-static DEFINE_MUTEX(cpufreq_mutex);
-
-static struct clk *gpu_clk;
-#define GPU_MAX_RATE 350*1000*1000
-
-static int cpufreq_scale_rate_for_dvfs(struct clk *clk, unsigned long rate, dvfs_set_rate_callback set_rate);
-
-/*******************************************************/
-static unsigned int rk30_getspeed(unsigned int cpu)
-{
- unsigned long rate;
-
- if (cpu >= NR_CPUS)
- return 0;
-
- rate = clk_get_rate(cpu_clk) / 1000;
- return rate;
-}
-
-static bool rk30_cpufreq_is_ondemand_policy(struct cpufreq_policy *policy)
-{
- char c = 0;
- if (policy && policy->governor)
- c = policy->governor->name[0];
- return (c == 'o' || c == 'i' || c == 'c' || c == 'h');
-}
-
-/**********************thermal limit**************************/
-#define CONFIG_RK30_CPU_FREQ_LIMIT_BY_TEMP
-
-#ifdef CONFIG_RK30_CPU_FREQ_LIMIT_BY_TEMP
-static void rk30_cpufreq_temp_limit_work_func(struct work_struct *work);
-
-static DECLARE_DELAYED_WORK(rk30_cpufreq_temp_limit_work, rk30_cpufreq_temp_limit_work_func);
-
-static unsigned int temp_limt_freq = -1;
-module_param(temp_limt_freq, uint, 0444);
-
-#define TEMP_LIMIT_FREQ 816000
-
-static const struct cpufreq_frequency_table temp_limits[] = {
- {.frequency = 1416 * 1000, .index = 50},
- {.frequency = 1200 * 1000, .index = 55},
- {.frequency = 1008 * 1000, .index = 60},
- {.frequency = 816 * 1000, .index = 75},
-};
-
-//extern int rk30_tsadc_get_temp(unsigned int chn);
-
-//#define get_cpu_thermal() rk30_tsadc_get_temp(0)
-static void rk30_cpufreq_temp_limit_work_func(struct work_struct *work)
-{
- struct cpufreq_policy *policy;
- int temp = 25, i;
- unsigned int new = -1;
-
- if (clk_get_rate(gpu_clk) > GPU_MAX_RATE)
- goto out;
-
- //temp = max(rk30_tsadc_get_temp(0), rk30_tsadc_get_temp(1));
- FREQ_PRINTK_LOG("cpu_thermal(%d)\n", temp);
-
- for (i = 0; i < ARRAY_SIZE(temp_limits); i++) {
- if (temp > temp_limits[i].index) {
- new = temp_limits[i].frequency;
- }
- }
- if (temp_limt_freq != new) {
- temp_limt_freq = new;
- if (new != -1) {
- FREQ_PRINTK_DBG("temp_limit set rate %d kHz\n", temp_limt_freq);
- policy = cpufreq_cpu_get(0);
- cpufreq_driver_target(policy, policy->cur, CPUFREQ_RELATION_L);
- cpufreq_cpu_put(policy);
- }
- }
-
-out:
- queue_delayed_work(freq_wq, &rk30_cpufreq_temp_limit_work, HZ);
-}
-
-static int rk30_cpufreq_notifier_policy(struct notifier_block *nb,
- unsigned long val, void *data)
-{
- struct cpufreq_policy *policy = data;
-
- if (val != CPUFREQ_NOTIFY)
- return 0;
-
- if (rk30_cpufreq_is_ondemand_policy(policy)) {
- FREQ_PRINTK_DBG("queue work\n");
- queue_delayed_work(freq_wq, &rk30_cpufreq_temp_limit_work, 0);
- } else {
- FREQ_PRINTK_DBG("cancel work\n");
- cancel_delayed_work_sync(&rk30_cpufreq_temp_limit_work);
- }
-
- return 0;
-}
-
-static struct notifier_block notifier_policy_block = {
- .notifier_call = rk30_cpufreq_notifier_policy
-};
-#endif
-
-/************************************dvfs tst************************************/
-//#define CPU_FREQ_DVFS_TST
-#ifdef CPU_FREQ_DVFS_TST
-static unsigned int freq_dvfs_tst_rate;
-static void rk30_cpufreq_dvsf_tst_work_func(struct work_struct *work);
-static DECLARE_DELAYED_WORK(rk30_cpufreq_dvsf_tst_work, rk30_cpufreq_dvsf_tst_work_func);
-static int test_count;
-#define TEST_FRE_NUM 11
-static int test_tlb_rate[TEST_FRE_NUM] = { 504, 1008, 504, 1200, 252, 816, 1416, 252, 1512, 252, 816 };
-//static int test_tlb_rate[TEST_FRE_NUM]={504,1008,504,1200,252,816,1416,126,1512,126,816};
-
-#define TEST_GPU_NUM 3
-
-static int test_tlb_gpu[TEST_GPU_NUM] = { 360, 400, 180 };
-static int test_tlb_ddr[TEST_GPU_NUM] = { 401, 200, 500 };
-
-static int gpu_ddr = 0;
-
-static void rk30_cpufreq_dvsf_tst_work_func(struct work_struct *work)
-{
- struct cpufreq_policy *policy = cpufreq_cpu_get(0);
-
- gpu_ddr++;
-
-#if 0
- FREQ_PRINTK_LOG("cpufreq_dvsf_tst,ddr%u,gpu%u\n",
- test_tlb_ddr[gpu_ddr % TEST_GPU_NUM],
- test_tlb_gpu[gpu_ddr % TEST_GPU_NUM]);
- clk_set_rate(ddr_clk, test_tlb_ddr[gpu_ddr % TEST_GPU_NUM] * 1000 * 1000);
- clk_set_rate(gpu_clk, test_tlb_gpu[gpu_ddr % TEST_GPU_NUM] * 1000 * 1000);
-#endif
-
- test_count++;
- freq_dvfs_tst_rate = test_tlb_rate[test_count % TEST_FRE_NUM] * 1000;
- FREQ_PRINTK_LOG("cpufreq_dvsf_tst,cpu set rate %d\n", freq_dvfs_tst_rate);
- cpufreq_driver_target(policy, policy->cur, CPUFREQ_RELATION_L);
- cpufreq_cpu_put(policy);
-
- queue_delayed_work(freq_wq, &rk30_cpufreq_dvsf_tst_work, msecs_to_jiffies(1000));
-}
-#endif /* CPU_FREQ_DVFS_TST */
-
-/***********************************************************************/
-static int rk30_verify_speed(struct cpufreq_policy *policy)
-{
- if (!freq_table)
- return -EINVAL;
- return cpufreq_frequency_table_verify(policy, freq_table);
-}
-
-static int rk30_cpu_init(struct cpufreq_policy *policy)
-{
- if (policy->cpu == 0) {
- int i;
- struct clk *ddr_clk;
- struct clk *aclk_vepu_clk;
-
- gpu_clk = clk_get(NULL, "gpu");
- if (!IS_ERR(gpu_clk))
- clk_enable_dvfs(gpu_clk);
-#if 0
-
- ddr_clk = clk_get(NULL, "ddr");
- if (!IS_ERR(ddr_clk))
- {
- clk_enable_dvfs(ddr_clk);
- clk_set_rate(ddr_clk,clk_get_rate(ddr_clk)-1);
- }
-
-#endif
- cpu_clk = clk_get(NULL, "cpu");
- cpu_pll = clk_get(NULL, "arm_pll");
-
- cpu_gpll = clk_get(NULL, "arm_gpll");
- if (IS_ERR(cpu_clk))
- return PTR_ERR(cpu_clk);
-
- dvfs_clk_register_set_rate_callback(cpu_clk, cpufreq_scale_rate_for_dvfs);
- freq_table = dvfs_get_freq_volt_table(cpu_clk);
- if (freq_table == NULL) {
- freq_table = default_freq_table;
- }
- max_freq = freq_table[0].frequency;
- for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
- max_freq = max(max_freq, freq_table[i].frequency);
- }
- clk_enable_dvfs(cpu_clk);
-
- /* Limit gpu frequency between 133M to 400M */
- dvfs_clk_enable_limit(gpu_clk, 133000000, 400000000);
-
- ddr_clk = clk_get(NULL, "ddr");
- if (!IS_ERR(ddr_clk))
- clk_enable_dvfs(ddr_clk);
-
- aclk_vepu_clk = clk_get(NULL, "aclk_vepu");
- if (!IS_ERR(aclk_vepu_clk))
- clk_enable_dvfs(aclk_vepu_clk);
-
- freq_wq = create_singlethread_workqueue("rk30_cpufreqd");
-#ifdef CONFIG_RK30_CPU_FREQ_LIMIT_BY_TEMP
- if (rk30_cpufreq_is_ondemand_policy(policy)) {
- queue_delayed_work(freq_wq, &rk30_cpufreq_temp_limit_work, 0*HZ);
- }
- cpufreq_register_notifier(¬ifier_policy_block, CPUFREQ_POLICY_NOTIFIER);
-#endif
-#ifdef CPU_FREQ_DVFS_TST
- queue_delayed_work(freq_wq, &rk30_cpufreq_dvsf_tst_work, msecs_to_jiffies(20 * 1000));
-#endif
- }
- //set freq min max
- cpufreq_frequency_table_cpuinfo(policy, freq_table);
- //sys nod
- cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
-
- policy->cur = rk30_getspeed(0);
-
- policy->cpuinfo.transition_latency = 40 * NSEC_PER_USEC; // make ondemand default sampling_rate to 40000
-
- /*
- * On rk30 SMP configuartion, both processors share the voltage
- * and clock. So both CPUs needs to be scaled together and hence
- * needs software co-ordination. Use cpufreq affected_cpus
- * interface to handle this scenario. Additional is_smp() check
- * is to keep SMP_ON_UP build working.
- */
- if (is_smp())
- cpumask_setall(policy->cpus);
-
- return 0;
-}
-
-static int rk30_cpu_exit(struct cpufreq_policy *policy)
-{
- if (policy->cpu != 0)
- return 0;
-
- cpufreq_frequency_table_cpuinfo(policy, freq_table);
- clk_put(cpu_clk);
-#ifdef CONFIG_RK30_CPU_FREQ_LIMIT_BY_TEMP
- cpufreq_unregister_notifier(¬ifier_policy_block, CPUFREQ_POLICY_NOTIFIER);
- if (freq_wq)
- cancel_delayed_work(&rk30_cpufreq_temp_limit_work);
-#endif
- if (freq_wq) {
- flush_workqueue(freq_wq);
- destroy_workqueue(freq_wq);
- freq_wq = NULL;
- }
-
- return 0;
-}
-
-static struct freq_attr *rk30_cpufreq_attr[] = {
- &cpufreq_freq_attr_scaling_available_freqs,
- NULL,
-};
-
-/**************************earlysuspend freeze cpu frequency******************************/
-static struct early_suspend ff_early_suspend;
-
-#define FILE_GOV_MODE "/sys/devices/system/cpu/cpu0/cpufreq/scaling_governor"
-#define FILE_SETSPEED "/sys/devices/system/cpu/cpu0/cpufreq/scaling_setspeed"
-#define FILE_CUR_FREQ "/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq"
-
-#define FF_DEBUG(fmt, args...) printk(KERN_DEBUG "FREEZE FREQ DEBUG:\t"fmt, ##args)
-#define FF_ERROR(fmt, args...) printk(KERN_ERR "FREEZE FREQ ERROR:\t"fmt, ##args)
-
-static int ff_read(char *file_path, char *buf)
-{
- struct file *file = NULL;
- mm_segment_t old_fs;
- loff_t offset = 0;
-
- FF_DEBUG("read %s\n", file_path);
- file = filp_open(file_path, O_RDONLY, 0);
-
- if (IS_ERR(file)) {
- FF_ERROR("%s error open file %s\n", __func__, file_path);
- return -1;
- }
-
- old_fs = get_fs();
- set_fs(KERNEL_DS);
-
- file->f_op->read(file, (char *)buf, 32, &offset);
- sscanf(buf, "%s", buf);
-
- set_fs(old_fs);
- filp_close(file, NULL);
-
- file = NULL;
-
- return 0;
-
-}
-
-static int ff_write(char *file_path, char *buf)
-{
- struct file *file = NULL;
- mm_segment_t old_fs;
- loff_t offset = 0;
-
- FF_DEBUG("write %s %s size = %d\n", file_path, buf, strlen(buf));
- file = filp_open(file_path, O_RDWR, 0);
-
- if (IS_ERR(file)) {
- FF_ERROR("%s error open file %s\n", __func__, file_path);
- return -1;
- }
-
- old_fs = get_fs();
- set_fs(KERNEL_DS);
-
- file->f_op->write(file, (char *)buf, strlen(buf), &offset);
-
- set_fs(old_fs);
- filp_close(file, NULL);
-
- file = NULL;
-
- return 0;
-
-}
-
-static void ff_scale_votlage(char *name, int volt)
-{
- struct regulator* regulator;
- int ret = 0;
-
- FF_DEBUG("enter %s\n", __func__);
- regulator = dvfs_get_regulator(name);
- if (!regulator) {
- FF_ERROR("get regulator %s ERROR\n", name);
- return ;
- }
-
- ret = regulator_set_voltage(regulator, volt, volt);
- if (ret != 0) {
- FF_ERROR("set voltage error %s %d, ret = %d\n", name, volt, ret);
- }
-
-}
-int clk_set_parent_force(struct clk *clk, struct clk *parent);
-static void ff_early_suspend_func(struct early_suspend *h)
-{
- char buf[32];
- FF_DEBUG("enter %s\n", __func__);
- if (ff_read(FILE_GOV_MODE, buf) != 0) {
- FF_ERROR("read current governor error\n");
- return ;
- } else {
- FF_DEBUG("current governor = %s\n", buf);
- }
-
- strcpy(buf, "userspace");
- if (ff_write(FILE_GOV_MODE, buf) != 0) {
- FF_ERROR("set current governor error\n");
- return ;
- }
-
- strcpy(buf, "252000");
- if (ff_write(FILE_SETSPEED, buf) != 0) {
- FF_ERROR("set speed to 252MHz error\n");
- return ;
- }
-
- if (!IS_ERR(cpu_pll)&&!IS_ERR(cpu_gpll)&&!IS_ERR(cpu_clk))
- {
- clk_set_parent_force(cpu_clk,cpu_gpll);
- clk_set_rate(cpu_clk,300*1000*1000);
-
- clk_disable_dvfs(cpu_clk);
- }
- if (!IS_ERR(gpu_clk))
- dvfs_clk_enable_limit(gpu_clk,75*1000*1000,133*1000*1000);
-
- //ff_scale_votlage("vdd_cpu", 1000000);
- //ff_scale_votlage("vdd_core", 1000000);
-#ifdef CONFIG_HOTPLUG_CPU
- cpu_down(1);
-#endif
-}
-
-static void ff_early_resume_func(struct early_suspend *h)
-{
- char buf[32];
- FF_DEBUG("enter %s\n", __func__);
-
- if (!IS_ERR(cpu_pll)&&!IS_ERR(cpu_gpll)&&!IS_ERR(cpu_clk))
- {
- clk_set_parent_force(cpu_clk,cpu_pll);
- clk_set_rate(cpu_clk,300*1000*1000);
- clk_enable_dvfs(cpu_clk);
- }
-
- if (!IS_ERR(gpu_clk))
- dvfs_clk_disable_limit(gpu_clk);
-#ifdef CONFIG_HOTPLUG_CPU
- cpu_up(1);
-#endif
- if (ff_read(FILE_GOV_MODE, buf) != 0) {
- FF_ERROR("read current governor error\n");
- return ;
- } else {
- FF_DEBUG("current governor = %s\n", buf);
- }
-
- if (ff_read(FILE_CUR_FREQ, buf) != 0) {
- FF_ERROR("read current frequency error\n");
- return ;
- } else {
- FF_DEBUG("current frequency = %s\n", buf);
- }
-
- strcpy(buf, "interactive");
- if (ff_write(FILE_GOV_MODE, buf) != 0) {
- FF_ERROR("set current governor error\n");
- return ;
- }
-
- strcpy(buf, "interactive");
- if (ff_write(FILE_GOV_MODE, buf) != 0) {
- FF_ERROR("set current governor error\n");
- return ;
- }
-}
-
-static int __init ff_init(void)
-{
- FF_DEBUG("enter %s\n", __func__);
- ff_early_suspend.suspend = ff_early_suspend_func;
- ff_early_suspend.resume = ff_early_resume_func;
- ff_early_suspend.level = EARLY_SUSPEND_LEVEL_DISABLE_FB + 100;
- register_early_suspend(&ff_early_suspend);
- return 0;
-}
-
-static void __exit ff_exit(void)
-{
- FF_DEBUG("enter %s\n", __func__);
- unregister_early_suspend(&ff_early_suspend);
-}
-
-
-/**************************target freq******************************/
-static unsigned int cpufreq_scale_limt(unsigned int target_freq, struct cpufreq_policy *policy)
-{
- bool is_ondemand = rk30_cpufreq_is_ondemand_policy(policy);
- static bool is_booting = true;
-
- if (is_ondemand && clk_get_rate(gpu_clk) > GPU_MAX_RATE) // high performance?
- return max_freq;
- if (is_ondemand && is_booting && target_freq >= 1600 * 1000) {
- s64 boottime_ms = ktime_to_ms(ktime_get_boottime());
- if (boottime_ms > 30 * MSEC_PER_SEC) {
- is_booting = false;
- } else {
- target_freq = 1416 * 1000;
- }
- }
-#ifdef CONFIG_RK30_CPU_FREQ_LIMIT_BY_TEMP
- if (is_ondemand && target_freq > policy->cur && policy->cur >= TEMP_LIMIT_FREQ) {
- unsigned int i;
- if (cpufreq_frequency_table_target(policy, freq_table, policy->cur + 1, CPUFREQ_RELATION_L, &i) == 0) {
- unsigned int f = freq_table[i].frequency;
- if (f < target_freq) {
- target_freq = f;
- }
- }
- }
- /*
- * If the new frequency is more than the thermal max allowed
- * frequency, go ahead and scale the mpu device to proper frequency.
- */
- if (is_ondemand) {
- target_freq = min(target_freq, temp_limt_freq);
- }
-#endif
-#ifdef CPU_FREQ_DVFS_TST
- if (freq_dvfs_tst_rate) {
- target_freq = freq_dvfs_tst_rate;
- freq_dvfs_tst_rate = 0;
- }
-#endif
- return target_freq;
-}
-
-int cpufreq_scale_rate_for_dvfs(struct clk *clk, unsigned long rate, dvfs_set_rate_callback set_rate)
-{
- unsigned int i;
- int ret = -EINVAL;
- struct cpufreq_freqs freqs;
-
- freqs.new = rate / 1000;
- freqs.old = rk30_getspeed(0);
-
- for_each_online_cpu(freqs.cpu) {
- cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
- }
- FREQ_PRINTK_DBG("cpufreq_scale_rate_for_dvfs(%lu)\n", rate);
- ret = set_rate(clk, rate);
-
-#ifdef CONFIG_SMP
- /*
- * Note that loops_per_jiffy is not updated on SMP systems in
- * cpufreq driver. So, update the per-CPU loops_per_jiffy value
- * on frequency transition. We need to update all dependent CPUs.
- */
- for_each_possible_cpu(i) {
- per_cpu(cpu_data, i).loops_per_jiffy = loops_per_jiffy;
- }
-#endif
-
- freqs.new = rk30_getspeed(0);
- /* notifiers */
- for_each_online_cpu(freqs.cpu) {
- cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
- }
- return ret;
-
-}
-
-static int rk30_target(struct cpufreq_policy *policy, unsigned int target_freq, unsigned int relation)
-{
- unsigned int i, new_rate = 0;
- int ret = 0;
-
- if (!freq_table) {
- FREQ_PRINTK_ERR("no freq table!\n");
- return -EINVAL;
- }
-
- mutex_lock(&cpufreq_mutex);
-
- if (relation & ENABLE_FURTHER_CPUFREQ)
- no_cpufreq_access--;
- if (no_cpufreq_access) {
-#ifdef CONFIG_PM_VERBOSE
- pr_err("denied access to %s as it is disabled temporarily\n", __func__);
-#endif
- ret = -EINVAL;
- goto out;
- }
- if (relation & DISABLE_FURTHER_CPUFREQ)
- no_cpufreq_access++;
- relation &= ~MASK_FURTHER_CPUFREQ;
-
- ret = cpufreq_frequency_table_target(policy, freq_table, target_freq, relation, &i);
- if (ret) {
- FREQ_PRINTK_ERR("no freq match for %d(ret=%d)\n", target_freq, ret);
- goto out;
- }
- new_rate = freq_table[i].frequency;
- if (!no_cpufreq_access)
- new_rate = cpufreq_scale_limt(new_rate, policy);
-
- FREQ_PRINTK_LOG("cpufreq req=%u,new=%u(was=%u)\n", target_freq, new_rate, rk30_getspeed(0));
- if (new_rate == rk30_getspeed(0))
- goto out;
- ret = clk_set_rate(cpu_clk, new_rate * 1000);
-out:
- mutex_unlock(&cpufreq_mutex);
- FREQ_PRINTK_DBG("cpureq set rate (%u) end\n", new_rate);
- return ret;
-}
-
-static int rk30_cpufreq_pm_notifier_event(struct notifier_block *this,
- unsigned long event, void *ptr)
-{
- int ret = NOTIFY_DONE;
- struct cpufreq_policy *policy = cpufreq_cpu_get(0);
-
- if (!policy)
- return ret;
-
- if (!rk30_cpufreq_is_ondemand_policy(policy))
- goto out;
-
- switch (event) {
- case PM_SUSPEND_PREPARE:
- ret = cpufreq_driver_target(policy, suspend_freq, DISABLE_FURTHER_CPUFREQ | CPUFREQ_RELATION_H);
- if (ret < 0) {
- ret = NOTIFY_BAD;
- goto out;
- }
- ret = NOTIFY_OK;
- break;
- case PM_POST_RESTORE:
- case PM_POST_SUSPEND:
- cpufreq_driver_target(policy, suspend_freq, ENABLE_FURTHER_CPUFREQ | CPUFREQ_RELATION_H);
- ret = NOTIFY_OK;
- break;
- }
-out:
- cpufreq_cpu_put(policy);
- return ret;
-}
-
-static struct notifier_block rk30_cpufreq_pm_notifier = {
- .notifier_call = rk30_cpufreq_pm_notifier_event,
-};
-
-static int rk30_cpufreq_reboot_notifier_event(struct notifier_block *this,
- unsigned long event, void *ptr)
-{
- struct cpufreq_policy *policy = cpufreq_cpu_get(0);
-
- if (policy) {
- cpufreq_driver_target(policy, reboot_freq, DISABLE_FURTHER_CPUFREQ | CPUFREQ_RELATION_L);
- cpufreq_cpu_put(policy);
- }
-
- return NOTIFY_OK;
-}
-
-static struct notifier_block rk30_cpufreq_reboot_notifier = {
- .notifier_call = rk30_cpufreq_reboot_notifier_event,
-};
-
-static struct cpufreq_driver rk30_cpufreq_driver = {
- .flags = CPUFREQ_CONST_LOOPS,
- .verify = rk30_verify_speed,
- .target = rk30_target,
- .get = rk30_getspeed,
- .init = rk30_cpu_init,
- .exit = rk30_cpu_exit,
- .name = "rk30",
- .attr = rk30_cpufreq_attr,
-};
-
-static int __init rk30_cpufreq_init(void)
-{
- register_pm_notifier(&rk30_cpufreq_pm_notifier);
- register_reboot_notifier(&rk30_cpufreq_reboot_notifier);
- return cpufreq_register_driver(&rk30_cpufreq_driver);
-}
-
-static void __exit rk30_cpufreq_exit(void)
-{
- cpufreq_unregister_driver(&rk30_cpufreq_driver);
-}
-
-MODULE_DESCRIPTION("cpufreq driver for rock chip rk30");
-MODULE_LICENSE("GPL");
-device_initcall(rk30_cpufreq_init);
-module_exit(rk30_cpufreq_exit);
+++ /dev/null
-/*
- * arch/arm/mach-rk2928/ddr.c-- for ddr3&ddr2
- *
- * Function Driver for DDR controller
- *
- * Copyright (C) 2012 Fuzhou Rockchip Electronics Co.,Ltd
- * Author:
- * hcy@rock-chips.com
- * yk@rock-chips.com
- * typ@rock-chips.com
- *
- * v1.00
- */
-
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/clk.h>
-
-#include <asm/cacheflush.h>
-#include <asm/tlbflush.h>
-
-#include <mach/sram.h>
-#include <mach/ddr.h>
-
-#include <linux/rk_fb.h>
-
-typedef uint32_t uint32 ;
-
-
-#define DDR3_DDR2_DLL_DISABLE_FREQ (300) // ¿ÅÁ£dll disableµÄƵÂÊ
-#define DDR3_DDR2_ODT_DISABLE_FREQ (333) //¿ÅÁ£odt disableµÄƵÂÊ
-#define SR_IDLE (0x1) //unit:32*DDR clk cycle, and 0 for disable auto self-refresh
-#define PD_IDLE (0x40) //unit:DDR clk cycle, and 0 for disable auto power-down
-#define PHY_ODT_DISABLE_FREQ (333) //¶¨ÒåÖ÷¿Ø¶Ëodt disableµÄƵÂÊ
-#define PHY_DLL_DISABLE_FREQ (266) //¶¨ÒåÖ÷¿Ø¶Ëdll bypassµÄƵÂÊ
-
-//#define PMU_BASE_ADDR RK30_PMU_BASE //??RK 2928 PMUÔÚÄÄÀï
-#define SDRAMC_BASE_ADDR RK2928_DDR_PCTL_BASE
-#define DDR_PHY_BASE RK2928_DDR_PHY_BASE
-#define CRU_BASE_ADDR RK2928_CRU_BASE
-#define REG_FILE_BASE_ADDR RK2928_GRF_BASE
-#define SysSrv_DdrConf (RK2928_CPU_AXI_BUS_BASE+0x08)
-#define SysSrv_DdrTiming (RK2928_CPU_AXI_BUS_BASE+0x0c)
-#define SysSrv_DdrMode (RK2928_CPU_AXI_BUS_BASE+0x10)
-#define SysSrv_ReadLatency (RK2928_CPU_AXI_BUS_BASE+0x14)
-
-#define ddr_print(x...) printk( "DDR DEBUG: " x )
-
-
-/***********************************
- * DDR3 define
- ***********************************/
-//mr0 for ddr3
-#define DDR3_BL8 (0)
-#define DDR3_BC4_8 (1)
-#define DDR3_BC4 (2)
-#define DDR3_CL(n) (((((n)-4)&0x7)<<4)|((((n)-4)&0x8)>>1))
-#define DDR3_WR(n) (((n)&0x7)<<9)
-#define DDR3_DLL_RESET (1<<8)
-#define DDR3_DLL_DeRESET (0<<8)
-
-//mr1 for ddr3
-#define DDR3_DLL_ENABLE (0)
-#define DDR3_DLL_DISABLE (1)
-#define DDR3_MR1_AL(n) (((n)&0x7)<<3)
-
-#define DDR3_DS_40 (0)
-#define DDR3_DS_34 (1<<1)
-#define DDR3_Rtt_Nom_DIS (0)
-#define DDR3_Rtt_Nom_60 (1<<2)
-#define DDR3_Rtt_Nom_120 (1<<6)
-#define DDR3_Rtt_Nom_40 ((1<<2)|(1<<6))
-
-//mr2 for ddr3
-#define DDR3_MR2_CWL(n) ((((n)-5)&0x7)<<3)
-#define DDR3_Rtt_WR_DIS (0)
-#define DDR3_Rtt_WR_60 (1<<9)
-#define DDR3_Rtt_WR_120 (2<<9)
-
-/***********************************
- * DDR2 define
- ***********************************/
-//MR; //Mode Register
-#define DDR2_BL4 (2)
-#define DDR2_BL8 (3)
-#define DDR2_CL(n) (((n)&0x7)<<4)
-#define DDR2_WR(n) ((((n)-1)&0x7)<<9)
-#define DDR2_DLL_RESET (1<<8)
-#define DDR2_DLL_DeRESET (0<<8)
-
-//EMR; //Extended Mode Register
-#define DDR2_DLL_ENABLE (0)
-#define DDR2_DLL_DISABLE (1)
-
-#define DDR2_STR_FULL (0)
-#define DDR2_STR_REDUCE (1<<1)
-#define DDR2_AL(n) (((n)&0x7)<<3)
-#define DDR2_Rtt_Nom_DIS (0)
-#define DDR2_Rtt_Nom_150 (0x40)
-#define DDR2_Rtt_Nom_75 (0x4)
-#define DDR2_Rtt_Nom_50 (0x44)
-
-
-#define DDR_PLL_REFDIV (1)
-#define FBDIV(n) ((0xFFF<<16) | (n&0xfff))
-#define REFDIV(n) ((0x3F<<16) | (n&0x3f))
-#define POSTDIV1(n) ((0x7<<(12+16)) | ((n&0x7)<<12))
-#define POSTDIV2(n) ((0x7<<(6+16)) | ((n&0x7)<<6))
-
-#define PLL_LOCK_STATUS (0x1<<10)
- //CRU Registers
-typedef volatile struct tagCRU_STRUCT
-{
- uint32 CRU_PLL_CON[4][4]; //cru_pll_con[][4] reserved
- uint32 CRU_MODE_CON;
- uint32 CRU_CLKSEL_CON[35];
- uint32 CRU_CLKGATE_CON[10];
- uint32 reserved2[(0x100-0xf8)/4];
- uint32 CRU_GLB_SRST_FST_VALUE;
- uint32 CRU_GLB_SRST_SND_VALUE;
- uint32 reserved3[(0x110-0x108)/4];
- uint32 CRU_SOFTRST_CON[9];
- uint32 CRU_MISC_CON;
- uint32 reserved4[(0x140-0x138)/4];
- uint32 CRU_GLB_CNT_TH;
-} CRU_REG, *pCRU_REG;
-
-#define pCRU_Reg ((pCRU_REG)CRU_BASE_ADDR)
-
-typedef struct tagGPIO_LH
-{
- uint32 GPIOL;
- uint32 GPIOH;
-}GPIO_LH_T;
-
-typedef struct tagGPIO_IOMUX
-{
- uint32 GPIOA_IOMUX;
- uint32 GPIOB_IOMUX;
- uint32 GPIOC_IOMUX;
- uint32 GPIOD_IOMUX;
-}GPIO_IOMUX_T;
-
-//GRF_OS_REG1 ddr message
-#define DDR_RANK_COUNT (11)
-#define DDR_COL_COUNT (9)
-#define DDR_BANK_COUNT (8)
-#define DDR_ROW_COUNT (6)
-/********************************
-GRF ¼Ä´æÆ÷ÖÐGRF_OS_REG1 ´æddr rank£¬typeµÈÐÅÏ¢
-GRF_SOC_CON2¼Ä´æÆ÷ÖпØÖÆc_sysreqÐźÅÏòpctl·¢ËͽøÈëlow power ÇëÇó
-GRF_DDRC_STAT ¿É²éѯpctlÊÇ·ñ½ÓÊÜÇëÇó ½øÈëlow power
-********************************/
-//REG FILE registers
-#if defined (CONFIG_ARCH_RK3026)
-//GRF_SOC_STATUS0
-#define sys_pwr_idle (1<<27)
-#define gpu_pwr_idle (1<<26)
-#define vpu_pwr_idle (1<<25)
-#define vio_pwr_idle (1<<24)
-#define peri_pwr_idle (1<<23)
-#define core_pwr_idle (1<<22)
-//GRF_SOC_CON2
-#define core_pwr_idlereq (13)
-#define peri_pwr_idlereq (12)
-#define vio_pwr_idlereq (11)
-#define vpu_pwr_idlereq (10)
-#define gpu_pwr_idlereq (9)
-#define sys_pwr_idlereq (8)
-
-typedef volatile struct tagREG_FILE
-{
- uint32 reserved0[(0xa8-0x0)/4];
- GPIO_IOMUX_T GRF_GPIO_IOMUX[4]; // 0x00a8
- uint32 reserved1[(0x100-0xe8)/4];
- uint32 GRF_GPIO_DS; //0x110
- uint32 reserved2[(0x118-0x104)/4];
- GPIO_LH_T GRF_GPIO_PULL[4]; // 0x118
- uint32 reserved3[(0x140-0x138)/4];
- uint32 GRF_SOC_CON[3]; // 0x140
- uint32 GRF_SOC_STATUS0;
- uint32 GRF_LVDS_CON0;
- uint32 reserved4[(0x15c-0x154)/4];
- uint32 GRF_DMAC1_CON[3]; //0x15c
- uint32 reserved5[(0x17c-0x168)/4];
- uint32 GRF_UOC0_CON0; //0x17c
- uint32 reserved6[(0x190-0x180)/4];
- uint32 GRF_UOC1_CON0; //0x190
- uint32 GRF_UOC1_COM1;
- uint32 reserved7;
- uint32 GRF_DDRC_STAT;
- uint32 GRF_UOC_CON;
- uint32 reserved8;
- uint32 GRF_CPU_CON[6];
- uint32 GRF_CPU_STATUS[2];
- uint32 GRF_OS_REG[8];
- uint32 reserved9[(0x200-0x1e8)/4];
- uint32 GRF_DLL_CON[4]; //0X200
- uint32 GRF_DLL_STATUS;
- uint32 reserved10[(0x220-0x214)/4];
- uint32 GRF_DFI_WRNUM; //0X220
- uint32 GRF_DFI_RDNUM;
- uint32 GRF_DFI_ACTNUM;
- uint32 GRF_DFI_TIMERVAL;
- uint32 GRF_NIF_FIFO[4];
- uint32 reserved11[(0x280-0x240)/4];
- uint32 GRF_USBPHY0_CON[8];
- uint32 GRF_USBPHY1_CON[8];
- uint32 reserved12[(0x300-0x2c0)/4];
- uint32 GRF_CHIP_TAG;
-} REG_FILE, *pREG_FILE;
-
-#else
-typedef volatile struct tagREG_FILE
-{
- uint32 reserved1[(0xa8-0x0)/4]; //42
- uint32 GRF_GPIO_IOMUX[16]; //ÆäÖÐ 12£¬13reserved
- uint32 reserved2[(0x118-0xe8)/4]; //12
- GPIO_LH_T GRF_GPIO_PULL[4];
- uint32 reserved3[(0x140-0x138)/4]; // 2
- uint32 GRF_SOC_CON[3];
- uint32 GRF_SOC_STATUS0;
- uint32 GRF_LCDS_CON0;
- uint32 reserved4[(0x15c-0x154)/4]; // 2
- uint32 GRF_DMAC1_CON[3];
- uint32 reserved5[(0x16c-0x168)/4]; // 1
- uint32 GRF_UOC0_CON[5];
- uint32 GRF_UOC1_CON[6];
- uint32 reserved6[(0x19c-0x198)/4]; // 1
- uint32 GRF_DDRC_STAT;
- uint32 reserved7[(0x1c8-0x1a0)/4]; //10
- uint32 GRF_OS_REG[4];
-} REG_FILE, *pREG_FILE;
-#endif
-
-#define pGRF_Reg ((pREG_FILE)REG_FILE_BASE_ADDR)
-
-//SCTL
-#define INIT_STATE (0)
-#define CFG_STATE (1)
-#define GO_STATE (2)
-#define SLEEP_STATE (3)
-#define WAKEUP_STATE (4)
-
-//STAT
-#define Init_mem (0)
-#define Config (1)
-#define Config_req (2)
-#define Access (3)
-#define Access_req (4)
-#define Low_power (5)
-#define Low_power_entry_req (6)
-#define Low_power_exit_req (7)
-
-//MCFG
-#define mddr_lpddr2_clk_stop_idle(n) ((n)<<24)
-#define pd_idle(n) ((n)<<8)
-#define mddr_en (2<<22)
-#define lpddr2_en (3<<22)
-#define ddr2_en (0<<5)
-#define ddr3_en (1<<5)
-#define lpddr2_s2 (0<<6)
-#define lpddr2_s4 (1<<6)
-#define mddr_lpddr2_bl_2 (0<<20)
-#define mddr_lpddr2_bl_4 (1<<20)
-#define mddr_lpddr2_bl_8 (2<<20)
-#define mddr_lpddr2_bl_16 (3<<20)
-#define ddr2_ddr3_bl_4 (0)
-#define ddr2_ddr3_bl_8 (1)
-#define tfaw_cfg(n) (((n)-4)<<18)
-#define pd_exit_slow (0<<17)
-#define pd_exit_fast (1<<17)
-#define pd_type(n) ((n)<<16)
-#define two_t_en(n) ((n)<<3)
-#define bl8int_en(n) ((n)<<2)
-#define cke_or_en(n) ((n)<<1)
-
-//POWCTL
-#define power_up_start (1<<0)
-
-//POWSTAT
-#define power_up_done (1<<0)
-
-//DFISTSTAT0
-#define dfi_init_complete (1<<0)
-
-//CMDTSTAT
-#define cmd_tstat (1<<0)
-
-//CMDTSTATEN
-#define cmd_tstat_en (1<<1)
-
-//MCMD
-#define Deselect_cmd (0)
-#define PREA_cmd (1)
-#define REF_cmd (2)
-#define MRS_cmd (3)
-#define ZQCS_cmd (4)
-#define ZQCL_cmd (5)
-#define RSTL_cmd (6)
-#define MRR_cmd (8)
-#define DPDE_cmd (9)
-
-#define lpddr2_op(n) ((n)<<12)
-#define lpddr2_ma(n) ((n)<<4)
-
-#define bank_addr(n) ((n)<<17)
-#define cmd_addr(n) ((n)<<4)
-
-#define start_cmd (1u<<31)
-
-typedef union STAT_Tag
-{
- uint32 d32;
- struct
- {
- unsigned ctl_stat : 3;
- unsigned reserved3 : 1;
- unsigned lp_trig : 3;
- unsigned reserved7_31 : 25;
- }b;
-}STAT_T;
-
-typedef union SCFG_Tag
-{
- uint32 d32;
- struct
- {
- unsigned hw_low_power_en : 1;
- unsigned reserved1_5 : 5;
- unsigned nfifo_nif1_dis : 1;
- unsigned reserved7 : 1;
- unsigned bbflags_timing : 4;
- unsigned reserved12_31 : 20;
- } b;
-}SCFG_T;
-
-/* DDR Controller register struct */
-typedef volatile struct DDR_REG_Tag
-{
- //Operational State, Control, and Status Registers
- SCFG_T SCFG; //State Configuration Register
- volatile uint32 SCTL; //State Control Register
- STAT_T STAT; //State Status Register
- volatile uint32 INTRSTAT; //Interrupt Status Register
- uint32 reserved0[(0x40-0x10)/4];
- //Initailization Control and Status Registers
- volatile uint32 MCMD; //Memory Command Register
- volatile uint32 POWCTL; //Power Up Control Registers
- volatile uint32 POWSTAT; //Power Up Status Register
- volatile uint32 CMDTSTAT; //Command Timing Status Register
- volatile uint32 CMDTSTATEN; //Command Timing Status Enable Register
- uint32 reserved1[(0x60-0x54)/4];
- volatile uint32 MRRCFG0; //MRR Configuration 0 Register
- volatile uint32 MRRSTAT0; //MRR Status 0 Register
- volatile uint32 MRRSTAT1; //MRR Status 1 Register
- uint32 reserved2[(0x7c-0x6c)/4];
- //Memory Control and Status Registers
- volatile uint32 MCFG1; //Memory Configuration 1 Register
- volatile uint32 MCFG; //Memory Configuration Register
- volatile uint32 PPCFG; //Partially Populated Memories Configuration Register
- volatile uint32 MSTAT; //Memory Status Register
- volatile uint32 LPDDR2ZQCFG; //LPDDR2 ZQ Configuration Register
- uint32 reserved3;
- //DTU Control and Status Registers
- volatile uint32 DTUPDES; //DTU Status Register
- volatile uint32 DTUNA; //DTU Number of Random Addresses Created Register
- volatile uint32 DTUNE; //DTU Number of Errors Register
- volatile uint32 DTUPRD0; //DTU Parallel Read 0
- volatile uint32 DTUPRD1; //DTU Parallel Read 1
- volatile uint32 DTUPRD2; //DTU Parallel Read 2
- volatile uint32 DTUPRD3; //DTU Parallel Read 3
- volatile uint32 DTUAWDT; //DTU Address Width
- uint32 reserved4[(0xc0-0xb4)/4];
- //Memory Timing Registers
- volatile uint32 TOGCNT1U; //Toggle Counter 1U Register
- volatile uint32 TINIT; //t_init Timing Register
- volatile uint32 TRSTH; //Reset High Time Register
- volatile uint32 TOGCNT100N; //Toggle Counter 100N Register
- volatile uint32 TREFI; //t_refi Timing Register
- volatile uint32 TMRD; //t_mrd Timing Register
- volatile uint32 TRFC; //t_rfc Timing Register
- volatile uint32 TRP; //t_rp Timing Register
- volatile uint32 TRTW; //t_rtw Timing Register
- volatile uint32 TAL; //AL Latency Register
- volatile uint32 TCL; //CL Timing Register
- volatile uint32 TCWL; //CWL Register
- volatile uint32 TRAS; //t_ras Timing Register
- volatile uint32 TRC; //t_rc Timing Register
- volatile uint32 TRCD; //t_rcd Timing Register
- volatile uint32 TRRD; //t_rrd Timing Register
- volatile uint32 TRTP; //t_rtp Timing Register
- volatile uint32 TWR; //t_wr Timing Register
- volatile uint32 TWTR; //t_wtr Timing Register
- volatile uint32 TEXSR; //t_exsr Timing Register
- volatile uint32 TXP; //t_xp Timing Register
- volatile uint32 TXPDLL; //t_xpdll Timing Register
- volatile uint32 TZQCS; //t_zqcs Timing Register
- volatile uint32 TZQCSI; //t_zqcsi Timing Register
- volatile uint32 TDQS; //t_dqs Timing Register
- volatile uint32 TCKSRE; //t_cksre Timing Register
- volatile uint32 TCKSRX; //t_cksrx Timing Register
- volatile uint32 TCKE; //t_cke Timing Register
- volatile uint32 TMOD; //t_mod Timing Register
- volatile uint32 TRSTL; //Reset Low Timing Register
- volatile uint32 TZQCL; //t_zqcl Timing Register
- volatile uint32 TMRR; //t_mrr Timing Register
- volatile uint32 TCKESR; //t_ckesr Timing Register
- volatile uint32 TDPD; //t_dpd Timing Register
- uint32 reserved5[(0x180-0x148)/4];
- //ECC Configuration, Control, and Status Registers
- volatile uint32 ECCCFG; //ECC Configuration Register
- volatile uint32 ECCTST; //ECC Test Register
- volatile uint32 ECCCLR; //ECC Clear Register
- volatile uint32 ECCLOG; //ECC Log Register
- uint32 reserved6[(0x200-0x190)/4];
- //DTU Control and Status Registers
- volatile uint32 DTUWACTL; //DTU Write Address Control Register
- volatile uint32 DTURACTL; //DTU Read Address Control Register
- volatile uint32 DTUCFG; //DTU Configuration Control Register
- volatile uint32 DTUECTL; //DTU Execute Control Register
- volatile uint32 DTUWD0; //DTU Write Data 0
- volatile uint32 DTUWD1; //DTU Write Data 1
- volatile uint32 DTUWD2; //DTU Write Data 2
- volatile uint32 DTUWD3; //DTU Write Data 3
- volatile uint32 DTUWDM; //DTU Write Data Mask
- volatile uint32 DTURD0; //DTU Read Data 0
- volatile uint32 DTURD1; //DTU Read Data 1
- volatile uint32 DTURD2; //DTU Read Data 2
- volatile uint32 DTURD3; //DTU Read Data 3
- volatile uint32 DTULFSRWD; //DTU LFSR Seed for Write Data Generation
- volatile uint32 DTULFSRRD; //DTU LFSR Seed for Read Data Generation
- volatile uint32 DTUEAF; //DTU Error Address FIFO
- //DFI Control Registers
- volatile uint32 DFITCTRLDELAY; //DFI tctrl_delay Register
- volatile uint32 DFIODTCFG; //DFI ODT Configuration Register
- volatile uint32 DFIODTCFG1; //DFI ODT Configuration 1 Register
- volatile uint32 DFIODTRANKMAP; //DFI ODT Rank Mapping Register
- //DFI Write Data Registers
- volatile uint32 DFITPHYWRDATA; //DFI tphy_wrdata Register
- volatile uint32 DFITPHYWRLAT; //DFI tphy_wrlat Register
- uint32 reserved7[(0x260-0x258)/4];
- volatile uint32 DFITRDDATAEN; //DFI trddata_en Register
- volatile uint32 DFITPHYRDLAT; //DFI tphy_rddata Register
- uint32 reserved8[(0x270-0x268)/4];
- //DFI Update Registers
- volatile uint32 DFITPHYUPDTYPE0; //DFI tphyupd_type0 Register
- volatile uint32 DFITPHYUPDTYPE1; //DFI tphyupd_type1 Register
- volatile uint32 DFITPHYUPDTYPE2; //DFI tphyupd_type2 Register
- volatile uint32 DFITPHYUPDTYPE3; //DFI tphyupd_type3 Register
- volatile uint32 DFITCTRLUPDMIN; //DFI tctrlupd_min Register
- volatile uint32 DFITCTRLUPDMAX; //DFI tctrlupd_max Register
- volatile uint32 DFITCTRLUPDDLY; //DFI tctrlupd_dly Register
- uint32 reserved9;
- volatile uint32 DFIUPDCFG; //DFI Update Configuration Register
- volatile uint32 DFITREFMSKI; //DFI Masked Refresh Interval Register
- volatile uint32 DFITCTRLUPDI; //DFI tctrlupd_interval Register
- uint32 reserved10[(0x2ac-0x29c)/4];
- volatile uint32 DFITRCFG0; //DFI Training Configuration 0 Register
- volatile uint32 DFITRSTAT0; //DFI Training Status 0 Register
- volatile uint32 DFITRWRLVLEN; //DFI Training dfi_wrlvl_en Register
- volatile uint32 DFITRRDLVLEN; //DFI Training dfi_rdlvl_en Register
- volatile uint32 DFITRRDLVLGATEEN; //DFI Training dfi_rdlvl_gate_en Register
- //DFI Status Registers
- volatile uint32 DFISTSTAT0; //DFI Status Status 0 Register
- volatile uint32 DFISTCFG0; //DFI Status Configuration 0 Register
- volatile uint32 DFISTCFG1; //DFI Status configuration 1 Register
- uint32 reserved11;
- volatile uint32 DFITDRAMCLKEN; //DFI tdram_clk_enalbe Register
- volatile uint32 DFITDRAMCLKDIS; //DFI tdram_clk_disalbe Register
- volatile uint32 DFISTCFG2; //DFI Status configuration 2 Register
- volatile uint32 DFISTPARCLR; //DFI Status Parity Clear Register
- volatile uint32 DFISTPARLOG; //DFI Status Parity Log Register
- uint32 reserved12[(0x2f0-0x2e4)/4];
- //DFI Low Power Registers
- volatile uint32 DFILPCFG0; //DFI Low Power Configuration 0 Register
- uint32 reserved13[(0x300-0x2f4)/4];
- //DFI Training 2 Registers
- volatile uint32 DFITRWRLVLRESP0; //DFI Training dif_wrlvl_resp Status 0 Register
- volatile uint32 DFITRWRLVLRESP1; //DFI Training dif_wrlvl_resp Status 1 Register
- volatile uint32 DFITRWRLVLRESP2; //DFI Training dif_wrlvl_resp Status 2 Register
- volatile uint32 DFITRRDLVLRESP0; //DFI Training dif_rdlvl_resp Status 0 Register
- volatile uint32 DFITRRDLVLRESP1; //DFI Training dif_rdlvl_resp Status 1 Register
- volatile uint32 DFITRRDLVLRESP2; //DFI Training dif_rdlvl_resp Status 2 Register
- volatile uint32 DFITRWRLVLDELAY0; //DFI Training dif_wrlvl_delay Configuration 0 Register
- volatile uint32 DFITRWRLVLDELAY1; //DFI Training dif_wrlvl_delay Configuration 1 Register
- volatile uint32 DFITRWRLVLDELAY2; //DFI Training dif_wrlvl_delay Configuration 2 Register
- volatile uint32 DFITRRDLVLDELAY0; //DFI Training dif_rdlvl_delay Configuration 0 Register
- volatile uint32 DFITRRDLVLDELAY1; //DFI Training dif_rdlvl_delay Configuration 1 Register
- volatile uint32 DFITRRDLVLDELAY2; //DFI Training dif_rdlvl_delay Configuration 2 Register
- volatile uint32 DFITRRDLVLGATEDELAY0; //DFI Training dif_rdlvl_gate_delay Configuration 0 Register
- volatile uint32 DFITRRDLVLGATEDELAY1; //DFI Training dif_rdlvl_gate_delay Configuration 1 Register
- volatile uint32 DFITRRDLVLGATEDELAY2; //DFI Training dif_rdlvl_gate_delay Configuration 2 Register
- volatile uint32 DFITRCMD; //DFI Training Command Register
- uint32 reserved14[(0x3f8-0x340)/4];
- //IP Status Registers
- volatile uint32 IPVR; //IP Version Register
- volatile uint32 IPTR; //IP Type Register
-}DDR_REG_T, *pDDR_REG_T;
-
-#define pDDR_Reg ((pDDR_REG_T)SDRAMC_BASE_ADDR)
-
-//PHY_REG2
-#define PHY_AUTO_CALIBRATION (1<<0)
-#define PHY_SW_CALIBRATION (1<<1)
-#define PHY_MEM_TYPE (6)
-
-//PHY_REG22,25,26,27,28
-#if defined (CONFIG_ARCH_RK3026) //RK3028A /rk3026
-#define PHY_RON_DISABLE (0)
-#define PHY_RON_309ohm (1)
-#define PHY_RON_155ohm (2)
-#define PHY_RON_103ohm (3)
-#define PHY_RON_77ohm (4)
-#define PHY_RON_63ohm (5)
-#define PHY_RON_52ohm (6)
-#define PHY_RON_45ohm (7)
-//#define PHY_RON_77ohm (8)
-#define PHY_RON_62ohm (9)
-//#define PHY_RON_52ohm (10)
-#define PHY_RON_44ohm (11)
-#define PHY_RON_39ohm (12)
-#define PHY_RON_34ohm (13)
-#define PHY_RON_31ohm (14)
-#define PHY_RON_28ohm (15)
-
-#define PHY_RTT_DISABLE (0)
-#define PHY_RTT_816ohm (1)
-#define PHY_RTT_431ohm (2)
-#define PHY_RTT_287ohm (3)
-#define PHY_RTT_216ohm (4)
-#define PHY_RTT_172ohm (5)
-#define PHY_RTT_145ohm (6)
-#define PHY_RTT_124ohm (7)
-#define PHY_RTT_215ohm (8)
-//#define PHY_RTT_172ohm (9)
-#define PHY_RTT_144ohm (10)
-#define PHY_RTT_123ohm (11)
-#define PHY_RTT_108ohm (12)
-#define PHY_RTT_96ohm (13)
-#define PHY_RTT_86ohm (14)
-#define PHY_RTT_78ohm (15)
-
-#else //RK292x
-#define PHY_RON_DISABLE (0)
-#define PHY_RON_138O (1)
-//#define PHY_RON_69O (2)
-//#define PHY_RON_46O (3)
-#define PHY_RON_69O (4)
-#define PHY_RON_46O (5)
-#define PHY_RON_34O (6)
-#define PHY_RON_28O (7)
-
-#define PHY_RTT_DISABLE (0)
-#define PHY_RTT_212O (1)
-#define PHY_RTT_106O (4)
-#define PHY_RTT_71O (5)
-#define PHY_RTT_53O (6)
-#define PHY_RTT_42O (7)
-#endif
-
-/* DDR PHY register struct */
-typedef volatile struct DDRPHY_REG_Tag
-{
- volatile uint32 PHY_REG1; //PHY soft reset Register
- volatile uint32 PHY_REG3; //Burst type select Register
- volatile uint32 PHY_REG2; //PHY DQS squelch calibration Register
- uint32 reserved1[(0x38-0x0a)/4];
- volatile uint32 PHY_REG4a; //CL,AL set register
- volatile uint32 PHY_REG4b; //dqs gata delay select bypass mode register
- uint32 reserved2[(0x54-0x40)/4];
- volatile uint32 PHY_REG16; //
- uint32 reserved3[(0x5c-0x58)/4];
- volatile uint32 PHY_REG18; //0x5c
- volatile uint32 PHY_REG19;
- uint32 reserved4[(0x68-0x64)/4];
- volatile uint32 PHY_REG21; //0x68
- uint32 reserved5[(0x70-0x6c)/4];
- volatile uint32 PHY_REG22; //0x70
- uint32 reserved6[(0x80-0x74)/4];
- volatile uint32 PHY_REG25; //0x80
- volatile uint32 PHY_REG26;
- volatile uint32 PHY_REG27;
- volatile uint32 PHY_REG28;
- uint32 reserved7[(0xd4-0x90)/4];
- volatile uint32 PHY_REG6; //0xd4
- volatile uint32 PHY_REG7;
- uint32 reserved8[(0xe0-0xdc)/4];
- volatile uint32 PHY_REG8; //0xe0
- volatile uint32 PHY_REG0e4; //use for DQS ODT off
- uint32 reserved9[(0x114-0xe8)/4];
- volatile uint32 PHY_REG9; //0x114
- volatile uint32 PHY_REG10;
- uint32 reserved10[(0x120-0x11c)/4];
- volatile uint32 PHY_REG11; //0x120
- volatile uint32 PHY_REG124; //use for DQS ODT off
- uint32 reserved11[(0x1c0-0x128)/4];
- volatile uint32 PHY_REG29; //0x1c0
- uint32 reserved12[(0x264-0x1c4)/4];
- volatile uint32 PHY_REG264; //use for phy soft reset
- uint32 reserved13[(0x2b0-0x268)/4];
- volatile uint32 PHY_REG2a; //0x2b0
- uint32 reserved14[(0x2c4-0x2b4)/4];
-// volatile uint32 PHY_TX_DeSkew[24]; //0x2c4-0x320
- volatile uint32 PHY_REG30;
- volatile uint32 PHY_REG31;
- volatile uint32 PHY_REG32;
- volatile uint32 PHY_REG33;
- volatile uint32 PHY_REG34;
- volatile uint32 PHY_REG35;
- volatile uint32 PHY_REG36;
- volatile uint32 PHY_REG37;
- volatile uint32 PHY_REG38;
- volatile uint32 PHY_REG39;
- volatile uint32 PHY_REG40;
- volatile uint32 PHY_REG41;
- volatile uint32 PHY_REG42;
- volatile uint32 PHY_REG43;
- volatile uint32 PHY_REG44;
- volatile uint32 PHY_REG45;
- volatile uint32 PHY_REG46;
- volatile uint32 PHY_REG47;
- volatile uint32 PHY_REG48;
- volatile uint32 PHY_REG49;
- volatile uint32 PHY_REG50;
- volatile uint32 PHY_REG51;
- volatile uint32 PHY_REG52;
- volatile uint32 PHY_REG53;
- uint32 reserved15[(0x328-0x324)/4];
-// volatile uint32 PHY_RX_DeSkew[11]; //0x328-0x350
- volatile uint32 PHY_REG54;
- volatile uint32 PHY_REG55;
- volatile uint32 PHY_REG56;
- volatile uint32 PHY_REG57;
- volatile uint32 PHY_REG58;
- volatile uint32 PHY_REG59;
- volatile uint32 PHY_REG5a;
- volatile uint32 PHY_REG5b;
- volatile uint32 PHY_REG5c;
- volatile uint32 PHY_REG5d;
- volatile uint32 PHY_REG5e;
- uint32 reserved16[(0x3c4-0x354)/4];
- volatile uint32 PHY_REG5f; //0x3c4
- uint32 reserved17[(0x3e0-0x3c8)/4];
- volatile uint32 PHY_REG60;
- volatile uint32 PHY_REG61;
- volatile uint32 PHY_REG62;
-}DDRPHY_REG_T, *pDDRPHY_REG_T;
-
-#define pPHY_Reg ((pDDRPHY_REG_T)DDR_PHY_BASE)
-
-typedef enum DRAM_TYPE_Tag
-{
- LPDDR = 0,
- DDR,
- DDR2,
- DDR3,
- LPDDR2_S2,
- LPDDR2_S4,
-
- DRAM_MAX
-}DRAM_TYPE;
-
-
-typedef struct PCTRL_TIMING_Tag
-{
- uint32 ddrFreq;
- //Memory Timing Registers
- uint32 togcnt1u; //Toggle Counter 1U Register
- uint32 tinit; //t_init Timing Register
- uint32 trsth; //Reset High Time Register
- uint32 togcnt100n; //Toggle Counter 100N Register
- uint32 trefi; //t_refi Timing Register
- uint32 tmrd; //t_mrd Timing Register
- uint32 trfc; //t_rfc Timing Register
- uint32 trp; //t_rp Timing Register
- uint32 trtw; //t_rtw Timing Register
- uint32 tal; //AL Latency Register
- uint32 tcl; //CL Timing Register
- uint32 tcwl; //CWL Register
- uint32 tras; //t_ras Timing Register
- uint32 trc; //t_rc Timing Register
- uint32 trcd; //t_rcd Timing Register
- uint32 trrd; //t_rrd Timing Register
- uint32 trtp; //t_rtp Timing Register
- uint32 twr; //t_wr Timing Register
- uint32 twtr; //t_wtr Timing Register
- uint32 texsr; //t_exsr Timing Register
- uint32 txp; //t_xp Timing Register
- uint32 txpdll; //t_xpdll Timing Register
- uint32 tzqcs; //t_zqcs Timing Register
- uint32 tzqcsi; //t_zqcsi Timing Register
- uint32 tdqs; //t_dqs Timing Register
- uint32 tcksre; //t_cksre Timing Register
- uint32 tcksrx; //t_cksrx Timing Register
- uint32 tcke; //t_cke Timing Register
- uint32 tmod; //t_mod Timing Register
- uint32 trstl; //Reset Low Timing Register
- uint32 tzqcl; //t_zqcl Timing Register
- uint32 tmrr; //t_mrr Timing Register
- uint32 tckesr; //t_ckesr Timing Register
- uint32 tdpd; //t_dpd Timing Register
-}PCTL_TIMING_T;
-
-
-typedef union NOC_TIMING_Tag
-{
- uint32 d32;
- struct
- {
- unsigned ActToAct : 6;
- unsigned RdToMiss : 6;
- unsigned WrToMiss : 6;
- unsigned BurstLen : 3;
- unsigned RdToWr : 5;
- unsigned WrToRd : 5;
- unsigned BwRatio : 1;
- } b;
-}NOC_TIMING_T;
-
-typedef struct PCTL_REG_Tag
-{
- uint32 SCFG;
- uint32 CMDTSTATEN;
- uint32 MCFG1;
- uint32 MCFG;
- PCTL_TIMING_T pctl_timing;
- //DFI Control Registers
- uint32 DFITCTRLDELAY;
- uint32 DFIODTCFG;
- uint32 DFIODTCFG1;
- uint32 DFIODTRANKMAP;
- //DFI Write Data Registers
- uint32 DFITPHYWRDATA;
- uint32 DFITPHYWRLAT;
- //DFI Read Data Registers
- uint32 DFITRDDATAEN;
- uint32 DFITPHYRDLAT;
- //DFI Update Registers
- uint32 DFITPHYUPDTYPE0;
- uint32 DFITPHYUPDTYPE1;
- uint32 DFITPHYUPDTYPE2;
- uint32 DFITPHYUPDTYPE3;
- uint32 DFITCTRLUPDMIN;
- uint32 DFITCTRLUPDMAX;
- uint32 DFITCTRLUPDDLY;
- uint32 DFIUPDCFG;
- uint32 DFITREFMSKI;
- uint32 DFITCTRLUPDI;
- //DFI Status Registers
- uint32 DFISTCFG0;
- uint32 DFISTCFG1;
- uint32 DFITDRAMCLKEN;
- uint32 DFITDRAMCLKDIS;
- uint32 DFISTCFG2;
- //DFI Low Power Register
- uint32 DFILPCFG0;
-}PCTL_REG_T;
-
-typedef struct BACKUP_REG_Tag
-{
- PCTL_REG_T pctl;
- uint32 DdrConf;
- NOC_TIMING_T noc_timing;
- uint32 DdrMode;
- uint32 ReadLatency;
- uint32 ddrMR[4];
-}BACKUP_REG_T;
-
-__sramdata BACKUP_REG_T ddr_reg;
-
-
-uint32_t ddr3_cl_cwl[22][4]={
-/* 0~330 330~400 400~533 speed
-* tCK >3 2.5~3 1.875~2.5 1.875~1.5
-* cl<<16, cwl cl<<16, cwl cl<<16, cwl */
- {((5<<16)|5), ((5<<16)|5), 0 , 0}, //DDR3_800D
- {((5<<16)|5), ((6<<16)|5), 0 , 0}, //DDR3_800E
-
- {((5<<16)|5), ((5<<16)|5), ((6<<16)|6), 0}, //DDR3_1066E
- {((5<<16)|5), ((6<<16)|5), ((7<<16)|6), 0}, //DDR3_1066F
- {((5<<16)|5), ((6<<16)|5), ((8<<16)|6), 0}, //DDR3_1066G
-
- {((5<<16)|5), ((5<<16)|5), ((6<<16)|6), ((7<<16)|7)}, //DDR3_1333F
- {((5<<16)|5), ((5<<16)|5), ((7<<16)|6), ((8<<16)|7)}, //DDR3_1333G
- {((5<<16)|5), ((6<<16)|5), ((7<<16)|6), ((9<<16)|7)}, //DDR3_1333H
- {((5<<16)|5), ((6<<16)|5), ((8<<16)|6), ((10<<16)|7)}, //DDR3_1333J
-
- {((5<<16)|5), ((5<<16)|5), ((6<<16)|6), ((7<<16)|7)}, //DDR3_1600G
- {((5<<16)|5), ((5<<16)|5), ((6<<16)|6), ((8<<16)|7)}, //DDR3_1600H
- {((5<<16)|5), ((5<<16)|5), ((7<<16)|6), ((9<<16)|7)}, //DDR3_1600J
- {((5<<16)|5), ((6<<16)|5), ((7<<16)|6), ((10<<16)|7)}, //DDR3_1600K
-
- {((5<<16)|5), ((5<<16)|5), ((6<<16)|6), ((8<<16)|7)}, //DDR3_1866J
- {((5<<16)|5), ((5<<16)|5), ((7<<16)|6), ((8<<16)|7)}, //DDR3_1866K
- {((6<<16)|5), ((6<<16)|5), ((7<<16)|6), ((9<<16)|7)}, //DDR3_1866L
- {((6<<16)|5), ((6<<16)|5), ((8<<16)|6), ((10<<16)|7)}, //DDR3_1866M
-
- {((5<<16)|5), ((5<<16)|5), ((6<<16)|6), ((7<<16)|7)}, //DDR3_2133K
- {((5<<16)|5), ((5<<16)|5), ((6<<16)|6), ((8<<16)|7)}, //DDR3_2133L
- {((5<<16)|5), ((5<<16)|5), ((7<<16)|6), ((9<<16)|7)}, //DDR3_2133M
- {((6<<16)|5), ((6<<16)|5), ((7<<16)|6), ((9<<16)|7)}, //DDR3_2133N
-
- {((6<<16)|5), ((6<<16)|5), ((8<<16)|6), ((10<<16)|7)} //DDR3_DEFAULT
-
-};
-uint32_t ddr3_tRC_tFAW[22]={
-/** tRC tFAW */
- ((50<<16)|50), //DDR3_800D
- ((53<<16)|50), //DDR3_800E
-
- ((49<<16)|50), //DDR3_1066E
- ((51<<16)|50), //DDR3_1066F
- ((53<<16)|50), //DDR3_1066G
-
- ((47<<16)|45), //DDR3_1333F
- ((48<<16)|45), //DDR3_1333G
- ((50<<16)|45), //DDR3_1333H
- ((51<<16)|45), //DDR3_1333J
-
- ((45<<16)|40), //DDR3_1600G
- ((47<<16)|40), //DDR3_1600H
- ((48<<16)|40), //DDR3_1600J
- ((49<<16)|40), //DDR3_1600K
-
- ((45<<16)|35), //DDR3_1866J
- ((46<<16)|35), //DDR3_1866K
- ((47<<16)|35), //DDR3_1866L
- ((48<<16)|35), //DDR3_1866M
-
- ((44<<16)|35), //DDR3_2133K
- ((45<<16)|35), //DDR3_2133L
- ((46<<16)|35), //DDR3_2133M
- ((47<<16)|35), //DDR3_2133N
-
- ((53<<16)|50) //DDR3_DEFAULT
-};
-
-__sramdata uint32_t mem_type; //0:DDR3 1:DDR2 ;ÓëInno PHY µÄPHY_REG2 ÀïÉèÖõÄÖµÏàÒ»ÖÂ
-static __sramdata uint32_t ddr_speed_bin; // used for ddr3 only
-static __sramdata uint32_t ddr_capability_per_die; // one chip cs capability
-static __sramdata uint32_t ddr_freq;
-static __sramdata uint32_t ddr_sr_idle;
-static __sramdata uint32_t ddr_dll_status; // ¼Ç¼ddr dllµÄ״̬£¬ÔÚselfrefresh exitʱѡÔñÊÇ·ñ½øÐÐdll reset
-
-/****************************************************************************
-Internal sram us delay function
-Cpu highest frequency is 1.6 GHz
-1 cycle = 1/1.6 ns
-1 us = 1000 ns = 1000 * 1.6 cycles = 1600 cycles
-*****************************************************************************/
-static __sramdata uint32_t loops_per_us;
-
-#define LPJ_100MHZ 999456UL
-
-/*----------------------------------------------------------------------
-Name : void __sramlocalfunc ddr_delayus(uint32_t us)
-Desc : ddr ÑÓʱº¯Êý
-Params : uint32_t us --ÑÓʱʱ¼ä
-Return : void
-Notes : loops_per_us Ϊȫ¾Ö±äÁ¿ ÐèÒª¸ù¾Ýarm freq¶ø¶¨
-----------------------------------------------------------------------*/
-
-/*static*/ void __sramlocalfunc ddr_delayus(uint32_t us)
-{
- uint32_t count;
-
- count = loops_per_us*us;
- while(count--) // 3 cycles
- barrier();
-}
-
-/*----------------------------------------------------------------------
-Name : __sramfunc void ddr_copy(uint32 *pDest, uint32 *pSrc, uint32 words)
-Desc : ddr ¿½±´¼Ä´æÆ÷º¯Êý
-Params : pDest ->Ä¿±ê¼Ä´æÆ÷Ê×µØÖ·
- pSrc ->Ô´±ê¼Ä´æÆ÷Ê×µØÖ·
- words ->¿½±´³¤¶È
-Return : void
-Notes :
-----------------------------------------------------------------------*/
-
-__sramfunc void ddr_copy(uint32 *pDest, uint32 *pSrc, uint32 words)
-{
- uint32 i;
-
- for(i=0; i<words; i++)
- {
- pDest[i] = pSrc[i];
- }
-}
-
-/*----------------------------------------------------------------------
-Name : uint32 ddr_get_row(void)
-Desc : »ñÈ¡ddr row ÐÅÏ¢
-Params : void
-Return : row Êý
-Notes :
-----------------------------------------------------------------------*/
-uint32 ddr_get_row(void)
-{
- return (13+((pGRF_Reg->GRF_OS_REG[1] >> DDR_ROW_COUNT) & 0x3));
-}
-
-/*----------------------------------------------------------------------
-Name : uint32 ddr_get_bank(void)
-Desc : »ñÈ¡ddr bank ÐÅÏ¢
-Params : void
-Return : bank Êý
-Notes :
-----------------------------------------------------------------------*/
-uint32 ddr_get_bank(void)
-{
- return (((pGRF_Reg->GRF_OS_REG[1] >> DDR_BANK_COUNT) & 0x1)? 2:3);
-}
-
-/*----------------------------------------------------------------------
-Name : uint32 ddr_get_col(void)
-Desc : »ñÈ¡ddr col ÐÅÏ¢
-Params : void
-Return : col Êý
-Notes :
-----------------------------------------------------------------------*/
-uint32 ddr_get_col(void)
-{
- return (9 + ((pGRF_Reg->GRF_OS_REG[1]>>DDR_COL_COUNT)&0x3));
-}
-
-/*----------------------------------------------------------------------
-Name : __sramfunc void ddr_move_to_Lowpower_state(void)
-Desc : pctl ½øÈë lowpower state
-Params : void
-Return : void
-Notes :
-----------------------------------------------------------------------*/
-__sramfunc void ddr_move_to_Lowpower_state(void)
-{
- volatile uint32 value;
-
- while(1)
- {
- value = pDDR_Reg->STAT.b.ctl_stat;
- if(value == Low_power)
- {
- break;
- }
- switch(value)
- {
- case Init_mem:
- pDDR_Reg->SCTL = CFG_STATE;
- dsb();
- while((pDDR_Reg->STAT.b.ctl_stat) != Config);
- case Config:
- pDDR_Reg->SCTL = GO_STATE;
- dsb();
- while((pDDR_Reg->STAT.b.ctl_stat) != Access);
- case Access:
- pDDR_Reg->SCTL = SLEEP_STATE;
- dsb();
- while((pDDR_Reg->STAT.b.ctl_stat) != Low_power);
- break;
- default: //Transitional state
- break;
- }
- }
-}
-
-/*----------------------------------------------------------------------
-Name : __sramfunc void ddr_move_to_Access_state(void)
-Desc : pctl ½øÈë Access state
-Params : void
-Return : void
-Notes :
-----------------------------------------------------------------------*/
-__sramfunc void ddr_move_to_Access_state(void)
-{
- volatile uint32 value;
-
- //set auto self-refresh idle
- pDDR_Reg->MCFG1=(pDDR_Reg->MCFG1&0xffffff00)|ddr_sr_idle | (1<<31);
-
- while(1)
- {
- value = pDDR_Reg->STAT.b.ctl_stat;
- if((value == Access)
- || ((pDDR_Reg->STAT.b.lp_trig == 1) && ((pDDR_Reg->STAT.b.ctl_stat) == Low_power)))
- {
- break;
- }
- switch(value)
- {
- case Low_power:
- pDDR_Reg->SCTL = WAKEUP_STATE;
- dsb();
- while((pDDR_Reg->STAT.b.ctl_stat) != Access);
- break;
- case Init_mem:
- pDDR_Reg->SCTL = CFG_STATE;
- dsb();
- while((pDDR_Reg->STAT.b.ctl_stat) != Config);
- case Config:
- pDDR_Reg->SCTL = GO_STATE;
- dsb();
- while(!(((pDDR_Reg->STAT.b.ctl_stat) == Access)
- || ((pDDR_Reg->STAT.b.lp_trig == 1) && ((pDDR_Reg->STAT.b.ctl_stat) == Low_power))));
- break;
- default: //Transitional state
- break;
- }
- }
- pGRF_Reg->GRF_SOC_CON[2] = (1<<16 | 0);//de_hw_wakeup :enable auto sr if sr_idle != 0
-}
-
-/*----------------------------------------------------------------------
-Name : __sramfunc void ddr_move_to_Config_state(void)
-Desc : pctl ½øÈë config state
-Params : void
-Return : void
-Notes :
-----------------------------------------------------------------------*/
-__sramfunc void ddr_move_to_Config_state(void)
-{
- volatile uint32 value;
- pGRF_Reg->GRF_SOC_CON[2] = (1<<16 | 1); //hw_wakeup :disable auto sr
- while(1)
- {
- value = pDDR_Reg->STAT.b.ctl_stat;
- if(value == Config)
- {
- break;
- }
- switch(value)
- {
- case Low_power:
- pDDR_Reg->SCTL = WAKEUP_STATE;
- dsb();
- case Access:
- case Init_mem:
- pDDR_Reg->SCTL = CFG_STATE;
- dsb();
- break;
- default: //Transitional state
- break;
- }
- }
-}
-
-/*----------------------------------------------------------------------
-Name : void __sramlocalfunc ddr_send_command(uint32 rank, uint32 cmd, uint32 arg)
-Desc : ͨ¹ýд pctl MCMD¼Ä´æÆ÷Ïòddr·¢ËÍÃüÁî
-Params : rank ->ddr rank Êý
- cmd ->·¢ËÍÃüÁîÀàÐÍ
- arg ->·¢Ë͵ÄÊý¾Ý
-Return : void
-Notes : arg°üÀ¨bank_addrºÍcmd_addr
-----------------------------------------------------------------------*/
-void __sramlocalfunc ddr_send_command(uint32 rank, uint32 cmd, uint32 arg)
-{
- pDDR_Reg->MCMD = (start_cmd | (rank<<20) | arg | cmd);
- dsb();
- while(pDDR_Reg->MCMD & start_cmd);
-}
-
-__sramdata uint32 copy_data[8]={0xffffffff,0x00000000,0x55555555,0xAAAAAAAA,
- 0xEEEEEEEE,0x11111111,0x22222222,0xDDDDDDDD};/**/
-
-/*----------------------------------------------------------------------
-Name : uint32_t __sramlocalfunc ddr_data_training(void)
-Desc : ¶Ôddr×ödata training
-Params : void
-Return : void
-Notes : ûÓÐ×ödata trainingУÑé
-----------------------------------------------------------------------*/
-uint32_t __sramlocalfunc ddr_data_training(void)
-{
- uint32 value, cs;
- value = pDDR_Reg->TREFI;
- pDDR_Reg->TREFI = 0;
- cs = (pGRF_Reg->GRF_OS_REG[1] >> DDR_RANK_COUNT) & 0x1;
- cs = cs + (1 << cs); //case 0:1rank cs=1; case 1:2rank cs =3;
- // trigger DTT
- pPHY_Reg->PHY_REG2 = ((pPHY_Reg->PHY_REG2 & (~0x1)) | PHY_AUTO_CALIBRATION);
- // wait echo byte DTDONE
- ddr_delayus(6);
- // stop DTT
- while((pPHY_Reg->PHY_REG62 & 0x3)!=0x3);
- pPHY_Reg->PHY_REG2 = (pPHY_Reg->PHY_REG2 & (~0x1));
- // send some auto refresh to complement the lost while DTT
- ddr_send_command(cs, REF_cmd, 0);
- ddr_send_command(cs, REF_cmd, 0);
- ddr_send_command(cs, REF_cmd, 0);
- ddr_send_command(cs, REF_cmd, 0);
-
- // resume auto refresh
- pDDR_Reg->TREFI = value;
-
- return(0);
-}
-
-/*----------------------------------------------------------------------
-Name : void __sramlocalfunc ddr_set_dll_bypass(uint32 freq)
-Desc : ÉèÖÃPHY dll ¹¤×÷ģʽ
-Params : freq -> ddr¹¤×÷ƵÂÊ
-Return : void
-Notes :
-----------------------------------------------------------------------*/
-void __sramlocalfunc ddr_set_dll_bypass(uint32 freq)
-{
- if(freq <= PHY_DLL_DISABLE_FREQ)
- {
- pPHY_Reg->PHY_REG2a = 0x1F; //set cmd,left right dll bypass
- pPHY_Reg->PHY_REG19 = 0x08; //cmd slave dll
- pPHY_Reg->PHY_REG6 = 0x18; //left TX DQ DLL
- pPHY_Reg->PHY_REG7 = 0x00; //left TX DQS DLL
- pPHY_Reg->PHY_REG9 = 0x18; //right TX DQ DLL
- pPHY_Reg->PHY_REG10 = 0x00; //right TX DQS DLL
-
- }
- else
- {
- pPHY_Reg->PHY_REG2a = 0x03; //set cmd,left right dll bypass
- pPHY_Reg->PHY_REG19 = 0x08; //cmd slave dll
- pPHY_Reg->PHY_REG6 = 0x0c; //left TX DQ DLL
- pPHY_Reg->PHY_REG7 = 0x00; //left TX DQS DLL
- pPHY_Reg->PHY_REG9 = 0x0c; //right TX DQ DLL
- pPHY_Reg->PHY_REG10 = 0x00; //right TX DQS DLL
- }
- dsb();
- //ÆäËûÓëdllÏà¹ØµÄ¼Ä´æÆ÷ÓÐ:REG8(RX DQS),REG11(RX DQS),REG18(CMD),REG21(CK) ±£³ÖĬÈÏÖµ
-}
-
-
-static __sramdata uint32_t clkFbDiv;
-static __sramdata uint32_t clkPostDiv1;
-static __sramdata uint32_t clkPostDiv2;
-
-/*****************************************
-REFDIV FBDIV POSTDIV1/POSTDIV2 FOUTPOSTDIV freq Step FOUTPOSRDIV finally use
-==================================================================================================================
-1 17 - 66 4 100MHz - 400MHz 6MHz 200MHz <= 300MHz <= 150MHz
-1 17 - 66 3 133MHz - 533MHz 8MHz
-1 17 - 66 2 200MHz - 800MHz 12MHz 300MHz <= 600MHz 150MHz <= 300MHz
-1 17 - 66 1 400MHz - 1600MHz 24MHz 600MHz <= 1200MHz 300MHz <= 600MHz
-******************************************/
-//for minimum jitter operation, the highest VCO and FREF frequencies should be used.
-/*----------------------------------------------------------------------
-Name : uint32_t __sramlocalfunc ddr_set_pll(uint32_t nMHz, uint32_t set)
-Desc : ÉèÖÃddr pll
-Params : nMHZ -> ddr¹¤×÷ƵÂÊ
- set ->0»ñÈ¡ÉèÖõÄƵÂÊÐÅÏ¢
- 1ÉèÖÃddr pll
-Return : ÉèÖõÄƵÂÊÖµ
-Notes : ÔÚ±äƵʱÐèÒªÏÈset=0µ÷ÓÃÒ»´Îddr_set_pll£¬ÔÙset=1 µ÷ÓÃddr_set_pll
-----------------------------------------------------------------------*/
-uint32_t __sramlocalfunc ddr_set_pll(uint32_t nMHz, uint32_t set)
-{
- uint32_t ret = 0;
- int delay = 1000;
- uint32_t pll_id=1; //DPLL
-
- if(nMHz == 24)
- {
- ret = 24;
- goto out;
- }
-#if defined (CONFIG_ARCH_RK3026) //RK3028A RK3026
- if(!set)
- {
- if(nMHz <= 150) //ʵ¼ÊÊä³öƵÂÊ<300
- {
- clkPostDiv1 = 6;
- }
- else if(nMHz <=200)
- {
- clkPostDiv1 = 4;
- }
- else if(nMHz <= 300)
- {
- clkPostDiv1 = 3;
- }
- else if(nMHz <=450)
- {
- clkPostDiv1 = 2;
- }
- else
- {
- clkPostDiv1 = 1;
- }
- clkPostDiv2 = 1;
- clkFbDiv = (nMHz * 2 * DDR_PLL_REFDIV * clkPostDiv1 * clkPostDiv2)/24;//×îºóËÍÈëddrµÄÊÇÔÙ¾¹ý2·ÖƵ
- ret = (24 * clkFbDiv)/(2 * DDR_PLL_REFDIV * clkPostDiv1 * clkPostDiv2);
- }
-#else //RK2928 2926
- if(!set)
- {
- if(nMHz <= 150)
- {
- clkPostDiv1 = 4;
- }
- else if(nMHz <= 300)
- {
- clkPostDiv1 = 2;
- }
- else
- {
- clkPostDiv1 = 1;
- }
- clkPostDiv2 = 1;
- clkFbDiv = (nMHz * 2 * DDR_PLL_REFDIV * clkPostDiv1 * clkPostDiv2)/24;//×îºóËÍÈëddrµÄÊÇÔÙ¾¹ý2·ÖƵ
- ret = (24 * clkFbDiv)/(2 * DDR_PLL_REFDIV * clkPostDiv1 * clkPostDiv2);
- }
-#endif
- else
- {
- pCRU_Reg->CRU_MODE_CON = (0x1<<((pll_id*4) + 16)) | (0x0<<(pll_id*4)); //PLL slow-mode
-
- pCRU_Reg->CRU_PLL_CON[pll_id][0] = FBDIV(clkFbDiv) | POSTDIV1(clkPostDiv1);
- pCRU_Reg->CRU_PLL_CON[pll_id][1] = REFDIV(DDR_PLL_REFDIV) | POSTDIV2(clkPostDiv2) | (0x10001<<12);//interger mode
-
- ddr_delayus(1);
-
- while (delay > 0)
- {
- ddr_delayus(1);
- if (pCRU_Reg->CRU_PLL_CON[pll_id][1] & (PLL_LOCK_STATUS)) // wait for pll locked
- break;
- delay--;
- }
-
- pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3<<16) | 0x0); //clk_ddr_src:clk_ddrphy = 1:1
- pCRU_Reg->CRU_MODE_CON = (0x1<<((pll_id*4) + 16)) | (0x1<<(pll_id*4)); //PLL normal
- }
-out:
- return ret;
-}
-
-/*----------------------------------------------------------------------
-Name : uint32_t ddr_get_parameter(uint32_t nMHz)
-Desc : »ñÈ¡ÅäÖòÎÊý
-Params : nMHZ -> ddr¹¤×÷ƵÂÊ
-Return : 0 ³É¹¦
- -1 ʧ°Ü
- -4 ƵÂÊÖµ³¬¹ý¿ÅÁ£×î´óƵÂÊ
-Notes :
-----------------------------------------------------------------------*/
-uint32_t ddr_get_parameter(uint32_t nMHz)
-{
- uint32_t tmp;
- uint32_t ret = 0;
- uint32_t al;
- uint32_t bl;
- uint32_t cl;
- uint32_t cwl;
- PCTL_TIMING_T *p_pctl_timing=&(ddr_reg.pctl.pctl_timing);
- NOC_TIMING_T *p_noc_timing=&(ddr_reg.noc_timing);
-
- p_pctl_timing->togcnt1u = nMHz;
- p_pctl_timing->togcnt100n = nMHz/10;
- p_pctl_timing->tinit = 200;
- p_pctl_timing->trsth = 500;
-
- if(mem_type == DDR3)
- {
- if(ddr_speed_bin > DDR3_DEFAULT)
- {
- ret = -1;
- goto out;
- }
-
- #define DDR3_tREFI_7_8_us (78)
- #define DDR3_tMRD (4)
- #define DDR3_tRFC_512Mb (90)
- #define DDR3_tRFC_1Gb (110)
- #define DDR3_tRFC_2Gb (160)
- #define DDR3_tRFC_4Gb (300)
- #define DDR3_tRFC_8Gb (350)
- #define DDR3_tRTW (2) //register min valid value
- #define DDR3_tRAS (37)
- #define DDR3_tRRD (10)
- #define DDR3_tRTP (7)
- #define DDR3_tWR (15)
- #define DDR3_tWTR (7)
- #define DDR3_tXP (7)
- #define DDR3_tXPDLL (24)
- #define DDR3_tZQCS (80)
- #define DDR3_tZQCSI (10000)
- #define DDR3_tDQS (1)
- #define DDR3_tCKSRE (10)
- #define DDR3_tCKE_400MHz (7)
- #define DDR3_tCKE_533MHz (6)
- #define DDR3_tMOD (15)
- #define DDR3_tRSTL (100)
- #define DDR3_tZQCL (320)
- #define DDR3_tDLLK (512)
-
- al = 0;
- bl = 8;
- if(nMHz <= 330)
- {
- tmp = 0;
- }
- else if(nMHz<=400)
- {
- tmp = 1;
- }
- else if(nMHz<=533)
- {
- tmp = 2;
- }
- else //666MHz
- {
- tmp = 3;
- }
- if(nMHz < DDR3_DDR2_DLL_DISABLE_FREQ) //when dll bypss cl = cwl = 6;
- {
- cl = 6;
- cwl = 6;
- }
- else
- {
- cl = ddr3_cl_cwl[ddr_speed_bin][tmp] >> 16;
- cwl = ddr3_cl_cwl[ddr_speed_bin][tmp] & 0x0ff;
- }
- if(cl == 0)
- {
- ret = -4; //³¬¹ý¿ÅÁ£µÄ×î´óƵÂÊ
- }
- if(nMHz <= DDR3_DDR2_ODT_DISABLE_FREQ)
- {
- ddr_reg.ddrMR[1] = DDR3_DS_40 | DDR3_Rtt_Nom_DIS;
- }
- else
- {
- ddr_reg.ddrMR[1] = DDR3_DS_40 | DDR3_Rtt_Nom_120;
- }
- ddr_reg.ddrMR[2] = DDR3_MR2_CWL(cwl) /* | DDR3_Rtt_WR_60 */;
- ddr_reg.ddrMR[3] = 0;
- /**************************************************
- * PCTL Timing
- **************************************************/
- /*
- * tREFI, average periodic refresh interval, 7.8us
- */
- p_pctl_timing->trefi = DDR3_tREFI_7_8_us;
- /*
- * tMRD, 4 tCK
- */
- p_pctl_timing->tmrd = DDR3_tMRD & 0x7;
- /*
- * tRFC, 90ns(512Mb),110ns(1Gb),160ns(2Gb),300ns(4Gb),350ns(8Gb)
- */
- if(ddr_capability_per_die <= 0x4000000) // 512Mb 90ns
- {
- tmp = DDR3_tRFC_512Mb;
- }
- else if(ddr_capability_per_die <= 0x8000000) // 1Gb 110ns
- {
- tmp = DDR3_tRFC_1Gb;
- }
- else if(ddr_capability_per_die <= 0x10000000) // 2Gb 160ns
- {
- tmp = DDR3_tRFC_2Gb;
- }
- else if(ddr_capability_per_die <= 0x20000000) // 4Gb 300ns
- {
- tmp = DDR3_tRFC_4Gb;
- }
- else // 8Gb 350ns
- {
- tmp = DDR3_tRFC_8Gb;
- }
- p_pctl_timing->trfc = (tmp*nMHz+999)/1000;
- /*
- * tXSR, =tDLLK=512 tCK
- */
- p_pctl_timing->texsr = DDR3_tDLLK;
- /*
- * tRP=CL
- */
- p_pctl_timing->trp = cl;
- /*
- * WrToMiss=WL*tCK + tWR + tRP + tRCD
- */
- p_noc_timing->b.WrToMiss = ((cwl+((DDR3_tWR*nMHz+999)/1000)+cl+cl)&0x3F);
- /*
- * tRC=tRAS+tRP
- */
- p_pctl_timing->trc = ((((ddr3_tRC_tFAW[ddr_speed_bin]>>16)*nMHz+999)/1000)&0x3F);
- p_noc_timing->b.ActToAct = ((((ddr3_tRC_tFAW[ddr_speed_bin]>>16)*nMHz+999)/1000)&0x3F);
-
- p_pctl_timing->trtw = (cl+2-cwl);//DDR3_tRTW;
- p_noc_timing->b.RdToWr = ((cl+2-cwl)&0x1F);
- p_pctl_timing->tal = al;
- p_pctl_timing->tcl = cl;
- p_pctl_timing->tcwl = cwl;
- /*
- * tRAS, 37.5ns(400MHz) 37.5ns(533MHz)
- */
- p_pctl_timing->tras = (((DDR3_tRAS*nMHz+(nMHz>>1)+999)/1000)&0x3F);
- /*
- * tRCD=CL
- */
- p_pctl_timing->trcd = cl;
- /*
- * tRRD = max(4nCK, 7.5ns), DDR3-1066(1K), DDR3-1333(2K), DDR3-1600(2K)
- * max(4nCK, 10ns), DDR3-800(1K,2K), DDR3-1066(2K)
- * max(4nCK, 6ns), DDR3-1333(1K), DDR3-1600(1K)
- *
- */
- tmp = ((DDR3_tRRD*nMHz+999)/1000);
- if(tmp < 4)
- {
- tmp = 4;
- }
- p_pctl_timing->trrd = (tmp&0xF);
- /*
- * tRTP, max(4 tCK,7.5ns)
- */
- tmp = ((DDR3_tRTP*nMHz+(nMHz>>1)+999)/1000);
- if(tmp < 4)
- {
- tmp = 4;
- }
- p_pctl_timing->trtp = tmp&0xF;
- /*
- * RdToMiss=tRTP+tRP + tRCD - (BL/2 * tCK)
- */
- p_noc_timing->b.RdToMiss = ((tmp+cl+cl-(bl>>1))&0x3F);
- /*
- * tWR, 15ns
- */
- tmp = ((DDR3_tWR*nMHz+999)/1000);
- p_pctl_timing->twr = tmp&0x1F;
- if(tmp<9)
- tmp = tmp - 4;
- else
- tmp = tmp>>1;
- ddr_reg.ddrMR[0] = DDR3_BL8 | DDR3_CL(cl) | DDR3_WR(tmp);
-
- /*
- * tWTR, max(4 tCK,7.5ns)
- */
- tmp = ((DDR3_tWTR*nMHz+(nMHz>>1)+999)/1000);
- if(tmp < 4)
- {
- tmp = 4;
- }
- p_pctl_timing->twtr = tmp&0xF;
- p_noc_timing->b.WrToRd = ((tmp+cwl)&0x1F);
- /*
- * tXP, max(3 tCK, 7.5ns)(<933MHz)
- */
- tmp = ((DDR3_tXP*nMHz+(nMHz>>1)+999)/1000);
- if(tmp < 3)
- {
- tmp = 3;
- }
- p_pctl_timing->txp = tmp&0x7;
- /*
- * tXPDLL, max(10 tCK,24ns)
- */
- tmp = ((DDR3_tXPDLL*nMHz+999)/1000);
- if(tmp < 10)
- {
- tmp = 10;
- }
- p_pctl_timing->txpdll = tmp & 0x3F;
- /*
- * tZQCS, max(64 tCK, 80ns)
- */
- tmp = ((DDR3_tZQCS*nMHz+999)/1000);
- if(tmp < 64)
- {
- tmp = 64;
- }
- p_pctl_timing->tzqcs = tmp&0x7F;
- /*
- * tZQCSI,
- */
- p_pctl_timing->tzqcsi = DDR3_tZQCSI;
- /*
- * tDQS,
- */
- p_pctl_timing->tdqs = DDR3_tDQS;
- /*
- * tCKSRE, max(5 tCK, 10ns)
- */
- tmp = ((DDR3_tCKSRE*nMHz+999)/1000);
- if(tmp < 5)
- {
- tmp = 5;
- }
- p_pctl_timing->tcksre = tmp & 0x1F;
- /*
- * tCKSRX, max(5 tCK, 10ns)
- */
- p_pctl_timing->tcksrx = tmp & 0x1F;
- /*
- * tCKE, max(3 tCK,7.5ns)(400MHz) max(3 tCK,5.625ns)(533MHz)
- */
- if(nMHz>=533)
- {
- tmp = ((DDR3_tCKE_533MHz*nMHz+999)/1000);
- }
- else
- {
- tmp = ((DDR3_tCKE_400MHz*nMHz+(nMHz>>1)+999)/1000);
- }
- if(tmp < 3)
- {
- tmp = 3;
- }
- p_pctl_timing->tcke = tmp & 0x7;
- /*
- * tCKESR, =tCKE + 1tCK
- */
- p_pctl_timing->tckesr = (tmp+1)&0xF;
- /*
- * tMOD, max(12 tCK,15ns)
- */
- tmp = ((DDR3_tMOD*nMHz+999)/1000);
- if(tmp < 12)
- {
- tmp = 12;
- }
- p_pctl_timing->tmod = tmp&0x1F;
- /*
- * tRSTL, 100ns
- */
- p_pctl_timing->trstl = ((DDR3_tRSTL*nMHz+999)/1000)&0x7F;
- /*
- * tZQCL, max(256 tCK, 320ns)
- */
- tmp = ((DDR3_tZQCL*nMHz+999)/1000);
- if(tmp < 256)
- {
- tmp = 256;
- }
- p_pctl_timing->tzqcl = tmp&0x3FF;
- /*
- * tMRR, 0 tCK
- */
- p_pctl_timing->tmrr = 0;
- /*
- * tDPD, 0
- */
- p_pctl_timing->tdpd = 0;
-
- /**************************************************
- * NOC Timing
- **************************************************/
- p_noc_timing->b.BurstLen = ((bl>>1)&0x7);
- }
- else if(mem_type == DDR2)
- {
- #define DDR2_tREFI_7_8_us (78)
- #define DDR2_tMRD (2)
- #define DDR2_tRFC_256Mb (75)
- #define DDR2_tRFC_512Mb (105)
- #define DDR2_tRFC_1Gb (128)
- #define DDR2_tRFC_2Gb (195)
- #define DDR2_tRFC_4Gb (328)
- #define DDR2_tRAS (45)
- #define DDR2_tRTW (2) //register min valid value
- #define DDR2_tRRD (10)
- #define DDR2_tRTP (7)
- #define DDR2_tWR (15)
- #define DDR2_tWTR_LITTLE_200MHz (10)
- #define DDR2_tWTR_GREAT_200MHz (7)
- #define DDR2_tDQS (1)
- #define DDR2_tCKSRE (1)
- #define DDR2_tCKSRX (1)
- #define DDR2_tCKE (3)
- #define DDR2_tCKESR DDR2_tCKE
- #define DDR2_tMOD (12)
- #define DDR2_tFAW_333MHz (50)
- #define DDR2_tFAW_400MHz (45)
- #define DDR2_tDLLK (200)
-
- al = 0;
- bl = 4;
- if(nMHz <= 266)
- {
- cl = 4;
- }
- else if((nMHz > 266) && (nMHz <= 333))
- {
- cl = 5;
- }
- else if((nMHz > 333) && (nMHz <= 400))
- {
- cl = 6;
- }
- else // > 400MHz
- {
- cl = 7;
- }
- cwl = cl -1;
- if(nMHz <= DDR3_DDR2_ODT_DISABLE_FREQ)
- {
- ddr_reg.ddrMR[1] = DDR2_STR_REDUCE | DDR2_Rtt_Nom_DIS;
- }
- else
- {
- ddr_reg.ddrMR[1] = DDR2_STR_REDUCE | DDR2_Rtt_Nom_75;
- }
- ddr_reg.ddrMR[2] = 0;
- ddr_reg.ddrMR[3] = 0;
- /**************************************************
- * PCTL Timing
- **************************************************/
- /*
- * tREFI, average periodic refresh interval, 7.8us
- */
- p_pctl_timing->trefi = DDR2_tREFI_7_8_us;
- /*
- * tMRD, 2 tCK
- */
- p_pctl_timing->tmrd = DDR2_tMRD & 0x7;
- /*
- * tRFC, 75ns(256Mb) 105ns(512Mb) 127.5ns(1Gb) 195ns(2Gb) 327.5ns(4Gb)
- */
- if(ddr_capability_per_die <= 0x2000000) // 256Mb
- {
- tmp = DDR2_tRFC_256Mb;
- }
- else if(ddr_capability_per_die <= 0x4000000) // 512Mb
- {
- tmp = DDR2_tRFC_512Mb;
- }
- else if(ddr_capability_per_die <= 0x8000000) // 1Gb
- {
- tmp = DDR2_tRFC_1Gb;
- }
- else if(ddr_capability_per_die <= 0x10000000) // 2Gb
- {
- tmp = DDR2_tRFC_2Gb;
- }
- else // 4Gb
- {
- tmp = DDR2_tRFC_4Gb;
- }
- p_pctl_timing->trfc = (tmp*nMHz+999)/1000;
- /*
- * tXSR, max(tRFC+10,200 tCK)
- */
- tmp = (((tmp+10)*nMHz+999)/1000);
- if(tmp<200)
- {
- tmp = 200;
- }
- p_pctl_timing->texsr = tmp&0x3FF;
- /*
- * tRP=CL DDR2 8bank need to add 1 additional cycles for PREA
- */
- if(ddr_get_bank() == 8)
- {
- p_pctl_timing->trp = (1<<16) | cl;
- }
- else
- {
- p_pctl_timing->trp = cl;
- }
- /*
- * WrToMiss=WL*tCK + tWR + tRP + tRCD
- */
- p_noc_timing->b.WrToMiss = ((cwl+((DDR2_tWR*nMHz+999)/1000)+cl+cl)&0x3F);
- /*
- * tRAS, 45ns
- */
- tmp=((DDR2_tRAS*nMHz+999)/1000);
- p_pctl_timing->tras = (tmp&0x3F);
- /*
- * tRC=tRAS+tRP
- */
- p_pctl_timing->trc = ((tmp+cl)&0x3F);
- p_noc_timing->b.ActToAct = ((tmp+cl)&0x3F);
-
- p_pctl_timing->trtw = (cl+2-cwl);//DDR2_tRTW;
- p_noc_timing->b.RdToWr = ((cl+2-cwl)&0x1F);
- p_pctl_timing->tal = al;
- p_pctl_timing->tcl = cl;
- p_pctl_timing->tcwl = cwl;
- /*
- * tRCD=CL
- */
- p_pctl_timing->trcd = cl;
- /*
- * tRRD = 10ns(2KB page)
- *
- */
- p_pctl_timing->trrd = (((DDR2_tRRD*nMHz+999)/1000)&0xF);
- /*
- * tRTP, 7.5ns
- */
- tmp = ((DDR2_tRTP*nMHz+(nMHz>>1)+999)/1000);
- p_pctl_timing->trtp = tmp&0xF;
- /*
- * RdToMiss=tRTP+tRP + tRCD - (BL/2 * tCK)
- */
- p_noc_timing->b.RdToMiss = ((tmp+cl+cl-(bl>>1))&0x3F);
- /*
- * tWR, 15ns
- */
- tmp = ((DDR2_tWR*nMHz+999)/1000);
- p_pctl_timing->twr = tmp&0x1F;
- /*
- * tWTR, 10ns(200MHz) 7.5ns(>200MHz)
- */
- if(nMHz<=200)
- {
- tmp = ((DDR2_tWTR_LITTLE_200MHz*nMHz+999)/1000);
- }
- else
- {
- tmp = ((DDR2_tWTR_GREAT_200MHz*nMHz+(nMHz>>1)+999)/1000);
- }
- p_pctl_timing->twtr = tmp&0xF;
- p_noc_timing->b.WrToRd = ((tmp+cwl)&0x1F);
- /*
- * tXP, 6-AL(200MHz) 6-AL(266MHz) 7-AL(333MHz) 8-AL(400MHz) 10-AL(533MHz)
- */
- if(nMHz<=266)
- {
- tmp = 6-al;
- }
- else if(nMHz<=333)
- {
- tmp = 7-al;
- }
- else if(nMHz<=400)
- {
- tmp = 8-al;
- }
- else
- {
- tmp = 10-al;
- }
- p_pctl_timing->txp = tmp&0x7;
- /*
- * tXPDLL, =tXP
- */
- p_pctl_timing->txpdll = tmp & 0x3F;
- /*
- * tZQCS, 0
- */
- p_pctl_timing->tzqcs = 0;
- /*
- * tZQCSI,
- */
- p_pctl_timing->tzqcsi = 0;
- /*
- * tDQS,
- */
- p_pctl_timing->tdqs = DDR2_tDQS;
- /*
- * tCKSRE, 1 tCK
- */
- p_pctl_timing->tcksre = DDR2_tCKSRE & 0x1F;
- /*
- * tCKSRX, no such timing
- */
- p_pctl_timing->tcksrx = DDR2_tCKSRX & 0x1F;
- /*
- * tCKE, 3 tCK
- */
- p_pctl_timing->tcke = DDR2_tCKE & 0x7;
- /*
- * tCKESR, =tCKE
- */
- p_pctl_timing->tckesr = DDR2_tCKESR&0xF;
- /*
- * tMOD, 12ns
- */
- p_pctl_timing->tmod = ((DDR2_tMOD*nMHz+999)/1000)&0x1F;
- /*
- * tRSTL, 0
- */
- p_pctl_timing->trstl = 0;
- /*
- * tZQCL, 0
- */
- p_pctl_timing->tzqcl = 0;
- /*
- * tMRR, 0 tCK
- */
- p_pctl_timing->tmrr = 0;
- /*
- * tDPD, 0
- */
- p_pctl_timing->tdpd = 0;
-
- /**************************************************
- * NOC Timing
- **************************************************/
- p_noc_timing->b.BurstLen = ((bl>>1)&0x7);
- }
-
-out:
- return ret;
-}
-
-/*----------------------------------------------------------------------
-Name : uint32_t __sramlocalfunc ddr_update_timing(void)
-Desc : ¸üÐÂpctl phy Ïà¹Øtiming¼Ä´æÆ÷
-Params : void
-Return : 0 ³É¹¦
-Notes :
-----------------------------------------------------------------------*/
-uint32_t __sramlocalfunc ddr_update_timing(void)
-{
- PCTL_TIMING_T *p_pctl_timing = &(ddr_reg.pctl.pctl_timing);
- NOC_TIMING_T *p_noc_timing = &(ddr_reg.noc_timing);
-
- ddr_copy((uint32_t *)&(pDDR_Reg->TOGCNT1U), (uint32_t*)&(p_pctl_timing->togcnt1u), 34);
- pPHY_Reg->PHY_REG3 = (0x12 << 1) | (ddr2_ddr3_bl_8); //0x12Ϊ±£ÁôλµÄĬÈÏÖµ£¬ÒÔĬÈÏÖµ»Øд
- pPHY_Reg->PHY_REG4a = ((p_pctl_timing->tcl << 4) | (p_pctl_timing->tal));
- *(volatile uint32_t *)SysSrv_DdrTiming = p_noc_timing->d32;
- // Update PCTL BL
- if(mem_type == DDR3)
- {
- pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~(0x1|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | ddr2_ddr3_bl_8 | tfaw_cfg(5)|pd_exit_slow|pd_type(1);
- pDDR_Reg->DFITRDDATAEN = (pDDR_Reg->TAL + pDDR_Reg->TCL)-3; //trdata_en = rl-3
- pDDR_Reg->DFITPHYWRLAT = pDDR_Reg->TCWL-1;
- }
- else if(mem_type == DDR2)
- {
- pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~(0x1|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | ddr2_ddr3_bl_8 | tfaw_cfg(5)|pd_exit_fast|pd_type(1);
- }
- return 0;
-}
-
-/*----------------------------------------------------------------------
-Name : uint32_t __sramlocalfunc ddr_update_mr(void)
-Desc : ¸üпÅÁ£MR¼Ä´æÆ÷
-Params : void
-Return : void
-Notes :
-----------------------------------------------------------------------*/
-uint32_t __sramlocalfunc ddr_update_mr(void)
-{
- uint32_t cs;
-
- cs = (pGRF_Reg->GRF_OS_REG[1] >> DDR_RANK_COUNT) & 0x1;
- cs = cs + (1 << cs); //case 0:1rank cs=1; case 1:2rank cs =3;
- if(ddr_freq > DDR3_DDR2_DLL_DISABLE_FREQ)
- {
- if(ddr_dll_status == DDR3_DLL_DISABLE) // off -> on
- {
- ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr((ddr_reg.ddrMR[1]))); //DLL enable
- ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr(((ddr_reg.ddrMR[0]))| DDR3_DLL_RESET)); //DLL reset
- ddr_delayus(2); //at least 200 DDR cycle
- ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr((ddr_reg.ddrMR[0])));
- ddr_dll_status = DDR3_DLL_ENABLE;
- }
- else // on -> on
- {
- ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr((ddr_reg.ddrMR[1])));
- ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr((ddr_reg.ddrMR[0])));
- }
- }
- else
- {
- ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr(((ddr_reg.ddrMR[1])) | DDR3_DLL_DISABLE)); //DLL disable
- ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr((ddr_reg.ddrMR[0])));
- ddr_dll_status = DDR3_DLL_DISABLE;
- }
- ddr_send_command(cs, MRS_cmd, bank_addr(0x2) | cmd_addr((ddr_reg.ddrMR[2])));
-
- return 0;
-}
-
-/*----------------------------------------------------------------------
-Name : void __sramlocalfunc ddr_update_odt(void)
-Desc : update PHY odt & PHY driver impedance
-Params : void
-Return : void
-Notes :
-----------------------------------------------------------------------*/
-void __sramlocalfunc ddr_update_odt(void)
-{
- uint32_t tmp;
-
- //adjust DRV and ODT
- if(ddr_freq <= PHY_ODT_DISABLE_FREQ)
- {
- pPHY_Reg->PHY_REG27 = PHY_RTT_DISABLE; //dynamic RTT disable, Left 8bit ODT
- pPHY_Reg->PHY_REG28 = PHY_RTT_DISABLE; //Right 8bit ODT
- pPHY_Reg->PHY_REG0e4 = (0x0E & 0xc)|0x1;//off DQS ODT bit[1:0]=2'b01
- pPHY_Reg->PHY_REG124 = (0x0E & 0xc)|0x1;//off DQS ODT bit[1:0]=2'b01
- }
-#if defined (CONFIG_ARCH_RK3026) //RK3028A RK3026
- else
- {
- pPHY_Reg->PHY_REG27 = ((PHY_RTT_215ohm<<4) | PHY_RTT_215ohm);
- pPHY_Reg->PHY_REG28 = ((PHY_RTT_215ohm<<4) | PHY_RTT_215ohm);
- pPHY_Reg->PHY_REG0e4 = 0x0E; //on DQS ODT default:0x0E
- pPHY_Reg->PHY_REG124 = 0x0E; //on DQS ODT default:0x0E
- }
- tmp = ((PHY_RON_45ohm<<4) | PHY_RON_45ohm);
-#else //RK2928 R2926
- else
- {
- pPHY_Reg->PHY_REG27 = ((PHY_RTT_212O<<3) | PHY_RTT_212O);
- pPHY_Reg->PHY_REG28 = ((PHY_RTT_212O<<3) | PHY_RTT_212O);
- pPHY_Reg->PHY_REG0e4 = 0x0E; //on DQS ODT default:0x0E
- pPHY_Reg->PHY_REG124 = 0x0E; //on DQS ODT default:0x0E
- }
- tmp = ((PHY_RON_46O<<3) | PHY_RON_46O);
-#endif
-
- pPHY_Reg->PHY_REG16 = tmp; //CMD driver strength
- pPHY_Reg->PHY_REG22 = tmp; //CK driver strength
- pPHY_Reg->PHY_REG25 = tmp; //Left 8bit DQ driver strength
- pPHY_Reg->PHY_REG26 = tmp; //Right 8bit DQ driver strength
- dsb();
-}
-
-/*----------------------------------------------------------------------
-Name : __sramfunc void ddr_adjust_config(uint32_t dram_type)
-Desc :
-Params : dram_type ->¿ÅÁ£ÀàÐÍ
-Return : void
-Notes :
-----------------------------------------------------------------------*/
-__sramfunc void ddr_adjust_config(uint32_t dram_type)
-{
-// uint32 value;
- unsigned long save_sp;
- uint32 i;
- volatile uint32 n;
- volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
-
- //get data training address before idle port
-// value = ddr_get_datatraing_addr(); //Inno PHY ²»ÐèÒªtraining address
-
- /** 1. Make sure there is no host access */
- flush_cache_all();
- outer_flush_all();
- flush_tlb_all();
- DDR_SAVE_SP(save_sp);
-
- for(i=0;i<2;i++) //8KB SRAM
- {
- n=temp[1024*i];
- barrier();
- }
- n= pDDR_Reg->SCFG.d32;
- n= pPHY_Reg->PHY_REG1;
- n= pCRU_Reg->CRU_PLL_CON[0][0];
- n= *(volatile uint32_t *)SysSrv_DdrConf;
- dsb();
-
- //enter config state
- ddr_move_to_Config_state();
-// pDDR_Reg->DFIODTCFG = ((1<<3) | (1<<11)); //loaderÖЩÁ˳õʼ»¯
- //set auto power down idle
- pDDR_Reg->MCFG=(pDDR_Reg->MCFG&0xffff00ff)|(PD_IDLE<<8);
-
- //enable the hardware low-power interface
- pDDR_Reg->SCFG.b.hw_low_power_en = 1;
-
- ddr_update_odt();
-
- //enter access state
- ddr_move_to_Access_state();
-
- DDR_RESTORE_SP(save_sp);
-}
-
-#if defined (CONFIG_ARCH_RK3026)
-void __sramlocalfunc idle_port(void)
-{
- int i;
- uint32 clk_gate[10];
-
- //save clock gate status
- for(i=0;i<10;i++)
- {
- clk_gate[i]=pCRU_Reg->CRU_CLKGATE_CON[i];
- }
- //enable all clock gate for request idle
- for(i=0;i<10;i++)
- {
- pCRU_Reg->CRU_CLKGATE_CON[i]=0xffff0000;
- }
-
- pGRF_Reg->GRF_SOC_CON[2] = (1 << (16+peri_pwr_idlereq))+(1 << peri_pwr_idlereq); //peri bit 12
- dsb();
- while( (pGRF_Reg->GRF_SOC_STATUS0 & peri_pwr_idle) == 0);// bit 23
-
- pGRF_Reg->GRF_SOC_CON[2] = (1 << (16+vio_pwr_idlereq))+(1 << vio_pwr_idlereq); //vio
- dsb();
- while( (pGRF_Reg->GRF_SOC_STATUS0 & vio_pwr_idle) == 0);
-
- pGRF_Reg->GRF_SOC_CON[2] = (1 << (16+vpu_pwr_idlereq))+(1 << vpu_pwr_idlereq); //vpu
- dsb();
- while( (pGRF_Reg->GRF_SOC_STATUS0 & vpu_pwr_idle) == 0);
-
- pGRF_Reg->GRF_SOC_CON[2] = (1 << (16+gpu_pwr_idlereq))+(1 << gpu_pwr_idlereq); //gpu
- dsb();
- while( (pGRF_Reg->GRF_SOC_STATUS0 & gpu_pwr_idle) == 0);
-
- //resume clock gate status
- for(i=0;i<10;i++)
- pCRU_Reg->CRU_CLKGATE_CON[i]= (clk_gate[i] | 0xffff0000);
-}
-
-
-void __sramlocalfunc deidle_port(void)
-{
- int i;
- uint32 clk_gate[10];
-
- //save clock gate status
- for(i=0;i<10;i++)
- {
- clk_gate[i]=pCRU_Reg->CRU_CLKGATE_CON[i];
- }
- //enable all clock gate for request idle
- for(i=0;i<10;i++)
- {
- pCRU_Reg->CRU_CLKGATE_CON[i]=0xffff0000;
- }
-
- pGRF_Reg->GRF_SOC_CON[2] = (1 << (16+peri_pwr_idlereq))+(0 << peri_pwr_idlereq); //peri bit 12
- dsb();
- while( (pGRF_Reg->GRF_SOC_STATUS0 & peri_pwr_idle) != 0);
-
- pGRF_Reg->GRF_SOC_CON[2] = (1 << (16+vio_pwr_idlereq))+(0 << vio_pwr_idlereq); //vio
- dsb();
- while( (pGRF_Reg->GRF_SOC_STATUS0 & vio_pwr_idle) != 0);
-
- pGRF_Reg->GRF_SOC_CON[2] = (1 << (16+vpu_pwr_idlereq))+(0 << vpu_pwr_idlereq); //vpu
- dsb();
- while( (pGRF_Reg->GRF_SOC_STATUS0 & vpu_pwr_idle) != 0);
-
- pGRF_Reg->GRF_SOC_CON[2] = (1 << (16+gpu_pwr_idlereq))+(0 << gpu_pwr_idlereq); //gpu
- dsb();
- while( (pGRF_Reg->GRF_SOC_STATUS0 & gpu_pwr_idle) != 0);
-
- //resume clock gate status
- for(i=0;i<10;i++)
- pCRU_Reg->CRU_CLKGATE_CON[i]= (clk_gate[i] | 0xffff0000);
-
-}
-#endif
-
-
-/*----------------------------------------------------------------------
-Name : void __sramlocalfunc ddr_selfrefresh_enter(uint32 nMHz)
-Desc : ½øÈë×ÔË¢ÐÂ
-Params : nMHz ->ddrƵÂÊ
-Return : void
-Notes :
-----------------------------------------------------------------------*/
-void __sramlocalfunc ddr_selfrefresh_enter(uint32 nMHz)
-{
- ddr_move_to_Config_state();
- ddr_move_to_Lowpower_state();
- pPHY_Reg->PHY_REG264 &= ~(1<<1);
- pPHY_Reg->PHY_REG1 = (pPHY_Reg->PHY_REG1 & (~(0x3<<2))); //phy soft reset
- dsb();
- pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1<<2)<<16) | (1<<2); //disable DDR PHY clock
- ddr_delayus(1);
-}
-
-uint32 dtt_buffer[8];
-
-/*----------------------------------------------------------------------
-Name : void ddr_dtt_check(void)
-Desc : data training check
-Params : void
-Return : void
-Notes :
-----------------------------------------------------------------------*/
-void ddr_dtt_check(void)
-{
- uint32 i;
- for(i=0;i<8;i++)
- {
- dtt_buffer[i] = copy_data[i];
- }
- dsb();
- flush_cache_all();
- outer_flush_all();
- for(i=0;i<8;i++)
- {
- if(dtt_buffer[i] != copy_data[i])
- {
- sram_printascii("DTT failed!\n");
- break;
- }
- dtt_buffer[i] = 0;
- }
-
-}
-
-/*----------------------------------------------------------------------
-Name : void __sramlocalfunc ddr_selfrefresh_exit(void)
-Desc : Í˳ö×ÔË¢ÐÂ
-Params : void
-Return : void
-Notes :
-----------------------------------------------------------------------*/
-void __sramlocalfunc ddr_selfrefresh_exit(void)
-{
- pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1<<2)<<16) | (0<<2); //enable DDR PHY clock
- dsb();
- ddr_delayus(1);
- pPHY_Reg->PHY_REG1 = (pPHY_Reg->PHY_REG1 | (0x3 << 2)); //phy soft de-reset
- pPHY_Reg->PHY_REG264 |= (1<<1);
- dsb();
- ddr_move_to_Config_state();
- ddr_data_training();
- ddr_move_to_Access_state();
- ddr_dtt_check();
-}
-
-/*----------------------------------------------------------------------
-Name : void __sramlocalfunc ddr_change_freq_in(uint32 freq_slew)
-Desc : ÉèÖÃddr pllÇ°µÄtiming¼°mr²ÎÊýµ÷Õû
-Params : freq_slew :±äƵбÂÊ 1Éýƽ 0½µÆµ
-Return : void
-Notes :
-----------------------------------------------------------------------*/
-void __sramlocalfunc ddr_change_freq_in(uint32 freq_slew)
-{
- uint32 value_100n, value_1u;
-
- if(freq_slew == 1)
- {
- value_100n = ddr_reg.pctl.pctl_timing.togcnt100n;
- value_1u = ddr_reg.pctl.pctl_timing.togcnt1u;
- ddr_reg.pctl.pctl_timing.togcnt1u = pDDR_Reg->TOGCNT1U;
- ddr_reg.pctl.pctl_timing.togcnt100n = pDDR_Reg->TOGCNT100N;
- ddr_update_timing();
- ddr_update_mr();
- ddr_reg.pctl.pctl_timing.togcnt100n = value_100n;
- ddr_reg.pctl.pctl_timing.togcnt1u = value_1u;
- }
- else
- {
- pDDR_Reg->TOGCNT100N = ddr_reg.pctl.pctl_timing.togcnt100n;
- pDDR_Reg->TOGCNT1U = ddr_reg.pctl.pctl_timing.togcnt1u;
- }
-
- pDDR_Reg->TZQCSI = 0;
-
-}
-
-/*----------------------------------------------------------------------
-Name : void __sramlocalfunc ddr_change_freq_out(uint32 freq_slew)
-Desc : ÉèÖÃddr pllºóµÄtiming¼°mr²ÎÊýµ÷Õû
-Params : freq_slew :±äƵбÂÊ 1Éýƽ 0½µÆµ
-Return : void
-Notes :
-----------------------------------------------------------------------*/
-void __sramlocalfunc ddr_change_freq_out(uint32 freq_slew)
-{
- if(freq_slew == 1)
- {
- pDDR_Reg->TOGCNT100N = ddr_reg.pctl.pctl_timing.togcnt100n;
- pDDR_Reg->TOGCNT1U = ddr_reg.pctl.pctl_timing.togcnt1u;
- pDDR_Reg->TZQCSI = ddr_reg.pctl.pctl_timing.tzqcsi;
- }
- else
- {
- ddr_update_timing();
- ddr_update_mr();
- }
- ddr_data_training();
-}
-
-static uint32 save_sp;
-/*----------------------------------------------------------------------
-Name : uint32_t __sramfunc ddr_change_freq(uint32_t nMHz)
-Desc : ddr±äƵ
-Params : nMHz -> ±äƵµÄƵÂÊÖµ
-Return : ƵÂÊÖµ
-Notes :
-----------------------------------------------------------------------*/
-uint32_t __sramfunc ddr_change_freq_sram(uint32_t nMHz, struct ddr_freq_t ddr_freq_t)
-{
- uint32_t ret;
- u32 i;
- volatile u32 n;
- unsigned long flags;
- volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
- uint32_t regvalue0 = pCRU_Reg->CRU_PLL_CON[0][0];
- uint32_t regvalue1 = pCRU_Reg->CRU_PLL_CON[0][1];
- uint32_t freq;
- uint32 freq_slew;
-
- // freq = (fin*fbdiv/(refdiv * postdiv1 * postdiv2))
- if((pCRU_Reg->CRU_MODE_CON & 1) == 1) // CPLL Normal mode
- {
- freq = 24*(regvalue0&0xfff)
- /((regvalue1&0x3f)*((regvalue0>>12)&0x7)*((regvalue1>>6)&0x7));
- }
- else
- {
- freq = 24;
- }
- loops_per_us = LPJ_100MHZ*freq / 1000000;
-
- ret=ddr_set_pll(nMHz,0);
- if(ret == ddr_freq)
- {
- goto out;
- }
- else
- {
- freq_slew = (ret>ddr_freq)? 1 : -1;
- }
- ddr_get_parameter(ret);
- /** 1. Make sure there is no host access */
- local_irq_save(flags);
- local_fiq_disable();
- flush_cache_all();
- outer_flush_all();
- flush_tlb_all();
- DDR_SAVE_SP(save_sp);
- for(i=0;i<2;i++) //8KB SRAM
- {
- n=temp[1024*i];
- barrier();
- }
- n= pDDR_Reg->SCFG.d32;
- n= pPHY_Reg->PHY_REG1;
- n= pCRU_Reg->CRU_PLL_CON[0][0];
- n= *(volatile uint32_t *)SysSrv_DdrConf;
- n= pGRF_Reg->GRF_SOC_STATUS0;
- dsb();
-
-#if defined (CONFIG_ARCH_RK3026)
-#if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
- n = ddr_freq_t.screen_ft_us;
- n = ddr_freq_t.t0;
- dsb();
-
- if(ddr_freq_t.screen_ft_us > 0){
-
- ddr_freq_t.t1 = cpu_clock(0);
- ddr_freq_t.t2 = (u32)(ddr_freq_t.t1 - ddr_freq_t.t0); //ns
-
-
- if( (ddr_freq_t.t2 > ddr_freq_t.screen_ft_us*1000) && (ddr_freq_t.screen_ft_us != 0xfefefefe)){
-
- DDR_RESTORE_SP(save_sp);
- local_fiq_enable();
- local_irq_restore(flags);
- return 0;
- }else{
- rk_fb_poll_wait_frame_complete();
- }
- }
-#endif
-
- idle_port();
-#endif
- ddr_move_to_Config_state();
- ddr_freq = ret;
- ddr_change_freq_in(freq_slew);
- ddr_move_to_Lowpower_state();
- pPHY_Reg->PHY_REG264 &= ~(1<<1);
- pPHY_Reg->PHY_REG1 = (pPHY_Reg->PHY_REG1 & (~(0x3<<2))); //phy soft reset
- dsb();
- /** 3. change frequence */
- ddr_set_pll(ret,1);
- ddr_set_dll_bypass(ddr_freq); //set phy dll mode;
- pPHY_Reg->PHY_REG1 = (pPHY_Reg->PHY_REG1 | (0x3 << 2)); //phy soft de-reset
- pPHY_Reg->PHY_REG264 |= (1<<1);
- dsb();
- ddr_update_odt();
- ddr_move_to_Config_state();
- ddr_change_freq_out(freq_slew);
- ddr_move_to_Access_state();
-
-#if defined (CONFIG_ARCH_RK3026)
- deidle_port();
-#endif
-
- /** 5. Issues a Mode Exit command */
- DDR_RESTORE_SP(save_sp);
- ddr_dtt_check();
- local_fiq_enable();
- local_irq_restore(flags);
-// clk_set_rate(clk_get(NULL, "ddr_pll"), 0);
-out:
- return ret;
-}
-
-uint32_t ddr_change_freq(uint32_t nMHz)
-{
- struct ddr_freq_t ddr_freq_t;
- ddr_freq_t.screen_ft_us = 0;
-
- return ddr_change_freq_sram(nMHz,ddr_freq_t);
-}
-
-
-EXPORT_SYMBOL(ddr_change_freq);
-
-/*----------------------------------------------------------------------
-Name : void ddr_set_auto_self_refresh(bool en)
-Desc : ÉèÖýøÈë selfrefesh µÄÖÜÆÚÊý
-Params : en -> ʹÄÜauto selfrefresh
-Return : ƵÂÊÖµ
-Notes : ÖÜÆÚÊýΪ1*32 cycle
-----------------------------------------------------------------------*/
-void ddr_set_auto_self_refresh(bool en)
-{
- //set auto self-refresh idle
- ddr_sr_idle = en ? SR_IDLE : 0;
-}
-
-EXPORT_SYMBOL(ddr_set_auto_self_refresh);
-
-/*----------------------------------------------------------------------
-Name : void __sramfunc ddr_suspend(void)
-Desc : ½øÈëddr suspend
-Params : void
-Return : void
-Notes :
-----------------------------------------------------------------------*/
-void __sramfunc ddr_suspend(void)
-{
- u32 i;
- volatile u32 n;
- volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
- /** 1. Make sure there is no host access */
- flush_cache_all();
- outer_flush_all();
-// flush_tlb_all();
-
- for(i=0;i<2;i++) //sram size = 8KB
- {
- n=temp[1024*i];
- barrier();
- }
- n= pDDR_Reg->SCFG.d32;
- n= pPHY_Reg->PHY_REG1;
- n= pCRU_Reg->CRU_PLL_CON[0][0];
- n= *(volatile uint32_t *)SysSrv_DdrConf;
- n= pGRF_Reg->GRF_SOC_STATUS0;
- dsb();
- ddr_selfrefresh_enter(0);
- pCRU_Reg->CRU_MODE_CON = (0x1<<((1*4) + 16)) | (0x0<<(1*4)); //PLL slow-mode
- dsb();
- ddr_delayus(1);
- pCRU_Reg->CRU_PLL_CON[1][1] = ((0x1<<13)<<16) | (0x1<<13); //PLL power-down
- dsb();
- ddr_delayus(1);
-
-}
-EXPORT_SYMBOL(ddr_suspend);
-
-/*----------------------------------------------------------------------
-Name : void __sramfunc ddr_resume(void)
-Desc : ddr resume
-Params : void
-Return : void
-Notes :
-----------------------------------------------------------------------*/
-void __sramfunc ddr_resume(void)
-{
- int delay=1000;
-
- pCRU_Reg->CRU_PLL_CON[1][1] = ((0x1<<13)<<16) | (0x0<<13); //PLL no power-down
- dsb();
- while (delay > 0)
- {
- ddr_delayus(1);
- if (pCRU_Reg->CRU_PLL_CON[1][1] & (0x1<<10))
- break;
- delay--;
- }
-
- pCRU_Reg->CRU_MODE_CON = (0x1<<((1*4) + 16)) | (0x1<<(1*4)); //PLL normal
- dsb();
-
- ddr_selfrefresh_exit();
-}
-EXPORT_SYMBOL(ddr_resume);
-
-/*----------------------------------------------------------------------
-Name : uint32 ddr_get_cap(void)
-Desc : »ñÈ¡ÈÝÁ¿£¬·µ»Ø×Ö½ÚÊý
-Params : void
-Return : ¿ÅÁ£ÈÝÁ¿
-Notes :
-----------------------------------------------------------------------*/
-uint32 ddr_get_cap(void)
-{
- uint32 value;
- uint32 cs, bank, row, col;
- value = pGRF_Reg->GRF_OS_REG[1];
- bank = (((value >> DDR_BANK_COUNT) & 0x1)? 2:3);
- row = (13+((value >> DDR_ROW_COUNT) & 0x3));
- col = (9 + ((value >> DDR_COL_COUNT)&0x3));
- cs = (1 + ((value >> DDR_RANK_COUNT)&0x1));
- return ((1 << (row + col + bank + 1))*cs);
-}
-EXPORT_SYMBOL(ddr_get_cap);
-
-/*----------------------------------------------------------------------
-Name : void ddr_reg_save(void)
-Desc : ±£´æ¿ØÖÆÆ÷¼Ä´æÆ÷Öµ
-Params : void
-Return : void
-Notes :
-----------------------------------------------------------------------*/
-void ddr_reg_save(void)
-{
- //PCTLR
- ddr_reg.pctl.SCFG = pDDR_Reg->SCFG.d32;
- ddr_reg.pctl.CMDTSTATEN = pDDR_Reg->CMDTSTATEN;
- ddr_reg.pctl.MCFG1 = pDDR_Reg->MCFG1;
- ddr_reg.pctl.MCFG = pDDR_Reg->MCFG;
- ddr_reg.pctl.pctl_timing.ddrFreq = ddr_freq;
- ddr_reg.pctl.DFITCTRLDELAY = pDDR_Reg->DFITCTRLDELAY;
- ddr_reg.pctl.DFIODTCFG = pDDR_Reg->DFIODTCFG;
- ddr_reg.pctl.DFIODTCFG1 = pDDR_Reg->DFIODTCFG1;
- ddr_reg.pctl.DFIODTRANKMAP = pDDR_Reg->DFIODTRANKMAP;
- ddr_reg.pctl.DFITPHYWRDATA = pDDR_Reg->DFITPHYWRDATA;
- ddr_reg.pctl.DFITPHYWRLAT = pDDR_Reg->DFITPHYWRLAT;
- ddr_reg.pctl.DFITRDDATAEN = pDDR_Reg->DFITRDDATAEN;
- ddr_reg.pctl.DFITPHYRDLAT = pDDR_Reg->DFITPHYRDLAT;
- ddr_reg.pctl.DFITPHYUPDTYPE0 = pDDR_Reg->DFITPHYUPDTYPE0;
- ddr_reg.pctl.DFITPHYUPDTYPE1 = pDDR_Reg->DFITPHYUPDTYPE1;
- ddr_reg.pctl.DFITPHYUPDTYPE2 = pDDR_Reg->DFITPHYUPDTYPE2;
- ddr_reg.pctl.DFITPHYUPDTYPE3 = pDDR_Reg->DFITPHYUPDTYPE3;
- ddr_reg.pctl.DFITCTRLUPDMIN = pDDR_Reg->DFITCTRLUPDMIN;
- ddr_reg.pctl.DFITCTRLUPDMAX = pDDR_Reg->DFITCTRLUPDMAX;
- ddr_reg.pctl.DFITCTRLUPDDLY = pDDR_Reg->DFITCTRLUPDDLY;
-
- ddr_reg.pctl.DFIUPDCFG = pDDR_Reg->DFIUPDCFG;
- ddr_reg.pctl.DFITREFMSKI = pDDR_Reg->DFITREFMSKI;
- ddr_reg.pctl.DFITCTRLUPDI = pDDR_Reg->DFITCTRLUPDI;
- ddr_reg.pctl.DFISTCFG0 = pDDR_Reg->DFISTCFG0;
- ddr_reg.pctl.DFISTCFG1 = pDDR_Reg->DFISTCFG1;
- ddr_reg.pctl.DFITDRAMCLKEN = pDDR_Reg->DFITDRAMCLKEN;
- ddr_reg.pctl.DFITDRAMCLKDIS = pDDR_Reg->DFITDRAMCLKDIS;
- ddr_reg.pctl.DFISTCFG2 = pDDR_Reg->DFISTCFG2;
- ddr_reg.pctl.DFILPCFG0 = pDDR_Reg->DFILPCFG0;
-
- //NOC
- ddr_reg.DdrConf = *(volatile uint32_t *)SysSrv_DdrConf;
- ddr_reg.DdrMode = *(volatile uint32_t *)SysSrv_DdrMode;
- ddr_reg.ReadLatency = *(volatile uint32_t *)SysSrv_ReadLatency;
-}
-EXPORT_SYMBOL(ddr_reg_save);
-/*
-__attribute__((aligned(4))) __sramdata uint32 ddr_reg_resume[] =
-{
-#include "ddr_reg_resume.inc"
-};
-*/
-
-/*----------------------------------------------------------------------
-Name : int ddr_init(uint32_t dram_speed_bin, uint32_t freq)
-Desc : ddr ³õʼ»¯º¯Êý
-Params : dram_speed_bin ->ddr¿ÅÁ£ÀàÐÍ
- freq ->ƵÂÊÖµ
-Return : 0 ³É¹¦
-Notes :
-----------------------------------------------------------------------*/
-int ddr_init(uint32_t dram_speed_bin, uint32_t freq)
-{
- volatile uint32_t value = 0;
- uint32_t cs,die=1;
- uint32_t calStatusLeft, calStatusRight;
-
- ddr_print("version 1.00 20130731 \n");
- cs = (1 << (((pGRF_Reg->GRF_OS_REG[1]) >> DDR_RANK_COUNT)&0x1)); //case 0:1rank ; case 1:2rank ;
- mem_type = ((pGRF_Reg->GRF_OS_REG[1] >> 13) &0x7);
- ddr_speed_bin = dram_speed_bin;
- ddr_freq = 0;
- ddr_sr_idle = 0;
- ddr_dll_status = DDR3_DLL_DISABLE;
-
- switch(mem_type)
- {
- case DDR3:
- die = 1;
- break;
- case DDR2:
- die = 1;
- break;
- default:
- ddr_print("ddr type error type=%d\n",mem_type);
- break;
- }
-
-
- //get capability per chip, not total size, used for calculate tRFC
- ddr_capability_per_die = ddr_get_cap()/(cs * die);
- ddr_print("%d CS, ROW=%d, Bank=%d, COL=%d, Total Capability=%dMB\n",
- cs, \
- ddr_get_row(), \
- (0x1<<(ddr_get_bank())), \
- ddr_get_col(), \
- (ddr_get_cap()>>20));
- ddr_adjust_config(mem_type);
- if(freq != 0)
- value=ddr_change_freq(freq);
- else
- value=ddr_change_freq(clk_get_rate(clk_get(NULL, "ddr"))/1000000);
-
- clk_set_rate(clk_get(NULL, "ddr"), 0);
- ddr_print("init success!!! freq=%dMHz\n", clk_get_rate(clk_get(NULL, "ddr"))/1000000);
-
- calStatusLeft = pPHY_Reg->PHY_REG60;
- calStatusRight = pPHY_Reg->PHY_REG61;
-
-
- ddr_print("left channel:Dllsel=%x, Ophsel=%x, Cycsel=%x\n",\
- (calStatusRight >> 5) & 0x07,\
- (calStatusRight >> 3) & 0x03,\
- calStatusRight & 0x07);
- ddr_print("right channel:Dllsel=%x, Ophsel=%x, Cycsel=%x\n",\
- (calStatusLeft >> 5) & 0x07,\
- (calStatusLeft >> 3) & 0x03,\
- calStatusLeft & 0x07);
-
- ddr_print("DRV Pull-Up=0x%x, DRV Pull-Dwn=0x%x\n", (pPHY_Reg->PHY_REG25>>3)&0x7, pPHY_Reg->PHY_REG25&0x7);
- ddr_print("ODT Pull-Up=0x%x, ODT Pull-Dwn=0x%x\n", (pPHY_Reg->PHY_REG27>>3)&0x7, pPHY_Reg->PHY_REG27&0x7);
- return 0;
-}
-
-EXPORT_SYMBOL(ddr_init);
-
+++ /dev/null
-/* arch/arm/mach-rk2928/devices.c
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/fs.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#ifdef CONFIG_USB_ANDROID
-#include <linux/usb/android_composite.h>
-#endif
-#include <linux/delay.h>
-#include <linux/dma-mapping.h>
-#include <asm/pmu.h>
-#include <mach/irqs.h>
-#include <mach/board.h>
-#include <mach/dma-pl330.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <mach/dvfs.h>
-#include <mach/debug_uart.h>
-#include <plat/rk_fiq_debugger.h>
-#include <linux/regulator/consumer.h>
-
-#ifdef CONFIG_ADC_RK30
-static int rk30_get_base_volt(void)
-{
- int volt;
- struct regulator *logic = dvfs_get_regulator("vdd_core");
-
- if(unlikely(IS_ERR_OR_NULL(logic))){
- printk("%s: fail to get logic voltage\n", __func__);
- return -EINVAL;
- }
- volt = regulator_get_voltage(logic)/1000;
-
- return volt;
-}
-
-static struct adc_platform_data rk30_adc_pdata = {
- .ref_volt = 3300, //3300mV
-#if defined(CONFIG_ARCH_RK3026)
- .base_chn = 6,
-#else
- .base_chn = 3,
-#endif
- .get_base_volt = &rk30_get_base_volt,
-};
-
-static struct resource rk30_adc_resource[] = {
- {
- .start = IRQ_SARADC,
- .end = IRQ_SARADC,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK2928_SARADC_PHYS,
- .end = RK2928_SARADC_PHYS + RK2928_SARADC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-struct platform_device device_adc = {
- .name = "rk30-adc",
- .id = -1,
- .num_resources = ARRAY_SIZE(rk30_adc_resource),
- .resource = rk30_adc_resource,
- .dev = {
- .platform_data = &rk30_adc_pdata,
- },
-};
-#endif
-
-static u64 dma_dmamask = DMA_BIT_MASK(32);
-
-static struct resource resource_dmac[] = {
- [0] = {
- .start = RK2928_DMAC_PHYS,
- .end = RK2928_DMAC_PHYS + RK2928_DMAC_SIZE -1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_DMAC_0,
- .end = IRQ_DMAC_1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct rk29_pl330_platdata dmac_pdata = {
- .peri = {
- [0] = DMACH_I2S0_8CH_TX,
- [1] = DMACH_I2S0_8CH_RX,
- [2] = DMACH_UART0_TX,
- [3] = DMACH_UART0_RX,
- [4] = DMACH_UART1_TX,
- [5] = DMACH_UART1_RX,
- [6] = DMACH_UART2_TX,
- [7] = DMACH_UART2_RX,
- [8] = DMACH_SPI0_TX,
- [9] = DMACH_SPI0_RX,
- [10] = DMACH_SDMMC,
- [11] = DMACH_SDIO,
- [12] = DMACH_EMMC,
- [13] = DMACH_DMAC1_MEMTOMEM,
- [14] = DMACH_MAX,
- [15] = DMACH_MAX,
- [16] = DMACH_MAX,
- [17] = DMACH_MAX,
- [18] = DMACH_MAX,
- [19] = DMACH_MAX,
- [20] = DMACH_MAX,
- [21] = DMACH_MAX,
- [22] = DMACH_MAX,
- [23] = DMACH_MAX,
- [24] = DMACH_MAX,
- [25] = DMACH_MAX,
- [26] = DMACH_MAX,
- [27] = DMACH_MAX,
- [28] = DMACH_MAX,
- [29] = DMACH_MAX,
- [30] = DMACH_MAX,
- [31] = DMACH_MAX,
- },
-};
-
-static struct platform_device device_dmac = {
- .name = "rk29-pl330",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_dmac),
- .resource = resource_dmac,
- .dev = {
- .dma_mask = &dma_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &dmac_pdata,
- },
-};
-
-static struct platform_device *rk2928_dmacs[] __initdata = {
- &device_dmac,
-};
-
-static void __init rk2928_init_dma(void)
-{
- platform_add_devices(rk2928_dmacs, ARRAY_SIZE(rk2928_dmacs));
-}
-
-#ifdef CONFIG_UART0_RK29
-static struct resource resources_uart0[] = {
- {
- .start = IRQ_UART0,
- .end = IRQ_UART0,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK2928_UART0_PHYS,
- .end = RK2928_UART0_PHYS + RK2928_UART0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_uart0 = {
- .name = "rk_serial",
- .id = 0,
- .num_resources = ARRAY_SIZE(resources_uart0),
- .resource = resources_uart0,
-};
-#endif
-
-#ifdef CONFIG_UART1_RK29
-static struct resource resources_uart1[] = {
- {
- .start = IRQ_UART1,
- .end = IRQ_UART1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK2928_UART1_PHYS,
- .end = RK2928_UART1_PHYS + RK2928_UART1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_uart1 = {
- .name = "rk_serial",
- .id = 1,
- .num_resources = ARRAY_SIZE(resources_uart1),
- .resource = resources_uart1,
-};
-#endif
-
-#ifdef CONFIG_UART2_RK29
-static struct resource resources_uart2[] = {
- {
- .start = IRQ_UART2,
- .end = IRQ_UART2,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK2928_UART2_PHYS,
- .end = RK2928_UART2_PHYS + RK2928_UART2_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_uart2 = {
- .name = "rk_serial",
- .id = 2,
- .num_resources = ARRAY_SIZE(resources_uart2),
- .resource = resources_uart2,
-};
-#endif
-
-static void __init rk2928_init_uart(void)
-{
-#ifdef CONFIG_UART0_RK29
- platform_device_register(&device_uart0);
-#endif
-#ifdef CONFIG_UART1_RK29
- platform_device_register(&device_uart1);
-#endif
-#ifdef CONFIG_UART2_RK29
- platform_device_register(&device_uart2);
-#endif
-}
-
-#ifdef CONFIG_I2C0_CONTROLLER_RK29
-#define I2C0_ADAP_TYPE I2C_RK29_ADAP
-#define I2C0_START RK2928_I2C0_PHYS
-#define I2C0_END RK2928_I2C0_PHYS + RK2928_I2C0_SIZE - 1
-#endif
-#ifdef CONFIG_I2C0_CONTROLLER_RK30
-#define I2C0_ADAP_TYPE I2C_RK30_ADAP
-#define I2C0_START RK2928_RKI2C0_PHYS
-#define I2C0_END RK2928_RKI2C0_PHYS + RK2928_RKI2C0_SIZE - 1
-#endif
-
-#ifdef CONFIG_I2C1_CONTROLLER_RK29
-#define I2C1_ADAP_TYPE I2C_RK29_ADAP
-#define I2C1_START RK2928_I2C1_PHYS
-#define I2C1_END RK2928_I2C1_PHYS + RK2928_I2C1_SIZE - 1
-#endif
-#ifdef CONFIG_I2C1_CONTROLLER_RK30
-#define I2C1_ADAP_TYPE I2C_RK30_ADAP
-#define I2C1_START RK2928_RKI2C1_PHYS
-#define I2C1_END RK2928_RKI2C1_PHYS + RK2928_RKI2C1_SIZE - 1
-#endif
-
-#ifdef CONFIG_I2C2_CONTROLLER_RK29
-#define I2C2_ADAP_TYPE I2C_RK29_ADAP
-#define I2C2_START RK2928_I2C2_PHYS
-#define I2C2_END RK2928_I2C2_PHYS + RK2928_I2C2_SIZE - 1
-#endif
-#ifdef CONFIG_I2C2_CONTROLLER_RK30
-#define I2C2_ADAP_TYPE I2C_RK30_ADAP
-#define I2C2_START RK2928_RKI2C2_PHYS
-#define I2C2_END RK2928_RKI2C2_PHYS + RK2928_RKI2C2_SIZE - 1
-#endif
-
-#ifdef CONFIG_I2C3_CONTROLLER_RK29
-#define I2C3_ADAP_TYPE I2C_RK29_ADAP
-#define I2C3_START RK2928_I2C3_PHYS
-#define I2C3_END RK2928_I2C3_PHYS + RK2928_I2C3_SIZE - 1
-#endif
-#ifdef CONFIG_I2C3_CONTROLLER_RK30
-#define I2C3_ADAP_TYPE I2C_RK30_ADAP
-#define I2C3_START RK2928_RKI2C3_PHYS
-#define I2C3_END RK2928_RKI2C3_PHYS + RK2928_RKI2C3_SIZE - 1
-#endif
-
-#ifdef CONFIG_I2C0_RK30
-static struct rk30_i2c_platform_data default_i2c0_data = {
- .bus_num = 0,
- .is_div_from_arm = 1,
- .adap_type = I2C0_ADAP_TYPE,
- .sda_mode = I2C0_SDA,
- .scl_mode = I2C0_SCL,
-
-};
-
-static struct resource resources_i2c0[] = {
- {
- .start = IRQ_I2C0,
- .end = IRQ_I2C0,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = I2C0_START,
- .end = I2C0_END,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_i2c0 = {
- .name = "rk30_i2c",
- .id = 0,
- .num_resources = ARRAY_SIZE(resources_i2c0),
- .resource = resources_i2c0,
- .dev = {
- .platform_data = &default_i2c0_data,
- },
-};
-#endif
-
-#ifdef CONFIG_I2C1_RK30
-static struct rk30_i2c_platform_data default_i2c1_data = {
- .bus_num = 1,
- .is_div_from_arm = 1,
- .adap_type = I2C1_ADAP_TYPE,
- .sda_mode = I2C1_SDA,
- .scl_mode = I2C1_SCL,
-};
-
-static struct resource resources_i2c1[] = {
- {
- .start = IRQ_I2C1,
- .end = IRQ_I2C1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = I2C1_START,
- .end = I2C1_END,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_i2c1 = {
- .name = "rk30_i2c",
- .id = 1,
- .num_resources = ARRAY_SIZE(resources_i2c1),
- .resource = resources_i2c1,
- .dev = {
- .platform_data = &default_i2c1_data,
- },
-};
-#endif
-
-#ifdef CONFIG_I2C2_RK30
-static struct rk30_i2c_platform_data default_i2c2_data = {
- .bus_num = 2,
- .is_div_from_arm = 0,
- .adap_type = I2C2_ADAP_TYPE,
- .sda_mode = I2C2_SDA,
- .scl_mode = I2C2_SCL,
-};
-
-static struct resource resources_i2c2[] = {
- {
- .start = IRQ_I2C2,
- .end = IRQ_I2C2,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = I2C2_START,
- .end = I2C2_END,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_i2c2 = {
- .name = "rk30_i2c",
- .id = 2,
- .num_resources = ARRAY_SIZE(resources_i2c2),
- .resource = resources_i2c2,
- .dev = {
- .platform_data = &default_i2c2_data,
- },
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-static struct rk30_i2c_platform_data default_i2c3_data = {
- .bus_num = 3,
- .is_div_from_arm = 0,
- .adap_type = I2C3_ADAP_TYPE,
- .sda_mode = I2C3_SDA,
- .scl_mode = I2C3_SCL,
-};
-
-static struct resource resources_i2c3[] = {
- {
- .start = IRQ_I2C3,
- .end = IRQ_I2C3,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = I2C3_START,
- .end = I2C3_END,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_i2c3 = {
- .name = "rk30_i2c",
- .id = 3,
- .num_resources = ARRAY_SIZE(resources_i2c3),
- .resource = resources_i2c3,
- .dev = {
- .platform_data = &default_i2c3_data,
- },
-};
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-static struct platform_device device_i2c_gpio = {
- .name = "i2c-gpio",
- .id = 4,
- .dev = {
- .platform_data = &default_i2c_gpio_data,
- },
-};
-#endif
-
-static void __init rk2928_init_i2c(void)
-{
-#ifdef CONFIG_I2C0_RK30
- platform_device_register(&device_i2c0);
-#endif
-#ifdef CONFIG_I2C1_RK30
- platform_device_register(&device_i2c1);
-#endif
-#ifdef CONFIG_I2C2_RK30
- platform_device_register(&device_i2c2);
-#endif
-#ifdef CONFIG_I2C3_RK30
- platform_device_register(&device_i2c3);
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- platform_device_register(&device_i2c_gpio);
-#endif
-}
-
-#if defined(CONFIG_SPIM0_RK29) || defined(CONFIG_SPIM1_RK29)
-/*****************************************************************************************
- * spi devices
- * author: cmc@rock-chips.com
- *****************************************************************************************/
-#define SPI_CHIPSELECT_NUM 2
-
-static int spi_io_init(struct spi_cs_gpio *cs_gpios, int cs_num)
-{
- int i;
- if (cs_gpios) {
- for (i = 0; i < cs_num; i++) {
- rk30_mux_api_set(cs_gpios[i].cs_iomux_name, cs_gpios[i].cs_iomux_mode);
- }
- }
- return 0;
-}
-
-static int spi_io_deinit(struct spi_cs_gpio *cs_gpios, int cs_num)
-{
- return 0;
-}
-
-static int spi_io_fix_leakage_bug(void)
-{
-#if 0
- gpio_direction_output(RK29_PIN2_PC1, GPIO_LOW);
-#endif
- return 0;
-}
-
-static int spi_io_resume_leakage_bug(void)
-{
-#if 0
- gpio_direction_output(RK29_PIN2_PC1, GPIO_HIGH);
-#endif
- return 0;
-}
-#endif
-
-/*
- * rk29xx spi master device
- */
-#ifdef CONFIG_SPIM0_RK29
-static struct spi_cs_gpio rk29xx_spi0_cs_gpios[SPI_CHIPSELECT_NUM] = {
-#if 0
- {
- .name = "spi0 cs0",
- .cs_gpio = RK2928_PIN1_PB3,
- .cs_iomux_name = GPIO1B3_SPI_CSN0_UART1_RTSN_NAME,
- .cs_iomux_mode = GPIO1B_SPI_CSN0,
- },
- {
- .name = "spi0 cs1",
- .cs_gpio = RK2928_PIN1_PB4,
- .cs_iomux_name = GPIO1B4_SPI_CSN1_UART1_CTSN_NAME,//if no iomux,set it NULL
- .cs_iomux_mode = GPIO1B_SPI_CSN1,
- },
-#endif
-};
-
-static struct rk29xx_spi_platform_data rk29xx_spi0_platdata = {
- .num_chipselect = SPI_CHIPSELECT_NUM,
- .chipselect_gpios = rk29xx_spi0_cs_gpios,
- .io_init = spi_io_init,
- .io_deinit = spi_io_deinit,
- .io_fix_leakage_bug = spi_io_fix_leakage_bug,
- .io_resume_leakage_bug = spi_io_resume_leakage_bug,
-};
-
-static struct resource rk29_spi0_resources[] = {
- {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK2928_SPI_PHYS,
- .end = RK2928_SPI_PHYS + RK2928_SPI_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DMACH_SPI0_TX,
- .end = DMACH_SPI0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = DMACH_SPI0_RX,
- .end = DMACH_SPI0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-struct platform_device rk29xx_device_spi0m = {
- .name = "rk29xx_spim",
- .id = 0,
- .num_resources = ARRAY_SIZE(rk29_spi0_resources),
- .resource = rk29_spi0_resources,
- .dev = {
- .dma_mask = &dma_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &rk29xx_spi0_platdata,
- },
-};
-#endif
-
-static void __init rk2928_init_spim(void)
-{
-#ifdef CONFIG_SPIM0_RK29
- platform_device_register(&rk29xx_device_spi0m);
-#endif
-}
-
-#ifdef CONFIG_MTD_NAND_RK29XX
-static struct resource resources_nand[] = {
- {
- .start = RK2928_NANDC_PHYS,
- .end = RK2928_NANDC_PHYS + RK2928_NANDC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- }
-};
-
-static struct platform_device device_nand = {
- .name = "rk29xxnand",
- .id = -1,
- .resource = resources_nand,
- .num_resources = ARRAY_SIZE(resources_nand),
-};
-#endif
-#if defined(CONFIG_HDMI_RK2928) || defined(CONFIG_HDMI_RK616)
-static struct resource resource_hdmi[] = {
- [0] = {
- .start = RK2928_HDMI_PHYS,
- .end = RK2928_HDMI_PHYS + RK2928_HDMI_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_HDMI,
- .end = IRQ_HDMI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_hdmi = {
-#ifdef CONFIG_HDMI_RK616
- .name = "rk3026-hdmi",
-#else
- .name = "rk2928-hdmi",
-#endif
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_hdmi),
- .resource = resource_hdmi,
-};
-#endif
-
-#ifdef CONFIG_RGA_RK30
-static struct resource resource_rga[] = {
- [0] = {
- .start = RK2928_RGA_PHYS,
- .end = RK2928_RGA_PHYS + RK2928_RGA_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_RGA,
- .end = IRQ_RGA,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_rga = {
- .name = "rga",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_rga),
- .resource = resource_rga,
-};
-#endif
-#ifdef CONFIG_SND_RK29_SOC_I2S
-#ifdef CONFIG_SND_RK29_SOC_I2S_8CH
-static struct resource resource_iis0_8ch[] = {
- [0] = {
- .start = RK2928_I2S_PHYS,
- .end = RK2928_I2S_PHYS + RK2928_I2S_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = DMACH_I2S0_8CH_TX,
- .end = DMACH_I2S0_8CH_TX,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = DMACH_I2S0_8CH_RX,
- .end = DMACH_I2S0_8CH_RX,
- .flags = IORESOURCE_DMA,
- },
- [3] = {
- .start = IRQ_I2S,
- .end = IRQ_I2S,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_iis0_8ch = {
- .name = "rk29_i2s",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_iis0_8ch),
- .resource = resource_iis0_8ch,
-};
-#endif
-#endif
-static struct platform_device device_pcm = {
- .name = "rockchip-audio",
- .id = -1,
-};
-
-static void __init rk2928_init_i2s(void)
-{
-#ifdef CONFIG_SND_RK29_SOC_I2S_8CH
- platform_device_register(&device_iis0_8ch);
-#endif
- platform_device_register(&device_pcm);
-}
-#ifdef CONFIG_KEYS_RK29
-extern struct rk29_keys_platform_data rk29_keys_pdata;
-static struct platform_device device_keys = {
- .name = "rk29-keypad",
- .id = -1,
- .dev = {
- .platform_data = &rk29_keys_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_EMMC_RK
-static struct resource resources_emmc[] = {
- {
- .start = IRQ_EMMC,
- .end = IRQ_EMMC,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK2928_EMMC_PHYS,
- .end = RK2928_EMMC_PHYS + RK2928_EMMC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- }
-};
-
-static struct platform_device device_emmc = {
- .name = "emmc",
- .id = -1,
- .num_resources = ARRAY_SIZE(resources_emmc),
- .resource = resources_emmc,
- .dev = {
- .platform_data = NULL,
- },
-};
-#endif
-
-#ifdef CONFIG_SDMMC0_RK29
-static struct resource resources_sdmmc0[] = {
- {
- .start = IRQ_SDMMC,
- .end = IRQ_SDMMC,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK2928_SDMMC_PHYS,
- .end = RK2928_SDMMC_PHYS + RK2928_SDMMC_SIZE -1,
- .flags = IORESOURCE_MEM,
- }
-};
-
-static struct platform_device device_sdmmc0 = {
- .name = "rk29_sdmmc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resources_sdmmc0),
- .resource = resources_sdmmc0,
- .dev = {
- .platform_data = &default_sdmmc0_data,
- },
-};
-#endif
-
-#ifdef CONFIG_SDMMC1_RK29
-static struct resource resources_sdmmc1[] = {
- {
- .start = IRQ_SDIO,
- .end = IRQ_SDIO,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK2928_SDIO_PHYS,
- .end = RK2928_SDIO_PHYS + RK2928_SDIO_SIZE - 1,
- .flags = IORESOURCE_MEM,
- }
-};
-
-static struct platform_device device_sdmmc1 = {
- .name = "rk29_sdmmc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resources_sdmmc1),
- .resource = resources_sdmmc1,
- .dev = {
- .platform_data = &default_sdmmc1_data,
- },
-};
-#endif
-static void __init rk2928_init_sdmmc(void)
-{
-#ifdef CONFIG_EMMC_RK
- platform_device_register(&device_emmc);
-#endif
-#ifdef CONFIG_SDMMC0_RK29
- platform_device_register(&device_sdmmc0);
-#endif
-#ifdef CONFIG_SDMMC1_RK29
- platform_device_register(&device_sdmmc1);
-#endif
-}
-
-#ifdef CONFIG_RK29_WATCHDOG
-static struct resource resources_wdt[] = {
- {
- .start = IRQ_WDT,
- .end = IRQ_WDT,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK2928_WDT_PHYS,
- .end = RK2928_WDT_PHYS + RK2928_WDT_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_wdt = {
- .name = "rk29-wdt",
- .id = 0,
- .num_resources = ARRAY_SIZE(resources_wdt),
- .resource = resources_wdt,
-};
-#endif
-
-static struct resource resource_arm_pmu[] = {
- {
- .start = IRQ_ARM_PMU,
- .end = IRQ_ARM_PMU,
- .flags = IORESOURCE_IRQ,
- },
-#if defined(CONFIG_ARCH_RK3026)
- {
- .start = IRQ_ARM_PMU + 1,
- .end = IRQ_ARM_PMU + 1,
- .flags = IORESOURCE_IRQ,
- },
-#endif
-};
-
-static struct platform_device device_arm_pmu = {
- .name = "arm-pmu",
- .id = ARM_PMU_DEVICE_CPU,
- .num_resources = ARRAY_SIZE(resource_arm_pmu),
- .resource = resource_arm_pmu,
-};
-
-
-#ifdef CONFIG_RK3026_LVDS
-static struct resource resource_lvds[] = {
- {
- .start = RK2928_GRF_PHYS + GRF_LVDS_CON0,
- .end = RK2928_GRF_PHYS + GRF_DMAC_CON0,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_lvds = {
- .name = "rk3026-lvds",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_lvds),
- .resource = resource_lvds,
-};
-#endif
-
-static struct resource resource_vpu[] = {
- {
- .start = IRQ_VDPU,
- .end = IRQ_VDPU,
- .name = "irq_vdpu",
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_VEPU,
- .end = IRQ_VEPU,
- .name = "irq_vepu",
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK2928_VCODEC_PHYS,
- .end = RK2928_VCODEC_PHYS + RK2928_VCODEC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_vpu = {
- .name = "vpu",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_vpu),
- .resource = resource_vpu,
-};
-
-static int __init rk2928_init_devices(void)
-{
- rk2928_init_dma();
- rk2928_init_uart();
- rk2928_init_i2c();
- rk2928_init_spim();
-#ifdef CONFIG_MTD_NAND_RK29XX
- platform_device_register(&device_nand);
-#endif
-#ifdef CONFIG_ADC_RK30
- platform_device_register(&device_adc);
-#endif
-#ifdef CONFIG_KEYS_RK29
- platform_device_register(&device_keys);
-#endif
-#ifdef CONFIG_RGA_RK30
- platform_device_register(&device_rga);
-#endif
- rk2928_init_sdmmc();
-#if defined(CONFIG_FIQ_DEBUGGER) && defined(DEBUG_UART_PHYS)
- rk_serial_debug_init(DEBUG_UART_BASE, IRQ_DEBUG_UART, IRQ_UART_SIGNAL, -1);
-#endif
- rk2928_init_i2s();
-#if defined(CONFIG_HDMI_RK2928) || defined(CONFIG_HDMI_RK616)
- platform_device_register(&device_hdmi);
-#endif
-#ifdef CONFIG_RK29_WATCHDOG
- platform_device_register(&device_wdt);
-#endif
- platform_device_register(&device_arm_pmu);
-
-#ifdef CONFIG_RK3026_LVDS
- platform_device_register(&device_lvds);
-#endif
- platform_device_register(&device_vpu);
-
- return 0;
-}
-arch_initcall(rk2928_init_devices);
+++ /dev/null
-/* arch/arm/mach-rk30/rk30_dvfs.c\r
- *\r
- * Copyright (C) 2012 ROCKCHIP, Inc.\r
- *\r
- * This software is licensed under the terms of the GNU General Public\r
- * License version 2, as published by the Free Software Foundation, and\r
- * may be copied, distributed, and modified under those terms.\r
- *\r
- * This program is distributed in the hope that it will be useful,\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- * GNU General Public License for more details.\r
- *\r
- */\r
-\r
-#include <linux/kernel.h>\r
-#include <linux/err.h>\r
-#include <linux/spinlock.h>\r
-#include <linux/list.h>\r
-#include <linux/slab.h>\r
-#include <linux/clk.h>\r
-#include <linux/cpufreq.h>\r
-#include <mach/dvfs.h>\r
-#include <mach/clock.h>\r
-#include <linux/regulator/consumer.h>\r
-#include <linux/delay.h>\r
-#include <linux/io.h>\r
-#include <linux/hrtimer.h>\r
-\r
-static int rk_dvfs_clk_notifier_event(struct notifier_block *this,\r
- unsigned long event, void *ptr)\r
-{\r
- struct clk_notifier_data *noti_info;\r
- struct clk *clk;\r
- struct clk_node *dvfs_clk;\r
- noti_info = (struct clk_notifier_data *)ptr;\r
- clk = noti_info->clk;\r
- dvfs_clk = clk->dvfs_info;\r
-\r
- switch (event) {\r
- case CLK_PRE_RATE_CHANGE:\r
- DVFS_DBG("%s CLK_PRE_RATE_CHANGE\n", __func__);\r
- break;\r
- case CLK_POST_RATE_CHANGE:\r
- DVFS_DBG("%s CLK_POST_RATE_CHANGE\n", __func__);\r
- break;\r
- case CLK_ABORT_RATE_CHANGE:\r
- DVFS_DBG("%s CLK_ABORT_RATE_CHANGE\n", __func__);\r
- break;\r
- case CLK_PRE_ENABLE:\r
- DVFS_DBG("%s CLK_PRE_ENABLE\n", __func__);\r
- break;\r
- case CLK_POST_ENABLE:\r
- DVFS_DBG("%s CLK_POST_ENABLE\n", __func__);\r
- break;\r
- case CLK_ABORT_ENABLE:\r
- DVFS_DBG("%s CLK_ABORT_ENABLE\n", __func__);\r
- break;\r
- case CLK_PRE_DISABLE:\r
- DVFS_DBG("%s CLK_PRE_DISABLE\n", __func__);\r
- break;\r
- case CLK_POST_DISABLE:\r
- DVFS_DBG("%s CLK_POST_DISABLE\n", __func__);\r
- dvfs_clk->set_freq = 0;\r
- break;\r
- case CLK_ABORT_DISABLE:\r
- DVFS_DBG("%s CLK_ABORT_DISABLE\n", __func__);\r
-\r
- break;\r
- default:\r
- break;\r
- }\r
- return 0;\r
-}\r
-\r
-static struct notifier_block rk_dvfs_clk_notifier = {\r
- .notifier_call = rk_dvfs_clk_notifier_event,\r
-};\r
-\r
-\r
-static struct clk_node *dvfs_clk_cpu;\r
-static struct vd_node vd_core;\r
-static int dvfs_target_cpu(struct clk *clk, unsigned long rate_hz)\r
-{\r
- struct clk_node *dvfs_clk;\r
- int volt_new = 0, volt_dep_new = 0, clk_volt_store = 0;\r
- struct cpufreq_frequency_table clk_fv;\r
- int ret = 0;\r
- unsigned long rate_new, rate_old;\r
- \r
- if (!clk) {\r
- DVFS_ERR("%s is not a clk\n", __func__);\r
- return -1;\r
- }\r
- dvfs_clk = clk_get_dvfs_info(clk);\r
- DVFS_DBG("enter %s: clk(%s) rate = %lu Hz\n", __func__, dvfs_clk->name, rate_hz);\r
-\r
- if (!dvfs_clk || dvfs_clk->vd == NULL || IS_ERR_OR_NULL(dvfs_clk->vd->regulator)) {\r
- DVFS_ERR("dvfs(%s) is not register regulator\n", dvfs_clk->name);\r
- return -1;\r
- }\r
-\r
- if (dvfs_clk->vd->volt_set_flag == DVFS_SET_VOLT_FAILURE) {\r
- /* It means the last time set voltage error */\r
- ret = dvfs_reset_volt(dvfs_clk->vd);\r
- if (ret < 0) {\r
- return -1;\r
- }\r
- }\r
-\r
- /* Check limit rate */\r
- if (dvfs_clk->freq_limit_en) {\r
- if (rate_hz < dvfs_clk->min_rate) {\r
- rate_hz = dvfs_clk->min_rate;\r
- } else if (rate_hz > dvfs_clk->max_rate) {\r
- rate_hz = dvfs_clk->max_rate;\r
- }\r
- }\r
- \r
- /* need round rate */\r
- rate_old = clk_get_rate(clk);\r
- rate_new = clk_round_rate_nolock(clk, rate_hz);\r
- if(rate_new == rate_old)\r
- return 0;\r
- DVFS_DBG("dvfs(%s) round rate (%lu)(rount %lu) old (%lu)\n", \r
- dvfs_clk->name, rate_hz, rate_new, rate_old);\r
-\r
- /* find the clk corresponding voltage */\r
- if (0 != dvfs_clk_get_ref_volt(dvfs_clk, rate_new / 1000, &clk_fv)) {\r
- DVFS_ERR("dvfs(%s) rate %luhz is larger,not support\n", dvfs_clk->name, rate_hz);\r
- return -1;\r
- }\r
- clk_volt_store = dvfs_clk->set_volt;\r
- dvfs_clk->set_volt = clk_fv.index;\r
- volt_new = dvfs_vd_get_newvolt_byclk(dvfs_clk);\r
-\r
- /* if up the rate */\r
- if (rate_new > rate_old) {\r
- if (!list_empty(&dvfs_clk->depend_list)) {\r
- // update depend's req_volt\r
- ret = dvfs_get_depend_volt(dvfs_clk, &vd_core, rate_new);\r
- if (ret <= 0)\r
- goto fail_roll_back;\r
- \r
- volt_dep_new = dvfs_vd_get_newvolt_bypd(&vd_core);\r
- if (volt_dep_new <= 0) \r
- goto fail_roll_back;\r
- ret = dvfs_scale_volt_direct(dvfs_clk->vd, volt_new);\r
-\r
- //ret = dvfs_scale_volt_bystep(dvfs_clk->vd, &vd_core, volt_new, volt_dep_new, \r
- // ARM_HIGHER_LOGIC, LOGIC_HIGHER_ARM); \r
- if (ret < 0) \r
- goto fail_roll_back;\r
- } else {\r
- ret = dvfs_scale_volt_direct(dvfs_clk->vd, volt_new);\r
- if (ret < 0) \r
- goto fail_roll_back;\r
- }\r
- }\r
-\r
- /* scale rate */\r
- if (dvfs_clk->clk_dvfs_target) {\r
- ret = dvfs_clk->clk_dvfs_target(clk, rate_new, clk_set_rate_locked);\r
- } else {\r
- ret = clk_set_rate_locked(clk, rate_new);\r
- }\r
-\r
- if (ret < 0) {\r
- DVFS_ERR("%s set rate err\n", __func__);\r
- goto fail_roll_back;\r
- }\r
- dvfs_clk->set_freq = rate_new / 1000;\r
-\r
- DVFS_DBG("dvfs %s set rate %lu ok\n", dvfs_clk->name, clk_get_rate(clk));\r
-\r
- /* if down the rate */\r
- if (rate_new < rate_old) {\r
- if (!list_empty(&dvfs_clk->depend_list)) {\r
- // update depend's req_volt\r
- ret = dvfs_get_depend_volt(dvfs_clk, &vd_core, rate_new);\r
- if (ret <= 0)\r
- goto out;\r
- \r
- volt_dep_new = dvfs_vd_get_newvolt_bypd(&vd_core);\r
- if (volt_dep_new <= 0) \r
- goto out;\r
- ret = dvfs_scale_volt_direct(dvfs_clk->vd, volt_new);\r
-\r
- //ret = dvfs_scale_volt_bystep(dvfs_clk->vd, &vd_core, volt_new, volt_dep_new, \r
- // ARM_HIGHER_LOGIC, LOGIC_HIGHER_ARM); \r
- if (ret < 0) \r
- goto out;\r
- } else {\r
- ret = dvfs_scale_volt_direct(dvfs_clk->vd, volt_new);\r
- if (ret < 0) \r
- goto out;\r
- }\r
- }\r
-\r
- return ret;\r
-fail_roll_back:\r
- dvfs_clk->set_volt = clk_volt_store;\r
- ret = dvfs_get_depend_volt(dvfs_clk, &vd_core, rate_old);\r
- if (ret <= 0) {\r
- DVFS_ERR("%s dvfs_get_depend_volt error when roll back!\n", __func__);\r
- }\r
-out:\r
- return -1;\r
-}\r
-\r
-static int dvfs_target_core(struct clk *clk, unsigned long rate_hz)\r
-{\r
- struct clk_node *dvfs_clk;\r
- int volt_new = 0, volt_dep_new = 0, clk_volt_store = 0;\r
- \r
- struct cpufreq_frequency_table clk_fv;\r
- \r
- int ret = 0;\r
- unsigned long rate_new, rate_old;\r
- \r
- if (!clk) {\r
- DVFS_ERR("%s is not a clk\n", __func__);\r
- return -1;\r
- }\r
- dvfs_clk = clk_get_dvfs_info(clk);\r
- DVFS_DBG("enter %s: clk(%s) rate = %lu Hz\n", __func__, dvfs_clk->name, rate_hz);\r
-\r
- if (!dvfs_clk || dvfs_clk->vd == NULL || IS_ERR_OR_NULL(dvfs_clk->vd->regulator)) {\r
- DVFS_ERR("dvfs(%s) is not register regulator\n", dvfs_clk->name);\r
- return -1;\r
- }\r
-\r
- if (dvfs_clk->vd->volt_set_flag == DVFS_SET_VOLT_FAILURE) {\r
- /* It means the last time set voltage error */\r
- ret = dvfs_reset_volt(dvfs_clk->vd);\r
- if (ret < 0) {\r
- return -1;\r
- }\r
- }\r
-\r
- /* Check limit rate */\r
- if (dvfs_clk->freq_limit_en) {\r
- if (rate_hz < dvfs_clk->min_rate) {\r
- rate_hz = dvfs_clk->min_rate;\r
- } else if (rate_hz > dvfs_clk->max_rate) {\r
- rate_hz = dvfs_clk->max_rate;\r
- }\r
- }\r
- \r
- /* need round rate */\r
- rate_old = clk_get_rate(clk);\r
- rate_new = clk_round_rate_nolock(clk, rate_hz);\r
- if(rate_new == rate_old)\r
- return 0;\r
- DVFS_DBG("dvfs(%s) round rate (%lu)(rount %lu) old (%lu)\n", \r
- dvfs_clk->name, rate_hz, rate_new, rate_old);\r
-\r
- /* find the clk corresponding voltage */\r
- if (0 != dvfs_clk_get_ref_volt(dvfs_clk, rate_new / 1000, &clk_fv)) {\r
- DVFS_ERR("dvfs(%s) rate %luhz is larger,not support\n", dvfs_clk->name, rate_hz);\r
- return -1;\r
- }\r
- clk_volt_store = dvfs_clk->set_volt;\r
- dvfs_clk->set_volt = clk_fv.index;\r
- volt_new = dvfs_vd_get_newvolt_byclk(dvfs_clk);\r
-\r
- /* if up the rate */\r
- if (rate_new > rate_old) {\r
- DVFS_DBG("-----------------------------rate_new > rate_old\n");\r
- volt_dep_new = dvfs_vd_get_newvolt_byclk(dvfs_clk_cpu);\r
-\r
- if (volt_dep_new < 0) \r
- goto fail_roll_back;\r
-\r
- ret = dvfs_scale_volt_direct(dvfs_clk->vd, volt_new);\r
- //ret = dvfs_scale_volt_bystep(dvfs_clk->vd, dvfs_clk_cpu->vd, volt_new, volt_dep_new, \r
- // LOGIC_HIGHER_ARM, ARM_HIGHER_LOGIC); \r
- if (ret < 0) \r
- goto fail_roll_back;\r
- }\r
-\r
- /* scale rate */\r
- if (dvfs_clk->clk_dvfs_target) {\r
- ret = dvfs_clk->clk_dvfs_target(clk, rate_new, clk_set_rate_locked);\r
- } else {\r
- \r
- ret = clk_set_rate_locked(clk, rate_new);\r
- }\r
-\r
- if (ret < 0) {\r
- DVFS_ERR("%s set rate err\n", __func__);\r
- goto fail_roll_back;\r
- }\r
- dvfs_clk->set_freq = rate_new / 1000;\r
-\r
- DVFS_DBG("dvfs %s set rate %lu ok\n", dvfs_clk->name, clk_get_rate(clk));\r
-\r
- /* if down the rate */\r
- if (rate_new < rate_old) {\r
- DVFS_DBG("-----------------------------rate_new < rate_old\n");\r
- volt_dep_new = dvfs_vd_get_newvolt_byclk(dvfs_clk_cpu);\r
-\r
- if (volt_dep_new < 0) \r
- goto out;\r
-\r
- ret = dvfs_scale_volt_direct(dvfs_clk->vd, volt_new);\r
- //ret = dvfs_scale_volt_bystep(dvfs_clk->vd, dvfs_clk_cpu->vd, volt_new, volt_dep_new, \r
- // LOGIC_HIGHER_ARM, ARM_HIGHER_LOGIC); \r
- if (ret < 0) \r
- goto out;\r
- }\r
-\r
- return ret;\r
-fail_roll_back: \r
- dvfs_clk->set_volt = clk_volt_store;\r
- ret = dvfs_get_depend_volt(dvfs_clk, &vd_core, rate_old);\r
- if (ret <= 0) {\r
- DVFS_ERR("%s dvfs_get_depend_volt error when roll back!\n", __func__);\r
- }\r
-\r
-out:\r
- return -1;\r
-}\r
-\r
-/*****************************init**************************/\r
-/**\r
- * rate must be raising sequence\r
- */\r
-static struct cpufreq_frequency_table cpu_dvfs_table[] = {\r
- // {.frequency = 48 * DVFS_KHZ, .index = 920*DVFS_MV},\r
- // {.frequency = 126 * DVFS_KHZ, .index = 970 * DVFS_MV},\r
- // {.frequency = 252 * DVFS_KHZ, .index = 1040 * DVFS_MV},\r
- // {.frequency = 504 * DVFS_KHZ, .index = 1050 * DVFS_MV},\r
- {.frequency = 816 * DVFS_KHZ, .index = 1050 * DVFS_MV},\r
- // {.frequency = 1008 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
- {.frequency = CPUFREQ_TABLE_END},\r
-};\r
-\r
-static struct cpufreq_frequency_table ddr_dvfs_table[] = {\r
- // {.frequency = 100 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
- {.frequency = 200 * DVFS_KHZ, .index = 1000 * DVFS_MV},\r
- {.frequency = 300 * DVFS_KHZ, .index = 1050 * DVFS_MV},\r
- {.frequency = 400 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
- {.frequency = 500 * DVFS_KHZ, .index = 1150 * DVFS_MV},\r
- {.frequency = 600 * DVFS_KHZ, .index = 1200 * DVFS_MV},\r
- {.frequency = CPUFREQ_TABLE_END},\r
-};\r
-\r
-static struct cpufreq_frequency_table gpu_dvfs_table[] = {\r
- {.frequency = 90 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
- {.frequency = 180 * DVFS_KHZ, .index = 1150 * DVFS_MV},\r
- {.frequency = 300 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
- {.frequency = 400 * DVFS_KHZ, .index = 1150 * DVFS_MV},\r
- {.frequency = 500 * DVFS_KHZ, .index = 1200 * DVFS_MV},\r
- {.frequency = CPUFREQ_TABLE_END},\r
-};\r
-\r
-static struct cpufreq_frequency_table peri_aclk_dvfs_table[] = {\r
- {.frequency = 100 * DVFS_KHZ, .index = 1000 * DVFS_MV},\r
- {.frequency = 200 * DVFS_KHZ, .index = 1050 * DVFS_MV},\r
- {.frequency = 300 * DVFS_KHZ, .index = 1070 * DVFS_MV},\r
- {.frequency = 500 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
- {.frequency = CPUFREQ_TABLE_END},\r
-};\r
-\r
-static struct cpufreq_frequency_table vpu_dvfs_table[] = {\r
- {.frequency = 266 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
- {.frequency = 300 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
- {.frequency = 400 * DVFS_KHZ, .index = 1200 * DVFS_MV},\r
- {.frequency = CPUFREQ_TABLE_END},\r
-};\r
-\r
-static struct cpufreq_frequency_table dep_cpu2core_table[] = {\r
- // {.frequency = 252 * DVFS_KHZ, .index = 1025 * DVFS_MV},\r
- // {.frequency = 504 * DVFS_KHZ, .index = 1025 * DVFS_MV},\r
- {.frequency = 816 * DVFS_KHZ, .index = 1050 * DVFS_MV},//logic 1.050V\r
- // {.frequency = 1008 * DVFS_KHZ,.index = 1050 * DVFS_MV},\r
- // {.frequency = 1200 * DVFS_KHZ,.index = 1050 * DVFS_MV},\r
- // {.frequency = 1272 * DVFS_KHZ,.index = 1050 * DVFS_MV},//logic 1.050V\r
- // {.frequency = 1416 * DVFS_KHZ,.index = 1100 * DVFS_MV},//logic 1.100V\r
- // {.frequency = 1512 * DVFS_KHZ,.index = 1125 * DVFS_MV},//logic 1.125V\r
- // {.frequency = 1608 * DVFS_KHZ,.index = 1175 * DVFS_MV},//logic 1.175V\r
- {.frequency = CPUFREQ_TABLE_END},\r
-};\r
-\r
-static struct vd_node vd_cpu = {\r
- .name = "vd_cpu",\r
- .regulator_name = "vdd_cpu",\r
- .volt_set_flag = DVFS_SET_VOLT_FAILURE,\r
- .vd_dvfs_target = dvfs_target_cpu,\r
-};\r
-\r
-static struct vd_node vd_core = {\r
- .name = "vd_core",\r
- .regulator_name = "vdd_core",\r
- .volt_set_flag = DVFS_SET_VOLT_FAILURE,\r
- .vd_dvfs_target = dvfs_target_core,\r
-};\r
-\r
-static struct vd_node vd_rtc = {\r
- .name = "vd_rtc",\r
- .regulator_name = "vdd_rtc",\r
- .volt_set_flag = DVFS_SET_VOLT_FAILURE,\r
- .vd_dvfs_target = NULL,\r
-};\r
-\r
-static struct vd_node *rk30_vds[] = {&vd_cpu, &vd_core, &vd_rtc};\r
-\r
-static struct pd_node pd_a9_0 = {\r
- .name = "pd_a9_0",\r
- .vd = &vd_cpu,\r
-};\r
-static struct pd_node pd_a9_1 = {\r
- .name = "pd_a9_1",\r
- .vd = &vd_cpu,\r
-};\r
-static struct pd_node pd_debug = {\r
- .name = "pd_debug",\r
- .vd = &vd_cpu,\r
-};\r
-static struct pd_node pd_scu = {\r
- .name = "pd_scu",\r
- .vd = &vd_cpu,\r
-};\r
-static struct pd_node pd_video = {\r
- .name = "pd_video",\r
- .vd = &vd_core,\r
-};\r
-static struct pd_node pd_vio = {\r
- .name = "pd_vio",\r
- .vd = &vd_core,\r
-};\r
-static struct pd_node pd_gpu = {\r
- .name = "pd_gpu",\r
- .vd = &vd_core,\r
-};\r
-static struct pd_node pd_peri = {\r
- .name = "pd_peri",\r
- .vd = &vd_core,\r
-};\r
-static struct pd_node pd_cpu = {\r
- .name = "pd_cpu",\r
- .vd = &vd_core,\r
-};\r
-static struct pd_node pd_alive = {\r
- .name = "pd_alive",\r
- .vd = &vd_core,\r
-};\r
-static struct pd_node pd_rtc = {\r
- .name = "pd_rtc",\r
- .vd = &vd_rtc,\r
-};\r
-#define LOOKUP_PD(_ppd) \\r
-{ \\r
- .pd = _ppd, \\r
-}\r
-static struct pd_node_lookup rk30_pds[] = {\r
- LOOKUP_PD(&pd_a9_0),\r
- LOOKUP_PD(&pd_a9_1),\r
- LOOKUP_PD(&pd_debug),\r
- LOOKUP_PD(&pd_scu),\r
- LOOKUP_PD(&pd_video),\r
- LOOKUP_PD(&pd_vio),\r
- LOOKUP_PD(&pd_gpu),\r
- LOOKUP_PD(&pd_peri),\r
- LOOKUP_PD(&pd_cpu),\r
- LOOKUP_PD(&pd_alive),\r
- LOOKUP_PD(&pd_rtc),\r
-};\r
-\r
-#define CLK_PDS(_ppd) \\r
-{ \\r
- .pd = _ppd, \\r
-}\r
-\r
-static struct pds_list cpu_pds[] = {\r
- CLK_PDS(&pd_a9_0),\r
- CLK_PDS(&pd_a9_1),\r
- CLK_PDS(NULL),\r
-};\r
-\r
-static struct pds_list ddr_pds[] = {\r
- CLK_PDS(&pd_cpu),\r
- CLK_PDS(NULL),\r
-};\r
-\r
-static struct pds_list gpu_pds[] = {\r
- CLK_PDS(&pd_gpu),\r
- CLK_PDS(NULL),\r
-};\r
-\r
-static struct pds_list aclk_periph_pds[] = {\r
- CLK_PDS(&pd_peri),\r
- CLK_PDS(NULL),\r
-};\r
-\r
-static struct pds_list aclk_vepu_pds[] = {\r
- CLK_PDS(&pd_video),\r
- CLK_PDS(NULL),\r
-};\r
-\r
-#define RK_CLKS(_clk_name, _ppds, _dvfs_table, _dvfs_nb) \\r
-{ \\r
- .name = _clk_name, \\r
- .pds = _ppds,\\r
- .dvfs_table = _dvfs_table, \\r
- .dvfs_nb = _dvfs_nb, \\r
-}\r
-\r
-static struct clk_node rk30_clks[] = {\r
- RK_CLKS("cpu", cpu_pds, cpu_dvfs_table, &rk_dvfs_clk_notifier),\r
- RK_CLKS("ddr", ddr_pds, ddr_dvfs_table, &rk_dvfs_clk_notifier),\r
- RK_CLKS("gpu", gpu_pds, gpu_dvfs_table, &rk_dvfs_clk_notifier),\r
- RK_CLKS("aclk_vepu", aclk_vepu_pds, vpu_dvfs_table, &rk_dvfs_clk_notifier),\r
- //RK_CLKS("aclk_periph", aclk_periph_pds, peri_aclk_dvfs_table, &rk_dvfs_clk_notifier),\r
-};\r
-\r
-#define RK_DEPPENDS(_clk_name, _pvd, _dep_table) \\r
-{ \\r
- .clk_name = _clk_name, \\r
- .dep_vd = _pvd,\\r
- .dep_table = _dep_table, \\r
-}\r
-\r
-static struct depend_lookup rk30_depends[] = {\r
- RK_DEPPENDS("cpu", &vd_core, dep_cpu2core_table),\r
- //RK_DEPPENDS("gpu", &vd_cpu, NULL),\r
- //RK_DEPPENDS("gpu", &vd_cpu, NULL),\r
-};\r
-\r
-\r
-static struct avs_ctr_st rk292x_avs_ctr;\r
-\r
-int rk292x_dvfs_init(void)\r
-{\r
- int i = 0;\r
- for (i = 0; i < ARRAY_SIZE(rk30_vds); i++) {\r
- rk_regist_vd(rk30_vds[i]);\r
- }\r
- for (i = 0; i < ARRAY_SIZE(rk30_pds); i++) {\r
- rk_regist_pd(&rk30_pds[i]);\r
- }\r
- for (i = 0; i < ARRAY_SIZE(rk30_clks); i++) {\r
- rk_regist_clk(&rk30_clks[i]);\r
- }\r
- for (i = 0; i < ARRAY_SIZE(rk30_depends); i++) {\r
- rk_regist_depends(&rk30_depends[i]);\r
- }\r
- dvfs_clk_cpu = dvfs_get_dvfs_clk_byname("cpu");\r
- avs_board_init(&rk292x_avs_ctr);\r
- return 0;\r
-}\r
-\r
-\r
-\r
-\r
-\r
-/******************************rk292x avs**************************************************/\r
-#if 0//def CONFIG_ARCH_RK2928\r
-\r
-static void __iomem *rk292x_nandc_base;\r
-#define nandc_readl(offset) readl_relaxed(rk292x_nandc_base + offset)\r
-#define nandc_writel(v, offset) do { writel_relaxed(v, rk292x_nandc_base + offset); dsb(); } while (0)\r
-static u8 rk292x_get_avs_val(void)\r
-{\r
- u32 nanc_save_reg[4];\r
- unsigned long flags;\r
- u32 paramet = 0;\r
- u32 count = 100;\r
- preempt_disable();\r
- local_irq_save(flags);\r
-\r
- nanc_save_reg[0] = nandc_readl(0);\r
- nanc_save_reg[1] = nandc_readl(0x130);\r
- nanc_save_reg[2] = nandc_readl(0x134);\r
- nanc_save_reg[3] = nandc_readl(0x158);\r
-\r
- nandc_writel(nanc_save_reg[0] | 0x1 << 14, 0);\r
- nandc_writel(0x5, 0x130);\r
-\r
- nandc_writel(7, 0x158);\r
- nandc_writel(1, 0x134);\r
-\r
- while(count--) {\r
- paramet = nandc_readl(0x138);\r
- if((paramet & 0x1))\r
- break;\r
- udelay(1);\r
- };\r
- paramet = (paramet >> 1) & 0xff;\r
- nandc_writel(nanc_save_reg[0], 0);\r
- nandc_writel(nanc_save_reg[1], 0x130);\r
- nandc_writel(nanc_save_reg[2], 0x134);\r
- nandc_writel(nanc_save_reg[3], 0x158);\r
-\r
- local_irq_restore(flags);\r
- preempt_enable();\r
- return (u8)paramet;\r
-\r
-}\r
-\r
-void rk292x_avs_init(void)\r
-{\r
- rk292x_nandc_base = ioremap(RK2928_NANDC_PHYS, RK2928_NANDC_SIZE);\r
- //avs_init_val_get(0,1150000,"board_init");\r
-}\r
-\r
-static struct avs_ctr_st rk292x_avs_ctr = {\r
- .avs_init =rk292x_avs_init,\r
- .avs_get_val = rk292x_get_avs_val,\r
-};\r
-#endif\r
+++ /dev/null
-#include <linux/io.h>
-#include <mach/board.h>
-#include <mach/sram.h>
-#include <mach/iomux.h>
-#include <mach/cru.h>
-#include <asm/io.h>
-#include <mach/gpio.h>
-
-#define cru_readl(offset) readl_relaxed(RK2928_CRU_BASE + offset)
-#define cru_writel(v, offset) do { writel_relaxed(v, RK2928_CRU_BASE + offset); dsb(); } while (0)
-
-#if defined(CONFIG_RK30_I2C_INSRAM)
-
-/******************need set when you use i2c*************************/
-#define I2C_SPEED 100
-#define I2C_SADDR (0x2D) /* slave address ,wm8310 addr is 0x34*/
-#define SRAM_I2C_CH 1 //CH==0, i2c0,CH==1, i2c1,CH==2, i2c2,CH==3, i2c3
-#if defined (CONFIG_MACH_RK2928_SDK)|| ( CONFIG_ARCH_RK3026_TB)||(CONFIG_ARCH_RK3028A_TB)
-#define SRAM_I2C_ADDRBASE (RK2928_RKI2C1_BASE )//RK29_I2C0_BASE\RK29_I2C2_BASE\RK29_I2C3_BASE
-#else
-#define SRAM_I2C_ADDRBASE (RK2928_RKI2C0_BASE )
-#endif
-
-#define I2C_SLAVE_ADDR_LEN 1 // 2:slav addr is 10bit ,1:slav addr is 7bit
-#define I2C_SLAVE_REG_LEN 1 // 2:slav reg addr is 16 bit ,1:is 8 bit
-#define SRAM_I2C_DATA_BYTE 1 //i2c transmission data is 1bit(8wei) or 2bit(16wei)
-#define GRF_GPIO_IOMUX 0xd4 //GRF_GPIO2D_IOMUX
-/*ch=0:GRF_GPIO2L_IOMUX,ch=1:GRF_GPIO1L_IOMUX,ch=2:GRF_GPIO5H_IOMUX,ch=3:GRF_GPIO2L_IOMUX*/
-#define I2C_GRF_GPIO_IOMUX (0x01<<14)|(0x01<<12)
-/*CH=0:(~(0x03<<30))&(~(0x03<<28))|(0x01<<30)|(0x01<<28),CH=1:(~(0x03<<14))&(~(0x03<<12))|(0x01<<14)|(0x01<<12),
-CH=2:(~(0x03<<24))&(~(0x03<<22))|(0x01<<24)|(0x01<<22),CH=3:(~(0x03<<26))&(~(0x03<<24))|(0x02<<26)|(0x02<<24)*/
-/***************************************/
-
-#define I2C_SLAVE_TYPE (((I2C_SLAVE_ADDR_LEN-1)<<4)|((I2C_SLAVE_REG_LEN-1)))
-
-#define uint8 unsigned char
-#define uint16 unsigned short
-#define uint32 unsigned int
-uint32 __sramdata data[5];
-uint8 __sramdata arm_voltage = 0;
-#if defined ( CONFIG_ARCH_RK3026)
-uint8 __sramdata logic_voltage = 0;
-#endif
-
-#define CRU_CLKGATE0_CON 0xd0
-#define CRU_CLKGATE8_CON 0xf0
-#define CRU_CLKSEL1_CON 0x48
-#define GRF_GPIO5H_IOMUX 0x74
-#define GRF_GPIO2L_IOMUX 0x58
-#define GRF_GPIO1L_IOMUX 0x50
-
-#define COMPLETE_READ (1<<STATE_START|1<<STATE_READ|1<<STATE_STOP)
-#define COMPLETE_WRITE (1<<STATE_START|1<<STATE_WRITE|1<<STATE_STOP)
-
-/* Control register */
-#define I2C_CON 0x0000
-#define I2C_CON_EN (1 << 0)
-#define I2C_CON_MOD(mod) ((mod) << 1)
-#define I2C_CON_MASK (3 << 1)
-enum{
- I2C_CON_MOD_TX = 0,
- I2C_CON_MOD_TRX,
- I2C_CON_MOD_RX,
- I2C_CON_MOD_RRX,
-};
-#define I2C_CON_START (1 << 3)
-#define I2C_CON_STOP (1 << 4)
-#define I2C_CON_LASTACK (1 << 5)
-#define I2C_CON_ACTACK (1 << 6)
-
-/* Clock dividor register */
-#define I2C_CLKDIV 0x0004
-#define I2C_CLKDIV_VAL(divl, divh) (((divl) & 0xffff) | (((divh) << 16) & 0xffff0000))
-#define rk30_ceil(x, y) \
- ({ unsigned long __x = (x), __y = (y); (__x + __y - 1) / __y; })
-
-/* the slave address accessed for master rx mode */
-#define I2C_MRXADDR 0x0008
-#define I2C_MRXADDR_LOW (1 << 24)
-#define I2C_MRXADDR_MID (1 << 25)
-#define I2C_MRXADDR_HIGH (1 << 26)
-
-/* the slave register address accessed for master rx mode */
-#define I2C_MRXRADDR 0x000c
-#define I2C_MRXRADDR_LOW (1 << 24)
-#define I2C_MRXRADDR_MID (1 << 25)
-#define I2C_MRXRADDR_HIGH (1 << 26)
-
-/* master tx count */
-#define I2C_MTXCNT 0x0010
-
-/* master rx count */
-#define I2C_MRXCNT 0x0014
-
-/* interrupt enable register */
-#define I2C_IEN 0x0018
-#define I2C_BTFIEN (1 << 0)
-#define I2C_BRFIEN (1 << 1)
-#define I2C_MBTFIEN (1 << 2)
-#define I2C_MBRFIEN (1 << 3)
-#define I2C_STARTIEN (1 << 4)
-#define I2C_STOPIEN (1 << 5)
-#define I2C_NAKRCVIEN (1 << 6)
-#define IRQ_MST_ENABLE (I2C_MBTFIEN | I2C_MBRFIEN | I2C_NAKRCVIEN | I2C_STARTIEN | I2C_STOPIEN)
-#define IRQ_ALL_DISABLE 0
-
-/* interrupt pending register */
-#define I2C_IPD 0x001c
-#define I2C_BTFIPD (1 << 0)
-#define I2C_BRFIPD (1 << 1)
-#define I2C_MBTFIPD (1 << 2)
-#define I2C_MBRFIPD (1 << 3)
-#define I2C_STARTIPD (1 << 4)
-#define I2C_STOPIPD (1 << 5)
-#define I2C_NAKRCVIPD (1 << 6)
-#define I2C_IPD_ALL_CLEAN 0x7f
-
-/* finished count */
-#define I2C_FCNT 0x0020
-
-/* I2C tx data register */
-#define I2C_TXDATA_BASE 0X0100
-
-/* I2C rx data register */
-#define I2C_RXDATA_BASE 0x0200
-
-void __sramfunc sram_i2c_enable(void);
-void __sramfunc sram_i2c_disenable(void);
-
-void __sramfunc sram_printch(char byte);
-void __sramfunc sram_printhex(unsigned int hex);
-
-#define sram_udelay(usecs) SRAM_LOOP((usecs)*SRAM_LOOPS_PER_USEC)
-
-/*-------------------------------------------------------------------------------------------------------
-Name : sram_i2c_init
-Desc : initialize the necessary registers
-Params : channel-determine which I2C bus we used
-Return : none
-------------------------------------------------------------------------------------------------------*/
-
-void __sramfunc sram_i2c_init()
-{
- unsigned int div, divl, divh;
- //enable cru_clkgate8 clock
- data[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_CLKID(8)));
-
- #if defined (CONFIG_MACH_RK2928_SDK) || ( CONFIG_ARCH_RK3026_TB)||(CONFIG_ARCH_RK3028A_TB)
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_PCLK_I2C1)|CLK_UN_GATE(CLK_GATE_PCLK_I2C1),
- CLK_GATE_CLKID_CONS(CLK_GATE_PCLK_I2C1));
- #else
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_PCLK_I2C0)|CLK_UN_GATE(CLK_GATE_PCLK_I2C0),
- CLK_GATE_CLKID_CONS(CLK_GATE_PCLK_I2C0));
- #endif
-
- data[2] = readl_relaxed(RK2928_GRF_BASE + GRF_GPIO_IOMUX);
- writel_relaxed(data[2]| I2C_GRF_GPIO_IOMUX, RK2928_GRF_BASE + GRF_GPIO_IOMUX);
-
- div = 0x1e;
- divh = divl = 0xf;
- writel_relaxed(I2C_CLKDIV_VAL(divl, divh), SRAM_I2C_ADDRBASE + I2C_CLKDIV);
- data[3] = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_CLKDIV);
-
-}
-
-
-/*-------------------------------------------------------------------------------------------------------
-Name : sram_i2c_deinit
-Desc : de-initialize the necessary registers
-Params : noe
-Return : none
-------------------------------------------------------------------------------------------------------*/
-void __sramfunc sram_i2c_deinit(void)
-{
- //restore iomux reg
- writel_relaxed(data[2], RK2928_GRF_BASE + GRF_GPIO_IOMUX);
-
- //restore scu clock reg
- cru_writel(data[1], CLK_GATE_CLKID_CONS(CLK_GATE_PCLK_I2C1));
-
-
-}
-
-/*-------------------------------------------------------------------------------------------------------
-Name : sram_i2c_start
-Desc : start i2c
-Params : none
-Return : none
-------------------------------------------------------------------------------------------------------*/
-void __sramfunc sram_i2c_read_enable(void)
-{
- writel_relaxed(((((I2C_CON_EN | I2C_CON_MOD(1)) | I2C_CON_LASTACK) )| I2C_CON_START) & (~(I2C_CON_STOP)) , SRAM_I2C_ADDRBASE + I2C_CON);
-}
-void __sramfunc sram_i2c_write_enable(void)
-{
- writel_relaxed(((((I2C_CON_EN | I2C_CON_MOD(0)) | I2C_CON_LASTACK) )| I2C_CON_START) & (~(I2C_CON_STOP)) , SRAM_I2C_ADDRBASE + I2C_CON);
-}
-
-void __sramfunc sram_i2c_disenable(void)
-{
- writel_relaxed(0, SRAM_I2C_ADDRBASE + I2C_CON);
-}
-
-void __sramfunc sram_i2c_clean_start(void)
-{
- unsigned int con = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_CON);
-
- con = (con & (~I2C_CON_START)) ;
- writel_relaxed(con, SRAM_I2C_ADDRBASE + I2C_CON);
-}
-void __sramfunc sram_i2c_send_start(void)
-{
- unsigned int con = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_CON);
- con |= I2C_CON_START;
- if(con & I2C_CON_STOP)
- sram_printch('E');
- writel_relaxed(con, SRAM_I2C_ADDRBASE + I2C_CON);
-}
-void __sramfunc sram_i2c_send_stop(void)
-{
- unsigned int con = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_CON);
- con &= ~I2C_CON_START;
- con |= I2C_CON_STOP;
- if(con & I2C_CON_START)
- sram_printch('E');
- writel_relaxed(con, SRAM_I2C_ADDRBASE + I2C_CON);
-}
-void __sramfunc sram_i2c_clean_stop(void)
-{
- unsigned int con = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_CON);
-
- con = (con & (~I2C_CON_STOP)) ;
- writel_relaxed(con, SRAM_I2C_ADDRBASE + I2C_CON);
-}
-
-void __sramfunc sram_i2c_get_ipd_event(int type)
-{
- int time = 2000;
- unsigned int con = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_IPD);
- writel_relaxed(type, SRAM_I2C_ADDRBASE + I2C_IEN);
- do{
- sram_udelay(10);
- con = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_IPD);
- }while(((--time) & (~(con & type))));
- writel_relaxed(type,SRAM_I2C_ADDRBASE + I2C_IPD);
-
- if(time <= 0){
- sram_printch('T');
- }
-}
-
-void __sramfunc sram_i2c_write_prepare(uint8 I2CSlaveAddr, uint8 regAddr,uint8 pdata)
-{
- u32 data = 0;
- unsigned int addr = (I2CSlaveAddr & 0x7f) << 1;
-
- data = (addr | (regAddr << 8))|(pdata << 16);
- writel_relaxed(data , SRAM_I2C_ADDRBASE + I2C_TXDATA_BASE);
- writel_relaxed(3, SRAM_I2C_ADDRBASE + I2C_MTXCNT);
-}
-uint8 __sramfunc sram_i2c_read_prepare(uint8 I2CSlaveAddr, uint8 regAddr)
-{
- unsigned int addr = (I2CSlaveAddr & 0x7f) << 1;
-
- writel_relaxed(addr | I2C_MRXADDR_LOW, SRAM_I2C_ADDRBASE + I2C_MRXADDR);
- writel_relaxed(regAddr | I2C_MRXADDR_LOW, SRAM_I2C_ADDRBASE + I2C_MRXRADDR);
- writel_relaxed(SRAM_I2C_DATA_BYTE, SRAM_I2C_ADDRBASE + I2C_MRXCNT);
- return 0;
-}
-
-uint8 __sramfunc sram_i2c_read_get_data(uint8 I2CSlaveAddr, uint8 regAddr)
-{
- unsigned int ret;
- ret = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_RXDATA_BASE);
- ret = ret & 0x000000ff;
- return ret;
-
-}
-uint8 __sramfunc sram_i2c_write(uint8 I2CSlaveAddr, uint8 regAddr,uint8 data)
-{
- sram_i2c_write_enable();
- sram_i2c_get_ipd_event(I2C_STARTIPD);
- sram_i2c_clean_start();
-
- sram_i2c_write_prepare(I2CSlaveAddr,regAddr,data);
- sram_i2c_get_ipd_event(I2C_MBTFIPD);
-
- sram_i2c_send_stop();
- sram_i2c_get_ipd_event(I2C_STOPIPD);
- sram_i2c_clean_stop();
- sram_i2c_disenable();
- return 0;
-
-}
-
-uint8 __sramfunc sram_i2c_read(uint8 I2CSlaveAddr, uint8 regAddr)
-{
- unsigned int data;
- sram_i2c_read_enable();
- sram_i2c_get_ipd_event(I2C_STARTIPD);
- sram_i2c_clean_start();
-
- sram_i2c_read_prepare(I2CSlaveAddr,regAddr);
- sram_i2c_get_ipd_event(I2C_MBRFIPD);
-
- data = sram_i2c_read_get_data(I2CSlaveAddr,regAddr);
-
- sram_i2c_send_stop();
- sram_i2c_get_ipd_event(I2C_STOPIPD);
- sram_i2c_clean_stop();
- sram_i2c_disenable();
- return data;
-}
-
-void __sramfunc rk30_suspend_voltage_set(unsigned int vol)
-{
- uint8 slaveaddr;
- uint8 slavereg;
- uint8 data,ret = 0;
- uint8 rtc_status_reg = 0x11;
- sram_i2c_init(); //init i2c device
- #if defined(CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- {
- slaveaddr = 0x2d; //slave device addr
- slavereg = 0x22; // reg addr
- data = 0x1C; //set arm 1.0v
-
- ret = sram_i2c_read(slaveaddr, rtc_status_reg);
- sram_i2c_write(slaveaddr, rtc_status_reg, ret);
- arm_voltage = sram_i2c_read(slaveaddr, slavereg);
-#if defined ( CONFIG_ARCH_RK3026)
- logic_voltage = sram_i2c_read(slaveaddr, 0x25);
- sram_i2c_write(slaveaddr, 0x25, data);//
-#endif
- //sram_printhex(ret);
- sram_i2c_write(slaveaddr, slavereg, data);//
- }
- #endif
-
- #if defined(CONFIG_REGULATOR_ACT8931)
- if(pmic_is_act8931())
- {
- slaveaddr = 0x5b; //slave device addr
- slavereg = 0x40; // reg addr
- data = 0x10; //set arm 1.0v
-
- arm_voltage = sram_i2c_read(slaveaddr, slavereg);
-
- //sram_printhex(ret);
- sram_i2c_write(slaveaddr, slavereg, data);//
- sram_i2c_write(slaveaddr,( slavereg+0x1), data);//
- }
- #endif
- sram_i2c_deinit(); //deinit i2c device
-
-}
-
-void __sramfunc rk30_suspend_voltage_resume(unsigned int vol)
-{
- uint8 slaveaddr;
- uint8 slavereg;
- uint8 data,ret = 0;
-#if defined ( CONFIG_ARCH_RK3026)
- uint8 data2;
- data2 = logic_voltage;
-#endif
-
- data = arm_voltage;
- sram_i2c_init(); //init i2c device
- #if defined(CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- {
- slaveaddr = 0x2d; //slave device addr
- slavereg = 0x22; // reg add
- sram_i2c_write(slaveaddr, slavereg, data);
- sram_udelay(20000);
-#if defined ( CONFIG_ARCH_RK3026)
- sram_i2c_write(slaveaddr, 0x25, data2);
- sram_udelay(20000);
-#endif
- }
- #endif
- #if defined(CONFIG_REGULATOR_ACT8931)
- if(pmic_is_act8931())
- {
- slaveaddr = 0x5b; //slave device addr
- slavereg = 0x40; // reg addr
- sram_i2c_write(slaveaddr, slavereg, data);
- sram_i2c_write(slaveaddr, (slavereg+0x1), data);
- sram_udelay(20000);
- }
- #endif
- sram_i2c_deinit(); //deinit i2c device
-}
-
-int __sramfunc act8931_dc_det(unsigned int vol)
-{
- uint8 slaveaddr;
- uint16 slavereg;
- uint8 ret = 0;
- int data = 0;
- slaveaddr = 0x5b; //slave device addr
- slavereg = 0x78; // reg addr
-
- sram_i2c_init(); //init i2c device
- ret = sram_i2c_read(slaveaddr,slavereg);
- data = (ret & (1<<1) )? 1:0;
- sram_i2c_deinit(); //deinit i2c device
- return data;
-}
-
-#else
-void __sramfunc rk30_suspend_voltage_set(unsigned int vol)
-{
-
-}
-void __sramfunc rk30_suspend_voltage_resume(unsigned int vol)
-{
-
-}
-int __sramfunc act8931_dc_det(unsigned int vol)
-{
- return -1;
-}
-#endif
-
-
-
+++ /dev/null
-#ifndef __MACH_BOARD_H
-#define __MACH_BOARD_H
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-#include <linux/types.h>
-#include <linux/timer.h>
-#include <linux/notifier.h>
-#include <asm/setup.h>
-#include <plat/board.h>
-#include <mach/sram.h>
-#include <linux/i2c-gpio.h>
-
-#define GPIO_SWPORTA_DR 0x0000
-#define GPIO_SWPORTA_DDR 0x0004
-
-void __init rk2928_map_common_io(void);
-void __init rk2928_init_irq(void);
-void __init rk2928_map_io(void);
-struct machine_desc;
-void __init rk2928_fixup(struct machine_desc *desc, struct tag *tags, char **cmdline, struct meminfo *mi);
-void __init rk2928_clock_data_init(unsigned long gpll,unsigned long cpll,u32 flags);
-void __init rk2928_iomux_init(void);
-extern struct sys_timer rk2928_timer;
-#if defined (CONFIG_TOUCHSCREEN_I30) || defined (CONFIG_TP_760_TS)
-struct ft5306_platform_data {
- int rest_pin;
- int irq_pin ;
- int (*get_pendown_state)(void);
- int (*init_platform_hw)(void);
- int (*platform_sleep)(void);
- int (*platform_wakeup)(void);
- void (*exit_platform_hw)(void);
-};
-#endif
-
-enum _periph_pll {
- periph_pll_1485mhz = 148500000,
- periph_pll_297mhz = 297000000,
- periph_pll_300mhz = 300000000,
- periph_pll_768mhz = 768000000,
- periph_pll_1188mhz = 1188000000, /* for box*/
-};
-enum _codec_pll {
- codec_pll_360mhz = 360000000, /* for HDMI */
- codec_pll_408mhz = 408000000,
- codec_pll_456mhz = 456000000,
- codec_pll_504mhz = 504000000,
- codec_pll_552mhz = 552000000, /* for HDMI */
- codec_pll_594mhz = 594000000, /* for HDMI */
- codec_pll_600mhz = 600000000,
- codec_pll_742_5khz = 742500000,
- codec_pll_798mhz = 798000000,
- codec_pll_1064mhz = 1064000000,
- codec_pll_1188mhz = 1188000000,
-};
-
-//max i2s rate
-#define CLK_FLG_MAX_I2S_12288KHZ (1<<1)
-#define CLK_FLG_MAX_I2S_22579_2KHZ (1<<2)
-#define CLK_FLG_MAX_I2S_24576KHZ (1<<3)
-#define CLK_FLG_MAX_I2S_49152KHZ (1<<4)
-
-#define RK30_CLOCKS_DEFAULT_FLAGS (CLK_FLG_MAX_I2S_12288KHZ/*|CLK_FLG_EXT_27MHZ*/)
-#if defined(CONFIG_ARCH_RK3026)
-#define periph_pll_default periph_pll_768mhz
-#define codec_pll_default codec_pll_594mhz
-#else
-#define periph_pll_default periph_pll_297mhz
-#define codec_pll_default codec_pll_798mhz
-#endif
-//#define codec_pll_default codec_pll_1064mhz
-
-
-#endif
+++ /dev/null
-#include <plat/clkdev.h>
+++ /dev/null
-#include <plat/clock.h>
+++ /dev/null
-#ifndef __MACH_CONFIG_H
-#define __MACH_CONFIG_H
-#include <mach/board.h>
-
-//#define RK2926_TB_DEFAULT_CONFIG
-//#define RK2928_TB_DEFAULT_CONFIG
-//#define RK2926_V86_DEFAULT_CONFIG
-//#define RK2926_SDK_DEFAULT_CONFIG
-//#define RK2928_SDK_DEFAULT_CONFIG
-#define RK2928_PHONEPAD_DEFAULT_CONFIG
-
-
-/* camera id */
-#define BACK_SENSOR_0 NONE
-#define BACK_SENSOR_0_ADDR 0x00
-#define BACK_SENSOR_1 NONE
-#define BACK_SENSOR_1_ADDR 0x00
-#define BACK_SENSOR_2 NONE
-#define BACK_SENSOR_2_ADDR 0x00
-
-#define FRONT_SENSOR_0 RK29_CAM_SENSOR_GC0308
-#define FRONT_SENSOR_0_ADDR 0x42
-#define FRONT_SENSOR_1 RK29_CAM_SENSOR_OV2659
-#define FRONT_SENSOR_1_ADDR 0x60
-#define FRONT_SENSOR_2 RK29_CAM_SENSOR_HI704
-#define FRONT_SENSOR_2_ADDR 0x60
-
-enum {
- CAM_ID_BACK_SENSOR_0 = 0,
- CAM_ID_BACK_SENSOR_1,
- CAM_ID_BACK_SENSOR_2,
- CAM_ID_FRONT_SENSOR_0,
- CAM_ID_FRONT_SENSOR_1,
- CAM_ID_FRONT_SENSOR_2,
-};
-
-enum {
- GS_TYPE_NONE = 0,
- GS_TYPE_MMA8452,
- GS_TYPE_MMA7660,
- GS_TYPE_KXTIK,
- GS_TYPE_MAX,
-};
-enum {
- LS_TYPE_NONE = 0,
- LS_TYPE_AP321XX,
- LS_TYPE_MAX,
-};
-enum {
- PS_TYPE_NONE = 0,
- PS_TYPE_AP321XX,
- PS_TYPE_MAX,
-};
-enum {
- WIFI_NONE = 0,
- WIFI_USB_NONE = 1<<4,
- //here: add usb wifi type
- WIFI_USB_MAX,
- WIFI_SDIO_NONE = 1<<8,
- //here: add sdio wifi type
- WIFI_SDIO_MAX,
-};
-
-int pmic_dcdc_set(int index, int on);
-int pmic_ldo_set(int index, int on);
-
-/**************************** rk2926 top board ******************************/
-#if defined(RK2926_TB_DEFAULT_CONFIG)
-/* keyboard */
-enum{
- DEF_KEY_ADC = 1,
- DEF_PLAY_KEY = 0x000101a4,
- DEF_VOLDN_KEY = 0x000102b6,
- DEF_VOLUP_KEY = 1 | (1<<31),
- DEF_MENU_KEY = 100 | (1<<31),
- DEF_ESC_KEY = 255 | (1<<31),
- DEF_HOME_KEY = 425 | (1<<31),
- DEF_CAM_KEY = 576 | (1<<31),
-};
-/* backlight */
-enum{
- DEF_BL_PWM = 0,
- DEF_BL_REF = 1,
- DEF_BL_MIN = 60,
- DEF_BL_EN = 0x000002c1,
-};
-/* usb */
-enum {
- DEF_OTG_DRV = 0x000003c1,
- DEF_HOST_DRV = 0x000002b4,
-};
-/* lcd */
-enum {
- DEF_LCD_CABC = 0x000002c3,
- DEF_LCD_EN = -1,
- DEF_LCD_STD = -1,
-};
-
-#define DEF_LCD_PARAM {SCREEN_LVDS, OUT_D888_P666, \
- 65000000, 300000000, \
- 10, 100, 1024, 210, \
- 10, 10, 768, 18, \
- 202, 102, \
- 1, 0 }
-/* gsensor */
-enum {
- DEF_GS_TYPE = GS_TYPE_MMA8452,
- DEF_GS_I2C = 0,
- DEF_GS_ADDR = 0x1d,
- DEF_GS_IRQ = 0x008001b2,
- DEF_GS_PWR = -1,
-};
-#define DEF_GS_ORIG {-1, 0, 0, 0, 0, 1, 0,-1, 0}
-/* lsensor */
-enum {
- DEF_LS_TYPE = LS_TYPE_NONE,
- DEF_LS_I2C = -1,
- DEF_LS_ADDR = -1,
- DEF_LS_IRQ = -1,
- DEF_LS_PWR = -1,
-};
-/* psensor */
-enum {
- DEF_PS_TYPE = PS_TYPE_NONE,
- DEF_PS_I2C = -1,
- DEF_PS_ADDR = -1,
- DEF_PS_IRQ = -1,
- DEF_PS_PWR = -1,
-};
-/* camera */
-enum {
- DEF_FRONT_CAM_ID = CAM_ID_FRONT_SENSOR_1,
- DEF_FRONT_CAM_I2C = 0,
- DEF_FRONT_CAM_PWR = 0x000003b3,
-};
-enum {
- DEF_BACK_CAM_ID = -1,
- DEF_BACK_CAM_I2C = -1,
- DEF_BACK_CAM_PWR = -1,
-};
-/* pwm regulator */
-enum {
- DEF_REG_PWM = 1,
-};
-/* pmic */
-enum {
- DEF_PMIC_TYPE = PMIC_TYPE_TPS65910,
- DEF_PMIC_SLP = 0x000001a1,
- DEF_PMIC_IRQ = 0x000001b1,
- DEF_PMIC_I2C = 1,
- DEF_PMIC_ADDR = 0x2d,
-};
-/* tps656910_dcdc: vdd_cpu, vdd2, vdd3, vio
- * tps65910_ldo: vdig1, vdig2, vaux1, vaux2, vaux33, vmmc, vdac, vpll
- * act8931_dcdc: act_dcdc1, act_dcdc2, vdd_cpu
- * act8931_ldo: act_ldo1, act_ldo2, act_ldo3, act_ldo4
- */
-#define DEF_TPS65910_DCDC {1200000,1200000,1200000,1200000,0,0,3300000,3300000}
-#define DEF_TPS65910_LDO {1800000,1800000,0,0,0,0,0,0,0,0,0,0,1800000,1800000,2500000,2500000}
-#define DEF_ACT8931_DCDC {0,0,0,0,0,0}
-#define DEF_ACT8931_LDO {0,0,0,0,0,0,0,0}
-
-/* ion */
-enum {
- DEF_ION_SIZE = 80 * 1024 * 1024,
-};
-/* codec */
-enum {
- DEF_SPK_CTL = 0x000001a0,
- DEF_HP_DET = -1,
-};
-/* sdmmc */
-enum {
- DEF_SD_DET = 0x000102a7,
-};
-/* wifi */
-enum {
- DEF_WIFI_RST = -1,
- DEF_WIFI_PWR = -1,
- DEF_WIFI_TYPE = WIFI_NONE,
- DEF_WIFI_LDO = 5,
-};
-/* rtc */
-enum {
- DEF_RTC_I2C = 0,
- DEF_RTC_ADDR = 0x51,
- DEF_RTC_IRQ = -1,
-};
-/* charge */
-enum {
- DEF_CHG_ADC = -1,
- DEF_DC_DET = -1,
- DEF_BAT_LOW = -1,
- DEF_CHG_OK = -1,
- DEF_CHG_SET = -1,
- DEF_CHG_SEL = -1,
-};
-
-/* global */
-enum {
- DEF_IS_PHONEPAD = 0,
- DEF_PWR_ON = 0x000001a2,
-};
-/**************************** rk2928 top board ******************************/
-#elif defined(RK2928_TB_DEFAULT_CONFIG)
-/* keyboard */
-enum{
- DEF_KEY_ADC = 1,
- DEF_PLAY_KEY = 0x000103c5,
- DEF_VOLDN_KEY = 0x000100d1,
- DEF_VOLUP_KEY = 1 | (1<<31),
- DEF_MENU_KEY = 135 | (1<<31),
- DEF_ESC_KEY = 334 | (1<<31),
- DEF_HOME_KEY = 550 | (1<<31),
- DEF_CAM_KEY = 700 | (1<<31),
-};
-/* backlight */
-enum{
- DEF_BL_PWM = 0,
- DEF_BL_REF = 1,
- DEF_BL_MIN = 60,
- DEF_BL_EN = 0x000003c4,
-};
-/* usb */
-enum {
- DEF_OTG_DRV = 0x000003c1,
- DEF_HOST_DRV = 0x000001b2,
-};
-/* lcd */
-enum {
- DEF_LCD_CABC = 0x000002d1,
- DEF_LCD_EN = -1,
- DEF_LCD_STD = -1,
-};
-
-#define DEF_LCD_PARAM {SCREEN_LVDS, OUT_D888_P666, \
- 65000000, 300000000, \
- 10, 100, 1024, 210, \
- 10, 10, 768, 18, \
- 202, 102, \
- 1, 0 }
-/* gsensor */
-enum {
- DEF_GS_TYPE = GS_TYPE_MMA8452,
- DEF_GS_I2C = 0,
- DEF_GS_ADDR = 0x1d,
- DEF_GS_IRQ = 0x008003d1,
- DEF_GS_PWR = -1,
-};
-#define DEF_GS_ORIG {-1, 0, 0, 0, 0, 1, 0,-1, 0}
-/* lsensor */
-enum {
- DEF_LS_TYPE = LS_TYPE_NONE,
- DEF_LS_I2C = -1,
- DEF_LS_ADDR = -1,
- DEF_LS_IRQ = -1,
- DEF_LS_PWR = -1,
-};
-/* psensor */
-enum {
- DEF_PS_TYPE = PS_TYPE_NONE,
- DEF_PS_I2C = -1,
- DEF_PS_ADDR = -1,
- DEF_PS_IRQ = -1,
- DEF_PS_PWR = -1,
-};
-
-/* camera */
-enum {
- DEF_FRONT_CAM_ID = CAM_ID_FRONT_SENSOR_1,
- DEF_FRONT_CAM_I2C = 0,
- DEF_FRONT_CAM_PWR = 0x000003b3,
-};
-enum {
- DEF_BACK_CAM_ID = -1,
- DEF_BACK_CAM_I2C = -1,
- DEF_BACK_CAM_PWR = -1,
-};
-
-/* pwm regulator */
-enum {
- DEF_REG_PWM = 1,
-};
-/* pmic */
-enum {
- DEF_PMIC_TYPE = PMIC_TYPE_TPS65910,
- DEF_PMIC_SLP = 0x000003d2,
- DEF_PMIC_IRQ = 0x000003c6,
- DEF_PMIC_I2C = 1,
- DEF_PMIC_ADDR = 0x2d,
-};
-/* tps656910_dcdc: vdd_cpu, vdd2, vdd3, vio
- * tps65910_ldo: vdig1, vdig2, vaux1, vaux2, vaux33, vmmc, vdac, vpll
- * act8931_dcdc: act_dcdc1, act_dcdc2, vdd_cpu
- * act8931_ldo: act_ldo1, act_ldo2, act_ldo3, act_ldo4
- */
-#define DEF_TPS65910_DCDC {1200000,1200000,1200000,1200000,0,0,3300000,3300000}
-#define DEF_TPS65910_LDO {1800000,1800000,0,0,0,0,0,0,0,0,0,0,1800000,1800000,2500000,2500000}
-#define DEF_ACT8931_DCDC {0,0,0,0,0,0}
-#define DEF_ACT8931_LDO {0,0,0,0,0,0,0,0}
-/* ion */
-enum {
- DEF_ION_SIZE = 80 * 1024 * 1024,
-};
-/* codec */
-enum {
- DEF_SPK_CTL = 0x000003d4,
- DEF_HP_DET = -1,
-};
-/* sdmmc */
-enum {
- DEF_SD_DET = 0x000101c1,
-};
-/* wifi */
-enum {
- DEF_WIFI_RST = -1,
- DEF_WIFI_PWR = -1,
- DEF_WIFI_TYPE = WIFI_NONE,
- DEF_WIFI_LDO = 5,
-};
-/* rtc */
-enum {
- DEF_RTC_I2C = 0,
- DEF_RTC_ADDR = 0x51,
- DEF_RTC_IRQ = -1,
-};
-/* charge */
-enum {
- DEF_CHG_ADC = -1,
- DEF_DC_DET = -1,
- DEF_BAT_LOW = -1,
- DEF_CHG_OK = -1,
- DEF_CHG_SET = -1,
- DEF_CHG_SEL = -1,
-};
-
-/* global */
-enum {
- DEF_IS_PHONEPAD = 0,
- DEF_PWR_ON = 0x000001b4,
-};
-
-/**************************** rk2926 sdk(m713) ******************************/
-#elif defined(RK2926_SDK_DEFAULT_CONFIG)
-/* keyboard */
-enum{
- DEF_KEY_ADC = 1,
- DEF_PLAY_KEY = 0x000101a4,
- DEF_VOLDN_KEY = 512 | (1<<31),
- DEF_VOLUP_KEY = 1 | (1<<31),
- DEF_MENU_KEY = 0 | (1<<31),
- DEF_ESC_KEY = 0 | (1<<31),
- DEF_HOME_KEY = 0 | (1<<31),
- DEF_CAM_KEY = 0 | (1<<31),
-};
-/* backlight */
-enum{
- DEF_BL_PWM = 0,
- DEF_BL_REF = 0,
- DEF_BL_MIN = 80,
- DEF_BL_EN = -1,
-};
-
-/* usb */
-enum {
- DEF_OTG_DRV = -1,
- DEF_HOST_DRV = -1,
-};
-/* lcd */
-enum {
- DEF_LCD_CABC = -1,
- DEF_LCD_EN = 0x000101b3,
- DEF_LCD_STD = -1,
-};
-
-#define DEF_LCD_PARAM {SCREEN_RGB, OUT_P666, \
- 33000000, 150000000, \
- 30, 10, 800, 210, \
- 13, 10, 480, 22, \
- 154, 85, \
- 1, 0 }
-/* gsensor */
-enum {
- DEF_GS_TYPE = GS_TYPE_MMA7660,
- DEF_GS_I2C = 1,
- DEF_GS_ADDR = 0x4c,
- DEF_GS_IRQ = 0x008001b2,
- DEF_GS_PWR = -1,
-};
-#define DEF_GS_ORIG {-1, 0, 0, 0, 0, -1, 0, 1, 0}
-/* lsensor */
-enum {
- DEF_LS_TYPE = LS_TYPE_NONE,
- DEF_LS_I2C = -1,
- DEF_LS_ADDR = -1,
- DEF_LS_IRQ = -1,
- DEF_LS_PWR = -1,
-};
-/* psensor */
-enum {
- DEF_PS_TYPE = PS_TYPE_NONE,
- DEF_PS_I2C = -1,
- DEF_PS_ADDR = -1,
- DEF_PS_IRQ = -1,
- DEF_PS_PWR = -1,
-};
-
-/* camera */
-enum {
- DEF_FRONT_CAM_ID = CAM_ID_FRONT_SENSOR_0,
- DEF_FRONT_CAM_I2C = 1,
- DEF_FRONT_CAM_PWR = 0x000003b3,
-};
-enum {
- DEF_BACK_CAM_ID = -1,
- DEF_BACK_CAM_I2C = -1,
- DEF_BACK_CAM_PWR = -1,
-};
-
-/* pwm regulator */
-enum {
- DEF_REG_PWM = 1,
-};
-/* pmic */
-enum {
- DEF_PMIC_TYPE = PMIC_TYPE_ACT8931,
- DEF_PMIC_SLP = 0x000001a1,
- DEF_PMIC_IRQ = 0x000001b1,
- DEF_PMIC_I2C = 0,
- DEF_PMIC_ADDR = 0x5b,
-};
-/* tps656910_dcdc: vdd_cpu, vdd2, vdd3, vio
- * tps65910_ldo: vdig1, vdig2, vaux1, vaux2, vaux33, vmmc, vdac, vpll
- * act8931_dcdc: act_dcdc1, act_dcdc2, vdd_cpu
- * act8931_ldo: act_ldo1, act_ldo2, act_ldo3, act_ldo4
- */
-#define DEF_TPS65910_DCDC {1200000,1200000,1200000,1200000,0,0,3300000,3300000}
-#define DEF_TPS65910_LDO {1500000,1500000,1200000,1200000,2800000,2800000,3300000,3300000,3300000,3300000,3300000,3300000,0,0,0,0}
-#define DEF_ACT8931_DCDC {3300000,3300000,1500000,1500000,1200000,1200000}
-#define DEF_ACT8931_LDO {2800000,2800000,1800000,1800000,3000000,3000000,3300000,3300000}
-/* ion */
-enum {
- DEF_ION_SIZE = 80 * 1024 * 1024,
-};
-/* codec */
-enum {
- DEF_SPK_CTL = 0x000001a0,
- DEF_HP_DET = -1,
-};
-/* sdmmc */
-enum {
- DEF_SD_DET = 0x000102a7,
-};
-/* wifi */
-enum {
- DEF_WIFI_RST = -1,
- DEF_WIFI_PWR = -1,
- DEF_WIFI_TYPE = WIFI_NONE,
- DEF_WIFI_LDO = 3,
-};
-/* rtc */
-enum {
- DEF_RTC_I2C = 0,
- DEF_RTC_ADDR = 0x51,
- DEF_RTC_IRQ = 0x008001a5,
-};
-/* charge */
-enum {
- DEF_CHG_ADC = 0,
- DEF_DC_DET = -1,
- DEF_BAT_LOW = -1,
- DEF_CHG_OK = -1,
- DEF_CHG_SET = -1,
- DEF_CHG_SEL = 0x000001a1,
-};
-
-/* global */
-enum {
- DEF_IS_PHONEPAD = 0,
- DEF_PWR_ON = 0x000001a2,
-};
-/**************************** rk2926 sdk(v86) ******************************/
-#elif defined(RK2926_V86_DEFAULT_CONFIG)
-/* keyboard */
-enum{
- DEF_KEY_ADC = 1,
- DEF_PLAY_KEY = 0x000101a4,
- DEF_VOLDN_KEY = 512 | (1<<31),
- DEF_VOLUP_KEY = 1 | (1<<31),
- DEF_MENU_KEY = 0 | (1<<31),
- DEF_ESC_KEY = 0 | (1<<31),
- DEF_HOME_KEY = 0 | (1<<31),
- DEF_CAM_KEY = 0 | (1<<31),
-};
-/* backlight */
-enum{
- DEF_BL_PWM = 0,
- DEF_BL_REF = 0,
- DEF_BL_MIN = 80,
- DEF_BL_EN = 0x000003c1,
-};
-
-/* usb */
-enum {
- DEF_OTG_DRV = -1,
- DEF_HOST_DRV = -1,
-};
-/* lcd */
-enum {
- DEF_LCD_CABC = -1,
- DEF_LCD_EN = 0x000101b3,
- DEF_LCD_STD = -1,
-};
-
-#define DEF_LCD_PARAM {SCREEN_RGB, OUT_P666, \
- 33000000, 15000000, \
- 30, 10, 800, 210, \
- 13, 10, 480, 22, \
- 154, 85, \
- 0, 0 }
-/* gsensor */
-enum {
- DEF_GS_TYPE = GS_TYPE_MMA7660,
- DEF_GS_I2C = 1,
- DEF_GS_ADDR = 0x4c,
- DEF_GS_IRQ = 0x008001b2,
- DEF_GS_PWR = -1,
-};
-#define DEF_GS_ORIG {0, 1, 0, 0, 0, -1, 1, 0, 0}
-/* lsensor */
-enum {
- DEF_LS_TYPE = LS_TYPE_NONE,
- DEF_LS_I2C = -1,
- DEF_LS_ADDR = -1,
- DEF_LS_IRQ = -1,
- DEF_LS_PWR = -1,
-};
-/* psensor */
-enum {
- DEF_PS_TYPE = PS_TYPE_NONE,
- DEF_PS_I2C = -1,
- DEF_PS_ADDR = -1,
- DEF_PS_IRQ = -1,
- DEF_PS_PWR = -1,
-};
-
-/* camera */
-enum {
- DEF_FRONT_CAM_ID = CAM_ID_FRONT_SENSOR_0,
- DEF_FRONT_CAM_I2C = 1,
- DEF_FRONT_CAM_PWR = 0x000003b3,
-};
-enum {
- DEF_BACK_CAM_ID = -1,
- DEF_BACK_CAM_I2C = -1,
- DEF_BACK_CAM_PWR = -1,
-};
-
-/* pwm regulator */
-enum {
- DEF_REG_PWM = 1,
-};
-/* pmic */
-enum {
- DEF_PMIC_TYPE = PMIC_TYPE_TPS65910,
- DEF_PMIC_SLP = 0x000001a1,
- DEF_PMIC_IRQ = 0x000001b1,
- DEF_PMIC_I2C = 0,
- DEF_PMIC_ADDR = 0x2d,
-};
-/* tps656910_dcdc: vdd_cpu, vdd2, vdd3, vio
- * tps65910_ldo: vdig1, vdig2, vaux1, vaux2, vaux33, vmmc, vdac, vpll
- * act8931_dcdc: act_dcdc1, act_dcdc2, vdd_cpu
- * act8931_ldo: act_ldo1, act_ldo2, act_ldo3, act_ldo4
- */
-#define DEF_TPS65910_DCDC {1200000,1200000,1200000,1200000,0,0,3300000,3300000}
-#define DEF_TPS65910_LDO {1500000,1500000,1200000,1200000,2800000,2800000,3300000,3300000,3300000,3300000,3300000,3300000,0,0,0,0}
-#define DEF_ACT8931_DCDC {3300000,3300000,1500000,1500000,1200000,1200000}
-#define DEF_ACT8931_LDO {2800000,2800000,1800000,1800000,3000000,3000000,3300000,3300000}
-/* ion */
-enum {
- DEF_ION_SIZE = 80 * 1024 * 1024,
-};
-/* codec */
-enum {
- DEF_SPK_CTL = 0x000001a0,
- DEF_HP_DET = -1,
-};
-/* sdmmc */
-enum {
- DEF_SD_DET = 0x000102a7,
-};
-/* wifi */
-enum {
- DEF_WIFI_RST = -1,
- DEF_WIFI_PWR = -1,
- DEF_WIFI_TYPE = WIFI_NONE,
- DEF_WIFI_LDO = 5,
-};
-/* rtc */
-enum {
- DEF_RTC_I2C = 0,
- DEF_RTC_ADDR = 0x51,
- DEF_RTC_IRQ = -1,
-};
-/* charge */
-enum {
- DEF_CHG_ADC = 0,
- DEF_DC_DET = 0x001101a5,
- DEF_BAT_LOW = -1,
- DEF_CHG_OK = -1,
- DEF_CHG_SET = -1,
- DEF_CHG_SEL = -1,
-};
-
-/* global */
-enum {
- DEF_IS_PHONEPAD = 0,
- DEF_PWR_ON = 0x000001a2,
-};
-/**************************** rk2928 sdk ******************************/
-#elif defined(RK2928_SDK_DEFAULT_CONFIG)
-/* keyboard */
-enum{
- DEF_KEY_ADC = 1,
- DEF_PLAY_KEY = 0x000100d1,
- DEF_VOLDN_KEY = 512 | (1<<31),
- DEF_VOLUP_KEY = 1 | (1<<31),
- DEF_MENU_KEY = 0 | (1<<31),
- DEF_ESC_KEY = 0 | (1<<31),
- DEF_HOME_KEY = 0 | (1<<31),
- DEF_CAM_KEY = 0 | (1<<31),
-};
-/* backlight */
-enum{
- DEF_BL_PWM = 0,
- DEF_BL_REF = 0,
- DEF_BL_MIN = 80,
- DEF_BL_EN = 0x000003c5,
-};
-/* usb */
-enum {
- DEF_OTG_DRV = -1,
- DEF_HOST_DRV = -1,
-};
-/* lcd */
-enum {
- DEF_LCD_CABC = -1,
- DEF_LCD_EN = 0x000103b3,
- DEF_LCD_STD = -1,
-};
-
-#define DEF_LCD_PARAM {SCREEN_RGB, OUT_P666, \
- 33000000, 150000000, \
- 30, 10, 800, 210, \
- 13, 10, 480, 22, \
- 154, 85, \
- 1, 0 }
-/* gsensor */
-enum {
- DEF_GS_TYPE = GS_TYPE_MMA7660,
- DEF_GS_I2C = 1,
- DEF_GS_ADDR = 0x4c,
- DEF_GS_IRQ = 0x008003d1,
- DEF_GS_PWR = -1,
-};
-#define DEF_GS_ORIG {-1, 0, 0, 0, 0, 1, 0, -1, 0}
-/* lsensor */
-enum {
- DEF_LS_TYPE = LS_TYPE_NONE,
- DEF_LS_I2C = -1,
- DEF_LS_ADDR = -1,
- DEF_LS_IRQ = -1,
- DEF_LS_PWR = -1,
-};
-/* psensor */
-enum {
- DEF_PS_TYPE = PS_TYPE_NONE,
- DEF_PS_I2C = -1,
- DEF_PS_ADDR = -1,
- DEF_PS_IRQ = -1,
- DEF_PS_PWR = -1,
-};
-
-/* camera */
-enum {
- DEF_FRONT_CAM_ID = CAM_ID_FRONT_SENSOR_0,
- DEF_FRONT_CAM_I2C = 1,
- DEF_FRONT_CAM_PWR = 0x000003d7,
-};
-enum {
- DEF_BACK_CAM_ID = -1,
- DEF_BACK_CAM_I2C = -1,
- DEF_BACK_CAM_PWR = -1,
-};
-
-/* pwm regulator */
-enum {
- DEF_REG_PWM = 2,
-};
-/* pmic */
-enum {
- DEF_PMIC_TYPE = PMIC_TYPE_TPS65910,
- DEF_PMIC_SLP = 0x000000d0,
- DEF_PMIC_IRQ = 0x000003c6,
- DEF_PMIC_I2C = 0,
- DEF_PMIC_ADDR = 0x5b,
-};
-/* tps656910_dcdc: vdd_cpu, vdd2, vdd3, vio
- * tps65910_ldo: vdig1, vdig2, vaux1, vaux2, vaux33, vmmc, vdac, vpll
- * act8931_dcdc: act_dcdc1, act_dcdc2, vdd_cpu
- * act8931_ldo: act_ldo1, act_ldo2, act_ldo3, act_ldo4
- */
-#define DEF_TPS65910_DCDC {1200000,1200000,1200000,1200000,0,0,3300000,3300000}
-#define DEF_TPS65910_LDO {1500000,1500000,1200000,1200000,2800000,2800000,3300000,3300000,3300000,3300000,3300000,3300000,0,0,0,0}
-#define DEF_ACT8931_DCDC {3300000,3300000,1500000,1500000,1200000,1200000}
-#define DEF_ACT8931_LDO {2800000,2800000,1800000,1800000,3000000,3000000,3300000,3300000}
-/* ion */
-enum {
- DEF_ION_SIZE = 80 * 1024 * 1024,
-};
-/* codec */
-enum {
- DEF_SPK_CTL = 0x000003d4,
- DEF_HP_DET = -1,
-};
-/* sdmmc */
-enum {
- DEF_SD_DET = 0x000101c1,
-};
-/* wifi */
-enum {
- DEF_WIFI_RST = -1,
- DEF_WIFI_PWR = -1,
- DEF_WIFI_TYPE = WIFI_NONE,
- DEF_WIFI_LDO = 3,
-};
-/* rtc */
-enum {
- DEF_RTC_I2C = 0,
- DEF_RTC_ADDR = 0x51,
- DEF_RTC_IRQ = 0x008001a5,
-};
-/* charge */
-enum {
- DEF_CHG_ADC = 0,
- DEF_DC_DET = 0x000101b4,
- DEF_BAT_LOW = -1,
- DEF_CHG_OK = 0x000001a0,
- DEF_CHG_SET = -1,
- DEF_CHG_SEL = 0x000000d0,
-};
-
-/* global */
-enum {
- DEF_IS_PHONEPAD = 0,
- DEF_PWR_ON = 0x000001a1,
-};
-/**************************** rk2928 phonepad ******************************/
-#elif defined(RK2928_PHONEPAD_DEFAULT_CONFIG)
-/* keyboard */
-enum{
- DEF_KEY_ADC = 1,
- DEF_PLAY_KEY = 0x000101a4,
- DEF_VOLDN_KEY = 512 | (1<<31),
- DEF_VOLUP_KEY = 1 | (1<<31),
- DEF_MENU_KEY = 0 | (1<<31),
- DEF_ESC_KEY = 0 | (1<<31),
- DEF_HOME_KEY = 0 | (1<<31),
- DEF_CAM_KEY = 0 | (1<<31),
-};
-/* backlight */
-enum{
- DEF_BL_PWM = 0,
- DEF_BL_REF = 1,
- DEF_BL_MIN = 80,
- DEF_BL_EN = 0x000001b0,
-};
-/* usb */
-enum {
- DEF_OTG_DRV = 0x000003c1,
- DEF_HOST_DRV = -1,
-};
-/* lcd */
-enum {
- DEF_LCD_CABC = -1,
- DEF_LCD_EN = 0x000100c3,
- DEF_LCD_STD = -1,
-};
-
-#define DEF_LCD_PARAM {SCREEN_RGB, OUT_P666, \
- 30000000, 150000000, \
- 48, 88, 800, 40, \
- 3, 32, 480, 13, \
- 154, 85, \
- 1, 0 }
-/* gsensor */
-enum {
- DEF_GS_TYPE = GS_TYPE_KXTIK,
- DEF_GS_I2C = 1,
- DEF_GS_ADDR = 0x0f,
- DEF_GS_IRQ = 0x008003d1,
- DEF_GS_PWR = -1,
-};
-#define DEF_GS_ORIG {-1, 0, 0, 0, 0, -1, 0, 1, 0}
-/* lsensor */
-enum {
- DEF_LS_TYPE = LS_TYPE_AP321XX,
- DEF_LS_I2C = 1,
- DEF_LS_ADDR = 0x1e,
- DEF_LS_IRQ = 0x008000c6,
- DEF_LS_PWR = -1,
-};
-/* psensor */
-enum {
- DEF_PS_TYPE = PS_TYPE_AP321XX,
- DEF_PS_I2C = 1,
- DEF_PS_ADDR = 0x1e,
- DEF_PS_IRQ = 0x008000c6,
- DEF_PS_PWR = -1,
-};
-
-/* camera */
-enum {
- DEF_FRONT_CAM_ID = CAM_ID_FRONT_SENSOR_2,
- DEF_FRONT_CAM_I2C = 1,
- DEF_FRONT_CAM_PWR = 0x000003b3,
-};
-enum {
- DEF_BACK_CAM_ID = -1,
- DEF_BACK_CAM_I2C = -1,
- DEF_BACK_CAM_PWR = -1,
-};
-
-/* pwm regulator */
-enum {
- DEF_REG_PWM = 2,
-};
-/* pmic */
-enum {
- DEF_PMIC_TYPE = PMIC_TYPE_TPS65910,
- DEF_PMIC_SLP = 0x000001a1,
- DEF_PMIC_IRQ = 0x000003c6,
- DEF_PMIC_I2C = 0,
- DEF_PMIC_ADDR = 0x2d,
-};
-/* tps656910_dcdc: vdd_cpu, vdd2, vdd3, vio
- * tps65910_ldo: vdig1, vdig2, vaux1, vaux2, vaux33, vmmc, vdac, vpll
- * act8931_dcdc: act_dcdc1, act_dcdc2, vdd_cpu
- * act8931_ldo: act_ldo1, act_ldo2, act_ldo3, act_ldo4
- */
-#define DEF_TPS65910_DCDC {1200000,1200000,1200000,1200000,0,0,3300000,3300000}
-#define DEF_TPS65910_LDO {1500000,1500000,1200000,1200000,2800000,2800000,3300000,3300000,3300000,3300000,3300000,3300000,0,0,0,0}
-#define DEF_ACT8931_DCDC {0,0,0,0,0,0}
-#define DEF_ACT8931_LDO {0,0,0,0,0,0,0,0}
-/* ion */
-enum {
- DEF_ION_SIZE = 80 * 1024 * 1024,
-};
-/* codec */
-enum {
- DEF_SPK_CTL = 0x000003d4,
- DEF_HP_DET = -1,
-};
-/* sdmmc */
-enum {
- DEF_SD_DET = 0x000101c1,
-};
-/* wifi */
-enum {
- DEF_WIFI_RST = -1,
- DEF_WIFI_PWR = -1,
- DEF_WIFI_TYPE = WIFI_NONE,
- DEF_WIFI_LDO = -1,
-};
-/* rtc */
-enum {
- DEF_RTC_I2C = 0,
- DEF_RTC_ADDR = 0x51,
- DEF_RTC_IRQ = 0x008001a5,
-};
-/* charge */
-enum {
- DEF_CHG_ADC = 0,
- DEF_DC_DET = 0x001101a5,
- DEF_BAT_LOW = -1,
- DEF_CHG_OK = 0x002001a0,
- DEF_CHG_SET = -1,
- DEF_CHG_SEL = -1,
-};
-
-/* global */
-enum {
- DEF_IS_PHONEPAD = 1,
- DEF_PWR_ON = 0x000001a2,
-};
-
-
-/**************************** other ******************************/
-#else
-/* keyboard */
-enum{
- DEF_KEY_ADC = -1,
- DEF_PLAY_KEY = 0x80000000,
- DEF_VOLDN_KEY = 0x80000000,
- DEF_VOLUP_KEY = 0x80000000,
- DEF_MENU_KEY = 0x80000000,
- DEF_ESC_KEY = 0x80000000,
- DEF_HOME_KEY = 0x80000000,
- DEF_CAM_KEY = 0x80000000,
-};
-/* backlight */
-enum{
- DEF_BL_PWM = -1,
- DEF_BL_REF = 0,
- DEF_BL_MIN = 0,
- DEF_BL_EN = -1,
-};
-/* usb */
-enum {
- DEF_OTG_DRV = -1,
- DEF_HOST_DRV = -1,
-};
-/* lcd */
-enum {
- DEF_LCD_CABC = -1,
- DEF_LCD_EN = -1,
- DEF_LCD_STD = -1,
-};
-
-#define DEF_LCD_PARAM {0, 0, \
- 0, 0, \
- 0, 0, 0, 0, \
- 0, 0, 0, 0, \
- 0, 0, \
- 0, 0 }
-/* gsensor */
-enum {
- DEF_GS_TYPE = GS_TYPE_NONE,
- DEF_GS_I2C = -1,
- DEF_GS_ADDR = -1,
- DEF_GS_IRQ = -1,
- DEF_GS_PWR = -1,
-};
-#define DEF_GS_ORIG {0, 0, 0, 0, 0, 0, 0, 0, 0}
-/* lsensor */
-enum {
- DEF_LS_TYPE = LS_TYPE_NONE,
- DEF_LS_I2C = -1,
- DEF_LS_ADDR = -1,
- DEF_LS_IRQ = -1,
- DEF_LS_PWR = -1,
-};
-/* psensor */
-enum {
- DEF_PS_TYPE = PS_TYPE_NONE,
- DEF_PS_I2C = -1,
- DEF_PS_ADDR = -1,
- DEF_PS_IRQ = -1,
- DEF_PS_PWR = -1,
-};
-
-/* camera */
-enum {
- DEF_FRONT_CAM_ID = -1,
- DEF_FRONT_CAM_I2C = -1,
- DEF_FRONT_CAM_PWR = -1,
-};
-enum {
- DEF_BACK_CAM_ID = -1,
- DEF_BACK_CAM_I2C = -1,
- DEF_BACK_CAM_PWR = -1,
-};
-
-/* pwm regulator */
-enum {
- DEF_REG_PWM = -1,
-};
-/* pmic */
-enum {
- DEF_PMIC_TYPE = PMIC_TYPE_NONE,
- DEF_PMIC_SLP = -1,
- DEF_PMIC_IRQ = -1,
- DEF_PMIC_I2C = -1,
- DEF_PMIC_ADDR = -1,
-};
-/* tps656910_dcdc: vdd_cpu, vdd2, vdd3, vio
- * tps65910_ldo: vdig1, vdig2, vaux1, vaux2, vaux33, vmmc, vdac, vpll
- * act8931_dcdc: act_dcdc1, act_dcdc2, vdd_cpu
- * act8931_ldo: act_ldo1, act_ldo2, act_ldo3, act_ldo4
- */
-#define DEF_TPS65910_DCDC {0,0,0,0,0,0,0,0}
-#define DEF_TPS65910_LDO {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}
-#define DEF_ACT8931_DCDC {0,0,0,0,0,0}
-#define DEF_ACT8931_LDO {0,0,0,0,0,0,0,0}
-/* ion */
-enum {
- DEF_ION_SIZE = 80 * 1024 * 1024,
-};
-/* codec */
-enum {
- DEF_SPK_CTL = -1,
- DEF_HP_DET = -1,
-};
-/* sdmmc */
-enum {
- DEF_SD_DET = -1,
-};
-/* wifi */
-enum {
- DEF_WIFI_RST = -1,
- DEF_WIFI_PWR = -1,
- DEF_WIFI_TYPE = WIFI_NONE,
- DEF_WIFI_LDO = -1,
-};
-/* rtc */
-enum {
- DEF_RTC_I2C = -1,
- DEF_RTC_ADDR = -1,
- DEF_RTC_IRQ = -1,
-};
-/* charge */
-enum {
- DEF_CHG_ADC = -1,
- DEF_DC_DET = -1,
- DEF_BAT_LOW = -1,
- DEF_CHG_OK = -1,
- DEF_CHG_SET = -1,
- DEF_CHG_SEL = -1,
-};
-
-/* global */
-enum {
- DEF_IS_PHONEPAD = 0,
- DEF_PWR_ON = -1,
-};
-#endif
-
-int inline otg_drv_init(int on);
-void inline otg_drv_on(void);
-void inline otg_drv_off(void);
-
-int inline host_drv_init(int on);
-void inline host_drv_on(void);
-void inline host_drv_off(void);
-
-#endif
+++ /dev/null
-#ifndef __MACH_CPU_H
-#define __MACH_CPU_H
-
-#include <plat/cpu.h>
-
-static inline void soc_gpio_init(void)
-{
- writel_relaxed(readl_relaxed(RK2928_GPIO3_BASE + 0x04) & (~0x07), RK2928_GPIO3_BASE + 0x04);
-}
-
-#endif
+++ /dev/null
-#ifndef __MACH_CPU_AXI_H
-#define __MACH_CPU_AXI_H
-
-#include <plat/cpu_axi.h>
-
-#define CPU_AXI_BUS_BASE RK2928_CPU_AXI_BUS_BASE
-
-#define CPU_AXI_CPU0_QOS_BASE (CPU_AXI_BUS_BASE + 0x0080)
-#define CPU_AXI_CPU1R_QOS_BASE (CPU_AXI_BUS_BASE + 0x0180)
-#define CPU_AXI_CPU1W_QOS_BASE (CPU_AXI_BUS_BASE + 0x0380)
-#define CPU_AXI_PERI_QOS_BASE (CPU_AXI_BUS_BASE + 0x4000)
-#define CPU_AXI_GPU_QOS_BASE (CPU_AXI_BUS_BASE + 0x5000)
-#define CPU_AXI_VPU_QOS_BASE (CPU_AXI_BUS_BASE + 0x6000)
-#define CPU_AXI_LCDC0_QOS_BASE (CPU_AXI_BUS_BASE + 0x7000)
-#define CPU_AXI_CIF0_QOS_BASE (CPU_AXI_BUS_BASE + 0x7200)
-#define CPU_AXI_RGA_QOS_BASE (CPU_AXI_BUS_BASE + 0x7280)
-
-#endif
+++ /dev/null
-#ifndef __MACH_CRU_H
-#define __MACH_CRU_H
-
-enum rk_plls_id {
- APLL_ID = 0,
- DPLL_ID,
- CPLL_ID,
- GPLL_ID,
- END_PLL_ID,
-};
-
-/*****cru reg offset*****/
-
-#define CRU_MODE_CON 0x40
-#define CRU_CLKSEL_CON 0x44
-#define CRU_CLKGATE_CON 0xd0
-#define CRU_GLB_SRST_FST 0x100
-#define CRU_GLB_SRST_SND 0x104
-#define CRU_SOFTRST_CON 0x110
-
-#define PLL_CONS(id, i) ((id) * 0x10 + ((i) * 4))
-
-#define CRU_CLKSELS_CON_CNT (35)
-#define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON + ((i) * 4))
-
-#define CRU_CLKGATES_CON_CNT (10)
-#define CRU_CLKGATES_CON(i) (CRU_CLKGATE_CON + ((i) * 4))
-
-#define CRU_SOFTRSTS_CON_CNT (9)
-#define CRU_SOFTRSTS_CON(i) (CRU_SOFTRST_CON + ((i) * 4))
-
-#define CRU_MISC_CON (0x134)
-#define CRU_GLB_CNT_TH (0x140)
-
-/*PLL_CON 0,1,2*/
-#define PLL_PWR_ON (0)
-#define PLL_PWR_DN (1)
-#define PLL_BYPASS (1 << 15)
-#define PLL_NO_BYPASS (0 << 15)
-//con0
-#define PLL_BYPASS_SHIFT (15)
-
-#define PLL_POSTDIV1_MASK (0x7)
-#define PLL_POSTDIV1_SHIFT (12)
-#define PLL_FBDIV_MASK (0xfff)
-#define PLL_FBDIV_SHIFT (0)
-
-//con1
-#define PLL_RSTMODE_SHIFT (15)
-#define PLL_RST_SHIFT (14)
-#define PLL_PWR_DN_SHIFT (13)
-#define PLL_DSMPD_SHIFT (12)
-#define PLL_LOCK_SHIFT (10)
-
-#define PLL_POSTDIV2_MASK (0x7)
-#define PLL_POSTDIV2_SHIFT (6)
-#define PLL_REFDIV_MASK (0x3f)
-#define PLL_REFDIV_SHIFT (0)
-
-//con2
-#define PLL_FOUT4PHASE_PWR_DN_SHIFT (27)
-#define PLL_FOUTVCO_PWR_DN_SHIFT (26)
-#define PLL_FOUTPOSTDIV_PWR_DN_SHIFT (25)
-#define PLL_DAC_PWR_DN_SHIFT (24)
-
-#define PLL_FRAC_MASK (0xffffff)
-#define PLL_FRAC_SHIFT (0)
-
-/********************************************************************/
-#define CRU_GET_REG_BIT_VAL(reg, bits_shift) (((reg) >> (bits_shift)) & (0x1))
-#define CRU_GET_REG_BITS_VAL(reg, bits_shift, msk) (((reg) >> (bits_shift)) & (msk))
-#define CRU_SET_BIT(val, bits_shift) (((val) & (0x1)) << (bits_shift))
-#define CRU_SET_BITS(val, bits_shift, msk) (((val) & (msk)) << (bits_shift))
-#define CRU_W_MSK(bits_shift, msk) ((msk) << ((bits_shift) + 16))
-
-#define CRU_W_MSK_SETBITS(val, bits_shift, msk) (CRU_W_MSK(bits_shift, msk) \
- | CRU_SET_BITS(val, bits_shift, msk))
-#define CRU_W_MSK_SETBIT(val, bits_shift) (CRU_W_MSK(bits_shift, 0x1) \
- | CRU_SET_BIT(val, bits_shift))
-
-#define PLL_SET_REFDIV(val) CRU_W_MSK_SETBITS(val, PLL_REFDIV_SHIFT, PLL_REFDIV_MASK)
-#define PLL_SET_FBDIV(val) CRU_W_MSK_SETBITS(val, PLL_FBDIV_SHIFT, PLL_FBDIV_MASK)
-#define PLL_SET_POSTDIV1(val) CRU_W_MSK_SETBITS(val, PLL_POSTDIV1_SHIFT, PLL_POSTDIV1_MASK)
-#define PLL_SET_POSTDIV2(val) CRU_W_MSK_SETBITS(val, PLL_POSTDIV2_SHIFT, PLL_POSTDIV2_MASK)
-#define PLL_SET_FRAC(val) CRU_SET_BITS(val, PLL_FRAC_SHIFT, PLL_FRAC_MASK)
-
-#define PLL_GET_REFDIV(reg) CRU_GET_REG_BITS_VAL(reg, PLL_REFDIV_SHIFT, PLL_REFDIV_MASK)
-#define PLL_GET_FBDIV(reg) CRU_GET_REG_BITS_VAL(reg, PLL_FBDIV_SHIFT, PLL_FBDIV_MASK)
-#define PLL_GET_POSTDIV1(reg) CRU_GET_REG_BITS_VAL(reg, PLL_POSTDIV1_SHIFT, PLL_POSTDIV1_MASK)
-#define PLL_GET_POSTDIV2(reg) CRU_GET_REG_BITS_VAL(reg, PLL_POSTDIV2_SHIFT, PLL_POSTDIV2_MASK)
-#define PLL_GET_FRAC(reg) CRU_GET_REG_BITS_VAL(reg, PLL_FRAC_SHIFT, PLL_FRAC_MASK)
-
-//#define APLL_SET_BYPASS(val) CRU_SET_BIT(val, PLL_BYPASS_SHIFT)
-#define PLL_SET_DSMPD(val) CRU_W_MSK_SETBIT(val, PLL_DSMPD_SHIFT)
-#define PLL_GET_DSMPD(reg) CRU_GET_REG_BIT_VAL(reg, PLL_DSMPD_SHIFT)
-/*******************MODE BITS***************************/
-#define PLL_MODE_MSK(id) (0x1 << ((id) * 4))
-#define PLL_MODE_SHIFT(id) ((id) * 4)
-#define PLL_MODE_SLOW(id) (CRU_W_MSK_SETBIT(0x0, PLL_MODE_SHIFT(id)))
-#define PLL_MODE_NORM(id) (CRU_W_MSK_SETBIT(0x1, PLL_MODE_SHIFT(id)))
-/*******************CLKSEL0 BITS***************************/
-#define CLK_SET_DIV_CON_SUB1(val, bits_shift, msk) CRU_W_MSK_SETBITS((val - 1), bits_shift, msk)
-
-#define CPU_CLK_PLL_SEL_SHIFT (13)
-#define CORE_CLK_PLL_SEL_SHIFT (7)
-#define SEL_APLL (0)
-#define SEL_GPLL (1)
-#define CPU_SEL_PLL(plls) CRU_W_MSK_SETBIT(plls, CPU_CLK_PLL_SEL_SHIFT)
-#define CORE_SEL_PLL(plls) CRU_W_MSK_SETBIT(plls, CORE_CLK_PLL_SEL_SHIFT)
-
-#define ACLK_CPU_DIV_MASK (0x1f)
-#define ACLK_CPU_DIV_SHIFT (8)
-#define A9_CORE_DIV_MASK (0x1f)
-#define A9_CORE_DIV_SHIFT (0)
-
-#define RATIO_11 (1)
-#define RATIO_21 (2)
-#define RATIO_41 (4)
-#define RATIO_81 (8)
-
-#define ACLK_CPU_DIV(val) CLK_SET_DIV_CON_SUB1(val, ACLK_CPU_DIV_SHIFT, ACLK_CPU_DIV_MASK)
-#define CLK_CORE_DIV(val) CLK_SET_DIV_CON_SUB1(val, A9_CORE_DIV_SHIFT, A9_CORE_DIV_MASK)
-/*******************CLKSEL1 BITS***************************/
-#define PCLK_CPU_DIV_MASK (0x7)
-#define PCLK_CPU_DIV_SHIFT (12)
-#define HCLK_CPU_DIV_MASK (0x3)
-#define HCLK_CPU_DIV_SHIFT (8)
-#define ACLK_CORE_DIV_MASK (0x1)
-#define ACLK_CORE_DIV_SHIFT (4)
-#define CORE_PERIPH_DIV_MASK (0xf)
-#define CORE_PERIPH_DIV_SHIFT (0)
-
-#define PCLK_CPU_DIV(val) CLK_SET_DIV_CON_SUB1(val, PCLK_CPU_DIV_SHIFT, PCLK_CPU_DIV_MASK)
-#define HCLK_CPU_DIV(val) CLK_SET_DIV_CON_SUB1(val, HCLK_CPU_DIV_SHIFT, HCLK_CPU_DIV_MASK)
-#define ACLK_CORE_DIV(val) CLK_SET_DIV_CON_SUB1(val, ACLK_CORE_DIV_SHIFT, ACLK_CORE_DIV_MASK)
-#define CLK_CORE_PERI_DIV(val) CLK_SET_DIV_CON_SUB1(val, CORE_PERIPH_DIV_SHIFT, CORE_PERIPH_DIV_MASK)
-
-/*******************clksel10***************************/
-#define PERI_PLL_SEL_SHIFT 15
-#define PERI_PCLK_DIV_MASK (0x3)
-#define PERI_PCLK_DIV_SHIFT (12)
-#define PERI_HCLK_DIV_MASK (0x3)
-#define PERI_HCLK_DIV_SHIFT (8)
-#define PERI_ACLK_DIV_MASK (0x1f)
-#define PERI_ACLK_DIV_SHIFT (0)
-
-#define SEL_2PLL_GPLL (0)
-#define SEL_2PLL_CPLL (1)
-
-#define PERI_CLK_SEL_PLL(plls) CRU_W_MSK_SETBIT(plls, PERI_PLL_SEL_SHIFT)
-#define PERI_SET_ACLK_DIV(val) CLK_SET_DIV_CON_SUB1(val, PERI_ACLK_DIV_SHIFT, PERI_ACLK_DIV_MASK)
-/*******************gate BITS***************************/
-#define CLK_GATE_CLKID_CONS(i) CRU_CLKGATES_CON((i) / 16)
-
-#define CLK_GATE(i) (1 << ((i)%16))
-#define CLK_UN_GATE(i) (0)
-
-#define CLK_GATE_W_MSK(i) (1 << (((i) % 16) + 16))
-#define CLK_GATE_CLKID(i) (16 * (i))
-
-enum cru_clk_gate {
- /* SCU CLK GATE 0 CON */
- CLK_GATE_CORE_PERIPH = CLK_GATE_CLKID(0),
- CLK_GATE_CPU_GPLL,
- CLK_GATE_DDRPHY_SRC,
- CLK_GATE_ACLK_CPU,
-
- CLK_GATE_HCLK_CPU,
- CLK_GATE_PCLK_CPU,
- CLK_GATE_0RES6,
- CLK_GATE_ACLK_CORE,
-
- CLK_GATE_0RES8,
- CLK_GATE_I2S_SRC,
- CLK_GATE_I2S_FRAC_SRC,
- CLK_GATE_HCLK_VIO_PRE,
-
- CLK_GATE_0RES12,
- CLK_GATE_0RES13,
- CLK_GATE_0RES14,
- CLK_GATE_TESTCLK,
-
- CLK_GATE_TIMER0 = CLK_GATE_CLKID(1),
- CLK_GATE_TIMER1,
- CLK_GATE_1RES2,
- CLK_GATE_JTAG,
-
- CLK_GATE_1RES4,
- CLK_GATE_OTGPHY0,
- CLK_GATE_OTGPHY1,
- CLK_GATE_1RES7,
-
- CLK_GATE_UART0_SRC,
- CLK_GATE_UART0_FRAC_SRC,
- CLK_GATE_UART1_SRC,
- CLK_GATE_UART1_FRAC_SRC,
-
- CLK_GATE_UART2_SRC,
- CLK_GATE_UART2_FRAC_SRC,
- CLK_GATE_1RES14,
- CLK_GATE_1RES15,
-
- CLK_GATE_PERIPH_SRC = CLK_GATE_CLKID(2),
- CLK_GATE_ACLK_PERIPH,
- CLK_GATE_HCLK_PERIPH,
- CLK_GATE_PCLK_PERIPH,
-
- CLK_GATE_2RES4,
- CLK_GATE_2RES5,
- CLK_GATE_2RES6,
- CLK_GATE_2RES7,
-
- CLK_GATE_SARADC_SRC,
- CLK_GATE_SPI0_SRC,
- CLK_GATE_2RES10,
- CLK_GATE_MMC0_SRC,
-
- CLK_GATE_2RES12,
- CLK_GATE_SDIO_SRC,
- CLK_GATE_EMMC_SRC,
- CLK_GATE_2RES15,
-
- CLK_GATE_ACLK_VIO_SRC = CLK_GATE_CLKID(3),
- CLK_GATE_DCLK_LCDC0_SRC,
- CLK_GATE_SCLK_LCDC_SRC,
- CLK_GATE_PCLKIN_CIF,
-
- CLK_GATE_ACLK_GPS,
- CLK_GATE_3RES5,
- CLK_GATE_3RES6,
- CLK_GATE_CIF_OUT_SRC,
-
- CLK_GATE_PCLK_HDMI,
- CLK_GATE_ACLK_VEPU_SRC,
- CLK_GATE_HCLK_VEPU,
- CLK_GATE_ACLK_VDPU_SRC,
-
- CLK_GATE_HCLK_VDPU,
- CLK_GATE_GPU_PRE,
- CLK_GATE_3RES14,
- CLK_GATE_3RES15,
-
- CLK_GATE_HCLK_PERI_AXI_MATRIX = CLK_GATE_CLKID(4),
- CLK_GATE_PCLK_PERI_AXI_MATRIX,
- CLK_GATE_ACLK_CPU_PERI,
- CLK_GATE_ACLK_PERI_AXI_MATRIX,
-
- CLK_GATE_4RES4,
- CLK_GATE_4RES5,
- CLK_GATE_4RES6,
- CLK_GATE_4RES7,
-
- CLK_GATE_4RES8,
- CLK_GATE_4RES9,
- CLK_GATE_ACLK_STRC_SYS,
- CLK_GATE_4RES11,
-
- CLK_GATE_ACLK_INTMEM,
- CLK_GATE_4RES13,
- CLK_GATE_4RES14,
- CLK_GATE_4RES15,
-
- CLK_GATE_5RES0 = CLK_GATE_CLKID(5),
- CLK_GATE_ACLK_DMAC2,
- CLK_GATE_PCLK_EFUSE,
- CLK_GATE_5RES3,
-
- CLK_GATE_PCLK_GRF,
- CLK_GATE_5RES5,
- CLK_GATE_HCLK_ROM,
- CLK_GATE_PCLK_DDRUPCTL,
-
- CLK_GATE_5RES8,
- CLK_GATE_HCLK_NANDC,
- CLK_GATE_HCLK_SDMMC0,
- CLK_GATE_HCLK_SDIO,
-
- CLK_GATE_5RES12,
- CLK_GATE_HCLK_OTG0,
- CLK_GATE_PCLK_ACODEC,
- CLK_GATE_5RES15,
-
- CLK_GATE_ACLK_LCDC0 = CLK_GATE_CLKID(6),
- CLK_GATE_HCLK_LCDC0,
- CLK_GATE_6RES2,
- CLK_GATE_6RES3,
-
- CLK_GATE_HCLK_CIF,
- CLK_GATE_ACLK_CIF,
- CLK_GATE_6RES6,
- CLK_GATE_6RES7,
-
- CLK_GATE_6RES8,
- CLK_GATE_6RES9,
- CLK_GATE_HCLK_RGA,
- CLK_GATE_ACLK_RGA,
-
- CLK_GATE_HCLK_VIO_BUS,
- CLK_GATE_ACLK_VIO0,
- CLK_GATE_6RES14,
- CLK_GATE_6RES15,
-
- CLK_GATE_HCLK_EMMC = CLK_GATE_CLKID(7),
- CLK_GATE_7RES1,
- CLK_GATE_HCLK_I2S,
- CLK_GATE_HCLK_OTG1,
-
- CLK_GATE_7RES4,
- CLK_GATE_7RES5,
- CLK_GATE_7RES6,
- CLK_GATE_PCLK_TIMER0,
-
- CLK_GATE_PCLK_TIMER1,
- CLK_GATE_7RES9,
- CLK_GATE_PCLK_PWM01,
- CLK_GATE_7RES11,
-
- CLK_GATE_PCLK_SPI0,
- CLK_GATE_7RES13,
- CLK_GATE_PCLK_SARADC,
- CLK_GATE_PCLK_WDT,
-
- CLK_GATE_PCLK_UART0 = CLK_GATE_CLKID(8),
- CLK_GATE_PCLK_UART1,
- CLK_GATE_PCLK_UART2,
- CLK_GATE_8RES3,
-
- CLK_GATE_PCLK_I2C0,
- CLK_GATE_PCLK_I2C1,
- CLK_GATE_PCLK_I2C2,
- CLK_GATE_PCLK_I2C3,
-
- CLK_GATE_8RES8,
- CLK_GATE_PCLK_GPIO0,
- CLK_GATE_PCLK_GPIO1,
- CLK_GATE_PCLK_GPIO2,
-
- CLK_GATE_PCLK_GPIO3,
- CLK_GATE_8RES13,
- CLK_GATE_8RES14,
- CLK_GATE_8RES15,
-
- CLK_GATE_CLK_CORE_DBG = CLK_GATE_CLKID(9),
- CLK_GATE_PCLK_DBG,
- CLK_GATE_9RES2,
- CLK_GATE_9RES3,
-
- CLK_GATE_CLK_L2C,
- CLK_GATE_9RES5,
- CLK_GATE_9RES6,
- CLK_GATE_9RES7,
-
- CLK_GATE_9RES8,
- CLK_GATE_9RES9,
- CLK_GATE_HCLK_USB_PERI,
- CLK_GATE_HCLK_PERI_ARBI,
-
- CLK_GATE_ACLK_PERI_NIU,
- CLK_GATE_9RES13,
- CLK_GATE_9RES14,
- CLK_GATE_9RES15,
-
- CLK_GATE_MAX,
-};
-
-#define SOFT_RST_ID(i) (16 * (i))
-
-enum cru_soft_reset {
- SOFT_RST_CORE_SRST_WDT_SEL = SOFT_RST_ID(0),
- SOFT_RST_ACLK_CORE,
- SOFT_RST_MCORE,
- SOFT_RST_0RES3,
-
- SOFT_RST_0RES4,
- SOFT_RST_0RES5,
- SOFT_RST_0RES6,
- SOFT_RST_MCORE_DBG,
-
- SOFT_RST_0RES8,
- SOFT_RST_0RES9,
- SOFT_RST_0RES10,
- SOFT_RST_0RES11,
-
- SOFT_RST_CORE0_WDT,
- SOFT_RST_0RES13,
- SOFT_RST_STRC_SYS_AXI,
- SOFT_RST_0RES15,
-
- SOFT_RST_CPU_STRC_SYS_AXI = SOFT_RST_ID(1),
- SOFT_RST_CPUSYS_AHB,
- SOFT_RST_L2MEM_CON_AXI,
- SOFT_RST_AHB2APB,
-
- SOFT_RST_1RES4,
- SOFT_RST_INTMEM,
- SOFT_RST_ROM,
- SOFT_RST_PERI_NIU,
-
- SOFT_RST_I2S,
- SOFT_RST_1RES9,
- SOFT_RST_1RES10,
- SOFT_RST_TIMER0,
-
- SOFT_RST_TIMER1,
- SOFT_RST_1RES13,
- SOFT_RST_EFUSE_APB,
- SOFT_RST_ACODEC,
-
- SOFT_RST_GPIO0 = SOFT_RST_ID(2),
- SOFT_RST_GPIO1,
- SOFT_RST_GPIO2,
- SOFT_RST_GPIO3,
-
- SOFT_RST_2RES4,
- SOFT_RST_2RES5,
- SOFT_RST_2RES6,
- SOFT_RST_UART0,
-
- SOFT_RST_UART1,
- SOFT_RST_UART2,
- SOFT_RST_2RES10,
- SOFT_RST_I2C0,
-
- SOFT_RST_I2C1,
- SOFT_RST_I2C2,
- SOFT_RST_I2C3,
- SOFT_RST_2RES15,
-
- SOFT_RST_PWM0 = SOFT_RST_ID(3),
- SOFT_RST_PWM1,
- SOFT_RST_DAP_PO,
- SOFT_RST_DAP,
-
- SOFT_RST_DAP_SYS,
- SOFT_RST_3RES5,
- SOFT_RST_3RES6,
- SOFT_RST_GRF,
-
- SOFT_RST_I2C,
- SOFT_RST_PERIPHSYS_AXI,
- SOFT_RST_PERIPHSYS_AHB,
- SOFT_RST_PERIPHSYS_APB,
-
- SOFT_RST_PWM2,
- SOFT_RST_CPU_PERI,
- SOFT_RST_EMEM_PERI,
- SOFT_RST_USB_PERI,
-
- SOFT_RST_DMA2 = SOFT_RST_ID(4),
- SOFT_RST_4RES1,
- SOFT_RST_4RES2,
- SOFT_RST_GPS,
-
- SOFT_RST_NANDC,
- SOFT_RST_USBOTG0,
- SOFT_RST_USBPHY0,
- SOFT_RST_OTGC0,
-
- SOFT_RST_USBOTG1,
- SOFT_RST_USBPHY1,
- SOFT_RST_OTGC1,
- SOFT_RST_4RES11,
-
- SOFT_RST_4RES12,
- SOFT_RST_4RES13,
- SOFT_RST_4RES14,
- SOFT_RST_DDRMSCH,
-
- SOFT_RST_5RES0 = SOFT_RST_ID(5),
- SOFT_RST_MMC0,
- SOFT_RST_SDIO,
- SOFT_RST_EMMC,
-
- SOFT_RST_SPI0,
- SOFT_RST_5RES5,
- SOFT_RST_WDT,
- SOFT_RST_SARADC,
-
- SOFT_RST_DDRPHY,
- SOFT_RST_DDRPHY_APB,
- SOFT_RST_DDRCTRL,
- SOFT_RST_DDRCTRL_APB,
-
- SOFT_RST_5RES12,
- SOFT_RST_5RES13,
- SOFT_RST_5RES14,
- SOFT_RST_5RES15,
-
- SOFT_RST_HDMI_PCLK = SOFT_RST_ID(6),
- SOFT_RST_HDMI_DCLK,
- SOFT_RST_VIO0_AXI,
- SOFT_RST_VIO_BUS_AHB,
-
- SOFT_RST_LCDC0_AXI,
- SOFT_RST_LCDC0_AHB,
- SOFT_RST_LCDC0_DCLK,
- SOFT_RST_UTMI0,
-
- SOFT_RST_UTMI1,
- SOFT_RST_USBPOR,
- SOFT_RST_6RES10,
- SOFT_RST_6RES11,
-
- SOFT_RST_RGA_AXI,
- SOFT_RST_RGA_AHB,
- SOFT_RST_CIF0,
- SOFT_RST_LCDC_SCL,
-
- SOFT_RST_VCODEC_AXI = SOFT_RST_ID(7),
- SOFT_RST_VCODEC_AHB,
- SOFT_RST_VIO1_AXI,
- SOFT_RST_CPU_VCODEC,
-
- SOFT_RST_VCODEC_NIU_AXI,
- SOFT_RST_7RES5,
- SOFT_RST_7RES6,
- SOFT_RST_7RES7,
-
- SOFT_RST_GPU,
- SOFT_RST_7RES9,
- SOFT_RST_GPU_NIU_AXI,
- SOFT_RST_7RES11,
-
- SOFT_RST_7RES12,
- SOFT_RST_7RES13,
- SOFT_RST_7RES14,
- SOFT_RST_7RES15,
-
- SOFT_RST_8RES0 = SOFT_RST_ID(8),
- SOFT_RST_8RES1,
- SOFT_RST_CORE_DBG,
- SOFT_RST_DBG_APB,
-
- SOFT_RST_8RES4,
- SOFT_RST_8RES5,
- SOFT_RST_8RES6,
- SOFT_RST_8RES7,
-
- SOFT_RST_8RES8,
- SOFT_RST_8RES9,
- SOFT_RST_8RES10,
- SOFT_RST_8RES11,
-
- SOFT_RST_8RES12,
- SOFT_RST_8RES13,
- SOFT_RST_8RES14,
- SOFT_RST_8RES15,
-
- SOFT_RST_MAX,
-};
-
-/*****cru reg end*****/
-static inline void cru_set_soft_reset(enum cru_soft_reset idx, bool on)
-{
- const void __iomem *reg = RK2928_CRU_BASE + CRU_SOFTRSTS_CON(idx >> 4);
- u32 val = on ? 0x10001U << (idx & 0xf) : 0x10000U << (idx & 0xf);
- writel_relaxed(val, reg);
- dsb();
-}
-
-#endif
+++ /dev/null
-#include <plat/ddr.h>
+++ /dev/null
-#include <plat/debug-macro.S>
+++ /dev/null
-#ifndef __MACH_DEBUG_UART
-#define __MACH_DEBUG_UART
-
-#if CONFIG_RK_DEBUG_UART >= 0 && CONFIG_RK_DEBUG_UART < 3
-
-#if CONFIG_RK_DEBUG_UART == 0
-#define DEBUG_UART_PHYS RK2928_UART0_PHYS
-#define DEBUG_UART_BASE RK2928_UART0_BASE
-#elif CONFIG_RK_DEBUG_UART == 1
-#define DEBUG_UART_PHYS RK2928_UART1_PHYS
-#define DEBUG_UART_BASE RK2928_UART1_BASE
-#elif CONFIG_RK_DEBUG_UART == 2
-#define DEBUG_UART_PHYS RK2928_UART2_PHYS
-#define DEBUG_UART_BASE RK2928_UART2_BASE
-#endif
-
-#define IRQ_DEBUG_UART (IRQ_UART0 + CONFIG_RK_DEBUG_UART)
-
-#endif
-
-#endif
+++ /dev/null
-#include <plat/dma-pl330.h>
+++ /dev/null
-#ifndef RK_MACH_DVFS_H\r
-#define RK_MACH_DVFS_H\r
-\r
-#include <plat/dvfs.h>\r
-\r
-#ifdef CONFIG_DVFS\r
-int rk292x_dvfs_init(void);\r
-#else\r
-static inline int rk292x_dvfs_init(void){ return 0; }\r
-#endif\r
-\r
-#endif\r
+++ /dev/null
-#include <plat/entry-macro.S>
+++ /dev/null
-#include <plat/fiq.h>
+++ /dev/null
-#ifndef __MACH_GPIO_H
-#define __MACH_GPIO_H
-
-#include <mach/irqs.h>
-#include <linux/init.h>
-
-#define GPIO_BANKS 4
-
-#define RK2928_PIN0_PA0 (0*NUM_GROUP + PIN_BASE + 0)
-#define RK2928_PIN0_PA1 (0*NUM_GROUP + PIN_BASE + 1)
-#define RK2928_PIN0_PA2 (0*NUM_GROUP + PIN_BASE + 2)
-#define RK2928_PIN0_PA3 (0*NUM_GROUP + PIN_BASE + 3)
-#define RK2928_PIN0_PA4 (0*NUM_GROUP + PIN_BASE + 4)
-#define RK2928_PIN0_PA5 (0*NUM_GROUP + PIN_BASE + 5)
-#define RK2928_PIN0_PA6 (0*NUM_GROUP + PIN_BASE + 6)
-#define RK2928_PIN0_PA7 (0*NUM_GROUP + PIN_BASE + 7)
-#define RK2928_PIN0_PB0 (0*NUM_GROUP + PIN_BASE + 8)
-#define RK2928_PIN0_PB1 (0*NUM_GROUP + PIN_BASE + 9)
-#define RK2928_PIN0_PB2 (0*NUM_GROUP + PIN_BASE + 10)
-#define RK2928_PIN0_PB3 (0*NUM_GROUP + PIN_BASE + 11)
-#define RK2928_PIN0_PB4 (0*NUM_GROUP + PIN_BASE + 12)
-#define RK2928_PIN0_PB5 (0*NUM_GROUP + PIN_BASE + 13)
-#define RK2928_PIN0_PB6 (0*NUM_GROUP + PIN_BASE + 14)
-#define RK2928_PIN0_PB7 (0*NUM_GROUP + PIN_BASE + 15)
-#define RK2928_PIN0_PC0 (0*NUM_GROUP + PIN_BASE + 16)
-#define RK2928_PIN0_PC1 (0*NUM_GROUP + PIN_BASE + 17)
-#define RK2928_PIN0_PC2 (0*NUM_GROUP + PIN_BASE + 18)
-#define RK2928_PIN0_PC3 (0*NUM_GROUP + PIN_BASE + 19)
-#define RK2928_PIN0_PC4 (0*NUM_GROUP + PIN_BASE + 20)
-#define RK2928_PIN0_PC5 (0*NUM_GROUP + PIN_BASE + 21)
-#define RK2928_PIN0_PC6 (0*NUM_GROUP + PIN_BASE + 22)
-#define RK2928_PIN0_PC7 (0*NUM_GROUP + PIN_BASE + 23)
-#define RK2928_PIN0_PD0 (0*NUM_GROUP + PIN_BASE + 24)
-#define RK2928_PIN0_PD1 (0*NUM_GROUP + PIN_BASE + 25)
-#define RK2928_PIN0_PD2 (0*NUM_GROUP + PIN_BASE + 26)
-#define RK2928_PIN0_PD3 (0*NUM_GROUP + PIN_BASE + 27)
-#define RK2928_PIN0_PD4 (0*NUM_GROUP + PIN_BASE + 28)
-#define RK2928_PIN0_PD5 (0*NUM_GROUP + PIN_BASE + 29)
-#define RK2928_PIN0_PD6 (0*NUM_GROUP + PIN_BASE + 30)
-#define RK2928_PIN0_PD7 (0*NUM_GROUP + PIN_BASE + 31)
-
-#define RK2928_PIN1_PA0 (1*NUM_GROUP + PIN_BASE + 0)
-#define RK2928_PIN1_PA1 (1*NUM_GROUP + PIN_BASE + 1)
-#define RK2928_PIN1_PA2 (1*NUM_GROUP + PIN_BASE + 2)
-#define RK2928_PIN1_PA3 (1*NUM_GROUP + PIN_BASE + 3)
-#define RK2928_PIN1_PA4 (1*NUM_GROUP + PIN_BASE + 4)
-#define RK2928_PIN1_PA5 (1*NUM_GROUP + PIN_BASE + 5)
-#define RK2928_PIN1_PA6 (1*NUM_GROUP + PIN_BASE + 6)
-#define RK2928_PIN1_PA7 (1*NUM_GROUP + PIN_BASE + 7)
-#define RK2928_PIN1_PB0 (1*NUM_GROUP + PIN_BASE + 8)
-#define RK2928_PIN1_PB1 (1*NUM_GROUP + PIN_BASE + 9)
-#define RK2928_PIN1_PB2 (1*NUM_GROUP + PIN_BASE + 10)
-#define RK2928_PIN1_PB3 (1*NUM_GROUP + PIN_BASE + 11)
-#define RK2928_PIN1_PB4 (1*NUM_GROUP + PIN_BASE + 12)
-#define RK2928_PIN1_PB5 (1*NUM_GROUP + PIN_BASE + 13)
-#define RK2928_PIN1_PB6 (1*NUM_GROUP + PIN_BASE + 14)
-#define RK2928_PIN1_PB7 (1*NUM_GROUP + PIN_BASE + 15)
-#define RK2928_PIN1_PC0 (1*NUM_GROUP + PIN_BASE + 16)
-#define RK2928_PIN1_PC1 (1*NUM_GROUP + PIN_BASE + 17)
-#define RK2928_PIN1_PC2 (1*NUM_GROUP + PIN_BASE + 18)
-#define RK2928_PIN1_PC3 (1*NUM_GROUP + PIN_BASE + 19)
-#define RK2928_PIN1_PC4 (1*NUM_GROUP + PIN_BASE + 20)
-#define RK2928_PIN1_PC5 (1*NUM_GROUP + PIN_BASE + 21)
-#define RK2928_PIN1_PC6 (1*NUM_GROUP + PIN_BASE + 22)
-#define RK2928_PIN1_PC7 (1*NUM_GROUP + PIN_BASE + 23)
-#define RK2928_PIN1_PD0 (1*NUM_GROUP + PIN_BASE + 24)
-#define RK2928_PIN1_PD1 (1*NUM_GROUP + PIN_BASE + 25)
-#define RK2928_PIN1_PD2 (1*NUM_GROUP + PIN_BASE + 26)
-#define RK2928_PIN1_PD3 (1*NUM_GROUP + PIN_BASE + 27)
-#define RK2928_PIN1_PD4 (1*NUM_GROUP + PIN_BASE + 28)
-#define RK2928_PIN1_PD5 (1*NUM_GROUP + PIN_BASE + 29)
-#define RK2928_PIN1_PD6 (1*NUM_GROUP + PIN_BASE + 30)
-#define RK2928_PIN1_PD7 (1*NUM_GROUP + PIN_BASE + 31)
-
-#define RK2928_PIN2_PA0 (2*NUM_GROUP + PIN_BASE + 0)
-#define RK2928_PIN2_PA1 (2*NUM_GROUP + PIN_BASE + 1)
-#define RK2928_PIN2_PA2 (2*NUM_GROUP + PIN_BASE + 2)
-#define RK2928_PIN2_PA3 (2*NUM_GROUP + PIN_BASE + 3)
-#define RK2928_PIN2_PA4 (2*NUM_GROUP + PIN_BASE + 4)
-#define RK2928_PIN2_PA5 (2*NUM_GROUP + PIN_BASE + 5)
-#define RK2928_PIN2_PA6 (2*NUM_GROUP + PIN_BASE + 6)
-#define RK2928_PIN2_PA7 (2*NUM_GROUP + PIN_BASE + 7)
-#define RK2928_PIN2_PB0 (2*NUM_GROUP + PIN_BASE + 8)
-#define RK2928_PIN2_PB1 (2*NUM_GROUP + PIN_BASE + 9)
-#define RK2928_PIN2_PB2 (2*NUM_GROUP + PIN_BASE + 10)
-#define RK2928_PIN2_PB3 (2*NUM_GROUP + PIN_BASE + 11)
-#define RK2928_PIN2_PB4 (2*NUM_GROUP + PIN_BASE + 12)
-#define RK2928_PIN2_PB5 (2*NUM_GROUP + PIN_BASE + 13)
-#define RK2928_PIN2_PB6 (2*NUM_GROUP + PIN_BASE + 14)
-#define RK2928_PIN2_PB7 (2*NUM_GROUP + PIN_BASE + 15)
-#define RK2928_PIN2_PC0 (2*NUM_GROUP + PIN_BASE + 16)
-#define RK2928_PIN2_PC1 (2*NUM_GROUP + PIN_BASE + 17)
-#define RK2928_PIN2_PC2 (2*NUM_GROUP + PIN_BASE + 18)
-#define RK2928_PIN2_PC3 (2*NUM_GROUP + PIN_BASE + 19)
-#define RK2928_PIN2_PC4 (2*NUM_GROUP + PIN_BASE + 20)
-#define RK2928_PIN2_PC5 (2*NUM_GROUP + PIN_BASE + 21)
-#define RK2928_PIN2_PC6 (2*NUM_GROUP + PIN_BASE + 22)
-#define RK2928_PIN2_PC7 (2*NUM_GROUP + PIN_BASE + 23)
-#define RK2928_PIN2_PD0 (2*NUM_GROUP + PIN_BASE + 24)
-#define RK2928_PIN2_PD1 (2*NUM_GROUP + PIN_BASE + 25)
-#define RK2928_PIN2_PD2 (2*NUM_GROUP + PIN_BASE + 26)
-#define RK2928_PIN2_PD3 (2*NUM_GROUP + PIN_BASE + 27)
-#define RK2928_PIN2_PD4 (2*NUM_GROUP + PIN_BASE + 28)
-#define RK2928_PIN2_PD5 (2*NUM_GROUP + PIN_BASE + 29)
-#define RK2928_PIN2_PD6 (2*NUM_GROUP + PIN_BASE + 30)
-#define RK2928_PIN2_PD7 (2*NUM_GROUP + PIN_BASE + 31)
-
-#define RK2928_PIN3_PA0 (3*NUM_GROUP + PIN_BASE + 0)
-#define RK2928_PIN3_PA1 (3*NUM_GROUP + PIN_BASE + 1)
-#define RK2928_PIN3_PA2 (3*NUM_GROUP + PIN_BASE + 2)
-#define RK2928_PIN3_PA3 (3*NUM_GROUP + PIN_BASE + 3)
-#define RK2928_PIN3_PA4 (3*NUM_GROUP + PIN_BASE + 4)
-#define RK2928_PIN3_PA5 (3*NUM_GROUP + PIN_BASE + 5)
-#define RK2928_PIN3_PA6 (3*NUM_GROUP + PIN_BASE + 6)
-#define RK2928_PIN3_PA7 (3*NUM_GROUP + PIN_BASE + 7)
-#define RK2928_PIN3_PB0 (3*NUM_GROUP + PIN_BASE + 8)
-#define RK2928_PIN3_PB1 (3*NUM_GROUP + PIN_BASE + 9)
-#define RK2928_PIN3_PB2 (3*NUM_GROUP + PIN_BASE + 10)
-#define RK2928_PIN3_PB3 (3*NUM_GROUP + PIN_BASE + 11)
-#define RK2928_PIN3_PB4 (3*NUM_GROUP + PIN_BASE + 12)
-#define RK2928_PIN3_PB5 (3*NUM_GROUP + PIN_BASE + 13)
-#define RK2928_PIN3_PB6 (3*NUM_GROUP + PIN_BASE + 14)
-#define RK2928_PIN3_PB7 (3*NUM_GROUP + PIN_BASE + 15)
-#define RK2928_PIN3_PC0 (3*NUM_GROUP + PIN_BASE + 16)
-#define RK2928_PIN3_PC1 (3*NUM_GROUP + PIN_BASE + 17)
-#define RK2928_PIN3_PC2 (3*NUM_GROUP + PIN_BASE + 18)
-#define RK2928_PIN3_PC3 (3*NUM_GROUP + PIN_BASE + 19)
-#define RK2928_PIN3_PC4 (3*NUM_GROUP + PIN_BASE + 20)
-#define RK2928_PIN3_PC5 (3*NUM_GROUP + PIN_BASE + 21)
-#define RK2928_PIN3_PC6 (3*NUM_GROUP + PIN_BASE + 22)
-#define RK2928_PIN3_PC7 (3*NUM_GROUP + PIN_BASE + 23)
-#define RK2928_PIN3_PD0 (3*NUM_GROUP + PIN_BASE + 24)
-#define RK2928_PIN3_PD1 (3*NUM_GROUP + PIN_BASE + 25)
-#define RK2928_PIN3_PD2 (3*NUM_GROUP + PIN_BASE + 26)
-#define RK2928_PIN3_PD3 (3*NUM_GROUP + PIN_BASE + 27)
-#define RK2928_PIN3_PD4 (3*NUM_GROUP + PIN_BASE + 28)
-#define RK2928_PIN3_PD5 (3*NUM_GROUP + PIN_BASE + 29)
-#define RK2928_PIN3_PD6 (3*NUM_GROUP + PIN_BASE + 30)
-#define RK2928_PIN3_PD7 (3*NUM_GROUP + PIN_BASE + 31)
-
-#define RK30_PIN0_PA0 RK2928_PIN0_PA0
-#define RK30_PIN0_PA1 RK2928_PIN0_PA1
-#define RK30_PIN0_PA2 RK2928_PIN0_PA2
-#define RK30_PIN0_PA3 RK2928_PIN0_PA3
-#define RK30_PIN0_PA4 RK2928_PIN0_PA4
-#define RK30_PIN0_PA5 RK2928_PIN0_PA5
-#define RK30_PIN0_PA6 RK2928_PIN0_PA6
-#define RK30_PIN0_PA7 RK2928_PIN0_PA7
-#define RK30_PIN0_PB0 RK2928_PIN0_PB0
-#define RK30_PIN0_PB1 RK2928_PIN0_PB1
-#define RK30_PIN0_PB2 RK2928_PIN0_PB2
-#define RK30_PIN0_PB3 RK2928_PIN0_PB3
-#define RK30_PIN0_PB4 RK2928_PIN0_PB4
-#define RK30_PIN0_PB5 RK2928_PIN0_PB5
-#define RK30_PIN0_PB6 RK2928_PIN0_PB6
-#define RK30_PIN0_PB7 RK2928_PIN0_PB7
-#define RK30_PIN0_PC0 RK2928_PIN0_PC0
-#define RK30_PIN0_PC1 RK2928_PIN0_PC1
-#define RK30_PIN0_PC2 RK2928_PIN0_PC2
-#define RK30_PIN0_PC3 RK2928_PIN0_PC3
-#define RK30_PIN0_PC4 RK2928_PIN0_PC4
-#define RK30_PIN0_PC5 RK2928_PIN0_PC5
-#define RK30_PIN0_PC6 RK2928_PIN0_PC6
-#define RK30_PIN0_PC7 RK2928_PIN0_PC7
-#define RK30_PIN0_PD0 RK2928_PIN0_PD0
-#define RK30_PIN0_PD1 RK2928_PIN0_PD1
-#define RK30_PIN0_PD2 RK2928_PIN0_PD2
-#define RK30_PIN0_PD3 RK2928_PIN0_PD3
-#define RK30_PIN0_PD4 RK2928_PIN0_PD4
-#define RK30_PIN0_PD5 RK2928_PIN0_PD5
-#define RK30_PIN0_PD6 RK2928_PIN0_PD6
-#define RK30_PIN0_PD7 RK2928_PIN0_PD7
-
-#define RK30_PIN1_PA0 RK2928_PIN1_PA0
-#define RK30_PIN1_PA1 RK2928_PIN1_PA1
-#define RK30_PIN1_PA2 RK2928_PIN1_PA2
-#define RK30_PIN1_PA3 RK2928_PIN1_PA3
-#define RK30_PIN1_PA4 RK2928_PIN1_PA4
-#define RK30_PIN1_PA5 RK2928_PIN1_PA5
-#define RK30_PIN1_PA6 RK2928_PIN1_PA6
-#define RK30_PIN1_PA7 RK2928_PIN1_PA7
-#define RK30_PIN1_PB0 RK2928_PIN1_PB0
-#define RK30_PIN1_PB1 RK2928_PIN1_PB1
-#define RK30_PIN1_PB2 RK2928_PIN1_PB2
-#define RK30_PIN1_PB3 RK2928_PIN1_PB3
-#define RK30_PIN1_PB4 RK2928_PIN1_PB4
-#define RK30_PIN1_PB5 RK2928_PIN1_PB5
-#define RK30_PIN1_PB6 RK2928_PIN1_PB6
-#define RK30_PIN1_PB7 RK2928_PIN1_PB7
-#define RK30_PIN1_PC0 RK2928_PIN1_PC0
-#define RK30_PIN1_PC1 RK2928_PIN1_PC1
-#define RK30_PIN1_PC2 RK2928_PIN1_PC2
-#define RK30_PIN1_PC3 RK2928_PIN1_PC3
-#define RK30_PIN1_PC4 RK2928_PIN1_PC4
-#define RK30_PIN1_PC5 RK2928_PIN1_PC5
-#define RK30_PIN1_PC6 RK2928_PIN1_PC6
-#define RK30_PIN1_PC7 RK2928_PIN1_PC7
-#define RK30_PIN1_PD0 RK2928_PIN1_PD0
-#define RK30_PIN1_PD1 RK2928_PIN1_PD1
-#define RK30_PIN1_PD2 RK2928_PIN1_PD2
-#define RK30_PIN1_PD3 RK2928_PIN1_PD3
-#define RK30_PIN1_PD4 RK2928_PIN1_PD4
-#define RK30_PIN1_PD5 RK2928_PIN1_PD5
-#define RK30_PIN1_PD6 RK2928_PIN1_PD6
-#define RK30_PIN1_PD7 RK2928_PIN1_PD7
-
-#define RK30_PIN2_PA0 RK2928_PIN2_PA0
-#define RK30_PIN2_PA1 RK2928_PIN2_PA1
-#define RK30_PIN2_PA2 RK2928_PIN2_PA2
-#define RK30_PIN2_PA3 RK2928_PIN2_PA3
-#define RK30_PIN2_PA4 RK2928_PIN2_PA4
-#define RK30_PIN2_PA5 RK2928_PIN2_PA5
-#define RK30_PIN2_PA6 RK2928_PIN2_PA6
-#define RK30_PIN2_PA7 RK2928_PIN2_PA7
-#define RK30_PIN2_PB0 RK2928_PIN2_PB0
-#define RK30_PIN2_PB1 RK2928_PIN2_PB1
-#define RK30_PIN2_PB2 RK2928_PIN2_PB2
-#define RK30_PIN2_PB3 RK2928_PIN2_PB3
-#define RK30_PIN2_PB4 RK2928_PIN2_PB4
-#define RK30_PIN2_PB5 RK2928_PIN2_PB5
-#define RK30_PIN2_PB6 RK2928_PIN2_PB6
-#define RK30_PIN2_PB7 RK2928_PIN2_PB7
-#define RK30_PIN2_PC0 RK2928_PIN2_PC0
-#define RK30_PIN2_PC1 RK2928_PIN2_PC1
-#define RK30_PIN2_PC2 RK2928_PIN2_PC2
-#define RK30_PIN2_PC3 RK2928_PIN2_PC3
-#define RK30_PIN2_PC4 RK2928_PIN2_PC4
-#define RK30_PIN2_PC5 RK2928_PIN2_PC5
-#define RK30_PIN2_PC6 RK2928_PIN2_PC6
-#define RK30_PIN2_PC7 RK2928_PIN2_PC7
-#define RK30_PIN2_PD0 RK2928_PIN2_PD0
-#define RK30_PIN2_PD1 RK2928_PIN2_PD1
-#define RK30_PIN2_PD2 RK2928_PIN2_PD2
-#define RK30_PIN2_PD3 RK2928_PIN2_PD3
-#define RK30_PIN2_PD4 RK2928_PIN2_PD4
-#define RK30_PIN2_PD5 RK2928_PIN2_PD5
-#define RK30_PIN2_PD6 RK2928_PIN2_PD6
-#define RK30_PIN2_PD7 RK2928_PIN2_PD7
-
-#define RK30_PIN3_PA0 RK2928_PIN3_PA0
-#define RK30_PIN3_PA1 RK2928_PIN3_PA1
-#define RK30_PIN3_PA2 RK2928_PIN3_PA2
-#define RK30_PIN3_PA3 RK2928_PIN3_PA3
-#define RK30_PIN3_PA4 RK2928_PIN3_PA4
-#define RK30_PIN3_PA5 RK2928_PIN3_PA5
-#define RK30_PIN3_PA6 RK2928_PIN3_PA6
-#define RK30_PIN3_PA7 RK2928_PIN3_PA7
-#define RK30_PIN3_PB0 RK2928_PIN3_PB0
-#define RK30_PIN3_PB1 RK2928_PIN3_PB1
-#define RK30_PIN3_PB2 RK2928_PIN3_PB2
-#define RK30_PIN3_PB3 RK2928_PIN3_PB3
-#define RK30_PIN3_PB4 RK2928_PIN3_PB4
-#define RK30_PIN3_PB5 RK2928_PIN3_PB5
-#define RK30_PIN3_PB6 RK2928_PIN3_PB6
-#define RK30_PIN3_PB7 RK2928_PIN3_PB7
-#define RK30_PIN3_PC0 RK2928_PIN3_PC0
-#define RK30_PIN3_PC1 RK2928_PIN3_PC1
-#define RK30_PIN3_PC2 RK2928_PIN3_PC2
-#define RK30_PIN3_PC3 RK2928_PIN3_PC3
-#define RK30_PIN3_PC4 RK2928_PIN3_PC4
-#define RK30_PIN3_PC5 RK2928_PIN3_PC5
-#define RK30_PIN3_PC6 RK2928_PIN3_PC6
-#define RK30_PIN3_PC7 RK2928_PIN3_PC7
-#define RK30_PIN3_PD0 RK2928_PIN3_PD0
-#define RK30_PIN3_PD1 RK2928_PIN3_PD1
-#define RK30_PIN3_PD2 RK2928_PIN3_PD2
-#define RK30_PIN3_PD3 RK2928_PIN3_PD3
-#define RK30_PIN3_PD4 RK2928_PIN3_PD4
-#define RK30_PIN3_PD5 RK2928_PIN3_PD5
-#define RK30_PIN3_PD6 RK2928_PIN3_PD6
-#define RK30_PIN3_PD7 RK2928_PIN3_PD7
-
-#include <plat/gpio.h>
-
-#endif
+++ /dev/null
-#ifndef __MACH_HARDWARE_H
-#define __MACH_HARDWARE_H
-
-#endif
+++ /dev/null
-#ifndef __MACH_IO_H
-#define __MACH_IO_H
-
-#include <plat/io.h>
-
-/*
- * RK2928 IO memory map:
- *
- * Virt Phys Size What
- * ---------------------------------------------------------------------------
- * FEA00000 10000000 3M
- * FED00000 20000000 1M
- * FEF00000 0 8K SRAM
- */
-
-#define RK2928_IO_TO_VIRT0(pa) IOMEM(pa + (0xFEA00000 - 0x10000000))
-#define RK2928_IO_TO_VIRT1(pa) IOMEM(pa + (0xFED00000 - 0x20000000))
-
-#define RK2928_IMEM_PHYS 0x10080000
-#define RK2928_IMEM_BASE IOMEM(0xFEF00000)
-#define RK2928_IMEM_NONCACHED RK2928_IO_TO_VIRT0(RK2928_IMEM_PHYS)
-#define RK2928_IMEM_SIZE SZ_8K
-
-#define RK2928_GPU_PHYS 0x10090000
-#define RK2928_GPU_SIZE SZ_64K
-
-#define RK2928_ROM_PHYS 0x10100000
-#define RK2928_ROM_BASE RK2928_IO_TO_VIRT0(RK2928_ROM_PHYS)
-#define RK2928_ROM_SIZE SZ_16K
-#define RK2928_VCODEC_PHYS 0x10104000
-#define RK2928_VCODEC_SIZE SZ_16K
-#define RK3026_IEP_PHYS 0x10108000
-#define RK3026_IEP_SIZE SZ_8K
-#define RK2928_CIF_PHYS 0x1010a000
-#define RK2928_CIF_SIZE SZ_8K
-#define RK2928_RGA_PHYS 0x1010c000
-#define RK2928_RGA_SIZE SZ_8K
-#define RK2928_LCDC_PHYS 0x1010e000
-#define RK2928_LCDC_SIZE SZ_8K
-#define RK3026_LCDC0_PHYS RK2928_LCDC_PHYS
-#define RK3026_LCDC0_SIZE RK2928_LCDC_SIZE
-#define RK3026_LCDC1_PHYS 0x10110000
-#define RK3026_LCDC1_SIZE SZ_8K
-
-#define RK3026_EBC_PHYS 0x10114000
-#define RK3026_EBC_SIZE SZ_16K
-
-#define RK2928_CPU_AXI_BUS_PHYS 0x10128000
-#define RK2928_CPU_AXI_BUS_BASE RK2928_IO_TO_VIRT0(RK2928_CPU_AXI_BUS_PHYS)
-#define RK2928_CPU_AXI_BUS_SIZE SZ_32K
-
-#define RK2928_L2C_PHYS 0x10138000
-#define RK2928_L2C_BASE RK2928_IO_TO_VIRT0(RK2928_L2C_PHYS)
-#define RK2928_L2C_SIZE SZ_16K
-#define RK2928_SCU_PHYS 0x1013c000
-#define RK2928_SCU_BASE RK2928_IO_TO_VIRT0(RK2928_SCU_PHYS)
-#define RK2928_SCU_SIZE SZ_256
-#define RK2928_GICC_PHYS 0x1013c100
-#define RK2928_GICC_BASE RK2928_IO_TO_VIRT0(RK2928_GICC_PHYS)
-#define RK2928_GICC_SIZE SZ_256
-#define RK2928_GTIMER_PHYS 0x1013c200
-#define RK2928_GTIMER_BASE RK2928_IO_TO_VIRT0(RK2928_GTIMER_PHYS)
-#define RK2928_GTIMER_SIZE SZ_1K
-#define RK2928_PTIMER_PHYS 0x1013c600
-#define RK2928_PTIMER_BASE RK2928_IO_TO_VIRT0(RK2928_PTIMER_PHYS)
-#define RK2928_PTIMER_SIZE (SZ_2K + SZ_512)
-#define RK2928_GICD_PHYS 0x1013d000
-#define RK2928_GICD_BASE RK2928_IO_TO_VIRT0(RK2928_GICD_PHYS)
-#define RK2928_GICD_SIZE SZ_4K
-
-#define RK2928_CORE_PHYS RK2928_L2C_PHYS
-#define RK2928_CORE_BASE RK2928_IO_TO_VIRT0(RK2928_CORE_PHYS)
-#define RK2928_CORE_SIZE (RK2928_L2C_SIZE + SZ_8K)
-
-#define RK2928_USBOTG20_PHYS 0x10180000
-#define RK2928_USBOTG20_SIZE SZ_256K
-#define RK2928_USBHOST20_PHYS 0x101c0000
-#define RK2928_USBHOST20_SIZE SZ_256K
-#define RK3026_CRYPTO_PHYS 0x10200000
-#define RK3026_CRYPTO_SIZE SZ_16K
-
-#define RK2928_SDMMC_PHYS 0x10214000
-#define RK2928_SDMMC_SIZE SZ_16K
-#define RK2928_SDIO_PHYS 0x10218000
-#define RK2928_SDIO_SIZE SZ_16K
-#define RK2928_EMMC_PHYS 0x1021c000
-#define RK2928_EMMC_SIZE SZ_16K
-#define RK2928_I2S_PHYS 0x10220000
-#define RK2928_I2S_SIZE SZ_8K
-
-#define RK2928_AHB_ARB0_PHYS 0x10234000
-#define RK2928_AHB_ARB0_SIZE SZ_32K
-#define RK2928_AHB_ARB1_PHYS 0x1023C000
-#define RK2928_AHB_ARB1_SIZE (784 * SZ_1K)
-#define RK2928_PERI_AXI_BUS_PHYS 0x10300000
-#define RK2928_PERI_AXI_BUS_SIZE SZ_1M
-#define RK2928_GPS_PHYS 0x10400000
-#define RK2928_GPS_SIZE SZ_1M
-#define RK2928_NANDC_PHYS 0x10500000
-#define RK2928_NANDC_SIZE SZ_16K
-
-#define RK2928_CRU_PHYS 0x20000000
-#define RK2928_CRU_BASE RK2928_IO_TO_VIRT1(RK2928_CRU_PHYS)
-#define RK2928_CRU_SIZE SZ_4K
-#define RK2928_DDR_PCTL_PHYS 0x20004000
-#define RK2928_DDR_PCTL_BASE RK2928_IO_TO_VIRT1(RK2928_DDR_PCTL_PHYS)
-#define RK2928_DDR_PCTL_SIZE SZ_16K
-#define RK2928_GRF_PHYS 0x20008000
-#define RK2928_GRF_BASE RK2928_IO_TO_VIRT1(RK2928_GRF_PHYS)
-#define RK2928_GRF_SIZE SZ_4K
-#define RK2928_DDR_PHY_PHYS 0x2000a000
-#define RK2928_DDR_PHY_BASE RK2928_IO_TO_VIRT1(RK2928_DDR_PHY_PHYS)
-#define RK2928_DDR_PHY_SIZE (SZ_16K + SZ_8K)
-
-#define RK2928_DBG_PHYS 0x20020000
-#define RK2928_DBG_SIZE SZ_64K
-#define RK2928_ACODEC_PHYS 0x20030000
-#define RK2928_ACODEC_SIZE SZ_16K
-#define RK2928_HDMI_PHYS 0x20034000
-#define RK2928_HDMI_SIZE SZ_16K
-
-#define RK2928_TIMER0_PHYS 0x20044000
-#define RK2928_TIMER0_BASE RK2928_IO_TO_VIRT1(RK2928_TIMER0_PHYS)
-#define RK2928_TIMER0_SIZE SZ_4K
-#define RK2928_TIMER1_PHYS 0x20046000
-#define RK2928_TIMER1_BASE RK2928_IO_TO_VIRT1(RK2928_TIMER1_PHYS)
-#define RK2928_TIMER1_SIZE SZ_4K
-
-#define RK2928_WDT_PHYS 0x2004c000
-#define RK2928_WDT_SIZE SZ_4K
-#define RK2928_PWM_PHYS 0x20050000
-#define RK2928_PWM_BASE RK2928_IO_TO_VIRT1(RK2928_PWM_PHYS)
-#define RK2928_PWM_SIZE SZ_4K
-
-#define RK2928_I2C1_PHYS 0x20054000
-#define RK2928_I2C1_SIZE SZ_4K
-#define RK2928_RKI2C1_PHYS 0x20056000
-#define RK2928_RKI2C1_BASE RK2928_IO_TO_VIRT1(RK2928_RKI2C1_PHYS)
-#define RK2928_RKI2C1_SIZE SZ_4K
-#define RK2928_I2C2_PHYS 0x20058000
-#define RK2928_I2C2_SIZE SZ_4K
-#define RK2928_RKI2C2_PHYS 0x2005a000
-#define RK2928_RKI2C2_SIZE SZ_4K
-#define RK2928_I2C3_PHYS 0x2005c000
-#define RK2928_I2C3_SIZE SZ_4K
-#define RK2928_RKI2C3_PHYS 0x2005e000
-#define RK2928_RKI2C3_SIZE SZ_4K
-
-#define RK2928_UART0_PHYS 0x20060000
-#define RK2928_UART0_BASE RK2928_IO_TO_VIRT1(RK2928_UART0_PHYS)
-#define RK2928_UART0_SIZE SZ_4K
-#define RK2928_UART1_PHYS 0x20064000
-#define RK2928_UART1_BASE RK2928_IO_TO_VIRT1(RK2928_UART1_PHYS)
-#define RK2928_UART1_SIZE SZ_4K
-#define RK2928_UART2_PHYS 0x20068000
-#define RK2928_UART2_BASE RK2928_IO_TO_VIRT1(RK2928_UART2_PHYS)
-#define RK2928_UART2_SIZE SZ_4K
-
-#define RK2928_SARADC_PHYS 0x2006c000
-#define RK2928_SARADC_SIZE SZ_4K
-#define RK2928_I2C0_PHYS 0x20070000
-#define RK2928_I2C0_SIZE SZ_4K
-#define RK2928_RKI2C0_PHYS 0x20072000
-#define RK2928_RKI2C0_BASE RK2928_IO_TO_VIRT1(RK2928_RKI2C0_PHYS)
-#define RK2928_RKI2C0_SIZE SZ_4K
-#define RK2928_SPI_PHYS 0x20074000
-#define RK2928_SPI_SIZE SZ_16K
-#define RK2928_DMAC_PHYS 0x20078000
-#define RK2928_DMAC_SIZE SZ_16K
-
-#define RK2928_GPIO0_PHYS 0x2007c000
-#define RK2928_GPIO0_BASE RK2928_IO_TO_VIRT1(RK2928_GPIO0_PHYS)
-#define RK2928_GPIO0_SIZE SZ_4K
-#define RK2928_GPIO1_PHYS 0x20080000
-#define RK2928_GPIO1_BASE RK2928_IO_TO_VIRT1(RK2928_GPIO1_PHYS)
-#define RK2928_GPIO1_SIZE SZ_4K
-#define RK2928_GPIO2_PHYS 0x20084000
-#define RK2928_GPIO2_BASE RK2928_IO_TO_VIRT1(RK2928_GPIO2_PHYS)
-#define RK2928_GPIO2_SIZE SZ_4K
-#define RK2928_GPIO3_PHYS 0x20088000
-#define RK2928_GPIO3_BASE RK2928_IO_TO_VIRT1(RK2928_GPIO3_PHYS)
-#define RK2928_GPIO3_SIZE SZ_4K
-
-#define RK2928_EFUSE_PHYS 0x20090000
-#define RK2928_EFUSE_SIZE SZ_4K
-#define RK2928_EFUSE_BASE RK2928_IO_TO_VIRT1(RK2928_EFUSE_PHYS)
-
-#define GIC_CPU_BASE RK2928_GICC_BASE
-#define GIC_DIST_BASE RK2928_GICD_BASE
-#define RK30_CRU_BASE RK2928_CRU_BASE
-#define RK30_GRF_PHYS RK2928_GRF_PHYS
-#define RK30_GRF_BASE RK2928_GRF_BASE
-#define RK30_IMEM_BASE RK2928_IMEM_BASE
-#define RK30_IMEM_NONCACHED RK2928_IMEM_NONCACHED
-#define RK30_PTIMER_BASE RK2928_PTIMER_BASE
-#define RK30_ROM_BASE RK2928_ROM_BASE
-#define RK30_CPU_AXI_BUS_BASE RK2928_CPU_AXI_BUS_BASE
-#define RK30_L2C_BASE RK2928_L2C_BASE
-#define RK30_SCU_BASE RK2928_SCU_BASE
-
-#endif
+++ /dev/null
-#ifndef __MACH_RK2928_IOMUX_H
-#define __MACH_RK2928_IOMUX_H
-#include <mach/io.h>
-#include <plat/iomux.h>
-
-#define GRF_IOMUX_BASE (RK2928_GRF_BASE + 0x00a8)
-#define GPIO_BANKS 4
-enum{
- /* GPIO0_A */
- GPIO0_A0 = 0x0a00, I2C0_SCL,
- GPIO0_A1 = 0x0a10, I2C0_SDA,
- GPIO0_A2 = 0x0a20, I2C1_SCL,
- GPIO0_A3 = 0x0a30, I2C1_SDA,
- GPIO0_A6 = 0x0a60, I2C3_SCL, HDMI_DDCSCL,
- GPIO0_A7 = 0x0a70, I2C3_SDA, HDMI_DDCSDA,
-
- /* GPIO0_B */
- GPIO0_B0 = 0x0b00, MMC1_CMD,
- GPIO0_B1 = 0x0b10, MMC1_CLKOUT,
- GPIO0_B2 = 0x0b20, MMC1_DETN,
- GPIO0_B3 = 0x0b30, MMC1_D0,
- GPIO0_B4 = 0x0b40, MMC1_D1,
- GPIO0_B5 = 0x0b50, MMC1_D2,
- GPIO0_B6 = 0x0b60, MMC1_D3,
- GPIO0_B7 = 0x0b70, HDMI_HOTPLUGIN,
-
- /* GPIO0_C */
- GPIO0_C0 = 0x0c00, UART0_SOUT,
- GPIO0_C1 = 0x0c10, UART0_SIN,
- GPIO0_C2 = 0x0c20, UART0_RTSN,
- GPIO0_C3 = 0x0c30, UART0_CTSN,
- GPIO0_C4 = 0x0c40, HDMI_CECSDA,
- GPIO0_C7 = 0x0c70, NAND_CS1,
-
- /* GPIO0_D */
- GPIO0_D0 = 0x0d00, UART2_RTSN,
- GPIO0_D1 = 0x0d10, UART2_CTSN,
- GPIO0_D2 = 0x0d20, PWM0,
- GPIO0_D3 = 0x0d30, PWM1,
- GPIO0_D4 = 0x0d40, PWM2,
- GPIO0_D5 = 0x0d50, MMC1_WRPRT,
- GPIO0_D6 = 0x0d60, MMC1_PWREN,
- GPIO0_D7 = 0x0d70, MMC1_BKEPWR,
-
- /* GPIO1_A */
- GPIO1_A0 = 0x1a00, I2S0_MCLK,
- GPIO1_A1 = 0x1a10, I2S0_SCLK,
- GPIO1_A2 = 0x1a20, I2S0_LRCKRX, GPS_CLK,
- GPIO1_A3 = 0x1a30, I2S0_LRCKTX,
- GPIO1_A4 = 0x1a40, I2S0_SDO, GPS_MAG,
- GPIO1_A5 = 0x1a50, I2S0_SDI, GPS_SIGN,
- GPIO1_A6 = 0x1a60, MMC1_INTN,
- GPIO1_A7 = 0x1a70, MMC0_WRPRT,
-
- /* GPIO1_B */
- GPIO1_B0 = 0x1b00, SPI0_CLK, UART1_CTSN,
- GPIO1_B1 = 0x1b10, SPI0_TXD, UART1_SOUT,
- GPIO1_B2 = 0x1b20, SPI0_RXD, UART1_SIN,
- GPIO1_B3 = 0x1b30, SPI0_CS0, UART1_RTSN,
- GPIO1_B4 = 0x1b40, SPI0_CS1,
- GPIO1_B5 = 0x1b50, MMC0_RSTNOUT,
- GPIO1_B6 = 0x1b60, MMC0_PWREN,
- GPIO1_B7 = 0x1b70, MMC0_CMD,
-
- /* GPIO1_C */
- GPIO1_C0 = 0x1c00, MMC0_CLKOUT,
- GPIO1_C1 = 0x1c10, MMC0_DETN,
- GPIO1_C2 = 0x1c20, MMC0_D0,
- GPIO1_C3 = 0x1c30, MMC0_D1,
- GPIO1_C4 = 0x1c40, MMC0_D2,
- GPIO1_C5 = 0x1c50, MMC0_D3,
- GPIO1_C6 = 0x1c60, NAND_CS2, EMMC_CMD,
- GPIO1_C7 = 0x1c70, NAND_CS3, EMMC_RSTNOUT,
-
- /* GPIO1_D */
- GPIO1_D0 = 0x1d00, NAND_D0, EMMC_D0,
- GPIO1_D1 = 0x1d10, NAND_D1, EMMC_D1,
- GPIO1_D2 = 0x1d20, NAND_D2, EMMC_D2,
- GPIO1_D3 = 0x1d30, NAND_D3, EMMC_D3,
- GPIO1_D4 = 0x1d40, NAND_D4, EMMC_D4,
- GPIO1_D5 = 0x1d50, NAND_D5, EMMC_D5,
- GPIO1_D6 = 0x1d60, NAND_D6, EMMC_D6,
- GPIO1_D7 = 0x1d70, NAND_D7, EMMC_D7,
-
- /* GPIO2_A */
- GPIO2_A0 = 0x2a00, NAND_ALE,
- GPIO2_A1 = 0x2a10, NAND_CLE,
- GPIO2_A2 = 0x2a20, NAND_WRN,
- GPIO2_A3 = 0x2a30, NAND_RDN,
- GPIO2_A4 = 0x2a40, NAND_RDY,
- GPIO2_A5 = 0x2a50, NAND_WP, EMMC_PWREN,
- GPIO2_A6 = 0x2a60, NAND_CS0,
- GPIO2_A7 = 0x2a70, NAND_DQS, EMMC_CLKOUT,
-
- /* GPIO2_B */
- GPIO2_B0 = 0x2b00, LCDC0_DCLK, LCDC1_DCLK,
- GPIO2_B1 = 0x2b10, LCDC0_HSYNC, LCDC1_HSYNC,
- GPIO2_B2 = 0x2b20, LCDC0_VSYNC, LCDC1_VSYNC,
- GPIO2_B3 = 0x2b30, LCDC0_DEN, LCDC1_DEN,
- GPIO2_B4 = 0x2b40, LCDC0_D10, LCDC1_D10,
- GPIO2_B5 = 0x2b50, LCDC0_D11, LCDC1_D11,
- GPIO2_B6 = 0x2b60, LCDC0_D12, LCDC1_D12,
- GPIO2_B7 = 0x2b70, LCDC0_D13, LCDC1_D13,
-
- /* GPIO2_C */
- GPIO2_C0 = 0x2c00, LCDC0_D14, LCDC1_D14,
- GPIO2_C1 = 0x2c10, LCDC0_D15, LCDC1_D15,
- GPIO2_C2 = 0x2c20, LCDC0_D16, LCDC1_D16,
- GPIO2_C3 = 0x2c30, LCDC0_D17, LCDC1_D17,
- GPIO2_C4 = 0x2c40, LCDC0_D18, LCDC1_D18, I2C2_SDA,
- GPIO2_C5 = 0x2c50, LCDC0_D19, LCDC1_D19, I2C2_SCL,
- GPIO2_C6 = 0x2c60, LCDC0_D20, LCDC1_D20, UART2_SIN,
- GPIO2_C7 = 0x2c70, LCDC0_D21, LCDC1_D21, UART2_SOUT,
-
- /* GPIO2_D */
- GPIO2_D0 = 0x2d00, LCDC0_D22, LCDC1_D22,
- GPIO2_D1 = 0x2d10, LCDC0_D23, LCDC1_D23,
-
- /* GPIO3_A */
- /* GPIO3_B */
- /* GPIO3_C */
- GPIO3_C1 = 0x3c10, OTG_DRV_VBUS,
-
- /* GPIO3_D */
- GPIO3_D7 = 0x3d70, TEST_CLK_OUT,
-
-};
-#endif
+++ /dev/null
-/*
- * arch/arm/mach-rk2928/include/mach/iomux.h
- *
- *Copyright (C) 2010 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __RK2928_IOMUX_H__
-#define __RK2928_IOMUX_H__
-
-#include <linux/init.h>
-#include <mach/iomux-rk2928.h>
-//gpio0a
-#define GPIO0A_GPIO0A0 0
-#define GPIO0A_I2C0_SCL 1
-#define GPIO0A_GPIO0A1 0
-#define GPIO0A_I2C0_SDA 1
-#define GPIO0A_GPIO0A2 0
-#define GPIO0A_I2C1_SCL 1
-#define GPIO0A_GPIO0A3 0
-#define GPIO0A_I2C1_SDA 1
-#define GPIO0A_GPIO0A6 0
-#define GPIO0A_I2C3_SCL 1
-#define GPIO0A_HDMI_DDCSCL 2
-#define GPIO0A_GPIO0A7 0
-#define GPIO0A_I2C3_SDA 1
-#define GPIO0A_HDMI_DDCSDA 2
-
-//gpio0b
-#define GPIO0B_GPIO0B0 0
-#define GPIO0B_MMC1_CMD 1
-#define GPIO0B_GPIO0B1 0
-#define GPIO0B_MMC1_CLKOUT 1
-#define GPIO0B_GPIO0B2 0
-#define GPIO0B_MMC1_DETN 1
-#define GPIO0B_GPIO0B3 0
-#define GPIO0B_MMC1_D0 1
-#define GPIO0B_GPIO0B4 0
-#define GPIO0B_MMC1_D1 1
-#define GPIO0B_GPIO0B5 0
-#define GPIO0B_MMC1_D2 1
-#define GPIO0B_GPIO0B6 0
-#define GPIO0B_MMC1_D3 1
-#define GPIO0B_GPIO0B7 0
-#define GPIO0B_HDMI_HOTPLUGIN 1
-
-//gpio0c
-#define GPIO0C_GPIO0C0 0
-#define GPIO0C_UART0_SOUT 1
-#define GPIO0C_GPIO0C1 0
-#define GPIO0C_UART0_SIN 1
-#define GPIO0C_GPIO0C2 0
-#define GPIO0C_UART0_RTSN 1
-#define GPIO0C_GPIO0C3 0
-#define GPIO0C_UART0_CTSN 1
-#define GPIO0C_GPIO0C4 0
-#define GPIO0C_HDMI_CECSDA 1
-#define GPIO0C_GPIO0C7 0
-#define GPIO0C_NAND_CS1 1
-
-//gpio0d
-#define GPIO0D_GPIO0D0 0
-#define GPIO0D_UART2_RTSN 1
-#define GPIO0D_GPIO0D1 0
-#define GPIO0D_UART2_CTSN 1
-#define GPIO0D_GPIO0D2 0
-#define GPIO0D_PWM_0 1
-#define GPIO0D_GPIO0D3 0
-#define GPIO0D_PWM_1 1
-#define GPIO0D_GPIO0D4 0
-#define GPIO0D_PWM_2 1
-#define GPIO0D_GPIO0D5 0
-#define GPIO0D_MMC1_WRPRT 1
-#define GPIO0D_GPIO0D6 0
-#define GPIO0D_MMC1_PWREN 1
-#define GPIO0D_GPIO0D7 0
-#define GPIO0D_MMC1_BKEPWR 1
-
-//gpio1a
-#define GPIO1A_GPIO1A0 0
-#define GPIO1A_I2S_MCLK 1
-#define GPIO1A_GPIO1A1 0
-#define GPIO1A_I2S_SCLK 1
-#define GPIO1A_GPIO1A2 0
-#define GPIO1A_I2S_LRCKRX 1
-#define GPIO1A_GPS_CLK 2
-#define GPIO1A_GPIO1A3 0
-#define GPIO1A_I2S_LRCKTX 1
-#define GPIO1A_GPIO1A4 0
-#define GPIO1A_I2S_SDO 1
-#define GPIO1A_GPS_MAG 2
-#define GPIO1A_GPIO1A5 0
-#define GPIO1A_I2S_SDI 1
-#define GPIO1A_GPS_SIGN 2
-#define GPIO1A_GPIO1A6 0
-#define GPIO1A_MMC1_INTN 1
-#define GPIO1A_GPIO1A7 0
-#define GPIO1A_MMC0_WRPRT 1
-
-//gpio1b
-#define GPIO1B_GPIO1B0 0
-#define GPIO1B_SPI_CLK 1
-#define GPIO1B_UART1_CTSN 2
-#define GPIO1B_GPIO1B1 0
-#define GPIO1B_SPI_TXD 1
-#define GPIO1B_UART1_SOUT 2
-#define GPIO1B_GPIO1B2 0
-#define GPIO1B_SPI_RXD 1
-#define GPIO1B_UART1_SIN 2
-#define GPIO1B_GPIO1B3 0
-#define GPIO1B_SPI_CSN0 1
-#define GPIO1B_UART1_RTSN 2
-#define GPIO1B_GPIO1B4 0
-#define GPIO1B_SPI_CSN1 1
-#define GPIO1B_GPIO1B5 0
-#define GPIO1B_MMC0_RSTNOUT 1
-#define GPIO1B_GPIO1B6 0
-#define GPIO1B_MMC0_PWREN 1
-#define GPIO1B_GPIO1B7 0
-#define GPIO1B_MMC0_CMD 1
-
-//gpio1c
-#define GPIO1C_GPIO1C0 0
-#define GPIO1C_MMC0_CLKOUT 1
-#define GPIO1C_GPIO1C1 0
-#define GPIO1C_MMC0_DETN 1
-#define GPIO1C_GPIO1C2 0
-#define GPIO1C_MMC0_D0 1
-#define GPIO1C_GPIO1C3 0
-#define GPIO1C_MMC0_D1 1
-#define GPIO1C_GPIO1C4 0
-#define GPIO1C_MMC0_D2 1
-#define GPIO1C_GPIO1C5 0
-#define GPIO1C_MMC0_D3 1
-#define GPIO1C_GPIO1C6 0
-#define GPIO1C_NAND_CS2 1
-#define GPIO1C_EMMC_CMD 2
-#define GPIO1C_GPIO1C7 0
-#define GPIO1C_NAND_CS3 1
-#define GPIO1C_EMMC_RSTNOUT 2
-
-//gpio1d
-#define GPIO1D_GPIO1D0 0
-#define GPIO1D_NAND_D0 1
-#define GPIO1D_EMMC_D0 2
-#define GPIO1D_GPIO1D1 0
-#define GPIO1D_NAND_D1 1
-#define GPIO1D_EMMC_D1 2
-#define GPIO1D_GPIO1D2 0
-#define GPIO1D_NAND_D2 1
-#define GPIO1D_EMMC_D2 2
-#define GPIO1D_GPIO1D3 0
-#define GPIO1D_NAND_D3 1
-#define GPIO1D_EMMC_D3 2
-#define GPIO1D_GPIO1D4 0
-#define GPIO1D_NAND_D4 1
-#define GPIO1D_EMMC_D4 2
-#define GPIO1D_GPIO1D5 0
-#define GPIO1D_NAND_D5 1
-#define GPIO1D_EMMC_D5 2
-#define GPIO1D_GPIO1D6 0
-#define GPIO1D_NAND_D6 1
-#define GPIO1D_EMMC_D6 2
-#define GPIO1D_GPIO1D7 0
-#define GPIO1D_NAND_D7 1
-#define GPIO1D_EMMC_D7 2
-
-//gpio2a
-#define GPIO2A_GPIO2A0 0
-#define GPIO2A_NAND_ALE 1
-#define GPIO2A_GPIO2A1 0
-#define GPIO2A_NAND_CLE 1
-#define GPIO2A_GPIO2A2 0
-#define GPIO2A_NAND_WRN 1
-#define GPIO2A_GPIO2A3 0
-#define GPIO2A_NAND_RDN 1
-#define GPIO2A_GPIO2A4 0
-#define GPIO2A_NAND_RDY 1
-#define GPIO2A_GPIO2A5 0
-#define GPIO2A_NAND_WP 1
-#define GPIO2A_EMMC_PWREN 2
-#define GPIO2A_GPIO2A6 0
-#define GPIO2A_NAND_CS0 1
-#define GPIO2A_GPIO2A7 0
-#define GPIO2A_NAND_DPS 1
-#define GPIO2A_EMMC_CLKOUT 2
-
-//gpio2b
-#define GPIO2B_GPIO2B0 0
-#define GPIO2B_LCDC0_DCLK 1
-#define GPIO2B_LCDC1_DCLK 2
-#define GPIO2B_GPIO2B1 0
-#define GPIO2B_LCDC0_HSYNC 1
-#define GPIO2B_LCDC1_HSYNC 2
-#define GPIO2B_GPIO2B2 0
-#define GPIO2B_LCDC0_VSYNC 1
-#define GPIO2B_LCDC1_VSYNC 2
-#define GPIO2B_GPIO2B3 0
-#define GPIO2B_LCDC0_DEN 1
-#define GPIO2B_LCDC1_DEN 2
-#define GPIO2B_GPIO2B4 0
-#define GPIO2B_LCDC0_D10 1
-#define GPIO2B_LCDC1_D10 2
-#define GPIO2B_GPIO2B5 0
-#define GPIO2B_LCDC0_D11 1
-#define GPIO2B_LCDC1_D11 2
-#define GPIO2B_GPIO2B6 0
-#define GPIO2B_LCDC0_D12 1
-#define GPIO2B_LCDC1_D12 2
-#define GPIO2B_GPIO2B7 0
-#define GPIO2B_LCDC0_D13 1
-#define GPIO2B_LCDC1_D13 2
-
-//gpio2c
-#define GPIO2C_GPIO2C0 0
-#define GPIO2C_LCDC0_D14 1
-#define GPIO2C_LCDC1_D14 2
-#define GPIO2C_GPIO2C1 0
-#define GPIO2C_LCDC0_D15 1
-#define GPIO2C_LCDC1_D15 2
-#define GPIO2C_GPIO2C2 0
-#define GPIO2C_LCDC0_D16 1
-#define GPIO2C_LCDC1_D16 2
-#define GPIO2C_GPIO2C3 0
-#define GPIO2C_LCDC0_D17 1
-#define GPIO2C_LCDC1_D17 2
-#define GPIO2C_GPIO2C4 0
-#define GPIO2C_LCDC0_D18 1
-#define GPIO2C_LCDC1_D18 2
-#define GPIO2C_I2C2_SDA 3
-#define GPIO2C_GPIO2C5 0
-#define GPIO2C_LCDC0_D19 1
-#define GPIO2C_LCDC1_D19 2
-#define GPIO2C_I2C2_SCL 3
-#define GPIO2C_GPIO2C6 0
-#define GPIO2C_LCDC0_D20 1
-#define GPIO2C_LCDC1_D20 2
-#define GPIO2C_UART2_SIN 3
-#define GPIO2C_GPIO2C7 0
-#define GPIO2C_LCDC0_D21 1
-#define GPIO2C_LCDC1_D21 2
-#define GPIO2C_UART2_SOUT 3
-
-//gpio2d
-#define GPIO2D_GPIO2D0 0
-#define GPIO2D_LCDC0_D22 1
-#define GPIO2D_LCDC1_D22 2
-#define GPIO2D_GPIO2D1 0
-#define GPIO2D_LCDC0_D23 1
-#define GPIO2D_LCDC1_D23 2
-
-//gpio3c
-#define GPIO3C_GPIO3C1 0
-#define GPIO3C_OTG_DRVVBUS 1
-
-//gpio3d
-#define GPIO3D_GPIO3D7 0
-#define GPIO3D_TESTCLK_OUT 1
-
-
-
-//gpio0a
-#define GPIO0A0_I2C0_SCL_NAME "gpio0a0_i2c0_scl_name"
-#define GPIO0A1_I2C0_SDA_NAME "gpio0a1_i2c0_sda_name"
-#define GPIO0A2_I2C1_SCL_NAME "gpio0a2_i2c1_scl_name"
-#define GPIO0A3_I2C1_SDA_NAME "gpio0a3_i2c1_sda_name"
-#define GPIO0A6_I2C3_SCL_HDMI_DDCSCL_NAME "gpio0a6_i2c3_scl_hdmi_ddcscl_name"
-#define GPIO0A7_I2C3_SDA_HDMI_DDCSDA_NAME "gpio0a7_i2c3_sda_hdmi_ddcsda_name"
-
-//gpio0b
-#define GPIO0B0_MMC1_CMD_NAME "gpio0b0_mmc1_cmd_name"
-#define GPIO0B1_MMC1_CLKOUT_NAME "gpio0b1_mmc1_clkout_name"
-#define GPIO0B2_MMC1_DETN_NAME "gpio0b2_mmc1_detn_name"
-#define GPIO0B3_MMC1_D0_NAME "gpio0b3_mmc1_d0_name"
-#define GPIO0B4_MMC1_D1_NAME "gpio0b4_mmc1_d1_name"
-#define GPIO0B5_MMC1_D2_NAME "gpio0b5_mmc1_d2_name"
-#define GPIO0B6_MMC1_D3_NAME "gpio0b6_mmc1_d3_name"
-#define GPIO0B7_HDMI_HOTPLUGIN_NAME "gpio0b7_hdmi_hotplugin_name"
-
-//gpio0c
-#define GPIO0C0_UART0_SOUT_NAME "gpio0c0_uart0_sout_name"
-#define GPIO0C1_UART0_SIN_NAME "gpio0c1_uart0_sin_name"
-#define GPIO0C2_UART0_RTSN_NAME "gpio0c2_uart0_rtsn_name"
-#define GPIO0C3_UART0_CTSN_NAME "gpio0c3_uart0_ctsn_name"
-#define GPIO0C4_HDMI_CECSDA_NAME "gpio0c4_hdmi_cecsda_name"
-#define GPIO0C7_NAND_CS1_NAME "gpio0c7_nand_cs1_name"
-
-//gpio0d
-#define GPIO0D0_UART2_RTSN_NAME "gpio0d0_uart2_rtsn_name"
-#define GPIO0D1_UART2_CTSN_NAME "gpio0d1_uart2_ctsn_name"
-#define GPIO0D2_PWM_0_NAME "gpio0d2_pwm_0_name"
-#define GPIO0D3_PWM_1_NAME "gpio0d3_pwm_1_name"
-#define GPIO0D4_PWM_2_NAME "gpio0d4_pwm_2_name"
-#define GPIO0D5_MMC1_WRPRT_NAME "gpio0d5_mmc1_wrprt_name"
-#define GPIO0D6_MMC1_PWREN_NAME "gpio0d6_mmc1_pwren_name"
-#define GPIO0D7_MMC1_BKEPWR_NAME "gpio0d7_mmc1_bkepwr_name"
-
-//gpio1a
-#define GPIO1A0_I2S_MCLK_NAME "gpio1a0_i2s_mclk_name"
-#define GPIO1A1_I2S_SCLK_NAME "gpio1a1_i2s_sclk_name"
-#define GPIO1A2_I2S_LRCKRX_GPS_CLK_NAME "gpio1a2_i2s_lrckrx_gps_clk_name"
-#define GPIO1A3_I2S_LRCKTX_NAME "gpio1a3_i2s_lrcktx_name"
-#define GPIO1A4_I2S_SDO_GPS_MAG_NAME "gpio1a4_i2s_sdo_gps_mag_name"
-#define GPIO1A5_I2S_SDI_GPS_SIGN_NAME "gpio1a5_i2s_sdi_gps_sign_name"
-#define GPIO1A6_MMC1_INTN_NAME "gpio1a6_mmc1_intn_name"
-#define GPIO1A7_MMC0_WRPRT_NAME "gpio1a7_mmc0_wrprt_name"
-
-//gpio1b
-#define GPIO1B0_SPI_CLK_UART1_CTSN_NAME "gpio1b0_spi_clk_uart1_ctsn_name"
-#define GPIO1B1_SPI_TXD_UART1_SOUT_NAME "gpio1b1_spi_txd_uart1_sout_name"
-#define GPIO1B2_SPI_RXD_UART1_SIN_NAME "gpio1b2_spi_rxd_uart1_sin_name"
-#define GPIO1B3_SPI_CSN0_UART1_RTSN_NAME "gpio1b3_spi_csn0_uart1_rtsn_name"
-#define GPIO1B4_SPI_CSN1_NAME "gpio1b4_spi_csn1_name"
-#define GPIO1B5_MMC0_RSTNOUT_NAME "gpio1b5_mmc0_rstnout_name"
-#define GPIO1B6_MMC0_PWREN_NAME "gpio1b6_mmc0_pwren_name"
-#define GPIO1B7_MMC0_CMD_NAME "gpio1b7_mmc0_cmd_name"
-
-//gpio1c
-#define GPIO1C0_MMC0_CLKOUT_NAME "gpio1c0_mmc0_clkout_name"
-#define GPIO1C1_MMC0_DETN_NAME "gpio1c1_mmc0_detn_name"
-#define GPIO1C2_MMC0_D0_NAME "gpio1c2_mmc0_d0_name"
-#define GPIO1C3_MMC0_D1_NAME "gpio1c3_mmc0_d1_name"
-#define GPIO1C4_MMC0_D2_NAME "gpio1c4_mmc0_d2_name"
-#define GPIO1C5_MMC0_D3_NAME "gpio1c5_mmc0_d3_name"
-#define GPIO1C6_NAND_CS2_EMMC_CMD_NAME "gpio1c6_nand_cs2_emmc_cmd_name"
-#define GPIO1C7_NAND_CS3_EMMC_RSTNOUT_NAME "gpio1c7_nand_cs3_emmc_rstnout_name"
-
-//gpio1d
-#define GPIO1D0_NAND_D0_EMMC_D0_NAME "gpio1d0_nand_d0_emmc_d0_name"
-#define GPIO1D1_NAND_D1_EMMC_D1_NAME "gpio1d1_nand_d1_emmc_d1_name"
-#define GPIO1D2_NAND_D2_EMMC_D2_NAME "gpio1d2_nand_d2_emmc_d2_name"
-#define GPIO1D3_NAND_D3_EMMC_D3_NAME "gpio1d3_nand_d3_emmc_d3_name"
-#define GPIO1D4_NAND_D4_EMMC_D4_NAME "gpio1d4_nand_d4_emmc_d4_name"
-#define GPIO1D5_NAND_D5_EMMC_D5_NAME "gpio1d5_nand_d5_emmc_d5_name"
-#define GPIO1D6_NAND_D6_EMMC_D6_NAME "gpio1d6_nand_d6_emmc_d6_name"
-#define GPIO1D7_NAND_D7_EMMC_D7_NAME "gpio1d7_nand_d7_emmc_d7_name"
-
-//gpio2a
-#define GPIO2A0_NAND_ALE_NAME "gpio2a0_nand_ale_name"
-#define GPIO2A1_NAND_CLE_NAME "gpio2a1_nand_cle_name"
-#define GPIO2A2_NAND_WRN_NAME "gpio2a2_nand_wrn_name"
-#define GPIO2A3_NAND_RDN_NAME "gpio2a3_nand_rdn_name"
-#define GPIO2A4_NAND_RDY_NAME "gpio2a4_nand_rdy_name"
-#define GPIO2A5_NAND_WP_EMMC_PWREN_NAME "gpio2a5_nand_wp_emmc_pwren_name"
-#define GPIO2A6_NAND_CS0_NAME "gpio2a6_nand_cs0_name"
-#define GPIO2A7_NAND_DPS_EMMC_CLKOUT_NAME "gpio2a7_nand_dps_emmc_clkout_name"
-
-//gpio2b
-#define GPIO2B0_LCDC0_DCLK_LCDC1_DCLK_NAME "gpio2b0_lcdc0_dclk_lcdc1_dclk_name"
-#define GPIO2B1_LCDC0_HSYNC_LCDC1_HSYNC_NAME "gpio2b1_lcdc0_hsync_lcdc1_hsync_name"
-#define GPIO2B2_LCDC0_VSYNC_LCDC1_VSYNC_NAME "gpio2b2_lcdc0_vsync_lcdc1_vsync_name"
-#define GPIO2B3_LCDC0_DEN_LCDC1_DEN_NAME "gpio2b3_lcdc0_den_lcdc1_den_name"
-#define GPIO2B4_LCDC0_D10_LCDC1_D10_NAME "gpio2b4_lcdc0_d10_lcdc1_d10_name"
-#define GPIO2B5_LCDC0_D11_LCDC1_D11_NAME "gpio2b5_lcdc0_d11_lcdc1_d11_name"
-#define GPIO2B6_LCDC0_D12_LCDC1_D12_NAME "gpio2b6_lcdc0_d12_lcdc1_d12_name"
-#define GPIO2B7_LCDC0_D13_LCDC1_D13_NAME "gpio2b7_lcdc0_d13_lcdc1_d13_name"
-
-//gpio2c
-#define GPIO2C0_LCDC0_D14_LCDC1_D14_NAME "gpio2c0_lcdc0_d14_lcdc1_d14_name"
-#define GPIO2C1_LCDC0_D15_LCDC1_D15_NAME "gpio2c1_lcdc0_d15_lcdc1_d15_name"
-#define GPIO2C2_LCDC0_D16_LCDC1_D16_NAME "gpio2c2_lcdc0_d16_lcdc1_d16_name"
-#define GPIO2C3_LCDC0_D17_LCDC1_D17_NAME "gpio2c3_lcdc0_d17_lcdc1_d17_name"
-#define GPIO2C4_LCDC0_D18_LCDC1_D18_I2C2_SDA_NAME "gpio2c4_lcdc0_d18_lcdc1_d18_i2c2_sda_name"
-#define GPIO2C5_LCDC0_D19_LCDC1_D19_I2C2_SCL_NAME "gpio2c5_lcdc0_d19_lcdc1_d19_i2c2_scl_name"
-#define GPIO2C6_LCDC0_D20_LCDC1_D20_UART2_SIN_NAME "gpio2c6_lcdc0_d20_lcdc1_d20_uart2_sin_name"
-#define GPIO2C7_LCDC0_D21_LCDC1_D21_UART2_SOUT_NAME "gpio2c7_lcdc0_d21_lcdc1_d21_uart2_sout_name"
-
-//gpio2d
-#define GPIO2D0_LCDC0_D22_LCDC1_D22_NAME "gpio2d0_lcdc0_d22_lcdc1_d22_name"
-#define GPIO2D1_LCDC0_D23_LCDC1_D23_NAME "gpio2d1_lcdc0_d23_lcdc1_d23_name"
-
-//gpio3c
-#define GPIO3C1_OTG_DRVVBUS_NAME "gpio3c1_otg_drvvbus_name"
-
-//gpio3d
-#define GPIO3D7_TESTCLK_OUT_NAME "gpio3d7_testclk_out_name"
-
-
-#define DEFAULT 0
-#define INITIAL 1
-
-#define GRF_GPIO0A_IOMUX RK2928_GRF_BASE+0x00a8
-#define GRF_GPIO0B_IOMUX RK2928_GRF_BASE+0x00ac
-#define GRF_GPIO0C_IOMUX RK2928_GRF_BASE+0x00b0
-#define GRF_GPIO0D_IOMUX RK2928_GRF_BASE+0x00b4
-
-#define GRF_GPIO1A_IOMUX RK2928_GRF_BASE+0x00b8
-#define GRF_GPIO1B_IOMUX RK2928_GRF_BASE+0x00bc
-#define GRF_GPIO1C_IOMUX RK2928_GRF_BASE+0x00c0
-#define GRF_GPIO1D_IOMUX RK2928_GRF_BASE+0x00c4
-
-#define GRF_GPIO2A_IOMUX RK2928_GRF_BASE+0x00c8
-#define GRF_GPIO2B_IOMUX RK2928_GRF_BASE+0x00cc
-#define GRF_GPIO2C_IOMUX RK2928_GRF_BASE+0x00d0
-#define GRF_GPIO2D_IOMUX RK2928_GRF_BASE+0x00d4
-
-#define GRF_GPIO3C_IOMUX RK2928_GRF_BASE+0x00e0
-#define GRF_GPIO3D_IOMUX RK2928_GRF_BASE+0x00e4
-
-#define GRF_GPIO0L_PULL 0x0118
-#define GRF_GPIO0H_PULL 0x011c
-
-#define GRF_GPIO1L_PULL 0x0120
-#define GRF_GPIO1H_PULL 0x0124
-
-#define GRF_GPIO2L_PULL 0x0128
-#define GRF_GPIO2H_PULL 0x012c
-
-#define GRF_GPIO3L_PULL 0x0130
-#define GRF_GPIO3H_PULL 0x0134
-
-#define GRF_SOC_CON0 0x0140
-#define GRF_SOC_CON1 0x0144
-#define GRF_SOC_CON2 0x0148
-
-#define GRF_SOC_STATUS0 0x014c
-
-#define GRF_LVDS_CON0 0x0150
-
-#define GRF_DMAC1_CON0 0x015c
-#define GRF_DMAC1_CON1 0x0160
-#define GRF_DMAC1_CON2 0x0164
-
-#define GRF_UOC0_CON0 0x016c
-#define GRF_UOC0_CON1 0x0170
-#define GRF_UOC0_CON2 0x0174
-#define GRF_UOC0_CON3 0x0178
-#define GRF_UOC0_CON5 0x017c
-
-#define GRF_UOC1_CON0 0x0180
-#define GRF_UOC1_CON1 0x0184
-#define GRF_UOC1_CON2 0x0188
-#define GRF_UOC1_CON3 0x018c
-#define GRF_UOC1_CON4 0x0190
-#define GRF_UOC1_CON5 0x0194
-
-#define GRF_DDRC_STAT 0x019c
-
-#define GRF_OS_REG0 0x01c8
-#define GRF_OS_REG1 0x01cc
-#define GRF_OS_REG2 0x01d0
-#define GRF_OS_REG3 0x01d4
-#define GRF_OS_REG4 0x01d8
-#define GRF_OS_REG5 0x01dc
-#define GRF_OS_REG6 0x01e0
-#define GRF_OS_REG7 0x01e4
-
-#define MUX_CFG(desc,reg,off,interl,mux_mode,bflags) \
-{ \
- .name = desc, \
- .offset = off, \
- .interleave = interl, \
- .mux_reg = GRF_##reg##_IOMUX, \
- .mode = mux_mode, \
- .premode = mux_mode, \
- .flags = bflags, \
-},
-
-struct mux_config {
- char *name;
- const unsigned int offset;
- unsigned int mode;
- unsigned int premode;
- const void* __iomem mux_reg;
- const unsigned int interleave;
- unsigned int flags;
-};
-#define rk29_mux_api_set rk30_mux_api_set
-
-extern int __init rk30_iomux_init(void);
-extern void rk30_mux_api_set(char *name, unsigned int mode);
-extern int rk30_mux_api_get(char *name);
-
-#endif
+++ /dev/null
-#ifndef __MACH_IRQS_H
-#define __MACH_IRQS_H
-
-#define FIQ_START 0
-
-#define IRQ_LOCALTIMER 29
-
-#define IRQ_DMAC_0 32
-#define IRQ_DMAC_1 33
-#define IRQ_DDR_PCTL 34
-#define IRQ_GPU_GP 35
-#define IRQ_GPU_MMU 36
-#define IRQ_GPU_PP 37
-#define IRQ_VEPU 38
-#define IRQ_VDPU 39
-#define IRQ_CIF 40
-#define IRQ_LCDC 41
-#define IRQ_USB_OTG 42
-#define IRQ_USB_HOST 43
-#define IRQ_GPS 44
-#define IRQ_GPS_TIMER 45
-#define IRQ_SDMMC 46
-#define IRQ_SDIO 47
-#define IRQ_EMMC 48
-#define IRQ_SARADC 49
-#define IRQ_NANDC 50
-#define IRQ_I2S 51
-#define IRQ_UART0 52
-#define IRQ_UART1 53
-#define IRQ_UART2 54
-#define IRQ_SPI 55
-#define IRQ_I2C0 56
-#define IRQ_I2C1 57
-#define IRQ_I2C2 58
-#define IRQ_I2C3 59
-#define IRQ_TIMER0 60
-#define IRQ_TIMER1 61
-#define IRQ_PWM0 62
-#define IRQ_PWM1 63
-#define IRQ_PWM2 64
-
-#define IRQ_WDT 66
-#define IRQ_OTG_BVALID 67
-#define IRQ_GPIO0 68
-#define IRQ_GPIO1 69
-#define IRQ_GPIO2 70
-#define IRQ_GPIO3 71
-#define IRQ_CRYPTO 72
-
-#ifdef CONFIG_ARCH_RK2928
-#define IRQ_PERI_AHB_USB_ARBITER 74
-#define IRQ_PERI_AHB_EMEM_ARBITER 75
-#else
-#define IRQ_PERI_AHB_USB_ARBITER 73
-#define IRQ_PERI_AHB_EMEM_ARBITER 74
-#endif
-#define IRQ_LCDC1 75
-#define IRQ_RGA 76
-#define IRQ_HDMI 77
-#define IRQ_SDMMC_DETECT 78
-#define IRQ_SDIO_DETECT 79
-#define IRQ_IEP 80
-#define IRQ_EBC 81
-
-#define IRQ_OTG0_ID 83
-#define IRQ_OTG0_LINESTATE 84
-#define IRQ_OTG1_LINESTATE 85
-#define IRQ_SD_DETECTN 86
-
-#define IRQ_ARM_PMU 118
-
-//hhb@rock-chips.com this spi is used for fiq_debugger signal irq
-#define IRQ_UART_SIGNAL 127
-
-#define NR_GIC_IRQS (4 * 32)
-#define NR_GPIO_IRQS (4 * 32)
-#define NR_BOARD_IRQS 64
-#define NR_IRQS (NR_GIC_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS)
-
-#define IRQ_BOARD_BASE (NR_GIC_IRQS + NR_GPIO_IRQS)
-
-#endif
+++ /dev/null
-#include <plat/loader.h>
+++ /dev/null
-#ifndef __MACH_MEMORY_H
-#define __MACH_MEMORY_H
-
-#include <plat/memory.h>
-#include <mach/io.h>
-
-/*
- * SRAM memory whereabouts
- */
-#define SRAM_CODE_OFFSET (RK2928_IMEM_BASE + 0x0000)
-#define SRAM_CODE_END (RK2928_IMEM_BASE + 0x0FFF)
-#define SRAM_DATA_OFFSET (RK2928_IMEM_BASE + 0x1000)
-#define SRAM_DATA_END (RK2928_IMEM_BASE + 0x1FFF)
-
-#endif
+++ /dev/null
-#ifndef __MACH_PMU_H
-#define __MACH_PMU_H
-
-enum pmu_power_domain {
- PD_A9_0 = 0,
- PD_A9_1,
- PD_ALIVE,
- PD_RTC,
- PD_SCU,
- PD_CPU,
- PD_PERI = 6,
- PD_VIO,
- PD_VIDEO,
- PD_VCODEC = PD_VIDEO,
- PD_GPU,
- PD_DBG,
-};
-
-static inline bool pmu_power_domain_is_on(enum pmu_power_domain pd)
-{
- return true;
-}
-
-static inline void pmu_set_power_domain(enum pmu_power_domain pd, bool on)
-{
-}
-
-enum pmu_idle_req {
- IDLE_REQ_CPU = 0,
- IDLE_REQ_PERI,
- IDLE_REQ_GPU,
- IDLE_REQ_VIDEO,
- IDLE_REQ_VIO,
-};
-
-static inline void pmu_set_idle_request(enum pmu_idle_req req, bool idle)
-{
-}
-
-#endif
+++ /dev/null
-/* camera driver header file
-
- Copyright (C) 2003, Intel Corporation
- Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-*/
-#ifndef __ASM_ARCH_CAMERA_RK2928_H_
-
-#define __ASM_ARCH_CAMERA_RK2928_H_
-
-#if defined(CONFIG_ARCH_RK2928)
-#define RK29_CAM_DRV_NAME "rk-camera-rk2928"
-#elif defined(CONFIG_ARCH_RK3026)
-#define RK29_CAM_DRV_NAME "rk-camera-rk3026"
-#endif
-
-#define RK_SUPPORT_CIF0 1
-#define RK_SUPPORT_CIF1 0
-
-#include <plat/rk_camera.h>
-
-#define CONFIG_CAMERA_SCALE_CROP_MACHINE RK_CAM_SCALE_CROP_ARM
-
-#if (CONFIG_CAMERA_SCALE_CROP_MACHINE==RK_CAM_SCALE_CROP_ARM)
- #define CAMERA_SCALE_CROP_MACHINE "arm"
-#elif (CONFIG_CAMERA_SCALE_CROP_MACHINE==RK_CAM_SCALE_CROP_IPP)
- #define CAMERA_SCALE_CROP_MACHINE "ipp"
-#elif (CONFIG_CAMERA_SCALE_CROP_MACHINE==RK_CAM_SCALE_CROP_RGA)
- #define CAMERA_SCALE_CROP_MACHINE "rga"
-#elif (CONFIG_CAMERA_SCALE_CROP_MACHINE==RK_CAM_SCALE_CROP_PP)
- #define CAMERA_SCALE_CROP_MACHINE "pp"
-#endif
-
-
-#define CAMERA_VIDEOBUF_ARM_ACCESS 1
-
-#endif
-
+++ /dev/null
-#ifndef __MACH_SRAM_H
-#define __MACH_SRAM_H
-
-#include <plat/sram.h>
-
-#define SRAM_LOOPS_PER_USEC 24
-#define SRAM_LOOP(loops) do { unsigned int i = (loops); if (i < 7) i = 7; barrier(); asm volatile(".align 4; 1: subs %0, %0, #1; bne 1b;" : "+r" (i)); } while (0)
-/* delay on slow mode */
-#define sram_udelay(usecs) SRAM_LOOP((usecs)*SRAM_LOOPS_PER_USEC)
-/* delay on deep slow mode */
-#define sram_32k_udelay(usecs) SRAM_LOOP(((usecs)*SRAM_LOOPS_PER_USEC)/(24000000/32768))
-
-#endif
+++ /dev/null
-#include <plat/system.h>
+++ /dev/null
-#include <plat/timex.h>
+++ /dev/null
-#include <plat/uncompress.h>
+++ /dev/null
-#ifndef __MACH_VMALLOC_H
-#define __MACH_VMALLOC_H
-
-#define VMALLOC_END 0xFE800000
-
-#endif
+++ /dev/null
-/* arch/arm/mach-rk2928/io.c
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-
-#include <asm/page.h>
-#include <asm/mach/map.h>
-
-#define RK2928_DEVICE(name) { \
- .virtual = (unsigned long) RK2928_##name##_BASE, \
- .pfn = __phys_to_pfn(RK2928_##name##_PHYS), \
- .length = RK2928_##name##_SIZE, \
- .type = MT_DEVICE, \
- }
-
-static struct map_desc rk2928_io_desc[] __initdata = {
- RK2928_DEVICE(ROM),
- RK2928_DEVICE(CORE),
- RK2928_DEVICE(CPU_AXI_BUS),
-#if CONFIG_RK_DEBUG_UART == 0
- RK2928_DEVICE(UART0),
-#elif CONFIG_RK_DEBUG_UART == 1
- RK2928_DEVICE(UART1),
-#elif CONFIG_RK_DEBUG_UART == 2
- RK2928_DEVICE(UART2),
-#endif
- RK2928_DEVICE(GRF),
- RK2928_DEVICE(CRU),
- RK2928_DEVICE(GPIO0),
- RK2928_DEVICE(GPIO1),
- RK2928_DEVICE(GPIO2),
- RK2928_DEVICE(GPIO3),
- RK2928_DEVICE(TIMER0),
- RK2928_DEVICE(TIMER1),
- RK2928_DEVICE(PWM),
- RK2928_DEVICE(DDR_PCTL),
- RK2928_DEVICE(DDR_PHY),
- RK2928_DEVICE(RKI2C0),
- RK2928_DEVICE(RKI2C1),
- RK2928_DEVICE(EFUSE),
-};
-
-void __init rk2928_map_common_io(void)
-{
- iotable_init(rk2928_io_desc, ARRAY_SIZE(rk2928_io_desc));
-}
+++ /dev/null
-/*
- * arch/arm/mach-rk2928/iomux.c
- *
- *Copyright (C) 2010 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <asm/system.h>
-#include <asm/io.h>
-#include <linux/spinlock.h>
-
-#include <mach/io.h>
-#include <mach/iomux.h>
-#include <mach/gpio.h>
-
-//#define IOMUX_DBG
-#define INVALID_MUX "invalid"
-static struct mux_config rk30_muxs[] = {
-/*
- * description mux mode mux mux
- * reg offset inter mode
- */
-//gpio0a
-MUX_CFG(GPIO0A0_I2C0_SCL_NAME, GPIO0A, 0, 1, 0, DEFAULT)
-MUX_CFG(GPIO0A1_I2C0_SDA_NAME, GPIO0A, 2, 1, 0, DEFAULT)
-MUX_CFG(GPIO0A2_I2C1_SCL_NAME, GPIO0A, 4, 1, 0, DEFAULT)
-MUX_CFG(GPIO0A3_I2C1_SDA_NAME, GPIO0A, 6, 1, 0, DEFAULT)
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-MUX_CFG(GPIO0A6_I2C3_SCL_HDMI_DDCSCL_NAME, GPIO0A, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO0A7_I2C3_SDA_HDMI_DDCSDA_NAME, GPIO0A, 14, 2, 0, DEFAULT)
-
-//gpio0b
-MUX_CFG(GPIO0B0_MMC1_CMD_NAME, GPIO0B, 0, 1, 0, DEFAULT)
-MUX_CFG(GPIO0B1_MMC1_CLKOUT_NAME, GPIO0B, 2, 1, 0, DEFAULT)
-MUX_CFG(GPIO0B2_MMC1_DETN_NAME, GPIO0B, 4, 1, 0, DEFAULT)
-MUX_CFG(GPIO0B3_MMC1_D0_NAME, GPIO0B, 6, 1, 0, DEFAULT)
-MUX_CFG(GPIO0B4_MMC1_D1_NAME, GPIO0B, 8, 1, 0, DEFAULT)
-MUX_CFG(GPIO0B5_MMC1_D2_NAME, GPIO0B, 10, 1, 0, DEFAULT)
-MUX_CFG(GPIO0B6_MMC1_D3_NAME, GPIO0B, 12, 1, 0, DEFAULT)
-MUX_CFG(GPIO0B7_HDMI_HOTPLUGIN_NAME, GPIO0B, 14, 1, 0, DEFAULT)
-
-//gpio0c
-MUX_CFG(GPIO0C0_UART0_SOUT_NAME, GPIO0C, 0, 1, 0, DEFAULT)
-MUX_CFG(GPIO0C1_UART0_SIN_NAME, GPIO0C, 2, 1, 0, DEFAULT)
-MUX_CFG(GPIO0C2_UART0_RTSN_NAME, GPIO0C, 4, 1, 0, DEFAULT)
-MUX_CFG(GPIO0C3_UART0_CTSN_NAME, GPIO0C, 6, 1, 0, DEFAULT)
-MUX_CFG(GPIO0C4_HDMI_CECSDA_NAME, GPIO0C, 8, 1, 0, DEFAULT)
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-MUX_CFG(GPIO0C7_NAND_CS1_NAME, GPIO0C, 14, 1, 0, DEFAULT)
-
-//gpio0d
-MUX_CFG(GPIO0D0_UART2_RTSN_NAME, GPIO0D, 0, 1, 0, DEFAULT)
-MUX_CFG(GPIO0D1_UART2_CTSN_NAME, GPIO0D, 2, 1, 0, DEFAULT)
-MUX_CFG(GPIO0D2_PWM_0_NAME, GPIO0D, 4, 1, 0, DEFAULT)
-MUX_CFG(GPIO0D3_PWM_1_NAME, GPIO0D, 6, 1, 0, DEFAULT)
-MUX_CFG(GPIO0D4_PWM_2_NAME, GPIO0D, 8, 1, 0, DEFAULT)
-MUX_CFG(GPIO0D5_MMC1_WRPRT_NAME, GPIO0D, 10, 1, 0, DEFAULT)
-MUX_CFG(GPIO0D6_MMC1_PWREN_NAME, GPIO0D, 12, 1, 0, DEFAULT)
-MUX_CFG(GPIO0D7_MMC1_BKEPWR_NAME, GPIO0D, 14, 1, 0, DEFAULT)
-
-//gpio1a
-MUX_CFG(GPIO1A0_I2S_MCLK_NAME, GPIO1A, 0, 1, 0, DEFAULT)
-MUX_CFG(GPIO1A1_I2S_SCLK_NAME, GPIO1A, 2, 1, 0, DEFAULT)
-MUX_CFG(GPIO1A2_I2S_LRCKRX_GPS_CLK_NAME, GPIO1A, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO1A3_I2S_LRCKTX_NAME, GPIO1A, 6, 1, 0, DEFAULT)
-MUX_CFG(GPIO1A4_I2S_SDO_GPS_MAG_NAME, GPIO1A, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO1A5_I2S_SDI_GPS_SIGN_NAME, GPIO1A, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO1A6_MMC1_INTN_NAME, GPIO1A, 12, 1, 0, DEFAULT)
-MUX_CFG(GPIO1A7_MMC0_WRPRT_NAME, GPIO1A, 14, 1, 0, DEFAULT)
-
-//gpio1b
-MUX_CFG(GPIO1B0_SPI_CLK_UART1_CTSN_NAME, GPIO1B, 0, 2, 0, DEFAULT)
-MUX_CFG(GPIO1B1_SPI_TXD_UART1_SOUT_NAME, GPIO1B, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO1B2_SPI_RXD_UART1_SIN_NAME, GPIO1B, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO1B3_SPI_CSN0_UART1_RTSN_NAME, GPIO1B, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO1B4_SPI_CSN1_NAME, GPIO1B, 8, 1, 0, DEFAULT)
-MUX_CFG(GPIO1B5_MMC0_RSTNOUT_NAME, GPIO1B, 10, 1, 0, DEFAULT)
-MUX_CFG(GPIO1B6_MMC0_PWREN_NAME, GPIO1B, 12, 1, 0, DEFAULT)
-MUX_CFG(GPIO1B7_MMC0_CMD_NAME, GPIO1B, 14, 1, 0, DEFAULT)
-
-//gpio1c
-MUX_CFG(GPIO1C0_MMC0_CLKOUT_NAME, GPIO1C, 0, 1, 0, DEFAULT)
-MUX_CFG(GPIO1C1_MMC0_DETN_NAME, GPIO1C, 2, 1, 0, DEFAULT)
-MUX_CFG(GPIO1C2_MMC0_D0_NAME, GPIO1C, 4, 1, 0, DEFAULT)
-MUX_CFG(GPIO1C3_MMC0_D1_NAME, GPIO1C, 6, 1, 0, DEFAULT)
-MUX_CFG(GPIO1C4_MMC0_D2_NAME, GPIO1C, 8, 1, 0, DEFAULT)
-MUX_CFG(GPIO1C5_MMC0_D3_NAME, GPIO1C, 10, 1, 0, DEFAULT)
-MUX_CFG(GPIO1C6_NAND_CS2_EMMC_CMD_NAME, GPIO1C, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO1C7_NAND_CS3_EMMC_RSTNOUT_NAME, GPIO1C, 14, 2, 0, DEFAULT)
-
-//gpio1d
-MUX_CFG(GPIO1D0_NAND_D0_EMMC_D0_NAME, GPIO1D, 0, 2, 0, DEFAULT)
-MUX_CFG(GPIO1D1_NAND_D1_EMMC_D1_NAME, GPIO1D, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO1D2_NAND_D2_EMMC_D2_NAME, GPIO1D, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO1D3_NAND_D3_EMMC_D3_NAME, GPIO1D, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO1D4_NAND_D4_EMMC_D4_NAME, GPIO1D, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO1D5_NAND_D5_EMMC_D5_NAME, GPIO1D, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO1D6_NAND_D6_EMMC_D6_NAME, GPIO1D, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO1D7_NAND_D7_EMMC_D7_NAME, GPIO1D, 14, 2, 0, DEFAULT)
-
-//gpio2a
-MUX_CFG(GPIO2A0_NAND_ALE_NAME, GPIO2A, 0, 1, 0, DEFAULT)
-MUX_CFG(GPIO2A1_NAND_CLE_NAME, GPIO2A, 2, 1, 0, DEFAULT)
-MUX_CFG(GPIO2A2_NAND_WRN_NAME, GPIO2A, 4, 1, 0, DEFAULT)
-MUX_CFG(GPIO2A3_NAND_RDN_NAME, GPIO2A, 6, 1, 0, DEFAULT)
-MUX_CFG(GPIO2A4_NAND_RDY_NAME, GPIO2A, 8, 1, 0, DEFAULT)
-MUX_CFG(GPIO2A5_NAND_WP_EMMC_PWREN_NAME, GPIO2A, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO2A6_NAND_CS0_NAME, GPIO2A, 12, 1, 0, DEFAULT)
-MUX_CFG(GPIO2A7_NAND_DPS_EMMC_CLKOUT_NAME, GPIO2A, 14, 2, 0, DEFAULT)
-
-//gpio2b
-MUX_CFG(GPIO2B0_LCDC0_DCLK_LCDC1_DCLK_NAME, GPIO2B, 0, 2, 0, DEFAULT)
-MUX_CFG(GPIO2B1_LCDC0_HSYNC_LCDC1_HSYNC_NAME, GPIO2B, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO2B2_LCDC0_VSYNC_LCDC1_VSYNC_NAME, GPIO2B, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO2B3_LCDC0_DEN_LCDC1_DEN_NAME, GPIO2B, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO2B4_LCDC0_D10_LCDC1_D10_NAME, GPIO2B, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO2B5_LCDC0_D11_LCDC1_D11_NAME, GPIO2B, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO2B6_LCDC0_D12_LCDC1_D12_NAME, GPIO2B, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO2B7_LCDC0_D13_LCDC1_D13_NAME, GPIO2B, 14, 2, 0, DEFAULT)
-
-//gpio2c
-MUX_CFG(GPIO2C0_LCDC0_D14_LCDC1_D14_NAME, GPIO2C, 0, 2, 0, DEFAULT)
-MUX_CFG(GPIO2C1_LCDC0_D15_LCDC1_D15_NAME, GPIO2C, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO2C2_LCDC0_D16_LCDC1_D16_NAME, GPIO2C, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO2C3_LCDC0_D17_LCDC1_D17_NAME, GPIO2C, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO2C4_LCDC0_D18_LCDC1_D18_I2C2_SDA_NAME,GPIO2C, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO2C5_LCDC0_D19_LCDC1_D19_I2C2_SCL_NAME,GPIO2C, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO2C6_LCDC0_D20_LCDC1_D20_UART2_SIN_NAME,GPIO2C, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO2C7_LCDC0_D21_LCDC1_D21_UART2_SOUT_NAME,GPIO2C, 14, 2, 0, DEFAULT)
-
-//gpio2d
-MUX_CFG(GPIO2D0_LCDC0_D22_LCDC1_D22_NAME, GPIO2D, 0, 2, 0, DEFAULT)
-MUX_CFG(GPIO2D1_LCDC0_D23_LCDC1_D23_NAME, GPIO2D, 2, 2, 0, DEFAULT)
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-
-//gpio3a
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-//gpio3b
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-//gpio3c
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-MUX_CFG(GPIO3C1_OTG_DRVVBUS_NAME, GPIO3C, 2, 1, 0, DEFAULT)
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-
-//gpio3d
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-MUX_CFG(INVALID_MUX, GPIO0A, 0, 0, 0, DEFAULT)
-MUX_CFG(GPIO3D7_TESTCLK_OUT_NAME, GPIO3D, 14, 1, 0, DEFAULT)
-};
-
-
-void rk30_mux_set(struct mux_config *cfg)
-{
- int regValue = 0;
- int mask;
-
- if(strcmp(cfg->name, INVALID_MUX) == 0)
- return;
-
- mask = (((1<<(cfg->interleave))-1)<<cfg->offset) << 16;
- regValue |= mask;
- regValue |=(cfg->mode<<cfg->offset);
-#ifdef IOMUX_DBG
- printk("%s::reg=0x%p,Value=0x%x,mask=0x%x\n",__FUNCTION__,cfg->mux_reg,regValue,mask);
-#endif
- writel_relaxed(regValue,cfg->mux_reg);
- dsb();
-
- return;
-}
-
-
-int __init rk2928_iomux_init(void)
-{
- int i;
- printk("%s\n",__func__);
-
- iomux_init();
-
- for(i=0;i<ARRAY_SIZE(rk30_muxs);i++)
- {
- if(rk30_muxs[i].flags != DEFAULT)
- rk30_mux_set(&rk30_muxs[i]);
- }
-
-#if defined(CONFIG_UART0_RK29) || (CONFIG_RK_DEBUG_UART == 0)
- rk30_mux_api_set(GPIO0C0_UART0_SOUT_NAME, GPIO0C_UART0_SOUT);
- rk30_mux_api_set(GPIO0C1_UART0_SIN_NAME, GPIO0C_UART0_SIN);
-#ifdef CONFIG_UART0_CTS_RTS_RK29
- rk30_mux_api_set(GPIO0C2_UART0_RTSN_NAME, GPIO0C_UART0_RTSN);
- rk30_mux_api_set(GPIO0C3_UART0_CTSN_NAME, GPIO0C_UART0_CTSN);
-#endif
-#endif
-
-#if defined(CONFIG_UART1_RK29) || (CONFIG_RK_DEBUG_UART == 1)
- //UART1 OR SPIM0
- rk30_mux_api_set(GPIO1B2_SPI_RXD_UART1_SIN_NAME, GPIO1B_UART1_SIN);
- rk30_mux_api_set(GPIO1B1_SPI_TXD_UART1_SOUT_NAME, GPIO1B_UART1_SOUT);
-#ifdef CONFIG_UART1_CTS_RTS_RK29
- rk30_mux_api_set(GPIO1B0_SPI_CLK_UART1_CTSN_NAME, GPIO1B_UART1_CTSN);
- rk30_mux_api_set(GPIO1B3_SPI_CSN0_UART1_RTSN_NAME, GPIO1B_UART1_RTSN);
-#endif
-#endif
-
-#if defined(CONFIG_UART2_RK29) || (CONFIG_RK_DEBUG_UART == 2)
- rk30_mux_api_set(GPIO2C6_LCDC0_D20_LCDC1_D20_UART2_SIN_NAME, GPIO2C_UART2_SIN);
- rk30_mux_api_set(GPIO2C7_LCDC0_D21_LCDC1_D21_UART2_SOUT_NAME, GPIO2C_UART2_SOUT);
-#ifdef CONFIG_UART2_CTS_RTS_RK29
- rk30_mux_api_set(GPIO0D0_UART2_RTSN_NAME, GPIO0D_UART2_RTSN);
- rk30_mux_api_set(GPIO0D1_UART2_CTSN_NAME, GPIO0D_UART2_CTSN);
-#endif
-#endif
-
-#ifdef CONFIG_SPIM0_RK29
- //UART1 OR SPIM0
- rk30_mux_api_set(GPIO1B0_SPI_CLK_UART1_CTSN_NAME, GPIO1B_SPI_CLK);
- rk30_mux_api_set(GPIO1B1_SPI_TXD_UART1_SOUT_NAME, GPIO1B_SPI_TXD);
- rk30_mux_api_set(GPIO1B2_SPI_RXD_UART1_SIN_NAME, GPIO1B_SPI_RXD);
- rk30_mux_api_set(GPIO1B3_SPI_CSN0_UART1_RTSN_NAME, GPIO1B_SPI_CSN0);
-#endif
-
-#ifdef CONFIG_I2C0_RK30
- rk30_mux_api_set(GPIO0A0_I2C0_SCL_NAME, GPIO0A_I2C0_SCL);
- rk30_mux_api_set(GPIO0A1_I2C0_SDA_NAME, GPIO0A_I2C0_SDA);
-#endif
-
-#ifdef CONFIG_I2C1_RK30
- rk30_mux_api_set(GPIO0A2_I2C1_SCL_NAME, GPIO0A_I2C1_SCL);
- rk30_mux_api_set(GPIO0A3_I2C1_SDA_NAME, GPIO0A_I2C1_SDA);
-#endif
-
-#ifdef CONFIG_I2C2_RK30
- rk30_mux_api_set(GPIO2C4_LCDC0_D18_LCDC1_D18_I2C2_SDA_NAME, GPIO2C_I2C2_SDA);
- rk30_mux_api_set(GPIO2C5_LCDC0_D19_LCDC1_D19_I2C2_SCL_NAME, GPIO2C_I2C2_SCL);
-#endif
-
-#ifdef CONFIG_I2C3_RK30
- rk30_mux_api_set(GPIO0A6_I2C3_SCL_HDMI_DDCSCL_NAME, GPIO0A_I2C3_SCL);
- rk30_mux_api_set(GPIO0A7_I2C3_SDA_HDMI_DDCSDA_NAME, GPIO0A_I2C3_SDA);
-#endif
-
- return 0;
-}
-
-/*
- *config iomux : input iomux name and iomux flags
- */
-void rk30_mux_api_set(char *name, unsigned int mode)
-{
- int i;
- if (!name) {
- return;
- }
- for(i=0;i<ARRAY_SIZE(rk30_muxs);i++)
- {
- if (!strcmp(rk30_muxs[i].name, name))
- {
- rk30_muxs[i].premode = rk30_muxs[i].mode;
- rk30_muxs[i].mode = mode;
- rk30_mux_set(&rk30_muxs[i]);
- break;
- }
- }
-}
-EXPORT_SYMBOL(rk30_mux_api_set);
-void gpio_set_iomux(int gpio)
-{
- struct mux_config *cfg;
-
- cfg = &rk30_muxs[(gpio - PIN_BASE)];
- cfg->mode = 0;
- rk30_mux_set(cfg);
-}
-EXPORT_SYMBOL(gpio_set_iomux);
-
-int rk30_mux_api_get(char *name)
-{
- int i,ret=0;
- if (!name) {
- return -1;
- }
- for(i=0;i<ARRAY_SIZE(rk30_muxs);i++)
- {
- if (!strcmp(rk30_muxs[i].name, name))
- {
- ret = readl(rk30_muxs[i].mux_reg);
- ret = (ret >> rk30_muxs[i].offset) &((1<<(rk30_muxs[i].interleave))-1);
- return ret;
- }
- }
-
- return -1;
-}
-EXPORT_SYMBOL(rk30_mux_api_get);
-
+++ /dev/null
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/pm.h>
-#include <linux/suspend.h>
-#include <linux/random.h>
-#include <linux/crc32.h>
-#include <linux/io.h>
-#include <linux/wakelock.h>
-#include <asm/cacheflush.h>
-#include <asm/tlbflush.h>
-#include <asm/hardware/cache-l2x0.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/pmu.h>
-#include <mach/board.h>
-#include <mach/system.h>
-#include <mach/sram.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <mach/cru.h>
-#include <mach/debug_uart.h>
-#include <linux/regulator/machine.h>
-
-
-#define cru_readl(offset) readl_relaxed(RK2928_CRU_BASE + offset)
-#define cru_writel(v, offset) do { writel_relaxed(v, RK2928_CRU_BASE + offset); dsb(); } while (0)
-
-#define grf_readl(offset) readl_relaxed(RK2928_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel_relaxed(v, RK2928_GRF_BASE + offset); dsb(); } while (0)
-
-#define gate_save_soc_clk(val, _save, cons, w_msk) \
- do { \
- (_save) = cru_readl(cons); \
- cru_writel(((~(val) | (_save)) & (w_msk)) | ((w_msk) << 16), cons); \
- } while (0)
-
-#define RK_SOC_PM_CTR_FUN(ctr,fun) \
- if(!(rk_soc_pm_ctr_bits_check((1<<RK_PM_CTR_##ctr))))\
-(fun)()
-
-void __sramfunc sram_printch(char byte)
-{
-#ifdef DEBUG_UART_BASE
- u32 clk_gate2, clk_gate4, clk_gate8;
-
- gate_save_soc_clk(0
- | (1 << CLK_GATE_ACLK_PERIPH % 16)
- | (1 << CLK_GATE_HCLK_PERIPH % 16)
- | (1 << CLK_GATE_PCLK_PERIPH % 16)
- , clk_gate2, CRU_CLKGATES_CON(2), 0
- | (1 << ((CLK_GATE_ACLK_PERIPH % 16) + 16))
- | (1 << ((CLK_GATE_HCLK_PERIPH % 16) + 16))
- | (1 << ((CLK_GATE_PCLK_PERIPH % 16) + 16)));
- gate_save_soc_clk((1 << CLK_GATE_ACLK_CPU_PERI % 16)
- , clk_gate4, CRU_CLKGATES_CON(4),
- (1 << ((CLK_GATE_ACLK_CPU_PERI % 16) + 16)));
- gate_save_soc_clk((1 << ((CLK_GATE_PCLK_UART0 + CONFIG_RK_DEBUG_UART) % 16)),
- clk_gate8, CRU_CLKGATES_CON(8),
- (1 << (((CLK_GATE_PCLK_UART0 + CONFIG_RK_DEBUG_UART) % 16) + 16)));
- sram_udelay(1);
-
- writel_relaxed(byte, DEBUG_UART_BASE);
- dsb();
-
- /* loop check LSR[6], Transmitter Empty bit */
- while (!(readl_relaxed(DEBUG_UART_BASE + 0x14) & 0x40))
- barrier();
-
- cru_writel(0xffff0000 | clk_gate2, CRU_CLKGATES_CON(2));
- cru_writel(0xffff0000 | clk_gate4, CRU_CLKGATES_CON(4));
- cru_writel(0xffff0000 | clk_gate8, CRU_CLKGATES_CON(8));
-
- if (byte == '\n')
- sram_printch('\r');
-
-#endif
-}
-/*********************************pm control******************************************/
-enum rk_soc_pm_ctr_flags_offset {
-
- RK_PM_CTR_NO_PD = 0,
- RK_PM_CTR_NO_CLK_GATING,
- RK_PM_CTR_NO_PLL,
- RK_PM_CTR_NO_VOLT,
- RK_PM_CTR_NO_GPIO,
- RK_PM_CTR_NO_SRAM,
- RK_PM_CTR_NO_DDR,
- RK_PM_CTR_NO_SYS_CLK,
- RK_PM_CTR_NO_PMIC,
-
- RK_PM_CTR_RET_DIRT = 24,
- RK_PM_CTR_SRAM_NO_WFI,
- RK_PM_CTR_WAKE_UP_KEY,
- RK_PM_CTR_ALL = 31,
-};
-
-struct rk_soc_pm_info_st {
- int offset;
- char *name;
-};
-
-#define RK_SOC_PM_HELP_(id,NAME)\
-{\
- .offset= RK_PM_CTR_##id,\
- .name= NAME,\
-}
-
-struct rk_soc_pm_info_st rk_soc_pm_helps[] = {
- RK_SOC_PM_HELP_(NO_PD, "pd is not power dn"),
- RK_SOC_PM_HELP_(NO_CLK_GATING, "clk is not gating"),
- RK_SOC_PM_HELP_(NO_PLL, "pll is not power dn"),
- RK_SOC_PM_HELP_(NO_VOLT, "volt is not set suspend"),
- RK_SOC_PM_HELP_(NO_GPIO, "gpio is not control "),
- //RK_SOC_PM_HELP_(NO_SRAM,"not enter sram code"),
- RK_SOC_PM_HELP_(NO_DDR, "ddr is not reflash"),
- RK_SOC_PM_HELP_(NO_PMIC, "pmic is not suspend"),
- RK_SOC_PM_HELP_(RET_DIRT, "sys return from pm_enter directly"),
- RK_SOC_PM_HELP_(SRAM_NO_WFI, "sys is not runing wfi in sram"),
- RK_SOC_PM_HELP_(WAKE_UP_KEY, "send a power key to wake up lcd"),
-};
-
-ssize_t rk_soc_pm_helps_sprintf(char *buf)
-{
- char *s = buf;
- int i;
-
- for(i=0;i<ARRAY_SIZE(rk_soc_pm_helps);i++)
- {
- s += sprintf(s, "bit(%d): %s\n", rk_soc_pm_helps[i].offset,rk_soc_pm_helps[i].name);
- }
-
- return (s-buf);
-}
-
-void rk_soc_pm_helps_printk(void)
-{
- int i;
- printk("**************rk_suspend_ctr_bits bits help***********:\n");
- for(i=0;i<ARRAY_SIZE(rk_soc_pm_helps);i++)
- {
- printk("bit(%d): %s\n", rk_soc_pm_helps[i].offset,rk_soc_pm_helps[i].name);
- }
-}
-
-
-// pm enter return directly
-#define RK_SUSPEND_RET_DIRT_BITS ((1<<RK_PM_CTR_RET_DIRT))
-// not enter rk30_suspend
-#define RK_NO_SUSPEND_CTR_BITS ((1<<RK_PM_CTR_NO_PLL))
-//not running wfi in sram code
-#define RK_SUSPEND_NO_SRAM_WFI_BITS ((1<<RK_PM_CTR_SRAM_NO_WFI))
-
-
-static u32 __sramdata rk_soc_pm_ctr_flags_sram = 0;
-static u32 rk_soc_pm_ctr_flags = 0;
-
-static int arm_suspend_volt = 0;
-static int logic_suspend_volt = 0;
-
-
-static int __init early_param_rk_soc_pm_ctr(char *str)
-{
- get_option(&str, &rk_soc_pm_ctr_flags);
-
- printk("********rk_suspend_ctr_bits information is following:*********\n");
- printk("rk_suspend_ctr_bits=%x\n",rk_soc_pm_ctr_flags);
- if(rk_soc_pm_ctr_flags)
- {
- rk_soc_pm_helps_printk();
- }
- printk("********rk_suspend_ctr_bits information end*********\n");
- return 0;
-}
-
-early_param("rk_suspend_ctr_bits", early_param_rk_soc_pm_ctr);
-
-
-
-void rk_soc_pm_ctr_bits_set(u32 flags)
-{
- rk_soc_pm_ctr_flags = flags;
-
-}
-u32 rk_soc_pm_ctr_bits_get(void)
-{
- return rk_soc_pm_ctr_flags;
-}
-
-void rk_soc_pm_ctr_bit_set(int offset)
-{
- rk_soc_pm_ctr_flags |= (1 << offset);
-}
-void inline rk_soc_pm_ctr_bit_clear(int offset)
-{
- rk_soc_pm_ctr_flags &= ~(1 << offset);
-}
-
-u32 inline rk_soc_pm_ctr_bits_check(int bits)
-{
- return (rk_soc_pm_ctr_flags_sram & (bits));
-}
-
-#define RK_SOC_PM_CTR_FUN(ctr,fun) \
- if(!(rk_soc_pm_ctr_bits_check((1<<RK_PM_CTR_##ctr))))\
-(fun)()
-
-void rk_soc_pm_ctr_bits_prepare(void)
-{
- rk_soc_pm_ctr_flags_sram = rk_soc_pm_ctr_flags;
-
- if (rk_soc_pm_ctr_flags_sram & (1 << RK_PM_CTR_NO_PLL)) {
- rk_soc_pm_ctr_flags_sram |= (1 << RK_PM_CTR_NO_VOLT);
- }
-}
-
-
-
-
-static int __init set_arm_suspend_volt(char *str)
-{
- get_option(&str, &arm_suspend_volt);
- printk("rk_suspend_arm_volt=%dmV\n", arm_suspend_volt);
- return 0;
-}
-early_param("rk_suspend_arm_volt", set_arm_suspend_volt);
-
-static int __init set_logic_suspend_volt(char *str)
-{
- get_option(&str, &logic_suspend_volt);
- printk("rk_suspend_logic_volt=%dmV\n", logic_suspend_volt);
- return 0;
-}
-early_param("rk_suspend_logic_volt", set_logic_suspend_volt);
-
-
-
-static int __init pm_suspend_volt_seting(void)
-{
- struct regulator *regulator;
-
- printk("pmic set pm_suspend_volt:\n");
- if (arm_suspend_volt){
- regulator = regulator_get(NULL, "vdd_cpu");
- if (IS_ERR(regulator)){
- printk("%s:get vdd_cpu regulator err\n", __func__);
- return 0;
- }
- regulator_set_suspend_voltage(regulator, arm_suspend_volt);
- regulator_put(regulator);
- }
-
- if (logic_suspend_volt){
- regulator = regulator_get(NULL, "vdd_core");
- if (IS_ERR(regulator)){
- printk("%s:get vdd_core regulator err\n", __func__);
- return 0;
- }
- regulator_set_suspend_voltage(regulator, logic_suspend_volt);
- regulator_put(regulator);
- }
- return 0;
-}
-
-device_initcall_sync(pm_suspend_volt_seting);
-
-
-/*********************************pm main function******************************************/
-__weak void __sramfunc ddr_suspend(void) {}
-__weak void __sramfunc ddr_resume(void) {}
-__weak uint32_t __sramfunc ddr_change_freq(uint32_t nMHz)
-{
- return nMHz;
-}
-
-#ifdef CONFIG_DDR_TEST
-static int ddr_debug = 0;
-module_param(ddr_debug, int, 0644);
-
-static int inline calc_crc32(u32 addr, size_t len)
-{
- return crc32_le(~0, (const unsigned char *) addr, len);
-}
-
-static void ddr_testmode(void)
-{
- int32_t g_crc1, g_crc2;
- uint32_t nMHz;
- uint32_t n = 0;
- uint32_t min, max;
- extern char _stext[], _etext[];
-
-
- if (ddr_debug == 1) {
- max = 500;
- min = 100;
-
- for (;;) {
- sram_printascii("\n change freq:");
- g_crc1 = calc_crc32((u32) _stext, (size_t)(_etext - _stext));
-
- do {
- nMHz = min + random32();
- nMHz %= max;
- } while (nMHz < min);
-
- sram_printhex(nMHz);
- sram_printch(' ');
- nMHz = ddr_change_freq(nMHz);
- sram_printhex(n++);
- sram_printch(' ');
- g_crc2 = calc_crc32((u32) _stext, (size_t)(_etext - _stext));
-
- if (g_crc1 != g_crc2) {
- sram_printascii("fail\n");
- }
-
- //ddr_print("check image crc32 success--crc value = 0x%x!, count:%d\n",g_crc1, n++);
- // sram_printascii("change freq success\n");
- }
- } else if (ddr_debug == 2) {
- for (;;) {
- sram_printch(' ');
- sram_printch('9');
- sram_printch('9');
- sram_printch('9');
- sram_printch(' ');
- g_crc1 = calc_crc32((u32) _stext, (size_t)(_etext - _stext));
- nMHz = (random32() >> 13); // 16.7s max
- ddr_suspend();
- sram_udelay(nMHz);
- ddr_resume();
- sram_printhex(nMHz);
- sram_printch(' ');
- sram_printhex(n++);
- g_crc2 = calc_crc32((u32) _stext, (size_t)(_etext - _stext));
-
- if (g_crc1 != g_crc2) {
- sram_printch(' ');
- sram_printch('f');
- sram_printch('a');
- sram_printch('i');
- sram_printch('l');
- }
-
- // ddr_print("check image crc32 fail!, count:%d\n", n++);
- // sram_printascii("self refresh fail\n");
- //else
- //ddr_print("check image crc32 success--crc value = 0x%x!, count:%d\n",g_crc1, n++);
- // sram_printascii("self refresh success\n");
- }
- } else if (ddr_debug == 3) {
- extern int memtester(void);
- memtester();
- } else {
- ddr_change_freq(ddr_debug);
- ddr_debug = 0;
- }
-}
-#else
-static void ddr_testmode(void) {}
-#endif
-
-static noinline void rk2928_pm_dump_irq(void)
-{
- u32 irq_gpio = (readl_relaxed(RK2928_GICD_BASE + GIC_DIST_PENDING_SET + (IRQ_GPIO0 / 32) * 4) >> (IRQ_GPIO0 % 32)) & 0xF;
- printk("wakeup irq: %08x %08x %08x\n",
- readl_relaxed(RK2928_GICD_BASE + GIC_DIST_PENDING_SET + 4),
- readl_relaxed(RK2928_GICD_BASE + GIC_DIST_PENDING_SET + 8),
- readl_relaxed(RK2928_GICD_BASE + GIC_DIST_PENDING_SET + 12));
-
- if (irq_gpio & 1)
- printk("wakeup gpio0: %08x\n", readl_relaxed(RK2928_GPIO0_BASE + GPIO_INT_STATUS));
-
- if (irq_gpio & 2)
- printk("wakeup gpio1: %08x\n", readl_relaxed(RK2928_GPIO1_BASE + GPIO_INT_STATUS));
-
- if (irq_gpio & 4)
- printk("wakeup gpio2: %08x\n", readl_relaxed(RK2928_GPIO2_BASE + GPIO_INT_STATUS));
-
- if (irq_gpio & 8)
- printk("wakeup gpio3: %08x\n", readl_relaxed(RK2928_GPIO3_BASE + GPIO_INT_STATUS));
-}
-
-#define DUMP_GPIO_INTEN(ID) \
- do { \
- u32 en = readl_relaxed(RK2928_GPIO##ID##_BASE + GPIO_INTEN); \
- if (en) { \
- sram_printascii("GPIO" #ID "_INTEN: "); \
- sram_printhex(en); \
- sram_printch('\n'); \
- } \
- } while (0)
-
-static noinline void rk2928_pm_dump_inten(void)
-{
- DUMP_GPIO_INTEN(0);
- DUMP_GPIO_INTEN(1);
- DUMP_GPIO_INTEN(2);
- DUMP_GPIO_INTEN(3);
-}
-
-static void pm_pll_wait_lock(int pll_idx)
-{
- int delay = 24000000;
-
- while (delay > 0) {
- if ((cru_readl(PLL_CONS(pll_idx, 1)) & (0x1 << PLL_LOCK_SHIFT))) {
- break;
- }
-
- delay--;
- }
-
- if (delay == 0) {
- sram_printch('p');
- sram_printch('l');
- sram_printch('l');
- sram_printhex(pll_idx);
- sram_printch('\n');
-
- while (1);
- }
-}
-
-#define power_on_pll(id) \
- cru_writel(PLL_PWR_DN_W_MSK|PLL_PWR_ON,PLL_CONS((id),3));\
-pm_pll_wait_lock((id))
-
-static int pm_pll_pwr_up(u8 pll_id)
-{
- //enter slowmode
- cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
- cru_writel(CRU_W_MSK(PLL_PWR_DN_SHIFT, 0x01), PLL_CONS(pll_id, 1));
-
- sram_udelay(100);
-
- pm_pll_wait_lock(pll_id);
- //return form slow
- //cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
- return 0;
-}
-
-#define DDR_SAVE_SP(save_sp) do { save_sp = ddr_save_sp(((unsigned long)SRAM_DATA_END & (~7))); } while (0)
-#define DDR_RESTORE_SP(save_sp) do { ddr_save_sp(save_sp); } while (0)
-
-static unsigned long save_sp;
-
-static noinline void interface_ctr_reg_pread(void)
-{
- u32 addr;
-
- flush_cache_all();
- outer_flush_all();
- local_flush_tlb_all();
-
- for (addr = (u32) SRAM_CODE_OFFSET; addr < (u32) SRAM_DATA_END; addr += PAGE_SIZE)
- readl_relaxed(addr);
-
- readl_relaxed(RK2928_GRF_BASE);
- readl_relaxed(RK2928_DDR_PCTL_BASE);
- readl_relaxed(RK2928_DDR_PHY_BASE);
- readl_relaxed(RK2928_GPIO0_BASE);
- readl_relaxed(RK2928_GPIO1_BASE);
- readl_relaxed(RK2928_GPIO2_BASE);
- readl_relaxed(RK2928_GPIO3_BASE);
-#if defined (CONFIG_MACH_RK2928_SDK)
- readl_relaxed(RK2928_RKI2C1_BASE);
-#else
- readl_relaxed(RK2928_RKI2C0_BASE);
-#endif
-}
-
-__weak void board_gpio_suspend(void) {}
-__weak void board_gpio_resume(void) {}
-__weak void __sramfunc board_pmu_suspend(void) {}
-__weak void __sramfunc board_pmu_resume(void) {}
-__weak void __sramfunc rk30_suspend_voltage_set(unsigned int vol) {}
-__weak void __sramfunc rk30_suspend_voltage_resume(unsigned int vol) {}
-
-__weak void rk30_pwm_suspend_voltage_set(void) {}
-__weak void rk30_pwm_resume_voltage_set(void) {}
-
-__weak void __sramfunc rk30_pwm_logic_suspend_voltage(void) {}
-__weak void __sramfunc rk30_pwm_logic_resume_voltage(void) {}
-
-#define CLK_GATEALL_W_MSK (0xffff)
-#define PM_HOLDGATE(ID) (1 << (CLK_GATE_##ID % 16))
-#define PM_GATING(msk, con) do {cru_writel((msk << 16) | 0xffff, con); } while(0)
-static u16 clkgt_first_w_msk[CRU_CLKGATES_CON_CNT] = {
- ~(0 | PM_HOLDGATE(CORE_PERIPH)
- | PM_HOLDGATE(CPU_GPLL)
- | PM_HOLDGATE(DDRPHY_SRC)
- | PM_HOLDGATE(ACLK_CPU)
- | PM_HOLDGATE(HCLK_CPU)
- | PM_HOLDGATE(PCLK_CPU)
- | PM_HOLDGATE(ACLK_CORE)),
- ~(0),
- ~(0 | PM_HOLDGATE(PERIPH_SRC)
- | PM_HOLDGATE(PCLK_PERIPH)
- | PM_HOLDGATE(ACLK_PERIPH)),
- ~(0),
- ~(0 | PM_HOLDGATE(HCLK_PERI_AXI_MATRIX)
- | PM_HOLDGATE(PCLK_PERI_AXI_MATRIX)
- | PM_HOLDGATE(ACLK_PERI_AXI_MATRIX)
- | PM_HOLDGATE(ACLK_CPU_PERI)
- | PM_HOLDGATE(ACLK_STRC_SYS)
- | PM_HOLDGATE(ACLK_INTMEM)),
- ~(0 | PM_HOLDGATE(PCLK_GRF)
- | PM_HOLDGATE(PCLK_DDRUPCTL)),
- ~(0),
- ~(0 | PM_HOLDGATE(PCLK_PWM01)),
- ~(0 | PM_HOLDGATE(PCLK_GPIO0)
- | PM_HOLDGATE(PCLK_GPIO1)
- | PM_HOLDGATE(PCLK_GPIO2)
- | PM_HOLDGATE(PCLK_GPIO3)),
- ~(0 | PM_HOLDGATE(CLK_L2C)
- | PM_HOLDGATE(HCLK_PERI_ARBI)
- | PM_HOLDGATE(ACLK_PERI_NIU)),
-};
-static u16 __sramdata clkgt_sram_w_msk[CRU_CLKGATES_CON_CNT] = {
- ~(0 | PM_HOLDGATE(CORE_PERIPH)
- | PM_HOLDGATE(DDRPHY_SRC)
- | PM_HOLDGATE(ACLK_CPU)
- | PM_HOLDGATE(HCLK_CPU)
- | PM_HOLDGATE(PCLK_CPU)
- | PM_HOLDGATE(ACLK_CORE)),
- ~(0),
- ~(0 | PM_HOLDGATE(PERIPH_SRC)
- | PM_HOLDGATE(PCLK_PERIPH)),
- ~(0),
- ~(0 | PM_HOLDGATE(ACLK_STRC_SYS)
- | PM_HOLDGATE(ACLK_INTMEM)),
- ~(0 | PM_HOLDGATE(PCLK_GRF)
- | PM_HOLDGATE(PCLK_DDRUPCTL)),
- ~(0),
- ~(0),
- ~(0 | PM_HOLDGATE(PCLK_GPIO0)
- | PM_HOLDGATE(PCLK_GPIO1)
- | PM_HOLDGATE(PCLK_GPIO2)
- | PM_HOLDGATE(PCLK_GPIO3)),
- ~(0 | PM_HOLDGATE(CLK_L2C)),
-};
-static u32 __sramdata clkgt_regs_sram[CRU_CLKGATES_CON_CNT];
-static u32 __sramdata grf_uoc1_con;
-static void __sramfunc rk_pm_soc_sram_volt_suspend(void)
-{
- rk30_suspend_voltage_set(1000000);
- rk30_pwm_logic_suspend_voltage();
- board_pmu_suspend();
-}
-
-static void __sramfunc rk_pm_soc_sram_clk_gating(void)
-{
- int i;
-#ifdef CONFIG_ARCH_RK2928
- grf_uoc1_con = grf_readl(GRF_UOC1_CON4);
- grf_writel(0x30000000, GRF_UOC1_CON4);
-#endif
-
- for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
- clkgt_regs_sram[i] = cru_readl(CRU_CLKGATES_CON(i));
- PM_GATING(clkgt_sram_w_msk[i], CRU_CLKGATES_CON(i));
- }
-
- if (((clkgt_regs_sram[8] >> (CLK_GATE_PCLK_GPIO0 % 16)) & 0xf) == 0xf) {
- PM_GATING(CLK_GATEALL_W_MSK, CRU_CLKGATES_CON(2));
- }
-}
-
-static u32 __sramdata sram_cru_clksel0_con;
-static void __sramfunc rk_pm_soc_sram_sys_clk_suspend(void)
-{
- sram_cru_clksel0_con = cru_readl(CRU_CLKSELS_CON(0));
- cru_writel(CLK_CORE_DIV(32), CRU_CLKSELS_CON(0));
-
-}
-static void __sramfunc rk_pm_soc_sram_sys_clk_resume(void)
-{
-
- cru_writel((0x1f << 16) | sram_cru_clksel0_con, CRU_CLKSELS_CON(0));
- //cru_writel((A9_CORE_DIV_MASK << (A9_CORE_DIV_SHIFT + 16)) | sram_cru_clksel0_con, CRU_CLKSELS_CON(0));
-
-}
-static void __sramfunc rk_pm_soc_sram_clk_ungating(void)
-{
- int i;
-
- for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
- cru_writel(clkgt_regs_sram[i] | 0xffff0000, CRU_CLKGATES_CON(i));
- }
-
-#ifdef CONFIG_ARCH_RK2928
- grf_writel(0x30000000 | grf_uoc1_con, GRF_UOC1_CON4);
-#endif
-}
-
-static void __sramfunc rk_pm_soc_sram_volt_resume(void)
-{
- board_pmu_resume();
- rk30_pwm_logic_resume_voltage();
- rk30_suspend_voltage_resume(1100000);
-}
-static void __sramfunc rk2928_sram_suspend(void)
-{
- int grf_uoc1_con0;
- sram_printch('5');
- RK_SOC_PM_CTR_FUN(NO_DDR, ddr_suspend);
- sram_printch('6');
- RK_SOC_PM_CTR_FUN(NO_VOLT, rk_pm_soc_sram_volt_suspend);
- sram_printch('7');
-#ifdef CONFIG_ARCH_RK3026
- grf_uoc1_con0 = grf_readl(GRF_UOC1_CON0);
- grf_writel(0x30000000, GRF_UOC1_CON0);
-#endif
-
- RK_SOC_PM_CTR_FUN(NO_CLK_GATING, rk_pm_soc_sram_clk_gating);
- RK_SOC_PM_CTR_FUN(NO_SYS_CLK, rk_pm_soc_sram_sys_clk_suspend);
-
- //RK_SOC_PM_CTR_FUN(NO_PMIC,board_pmu_suspend);
- if (!rk_soc_pm_ctr_bits_check(RK_SUSPEND_NO_SRAM_WFI_BITS)) {
- dsb();
- wfi();
- }
-
- //RK_SOC_PM_CTR_FUN(NO_PMIC,board_pmu_resume);
- RK_SOC_PM_CTR_FUN(NO_SYS_CLK, rk_pm_soc_sram_sys_clk_resume);
- RK_SOC_PM_CTR_FUN(NO_CLK_GATING, rk_pm_soc_sram_clk_ungating);
-#ifdef CONFIG_ARCH_RK3026
- grf_writel(0x30000000 | grf_uoc1_con0, GRF_UOC1_CON0);
-#endif
- sram_printch('7');
- RK_SOC_PM_CTR_FUN(NO_VOLT, rk_pm_soc_sram_volt_resume);
- sram_printch('6');
- RK_SOC_PM_CTR_FUN(NO_DDR, ddr_resume);
- sram_printch('5');
-}
-static void noinline rk2928_suspend(void)
-{
- DDR_SAVE_SP(save_sp);
- rk2928_sram_suspend();
- DDR_RESTORE_SP(save_sp);
-}
-static u32 clk_sel0, clk_sel1, clk_sel10;
-static u32 cru_mode_con;
-static u32 apll_con1, cpll_con1, gpll_con1;
-static u32 clkgt_regs_first[CRU_CLKGATES_CON_CNT];
-static void rk_pm_soc_clk_gating_first(void)
-{
- int i;
-
- for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
- clkgt_regs_first[i] = cru_readl(CRU_CLKGATES_CON(i));
- PM_GATING(clkgt_first_w_msk[i], CRU_CLKGATES_CON(i));
- }
-
- cru_writel(((1 << CLK_GATE_PCLK_GPIO0 % 16) << 16), CRU_CLKGATES_CON(8));
-}
-
-static void rk_pm_soc_pll_suspend(void)
-{
- cru_mode_con = cru_readl(CRU_MODE_CON);
-
- //apll
- clk_sel0 = cru_readl(CRU_CLKSELS_CON(0));
- clk_sel1 = cru_readl(CRU_CLKSELS_CON(1));
- apll_con1 = cru_readl(PLL_CONS(APLL_ID, 1));
-
- cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
- cru_writel(CLK_CORE_DIV(1) | ACLK_CPU_DIV(1) | CPU_SEL_PLL(SEL_APLL), CRU_CLKSELS_CON(0));
- cru_writel(CLK_CORE_PERI_DIV(1) | ACLK_CORE_DIV(1) | HCLK_CPU_DIV(1) | PCLK_CPU_DIV(1), CRU_CLKSELS_CON(1));
- //cru_writel((0x01 <<(PLL_PWR_DN_SHIFT + 16))|(1<<PLL_PWR_DN_SHIFT), PLL_CONS(APLL_ID, 1));
- cru_writel(CRU_W_MSK_SETBIT(0x01, PLL_PWR_DN_SHIFT) , PLL_CONS(APLL_ID, 1)); //power down apll
-
- //cpll
- cpll_con1 = cru_readl(PLL_CONS(CPLL_ID, 1));
-
- cru_writel(PLL_MODE_SLOW(CPLL_ID), CRU_MODE_CON);
- cru_writel(CRU_W_MSK_SETBIT(0x01, PLL_PWR_DN_SHIFT), PLL_CONS(CPLL_ID, 1)); //power down cpll
-
- //gpll
- clk_sel10 = cru_readl(CRU_CLKSELS_CON(10));
- gpll_con1 = cru_readl(PLL_CONS(GPLL_ID, 1));
-
- cru_writel(PLL_MODE_SLOW(GPLL_ID), CRU_MODE_CON);
- cru_writel(PERI_SET_ACLK_DIV(1)
- | CRU_W_MSK_SETBITS(0, PERI_PCLK_DIV_SHIFT, PERI_PCLK_DIV_MASK)
- | CRU_W_MSK_SETBITS(0, PERI_HCLK_DIV_SHIFT, PERI_HCLK_DIV_MASK)
- , CRU_CLKSELS_CON(10));
- cru_writel(CRU_W_MSK_SETBIT(0x01, PLL_PWR_DN_SHIFT), PLL_CONS(GPLL_ID, 1)); //power down gpll
-
-}
-
-static void rk_pm_soc_pll_resume(void)
-{
-
- //gpll
- pm_pll_pwr_up(GPLL_ID);
- cru_writel(0xffff0000 | clk_sel10, CRU_CLKSELS_CON(10));
- cru_writel(clk_sel10, CRU_CLKSELS_CON(10));
- cru_writel((PLL_MODE_MSK(GPLL_ID) << 16) | (PLL_MODE_MSK(GPLL_ID) & cru_mode_con), CRU_MODE_CON);
-
- //cpll
- if (!(cpll_con1 & (0x1 << PLL_PWR_DN_SHIFT)))
- pm_pll_pwr_up(CPLL_ID);
-
- cru_writel((PLL_MODE_MSK(CPLL_ID) << 16) | (PLL_MODE_MSK(CPLL_ID) & cru_mode_con), CRU_MODE_CON);
-
- //apll
- pm_pll_pwr_up(APLL_ID);
- cru_writel(0xffff0000 | clk_sel1, CRU_CLKSELS_CON(1));
- cru_writel(0xffff0000 | clk_sel0, CRU_CLKSELS_CON(0));
- cru_writel((PLL_MODE_MSK(APLL_ID) << 16) | (PLL_MODE_MSK(APLL_ID) & cru_mode_con), CRU_MODE_CON);
-
-
-}
-static void rk_pm_soc_clk_ungating_first(void)
-{
- int i;
-
- for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
- cru_writel(clkgt_regs_first[i] | 0xffff0000, CRU_CLKGATES_CON(i));
- }
-}
-static int rk2928_pm_enter(suspend_state_t state)
-{
- // dump GPIO INTEN for debug
- rk2928_pm_dump_inten();
-
- sram_printch('0');
-
-#ifdef CONFIG_DDR_TEST
-
- // memory tester
- if (ddr_debug != 0)
- ddr_testmode();
-
-#endif
-
- sram_printch('1');
- local_fiq_disable();
- RK_SOC_PM_CTR_FUN(NO_CLK_GATING, rk_pm_soc_clk_gating_first);
-
- sram_printch('2');
- RK_SOC_PM_CTR_FUN(NO_PLL, rk_pm_soc_pll_suspend);
-
- sram_printch('3');
- //RK_SOC_PM_CTR_FUN(NO_VOLT,rk30_pwm_suspend_voltage_set);
- RK_SOC_PM_CTR_FUN(NO_GPIO, board_gpio_suspend);
-
- interface_ctr_reg_pread();
-
- sram_printch('4');
-
- if (!rk_soc_pm_ctr_bits_check(RK_NO_SUSPEND_CTR_BITS))
- rk2928_suspend();
-
- sram_printch('4');
- RK_SOC_PM_CTR_FUN(NO_GPIO, board_gpio_resume);
- //RK_SOC_PM_CTR_FUN(NO_VOLT,rk30_pwm_resume_voltage_set);
-
- sram_printch('3');
- RK_SOC_PM_CTR_FUN(NO_PLL, rk_pm_soc_pll_resume);
-
- sram_printch('2');
- RK_SOC_PM_CTR_FUN(NO_CLK_GATING, rk_pm_soc_clk_ungating_first);
-
- local_fiq_enable();
- sram_printch('1');
-
- sram_printascii("0\n");
-
- rk2928_pm_dump_irq();
-
- return 0;
-}
-
-static int rk2928_pm_prepare(void)
-{
- /* disable entering idle by disable_hlt() */
- disable_hlt();
- return 0;
-}
-
-static void rk2928_pm_finish(void)
-{
- enable_hlt();
-}
-
-static struct platform_suspend_ops rk2928_pm_ops = {
- .enter = rk2928_pm_enter,
- .valid = suspend_valid_only_mem,
- .prepare = rk2928_pm_prepare,
- .finish = rk2928_pm_finish,
-};
-
-static int __init rk2928_pm_init(void)
-{
- suspend_set_ops(&rk2928_pm_ops);
-
-#ifdef CONFIG_EARLYSUSPEND
- pm_set_vt_switch(0); /* disable vt switch while suspend */
-#endif
-
- return 0;
-}
-__initcall(rk2928_pm_init);
+++ /dev/null
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <mach/system.h>
-#include <linux/string.h>
-#include <mach/cru.h>
-#include <mach/iomux.h>
-#include <mach/loader.h>
-#include <mach/board.h>
-
-static void rk2928_arch_reset(char mode, const char *cmd)
-{
- u32 boot_flag = 0;
- u32 boot_mode = BOOT_MODE_REBOOT;
-
- if (cmd) {
- if (!strcmp(cmd, "loader") || !strcmp(cmd, "bootloader"))
- boot_flag = SYS_LOADER_REBOOT_FLAG + BOOT_LOADER;
- else if(!strcmp(cmd, "recovery"))
- boot_flag = SYS_LOADER_REBOOT_FLAG + BOOT_RECOVER;
- else if (!strcmp(cmd, "charge"))
- boot_mode = BOOT_MODE_CHARGE;
- } else {
- if (system_state != SYSTEM_RESTART)
- boot_mode = BOOT_MODE_PANIC;
- }
- writel_relaxed(0xffff0000 | (boot_flag&0xFFFFuL), RK2928_GRF_BASE + GRF_OS_REG4); // for loader
- writel_relaxed(0xffff0000 | ((boot_flag>>16)&0xFFFFuL), RK2928_GRF_BASE + GRF_OS_REG5); // for loader
- writel_relaxed(0xffff0000 | boot_mode, RK2928_GRF_BASE + GRF_OS_REG6); // for linux
- dsb();
- /* disable remap */
- writel_relaxed(1 << (12 + 16), RK2928_GRF_BASE + GRF_SOC_CON0);
- /* pll enter slow mode */
- writel_relaxed(PLL_MODE_SLOW(APLL_ID) | PLL_MODE_SLOW(CPLL_ID) | PLL_MODE_SLOW(GPLL_ID), RK2928_CRU_BASE + CRU_MODE_CON);
- dsb();
- writel_relaxed(0xeca8, RK2928_CRU_BASE + CRU_GLB_SRST_SND);
- dsb();
-}
-
-void (*arch_reset)(char, const char *) = rk2928_arch_reset;
+++ /dev/null
-/* linux/arch/arm/mach-rk2928/timer.c
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/init.h>
-#include <linux/time.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/clk.h>
-#include <linux/clockchips.h>
-#include <linux/io.h>
-
-#include <asm/sched_clock.h>
-#include <asm/mach/time.h>
-
-#define TIMER_LOAD_COUNT 0x0000
-#define TIMER_CUR_VALUE 0x0004
-#define TIMER_CONTROL_REG 0x0008
-#define TIMER_EOI 0x000C
-#define TIMER_INT_STATUS 0x0010
-
-#define TIMER_DISABLE 6
-#define TIMER_ENABLE 3
-#define TIMER_ENABLE_FREE_RUNNING 5
-
-static inline void timer_write(u32 n, u32 v, u32 offset)
-{
- __raw_writel(v, RK2928_TIMER0_BASE + 0x2000 * n + offset);
- dsb();
-}
-
-static inline u32 timer_read(u32 n, u32 offset)
-{
- return __raw_readl(RK2928_TIMER0_BASE + 0x2000 * n + offset);
-}
-
-#define RK_TIMER_ENABLE(n) timer_write(n, TIMER_ENABLE, TIMER_CONTROL_REG)
-#define RK_TIMER_ENABLE_FREE_RUNNING(n) timer_write(n, TIMER_ENABLE_FREE_RUNNING, TIMER_CONTROL_REG)
-#define RK_TIMER_DISABLE(n) timer_write(n, TIMER_DISABLE, TIMER_CONTROL_REG)
-
-#define RK_TIMER_SETCOUNT(n, count) timer_write(n, count, TIMER_LOAD_COUNT)
-#define RK_TIMER_GETCOUNT(n) timer_read(n, TIMER_LOAD_COUNT)
-
-#define RK_TIMER_READVALUE(n) timer_read(n, TIMER_CUR_VALUE)
-#define RK_TIMER_INT_CLEAR(n) timer_read(n, TIMER_EOI)
-
-#define RK_TIMER_INT_STATUS(n) timer_read(n, TIMER_INT_STATUS)
-
-#define TIMER_CLKEVT 0 /* timer0 */
-#define IRQ_NR_TIMER_CLKEVT IRQ_TIMER0
-#define TIMER_CLKEVT_NAME "timer0"
-
-#define TIMER_CLKSRC 1 /* timer1 */
-#define IRQ_NR_TIMER_CLKSRC IRQ_TIMER1
-#define TIMER_CLKSRC_NAME "timer1"
-
-static int rk2928_timer_set_next_event(unsigned long cycles, struct clock_event_device *evt)
-{
- do {
- RK_TIMER_DISABLE(TIMER_CLKEVT);
- RK_TIMER_SETCOUNT(TIMER_CLKEVT, cycles);
- RK_TIMER_ENABLE(TIMER_CLKEVT);
- } while (RK_TIMER_READVALUE(TIMER_CLKEVT) > cycles);
- return 0;
-}
-
-static void rk2928_timer_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
-{
- switch (mode) {
- case CLOCK_EVT_MODE_PERIODIC:
- rk2928_timer_set_next_event(24000000 / HZ - 1, evt);
- break;
- case CLOCK_EVT_MODE_RESUME:
- case CLOCK_EVT_MODE_ONESHOT:
- break;
- case CLOCK_EVT_MODE_UNUSED:
- case CLOCK_EVT_MODE_SHUTDOWN:
- RK_TIMER_DISABLE(TIMER_CLKEVT);
- break;
- }
-}
-
-static struct clock_event_device rk2928_timer_clockevent = {
- .name = TIMER_CLKEVT_NAME,
- .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
- .rating = 200,
- .set_next_event = rk2928_timer_set_next_event,
- .set_mode = rk2928_timer_set_mode,
-};
-
-static irqreturn_t rk2928_timer_clockevent_interrupt(int irq, void *dev_id)
-{
- struct clock_event_device *evt = dev_id;
-
- RK_TIMER_INT_CLEAR(TIMER_CLKEVT);
- if (evt->mode == CLOCK_EVT_MODE_ONESHOT)
- RK_TIMER_DISABLE(TIMER_CLKEVT);
-
- evt->event_handler(evt);
-
- return IRQ_HANDLED;
-}
-
-static struct irqaction rk2928_timer_clockevent_irq = {
- .name = TIMER_CLKEVT_NAME,
- .flags = IRQF_DISABLED | IRQF_TIMER,
- .handler = rk2928_timer_clockevent_interrupt,
- .irq = IRQ_NR_TIMER_CLKEVT,
- .dev_id = &rk2928_timer_clockevent,
-};
-
-static __init int rk2928_timer_init_clockevent(void)
-{
- struct clock_event_device *ce = &rk2928_timer_clockevent;
- struct clk *clk = clk_get(NULL, TIMER_CLKEVT_NAME);
- struct clk *pclk = clk_get(NULL, "pclk_" TIMER_CLKEVT_NAME);
- struct clk *peri_pclk = clk_get(NULL, "peri_pclk");
-
- clk_set_parent(clk, peri_pclk);
- clk_enable(pclk);
- clk_enable(clk);
-
- RK_TIMER_DISABLE(TIMER_CLKEVT);
-
- setup_irq(rk2928_timer_clockevent_irq.irq, &rk2928_timer_clockevent_irq);
-
- ce->irq = rk2928_timer_clockevent_irq.irq;
- ce->cpumask = cpu_all_mask;
- clockevents_config_and_register(ce, clk_get_rate(clk), 0xF, 0xFFFFFFFF);
-
- return 0;
-}
-
-static cycle_t rk2928_timer_read(struct clocksource *cs)
-{
- return ~RK_TIMER_READVALUE(TIMER_CLKSRC);
-}
-
-#define MASK (u32)~0
-
-static struct clocksource rk2928_timer_clocksource = {
- .name = TIMER_CLKSRC_NAME,
- .rating = 200,
- .read = rk2928_timer_read,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-static void __init rk2928_timer_init_clocksource(void)
-{
- static char err[] __initdata = KERN_ERR "%s: can't register clocksource!\n";
- struct clocksource *cs = &rk2928_timer_clocksource;
- struct clk *clk = clk_get(NULL, TIMER_CLKSRC_NAME);
- struct clk *pclk = clk_get(NULL, "pclk_" TIMER_CLKSRC_NAME);
- struct clk *peri_pclk = clk_get(NULL, "peri_pclk");
-
- clk_set_parent(clk, peri_pclk);
- clk_enable(pclk);
- clk_enable(clk);
-
- RK_TIMER_DISABLE(TIMER_CLKSRC);
- clk_disable(clk);
- RK_TIMER_SETCOUNT(TIMER_CLKSRC, 0xFFFFFFFF);
- RK_TIMER_ENABLE_FREE_RUNNING(TIMER_CLKSRC);
- clk_enable(clk);
-
- if (clocksource_register_hz(cs, clk_get_rate(clk)))
- printk(err, cs->name);
-}
-
-#ifdef CONFIG_HAVE_SCHED_CLOCK
-static DEFINE_CLOCK_DATA(cd);
-
-unsigned long long notrace sched_clock(void)
-{
- u32 cyc = ~RK_TIMER_READVALUE(TIMER_CLKSRC);
- return cyc_to_sched_clock(&cd, cyc, MASK);
-}
-
-static void notrace rk2928_update_sched_clock(void)
-{
- u32 cyc = ~RK_TIMER_READVALUE(TIMER_CLKSRC);
- update_sched_clock(&cd, cyc, MASK);
-}
-
-static void __init rk2928_sched_clock_init(void)
-{
- init_sched_clock(&cd, rk2928_update_sched_clock, 32, clk_get_rate(clk_get(NULL, TIMER_CLKSRC_NAME)));
-}
-#endif
-
-static void __init rk2928_timer_init(void)
-{
- rk2928_timer_init_clocksource();
- rk2928_timer_init_clockevent();
-#ifdef CONFIG_HAVE_SCHED_CLOCK
- rk2928_sched_clock_init();
-#endif
-}
-
-struct sys_timer rk2928_timer = {
- .init = rk2928_timer_init
-};
-
+++ /dev/null
-config ARCH_RK30XX
- depends on ARCH_RK30
- bool
-
-config ARCH_RK3066B
- depends on ARCH_RK30
- bool
-
-choice
- prompt "Rockchip SoC Type"
- depends on ARCH_RK30
- default SOC_RK3066
-
-config SOC_RK3000
- bool "RK3000"
- select ARCH_RK30XX
-
-config SOC_RK3028
- bool "RK3028"
- select ARCH_RK3066B
-
-config SOC_RK3066
- bool "RK3066"
- select ARCH_RK30XX
-
-config SOC_RK3068
- bool "RK3068"
- select ARCH_RK30XX
-
-config SOC_RK3066B
- bool "RK3066B"
- select ARCH_RK3066B
-
-config SOC_RK3108
- bool "RK3108"
- select ARCH_RK3066B
- select USB_ARCH_HAS_EHCI if USB_SUPPORT
-
-config SOC_RK3168
- bool "RK3168"
- select ARCH_RK3066B
- select USB_ARCH_HAS_EHCI if USB_SUPPORT
-
-config SOC_RK3168M
- bool "RK3168M"
- select ARCH_RK3066B
- select USB_ARCH_HAS_EHCI if USB_SUPPORT
-
-endchoice
-
-choice
- prompt "RK30xx Board Type"
- depends on ARCH_RK30XX
- default MACH_RK30_SDK
-
-config MACH_RK30_SDK
- bool "RK30 SDK board"
-
-config MACH_RK30_DS975
- bool "RK30 DS975 board"
-
-config MACH_RK3066_SDK
- bool "RK3066 SDK board"
-
-config MACH_RK30_DS1001B
- bool "RK30 DS1001B board"
-
-config MACH_RK30_PHONE
- bool "RK30 smart phone board"
-
-config MACH_RK30_PHONE_LOQUAT
- bool "RK30 smart phone loquat board"
-
-config MACH_RK30_PHONE_A22
- bool "RK30 smart phone a22 board"
-
-config MACH_RK30_PHONE_PAD
- bool "RK30 phone pad board"
-
-config MACH_RK30_Z600T
- bool "RK30 Z600T smart phone pad board"
-
-endchoice
-
-choice
- prompt "RK30 phone pad board type"
- depends on MACH_RK30_PHONE_PAD
- default MACH_RK30_PHONE_PAD_DS763
-
- config MACH_RK30_PHONE_PAD_DS763
- bool "ds763"
-
- config MACH_RK30_PHONE_PAD_C8003
- bool "c8003"
-
-endchoice
-
-choice
- prompt "RK3028 Board Type"
- depends on SOC_RK3028
-
-config MACH_RK3028_TB
- bool "RK3028 Top Board"
-
-config MACH_RK3028_FT
- bool "RK3028 FT Board"
-
-config MACH_RK3028_86V
- bool "RK3028 86V Board"
-endchoice
-
-choice
- prompt "RK3066B Board Type"
- depends on SOC_RK3066B
-
-config MACH_RK3066B_FPGA
- bool "RK3066B FPGA board"
- select RK_FPGA
-
-config MACH_RK3066B_SDK
- bool "RK3066B SDK board"
-
-config MACH_RK3066B_M701
- bool "RK3066B M701 board"
-
-endchoice
-
-choice
- prompt "RK3108 Board Type"
- depends on SOC_RK3108
-
-config MACH_RK3108_TB
- bool "RK3108 Top Board"
-
-endchoice
-
-choice
- prompt "RK3168 Board Type"
- depends on SOC_RK3168
-
-config MACH_RK3168_TB
- bool "RK3168 Top Board"
-
-config MACH_RK3168_FT
- bool "RK3168 FT Board"
-
-config MACH_RK3168_LR097
- bool "RK3168 LR097 JC21CA board"
-
-config MACH_RK3168_DS1006H
- bool "RK3168 DS1006h Board"
-
-config MACH_RK3168_86V
- bool "RK3168 86V Board"
-
-config MACH_RK3168_86V_OLD
- bool "RK3168 86V Old Board"
-
-config MACH_RK3168_FAC
- bool "RK3168 Board for factory"
- select MACH_RK_FAC
-
-endchoice
-
-choice
- prompt "RK3168M Board Type"
- depends on SOC_RK3168M
-
-config MACH_RK3168M_TB
- bool "RK3168M Top Board"
-
-config MACH_RK3168M_F304
- bool "RK3168M F304 Board"
-
-endchoice
+++ /dev/null
-EXTRA_CFLAGS += -Os
-ifneq ($(CONFIG_RK_FPGA),y)
-obj-y += ../plat-rk/clock.o
-obj-$(CONFIG_ARCH_RK30XX) += clock_data.o
-obj-$(CONFIG_ARCH_RK3066B) += clock_data-rk3066b.o
-endif
-obj-y += common.o
-CFLAGS_common.o += -DTEXT_OFFSET=$(TEXT_OFFSET)
-obj-y += ddr.o
-obj-y += devices.o
-obj-y += io.o
-ifeq ($(CONFIG_ARCH_RK30XX),y)
-obj-y += iomux.o
-obj-$(CONFIG_CPU_FREQ) += cpufreq.o
-else
-obj-$(CONFIG_CPU_FREQ) += ../mach-rk3188/cpufreq.o
-endif
-obj-y += pmu.o
-obj-y += reset.o
-obj-y += timer.o
-obj-y += tsadc.o
-obj-$(CONFIG_SMP) += platsmp.o headsmp.o
-obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
-obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
-obj-$(CONFIG_PM) += pm.o
-obj-$(CONFIG_CPU_IDLE) += cpuidle.o
-ifeq ($(CONFIG_DVFS_WITH_UOC),y)
-obj-$(CONFIG_DVFS) += dvfs-rk3066b.o
-else
-obj-$(CONFIG_DVFS) += dvfs.o
-endif
-obj-$(CONFIG_RK30_I2C_INSRAM) += i2c_sram.o
-
-obj-$(CONFIG_ARCH_RK30XX) += board.o
-board-$(CONFIG_MACH_RK3066_SDK) += board-rk30-sdk.o
-board-$(CONFIG_MACH_RK30_SDK) += board-rk30-sdk.o
-board-$(CONFIG_MACH_RK30_DS975) += board-rk30-ds975.o
-board-$(CONFIG_MACH_RK30_Z600T) += board-rk30-phonepad-z600t.o
-board-$(CONFIG_MACH_RK30_PHONE) += board-rk30-phone.o board-rk30-phone-key.o
-board-$(CONFIG_MACH_RK30_PHONE_PAD) += board-rk30-phonepad.o board-rk30-phonepad-key.o
-board-$(CONFIG_MACH_RK30_PHONE_LOQUAT) += board-rk30-phone-loquat.o board-rk30-phone-loquat-key.o
-board-$(CONFIG_MACH_RK30_DS1001B) += board-rk30-ds1001b.o board-rk30-ds1001b-key.o board-rk30-ds1001b-rfkill.o
-board-$(CONFIG_MACH_RK30_PHONE_A22) += board-rk30-phone-a22.o board-rk30-phone-a22-key.o
-
-obj-$(CONFIG_SOC_RK3028) += board.o
-board-$(CONFIG_MACH_RK3028_TB) += board-rk3028-tb.o
-board-$(CONFIG_MACH_RK3028_FT) += ../mach-rk3188/board-rk3188-ft.o
-board-$(CONFIG_MACH_RK3028_86V)+= board-rk3028-86v.o
-
-obj-$(CONFIG_SOC_RK3066B) += board.o
-board-$(CONFIG_MACH_RK3066B_FPGA) += board-rk3066b-fpga.o
-board-$(CONFIG_MACH_RK3066B_SDK) += board-rk3066b-sdk.o
-board-$(CONFIG_MACH_RK3066B_M701) += board-rk3066b-m701.o
-
-obj-$(CONFIG_SOC_RK3108) += board.o
-board-$(CONFIG_MACH_RK3108_TB) += board-rk3108-tb.o
-
-obj-$(CONFIG_SOC_RK3168) += board.o
-board-$(CONFIG_MACH_RK3168_TB) += board-rk3168-tb.o
-board-$(CONFIG_MACH_RK3168_FT) += ../mach-rk3188/board-rk3188-ft.o
-board-$(CONFIG_MACH_RK3168_LR097) += board-rk3168-LR097.o
-board-$(CONFIG_MACH_RK3168_DS1006H) += board-rk3168-ds1006h.o
-board-$(CONFIG_MACH_RK3168_86V) += board-rk3168-86v.o
-board-$(CONFIG_MACH_RK3168_86V_OLD) += board-rk3168-86v-old.o
-board-$(CONFIG_MACH_RK3168_FAC) += board-rk3168-fac.o
-
-obj-$(CONFIG_SOC_RK3168M) += board.o
-board-$(CONFIG_MACH_RK3168M_TB) += board-rk3168m-tb.o
-board-$(CONFIG_MACH_RK3168M_F304) += board-rk3168m-f304.o
+++ /dev/null
- zreladdr-y := 0x60408000
-params_phys-y := 0x60088000
-initrd_phys-y := 0x60800000
+++ /dev/null
-/*****************************************************************************************
- * arch/arm/mach-rkxx/baord-xxx-sdmmc-config.c
- *
- * Copyright (C) 2013 ROCKCHIP, Inc.
- *
- * Description:
- * define the gpio for SD-MMC-SDIO-Wifi functions according to your own projects.
- *
- * Author: Michael Xie
- * 15 Jan,2013
- * E-mail: xbw@rock-chips.com
- *
- ******************************************************************************************/
-
-/*
-** If you select the macro of CONFIG_SDMMC0_RK29_WRITE_PROTECT, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define SDMMC0_WRITE_PROTECT_PIN RK30_PIN3_PB2 //According to your own project to set the value of write-protect-pin.
-//#define SDMMC0_WRITE_PROTECT_ENABLE_VALUE GPIO_HIGH
-
-/*
-** If you select the macro of CONFIG_SDMMC1_RK29_WRITE_PROTECT, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define SDMMC1_WRITE_PROTECT_PIN RK30_PIN3_PB3 //According to your own project to set the value of write-protect-pin.
-//#define SDMMC1_WRITE_PROTECT_ENABLE_VALUE GPIO_HIGH
-
-/*
-** If you select the macro of CONFIG_RK29_SDIO_IRQ_FROM_GPIO, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define RK29SDK_WIFI_SDIO_CARD_INT RK30_PIN3_PD2
-
-
-/*
-* define sdcard PowerEn-pin
-*/
-#define RK29SDK_SD_CARD_PWR_EN RK30_PIN3_PA1
-#define RK29SDK_SD_CARD_PWR_EN_LEVEL GPIO_LOW
-
-/*
-* define the card-detect-pin.
-*/
-#define RK29SDK_SD_CARD_DETECT_N RK30_PIN3_PB0 //According to your own project to set the value of card-detect-pin.
-#define RK29SDK_SD_CARD_INSERT_LEVEL GPIO_LOW // set the voltage of insert-card. Please pay attention to the default setting.
-
-/*
-* Define wifi module's power and reset gpio, and gpio sensitive level.
-* Please set the value according to your own project.
-*
-* Well, you just own engineering module to set the value in the corresponding module branch.
-* Otherwise, you do not define this macro, eliminate it.
-*
-*/
-#if defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU)
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_LOW//GPIO_HIGH
-
-#elif defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319) || defined(CONFIG_RK903) || defined(CONFIG_RK901)
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN2_PA7
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
-
-#elif defined(CONFIG_MT5931_MT6622) || defined(CONFIG_MT5931)
-
- #if 1
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- //#define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- //#define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
-
- #else
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN0_PA5
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #endif
-
-#elif defined(CONFIG_MT6620)
- #define COMBO_MODULE_MT6620_CDT 1 // to control antsel2,antsel3 and gps_lan foot when using AcSip or Cdtech chip.
- //- 1--use Cdtech chip; 0--unuse CDT chip
-
- //power, PMU_EN
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PC7
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- //reset, DAIRST,SYSRST_B
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- //VDDIO
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL RK30_PIN0_PD2 //You do not get control of the foot, and you do not need to define the macro
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_ENABLE_VALUE GPIO_HIGH
- //WIFI_INT_B
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
- //BGF_INT_B
- #define RK30SDK_WIFI_GPIO_BGF_INT_B RK30_PIN6_PA7
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_ENABLE_VALUE GPIO_HIGH
- //GPS_SYNC
- #define RK30SDK_WIFI_GPIO_GPS_SYNC RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_ENABLE_VALUE GPIO_HIGH
-
- #if COMBO_MODULE_MT6620_CDT
- //ANTSEL2
- #define RK30SDK_WIFI_GPIO_ANTSEL2 RK30_PIN4_PD4
- #define RK30SDK_WIFI_GPIO_ANTSEL2_ENABLE_VALUE GPIO_LOW //use 6620 in CDT chip, LOW--work; High--no work.
- //ANTSEL3
- #define RK30SDK_WIFI_GPIO_ANTSEL3 RK30_PIN4_PD3
- #define RK30SDK_WIFI_GPIO_ANTSEL3_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- //GPS_LAN
- #define RK30SDK_WIFI_GPIO_GPS_LAN RK30_PIN4_PD6
- #define RK30SDK_WIFI_GPIO_GPS_LAN_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- #endif // #if COMBO_MODULE_MT6620_CDT--#endif
-#endif
-
-double rk31sdk_get_sdio_wifi_voltage(void)
-{
- double voltage;
-
- /******************************************************************************
- ** Please tell me how much wifi-module uses voltage in your project.
- ******************************************************************************/
-#if defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319) || defined(CONFIG_RK903) || defined(CONFIG_RK901)
- voltage = 1800 ; //power 1.8V
-
-#elif defined(CONFIG_MT5931_MT6622)||defined(CONFIG_MT5931)||defined(CONFIG_MT6620)
- voltage = 1800 ; //power 2.8V
-#elif defined(CONFIG_RDA5990)||defined(CONFIG_RTL8723AS)
- voltage = 3300 ; //power 3.3V
-#else
- //default, sdio use 3.0V
- voltage = 3000 ; //power 3.0V
-#endif
-
- return voltage;
-}
-
-
-
+++ /dev/null
-#include <linux/regulator/machine.h>
-#include <linux/regulator/act8846.h>
-#include <mach/sram.h>
-#include <linux/platform_device.h>
-
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <mach/board.h>
-
-#ifdef CONFIG_REGULATOR_ACT8846
-
-static int act8846_set_init(struct act8846 *act8846)
-{
- struct regulator *dcdc;
- struct regulator *ldo;
- int i = 0;
- printk("%s,line=%d\n", __func__,__LINE__);
-
- #ifndef CONFIG_RK_CONFIG
- g_pmic_type = PMIC_TYPE_ACT8846;
- #endif
- printk("%s:g_pmic_type=%d\n",__func__,g_pmic_type);
-
- for(i = 0; i < ARRAY_SIZE(act8846_dcdc_info); i++)
- {
-
- if(act8846_dcdc_info[i].min_uv == 0 && act8846_dcdc_info[i].max_uv == 0)
- continue;
- dcdc =regulator_get(NULL, act8846_dcdc_info[i].name);
- regulator_set_voltage(dcdc, act8846_dcdc_info[i].min_uv, act8846_dcdc_info[i].max_uv);
- regulator_set_suspend_voltage(dcdc, act8846_dcdc_info[i].suspend_vol);
- regulator_enable(dcdc);
- printk("%s %s =%dmV end\n", __func__,act8846_dcdc_info[i].name, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
- }
-
- for(i = 0; i < ARRAY_SIZE(act8846_ldo_info); i++)
- {
- if(act8846_ldo_info[i].min_uv == 0 && act8846_ldo_info[i].max_uv == 0)
- continue;
- ldo =regulator_get(NULL, act8846_ldo_info[i].name);
- regulator_set_voltage(ldo, act8846_ldo_info[i].min_uv, act8846_ldo_info[i].max_uv);
- regulator_enable(ldo);
- printk("%s %s =%dmV end\n", __func__,act8846_ldo_info[i].name, regulator_get_voltage(ldo));
- regulator_put(ldo);
- }
-
- #ifdef CONFIG_RK_CONFIG
- if(sram_gpio_init(get_port_config(pmic_slp).gpio, &pmic_sleep) < 0){
- printk(KERN_ERR "sram_gpio_init failed\n");
- return -EINVAL;
- }
- if(port_output_init(pmic_slp, 0, "pmic_slp") < 0){
- printk(KERN_ERR "port_output_init failed\n");
- return -EINVAL;
- }
- #else
- if(sram_gpio_init(PMU_POWER_SLEEP, &pmic_sleep) < 0){
- printk(KERN_ERR "sram_gpio_init failed\n");
- return -EINVAL;
- }
- gpio_request(PMU_POWER_SLEEP, "NULL");
- gpio_direction_output(PMU_POWER_SLEEP, GPIO_LOW);
-
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- if(sram_gpio_init(PMU_VSEL, &pmic_vsel) < 0){
- printk(KERN_ERR "sram_gpio_init failed\n");
- return -EINVAL;
- }
-// rk30_mux_api_set(GPIO3D3_PWM0_NAME,GPIO3D_GPIO3D3);
- gpio_request(PMU_VSEL, "NULL");
- gpio_direction_output(PMU_VSEL, GPIO_HIGH);
- #endif
-
- #endif
-
- printk("%s,line=%d END\n", __func__,__LINE__);
-
-
- return 0;
-}
-
-static struct regulator_consumer_supply act8846_buck1_supply[] = {
- {
- .supply = "act_dcdc1",
- },
-
-};
-static struct regulator_consumer_supply act8846_buck2_supply[] = {
- {
- .supply = "act_dcdc2",
- },
- {
- .supply = "vdd_core",
- },
-
-};
-static struct regulator_consumer_supply act8846_buck3_supply[] = {
- {
- .supply = "act_dcdc3",
- },
- {
- .supply = "vdd_cpu",
- },
-};
-
-static struct regulator_consumer_supply act8846_buck4_supply[] = {
- {
- .supply = "act_dcdc4",
- },
-
-};
-
-static struct regulator_consumer_supply act8846_ldo1_supply[] = {
- {
- .supply = "act_ldo1",
- },
-};
-static struct regulator_consumer_supply act8846_ldo2_supply[] = {
- {
- .supply = "act_ldo2",
- },
-};
-
-static struct regulator_consumer_supply act8846_ldo3_supply[] = {
- {
- .supply = "act_ldo3",
- },
-};
-static struct regulator_consumer_supply act8846_ldo4_supply[] = {
- {
- .supply = "act_ldo4",
- },
-};
-static struct regulator_consumer_supply act8846_ldo5_supply[] = {
- {
- .supply = "act_ldo5",
- },
-};
-static struct regulator_consumer_supply act8846_ldo6_supply[] = {
- {
- .supply = "act_ldo6",
- },
-};
-
-static struct regulator_consumer_supply act8846_ldo7_supply[] = {
- {
- .supply = "act_ldo7",
- },
-};
-static struct regulator_consumer_supply act8846_ldo8_supply[] = {
- {
- .supply = "act_ldo8",
- },
-};
-static struct regulator_consumer_supply act8846_ldo9_supply[] = {
- {
- .supply = "act_ldo9",
- },
-};
-
-
-static struct regulator_init_data act8846_buck1 = {
- .constraints = {
- .name = "ACT_DCDC1",
- .min_uV = 600000,
- .max_uV = 3900000,
- .apply_uV = 1,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(act8846_buck1_supply),
- .consumer_supplies = act8846_buck1_supply,
-};
-
-/* */
-static struct regulator_init_data act8846_buck2 = {
- .constraints = {
- .name = "ACT_DCDC2",
- .min_uV = 600000,
- .max_uV = 3900000,
- .apply_uV = 1,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(act8846_buck2_supply),
- .consumer_supplies = act8846_buck2_supply,
-};
-
-/* */
-static struct regulator_init_data act8846_buck3 = {
- .constraints = {
- .name = "ACT_DCDC3",
- .min_uV = 600000,
- .max_uV = 3900000,
- .apply_uV = 1,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(act8846_buck3_supply),
- .consumer_supplies = act8846_buck3_supply,
-};
-
-static struct regulator_init_data act8846_buck4 = {
- .constraints = {
- .name = "ACT_DCDC4",
- .min_uV = 600000,
- .max_uV = 3900000,
- .apply_uV = 1,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(act8846_buck4_supply),
- .consumer_supplies = act8846_buck4_supply,
-};
-
-static struct regulator_init_data act8846_ldo1 = {
- .constraints = {
- .name = "ACT_LDO1",
- .min_uV = 600000,
- .max_uV = 3900000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(act8846_ldo1_supply),
- .consumer_supplies = act8846_ldo1_supply,
-};
-
-/* */
-static struct regulator_init_data act8846_ldo2 = {
- .constraints = {
- .name = "ACT_LDO2",
- .min_uV = 600000,
- .max_uV = 3900000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(act8846_ldo2_supply),
- .consumer_supplies = act8846_ldo2_supply,
-};
-
-/* */
-static struct regulator_init_data act8846_ldo3 = {
- .constraints = {
- .name = "ACT_LDO3",
- .min_uV = 600000,
- .max_uV = 3900000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(act8846_ldo3_supply),
- .consumer_supplies = act8846_ldo3_supply,
-};
-
-/* */
-static struct regulator_init_data act8846_ldo4 = {
- .constraints = {
- .name = "ACT_LDO4",
- .min_uV = 600000,
- .max_uV = 3900000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(act8846_ldo4_supply),
- .consumer_supplies = act8846_ldo4_supply,
-};
-
-static struct regulator_init_data act8846_ldo5 = {
- .constraints = {
- .name = "ACT_LDO5",
- .min_uV = 600000,
- .max_uV = 3900000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(act8846_ldo5_supply),
- .consumer_supplies = act8846_ldo5_supply,
-};
-
-static struct regulator_init_data act8846_ldo6 = {
- .constraints = {
- .name = "ACT_LDO6",
- .min_uV = 600000,
- .max_uV = 3900000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(act8846_ldo6_supply),
- .consumer_supplies = act8846_ldo6_supply,
-};
-
-static struct regulator_init_data act8846_ldo7 = {
- .constraints = {
- .name = "ACT_LDO7",
- .min_uV = 600000,
- .max_uV = 3900000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(act8846_ldo7_supply),
- .consumer_supplies = act8846_ldo7_supply,
-};
-
-static struct regulator_init_data act8846_ldo8 = {
- .constraints = {
- .name = "ACT_LDO8",
- .min_uV = 600000,
- .max_uV = 3900000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(act8846_ldo8_supply),
- .consumer_supplies = act8846_ldo8_supply,
-};
-
-static struct regulator_init_data act8846_ldo9 = {
- .constraints = {
- .name = "ACT_LDO9",
- .min_uV = 600000,
- .max_uV = 3900000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(act8846_ldo9_supply),
- .consumer_supplies = act8846_ldo9_supply,
-};
-
-struct act8846_regulator_subdev act8846_regulator_subdev_id[] = {
- {
- .id=0,
- .initdata=&act8846_buck1,
- },
-
- {
- .id=1,
- .initdata=&act8846_buck2,
- },
- {
- .id=2,
- .initdata=&act8846_buck3,
- },
- {
- .id=3,
- .initdata=&act8846_buck4,
- },
-
- {
- .id=4,
- .initdata=&act8846_ldo1,
- },
-
- {
- .id=5,
- .initdata=&act8846_ldo2,
- },
-
- {
- .id=6,
- .initdata=&act8846_ldo3,
- },
-
- {
- .id=7,
- .initdata=&act8846_ldo4,
- },
-
- {
- .id=8,
- .initdata=&act8846_ldo5,
- },
-
- {
- .id=9,
- .initdata=&act8846_ldo6,
- },
-
- {
- .id=10,
- .initdata=&act8846_ldo7,
- },
-
- {
- .id=11,
- .initdata=&act8846_ldo8,
- },
-#if 1
- {
- .id=12,
- .initdata=&act8846_ldo9,
- },
-#endif
-};
-
-static struct act8846_platform_data act8846_data={
- .set_init=act8846_set_init,
- .num_regulators=13,
- .regulators=act8846_regulator_subdev_id,
-};
-
-#ifdef CONFIG_HAS_EARLYSUSPEND
-void act8846_early_suspend(struct early_suspend *h)
-{
-}
-
-void act8846_late_resume(struct early_suspend *h)
-{
-}
-#endif
-
-#ifdef CONFIG_PM
-int __sramdata vdd_cpu_vol ,vdd_core_vol;
-void act8846_device_suspend(void)
-{
- struct regulator *dcdc;
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- sram_gpio_set_value(pmic_vsel, GPIO_LOW);
-
- dcdc =dvfs_get_regulator( "vdd_cpu");
- vdd_cpu_vol = regulator_get_voltage(dcdc);
- regulator_set_voltage(dcdc, 900000, 900000);
- udelay(100);
-
- dcdc =dvfs_get_regulator( "vdd_core");
- vdd_core_vol = regulator_get_voltage(dcdc);
- regulator_set_voltage(dcdc, 900000, 900000);
- udelay(100);
-
- dcdc =regulator_get(NULL, "act_dcdc4");
- regulator_set_voltage(dcdc, 2800000, 2800000);
- regulator_put(dcdc);
- udelay(100);
-
- #endif
-}
-
-void act8846_device_resume(void)
-{
- struct regulator *dcdc;
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
-
- dcdc =dvfs_get_regulator( "vdd_cpu");
- regulator_set_voltage(dcdc, vdd_cpu_vol, vdd_cpu_vol);
- udelay(100);
-
- dcdc =dvfs_get_regulator( "vdd_core");
- regulator_set_voltage(dcdc, vdd_core_vol, vdd_core_vol);
- udelay(100);
-
- dcdc =regulator_get(NULL, "act_dcdc4");
- regulator_set_voltage(dcdc, 3000000, 3000000);
- regulator_put(dcdc);
- udelay(100);
-
- sram_gpio_set_value(pmic_vsel, GPIO_HIGH);
-
- #endif
-
-}
-#else
-void act8846_device_suspend(void)
-{
-}
-void act8846_device_resume(void)
-{
-}
-#endif
-
-void __sramfunc board_pmu_act8846_suspend(void)
-{
- #ifdef CONFIG_CLK_SWITCH_TO_32K
- sram_gpio_set_value(pmic_sleep, GPIO_HIGH);
- #endif
-}
-void __sramfunc board_pmu_act8846_resume(void)
-{
- #ifdef CONFIG_CLK_SWITCH_TO_32K
- sram_gpio_set_value(pmic_sleep, GPIO_LOW);
- sram_32k_udelay(10000);
- #endif
-}
-void __sramfunc board_act8846_set_suspend_vol(void)
-{
-#ifdef CONFIG_ACT8846_SUPPORT_RESET
- if(pmic_is_act8846()){
- sram_gpio_set_value(pmic_vsel, GPIO_HIGH);
- }
-#endif
-}
-void __sramfunc board_act8846_set_resume_vol(void)
-{
-#ifdef CONFIG_ACT8846_SUPPORT_RESET
- if(pmic_is_act8846()){
- sram_gpio_set_value(pmic_vsel, GPIO_LOW);
- }
-#endif
-}
-
-
-#endif
-
-
-
-
+++ /dev/null
-#include <linux/regulator/machine.h>
-#include <linux/mfd/ricoh619.h>
-#include <linux/regulator/ricoh619-regulator.h>
-#include <linux/power/ricoh619_battery.h>
-#include <linux/rtc/rtc-ricoh619.h>
-#include <mach/sram.h>
-#include <linux/platform_device.h>
-
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <mach/board.h>
-
-#ifdef CONFIG_MFD_RICOH619
-
-static struct ricoh619 *Ricoh619;
-static int ricoh619_pre_init(struct ricoh619 *ricoh619){
-
- Ricoh619 = ricoh619;
- printk("%s,line=%d\n", __func__,__LINE__);
- int ret;
-
- ret = ricoh619_set_bits(ricoh619->dev,RICOH619_PWR_REP_CNT,(1 << 0)); //set restart when power off
-
- /**********set dcdc mode when in sleep mode **************/
-
- /*****************************************************/
-
- /****************set Re-charging voltage*****************/
- ret = ricoh619_set_bits(ricoh619->dev,BATSET2_REG,(3 << 0));
- ret = ricoh619_clr_bits(ricoh619->dev,BATSET2_REG,(1 << 2)); //set vrchg 4v
- /*****************************************************/
-
- /****************set dcdc & ldo on or off when in sleep******/
-// ret = ricoh619_clr_bits(ricoh619->dev,RICOH_DC1_SLOT,(0xf << 0));
-
-// ret = ricoh619_clr_bits(ricoh619->dev,RICOH_LDO1_SLOT,(0xf << 0));
- /*****************************************************/
- return 0;
- }
-static int ricoh619_post_init(struct ricoh619 *ricoh619)
-{
- struct regulator *dcdc;
- struct regulator *ldo;
- int i = 0,ret=0;
- printk("%s,line=%d\n", __func__,__LINE__);
-
- #ifndef CONFIG_RK_CONFIG
- g_pmic_type = PMIC_TYPE_RICOH619;
- #endif
- printk("%s:g_pmic_type=%d\n",__func__,g_pmic_type);
-
- for(i = 0; i < ARRAY_SIZE(ricoh619_dcdc_info); i++)
- {
-
- if(ricoh619_dcdc_info[i].min_uv == 0 && ricoh619_dcdc_info[i].max_uv == 0)
- continue;
- dcdc =regulator_get(NULL, ricoh619_dcdc_info[i].name);
- regulator_set_voltage(dcdc, ricoh619_dcdc_info[i].min_uv, ricoh619_dcdc_info[i].max_uv);
- regulator_set_suspend_voltage(dcdc, ricoh619_dcdc_info[i].suspend_vol);
- regulator_set_mode(dcdc, REGULATOR_MODE_NORMAL);
- regulator_enable(dcdc);
- printk("%s %s =%duV end\n", __func__,ricoh619_dcdc_info[i].name, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
- }
-
- for(i = 0; i < ARRAY_SIZE(ricoh619_ldo_info); i++)
- {
- if(ricoh619_ldo_info[i].min_uv == 0 && ricoh619_ldo_info[i].max_uv == 0)
- continue;
- ldo =regulator_get(NULL, ricoh619_ldo_info[i].name);
- regulator_set_voltage(ldo, ricoh619_ldo_info[i].min_uv, ricoh619_ldo_info[i].max_uv);
- regulator_enable(ldo);
- printk("%s %s =%duV end\n", __func__,ricoh619_ldo_info[i].name, regulator_get_voltage(ldo));
- regulator_put(ldo);
- }
-
- #ifdef CONFIG_RK_CONFIG
- if(sram_gpio_init(get_port_config(pmic_slp).gpio, &pmic_sleep) < 0){
- printk(KERN_ERR "sram_gpio_init failed\n");
- return -EINVAL;
- }
- if(port_output_init(pmic_slp, 0, "pmic_slp") < 0){
- printk(KERN_ERR "port_output_init failed\n");
- return -EINVAL;
- }
- #else
- if(sram_gpio_init(PMU_POWER_SLEEP, &pmic_sleep) < 0){
- printk(KERN_ERR "sram_gpio_init failed\n");
- return -EINVAL;
- }
- gpio_request(PMU_POWER_SLEEP, "NULL");
- gpio_direction_output(PMU_POWER_SLEEP, GPIO_LOW);
-
- #endif
-
- ret = ricoh619_clr_bits(ricoh619->dev,0xb1,(7<< 0)); //set vbatdec voltage 3.0v
- ret = ricoh619_set_bits(ricoh619->dev,0xb1,(3<< 0)); //set vbatdec voltage 3.0v
-
- printk("%s,line=%d END\n", __func__,__LINE__);
-
- return 0;
-}
-static struct regulator_consumer_supply ricoh619_dcdc1_supply[] = {
- {
- .supply = "ricoh_dc1",
- },
- {
- .supply = "vdd_cpu",
- },
-
-};
-static struct regulator_consumer_supply ricoh619_dcdc2_supply[] = {
- {
- .supply = "ricoh_dc2",
- },
- {
- .supply = "vdd_core",
- },
-
-};
-static struct regulator_consumer_supply ricoh619_dcdc3_supply[] = {
- {
- .supply = "ricoh_dc3",
- },
-};
-
-static struct regulator_consumer_supply ricoh619_dcdc4_supply[] = {
- {
- .supply = "ricoh_dc4",
- },
-};
-
-static struct regulator_consumer_supply ricoh619_dcdc5_supply[] = {
- {
- .supply = "ricoh_dc5",
- },
-};
-
-static struct regulator_consumer_supply ricoh619_ldo1_supply[] = {
- {
- .supply = "ricoh_ldo1",
- },
-};
-static struct regulator_consumer_supply ricoh619_ldo2_supply[] = {
- {
- .supply = "ricoh_ldo2",
- },
-};
-
-static struct regulator_consumer_supply ricoh619_ldo3_supply[] = {
- {
- .supply = "ricoh_ldo3",
- },
-};
-static struct regulator_consumer_supply ricoh619_ldo4_supply[] = {
- {
- .supply = "ricoh_ldo4",
- },
-};
-static struct regulator_consumer_supply ricoh619_ldo5_supply[] = {
- {
- .supply = "ricoh_ldo5",
- },
-};
-static struct regulator_consumer_supply ricoh619_ldo6_supply[] = {
- {
- .supply = "ricoh_ldo6",
- },
-};
-static struct regulator_consumer_supply ricoh619_ldo7_supply[] = {
- {
- .supply = "ricoh_ldo7",
- },
-};
-static struct regulator_consumer_supply ricoh619_ldo8_supply[] = {
- {
- .supply = "ricoh_ldo8",
- },
-};
-static struct regulator_consumer_supply ricoh619_ldo9_supply[] = {
- {
- .supply = "ricoh_ldo9",
- },
-};
-static struct regulator_consumer_supply ricoh619_ldo10_supply[] = {
- {
- .supply = "ricoh_ldo10",
- },
-};
-static struct regulator_consumer_supply ricoh619_ldortc1_supply[] = {
- {
- .supply = "ricoh_ldortc1",
- },
-};
-
-static struct regulator_init_data ricoh619_dcdc1 = {
- .constraints = {
- .name = "RICOH_DC1",
- .min_uV = 600000,
- .max_uV = 3500000,
- .apply_uV = 1,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL | REGULATOR_MODE_FAST,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(ricoh619_dcdc1_supply),
- .consumer_supplies = ricoh619_dcdc1_supply,
-};
-
-/* */
-static struct regulator_init_data ricoh619_dcdc2 = {
- .constraints = {
- .name = "RICOH_DC2",
- .min_uV = 600000,
- .max_uV = 3500000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL | REGULATOR_MODE_FAST,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(ricoh619_dcdc2_supply),
- .consumer_supplies = ricoh619_dcdc2_supply,
-};
-
-/* */
-static struct regulator_init_data ricoh619_dcdc3 = {
- .constraints = {
- .name = "RICOH_DC3",
- .min_uV = 600000,
- .max_uV = 3500000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL | REGULATOR_MODE_FAST,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(ricoh619_dcdc3_supply),
- .consumer_supplies = ricoh619_dcdc3_supply,
-};
-
-static struct regulator_init_data ricoh619_dcdc4 = {
- .constraints = {
- .name = "RICOH_DC4",
- .min_uV = 600000,
- .max_uV = 3500000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL | REGULATOR_MODE_FAST,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(ricoh619_dcdc4_supply),
- .consumer_supplies = ricoh619_dcdc4_supply,
-};
-static struct regulator_init_data ricoh619_dcdc5 = {
- .constraints = {
- .name = "RICOH_DC5",
- .min_uV = 600000,
- .max_uV = 3500000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL | REGULATOR_MODE_FAST,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(ricoh619_dcdc5_supply),
- .consumer_supplies = ricoh619_dcdc5_supply,
-};
-
-static struct regulator_init_data ricoh619_ldo1 = {
- .constraints = {
- .name = "RICOH_LDO1",
- .min_uV = 900000,
- .max_uV = 3500000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(ricoh619_ldo1_supply),
- .consumer_supplies = ricoh619_ldo1_supply,
-};
-
-/* */
-static struct regulator_init_data ricoh619_ldo2 = {
- .constraints = {
- .name = "RICOH_LDO2",
- .min_uV = 900000,
- .max_uV = 3500000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(ricoh619_ldo2_supply),
- .consumer_supplies = ricoh619_ldo2_supply,
-};
-
-/* */
-static struct regulator_init_data ricoh619_ldo3 = {
- .constraints = {
- .name = "RICOH_LDO3",
- .min_uV = 900000,
- .max_uV = 3500000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(ricoh619_ldo3_supply),
- .consumer_supplies = ricoh619_ldo3_supply,
-};
-
-/* */
-static struct regulator_init_data ricoh619_ldo4 = {
- .constraints = {
- .name = "RICOH_LDO4",
- .min_uV = 900000,
- .max_uV = 3500000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(ricoh619_ldo4_supply),
- .consumer_supplies = ricoh619_ldo4_supply,
-};
-
-/* */
-static struct regulator_init_data ricoh619_ldo5 = {
- .constraints = {
- .name = "RICOH_LDO5",
- .min_uV = 900000,
- .max_uV = 3500000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(ricoh619_ldo5_supply),
- .consumer_supplies = ricoh619_ldo5_supply,
-};
-
-static struct regulator_init_data ricoh619_ldo6 = {
- .constraints = {
- .name = "RICOH_LDO6",
- .min_uV = 900000,
- .max_uV = 3500000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(ricoh619_ldo6_supply),
- .consumer_supplies = ricoh619_ldo6_supply,
-};
-
-static struct regulator_init_data ricoh619_ldo7 = {
- .constraints = {
- .name = "RICOH_LDO7",
- .min_uV = 900000,
- .max_uV = 3500000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(ricoh619_ldo7_supply),
- .consumer_supplies = ricoh619_ldo7_supply,
-};
-
-static struct regulator_init_data ricoh619_ldo8 = {
- .constraints = {
- .name = "RICOH_LDO8",
- .min_uV = 900000,
- .max_uV = 3500000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(ricoh619_ldo8_supply),
- .consumer_supplies = ricoh619_ldo8_supply,
-};
-
-static struct regulator_init_data ricoh619_ldo9 = {
- .constraints = {
- .name = "RICOH_LDO9",
- .min_uV = 900000,
- .max_uV = 3500000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(ricoh619_ldo9_supply),
- .consumer_supplies = ricoh619_ldo9_supply,
-};
-
-static struct regulator_init_data ricoh619_ldo10 = {
- .constraints = {
- .name = "RICOH_LDO10",
- .min_uV = 900000,
- .max_uV = 3500000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(ricoh619_ldo10_supply),
- .consumer_supplies = ricoh619_ldo10_supply,
-};
-
-/* */
-static struct regulator_init_data ricoh619_ldortc1 = {
- .constraints = {
- .name = "RICOH_LDORTC1",
- .min_uV = 1700000,
- .max_uV = 3500000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(ricoh619_ldortc1_supply),
- .consumer_supplies = ricoh619_ldortc1_supply,
-};
-
-static struct ricoh619_battery_platform_data ricoh619_power_battery = {
- .irq = IRQ_BOARD_BASE,//INT_PMIC_BASE,
- .alarm_vol_mv = 3300,
- .multiple = 100,
- .monitor_time = 60,
-
- //4200mv type battery
-
- .ch_vfchg = 0xFF, /* VFCHG = 0x0-0x4 (4.05v 4.10v 4.15v 4.20v 4.35v) 0xFF is OTP setting*/
- .ch_vrchg = 0xFF, /* VRCHG = 0x0-0x4 (3.85v 3.90v 3.95v 4.00v 4.10v) 0xFF is OTP setting*/
- .ch_vbatovset = 0xFF, /* VBATOVSET = 0 or 1 (0 : 4.38V(up)/3.95V(down) 1: 4.53V(up)/4.10V(down))
- 0xFF is OTP setting*/
- .ch_ichg = 0xFF, /* ICHG = 0x0-0x1D (100mA - 3000mA) 0xFF is OTP setting*/
- .ch_icchg = 0x03, /* ICCHG = 0x0-3 (50mA 100mA 150mA 200mA) 0xFF is OTP setting*/
- .ch_ilim_adp = 0xFF, /* ILIM_ADP = 0x0-0x1D (100mA - 3000mA) */
- .ch_ilim_usb = 0xFF, /* ILIM_USB = 0x0-0x1D (100mA - 3000mA) */
- .fg_target_vsys = 3200, /* This value is the target one to DSOC=0% */
- .fg_target_ibat = 2000, /* This value is the target one to DSOC=0% */
- .jt_en = 0, /* JEITA Switch = 1:enable, 0:disable */
- .jt_hw_sw = 1, /* JEITA is controlled by 1:HW, 0:SW */
- .jt_temp_h = 50, /* degree C */
- .jt_temp_l = 12, /* degree C */
- .jt_vfchg_h = 0x03, /* VFCHG High = 0 - 0x04 (4.05, 4.10, 4.15, 4.20, 4.35V) */
- .jt_vfchg_l = 0, /* VFCHG Low = 0 - 0x04 (4.05, 4.10, 4.15, 4.20, 4.35V) */
- .jt_ichg_h = 0x0D, /* ICHG High = 0 - 0x1D (100 - 3000mA) */
- .jt_ichg_l = 0x09, /* ICHG Low = 0 - 0x1D (100 - 3000mA) */
-};
-
-static struct rtc_time rk_time = { // 2012.1.1 12:00:00 Saturday
- .tm_wday = 6,
- .tm_year = 111,
- .tm_mon = 0,
- .tm_mday = 1,
- .tm_hour = 12,
- .tm_min = 0,
- .tm_sec = 0,
-};
-
-static struct ricoh619_rtc_platform_data ricoh619_rtc_data = {
- .irq = IRQ_BOARD_BASE ,
- .time = &rk_time,
-};
-
-#define RICOH_REG(_id, _data) \
-{ \
- .id = RICOH619_ID_##_id, \
- .name = "ricoh619-regulator", \
- .platform_data = _data, \
-} \
-
-static struct ricoh619_pwrkey_platform_data ricoh619_pwrkey_data= {
- .irq = IRQ_BOARD_BASE + RICOH619_IRQ_POWER_ON,
- .delay_ms = 20,
-};
-
-static struct ricoh619_subdev_info ricoh619_devs[] = {
- RICOH_REG(DC1, &ricoh619_dcdc1),
- RICOH_REG(DC2, &ricoh619_dcdc2),
- RICOH_REG(DC3, &ricoh619_dcdc3),
- RICOH_REG(DC4, &ricoh619_dcdc4),
- RICOH_REG(DC5, &ricoh619_dcdc5),
-
- RICOH_REG(LDO1, &ricoh619_ldo1),
- RICOH_REG(LDO2, &ricoh619_ldo2),
- RICOH_REG(LDO3, &ricoh619_ldo3),
- RICOH_REG(LDO4, &ricoh619_ldo4),
- RICOH_REG(LDO5, &ricoh619_ldo5),
- RICOH_REG(LDO6, &ricoh619_ldo6),
- RICOH_REG(LDO7, &ricoh619_ldo7),
- RICOH_REG(LDO8, &ricoh619_ldo8),
- RICOH_REG(LDO9, &ricoh619_ldo9),
- RICOH_REG(LDO10, &ricoh619_ldo10),
- RICOH_REG(LDORTC1, &ricoh619_ldortc1),
-
- {
- .id = 16,
- .name ="ricoh619-battery",
- .platform_data = &ricoh619_power_battery,
- },
-
- {
- .id = 17,
- .name ="rtc_ricoh619",
- .platform_data = &ricoh619_rtc_data,
- },
-
- {
- .id = 18,
- .name ="ricoh619-pwrkey",
- .platform_data = &ricoh619_pwrkey_data,
- },
-
-};
-
-#define RICOH_GPIO_INIT(_init_apply, _output_mode, _output_val, _led_mode, _led_func) \
-{ \
- .output_mode_en = _output_mode, \
- .output_val = _output_val, \
- .init_apply = _init_apply, \
- .led_mode = _led_mode, \
- .led_func = _led_func, \
-} \
-
-struct ricoh619_gpio_init_data ricoh_gpio_data[] = {
- RICOH_GPIO_INIT(0, 1, 0, 0, 1),
- RICOH_GPIO_INIT(0, 0, 0, 0, 0),
- RICOH_GPIO_INIT(0, 0, 0, 0, 0),
- RICOH_GPIO_INIT(0, 0, 0, 0, 0),
- RICOH_GPIO_INIT(0, 0, 0, 0, 0),
-};
-
-static struct ricoh619_platform_data ricoh619_data={
- .irq_base = IRQ_BOARD_BASE,
-// .init_port = RICOH619_HOST_IRQ,
- .num_subdevs = ARRAY_SIZE(ricoh619_devs),
- .subdevs = ricoh619_devs,
- .pre_init = ricoh619_pre_init,
- .post_init = ricoh619_post_init,
- //.gpio_base = RICOH619_GPIO_EXPANDER_BASE,
- .gpio_init_data = ricoh_gpio_data,
- .num_gpioinit_data = ARRAY_SIZE(ricoh_gpio_data),
- .enable_shutdown_pin = 0,
-};
-
-void __sramfunc board_pmu_ricoh619_suspend(void)
-{
- #ifdef CONFIG_CLK_SWITCH_TO_32K
- sram_gpio_set_value(pmic_sleep, GPIO_HIGH);
- #endif
-}
-void __sramfunc board_pmu_ricoh619_resume(void)
-{
- #ifdef CONFIG_CLK_SWITCH_TO_32K
- sram_gpio_set_value(pmic_sleep, GPIO_LOW);
- sram_32k_udelay(10000);
- #endif
-}
-
-
-#endif
-
-
-
-
+++ /dev/null
-#include <linux/regulator/machine.h>
-#include <linux/mfd/rk808.h>
-#include <mach/sram.h>
-#include <linux/platform_device.h>
-
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <mach/board.h>
-
-#ifdef CONFIG_MFD_RK808
-
-static int rk808_pre_init(struct rk808 *rk808)
-{
- int ret,val;
- printk("%s,line=%d\n", __func__,__LINE__);
- /***********set ILIM ************/
- val = rk808_reg_read(rk808,RK808_BUCK3_CONFIG_REG);
- val &= (~(0x7 <<0));
- val |= (0x2 <<0);
- ret = rk808_reg_write(rk808,RK808_BUCK3_CONFIG_REG,val);
- if (ret < 0) {
- printk(KERN_ERR "Unable to write RK808_BUCK3_CONFIG_REG reg\n");
- return ret;
- }
-
- val = rk808_reg_read(rk808,RK808_BUCK4_CONFIG_REG);
- val &= (~(0x7 <<0));
- val |= (0x3 <<0);
- ret = rk808_reg_write(rk808,RK808_BUCK4_CONFIG_REG,val);
- if (ret < 0) {
- printk(KERN_ERR "Unable to write RK808_BUCK4_CONFIG_REG reg\n");
- return ret;
- }
-
- val = rk808_reg_read(rk808,RK808_BOOST_CONFIG_REG);
- val &= (~(0x7 <<0));
- val |= (0x1 <<0);
- ret = rk808_reg_write(rk808,RK808_BOOST_CONFIG_REG,val);
- if (ret < 0) {
- printk(KERN_ERR "Unable to write RK808_BOOST_CONFIG_REG reg\n");
- return ret;
- }
- /*****************************************/
- /***********set buck OTP function************/
- ret = rk808_reg_write(rk808,0x6f,0x5a);
- if (ret < 0) {
- printk(KERN_ERR "Unable to write 0x6f reg\n");
- return ret;
- }
-
- ret = rk808_reg_write(rk808,0x91,0x80);
- if (ret < 0) {
- printk(KERN_ERR "Unable to write 0x91 reg\n");
- return ret;
- }
-
- ret = rk808_reg_write(rk808,0x92,0x55);
- if (ret <0) {
- printk(KERN_ERR "Unable to write 0x92 reg\n");
- return ret;
- }
- /*****************************************/
- /***********set buck 12.5mv/us ************/
- val = rk808_reg_read(rk808,RK808_BUCK1_CONFIG_REG);
- val &= (~(0x3 <<3));
- val |= (0x3 <<0);
- ret = rk808_reg_write(rk808,RK808_BUCK1_CONFIG_REG,val);
- if (ret < 0) {
- printk(KERN_ERR "Unable to write RK808_BUCK1_CONFIG_REG reg\n");
- return ret;
- }
-
- val = rk808_reg_read(rk808,RK808_BUCK2_CONFIG_REG);
- val &= (~(0x3 <<3));
- val |= (0x3 <<0);
- ret = rk808_reg_write(rk808,RK808_BUCK2_CONFIG_REG,val);
- if (ret <0) {
- printk(KERN_ERR "Unable to write RK808_BUCK2_CONFIG_REG reg\n");
- return ret;
- }
- /*****************************************/
-
- /*******enable switch and boost***********/
- val = rk808_reg_read(rk808,RK808_DCDC_EN_REG);
- val |= (0x3 << 5); //enable switch1/2
-// val |= (0x1 << 4); //enable boost
- ret = rk808_reg_write(rk808,RK808_DCDC_EN_REG,val);
- if (ret <0) {
- printk(KERN_ERR "Unable to write RK808_DCDC_EN_REG reg\n");
- return ret;
- }
- /****************************************/
- /***********set dc1\2 dvs voltge*********/
- val = rk808_reg_read(rk808,RK808_BUCK1_DVS_REG);
- val |= 0x34; //set dc1 dvs 1.35v
- ret = rk808_reg_write(rk808,RK808_BUCK1_DVS_REG,val);
- if (ret <0) {
- printk(KERN_ERR "Unable to write RK808_BUCK1_DVS_REG reg\n");
- return ret;
- }
-
- val = rk808_reg_read(rk808,RK808_BUCK2_DVS_REG);
- val |= 0x34; //set dc2 dvs 1.35v
- ret = rk808_reg_write(rk808,RK808_BUCK2_DVS_REG,val);
- if (ret <0) {
- printk(KERN_ERR "Unable to write RK808_BUCK2_DVS_REG reg\n");
- return ret;
- }
- /***********************************/
-
- /****************set vbat low **********/
- val = rk808_reg_read(rk808,RK808_VB_MON_REG);
- val &= (~(0x7<<0)); //set vbat < 3.5v irq
- val &= (~(0x1 <<4));
- val |= (0x7 <<0);
- val |= (0x1 << 4);
- ret = rk808_reg_write(rk808,RK808_VB_MON_REG,val);
- if (ret <0) {
- printk(KERN_ERR "Unable to write RK808_VB_MON_REG reg\n");
- return ret;
- }
- /**************************************/
- /********set dcdc/ldo/switch off when in sleep******/
- val = rk808_reg_read(rk808,RK808_SLEEP_SET_OFF_REG1);
-// val |= (0x3<<5);
- ret = rk808_reg_write(rk808,RK808_SLEEP_SET_OFF_REG1,val);
- if (ret <0) {
- printk(KERN_ERR "Unable to write RK808_SLEEP_SET_OFF_REG1 reg\n");
- return ret;
- }
- val = rk808_reg_read(rk808,RK808_SLEEP_SET_OFF_REG2);
-// val |= (0x1<<4);
- ret = rk808_reg_write(rk808,RK808_SLEEP_SET_OFF_REG2,val);
- if (ret <0) {
- printk(KERN_ERR "Unable to write RK808_SLEEP_SET_OFF_REG2 reg\n");
- return ret;
- }
- /**************************************************/
- /**********mask int****************/
- val = rk808_reg_read(rk808,RK808_INT_STS_MSK_REG1);
- val |= (0x1<<0); //mask vout_lo_int
- ret = rk808_reg_write(rk808,RK808_INT_STS_MSK_REG1,val);
- if (ret <0) {
- printk(KERN_ERR "Unable to write RK808_INT_STS_MSK_REG1 reg\n");
- return ret;
- }
- /**********************************/
- printk("%s,line=%d\n", __func__,__LINE__);
-}
-static int rk808_set_init(struct rk808 *rk808)
-{
- struct regulator *dcdc;
- struct regulator *ldo;
- int i = 0;
- printk("%s,line=%d\n", __func__,__LINE__);
-
- #ifndef CONFIG_RK_CONFIG
- g_pmic_type = PMIC_TYPE_RK808;
- #endif
- printk("%s:g_pmic_type=%d\n",__func__,g_pmic_type);
-
- for(i = 0; i < ARRAY_SIZE(rk808_dcdc_info); i++)
- {
-
- if(rk808_dcdc_info[i].min_uv == 0 && rk808_dcdc_info[i].max_uv == 0)
- continue;
- dcdc =regulator_get(NULL, rk808_dcdc_info[i].name);
- regulator_set_voltage(dcdc, rk808_dcdc_info[i].min_uv, rk808_dcdc_info[i].max_uv);
- regulator_set_suspend_voltage(dcdc, rk808_dcdc_info[i].suspend_vol);
- regulator_enable(dcdc);
- printk("%s %s =%duV end\n", __func__,rk808_dcdc_info[i].name, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
- }
-
- for(i = 0; i < ARRAY_SIZE(rk808_ldo_info); i++)
- {
- if(rk808_ldo_info[i].min_uv == 0 && rk808_ldo_info[i].max_uv == 0)
- continue;
- ldo =regulator_get(NULL, rk808_ldo_info[i].name);
-
- regulator_set_voltage(ldo, rk808_ldo_info[i].min_uv, rk808_ldo_info[i].max_uv);
- regulator_set_suspend_voltage(ldo, rk808_ldo_info[i].suspend_vol);
- regulator_enable(ldo);
- printk("%s %s =%duV end\n", __func__,rk808_ldo_info[i].name, regulator_get_voltage(ldo));
- regulator_put(ldo);
- }
-
- #ifdef CONFIG_RK_CONFIG
- if(sram_gpio_init(get_port_config(pmic_slp).gpio, &pmic_sleep) < 0){
- printk(KERN_ERR "sram_gpio_init failed\n");
- return -EINVAL;
- }
- if(port_output_init(pmic_slp, 0, "pmic_slp") < 0){
- printk(KERN_ERR "port_output_init failed\n");
- return -EINVAL;
- }
- #else
- if(sram_gpio_init(PMU_POWER_SLEEP, &pmic_sleep) < 0){
- printk(KERN_ERR "sram_gpio_init failed\n");
- return -EINVAL;
- }
- gpio_request(PMU_POWER_SLEEP, "NULL");
- gpio_direction_output(PMU_POWER_SLEEP, GPIO_LOW);
-
- #endif
-
- printk("%s,line=%d END\n", __func__,__LINE__);
-
-
- return 0;
-}
-
-static struct regulator_consumer_supply rk808_buck1_supply[] = {
- {
- .supply = "rk_dcdc1",
- },
-
- {
- .supply = "vdd_cpu",
- },
-
-};
-static struct regulator_consumer_supply rk808_buck2_supply[] = {
- {
- .supply = "rk_dcdc2",
- },
-
- {
- .supply = "vdd_core",
- },
-
-};
-static struct regulator_consumer_supply rk808_buck3_supply[] = {
- {
- .supply = "rk_dcdc3",
- },
-};
-
-static struct regulator_consumer_supply rk808_buck4_supply[] = {
- {
- .supply = "rk_dcdc4",
- },
-
-};
-
-static struct regulator_consumer_supply rk808_ldo1_supply[] = {
- {
- .supply = "rk_ldo1",
- },
-};
-static struct regulator_consumer_supply rk808_ldo2_supply[] = {
- {
- .supply = "rk_ldo2",
- },
-};
-
-static struct regulator_consumer_supply rk808_ldo3_supply[] = {
- {
- .supply = "rk_ldo3",
- },
-};
-static struct regulator_consumer_supply rk808_ldo4_supply[] = {
- {
- .supply = "rk_ldo4",
- },
-};
-static struct regulator_consumer_supply rk808_ldo5_supply[] = {
- {
- .supply = "rk_ldo5",
- },
-};
-static struct regulator_consumer_supply rk808_ldo6_supply[] = {
- {
- .supply = "rk_ldo6",
- },
-};
-
-static struct regulator_consumer_supply rk808_ldo7_supply[] = {
- {
- .supply = "rk_ldo7",
- },
-};
-static struct regulator_consumer_supply rk808_ldo8_supply[] = {
- {
- .supply = "rk_ldo8",
- },
-};
-
-static struct regulator_init_data rk808_buck1 = {
- .constraints = {
- .name = "RK_DCDC1",
- .min_uV = 700000,
- .max_uV = 1500000,
- .apply_uV = 1,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(rk808_buck1_supply),
- .consumer_supplies = rk808_buck1_supply,
-};
-
-/* */
-static struct regulator_init_data rk808_buck2 = {
- .constraints = {
- .name = "RK_DCDC2",
- .min_uV = 700000,
- .max_uV = 1500000,
- .apply_uV = 1,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(rk808_buck2_supply),
- .consumer_supplies = rk808_buck2_supply,
-};
-
-/* */
-static struct regulator_init_data rk808_buck3 = {
- .constraints = {
- .name = "RK_DCDC3",
- .min_uV = 1000000,
- .max_uV = 1800000,
- .apply_uV = 1,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(rk808_buck3_supply),
- .consumer_supplies = rk808_buck3_supply,
-};
-
-static struct regulator_init_data rk808_buck4 = {
- .constraints = {
- .name = "RK_DCDC4",
- .min_uV = 1800000,
- .max_uV = 3300000,
- .apply_uV = 1,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(rk808_buck4_supply),
- .consumer_supplies = rk808_buck4_supply,
-};
-
-static struct regulator_init_data rk808_ldo1 = {
- .constraints = {
- .name = "RK_LDO1",
- .min_uV = 1800000,
- .max_uV = 3400000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(rk808_ldo1_supply),
- .consumer_supplies = rk808_ldo1_supply,
-};
-
-/* */
-static struct regulator_init_data rk808_ldo2 = {
- .constraints = {
- .name = "RK_LDO2",
- .min_uV = 1800000,
- .max_uV = 3400000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(rk808_ldo2_supply),
- .consumer_supplies = rk808_ldo2_supply,
-};
-
-/* */
-static struct regulator_init_data rk808_ldo3 = {
- .constraints = {
- .name = "RK_LDO3",
- .min_uV = 800000,
- .max_uV = 2500000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(rk808_ldo3_supply),
- .consumer_supplies = rk808_ldo3_supply,
-};
-
-/* */
-static struct regulator_init_data rk808_ldo4 = {
- .constraints = {
- .name = "RK_LDO4",
- .min_uV = 1800000,
- .max_uV = 3400000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(rk808_ldo4_supply),
- .consumer_supplies = rk808_ldo4_supply,
-};
-
-static struct regulator_init_data rk808_ldo5 = {
- .constraints = {
- .name = "RK_LDO5",
- .min_uV = 1800000,
- .max_uV = 3400000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(rk808_ldo5_supply),
- .consumer_supplies = rk808_ldo5_supply,
-};
-
-static struct regulator_init_data rk808_ldo6 = {
- .constraints = {
- .name = "RK_LDO6",
- .min_uV = 800000,
- .max_uV = 2500000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(rk808_ldo6_supply),
- .consumer_supplies = rk808_ldo6_supply,
-};
-
-static struct regulator_init_data rk808_ldo7 = {
- .constraints = {
- .name = "RK_LDO7",
- .min_uV = 800000,
- .max_uV = 2500000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(rk808_ldo7_supply),
- .consumer_supplies = rk808_ldo7_supply,
-};
-
-static struct regulator_init_data rk808_ldo8 = {
- .constraints = {
- .name = "RK_LDO8",
- .min_uV = 1800000,
- .max_uV = 3400000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(rk808_ldo8_supply),
- .consumer_supplies = rk808_ldo8_supply,
-};
-
-struct rk808_regulator_subdev rk808_regulator_subdev_id[] = {
- {
- .id=0,
- .initdata=&rk808_buck1,
- },
-
- {
- .id=1,
- .initdata=&rk808_buck2,
- },
- {
- .id=2,
- .initdata=&rk808_buck3,
- },
- {
- .id=3,
- .initdata=&rk808_buck4,
- },
-
- {
- .id=4,
- .initdata=&rk808_ldo1,
- },
-
- {
- .id=5,
- .initdata=&rk808_ldo2,
- },
-
- {
- .id=6,
- .initdata=&rk808_ldo3,
- },
-
- {
- .id=7,
- .initdata=&rk808_ldo4,
- },
-
- {
- .id=8,
- .initdata=&rk808_ldo5,
- },
-
- {
- .id=9,
- .initdata=&rk808_ldo6,
- },
-
- {
- .id=10,
- .initdata=&rk808_ldo7,
- },
-
- {
- .id=11,
- .initdata=&rk808_ldo8,
- },
-};
-
- struct rk808_platform_data rk808_data={
- .pre_init=rk808_pre_init,
- .set_init=rk808_set_init,
- .num_regulators=12,
- .regulators=rk808_regulator_subdev_id,
- .irq = (unsigned)RK808_HOST_IRQ,
- .irq_base = IRQ_BOARD_BASE,
-};
-
-#ifdef CONFIG_HAS_EARLYSUSPEND
-void rk808_early_suspend(struct early_suspend *h)
-{
-}
-
-void rk808_late_resume(struct early_suspend *h)
-{
-}
-#endif
-#ifdef CONFIG_PM
-
-void rk808_device_suspend(void)
-{
-}
-void rk808_device_resume(void)
-{
-}
-#endif
-
-void __sramfunc board_pmu_rk808_suspend(void)
-{
- #ifdef CONFIG_CLK_SWITCH_TO_32K
- sram_gpio_set_value(pmic_sleep, GPIO_HIGH);
- #endif
-}
-void __sramfunc board_pmu_rk808_resume(void)
-{
- #ifdef CONFIG_CLK_SWITCH_TO_32K
- sram_gpio_set_value(pmic_sleep, GPIO_LOW);
- sram_32k_udelay(10000);
- #endif
-}
-
-#endif
-
-
-
-
+++ /dev/null
-#include <linux/regulator/machine.h>
-#include <mach/sram.h>
-#include <linux/platform_device.h>
-
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <mach/board.h>
-
-#include <linux/mfd/rt5025.h>
-
-#ifdef CONFIG_MFD_RT5025
-
-static int rt5025_pre_init(struct rt5025_chip *rt5025_chip){
-
-
- printk("%s,line=%d\n", __func__,__LINE__);
- int ret;
- /**********set voltage speed***********************/
- ret = rt5025_reg_read(rt5025_chip->i2c, 0x08);
- ret &= (~(3<<0)); //dcdc1 25mv/10us
- rt5025_reg_write(rt5025_chip->i2c, 0x08,ret);
-
- ret = rt5025_reg_read(rt5025_chip->i2c, 0x09);
- ret &= (~(3<<0));//dcdc2 100mv/10us
- rt5025_reg_write(rt5025_chip->i2c, 0x09,ret);
-
- ret = rt5025_reg_read(rt5025_chip->i2c, 0x0a);
- ret &= (~(3<<0));//dcdc3 50mv/12us
- rt5025_reg_write(rt5025_chip->i2c, 0x0a,ret);
- /************************************************/
- /***************set power off voltage***************/
- ret = rt5025_reg_read(rt5025_chip->i2c, 0x17);
- ret &= (~(7<<5)); //power off 2.8v
- rt5025_reg_write(rt5025_chip->i2c, 0x17,ret);
-
- ret = rt5025_reg_read(rt5025_chip->i2c, 0x17);
- ret |= (1<<3); //enable DC4 boost
- rt5025_reg_write(rt5025_chip->i2c, 0x17,ret);
- /***********************************************/
- /************************************************/
- return 0;
- }
-static int rt5025_post_init(void)
-{
- struct regulator *dcdc;
- struct regulator *ldo;
- int i = 0;
- printk("%s,line=%d\n", __func__,__LINE__);
-
- #ifndef CONFIG_RK_CONFIG
- g_pmic_type = PMIC_TYPE_RT5025;
- #endif
- printk("%s:g_pmic_type=%d\n",__func__,g_pmic_type);
-
- for(i = 0; i < ARRAY_SIZE(rt5025_dcdc_info); i++)
- {
- if(rt5025_dcdc_info[i].min_uv == 0 && rt5025_dcdc_info[i].max_uv == 0)
- continue;
- dcdc =regulator_get(NULL, rt5025_dcdc_info[i].name);
-
- regulator_set_voltage(dcdc, rt5025_dcdc_info[i].min_uv, rt5025_dcdc_info[i].max_uv);
-
- regulator_set_mode(dcdc, REGULATOR_MODE_NORMAL);
- regulator_enable(dcdc);
- printk("%s %s =%duV end\n", __func__,rt5025_dcdc_info[i].name, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
- }
-
- for(i = 0; i < ARRAY_SIZE(rt5025_ldo_info); i++)
- {
- if(rt5025_ldo_info[i].min_uv == 0 && rt5025_ldo_info[i].max_uv == 0)
- continue;
- ldo =regulator_get(NULL, rt5025_ldo_info[i].name);
- regulator_set_voltage(ldo, rt5025_ldo_info[i].min_uv, rt5025_ldo_info[i].max_uv);
- regulator_enable(ldo);
- printk("%s %s =%duV end\n", __func__,rt5025_ldo_info[i].name, regulator_get_voltage(ldo));
- regulator_put(ldo);
- }
-
- printk("%s,line=%d END\n", __func__,__LINE__);
-
- return 0;
-}
-
- int rt5025_set_otg_enable(int enable)
-{
- if (enable)
- rt5025_ext_set_charging_buck(0);
- else
- rt5025_ext_set_charging_buck(1);
- return 0;
-}
-
-static struct regulator_consumer_supply rt5025_dcdc1_supply[] = {
- {
- .supply = "rt5025-dcdc1",
- },
- {
- .supply = "vdd_cpu",
- },
-
-};
-static struct regulator_consumer_supply rt5025_dcdc2_supply[] = {
- {
- .supply = "rt5025-dcdc2",
- },
- {
- .supply = "vdd_core",
- },
-};
-static struct regulator_consumer_supply rt5025_dcdc3_supply[] = {
- {
- .supply = "rt5025-dcdc3",
- },
-};
-
-static struct regulator_consumer_supply rt5025_dcdc4_supply[] = {
- {
- .supply = "rt5025-dcdc4",
- },
-};
-
-static struct regulator_consumer_supply rt5025_ldo1_supply[] = {
- {
- .supply = "rt5025-ldo1",
- },
-};
-static struct regulator_consumer_supply rt5025_ldo2_supply[] = {
- {
- .supply = "rt5025-ldo2",
- },
-};
-
-static struct regulator_consumer_supply rt5025_ldo3_supply[] = {
- {
- .supply = "rt5025-ldo3",
- },
-};
-static struct regulator_consumer_supply rt5025_ldo4_supply[] = {
- {
- .supply = "rt5025-ldo4",
- },
-};
-static struct regulator_consumer_supply rt5025_ldo5_supply[] = {
- {
- .supply = "rt5025-ldo5",
- },
-};
-static struct regulator_consumer_supply rt5025_ldo6_supply[] = {
- {
- .supply = "rt5025-ldo6",
- },
-};
-
-static struct regulator_init_data rt5025_dcdc1_info = {
- .constraints = {
- .name = "RT5025-DCDC1",
- .min_uV = 700000,
- .max_uV = 2275000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL | REGULATOR_MODE_FAST,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS| REGULATOR_CHANGE_MODE,
- },
- .num_consumer_supplies = ARRAY_SIZE(rt5025_dcdc1_supply),
- .consumer_supplies = rt5025_dcdc1_supply,
-};
-
-static struct regulator_init_data rt5025_dcdc2_info = {
- .constraints = {
- .name = "RT5025-DCDC2",
- .min_uV = 700000,
- .max_uV = 3500000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL | REGULATOR_MODE_FAST,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE,
- },
- .num_consumer_supplies = ARRAY_SIZE(rt5025_dcdc2_supply),
- .consumer_supplies = rt5025_dcdc2_supply,
-};
-
-static struct regulator_init_data rt5025_dcdc3_info = {
- .constraints = {
- .name = "RT5025-DCDC3",
- .min_uV = 700000,
- .max_uV = 3500000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL | REGULATOR_MODE_FAST,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE,
- },
- .num_consumer_supplies = ARRAY_SIZE(rt5025_dcdc3_supply),
- .consumer_supplies = rt5025_dcdc3_supply,
-};
-
-static struct regulator_init_data rt5025_dcdc4_info = {
- .constraints = {
- .name = "RT5025-DCDC4",
- .min_uV = 4500000,
- .max_uV = 5500000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(rt5025_dcdc4_supply),
- .consumer_supplies = rt5025_dcdc4_supply,
-};
-
-static struct regulator_init_data rt5025_ldo1_info = {
- .constraints = {
- .name = "RT5025-LDO1",
- .min_uV = 700000,
- .max_uV = 3500000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(rt5025_ldo1_supply),
- .consumer_supplies = rt5025_ldo1_supply,
-};
-
-static struct regulator_init_data rt5025_ldo2_info = {
- .constraints = {
- .name = "RT5025-LDO2",
- .min_uV = 700000,
- .max_uV = 3500000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(rt5025_ldo2_supply),
- .consumer_supplies = rt5025_ldo2_supply,
-};
-
-static struct regulator_init_data rt5025_ldo3_info = {
- .constraints = {
- .name = "RT5025-LDO3",
- .min_uV = 1000000,
- .max_uV = 3300000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(rt5025_ldo3_supply),
- .consumer_supplies = rt5025_ldo3_supply,
-};
-
-static struct regulator_init_data rt5025_ldo4_info = {
- .constraints = {
- .name = "RT5025-LDO4",
- .min_uV = 1000000,
- .max_uV = 3300000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(rt5025_ldo4_supply),
- .consumer_supplies = rt5025_ldo4_supply,
-};
-
-static struct regulator_init_data rt5025_ldo5_info = {
- .constraints = {
- .name = "RT5025-LDO5",
- .min_uV = 1000000,
- .max_uV = 3300000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(rt5025_ldo5_supply),
- .consumer_supplies = rt5025_ldo5_supply,
-};
-
-static struct regulator_init_data rt5025_ldo6_info = {
- .constraints = {
- .name = "RT5025-LDO6",
- .min_uV = 1000000,
- .max_uV = 3300000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(rt5025_ldo6_supply),
- .consumer_supplies = rt5025_ldo6_supply,
-};
-
-static struct rt5025_power_data rt5025_power_data = {
- .CHGControl2 = {
- .bitfield = {
- .CHGBC_EN = 1,
- .TE = 1,
- .CCCHG_TIMEOUT = RT5025_CCCHG_TO_10H,
- .PRECHG_TIMEOUT = RT5025_PRECHG_TO_60M,
- },
- },
- .CHGControl3 = {
- .bitfield = {
- .VOREG = 0x23,
- },
- },
- .CHGControl4 = {
- .bitfield = {
- .AICR_CON = 1,
- .AICR = RT5025_AICR_500MA,
- .ICC = RT5025_ICC_0P5A,
- },
- },
- .CHGControl5 = {
- .bitfield = {
- .DPM = RT5025_DPM_4P5V,
- },
- },
- .CHGControl6 = {
- .bitfield = {
- .IPREC = RT5025_IPREC_20P,
- .IEOC = RT5025_IEOC_10P,
- .VPREC = RT5025_VPREC_3V,
- },
- },
- .CHGControl7 = {
- .bitfield = {
- .CHGC_EN = 1,
- .CHG_DCDC_MODE = 0,
- .BATD_EN = 0,
- },
- },
-// .fcc = 6200, //6200 mAh
-};
-
-static struct rt5025_gpio_data rt5025_gpio_data = {
-// .gpio_base = RT5025_GPIO_BASE,
- .irq_base = IRQ_BOARD_BASE,
-};
-
-static struct rt5025_misc_data rt5025_misc_data = {
- .RSTCtrl = {
- .bitfield = {
- .Action = 2,
- .Delayed1 = RT5025_RSTDELAY1_1S,
- .Delayed2 = RT5025_RSTDELAY2_1S,
- },
- },
- .VSYSCtrl = {
- .bitfield = {
- .VOFF = RT5025_VOFF_3P0V,
- },
- },
- .PwrOnCfg = {
- .bitfield = {
- .PG_DLY = RT5025_PGDLY_100MS,
- .SHDN_PRESS = RT5025_SHDNPRESS_6S,
- .LPRESS_TIME = RT5025_LPRESS_1P5S,
- .START_TIME = RT5025_STARTIME_100MS,
- },
- },
- .SHDNCtrl = {
- .bitfield = {
- .SHDN_DLYTIME = RT5025_SHDNDLY_1S,
- .SHDN_TIMING = 1,
- .SHDN_CTRL = 0,
- },
- },
- .PwrOffCond = {
- .bitfield = {
- .OT_ENSHDN = 1,
- .PWRON_ENSHDN = 1,
- .DCDC3LV_ENSHDN = 0,
- .DCDC2LV_ENSHDN = 0,
- .DCDC1LV_ENSHDN = 0,
- .SYSLV_ENSHDN = 1,
- },
- },
-};
-
-static struct rt5025_irq_data rt5025_irq_data = {
- .irq_enable1 = {
- .bitfield = {
- .BATABS = 0,
- .INUSB_PLUGIN = 1,
- .INUSBOVP = 1,
- .INAC_PLUGIN = 1,
- .INACOVP = 1,
- },
- },
- .irq_enable2 = {
- .bitfield = {
- .CHTERMI = 1,
- .CHBATOVI = 1,
- .CHGOODI_INUSB = 0,
- .CHBADI_INUSB = 0,
- .CHSLPI_INUSB = 1,
- .CHGOODI_INAC = 0,
- .CHBADI_INAC = 0,
- .CHSLPI_INAC = 1,
- },
- },
- .irq_enable3 = {
- .bitfield = {
- .TIMEOUT_CC = 0,
- .TIMEOUT_PC = 0,
- .CHVSREGI = 0,
- .CHTREGI = 0,
- .CHRCHGI = 1,
- },
- },
- .irq_enable4 = {
- .bitfield = {
- .SYSLV = 0,
- .DCDC4LVHV = 0,
- .PWRONLP = 0,
- .PWRONSP = 0,
- .DCDC3LV = 0,
- .DCDC2LV = 0,
- .DCDC1LV = 0,
- .OT = 1,
- },
- },
- .irq_enable5 = {
- .bitfield = {
- .GPIO0_IE = 0,
- .GPIO1_IE = 0,
- .GPIO2_IE = 0,
- .RESETB = 1,
- .PWRONF = 0,
- .PWRONR = 0,
- .KPSHDN = 1,
- },
- },
-};
-
-//temp unit: 'c*10 degree
-static int jeita_temp[4] = { 0, 150, 500, 600};
- //-5', 5', 10', 20', 45' 55' 55', 65'
-static u8 jeita_scalar[8] = { 0x30, 0x2B, 0x28, 0x22, 0x15, 0x10, 0x10, 0x0D };
-//cc unit: xxx mA
-static int jeita_temp_cc[][5] = {{ 500, 500, 500, 500, 500}, // not plugin
- { 0 , 500, 500, 500, 0}, // normal USB
- { 0, 1000, 2000, 1000, 0}, // USB charger
- { 0, 1000, 2000, 1000, 0}}; // AC Adapter
-//cv unit: xxx mV
-static int jeita_temp_cv[][5] = {{ 4200, 4200, 4200, 4200, 4200}, // not plugin
- { 4200, 4200, 4200, 4200, 4200}, // normal USB
- { 4200, 4200, 4200, 4200, 4200}, // USB charger
- { 4200, 4200, 4200, 4200, 4200}}; // AC Adapter
-
-static struct rt5025_jeita_data rt5025_jeita_data = {
- .temp = jeita_temp,
- .temp_scalar = jeita_scalar,
- .temp_cc = jeita_temp_cc,
- .temp_cv = jeita_temp_cv,
-};
-
-static void rt5025_charger_event_callback(uint32_t detected)
-{
- RTINFO("charger event detected = 0x%08x\n", detected);
- if (detected & CHG_EVENT_CHTERMI)
- {
- pr_info("charger termination OK\n");
- }
-}
-
-static void rt5025_power_event_callback(uint32_t detected)
-{
- RTINFO("power event detected = 0x%08x\n", detected);
-}
-
-static struct rt5025_event_callback rt5025_event_callback = {
- .charger_event_callback = rt5025_charger_event_callback,
- .power_event_callkback = rt5025_power_event_callback,
-};
-
-static struct rt5025_platform_data rt5025_data = {
- .pre_init=rt5025_pre_init,
- .post_init=rt5025_post_init,
- .regulator = {
- &rt5025_dcdc1_info,
- &rt5025_dcdc2_info,
- &rt5025_dcdc3_info,
- &rt5025_dcdc4_info,
- &rt5025_ldo1_info,
- &rt5025_ldo2_info,
- &rt5025_ldo3_info,
- &rt5025_ldo4_info,
- &rt5025_ldo5_info,
- &rt5025_ldo6_info,
- },
- .power_data = &rt5025_power_data,
- .gpio_data = &rt5025_gpio_data,
- .misc_data = &rt5025_misc_data,
- .irq_data = &rt5025_irq_data,
- .jeita_data = &rt5025_jeita_data,
- .cb = &rt5025_event_callback,
- .intr_pin = 81, //GPIO81
-};
-
-void __sramfunc board_pmu_rt5025_suspend(void)
-{
-}
-void __sramfunc board_pmu_rt5025_resume(void)
-{
-}
-
-
-#endif
-
-
-
-
+++ /dev/null
-#include <linux/regulator/machine.h>
-#include <linux/i2c/twl.h>
-#include <linux/mfd/tps65910.h>
-#include <mach/sram.h>
-#include <linux/platform_device.h>
-
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-
-#ifdef CONFIG_MFD_TPS65910
-
-extern int platform_device_register(struct platform_device *pdev);
-
-int tps65910_pre_init(struct tps65910 *tps65910){
-
- int val = 0;
- int err = -1;
-
- printk("%s,line=%d\n", __func__,__LINE__);
-
- #ifdef CONFIG_RK_CONFIG
- if(sram_gpio_init(get_port_config(pmic_slp).gpio, &pmic_sleep) < 0){
- printk(KERN_ERR "sram_gpio_init failed\n");
- return -EINVAL;
- }
- if(port_output_init(pmic_slp, 0, "pmic_slp") < 0){
- printk(KERN_ERR "port_output_init failed\n");
- return -EINVAL;
- }
- #else
- if(sram_gpio_init(PMU_POWER_SLEEP, &pmic_sleep) < 0){
- printk(KERN_ERR "sram_gpio_init failed\n");
- return -EINVAL;
- }
-
- gpio_request(PMU_POWER_SLEEP, "NULL");
- gpio_direction_output(PMU_POWER_SLEEP, GPIO_LOW);
- #endif
-
-#if 0
- /*************set vdd11 (pll) voltage 1.0v********************/
- val = tps65910_reg_read(tps65910, TPS65910_VDIG2);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_VDIG2 reg\n");
- return val;
- }
- val &= (~(0x3<<2));
- err = tps65910_reg_write(tps65910, TPS65910_VDIG2, val);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_VDIG2 reg\n");
- return err;
- }
- /****************************************/
-#endif
- val = tps65910_reg_read(tps65910, TPS65910_DEVCTRL2);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_DEVCTRL2 reg\n");
- return val;
- }
- /* Set sleep state active high and allow device turn-off after PWRON long press */
- val |= (DEVCTRL2_SLEEPSIG_POL_MASK | DEVCTRL2_PWON_LP_OFF_MASK);
-
- err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL2, val);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_DEVCTRL2 reg\n");
- return err;
- }
-
- #if 1
- /* set PSKIP=0 */
- val = tps65910_reg_read(tps65910, TPS65910_DCDCCTRL);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
- return val;
- }
-
- val &= ~DEVCTRL_DEV_OFF_MASK;
- val &= ~DEVCTRL_DEV_SLP_MASK;
- err = tps65910_reg_write(tps65910, TPS65910_DCDCCTRL, val);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_DCDCCTRL reg\n");
- return err;
- }
- #endif
- /* Set the maxinum load current */
- /* VDD1 */
- val = tps65910_reg_read(tps65910, TPS65910_VDD1);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_VDD1 reg\n");
- return val;
- }
-
- val |= (1<<5); //when 1: 1.5 A
- val &= (~(0x3 <<2));
- val |= (0x01<<2); //TSTEP[3:2] = 01 : 12.5 mV/us(sampling 3 Mhz)
- err = tps65910_reg_write(tps65910, TPS65910_VDD1, val);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_VDD1 reg\n");
- return err;
- }
-
- /* VDD2 */
- val = tps65910_reg_read(tps65910, TPS65910_VDD2);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_VDD2 reg\n");
- return val;
- }
-
- val |= (1<<5); //when 1: 1.5 A
- val &= (~(0x3 <<2));
- val |= (0x01<<2); //TSTEP[3:2] = 01 : 12.5 mV/us(sampling 3 Mhz)
- err = tps65910_reg_write(tps65910, TPS65910_VDD2, val);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_VDD2 reg\n");
- return err;
- }
-
- /* VIO */
- val = tps65910_reg_read(tps65910, TPS65910_VIO);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_VIO reg\n");
- return -EIO;
- }
-
- val |= (1<<6); //when 01: 1.0 A
- err = tps65910_reg_write(tps65910, TPS65910_VIO, val);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_VIO reg\n");
- return err;
- }
- #if 1
- /* Mask ALL interrupts */
- err = tps65910_reg_write(tps65910,TPS65910_INT_MSK, 0xFF);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_INT_MSK reg\n");
- return err;
- }
-
- err = tps65910_reg_write(tps65910, TPS65910_INT_MSK2, 0x03);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_INT_MSK2 reg\n");
- return err;
- }
-
- /* Set RTC Power, disable Smart Reflex in DEVCTRL_REG */
- #if 1
- val = 0;
- val |= (DEVCTRL_SR_CTL_I2C_SEL_MASK);
- err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL, val);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_DEVCTRL reg\n");
- return err;
- }
- printk(KERN_INFO "TPS65910 Set default voltage.\n");
- #endif
- #if 0
- //read sleep control register for debug
- for(i=0; i<6; i++)
- {
- err = tps65910_reg_read(tps65910, &val, TPS65910_DEVCTRL+i);
- if (err) {
- printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
- return -EIO;
- }
- else
- printk("%s.......is 0x%04x\n",__FUNCTION__,val);
- }
- #endif
-
- #if 1
- //sleep control register
- /*set func when in sleep mode */
- val = tps65910_reg_read(tps65910, TPS65910_DEVCTRL);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
- return val;
- }
-
- val |= (1 << 1);
- err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL, val);
- if (err) {
- printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
- \n", TPS65910_VDIG1);
- return err;
- }
-
- /* open ldo when in sleep mode */
- val = tps65910_reg_read(tps65910, TPS65910_SLEEP_KEEP_LDO_ON);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
- return val;
- }
-
- val &= 0;
- err = tps65910_reg_write(tps65910, TPS65910_SLEEP_KEEP_LDO_ON, val);
- if (err) {
- printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
- \n", TPS65910_VDIG1);
- return err;
- }
-
- /*set dc mode when in sleep mode */
- val = tps65910_reg_read(tps65910, TPS65910_SLEEP_KEEP_RES_ON);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
- return val;
- }
-
- val |= 0xff;
- val &= ~(0x07); //set vdd1 vdd2 vio in pfm mode when in sleep
- err = tps65910_reg_write(tps65910, TPS65910_SLEEP_KEEP_RES_ON, val);
- if (err) {
- printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
- \n", TPS65910_VDIG1);
- return err;
- }
-
- /*close ldo when in sleep mode */
- val = tps65910_reg_read(tps65910, TPS65910_SLEEP_SET_LDO_OFF);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
- return val;
- }
-#if defined ( CONFIG_ARCH_RK3026)
- val |= 0x2b;
-#else
- val |= 0x0b;
-#endif
- err = tps65910_reg_write(tps65910, TPS65910_SLEEP_SET_LDO_OFF, val);
- if (err) {
- printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
- \n", TPS65910_VDIG1);
- return err;
- }
- #endif
- #if 0
- //read sleep control register for debug
- for(i=0; i<6; i++)
- {
- err = tps65910_reg_read(tps65910, &val, TPS65910_DEVCTRL+i);
- if (err) {
- printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
- return -EIO;
- }
- else
- printk("%s.......is 0x%4x\n",__FUNCTION__,val);
- }
- #endif
- #endif
-
- /*****************set arm and logic (dc1&dc2)in pwm ****************/
- val = tps65910_reg_read(tps65910, TPS65910_DCDCCTRL);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
- return val;
- }
-
- val &= ~(3<<4);
- err = tps65910_reg_write(tps65910, TPS65910_DCDCCTRL, val);
- if (err) {
- printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
- \n", TPS65910_VDIG1);
- return err;
- }
- /************************************************/
-
- printk("%s,line=%d\n", __func__,__LINE__);
- return 0;
-
-}
-int tps65910_post_init(struct tps65910 *tps65910)
-{
- struct regulator *dcdc;
- struct regulator *ldo;
- int i=0;
- printk("%s,line=%d\n", __func__,__LINE__);
-
- g_pmic_type = PMIC_TYPE_TPS65910;
- printk("%s:g_pmic_type=%d\n",__func__,g_pmic_type);
-
- #ifdef CONFIG_RK30_PWM_REGULATOR
- platform_device_register(&pwm_regulator_device[0]);
- #endif
-
- for(i = 0; i < ARRAY_SIZE(tps65910_dcdc_info); i++)
- {
- dcdc =regulator_get(NULL, tps65910_dcdc_info[i].name);
- regulator_set_voltage(dcdc, tps65910_dcdc_info[i].min_uv, tps65910_dcdc_info[i].max_uv);
- regulator_enable(dcdc);
- printk("%s %s =%dmV end\n", __func__,tps65910_dcdc_info[i].name, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
- }
-
- for(i = 0; i < ARRAY_SIZE(tps65910_ldo_info); i++)
- {
- ldo =regulator_get(NULL, tps65910_ldo_info[i].name);
- regulator_set_voltage(ldo, tps65910_ldo_info[i].min_uv, tps65910_ldo_info[i].max_uv);
- regulator_enable(ldo);
- //printk("%s %s =%dmV end\n", __func__,tps65910_dcdc_info[i].name, regulator_get_voltage(ldo));
- regulator_put(ldo);
- }
-
- printk("%s,line=%d END\n", __func__,__LINE__);
-
- return 0;
-}
-
-static struct regulator_consumer_supply tps65910_smps1_supply[] = {
- {
- .supply = "vdd1",
- },
- #if defined(CONFIG_SOC_RK3168) || defined(CONFIG_ARCH_RK3188) || defined(CONFIG_SOC_RK3028) ||defined(CONFIG_MACH_RK3028A_86V)||defined(CONFIG_MACH_RK3028A_FAC)
-
- {
- .supply = "vdd_core",
- },
- #else
- {
- .supply = "vdd_cpu",
- },
- #endif
-};
-static struct regulator_consumer_supply tps65910_smps2_supply[] = {
- {
- .supply = "vdd2",
- },
- #if defined(CONFIG_MACH_RK3168_86V) || defined(CONFIG_SOC_RK3028)||defined(CONFIG_MACH_RK3168_FAC) ||defined(CONFIG_MACH_RK3028A_86V)||defined(CONFIG_MACH_RK3028A_FAC)
-
- {
- .supply = "vdd_cpu",
- },
- #elif (defined(CONFIG_MACH_RK3026_86V)||defined(CONFIG_MACH_RK3026_86V_FAC))
- {
- .supply = "vdd_core",
- },
- #endif
-};
-static struct regulator_consumer_supply tps65910_smps3_supply[] = {
- {
- .supply = "vdd3",
- },
-};
-static struct regulator_consumer_supply tps65910_smps4_supply[] = {
- {
- .supply = "vio",
- },
-};
-static struct regulator_consumer_supply tps65910_ldo1_supply[] = {
- {
- .supply = "vdig1",
- },
-};
-static struct regulator_consumer_supply tps65910_ldo2_supply[] = {
- {
- .supply = "vdig2",
- },
-};
-
-static struct regulator_consumer_supply tps65910_ldo3_supply[] = {
- {
- .supply = "vaux1",
- },
-};
-static struct regulator_consumer_supply tps65910_ldo4_supply[] = {
- {
- .supply = "vaux2",
- },
-};
-static struct regulator_consumer_supply tps65910_ldo5_supply[] = {
- {
- .supply = "vaux33",
- },
-};
-static struct regulator_consumer_supply tps65910_ldo6_supply[] = {
- {
- .supply = "vmmc",
- },
-};
-static struct regulator_consumer_supply tps65910_ldo7_supply[] = {
- {
- .supply = "vdac",
- },
-};
-
-static struct regulator_consumer_supply tps65910_ldo8_supply[] = {
- {
- .supply = "vpll",
- },
-};
-
-static struct regulator_init_data tps65910_smps1 = {
- .constraints = {
- .name = "VDD1",
- .min_uV = 600000,
- .max_uV = 1500000,
- .apply_uV = 1,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_smps1_supply),
- .consumer_supplies = tps65910_smps1_supply,
-};
-
-/* */
-static struct regulator_init_data tps65910_smps2 = {
- .constraints = {
- .name = "VDD2",
- .min_uV = 600000,
- .max_uV = 1500000,
- .apply_uV = 1,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_smps2_supply),
- .consumer_supplies = tps65910_smps2_supply,
-};
-
-/* */
-static struct regulator_init_data tps65910_smps3 = {
- .constraints = {
- .name = "VDD3",
- .min_uV = 1000000,
- .max_uV = 1400000,
- .apply_uV = 1,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_smps3_supply),
- .consumer_supplies = tps65910_smps3_supply,
-};
-
-static struct regulator_init_data tps65910_smps4 = {
- .constraints = {
- .name = "VIO",
- .min_uV = 1800000,
- .max_uV = 3300000,
- .apply_uV = 1,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_smps4_supply),
- .consumer_supplies = tps65910_smps4_supply,
-};
-static struct regulator_init_data tps65910_ldo1 = {
- .constraints = {
- .name = "VDIG1",
- .min_uV = 1200000,
- .max_uV = 2700000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo1_supply),
- .consumer_supplies = tps65910_ldo1_supply,
-};
-
-/* */
-static struct regulator_init_data tps65910_ldo2 = {
- .constraints = {
- .name = "VDIG2",
- .min_uV = 1000000,
- .max_uV = 1800000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo2_supply),
- .consumer_supplies = tps65910_ldo2_supply,
-};
-
-/* */
-static struct regulator_init_data tps65910_ldo3 = {
- .constraints = {
- .name = "VAUX1",
- .min_uV = 1800000,
- .max_uV = 3300000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo3_supply),
- .consumer_supplies = tps65910_ldo3_supply,
-};
-
-/* */
-static struct regulator_init_data tps65910_ldo4 = {
- .constraints = {
- .name = "VAUX2",
- .min_uV = 1800000,
- .max_uV = 3300000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo4_supply),
- .consumer_supplies = tps65910_ldo4_supply,
-};
-
-/* */
-static struct regulator_init_data tps65910_ldo5 = {
- .constraints = {
- .name = "VAUX33",
- .min_uV = 1800000,
- .max_uV = 3300000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo5_supply),
- .consumer_supplies = tps65910_ldo5_supply,
-};
-
-/* */
-static struct regulator_init_data tps65910_ldo6 = {
- .constraints = {
- .name = "VMMC",
- .min_uV = 1800000,
- .max_uV = 3300000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo6_supply),
- .consumer_supplies = tps65910_ldo6_supply,
-};
-
-/* */
-static struct regulator_init_data tps65910_ldo7 = {
- .constraints = {
- .name = "VDAC",
- .min_uV = 1800000,
- .max_uV = 2850000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo7_supply),
- .consumer_supplies = tps65910_ldo7_supply,
-};
-
-/* */
-static struct regulator_init_data tps65910_ldo8 = {
- .constraints = {
- .name = "VPLL",
- .min_uV = 1000000,
- .max_uV = 2500000,
- .apply_uV = 1,
-// .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo8_supply),
- .consumer_supplies = tps65910_ldo8_supply,
-};
-
-void __sramfunc board_pmu_tps65910_suspend(void)
-{
- #ifdef CONFIG_CLK_SWITCH_TO_32K
- sram_gpio_set_value(pmic_sleep, GPIO_HIGH);
- #endif
-}
-void __sramfunc board_pmu_tps65910_resume(void)
-{
- #ifdef CONFIG_CLK_SWITCH_TO_32K
- sram_gpio_set_value(pmic_sleep, GPIO_LOW);
- sram_32k_udelay(10000);
- #endif
-}
-static struct tps65910_board tps65910_data = {
- .irq = (unsigned)TPS65910_HOST_IRQ,
- .irq_base = IRQ_BOARD_BASE,
- .gpio_base = TPS65910_GPIO_EXPANDER_BASE,
-
- .pre_init = tps65910_pre_init,
- .post_init = tps65910_post_init,
-
- //TPS65910_NUM_REGS = 13
- // Regulators
- .tps65910_pmic_init_data[TPS65910_REG_VRTC] = NULL,
- .tps65910_pmic_init_data[TPS65910_REG_VIO] = &tps65910_smps4,
- .tps65910_pmic_init_data[TPS65910_REG_VDD1] = &tps65910_smps1,
- .tps65910_pmic_init_data[TPS65910_REG_VDD2] = &tps65910_smps2,
- .tps65910_pmic_init_data[TPS65910_REG_VDD3] = &tps65910_smps3,
- .tps65910_pmic_init_data[TPS65910_REG_VDIG1] = &tps65910_ldo1,
- .tps65910_pmic_init_data[TPS65910_REG_VDIG2] = &tps65910_ldo2,
- .tps65910_pmic_init_data[TPS65910_REG_VPLL] = &tps65910_ldo8,
- .tps65910_pmic_init_data[TPS65910_REG_VDAC] = &tps65910_ldo7,
- .tps65910_pmic_init_data[TPS65910_REG_VAUX1] = &tps65910_ldo3,
- .tps65910_pmic_init_data[TPS65910_REG_VAUX2] = &tps65910_ldo4,
- .tps65910_pmic_init_data[TPS65910_REG_VAUX33] = &tps65910_ldo5,
- .tps65910_pmic_init_data[TPS65910_REG_VMMC] = &tps65910_ldo6,
-
-
-};
-
-#endif
-
+++ /dev/null
-#include <linux/regulator/machine.h>
-#include <linux/mfd/wm831x/pdata.h>
-#include <linux/mfd/wm831x/core.h>
-#include <linux/mfd/wm831x/gpio.h>
-#include <linux/mfd/wm831x/pmu.h>
-
-#include <mach/sram.h>
-#include <linux/earlysuspend.h>
-
-
-/* wm8326 pmu*/
-#if defined(CONFIG_GPIO_WM831X)
-static struct rk29_gpio_expander_info wm831x_gpio_settinginfo[] = {
- {
- .gpio_num = WM831X_P01, // tp3
- .pin_type = GPIO_OUT,
- .pin_value = GPIO_LOW,
- },
- {
- .gpio_num = WM831X_P02, //tp4
- .pin_type = GPIO_IN,
- },
- {
- .gpio_num = WM831X_P03, //tp2
- .pin_type = GPIO_OUT,
- .pin_value = GPIO_HIGH,
- },
- {
- .gpio_num = WM831X_P04, //tp1
- .pin_type = GPIO_IN,
- },
- {
- .gpio_num = WM831X_P05, //tp1
- .pin_type = GPIO_IN,
- },
- {
- .gpio_num = WM831X_P06, //tp1
- .pin_type = GPIO_OUT,
- .pin_value = GPIO_HIGH,
- },
- {
- .gpio_num = WM831X_P07, //tp1
- .pin_type = GPIO_IN,
- },
- {
- .gpio_num = WM831X_P08, //tp1
- .pin_type = GPIO_OUT,
- .pin_value = GPIO_HIGH,
- },
- {
- .gpio_num = WM831X_P09, //tp1
- .pin_type = GPIO_OUT,
- .pin_value = GPIO_HIGH,
- },
- {
- .gpio_num = WM831X_P10, //tp1
- .pin_type = GPIO_IN,
- },
- {
- .gpio_num = WM831X_P11, //tp1
- .pin_type = GPIO_OUT,
- .pin_value = GPIO_HIGH,
- },
- {
- .gpio_num = WM831X_P12,
- .pin_type = GPIO_OUT,
- .pin_value = GPIO_HIGH,
- },
-};
-#endif
-
-#if defined(CONFIG_MFD_WM831X)
-
-#define UNLOCK_SECURITY_KEY ~(0x1<<5)
-#define LOCK_SECURITY_KEY 0x00
-
-static struct wm831x *Wm831x;
-
-static int wm831x_pre_init(struct wm831x *parm)
-{
- int ret;
- Wm831x = parm;
- printk("%s\n", __func__);
-
- #ifdef CONFIG_RK_CONFIG
- if(sram_gpio_init(get_port_config(pmic_slp).gpio, &pmic_sleep) < 0){
- printk(KERN_ERR "sram_gpio_init failed\n");
- return -EINVAL;
- }
- if(port_output_init(pmic_slp, 0, "pmic_slp") < 0){
- printk(KERN_ERR "port_output_init failed\n");
- return -EINVAL;
- }
- #else
- if(sram_gpio_init(PMU_POWER_SLEEP, &pmic_sleep) < 0){
- printk(KERN_ERR "sram_gpio_init failed\n");
- return -EINVAL;
- }
-
- gpio_request(PMU_POWER_SLEEP, "NULL");
- gpio_direction_output(PMU_POWER_SLEEP, GPIO_LOW);
- #endif
-
- #ifdef CONFIG_WM8326_VBAT_LOW_DETECTION
- #ifdef CONFIG_BATTERY_RK30_VOL3V8
- wm831x_set_bits(parm,WM831X_SYSVDD_CONTROL ,0xc077,0xc035); //pvdd power on dect vbat voltage
- printk("+++The vbat is too low+++\n");
- #endif
- #endif
-
- ret = wm831x_reg_read(parm, WM831X_POWER_STATE) & 0xffff;
- wm831x_reg_write(parm, WM831X_POWER_STATE, (ret & 0xfff8) | 0x04);
-
- wm831x_set_bits(parm, WM831X_RTC_CONTROL, WM831X_RTC_ALAM_ENA_MASK, 0x0400);//enable rtc alam
- //BATT_FET_ENA = 1
- wm831x_reg_write(parm, WM831X_SECURITY_KEY, 0x9716); // unlock security key
- wm831x_set_bits(parm, WM831X_RESET_CONTROL, 0x1003, 0x1001);
- ret = wm831x_reg_read(parm, WM831X_RESET_CONTROL) & 0xffff & UNLOCK_SECURITY_KEY; // enternal reset active in sleep
-// printk("%s:WM831X_RESET_CONTROL=0x%x\n", __func__, ret);
- wm831x_reg_write(parm, WM831X_RESET_CONTROL, ret);
-
- wm831x_set_bits(parm,WM831X_DC1_ON_CONFIG ,0x0300,0x0000); //set dcdc mode is FCCM
- wm831x_set_bits(parm,WM831X_DC2_ON_CONFIG ,0x0300,0x0000);
- wm831x_set_bits(parm,WM831X_DC3_ON_CONFIG ,0x0300,0x0000);
- wm831x_set_bits(parm,0x4066,0x0300,0x0000);
-
-#ifndef CONFIG_MACH_RK3066_SDK
- wm831x_set_bits(parm,WM831X_LDO10_CONTROL ,0x0040,0x0040);// set ldo10 in switch mode
-#endif
- wm831x_set_bits(parm,WM831X_STATUS_LED_1 ,0xc300,0xc100);// set led1 on(in manual mode)
- wm831x_set_bits(parm,WM831X_STATUS_LED_2 ,0xc300,0xc000);//set led2 off(in manual mode)
-
- wm831x_set_bits(parm,WM831X_LDO5_SLEEP_CONTROL ,0xe000,0x2000);// set ldo5 is disable in sleep mode
- wm831x_set_bits(parm,WM831X_LDO1_SLEEP_CONTROL ,0xe000,0x2000);// set ldo1 is disable in sleep mode
-
- wm831x_reg_write(parm, WM831X_SECURITY_KEY, LOCK_SECURITY_KEY); // lock security key
-
- return 0;
-}
-static int wm831x_mask_interrupt(struct wm831x *Wm831x)
-{
- /**************************clear interrupt********************/
- wm831x_reg_write(Wm831x,WM831X_INTERRUPT_STATUS_1,0xffff);
- wm831x_reg_write(Wm831x,WM831X_INTERRUPT_STATUS_2,0xffff);
- wm831x_reg_write(Wm831x,WM831X_INTERRUPT_STATUS_3,0xffff);
- wm831x_reg_write(Wm831x,WM831X_INTERRUPT_STATUS_4,0xffff);
- wm831x_reg_write(Wm831x,WM831X_INTERRUPT_STATUS_5,0xffff);
-
- wm831x_reg_write(Wm831x,WM831X_SYSTEM_INTERRUPTS_MASK,0xbedc); //mask interrupt which not used
- return 0;
- /*****************************************************************/
-}
-
-#ifdef CONFIG_WM8326_VBAT_LOW_DETECTION
-static int wm831x_low_power_detection(struct wm831x *wm831x)
-{
- #ifdef CONFIG_BATTERY_RK30_VOL3V8
- wm831x_reg_write(wm831x,WM831X_SYSTEM_INTERRUPTS_MASK,0xbe5c);
- wm831x_set_bits(wm831x,WM831X_INTERRUPT_STATUS_1_MASK,0x8000,0x0000);
- wm831x_set_bits(wm831x,WM831X_SYSVDD_CONTROL ,0xc077,0x0035); //set pvdd low voltage is 3.1v hi voltage is 3.3v
- #else
- wm831x_reg_write(wm831x,WM831X_AUXADC_CONTROL,0x803f); //open adc
- wm831x_reg_write(wm831x,WM831X_AUXADC_CONTROL,0xd03f);
- wm831x_reg_write(wm831x,WM831X_AUXADC_SOURCE,0x0001);
-
- wm831x_reg_write(wm831x,WM831X_COMPARATOR_CONTROL,0x0001);
- wm831x_reg_write(wm831x,WM831X_COMPARATOR_1,0x2844); //set the low power is 3.1v
-
- wm831x_reg_write(wm831x,WM831X_INTERRUPT_STATUS_1_MASK,0x99ee);
- wm831x_set_bits(wm831x,WM831X_SYSTEM_INTERRUPTS_MASK,0x0100,0x0000);
- if (wm831x_reg_read(wm831x,WM831X_AUXADC_DATA)< 0x1844){
- printk("The vbat is too low.\n");
- wm831x_device_shutdown(wm831x);
- }
- #endif
- return 0;
-}
-#endif
-
-#define AVS_BASE 172
-int wm831x_post_init(struct wm831x *Wm831x)
-{
- struct regulator *dcdc;
- struct regulator *ldo;
- int i = 0;
-
- g_pmic_type = PMIC_TYPE_WM8326;
- printk("%s:g_pmic_type=%d\n",__func__,g_pmic_type);
-
- for(i = 0; i < ARRAY_SIZE(wm8326_dcdc_info); i++)
- {
- dcdc =regulator_get(NULL, wm8326_dcdc_info[i].name);
- regulator_set_voltage(dcdc, wm8326_dcdc_info[i].min_uv, wm8326_dcdc_info[i].max_uv);
- regulator_set_suspend_voltage(dcdc, wm8326_dcdc_info[i].suspend_vol);
- regulator_enable(dcdc);
- printk("%s %s =%dmV end\n", __func__,wm8326_dcdc_info[i].name, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
- }
-
- for(i = 0; i < ARRAY_SIZE(wm8326_ldo_info); i++)
- {
- ldo =regulator_get(NULL, wm8326_ldo_info[i].name);
- regulator_set_voltage(ldo, wm8326_ldo_info[i].min_uv, wm8326_ldo_info[i].max_uv);
- regulator_set_suspend_voltage(ldo, wm8326_ldo_info[i].suspend_vol);
- regulator_enable(ldo);
- //printk("%s %s =%dmV end\n", __func__,tps65910_dcdc_info[i].name, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
- }
-
- wm831x_mask_interrupt(Wm831x);
-
- #ifdef CONFIG_WM8326_VBAT_LOW_DETECTION
- wm831x_low_power_detection(Wm831x);
- #endif
-
- printk("wm831x_post_init end");
- return 0;
-}
-
-static int wm831x_last_deinit(struct wm831x *Wm831x)
-{
- struct regulator *ldo;
-
- printk("%s\n", __func__);
- ldo = regulator_get(NULL, "ldo1");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo2");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo3");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo4");
- //regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo5");
-// regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo6");
-// regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo7");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo8");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo9");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo10");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- return 0;
-}
-
-struct wm831x_status_pdata wm831x_status_platdata[WM831X_MAX_STATUS] = {
- {
- .default_src = WM831X_STATUS_OTP,
- .name = "wm831x_status0",
- .default_trigger = "wm831x_otp",
- },
- {
- .default_src = WM831X_STATUS_POWER,
- .name = "wm831x_status1",
- .default_trigger = "wm831x_power",
- },
-};
-
-static struct regulator_consumer_supply dcdc1_consumers[] = {
- {
- .supply = "vdd_core",
- }
-};
-
-static struct regulator_consumer_supply dcdc2_consumers[] = {
- {
- .supply = "vdd_cpu",
- }
-
-};
-
-static struct regulator_consumer_supply dcdc3_consumers[] = {
- {
- .supply = "dcdc3",
- }
-};
-
-static struct regulator_consumer_supply dcdc4_consumers[] = {
- {
- .supply = "dcdc4",
- }
-};
-
-#if 0
-static struct regulator_consumer_supply epe1_consumers[] = {
- {
- .supply = "epe1",
- }
-};
-
-static struct regulator_consumer_supply epe2_consumers[] = {
- {
- .supply = "epe2",
- }
-};
-#endif
-
-static struct regulator_consumer_supply ldo1_consumers[] = {
- {
- .supply = "ldo1",
- }
-};
-
-static struct regulator_consumer_supply ldo2_consumers[] = {
- {
- .supply = "ldo2",
- }
-};
-
-static struct regulator_consumer_supply ldo3_consumers[] = {
- {
- .supply = "ldo3",
- }
-};
-
-static struct regulator_consumer_supply ldo4_consumers[] = {
- {
- .supply = "ldo4",
- }
-};
-
-static struct regulator_consumer_supply ldo5_consumers[] = {
- {
- .supply = "ldo5",
- }
-};
-
-static struct regulator_consumer_supply ldo6_consumers[] = {
- {
- .supply = "ldo6",
- }
-};
-
-static struct regulator_consumer_supply ldo7_consumers[] = {
- {
- .supply = "ldo7",
- }
-};
-
-static struct regulator_consumer_supply ldo8_consumers[] = {
- {
- .supply = "ldo8",
- }
-};
-
-static struct regulator_consumer_supply ldo9_consumers[] = {
- {
- .supply = "ldo9",
- }
-};
-
-static struct regulator_consumer_supply ldo10_consumers[] = {
- {
- .supply = "ldo10",
- }
-};
-
-static struct regulator_consumer_supply ldo11_consumers[] = {
- {
- .supply = "ldo11",
- }
-};
-
-struct regulator_init_data wm831x_regulator_init_dcdc[WM831X_MAX_DCDC] = {
- {
- .constraints = {
- .name = "DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL | REGULATOR_MODE_FAST | REGULATOR_MODE_IDLE,
- },
- .num_consumer_supplies = ARRAY_SIZE(dcdc1_consumers),
- .consumer_supplies = dcdc1_consumers,
- },
- {
- .constraints = {
- .name = "DCDC2",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL | REGULATOR_MODE_FAST | REGULATOR_MODE_IDLE,
- },
- .num_consumer_supplies = ARRAY_SIZE(dcdc2_consumers),
- .consumer_supplies = dcdc2_consumers,
- },
- {
- .constraints = {
- .name = "DCDC3",
- .min_uV = 850000,
- .max_uV = 3400000, //0.85-3.4V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL | REGULATOR_MODE_FAST | REGULATOR_MODE_IDLE,
- },
- .num_consumer_supplies = ARRAY_SIZE(dcdc3_consumers),
- .consumer_supplies = dcdc3_consumers,
- },
- {
- .constraints = {
- .name = "DCDC4",
- .min_uV = 850000,
- .max_uV = 3400000, //0.85-3.4V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL | REGULATOR_MODE_FAST | REGULATOR_MODE_IDLE,
- },
- .num_consumer_supplies = ARRAY_SIZE(dcdc4_consumers),
- .consumer_supplies = dcdc4_consumers,
- },
-};
-
-#if 0
-struct regulator_init_data wm831x_regulator_init_epe[WM831X_MAX_EPE] = {
- {
- .constraints = {
- .name = "EPE1",
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(epe1_consumers),
- .consumer_supplies = epe1_consumers,
- },
- {
- .constraints = {
- .name = "EPE2",
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(epe2_consumers),
- .consumer_supplies = epe2_consumers,
- },
-};
-#endif
-
-struct regulator_init_data wm831x_regulator_init_ldo[WM831X_MAX_LDO] = {
- {
- .constraints = {
- .name = "LDO1",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_IDLE | REGULATOR_MODE_NORMAL,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo1_consumers),
- .consumer_supplies = ldo1_consumers,
- },
- {
- .constraints = {
- .name = "LDO2",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_IDLE | REGULATOR_MODE_NORMAL,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
- .consumer_supplies = ldo2_consumers,
- },
- {
- .constraints = {
- .name = "LDO3",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_IDLE | REGULATOR_MODE_NORMAL,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo3_consumers),
- .consumer_supplies = ldo3_consumers,
- },
- {
- .constraints = {
- .name = "LDO4",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_IDLE | REGULATOR_MODE_NORMAL,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo4_consumers),
- .consumer_supplies = ldo4_consumers,
- },
- {
- .constraints = {
- .name = "LDO5",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_IDLE | REGULATOR_MODE_NORMAL,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo5_consumers),
- .consumer_supplies = ldo5_consumers,
- },
- {
- .constraints = {
- .name = "LDO6",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_IDLE | REGULATOR_MODE_NORMAL,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo6_consumers),
- .consumer_supplies = ldo6_consumers,
- },
- {
- .constraints = {
- .name = "LDO7",
- .min_uV = 1000000,
- .max_uV = 3500000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_IDLE | REGULATOR_MODE_NORMAL,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo7_consumers),
- .consumer_supplies = ldo7_consumers,
- },
- {
- .constraints = {
- .name = "LDO8",
- .min_uV = 1000000,
- .max_uV = 3500000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_IDLE | REGULATOR_MODE_NORMAL,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo8_consumers),
- .consumer_supplies = ldo8_consumers,
- },
- {
- .constraints = {
- .name = "LDO9",
- .min_uV = 1000000,
- .max_uV = 3500000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_IDLE | REGULATOR_MODE_NORMAL,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo9_consumers),
- .consumer_supplies = ldo9_consumers,
- },
- {
- .constraints = {
- .name = "LDO10",
- .min_uV = 1000000,
- .max_uV = 3500000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_IDLE | REGULATOR_MODE_NORMAL,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo10_consumers),
- .consumer_supplies = ldo10_consumers,
- },
- {
- .constraints = {
- .name = "LDO11",
- .min_uV = 800000,
- .max_uV = 1550000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_IDLE | REGULATOR_MODE_NORMAL,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo11_consumers),
- .consumer_supplies = ldo11_consumers,
- },
-};
-
-static int wm831x_init_pin_type(struct wm831x *wm831x)
-{
- struct wm831x_pdata *pdata;
- struct rk29_gpio_expander_info *wm831x_gpio_settinginfo;
- uint16_t wm831x_settingpin_num;
- int i;
-
- if (!wm831x || !wm831x->dev)
- goto out;
-
- pdata = wm831x->dev->platform_data;
- if (!pdata)
- goto out;
-
- wm831x_gpio_settinginfo = pdata->settinginfo;
- if (!wm831x_gpio_settinginfo)
- goto out;
-
- wm831x_settingpin_num = pdata->settinginfolen;
- for (i = 0; i < wm831x_settingpin_num; i++) {
- if (wm831x_gpio_settinginfo[i].pin_type == GPIO_IN) {
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_DIR_MASK | WM831X_GPN_TRI_MASK,
- 1 << WM831X_GPN_DIR_SHIFT | 1 << WM831X_GPN_TRI_SHIFT);
- if (i == 1) {
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_POL_MASK,
- 0x0400);
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_FN_MASK,
- 0x0003);
- } // set gpio2 sleep/wakeup
-
- if (i == 9) {
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_PULL_MASK,
- 0x0000); //disable pullup/down
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_PWR_DOM_MASK,
- 0x0800);
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_ENA_MASK,
- 0x0000);
- } //set gpio10 as adc input
-
- } else {
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_DIR_MASK | WM831X_GPN_TRI_MASK,
- 1 << WM831X_GPN_TRI_SHIFT);
- if (wm831x_gpio_settinginfo[i].pin_value == GPIO_HIGH) {
- wm831x_set_bits(wm831x, WM831X_GPIO_LEVEL, 1 << i, 1 << i);
- } else {
- wm831x_set_bits(wm831x, WM831X_GPIO_LEVEL, 1 << i, 0 << i);
- }
- if (i == 2) {
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_PWR_DOM_MASK | WM831X_GPN_POL_MASK |WM831X_GPN_FN_MASK,
- 1 << WM831X_GPN_POL_SHIFT | 1 << WM831X_GPN_PWR_DOM_SHIFT | 1 << 0);
-
- } // set gpio3 as clkout output 32.768K
-
- }
- }
-
-#if 0
- for (i = 0; i < pdata->gpio_pin_num; i++) {
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_PULL_MASK | WM831X_GPN_POL_MASK | WM831X_GPN_OD_MASK | WM831X_GPN_TRI_MASK,
- 1 << WM831X_GPN_POL_SHIFT | 1 << WM831X_GPN_TRI_SHIFT);
-
- ret = wm831x_reg_read(wm831x, WM831X_GPIO1_CONTROL + i);
- printk("Gpio%d Pin Configuration = %x\n", i, ret);
- }
-#endif
-
-out:
- return 0;
-}
-
-#ifdef CONFIG_HAS_EARLYSUSPEND
-void wm831x_pmu_early_suspend(struct early_suspend *h)
-{
- struct regulator *dcdc;
- struct regulator *ldo;
- printk("%s\n", __func__);
-
- dcdc = regulator_get(NULL, "dcdc4"); //vcc_io
- regulator_set_voltage(dcdc, 2800000, 2800000);
- regulator_set_mode(dcdc, REGULATOR_MODE_STANDBY);
- regulator_enable(dcdc);
- printk("%s set dcdc4 vcc_io=%dmV end\n", __func__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo1"); //
- regulator_set_mode(ldo, REGULATOR_MODE_IDLE);
- regulator_enable(ldo);
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo4");
- regulator_set_mode(ldo, REGULATOR_MODE_IDLE);
- regulator_enable(ldo);
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo6");
- regulator_set_mode(ldo, REGULATOR_MODE_IDLE);
- regulator_enable(ldo);
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo8");
- regulator_set_mode(ldo, REGULATOR_MODE_IDLE);
- regulator_enable(ldo);
- regulator_put(ldo);
- udelay(100);
-
-}
-void wm831x_pmu_early_resume(struct early_suspend *h)
-{
- struct regulator *dcdc;
- struct regulator *ldo;
- printk("%s\n", __func__);
-
- dcdc = regulator_get(NULL, "dcdc4"); //vcc_io
- #ifdef CONFIG_MACH_RK3066_SDK
- regulator_set_voltage(dcdc, 3300000, 3300000);
- #else
- regulator_set_voltage(dcdc, 3000000, 3000000);
- #endif
- regulator_set_mode(dcdc, REGULATOR_MODE_FAST);
- regulator_enable(dcdc);
- printk("%s set dcdc4 vcc_io=%dmV end\n", __func__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo1"); //
- regulator_set_mode(ldo, REGULATOR_MODE_NORMAL);
- regulator_enable(ldo);
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo4");
- regulator_set_mode(ldo, REGULATOR_MODE_NORMAL);
- regulator_enable(ldo);
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo6");
- regulator_set_mode(ldo, REGULATOR_MODE_NORMAL);
- regulator_enable(ldo);
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo8");
- regulator_set_mode(ldo, REGULATOR_MODE_NORMAL);
- regulator_enable(ldo);
- regulator_put(ldo);
- udelay(100);
-}
-#else
-void wm831x_pmu_early_suspend(struct regulator_dev *rdev)
-{
-}
-void wm831x_pmu_early_resume(struct regulator_dev *rdev)
-{
-}
-#endif
-
-void __sramfunc board_pmu_wm8326_suspend(void)
-{
- #ifdef CONFIG_CLK_SWITCH_TO_32K
- sram_gpio_set_value(pmic_sleep, GPIO_HIGH);
- #endif
- }
-void __sramfunc board_pmu_wm8326_resume(void)
-{
- #ifdef CONFIG_CLK_SWITCH_TO_32K
- sram_gpio_set_value(pmic_sleep, GPIO_LOW);
- sram_32k_udelay(10000);
- #endif
-}
-static struct wm831x_pdata wm831x_platdata = {
-
- /** Called before subdevices are set up */
- .pre_init = wm831x_pre_init,
- /** Called after subdevices are set up */
- .post_init = wm831x_post_init,
- /** Called before subdevices are power down */
- .last_deinit = wm831x_last_deinit,
-
-#if defined(CONFIG_GPIO_WM831X)
- .gpio_base = WM831X_GPIO_EXPANDER_BASE,
- .gpio_pin_num = WM831X_TOTOL_GPIO_NUM,
- .settinginfo = wm831x_gpio_settinginfo,
- .settinginfolen = ARRAY_SIZE(wm831x_gpio_settinginfo),
- .pin_type_init = wm831x_init_pin_type,
- .irq_base = IRQ_BOARD_BASE,
-#endif
-
- /** LED1 = 0 and so on */
- .status = { &wm831x_status_platdata[0], &wm831x_status_platdata[1] },
-
- /** DCDC1 = 0 and so on */
- .dcdc = {
- &wm831x_regulator_init_dcdc[0],
- &wm831x_regulator_init_dcdc[1],
- &wm831x_regulator_init_dcdc[2],
- &wm831x_regulator_init_dcdc[3],
- },
-
- /** EPE1 = 0 and so on */
- //.epe = { &wm831x_regulator_init_epe[0], &wm831x_regulator_init_epe[1] },
-
- /** LDO1 = 0 and so on */
- .ldo = {
- &wm831x_regulator_init_ldo[0],
- &wm831x_regulator_init_ldo[1],
- &wm831x_regulator_init_ldo[2],
- &wm831x_regulator_init_ldo[3],
- &wm831x_regulator_init_ldo[4],
- &wm831x_regulator_init_ldo[5],
- &wm831x_regulator_init_ldo[6],
- &wm831x_regulator_init_ldo[7],
- &wm831x_regulator_init_ldo[8],
- &wm831x_regulator_init_ldo[9],
- &wm831x_regulator_init_ldo[10],
- },
-};
-#endif
+++ /dev/null
-#include <mach/gpio.h>
-#include <plat/key.h>
-
-#define EV_ENCALL KEY_F4
-#define EV_MENU KEY_F1
-
-#define PRESS_LEV_LOW 1
-#define PRESS_LEV_HIGH 0
-
-static struct rk29_keys_button key_button[] = {
-#if 0
- {
- .desc = "menu",
- .code = EV_MENU,
- .gpio = RK30_PIN6_PA0,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .gpio = RK30_PIN6_PA1,
- .active_low = PRESS_LEV_LOW,
- },
-#endif
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .gpio = RK30_PIN4_PC5,
- .active_low = PRESS_LEV_LOW,
- },
-#if 0
- {
- .desc = "home",
- .code = KEY_HOME,
- .gpio = RK30_PIN6_PA3,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "search",
- .code = KEY_SEARCH,
- .gpio = RK30_PIN6_PA4,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .gpio = RK30_PIN6_PA5,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "sensor",
- .code = KEY_CAMERA,
- .gpio = RK30_PIN6_PA6,
- .active_low = PRESS_LEV_LOW,
- },
-#endif
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK30_PIN6_PA2,
- .active_low = PRESS_LEV_LOW,
- //.code_long_press = EV_ENCALL,
- .wakeup = 1,
- },
-#if 1
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .adc_value = 1,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-#if 0
- {
- .desc = "vol-",
- .code = KEY_VOLUMEUP,
- .adc_value = 249,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-#endif
- {
- .desc = "menu",
- .code = EV_MENU,
- .adc_value = 135,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .adc_value = 498,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .adc_value = 333,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-#if 0
- {
- .desc = "camera",
- .code = KEY_CAMERA,
- .adc_value = 827,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-#endif
-#endif
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = 1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
+++ /dev/null
-/*
- * Copyright (C) 2010 ROCKCHIP, Inc.
- * Author: roger_chen <cz@rock-chips.com>
- *
- * This program is the bluetooth device bcm4329's driver,
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/module.h>
-#include <linux/device.h>
-#include <linux/rfkill.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/interrupt.h>
-#include <linux/wakelock.h>
-#include <linux/fs.h>
-#include <asm/uaccess.h>
-#include <mach/gpio.h>
-#include <asm/irq.h>
-#include <mach/iomux.h>
-#include <linux/wakelock.h>
-#include <linux/timer.h>
-#include <mach/board.h>
-
-#if 0
-#define DBG(x...) printk(KERN_INFO "[BT_RFKILL]: "x)
-#else
-#define DBG(x...)
-#endif
-
-#define LOG(x...) printk(KERN_INFO "[BT_RFKILL]: "x)
-
-#ifdef CONFIG_BCM4329
-#define WIFI_BT_POWER_TOGGLE 1
-#else
-#define WIFI_BT_POWER_TOGGLE 0
-#endif
-
-#define BT_WAKE_LOCK_TIMEOUT 10 //s
-
-#define BT_AUTO_SLEEP_TIMEOUT 3
-
-/*
- * IO Configuration for RK29
- */
-#ifdef CONFIG_ARCH_RK29
-
-#define BT_WAKE_HOST_SUPPORT 0
-
-/* IO configuration */
-// BT power pin
-#define BT_GPIO_POWER RK29_PIN5_PD6
-#define IOMUX_BT_GPIO_POWER() rk29_mux_api_set(GPIO5D6_SDMMC1PWREN_NAME, GPIO5H_GPIO5D6);
-
-// BT reset pin
-#define BT_GPIO_RESET RK29_PIN6_PC4
-#define IOMUX_BT_GPIO_RESET()
-
-// BT wakeup pin
-#define BT_GPIO_WAKE_UP RK29_PIN6_PC5
-#define IOMUX_BT_GPIO_WAKE_UP()
-
-// BT wakeup host pin
-#define BT_GPIO_WAKE_UP_HOST
-#define IOMUX_BT_GPIO_WAKE_UP_HOST()
-
-//bt cts paired to uart rts
-#define UART_RTS RK29_PIN2_PA7
-#define IOMUX_UART_RTS_GPIO() rk29_mux_api_set(GPIO2A7_UART2RTSN_NAME, GPIO2L_GPIO2A7)
-#define IOMUX_UART_RTS() rk29_mux_api_set(GPIO2A7_UART2RTSN_NAME, GPIO2L_UART2_RTS_N)
-
-/*
- * IO Configuration for RK30
- */
-#elif defined (CONFIG_ARCH_RK30)
-
-#define BT_WAKE_HOST_SUPPORT 1
-
-/* IO configuration */
-// BT power pin
-#define BT_GPIO_POWER RK30_PIN3_PC7
-#define IOMUX_BT_GPIO_POWER() rk30_mux_api_set(GPIO3C7_SDMMC1WRITEPRT_NAME, GPIO3C_GPIO3C7);
-
-// BT reset pin
-#define BT_GPIO_RESET RK30_PIN3_PD1
-#define IOMUX_BT_GPIO_RESET() rk30_mux_api_set(GPIO3D1_SDMMC1BACKENDPWR_NAME, GPIO3D_GPIO3D1);
-
-// BT wakeup pin
-#define BT_GPIO_WAKE_UP RK30_PIN3_PC6
-#define IOMUX_BT_GPIO_WAKE_UP() rk30_mux_api_set(GPIO3C6_SDMMC1DETECTN_NAME, GPIO3C_GPIO3C6);
-
-// BT wakeup host pin
-#define BT_GPIO_WAKE_UP_HOST RK30_PIN6_PA7
-#define BT_IRQ_WAKE_UP_HOST gpio_to_irq(BT_GPIO_WAKE_UP_HOST)
-#define IOMUX_BT_GPIO_WAKE_UP_HOST()
-
-//bt cts paired to uart rts
-#define UART_RTS RK30_PIN1_PA3
-#define IOMUX_UART_RTS_GPIO() rk30_mux_api_set(GPIO1A3_UART0RTSN_NAME, GPIO1A_GPIO1A3)
-#define IOMUX_UART_RTS() rk30_mux_api_set(GPIO1A3_UART0RTSN_NAME, GPIO1A_UART0_RTS_N)
-
-#endif
-
-struct bt_ctrl
-{
- struct rfkill *bt_rfk;
-#if BT_WAKE_HOST_SUPPORT
- struct timer_list tl;
- bool b_HostWake;
- struct wake_lock bt_wakelock;
-#endif
-};
-
-static const char bt_name[] =
-#if defined(CONFIG_RKWIFI)
- #if defined(CONFIG_RKWIFI_26M)
- "rk903_26M"
- #else
- "rk903"
- #endif
-#elif defined(CONFIG_BCM4329)
- "bcm4329"
-#elif defined(CONFIG_MV8787)
- "mv8787"
-#else
- "bt_default"
-#endif
-;
-
-#if WIFI_BT_POWER_TOGGLE
-extern int rk29sdk_bt_power_state;
-extern int rk29sdk_wifi_power_state;
-#endif
-
-struct bt_ctrl gBtCtrl;
-struct timer_list bt_sleep_tl;
-
-
-#if BT_WAKE_HOST_SUPPORT
-void resetBtHostSleepTimer(void)
-{
- mod_timer(&(gBtCtrl.tl),jiffies + BT_WAKE_LOCK_TIMEOUT*HZ);//ÔÙÖØÐÂÉèÖó¬Ê±Öµ¡£
-}
-
-void btWakeupHostLock(void)
-{
- if(gBtCtrl.b_HostWake == false){
- DBG("** Lock **\n");
- wake_lock(&(gBtCtrl.bt_wakelock));
- gBtCtrl.b_HostWake = true;
- }
-}
-
-void btWakeupHostUnlock(void)
-{
- if(gBtCtrl.b_HostWake == true){
- DBG("** UnLock **\n");
- wake_unlock(&(gBtCtrl.bt_wakelock)); //ÈÃϵͳ˯Ãß
- gBtCtrl.b_HostWake = false;
- }
-}
-
-static void timer_hostSleep(unsigned long arg)
-{
- DBG("b_HostWake=%d\n", gBtCtrl.b_HostWake);
- btWakeupHostUnlock();
-}
-
-void bcm4325_sleep(unsigned long bSleep);
-
-#ifdef CONFIG_PM
-static irqreturn_t bcm4329_wake_host_irq(int irq, void *dev)
-{
- DBG("%s\n",__FUNCTION__);
-
- btWakeupHostLock();
- resetBtHostSleepTimer();
- return IRQ_HANDLED;
-}
-
-static void rfkill_do_wakeup(struct work_struct *work)
-{
- // disable bt wakeup host
- DBG("** free irq\n");
- free_irq(BT_IRQ_WAKE_UP_HOST, NULL);
-
- DBG("Enable UART_RTS\n");
- gpio_set_value(UART_RTS, GPIO_LOW);
- IOMUX_UART_RTS();
-}
-
-static DECLARE_DELAYED_WORK(wakeup_work, rfkill_do_wakeup);
-
-static int bcm4329_rfkill_suspend(struct platform_device *pdev, pm_message_t state)
-{
- DBG("%s\n",__FUNCTION__);
-
- cancel_delayed_work(&wakeup_work);
-
-#ifdef CONFIG_BT_AUTOSLEEP
- bcm4325_sleep(1);
-#endif
-
- DBG("Disable UART_RTS\n");
- //To prevent uart to receive bt data when suspended
- IOMUX_UART_RTS_GPIO();
- gpio_request(UART_RTS, "uart_rts");
- gpio_set_value(UART_RTS, GPIO_HIGH);
-
- // enable bt wakeup host
- DBG("Request irq for bt wakeup host\n");
- if (0 == request_irq(BT_IRQ_WAKE_UP_HOST,
- bcm4329_wake_host_irq,
- IRQF_TRIGGER_FALLING,
- "bt_wake",
- NULL))
- enable_irq_wake(BT_IRQ_WAKE_UP_HOST);
- else
- LOG("Failed to request BT_WAKE_UP_HOST irq\n");
-
-#ifdef CONFIG_RFKILL_RESET
- extern void rfkill_set_block(struct rfkill *rfkill, bool blocked);
- rfkill_set_block(gBtCtrl.bt_rfk, true);
-#endif
-
- return 0;
-}
-
-static int bcm4329_rfkill_resume(struct platform_device *pdev)
-{
- DBG("%s\n",__FUNCTION__);
-
- // ϵͳÍ˳ö¶þ¼¶Ë¯ÃߺóÐèÒªÀµÍRTS£¬´Ó¶ø²ÅÔÊÐíBT·¢Êý¾Ý¹ýÀ´
- // µ«ÊÇÄ¿Ç°·¢ÏÖÔÚresumeº¯ÊýÖÐÖ±½ÓÀµÍRTS»áµ¼ÖÂBTÊý¾Ý¶ªÊ§
- // ËùÒÔÑÓ³Ù1sºóÔÙÀµÍRTS
- // ϵͳÍ˳ö¶þ¼¶Ë¯ÃßʱÊͷŵôBT_IRQ_WAKE_UP_HOST£¬ÔÚ˯ÃßʱºòÔÙ
- // ´ÎÉêÇ룬Ŀǰ·¢ÏÖÖжϻص÷º¯Êý±Èresume¸üÍíÖ´ÐУ¬Èç¹ûresume
- // ʱֱ½ÓfreeµôIRQ£¬»áµ¼ÖÂÖжϻص÷º¯Êý²»»á±»Ö´ÐУ¬
- DBG("delay 1s\n");
- schedule_delayed_work(&wakeup_work, HZ);
-
- return 0;
-}
-#else
-#define bcm4329_rfkill_suspend NULL
-#define bcm4329_rfkill_resume NULL
-#endif
-
-#endif
-
-void bcm4325_sleep(unsigned long bSleep)
-{
- DBG("*** bt sleep: %d ***\n", bSleep);
-#ifdef CONFIG_BT_AUTOSLEEP
- del_timer(&bt_sleep_tl);// cmy: È·±£ÔÚ»½ÐÑBTʱ£¬²»»áÒò´¥·¢bt_sleep_tl¶øÂíÉÏ˯Ãß
-#endif
-
- IOMUX_BT_GPIO_WAKE_UP();
- gpio_set_value(BT_GPIO_WAKE_UP, bSleep?GPIO_LOW:GPIO_HIGH);
-
-#ifdef CONFIG_BT_AUTOSLEEP
- if(!bSleep)
- mod_timer(&bt_sleep_tl, jiffies + BT_AUTO_SLEEP_TIMEOUT*HZ);//ÔÙÖØÐÂÉèÖó¬Ê±Öµ¡£
-#endif
-}
-
-static int bcm4329_set_block(void *data, bool blocked)
-{
- DBG("set blocked :%d\n", blocked);
-
- IOMUX_BT_GPIO_POWER();
- IOMUX_BT_GPIO_RESET();
-
- if (false == blocked) {
- gpio_set_value(BT_GPIO_POWER, GPIO_HIGH); /* bt power on */
- mdelay(20);
-
- gpio_set_value(BT_GPIO_RESET, GPIO_LOW);
- mdelay(20);
- gpio_set_value(BT_GPIO_RESET, GPIO_HIGH); /* bt reset deactive*/
-
- mdelay(20);
- bcm4325_sleep(0); // ensure bt is wakeup
-
- pr_info("bt turn on power\n");
- } else {
-#if WIFI_BT_POWER_TOGGLE
- if (!rk29sdk_wifi_power_state) {
-#endif
- gpio_set_value(BT_GPIO_POWER, GPIO_LOW); /* bt power off */
- mdelay(20);
- pr_info("bt shut off power\n");
-#if WIFI_BT_POWER_TOGGLE
- }else {
- pr_info("bt shouldn't shut off power, wifi is using it!\n");
- }
-#endif
-
- gpio_set_value(BT_GPIO_RESET, GPIO_LOW); /* bt reset active*/
- mdelay(20);
- }
-
-#if WIFI_BT_POWER_TOGGLE
- rk29sdk_bt_power_state = !blocked;
-#endif
- return 0;
-}
-
-static const struct rfkill_ops bcm4329_rfk_ops = {
- .set_block = bcm4329_set_block,
-};
-
-static int __devinit bcm4329_rfkill_probe(struct platform_device *pdev)
-{
- int rc = 0;
- bool default_state = true;
-
- DBG("Enter %s\n",__FUNCTION__);
-
- /* default to bluetooth off */
- bcm4329_set_block(NULL, default_state); /* blocked -> bt off */
-
- gBtCtrl.bt_rfk = rfkill_alloc(bt_name,
- NULL,
- RFKILL_TYPE_BLUETOOTH,
- &bcm4329_rfk_ops,
- NULL);
-
- if (!gBtCtrl.bt_rfk)
- {
- LOG("fail to rfkill_allocate\n");
- return -ENOMEM;
- }
-
- rfkill_set_states(gBtCtrl.bt_rfk, default_state, false);
-
- rc = rfkill_register(gBtCtrl.bt_rfk);
- if (rc)
- {
- LOG("failed to rfkill_register,rc=0x%x\n",rc);
- rfkill_destroy(gBtCtrl.bt_rfk);
- }
-
- gpio_request(BT_GPIO_POWER, NULL);
- gpio_request(BT_GPIO_RESET, NULL);
- gpio_request(BT_GPIO_WAKE_UP, NULL);
-
-#ifdef CONFIG_BT_AUTOSLEEP
- init_timer(&bt_sleep_tl);
- bt_sleep_tl.expires = 0;
- bt_sleep_tl.function = bcm4325_sleep;
- bt_sleep_tl.data = 1;
- add_timer(&bt_sleep_tl);
-#endif
-
-#if BT_WAKE_HOST_SUPPORT
- init_timer(&(gBtCtrl.tl));
- gBtCtrl.tl.expires = 0;
- gBtCtrl.tl.function = timer_hostSleep;
- add_timer(&(gBtCtrl.tl));
- gBtCtrl.b_HostWake = false;
-
- wake_lock_init(&(gBtCtrl.bt_wakelock), WAKE_LOCK_SUSPEND, "bt_wake");
-
- rc = gpio_request(BT_GPIO_WAKE_UP_HOST, "bt_wake");
- if (rc) {
- LOG("Failed to request BT_WAKE_UP_HOST\n");
- }
-
- IOMUX_BT_GPIO_WAKE_UP_HOST();
- gpio_pull_updown(BT_GPIO_WAKE_UP_HOST,GPIOPullUp);
- #endif
-
- LOG("bcm4329 module has been initialized,rc=0x%x\n",rc);
-
- return rc;
-}
-
-
-static int __devexit bcm4329_rfkill_remove(struct platform_device *pdev)
-{
- if (gBtCtrl.bt_rfk)
- rfkill_unregister(gBtCtrl.bt_rfk);
- gBtCtrl.bt_rfk = NULL;
-#if BT_WAKE_HOST_SUPPORT
- del_timer(&(gBtCtrl.tl));//ɾµô¶¨Ê±Æ÷
- btWakeupHostUnlock();
- wake_lock_destroy(&(gBtCtrl.bt_wakelock));
-#endif
-#ifdef CONFIG_BT_AUTOSLEEP
- del_timer(&bt_sleep_tl);
-#endif
-
- platform_set_drvdata(pdev, NULL);
-
- DBG("Enter %s\n",__FUNCTION__);
- return 0;
-}
-
-static struct platform_driver bcm4329_rfkill_driver = {
- .probe = bcm4329_rfkill_probe,
- .remove = __devexit_p(bcm4329_rfkill_remove),
- .driver = {
- .name = "rk29sdk_rfkill",
- .owner = THIS_MODULE,
- },
-#if BT_WAKE_HOST_SUPPORT
- .suspend = bcm4329_rfkill_suspend,
- .resume = bcm4329_rfkill_resume,
-#endif
-};
-
-/*
- * Module initialization
- */
-static int __init bcm4329_mod_init(void)
-{
- int ret;
- DBG("Enter %s\n",__FUNCTION__);
- ret = platform_driver_register(&bcm4329_rfkill_driver);
- LOG("ret=0x%x\n", ret);
- return ret;
-}
-
-static void __exit bcm4329_mod_exit(void)
-{
- platform_driver_unregister(&bcm4329_rfkill_driver);
-}
-
-module_init(bcm4329_mod_init);
-module_exit(bcm4329_mod_exit);
-MODULE_DESCRIPTION("bcm4329 Bluetooth driver");
-MODULE_AUTHOR("roger_chen cz@rock-chips.com, cmy@rock-chips.com");
-MODULE_LICENSE("GPL");
-
+++ /dev/null
-#include <linux/regulator/machine.h>
-#include <linux/mfd/wm831x/pdata.h>
-#include <linux/mfd/wm831x/core.h>
-#include <linux/mfd/wm831x/gpio.h>
-#include <linux/mfd/wm831x/pmu.h>
-
-#include <mach/sram.h>
-
-#define cru_readl(offset) readl_relaxed(RK30_CRU_BASE + offset)
-#define cru_writel(v, offset) do { writel_relaxed(v, RK30_CRU_BASE + offset); dsb(); } while (0)
-
-#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
-
-#define CRU_CLKGATE5_CON_ADDR 0x00e4
-#define GRF_GPIO6L_DIR_ADDR 0x0030
-#define GRF_GPIO6L_DO_ADDR 0x0068
-#define GRF_GPIO6L_EN_ADDR 0x00a0
-#define CRU_CLKGATE5_GRFCLK_ON 0x00100000
-#define CRU_CLKGATE5_GRFCLK_OFF 0x00100010
-#define GPIO6_PB1_DIR_OUT 0x02000200
-#define GPIO6_PB1_DO_LOW 0x02000000
-#define GPIO6_PB1_DO_HIGH 0x02000200
-#define GPIO6_PB1_EN_MASK 0x02000200
-#define GPIO6_PB1_UNEN_MASK 0x02000000
-
-/* wm8326 pmu*/
-#if defined(CONFIG_GPIO_WM831X)
-static struct rk29_gpio_expander_info wm831x_gpio_settinginfo[] = {
- {
- .gpio_num = WM831X_P01, // tp3
- .pin_type = GPIO_OUT,
- .pin_value = GPIO_LOW,
- },
- {
- .gpio_num = WM831X_P02, //tp4
- .pin_type = GPIO_IN,
- },
- {
- .gpio_num = WM831X_P03, //tp2
- .pin_type = GPIO_OUT,
- .pin_value = GPIO_HIGH,
- },
- {
- .gpio_num = WM831X_P04, //tp1
- .pin_type = GPIO_IN,
- },
- {
- .gpio_num = WM831X_P05, //tp1
- .pin_type = GPIO_IN,
- },
- {
- .gpio_num = WM831X_P06, //tp1
- .pin_type = GPIO_OUT,
- .pin_value = GPIO_HIGH,
- },
- {
- .gpio_num = WM831X_P07, //tp1
- .pin_type = GPIO_IN,
- },
- {
- .gpio_num = WM831X_P08, //tp1
- .pin_type = GPIO_OUT,
- .pin_value = GPIO_HIGH,
- },
- {
- .gpio_num = WM831X_P09, //tp1
- .pin_type = GPIO_OUT,
- .pin_value = GPIO_HIGH,
- },
- {
- .gpio_num = WM831X_P10, //tp1
- .pin_type = GPIO_IN,
- },
- {
- .gpio_num = WM831X_P11, //tp1
- .pin_type = GPIO_OUT,
- .pin_value = GPIO_HIGH,
- },
- {
- .gpio_num = WM831X_P12,
- .pin_type = GPIO_OUT,
- .pin_value = GPIO_HIGH,
- },
-};
-#endif
-
-#if defined(CONFIG_MFD_WM831X)
-
-#define UNLOCK_SECURITY_KEY ~(0x1<<5)
-#define LOCK_SECURITY_KEY 0x00
-#define PMU_POWER_SLEEP RK30_PIN6_PB1
-static struct wm831x *Wm831x;
-
-static int wm831x_pre_init(struct wm831x *parm)
-{
- int ret;
- Wm831x = parm;
-// printk("%s\n", __func__);
- gpio_request(PMU_POWER_SLEEP, "NULL");
- gpio_direction_output(PMU_POWER_SLEEP, GPIO_LOW);
-
- #ifdef CONFIG_WM8326_VBAT_LOW_DETECTION
- #ifdef CONFIG_BATTERY_RK30_VOL3V8
- wm831x_set_bits(parm,WM831X_SYSVDD_CONTROL ,0xc077,0xc035); //pvdd power on dect vbat voltage
- printk("+++The vbat is too low+++\n");
- #endif
- #endif
-
- ret = wm831x_reg_read(parm, WM831X_POWER_STATE) & 0xffff;
- wm831x_reg_write(parm, WM831X_POWER_STATE, (ret & 0xfff8) | 0x04);
-
- wm831x_set_bits(parm, WM831X_RTC_CONTROL, WM831X_RTC_ALAM_ENA_MASK, 0x0400);//enable rtc alam
- //BATT_FET_ENA = 1
- wm831x_reg_write(parm, WM831X_SECURITY_KEY, 0x9716); // unlock security key
- wm831x_set_bits(parm, WM831X_RESET_CONTROL, 0x1003, 0x1001);
- ret = wm831x_reg_read(parm, WM831X_RESET_CONTROL) & 0xffff & UNLOCK_SECURITY_KEY; // enternal reset active in sleep
-// printk("%s:WM831X_RESET_CONTROL=0x%x\n", __func__, ret);
- wm831x_reg_write(parm, WM831X_RESET_CONTROL, ret);
-
- wm831x_set_bits(parm,WM831X_DC1_ON_CONFIG ,0x0300,0x0000); //set dcdc mode is FCCM
- wm831x_set_bits(parm,WM831X_DC2_ON_CONFIG ,0x0300,0x0000);
- wm831x_set_bits(parm,WM831X_DC3_ON_CONFIG ,0x0300,0x0000);
- wm831x_set_bits(parm,0x4066,0x0300,0x0000);
-
-#ifndef CONFIG_MACH_RK3066_SDK
- wm831x_set_bits(parm,WM831X_LDO10_CONTROL ,0x0040,0x0040);// set ldo10 in switch mode
-#endif
- wm831x_set_bits(parm,WM831X_STATUS_LED_1 ,0xc300,0xc100);// set led1 on(in manual mode)
- wm831x_set_bits(parm,WM831X_STATUS_LED_2 ,0xc300,0xc000);//set led2 off(in manual mode)
-
- wm831x_set_bits(parm,WM831X_LDO5_SLEEP_CONTROL ,0xe000,0x2000);// set ldo5 is disable in sleep mode
- wm831x_set_bits(parm,WM831X_LDO1_SLEEP_CONTROL ,0xe000,0x2000);// set ldo1 is disable in sleep mode
-
- wm831x_reg_write(parm, WM831X_SECURITY_KEY, LOCK_SECURITY_KEY); // lock security key
-
- return 0;
-}
-static int wm831x_mask_interrupt(struct wm831x *Wm831x)
-{
- /**************************clear interrupt********************/
- wm831x_reg_write(Wm831x,WM831X_INTERRUPT_STATUS_1,0xffff);
- wm831x_reg_write(Wm831x,WM831X_INTERRUPT_STATUS_2,0xffff);
- wm831x_reg_write(Wm831x,WM831X_INTERRUPT_STATUS_3,0xffff);
- wm831x_reg_write(Wm831x,WM831X_INTERRUPT_STATUS_4,0xffff);
- wm831x_reg_write(Wm831x,WM831X_INTERRUPT_STATUS_5,0xffff);
-
- wm831x_reg_write(Wm831x,WM831X_SYSTEM_INTERRUPTS_MASK,0xbedc); //mask interrupt which not used
- return 0;
- /*****************************************************************/
-}
-
-#ifdef CONFIG_WM8326_VBAT_LOW_DETECTION
-static int wm831x_low_power_detection(struct wm831x *wm831x)
-{
- #ifdef CONFIG_BATTERY_RK30_VOL3V8
- wm831x_reg_write(wm831x,WM831X_SYSTEM_INTERRUPTS_MASK,0xbe5c);
- wm831x_set_bits(wm831x,WM831X_INTERRUPT_STATUS_1_MASK,0x8000,0x0000);
- wm831x_set_bits(wm831x,WM831X_SYSVDD_CONTROL ,0xc077,0x0035); //set pvdd low voltage is 3.1v hi voltage is 3.3v
- #else
- wm831x_reg_write(wm831x,WM831X_AUXADC_CONTROL,0x803f); //open adc
- wm831x_reg_write(wm831x,WM831X_AUXADC_CONTROL,0xd03f);
- wm831x_reg_write(wm831x,WM831X_AUXADC_SOURCE,0x0001);
-
- wm831x_reg_write(wm831x,WM831X_COMPARATOR_CONTROL,0x0001);
- wm831x_reg_write(wm831x,WM831X_COMPARATOR_1,0x2844); //set the low power is 3.1v
-
- wm831x_reg_write(wm831x,WM831X_INTERRUPT_STATUS_1_MASK,0x99ee);
- wm831x_set_bits(wm831x,WM831X_SYSTEM_INTERRUPTS_MASK,0x0100,0x0000);
- if (wm831x_reg_read(wm831x,WM831X_AUXADC_DATA)< 0x1844){
- printk("The vbat is too low.\n");
- wm831x_device_shutdown(wm831x);
- }
- #endif
- return 0;
-}
-#endif
-
-#define AVS_BASE 172
-int wm831x_post_init(struct wm831x *Wm831x)
-{
- struct regulator *dcdc;
- struct regulator *ldo;
-
-
- ldo = regulator_get(NULL, "ldo6"); //vcc_33
- regulator_set_voltage(ldo, 3300000, 3300000);
- regulator_set_suspend_voltage(ldo, 3300000);
- regulator_enable(ldo);
-// printk("%s set ldo6 vcc_33=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo4"); // vdd_11
- regulator_set_voltage(ldo, 1100000, 1100000);
- regulator_set_suspend_voltage(ldo, 1000000);
- regulator_enable(ldo);
-// printk("%s set ldo4 vdd_11=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo5"); //vcc_25
- regulator_set_voltage(ldo, 2500000, 2500000);
- regulator_set_suspend_voltage(ldo, 2500000);
- regulator_enable(ldo);
-// printk("%s set ldo5 vcc_25=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
-
- dcdc = regulator_get(NULL, "dcdc4"); // vcc_io
-#ifdef CONFIG_MACH_RK3066_SDK
- regulator_set_voltage(dcdc, 3300000, 3300000);
- regulator_set_suspend_voltage(dcdc, 3100000);
-#else
- regulator_set_voltage(dcdc, 3000000, 3000000);
- regulator_set_suspend_voltage(dcdc, 2800000);
-#endif
- regulator_enable(dcdc);
-// printk("%s set dcdc4 vcc_io=%dmV end\n", __func__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- dcdc = regulator_get(NULL, "vdd_cpu"); // vdd_arm
- regulator_set_voltage(dcdc, 1100000, 1100000);
- regulator_set_suspend_voltage(dcdc, 1000000);
- regulator_enable(dcdc);
- printk("%s set dcdc2 vdd_cpu(vdd_arm)=%dmV end\n", __func__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- dcdc = regulator_get(NULL, "vdd_core"); // vdd_log
-
- /* Read avs value under logic 1.1V*/
- regulator_set_voltage(dcdc, 1100000, 1100000);
- avs_init_val_get(1,1100000,"wm8326 init");
- udelay(600);
- avs_set_scal_val(AVS_BASE);
-
- regulator_set_voltage(dcdc, 1150000, 1150000);
- regulator_set_suspend_voltage(dcdc, 1000000);
- regulator_enable(dcdc);
- printk("%s set dcdc1 vdd_core(vdd_log)=%dmV end\n", __func__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- dcdc = regulator_get(NULL, "dcdc3"); // vcc_ddr
- regulator_set_voltage(dcdc, 1150000, 1150000);
- regulator_set_suspend_voltage(dcdc, 1150000);
- regulator_enable(dcdc);
-// printk("%s set dcdc3 vcc_ddr=%dmV end\n", __func__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo7"); // vcc28_cif
- regulator_set_voltage(ldo, 2800000, 2800000);
- regulator_set_suspend_voltage(ldo, 2800000);
- regulator_enable(ldo);
-// printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo1"); // vcc18_cif
- regulator_set_voltage(ldo, 1800000, 1800000);
- regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(ldo);
-// printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo8"); // vcca_33
- regulator_set_voltage(ldo, 3300000, 3300000);
- regulator_set_suspend_voltage(ldo, 3300000);
- regulator_enable(ldo);
-// printk("%s set ldo8 vcca_33=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo2"); //vccio_wl
- regulator_set_voltage(ldo, 1800000, 1800000);
- regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(ldo);
-// printk("%s set ldo2 vccio_wl=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo10"); //flash io
- regulator_set_voltage(ldo, 1800000, 1800000);
- regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(ldo);
-// printk("%s set ldo10 vcca_wl=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
-#ifdef CONFIG_MACH_RK3066_SDK
- ldo = regulator_get(NULL, "ldo3"); //vdd11_hdmi
- regulator_set_voltage(ldo, 1100000, 1100000);
- regulator_set_suspend_voltage(ldo, 1100000);
-#else
- ldo = regulator_get(NULL, "ldo3"); //vdd_12
- regulator_set_voltage(ldo, 1200000, 1200000);
- regulator_set_suspend_voltage(ldo, 1200000);
-#endif
- regulator_enable(ldo);
-// printk("%s set ldo3 vdd_12=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo9"); //vcc_tp
- regulator_set_voltage(ldo, 3300000, 3300000);
- regulator_set_suspend_voltage(ldo, 3300000);
- regulator_enable(ldo);
-// printk("%s set ldo9 vcc_tp=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- wm831x_mask_interrupt(Wm831x);
-
- #ifdef CONFIG_WM8326_VBAT_LOW_DETECTION
- wm831x_low_power_detection(Wm831x);
- #endif
-
- printk("wm831x_post_init end");
- return 0;
-}
-
-static int wm831x_last_deinit(struct wm831x *Wm831x)
-{
- struct regulator *ldo;
-
- printk("%s\n", __func__);
- ldo = regulator_get(NULL, "ldo1");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo2");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo3");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo4");
- //regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo5");
-// regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo6");
-// regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo7");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo8");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo9");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo10");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- return 0;
-}
-
-struct wm831x_status_pdata wm831x_status_platdata[WM831X_MAX_STATUS] = {
- {
- .default_src = WM831X_STATUS_OTP,
- .name = "wm831x_status0",
- .default_trigger = "wm831x_otp",
- },
- {
- .default_src = WM831X_STATUS_POWER,
- .name = "wm831x_status1",
- .default_trigger = "wm831x_power",
- },
-};
-
-static struct regulator_consumer_supply dcdc1_consumers[] = {
- {
- .supply = "vdd_core",
- }
-};
-
-static struct regulator_consumer_supply dcdc2_consumers[] = {
- {
- .supply = "vdd_cpu",
- }
-
-};
-
-static struct regulator_consumer_supply dcdc3_consumers[] = {
- {
- .supply = "dcdc3",
- }
-};
-
-static struct regulator_consumer_supply dcdc4_consumers[] = {
- {
- .supply = "dcdc4",
- }
-};
-
-#if 0
-static struct regulator_consumer_supply epe1_consumers[] = {
- {
- .supply = "epe1",
- }
-};
-
-static struct regulator_consumer_supply epe2_consumers[] = {
- {
- .supply = "epe2",
- }
-};
-#endif
-
-static struct regulator_consumer_supply ldo1_consumers[] = {
- {
- .supply = "ldo1",
- }
-};
-
-static struct regulator_consumer_supply ldo2_consumers[] = {
- {
- .supply = "ldo2",
- }
-};
-
-static struct regulator_consumer_supply ldo3_consumers[] = {
- {
- .supply = "ldo3",
- }
-};
-
-static struct regulator_consumer_supply ldo4_consumers[] = {
- {
- .supply = "ldo4",
- }
-};
-
-static struct regulator_consumer_supply ldo5_consumers[] = {
- {
- .supply = "ldo5",
- }
-};
-
-static struct regulator_consumer_supply ldo6_consumers[] = {
- {
- .supply = "ldo6",
- }
-};
-
-static struct regulator_consumer_supply ldo7_consumers[] = {
- {
- .supply = "ldo7",
- }
-};
-
-static struct regulator_consumer_supply ldo8_consumers[] = {
- {
- .supply = "ldo8",
- }
-};
-
-static struct regulator_consumer_supply ldo9_consumers[] = {
- {
- .supply = "ldo9",
- }
-};
-
-static struct regulator_consumer_supply ldo10_consumers[] = {
- {
- .supply = "ldo10",
- }
-};
-
-static struct regulator_consumer_supply ldo11_consumers[] = {
- {
- .supply = "ldo11",
- }
-};
-
-struct regulator_init_data wm831x_regulator_init_dcdc[WM831X_MAX_DCDC] = {
- {
- .constraints = {
- .name = "DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(dcdc1_consumers),
- .consumer_supplies = dcdc1_consumers,
- },
- {
- .constraints = {
- .name = "DCDC2",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(dcdc2_consumers),
- .consumer_supplies = dcdc2_consumers,
- },
- {
- .constraints = {
- .name = "DCDC3",
- .min_uV = 850000,
- .max_uV = 3400000, //0.85-3.4V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(dcdc3_consumers),
- .consumer_supplies = dcdc3_consumers,
- },
- {
- .constraints = {
- .name = "DCDC4",
- .min_uV = 850000,
- .max_uV = 3400000, //0.85-3.4V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(dcdc4_consumers),
- .consumer_supplies = dcdc4_consumers,
- },
-};
-
-#if 0
-struct regulator_init_data wm831x_regulator_init_epe[WM831X_MAX_EPE] = {
- {
- .constraints = {
- .name = "EPE1",
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(epe1_consumers),
- .consumer_supplies = epe1_consumers,
- },
- {
- .constraints = {
- .name = "EPE2",
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(epe2_consumers),
- .consumer_supplies = epe2_consumers,
- },
-};
-#endif
-
-struct regulator_init_data wm831x_regulator_init_ldo[WM831X_MAX_LDO] = {
- {
- .constraints = {
- .name = "LDO1",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo1_consumers),
- .consumer_supplies = ldo1_consumers,
- },
- {
- .constraints = {
- .name = "LDO2",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
- .consumer_supplies = ldo2_consumers,
- },
- {
- .constraints = {
- .name = "LDO3",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo3_consumers),
- .consumer_supplies = ldo3_consumers,
- },
- {
- .constraints = {
- .name = "LDO4",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo4_consumers),
- .consumer_supplies = ldo4_consumers,
- },
- {
- .constraints = {
- .name = "LDO5",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo5_consumers),
- .consumer_supplies = ldo5_consumers,
- },
- {
- .constraints = {
- .name = "LDO6",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo6_consumers),
- .consumer_supplies = ldo6_consumers,
- },
- {
- .constraints = {
- .name = "LDO7",
- .min_uV = 1000000,
- .max_uV = 3500000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo7_consumers),
- .consumer_supplies = ldo7_consumers,
- },
- {
- .constraints = {
- .name = "LDO8",
- .min_uV = 1000000,
- .max_uV = 3500000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo8_consumers),
- .consumer_supplies = ldo8_consumers,
- },
- {
- .constraints = {
- .name = "LDO9",
- .min_uV = 1000000,
- .max_uV = 3500000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo9_consumers),
- .consumer_supplies = ldo9_consumers,
- },
- {
- .constraints = {
- .name = "LDO10",
- .min_uV = 1000000,
- .max_uV = 3500000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo10_consumers),
- .consumer_supplies = ldo10_consumers,
- },
- {
- .constraints = {
- .name = "LDO11",
- .min_uV = 800000,
- .max_uV = 1550000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo11_consumers),
- .consumer_supplies = ldo11_consumers,
- },
-};
-
-static int wm831x_init_pin_type(struct wm831x *wm831x)
-{
- struct wm831x_pdata *pdata;
- struct rk29_gpio_expander_info *wm831x_gpio_settinginfo;
- uint16_t wm831x_settingpin_num;
- int i;
-
- if (!wm831x || !wm831x->dev)
- goto out;
-
- pdata = wm831x->dev->platform_data;
- if (!pdata)
- goto out;
-
- wm831x_gpio_settinginfo = pdata->settinginfo;
- if (!wm831x_gpio_settinginfo)
- goto out;
-
- wm831x_settingpin_num = pdata->settinginfolen;
- for (i = 0; i < wm831x_settingpin_num; i++) {
- if (wm831x_gpio_settinginfo[i].pin_type == GPIO_IN) {
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_DIR_MASK | WM831X_GPN_TRI_MASK,
- 1 << WM831X_GPN_DIR_SHIFT | 1 << WM831X_GPN_TRI_SHIFT);
- if (i == 1) {
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_POL_MASK,
- 0x0400);
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_FN_MASK,
- 0x0003);
- } // set gpio2 sleep/wakeup
-
- if (i == 9) {
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_PULL_MASK,
- 0x0000); //disable pullup/down
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_PWR_DOM_MASK,
- 0x0800);
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_ENA_MASK,
- 0x0000);
- } //set gpio10 as adc input
-
- } else {
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_DIR_MASK | WM831X_GPN_TRI_MASK,
- 1 << WM831X_GPN_TRI_SHIFT);
- if (wm831x_gpio_settinginfo[i].pin_value == GPIO_HIGH) {
- wm831x_set_bits(wm831x, WM831X_GPIO_LEVEL, 1 << i, 1 << i);
- } else {
- wm831x_set_bits(wm831x, WM831X_GPIO_LEVEL, 1 << i, 0 << i);
- }
- if (i == 2) {
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_PWR_DOM_MASK | WM831X_GPN_POL_MASK |WM831X_GPN_FN_MASK,
- 1 << WM831X_GPN_POL_SHIFT | 1 << WM831X_GPN_PWR_DOM_SHIFT | 1 << 0);
-
- } // set gpio3 as clkout output 32.768K
-
- }
- }
-
-#if 0
- for (i = 0; i < pdata->gpio_pin_num; i++) {
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_PULL_MASK | WM831X_GPN_POL_MASK | WM831X_GPN_OD_MASK | WM831X_GPN_TRI_MASK,
- 1 << WM831X_GPN_POL_SHIFT | 1 << WM831X_GPN_TRI_SHIFT);
-
- ret = wm831x_reg_read(wm831x, WM831X_GPIO1_CONTROL + i);
- printk("Gpio%d Pin Configuration = %x\n", i, ret);
- }
-#endif
-
-out:
- return 0;
-}
-
-void __sramfunc board_pmu_suspend(void)
-{
- cru_writel(CRU_CLKGATE5_GRFCLK_ON,CRU_CLKGATE5_CON_ADDR); //open grf clk
- grf_writel(GPIO6_PB1_DIR_OUT, GRF_GPIO6L_DIR_ADDR);
- grf_writel(GPIO6_PB1_DO_HIGH, GRF_GPIO6L_DO_ADDR); //set gpio6_b1 output low
- grf_writel(GPIO6_PB1_EN_MASK, GRF_GPIO6L_EN_ADDR);
-}
-void __sramfunc board_pmu_resume(void)
-{
- grf_writel(GPIO6_PB1_DIR_OUT, GRF_GPIO6L_DIR_ADDR);
- grf_writel(GPIO6_PB1_DO_LOW, GRF_GPIO6L_DO_ADDR); //set gpio6_b1 output high
- grf_writel(GPIO6_PB1_EN_MASK, GRF_GPIO6L_EN_ADDR);
-#ifdef CONFIG_CLK_SWITCH_TO_32K
- sram_32k_udelay(10000);
-#else
- sram_udelay(10000);
-#endif
-}
-static struct wm831x_pdata wm831x_platdata = {
-
- /** Called before subdevices are set up */
- .pre_init = wm831x_pre_init,
- /** Called after subdevices are set up */
- .post_init = wm831x_post_init,
- /** Called before subdevices are power down */
- .last_deinit = wm831x_last_deinit,
-
-#if defined(CONFIG_GPIO_WM831X)
- .gpio_base = WM831X_GPIO_EXPANDER_BASE,
- .gpio_pin_num = WM831X_TOTOL_GPIO_NUM,
- .settinginfo = wm831x_gpio_settinginfo,
- .settinginfolen = ARRAY_SIZE(wm831x_gpio_settinginfo),
- .pin_type_init = wm831x_init_pin_type,
- .irq_base = IRQ_BOARD_BASE,
-#endif
-
- /** LED1 = 0 and so on */
- .status = { &wm831x_status_platdata[0], &wm831x_status_platdata[1] },
-
- /** DCDC1 = 0 and so on */
- .dcdc = {
- &wm831x_regulator_init_dcdc[0],
- &wm831x_regulator_init_dcdc[1],
- &wm831x_regulator_init_dcdc[2],
- &wm831x_regulator_init_dcdc[3],
- },
-
- /** EPE1 = 0 and so on */
- //.epe = { &wm831x_regulator_init_epe[0], &wm831x_regulator_init_epe[1] },
-
- /** LDO1 = 0 and so on */
- .ldo = {
- &wm831x_regulator_init_ldo[0],
- &wm831x_regulator_init_ldo[1],
- &wm831x_regulator_init_ldo[2],
- &wm831x_regulator_init_ldo[3],
- &wm831x_regulator_init_ldo[4],
- &wm831x_regulator_init_ldo[5],
- &wm831x_regulator_init_ldo[6],
- &wm831x_regulator_init_ldo[7],
- &wm831x_regulator_init_ldo[8],
- &wm831x_regulator_init_ldo[9],
- &wm831x_regulator_init_ldo[10],
- },
-};
-#endif
+++ /dev/null
-/* arch/arm/mach-rk30/board-rk30-sdk.c
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <mach/dvfs.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <linux/fb.h>
-#include <linux/regulator/machine.h>
-#if defined(CONFIG_HDMI_RK30)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-#if defined(CONFIG_ANDROID_TIMED_GPIO)
-#include "../../../drivers/staging/android/timed_gpio.h"
-#endif
-
-#ifdef CONFIG_THREE_FB_BUFFER
-#define RK30_FB0_MEM_SIZE 12*SZ_1M
-#else
-#define RK30_FB0_MEM_SIZE 8*SZ_1M
-#endif
-
-#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Macro Define Begin ------------------------*/
-/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
-
-#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_OV2655 /* back camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_0 0x60
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 3
-#define CONFIG_SENSOR_CIF_INDEX_0 0
-#define CONFIG_SENSOR_ORIENTATION_0 90
-#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 RK30_PIN1_PB6
-#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 12504
-#define CONFIG_SENSOR_240X160_FPS_FIXED_0 12504
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 12504
-#define CONFIG_SENSOR_CIF_FPS_FIXED_0 12504
-#define CONFIG_SENSOR_VGA_FPS_FIXED_0 12504
-#define CONFIG_SENSOR_480P_FPS_FIXED_0 12504
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 12504
-#define CONFIG_SENSOR_720P_FPS_FIXED_0 12504
-
-#define CONFIG_SENSOR_01 RK29_CAM_SENSOR_OV5642 /* back camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_01 0x00
-#define CONFIG_SENSOR_CIF_INDEX_01 1
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 4
-#define CONFIG_SENSOR_ORIENTATION_01 90
-#define CONFIG_SENSOR_POWER_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 12504
-#define CONFIG_SENSOR_240X160_FPS_FIXED_01 12504
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 12504
-#define CONFIG_SENSOR_CIF_FPS_FIXED_01 12504
-#define CONFIG_SENSOR_VGA_FPS_FIXED_01 12504
-#define CONFIG_SENSOR_480P_FPS_FIXED_01 12504
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 12504
-#define CONFIG_SENSOR_720P_FPS_FIXED_01 12504
-
-#define CONFIG_SENSOR_02 RK29_CAM_SENSOR_OV5640 /* back camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_02 0x00
-#define CONFIG_SENSOR_CIF_INDEX_02 1
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 4
-#define CONFIG_SENSOR_ORIENTATION_02 90
-#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 12504
-#define CONFIG_SENSOR_240X160_FPS_FIXED_02 12504
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 12504
-#define CONFIG_SENSOR_CIF_FPS_FIXED_02 12504
-#define CONFIG_SENSOR_VGA_FPS_FIXED_02 12504
-#define CONFIG_SENSOR_480P_FPS_FIXED_02 12504
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 12504
-#define CONFIG_SENSOR_720P_FPS_FIXED_02 12504
-
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_OV2655 /* front camera sensor 0 */
-#define CONFIG_SENSOR_IIC_ADDR_1 0x60
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 3
-#define CONFIG_SENSOR_CIF_INDEX_1 0
-#define CONFIG_SENSOR_ORIENTATION_1 270
-#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_1 RK30_PIN1_PB7
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 12504
-#define CONFIG_SENSOR_240X160_FPS_FIXED_1 12504
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 12504
-#define CONFIG_SENSOR_CIF_FPS_FIXED_1 12504
-#define CONFIG_SENSOR_VGA_FPS_FIXED_1 12504
-#define CONFIG_SENSOR_480P_FPS_FIXED_1 12504
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 12504
-#define CONFIG_SENSOR_720P_FPS_FIXED_1 12504
-
-#define CONFIG_SENSOR_11 RK29_CAM_SENSOR_OV2659 /* front camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_11 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 3
-#define CONFIG_SENSOR_CIF_INDEX_11 0
-#define CONFIG_SENSOR_ORIENTATION_11 270
-#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 12504
-#define CONFIG_SENSOR_240X160_FPS_FIXED_11 12504
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 12500
-#define CONFIG_SENSOR_CIF_FPS_FIXED_11 12504
-#define CONFIG_SENSOR_VGA_FPS_FIXED_11 12504
-#define CONFIG_SENSOR_480P_FPS_FIXED_11 12504
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 12504
-#define CONFIG_SENSOR_720P_FPS_FIXED_11 12504
-
-#define CONFIG_SENSOR_12 RK29_CAM_SENSOR_OV2655 /* front camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_12 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 3
-#define CONFIG_SENSOR_CIF_INDEX_12 0
-#define CONFIG_SENSOR_ORIENTATION_12 270
-#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 12504
-#define CONFIG_SENSOR_240X160_FPS_FIXED_12 12504
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 12504
-#define CONFIG_SENSOR_CIF_FPS_FIXED_12 12504
-#define CONFIG_SENSOR_VGA_FPS_FIXED_12 12504
-#define CONFIG_SENSOR_480P_FPS_FIXED_12 12504
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 12504
-#define CONFIG_SENSOR_720P_FPS_FIXED_12 12504
-
-#endif //#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk30_camera.c"
-/*---------------- Camera Sensor Macro Define End ---------*/
-
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#define CONFIG_SENSOR_POWER_IOCTL_USR 0
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
-
-static void rk_cif_power(int on)
-{
- struct regulator *ldo_18,*ldo_28;
- ldo_28 = regulator_get(NULL, "ldo7"); // vcc28_cif
- ldo_18 = regulator_get(NULL, "ldo1"); // vcc18_cif
-
- if(on == 0){
- regulator_disable(ldo_28);
- regulator_put(ldo_28);
- regulator_disable(ldo_18);
- regulator_put(ldo_18);
- mdelay(500);
- }
- else{
- regulator_set_voltage(ldo_28, 2800000, 2800000);
- regulator_enable(ldo_28);
- // printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
- regulator_put(ldo_28);
-
- regulator_set_voltage(ldo_18, 1800000, 1800000);
- // regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(ldo_18);
- // printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo_18);
- }
-}
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- //#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
- rk_cif_power(on);
-}
-#endif
-
-#if CONFIG_SENSOR_RESET_IOCTL_USR
-static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
-static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-
-#if CONFIG_SENSOR_IIC_ADDR_0
-static struct reginfo_t rk_init_data_sensor_reg_0[] =
-{
- {0x0000, 0x00,0,0}
- };
-static struct reginfo_t rk_init_data_sensor_winseqreg_0[] ={
- {0x0000, 0x00,0,0}
- };
-#endif
-
-#if CONFIG_SENSOR_IIC_ADDR_1
-static struct reginfo_t rk_init_data_sensor_reg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_01
-static struct reginfo_t rk_init_data_sensor_reg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_02
-static struct reginfo_t rk_init_data_sensor_reg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_11
-static struct reginfo_t rk_init_data_sensor_reg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_12
-static struct reginfo_t rk_init_data_sensor_reg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] =
-{
- #if CONFIG_SENSOR_IIC_ADDR_0
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_0,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_1
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_1,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_01
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_01,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_02
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_02,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_11
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_11,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_12
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_12,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
-
- };
-#include "../../../drivers/media/video/rk30_camera.c"
-
-#endif /* CONFIG_VIDEO_RK29 */
-
-#if defined(CONFIG_TOUCHSCREEN_GT8XX)
-#define TOUCH_RESET_PIN RK30_PIN4_PD0
-#define TOUCH_PWR_PIN INVALID_GPIO
-int goodix_init_platform_hw(void)
-{
- int ret;
-
- rk30_mux_api_set(GPIO4D0_SMCDATA8_TRACEDATA8_NAME, GPIO4D_GPIO4D0);
- rk30_mux_api_set(GPIO4C2_SMCDATA2_TRACEDATA2_NAME, GPIO4C_GPIO4C2);
- printk("%s:0x%x,0x%x\n",__func__,rk30_mux_api_get(GPIO4D0_SMCDATA8_TRACEDATA8_NAME),rk30_mux_api_get(GPIO4C2_SMCDATA2_TRACEDATA2_NAME));
-
- if (TOUCH_PWR_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_PWR_PIN, "goodix power pin");
- if (ret != 0) {
- gpio_free(TOUCH_PWR_PIN);
- printk("goodix power error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_PWR_PIN, 0);
- gpio_set_value(TOUCH_PWR_PIN, GPIO_LOW);
- msleep(100);
- }
-
- if (TOUCH_RESET_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_RESET_PIN, "goodix reset pin");
- if (ret != 0) {
- gpio_free(TOUCH_RESET_PIN);
- printk("goodix gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, 1);
- msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_LOW);
- //msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_HIGH);
- //msleep(500);
- }
- return 0;
-}
-
-struct goodix_platform_data goodix_info = {
- .model = 8105,
- .irq_pin = RK30_PIN4_PC2,
- .rest_pin = TOUCH_RESET_PIN,
- .init_platform_hw = goodix_init_platform_hw,
-};
-#endif
-
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-#define PWM_ID 0
-#define PWM_MUX_NAME GPIO0A3_PWM0_NAME
-#define PWM_MUX_MODE GPIO0A_PWM0
-#define PWM_MUX_MODE_GPIO GPIO0A_GPIO0A3
-#define PWM_GPIO RK30_PIN0_PA3
-#define PWM_EFFECT_VALUE 1
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-//#define BL_EN_MUX_NAME GPIOF34_UART3_SEL_NAME
-//#define BL_EN_MUX_MODE IOMUXB_GPIO1_B34
-
-#define BL_EN_PIN RK30_PIN6_PB3
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
-#ifdef LCD_DISP_ON_PIN
- // rk30_mux_api_set(BL_EN_MUX_NAME, BL_EN_MUX_MODE);
-
- ret = gpio_request(BL_EN_PIN, NULL);
- if (ret != 0) {
- gpio_free(BL_EN_PIN);
- }
-
- gpio_direction_output(BL_EN_PIN, BL_EN_VALUE);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0;
-#ifdef LCD_DISP_ON_PIN
- gpio_free(BL_EN_PIN);
-#endif
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- gpio_free(PWM_GPIO);
- if (ret = gpio_request(PWM_GPIO, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- gpio_direction_output(PWM_GPIO, !BL_EN_VALUE);
- gpio_set_value(PWM_GPIO,!BL_EN_VALUE);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret = 0;
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- if (gpio_request(PWM_GPIO, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- gpio_direction_output(PWM_GPIO, GPIO_LOW);
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, !BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- gpio_free(PWM_GPIO);
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
-#ifdef LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, 1);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
- .min_brightness = 60,
- .pre_div = 20000,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-#endif
-
-#ifdef CONFIG_RK29_SUPPORT_MODEM
-
-#define RK30_MODEM_POWER RK30_PIN4_PD1
-#define RK30_MODEM_POWER_IOMUX rk29_mux_api_set(GPIO4D1_SMCDATA9_TRACEDATA9_NAME, GPIO4D_GPIO4D1)
-
-static int rk30_modem_io_init(void)
-{
- printk("%s\n", __FUNCTION__);
- RK30_MODEM_POWER_IOMUX;
-
- return 0;
-}
-
-static struct rk29_io_t rk30_modem_io = {
- .io_addr = RK30_MODEM_POWER,
- .enable = GPIO_HIGH,
- .disable = GPIO_LOW,
- .io_init = rk30_modem_io_init,
-};
-
-static struct platform_device rk30_device_modem = {
- .name = "rk30_modem",
- .id = -1,
- .dev = {
- .platform_data = &rk30_modem_io,
- }
-};
-#endif
-
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN RK30_PIN4_PC0
-
-static int mma8452_init_platform_hw(void)
-{
- rk30_mux_api_set(GPIO4C0_SMCDATA0_TRACEDATA0_NAME, GPIO4C_GPIO4C0);
-
- return 0;
-}
-
-static struct gsensor_platform_data mma8452_info = {
- .model = 8452,
- .swap_xy = 0,
- .swap_xyz = 1,
- .init_platform_hw = mma8452_init_platform_hw,
- .orientation ={1, 0, 0, 0, 0, -1, 0, -1, 0},
-};
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
-static struct akm8975_platform_data akm8975_info =
-{
- .m_layout =
- {
- {
- {1, 0, 0},
- {0, 0, 1},
- {0, 1, 0},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-#if defined(CONFIG_GYRO_L3G4200D)
-
-#include <linux/l3g4200d.h>
-#define L3G4200D_INT_PIN RK30_PIN4_PC3
-
-static int l3g4200d_init_platform_hw(void)
-{
- rk30_mux_api_set(GPIO4C3_SMCDATA3_TRACEDATA3_NAME, GPIO4C_GPIO4C3);
-
- return 0;
-}
-
-static struct l3g4200d_platform_data l3g4200d_info = {
- .orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
- .init = l3g4200d_init_platform_hw,
- .x_min = 40,//x_min,y_min,z_min = (0-100) according to hardware
- .y_min = 40,
- .z_min = 20,
-};
-
-#endif
-
-#ifdef CONFIG_LS_CM3217
-
-#define CM3217_POWER_PIN INVALID_GPIO
-#define CM3217_IRQ_PIN INVALID_GPIO
-static int cm3217_init_hw(void)
-{
-#if 0
- if (gpio_request(CM3217_POWER_PIN, NULL) != 0) {
- gpio_free(CM3217_POWER_PIN);
- printk("%s: request cm3217 power pin error\n", __func__);
- return -EIO;
- }
- gpio_pull_updown(CM3217_POWER_PIN, PullDisable);
-
- if (gpio_request(CM3217_IRQ_PIN, NULL) != 0) {
- gpio_free(CM3217_IRQ_PIN);
- printk("%s: request cm3217 int pin error\n", __func__);
- return -EIO;
- }
- gpio_pull_updown(CM3217_IRQ_PIN, PullDisable);
-#endif
- return 0;
-}
-
-static void cm3217_exit_hw(void)
-{
-#if 0
- gpio_free(CM3217_POWER_PIN);
- gpio_free(CM3217_IRQ_PIN);
-#endif
- return;
-}
-
-static struct cm3217_platform_data cm3217_info = {
- .irq_pin = CM3217_IRQ_PIN,
- .power_pin = CM3217_POWER_PIN,
- .init_platform_hw = cm3217_init_hw,
- .exit_platform_hw = cm3217_exit_hw,
-};
-#endif
-
-#ifdef CONFIG_FB_ROCKCHIP
-
-#define LCD_CS_MUX_NAME GPIO4C7_SMCDATA7_TRACEDATA7_NAME
-#define LCD_CS_PIN RK30_PIN4_PC7
-#define LCD_CS_VALUE GPIO_HIGH
-#define LCD_EN_PIN RK30_PIN6_PB4
-#define LCD_EN_VALUE GPIO_HIGH
-
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
- rk30_mux_api_set(LCD_CS_MUX_NAME, GPIO4C_GPIO4C7);
- ret = gpio_request(LCD_CS_PIN, "lcd_CS");
- if(ret!=0){
- gpio_free(LCD_CS_PIN);
- printk(KERN_ERR "request lcd cs pin fail!\n");
- }
- gpio_direction_output(LCD_CS_PIN, LCD_CS_VALUE);
- gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE);
-
- ret = gpio_request(LCD_EN_PIN, "lcd_en");
- if (ret != 0)
- {
- gpio_free(LCD_EN_PIN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_EN_PIN, LCD_EN_VALUE);
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
- }
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
- gpio_set_value(LCD_EN_PIN, !LCD_EN_VALUE);
- gpio_set_value(LCD_CS_PIN, !LCD_CS_VALUE);
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
- gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE);
- return 0;
-}
-
-#if defined(CONFIG_LCDC0_RK30)
-struct rk29fb_info lcdc0_screen_info = {
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK30)
-struct rk29fb_info lcdc1_screen_info = {
- #if defined(CONFIG_HDMI_RK30)
- .prop = EXTEND, //extend display device
- .lcd_info = NULL,
- .set_screen_info = hdmi_init_lcdc,
- #endif
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-
-#if defined(CONFIG_LCDC0_RK30)
-static struct resource resource_lcdc0[] = {
- [0] = {
- .name = "lcdc0 reg",
- .start = RK30_LCDC0_PHYS,
- .end = RK30_LCDC0_PHYS + RK30_LCDC0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc0 irq",
- .start = IRQ_LCDC0,
- .end = IRQ_LCDC0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc0 = {
- .name = "rk30-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc0),
- .resource = resource_lcdc0,
- .dev = {
- .platform_data = &lcdc0_screen_info,
- },
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK30)
-extern struct rk29fb_info lcdc1_screen_info;
-static struct resource resource_lcdc1[] = {
- [0] = {
- .name = "lcdc1 reg",
- .start = RK30_LCDC1_PHYS,
- .end = RK30_LCDC1_PHYS + RK30_LCDC1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc1 irq",
- .start = IRQ_LCDC1,
- .end = IRQ_LCDC1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc1 = {
- .name = "rk30-lcdc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resource_lcdc1),
- .resource = resource_lcdc1,
- .dev = {
- .platform_data = &lcdc1_screen_info,
- },
-};
-#endif
-
-#ifdef CONFIG_ANDROID_TIMED_GPIO
-static struct timed_gpio timed_gpios[] = {
- {
- .name = "vibrator",
- .gpio = RK30_PIN0_PA4,
- .max_timeout = 1000,
- .active_low = 0,
- .adjust_time =20, //adjust for diff product
- },
-};
-
-static struct timed_gpio_platform_data rk29_vibrator_info = {
- .num_gpios = 1,
- .gpios = timed_gpios,
-};
-
-static struct platform_device rk29_device_vibrator = {
- .name = "timed-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_vibrator_info,
- },
-
-};
-#endif
-
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
-static struct gpio_led rk29_leds[] = {
- {
- .name = "button-backlight",
- .gpio = RK30_PIN4_PD7,
- .default_trigger = "timer",
- .active_low = 0,
- .retain_state_suspended = 0,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- },
-};
-
-static struct gpio_led_platform_data rk29_leds_pdata = {
- .leds = rk29_leds,
- .num_leds = ARRAY_SIZE(rk29_leds),
-};
-
-static struct platform_device rk29_device_gpio_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_leds_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_RK_IRDA
-#define IRDA_IRQ_PIN RK30_PIN6_PA1
-
-static int irda_iomux_init(void)
-{
- int ret = 0;
-
- //irda irq pin
- ret = gpio_request(IRDA_IRQ_PIN, NULL);
- if (ret != 0) {
- gpio_free(IRDA_IRQ_PIN);
- printk(">>>>>> IRDA_IRQ_PIN gpio_request err \n ");
- }
- gpio_pull_updown(IRDA_IRQ_PIN, PullDisable);
- gpio_direction_input(IRDA_IRQ_PIN);
-
- return 0;
-}
-
-static int irda_iomux_deinit(void)
-{
- gpio_free(IRDA_IRQ_PIN);
- return 0;
-}
-
-static struct irda_info rk29_irda_info = {
- .intr_pin = IRDA_IRQ_PIN,
- .iomux_init = irda_iomux_init,
- .iomux_deinit = irda_iomux_deinit,
- //.irda_pwr_ctl = bu92747guw_power_ctl,
-};
-
-static struct platform_device irda_device = {
-#ifdef CONFIG_RK_IRDA_NET
- .name = "rk_irda",
-#else
- .name = "bu92747_irda",
-#endif
- .id = -1,
- .dev = {
- .platform_data = &rk29_irda_info,
- }
-};
-#endif
-
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and sdio.noted by xbw at 2012-03-05
-**************************************************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "board-rk30-sdk-sdmmc.c"
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
-#define SDMMC0_WRITE_PROTECT_PIN RK30_PIN3_PB7 //According to your own project to set the value of write-protect-pin.
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
-#define SDMMC1_WRITE_PROTECT_PIN RK30_PIN3_PC7 //According to your own project to set the value of write-protect-pin.
-#endif
-
-#define RK29SDK_WIFI_SDIO_CARD_DETECT_N RK30_PIN6_PB2
-
-#endif //endif ---#ifdef CONFIG_SDMMC_RK29
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- rk30_mux_api_set(GPIO3B1_SDMMC0CMD_NAME, GPIO3B_SDMMC0_CMD);
- rk30_mux_api_set(GPIO3B0_SDMMC0CLKOUT_NAME, GPIO3B_SDMMC0_CLKOUT);
- rk30_mux_api_set(GPIO3B2_SDMMC0DATA0_NAME, GPIO3B_SDMMC0_DATA0);
- rk30_mux_api_set(GPIO3B3_SDMMC0DATA1_NAME, GPIO3B_SDMMC0_DATA1);
- rk30_mux_api_set(GPIO3B4_SDMMC0DATA2_NAME, GPIO3B_SDMMC0_DATA2);
- rk30_mux_api_set(GPIO3B5_SDMMC0DATA3_NAME, GPIO3B_SDMMC0_DATA3);
-
- rk30_mux_api_set(GPIO3B6_SDMMC0DETECTN_NAME, GPIO3B_GPIO3B6);
-
- rk30_mux_api_set(GPIO3A7_SDMMC0PWREN_NAME, GPIO3A_GPIO3A7);
- gpio_request(RK30_PIN3_PA7, "sdmmc-power");
- gpio_direction_output(RK30_PIN3_PA7, GPIO_LOW);
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- rk30_mux_api_set(GPIO3B6_SDMMC0DETECTN_NAME, GPIO3B_SDMMC0_DETECT_N);
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
- .detect_irq = RK30_PIN3_PB6, // INVALID_GPIO
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
-#else
- .write_prt = INVALID_GPIO,
-#endif
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SND_SOC_RK610
-static int rk610_codec_io_init(void)
-{
-//if need iomux.
-//Must not gpio_request
- return 0;
-}
-
-static struct rk610_codec_platform_data rk610_codec_pdata = {
- .spk_ctl_io = RK30_PIN4_PC6,
- .io_init = rk610_codec_io_init,
-};
-#endif
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- rk30_mux_api_set(GPIO3C0_SMMC1CMD_NAME, GPIO3C_SMMC1_CMD);
- rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_NAME, GPIO3C_SDMMC1_CLKOUT);
- rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_NAME, GPIO3C_SDMMC1_DATA0);
- rk30_mux_api_set(GPIO3C2_SDMMC1DATA1_NAME, GPIO3C_SDMMC1_DATA1);
- rk30_mux_api_set(GPIO3C3_SDMMC1DATA2_NAME, GPIO3C_SDMMC1_DATA2);
- rk30_mux_api_set(GPIO3C4_SDMMC1DATA3_NAME, GPIO3C_SDMMC1_DATA3);
- //rk30_mux_api_set(GPIO3C6_SDMMC1DETECTN_NAME, GPIO3C_SDMMC1_DETECT_N);
-
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-#if 0
- .detect_irq = RK29SDK_WIFI_SDIO_CARD_DETECT_N,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
-#else
- .detect_irq = INVALID_GPIO,
- .enable_sd_wakeup = 0,
-#endif
-
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-/**************************************************************************************************
- * the end of setting for SDMMC devices
-**************************************************************************************************/
-
-/* bluetooth rfkill device */
-static struct platform_device rk29sdk_rfkill = {
- .name = "rk29sdk_rfkill",
- .id = -1,
-};
-
-#ifdef CONFIG_BATTERY_RK30_ADC
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = RK30_PIN6_PA5,
- .batt_low_pin = RK30_PIN6_PA0,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = RK30_PIN6_PA6,
- .dc_det_level = GPIO_LOW,
- .charge_ok_level = GPIO_HIGH,
-};
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-
-#ifdef CONFIG_RK29_VMAC
-#define PHY_PWR_EN_GPIO RK30_PIN1_PD6
-#include "board-rk30-sdk-vmac.c"
-#endif
-
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_FB_ROCKCHIP
- &device_fb,
-#endif
-#if defined(CONFIG_LCDC0_RK30)
- &device_lcdc0,
-#endif
-#if defined(CONFIG_LCDC1_RK30)
- &device_lcdc1,
-#endif
-
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- &rk29_device_backlight,
-#endif
-
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_ANDROID_TIMED_GPIO
- &rk29_device_vibrator,
-#endif
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
- &rk29_device_gpio_leds,
-#endif
-#ifdef CONFIG_RK_IRDA
- &irda_device,
-#endif
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- &rk29sdk_wifi_device,
-#endif
-#ifdef CONFIG_BT
- &rk29sdk_rfkill,
-#endif
-#ifdef CONFIG_RK29_SUPPORT_MODEM
- &rk30_device_modem,
-#endif
-#ifdef CONFIG_BATTERY_RK30_ADC
- &rk30_device_adc_battery,
-#endif
-};
-
-// i2c
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1d,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN4_PC1,
- .platform_data = &akm8975_info,
- },
-#endif
-#if defined (CONFIG_GYRO_L3G4200D)
- {
- .type = "l3g4200d_gryo",
- .addr = 0x69,
- .flags = 0,
- .irq = L3G4200D_INT_PIN,
- .platform_data = &l3g4200d_info,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RT5631)
- {
- .type = "rt5631",
- .addr = 0x1a,
- .flags = 0,
- },
-#endif
-
-#ifdef CONFIG_MFD_RK610
- {
- .type = "rk610_ctl",
- .addr = 0x40,
- .flags = 0,
- },
-#ifdef CONFIG_RK610_TVOUT
- {
- .type = "rk610_tvout",
- .addr = 0x42,
- .flags = 0,
- },
-#endif
-#ifdef CONFIG_HDMI_RK610
- {
- .type = "rk610_hdmi",
- .addr = 0x46,
- .flags = 0,
- .irq = RK29_PIN5_PA2,
- },
-#endif
-#ifdef CONFIG_SND_SOC_RK610
- {//RK610_CODEC addr from 0x60 to 0x80 (0x60~0x80)
- .type = "rk610_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- .platform_data = &rk610_codec_pdata,
- },
-#endif
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C1_RK30
-#include "board-rk30-ds1001b-wm8326.c"
-
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_MFD_WM831X_I2C)
- {
- .type = "wm8326",
- .addr = 0x34,
- .flags = 0,
- .irq = RK30_PIN6_PA4,
- .platform_data = &wm831x_platdata,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-#if defined (CONFIG_TOUCHSCREEN_GT8XX)
- {
- .type = "Goodix-TS",
- .addr = 0x55,
- .flags = 0,
- .irq = RK30_PIN4_PC2,
- .platform_data = &goodix_info,
- },
-#endif
-#if defined (CONFIG_LS_CM3217)
- {
- .type = "lightsensor",
- .addr = 0x10,
- .flags = 0,
- .irq = CM3217_IRQ_PIN,
- .platform_data = &cm3217_info,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C4_RK30
-static struct i2c_board_info __initdata i2c4_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO// RK30_PIN2_PD6 //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO//RK30_PIN2_PD7 //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- //set iomux (gpio) here
- //rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME, GPIO2D_GPIO2D7);
- //rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME, GPIO2D_GPIO2D6);
-
- return 0;
-}
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C4_RK30
- i2c_register_board_info(4, i2c4_info, ARRAY_SIZE(i2c4_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(5, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-
-static void dcr_en_low(void)
-{
- int ret;
- ret=gpio_request(RK30_PIN4_PB7,"dcr_en");
- if(ret<0){
- printk("dcr_en_low request io error");
- gpio_free(RK30_PIN4_PB7);
- return;
- }
- gpio_direction_output(RK30_PIN4_PB7, GPIO_LOW);
-}
-#define POWER_ON_PIN RK30_PIN6_PB0 //power_hold
-static void rk30_pm_power_off(void)
-{
- printk(KERN_ERR "rk30_pm_power_off start...\n");
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
-#if defined(CONFIG_MFD_WM831X)
- wm831x_set_bits(Wm831x,WM831X_GPIO_LEVEL,0x0001,0x0000); //set sys_pwr 0
- wm831x_device_shutdown(Wm831x);//wm8326 shutdown
-#endif
- while (1);
-}
-static void __init machine_rk30_board_init(void)
-{
- avs_init();
- gpio_request(POWER_ON_PIN, "poweronpin");
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
- pm_power_off = rk30_pm_power_off;
-
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- board_usb_detect_init(RK30_PIN6_PA3);
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- rk29sdk_wifi_bt_gpio_control_init();
-#endif
- dcr_en_low();
-}
-
-static void __init rk30_reserve(void)
-{
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0", RK30_FB0_MEM_SIZE);
- resource_fb[0].end = resource_fb[0].start + RK30_FB0_MEM_SIZE - 1;
- #if 0
- resource_fb[1].start = board_mem_reserve_add("ipp buf", RK30_FB0_MEM_SIZE);
- resource_fb[1].end = resource_fb[1].start + RK30_FB0_MEM_SIZE - 1;
- resource_fb[2].start = board_mem_reserve_add("fb2", RK30_FB0_MEM_SIZE);
- resource_fb[2].end = resource_fb[2].start + RK30_FB0_MEM_SIZE - 1;
- #endif
-#endif
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
- board_mem_reserved();
-}
-
-/**
- * dvfs_cpu_logic_table: table for arm and logic dvfs
- * @frequency : arm frequency
- * @cpu_volt : arm voltage depend on frequency
- * @logic_volt : logic voltage arm requests depend on frequency
- * comments : min arm/logic voltage
- */
-static struct dvfs_arm_table dvfs_cpu_logic_table[] = {
- {.frequency = 252 * 1000, .cpu_volt = 1050 * 1000, .logic_volt = 1050 * 1000},//0.975V/1.000V
- {.frequency = 504 * 1000, .cpu_volt = 1050 * 1000, .logic_volt = 1100 * 1000},//0.975V/1.000V
- {.frequency = 816 * 1000, .cpu_volt = 1100 * 1000, .logic_volt = 1150 * 1000},//1.000V/1.025V
- {.frequency = 1008 * 1000, .cpu_volt = 1100 * 1000, .logic_volt = 1150 * 1000},//1.025V/1.050V
- {.frequency = 1200 * 1000, .cpu_volt = 1175 * 1000, .logic_volt = 1200 * 1000},//1.100V/1.050V
- {.frequency = 1272 * 1000, .cpu_volt = 1225 * 1000, .logic_volt = 1200 * 1000},//1.150V/1.100V
- {.frequency = 1416 * 1000, .cpu_volt = 1300 * 1000, .logic_volt = 1200 * 1000},//1.225V/1.100V
- {.frequency = 1512 * 1000, .cpu_volt = 1350 * 1000, .logic_volt = 1250 * 1000},//1.300V/1.150V
- {.frequency = 1608 * 1000, .cpu_volt = 1375 * 1000, .logic_volt = 1275 * 1000},//1.325V/1.175V
- {.frequency = CPUFREQ_TABLE_END},
-};
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- {.frequency = 266 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1275 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1125 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
-static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
-static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
-
-void __init board_clock_init(void)
-{
- rk30_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
- dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
-}
-
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk30_fixup,
- .reserve = &rk30_reserve,
- .map_io = rk30_map_io,
- .init_irq = rk30_init_irq,
- .timer = &rk30_timer,
- .init_machine = machine_rk30_board_init,
-MACHINE_END
+++ /dev/null
-/* arch/arm/mach-rk30/board-rk30-sdk.c
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <mach/dvfs.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <linux/fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#if defined(CONFIG_HDMI_RK30)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-#if defined(CONFIG_MU509)
-#include <linux/mu509.h>
-#endif
-#if defined(CONFIG_MW100)
-#include <linux/mw100.h>
-#endif
-#if defined(CONFIG_MT6229)
-#include <linux/mt6229.h>
-#endif
-#if defined(CONFIG_SEW868)
-#include <linux/sew868.h>
-#endif
-#if defined(CONFIG_ANDROID_TIMED_GPIO)
-#include "../../../drivers/staging/android/timed_gpio.h"
-#endif
-
-#include <plat/key.h>
-
-/* Android Parameter */
-static int ap_mdm = 0;
-module_param(ap_mdm, int, 0644);
-static int ap_has_alsa = 0;
-module_param(ap_has_alsa, int, 0644);
-static int ap_data_only = 2;
-module_param(ap_data_only, int, 0644);
-static int ap_has_earphone = 0;
-module_param(ap_has_earphone, int, 0644);
-
-
-static struct rk29_keys_button key_button[] = {
- #if 0
- {
- .desc = "menu",
- .code = EV_MENU,
- .gpio = RK30_PIN6_PA0,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .gpio = RK30_PIN6_PA1,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .gpio = RK30_PIN4_PC5,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .gpio = RK30_PIN6_PA3,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "search",
- .code = KEY_SEARCH,
- .gpio = RK30_PIN6_PA4,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .gpio = RK30_PIN6_PA5,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "sensor",
- .code = KEY_CAMERA,
- .gpio = RK30_PIN6_PA6,
- .active_low = PRESS_LEV_LOW,
- },
- #endif
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK30_PIN6_PA2,
- .active_low = PRESS_LEV_LOW,
- //.code_long_press = EV_ENCALL,
- .wakeup = 1,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .adc_value = 155,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .adc_value = 1,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "menu",
- .code = EV_MENU,
- .adc_value = 328,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .gpio = RK30_PIN4_PC5,
- .active_low = PRESS_LEV_LOW,
- },
-#if 0
- {
- .desc = "esc",
- .code = KEY_BACK,
- .adc_value = 386,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "camera",
- .code = KEY_CAMERA,
- .adc_value = 827,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-#endif
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = 1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
-
-#ifdef CONFIG_THREE_FB_BUFFER
-#define RK30_FB0_MEM_SIZE 12*SZ_1M
-#else
-#define RK30_FB0_MEM_SIZE 12*SZ_1M
-#ifdef CONFIG_LCDC1_THREE_BUFFER
-#define RK30_FB1_MEM_SIZE 12*SZ_1M
-#endif
-#define RK30_IPP_MEM_SIZE 8*SZ_1M
-#endif
-#ifdef CONFIG_VIDEO_RK29
-#include <plat/rk_camera.h>
-/* Notes:
-
-Simple camera device registration:
-
- new_camera_device(sensor_name,\ // sensor name, it is equal to CONFIG_SENSOR_X
- face,\ // sensor face information, it can be back or front
- pwdn_io,\ // power down gpio configuration, it is equal to CONFIG_SENSOR_POWERDN_PIN_XX
- flash_attach,\ // sensor is attach flash or not
- mir,\ // sensor image mirror and flip control information
- i2c_chl,\ // i2c channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_IIC_ADAPTER_ID_X
- cif_chl) \ // cif channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_CIF_INDEX_X
-
-Comprehensive camera device registration:
-
- new_camera_device_ex(sensor_name,\
- face,\
- ori,\ // sensor orientation, it is equal to CONFIG_SENSOR_ORIENTATION_X
- pwr_io,\ // sensor power gpio configuration, it is equal to CONFIG_SENSOR_POWER_PIN_XX
- pwr_active,\ // sensor power active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- rst_io,\ // sensor reset gpio configuration, it is equal to CONFIG_SENSOR_RESET_PIN_XX
- rst_active,\ // sensor reset active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- pwdn_io,\
- pwdn_active,\ // sensor power down active level, is equal to CONFIG_SENSOR_POWERDNACTIVE_LEVEL_X
- flash_attach,\
- res,\ // sensor resolution, this is real resolution or resoltuion after interpolate
- mir,\
- i2c_chl,\
- i2c_spd,\ // i2c speed , 100000 = 100KHz
- i2c_addr,\ // the i2c slave device address for sensor
- cif_chl,\
- mclk)\ // sensor input clock rate, 24 or 48
-
-*/
-static struct rkcamera_platform_data new_camera[] = {
- new_camera_device(RK29_CAM_SENSOR_OV2659,
- back,
- RK30_PIN1_PD6,
- 0,
- 0,
- 3,
- 0),
- new_camera_device(RK29_CAM_SENSOR_OV2659,
- front,
- RK30_PIN1_PB7,
- 0,
- 0,
- 3,
- 0),
- new_camera_device_end
-};
-/*---------------- Camera Sensor Macro Define Begin ------------------------*/
-/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
-#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_OV2659 /* back camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_0 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 3
-#define CONFIG_SENSOR_CIF_INDEX_0 0
-#define CONFIG_SENSOR_ORIENTATION_0 90
-#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 RK30_PIN1_PD6
-#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000
-
-#define CONFIG_SENSOR_01 RK29_CAM_SENSOR_OV5642 /* back camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_01 0x00
-#define CONFIG_SENSOR_CIF_INDEX_01 1
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 4
-#define CONFIG_SENSOR_ORIENTATION_01 90
-#define CONFIG_SENSOR_POWER_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_01 30000
-
-#define CONFIG_SENSOR_02 RK29_CAM_SENSOR_OV5640 /* back camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_02 0x00
-#define CONFIG_SENSOR_CIF_INDEX_02 1
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 4
-#define CONFIG_SENSOR_ORIENTATION_02 90
-#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000
-
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_OV2659 /* front camera sensor 0 */
-#define CONFIG_SENSOR_IIC_ADDR_1 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 3
-#define CONFIG_SENSOR_CIF_INDEX_1 0
-#define CONFIG_SENSOR_ORIENTATION_1 270
-#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_1 RK30_PIN1_PB7
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000
-
-#define CONFIG_SENSOR_11 RK29_CAM_SENSOR_OV2659 /* front camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_11 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 3
-#define CONFIG_SENSOR_CIF_INDEX_11 0
-#define CONFIG_SENSOR_ORIENTATION_11 270
-#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_11 INVALID_GPIO//RK30_PIN1_PB7
-#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_11 30000
-
-#define CONFIG_SENSOR_12 RK29_CAM_SENSOR_OV2659//RK29_CAM_SENSOR_OV2655 /* front camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_12 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 3
-#define CONFIG_SENSOR_CIF_INDEX_12 0
-#define CONFIG_SENSOR_ORIENTATION_12 270
-#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_12 INVALID_GPIO//RK30_PIN1_PB7
-#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_12 30000
-
-
-#endif //#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk30_camera.c"
-/*---------------- Camera Sensor Macro Define End ---------*/
-
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#define CONFIG_SENSOR_POWER_IOCTL_USR 1 //define this refer to your board layout
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
-
-static void rk_cif_power(struct rk29camera_gpio_res *res,int on)
-{
- struct regulator *ldo_18,*ldo_28;
- int camera_power = res->gpio_power;
- int camera_ioflag = res->gpio_flag;
- int camera_io_init = res->gpio_init;
- ldo_28 = regulator_get(NULL, "ldo7"); // vcc28_cif
- ldo_18 = regulator_get(NULL, "ldo1"); // vcc18_cif
- if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){
- printk("get cif ldo failed!\n");
- return;
- }
- if(on == 0){
- while(regulator_is_enabled(ldo_28)>0)
- regulator_disable(ldo_28);
- regulator_put(ldo_28);
- while(regulator_is_enabled(ldo_18)>0)
- regulator_disable(ldo_18);
- regulator_put(ldo_18);
- mdelay(10);
- if (camera_power != INVALID_GPIO) {
- if (camera_io_init & RK29_CAM_POWERACTIVE_MASK) {
- gpio_set_value(camera_power, (((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
- }
- }
- }
- else{
- regulator_set_voltage(ldo_28, 2800000, 2800000);
- regulator_enable(ldo_28);
- // printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
- regulator_put(ldo_28);
-
- regulator_set_voltage(ldo_18, 1800000, 1800000);
- // regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(ldo_18);
- // printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo_18);
- if (camera_power != INVALID_GPIO) {
- if (camera_io_init & RK29_CAM_POWERACTIVE_MASK) {
- gpio_set_value(camera_power, ((camera_ioflag&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
- mdelay(10);
- }
- }
- }
-}
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- //#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
- rk_cif_power(res,on);
- return 0;
-}
-#endif
-
-#if CONFIG_SENSOR_RESET_IOCTL_USR
-static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
-static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-
-#if CONFIG_SENSOR_IIC_ADDR_0
-static struct reginfo_t rk_init_data_sensor_reg_0[] =
-{
- {0x0000, 0x00,0,0}
- };
-static struct reginfo_t rk_init_data_sensor_winseqreg_0[] ={
- {0x0000, 0x00,0,0}
- };
-#endif
-
-#if CONFIG_SENSOR_IIC_ADDR_1
-static struct reginfo_t rk_init_data_sensor_reg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_01
-static struct reginfo_t rk_init_data_sensor_reg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_02
-static struct reginfo_t rk_init_data_sensor_reg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_11
-static struct reginfo_t rk_init_data_sensor_reg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_12
-static struct reginfo_t rk_init_data_sensor_reg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] =
-{
- #if CONFIG_SENSOR_IIC_ADDR_0
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_0,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_1
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_1,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_01
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_01,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_02
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_02,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_11
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_11,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_12
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_12,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
-
- };
-#include "../../../drivers/media/video/rk30_camera.c"
-
-#endif /* CONFIG_VIDEO_RK29 */
-
-#if defined(CONFIG_TOUCHSCREEN_GT8XX)
-#define TOUCH_RESET_PIN RK30_PIN4_PD0
-#define TOUCH_PWR_PIN INVALID_GPIO
-int goodix_init_platform_hw(void)
-{
- int ret;
-
- rk30_mux_api_set(GPIO4D0_SMCDATA8_TRACEDATA8_NAME, GPIO4D_GPIO4D0);
- rk30_mux_api_set(GPIO4C2_SMCDATA2_TRACEDATA2_NAME, GPIO4C_GPIO4C2);
- printk("%s:0x%x,0x%x\n",__func__,rk30_mux_api_get(GPIO4D0_SMCDATA8_TRACEDATA8_NAME),rk30_mux_api_get(GPIO4C2_SMCDATA2_TRACEDATA2_NAME));
-
- if (TOUCH_PWR_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_PWR_PIN, "goodix power pin");
- if (ret != 0) {
- gpio_free(TOUCH_PWR_PIN);
- printk("goodix power error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_PWR_PIN, 0);
- gpio_set_value(TOUCH_PWR_PIN, GPIO_LOW);
- msleep(100);
- }
-
- if (TOUCH_RESET_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_RESET_PIN, "goodix reset pin");
- if (ret != 0) {
- gpio_free(TOUCH_RESET_PIN);
- printk("goodix gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, 1);
- msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_LOW);
- //msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_HIGH);
- //msleep(500);
- }
- return 0;
-}
-
-struct goodix_platform_data goodix_info = {
- .model = 8105,
- .irq_pin = RK30_PIN4_PC2,
- .rest_pin = TOUCH_RESET_PIN,
- .init_platform_hw = goodix_init_platform_hw,
-};
-#endif
-
-#if defined(CONFIG_TOUCHSCREEN_CT36X)
-#define TOUCH_MAX_X 1024
-#define TOUCH_MAX_y 768
-#define TOUCH_RESET_PIN RK30_PIN4_PD0
-#define TOUCH_INT_PIN RK30_PIN4_PC2
-
-static void ct3610_hw_init(void)
-{
- int ret;
-
- printk("%s\n", __FUNCTION__);
-
- if(TOUCH_RESET_PIN != INVALID_GPIO){
- gpio_request(TOUCH_RESET_PIN, "ct360_reset");
- gpio_direction_output(TOUCH_RESET_PIN, GPIO_HIGH);
- }
-
- if(TOUCH_INT_PIN != INVALID_GPIO){
- ret = gpio_request(TOUCH_INT_PIN, "ct360_irq");
- if(ret != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("%s: ct360 irq request err\n", __func__);
- }
- else{
- gpio_direction_input(TOUCH_INT_PIN);
- gpio_pull_updown(TOUCH_INT_PIN, GPIO_HIGH);
- }
- }
-}
-
-static void ct3610_hw_shutdown(int reset)
-{
- printk("%s: %d\n", __FUNCTION__, reset);
-
- if(TOUCH_RESET_PIN != INVALID_GPIO){
- if(reset){
- gpio_set_value(TOUCH_RESET_PIN, GPIO_HIGH);
- }
- else{
- gpio_set_value(TOUCH_RESET_PIN, GPIO_LOW);
- }
- }
-}
-
-static struct ct360_platform_data ct3610_info = {
- .model = 360,
- .x_max = TOUCH_MAX_X,
- .y_max = TOUCH_MAX_y,
- .hw_init = ct3610_hw_init,
- .shutdown = ct3610_hw_shutdown,
-};
-#endif
-
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-#define PWM_ID 2
-#define PWM_MUX_NAME GPIO0D6_PWM2_NAME
-#define PWM_MUX_MODE GPIO0D_PWM2
-#define PWM_MUX_MODE_GPIO GPIO0D_GPIO0D6
-#define PWM_GPIO RK30_PIN0_PD6
-#define PWM_EFFECT_VALUE 0
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-//#define BL_EN_MUX_NAME GPIOF34_UART3_SEL_NAME
-//#define BL_EN_MUX_MODE IOMUXB_GPIO1_B34
-
-#define BL_EN_PIN RK30_PIN6_PB3
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
-#ifdef LCD_DISP_ON_PIN
- // rk30_mux_api_set(BL_EN_MUX_NAME, BL_EN_MUX_MODE);
-
- ret = gpio_request(BL_EN_PIN, NULL);
- if (ret != 0) {
- gpio_free(BL_EN_PIN);
- }
-
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0;
-#ifdef LCD_DISP_ON_PIN
- gpio_set_value(BL_EN_PIN, !BL_EN_VALUE);
- gpio_free(BL_EN_PIN);
-#endif
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret = 0;
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- if (gpio_request(PWM_GPIO, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- gpio_direction_output(PWM_GPIO, GPIO_LOW);
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, !BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- gpio_free(PWM_GPIO);
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
-#ifdef LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, 1);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .pre_div = 30*1000,
- .pwm_id = PWM_ID,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
- .min_brightness = 70,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-#endif
-
-#ifdef CONFIG_RK29_SUPPORT_MODEM
-
-#define RK30_MODEM_POWER RK30_PIN4_PD1
-#define RK30_MODEM_POWER_IOMUX rk29_mux_api_set(GPIO4D1_SMCDATA9_TRACEDATA9_NAME, GPIO4D_GPIO4D1)
-
-static int rk30_modem_io_init(void)
-{
- printk("%s\n", __FUNCTION__);
- RK30_MODEM_POWER_IOMUX;
-
- return 0;
-}
-
-static struct rk29_io_t rk30_modem_io = {
- .io_addr = RK30_MODEM_POWER,
- .enable = GPIO_HIGH,
- .disable = GPIO_LOW,
- .io_init = rk30_modem_io_init,
-};
-
-static struct platform_device rk30_device_modem = {
- .name = "rk30_modem",
- .id = -1,
- .dev = {
- .platform_data = &rk30_modem_io,
- }
-};
-#endif
-#if defined(CONFIG_MU509)
-static int mu509_io_init(void)
-{
-
- rk30_mux_api_set(GPIO2B6_LCDC1DATA14_SMCADDR18_TSSYNC_NAME, GPIO2B_GPIO2B6);
- rk30_mux_api_set(GPIO4D2_SMCDATA10_TRACEDATA10_NAME, GPIO4D_GPIO4D2);
- rk30_mux_api_set(GPIO2B7_LCDC1DATA15_SMCADDR19_HSADCDATA7_NAME, GPIO2B_GPIO2B7);
- rk30_mux_api_set(GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME, GPIO2C_GPIO2C0);
- return 0;
-}
-
-static int mu509_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mu509_data rk29_mu509_info = {
- .io_init = mu509_io_init,
- .io_deinit = mu509_io_deinit,
- .modem_power_en = RK30_PIN6_PB2,//RK30_PIN4_PD1,
- .bp_power = RK30_PIN2_PB6,//RK30_PIN4_PD1,
- .bp_reset = RK30_PIN4_PD2,
- .ap_wakeup_bp = RK30_PIN2_PB7,
- .bp_wakeup_ap = RK30_PIN6_PA0,
-};
-struct platform_device rk29_device_mu509 = {
- .name = "mu509",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mu509_info,
- }
- };
-#endif
-#if defined(CONFIG_MW100)
-static int mw100_io_init(void)
-{
- rk30_mux_api_set(GPIO2B6_LCDC1DATA14_SMCADDR18_TSSYNC_NAME, GPIO2B_GPIO2B6);
- rk30_mux_api_set(GPIO4D2_SMCDATA10_TRACEDATA10_NAME, GPIO4D_GPIO4D2);
- rk30_mux_api_set(GPIO2B7_LCDC1DATA15_SMCADDR19_HSADCDATA7_NAME, GPIO2B_GPIO2B7);
- rk30_mux_api_set(GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME, GPIO2C_GPIO2C0);
- return 0;
-}
-
-static int mw100_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mw100_data rk29_mw100_info = {
- .io_init = mw100_io_init,
- .io_deinit = mw100_io_deinit,
- .modem_power_en = RK30_PIN6_PB2,
- .bp_power = RK30_PIN2_PB6,
- .bp_reset = RK30_PIN4_PD2,
- .ap_wakeup_bp = RK30_PIN2_PB7,
- .bp_wakeup_ap = RK30_PIN6_PA0,
-};
-struct platform_device rk29_device_mw100 = {
- .name = "mw100",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mw100_info,
- }
- };
-#endif
-#if defined(CONFIG_MT6229)
-static int mt6229_io_init(void)
-{
- rk30_mux_api_set(GPIO2B6_LCDC1DATA14_SMCADDR18_TSSYNC_NAME, GPIO2B_GPIO2B6);
- rk30_mux_api_set(GPIO4D2_SMCDATA10_TRACEDATA10_NAME, GPIO4D_GPIO4D2);
- rk30_mux_api_set(GPIO2B7_LCDC1DATA15_SMCADDR19_HSADCDATA7_NAME, GPIO2B_GPIO2B7);
- rk30_mux_api_set(GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME, GPIO2C_GPIO2C0);
- return 0;
-}
-
-static int mt6229_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mt6229_data rk29_mt6229_info = {
- .io_init = mt6229_io_init,
- .io_deinit = mt6229_io_deinit,
- .modem_power_en = RK30_PIN6_PB2,
- .bp_power = RK30_PIN2_PB7,
- .bp_reset = RK30_PIN4_PD2,
- .ap_wakeup_bp = RK30_PIN2_PC0,
- .bp_wakeup_ap = RK30_PIN6_PA0,
-};
-struct platform_device rk29_device_mt6229 = {
- .name = "mt6229",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mt6229_info,
- }
- };
-#endif
-#if defined(CONFIG_SEW868)
-static int sew868_io_init(void)
-{
- rk30_mux_api_set(GPIO2B6_LCDC1DATA14_SMCADDR18_TSSYNC_NAME, GPIO2B_GPIO2B6);
- rk30_mux_api_set(GPIO4D2_SMCDATA10_TRACEDATA10_NAME, GPIO4D_GPIO4D2);
- rk30_mux_api_set(GPIO4D4_SMCDATA12_TRACEDATA12_NAME, GPIO4D_GPIO4D4);
- return 0;
-}
-static int sew868_io_deinit(void)
-{
- return 0;
-}
-struct rk30_sew868_data rk30_sew868_info = {
- .io_init = sew868_io_init,
- .io_deinit = sew868_io_deinit,
- .bp_power = RK30_PIN6_PB2,
- .bp_power_active_low = 1,
- .bp_sys = RK30_PIN2_PB6,
- .bp_reset = RK30_PIN4_PD2,
- .bp_reset_active_low = 1,
- .bp_wakeup_ap = RK30_PIN4_PD4,
- .ap_wakeup_bp = NULL,
-};
-
-struct platform_device rk30_device_sew868 = {
- .name = "sew868",
- .id = -1,
- .dev = {
- .platform_data = &rk30_sew868_info,
- }
- };
-#endif
-
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN RK30_PIN4_PC0
-
-static int mma8452_init_platform_hw(void)
-{
- rk30_mux_api_set(GPIO4C0_SMCDATA0_TRACEDATA0_NAME, GPIO4C_GPIO4C0);
-
- return 0;
-}
-
-static struct sensor_platform_data mma8452_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma8452_init_platform_hw,
- .orientation = {0, -1, 0, -1, 0, 0, 0, 0, -1},
-};
-#endif
-#if defined (CONFIG_GS_LIS3DH)
-#define LIS3DH_INT_PIN RK30_PIN4_PC0
-
-static int lis3dh_init_platform_hw(void)
-{
- rk30_mux_api_set(GPIO4C0_SMCDATA0_TRACEDATA0_NAME, GPIO4C_GPIO4C0);
-
- return 0;
-}
-
-static struct sensor_platform_data lis3dh_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lis3dh_init_platform_hw,
- .orientation = {0, -1, 0, -1, 0, 0, 0, 0, -1},
-};
-#endif
-
-
-
-#if defined (CONFIG_COMPASS_AK8975)
-static struct sensor_platform_data akm8975_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {1, 0, 0},
- {0, 0, 1},
- {0, 1, 0},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-#if defined(CONFIG_GYRO_L3G4200D)
-
-#include <linux/l3g4200d.h>
-#define L3G4200D_INT_PIN RK30_PIN4_PC3
-
-static int l3g4200d_init_platform_hw(void)
-{
- rk30_mux_api_set(GPIO4C3_SMCDATA3_TRACEDATA3_NAME, GPIO4C_GPIO4C3);
-
- return 0;
-}
-
-static struct sensor_platform_data l3g4200d_info = {
- .type = SENSOR_TYPE_GYROSCOPE,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
- .init_platform_hw = l3g4200d_init_platform_hw,
- .x_min = 40,//x_min,y_min,z_min = (0-100) according to hardware
- .y_min = 40,
- .z_min = 20,
-};
-
-#endif
-
-#ifdef CONFIG_LS_CM3217
-
-#define CM3217_POWER_PIN INVALID_GPIO
-#define CM3217_IRQ_PIN INVALID_GPIO
-static int cm3217_init_hw(void)
-{
-#if 0
- if (gpio_request(CM3217_POWER_PIN, NULL) != 0) {
- gpio_free(CM3217_POWER_PIN);
- printk("%s: request cm3217 power pin error\n", __func__);
- return -EIO;
- }
- gpio_pull_updown(CM3217_POWER_PIN, PullDisable);
-
- if (gpio_request(CM3217_IRQ_PIN, NULL) != 0) {
- gpio_free(CM3217_IRQ_PIN);
- printk("%s: request cm3217 int pin error\n", __func__);
- return -EIO;
- }
- gpio_pull_updown(CM3217_IRQ_PIN, PullDisable);
-#endif
- return 0;
-}
-
-static void cm3217_exit_hw(void)
-{
-#if 0
- gpio_free(CM3217_POWER_PIN);
- gpio_free(CM3217_IRQ_PIN);
-#endif
- return;
-}
-
-static struct cm3217_platform_data cm3217_info = {
- .irq_pin = CM3217_IRQ_PIN,
- .power_pin = CM3217_POWER_PIN,
- .init_platform_hw = cm3217_init_hw,
- .exit_platform_hw = cm3217_exit_hw,
-};
-#endif
-
-#ifdef CONFIG_FB_ROCKCHIP
-
-#define LCD_EN_MUX_NAME GPIO4C7_SMCDATA7_TRACEDATA7_NAME
-#define LCD_EN_PIN RK30_PIN4_PC7
-#define LCD_EN_VALUE GPIO_HIGH
-
-#define LCD_CS_PIN RK30_PIN6_PB4
-#define LCD_CS_VALUE GPIO_LOW
-
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
- rk30_mux_api_set(LCD_EN_MUX_NAME, GPIO4C_GPIO4C7);
- ret = gpio_request(LCD_EN_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_EN_PIN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_EN_PIN, 1);
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
- }
-
- ret = gpio_request(LCD_CS_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_CS_PIN);
- printk(KERN_ERR "request lcd cs pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_CS_PIN, LCD_CS_VALUE);
- }
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
- gpio_set_value(LCD_EN_PIN, !LCD_EN_VALUE);
- gpio_set_value(LCD_CS_PIN, !LCD_CS_VALUE);
- mdelay(400);
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
- gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE);
- return 0;
-}
-
-#if defined(CONFIG_LCDC0_RK30)
-struct rk29fb_info lcdc0_screen_info = {
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK30)
-struct rk29fb_info lcdc1_screen_info = {
- #if defined(CONFIG_HDMI_RK30)
- .prop = EXTEND, //extend display device
- .lcd_info = NULL,
- .set_screen_info = hdmi_init_lcdc,
- #endif
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-#if defined(CONFIG_LCDC0_RK30)
-static struct resource resource_lcdc0[] = {
- [0] = {
- .name = "lcdc0 reg",
- .start = RK30_LCDC0_PHYS,
- .end = RK30_LCDC0_PHYS + RK30_LCDC0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc0 irq",
- .start = IRQ_LCDC0,
- .end = IRQ_LCDC0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc0 = {
- .name = "rk30-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc0),
- .resource = resource_lcdc0,
- .dev = {
- .platform_data = &lcdc0_screen_info,
- },
-};
-#endif
-#if defined(CONFIG_LCDC1_RK30)
-extern struct rk29fb_info lcdc1_screen_info;
-static struct resource resource_lcdc1[] = {
- [0] = {
- .name = "lcdc1 reg",
- .start = RK30_LCDC1_PHYS,
- .end = RK30_LCDC1_PHYS + RK30_LCDC1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc1 irq",
- .start = IRQ_LCDC1,
- .end = IRQ_LCDC1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc1 = {
- .name = "rk30-lcdc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resource_lcdc1),
- .resource = resource_lcdc1,
- .dev = {
- .platform_data = &lcdc1_screen_info,
- },
-};
-#endif
-
-
-#ifdef CONFIG_ANDROID_TIMED_GPIO
-static struct timed_gpio timed_gpios[] = {
- {
- .name = "vibrator",
- .gpio = RK30_PIN0_PA4,
- .max_timeout = 1000,
- .active_low = 0,
- .adjust_time =20, //adjust for diff product
- },
-};
-
-static struct timed_gpio_platform_data rk29_vibrator_info = {
- .num_gpios = 1,
- .gpios = timed_gpios,
-};
-
-static struct platform_device rk29_device_vibrator = {
- .name = "timed-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_vibrator_info,
- },
-
-};
-#endif
-
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
-static struct gpio_led rk29_leds[] = {
- {
- .name = "button-backlight",
- .gpio = RK30_PIN4_PD7,
- .default_trigger = "timer",
- .active_low = 0,
- .retain_state_suspended = 0,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- },
-};
-
-static struct gpio_led_platform_data rk29_leds_pdata = {
- .leds = rk29_leds,
- .num_leds = ARRAY_SIZE(rk29_leds),
-};
-
-static struct platform_device rk29_device_gpio_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_leds_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_RK_IRDA
-#define IRDA_IRQ_PIN RK30_PIN6_PA1
-
-static int irda_iomux_init(void)
-{
- int ret = 0;
-
- //irda irq pin
- ret = gpio_request(IRDA_IRQ_PIN, NULL);
- if (ret != 0) {
- gpio_free(IRDA_IRQ_PIN);
- printk(">>>>>> IRDA_IRQ_PIN gpio_request err \n ");
- }
- gpio_pull_updown(IRDA_IRQ_PIN, PullDisable);
- gpio_direction_input(IRDA_IRQ_PIN);
-
- return 0;
-}
-
-static int irda_iomux_deinit(void)
-{
- gpio_free(IRDA_IRQ_PIN);
- return 0;
-}
-
-static struct irda_info rk29_irda_info = {
- .intr_pin = IRDA_IRQ_PIN,
- .iomux_init = irda_iomux_init,
- .iomux_deinit = irda_iomux_deinit,
- //.irda_pwr_ctl = bu92747guw_power_ctl,
-};
-
-static struct platform_device irda_device = {
-#ifdef CONFIG_RK_IRDA_NET
- .name = "rk_irda",
-#else
- .name = "bu92747_irda",
-#endif
- .id = -1,
- .dev = {
- .platform_data = &rk29_irda_info,
- }
-};
-#endif
-
-#ifdef CONFIG_BATTERY_RK29_ADC
-static struct rk29_adc_battery_platform_data rk29_adc_battery_platdata = {
- .dc_det_pin = RK30_PIN6_PA5,
- .batt_low_pin = INVALID_GPIO,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = RK30_PIN6_PA6,
-
- .dc_det_level = GPIO_LOW,
- .charge_ok_level = GPIO_HIGH,
-};
-
-static struct platform_device rk29_device_adc_battery = {
- .name = "rk2918-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk29_adc_battery_platdata,
- },
-};
-#endif
-
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and SDIO.noted by xbw at 2012-03-05
-**************************************************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "board-rk30-sdk-sdmmc.c"
-#endif
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- rk30_mux_api_set(GPIO3B1_SDMMC0CMD_NAME, GPIO3B_SDMMC0_CMD);
- rk30_mux_api_set(GPIO3B0_SDMMC0CLKOUT_NAME, GPIO3B_SDMMC0_CLKOUT);
- rk30_mux_api_set(GPIO3B2_SDMMC0DATA0_NAME, GPIO3B_SDMMC0_DATA0);
- rk30_mux_api_set(GPIO3B3_SDMMC0DATA1_NAME, GPIO3B_SDMMC0_DATA1);
- rk30_mux_api_set(GPIO3B4_SDMMC0DATA2_NAME, GPIO3B_SDMMC0_DATA2);
- rk30_mux_api_set(GPIO3B5_SDMMC0DATA3_NAME, GPIO3B_SDMMC0_DATA3);
-
- rk30_mux_api_set(GPIO3B6_SDMMC0DETECTN_NAME, GPIO3B_GPIO3B6);
-
- rk30_mux_api_set(GPIO3A7_SDMMC0PWREN_NAME, GPIO3A_GPIO3A7);
- gpio_request(RK30_PIN3_PA7, "sdmmc-power");
- gpio_direction_output(RK30_PIN3_PA7, GPIO_LOW);
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- #if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO);
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FMUX);
- #endif
-
- #if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
- #endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) && defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- .status = rk29sdk_wifi_mmc0_status,
- .register_status_notify = rk29sdk_wifi_mmc0_status_register,
-#endif
-
- .power_en = RK29SDK_SD_CARD_PWR_EN,
- .power_en_level = RK29SDK_SD_CARD_PWR_EN_LEVEL,
-
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC0_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- .det_pin_info = {
- .io = RK29SDK_SD_CARD_DETECT_N, //INVALID_GPIO,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- },
- },
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SND_SOC_RK610
-static int rk610_codec_io_init(void)
-{
-//if need iomux.
-//Must not gpio_request
- return 0;
-}
-
-static struct rk610_codec_platform_data rk610_codec_pdata = {
- .spk_ctl_io = RK30_PIN4_PC6,
- .io_init = rk610_codec_io_init,
-};
-#endif
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- rk30_mux_api_set(GPIO3C0_SMMC1CMD_NAME, GPIO3C_SMMC1_CMD);
- rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_NAME, GPIO3C_SDMMC1_CLKOUT);
- rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_NAME, GPIO3C_SDMMC1_DATA0);
- rk30_mux_api_set(GPIO3C2_SDMMC1DATA1_NAME, GPIO3C_SDMMC1_DATA1);
- rk30_mux_api_set(GPIO3C3_SDMMC1DATA2_NAME, GPIO3C_SDMMC1_DATA2);
- rk30_mux_api_set(GPIO3C4_SDMMC1DATA3_NAME, GPIO3C_SDMMC1_DATA3);
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC) || defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-
- #if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC1_WRITE_PROTECT_ENABLE_VALUE;
- #else
- .write_prt = INVALID_GPIO,
- #endif
-
- #if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
- .sdio_INT_gpio = RK29SDK_WIFI_SDIO_CARD_INT,
- #endif
-
- .det_pin_info = {
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .io = RK29SDK_SD_CARD_DETECT_N,
-#else
- .io = INVALID_GPIO,
-#endif
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- },
- },
-
- .enable_sd_wakeup = 0,
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-/**************************************************************************************************
- * the end of setting for SDMMC devices
-**************************************************************************************************/
-
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = RK30_PIN6_PA5,
- .batt_low_pin = RK30_PIN6_PA0,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = RK30_PIN6_PA6,
- .dc_det_level = GPIO_LOW,
- .charge_ok_level = GPIO_HIGH,
-};
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-
-#ifdef CONFIG_RK29_VMAC
-#define PHY_PWR_EN_GPIO RK30_PIN1_PD6
-#include "board-rk30-sdk-vmac.c"
-#endif
-#ifdef CONFIG_RFKILL_RK
-// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
-static struct rfkill_rk_platform_data rfkill_rk_platdata = {
- .type = RFKILL_TYPE_BLUETOOTH,
-
- .poweron_gpio = { // BT_REG_ON
- .io = RK30_PIN3_PC7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C7_SDMMC1WRITEPRT_NAME,
- .fgpio = GPIO3C_GPIO3C7,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN3_PD1, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = GPIO3D1_SDMMC1BACKENDPWR_NAME,
- .fgpio = GPIO3D_GPIO3D1,
- },
- },
-
- .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
- .io = RK30_PIN3_PC6, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C6_SDMMC1DETECTN_NAME,
- .fgpio = GPIO3C_GPIO3C6,
- },
- },
-
- .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .gpio = {
- .io = RK30_PIN6_PA7, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
- .iomux = {
- .name = NULL,
- },
- },
- },
-
- .rts_gpio = { // UART_RTS, enable or disable BT's data coming
- .io = RK30_PIN1_PA3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = GPIO1A3_UART0RTSN_NAME,
- .fgpio = GPIO1A_GPIO1A3,
- .fmux = GPIO1A_UART0_RTS_N,
- },
- },
-};
-
-static struct platform_device device_rfkill_rk = {
- .name = "rfkill_rk",
- .id = -1,
- .dev = {
- .platform_data = &rfkill_rk_platdata,
- },
-};
-#endif
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_FB_ROCKCHIP
- &device_fb,
-#endif
-#if defined(CONFIG_LCDC0_RK30)
- &device_lcdc0,
-#endif
-#if defined(CONFIG_LCDC1_RK30)
- &device_lcdc1,
-#endif
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- &rk29_device_backlight,
-#endif
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_ANDROID_TIMED_GPIO
- &rk29_device_vibrator,
-#endif
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
- &rk29_device_gpio_leds,
-#endif
-#ifdef CONFIG_RK_IRDA
- &irda_device,
-#endif
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- &rk29sdk_wifi_device,
-#endif
-#ifdef CONFIG_RK29_SUPPORT_MODEM
- &rk30_device_modem,
-#endif
-#if defined(CONFIG_MU509)
- &rk29_device_mu509,
-#endif
-#if defined(CONFIG_MW100)
- &rk29_device_mw100,
-#endif
-#if defined(CONFIG_MT6229)
- &rk29_device_mt6229,
-#endif
-#if defined(CONFIG_SEW868)
- &rk30_device_sew868,
-#endif
-#ifdef CONFIG_RFKILL_RK
- &device_rfkill_rk,
-#endif
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
- &rk30_device_adc_battery,
-#endif
-#ifdef CONFIG_BATTERY_RK29_ADC
- &rk29_device_adc_battery,
-#endif
-};
-
-// i2c
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1d,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_GS_LIS3DH)
- {
- .type = "gs_lis3dh",
- .addr = 0x19,
- .flags = 0,
- .irq = LIS3DH_INT_PIN,
- .platform_data = &lis3dh_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN4_PC1,
- .platform_data = &akm8975_info,
- },
-#endif
-#if defined (CONFIG_GYRO_L3G4200D)
- {
- .type = "l3g4200d_gryo",
- .addr = 0x69,
- .flags = 0,
- .irq = L3G4200D_INT_PIN,
- .platform_data = &l3g4200d_info,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RT5631)
- {
- .type = "rt5631",
- .addr = 0x1a,
- .flags = 0,
- },
-#endif
-
-#if 0//def CONFIG_MFD_RK610
- {
- .type = "rk610_ctl",
- .addr = 0x40,
- .flags = 0,
- },
-#ifdef CONFIG_RK610_TVOUT
- {
- .type = "rk610_tvout",
- .addr = 0x42,
- .flags = 0,
- },
-#endif
-#ifdef CONFIG_HDMI_RK610
- {
- .type = "rk610_hdmi",
- .addr = 0x46,
- .flags = 0,
- .irq = RK29_PIN5_PA2,
- },
-#endif
-#ifdef CONFIG_SND_SOC_RK610
- {//RK610_CODEC addr from 0x60 to 0x80 (0x60~0x80)
- .type = "rk610_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- .platform_data = &rk610_codec_pdata,
- },
-#endif
-#endif
-
-};
-#endif
-int __sramdata g_pmic_type = 0;
-#ifdef CONFIG_I2C1_RK30
-#ifdef CONFIG_MFD_WM831X_I2C
-#include "board-rk30-sdk-wm8326.c"
-#endif
-#ifdef CONFIG_MFD_TPS65910
-#define TPS65910_HOST_IRQ RK30_PIN6_PA4
-#include "board-rk30-sdk-tps65910.c"
-#endif
-#endif
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_MFD_WM831X_I2C)
- {
- .type = "wm8326",
- .addr = 0x34,
- .flags = 0,
- .irq = RK30_PIN6_PA4,
- .platform_data = &wm831x_platdata,
- },
-#endif
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-#if defined (CONFIG_BATTERY_OZ8806)
- {
- .type = "oz8806",
- .addr = 0x2f,
- .flags = 0,
- },
-#endif
-#ifdef CONFIG_MFD_RK610
- {
- .type = "rk610_ctl",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#ifdef CONFIG_RK610_TVOUT
- {
- .type = "rk610_tvout",
- .addr = 0x42,
- .flags = 0,
- },
-#endif
-#ifdef CONFIG_HDMI_RK610
- {
- .type = "rk610_hdmi",
- .addr = 0x46,
- .flags = 0,
- .irq = RK29_PIN5_PA2,
- },
-#endif
-#ifdef CONFIG_SND_SOC_RK610
- {//RK610_CODEC addr from 0x60 to 0x80 (0x60~0x80)
- .type = "rk610_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- .platform_data = &rk610_codec_pdata,
- },
-#endif
-};
-//#endif
-
-void __sramfunc board_pmu_suspend(void)
-{
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_suspend();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_suspend();
- #endif
-}
-
-void __sramfunc board_pmu_resume(void)
-{
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_resume();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_resume();
- #endif
-}
-
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-#if defined (CONFIG_TOUCHSCREEN_GT8XX)
- {
- .type = "Goodix-TS",
- .addr = 0x55,
- .flags = 0,
- .irq = RK30_PIN4_PC2,
- .platform_data = &goodix_info,
- },
-#endif
-#if defined(CONFIG_TOUCHSCREEN_CT36X)
-{
- .type ="ct3610_ts",
- .addr =0x01,
- .flags =0,
- .irq = RK30_PIN4_PC2,
- .platform_data = &ct3610_info,
-},
-#endif
-#if defined (CONFIG_LS_CM3217)
- {
- .type = "light_cm3217",
- .addr = 0x10,
- .flags = 0,
- .platform_data = &cm3217_info,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C4_RK30
-static struct i2c_board_info __initdata i2c4_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO// RK30_PIN2_PD6 //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO//RK30_PIN2_PD7 //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- //set iomux (gpio) here
- //rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME, GPIO2D_GPIO2D7);
- //rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME, GPIO2D_GPIO2D6);
-
- return 0;
-}
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C4_RK30
- i2c_register_board_info(4, i2c4_info, ARRAY_SIZE(i2c4_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(5, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-
-#define POWER_ON_PIN RK30_PIN6_PB0 //power_hold
-static void rk30_pm_power_off(void)
-{
- printk(KERN_ERR "rk30_pm_power_off start...\n");
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
- #if defined(CONFIG_MFD_WM831X)
- if(g_pmic_type == PMIC_TYPE_WM8326)
- {
- wm831x_set_bits(Wm831x,WM831X_GPIO_LEVEL,0x0001,0x0000); //set sys_pwr 0
- wm831x_device_shutdown(Wm831x);//wm8326 shutdown
- }
- #endif
- #if defined(CONFIG_MFD_TPS65910)
- if(g_pmic_type == PMIC_TYPE_TPS65910)
- {
- tps65910_device_shutdown();//tps65910 shutdown
- }
- #endif
-
- while (1);
-}
-
-static void __init machine_rk30_board_init(void)
-{
- avs_init();
- gpio_request(POWER_ON_PIN, "poweronpin");
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
- pm_power_off = rk30_pm_power_off;
-
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- board_usb_detect_init(RK30_PIN6_PA3);
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- rk29sdk_wifi_bt_gpio_control_init();
-#endif
-}
-
-static void __init rk30_reserve(void)
-{
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0", RK30_FB0_MEM_SIZE);
- resource_fb[0].end = resource_fb[0].start + RK30_FB0_MEM_SIZE - 1;
-#ifdef CONFIG_FB_WORK_IPP // alloc ipp buf for rotate
- resource_fb[1].start = board_mem_reserve_add("ipp buf",RK30_IPP_MEM_SIZE);
- resource_fb[1].end = resource_fb[1].start + RK30_IPP_MEM_SIZE - 1;
-#endif
-#ifdef CONFIG_LCDC1_THREE_BUFFER
- resource_fb[2].start = board_mem_reserve_add("fb2", RK30_FB1_MEM_SIZE);
- resource_fb[2].end = resource_fb[2].start + RK30_FB1_MEM_SIZE - 1;
-#endif
-#endif
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
- board_mem_reserved();
-}
-
-/**
- * dvfs_cpu_logic_table: table for arm and logic dvfs
- * @frequency : arm frequency
- * @cpu_volt : arm voltage depend on frequency
- * @logic_volt : logic voltage arm requests depend on frequency
- * comments : min arm/logic voltage
- */
-static struct dvfs_arm_table dvfs_cpu_logic_table[] = {
- {.frequency = 252 * 1000, .cpu_volt = 1075 * 1000, .logic_volt = 1125 * 1000},//0.975V/1.000V
- {.frequency = 504 * 1000, .cpu_volt = 1100 * 1000, .logic_volt = 1125 * 1000},//0.975V/1.000V
- {.frequency = 816 * 1000, .cpu_volt = 1125 * 1000, .logic_volt = 1150 * 1000},//1.000V/1.025V
- {.frequency = 1008 * 1000, .cpu_volt = 1125 * 1000, .logic_volt = 1150 * 1000},//1.025V/1.050V
- {.frequency = 1200 * 1000, .cpu_volt = 1175 * 1000, .logic_volt = 1200 * 1000},//1.100V/1.050V
- {.frequency = 1272 * 1000, .cpu_volt = 1225 * 1000, .logic_volt = 1200 * 1000},//1.150V/1.100V
- {.frequency = 1416 * 1000, .cpu_volt = 1300 * 1000, .logic_volt = 1200 * 1000},//1.225V/1.100V
- {.frequency = 1512 * 1000, .cpu_volt = 1350 * 1000, .logic_volt = 1250 * 1000},//1.300V/1.150V
- {.frequency = 1608 * 1000, .cpu_volt = 1425 * 1000, .logic_volt = 1300 * 1000},//1.325V/1.175V
- {.frequency = CPUFREQ_TABLE_END},
-};
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
-{.frequency = 266 * 1000, .index = 1050 * 1000},
-{.frequency = 400 * 1000, .index = 1275 * 1000},
-{.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
-{.frequency = 300 * 1000, .index = 1050 * 1000},
-{.frequency = 400 * 1000, .index = 1125 * 1000},
-{.frequency = CPUFREQ_TABLE_END},
-};
-
-
-
-#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
-static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
-static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
-
-void __init board_clock_init(void)
-{
- rk30_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
- dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
-}
-
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk30_fixup,
- .reserve = &rk30_reserve,
- .map_io = rk30_map_io,
- .init_irq = rk30_init_irq,
- .timer = &rk30_timer,
- .init_machine = machine_rk30_board_init,
-MACHINE_END
+++ /dev/null
-#include <mach/gpio.h>
-#include <plat/key.h>
-
-#define EV_ENCALL KEY_F4
-#define EV_MENU KEY_F1
-
-#define PRESS_LEV_LOW 1
-#define PRESS_LEV_HIGH 0
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "menu",
- .code = EV_MENU,
- .gpio = RK30_PIN0_PD0,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .gpio = RK30_PIN4_PC4,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .gpio = RK30_PIN4_PC5,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .gpio = RK30_PIN0_PD2,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "search",
- .code = KEY_SEARCH,
- .gpio = RK30_PIN0_PD1,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .gpio = RK30_PIN0_PD3,
- .active_low = PRESS_LEV_LOW,
- },
-#if 0
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK30_PIN6_PA2,
- .active_low = PRESS_LEV_LOW,
- //.code_long_press = EV_ENCALL,
- .wakeup = 1,
- },
-#endif
- {
- .desc = "camera",
- .code = KEY_CAMERA,
- .gpio = RK30_PIN0_PD4,
- .active_low = PRESS_LEV_LOW,
- },
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = 1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
+++ /dev/null
-/* arch/arm/mach-rk30/board-rk30-sdk.c
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <mach/dvfs.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <linux/mpu.h>
-#include <linux/fb.h>
-#include <linux/wimo.h>
-
-#if defined(CONFIG_HDMI_RK30)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#include <linux/regulator/fixed.h>
-#include <linux/mfd/wm8994/pdata.h>
-#include <linux/regulator/machine.h>
-#include "../../../drivers/headset_observe/rk_headset.h"
-#include <linux/regulator/rk29-pwm-regulator.h>
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-#if defined(CONFIG_ANDROID_TIMED_GPIO)
-#include "../../../drivers/staging/android/timed_gpio.h"
-#endif
-#if defined(CONFIG_BACKLIGHT_AW9364)
-#include "../../../drivers/video/backlight/aw9364_bl.h"
-#endif
-#if defined(CONFIG_RK29_SC8800)
-#include "../../../drivers/tty/serial/sc8800.h"
-#endif
-#if defined(CONFIG_TDSC8800)
-#include <linux/mtk23d.h>
-#endif
-#if defined(CONFIG_SMS_SPI_ROCKCHIP)
-#include "../../../drivers/cmmb/siano/smsspiphy.h"
-#endif
-
-
-#define RK30_FB0_MEM_SIZE 8*SZ_1M
-
-#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Macro Define Begin ------------------------*/
-/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
-#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_MT9T111 /* back camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_0 0x78
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 4
-#define CONFIG_SENSOR_CIF_INDEX_0 1
-#define CONFIG_SENSOR_ORIENTATION_0 90
-#define CONFIG_SENSOR_POWER_PIN_0 RK30_PIN4_PC6
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 RK30_PIN1_PD6
-#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_H
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_H
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000
-
-#define CONFIG_SENSOR_01 RK29_CAM_SENSOR_OV5642 /* back camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_01 0x00
-#define CONFIG_SENSOR_CIF_INDEX_01 1
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 4
-#define CONFIG_SENSOR_ORIENTATION_01 90
-#define CONFIG_SENSOR_POWER_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_01 RK30_PIN1_PD6
-#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_01 30000
-
-#define CONFIG_SENSOR_02 RK29_CAM_SENSOR_OV5640 /* back camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_02 0x00
-#define CONFIG_SENSOR_CIF_INDEX_02 1
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 4
-#define CONFIG_SENSOR_ORIENTATION_02 90
-#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_02 RK30_PIN1_PD6
-#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000
-
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_GC0309 /* front camera sensor 0 */
-#define CONFIG_SENSOR_IIC_ADDR_1 0x42
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 3
-#define CONFIG_SENSOR_CIF_INDEX_1 0
-#define CONFIG_SENSOR_ORIENTATION_1 270
-#define CONFIG_SENSOR_POWER_PIN_1 RK30_PIN4_PC6
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_1 RK30_PIN1_PB7
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_H
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000
-
-#define CONFIG_SENSOR_11 RK29_CAM_SENSOR_OV2659 /* front camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_11 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 3
-#define CONFIG_SENSOR_CIF_INDEX_1 0
-#define CONFIG_SENSOR_ORIENTATION_11 270
-#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_11 RK30_PIN1_PB7
-#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_11 30000
-
-#define CONFIG_SENSOR_12 RK29_CAM_SENSOR_OV2655 /* front camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_12 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 3
-#define CONFIG_SENSOR_CIF_INDEX_1 0
-#define CONFIG_SENSOR_ORIENTATION_12 270
-#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_12 RK30_PIN1_PB7
-#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_12 30000
-
-
-#endif //#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk30_camera.c"
-/*---------------- Camera Sensor Macro Define End ---------*/
-
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#define CONFIG_SENSOR_POWER_IOCTL_USR 0
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_RESET_IOCTL_USR
-static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
-static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-
-#if CONFIG_SENSOR_IIC_ADDR_0
-static struct reginfo_t rk_init_data_sensor_reg_0[] =
-{
- {0x0000, 0x00,0,0}
- };
-static struct reginfo_t rk_init_data_sensor_winseqreg_0[] ={
- {0x0000, 0x00,0,0}
- };
-#endif
-
-#if CONFIG_SENSOR_IIC_ADDR_1
-static struct reginfo_t rk_init_data_sensor_reg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] =
-{
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,//rk_init_data_sensor_reg_0,
- .rk_sensor_init_winseq = NULL,//rk_init_data_sensor_winseqreg_0,
- .rk_sensor_winseq_size = 0,//sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t),
- },{
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,//rk_init_data_sensor_reg_1,
- .rk_sensor_init_winseq = NULL,//rk_init_data_sensor_winseqreg_1,
- .rk_sensor_winseq_size = 0,//sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t),
- }
-
- };
-#include "../../../drivers/media/video/rk30_camera.c"
-
-#endif /* CONFIG_VIDEO_RK29 */
-
-#if defined(CONFIG_TOUCHSCREEN_ILI2102_IIC)
-#include "../../../drivers/input/touchscreen/ili2102_ts.h"
-#define TOUCH_GPIO_INT RK30_PIN4_PC2
-#define TOUCH_GPIO_RESET RK30_PIN4_PD0
-static struct ili2102_platform_data ili2102_info = {
- .model = 2102,
- .swap_xy = 0,
- .x_min = 0,
- .x_max = 480,
- .y_min = 0,
- .y_max = 800,
- .gpio_reset = TOUCH_GPIO_RESET,
- .gpio_reset_active_low = 1,
- .gpio_pendown = TOUCH_GPIO_INT,
- .pendown_iomux_name = GPIO4C2_SMCDATA2_TRACEDATA2_NAME,
- .resetpin_iomux_name = GPIO4D0_SMCDATA8_TRACEDATA8_NAME,
- .pendown_iomux_mode = GPIO4C_GPIO4C2,
- .resetpin_iomux_mode = GPIO4D_GPIO4D0,
-};
-#endif
-
-
-#if defined(CONFIG_TOUCHSCREEN_GT8XX)
-#define TOUCH_RESET_PIN RK30_PIN4_PD0
-#define TOUCH_PWR_PIN INVALID_GPIO
-int goodix_init_platform_hw(void)
-{
- int ret;
-
- rk30_mux_api_set(GPIO4D0_SMCDATA8_TRACEDATA8_NAME, GPIO4D_GPIO4D0);
- rk30_mux_api_set(GPIO4C2_SMCDATA2_TRACEDATA2_NAME, GPIO4C_GPIO4C2);
- printk("%s:0x%x,0x%x\n",__func__,rk30_mux_api_get(GPIO4D0_SMCDATA8_TRACEDATA8_NAME),rk30_mux_api_get(GPIO4C2_SMCDATA2_TRACEDATA2_NAME));
-
- if (TOUCH_PWR_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_PWR_PIN, "goodix power pin");
- if (ret != 0) {
- gpio_free(TOUCH_PWR_PIN);
- printk("goodix power error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_PWR_PIN, 0);
- gpio_set_value(TOUCH_PWR_PIN, GPIO_LOW);
- msleep(100);
- }
-
- if (TOUCH_RESET_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_RESET_PIN, "goodix reset pin");
- if (ret != 0) {
- gpio_free(TOUCH_RESET_PIN);
- printk("goodix gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- gpio_set_value(TOUCH_RESET_PIN, GPIO_LOW);
- msleep(10);
- gpio_set_value(TOUCH_RESET_PIN, GPIO_HIGH);
- msleep(500);
- }
- return 0;
-}
-
-struct goodix_platform_data goodix_info = {
- .model = 8105,
- .irq_pin = RK30_PIN4_PC2,
- .rest_pin = TOUCH_RESET_PIN,
- .init_platform_hw = goodix_init_platform_hw,
-};
-#endif
-
-#if defined(CONFIG_RK29_SC8800)
-static int sc8800_io_init(void)
-{
- rk30_mux_api_set(GPIO2B5_LCDC1DATA13_SMCADDR17_HSADCDATA8_NAME, GPIO2B_GPIO2B5);
- rk30_mux_api_set(GPIO2A2_LCDCDATA2_SMCADDR6_NAME, GPIO2A_GPIO2A2);
- return 0;
-}
-
-static int sc8800_io_deinit(void)
-{
-
- return 0;
-}
-
-
-static struct plat_sc8800 sc8800_plat_data = {
- .slav_rts_pin = RK30_PIN6_PA0,
- .slav_rdy_pin = RK30_PIN2_PB5,
- .master_rts_pin = RK30_PIN6_PA1,
- .master_rdy_pin = RK30_PIN2_PA2,
- //.poll_time = 100,
- .io_init = sc8800_io_init,
- .io_deinit = sc8800_io_deinit,
-};
-
-static struct rk29xx_spi_chip sc8800_spi_chip = {
- //.poll_mode = 1,
- .enable_dma = 1,
-};
-
-#endif
-#if defined(CONFIG_SMS_SPI_ROCKCHIP)
-#define CMMB_1186_SPIIRQ RK30_PIN4_PB7
-#define CMMB_1186_RESET RK30_PIN0_PD5
-
-void cmmb_io_init_mux(void)
-{
-// rk30_mux_api_set(GPIO1A4_UART1SIN_SPI0CSN0_NAME,GPIO1A_GPIO1A4);
-
-}
-void cmmb_io_set_for_pm(void)
-{
- printk("entering cmmb_io_set_for_pm\n");
- rk30_mux_api_set(GPIO0D5_I2S22CHSDO_SMCADDR1_NAME,GPIO0D_GPIO0D5);
- gpio_request(CMMB_1186_RESET, NULL);//cmmb reset pin
- gpio_direction_output(CMMB_1186_RESET,0);
- rk30_mux_api_set(GPIO1A4_UART1SIN_SPI0CSN0_NAME,GPIO1A_GPIO1A4);
- gpio_request(RK30_PIN1_PA4, NULL);//cmmb cs pin
- gpio_direction_input(RK30_PIN1_PA4);
- gpio_pull_updown(RK30_PIN1_PA4, 0);
-}
-
-void cmmb_power_on_by_wm831x(void)
-{
- struct regulator *ldo;
-#if 0
- printk("entering cmmb_power_on_by_wm831x\n");
-
- rk29_mux_api_set(GPIO1A3_EMMCDETECTN_SPI1CS1_NAME,GPIO1L_SPI0_CSN1);
- gpio_request(RK29_PIN6_PD2, NULL);
- gpio_direction_output(RK29_PIN6_PD2,0);
- mdelay(200);
-
- ldo = regulator_get(NULL, "ldo8"); //cmmb
- regulator_set_voltage(ldo,1200000,1200000);
- regulator_set_suspend_voltage(ldo,1200000);
- regulator_enable(ldo);
- printk("%s set ldo8=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo9"); //cmmb
- regulator_set_voltage(ldo,3000000,3000000);
- regulator_set_suspend_voltage(ldo,3000000);
- regulator_enable(ldo);
- printk("%s set ldo9=%dmV end\n", __FUNCTION__, regulator_get_voltage(ldo));
- regulator_put(ldo);
-
- mdelay(200);
- gpio_direction_output(RK29_PIN6_PD2,1);
-#endif
-}
-
-void cmmb_power_down_by_wm831x(void)
-{
- struct regulator* ldo;
-#if 0
- printk("entering cmmb_power_down_by_wm831x\n");
-
- ldo = regulator_get(NULL, "ldo8");
- regulator_set_voltage(ldo,0,0);
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo9");
- regulator_set_voltage(ldo,0,0);
- regulator_disable(ldo);
- regulator_put(ldo);
-#endif
-}
-
-static struct cmmb_io_def_s cmmb_io = {
- .cmmb_pw_en = INVALID_GPIO,
- .cmmb_pw_dwn = INVALID_GPIO,
- .cmmb_pw_rst = CMMB_1186_RESET,
- .cmmb_irq = CMMB_1186_SPIIRQ,
- .io_init_mux = cmmb_io_init_mux,
- .cmmb_io_pm = cmmb_io_set_for_pm,
- .cmmb_power_on = cmmb_power_on_by_wm831x,
- .cmmb_power_down = cmmb_power_down_by_wm831x
-};
-
-static struct rk29xx_spi_chip cmb_spi_chip = {
- //.poll_mode = 1,
- .enable_dma = 1,
-};
-
-#endif
-
-static struct spi_board_info board_spi_devices[] = {
-#if defined(CONFIG_RK29_SC8800)
- {
- .modalias = "sc8800",
- .bus_num = 1,
- .platform_data = &sc8800_plat_data,
- .max_speed_hz = 12*1000*1000,
- .chip_select = 0,
- .controller_data = &sc8800_spi_chip,
- },
-#endif
-
-#if defined(CONFIG_SMS_SPI_ROCKCHIP)
- {
- .modalias = "siano1186",
- .chip_select = 0,
- .max_speed_hz = 12*1000*1000,
- .bus_num = 0,
- .irq =CMMB_1186_SPIIRQ,
- .platform_data = &cmmb_io,
- .controller_data = &cmb_spi_chip,
- },
-#endif
-
-};
-/*****************************************************************************************
- * wm8994 codec
- * author: qjb@rock-chips.com
- *****************************************************************************************/
-#if defined(CONFIG_MFD_WM8994)
-static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = {
- REGULATOR_SUPPLY("DBVDD", "0-001a"),
- REGULATOR_SUPPLY("AVDD2", "0-001a"),
- REGULATOR_SUPPLY("CPVDD", "0-001a"),
-};
-
-static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = {
- REGULATOR_SUPPLY("SPKVDD1", "0-001a"),
- REGULATOR_SUPPLY("SPKVDD2", "0-001a"),
-};
-
-static struct regulator_init_data wm8994_fixed_voltage0_init_data = {
- .constraints = {
- .always_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage0_supplies),
- .consumer_supplies = wm8994_fixed_voltage0_supplies,
-};
-
-static struct regulator_init_data wm8994_fixed_voltage1_init_data = {
- .constraints = {
- .always_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage1_supplies),
- .consumer_supplies = wm8994_fixed_voltage1_supplies,
-};
-
-static struct fixed_voltage_config wm8994_fixed_voltage0_config = {
- .supply_name = "VCC_1.8V_PDA",
- .microvolts = 1800000,
- .gpio = -EINVAL,
- .init_data = &wm8994_fixed_voltage0_init_data,
-};
-
-static struct fixed_voltage_config wm8994_fixed_voltage1_config = {
- .supply_name = "V_BAT",
- .microvolts = 3700000,
- .gpio = -EINVAL,
- .init_data = &wm8994_fixed_voltage1_init_data,
-};
-
-static struct platform_device wm8994_fixed_voltage0 = {
- .name = "reg-fixed-voltage",
- .id = 0,
- .dev = {
- .platform_data = &wm8994_fixed_voltage0_config,
- },
-};
-
-static struct platform_device wm8994_fixed_voltage1 = {
- .name = "reg-fixed-voltage",
- .id = 1,
- .dev = {
- .platform_data = &wm8994_fixed_voltage1_config,
- },
-};
-
-static struct regulator_consumer_supply wm8994_avdd1_supply =
- REGULATOR_SUPPLY("AVDD1", "0-001a");
-
-static struct regulator_consumer_supply wm8994_dcvdd_supply =
- REGULATOR_SUPPLY("DCVDD", "0-001a");
-
-
-
-static struct regulator_init_data wm8994_ldo1_data = {
- .constraints = {
- .name = "AVDD1_3.0V",
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = 1,
- .consumer_supplies = &wm8994_avdd1_supply,
-};
-
-static struct regulator_init_data wm8994_ldo2_data = {
- .constraints = {
- .name = "DCVDD_1.0V",
- },
- .num_consumer_supplies = 1,
- .consumer_supplies = &wm8994_dcvdd_supply,
-};
-
-static struct wm8994_pdata wm8994_platform_data = {
-#if defined (CONFIG_GPIO_WM8994)
- .gpio_base = WM8994_GPIO_EXPANDER_BASE,
- //Fill value to initialize the GPIO
-// .gpio_defaults ={},
- /* configure gpio1 function: 0x0001(Logic level input/output) */
-// .gpio_defaults[0] = 0x0001,
- /* configure gpio3/4/5/7 function for AIF2 voice */
- .gpio_defaults[2] = 0x2100,
- .gpio_defaults[3] = 0x2100,
- .gpio_defaults[4] = 0xA100,
-// .gpio_defaults[6] = 0x0100,
- /* configure gpio8/9/10/11 function for AIF3 BT */
- .gpio_defaults[7] = 0xA100,
- .gpio_defaults[8] = 0x2100,
- .gpio_defaults[9] = 0x2100,
- .gpio_defaults[10] = 0x2100,
-#endif
-
- .ldo[0] = { RK30_PIN3_PA6, NULL, &wm8994_ldo1_data,GPIO3A6_SDMMC0RSTNOUT_NAME, GPIO3A_GPIO3A6}, /* XM0FRNB_2 */
- .ldo[1] = { 0, NULL, &wm8994_ldo2_data },
-
- .micdet_irq = 0,
- .irq_base = 0,
-
- .lineout1_diff = 1,
-// .BB_input_diff = 1,
-};
-#endif
-
-#ifdef CONFIG_RK_HEADSET_DET
-#define HEADSET_GPIO RK29_PIN4_PD2
-struct rk_headset_pdata rk_headset_info = {
- .Headset_gpio = RK30_PIN6_PA5,
- .headset_in_type= HEADSET_IN_HIGH,
- .Hook_gpio = RK30_PIN1_PB2,//Detection Headset--Must be set
- .hook_key_code = KEY_MEDIA,
-};
-
-struct platform_device rk_device_headset = {
- .name = "rk_headsetdet",
- .id = 0,
- .dev = {
- .platform_data = &rk_headset_info,
- }
-};
-#endif
-
-#if CONFIG_RK30_PWM_REGULATOR
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_core",
- }
-};
-
-static struct regulator_consumer_supply pwm_dcdc2_consumers[] = {
- {
- .supply = "vdd_cpu",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[2] =
-{
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
- {
- .constraints = {
- .name = "PWM_DCDC2",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc2_consumers),
- .consumer_supplies = pwm_dcdc2_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[2] = {
- {
- .pwm_id = 0,
- .pwm_gpio = RK30_PIN0_PA3,
- .pwm_iomux_name = GPIO0A3_PWM0_NAME,
- .pwm_iomux_pwm = GPIO0A_PWM0,
- .pwm_iomux_gpio = GPIO0A_GPIO0A3,
- .pwm_voltage = 1100000,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
- {
- .pwm_id = 2,
- .pwm_gpio = RK30_PIN0_PD6,
- .pwm_iomux_name = GPIO0D6_PWM2_NAME,
- .pwm_iomux_pwm = GPIO0D_PWM2,
- .pwm_iomux_gpio = GPIO0D_GPIO0D6,
- .pwm_voltage = 1100000,
- .init_data = &pwm_regulator_init_dcdc[1],
- },
-
-};
-
-
-struct platform_device pwm_regulator_device[2] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
- {
- .name = "pwm-voltage-regulator",
- .id = 1,
- .dev = {
- .platform_data = &pwm_regulator_info[1],
- }
- },
-
-};
-
-
-#endif
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_AW9364
-static int aw9364_backlight_io_init(void)
-{
- rk30_mux_api_set(GPIO4D2_SMCDATA10_TRACEDATA10_NAME, GPIO4D_GPIO4D2);
- return 0;
-}
-
-static int aw9364_backlight_io_deinit(void)
-{
- return 0;
-}
-struct aw9364_platform_data aw9364_bl_info = {
- .pin_en = RK30_PIN4_PD2,
- .io_init = aw9364_backlight_io_init,
- .io_deinit = aw9364_backlight_io_deinit,
-};
-
-struct platform_device aw9364_device_backlight = {
- .name = "aw9364_backlight",
- .id = -1,
- .dev = {
- .platform_data = &aw9364_bl_info,
- }
-};
-
-#endif
-
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-#define PWM_ID 0
-#define PWM_MUX_NAME GPIO0A3_PWM0_NAME
-#define PWM_MUX_MODE GPIO0A_PWM0
-#define PWM_MUX_MODE_GPIO GPIO0A_GPIO0A3
-#define PWM_GPIO RK30_PIN0_PA3
-#define PWM_EFFECT_VALUE 1
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-//#define BL_EN_MUX_NAME GPIOF34_UART3_SEL_NAME
-//#define BL_EN_MUX_MODE IOMUXB_GPIO1_B34
-
-#define BL_EN_PIN RK30_PIN6_PB3
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
-#ifdef LCD_DISP_ON_PIN
- // rk30_mux_api_set(BL_EN_MUX_NAME, BL_EN_MUX_MODE);
-
- ret = gpio_request(BL_EN_PIN, NULL);
- if (ret != 0) {
- gpio_free(BL_EN_PIN);
- }
-
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0;
-#ifdef LCD_DISP_ON_PIN
- gpio_free(BL_EN_PIN);
-#endif
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret = 0;
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- if (gpio_request(PWM_GPIO, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- gpio_direction_output(PWM_GPIO, GPIO_LOW);
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, !BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- gpio_free(PWM_GPIO);
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
-#ifdef LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, 1);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-#endif
-
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN RK30_PIN4_PC0
-
-static int mma8452_init_platform_hw(void)
-{
- rk30_mux_api_set(GPIO4C0_SMCDATA0_TRACEDATA0_NAME, GPIO4C_GPIO4C0);
-
- if (gpio_request(MMA8452_INT_PIN, NULL) != 0) {
- gpio_free(MMA8452_INT_PIN);
- printk("mma8452_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_pull_updown(MMA8452_INT_PIN, 1);
- return 0;
-}
-
-static struct gsensor_platform_data mma8452_info = {
- .model = 8452,
- .swap_xy = 0,
- .swap_xyz = 1,
- .init_platform_hw = mma8452_init_platform_hw,
- .orientation = {0, -1, 0, 0, 0, -1, -1, 0, 0},
-};
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
-static struct akm8975_platform_data akm8975_info =
-{
- .m_layout =
- {
- {
- {0, 1, 0},
- {-1, 0, 0},
- {0, 0, -1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-/*mpu3050*/
-#if defined (CONFIG_MPU_SENSORS_MPU3050)
-static struct mpu_platform_data mpu3050_data = {
- .int_config = 0x10,
- .orientation = { 1, 0, 0,0, 1, 0, 0, 0, 1 },
-};
-#endif
-
-/* accel */
-#if defined (CONFIG_MPU_SENSORS_MMA845X)
-static struct ext_slave_platform_data inv_mpu_mma845x_data = {
- .bus = EXT_SLAVE_BUS_SECONDARY,
- .adapt_num = 0,
- .orientation = {1, 0, 0, 0, 1, 0, 0, 0, 1},
-};
-#endif
-
-/* compass */
-#if defined (CONFIG_MPU_SENSORS_AK8975)
-static struct ext_slave_platform_data inv_mpu_ak8975_data = {
- .bus = EXT_SLAVE_BUS_PRIMARY,
- .adapt_num = 0,
- .orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
-};
-#endif
-
-
-#if defined(CONFIG_GYRO_L3G4200D)
-
-#include <linux/l3g4200d.h>
-#define L3G4200D_INT_PIN RK30_PIN4_PC3
-
-static int l3g4200d_init_platform_hw(void)
-{
- if (gpio_request(L3G4200D_INT_PIN, NULL) != 0) {
- gpio_free(L3G4200D_INT_PIN);
- printk("%s: request l3g4200d int pin error\n", __func__);
- return -EIO;
- }
- gpio_pull_updown(L3G4200D_INT_PIN, 1);
- return 0;
-}
-
-static struct l3g4200d_platform_data l3g4200d_info = {
- .orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
- .init = l3g4200d_init_platform_hw,
- .x_min = 40,//x_min,y_min,z_min = (0-100) according to hardware
- .y_min = 40,
- .z_min = 20,
-};
-
-#endif
-
-
-
-#ifdef CONFIG_LS_CM3217
-
-#define CM3217_POWER_PIN INVALID_GPIO
-#define CM3217_IRQ_PIN INVALID_GPIO
-static int cm3217_init_hw(void)
-{
-#if 0
- if (gpio_request(CM3217_POWER_PIN, NULL) != 0) {
- gpio_free(CM3217_POWER_PIN);
- printk("%s: request cm3217 power pin error\n", __func__);
- return -EIO;
- }
- gpio_pull_updown(CM3217_POWER_PIN, PullDisable);
-
- if (gpio_request(CM3217_IRQ_PIN, NULL) != 0) {
- gpio_free(CM3217_IRQ_PIN);
- printk("%s: request cm3217 int pin error\n", __func__);
- return -EIO;
- }
- gpio_pull_updown(CM3217_IRQ_PIN, PullDisable);
-#endif
- return 0;
-}
-
-static void cm3217_exit_hw(void)
-{
-#if 0
- gpio_free(CM3217_POWER_PIN);
- gpio_free(CM3217_IRQ_PIN);
-#endif
- return;
-}
-
-static struct cm3217_platform_data cm3217_info = {
- .irq_pin = CM3217_IRQ_PIN,
- .power_pin = CM3217_POWER_PIN,
- .init_platform_hw = cm3217_init_hw,
- .exit_platform_hw = cm3217_exit_hw,
-};
-#endif
-
-#ifdef CONFIG_FB_ROCKCHIP
-
-/*****************************************************************************************
- * lcd devices
- * author: zyw@rock-chips.com
- *****************************************************************************************/
-//#ifdef CONFIG_LCD_TD043MGEA1
-
-#define LCD_TXD_PIN RK30_PIN0_PB7
-#define LCD_CLK_PIN RK30_PIN0_PB6
-#define LCD_CS_PIN RK30_PIN0_PB5
-#define LCD_RST_PIN RK30_PIN4_PC7
-
-/*****************************************************************************************
-* frame buffer devices
-* author: zyw@rock-chips.com
-*****************************************************************************************/
-#define FB_ID 0
-#define FB_DISPLAY_ON_PIN INVALID_GPIO//RK29_PIN6_PD0
-#define FB_LCD_STANDBY_PIN INVALID_GPIO//RK29_PIN6_PD1
-#define FB_LCD_CABC_EN_PIN INVALID_GPIO//RK29_PIN6_PD2
-#define FB_MCU_FMK_PIN INVALID_GPIO
-
-#define FB_DISPLAY_ON_VALUE GPIO_HIGH
-#define FB_LCD_STANDBY_VALUE GPIO_HIGH
-
-
-//#endif
-static int rk29_lcd_io_init(void)
-{
- int ret = 0;
- //printk("rk29_lcd_io_init\n");
- //ret = gpio_request(LCD_RXD_PIN, NULL);
- ret = gpio_request(LCD_TXD_PIN, NULL);
- ret = gpio_request(LCD_CLK_PIN, NULL);
- ret = gpio_request(LCD_CS_PIN, NULL);
-
- rk30_mux_api_set(GPIO0B7_I2S8CHSDO3_NAME, GPIO0B_GPIO0B7);
- rk30_mux_api_set(GPIO0B6_I2S8CHSDO2_NAME, GPIO0B_GPIO0B6);
- rk30_mux_api_set(GPIO0B5_I2S8CHSDO1_NAME, GPIO0B_GPIO0B5);
-
-
- gpio_request(LCD_RST_PIN, NULL);
- gpio_direction_output(LCD_RST_PIN, 1);
- gpio_direction_output(LCD_RST_PIN, 0);
- usleep_range(5*1000, 5*1000);
- gpio_set_value(LCD_RST_PIN, 1);
- usleep_range(50*1000, 50*1000);
- gpio_free(LCD_RST_PIN);
-
- return ret;
-}
-
-#if defined (CONFIG_RK29_WORKING_POWER_MANAGEMENT)
-static int rk29_lcd_io_deinit(void)
-{
- int ret = 0;
-
- gpio_direction_output(LCD_TXD_PIN, 1);
- gpio_direction_output(LCD_CLK_PIN, 1);
-
- gpio_free(LCD_CS_PIN);
- gpio_free(LCD_CLK_PIN);
- gpio_free(LCD_TXD_PIN);
-
- return ret;
-}
-#else
-static int rk29_lcd_io_deinit(void)
-{
- int ret = 0;
- //printk("rk29_lcd_io_deinit\n");
- gpio_free(LCD_CS_PIN);
- gpio_free(LCD_CLK_PIN);
- gpio_free(LCD_TXD_PIN);
- //gpio_free(LCD_RXD_PIN);
-
- //rk30_mux_api_set(GPIO0B7_I2S8CHSDO3_NAME, GPIO0B_GPIO0B7);
- //rk30_mux_api_set(GPIO0B6_I2S8CHSDO2_NAME, GPIO0B_GPIO0B6);
- //rk30_mux_api_set(GPIO0B5_I2S8CHSDO1_NAME, GPIO0B_GPIO0B5);
-
- return ret;
-}
-#endif
-
-
-static struct rk29lcd_info rk29_lcd_info = {
- .txd_pin = LCD_TXD_PIN,
- .clk_pin = LCD_CLK_PIN,
- .cs_pin = LCD_CS_PIN,
- .io_init = rk29_lcd_io_init,
- .io_deinit = rk29_lcd_io_deinit,
-};
-
-
-
-#define LCD_EN_MUX_NAME GPIO4C7_SMCDATA7_TRACEDATA7_NAME
-#define LCD_EN_PIN RK30_PIN4_PC7
-#define LCD_EN_VALUE GPIO_HIGH
-
-static int rk_fb_io_init(void)
-{
- int ret = 0;
- rk30_mux_api_set(LCD_EN_MUX_NAME, GPIO4C_GPIO4C7);
- ret = gpio_request(LCD_EN_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_EN_PIN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_EN_PIN, 1);
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
- }
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
- gpio_set_value(LCD_EN_PIN, ~LCD_EN_VALUE);
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
- return 0;
-}
-
-
-#if defined(CONFIG_LCDC0_RK30)
-struct rk29fb_info lcdc0_screen_info = {
- .fb_id = FB_ID,
- .prop = PRMRY,
- .mcu_fmk_pin = FB_MCU_FMK_PIN,
- .lcd_info = &rk29_lcd_info,
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-};
-#endif
-#if defined(CONFIG_LCDC1_RK30)
-struct rk29fb_info lcdc1_screen_info = {
- #if defined(CONFIG_HDMI_RK30)
- .prop = EXTEND,
- .lcd_info = NULL,
- .set_screen_info = hdmi_set_info,
- #endif
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-#ifdef CONFIG_FB_WIMO
-static struct wimo_platform_data wimo_pdata = {
- .name = "wimo",
-};
-
-static struct platform_device wimo_device = {
- .name = "wimo",
- .id = -1,
- .dev = {
- .platform_data = &wimo_pdata,
- },
-};
-#endif
-
-
-#ifdef CONFIG_ANDROID_TIMED_GPIO
-static struct timed_gpio timed_gpios[] = {
- {
- .name = "vibrator",
- .gpio = RK30_PIN0_PA4,
- .max_timeout = 1000,
- .active_low = 0,
- .adjust_time =20, //adjust for diff product
- },
-};
-
-static struct timed_gpio_platform_data rk29_vibrator_info = {
- .num_gpios = 1,
- .gpios = timed_gpios,
-};
-
-static struct platform_device rk29_device_vibrator = {
- .name = "timed-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_vibrator_info,
- },
-
-};
-#endif
-
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
-static struct gpio_led rk29_leds[] = {
- {
- .name = "button-backlight",
- .gpio = RK30_PIN4_PD7,
- .default_trigger = "timer",
- .active_low = 0,
- .retain_state_suspended = 0,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- },
-};
-
-static struct gpio_led_platform_data rk29_leds_pdata = {
- .leds = rk29_leds,
- .num_leds = ARRAY_SIZE(rk29_leds),
-};
-
-static struct platform_device rk29_device_gpio_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_leds_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_RK_IRDA
-#define IRDA_IRQ_PIN RK30_PIN6_PA1
-
-static int irda_iomux_init(void)
-{
- int ret = 0;
-
- //irda irq pin
- ret = gpio_request(IRDA_IRQ_PIN, NULL);
- if (ret != 0) {
- gpio_free(IRDA_IRQ_PIN);
- printk(">>>>>> IRDA_IRQ_PIN gpio_request err \n ");
- }
- gpio_pull_updown(IRDA_IRQ_PIN, PullDisable);
- gpio_direction_input(IRDA_IRQ_PIN);
-
- return 0;
-}
-
-static int irda_iomux_deinit(void)
-{
- gpio_free(IRDA_IRQ_PIN);
- return 0;
-}
-
-static struct irda_info rk29_irda_info = {
- .intr_pin = IRDA_IRQ_PIN,
- .iomux_init = irda_iomux_init,
- .iomux_deinit = irda_iomux_deinit,
- //.irda_pwr_ctl = bu92747guw_power_ctl,
-};
-
-static struct platform_device irda_device = {
-#ifdef CONFIG_RK_IRDA_NET
- .name = "rk_irda",
-#else
- .name = "bu92747_irda",
-#endif
- .id = -1,
- .dev = {
- .platform_data = &rk29_irda_info,
- }
-};
-#endif
-
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and sdio.noted by xbw at 2012-03-05
-**************************************************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "board-rk30-phone-sdmmc.c"
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
-#define SDMMC0_WRITE_PROTECT_PIN RK30_PIN3_PB7 //According to your own project to set the value of write-protect-pin.
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
-#define SDMMC1_WRITE_PROTECT_PIN RK30_PIN3_PC7 //According to your own project to set the value of write-protect-pin.
-#endif
-
-#define RK29SDK_WIFI_SDIO_CARD_DETECT_N RK30_PIN6_PB2
-
-#endif //endif ---#ifdef CONFIG_SDMMC_RK29
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- rk30_mux_api_set(GPIO3B1_SDMMC0CMD_NAME, GPIO3B_SDMMC0_CMD);
- rk30_mux_api_set(GPIO3B0_SDMMC0CLKOUT_NAME, GPIO3B_SDMMC0_CLKOUT);
- rk30_mux_api_set(GPIO3B2_SDMMC0DATA0_NAME, GPIO3B_SDMMC0_DATA0);
- rk30_mux_api_set(GPIO3B3_SDMMC0DATA1_NAME, GPIO3B_SDMMC0_DATA1);
- rk30_mux_api_set(GPIO3B4_SDMMC0DATA2_NAME, GPIO3B_SDMMC0_DATA2);
- rk30_mux_api_set(GPIO3B5_SDMMC0DATA3_NAME, GPIO3B_SDMMC0_DATA3);
-
- rk30_mux_api_set(GPIO3B6_SDMMC0DETECTN_NAME, GPIO3B_GPIO3B6);
-
- rk30_mux_api_set(GPIO3A7_SDMMC0PWREN_NAME, GPIO3A_GPIO3A7);
- gpio_request(RK30_PIN3_PA7, "sdmmc-power");
- gpio_direction_output(RK30_PIN3_PA7, GPIO_LOW);
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- rk30_mux_api_set(GPIO3B6_SDMMC0DETECTN_NAME, GPIO3B_SDMMC0_DETECT_N);
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
- .detect_irq = INVALID_GPIO, // INVALID_GPIO
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
-#else
- .write_prt = INVALID_GPIO,
-#endif
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- rk30_mux_api_set(GPIO3C0_SMMC1CMD_NAME, GPIO3C_SMMC1_CMD);
- rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_NAME, GPIO3C_SDMMC1_CLKOUT);
- rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_NAME, GPIO3C_SDMMC1_DATA0);
- rk30_mux_api_set(GPIO3C2_SDMMC1DATA1_NAME, GPIO3C_SDMMC1_DATA1);
- rk30_mux_api_set(GPIO3C3_SDMMC1DATA2_NAME, GPIO3C_SDMMC1_DATA2);
- rk30_mux_api_set(GPIO3C4_SDMMC1DATA3_NAME, GPIO3C_SDMMC1_DATA3);
- //rk30_mux_api_set(GPIO3C6_SDMMC1DETECTN_NAME, GPIO3C_SDMMC1_DETECT_N);
-
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-#if 0
- .detect_irq = RK29SDK_WIFI_SDIO_CARD_DETECT_N,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
-#else
- .detect_irq = INVALID_GPIO,
- .enable_sd_wakeup = 0,
-#endif
-
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-/* bluetooth rfkill device */
-static struct platform_device rk29sdk_rfkill = {
- .name = "rk29sdk_rfkill",
- .id = -1,
-};
-
-/**************************************************************************************************
- * the end of setting for SDMMC devices
-**************************************************************************************************/
-
-/*************td modem sc8800 power control*************/
-
-#if defined(CONFIG_TDSC8800)
-#define BP_VOL_PIN RK30_PIN6_PB2
-
-static int tdsc8800_io_init(void)
-{
-
- return 0;
-}
-
-static int tdsc8800_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk2818_23d_data rk29_tdsc8800_info = {
- .io_init = tdsc8800_io_init,
- .io_deinit = tdsc8800_io_deinit,
- .bp_power = BP_VOL_PIN,
- .bp_power_active_low = 1,
-};
-struct platform_device rk29_device_tdsc8800 = {
- .name = "tdsc8800",
- .id = -1,
- .dev = {
- .platform_data = &rk29_tdsc8800_info,
- }
- };
-#endif
-
-
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_RK30_PWM_REGULATOR
- &pwm_regulator_device[0],
- &pwm_regulator_device[1],
-#endif
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- &rk29_device_backlight,
-#endif
-#ifdef CONFIG_BACKLIGHT_AW9364
- &aw9364_device_backlight,
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
- &device_fb,
-#endif
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_FB_WIMO
- &wimo_device,
-#endif
-#ifdef CONFIG_ANDROID_TIMED_GPIO
- &rk29_device_vibrator,
-#endif
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
- &rk29_device_gpio_leds,
-#endif
-#ifdef CONFIG_RK_IRDA
- &irda_device,
-#endif
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- &rk29sdk_wifi_device,
-#endif
-#ifdef CONFIG_BT
- &rk29sdk_rfkill,
-#endif
-#ifdef CONFIG_MFD_WM8994
- &wm8994_fixed_voltage0,
- &wm8994_fixed_voltage1,
-#endif
-#ifdef CONFIG_RK_HEADSET_DET
- &rk_device_headset,
-#endif
-#ifdef CONFIG_TDSC8800
- &rk29_device_tdsc8800,
-#endif
-
-};
-
-// i2c
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1c,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN4_PC1,
- .platform_data = &akm8975_info,
- },
-#endif
-#if defined (CONFIG_GYRO_L3G4200D)
- {
- .type = "l3g4200d_gryo",
- .addr = 0x69,
- .flags = 0,
- .irq = L3G4200D_INT_PIN,
- .platform_data = &l3g4200d_info,
- },
-#endif
-#if defined (CONFIG_MPU_SENSORS_MPU3050)
- {
- .type = "mpu3050",
- .addr = 0x68,
- .flags = 0,
- .irq = RK30_PIN4_PC3,
- .platform_data = &mpu3050_data,
- },
-#endif
-#if defined (CONFIG_MPU_SENSORS_MMA845X)
- {
- .type = "mma845x",
- .addr = 0x1c,
- .flags = 0,
- .irq = RK30_PIN4_PC0,
- .platform_data = &inv_mpu_mma845x_data,
- },
-#endif
-#if defined (CONFIG_MPU_SENSORS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN4_PC1,
- .platform_data = &inv_mpu_ak8975_data,
- },
-#endif
-
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RT5631)
- {
- .type = "rt5631",
- .addr = 0x1a,
- .flags = 0,
- },
-#endif
-
-#ifdef CONFIG_MFD_RK610
- {
- .type = "rk610_ctl",
- .addr = 0x40,
- .flags = 0,
- },
-#ifdef CONFIG_RK610_TVOUT
- {
- .type = "rk610_tvout",
- .addr = 0x42,
- .flags = 0,
- },
-#endif
-#ifdef CONFIG_HDMI_RK610
- {
- .type = "rk610_hdmi",
- .addr = 0x46,
- .flags = 0,
- .irq = RK29_PIN5_PA2,
- },
-#endif
-#ifdef CONFIG_SND_SOC_RK610
- {//RK610_CODEC addr from 0x60 to 0x80 (0x60~0x80)
- .type = "rk610_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
-#endif
-#endif
-#if defined (CONFIG_SND_SOC_WM8994)
- {
- .type = "wm8994",
- .addr = 0x1a,
- .flags = 0,
- #if defined(CONFIG_MFD_WM8994)
- .platform_data = &wm8994_platform_data,
- #endif
- },
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C1_RK30
-#if 0
-#include "board-rk30-phone-wm831x.c"
-
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_MFD_WM831X_I2C)
- {
- .type = "wm8310",
- .addr = 0x34,
- .flags = 0,
- .irq = RK30_PIN6_PA4,
- .platform_data = &wm831x_platdata,
- },
-#endif
-};
-#endif
-#endif
-
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-#if defined (CONFIG_TOUCHSCREEN_ILI2102_IIC)
- {
- .type = "ili2102_ts",
- .addr = 0x41,
- .flags = I2C_M_NEED_DELAY,
- .udelay = 100,
- .irq = TOUCH_GPIO_INT,
- .platform_data = &ili2102_info,
- },
-#endif
-
-#if defined (CONFIG_TOUCHSCREEN_GT8XX)
- {
- .type = "Goodix-TS",
- .addr = 0x55,
- .flags = 0,
- .irq = RK30_PIN4_PC2,
- .platform_data = &goodix_info,
- },
-#endif
-#if defined (CONFIG_LS_CM3217)
- {
- .type = "lightsensor",
- .addr = 0x10,
- .flags = 0,
- .irq = CM3217_IRQ_PIN,
- .platform_data = &cm3217_info,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C4_RK30
-static struct i2c_board_info __initdata i2c4_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-#include "board-rk30-phone-wm831x.c"
-
-#define I2C_SDA_PIN RK30_PIN2_PD7 //set sda_pin here
-#define I2C_SCL_PIN RK30_PIN2_PD6 //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- //set iomux (gpio) here
- rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME, GPIO2D_GPIO2D7);
- rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME, GPIO2D_GPIO2D6);
-
- return 0;
-}
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-#if defined (CONFIG_MFD_WM831X_I2C)
- {
- .type = "wm8310",
- .addr = 0x34,
- .flags = 0,
- .irq = RK30_PIN6_PA4,
- .platform_data = &wm831x_platdata,
- },
-#endif
-};
-#endif
-
-
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C4_RK30
- i2c_register_board_info(4, i2c4_info, ARRAY_SIZE(i2c4_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(5, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-
-}
-//end of i2c
-
-#define POWER_ON_PIN RK30_PIN6_PB0 //power_hold
-static void rk30_pm_power_off(void)
-{
- printk(KERN_ERR "rk30_pm_power_off start...\n");
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
-#if defined(CONFIG_MFD_WM831X)
- wm831x_device_shutdown(Wm831x);//wm8326 shutdown
-#endif
- while (1);
-}
-
-static void __init machine_rk30_board_init(void)
-{
- gpio_request(POWER_ON_PIN, "poweronpin");
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
- pm_power_off = rk30_pm_power_off;
-
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- board_usb_detect_init(RK30_PIN6_PA3);
-
-#if defined (CONFIG_MPU_SENSORS_MPU3050)
- rk30_mux_api_set(GPIO4C3_SMCDATA3_TRACEDATA3_NAME, GPIO4C_GPIO4C3);
-#endif
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- rk29sdk_wifi_bt_gpio_control_init();
-#endif
-}
-
-static void __init rk30_reserve(void)
-{
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0", RK30_FB0_MEM_SIZE);
- resource_fb[0].end = resource_fb[0].start + RK30_FB0_MEM_SIZE - 1;
- resource_fb[1].start = board_mem_reserve_add("ipp buf", RK30_FB0_MEM_SIZE);
- resource_fb[1].end = resource_fb[1].start + RK30_FB0_MEM_SIZE - 1;
- resource_fb[2].start = board_mem_reserve_add("fb2", RK30_FB0_MEM_SIZE);
- resource_fb[2].end = resource_fb[2].start + RK30_FB0_MEM_SIZE - 1;
-#endif
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
- board_mem_reserved();
-}
-
-/**
- * dvfs_cpu_logic_table: table for arm and logic dvfs
- * @frequency : arm frequency
- * @cpu_volt : arm voltage depend on frequency
- * @logic_volt : logic voltage arm requests depend on frequency
- * comments : min arm/logic voltage
- */
-static struct dvfs_arm_table dvfs_cpu_logic_table[] = {
- //{.frequency = 252 * 1000, .cpu_volt = 1050 * 1000, .logic_volt = 1050 * 1000},//0.975V/1.000V
- //{.frequency = 504 * 1000, .cpu_volt = 1050 * 1000, .logic_volt = 1050 * 1000},//0.975V/1.000V
- {.frequency = 816 * 1000, .cpu_volt = 1100 * 1000, .logic_volt = 1100 * 1000},
- {.frequency = 1008 * 1000, .cpu_volt = 1150 * 1000, .logic_volt = 1100 * 1000},
- {.frequency = 1200 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1100 * 1000},
- //{.frequency = 1272 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1150 * 1000},//1.150V/1.100V
- //{.frequency = 1416 * 1000, .cpu_volt = 1275 * 1000, .logic_volt = 1150 * 1000},//1.225V/1.100V
- //{.frequency = 1512 * 1000, .cpu_volt = 1325 * 1000, .logic_volt = 1200 * 1000},//1.300V/1.150V
- //{.frequency = 1608 * 1000, .cpu_volt = 1350 * 1000, .logic_volt = 1200 * 1000},//1.325V/1.175V
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
-static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
-static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
-
-void __init board_clock_init(void)
-{
- rk30_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
- dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
-}
-
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk30_fixup,
- .reserve = &rk30_reserve,
- .map_io = rk30_map_io,
- .init_irq = rk30_init_irq,
- .timer = &rk30_timer,
- .init_machine = machine_rk30_board_init,
-MACHINE_END
+++ /dev/null
-#include <mach/gpio.h>
-#include <plat/key.h>
-
-#define EV_ENCALL KEY_F4
-#define EV_MENU KEY_F1
-
-#define PRESS_LEV_LOW 1
-#define PRESS_LEV_HIGH 0
-
-static struct rk29_keys_button key_button[] = {
-#if 0
- {
- .desc = "menu",
- .code = EV_MENU,
- .gpio = RK30_PIN0_PD0,
- .active_low = PRESS_LEV_LOW,
- },
-#endif
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .gpio = RK30_PIN4_PC4,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .gpio = RK30_PIN4_PC5,
- .active_low = PRESS_LEV_LOW,
- },
-#if 0
-
- {
- .desc = "home",
- .code = KEY_HOME,
- .gpio = RK30_PIN0_PD2,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "search",
- .code = KEY_SEARCH,
- .gpio = RK30_PIN0_PD1,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .gpio = RK30_PIN0_PD3,
- .active_low = PRESS_LEV_LOW,
- },
-
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK30_PIN6_PA2,
- .active_low = PRESS_LEV_LOW,
- //.code_long_press = EV_ENCALL,
- .wakeup = 1,
- },
- {
- .desc = "camera",
- .code = KEY_CAMERA,
- .gpio = RK30_PIN0_PD4,
- .active_low = PRESS_LEV_LOW,
- },
-#endif
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = 1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
+++ /dev/null
-#include <mach/gpio.h>
-#include <plat/key.h>
-
-#define EV_ENCALL KEY_F4
-#define EV_MENU KEY_F1
-
-#define PRESS_LEV_LOW 1
-#define PRESS_LEV_HIGH 0
-
-static struct rk29_keys_button key_button[] = {
-#if 0
- {
- .desc = "menu",
- .code = EV_MENU,
- .gpio = RK30_PIN0_PD0,
- .active_low = PRESS_LEV_LOW,
- },
-#endif
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .gpio = RK30_PIN4_PC4,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .gpio = RK30_PIN4_PC5,
- .active_low = PRESS_LEV_LOW,
- },
-#if 0
-
- {
- .desc = "home",
- .code = KEY_HOME,
- .gpio = RK30_PIN0_PD2,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "search",
- .code = KEY_SEARCH,
- .gpio = RK30_PIN0_PD1,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .gpio = RK30_PIN0_PD3,
- .active_low = PRESS_LEV_LOW,
- },
-
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK30_PIN6_PA2,
- .active_low = PRESS_LEV_LOW,
- //.code_long_press = EV_ENCALL,
- .wakeup = 1,
- },
- {
- .desc = "camera",
- .code = KEY_CAMERA,
- .gpio = RK30_PIN0_PD4,
- .active_low = PRESS_LEV_LOW,
- },
-#endif
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = 1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
+++ /dev/null
-/*
- * Copyright (C) 2010 ROCKCHIP, Inc.
- * Author: roger_chen <cz@rock-chips.com>
- *
- * This program is the bluetooth device bcm4330's driver,
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/module.h>
-#include <linux/device.h>
-#include <linux/rfkill.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/interrupt.h>
-#include <linux/wakelock.h>
-#include <linux/fs.h>
-#include <asm/uaccess.h>
-#include <mach/gpio.h>
-#include <asm/irq.h>
-#include <mach/iomux.h>
-#include <linux/wakelock.h>
-#include <linux/timer.h>
-#include <mach/board.h>
-
-#if 0
-#define DBG(x...) printk(KERN_INFO "[BT_RFKILL]: "x)
-#else
-#define DBG(x...)
-#endif
-
-#define LOG(x...) printk(KERN_INFO "[BT_RFKILL]: "x)
-
-#ifdef CONFIG_BCM4329
-#define WIFI_BT_POWER_TOGGLE 1
-#else
-#define WIFI_BT_POWER_TOGGLE 0
-#endif
-
-#define BT_WAKE_LOCK_TIMEOUT 10 //s
-
-#define BT_AUTO_SLEEP_TIMEOUT 3
-
-/*
- * IO Configuration for RK29
- */
-#ifdef CONFIG_ARCH_RK29
-
-#define BT_WAKE_HOST_SUPPORT 0
-
-/* IO configuration */
-// BT power pin
-#define BT_GPIO_POWER RK29_PIN5_PD6
-#define IOMUX_BT_GPIO_POWER() rk29_mux_api_set(GPIO5D6_SDMMC1PWREN_NAME, GPIO5H_GPIO5D6);
-
-// BT reset pin
-#define BT_GPIO_RESET RK29_PIN6_PC4
-#define IOMUX_BT_GPIO_RESET()
-
-// BT wakeup pin
-#define BT_GPIO_WAKE_UP RK29_PIN6_PC5
-#define IOMUX_BT_GPIO_WAKE_UP()
-
-// BT wakeup host pin
-#define BT_GPIO_WAKE_UP_HOST
-#define IOMUX_BT_GPIO_WAKE_UP_HOST()
-
-//bt cts paired to uart rts
-#define UART_RTS RK29_PIN2_PA7
-#define IOMUX_UART_RTS_GPIO() rk29_mux_api_set(GPIO2A7_UART2RTSN_NAME, GPIO2L_GPIO2A7)
-#define IOMUX_UART_RTS() rk29_mux_api_set(GPIO2A7_UART2RTSN_NAME, GPIO2L_UART2_RTS_N)
-
-/*
- * IO Configuration for RK30
- */
-#elif defined (CONFIG_ARCH_RK30)
-
-#define BT_WAKE_HOST_SUPPORT 1
-
-/* IO configuration */
-// BT power pin
-#define BT_GPIO_POWER RK30_PIN4_PD5
-#define IOMUX_BT_GPIO_POWER rk30_mux_api_set(GPIO4D5_SMCDATA13_TRACEDATA13_NAME, GPIO4D_GPIO4D5)
-
-// BT reset pin
-#define BT_GPIO_RESET RK30_PIN3_PD1
-#define IOMUX_BT_GPIO_RESET rk30_mux_api_set(GPIO3D1_SDMMC1BACKENDPWR_NAME, GPIO3D_GPIO3D1)
-
-
-// BT wakeup pin
-#define BT_GPIO_WAKE_UP RK30_PIN3_PC6
-#define IOMUX_BT_GPIO_WAKE_UP() rk29_mux_api_set(GPIO3C6_SDMMC1DETECTN_NAME, GPIO3C_GPIO3C6);
-
-// BT wakeup host pin
-#define BT_GPIO_WAKE_UP_HOST RK30_PIN3_PD2
-#define IOMUX_BT_GPIO_WAKE_UP_HOST() rk29_mux_api_set(GPIO3D2_SDMMC1INTN_NAME, GPIO3D_GPIO3D2)
-#define BT_IRQ_WAKE_UP_HOST gpio_to_irq(BT_GPIO_WAKE_UP_HOST)
-
-//bt cts paired to uart rts
-#define UART_RTS RK30_PIN1_PA3
-#define IOMUX_UART_RTS_GPIO() rk29_mux_api_set(GPIO1A3_UART0RTSN_NAME, GPIO1A_GPIO1A3)
-#define IOMUX_UART_RTS() rk29_mux_api_set(GPIO1A3_UART0RTSN_NAME, GPIO1A_UART0_RTS_N)
-
-#endif
-
-struct bt_ctrl
-{
- struct rfkill *bt_rfk;
-#if BT_WAKE_HOST_SUPPORT
- struct timer_list tl;
- bool b_HostWake;
- struct wake_lock bt_wakelock;
-#endif
-};
-
-static const char bt_name[] =
-#if defined(CONFIG_RKWIFI)
- #if defined(CONFIG_RKWIFI_26M)
- "rk903_26M"
- #else
- "rk903"
- #endif
-#elif defined(CONFIG_BCM4329)
- "bcm4329"
-#elif defined(CONFIG_MV8787)
- "mv8787"
-#else
- "bt_default"
-#endif
-;
-
-#if WIFI_BT_POWER_TOGGLE
-extern int rk29sdk_bt_power_state;
-extern int rk29sdk_wifi_power_state;
-#endif
-
-struct bt_ctrl gBtCtrl;
-struct timer_list bt_sleep_tl;
-
-
-#if BT_WAKE_HOST_SUPPORT
-void resetBtHostSleepTimer(void)
-{
- mod_timer(&(gBtCtrl.tl),jiffies + BT_WAKE_LOCK_TIMEOUT*HZ);//ÔÙÖØÐÂÉèÖó¬Ê±Öµ¡£
-}
-
-void btWakeupHostLock(void)
-{
- if(gBtCtrl.b_HostWake == false){
- DBG("** Lock **\n");
- wake_lock(&(gBtCtrl.bt_wakelock));
- gBtCtrl.b_HostWake = true;
- }
-}
-
-void btWakeupHostUnlock(void)
-{
- if(gBtCtrl.b_HostWake == true){
- DBG("** UnLock **\n");
- wake_unlock(&(gBtCtrl.bt_wakelock)); //ÈÃϵͳ˯Ãß
- gBtCtrl.b_HostWake = false;
- }
-}
-
-static void timer_hostSleep(unsigned long arg)
-{
- DBG("b_HostWake=%d\n", gBtCtrl.b_HostWake);
- btWakeupHostUnlock();
-}
-
-void bcm4325_sleep(unsigned long bSleep);
-
-#ifdef CONFIG_PM
-static irqreturn_t bcm4329_wake_host_irq(int irq, void *dev)
-{
- DBG("%s\n",__FUNCTION__);
-
- btWakeupHostLock();
- resetBtHostSleepTimer();
- return IRQ_HANDLED;
-}
-
-static void rfkill_do_wakeup(struct work_struct *work)
-{
- // disable bt wakeup host
- DBG("** free irq\n");
- free_irq(BT_IRQ_WAKE_UP_HOST, NULL);
-
- DBG("Enable UART_RTS\n");
- gpio_set_value(UART_RTS, GPIO_LOW);
- IOMUX_UART_RTS();
-}
-
-static DECLARE_DELAYED_WORK(wakeup_work, rfkill_do_wakeup);
-
-static int bcm4329_rfkill_suspend(struct platform_device *pdev, pm_message_t state)
-{
- DBG("%s\n",__FUNCTION__);
-
- cancel_delayed_work(&wakeup_work);
-
-#ifdef CONFIG_BT_AUTOSLEEP
- bcm4325_sleep(1);
-#endif
-
- DBG("Disable UART_RTS\n");
- //To prevent uart to receive bt data when suspended
- IOMUX_UART_RTS_GPIO();
- gpio_request(UART_RTS, "uart_rts");
- gpio_set_value(UART_RTS, GPIO_HIGH);
-
- // enable bt wakeup host
- DBG("Request irq for bt wakeup host\n");
- if (0 == request_irq(BT_IRQ_WAKE_UP_HOST,
- bcm4329_wake_host_irq,
- IRQF_TRIGGER_FALLING,
- "bt_wake",
- NULL))
- enable_irq_wake(BT_IRQ_WAKE_UP_HOST);
- else
- LOG("Failed to request BT_WAKE_UP_HOST irq\n");
-
-#ifdef CONFIG_RFKILL_RESET
- extern void rfkill_set_block(struct rfkill *rfkill, bool blocked);
- rfkill_set_block(gBtCtrl.bt_rfk, true);
-#endif
-
- return 0;
-}
-
-static int bcm4329_rfkill_resume(struct platform_device *pdev)
-{
- DBG("%s\n",__FUNCTION__);
-
- // ϵͳÍ˳ö¶þ¼¶Ë¯ÃߺóÐèÒªÀµÍRTS£¬´Ó¶ø²ÅÔÊÐíBT·¢Êý¾Ý¹ýÀ´
- // µ«ÊÇÄ¿Ç°·¢ÏÖÔÚresumeº¯ÊýÖÐÖ±½ÓÀµÍRTS»áµ¼ÖÂBTÊý¾Ý¶ªÊ§
- // ËùÒÔÑÓ³Ù1sºóÔÙÀµÍRTS
- // ϵͳÍ˳ö¶þ¼¶Ë¯ÃßʱÊͷŵôBT_IRQ_WAKE_UP_HOST£¬ÔÚ˯ÃßʱºòÔÙ
- // ´ÎÉêÇ룬Ŀǰ·¢ÏÖÖжϻص÷º¯Êý±Èresume¸üÍíÖ´ÐУ¬Èç¹ûresume
- // ʱֱ½ÓfreeµôIRQ£¬»áµ¼ÖÂÖжϻص÷º¯Êý²»»á±»Ö´ÐУ¬
- DBG("delay 1s\n");
- schedule_delayed_work(&wakeup_work, HZ);
-
- return 0;
-}
-#else
-#define bcm4329_rfkill_suspend NULL
-#define bcm4329_rfkill_resume NULL
-#endif
-
-#endif
-
-void bcm4325_sleep(unsigned long bSleep)
-{
- DBG("*** bt sleep: %d ***\n", bSleep);
-#ifdef CONFIG_BT_AUTOSLEEP
- del_timer(&bt_sleep_tl);// cmy: È·±£ÔÚ»½ÐÑBTʱ£¬²»»áÒò´¥·¢bt_sleep_tl¶øÂíÉÏ˯Ãß
-#endif
-
- IOMUX_BT_GPIO_WAKE_UP();
- gpio_set_value(BT_GPIO_WAKE_UP, bSleep?GPIO_LOW:GPIO_HIGH);
-
-#ifdef CONFIG_BT_AUTOSLEEP
- if(!bSleep)
- mod_timer(&bt_sleep_tl, jiffies + BT_AUTO_SLEEP_TIMEOUT*HZ);//ÔÙÖØÐÂÉèÖó¬Ê±Öµ¡£
-#endif
-}
-
-static int bcm4329_set_block(void *data, bool blocked)
-{
- DBG("set blocked :%d\n", blocked);
-
- IOMUX_BT_GPIO_POWER;
- IOMUX_BT_GPIO_RESET;
-
- if (false == blocked) {
- gpio_set_value(BT_GPIO_POWER, GPIO_HIGH); /* bt power on */
- mdelay(20);
-
- gpio_set_value(BT_GPIO_RESET, GPIO_LOW);
- mdelay(20);
- gpio_set_value(BT_GPIO_RESET, GPIO_HIGH); /* bt reset deactive*/
-
- mdelay(20);
- bcm4325_sleep(0); // ensure bt is wakeup
-
- pr_info("bt turn on power\n");
- } else {
-#if WIFI_BT_POWER_TOGGLE
- if (!rk29sdk_wifi_power_state) {
-#endif
- gpio_set_value(BT_GPIO_POWER, GPIO_LOW); /* bt power off */
- mdelay(20);
- pr_info("bt shut off power\n");
-#if WIFI_BT_POWER_TOGGLE
- }else {
- pr_info("bt shouldn't shut off power, wifi is using it!\n");
- }
-#endif
-
- gpio_set_value(BT_GPIO_RESET, GPIO_LOW); /* bt reset active*/
- mdelay(20);
- }
-
-#if WIFI_BT_POWER_TOGGLE
- rk29sdk_bt_power_state = !blocked;
-#endif
- return 0;
-}
-
-static const struct rfkill_ops bcm4329_rfk_ops = {
- .set_block = bcm4329_set_block,
-};
-
-static int __devinit bcm4329_rfkill_probe(struct platform_device *pdev)
-{
- int rc = 0;
- bool default_state = true;
-
- DBG("Enter %s\n",__FUNCTION__);
-
- /* default to bluetooth off */
- bcm4329_set_block(NULL, default_state); /* blocked -> bt off */
-
- gBtCtrl.bt_rfk = rfkill_alloc(bt_name,
- NULL,
- RFKILL_TYPE_BLUETOOTH,
- &bcm4329_rfk_ops,
- NULL);
-
- if (!gBtCtrl.bt_rfk)
- {
- LOG("fail to rfkill_allocate\n");
- return -ENOMEM;
- }
-
- rfkill_set_states(gBtCtrl.bt_rfk, default_state, false);
-
- rc = rfkill_register(gBtCtrl.bt_rfk);
- if (rc)
- {
- LOG("failed to rfkill_register,rc=0x%x\n",rc);
- rfkill_destroy(gBtCtrl.bt_rfk);
- }
-
- gpio_request(BT_GPIO_POWER, NULL);
- gpio_request(BT_GPIO_RESET, NULL);
- gpio_request(BT_GPIO_WAKE_UP, NULL);
-
-#ifdef CONFIG_BT_AUTOSLEEP
- init_timer(&bt_sleep_tl);
- bt_sleep_tl.expires = 0;
- bt_sleep_tl.function = bcm4325_sleep;
- bt_sleep_tl.data = 1;
- add_timer(&bt_sleep_tl);
-#endif
-
-#if BT_WAKE_HOST_SUPPORT
- init_timer(&(gBtCtrl.tl));
- gBtCtrl.tl.expires = 0;
- gBtCtrl.tl.function = timer_hostSleep;
- add_timer(&(gBtCtrl.tl));
- gBtCtrl.b_HostWake = false;
-
- wake_lock_init(&(gBtCtrl.bt_wakelock), WAKE_LOCK_SUSPEND, "bt_wake");
-
- rc = gpio_request(BT_GPIO_WAKE_UP_HOST, "bt_wake");
- if (rc) {
- LOG("Failed to request BT_WAKE_UP_HOST\n");
- }
-
- IOMUX_BT_GPIO_WAKE_UP_HOST();
- gpio_pull_updown(BT_GPIO_WAKE_UP_HOST,GPIOPullUp);
- #endif
-
- LOG("bcm4329 module has been initialized,rc=0x%x\n",rc);
-
- return rc;
-}
-
-
-static int __devexit bcm4329_rfkill_remove(struct platform_device *pdev)
-{
- if (gBtCtrl.bt_rfk)
- rfkill_unregister(gBtCtrl.bt_rfk);
- gBtCtrl.bt_rfk = NULL;
-#if BT_WAKE_HOST_SUPPORT
- del_timer(&(gBtCtrl.tl));//ɾµô¶¨Ê±Æ÷
- btWakeupHostUnlock();
- wake_lock_destroy(&(gBtCtrl.bt_wakelock));
-#endif
-#ifdef CONFIG_BT_AUTOSLEEP
- del_timer(&bt_sleep_tl);
-#endif
-
- platform_set_drvdata(pdev, NULL);
-
- DBG("Enter %s\n",__FUNCTION__);
- return 0;
-}
-
-static struct platform_driver bcm4329_rfkill_driver = {
- .probe = bcm4329_rfkill_probe,
- .remove = __devexit_p(bcm4329_rfkill_remove),
- .driver = {
- .name = "rk29sdk_rfkill",
- .owner = THIS_MODULE,
- },
-#if BT_WAKE_HOST_SUPPORT
- .suspend = bcm4329_rfkill_suspend,
- .resume = bcm4329_rfkill_resume,
-#endif
-};
-
-/*
- * Module initialization
- */
-static int __init bcm4329_mod_init(void)
-{
- int ret;
- DBG("Enter %s\n",__FUNCTION__);
- ret = platform_driver_register(&bcm4329_rfkill_driver);
- LOG("ret=0x%x\n", ret);
- return ret;
-}
-
-static void __exit bcm4329_mod_exit(void)
-{
- platform_driver_unregister(&bcm4329_rfkill_driver);
-}
-
-module_init(bcm4329_mod_init);
-module_exit(bcm4329_mod_exit);
-MODULE_DESCRIPTION("bcm4329 Bluetooth driver");
-MODULE_AUTHOR("roger_chen cz@rock-chips.com, cmy@rock-chips.com");
-MODULE_LICENSE("GPL");
-
+++ /dev/null
-/* arch/arm/mach-rk30/board-rk30-sdk.c
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <mach/dvfs.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <linux/fb.h>
-
-#ifdef CONFIG_TOUCHSCREEN_SYNAPTICS_S3202
-#include <linux/interrupt.h>
-#include <linux/rmi.h>
-#endif
-#include <linux/sensor-dev.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-
-#if defined(CONFIG_HDMI_RK30)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-#include "../../../drivers/headset_observe/rk_headset.h"
-#include <linux/mfd/tlv320aic3262-core.h>
-#include <linux/mfd/tlv320aic3262-registers.h>
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-#if defined(CONFIG_ANDROID_TIMED_GPIO)
-#include "../../../drivers/staging/android/timed_gpio.h"
-#endif
-#include <linux/mtk23d.h>
-#include "../../../drivers/tty/serial/sc8800.h"
-#define BP_VOL_PIN RK30_PIN6_PB2
-#define RK30_FB0_MEM_SIZE 8*SZ_1M
-
-#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Macro Define Begin ------------------------*/
-/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
-
-#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_OV5640 /* back camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_0 0x78
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 3
-#define CONFIG_SENSOR_CIF_INDEX_0 0
-#define CONFIG_SENSOR_ORIENTATION_0 90
-#define CONFIG_SENSOR_POWER_PIN_0 RK30_PIN4_PC6
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 RK30_PIN1_PB6
-#define CONFIG_SENSOR_FALSH_PIN_0 RK30_PIN4_PD6
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_H
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_H
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000
-
-#define CONFIG_SENSOR_01 RK29_CAM_SENSOR_OV5642 /* back camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_01 0x00
-#define CONFIG_SENSOR_CIF_INDEX_01 1
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 4
-#define CONFIG_SENSOR_ORIENTATION_01 90
-#define CONFIG_SENSOR_POWER_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_01 RK30_PIN1_PD6
-#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_01 30000
-
-#define CONFIG_SENSOR_02 RK29_CAM_SENSOR_OV5640 /* back camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_02 0x00
-#define CONFIG_SENSOR_CIF_INDEX_02 1
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 4
-#define CONFIG_SENSOR_ORIENTATION_02 90
-#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_02 RK30_PIN1_PD6
-#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000
-
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_GT2005 /* front camera sensor 0 */
-#define CONFIG_SENSOR_IIC_ADDR_1 0x78
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 3
-#define CONFIG_SENSOR_CIF_INDEX_1 0
-#define CONFIG_SENSOR_ORIENTATION_1 270
-#define CONFIG_SENSOR_POWER_PIN_1 RK30_PIN4_PC6
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_1 RK30_PIN1_PB7
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_H
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_L
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000
-
-#define CONFIG_SENSOR_11 RK29_CAM_SENSOR_OV2659 /* front camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_11 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 3
-#define CONFIG_SENSOR_CIF_INDEX_11 0
-#define CONFIG_SENSOR_ORIENTATION_11 270
-#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_11 INVALID_GPIO//RK30_PIN1_PB7
-#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_11 30000
-
-#define CONFIG_SENSOR_12 RK29_CAM_SENSOR_OV2659//RK29_CAM_SENSOR_OV2655 /* front camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_12 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 3
-#define CONFIG_SENSOR_CIF_INDEX_12 0
-#define CONFIG_SENSOR_ORIENTATION_12 270
-#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_12 INVALID_GPIO//RK30_PIN1_PB7
-#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_12 30000
-
-
-#endif //#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk30_camera.c"
-/*---------------- Camera Sensor Macro Define End ---------*/
-
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#define CONFIG_SENSOR_POWER_IOCTL_USR 0
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 1
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_RESET_IOCTL_USR
-static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
-static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
-}
-#endif
-//hhb@rock-chips.com
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-//sgm3140 LED driver
-#define CONFIG_SENSOR_FALSH_EN_PIN_0 RK30_PIN4_PD6 //high:enable
-#define CONFIG_SENSOR_FALSH_MODE_PIN_0 RK30_PIN0_PD6 //high:FLASH, low:torch
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res, int on)
-{
- static int init_flag = 0;
- if(init_flag == 0) {
- gpio_request(CONFIG_SENSOR_FALSH_MODE_PIN_0, "camera_falsh_mode");
- rk30_mux_api_set(GPIO0D6_PWM2_NAME, GPIO0D_GPIO0D6);
- gpio_request(CONFIG_SENSOR_FALSH_EN_PIN_0, "camera_falsh_en");
- rk30_mux_api_set(GPIO4D6_SMCDATA14_TRACEDATA14_NAME, GPIO4D_GPIO4D6);
- init_flag = 1;
- }
- switch (on) {
- case Flash_Off: {
- gpio_direction_output(CONFIG_SENSOR_FALSH_EN_PIN_0, 0);
- gpio_direction_output(CONFIG_SENSOR_FALSH_MODE_PIN_0, 1);
- break;
- }
-
- case Flash_On: {
- gpio_direction_output(CONFIG_SENSOR_FALSH_EN_PIN_0, 1);
- gpio_direction_output(CONFIG_SENSOR_FALSH_MODE_PIN_0, 1);
- break;
- }
-
- case Flash_Torch: {
- gpio_direction_output(CONFIG_SENSOR_FALSH_EN_PIN_0, 1);
- gpio_direction_output(CONFIG_SENSOR_FALSH_MODE_PIN_0, 0);
- break;
- }
-
- default: {
- printk("%s..Flash command(%d) is invalidate \n",__FUNCTION__, on);
- gpio_direction_output(CONFIG_SENSOR_FALSH_EN_PIN_0, 0);
- break;
- }
- }
- return 0;
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-
-#if CONFIG_SENSOR_IIC_ADDR_0
-static struct reginfo_t rk_init_data_sensor_reg_0[] =
-{
- {0x0000, 0x00,0,0}
- };
-static struct reginfo_t rk_init_data_sensor_winseqreg_0[] ={
- {0x0000, 0x00,0,0}
- };
-#endif
-
-#if CONFIG_SENSOR_IIC_ADDR_1
-static struct reginfo_t rk_init_data_sensor_reg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_01
-static struct reginfo_t rk_init_data_sensor_reg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_02
-static struct reginfo_t rk_init_data_sensor_reg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_11
-static struct reginfo_t rk_init_data_sensor_reg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_12
-static struct reginfo_t rk_init_data_sensor_reg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] =
-{
- #if CONFIG_SENSOR_IIC_ADDR_0
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_0,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_1
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_1,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_01
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_01,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_02
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_02,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_11
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_11,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_12
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_12,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
-
- };
-#include "../../../drivers/media/video/rk30_camera.c"
-
-#endif /* CONFIG_VIDEO_RK29 */
-
-//hhb@rock-chips.com 2012-04-27
-
-#if defined(CONFIG_TOUCHSCREEN_FT5306)
-
-#define TOUCH_RESET_PIN RK30_PIN6_PB1
-#define TOUCH_INT_PIN RK30_PIN4_PD7
-int ft5306_init_platform_hw(void)
-{
-
- printk("ft5406_init_platform_hw\n");
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("ft5406_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("ift5406_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- rk30_mux_api_set(GPIO4D7_SMCDATA15_TRACEDATA15_NAME, 0);
-
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- mdelay(10);
- gpio_direction_input(TOUCH_INT_PIN);
- mdelay(10);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- msleep(300);
- return 0;
-
-}
-
-void ft5306_exit_platform_hw(void)
-{
- printk("ft5306_exit_platform_hw\n");
- gpio_free(TOUCH_RESET_PIN);
- gpio_free(TOUCH_INT_PIN);
-}
-
-int ft5306_platform_sleep(void)
-{
- //printk("ft5306_platform_sleep\n");
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- return 0;
-}
-
-int ft5306_platform_wakeup(void)
-{
- //printk("ft5306_platform_wakeup\n");
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- msleep(300);
- return 0;
-}
-
-struct ft5x0x_platform_data ft5306_info = {
-
- .init_platform_hw= ft5306_init_platform_hw,
- .exit_platform_hw= ft5306_exit_platform_hw,
- .ft5x0x_platform_sleep = ft5306_platform_sleep,
- .ft5x0x_platform_wakeup = ft5306_platform_wakeup,
-};
-
-
-#endif
-
-#if defined (CONFIG_TOUCHSCREEN_SYNAPTICS_S3202)
-
-#define TOUCH_RESET_PIN -1
-#define TOUCH_INT_PIN RK30_PIN4_PC2
-#define TOUCH_POWER_PIN -1
-#define TOUCH_IO_POWER_PIN -1
-
-struct syna_gpio_data {
- u16 gpio_number;
- char* gpio_name;
-};
-
-int syna_init_platform_hw(void)
-{
- return 0;
-}
-
-static int synaptics_touchpad_gpio_setup(void *gpio_data, bool configure)
-{
- int retval=0;
- struct syna_gpio_data *data = gpio_data;
-
- if (configure) {
- retval = gpio_request(data->gpio_number, "rmi4_attn");
- if (retval) {
- pr_err("%s: Failed to get attn gpio %d. Code: %d.",
- __func__, data->gpio_number, retval);
- return retval;
- }
- rk30_mux_api_set(GPIO4C2_SMCDATA2_TRACEDATA2_NAME, 0);
- retval = gpio_direction_input(data->gpio_number);
- if (retval) {
- pr_err("%s: Failed to setup attn gpio %d. Code: %d.",
- __func__, data->gpio_number, retval);
- gpio_free(data->gpio_number);
- }
- } else {
- printk("%s: No way to deconfigure gpio %d.",
- __func__, data->gpio_number);
- }
-
- return retval;
-
-}
-
-static struct syna_gpio_data s3202_gpiodata = {
- .gpio_number = TOUCH_INT_PIN,
- .gpio_name = "GPIO4_C2",
-};
-static unsigned char s3202_key_array[4]={ KEY_BACK, KEY_MENU, KEY_HOMEPAGE, KEY_SEARCH };
-
-struct rmi_f1a_button_map s3202_buttons = {
- .nbuttons = 4,
- .map = s3202_key_array,
-};
-
-static struct rmi_device_platform_data s3202_platformdata = {
- .sensor_name = "Espresso",
- .driver_name = "rmi_generic",
- .attn_gpio = TOUCH_INT_PIN,
- .attn_polarity = RMI_ATTN_ACTIVE_LOW,
- .level_triggered = false, /* For testing */
- .gpio_data = &s3202_gpiodata,
- .gpio_config = synaptics_touchpad_gpio_setup,
- .init_hw = syna_init_platform_hw,
- .axis_align = {
- .flip_x = 1,
- .flip_y = 1,
- .clip_X_low = 0,
- .clip_Y_low = 0,
- .clip_X_high = 0,
- .clip_Y_high = 0,
- },
- .f1a_button_map = &s3202_buttons,
-};
-
-#endif
-
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-#define PWM_ID 0
-#define PWM_MUX_NAME GPIO0A3_PWM0_NAME
-#define PWM_MUX_MODE GPIO0A_PWM0
-#define PWM_MUX_MODE_GPIO GPIO0A_GPIO0A3
-#define PWM_GPIO RK30_PIN0_PA3
-#define PWM_EFFECT_VALUE 0
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-#define BL_EN_MUX_NAME GPIO4D2_SMCDATA10_TRACEDATA10_NAME
-#define BL_EN_MUX_MODE GPIO4D_GPIO4D2
-#define BL_EN_PIN RK30_PIN4_PD2
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
-#ifdef LCD_DISP_ON_PIN
- rk30_mux_api_set(BL_EN_MUX_NAME, BL_EN_MUX_MODE);
- ret = gpio_request(BL_EN_PIN, NULL);
- if (ret != 0) {
- gpio_free(BL_EN_PIN);
- }
-
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0;
-#ifdef LCD_DISP_ON_PIN
- gpio_free(BL_EN_PIN);
-#endif
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret = 0;
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- if (gpio_request(PWM_GPIO, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- gpio_direction_output(PWM_GPIO, GPIO_HIGH);
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, !BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- gpio_direction_output(PWM_GPIO, GPIO_LOW);
- gpio_free(PWM_GPIO);
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
-#ifdef LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, 1);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-#endif
-
-#ifdef CONFIG_RK29_SUPPORT_MODEM
-
-#define RK30_MODEM_POWER RK30_PIN4_PD1
-#define RK30_MODEM_POWER_IOMUX rk29_mux_api_set(GPIO4D1_SMCDATA9_TRACEDATA9_NAME, GPIO4D_GPIO4D1)
-
-static int rk30_modem_io_init(void)
-{
- printk("%s\n", __FUNCTION__);
- RK30_MODEM_POWER_IOMUX;
-
- return 0;
-}
-
-static struct rk29_io_t rk30_modem_io = {
- .io_addr = RK30_MODEM_POWER,
- .enable = GPIO_HIGH,
- .disable = GPIO_LOW,
- .io_init = rk30_modem_io_init,
-};
-
-static struct platform_device rk30_device_modem = {
- .name = "rk30_modem",
- .id = -1,
- .dev = {
- .platform_data = &rk30_modem_io,
- }
-};
-#endif
-#if defined(CONFIG_RK29_SC8800)
-// tdsc8800
-static int tdsc8800_io_init(void)
-{
-
- return 0;
-}
-
-static int tdsc8800_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk2818_23d_data rk29_tdsc8800_info = {
- .io_init = tdsc8800_io_init,
- .io_deinit = tdsc8800_io_deinit,
- .bp_power = BP_VOL_PIN,
- .bp_power_active_low = 1,
-};
-struct platform_device rk29_device_tdsc8800 = {
- .name = "tdsc8800",
- .id = -1,
- .dev = {
- .platform_data = &rk29_tdsc8800_info,
- }
- };
-//sc8800
-static int sc8800_io_init(void)
-{
- rk30_mux_api_set(GPIO2B5_LCDC1DATA13_SMCADDR17_HSADCDATA8_NAME, GPIO2B_GPIO2B5);
- rk30_mux_api_set(GPIO2A2_LCDCDATA2_SMCADDR6_NAME, GPIO2A_GPIO2A2);
-
- rk30_mux_api_set(GPIO2C2_LCDC1DATA18_SMCBLSN1_HSADCDATA5_NAME, GPIO2C_GPIO2C2);//AP_ASK_BP_TEST1
- gpio_request(RK30_PIN2_PC2, NULL);
- gpio_direction_output(RK30_PIN2_PC2, 0);
- gpio_request(RK30_PIN6_PB0, NULL);//AP_ON/OFF_BP
- gpio_direction_output(RK30_PIN6_PB0, 0);
-
-
- rk30_mux_api_set(GPIO2C3_LCDC1DATA19_SPI1CLK_HSADCDATA0_NAME, GPIO2C_SPI1_CLK);//spi 1
- rk30_mux_api_set(GPIO2C4_LCDC1DATA20_SPI1CSN0_HSADCDATA1_NAME, GPIO2C_SPI1_CSN0);
- rk30_mux_api_set(GPIO2C5_LCDC1DATA21_SPI1TXD_HSADCDATA2_NAME, GPIO2C_SPI1_TXD);
- rk30_mux_api_set(GPIO2C6_LCDC1DATA22_SPI1RXD_HSADCDATA3_NAME, GPIO2C_SPI1_RXD);
- return 0;
-}
-
-static int sc8800_io_deinit(void)
-{
-
- return 0;
-}
-
-static struct plat_sc8800 sc8800_plat_data = {
- .slav_rts_pin = RK30_PIN6_PA0,
- .slav_rdy_pin = RK30_PIN6_PA1,
- .master_rts_pin = RK30_PIN2_PB5,
- .master_rdy_pin = RK30_PIN2_PA2,
- //.poll_time = 100,
- .io_init = sc8800_io_init,
- .io_deinit = sc8800_io_deinit,
-};
-static struct rk29xx_spi_chip sc8800_spi_chip = {
- //.poll_mode = 1,
- .enable_dma = 1,
-};
-
-#endif
-
-static struct spi_board_info board_spi_devices[] = {
-
-#if defined(CONFIG_RK29_SC8800)
- {
- .modalias = "sc8800",
- .bus_num = 1,
- .platform_data = &sc8800_plat_data,
- .max_speed_hz = 13*1000*1000,
- .chip_select = 0,
- .controller_data = &sc8800_spi_chip,
- },
-#endif
-
-};
-
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN RK30_PIN4_PC0
-
-static int mma8452_init_platform_hw(void)
-{
- rk30_mux_api_set(GPIO4C0_SMCDATA0_TRACEDATA0_NAME, GPIO4C_GPIO4C0);
-
- return 0;
-}
-
-static struct sensor_platform_data mma8452_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma8452_init_platform_hw,
- .orientation = {-1, 0, 0, 0, 0, 1, 0, -1, 0},
-};
-#endif
-
-#if defined (CONFIG_GS_LIS3DH)
-#define LIS3DH_INT_PIN RK30_PIN4_PC0
-
-static int lis3dh_init_platform_hw(void)
-{
- rk30_mux_api_set(GPIO4C0_SMCDATA0_TRACEDATA0_NAME, GPIO4C_GPIO4C0);
-
- return 0;
-}
-
-static struct gsensor_platform_data lis3dh_info = {
- .model = 8452,
- .swap_xy = 0,
- .swap_xyz = 1,
- .init_platform_hw = lis3dh_init_platform_hw,
- .orientation = {-1, 0, 0, 0, 0, 1, 0, -1, 0},
-};
-#endif
-
-
-#if defined (CONFIG_RK_HEADSET_DET) || defined (CONFIG_RK_HEADSET_IRQ_HOOK_ADC_DET)
-
-static int rk_headset_io_init(int gpio)
-{
- int ret;
- ret = gpio_request(gpio, "headset_input");
- if(ret)
- return ret;
-
- rk30_mux_api_set(GPIO0D3_I2S22CHLRCKTX_SMCADVN_NAME, GPIO0D_GPIO0D3);
- gpio_pull_updown(gpio, PullDisable);
- gpio_direction_input(gpio);
- return 0;
-};
-
-struct rk_headset_pdata rk_headset_info = {
- .Headset_gpio = RK30_PIN0_PD3,
- .headset_in_type = HEADSET_IN_LOW,
- .Hook_adc_chn = 2,
- .hook_key_code = KEY_MEDIA,
- .headset_io_init = rk_headset_io_init,
-};
-
-struct platform_device rk_device_headset = {
- .name = "rk_headsetdet",
- .id = 0,
- .dev = {
- .platform_data = &rk_headset_info,
- }
-};
-#endif
-
-#if defined (CONFIG_COMPASS_AK8975)
-static struct sensor_platform_data akm8975_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {0, 0, 1},
- {1, 0, 0},
- {0, 1, 0},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-#if defined(CONFIG_GYRO_L3G4200D)
-
-#include <linux/l3g4200d.h>
-#define L3G4200D_INT_PIN RK30_PIN4_PC3
-
-static int l3g4200d_init_platform_hw(void)
-{
- rk30_mux_api_set(GPIO4C3_SMCDATA3_TRACEDATA3_NAME, GPIO4C_GPIO4C3);
-
- return 0;
-}
-
-static struct sensor_platform_data l3g4200d_info = {
- .type = SENSOR_TYPE_GYROSCOPE,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .orientation = {1, 0, 0, 0, 1, 0, 0, 0, 1},
- .init_platform_hw = l3g4200d_init_platform_hw,
- .x_min = 40,//x_min,y_min,z_min = (0-100) according to hardware
- .y_min = 40,
- .z_min = 20,
-};
-
-#endif
-
-#ifdef CONFIG_LS_CM3217
-
-#define CM3217_POWER_PIN INVALID_GPIO
-#define CM3217_IRQ_PIN INVALID_GPIO
-static int cm3217_init_hw(void)
-{
-#if 0
- if (gpio_request(CM3217_POWER_PIN, NULL) != 0) {
- gpio_free(CM3217_POWER_PIN);
- printk("%s: request cm3217 power pin error\n", __func__);
- return -EIO;
- }
- gpio_pull_updown(CM3217_POWER_PIN, PullDisable);
-
- if (gpio_request(CM3217_IRQ_PIN, NULL) != 0) {
- gpio_free(CM3217_IRQ_PIN);
- printk("%s: request cm3217 int pin error\n", __func__);
- return -EIO;
- }
- gpio_pull_updown(CM3217_IRQ_PIN, PullDisable);
-#endif
- return 0;
-}
-
-static void cm3217_exit_hw(void)
-{
-#if 0
- gpio_free(CM3217_POWER_PIN);
- gpio_free(CM3217_IRQ_PIN);
-#endif
- return;
-}
-
-static struct cm3217_platform_data cm3217_info = {
- .irq_pin = CM3217_IRQ_PIN,
- .power_pin = CM3217_POWER_PIN,
- .init_platform_hw = cm3217_init_hw,
- .exit_platform_hw = cm3217_exit_hw,
-};
-#endif
-
-#if defined(CONFIG_PS_AL3006)
-static struct sensor_platform_data proximity_info = {
- .type = SENSOR_TYPE_PROXIMITY,
- .irq_enable = 1,
- .poll_delay_ms = 200,
-};
-#endif
-
-#if defined(CONFIG_LS_AL3006)
-static struct sensor_platform_data light_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 1,
- .poll_delay_ms = 200,
-};
-#endif
-
-
-#ifdef CONFIG_FB_ROCKCHIP
-
-/*****************************************************************************************
- * lcd devices
- * author: hhb@rock-chips.com
- *****************************************************************************************/
-
-#define LCD_TXD_PIN RK30_PIN1_PA7
-#define LCD_CLK_PIN RK30_PIN1_PA5
-#define LCD_CS_PIN RK30_PIN1_PA4
-#define LCD_RST_PIN RK30_PIN4_PC7
-
-/*****************************************************************************************
-* frame buffer devices
-* author: hhb@rock-chips.com
-*****************************************************************************************/
-#define FB_ID 0
-#define FB_DISPLAY_ON_PIN INVALID_GPIO//RK29_PIN6_PD0
-#define FB_LCD_STANDBY_PIN INVALID_GPIO//RK29_PIN6_PD1
-#define FB_LCD_CABC_EN_PIN INVALID_GPIO//RK29_PIN6_PD2
-#define FB_MCU_FMK_PIN INVALID_GPIO
-
-#define FB_DISPLAY_ON_VALUE GPIO_HIGH
-#define FB_LCD_STANDBY_VALUE GPIO_HIGH
-
-
-//#endif
-static int rk29_lcd_io_init(void)
-{
- int ret = 0;
-
- //printk("rk29_lcd_io_init\n");
-
- ret = gpio_request(LCD_TXD_PIN, NULL);
- if (ret != 0) {
- gpio_free(LCD_TXD_PIN);
- printk("%s: request LCD_TXD_PIN error\n", __func__);
- return -EIO;
- }
-
- ret = gpio_request(LCD_CLK_PIN, NULL);
- if (ret != 0) {
- gpio_free(LCD_CLK_PIN);
- printk("%s: request LCD_CLK_PIN error\n", __func__);
- return -EIO;
- }
-
- ret = gpio_request(LCD_CS_PIN, NULL);
- if (ret != 0) {
- gpio_free(LCD_CS_PIN);
- printk("%s: request LCD_CS_PIN error\n", __func__);
- return -EIO;
- }
-
- rk30_mux_api_set(GPIO1A7_UART1RTSN_SPI0TXD_NAME, GPIO1A_GPIO1A7);
- rk30_mux_api_set(GPIO1A5_UART1SOUT_SPI0CLK_NAME, GPIO1A_GPIO1A5);
- rk30_mux_api_set(GPIO1A4_UART1SIN_SPI0CSN0_NAME, GPIO1A_GPIO1A4);
- //rk30_mux_api_set(GPIO4C7_SMCDATA7_TRACEDATA7_NAME, GPIO4C_GPIO4C7);
- gpio_direction_output(LCD_CS_PIN, 1);
- gpio_direction_output(LCD_CLK_PIN, 1);
- gpio_direction_output(LCD_TXD_PIN, 1);
- return ret;
-}
-
-#if defined (CONFIG_RK29_WORKING_POWER_MANAGEMENT)
-static int rk29_lcd_io_deinit(void)
-{
- int ret = 0;
-
- gpio_direction_input(LCD_TXD_PIN);
- gpio_direction_input(LCD_CLK_PIN);
- gpio_direction_input(LCD_CS_PIN);
-
- gpio_free(LCD_CS_PIN);
- gpio_free(LCD_CLK_PIN);
- gpio_free(LCD_TXD_PIN);
- return ret;
-}
-#else
-static int rk29_lcd_io_deinit(void)
-{
- int ret = 0;
- //printk("rk29_lcd_io_deinit\n");
-
- gpio_direction_input(LCD_TXD_PIN);
- gpio_direction_input(LCD_CLK_PIN);
- gpio_direction_input(LCD_CS_PIN);
-
- gpio_free(LCD_CS_PIN);
- gpio_free(LCD_CLK_PIN);
- gpio_free(LCD_TXD_PIN);
- //gpio_free(LCD_RXD_PIN);
-
- //rk30_mux_api_set(GPIO0B7_I2S8CHSDO3_NAME, GPIO0B_GPIO0B7);
- //rk30_mux_api_set(GPIO0B6_I2S8CHSDO2_NAME, GPIO0B_GPIO0B6);
- //rk30_mux_api_set(GPIO0B5_I2S8CHSDO1_NAME, GPIO0B_GPIO0B5);
-
- return ret;
-}
-#endif
-
-
-static struct rk29lcd_info rk29_lcd_info = {
- .txd_pin = LCD_TXD_PIN,
- .clk_pin = LCD_CLK_PIN,
- .cs_pin = LCD_CS_PIN,
- .reset_pin = LCD_RST_PIN,
- .io_init = rk29_lcd_io_init,
- .io_deinit = rk29_lcd_io_deinit,
-};
-
-
-#define LCD_EN_MUX_NAME GPIO0D4_I2S22CHSDI_SMCADDR0_NAME
-#define LCD_EN_PIN RK30_PIN0_PD4
-#define LCD_EN_VALUE GPIO_HIGH
-
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
- rk30_mux_api_set(LCD_EN_MUX_NAME, GPIO0D_GPIO0D4);
- ret = gpio_request(LCD_EN_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_EN_PIN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_EN_PIN, 1);
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
- }
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE ? 0:1);
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
- return 0;
-}
-
-#if defined(CONFIG_LCDC0_RK30)
-struct rk29fb_info lcdc0_screen_info = {
- .fb_id = FB_ID,
- .prop = PRMRY, //primary display device
- .lcd_info = &rk29_lcd_info,
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK30)
-struct rk29fb_info lcdc1_screen_info = {
- #if defined(CONFIG_HDMI_RK30)
- .prop = EXTEND, //extend display device
- .lcd_info = NULL,
- .set_screen_info = hdmi_set_info,
- #endif
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-
-#ifdef CONFIG_ANDROID_TIMED_GPIO
-static struct timed_gpio timed_gpios[] = {
- {
- .name = "vibrator",
- .gpio = RK30_PIN0_PA4,
- .max_timeout = 1000,
- .active_low = 0,
- .adjust_time =20, //adjust for diff product
- },
-};
-
-static struct timed_gpio_platform_data rk29_vibrator_info = {
- .num_gpios = 1,
- .gpios = timed_gpios,
-};
-
-static struct platform_device rk29_device_vibrator = {
- .name = "timed-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_vibrator_info,
- },
-
-};
-#endif
-
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
-static struct gpio_led rk29_leds[] = {
- {
- .name = "button-backlight",
- .gpio = RK30_PIN4_PD7,
- .default_trigger = "timer",
- .active_low = 0,
- .retain_state_suspended = 0,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- },
-};
-
-static struct gpio_led_platform_data rk29_leds_pdata = {
- .leds = rk29_leds,
- .num_leds = ARRAY_SIZE(rk29_leds),
-};
-
-static struct platform_device rk29_device_gpio_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_leds_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_RK_IRDA
-#define IRDA_IRQ_PIN RK30_PIN6_PA1
-
-static int irda_iomux_init(void)
-{
- int ret = 0;
-
- //irda irq pin
- ret = gpio_request(IRDA_IRQ_PIN, NULL);
- if (ret != 0) {
- gpio_free(IRDA_IRQ_PIN);
- printk(">>>>>> IRDA_IRQ_PIN gpio_request err \n ");
- }
- gpio_pull_updown(IRDA_IRQ_PIN, PullDisable);
- gpio_direction_input(IRDA_IRQ_PIN);
-
- return 0;
-}
-
-static int irda_iomux_deinit(void)
-{
- gpio_free(IRDA_IRQ_PIN);
- return 0;
-}
-
-static struct irda_info rk29_irda_info = {
- .intr_pin = IRDA_IRQ_PIN,
- .iomux_init = irda_iomux_init,
- .iomux_deinit = irda_iomux_deinit,
- //.irda_pwr_ctl = bu92747guw_power_ctl,
-};
-
-static struct platform_device irda_device = {
-#ifdef CONFIG_RK_IRDA_NET
- .name = "rk_irda",
-#else
- .name = "bu92747_irda",
-#endif
- .id = -1,
- .dev = {
- .platform_data = &rk29_irda_info,
- }
-};
-#endif
-
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and sdio.noted by xbw at 2012-03-05
-**************************************************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "board-rk30-phone-sdmmc.c"
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
-#define SDMMC0_WRITE_PROTECT_PIN RK30_PIN3_PB7 //According to your own project to set the value of write-protect-pin.
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
-#define SDMMC1_WRITE_PROTECT_PIN RK30_PIN3_PC7 //According to your own project to set the value of write-protect-pin.
-#endif
-
-#define RK29SDK_WIFI_SDIO_CARD_DETECT_N RK30_PIN6_PB2
-
-#endif //endif ---#ifdef CONFIG_SDMMC_RK29
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- rk30_mux_api_set(GPIO3B1_SDMMC0CMD_NAME, GPIO3B_SDMMC0_CMD);
- rk30_mux_api_set(GPIO3B0_SDMMC0CLKOUT_NAME, GPIO3B_SDMMC0_CLKOUT);
- rk30_mux_api_set(GPIO3B2_SDMMC0DATA0_NAME, GPIO3B_SDMMC0_DATA0);
- rk30_mux_api_set(GPIO3B3_SDMMC0DATA1_NAME, GPIO3B_SDMMC0_DATA1);
- rk30_mux_api_set(GPIO3B4_SDMMC0DATA2_NAME, GPIO3B_SDMMC0_DATA2);
- rk30_mux_api_set(GPIO3B5_SDMMC0DATA3_NAME, GPIO3B_SDMMC0_DATA3);
-
- rk30_mux_api_set(GPIO3B6_SDMMC0DETECTN_NAME, GPIO3B_GPIO3B6);
-
- rk30_mux_api_set(GPIO3A7_SDMMC0PWREN_NAME, GPIO3A_GPIO3A7);
- gpio_request(RK30_PIN3_PA7, "sdmmc-power");
- gpio_direction_output(RK30_PIN3_PA7, GPIO_LOW);
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- rk30_mux_api_set(GPIO3B6_SDMMC0DETECTN_NAME, GPIO3B_SDMMC0_DETECT_N);
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
- .detect_irq = RK30_PIN3_PB6, // INVALID_GPIO
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
-#else
- .write_prt = INVALID_GPIO,
-#endif
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- rk30_mux_api_set(GPIO3C0_SMMC1CMD_NAME, GPIO3C_SMMC1_CMD);
- rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_NAME, GPIO3C_SDMMC1_CLKOUT);
- rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_NAME, GPIO3C_SDMMC1_DATA0);
- rk30_mux_api_set(GPIO3C2_SDMMC1DATA1_NAME, GPIO3C_SDMMC1_DATA1);
- rk30_mux_api_set(GPIO3C3_SDMMC1DATA2_NAME, GPIO3C_SDMMC1_DATA2);
- rk30_mux_api_set(GPIO3C4_SDMMC1DATA3_NAME, GPIO3C_SDMMC1_DATA3);
- //rk30_mux_api_set(GPIO3C6_SDMMC1DETECTN_NAME, GPIO3C_SDMMC1_DETECT_N);
-
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-#if 0
- .detect_irq = RK29SDK_WIFI_SDIO_CARD_DETECT_N,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
-#else
- .detect_irq = INVALID_GPIO,
- .enable_sd_wakeup = 0,
-#endif
-
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-
-#ifdef CONFIG_BATTERY_RK30_ADC
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = RK30_PIN6_PA5,
- .batt_low_pin = RK30_PIN6_PA0,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = RK30_PIN6_PA6,
- .dc_det_level = GPIO_LOW,
- .charge_ok_level = GPIO_HIGH,
-};
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-
-
-#ifdef CONFIG_RFKILL_RK
-// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
-static struct rfkill_rk_platform_data rfkill_rk_platdata = {
- .type = RFKILL_TYPE_BLUETOOTH,
-
- .poweron_gpio = { // BT_REG_ON
- .io = RK30_PIN4_PD5,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO4D5_SMCDATA13_TRACEDATA13_NAME,
- .fgpio = GPIO4D_GPIO4D5,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN3_PD1, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = GPIO3D1_SDMMC1BACKENDPWR_NAME,
- .fgpio = GPIO3D_GPIO3D1,
- },
- },
-
- .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
- .io = RK30_PIN3_PC6, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C6_SDMMC1DETECTN_NAME,
- .fgpio = GPIO3C_GPIO3C6,
- },
- },
-
- .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .gpio = {
- .io = RK30_PIN3_PD2, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
- .iomux = {
- .name = GPIO3D2_SDMMC1INTN_NAME,
- .fgpio = RK30_PIN3_PD2,
- },
- },
- },
-
- .rts_gpio = { // UART_RTS, enable or disable BT's data coming
- .io = RK30_PIN1_PA3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = GPIO1A3_UART0RTSN_NAME,
- .fgpio = GPIO1A_GPIO1A3,
- .fmux = GPIO1A_UART0_RTS_N,
- },
- },
-};
-
-static struct platform_device device_rfkill_rk = {
- .name = "rfkill_rk",
- .id = -1,
- .dev = {
- .platform_data = &rfkill_rk_platdata,
- },
-};
-#endif
-
-/**************************************************************************************************
- * the end of setting for SDMMC devices
-**************************************************************************************************/
-
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- &rk29_device_backlight,
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
- &device_fb,
-#endif
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_ANDROID_TIMED_GPIO
- &rk29_device_vibrator,
-#endif
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
- &rk29_device_gpio_leds,
-#endif
-#ifdef CONFIG_RK_IRDA
- &irda_device,
-#endif
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- &rk29sdk_wifi_device,
-#endif
-#ifdef CONFIG_RFKILL_RK
- &device_rfkill_rk,
-#endif
-#ifdef CONFIG_RK29_SUPPORT_MODEM
- &rk30_device_modem,
-#endif
-#if defined(CONFIG_TDSC8800)
-&rk29_device_tdsc8800,
-#endif
-#if defined (CONFIG_RK_HEADSET_DET) || defined (CONFIG_RK_HEADSET_IRQ_HOOK_ADC_DET)
- &rk_device_headset,
-#endif
-#ifdef CONFIG_BATTERY_RK30_ADC
- &rk30_device_adc_battery,
-#endif
-};
-
-static struct aic3262_gpio_setup aic3262_gpio[] = {
- { // GPIO1
- .used = 0,
- .in = 0,
- .value = AIC3262_GPIO1_FUNC_INT1_OUTPUT ,
-
- },
- {// GPIO2
- .used = 0,
- .in = 0,
- .value = AIC3262_GPIO2_FUNC_CLOCK_OUTPUT,
- },
- {// GPI1
- .used = 1,
- .in = 1,
- .value = 0,
- },
- {// GPI2
- .used = 1,
- .in = 1,
- .value = AIC3262_GPO1_FUNC_DISABLED,
- },
- {// GPO1
- .used = 0,
- .in = 0,
- .value = AIC3262_GPO1_FUNC_ADC_MOD_CLK_OUTPUT,
- },
-};
-static struct aic3262_pdata aic3262_codec_pdata = {
- .gpio = aic3262_gpio,
- .gpio_reset = RK30_PIN0_PB7,
-};
-
-// i2c
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1d,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_GS_LIS3DH)
- {
- .type = "lis3dh",
- .addr = 0x19,
- .flags = 0,
- .irq = LIS3DH_INT_PIN,
- .platform_data = &lis3dh_info,
- },
-#endif
-
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN4_PC1,
- .platform_data = &akm8975_info,
- },
-#endif
-#if defined (CONFIG_GYRO_L3G4200D)
- {
- .type = "l3g4200d_gryo",
- .addr = 0x69,
- .flags = 0,
- .irq = L3G4200D_INT_PIN,
- .platform_data = &l3g4200d_info,
- },
-#endif
-#if defined (CONFIG_INPUT_LPSENSOR_AL3006)
- {
- .type = "al3006",
- .addr = 0x1c, //sel = 0; if sel =1, then addr = 0x1D
- .flags = 0,
- .irq = RK30_PIN6_PA2,
- },
-#endif
-#if defined (CONFIG_LS_AL3006)
- {
- .type = "light_al3006",
- .addr = 0x1c, //sel = 0; if sel =1, then addr = 0x1D
- .flags = 0,
- .irq = RK30_PIN6_PA2,
- .platform_data = &light_info,
- },
-#endif
-
-#if defined (CONFIG_PS_AL3006)
- {
- .type = "proximity_al3006",
- .addr = 0x1c, //sel = 0; if sel =1, then addr = 0x1D
- .flags = 0,
- .irq = RK30_PIN6_PA2,
- .platform_data = &proximity_info,
- },
-#endif
-
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-
-#if defined (CONFIG_SND_SOC_TLV320AIC326X)
- {
- .type = "tlv320aic3262",
- .addr = 0x18,
- .flags = 0,
- .platform_data = &aic3262_codec_pdata,
- },
-#endif
-
-#if defined (CONFIG_SND_SOC_RT5631)
- {
- .type = "rt5631",
- .addr = 0x1a,
- .flags = 0,
- },
-#endif
-
-#ifdef CONFIG_MFD_RK610
- {
- .type = "rk610_ctl",
- .addr = 0x40,
- .flags = 0,
- },
-#ifdef CONFIG_RK610_TVOUT
- {
- .type = "rk610_tvout",
- .addr = 0x42,
- .flags = 0,
- },
-#endif
-#ifdef CONFIG_HDMI_RK610
- {
- .type = "rk610_hdmi",
- .addr = 0x46,
- .flags = 0,
- .irq = RK29_PIN5_PA2,
- },
-#endif
-#ifdef CONFIG_SND_SOC_RK610
- {//RK610_CODEC addr from 0x60 to 0x80 (0x60~0x80)
- .type = "rk610_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
-#endif
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C1_RK30
-#define DC3_VCC_DDR_VOL 1800000 //for vcc_lpddr2_1v8
-#define DC5_VCC_DDR_VOL 1200000 //for vcc_lpddr2_1v2
-#include "board-rk30-phone-twl60xx.c"
-static struct i2c_board_info __initdata i2c1_info[] = {
-
-#if defined (CONFIG_TWL4030_CORE)
- {
- .type = "twl6032",
- .addr = 0x48,
- .flags = 0,
- .irq = RK30_PIN6_PA4,
- .platform_data = &tps80032_data,
-
- },
-
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-
-#if defined (CONFIG_TOUCHSCREEN_SYNAPTICS_S3202)
-{
- .type = "rmi_i2c",
- .addr = 0x20,
- .flags = 0,
- .irq = RK30_PIN4_PC2,
- .platform_data = &s3202_platformdata,
-},
-#endif
-
-
-#if defined (CONFIG_TOUCHSCREEN_FT5306)
-{
- .type = "ft5x0x_ts",
- .addr = 0x38,
- .flags = 0,
- .irq = RK30_PIN4_PD7,//RK30_PIN2_PC2,
- .platform_data = &ft5306_info,
-},
-#endif
-
-#if defined (CONFIG_LS_CM3217)
- {
- .type = "lightsensor",
- .addr = 0x10,
- .flags = 0,
- .irq = CM3217_IRQ_PIN,
- .platform_data = &cm3217_info,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-
-static struct i2c_board_info __initdata i2c3_info[] = {
-
-
-};
-#endif
-
-#ifdef CONFIG_I2C4_RK30
-static struct i2c_board_info __initdata i2c4_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO// RK30_PIN2_PD6 //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO//RK30_PIN2_PD7 //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- //set iomux (gpio) here
- //rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME, GPIO2D_GPIO2D7);
- //rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME, GPIO2D_GPIO2D6);
-
- return 0;
-}
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C4_RK30
- i2c_register_board_info(4, i2c4_info, ARRAY_SIZE(i2c4_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(5, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-
-static void rk30_pm_power_off(void)
-{
- printk(KERN_ERR "rk30_pm_power_off start...\n");
-#if defined(CONFIG_TWL4030_CORE)
- twl6030_poweroff();
-#endif
- while (1);
-}
-
-#if 0
-/**********************************************************************************************
- *
- * The virtual keys for android "back", "home", "menu", "search", these four keys are touch key
- * on the touch screen panel. (added by hhb@rock-chips.com 2011.04.21)
- * attention please: kobj_attribute.attr.name virtualkeys.synaptics_rmi4_i2c should be the same as
- * the input device in the touch screen driver.
- ***********************************************************************************************/
-static ssize_t rk_virtual_keys_show(struct kobject *kobj,
- struct kobj_attribute *attr, char *buf)
-{
-#if (defined(CONFIG_TOUCHSCREEN_SYNAPTICS_S3202))
- printk("rk_virtual_keys_show S3202\n");
- /* centerx;centery;width;height; */
- return sprintf(buf,
- __stringify(EV_KEY) ":" __stringify(KEY_BACK) ":100:980:100:40"
- ":" __stringify(EV_KEY) ":" __stringify(KEY_MENU) ":200:980:100:40"
- ":" __stringify(EV_KEY) ":" __stringify(KEY_HOMEPAGE) ":300:980:100:40"
- ":" __stringify(EV_KEY) ":" __stringify(KEY_SEARCH) ":400:980:100:40"
- "\n");
-#endif
- return 0;
-}
-
-static struct kobj_attribute rk_virtual_keys_attr = {
- .attr = {
-#if defined(CONFIG_TOUCHSCREEN_SYNAPTICS_S3202)
- .name = "virtualkeys.synaptics_rmi4_i2c",
-#else
- .name = "virtualkeys",
-#endif
- .mode = S_IRUGO,
- },
- .show = rk_virtual_keys_show,
-};
-
-static struct attribute *rk_properties_attrs[] = {
- &rk_virtual_keys_attr.attr,
- NULL
-};
-
-static struct attribute_group rk_properties_attr_group = {
- .attrs = rk_properties_attrs,
-};
-static int rk_virtual_keys_init(void)
-{
- int ret;
- struct kobject *properties_kobj;
- printk("rk_virtual_keys_init \n");
- properties_kobj = kobject_create_and_add("board_properties", NULL);
- if (properties_kobj)
- ret = sysfs_create_group(properties_kobj,
- &rk_properties_attr_group);
- if (!properties_kobj || ret)
- {
- printk("failed to create board_properties for virtual key\n");
- }
- return ret;
-}
-
-/*************************end of virtual_keys************************/
-#endif
-
-void board_gpio_suspend(void) {
- gpio_request(RK30_PIN2_PC3, NULL);
- rk30_mux_api_set(GPIO2C3_LCDC1DATA19_SPI1CLK_HSADCDATA0_NAME,GPIO2C_GPIO2C3);
- gpio_direction_input(RK30_PIN2_PC3);
- gpio_pull_updown(RK30_PIN2_PC3, 0);
-
- gpio_request(RK30_PIN2_PC5, NULL);
- rk30_mux_api_set(GPIO2C5_LCDC1DATA21_SPI1TXD_HSADCDATA2_NAME,GPIO2C_GPIO2C5);
- gpio_direction_input(RK30_PIN2_PC5);
- gpio_pull_updown(RK30_PIN2_PC5, 0);
-
- gpio_request(RK30_PIN2_PC6, NULL);
- rk30_mux_api_set(GPIO2C6_LCDC1DATA22_SPI1RXD_HSADCDATA3_NAME,GPIO2C_GPIO2C6);
- gpio_direction_input(RK30_PIN2_PC6);
- gpio_pull_updown(RK30_PIN2_PC6, 0);
-
-}
- void board_gpio_resume(void) {
-
- gpio_request(RK30_PIN2_PC3, NULL);
- gpio_pull_updown(RK30_PIN2_PC3, 1);
- rk30_mux_api_set(GPIO2C3_LCDC1DATA19_SPI1CLK_HSADCDATA0_NAME,GPIO2C_SPI1_CLK);
-
- gpio_request(RK30_PIN2_PC5, NULL);
- gpio_pull_updown(RK30_PIN2_PC5, 1);
- rk30_mux_api_set(GPIO2C5_LCDC1DATA21_SPI1TXD_HSADCDATA2_NAME,GPIO2C_SPI1_TXD);
-
- gpio_request(RK30_PIN2_PC6, NULL);
- gpio_pull_updown(RK30_PIN2_PC6, 1);
- rk30_mux_api_set(GPIO2C6_LCDC1DATA22_SPI1RXD_HSADCDATA3_NAME,GPIO2C_SPI1_RXD);
-
- gpio_free(RK30_PIN2_PC3);
- gpio_free(RK30_PIN2_PC5);
- gpio_free(RK30_PIN2_PC6);
-}
-
-static void __init machine_rk30_board_init(void)
-{
- pm_power_off = rk30_pm_power_off;
-
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- board_usb_detect_init(RK30_PIN6_PA3);
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- rk29sdk_wifi_bt_gpio_control_init();
-#endif
-}
-
-static void __init rk30_reserve(void)
-{
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0", RK30_FB0_MEM_SIZE);
- resource_fb[0].end = resource_fb[0].start + RK30_FB0_MEM_SIZE - 1;
- resource_fb[1].start = board_mem_reserve_add("ipp buf", RK30_FB0_MEM_SIZE);
- resource_fb[1].end = resource_fb[1].start + RK30_FB0_MEM_SIZE - 1;
- resource_fb[2].start = board_mem_reserve_add("fb2", RK30_FB0_MEM_SIZE);
- resource_fb[2].end = resource_fb[2].start + RK30_FB0_MEM_SIZE - 1;
-#endif
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
- board_mem_reserved();
-}
-
-/**
- * dvfs_cpu_logic_table: table for arm and logic dvfs
- * @frequency : arm frequency
- * @cpu_volt : arm voltage depend on frequency
- * @logic_volt : logic voltage arm requests depend on frequency
- * comments : min arm/logic voltage
- */
-static struct dvfs_arm_table dvfs_cpu_logic_table[] = {
- //{.frequency = 252 * 1000, .cpu_volt = 1050 * 1000, .logic_volt = 1050 * 1000},//0.975V/1.000V
- //{.frequency = 504 * 1000, .cpu_volt = 1050 * 1000, .logic_volt = 1050 * 1000},//0.975V/1.000V
- {.frequency = 816 * 1000, .cpu_volt = 1050 * 1000, .logic_volt = 1050 * 1000},//1.000V/1.025V
- {.frequency = 1008 * 1000, .cpu_volt = 1050 * 1000, .logic_volt = 1050 * 1000},//1.025V/1.050V
- {.frequency = 1200 * 1000, .cpu_volt = 1150 * 1000, .logic_volt = 1100 * 1000},//1.100V/1.050V
- {.frequency = 1272 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1150 * 1000},//1.150V/1.100V
- {.frequency = 1416 * 1000, .cpu_volt = 1275 * 1000, .logic_volt = 1150 * 1000},//1.225V/1.100V
- //{.frequency = 1512 * 1000, .cpu_volt = 1325 * 1000, .logic_volt = 1200 * 1000},//1.300V/1.150V
- //{.frequency = 1608 * 1000, .cpu_volt = 1350 * 1000, .logic_volt = 1200 * 1000},//1.325V/1.175V
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
-static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
-static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
-
-void __init board_clock_init(void)
-{
- rk30_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
- dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
-}
-
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk30_fixup,
- .reserve = &rk30_reserve,
- .map_io = rk30_map_io,
- .init_irq = rk30_init_irq,
- .timer = &rk30_timer,
- .init_machine = machine_rk30_board_init,
-MACHINE_END
+++ /dev/null
-/*
- * Copyright (C) 2010 ROCKCHIP, Inc.
- * Author: roger_chen <cz@rock-chips.com>
- *
- * This program is the bluetooth device bcm4330's driver,
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/module.h>
-#include <linux/device.h>
-#include <linux/rfkill.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/interrupt.h>
-#include <linux/wakelock.h>
-#include <linux/fs.h>
-#include <asm/uaccess.h>
-#include <mach/gpio.h>
-#include <asm/irq.h>
-#include <mach/iomux.h>
-#include <linux/wakelock.h>
-#include <linux/timer.h>
-
-#if 0
-#define DBG(x...) printk(KERN_INFO x)
-#else
-#define DBG(x...)
-#endif
-
-#define BT_WAKE_HOST_SUPPORT 0
-
-struct bt_ctrl
-{
- struct rfkill *bt_rfk;
-#if BT_WAKE_HOST_SUPPORT
- struct timer_list tl;
- bool b_HostWake;
- struct wake_lock bt_wakelock;
-#endif
-};
-
-#define BT_GPIO_POWER RK30_PIN4_PD5
-#define IOMUX_BT_GPIO_POWER rk29_mux_api_set(GPIO4D5_SMCDATA13_TRACEDATA13_NAME, GPIO4D_GPIO4D5);
-#define BT_GPIO_RESET RK30_PIN3_PD1
-#define IOMUX_BT_GPIO_RESET rk29_mux_api_set(GPIO3D1_SDMMC1BACKENDPWR_NAME, GPIO3D_GPIO3D1);
-
-#ifdef CONFIG_BT_HCIBCM4325
-#define BT_GPIO_WAKE_UP RK30_PIN3_PC6
-#endif
-
-#if BT_WAKE_HOST_SUPPORT
-#define BT_GPIO_WAKE_UP_HOST //RK2818_PIN_PA7
-#define IOMUX_BT_GPIO_WAKE_UP_HOST() //rk2818_mux_api_set(GPIOA7_FLASHCS3_SEL_NAME,0);
-
-#define BT_WAKE_LOCK_TIMEOUT 10 //s
-#endif
-
-static const char bt_name[] =
-#if defined(CONFIG_RKWIFI)
- "rk903"
-#elif defined(CONFIG_BCM4329)
- "bcm4329"
-#elif defined(CONFIG_MV8787)
- "mv8787"
-#else
- "bt_default"
-#endif
-;
-
-extern int rk29sdk_bt_power_state;
-extern int rk29sdk_wifi_power_state;
-
-struct bt_ctrl gBtCtrl;
-
-#if BT_WAKE_HOST_SUPPORT
-void resetBtHostSleepTimer(void)
-{
- mod_timer(&(gBtCtrl.tl),jiffies + BT_WAKE_LOCK_TIMEOUT*HZ);//ÔÙÖØÐÂÉèÖó¬Ê±Öµ¡£
-}
-
-void btWakeupHostLock(void)
-{
- if(gBtCtrl.b_HostWake == false){
- DBG("*************************Lock\n");
- wake_lock(&(gBtCtrl.bt_wakelock));
- gBtCtrl.b_HostWake = true;
- }
-}
-
-void btWakeupHostUnlock(void)
-{
- if(gBtCtrl.b_HostWake == true){
- DBG("*************************UnLock\n");
- wake_unlock(&(gBtCtrl.bt_wakelock)); //ÈÃϵͳ˯Ãß
- gBtCtrl.b_HostWake = false;
- }
-}
-
-static void timer_hostSleep(unsigned long arg)
-{
- DBG("%s---b_HostWake=%d\n",__FUNCTION__,gBtCtrl.b_HostWake);
- btWakeupHostUnlock();
-}
-
-
-#ifdef CONFIG_PM
-static int bcm4329_rfkill_suspend(struct platform_device *pdev, pm_message_t state)
-{
- DBG("%s\n",__FUNCTION__);
- return 0;
-}
-
-static int bcm4329_rfkill_resume(struct platform_device *pdev)
-{
- DBG("%s\n",__FUNCTION__);
- btWakeupHostLock();
- resetBtHostSleepTimer();
- return 0;
-}
-#else
-#define bcm4329_rfkill_suspend NULL
-#define bcm4329_rfkill_resume NULL
-#endif
-
-static irqreturn_t bcm4329_wake_host_irq(int irq, void *dev)
-{
- btWakeupHostLock();
- resetBtHostSleepTimer();
- return IRQ_HANDLED;
-}
-#endif
-
-#ifdef CONFIG_BT_HCIBCM4325
-int bcm4325_sleep(int bSleep)
-{
- //printk("*************bt enter sleep***************\n");
- if (bSleep)
- gpio_set_value(BT_GPIO_WAKE_UP, GPIO_LOW); //low represent bt device may enter sleep
- else
- gpio_set_value(BT_GPIO_WAKE_UP, GPIO_HIGH); //high represent bt device must be awake
- //printk("sleep=%d\n",bSleep);
- return 0;
-}
-#endif
-
-static int bcm4329_set_block(void *data, bool blocked)
-{
- DBG("%s---blocked :%d\n", __FUNCTION__, blocked);
-
- IOMUX_BT_GPIO_POWER;
- IOMUX_BT_GPIO_RESET;
-
- if (false == blocked) {
- gpio_set_value(BT_GPIO_POWER, GPIO_HIGH); /* bt power on */
-
- gpio_set_value(BT_GPIO_RESET, GPIO_LOW);
- mdelay(20);
- gpio_set_value(BT_GPIO_RESET, GPIO_HIGH); /* bt reset deactive*/
- mdelay(20);
-
-#if BT_WAKE_HOST_SUPPORT
- btWakeupHostLock();
-#endif
- pr_info("bt turn on power\n");
- }
- else {
-#if BT_WAKE_HOST_SUPPORT
- btWakeupHostUnlock();
-#endif
- if (!rk29sdk_wifi_power_state) {
- gpio_set_value(BT_GPIO_POWER, GPIO_LOW); /* bt power off */
- mdelay(20);
- pr_info("bt shut off power\n");
- }else {
- pr_info("bt shouldn't shut off power, wifi is using it!\n");
- }
-
- gpio_set_value(BT_GPIO_RESET, GPIO_LOW); /* bt reset active*/
- mdelay(20);
- }
-
- rk29sdk_bt_power_state = !blocked;
- return 0;
-}
-
-
-static const struct rfkill_ops bcm4329_rfk_ops = {
- .set_block = bcm4329_set_block,
-};
-
-static int __devinit bcm4329_rfkill_probe(struct platform_device *pdev)
-{
- int rc = 0;
- bool default_state = true;
-
- DBG("Enter::%s,line=%d\n",__FUNCTION__,__LINE__);
-
- /* default to bluetooth off */
- bcm4329_set_block(NULL, default_state); /* blocked -> bt off */
-
- gBtCtrl.bt_rfk = rfkill_alloc(bt_name,
- NULL,
- RFKILL_TYPE_BLUETOOTH,
- &bcm4329_rfk_ops,
- NULL);
-
- if (!gBtCtrl.bt_rfk)
- {
- printk("fail to rfkill_allocate************\n");
- return -ENOMEM;
- }
-
- rfkill_set_states(gBtCtrl.bt_rfk, default_state, false);
-
- rc = rfkill_register(gBtCtrl.bt_rfk);
- if (rc)
- {
- printk("failed to rfkill_register,rc=0x%x\n",rc);
- rfkill_destroy(gBtCtrl.bt_rfk);
- }
-
- gpio_request(BT_GPIO_POWER, NULL);
- gpio_request(BT_GPIO_RESET, NULL);
-#ifdef CONFIG_BT_HCIBCM4325
- gpio_request(BT_GPIO_WAKE_UP, NULL);
-#endif
-
-#if BT_WAKE_HOST_SUPPORT
- init_timer(&(gBtCtrl.tl));
- gBtCtrl.tl.expires = jiffies + BT_WAKE_LOCK_TIMEOUT*HZ;
- gBtCtrl.tl.function = timer_hostSleep;
- add_timer(&(gBtCtrl.tl));
- gBtCtrl.b_HostWake = false;
-
- wake_lock_init(&(gBtCtrl.bt_wakelock), WAKE_LOCK_SUSPEND, "bt_wake");
-
- rc = gpio_request(BT_GPIO_WAKE_UP_HOST, "bt_wake");
- if (rc) {
- printk("%s:failed to request RAHO_BT_WAKE_UP_HOST\n",__FUNCTION__);
- }
-
- IOMUX_BT_GPIO_WAKE_UP_HOST();
- gpio_pull_updown(BT_GPIO_WAKE_UP_HOST,GPIOPullUp);
- rc = request_irq(gpio_to_irq(BT_GPIO_WAKE_UP_HOST),bcm4329_wake_host_irq,IRQF_TRIGGER_FALLING,NULL,NULL);
- if(rc)
- {
- printk("%s:failed to request RAHO_BT_WAKE_UP_HOST irq\n",__FUNCTION__);
- gpio_free(BT_GPIO_WAKE_UP_HOST);
- }
- enable_irq_wake(gpio_to_irq(BT_GPIO_WAKE_UP_HOST)); // so RAHO_BT_WAKE_UP_HOST can wake up system
-
- printk(KERN_INFO "bcm4329 module has been initialized,rc=0x%x\n",rc);
- #endif
-
- return rc;
-}
-
-
-static int __devexit bcm4329_rfkill_remove(struct platform_device *pdev)
-{
- if (gBtCtrl.bt_rfk)
- rfkill_unregister(gBtCtrl.bt_rfk);
- gBtCtrl.bt_rfk = NULL;
-#if BT_WAKE_HOST_SUPPORT
- del_timer(&(gBtCtrl.tl));//ɾµô¶¨Ê±Æ÷
- btWakeupHostUnlock();
- wake_lock_destroy(&(gBtCtrl.bt_wakelock));
-#endif
- platform_set_drvdata(pdev, NULL);
-
- DBG("Enter::%s,line=%d\n",__FUNCTION__,__LINE__);
- return 0;
-}
-
-static struct platform_driver bcm4329_rfkill_driver = {
- .probe = bcm4329_rfkill_probe,
- .remove = __devexit_p(bcm4329_rfkill_remove),
- .driver = {
- .name = "rk29sdk_rfkill",
- .owner = THIS_MODULE,
- },
-#if BT_WAKE_HOST_SUPPORT
- .suspend = bcm4329_rfkill_suspend,
- .resume = bcm4329_rfkill_resume,
-#endif
-};
-
-/*
- * Module initialization
- */
-static int __init bcm4329_mod_init(void)
-{
- int ret;
- DBG("Enter::%s,line=%d\n",__FUNCTION__,__LINE__);
- ret = platform_driver_register(&bcm4329_rfkill_driver);
- printk("ret=0x%x\n", ret);
- return ret;
-}
-
-static void __exit bcm4329_mod_exit(void)
-{
- platform_driver_unregister(&bcm4329_rfkill_driver);
-}
-
-module_init(bcm4329_mod_init);
-module_exit(bcm4329_mod_exit);
-MODULE_DESCRIPTION("bcm4330 Bluetooth driver");
-MODULE_AUTHOR("roger_chen cz@rock-chips.com, cmy@rock-chips.com");
-MODULE_LICENSE("GPL");
-
+++ /dev/null
-#include <linux/regulator/machine.h>
-#include <linux/i2c/twl.h>
-
-#include <mach/sram.h>
-
-#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
-
-#define CRU_CLKGATE5_CON_ADDR 0x00e4
-#define GRF_GPIO6L_DIR_ADDR 0x0030
-#define GRF_GPIO6L_DO_ADDR 0x0068
-#define GRF_GPIO6L_EN_ADDR 0x00a0
-#define GPIO6_PB3_DIR_OUT 0x08000800
-#define GPIO6_PB3_DO_LOW 0x08000000
-#define GPIO6_PB3_DO_HIGH 0x08000800
-#define GPIO6_PB3_EN_MASK 0x08000800
-#define GPIO6_PB3_UNEN_MASK 0x08000000
-#define GPIO6_PB1_DIR_OUT 0x02000200
-#define GPIO6_PB1_DO_LOW 0x02000000
-#define GPIO6_PB1_DO_HIGH 0x02000200
-#define GPIO6_PB1_EN_MASK 0x02000200
-#define GPIO6_PB1_UNEN_MASK 0x02000000
-
-#define TWL60xx_IRQ_BASE IRQ_BOARD_BASE
-#ifdef CONFIG_TWL4030_CORE
-#define TWL60xx_BASE_NR_IRQS 24
-#else
-#define TWL60xx_BASE_NR_IRQS 0
-#endif
-#define TWL60xx_IRQ_END (TWL60xx_IRQ_BASE + TWL60xx_BASE_NR_IRQS)
-
-#ifdef CONFIG_TWL4030_CORE
-
-static inline int twl_reg_read(unsigned base, unsigned slave_subgp)
-{
- u8 value;
- int status;
- status = twl_i2c_read_u8(slave_subgp,&value, base);
- return (status < 0) ? status : value;
-}
-
-
-static inline int twl_reg_write(unsigned base, unsigned slave_subgp,
- u8 value)
-{
- return twl_i2c_write_u8(slave_subgp,value, base);
-}
-
-#define PMU_POWER_SLEEP RK30_PIN6_PB3
-#define PMU_CHRG_DET_N RK30_PIN0_PC7
-int tps80032_pre_init(void){
-
- printk("%s\n", __func__);
-
- gpio_request(PMU_POWER_SLEEP, "NULL");
- gpio_direction_output(PMU_POWER_SLEEP, GPIO_LOW);
-
- gpio_request(PMU_CHRG_DET_N, "NULL");
- gpio_direction_output(PMU_CHRG_DET_N, GPIO_HIGH);
-
- twl_reg_write(0x0e,TWL_MODULE_PM_MASTER,0x5f);
- twl_reg_write(PREQ1_RES_ASS_A,TWL_MODULE_PM_SLAVE_RES,0x2b);
- twl_reg_write(PREQ1_RES_ASS_B,TWL_MODULE_PM_SLAVE_RES,0x50);
- twl_reg_write(PREQ1_RES_ASS_C,TWL_MODULE_PM_SLAVE_RES,0x27);
- twl_reg_write(PHOENIX_MSK_TRANSITION,TWL_MODULE_PM_MASTER,0x00);
- twl_reg_write(PHOENIX_SENS_TRANSITION,TWL_MODULE_PM_MASTER,0xc0); //set pmu enter sleep on a preq1 rising edge
-
- twl_reg_write(SMPS1_CFG_STATE,TWL_MODULE_PM_RECEIVER,0x01); //set state
- twl_reg_write(SMPS2_CFG_STATE,TWL_MODULE_PM_RECEIVER,0x01);
- twl_reg_write(LDO7_CFG_STATE,TWL_MODULE_PM_RECEIVER,0x01);
-
- twl_reg_write(CLK32KG_CFG_STATE,TWL_MODULE_PM_SLAVE_RES,0x01); //set clk32kg on when we use
- twl_reg_write(CLK32KAUDIO_CFG_STATE,TWL_MODULE_PM_SLAVE_RES,0x01); //set clk32kaudio on when we use
-
- twl_reg_write(CHARGERUSB_CTRLLIMIT2,TWL6030_MODULE_CHARGER, 0x0f);
- twl_reg_write(CHARGERUSB_CTRLLIMIT2,TWL6030_MODULE_CHARGER, 0x1f);
-
- twl_reg_write(0x05,TWL_MODULE_PM_MASTER,0x1d); //set vlow wakeup voltage 3.45v
-
- twl_reg_write(LDO5_CFG_TRANS,TWL_MODULE_PM_RECEIVER,0x03); //set ldo5 is disabled when in sleep mode
- twl_reg_write(LDO7_CFG_TRANS,TWL_MODULE_PM_RECEIVER,0x03); //set ldo7 is disabled when in sleep mode
- twl_reg_write(LDOUSB_CFG_TRANS,TWL_MODULE_PM_RECEIVER,0x03);
- return 0;
-
-}
-int tps80032_set_init(void)
-{
- struct regulator *dcdc;
- struct regulator *ldo;
- printk("%s\n", __func__);
-
- ldo = regulator_get(NULL, "ldo1"); //vcca_33
- regulator_set_voltage(ldo, 3300000, 3300000);
- regulator_enable(ldo);
-// printk("%s set ldo1 vcca_33=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo4"); // vdd_11
- regulator_set_voltage(ldo, 1100000, 1100000);
- regulator_enable(ldo);
-// printk("%s set ldo4 vdd_11=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- dcdc = regulator_get(NULL, "vcc_io");
- regulator_set_voltage(dcdc,3000000,3000000);
- regulator_enable(dcdc);
-// printk("%s set dcdc4 vcc_io=%dmV end\n", __func__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo2"); // vdd_usb11
- regulator_set_voltage(ldo, 1100000, 1100000);
- regulator_enable(ldo);
-// printk("%s set ldo2 vdd_usb11=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo5"); // vcc_25
- regulator_set_voltage(ldo, 2500000, 2500000);
- regulator_enable(ldo);
-// printk("%s set ldo5 vcc_25=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldousb"); // vcc_usb33
- regulator_set_voltage(ldo, 3300000, 3300000);
- regulator_enable(ldo);
-// printk("%s set ldousb vcc_usb33=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- dcdc = regulator_get(NULL, "vdd_cpu"); // vdd_arm
- regulator_set_voltage(dcdc,1100000,1100000);
- regulator_enable(dcdc);
- printk("%s set dcdc1 vdd_cpu=%dmV end\n", __func__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- dcdc = regulator_get(NULL, "vdd_core"); //vdd_log
- regulator_set_voltage(dcdc,1100000,1100000);
- regulator_enable(dcdc);
- printk("%s set dcdc2 vdd_core=%dmV end\n", __func__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- dcdc = regulator_get(NULL, "vcc_lpddr2_1v8"); //vcc_lpddr2_1v8
- regulator_set_voltage(dcdc,DC3_VCC_DDR_VOL,DC3_VCC_DDR_VOL);
- regulator_enable(dcdc);
-// printk("%s set dcdc3 vcc_lpddr2_1v8=%dmV end\n", __func__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- dcdc = regulator_get(NULL, "vcc_lpddr2_1v2"); //vcc_lpddr2_1v2
- regulator_set_voltage(dcdc,DC5_VCC_DDR_VOL,DC5_VCC_DDR_VOL);
- regulator_enable(dcdc);
-// printk("%s set dcdc5 vcc_lpddr2_1v2=%dmV end\n", __func__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo3"); //vcc_nandflash
- regulator_set_voltage(ldo, 3300000, 3300000);
- regulator_enable(ldo);
-// printk("%s set ldo3 vcc_nandflash=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo6"); //codecvdd_1v8
- regulator_set_voltage(ldo, 1800000, 1800000);
- regulator_enable(ldo);
-// printk("%s set ldo6 codecvdd_1v8=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo7"); //vcc_lcd
- regulator_set_voltage(ldo, 3000000, 3000000);
- regulator_enable(ldo);
-// printk("%s set ldo7 vcc_lcd=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
-
- ldo = regulator_get(NULL, "ldoln"); //vcccodec_io
- regulator_set_voltage(ldo, 3300000, 3300000);
- regulator_enable(ldo);
-// printk("%s set ldoln vcccodec_io=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
-/*
- ldo = regulator_get(NULL, "vana"); //vana_out
- regulator_set_voltage(ldo, 2500000, 2500000);
-// regulator_set_suspend_voltage(ldo, 2500000);
- regulator_enable(ldo);
- printk("%s set vana vana_out=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-*/
-
- printk("tps80032_set_init end.\n");
- return 0;
-}
-
-
-static struct regulator_consumer_supply tps80032_smps1_supply[] = {
- {
- .supply = "smps1",
- },
- {
- .supply = "vdd_cpu",
- },
-};
-static struct regulator_consumer_supply tps80032_smps2_supply[] = {
- {
- .supply = "smps2",
- },
- {
- .supply = "vdd_core",
- },
-};
-static struct regulator_consumer_supply tps80032_smps3_supply[] = {
- {
- .supply = "smps3",
- },
- {
- .supply = "vcc_lpddr2_1v8",
- },
- {
- .supply = "vcc_ddr3",
- },
-};
-static struct regulator_consumer_supply tps80032_smps4_supply[] = {
- {
- .supply = "smps4",
- },
- {
- .supply = "vcc_io",
- },
-};
-static struct regulator_consumer_supply tps80032_smps5_supply[] = {
- {
- .supply = "smps5",
- },
- {
- .supply = "vcc_lpddr2_1v2",
- },
-};
-static struct regulator_consumer_supply tps80032_ldo1_supply[] = {
- {
- .supply = "ldo1",
- },
-};
-static struct regulator_consumer_supply tps80032_ldo2_supply[] = {
- {
- .supply = "ldo2",
- },
-};
-
-static struct regulator_consumer_supply tps80032_ldo3_supply[] = {
- {
- .supply = "ldo3",
- },
-};
-static struct regulator_consumer_supply tps80032_ldo4_supply[] = {
- {
- .supply = "ldo4",
- },
-};
-static struct regulator_consumer_supply tps80032_ldo5_supply[] = {
- {
- .supply = "ldo5",
- },
-};
-static struct regulator_consumer_supply tps80032_ldo6_supply[] = {
- {
- .supply = "ldo6",
- },
-};
-static struct regulator_consumer_supply tps80032_ldo7_supply[] = {
- {
- .supply = "ldo7",
- },
-};
-
-static struct regulator_consumer_supply tps80032_ldoln_supply[] = {
- {
- .supply = "ldoln",
- },
-};
-static struct regulator_consumer_supply tps80032_ldousb_supply[] = {
- {
- .supply = "ldousb",
- },
-};
-static struct regulator_consumer_supply tps80032_ldovana_supply[] = {
- {
- .supply = "vana",
- },
-};
-/* */
-static struct regulator_init_data tps80032_smps1 = {
- .constraints = {
- .name = "SMPS1",
- .min_uV = 600000,
- .max_uV = 2100000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps80032_smps1_supply),
- .consumer_supplies = tps80032_smps1_supply,
-};
-
-/* */
-static struct regulator_init_data tps80032_smps2 = {
- .constraints = {
- .name = "SMPS2",
- .min_uV = 600000,
- .max_uV = 2100000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps80032_smps2_supply),
- .consumer_supplies = tps80032_smps2_supply,
-};
-
-
-
-/* */
-static struct regulator_init_data tps80032_smps3 = {
- .constraints = {
- .name = "SMPS3",
- .min_uV = 600000,
- .max_uV = 2100000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps80032_smps3_supply),
- .consumer_supplies = tps80032_smps3_supply,
-};
-
-
-/* */
-static struct regulator_init_data tps80032_smps4 = {
- .constraints = {
- .name = "SMPS4",
- .min_uV = 600000,
- .max_uV = 2100000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps80032_smps4_supply),
- .consumer_supplies = tps80032_smps4_supply,
-};
-/* */
-static struct regulator_init_data tps80032_smps5 = {
- .constraints = {
- .name = "SMPS5",
- .min_uV = 600000,
- .max_uV = 2100000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps80032_smps5_supply),
- .consumer_supplies = tps80032_smps5_supply,
-};
-static struct regulator_init_data tps80032_ldo1 = {
- .constraints = {
- .name = "LDO1",
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps80032_ldo1_supply),
- .consumer_supplies = tps80032_ldo1_supply,
-};
-
-/* */
-static struct regulator_init_data tps80032_ldo2 = {
- .constraints = {
- .name = "LDO2",
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps80032_ldo2_supply),
- .consumer_supplies = tps80032_ldo2_supply,
-};
-
-/* */
-static struct regulator_init_data tps80032_ldo3 = {
- .constraints = {
- .name = "LDO3",
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps80032_ldo3_supply),
- .consumer_supplies = tps80032_ldo3_supply,
-};
-
-/* */
-static struct regulator_init_data tps80032_ldo4 = {
- .constraints = {
- .name = "LDO4",
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps80032_ldo4_supply),
- .consumer_supplies = tps80032_ldo4_supply,
-};
-
-/* */
-static struct regulator_init_data tps80032_ldo5 = {
- .constraints = {
- .name = "LDO5",
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps80032_ldo5_supply),
- .consumer_supplies = tps80032_ldo5_supply,
-};
-
-/* */
-static struct regulator_init_data tps80032_ldo6 = {
- .constraints = {
- .name = "LDO6",
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps80032_ldo6_supply),
- .consumer_supplies = tps80032_ldo6_supply,
-};
-
-/* */
-static struct regulator_init_data tps80032_ldo7 = {
- .constraints = {
- .name = "LDO7",
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps80032_ldo7_supply),
- .consumer_supplies = tps80032_ldo7_supply,
-};
-
-/* */
-static struct regulator_init_data tps80032_ldoln = {
- .constraints = {
- .name = "LDOLN",
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps80032_ldoln_supply),
- .consumer_supplies = tps80032_ldoln_supply,
-};
-
-/* */
-static struct regulator_init_data tps80032_ldousb = {
- .constraints = {
- .name = "LDOUSB",
- .min_uV = 3300000,
- .max_uV = 3300000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps80032_ldousb_supply),
- .consumer_supplies = tps80032_ldousb_supply,
-};
-
-/* */
-static struct regulator_init_data tps80032_ldovana = {
- .constraints = {
- .name = "LDOVANA",
- .min_uV = 600000,
- .max_uV = 2500000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps80032_ldovana_supply),
- .consumer_supplies = tps80032_ldovana_supply,
-};
-
-static struct twl4030_madc_platform_data tps80032_madc_data = {
- .irq_line = 1,
-};
-static int tps_batt_table[] = {
-/* 0 C*/
- 3400,3420,3440,3475,3505,3525,
- 3540,3557,3570,3580,3610,
- 3630,3640,3652,3662,3672,
- 3680,3687,3693,3699,3705,
- 3710,3714,3718,3722,3726,
- 3730,3734,3738,3742,3746,
- 3750,3756,3764,3774,3786,
- 3800,3808,3817,3827,3845,
- 3950,3964,3982,4002,4026,
- 4030,4034,4055,4070,4085,4120
-};
-static struct twl4030_bci_platform_data tps80032_bci_data = {
- .battery_tmp_tbl = tps_batt_table,
- .tblsize = ARRAY_SIZE(tps_batt_table),
-};
-
-static int rk30_phy_init(struct device *dev){
- return 0;
- }
-static int rk30_phy_exit(struct device *dev){
- return 0;
- }
-static int rk30_phy_power(struct device *dev, int ID, int on){
- return 0;
- }
-static int rk30_phy_set_clk(struct device *dev, int on){
- return 0;
- }
-static int rk30_phy_suspend(struct device *dev, int suspend){
- return 0;
- }
-static struct twl4030_usb_data tps80032_usbphy_data = {
- .phy_init = rk30_phy_init,
- .phy_exit = rk30_phy_exit,
- .phy_power = rk30_phy_power,
- .phy_set_clock = rk30_phy_set_clk,
- .phy_suspend = rk30_phy_suspend,
-
-};
-static struct twl4030_ins sleep_on_seq[] __initdata = {
-/*
- * Turn off everything
- */
- {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, 1, 0, RES_STATE_SLEEP), 2},
-};
-
-static struct twl4030_script sleep_on_script __initdata = {
- .script = sleep_on_seq,
- .size = ARRAY_SIZE(sleep_on_seq),
- .flags = TWL4030_SLEEP_SCRIPT,
-};
-
-static struct twl4030_ins wakeup_seq[] __initdata = {
-/*
- * Reenable everything
- */
- {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, 1, 0, RES_STATE_ACTIVE), 2},
-};
-
-static struct twl4030_script wakeup_script __initdata = {
- .script = wakeup_seq,
- .size = ARRAY_SIZE(wakeup_seq),
- .flags = TWL4030_WAKEUP12_SCRIPT,
-};
-
-static struct twl4030_ins wakeup_p3_seq[] __initdata = {
-/*
- * Reenable everything
- */
- {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, 1, 0, RES_STATE_ACTIVE), 2},
-};
-
-static struct twl4030_script wakeup_p3_script __initdata = {
- .script = wakeup_p3_seq,
- .size = ARRAY_SIZE(wakeup_p3_seq),
- .flags = TWL4030_WAKEUP3_SCRIPT,
-};
-static struct twl4030_ins wrst_seq[] __initdata = {
-/*
- * Reset twl4030.
- * Reset VDD1 regulator.
- * Reset VDD2 regulator.
- * Reset VPLL1 regulator.
- * Enable sysclk output.
- * Reenable twl4030.
- */
- {MSG_SINGULAR(DEV_GRP_NULL, RES_RESET, RES_STATE_OFF), 2},
- {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, 0, 1, RES_STATE_ACTIVE),
- 0x13},
- {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_PP, 0, 3, RES_STATE_OFF), 0x13},
- {MSG_SINGULAR(DEV_GRP_NULL, RES_VDD1, RES_STATE_WRST), 0x13},
- {MSG_SINGULAR(DEV_GRP_NULL, RES_VDD2, RES_STATE_WRST), 0x13},
- {MSG_SINGULAR(DEV_GRP_NULL, RES_VPLL1, RES_STATE_WRST), 0x35},
- {MSG_SINGULAR(DEV_GRP_P3, RES_HFCLKOUT, RES_STATE_ACTIVE), 2},
- {MSG_SINGULAR(DEV_GRP_NULL, RES_RESET, RES_STATE_ACTIVE), 2},
-};
-static struct twl4030_script wrst_script __initdata = {
- .script = wrst_seq,
- .size = ARRAY_SIZE(wrst_seq),
- .flags = TWL4030_WRST_SCRIPT,
-};
-
-static struct twl4030_script *twl4030_scripts[] __initdata = {
- /* wakeup12 script should be loaded before sleep script, otherwise a
- board might hit retention before loading of wakeup script is
- completed. This can cause boot failures depending on timing issues.
- */
- &wakeup_script,
- &sleep_on_script,
- &wakeup_p3_script,
- &wrst_script,
-};
-static struct twl4030_resconfig twl4030_rconfig[] __initdata = {
- { .resource = RES_VDD1, .devgroup = -1,
- .type = 1, .type2 = -1, .remap_off = RES_STATE_OFF,
- .remap_sleep = RES_STATE_OFF
- },
- { .resource = RES_VDD2, .devgroup = -1,
- .type = 1, .type2 = -1, .remap_off = RES_STATE_OFF,
- .remap_sleep = RES_STATE_OFF
- },
- { .resource = RES_VPLL1, .devgroup = -1,
- .type = 1, .type2 = -1, .remap_off = RES_STATE_OFF,
- .remap_sleep = RES_STATE_OFF
- },
- { .resource = RES_VPLL2, .devgroup = -1,
- .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_VAUX1, .devgroup = -1,
- .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_VAUX2, .devgroup = -1,
- .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_VAUX3, .devgroup = -1,
- .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_VAUX4, .devgroup = -1,
- .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_VMMC1, .devgroup = -1,
- .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_VMMC2, .devgroup = -1,
- .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_VDAC, .devgroup = -1,
- .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_VSIM, .devgroup = -1,
- .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_VINTANA1, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
- .type = -1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_VINTANA2, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
- .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_VINTDIG, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
- .type = -1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_VIO, .devgroup = DEV_GRP_P3,
- .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_CLKEN, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
- .type = 1, .type2 = -1 , .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_REGEN, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
- .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_NRES_PWRON, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
- .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_SYSEN, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
- .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_HFCLKOUT, .devgroup = DEV_GRP_P3,
- .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_32KCLKOUT, .devgroup = -1,
- .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_RESET, .devgroup = -1,
- .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_MAIN_REF, .devgroup = -1,
- .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
- },
- { 0, 0},
-};
-static struct twl4030_power_data tps80032_scripts_data __initdata = {
- .scripts = twl4030_scripts,
- .num = ARRAY_SIZE(twl4030_scripts),
- .resource_config = twl4030_rconfig,
-};
-
-#ifdef CONFIG_HAS_EARLYSUSPEND
-void twl60xx_pmu_early_suspend(struct regulator_dev *rdev)
-{
- printk("%s\n", __func__);
- int ret;
- ret = twl_reg_read(REG_INT_MSK_STS_A,TWL_MODULE_PIH);
- twl_reg_write(REG_INT_MSK_STS_A,TWL_MODULE_PIH, ret & (~(1 << 2))); //open vlow interrupt
-}
-void twl60xx_pmu_early_resume(struct regulator_dev *rdev)
-{
- printk("%s\n", __func__);
- int ret;
- ret = twl_reg_read(REG_INT_MSK_STS_A,TWL_MODULE_PIH);
- twl_reg_write(REG_INT_MSK_STS_A,TWL_MODULE_PIH, ret |(1 << 2)); //close vlow interrupt
-}
-#else
-void twl60xx_pmu_early_suspend(struct regulator_dev *rdev)
-{
-}
-void twl60xx_pmu_early_resume(struct regulator_dev *rdev)
-{
-}
-#endif
-
-void __sramfunc board_pmu_suspend(void)
-{
- #ifdef CONFIG_CLK_SWITCH_TO_32K //switch clk to 32k
- grf_writel(GPIO6_PB1_DIR_OUT, GRF_GPIO6L_DIR_ADDR);
- grf_writel(GPIO6_PB1_DO_HIGH, GRF_GPIO6L_DO_ADDR); //set gpio6_b1 output low
- grf_writel(GPIO6_PB1_EN_MASK, GRF_GPIO6L_EN_ADDR);
- #endif
-
- grf_writel(GPIO6_PB3_DIR_OUT, GRF_GPIO6L_DIR_ADDR);
- grf_writel(GPIO6_PB3_DO_HIGH, GRF_GPIO6L_DO_ADDR); //set gpio6_b3 output low
- grf_writel(GPIO6_PB3_EN_MASK, GRF_GPIO6L_EN_ADDR);
-
-}
-void __sramfunc board_pmu_resume(void)
-{
- grf_writel(GPIO6_PB3_DIR_OUT, GRF_GPIO6L_DIR_ADDR);
- grf_writel(GPIO6_PB3_DO_LOW, GRF_GPIO6L_DO_ADDR); //set gpio6_b3 output high
- grf_writel(GPIO6_PB3_EN_MASK, GRF_GPIO6L_EN_ADDR);
-
- #ifdef CONFIG_CLK_SWITCH_TO_32K //switch clk to 24M
- grf_writel(GPIO6_PB1_DIR_OUT, GRF_GPIO6L_DIR_ADDR);
- grf_writel(GPIO6_PB1_DO_LOW, GRF_GPIO6L_DO_ADDR); //set gpio6_b1 output low
- grf_writel(GPIO6_PB1_EN_MASK, GRF_GPIO6L_EN_ADDR);
- sram_32k_udelay(10000);
- #else
- sram_udelay(2000);
- #endif
-}
-
-static struct twl4030_platform_data tps80032_data = {
- .irq_base = TWL60xx_IRQ_BASE,
- .irq_end = TWL60xx_IRQ_END,
- //.irq = RK29_PIN0_PA1,
- .pre_init = tps80032_pre_init,
- .set_init = tps80032_set_init,
-
- .madc = &tps80032_madc_data,
- .bci = &tps80032_bci_data,
- .usb = &tps80032_usbphy_data,
-// .power = &tps80032_scripts_data,
- /* Regulators */
- .ldo1 = &tps80032_ldo1,
- .ldo2 = &tps80032_ldo2,
- .ldo3 = &tps80032_ldo3,
- .ldo4 = &tps80032_ldo4,
- .ldo5 = &tps80032_ldo5,
- .ldo6 = &tps80032_ldo6,
- .ldo7 = &tps80032_ldo7,
- .ldoln = &tps80032_ldoln,
- .ldousb =&tps80032_ldousb,
- .vana = &tps80032_ldovana,
-
- .smps1 = &tps80032_smps1,
- .smps2= &tps80032_smps2,
- .smps3 = &tps80032_smps3,
- .smps4 = &tps80032_smps4,
- .smps5 = &tps80032_smps5,
-
-};
-
-#endif
+++ /dev/null
-#include <linux/regulator/machine.h>
-#include <linux/mfd/wm831x/pdata.h>
-#include <linux/mfd/wm831x/core.h>
-#include <linux/mfd/wm831x/gpio.h>
-
-/* wm8326 pmu*/
-#if defined(CONFIG_GPIO_WM831X)
-static struct rk29_gpio_expander_info wm831x_gpio_settinginfo[] = {
- {
- .gpio_num = WM831X_P01, // tp3
- .pin_type = GPIO_IN,
- },
- {
- .gpio_num = WM831X_P02, //tp4
- .pin_type = GPIO_IN,
- },
- {
- .gpio_num = WM831X_P03, //tp2
- .pin_type = GPIO_OUT,
- .pin_value = GPIO_HIGH,
- },
- {
- .gpio_num = WM831X_P04, //tp1
- .pin_type = GPIO_IN,
- },
- {
- .gpio_num = WM831X_P05, //tp1
- .pin_type = GPIO_IN,
- },
- {
- .gpio_num = WM831X_P06, //tp1
- .pin_type = GPIO_OUT,
- .pin_value = GPIO_HIGH,
- },
- {
- .gpio_num = WM831X_P07, //tp1
- .pin_type = GPIO_IN,
- },
- {
- .gpio_num = WM831X_P08, //tp1
- .pin_type = GPIO_OUT,
- .pin_value = GPIO_HIGH,
- },
- {
- .gpio_num = WM831X_P09, //tp1
- .pin_type = GPIO_OUT,
- .pin_value = GPIO_HIGH,
- },
- {
- .gpio_num = WM831X_P10, //tp1
- .pin_type = GPIO_IN,
- },
- {
- .gpio_num = WM831X_P11, //tp1
- .pin_type = GPIO_OUT,
- .pin_value = GPIO_HIGH,
- },
- {
- .gpio_num = WM831X_P12,
- .pin_type = GPIO_OUT,
- .pin_value = GPIO_HIGH,
- },
-};
-#endif
-
-#if defined(CONFIG_MFD_WM831X)
-
-#define UNLOCK_SECURITY_KEY ~(0x1<<5)
-#define LOCK_SECURITY_KEY 0x00
-#define PMU_POWER_SLEEP RK30_PIN6_PB1
-static struct wm831x *Wm831x;
-
-static int wm831x_pre_init(struct wm831x *parm)
-{
- int ret;
- Wm831x = parm;
-// printk("%s\n", __func__);
- gpio_request(PMU_POWER_SLEEP, "NULL");
- gpio_direction_output(PMU_POWER_SLEEP, GPIO_HIGH);
-
- ret = wm831x_reg_read(parm, WM831X_POWER_STATE) & 0xffff;
- wm831x_reg_write(parm, WM831X_POWER_STATE, (ret & 0xfff8) | 0x04);
-
- //BATT_FET_ENA = 1
- wm831x_reg_write(parm, WM831X_SECURITY_KEY, 0x9716); // unlock security key
- wm831x_set_bits(parm, WM831X_RESET_CONTROL, 0x1000, 0x1000);
- ret = wm831x_reg_read(parm, WM831X_RESET_CONTROL) & 0xffff & UNLOCK_SECURITY_KEY; // enternal reset active in sleep
-// printk("%s:WM831X_RESET_CONTROL=0x%x\n", __func__, ret);
- wm831x_reg_write(parm, WM831X_RESET_CONTROL, ret);
-
- wm831x_set_bits(parm,WM831X_DC1_ON_CONFIG ,0x0300,0x0000); //set dcdc mode is FCCM
- wm831x_set_bits(parm,WM831X_DC2_ON_CONFIG ,0x0300,0x0000);
- wm831x_set_bits(parm,WM831X_DC3_ON_CONFIG ,0x0300,0x0000);
-// wm831x_set_bits(parm,0x4066,0x0300,0x0000);
-
-// wm831x_set_bits(parm,WM831X_LDO10_CONTROL ,0x0040,0x0040);// set ldo10 in switch mode
-
- wm831x_set_bits(parm,WM831X_STATUS_LED_1 ,0xc300,0xc100);// set led1 on(in manual mode)
- wm831x_set_bits(parm,WM831X_STATUS_LED_2 ,0xc300,0xc000);//set led2 off(in manual mode)
-
- wm831x_reg_write(parm, WM831X_SECURITY_KEY, LOCK_SECURITY_KEY); // lock security key
-
- return 0;
-}
-
-int wm831x_post_init(struct wm831x *Wm831x)
-{
- struct regulator *dcdc;
- struct regulator *ldo;
-
-
- ldo = regulator_get(NULL, "ldo8"); //vcca33
- regulator_set_voltage(ldo, 3300000, 3300000);
- regulator_set_suspend_voltage(ldo, 3300000);
- regulator_enable(ldo);
-// printk("%s set ldo8 vcca33=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo3"); // vdd_11
- regulator_set_voltage(ldo, 1100000, 1100000);
- regulator_set_suspend_voltage(ldo, 1100000);
- regulator_enable(ldo);
-// printk("%s set ldo3 vdd_11=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- dcdc = regulator_get(NULL, "dcdc3"); // vcc_io
- regulator_set_voltage(dcdc, 3000000, 3000000);
- regulator_set_suspend_voltage(dcdc, 3000000);
- regulator_enable(dcdc);
-// printk("%s set dcdc3 vcc_io=%dmV end\n", __func__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo4"); //vdd_usb11
- regulator_set_voltage(ldo, 1100000, 1100000);
- regulator_set_suspend_voltage(ldo, 1100000);
- regulator_enable(ldo);
-// printk("%s set ldo4 vdd_usb11=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo5"); //vcc_25
- regulator_set_voltage(ldo, 2500000, 2500000);
- regulator_set_suspend_voltage(ldo, 2500000);
- regulator_enable(ldo);
-// printk("%s set ldo5 vcc_25=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
-
-
- ldo = regulator_get(NULL, "ldo10"); //vcc_usb33
- regulator_set_voltage(ldo, 3300000, 3300000);
- regulator_set_suspend_voltage(ldo, 3300000);
- regulator_enable(ldo);
-// printk("%s set ldo10 vcc_usb33=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
-
- dcdc = regulator_get(NULL, "dcdc1"); // vcc_lpddr2_1v8
- regulator_set_voltage(dcdc, 1800000, 1800000);
- regulator_set_suspend_voltage(dcdc, 1800000);
- regulator_enable(dcdc);
- printk("%s set dcdc1 vcc_lpddr2_1v8=%dmV end\n", __func__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- dcdc = regulator_get(NULL, "dcdc2"); // vcc_lpddr2_1v2
- regulator_set_voltage(dcdc, 1200000, 1200000);
- regulator_set_suspend_voltage(dcdc, 1200000);
- regulator_enable(dcdc);
- printk("%s set dcdc2 vcc_lpddr2_1v2=%dmV end\n", __func__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo2"); // vcc_emmc3v3
- regulator_set_voltage(ldo, 3000000, 3000000);
- regulator_set_suspend_voltage(ldo, 3000000);
- regulator_enable(ldo);
-// printk("%s set ldo2 vcc_emmc3v3=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo6"); // vcc_codec18
- regulator_set_voltage(ldo, 1800000, 1800000);
- regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(ldo);
-// printk("%s set ldo6 vcc_codec18=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo1"); // vcc_lcd
- regulator_set_voltage(ldo, 3000000, 3000000);
- regulator_set_suspend_voltage(ldo, 3000000);
- regulator_enable(ldo);
-// printk("%s set ldo1 vcc_lcd=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-#if 0
-
- ldo = regulator_get(NULL, "ldo7"); //vdd_mtv_1v2
- regulator_set_voltage(ldo, 1200000, 1200000);
- regulator_set_suspend_voltage(ldo, 1200000);
- regulator_enable(ldo);
-// printk("%s set ldo7 vdd_mtv_1v2=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo9"); //vdd_mtv_3v
- regulator_set_voltage(ldo, 3000000, 3000000);
- regulator_set_suspend_voltage(ldo, 3000000);
- regulator_enable(ldo);
-// printk("%s set ldo9 vdd_mtv_3v=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-#endif
-
-//discrete dcdc device
-#ifdef CONFIG_RK30_PWM_REGULATOR
- dcdc = regulator_get(NULL, "vdd_core"); // vdd_log
- regulator_set_voltage(dcdc, 1050000, 1050000);
- regulator_enable(dcdc);
- printk("%s set vdd_core=%dmV end\n", __func__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- dcdc = regulator_get(NULL, "vdd_cpu"); // vdd_arm
- regulator_set_voltage(dcdc, 1100000, 1100000);
- regulator_enable(dcdc);
- printk("%s set vdd_cpu=%dmV end\n", __func__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-#endif
- printk("wm831x_post_init end");
- return 0;
-}
-
-static int wm831x_last_deinit(struct wm831x *Wm831x)
-{
- struct regulator *ldo;
-
- printk("%s\n", __func__);
- ldo = regulator_get(NULL, "ldo1");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo2");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo3");
- //regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo4");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo5");
- //regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo6");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo7");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo8");
- //regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo9");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo10");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- return 0;
-}
-
-struct wm831x_backlight_pdata wm831x_backlight_platdata = {
- .isink = 1, /** ISINK to use, 1 or 2 */
- .max_uA = 19484, /** Maximum current to allow */
-};
-
-struct wm831x_backup_pdata wm831x_backup_platdata = {
- .charger_enable = 1,
- .no_constant_voltage = 0, /** Disable constant voltage charging */
- .vlim = 3100, /** Voltage limit in milivolts */
- .ilim = 300, /** Current limit in microamps */
-};
-
-struct wm831x_battery_pdata wm831x_battery_platdata = {
- .enable = 1, /** Enable charging */
- .fast_enable = 1, /** Enable fast charging */
- .off_mask = 1, /** Mask OFF while charging */
- .trickle_ilim = 200, /** Trickle charge current limit, in mA */
- .vsel = 4200, /** Target voltage, in mV */
- .eoc_iterm = 50, /** End of trickle charge current, in mA */
- .fast_ilim = 500, /** Fast charge current limit, in mA */
- .timeout = 480, /** Charge cycle timeout, in minutes */
- .syslo = 3300, /* syslo threshold, in mV*/
- .sysok = 3500, /* sysko threshold, in mV*/
-};
-
-struct wm831x_status_pdata wm831x_status_platdata[WM831X_MAX_STATUS] = {
- {
- .default_src = WM831X_STATUS_OTP,
- .name = "wm831x_status0",
- .default_trigger = "wm831x_otp",
- },
- {
- .default_src = WM831X_STATUS_POWER,
- .name = "wm831x_status1",
- .default_trigger = "wm831x_power",
- },
-};
-
-static struct regulator_consumer_supply dcdc1_consumers[] = {
- {
- .supply = "dcdc1",
- }
-};
-
-static struct regulator_consumer_supply dcdc2_consumers[] = {
- {
- .supply = "dcdc2",
- }
-
-};
-
-static struct regulator_consumer_supply dcdc3_consumers[] = {
- {
- .supply = "dcdc3",
- }
-};
-
-static struct regulator_consumer_supply dcdc4_consumers[] = {
- {
- .supply = "dcdc4",
- }
-};
-
-
-static struct regulator_consumer_supply epe1_consumers[] = {
- {
- .supply = "epe1",
- }
-};
-
-static struct regulator_consumer_supply epe2_consumers[] = {
- {
- .supply = "epe2",
- }
-};
-
-
-static struct regulator_consumer_supply ldo1_consumers[] = {
- {
- .supply = "ldo1",
- }
-};
-
-static struct regulator_consumer_supply ldo2_consumers[] = {
- {
- .supply = "ldo2",
- }
-};
-
-static struct regulator_consumer_supply ldo3_consumers[] = {
- {
- .supply = "ldo3",
- }
-};
-
-static struct regulator_consumer_supply ldo4_consumers[] = {
- {
- .supply = "ldo4",
- }
-};
-
-static struct regulator_consumer_supply ldo5_consumers[] = {
- {
- .supply = "ldo5",
- }
-};
-
-static struct regulator_consumer_supply ldo6_consumers[] = {
- {
- .supply = "ldo6",
- }
-};
-
-static struct regulator_consumer_supply ldo7_consumers[] = {
- {
- .supply = "ldo7",
- }
-};
-
-static struct regulator_consumer_supply ldo8_consumers[] = {
- {
- .supply = "ldo8",
- }
-};
-
-static struct regulator_consumer_supply ldo9_consumers[] = {
- {
- .supply = "ldo9",
- }
-};
-
-static struct regulator_consumer_supply ldo10_consumers[] = {
- {
- .supply = "ldo10",
- }
-};
-
-static struct regulator_consumer_supply ldo11_consumers[] = {
- {
- .supply = "ldo11",
- }
-};
-
-static struct regulator_consumer_supply isink1_consumers[] = {
- {
- .supply = "isink1",
- }
-};
-static struct regulator_consumer_supply isink2_consumers[] = {
- {
- .supply = "isink2",
- }
-};
-struct regulator_init_data wm831x_regulator_init_dcdc[WM831X_MAX_DCDC] = {
- {
- .constraints = {
- .name = "DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(dcdc1_consumers),
- .consumer_supplies = dcdc1_consumers,
- },
- {
- .constraints = {
- .name = "DCDC2",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(dcdc2_consumers),
- .consumer_supplies = dcdc2_consumers,
- },
- {
- .constraints = {
- .name = "DCDC3",
- .min_uV = 850000,
- .max_uV = 3400000, //0.85-3.4V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(dcdc3_consumers),
- .consumer_supplies = dcdc3_consumers,
- },
- {
- .constraints = {
- .name = "DCDC4",
- .min_uV = 00000000,
- .max_uV = 30000000,//30V/40mA
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(dcdc4_consumers),
- .consumer_supplies = dcdc4_consumers,
- },
-};
-
-struct regulator_init_data wm831x_regulator_init_epe[WM831X_MAX_EPE] = {
- {
- .constraints = {
- .name = "EPE1",
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(epe1_consumers),
- .consumer_supplies = epe1_consumers,
- },
- {
- .constraints = {
- .name = "EPE2",
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(epe2_consumers),
- .consumer_supplies = epe2_consumers,
- },
-};
-
-
-struct regulator_init_data wm831x_regulator_init_ldo[WM831X_MAX_LDO] = {
- {
- .constraints = {
- .name = "LDO1",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo1_consumers),
- .consumer_supplies = ldo1_consumers,
- },
- {
- .constraints = {
- .name = "LDO2",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
- .consumer_supplies = ldo2_consumers,
- },
- {
- .constraints = {
- .name = "LDO3",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo3_consumers),
- .consumer_supplies = ldo3_consumers,
- },
- {
- .constraints = {
- .name = "LDO4",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo4_consumers),
- .consumer_supplies = ldo4_consumers,
- },
- {
- .constraints = {
- .name = "LDO5",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo5_consumers),
- .consumer_supplies = ldo5_consumers,
- },
- {
- .constraints = {
- .name = "LDO6",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo6_consumers),
- .consumer_supplies = ldo6_consumers,
- },
- {
- .constraints = {
- .name = "LDO7",
- .min_uV = 1000000,
- .max_uV = 3500000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo7_consumers),
- .consumer_supplies = ldo7_consumers,
- },
- {
- .constraints = {
- .name = "LDO8",
- .min_uV = 1000000,
- .max_uV = 3500000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo8_consumers),
- .consumer_supplies = ldo8_consumers,
- },
- {
- .constraints = {
- .name = "LDO9",
- .min_uV = 1000000,
- .max_uV = 3500000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo9_consumers),
- .consumer_supplies = ldo9_consumers,
- },
- {
- .constraints = {
- .name = "LDO10",
- .min_uV = 1000000,
- .max_uV = 3500000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo10_consumers),
- .consumer_supplies = ldo10_consumers,
- },
- {
- .constraints = {
- .name = "LDO11",
- .min_uV = 800000,
- .max_uV = 1550000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo11_consumers),
- .consumer_supplies = ldo11_consumers,
- },
-};
-struct regulator_init_data wm831x_regulator_init_isink[WM831X_MAX_ISINK] = {
- {
- .constraints = {
- .name = "ISINK1",
- .min_uA = 00000,
- .max_uA = 40000,
- .always_on = true,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_CURRENT,
- },
- .num_consumer_supplies = ARRAY_SIZE(isink1_consumers),
- .consumer_supplies = isink1_consumers,
- },
- {
- .constraints = {
- .name = "ISINK2",
- .min_uA = 0000000,
- .max_uA = 0000000,
- .apply_uV = false,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_CURRENT,
- },
- .num_consumer_supplies = ARRAY_SIZE(isink2_consumers),
- .consumer_supplies = isink2_consumers,
- },
-};
-static int wm831x_checkrange(int start,int num,int val)
-{
- if((val<(start+num))&&(val>=start))
- return 0;
- else
- return -1;
-}
-static int wm831x_init_pin_type(struct wm831x *wm831x)
-{
- struct wm831x_pdata *pdata;
- struct rk29_gpio_expander_info *wm831x_gpio_settinginfo;
- uint16_t wm831x_settingpin_num;
- int i;
-
- if (!wm831x || !wm831x->dev)
- goto out;
-
- pdata = wm831x->dev->platform_data;
- if (!pdata)
- goto out;
-
- wm831x_gpio_settinginfo = pdata->settinginfo;
- if (!wm831x_gpio_settinginfo)
- goto out;
-
- wm831x_settingpin_num = pdata->settinginfolen;
- for (i = 0; i < wm831x_settingpin_num; i++) {
- if (wm831x_gpio_settinginfo[i].pin_type == GPIO_IN) {
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_DIR_MASK | WM831X_GPN_TRI_MASK,
- 1 << WM831X_GPN_DIR_SHIFT | 1 << WM831X_GPN_TRI_SHIFT);
-
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_PULL_MASK, 1 << WM831X_GPN_PULL_SHIFT); //pull down
- if (i == 0 ) {
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_PWR_DOM_MASK,
- WM831X_GPN_PWR_DOM);
- } // set gpiox power domain
- else {
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_PWR_DOM_MASK,
- ~WM831X_GPN_PWR_DOM);
- }
- if (i == 1) {
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_POL_MASK,
- 0x0000);
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_FN_MASK,
- 0x0004);
- } // set gpio2 sleep/wakeup
-
- } else {
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_DIR_MASK | WM831X_GPN_TRI_MASK,
- 1 << WM831X_GPN_TRI_SHIFT);
- if (wm831x_gpio_settinginfo[i].pin_value == GPIO_HIGH) {
- wm831x_set_bits(wm831x, WM831X_GPIO_LEVEL, 1 << i, 1 << i);
- } else {
- wm831x_set_bits(wm831x, WM831X_GPIO_LEVEL, 1 << i, 0 << i);
- }
- if (i == 2) {
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_PWR_DOM_MASK | WM831X_GPN_POL_MASK |WM831X_GPN_FN_MASK,
- 1 << WM831X_GPN_POL_SHIFT | 1 << WM831X_GPN_PWR_DOM_SHIFT | 1 << 0);
-
- } // set gpio3 as clkout output 32.768K
- else {
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_PWR_DOM_MASK,
- ~WM831X_GPN_PWR_DOM);
- }
- }
- }
-
-#if 0
- for (i = 0; i < pdata->gpio_pin_num; i++) {
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_PULL_MASK | WM831X_GPN_POL_MASK | WM831X_GPN_OD_MASK | WM831X_GPN_TRI_MASK,
- 1 << WM831X_GPN_POL_SHIFT | 1 << WM831X_GPN_TRI_SHIFT);
-
- ret = wm831x_reg_read(wm831x, WM831X_GPIO1_CONTROL + i);
- printk("Gpio%d Pin Configuration = %x\n", i, ret);
- }
-#endif
-
-out:
- return 0;
-}
-#if defined(CONFIG_KEYBOARD_WM831X_GPIO)
-static struct wm831x_gpio_keys_button wm831x_gpio_buttons[] = {
-{
- .code = KEY_MEDIA,
- .gpio = TCA6424_P21,
- .active_low = 1,
- .desc = "media",
- .wakeup = 0,
- .debounce_interval = 120,
-},
-{
- .code= KEY_VOLUMEUP,
- .gpio= WM831X_P05,
- .active_low= 1,
- .desc= "volume_up",
- .wakeup= 0,
-},
-{
- .code= KEY_CAMERA,
- .gpio= WM831X_P06,
- .active_low= 1,
- .desc= "camera",
- .wakeup= 0,
-},
-{
- .code= KEY_VOLUMEDOWN,
- .gpio= WM831X_P07,
- .active_low= 1,
- .desc= "volume_down",
- .wakeup= 0,
-},
-{
- .code= KEY_END,
- .gpio= WM831X_P09,
- .active_low= 1,
- .desc= "enter",
- .wakeup= 0,
-},
-{
- .code= KEY_MENU,
- .gpio= WM831X_P10,
- .active_low= 1,
- .desc= "menu",
- .wakeup= 0,
-},
-{
- .code= KEY_SEND,
- .gpio= WM831X_P11,
- .active_low= 1,
- .desc= "esc",
- .wakeup= 0,
-},
-{
- .code= KEY_BACK,
- .gpio= WM831X_P12,
- .active_low= 1,
- .desc= "home",
- .wakeup= 0,
-},
-};
-
-struct wm831x_gpio_keys_pdata wm831x_gpio_keys_platdata = {
- .buttons = wm831x_gpio_buttons,
- .nbuttons = ARRAY_SIZE(wm831x_gpio_buttons),
-};
-
-#endif
-
-static struct wm831x_pdata wm831x_platdata = {
-
- /** Called before subdevices are set up */
- .pre_init = wm831x_pre_init,
- /** Called after subdevices are set up */
- .post_init = wm831x_post_init,
- /** Called before subdevices are power down */
- .last_deinit = wm831x_last_deinit,
-
-#if defined(CONFIG_GPIO_WM831X)
- .gpio_base = WM831X_GPIO_EXPANDER_BASE,
- .gpio_pin_num = WM831X_TOTOL_GPIO_NUM,
- .settinginfo = wm831x_gpio_settinginfo,
- .settinginfolen = ARRAY_SIZE(wm831x_gpio_settinginfo),
- .pin_type_init = wm831x_init_pin_type,
- .irq_base = IRQ_BOARD_BASE,
-#endif
- .backlight = &wm831x_backlight_platdata,
-
- .backup = &wm831x_backup_platdata,
-
- .battery = &wm831x_battery_platdata,
- //.wm831x_touch_pdata = NULL,
- //.watchdog = NULL,
-
-#if defined(CONFIG_KEYBOARD_WM831X_GPIO)
- .gpio_keys = &wm831x_gpio_keys_platdata,
-#endif
- /** LED1 = 0 and so on */
- .status = { &wm831x_status_platdata[0], &wm831x_status_platdata[1] },
-
- /** DCDC1 = 0 and so on */
- .dcdc = {
- &wm831x_regulator_init_dcdc[0],
- &wm831x_regulator_init_dcdc[1],
- &wm831x_regulator_init_dcdc[2],
- &wm831x_regulator_init_dcdc[3],
- },
-
- /** EPE1 = 0 and so on */
- .epe = { &wm831x_regulator_init_epe[0], &wm831x_regulator_init_epe[1] },
-
- /** LDO1 = 0 and so on */
- .ldo = {
- &wm831x_regulator_init_ldo[0],
- &wm831x_regulator_init_ldo[1],
- &wm831x_regulator_init_ldo[2],
- &wm831x_regulator_init_ldo[3],
- &wm831x_regulator_init_ldo[4],
- &wm831x_regulator_init_ldo[5],
- &wm831x_regulator_init_ldo[6],
- &wm831x_regulator_init_ldo[7],
- &wm831x_regulator_init_ldo[8],
- &wm831x_regulator_init_ldo[9],
- &wm831x_regulator_init_ldo[10],
- },
- /** ISINK1 = 0 and so on*/
- //.isink = {&wm831x_regulator_init_isink[0], &wm831x_regulator_init_isink[1]},
-};
-#endif
+++ /dev/null
-/* arch/arm/mach-rk30/board-rk30-sdk.c
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <mach/dvfs.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <linux/fb.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#if defined(CONFIG_HDMI_RK30)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-#include "../../../drivers/headset_observe/rk_headset.h"
-#include <linux/mfd/tlv320aic3262-core.h>
-#include <linux/mfd/tlv320aic3262-registers.h>
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-#if defined(CONFIG_ANDROID_TIMED_GPIO)
-#include "../../../drivers/staging/android/timed_gpio.h"
-#endif
-#include <linux/mtk23d.h>
-#include "../../../drivers/tty/serial/sc8800.h"
-#define BP_VOL_PIN RK30_PIN6_PB2
-#define RK30_FB0_MEM_SIZE 8*SZ_1M
-
-#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Macro Define Begin ------------------------*/
-/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
-
-//for back wpx2 back camera
-#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_OV5640 /* back camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_0 0x78
-#define CONFIG_SENSOR_CIF_INDEX_0 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 3
-#define CONFIG_SENSOR_ORIENTATION_0 90
-#define CONFIG_SENSOR_POWER_PIN_0 RK30_PIN4_PC6
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 RK30_PIN4_PB7
-#define CONFIG_SENSOR_FALSH_PIN_0 RK30_PIN4_PD6
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_H
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_H
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000
-
-#define CONFIG_SENSOR_02 RK29_CAM_SENSOR_OV5642 /* back camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_02 0x00//0x78
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 4
-#define CONFIG_SENSOR_CIF_INDEX_02 1
-#define CONFIG_SENSOR_ORIENTATION_02 90
-#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_02 RK30_PIN1_PD6
-#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000
-
-#define CONFIG_SENSOR_01 RK29_CAM_SENSOR_OV5642 /* back camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_01 0x00
-#define CONFIG_SENSOR_CIF_INDEX_01 1
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 4
-#define CONFIG_SENSOR_ORIENTATION_01 90
-#define CONFIG_SENSOR_POWER_PIN_01 RK30_PIN4_PC6
-#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_01 RK30_PIN1_PD6
-#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_H
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_01 30000
-
-
-//front camera for wxp2
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_OV7675 /* front camera sensor 0 */
-#define CONFIG_SENSOR_IIC_ADDR_1 0x42
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 4
-#define CONFIG_SENSOR_CIF_INDEX_1 1
-#define CONFIG_SENSOR_ORIENTATION_1 0//270
-#define CONFIG_SENSOR_POWER_PIN_1 RK30_PIN4_PC6
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_1 RK30_PIN1_PD6
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_H
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000
-
-#define CONFIG_SENSOR_11 RK29_CAM_SENSOR_OV2659 /* front camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_11 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 3
-#define CONFIG_SENSOR_CIF_INDEX_11 0
-#define CONFIG_SENSOR_ORIENTATION_11 270
-#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_11 INVALID_GPIO//RK30_PIN1_PB7
-#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_11 30000
-
-#define CONFIG_SENSOR_12 RK29_CAM_SENSOR_OV2659//RK29_CAM_SENSOR_OV2655 /* front camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_12 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 3
-#define CONFIG_SENSOR_CIF_INDEX_12 0
-#define CONFIG_SENSOR_ORIENTATION_12 270
-#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_12 INVALID_GPIO//RK30_PIN1_PB7
-#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_12 30000
-
-
-
-#endif //#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk30_camera.c"
-/*---------------- Camera Sensor Macro Define End ---------*/
-
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#define CONFIG_SENSOR_POWER_IOCTL_USR 0
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 1
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_RESET_IOCTL_USR
-static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
-static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
-}
-#endif
-//hhb@rock-chips.com
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-//sgm3140 LED driver
-#define CONFIG_SENSOR_FALSH_EN_PIN_0 RK30_PIN4_PD6 //high:enable
-#define CONFIG_SENSOR_FALSH_MODE_PIN_0 RK30_PIN0_PD6 //high:FLASH, low:torch
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- static int init_flag = 0;
- if(init_flag == 0) {
- gpio_request(CONFIG_SENSOR_FALSH_MODE_PIN_0, "camera_falsh_mode");
- rk30_mux_api_set(GPIO0D6_PWM2_NAME, GPIO0D_GPIO0D6);
- gpio_request(CONFIG_SENSOR_FALSH_EN_PIN_0, "camera_falsh_en");
- rk30_mux_api_set(GPIO4D6_SMCDATA14_TRACEDATA14_NAME, GPIO4D_GPIO4D6);
- init_flag = 1;
- }
- switch (on) {
- case Flash_Off: {
- gpio_direction_output(CONFIG_SENSOR_FALSH_EN_PIN_0, 0);
- gpio_direction_output(CONFIG_SENSOR_FALSH_MODE_PIN_0, 1);
- break;
- }
-
- case Flash_On: {
- gpio_direction_output(CONFIG_SENSOR_FALSH_EN_PIN_0, 1);
- gpio_direction_output(CONFIG_SENSOR_FALSH_MODE_PIN_0, 1);
- break;
- }
-
- case Flash_Torch: {
- gpio_direction_output(CONFIG_SENSOR_FALSH_EN_PIN_0, 1);
- gpio_direction_output(CONFIG_SENSOR_FALSH_MODE_PIN_0, 0);
- break;
- }
-
- default: {
- printk("%s..Flash command(%d) is invalidate \n",__FUNCTION__, on);
- gpio_direction_output(CONFIG_SENSOR_FALSH_EN_PIN_0, 0);
- break;
- }
- }
- return 0;
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-
-#if CONFIG_SENSOR_IIC_ADDR_0
-static struct reginfo_t rk_init_data_sensor_reg_0[] =
-{
- {0x0000, 0x00,0,0}
- };
-static struct reginfo_t rk_init_data_sensor_winseqreg_0[] ={
- {0x0000, 0x00,0,0}
- };
-#endif
-
-#if CONFIG_SENSOR_IIC_ADDR_1
-static struct reginfo_t rk_init_data_sensor_reg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_01
-static struct reginfo_t rk_init_data_sensor_reg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_02
-static struct reginfo_t rk_init_data_sensor_reg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_11
-static struct reginfo_t rk_init_data_sensor_reg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_12
-static struct reginfo_t rk_init_data_sensor_reg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] =
-{
- #if CONFIG_SENSOR_IIC_ADDR_0
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_0,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_1
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_1,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_01
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_01,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_02
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_02,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_11
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_11,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_12
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_12,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
-
- };
-#include "../../../drivers/media/video/rk30_camera.c"
-
-#endif /* CONFIG_VIDEO_RK29 */
-
-//hhb@rock-chips.com 2012-04-27
-#if defined(CONFIG_TOUCHSCREEN_SYNAPTICS_S3202)
-#include "../../../drivers/input/touchscreen/synaptics_i2c_rmi4.h"
-struct synaptics_rmi4_platform_data synaptics_s3202_info = {
- .irq_type = IRQF_TRIGGER_FALLING,
- .virtual_keys = true,
- .lcd_width = 640,
- .lcd_height = 960,
- .h_delta = 40,
- .w_delta = 0,
- .x_flip = false,
- .y_flip = false,
- .regulator_en = false,
-};
-#endif
-
-
-#if defined(CONFIG_TOUCHSCREEN_FT5306_WPX2)
-#define TOUCH_RESET_PIN RK30_PIN4_PD0 //for_wpx2
-#define TOUCH_INT_PIN RK30_PIN4_PC2
-int ft5306_init_platform_hw(void)
-{
-
- rk30_mux_api_set(GPIO4C2_SMCDATA2_TRACEDATA2_NAME, GPIO4C_GPIO4C2);
- rk30_mux_api_set(GPIO4D0_SMCDATA8_TRACEDATA8_NAME, GPIO4D_GPIO4D0);
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("ft5406_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("ift5406_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
-
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- mdelay(10);
- gpio_direction_input(TOUCH_INT_PIN);
- mdelay(10);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- msleep(300);
- return 0;
-
-}
-
-void ft5306_exit_platform_hw(void)
-{
- printk("ft5306_exit_platform_hw\n");
- gpio_free(TOUCH_RESET_PIN);
- gpio_free(TOUCH_INT_PIN);
-}
-
-int ft5306_platform_sleep(void)
-{
- //printk("ft5306_platform_sleep\n");
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- return 0;
-}
-
-int ft5306_platform_wakeup(void)
-{
- //printk("ft5306_platform_wakeup\n");
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- return 0;
-}
-
-struct ft5x0x_platform_data ft5306_info = {
-
- .init_platform_hw= ft5306_init_platform_hw,
- .exit_platform_hw= ft5306_exit_platform_hw,
- .ft5x0x_platform_sleep = ft5306_platform_sleep,
- .ft5x0x_platform_wakeup = ft5306_platform_wakeup,
-};
-
-
-#endif
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-#define PWM_ID 0
-#define PWM_MUX_NAME GPIO0A3_PWM0_NAME
-#define PWM_MUX_MODE GPIO0A_PWM0
-#define PWM_MUX_MODE_GPIO GPIO0A_GPIO0A3
-#define PWM_GPIO RK30_PIN0_PA3
-#define PWM_EFFECT_VALUE 0
-
-#define LCD_DISP_ON_PIN
-
-#define LCD_BL_IO RK30_PIN4_PD2
-#define LCD_BL_ON GPIO_HIGH
-#define LCD_BL_OFF GPIO_LOW
-#define LCD_BL_MUX_NAME GPIO4D2_SMCDATA10_TRACEDATA10_NAME
-static int wpx_lcd_bl_io_set(int value)
-{
- int ret = 0;
-
- rk30_mux_api_set(LCD_BL_MUX_NAME, GPIO0D_GPIO0D2);
- ret = gpio_request(LCD_BL_IO, NULL);
- if(ret < 0)
- return ret;
-
- gpio_direction_output(LCD_BL_IO, value);
- gpio_free(LCD_BL_IO);
-
- return 0;
-}
-
-#ifdef LCD_DISP_ON_PIN
-#define BL_EN_MUX_NAME GPIO4D2_SMCDATA10_TRACEDATA10_NAME
-#define BL_EN_MUX_MODE GPIO4D_GPIO4D2
-#define BL_EN_PIN RK30_PIN4_PD2
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
-#ifdef LCD_DISP_ON_PIN
- usleep_range(80*1000, 80*1000);
-#if 0
- rk30_mux_api_set(BL_EN_MUX_NAME, BL_EN_MUX_MODE);
- ret = gpio_request(BL_EN_PIN, NULL);
- if (ret != 0) {
- gpio_free(BL_EN_PIN);
- printk("%s: gpio: %d request failed\n", __func__, BL_EN_PIN);
- return ret;
- }
-
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#else
- wpx_lcd_bl_io_set(LCD_BL_ON);
-#endif
-#endif
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0;
-#ifdef LCD_DISP_ON_PIN
-#if 0
- gpio_free(BL_EN_PIN);
-#else
- wpx_lcd_bl_io_set(LCD_BL_OFF);
-#endif
-#endif
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret = 0;
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- if (gpio_request(PWM_GPIO, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- gpio_direction_output(PWM_GPIO, GPIO_LOW);
-#ifdef LCD_DISP_ON_PIN
-#if 0
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, !BL_EN_VALUE);
-#else
- wpx_lcd_bl_io_set(LCD_BL_OFF);
-#endif
-#endif
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- gpio_free(PWM_GPIO);
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
-#ifdef LCD_DISP_ON_PIN
- usleep_range(80*1000, 80*1000);
-#if 0
- gpio_direction_output(BL_EN_PIN, 1);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#else
- wpx_lcd_bl_io_set(LCD_BL_ON);
-#endif
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .bl_ref = PWM_EFFECT_VALUE,
- .min_brightness = 26,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
- .delay_ms = 1,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-#endif
-
-#ifdef CONFIG_RK29_SUPPORT_MODEM
-
-#define RK30_MODEM_POWER RK30_PIN4_PD1
-#define RK30_MODEM_POWER_IOMUX rk29_mux_api_set(GPIO4D1_SMCDATA9_TRACEDATA9_NAME, GPIO4D_GPIO4D1)
-
-static int rk30_modem_io_init(void)
-{
- printk("%s\n", __FUNCTION__);
- RK30_MODEM_POWER_IOMUX;
-
- return 0;
-}
-
-static struct rk29_io_t rk30_modem_io = {
- .io_addr = RK30_MODEM_POWER,
- .enable = GPIO_HIGH,
- .disable = GPIO_LOW,
- .io_init = rk30_modem_io_init,
-};
-
-static struct platform_device rk30_device_modem = {
- .name = "rk30_modem",
- .id = -1,
- .dev = {
- .platform_data = &rk30_modem_io,
- }
-};
-#endif
-#if defined(CONFIG_RK29_SC8800)
-// tdsc8800
-static int tdsc8800_io_init(void)
-{
-
- return 0;
-}
-
-static int tdsc8800_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk2818_23d_data rk29_tdsc8800_info = {
- .io_init = tdsc8800_io_init,
- .io_deinit = tdsc8800_io_deinit,
- .bp_power = BP_VOL_PIN,
- .bp_power_active_low = 1,
-};
-struct platform_device rk29_device_tdsc8800 = {
- .name = "tdsc8800",
- .id = -1,
- .dev = {
- .platform_data = &rk29_tdsc8800_info,
- }
- };
-//sc8800
-static int sc8800_io_init(void)
-{
- rk30_mux_api_set(GPIO2B5_LCDC1DATA13_SMCADDR17_HSADCDATA8_NAME, GPIO2B_GPIO2B5);
- rk30_mux_api_set(GPIO2A2_LCDCDATA2_SMCADDR6_NAME, GPIO2A_GPIO2A2);
-
- rk30_mux_api_set(GPIO2C2_LCDC1DATA18_SMCBLSN1_HSADCDATA5_NAME, GPIO2C_GPIO2C2);//AP_ASK_BP_TEST1
- gpio_request(RK30_PIN2_PC2, NULL);
- gpio_direction_output(RK30_PIN2_PC2, 0);
- gpio_request(RK30_PIN6_PB0, NULL);//AP_ON/OFF_BP
- gpio_direction_output(RK30_PIN6_PB0, 0);
-
-
- rk30_mux_api_set(GPIO2C3_LCDC1DATA19_SPI1CLK_HSADCDATA0_NAME, GPIO2C_SPI1_CLK);//spi 1
- rk30_mux_api_set(GPIO2C4_LCDC1DATA20_SPI1CSN0_HSADCDATA1_NAME, GPIO2C_SPI1_CSN0);
- rk30_mux_api_set(GPIO2C5_LCDC1DATA21_SPI1TXD_HSADCDATA2_NAME, GPIO2C_SPI1_TXD);
- rk30_mux_api_set(GPIO2C6_LCDC1DATA22_SPI1RXD_HSADCDATA3_NAME, GPIO2C_SPI1_RXD);
- return 0;
-}
-
-static int sc8800_io_deinit(void)
-{
-
- return 0;
-}
-
-static struct plat_sc8800 sc8800_plat_data = {
- .slav_rts_pin = RK30_PIN6_PA0,
- .slav_rdy_pin = RK30_PIN6_PA1,
- .master_rts_pin = RK30_PIN2_PB5,
- .master_rdy_pin = RK30_PIN2_PA2,
- //.poll_time = 100,
- .io_init = sc8800_io_init,
- .io_deinit = sc8800_io_deinit,
-};
-static struct rk29xx_spi_chip sc8800_spi_chip = {
- //.poll_mode = 1,
- .enable_dma = 1,
-};
-
-#endif
-
-static struct spi_board_info board_spi_devices[] = {
-
-#if defined(CONFIG_RK29_SC8800)
- {
- .modalias = "sc8800",
- .bus_num = 1,
- .platform_data = &sc8800_plat_data,
- .max_speed_hz = 13*1000*1000,
- .chip_select = 0,
- .controller_data = &sc8800_spi_chip,
- },
-#endif
-
-};
-
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN RK30_PIN4_PC0
-
-static int mma8452_init_platform_hw(void)
-{
- rk30_mux_api_set(GPIO4C0_SMCDATA0_TRACEDATA0_NAME, GPIO4C_GPIO4C0);
-
- return 0;
-}
-
-static struct sensor_platform_data mma8452_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma8452_init_platform_hw,
- .orientation = {0, 1, 0, 0, 0, -1, 1, 0, 0},
-};
-#endif
-
-#if defined (CONFIG_GS_LIS3DH)
-#define LIS3DH_INT_PIN RK30_PIN4_PC0
-
-static int lis3dh_init_platform_hw(void)
-{
- rk30_mux_api_set(GPIO4C0_SMCDATA0_TRACEDATA0_NAME, GPIO4C_GPIO4C0);
-
- return 0;
-}
-
-static struct sensor_platform_data lis3dh_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lis3dh_init_platform_hw,
- .orientation = {0, 1, 0, 0, 0, -1, 1, 0, 0},
-};
-
-#endif
-
-#if defined (CONFIG_GS_KXTIK)
-#define KXTIK_INT_PIN RK30_PIN4_PC0
-
-static int kxtik_init_platform_hw(void)
-{
- rk30_mux_api_set(GPIO4C0_SMCDATA0_TRACEDATA0_NAME, GPIO4C_GPIO4C0);
-
- return 0;
-}
-
-static struct sensor_platform_data kxtik_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = kxtik_init_platform_hw,
- .orientation = {0, 1, 0, 0, 0, -1, 1, 0, 0},
-};
-
-#endif
-
-
-
-#if defined (CONFIG_RK_HEADSET_DET) || defined (CONFIG_RK_HEADSET_IRQ_HOOK_ADC_DET)
-
-static int rk_headset_io_init(int gpio)
-{
- int ret;
- ret = gpio_request(gpio, "headset_input");
- if(ret)
- return ret;
-
- rk30_mux_api_set(GPIO0D3_I2S22CHLRCKTX_SMCADVN_NAME, GPIO0D_GPIO0D3);
- gpio_pull_updown(gpio, PullDisable);
- gpio_direction_input(gpio);
- return 0;
-};
-
-struct rk_headset_pdata rk_headset_info = {
- .Headset_gpio = RK30_PIN0_PD3,
- .headset_in_type = HEADSET_IN_HIGH,
- .Hook_adc_chn = 2,
- .hook_key_code = KEY_MEDIA,
- .headset_io_init = rk_headset_io_init,
-};
-
-struct platform_device rk_device_headset = {
- .name = "rk_headsetdet",
- .id = 0,
- .dev = {
- .platform_data = &rk_headset_info,
- }
-};
-#endif
-
-#if defined (CONFIG_COMPASS_AK8975)
-static struct sensor_platform_data akm8975_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {0, 1, 0},
- {1, 0, 0},
- {0, 0, -1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-#if defined(CONFIG_GYRO_L3G4200D)
-
-#include <linux/l3g4200d.h>
-#define L3G4200D_INT_PIN RK30_PIN4_PC3
-
-static int l3g4200d_init_platform_hw(void)
-{
- rk30_mux_api_set(GPIO4C3_SMCDATA3_TRACEDATA3_NAME, GPIO4C_GPIO4C3);
-
- return 0;
-}
-
-static struct sensor_platform_data l3g4200d_info = {
- .type = SENSOR_TYPE_GYROSCOPE,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .orientation = {1, 0, 0, 0, -1, 0, 0, 0, -1},
- .init_platform_hw = l3g4200d_init_platform_hw,
- .x_min = 40,//x_min,y_min,z_min = (0-100) according to hardware
- .y_min = 40,
- .z_min = 20,
-};
-
-#endif
-
-
-#ifdef CONFIG_LS_CM3217
-static struct sensor_platform_data cm3217_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 0,
- .poll_delay_ms = 500,
-};
-
-#endif
-
-
-#if defined(CONFIG_PS_AL3006)
-static struct sensor_platform_data proximity_al3006_info = {
- .type = SENSOR_TYPE_PROXIMITY,
- .irq_enable = 1,
- .poll_delay_ms = 200,
-};
-#endif
-
-#if defined(CONFIG_PS_STK3171)
-static struct sensor_platform_data proximity_stk3171_info = {
- .type = SENSOR_TYPE_PROXIMITY,
- .irq_enable = 1,
- .poll_delay_ms = 200,
-};
-#endif
-
-
-#if defined(CONFIG_LS_AL3006)
-static struct sensor_platform_data light_al3006_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 1,
- .poll_delay_ms = 200,
-};
-#endif
-
-#if defined(CONFIG_LS_STK3171)
-static struct sensor_platform_data light_stk3171_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 1,
- .poll_delay_ms = 200,
-};
-#endif
-
-
-
-#ifdef CONFIG_FB_ROCKCHIP
-
-/*****************************************************************************************
- * lcd devices
- * author: hhb@rock-chips.com
- *****************************************************************************************/
-
-#define LCD_TXD_PIN RK30_PIN1_PA6
-#define LCD_CLK_PIN RK30_PIN1_PA5
-#define LCD_CS_PIN RK30_PIN1_PA4
-#define LCD_RST_PIN RK30_PIN4_PC7
-
-/*****************************************************************************************
-* frame buffer devices
-* author: hhb@rock-chips.com
-*****************************************************************************************/
-#define FB_ID 0
-#define FB_DISPLAY_ON_PIN INVALID_GPIO//RK29_PIN6_PD0
-#define FB_LCD_STANDBY_PIN INVALID_GPIO//RK29_PIN6_PD1
-#define FB_LCD_CABC_EN_PIN INVALID_GPIO//RK29_PIN6_PD2
-#define FB_MCU_FMK_PIN INVALID_GPIO
-
-#define FB_DISPLAY_ON_VALUE GPIO_HIGH
-#define FB_LCD_STANDBY_VALUE GPIO_HIGH
-
-
-//#endif
-static int rk29_lcd_io_init(void)
-{
- int ret = 0;
-
- //printk("rk29_lcd_io_init\n");
-
- ret = gpio_request(LCD_TXD_PIN, NULL);
- if (ret != 0) {
- gpio_free(LCD_TXD_PIN);
- printk("%s: request LCD_TXD_PIN error\n", __func__);
- return -EIO;
- }
-
- ret = gpio_request(LCD_CLK_PIN, NULL);
- if (ret != 0) {
- gpio_free(LCD_CLK_PIN);
- printk("%s: request LCD_CLK_PIN error\n", __func__);
- return -EIO;
- }
-
- ret = gpio_request(LCD_CS_PIN, NULL);
- if (ret != 0) {
- gpio_free(LCD_CS_PIN);
- printk("%s: request LCD_CS_PIN error\n", __func__);
- return -EIO;
- }
-
- ret = gpio_request(LCD_RST_PIN, NULL);
- if (ret != 0) {
- gpio_free(LCD_CS_PIN);
- printk("%s: request LCD_RST_PIN error\n", __func__);
- return -EIO;
- }
- rk30_mux_api_set(GPIO1A6_UART1CTSN_SPI0RXD_NAME,GPIO1A_GPIO1A6);
- rk30_mux_api_set(GPIO1A5_UART1SOUT_SPI0CLK_NAME,GPIO1A_GPIO1A5);
- rk30_mux_api_set(GPIO1A4_UART1SIN_SPI0CSN0_NAME,GPIO1A_GPIO1A4);
-
- rk30_mux_api_set(GPIO0C7_TRACECTL_SMCADDR3_NAME,GPIO4C_GPIO4C7);
-
- gpio_direction_output(LCD_CS_PIN, 1);
- gpio_direction_output(LCD_CLK_PIN, 1);
- gpio_direction_output(LCD_TXD_PIN, 1);
- gpio_direction_output(LCD_RST_PIN, 1);
-
- return ret;
-}
-
-static int rk29_lcd_io_deinit(void)
-{
- int ret = 0;
-
- gpio_direction_input(LCD_CS_PIN);
- gpio_direction_input(LCD_CLK_PIN);
- gpio_direction_input(LCD_TXD_PIN);
- gpio_direction_input(LCD_RST_PIN);
- gpio_free(LCD_CS_PIN);
- gpio_free(LCD_CLK_PIN);
- gpio_free(LCD_TXD_PIN);
- gpio_free(LCD_RST_PIN);
- //rk30_mux_api_set(GPIO1A6_UART1CTSN_SPI0RXD_NAME,GPIO1A_GPIO1A6);
- //rk30_mux_api_set(GPIO1A5_UART1SOUT_SPI0CLK_NAME,GPIO1A_GPIO1A5);
- //rk30_mux_api_set(GPIO1A4_UART1SIN_SPI0CSN0_NAME,GPIO1A_GPIO1A4);
-
- //rk30_mux_api_set(GPIO0C7_TRACECTL_SMCADDR3_NAME,GPIO4C_GPIO4C7);
- return ret;
-}
-
-static struct rk29lcd_info rk29_lcd_info = {
- .txd_pin = LCD_TXD_PIN,
- .clk_pin = LCD_CLK_PIN,
- .cs_pin = LCD_CS_PIN,
- .reset_pin = LCD_RST_PIN,
- .io_init = rk29_lcd_io_init,
- .io_deinit = rk29_lcd_io_deinit,
-};
-
-
-#define LCD_EN_MUX_NAME GPIO4D2_SMCDATA10_TRACEDATA10_NAME //for wpx2
-#define LCD_EN_PIN RK30_PIN4_PD2
-#define LCD_EN_VALUE GPIO_HIGH
-
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
-#if 0
- rk30_mux_api_set(LCD_EN_MUX_NAME, GPIO0D_GPIO0D2);
- ret = gpio_request(LCD_EN_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_EN_PIN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_EN_PIN, 1);
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
- }
-#else
- //wpx_lcd_bl_io_set(LCD_BL_OFF);
-#endif
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
-#if 0
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE ? 0:1);
-#else
- //wpx_lcd_bl_io_set(LCD_BL_OFF);
-#endif
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
-#if 0
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
-#else
- //wpx_lcd_bl_io_set(LCD_BL_ON);
-#endif
- return 0;
-}
-
-#if defined(CONFIG_LCDC0_RK30)
-struct rk29fb_info lcdc0_screen_info = {
- .fb_id = FB_ID,
- .prop = PRMRY, //primary display device
- .lcd_info = &rk29_lcd_info,
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK30)
-struct rk29fb_info lcdc1_screen_info = {
- #if defined(CONFIG_HDMI_RK30)
- .prop = EXTEND, //extend display device
- .lcd_info = NULL,
- .set_screen_info = hdmi_set_info,
- #endif
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-
-#ifdef CONFIG_ANDROID_TIMED_GPIO
-static struct timed_gpio timed_gpios[] = {
- {
- .name = "vibrator",
- .gpio = RK30_PIN0_PA4,
- .max_timeout = 1000,
- .active_low = 0,
- .adjust_time =20, //adjust for diff product
- },
-};
-
-static struct timed_gpio_platform_data rk29_vibrator_info = {
- .num_gpios = 1,
- .gpios = timed_gpios,
-};
-
-static struct platform_device rk29_device_vibrator = {
- .name = "timed-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_vibrator_info,
- },
-
-};
-#endif
-
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
-static struct gpio_led rk29_leds[] = {
- {
- .name = "button-backlight",
- .gpio = RK30_PIN4_PD7,
- .default_trigger = "timer",
- .active_low = 0,
- .retain_state_suspended = 0,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- },
-};
-
-static struct gpio_led_platform_data rk29_leds_pdata = {
- .leds = rk29_leds,
- .num_leds = ARRAY_SIZE(rk29_leds),
-};
-
-static struct platform_device rk29_device_gpio_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_leds_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_RK_IRDA
-#define IRDA_IRQ_PIN RK30_PIN6_PA1
-
-static int irda_iomux_init(void)
-{
- int ret = 0;
-
- //irda irq pin
- ret = gpio_request(IRDA_IRQ_PIN, NULL);
- if (ret != 0) {
- gpio_free(IRDA_IRQ_PIN);
- printk(">>>>>> IRDA_IRQ_PIN gpio_request err \n ");
- }
- gpio_pull_updown(IRDA_IRQ_PIN, PullDisable);
- gpio_direction_input(IRDA_IRQ_PIN);
-
- return 0;
-}
-
-static int irda_iomux_deinit(void)
-{
- gpio_free(IRDA_IRQ_PIN);
- return 0;
-}
-
-static struct irda_info rk29_irda_info = {
- .intr_pin = IRDA_IRQ_PIN,
- .iomux_init = irda_iomux_init,
- .iomux_deinit = irda_iomux_deinit,
- //.irda_pwr_ctl = bu92747guw_power_ctl,
-};
-
-static struct platform_device irda_device = {
-#ifdef CONFIG_RK_IRDA_NET
- .name = "rk_irda",
-#else
- .name = "bu92747_irda",
-#endif
- .id = -1,
- .dev = {
- .platform_data = &rk29_irda_info,
- }
-};
-#endif
-
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and sdio.noted by xbw at 2012-03-05
-**************************************************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "board-rk30-phone-sdmmc.c"
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
-#define SDMMC0_WRITE_PROTECT_PIN RK30_PIN3_PB7 //According to your own project to set the value of write-protect-pin.
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
-#define SDMMC1_WRITE_PROTECT_PIN RK30_PIN3_PC7 //According to your own project to set the value of write-protect-pin.
-#endif
-
-#define RK29SDK_WIFI_SDIO_CARD_DETECT_N RK30_PIN6_PB2
-
-#endif //endif ---#ifdef CONFIG_SDMMC_RK29
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- rk30_mux_api_set(GPIO3B1_SDMMC0CMD_NAME, GPIO3B_SDMMC0_CMD);
- rk30_mux_api_set(GPIO3B0_SDMMC0CLKOUT_NAME, GPIO3B_SDMMC0_CLKOUT);
- rk30_mux_api_set(GPIO3B2_SDMMC0DATA0_NAME, GPIO3B_SDMMC0_DATA0);
- rk30_mux_api_set(GPIO3B3_SDMMC0DATA1_NAME, GPIO3B_SDMMC0_DATA1);
- rk30_mux_api_set(GPIO3B4_SDMMC0DATA2_NAME, GPIO3B_SDMMC0_DATA2);
- rk30_mux_api_set(GPIO3B5_SDMMC0DATA3_NAME, GPIO3B_SDMMC0_DATA3);
-
- rk30_mux_api_set(GPIO3B6_SDMMC0DETECTN_NAME, GPIO3B_GPIO3B6);
-
- rk30_mux_api_set(GPIO3A7_SDMMC0PWREN_NAME, GPIO3A_GPIO3A7);
- gpio_request(RK30_PIN3_PA7, "sdmmc-power");
- gpio_direction_output(RK30_PIN3_PA7, GPIO_LOW);
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- rk30_mux_api_set(GPIO3B6_SDMMC0DETECTN_NAME, GPIO3B_SDMMC0_DETECT_N);
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
- .detect_irq = INVALID_GPIO, //RK30_PIN3_PB6, // INVALID_GPIO
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
-#else
- .write_prt = INVALID_GPIO,
-#endif
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- rk30_mux_api_set(GPIO3C0_SMMC1CMD_NAME, GPIO3C_SMMC1_CMD);
- rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_NAME, GPIO3C_SDMMC1_CLKOUT);
- rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_NAME, GPIO3C_SDMMC1_DATA0);
- rk30_mux_api_set(GPIO3C2_SDMMC1DATA1_NAME, GPIO3C_SDMMC1_DATA1);
- rk30_mux_api_set(GPIO3C3_SDMMC1DATA2_NAME, GPIO3C_SDMMC1_DATA2);
- rk30_mux_api_set(GPIO3C4_SDMMC1DATA3_NAME, GPIO3C_SDMMC1_DATA3);
- //rk30_mux_api_set(GPIO3C6_SDMMC1DETECTN_NAME, GPIO3C_SDMMC1_DETECT_N);
-
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-#if 0
- .detect_irq = RK29SDK_WIFI_SDIO_CARD_DETECT_N,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
-#else
- .detect_irq = INVALID_GPIO,
- .enable_sd_wakeup = 0,
-#endif
-
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-/**************************************************************************************************
- * the end of setting for SDMMC devices
-**************************************************************************************************/
-
-#ifdef CONFIG_BATTERY_RK30_ADC
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = RK30_PIN6_PA5,
- .batt_low_pin = RK30_PIN6_PA0,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = RK30_PIN6_PA6,
- .dc_det_level = GPIO_LOW,
- .charge_ok_level = GPIO_HIGH,
-};
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-
-#ifdef CONFIG_RFKILL_RK
-// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
-static struct rfkill_rk_platform_data rfkill_rk_platdata = {
- .type = RFKILL_TYPE_BLUETOOTH,
-
- .poweron_gpio = { // BT_REG_ON
- .io = RK30_PIN4_PD5,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO4D5_SMCDATA13_TRACEDATA13_NAME,
- .fgpio = GPIO4D_GPIO4D5,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN3_PD1, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = GPIO3D1_SDMMC1BACKENDPWR_NAME,
- .fgpio = GPIO3D_GPIO3D1,
- },
- },
-
- .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
- .io = RK30_PIN3_PC6, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C6_SDMMC1DETECTN_NAME,
- .fgpio = GPIO3C_GPIO3C6,
- },
- },
-
- .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .gpio = {
- .io = RK30_PIN6_PA5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
- .iomux = {
- .name = NULL,
- },
- },
- },
-
- .rts_gpio = { // UART_RTS, enable or disable BT's data coming
- .io = RK30_PIN1_PA3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = GPIO1A3_UART0RTSN_NAME,
- .fgpio = GPIO1A_GPIO1A3,
- .fmux = GPIO1A_UART0_RTS_N,
- },
- },
-};
-
-static struct platform_device device_rfkill_rk = {
- .name = "rfkill_rk",
- .id = -1,
- .dev = {
- .platform_data = &rfkill_rk_platdata,
- },
-};
-#endif
-
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- &rk29_device_backlight,
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
- &device_fb,
-#endif
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_ANDROID_TIMED_GPIO
- &rk29_device_vibrator,
-#endif
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
- &rk29_device_gpio_leds,
-#endif
-#ifdef CONFIG_RK_IRDA
- &irda_device,
-#endif
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- &rk29sdk_wifi_device,
-#endif
-#ifdef CONFIG_RFKILL_RK
- &device_rfkill_rk,
-#endif
-#ifdef CONFIG_RK29_SUPPORT_MODEM
- &rk30_device_modem,
-#endif
-#if defined(CONFIG_TDSC8800)
-&rk29_device_tdsc8800,
-#endif
-#if defined (CONFIG_RK_HEADSET_DET) || defined (CONFIG_RK_HEADSET_IRQ_HOOK_ADC_DET)
- &rk_device_headset,
-#endif
-#ifdef CONFIG_BATTERY_RK30_ADC
- &rk30_device_adc_battery,
-#endif
-};
-
-static struct aic3262_gpio_setup aic3262_gpio[] = {
- { // GPIO1
- .used = 0,
- .in = 0,
- .value = AIC3262_GPIO1_FUNC_INT1_OUTPUT ,
-
- },
- {// GPIO2
- .used = 0,
- .in = 0,
- .value = AIC3262_GPIO2_FUNC_CLOCK_OUTPUT,
- },
- {// GPI1
- .used = 1,
- .in = 1,
- .value = 0,
- },
- {// GPI2
- .used = 1,
- .in = 1,
- .value = AIC3262_GPO1_FUNC_DISABLED,
- },
- {// GPO1
- .used = 0,
- .in = 0,
- .value = AIC3262_GPO1_FUNC_ADC_MOD_CLK_OUTPUT,
- },
-};
-static struct aic3262_pdata aic3262_codec_pdata = {
- .gpio = aic3262_gpio,
- .gpio_reset = RK30_PIN0_PB7,
-};
-
-// i2c
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1d,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_GS_LIS3DH)
- {
- .type = "gs_lis3dh",
- .addr = 0x19,
- .flags = 0,
- .irq = LIS3DH_INT_PIN,
- .platform_data = &lis3dh_info,
- },
-#endif
-
-#if defined (CONFIG_GS_KXTIK)
- {
- .type = "gs_kxtik",
- .addr = 0x0F,
- .flags = 0,
- .irq = KXTIK_INT_PIN,
- .platform_data = &kxtik_info,
- },
-#endif
-
-
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN4_PC1,
- .platform_data = &akm8975_info,
- },
-#endif
-#if defined (CONFIG_GYRO_L3G4200D)
- {
- .type = "l3g4200d_gryo",
- .addr = 0x69,
- .flags = 0,
- .irq = L3G4200D_INT_PIN,
- .platform_data = &l3g4200d_info,
- },
-#endif
-#if defined (CONFIG_INPUT_LPSENSOR_AL3006)
- {
- .type = "al3006",
- .addr = 0x1c, //sel = 0; if sel =1, then addr = 0x1D
- .flags = 0,
- .irq = RK30_PIN6_PA2,
- },
-#endif
-
-#if defined (CONFIG_LS_AL3006)
- {
- .type = "light_al3006",
- .addr = 0x1c, //sel = 0; if sel =1, then addr = 0x1D
- .flags = 0,
- .irq = RK30_PIN6_PA2,
- .platform_data = &light_al3006_info,
- },
-#endif
-#if defined (CONFIG_LS_STK3171)
- {
- .type = "ls_stk3171",
- .addr = 0x48,
- .flags = 0,
- .irq = RK30_PIN6_PA2,
- .platform_data = &light_stk3171_info,
- },
-#endif
-
-
-#if defined (CONFIG_PS_AL3006)
- {
- .type = "proximity_al3006",
- .addr = 0x1c, //sel = 0; if sel =1, then addr = 0x1D
- .flags = 0,
- .irq = RK30_PIN6_PA2,
- .platform_data = &proximity_al3006_info,
- },
-#endif
-
-#if defined (CONFIG_PS_STK3171)
- {
- .type = "ps_stk3171",
- .addr = 0x48,
- .flags = 0,
- .irq = RK30_PIN6_PA2,
- .platform_data = &proximity_stk3171_info,
- },
-#endif
-
-
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-
-#if defined (CONFIG_SND_SOC_TLV320AIC326X)
- {
- .type = "tlv320aic3262",
- .addr = 0x18,
- .flags = 0,
- .platform_data = &aic3262_codec_pdata,
- },
-#endif
-
-#if defined (CONFIG_SND_SOC_RT5631)
- {
- .type = "rt5631",
- .addr = 0x1a,
- .flags = 0,
- },
-#endif
-
-#ifdef CONFIG_MFD_RK610
- {
- .type = "rk610_ctl",
- .addr = 0x40,
- .flags = 0,
- },
-#ifdef CONFIG_RK610_TVOUT
- {
- .type = "rk610_tvout",
- .addr = 0x42,
- .flags = 0,
- },
-#endif
-#ifdef CONFIG_HDMI_RK610
- {
- .type = "rk610_hdmi",
- .addr = 0x46,
- .flags = 0,
- .irq = RK29_PIN5_PA2,
- },
-#endif
-#ifdef CONFIG_SND_SOC_RK610
- {//RK610_CODEC addr from 0x60 to 0x80 (0x60~0x80)
- .type = "rk610_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
-#endif
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C1_RK30
-#define DC3_VCC_DDR_VOL 1500000 //for vcc_ddr3 1.5v
-#define DC5_VCC_DDR_VOL 0000000 //
-#include "board-rk30-phone-twl60xx.c"
-static struct i2c_board_info __initdata i2c1_info[] = {
-
-#if defined (CONFIG_TWL4030_CORE)
- {
- .type = "twl6032",
- .addr = 0x48,
- .flags = 0,
- .irq = RK30_PIN6_PA4,
- .platform_data = &tps80032_data,
-
- },
-
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-
-#if defined (CONFIG_TOUCHSCREEN_SYNAPTICS_S3202)
-{
- .type = "synaptics_rmi4_i2c",
- .addr = 0x20, //0x70
- .flags = 0,
- .irq = RK30_PIN4_PC2,
- .platform_data = &synaptics_s3202_info,
-},
-#endif
-
-#if defined (CONFIG_TOUCHSCREEN_FT5306_WPX2)
-{
- .type = "ft5x0x_ts",
- .addr = 0x38,
- .flags = 0,
- .irq = RK30_PIN4_PC2,//RK30_PIN2_PC2,
- .platform_data = &ft5306_info,
-},
-#endif
-
-#if defined (CONFIG_LS_CM3217)
- {
- .type = "light_cm3217",
- .addr = 0x10,
- .flags = 0,
- .platform_data = &cm3217_info,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-
-static struct i2c_board_info __initdata i2c3_info[] = {
-
-
-};
-#endif
-
-#ifdef CONFIG_I2C4_RK30
-static struct i2c_board_info __initdata i2c4_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO// RK30_PIN2_PD6 //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO//RK30_PIN2_PD7 //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- //set iomux (gpio) here
- //rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME, GPIO2D_GPIO2D7);
- //rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME, GPIO2D_GPIO2D6);
-
- return 0;
-}
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C4_RK30
- i2c_register_board_info(4, i2c4_info, ARRAY_SIZE(i2c4_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(5, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-
-static void rk30_pm_power_off(void)
-{
- printk(KERN_ERR "rk30_pm_power_off start...\n");
-#if defined(CONFIG_TWL4030_CORE)
- twl6030_poweroff();
-#endif
- while (1);
-}
-
-/**********************************************************************************************
- *
- * The virtual keys for android "back", "home", "menu", "search", these four keys are touch key
- * on the touch screen panel. (added by hhb@rock-chips.com 2011.04.21)
- * attention please: kobj_attribute.attr.name virtualkeys.synaptics_rmi4_i2c should be the same as
- * the input device in the touch screen driver.
- ***********************************************************************************************/
-static ssize_t rk_virtual_keys_show(struct kobject *kobj,
- struct kobj_attribute *attr, char *buf)
-{
-#if (defined(CONFIG_TOUCHSCREEN_SYNAPTICS_S3202))
- printk("rk_virtual_keys_show S3202\n");
- /* centerx;centery;width;height; */
- return sprintf(buf,
- __stringify(EV_KEY) ":" __stringify(KEY_BACK) ":100:980:100:40"
- ":" __stringify(EV_KEY) ":" __stringify(KEY_MENU) ":200:980:100:40"
- ":" __stringify(EV_KEY) ":" __stringify(KEY_HOMEPAGE) ":300:980:100:40"
- ":" __stringify(EV_KEY) ":" __stringify(KEY_SEARCH) ":400:980:100:40"
- "\n");
-#elif defined(CONFIG_TOUCHSCREEN_FT5306_WPX2)
- printk("rk_virtual_keys_show FT5306\n");
- /* centerx;centery;width;height; */
- return sprintf(buf,
- __stringify(EV_KEY) ":" __stringify(KEY_BACK) ":320:840:70:40"
- ":" __stringify(EV_KEY) ":" __stringify(KEY_MENU) ":190:840:80:40"
- ":" __stringify(EV_KEY) ":" __stringify(KEY_HOMEPAGE) ":50:840:100:40"
- ":" __stringify(EV_KEY) ":" __stringify(KEY_SEARCH) ":440:840:80:40"
- "\n");
-#endif
- return 0;
-}
-
-static struct kobj_attribute rk_virtual_keys_attr = {
- .attr = {
-#if defined(CONFIG_TOUCHSCREEN_SYNAPTICS_S3202)
- .name = "virtualkeys.synaptics_rmi4_i2c",
-#elif defined(CONFIG_TOUCHSCREEN_FT5306_WPX2)
- .name = "virtualkeys.ft5x0x_ts-touchscreen",
-#else
- .name = "virtualkeys",
-#endif
- .mode = S_IRUGO,
- },
- .show = &rk_virtual_keys_show,
-};
-
-static struct attribute *rk_properties_attrs[] = {
- &rk_virtual_keys_attr.attr,
- NULL
-};
-
-static struct attribute_group rk_properties_attr_group = {
- .attrs = rk_properties_attrs,
-};
-static int rk_virtual_keys_init(void)
-{
- int ret;
- struct kobject *properties_kobj;
- printk("rk_virtual_keys_init \n");
- properties_kobj = kobject_create_and_add("board_properties", NULL);
- if (properties_kobj)
- ret = sysfs_create_group(properties_kobj,
- &rk_properties_attr_group);
- if (!properties_kobj || ret)
- {
- printk("failed to create board_properties for virtual key\n");
- }
- return ret;
-}
-
-/*************************end of virtual_keys************************/
-
-
-
-
-static void __init machine_rk30_board_init(void)
-{
- pm_power_off = rk30_pm_power_off;
-
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- board_usb_detect_init(RK30_PIN6_PA3);
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- rk29sdk_wifi_bt_gpio_control_init();
-#endif
-
-#if (defined(CONFIG_TOUCHSCREEN_SYNAPTICS_S3202)) || defined(CONFIG_TOUCHSCREEN_FT5306_WPX2)
- rk_virtual_keys_init();
-#endif
-
-}
-
-static void __init rk30_reserve(void)
-{
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0", RK30_FB0_MEM_SIZE);
- resource_fb[0].end = resource_fb[0].start + RK30_FB0_MEM_SIZE - 1;
- resource_fb[1].start = board_mem_reserve_add("ipp buf", RK30_FB0_MEM_SIZE);
- resource_fb[1].end = resource_fb[1].start + RK30_FB0_MEM_SIZE - 1;
- resource_fb[2].start = board_mem_reserve_add("fb2", RK30_FB0_MEM_SIZE);
- resource_fb[2].end = resource_fb[2].start + RK30_FB0_MEM_SIZE - 1;
-#endif
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
- board_mem_reserved();
-}
-
-/**
- * dvfs_cpu_logic_table: table for arm and logic dvfs
- * @frequency : arm frequency
- * @cpu_volt : arm voltage depend on frequency
- * @logic_volt : logic voltage arm requests depend on frequency
- * comments : min arm/logic voltage
- */
-static struct dvfs_arm_table dvfs_cpu_logic_table[] = {
- {.frequency = 252 * 1000, .cpu_volt = 1050 * 1000, .logic_volt = 1050 * 1000},//0.975V/1.000V
- {.frequency = 504 * 1000, .cpu_volt = 1050 * 1000, .logic_volt = 1100 * 1000},//0.975V/1.000V
- {.frequency = 816 * 1000, .cpu_volt = 1100 * 1000, .logic_volt = 1150 * 1000},//1.000V/1.025V
- {.frequency = 1008 * 1000, .cpu_volt = 1100 * 1000, .logic_volt = 1150 * 1000},//1.025V/1.050V
- {.frequency = 1200 * 1000, .cpu_volt = 1175 * 1000, .logic_volt = 1200 * 1000},//1.100V/1.050V
- {.frequency = 1272 * 1000, .cpu_volt = 1225 * 1000, .logic_volt = 1200 * 1000},//1.150V/1.100V
- {.frequency = 1416 * 1000, .cpu_volt = 1300 * 1000, .logic_volt = 1200 * 1000},//1.225V/1.100V
- {.frequency = 1512 * 1000, .cpu_volt = 1350 * 1000, .logic_volt = 1250 * 1000},//1.300V/1.150V
- {.frequency = 1608 * 1000, .cpu_volt = 1375 * 1000, .logic_volt = 1275 * 1000},//1.325V/1.175V
- {.frequency = CPUFREQ_TABLE_END},
-};
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- {.frequency = 266 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1275 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1125 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
-static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
-static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
-
-void __init board_clock_init(void)
-{
- rk30_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
- dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
-}
-
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk30_fixup,
- .reserve = &rk30_reserve,
- .map_io = rk30_map_io,
- .init_irq = rk30_init_irq,
- .timer = &rk30_timer,
- .init_machine = machine_rk30_board_init,
-MACHINE_END
+++ /dev/null
-#include <mach/gpio.h>
-#include <plat/key.h>
-
-#define EV_ENCALL KEY_F4
-#define EV_MENU KEY_F1
-
-#define PRESS_LEV_LOW 1
-#define PRESS_LEV_HIGH 0
-
-static struct rk29_keys_button key_button[] = {
-
-#ifdef CONFIG_MACH_RK30_PHONE_PAD_DS763
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .adc_value = 180,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .adc_value = 1,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .adc_value = 460,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK30_PIN6_PA2,
- .active_low = PRESS_LEV_LOW,
- //.code_long_press = EV_ENCALL,
- .wakeup = 1,
- },
-#endif
-
-#ifdef CONFIG_MACH_RK30_PHONE_PAD_C8003
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .adc_value = 1,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .gpio = RK30_PIN4_PC5,
- .active_low = PRESS_LEV_LOW,
- },
-
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK30_PIN6_PA2,
- .active_low = PRESS_LEV_LOW,
- //.code_long_press = EV_ENCALL,
- .wakeup = 1,
- },
-#endif
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = 1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
+++ /dev/null
-/* arch/arm/mach-rk30/board-rk30-sdk.c
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <mach/dvfs.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <linux/power/smb347-charger.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-
-#include "../../../drivers/headset_observe/rk_headset.h"
-#if defined(CONFIG_MFD_RK610)
-#include <linux/mfd/rk610_core.h>
-#endif
-
-#if defined(CONFIG_RK_HDMI)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-
-#if defined (CONFIG_BP_AUTO)
-#include <linux/bp-auto.h>
-#endif
-#if defined(CONFIG_ANDROID_TIMED_GPIO)
-#include "../../../drivers/staging/android/timed_gpio.h"
-#endif
-
-/* Android Parameter */
-static int ap_mdm = 0;
-module_param(ap_mdm, int, 0644);
-static int ap_has_alsa = 0;
-module_param(ap_has_alsa, int, 0644);
-static int ap_data_only = 2;
-module_param(ap_data_only, int, 0644);
-static int ap_has_earphone = 0;
-module_param(ap_has_earphone, int, 0644);
-#if defined(CONFIG_MT6620)
-#include <linux/gps.h>
-#endif
-
-#if defined(CONFIG_DP501) //for display port transmitter dp501
-#include<linux/dp501.h>
-#endif
-
-#include "board-rk30-sdk-camera.c"
-
-#include <plat/key.h>
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .gpio = RK30_PIN4_PC5,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK30_PIN6_PA2,
- .active_low = PRESS_LEV_LOW,
- //.code_long_press = EV_ENCALL,
- .wakeup = 1,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .adc_value = 1,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-#ifndef RK3000_SDK
- {
- .desc = "menu",
- .code = EV_MENU,
- .adc_value = 135,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .adc_value = 550,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .adc_value = 334,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "camera",
- .code = KEY_CAMERA,
- .adc_value = 743,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-#else
- {
- .desc = "menu",
- .code = EV_MENU,
- .adc_value = 155,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .adc_value = 630,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .adc_value = 386,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "camera",
- .code = KEY_CAMERA,
- .adc_value = 827,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-#endif
-};
-
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = 1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
-#if defined (CONFIG_RK_HEADSET_DET) || defined (CONFIG_RK_HEADSET_IRQ_HOOK_ADC_DET)
-
-static int rk_headset_io_init(int gpio)
-{
- int ret;
- ret = gpio_request(gpio, NULL);
- if(ret)
- return ret;
-
- rk30_mux_api_set(GPIO0C7_TRACECTL_SMCADDR3_NAME, GPIO0C_GPIO0C7);
- gpio_pull_updown(gpio, PullDisable);
- gpio_direction_input(gpio);
- mdelay(50);
- return 0;
-};
-
-struct rk_headset_pdata rk_headset_info = {
- .Headset_gpio = RK30_PIN0_PC7,
- .headset_in_type = HEADSET_IN_LOW,
- .Hook_adc_chn = 2,
- .hook_key_code = KEY_MEDIA,
- .headset_io_init = rk_headset_io_init,
-};
-
-struct platform_device rk_device_headset = {
- .name = "rk_headsetdet",
- .id = 0,
- .dev = {
- .platform_data = &rk_headset_info,
- }
-};
-#endif
-#if defined(CONFIG_TOUCHSCREEN_GT8XX)
-#define TOUCH_RESET_PIN RK30_PIN4_PD0
-#define TOUCH_PWR_PIN INVALID_GPIO
-int goodix_init_platform_hw(void)
-{
- int ret;
-
- rk30_mux_api_set(GPIO4D0_SMCDATA8_TRACEDATA8_NAME, GPIO4D_GPIO4D0);
- rk30_mux_api_set(GPIO4C2_SMCDATA2_TRACEDATA2_NAME, GPIO4C_GPIO4C2);
- printk("%s:0x%x,0x%x\n",__func__,rk30_mux_api_get(GPIO4D0_SMCDATA8_TRACEDATA8_NAME),rk30_mux_api_get(GPIO4C2_SMCDATA2_TRACEDATA2_NAME));
-
- if (TOUCH_PWR_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_PWR_PIN, "goodix power pin");
- if (ret != 0) {
- gpio_free(TOUCH_PWR_PIN);
- printk("goodix power error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_PWR_PIN, 0);
- gpio_set_value(TOUCH_PWR_PIN, GPIO_LOW);
- msleep(100);
- }
-
- if (TOUCH_RESET_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_RESET_PIN, "goodix reset pin");
- if (ret != 0) {
- gpio_free(TOUCH_RESET_PIN);
- printk("goodix gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, 1);
- msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_LOW);
- //msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_HIGH);
- //msleep(500);
- }
- return 0;
-}
-
-struct goodix_platform_data goodix_info = {
- .model = 8105,
- .irq_pin = RK30_PIN4_PC2,
- .rest_pin = TOUCH_RESET_PIN,
- .init_platform_hw = goodix_init_platform_hw,
-};
-#endif
-
-#if defined (CONFIG_TOUCHSCREEN_FT5506)
-#define TOUCH_RESET_PIN RK30_PIN4_PD0
-#define TOUCH_INT_PIN RK30_PIN4_PC2
-int ft5506_init_platform_hw(void)
-{
- printk("ft5506_init_platform_hw\n");
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("ft5506_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("ift5506_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- mdelay(10);
- gpio_direction_input(TOUCH_INT_PIN);
- mdelay(10);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- msleep(300);
- return 0;
-}
-
-void ft5506_exit_platform_hw(void)
-{
- printk("ft5506_exit_platform_hw\n");
- gpio_free(TOUCH_RESET_PIN);
- gpio_free(TOUCH_INT_PIN);
-}
-
-
-int ft5506_platform_sleep(void)
-{
- printk("ft5506_platform_sleep\n");
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- return 0;
-}
-int ft5506_platform_wakeup(void)
-{
- printk("ft5506_platform_wakeup\n");
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- msleep(300);
- return 0;
-}
-
-struct ft5506_platform_data ft5506_info = {
-
- .init_platform_hw= ft5506_init_platform_hw,
- .exit_platform_hw= ft5506_exit_platform_hw,
- .platform_sleep = ft5506_platform_sleep,
- .platform_wakeup = ft5506_platform_wakeup,
-
-};
-#endif
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-#define PWM_ID 2
-#define PWM_MUX_NAME GPIO0D6_PWM2_NAME
-#define PWM_MUX_MODE GPIO0D_PWM2
-#define PWM_MUX_MODE_GPIO GPIO0A_GPIO0A3
-#define PWM_GPIO RK30_PIN0_PD6
-#define PWM_EFFECT_VALUE 1
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-//#define BL_EN_MUX_NAME GPIOF34_UART3_SEL_NAME
-//#define BL_EN_MUX_MODE IOMUXB_GPIO1_B34
-
-#define BL_EN_PIN RK30_PIN6_PB3
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
- //rk30_mux_api_set(GPIO0D6_PWM2_NAME, GPIO0D_GPIO0D6);
- //gpio_request(RK30_PIN0_PD6, NULL);
- //gpio_direction_output(RK30_PIN0_PD6, GPIO_HIGH);
-
- msleep(50);
-
- rk30_mux_api_set(GPIO0D6_PWM2_NAME, GPIO0D_PWM2);
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
-#ifdef LCD_DISP_ON_PIN
- // rk30_mux_api_set(BL_EN_MUX_NAME, BL_EN_MUX_MODE);
-
- ret = gpio_request(BL_EN_PIN, NULL);
- if (ret != 0) {
- gpio_free(BL_EN_PIN);
- }
-
- gpio_direction_output(BL_EN_PIN, BL_EN_VALUE);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0;
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- if (gpio_request(PWM_GPIO, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- gpio_direction_output(PWM_GPIO, GPIO_LOW);
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, !BL_EN_VALUE);
- gpio_set_value(BL_EN_PIN, !BL_EN_VALUE);
- gpio_free(BL_EN_PIN);
-#endif
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret = 0;
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- if (gpio_request(PWM_GPIO, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- gpio_direction_output(PWM_GPIO, GPIO_LOW);
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, !BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- gpio_free(PWM_GPIO);
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
-#ifdef LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, 1);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
- .pre_div = 20000,
- .delay_ms = 50,
- .min_brightness = 150,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-#endif
-
-#if defined (CONFIG_SND_SOC_RT3224) || defined (CONFIG_SND_SOC_RT3261)
-
-#define DIFFERENTIAL 1
-#define SINGLE_END 0
-#define TWO_SPK 2
-#define ONE_SPK 1
-
-enum {
- SPK_AMPLIFY_ZERO_POINT_FIVE_WATT=1,
- SPK_AMPLIFY_ZERO_POINT_SIX_WATT,
- SPK_AMPLIFY_ZERO_POINT_EIGHT_WATT,
- SPK_AMPLIFY_ONE_WATT,
-};
-
-enum {
- LR_NORMAL,
- LR_SWAP,
- LEFT_COPY_TO_RIGHT,
- RIGHT_COPY_LEFT,
-};
-
-static int rt3261_io_init(int gpio, char *iomux_name, int iomux_mode)
-{
- gpio_request(gpio,NULL);
- rk30_mux_api_set(iomux_name, iomux_mode);
- gpio_direction_output(gpio,1);
-
-};
-
-static struct rt3261_platform_data rt3261_info = {
- .codec_en_gpio = RK30_PIN4_PD7,
- .codec_en_gpio_info = {GPIO4D7_SMCDATA15_TRACEDATA15_NAME,GPIO4D_GPIO4D7},
- .io_init = rt3261_io_init,
- .spk_num = TWO_SPK,
- .modem_input_mode = DIFFERENTIAL,
- .lout_to_modem_mode = DIFFERENTIAL,
- .spk_amplify = SPK_AMPLIFY_ZERO_POINT_SIX_WATT,
- .playback_if1_data_control = LR_NORMAL,
- .playback_if2_data_control = LR_NORMAL,
-};
-#endif
-
-#if defined(CONFIG_BP_AUTO)
-static int bp_io_init(void)
-{
- rk30_mux_api_set(GPIO2B6_LCDC1DATA14_SMCADDR18_TSSYNC_NAME, GPIO2B_GPIO2B6);
- rk30_mux_api_set(GPIO4D2_SMCDATA10_TRACEDATA10_NAME, GPIO4D_GPIO4D2);
- rk30_mux_api_set(GPIO4C6_SMCDATA6_TRACEDATA6_NAME, GPIO4C_GPIO4C6);
- rk30_mux_api_set(GPIO4C4_SMCDATA4_TRACEDATA4_NAME, GPIO4C_GPIO4C4);
- //rk30_mux_api_set(GPIO2B7_LCDC1DATA15_SMCADDR19_HSADCDATA7_NAME, GPIO2B_GPIO2B7);
- //rk30_mux_api_set(GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME, GPIO2C_GPIO2C0);
- return 0;
-}
-
-static int bp_io_deinit(void)
-{
-
- return 0;
-}
-static int bp_id_get(void)
-{
- return ap_mdm; //internally 3G modem ID, defined in include\linux\Bp-auto.h
-}
-
-struct bp_platform_data bp_auto_info = {
- .init_platform_hw = bp_io_init,
- .exit_platform_hw = bp_io_deinit,
- .get_bp_id = bp_id_get,
- .bp_power = RK30_PIN6_PB2, // 3g_power
- .bp_en = RK30_PIN2_PB6, // 3g_en
- .bp_reset = RK30_PIN4_PD2,
- .bp_usb_en = BP_UNKNOW_DATA, //W_disable
- .bp_uart_en = BP_UNKNOW_DATA, //EINT9
- .bp_wakeup_ap = RK30_PIN4_PC6, //
- .ap_wakeup_bp = RK30_PIN4_PC4,
- .ap_ready = BP_UNKNOW_DATA, //
- .bp_ready = BP_UNKNOW_DATA,
- .gpio_valid = 1, //if 1:gpio is define in bp_auto_info,if 0:is not use gpio in bp_auto_info
-};
-
-struct platform_device device_bp_auto = {
- .name = "bp-auto",
- .id = -1,
- .dev = {
- .platform_data = &bp_auto_info,
- }
- };
-#endif
-#ifdef CONFIG_RK29_SUPPORT_MODEM
-
-#define RK30_MODEM_POWER RK30_PIN4_PD1
-#define RK30_MODEM_POWER_IOMUX rk29_mux_api_set(GPIO4D1_SMCDATA9_TRACEDATA9_NAME, GPIO4D_GPIO4D1)
-
-static int rk30_modem_io_init(void)
-{
- printk("%s\n", __FUNCTION__);
- RK30_MODEM_POWER_IOMUX;
-
- return 0;
-}
-
-static struct rk29_io_t rk30_modem_io = {
- .io_addr = RK30_MODEM_POWER,
- .enable = GPIO_HIGH,
- .disable = GPIO_LOW,
- .io_init = rk30_modem_io_init,
-};
-
-static struct platform_device rk30_device_modem = {
- .name = "rk30_modem",
- .id = -1,
- .dev = {
- .platform_data = &rk30_modem_io,
- }
-};
-#endif
-
-
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN RK30_PIN4_PC0
-
-static int mma8452_init_platform_hw(void)
-{
- rk30_mux_api_set(GPIO4C0_SMCDATA0_TRACEDATA0_NAME, GPIO4C_GPIO4C0);
-
- return 0;
-}
-
-static struct sensor_platform_data mma8452_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma8452_init_platform_hw,
- .orientation = {0, 1, 0, 0, 0, -1, 1, 0, 0},
-};
-#endif
-#if defined (CONFIG_GS_LIS3DH)
-#define LIS3DH_INT_PIN RK30_PIN4_PC0
-
-static int lis3dh_init_platform_hw(void)
-{
- rk30_mux_api_set(GPIO4C0_SMCDATA0_TRACEDATA0_NAME, GPIO4C_GPIO4C0);
-
- return 0;
-}
-
-static struct sensor_platform_data lis3dh_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lis3dh_init_platform_hw,
- .orientation = {-1, 0, 0, 0, 0, 1, 0, -1, 0},
-};
-#endif
-#if defined (CONFIG_GS_KXTIK)
-#define KXTIK_INT_PIN RK30_PIN4_PC0
-
-static int kxtik_init_platform_hw(void)
-{
- rk30_mux_api_set(GPIO4C0_SMCDATA0_TRACEDATA0_NAME, GPIO4C_GPIO4C0);
-
- return 0;
-}
-
-static struct sensor_platform_data kxtik_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = kxtik_init_platform_hw,
- .orientation = {0, 1, 0, 0, 0, -1, 1, 0, 0},
-};
-
-#endif
-#if defined(CONFIG_CHARGER_SMB347)
-struct smb347_info smb347_info = {
- .chg_en_pin = RK30_PIN4_PD5, // charge enable pin (smb347's c4 pin)
- .chg_ctl_pin = RK30_PIN0_PC6, // charge control pin (smb347's d2 pin)
- .chg_stat_pin = RK30_PIN6_PA6, // charge stat pin (smb347's f5 pin)
- .chg_susp_pin = RK30_PIN4_PD1, // charge usb suspend pin (smb347's d3 pin)
- .max_current = 1800, // dc and hc input current limit can set 300/500/700/900/1200/1500/1800/2000/2200/2500(ma)
- .otg_power_form_smb = 0, // if otg 5v power form smb347 set 1 otherwise set 0
-};
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
-static struct sensor_platform_data akm8975_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-#if defined(CONFIG_GYRO_L3G4200D)
-
-#include <linux/l3g4200d.h>
-#define L3G4200D_INT_PIN RK30_PIN4_PC3
-
-static int l3g4200d_init_platform_hw(void)
-{
- rk30_mux_api_set(GPIO4C3_SMCDATA3_TRACEDATA3_NAME, GPIO4C_GPIO4C3);
-
- return 0;
-}
-
-static struct sensor_platform_data l3g4200d_info = {
- .type = SENSOR_TYPE_GYROSCOPE,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
- .init_platform_hw = l3g4200d_init_platform_hw,
- .x_min = 40,//x_min,y_min,z_min = (0-100) according to hardware
- .y_min = 40,
- .z_min = 20,
-};
-
-#endif
-
-#ifdef CONFIG_LS_CM3217
-static struct sensor_platform_data cm3217_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 0,
- .poll_delay_ms = 500,
-};
-
-#endif
-
-#ifdef CONFIG_LS_CM3231
-static struct sensor_platform_data cm3231_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 0,
- .poll_delay_ms = 500,
-};
-#endif
-
-#if defined(CONFIG_PS_AL3006)
-static struct sensor_platform_data proximity_al3006_info = {
- .type = SENSOR_TYPE_PROXIMITY,
- .irq_enable = 1,
- .poll_delay_ms = 200,
-};
-#endif
-
-#if defined(CONFIG_PS_STK3171)
-static struct sensor_platform_data proximity_stk3171_info = {
- .type = SENSOR_TYPE_PROXIMITY,
- .irq_enable = 1,
- .poll_delay_ms = 200,
-};
-#endif
-
-
-#if defined(CONFIG_LS_AL3006)
-static struct sensor_platform_data light_al3006_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 1,
- .poll_delay_ms = 200,
-};
-#endif
-
-#if defined(CONFIG_LS_STK3171)
-static struct sensor_platform_data light_stk3171_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 1,
- .poll_delay_ms = 200,
-};
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
-
-#define LCD_CS_MUX_NAME GPIO4C7_SMCDATA7_TRACEDATA7_NAME
-#define LCD_CS_PIN RK30_PIN4_PC7
-#define LCD_CS_VALUE GPIO_HIGH
-
-#define LCD_STANDBY_MUX_NAME GPIO4D6_SMCDATA14_TRACEDATA14_NAME
-#define LCD_STANDBY_PIN RK30_PIN4_PD6
-#define LCD_STANDBY_VALUE GPIO_HIGH
-
-
-#define LCD_EN_MUX_NAME GPIO4C7_SMCDATA7_TRACEDATA7_NAME
-#define LCD_EN_PIN RK30_PIN6_PB4
-#define LCD_EN_VALUE GPIO_LOW
-
-#define HDMI11_MUX_NAME GPIO3A6_SDMMC0RSTNOUT_NAME
-#define HDMI11_EN_PIN RK30_PIN3_PA6
-#define HDMI11_EN_VALUE GPIO_HIGH
-
-
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
-
- rk30_mux_api_set(LCD_STANDBY_MUX_NAME, GPIO4D_GPIO4D6);
- ret = gpio_request(LCD_STANDBY_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_STANDBY_PIN);
- printk(KERN_ERR "request lcd cs pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_STANDBY_PIN, LCD_STANDBY_VALUE);
- }
-
- rk30_mux_api_set(GPIO3A6_SDMMC0RSTNOUT_NAME, GPIO3A_GPIO3A6);
- ret = gpio_request(HDMI11_EN_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(HDMI11_EN_PIN);
- printk(KERN_ERR "hdmi gpio fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(HDMI11_EN_PIN, HDMI11_EN_VALUE);
- }
-
- rk30_mux_api_set(LCD_CS_MUX_NAME, GPIO4C_GPIO4C7);
- ret = gpio_request(LCD_CS_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_CS_PIN);
- printk(KERN_ERR "request lcd cs pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_CS_PIN, LCD_CS_VALUE);
- }
- ret = gpio_request(LCD_EN_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_EN_PIN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_EN_PIN, LCD_EN_VALUE);
- }
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
- msleep(100); //Response Time (Rising + Falling)
- gpio_set_value(HDMI11_EN_PIN, HDMI11_EN_VALUE? 0:1);
- gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE? 0:1);
- gpio_set_value(LCD_STANDBY_PIN, LCD_CS_VALUE? 0:1);
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE? 0:1);
-
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
- gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE);
- gpio_set_value(LCD_STANDBY_PIN, LCD_CS_VALUE);
- gpio_set_value(HDMI11_EN_PIN, HDMI11_EN_VALUE);
- msleep(150); //wait for power stable
-
- return 0;
-}
-
-#if defined(CONFIG_LCDC0_RK30)
-struct rk29fb_info lcdc0_screen_info = {
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK30)
-struct rk29fb_info lcdc1_screen_info = {
- #if defined(CONFIG_RK_HDMI)
- .prop = EXTEND, //extend display device
- .lcd_info = NULL,
- .set_screen_info = hdmi_init_lcdc,
- #endif
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-
-#if defined(CONFIG_LCDC0_RK30)
-static struct resource resource_lcdc0[] = {
- [0] = {
- .name = "lcdc0 reg",
- .start = RK30_LCDC0_PHYS,
- .end = RK30_LCDC0_PHYS + RK30_LCDC0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc0 irq",
- .start = IRQ_LCDC0,
- .end = IRQ_LCDC0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc0 = {
- .name = "rk30-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc0),
- .resource = resource_lcdc0,
- .dev = {
- .platform_data = &lcdc0_screen_info,
- },
-};
-#endif
-#if defined(CONFIG_LCDC1_RK30)
-extern struct rk29fb_info lcdc1_screen_info;
-static struct resource resource_lcdc1[] = {
- [0] = {
- .name = "lcdc1 reg",
- .start = RK30_LCDC1_PHYS,
- .end = RK30_LCDC1_PHYS + RK30_LCDC1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc1 irq",
- .start = IRQ_LCDC1,
- .end = IRQ_LCDC1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc1 = {
- .name = "rk30-lcdc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resource_lcdc1),
- .resource = resource_lcdc1,
- .dev = {
- .platform_data = &lcdc1_screen_info,
- },
-};
-#endif
-
-#if defined(CONFIG_DP501)
- #define DVDD33_EN_PIN RK30_PIN6_PB4
- #define DVDD33_EN_VALUE GPIO_LOW
-
- #define DVDD12_EN_PIN RK30_PIN4_PC7
- #define DVDD12_EN_VALUE GPIO_HIGH
-
- #define EDP_RST_PIN RK30_PIN2_PC4
- static int rk_edp_power_ctl(void)
- {
- int ret;
- ret = gpio_request(DVDD33_EN_PIN, "dvdd33_en_pin");
- if (ret != 0)
- {
- gpio_free(DVDD33_EN_PIN);
- printk(KERN_ERR "request dvdd33 en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(DVDD33_EN_PIN, DVDD33_EN_VALUE);
- }
-
- ret = gpio_request(DVDD12_EN_PIN, "dvdd18_en_pin");
- if (ret != 0)
- {
- gpio_free(DVDD12_EN_PIN);
- printk(KERN_ERR "request dvdd18 en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(DVDD12_EN_PIN, DVDD12_EN_VALUE);
- }
-
- ret = gpio_request(EDP_RST_PIN, "edp_rst_pin");
- if (ret != 0)
- {
- gpio_free(EDP_RST_PIN);
- printk(KERN_ERR "request rst pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(EDP_RST_PIN, GPIO_LOW);
- msleep(10);
- gpio_direction_output(EDP_RST_PIN, GPIO_HIGH);
- }
- return 0;
-
- }
- static struct dp501_platform_data dp501_platform_data = {
- .power_ctl = rk_edp_power_ctl,
- .dvdd33_en_pin = DVDD33_EN_PIN,
- .dvdd33_en_val = DVDD33_EN_VALUE,
- .dvdd18_en_pin = DVDD12_EN_PIN,
- .dvdd18_en_val = DVDD12_EN_VALUE,
- .edp_rst_pin = EDP_RST_PIN,
- };
-#endif
-
-#if defined(CONFIG_MFD_RK610)
-#define RK610_RST_PIN_MUX_NAME GPIO0C6_TRACECLK_SMCADDR2_NAME
-#define RK610_RST_PIN_MUX_MODE GPIO0C_GPIO0C6
-#define RK610_RST_PIN RK30_PIN0_PC6
-static int rk610_power_on_init(void)
-{
- int ret;
- if(RK610_RST_PIN != INVALID_GPIO)
- {
- rk30_mux_api_set(RK610_RST_PIN_MUX_NAME,RK610_RST_PIN_MUX_MODE);
- ret = gpio_request(RK610_RST_PIN, "rk610 reset");
- if (ret)
- {
- printk(KERN_ERR "rk610_control_probe request gpio fail\n");
- }
- else
- {
- gpio_direction_output(RK610_RST_PIN, GPIO_HIGH);
- msleep(100);
- gpio_direction_output(RK610_RST_PIN, GPIO_LOW);
- msleep(100);
- gpio_set_value(RK610_RST_PIN, GPIO_HIGH);
- }
- }
-
- return 0;
-
-}
-
-
-static struct rk610_ctl_platform_data rk610_ctl_pdata = {
- .rk610_power_on_init = rk610_power_on_init,
-};
-#endif
-#ifdef CONFIG_SND_SOC_RK610
-static int rk610_codec_io_init(void)
-{
-//if need iomux.
-//Must not gpio_request
- return 0;
-}
-
-static struct rk610_codec_platform_data rk610_codec_pdata = {
- .spk_ctl_io = RK30_PIN4_PC6,
- .io_init = rk610_codec_io_init,
-};
-#endif
-#ifdef CONFIG_ANDROID_TIMED_GPIO
-static struct timed_gpio timed_gpios[] = {
- {
- .name = "vibrator",
- .gpio = RK30_PIN0_PA4,
- .max_timeout = 1000,
- .active_low = 0,
- .adjust_time =20, //adjust for diff product
- },
-};
-
-static struct timed_gpio_platform_data rk29_vibrator_info = {
- .num_gpios = 1,
- .gpios = timed_gpios,
-};
-
-static struct platform_device rk29_device_vibrator = {
- .name = "timed-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_vibrator_info,
- },
-
-};
-#endif
-
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
-static struct gpio_led rk29_leds[] = {
- {
- .name = "button-backlight",
- .gpio = RK30_PIN4_PD7,
- .default_trigger = "timer",
- .active_low = 0,
- .retain_state_suspended = 0,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- },
-};
-
-static struct gpio_led_platform_data rk29_leds_pdata = {
- .leds = rk29_leds,
- .num_leds = ARRAY_SIZE(rk29_leds),
-};
-
-static struct platform_device rk29_device_gpio_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_leds_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_RK_IRDA
-#define IRDA_IRQ_PIN RK30_PIN6_PA1
-
-static int irda_iomux_init(void)
-{
- int ret = 0;
-
- //irda irq pin
- ret = gpio_request(IRDA_IRQ_PIN, NULL);
- if (ret != 0) {
- gpio_free(IRDA_IRQ_PIN);
- printk(">>>>>> IRDA_IRQ_PIN gpio_request err \n ");
- }
- gpio_pull_updown(IRDA_IRQ_PIN, PullDisable);
- gpio_direction_input(IRDA_IRQ_PIN);
-
- return 0;
-}
-
-static int irda_iomux_deinit(void)
-{
- gpio_free(IRDA_IRQ_PIN);
- return 0;
-}
-
-static struct irda_info rk29_irda_info = {
- .intr_pin = IRDA_IRQ_PIN,
- .iomux_init = irda_iomux_init,
- .iomux_deinit = irda_iomux_deinit,
- //.irda_pwr_ctl = bu92747guw_power_ctl,
-};
-
-static struct platform_device irda_device = {
-#ifdef CONFIG_RK_IRDA_NET
- .name = "rk_irda",
-#else
- .name = "bu92747_irda",
-#endif
- .id = -1,
- .dev = {
- .platform_data = &rk29_irda_info,
- }
-};
-#endif
-
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and SDIO.noted by xbw at 2012-03-05
-**************************************************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "board-rk30-sdk-sdmmc.c"
-#endif
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- rk30_mux_api_set(GPIO3B1_SDMMC0CMD_NAME, GPIO3B_SDMMC0_CMD);
- rk30_mux_api_set(GPIO3B0_SDMMC0CLKOUT_NAME, GPIO3B_SDMMC0_CLKOUT);
- rk30_mux_api_set(GPIO3B2_SDMMC0DATA0_NAME, GPIO3B_SDMMC0_DATA0);
- rk30_mux_api_set(GPIO3B3_SDMMC0DATA1_NAME, GPIO3B_SDMMC0_DATA1);
- rk30_mux_api_set(GPIO3B4_SDMMC0DATA2_NAME, GPIO3B_SDMMC0_DATA2);
- rk30_mux_api_set(GPIO3B5_SDMMC0DATA3_NAME, GPIO3B_SDMMC0_DATA3);
-
- rk30_mux_api_set(GPIO3B6_SDMMC0DETECTN_NAME, GPIO3B_GPIO3B6);
-
- rk30_mux_api_set(GPIO3A7_SDMMC0PWREN_NAME, GPIO3A_GPIO3A7);
- gpio_request(RK30_PIN3_PA7, "sdmmc-power");
- gpio_direction_output(RK30_PIN3_PA7, GPIO_LOW);
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- #if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO);
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FMUX);
- #endif
-
- #if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
- #endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) && defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- .status = rk29sdk_wifi_mmc0_status,
- .register_status_notify = rk29sdk_wifi_mmc0_status_register,
-#endif
-
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .power_en = RK29SDK_SD_CARD_PWR_EN,
- .power_en_level = RK29SDK_SD_CARD_PWR_EN_LEVEL,
-#else
- .power_en = INVALID_GPIO,
- .power_en_level = GPIO_LOW,
-#endif
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC0_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- .det_pin_info = {
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N, //INVALID_GPIO,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
- #endif
- },
-
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- rk30_mux_api_set(GPIO3C0_SMMC1CMD_NAME, GPIO3C_SMMC1_CMD);
- rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_NAME, GPIO3C_SDMMC1_CLKOUT);
- rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_NAME, GPIO3C_SDMMC1_DATA0);
- rk30_mux_api_set(GPIO3C2_SDMMC1DATA1_NAME, GPIO3C_SDMMC1_DATA1);
- rk30_mux_api_set(GPIO3C3_SDMMC1DATA2_NAME, GPIO3C_SDMMC1_DATA2);
- rk30_mux_api_set(GPIO3C4_SDMMC1DATA3_NAME, GPIO3C_SDMMC1_DATA3);
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC) || defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-
- #if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC1_WRITE_PROTECT_ENABLE_VALUE;
- #else
- .write_prt = INVALID_GPIO,
- #endif
-
- #if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
- .sdio_INT_gpio = RK29SDK_WIFI_SDIO_CARD_INT,
- #endif
-
- .det_pin_info = {
-#if defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- #else
- .io = INVALID_GPIO,
- #endif
-
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-
- .enable_sd_wakeup = 0,
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-/**************************************************************************************************
- * the end of setting for SDMMC devices
-**************************************************************************************************/
-
-
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = RK30_PIN6_PA5,//INVALID_GPIO,
- .batt_low_pin = RK30_PIN6_PA0,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = INVALID_GPIO,
- .dc_det_level = GPIO_LOW,
- .charge_ok_level = GPIO_HIGH,
- .usb_det_pin = RK30_PIN6_PA3,
- .usb_det_level = GPIO_LOW,
-
- .charging_sleep = 0 ,
- .save_capacity = 1 ,
- .adc_channel =0 ,
- .spport_usb_charging = 1,
-};
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-
-#if defined(CONFIG_BATTERY_RK30_ADC)
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = RK30_PIN6_PA5,
- .batt_low_pin = RK30_PIN6_PA0,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = RK30_PIN6_PA6,
- .dc_det_level = GPIO_LOW,
- .charge_ok_level = GPIO_HIGH,
-};
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-
-#ifdef CONFIG_RK30_PWM_REGULATOR
-const static int pwm_voltage_map[] = {
- 950000,975000,1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000, 1375000, 1400000
-};
-
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_core",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] =
-{
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
- .pwm_id = 3,
- .pwm_gpio = RK30_PIN0_PD7,
- .pwm_iomux_name = GPIO0D7_PWM3_NAME,
- .pwm_iomux_pwm = GPIO0D_PWM3,
- .pwm_iomux_gpio = GPIO0D_GPIO0D6,
- .pwm_voltage = 1100000,
- .suspend_voltage = 1050000,
- .min_uV = 950000,
- .max_uV = 1400000,
- .coefficient = 455, //45.5%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-#endif
-
-#ifdef CONFIG_RK29_VMAC
-#define PHY_PWR_EN_GPIO RK30_PIN1_PD6
-#include "board-rk30-sdk-vmac.c"
-#endif
-
-#ifdef CONFIG_RFKILL_RK
-// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
-static struct rfkill_rk_platform_data rfkill_rk_platdata = {
- .type = RFKILL_TYPE_BLUETOOTH,
-
- .poweron_gpio = { // BT_REG_ON
- .io = RK30_PIN3_PC7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C7_SDMMC1WRITEPRT_NAME,
- .fgpio = GPIO3C_GPIO3C7,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN3_PD1, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = GPIO3D1_SDMMC1BACKENDPWR_NAME,
- .fgpio = GPIO3D_GPIO3D1,
- },
- },
-
- .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
- .io = RK30_PIN3_PC6, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C6_SDMMC1DETECTN_NAME,
- .fgpio = GPIO3C_GPIO3C6,
- },
- },
-
- .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .gpio = {
- .io = RK30_PIN6_PA7, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
- .iomux = {
- .name = NULL,
- },
- },
- },
-
- .rts_gpio = { // UART_RTS, enable or disable BT's data coming
- .io = RK30_PIN1_PA3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = GPIO1A3_UART0RTSN_NAME,
- .fgpio = GPIO1A_GPIO1A3,
- .fmux = GPIO1A_UART0_RTS_N,
- },
- },
-};
-
-static struct platform_device device_rfkill_rk = {
- .name = "rfkill_rk",
- .id = -1,
- .dev = {
- .platform_data = &rfkill_rk_platdata,
- },
-};
-#endif
-
-#if defined(CONFIG_MT5931_MT6622)
-static struct mt6622_platform_data mt6622_platdata = {
- .power_gpio = { // BT_REG_ON
- .io = RK30_PIN3_PC7, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN3_PD1,
- .enable = GPIO_LOW,
- .iomux = {
- .name = NULL,
- },
- },
-
- .irq_gpio = {
- .io = RK30_PIN6_PA7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- }
-};
-
-static struct platform_device device_mt6622 = {
- .name = "mt6622",
- .id = -1,
- .dev = {
- .platform_data = &mt6622_platdata,
- },
-};
-#endif
-
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_ANDROID_TIMED_GPIO
- &rk29_device_vibrator,
-#endif
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
- &rk29_device_gpio_leds,
-#endif
-#ifdef CONFIG_RK_IRDA
- &irda_device,
-#endif
-#if defined(CONFIG_WIFI_CONTROL_FUNC)||defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- &rk29sdk_wifi_device,
-#endif
-
-#if defined(CONFIG_MT6620)
- &mt3326_device_gps,
-#endif
-
-#ifdef CONFIG_RK29_SUPPORT_MODEM
- &rk30_device_modem,
-#endif
-#if defined (CONFIG_RK_HEADSET_DET) || defined (CONFIG_RK_HEADSET_IRQ_HOOK_ADC_DET)
- &rk_device_headset,
-#endif
-
-#if defined(CONFIG_BATTERY_RK30_ADC)||defined(CONFIG_BATTERY_RK30_ADC_FAC)
- &rk30_device_adc_battery,
-#endif
-#ifdef CONFIG_RFKILL_RK
- &device_rfkill_rk,
-#endif
-#ifdef CONFIG_MT5931_MT6622
- &device_mt6622,
-#endif
-#if defined(CONFIG_BP_AUTO)
- &device_bp_auto,
-#endif
-};
-
-
-static int rk_platform_add_display_devices(void)
-{
- struct platform_device *fb = NULL; //fb
- struct platform_device *lcdc0 = NULL; //lcdc0
- struct platform_device *lcdc1 = NULL; //lcdc1
- struct platform_device *bl = NULL; //backlight
-#ifdef CONFIG_FB_ROCKCHIP
- fb = &device_fb;
-#endif
-
-#if defined(CONFIG_LCDC0_RK30)
- lcdc0 = &device_lcdc0,
-#endif
-
-#if defined(CONFIG_LCDC1_RK30)
- lcdc1 = &device_lcdc1,
-#endif
-
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- bl = &rk29_device_backlight,
-#endif
- __rk_platform_add_display_devices(fb,lcdc0,lcdc1,bl);
-
- return 0;
-
-}
-// i2c
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1d,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_GS_LIS3DH)
- {
- .type = "gs_lis3dh",
- .addr = 0x19, //0x19(SA0-->VCC), 0x18(SA0-->GND)
- .flags = 0,
- .irq = LIS3DH_INT_PIN,
- .platform_data = &lis3dh_info,
- },
-#endif
-#if defined (CONFIG_GS_KXTIK)
- {
- .type = "gs_kxtik",
- .addr = 0x0F,
- .flags = 0,
- .irq = KXTIK_INT_PIN,
- .platform_data = &kxtik_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN4_PC1,
- .platform_data = &akm8975_info,
- },
-#endif
-#if defined (CONFIG_GYRO_L3G4200D)
- {
- .type = "l3g4200d_gryo",
- .addr = 0x69,
- .flags = 0,
- .irq = L3G4200D_INT_PIN,
- .platform_data = &l3g4200d_info,
- },
-#endif
-#if defined (CONFIG_LS_AL3006)
- {
- .type = "light_al3006",
- .addr = 0x1c, //sel = 0; if sel =1, then addr = 0x1D
- .flags = 0,
- .irq = RK30_PIN6_PA2,
- .platform_data = &light_al3006_info,
- },
-#endif
-#if defined (CONFIG_LS_STK3171)
- {
- .type = "ls_stk3171",
- .addr = 0x48,
- .flags = 0,
- .irq = RK30_PIN6_PA2,
- .platform_data = &light_stk3171_info,
- },
-#endif
-
-
-#if defined (CONFIG_PS_AL3006)
- {
- .type = "proximity_al3006",
- .addr = 0x1c, //sel = 0; if sel =1, then addr = 0x1D
- .flags = 0,
- .irq = RK30_PIN6_PA2,
- .platform_data = &proximity_al3006_info,
- },
-#endif
-
-#if defined (CONFIG_PS_STK3171)
- {
- .type = "ps_stk3171",
- .addr = 0x48,
- .flags = 0,
- .irq = RK30_PIN6_PA2,
- .platform_data = &proximity_stk3171_info,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RT5631)
- {
- .type = "rt5631",
- .addr = 0x1a,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RT3224) || defined (CONFIG_SND_SOC_RT3261)
- {
- .type = "rt3261",
- .addr = 0x1c,
- .flags = 0,
- .platform_data = &rt3261_info,
- },
-#endif
-
-#ifdef CONFIG_MFD_RK610
- {
- .type = "rk610_ctl",
- .addr = 0x40,
- .flags = 0,
- .platform_data = &rk610_ctl_pdata,
- },
-#ifdef CONFIG_RK610_TVOUT
- {
- .type = "rk610_tvout",
- .addr = 0x42,
- .flags = 0,
- },
-#endif
-#ifdef CONFIG_HDMI_RK610
- {
- .type = "rk610_hdmi",
- .addr = 0x46,
- .flags = 0,
- .irq = INVALID_GPIO,
- },
-#endif
-#ifdef CONFIG_SND_SOC_RK610
- {//RK610_CODEC addr from 0x60 to 0x80 (0x60~0x80)
- .type = "rk610_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- .platform_data = &rk610_codec_pdata,
- },
-#endif
-#endif
-
-};
-#endif
-int __sramdata g_pmic_type = 0;
-#ifdef CONFIG_I2C1_RK30
-#ifdef CONFIG_MFD_WM831X_I2C
-#include "board-rk30-sdk-wm8326.c"
-#endif
-#ifdef CONFIG_MFD_TPS65910
-#define TPS65910_HOST_IRQ RK30_PIN6_PA4
-#include "board-rk30-sdk-tps65910.c"
-#endif
-
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_MFD_WM831X_I2C)
- {
- .type = "wm8326",
- .addr = 0x34,
- .flags = 0,
- .irq = RK30_PIN6_PA4,
- .platform_data = &wm831x_platdata,
- },
-#endif
-#if defined (CONFIG_CHARGER_SMB347)
- {
- .type = "smb347",
- .addr = 0x06,
- .flags = 0,
- .platform_data = &smb347_info,
- },
-#endif
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-};
-#endif
-
-void __sramfunc board_pmu_suspend(void)
-{
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_suspend();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_suspend();
- #endif
-}
-
-void __sramfunc board_pmu_resume(void)
-{
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_resume();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_resume();
- #endif
-}
-
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-#if defined (CONFIG_TOUCHSCREEN_GT8XX)
- {
- .type = "Goodix-TS",
- .addr = 0x55,
- .flags = 0,
- .irq = RK30_PIN4_PC2,
- .platform_data = &goodix_info,
- },
-#endif
-#if defined (CONFIG_LS_CM3217)
- {
- .type = "light_cm3217",
- .addr = 0x10,
- .flags = 0,
- .platform_data = &cm3217_info,
- },
-#endif
-#if defined (CONFIG_LS_CM3231)
- {
- .type = "cm3217",
- .addr = 0x10,
- .flags = 0,
- .platform_data = &cm3231_info,
- },
-#endif
-
-#if defined(CONFIG_DP501)
- {
- .type = "dp501",
- .addr = 0x30,
- .flags = 0,
- .platform_data = &dp501_platform_data,
- },
-#endif
-#if defined (CONFIG_TOUCHSCREEN_FT5506)
-{
- .type = "laibao_touch",
- .addr = 0x38,
- .flags = 0,
- .irq = RK30_PIN4_PC2,
- .platform_data = &ft5506_info,
-},
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C4_RK30
-static struct i2c_board_info __initdata i2c4_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO// RK30_PIN2_PD6 //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO//RK30_PIN2_PD7 //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- //set iomux (gpio) here
- //rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME, GPIO2D_GPIO2D7);
- //rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME, GPIO2D_GPIO2D6);
-
- return 0;
-}
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C4_RK30
- i2c_register_board_info(4, i2c4_info, ARRAY_SIZE(i2c4_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(5, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-
-#define POWER_ON_PIN RK30_PIN6_PB0 //power_hold
-static void rk30_pm_power_off(void)
-{
- printk(KERN_ERR "rk30_pm_power_off start...\n");
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
- #if defined(CONFIG_MFD_WM831X)
- if(pmic_is_wm8326())
- {
- wm831x_set_bits(Wm831x,WM831X_GPIO_LEVEL,0x0001,0x0000); //set sys_pwr 0
- wm831x_device_shutdown(Wm831x);//wm8326 shutdown
- }
- #endif
- #if defined(CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- {
- tps65910_device_shutdown();//tps65910 shutdown
- }
- #endif
-
- while (1);
-}
-
-static void __init machine_rk30_board_init(void)
-{
- avs_init();
- gpio_request(POWER_ON_PIN, "poweronpin");
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
- pm_power_off = rk30_pm_power_off;
-
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- rk_platform_add_display_devices();
- board_usb_detect_init(RK30_PIN6_PA3);
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC)
- rk29sdk_wifi_bt_gpio_control_init();
-#elif defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- rk29sdk_wifi_combo_module_gpio_init();
-#endif
-
-#if defined(CONFIG_MT6620)
- clk_set_rate(clk_get_sys("rk_serial.0", "uart"), 48*1000000);
-#endif
-#if defined (CONFIG_SND_SOC_RT3224) || defined (CONFIG_SND_SOC_RT3261)
- //add for codec_en
- gpio_request(RK30_PIN4_PD7, "codec_en");
- rk30_mux_api_set(GPIO4D7_SMCDATA15_TRACEDATA15_NAME, GPIO4D_GPIO4D7);
- gpio_direction_output(RK30_PIN4_PD7, GPIO_HIGH);
-#endif
-}
-
-static void __init rk30_reserve(void)
-{
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0 buf", get_fb_size());
- resource_fb[0].end = resource_fb[0].start + get_fb_size()- 1;
-#if 0
- resource_fb[1].start = board_mem_reserve_add("ipp buf", RK30_FB0_MEM_SIZE);
- resource_fb[1].end = resource_fb[1].start + RK30_FB0_MEM_SIZE - 1;
-#endif
-
-#if defined(CONFIG_FB_ROTATE) || !defined(CONFIG_THREE_FB_BUFFER)
- resource_fb[2].start = board_mem_reserve_add("fb2 buf",get_fb_size());
- resource_fb[2].end = resource_fb[2].start + get_fb_size() - 1;
-#endif
-#endif
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
- board_mem_reserved();
-}
-
-/**
- * dvfs_cpu_logic_table: table for arm and logic dvfs
- * @frequency : arm frequency
- * @cpu_volt : arm voltage depend on frequency
- * @logic_volt : logic voltage arm requests depend on frequency
- * comments : min arm/logic voltage
- */
-static struct dvfs_arm_table dvfs_cpu_logic_table[] = {
- {.frequency = 252 * 1000, .cpu_volt = 1075 * 1000, .logic_volt = 1125 * 1000},//0.975V/1.000V
- {.frequency = 504 * 1000, .cpu_volt = 1100 * 1000, .logic_volt = 1125 * 1000},//0.975V/1.000V
- {.frequency = 816 * 1000, .cpu_volt = 1125 * 1000, .logic_volt = 1150 * 1000},//1.000V/1.025V
- {.frequency = 1008 * 1000, .cpu_volt = 1125 * 1000, .logic_volt = 1150 * 1000},//1.025V/1.050V
- {.frequency = 1200 * 1000, .cpu_volt = 1175 * 1000, .logic_volt = 1200 * 1000},//1.100V/1.050V
- {.frequency = 1272 * 1000, .cpu_volt = 1225 * 1000, .logic_volt = 1200 * 1000},//1.150V/1.100V
- {.frequency = 1416 * 1000, .cpu_volt = 1300 * 1000, .logic_volt = 1200 * 1000},//1.225V/1.100V
- {.frequency = 1512 * 1000, .cpu_volt = 1350 * 1000, .logic_volt = 1250 * 1000},//1.300V/1.150V
- {.frequency = 1608 * 1000, .cpu_volt = 1425 * 1000, .logic_volt = 1300 * 1000},//1.325V/1.175V
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- {.frequency = 266 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1275 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 1050 * 1000},
- {.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = 1050 * 1000},
- {.frequency = 400 * 1000 + DDR_FREQ_NORMAL, .index = 1125 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
-static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
-static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
-
-void __init board_clock_init(void)
-{
- rk30_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
- dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
-}
-
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk30_fixup,
- .reserve = &rk30_reserve,
- .map_io = rk30_map_io,
- .init_irq = rk30_init_irq,
- .timer = &rk30_timer,
- .init_machine = machine_rk30_board_init,
-MACHINE_END
+++ /dev/null
-/* arch/arm/mach-rk30/board-rk30-sdk.c
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <mach/dvfs.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <linux/fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/mfd/tps65910.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-#include <plat/rk_fiq_debugger.h>
-#include "../../../drivers/headset_observe/rk_headset.h"
-
-#if defined(CONFIG_HDMI_RK30)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#ifdef CONFIG_TOUCHSCREEN_GT82X_IIC
-#include <linux/goodix_touch_82x.h>
-#endif
-#ifdef CONFIG_TOUCHSCREEN_SYNAPTICS_S3202
-#include <linux/interrupt.h>
-#include <linux/rmi.h>
-#endif
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-#if defined(CONFIG_MU509)
-#include <linux/mu509.h>
-#endif
-#if defined(CONFIG_MW100)
-#include <linux/mw100.h>
-#endif
-#if defined(CONFIG_MT6229)
-#include <linux/mt6229.h>
-#endif
-#if defined(CONFIG_SEW868)
-#include <linux/sew868.h>
-#endif
-
-#if defined(CONFIG_MI700)
-#include <linux/mi700.h>
-#endif
-
-#if defined(CONFIG_ANDROID_TIMED_GPIO)
-#include "../../../drivers/staging/android/timed_gpio.h"
-#endif
-#if defined(CONFIG_TOUCHSCREEN_GT8110)
-#include <linux/gt8110.h>
-#endif
-
-#if defined(CONFIG_MT6620)
-#include <linux/gps.h>
-#endif
-
-#if defined (CONFIG_TS_AUTO)
-#include <linux/ts-auto.h>
-#endif
-
-#if defined (CONFIG_BP_AUTO)
-#include <linux/bp-auto.h>
-#endif
-#include <linux/rk_board_id.h>
-
-#ifdef CONFIG_THREE_FB_BUFFER
-#define RK30_FB0_MEM_SIZE 12*SZ_1M
-#else
-#define RK30_FB0_MEM_SIZE 8*SZ_1M
-#endif
-#define PMIC_IS_WM831X 0
-
-#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Macro Define Begin ------------------------*/
-/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
-#if defined(CONFIG_SOC_CAMERA_SID130B)
-#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_SID130B /* back camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_0 0x6e
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 3
-#define CONFIG_SENSOR_CIF_INDEX_0 0 // 1
-#define CONFIG_SENSOR_ORIENTATION_0 90
-#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 RK30_PIN1_PB6
-#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_L
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000
-#endif
-
-#if defined(CONFIG_SOC_CAMERA_GT2005)
-#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_GT2005 /* back camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_0 0x78
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 3
-#define CONFIG_SENSOR_CIF_INDEX_0 0 // 1
-#define CONFIG_SENSOR_ORIENTATION_0 90
-#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 RK30_PIN1_PB6
-#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_H
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_L
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_L
-
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000
-#endif
-
-#define CONFIG_SENSOR_01 RK29_CAM_SENSOR_HI253 /* back camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_01 0x40
-#define CONFIG_SENSOR_CIF_INDEX_01 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 3
-#define CONFIG_SENSOR_ORIENTATION_01 90
-#define CONFIG_SENSOR_POWER_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_01 RK30_PIN1_PB6
-#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_01 30000
-
-#define CONFIG_SENSOR_02 RK29_CAM_SENSOR_OV5640 /* back camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_02 0x78
-#define CONFIG_SENSOR_CIF_INDEX_02 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 3
-#define CONFIG_SENSOR_ORIENTATION_02 90
-#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_02 RK30_PIN1_PB6
-#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000
-
-#if defined(CONFIG_SOC_CAMERA_SIV121D)
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_SIV121D /* front camera sensor 0 */
-#define CONFIG_SENSOR_IIC_ADDR_1 0x66
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 3
-#define CONFIG_SENSOR_CIF_INDEX_1 0
-#define CONFIG_SENSOR_ORIENTATION_1 270
-#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_1 RK30_PIN1_PB7
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000
-#endif
-
-#if defined(CONFIG_SOC_CAMERA_GC0308)
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_GC0308 /* front camera sensor 0 */
-#define CONFIG_SENSOR_IIC_ADDR_1 0x42
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 3
-#define CONFIG_SENSOR_CIF_INDEX_1 0
-#define CONFIG_SENSOR_ORIENTATION_1 270
-#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_1 RK30_PIN1_PB7
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000
-#endif
-
-#define CONFIG_SENSOR_11 RK29_CAM_SENSOR_HI704 /* front camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_11 0x60
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 3
-#define CONFIG_SENSOR_CIF_INDEX_11 0
-#define CONFIG_SENSOR_ORIENTATION_11 270
-#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_11 RK30_PIN1_PB7
-#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_11 30000
-
-#define CONFIG_SENSOR_12 RK29_CAM_SENSOR_OV2659//RK29_CAM_SENSOR_OV2655 /* front camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_12 0x60
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 3
-#define CONFIG_SENSOR_CIF_INDEX_12 0
-#define CONFIG_SENSOR_ORIENTATION_12 270
-#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_12 RK30_PIN1_PB7
-#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_12 30000
-
-
-#endif //#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk30_camera.c"
-/*---------------- Camera Sensor Macro Define End ---------*/
-
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#define CONFIG_SENSOR_POWER_IOCTL_USR 1 //define this refer to your board layout
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
-
-static void rk_cif_power(int on)
-{
- struct regulator *ldo_18,*ldo_28;
- ldo_28 = regulator_get(NULL, "vmmc"); // vcc28_cif ldo7
- ldo_18 = regulator_get(NULL, "vdig1"); // vcc18_cif ldo1
- if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){
- printk("get cif ldo failed!\n");
- return;
- }
- if(on == 0){
- regulator_disable(ldo_28);
- regulator_put(ldo_28);
- regulator_disable(ldo_18);
- regulator_put(ldo_18);
- mdelay(500);
- }
- else{
- regulator_set_voltage(ldo_28, 2800000, 2800000);
- regulator_enable(ldo_28);
- // printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
- regulator_put(ldo_28);
-
- regulator_set_voltage(ldo_18, 1800000, 1800000);
- // regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(ldo_18);
- // printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
- regulator_put(ldo_18);
- }
-}
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- //#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
- rk_cif_power(on);
-}
-#endif
-
-#if CONFIG_SENSOR_RESET_IOCTL_USR
-static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
-static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-
-#if CONFIG_SENSOR_IIC_ADDR_0
-static struct reginfo_t rk_init_data_sensor_reg_0[] =
-{
- {0x0000, 0x00,0,0}
- };
-static struct reginfo_t rk_init_data_sensor_winseqreg_0[] ={
- {0x0000, 0x00,0,0}
- };
-#endif
-
-#if CONFIG_SENSOR_IIC_ADDR_1
-static struct reginfo_t rk_init_data_sensor_reg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_01
-static struct reginfo_t rk_init_data_sensor_reg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_02
-static struct reginfo_t rk_init_data_sensor_reg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_11
-static struct reginfo_t rk_init_data_sensor_reg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_12
-static struct reginfo_t rk_init_data_sensor_reg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] =
-{
- #if CONFIG_SENSOR_IIC_ADDR_0
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_0,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_1
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_1,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_01
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_01,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_02
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_02,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_11
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_11,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_12
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_12,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
-
- };
-#include "../../../drivers/media/video/rk30_camera.c"
-
-#endif /* CONFIG_VIDEO_RK29 */
-
-#ifdef CONFIG_TOUCHSCREEN_GT82X_IIC
-#define TOUCH_ENABLE_PIN INVALID_GPIO
-#define TOUCH_RESET_PIN RK30_PIN4_PD0
-#define TOUCH_INT_PIN RK30_PIN4_PC2
-int goodix_init_platform_hw(void)
-{
- int ret;
-
- rk30_mux_api_set(GPIO4D0_SMCDATA8_TRACEDATA8_NAME, GPIO4D_GPIO4D0);
- rk30_mux_api_set(GPIO4C2_SMCDATA2_TRACEDATA2_NAME, GPIO4C_GPIO4C2);
- //printk("%s:0x%x,0x%x\n",__func__,rk30_mux_api_get(GPIO4D0_SMCDATA8_TRACEDATA8_NAME),rk30_mux_api_get(GPIO4C2_SMCDATA2_TRACEDATA2_NAME));
- if (TOUCH_ENABLE_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_ENABLE_PIN, "goodix power pin");
- if (ret != 0) {
- gpio_free(TOUCH_ENABLE_PIN);
- printk("goodix power error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_ENABLE_PIN, 0);
- gpio_set_value(TOUCH_ENABLE_PIN, GPIO_LOW);
- msleep(100);
- }
-
- if (TOUCH_RESET_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_RESET_PIN, "goodix reset pin");
- if (ret != 0) {
- gpio_free(TOUCH_RESET_PIN);
- printk("goodix gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- gpio_set_value(TOUCH_RESET_PIN, GPIO_LOW);
- msleep(10);
- gpio_set_value(TOUCH_RESET_PIN, GPIO_HIGH);
- msleep(500);
- }
- return 0;
-}
-u8 ts82x_config_data[] = {
- 0x65,0x00,0x04,0x00,0x03,0x00,0x0A,0x0D,0x1E,0xE7,
- 0x32,0x03,0x08,0x10,0x48,0x42,0x42,0x20,0x00,0x01,
- 0x60,0x60,0x4B,0x6E,0x0E,0x0D,0x0C,0x0B,0x0A,0x09,
- 0x08,0x07,0x06,0x05,0x04,0x03,0x02,0x01,0x00,0x1D,
- 0x1C,0x1B,0x1A,0x19,0x18,0x17,0x16,0x15,0x14,0x13,
- 0x12,0x11,0x10,0x0F,0x50,0x00,0x00,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2B,0x00,0x00,
- 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x00
-};
-static struct goodix_i2c_rmi_platform_data ts82x_pdata = {
- .gpio_shutdown = TOUCH_ENABLE_PIN,
- .gpio_irq = TOUCH_INT_PIN,
- .gpio_reset = TOUCH_RESET_PIN,
- .irq_edge = 1, /* 0:rising edge, 1:falling edge */
-
- .ypol = 1,
- .swap_xy = 1,
- .xpol = 0,
- .xmax = 1024,
- .ymax = 600,
- .config_info_len =ARRAY_SIZE(ts82x_config_data),
- .config_info = ts82x_config_data,
- .init_platform_hw= goodix_init_platform_hw,
-};
-#endif
-
-#if defined (CONFIG_RK_HEADSET_DET) || defined (CONFIG_RK_HEADSET_IRQ_HOOK_ADC_DET)
-
-static int rk_headset_io_init(int gpio)
-{
- int ret;
- ret = gpio_request(gpio, "headset_input");
- if(ret)
- return ret;
-
- rk30_mux_api_set(GPIO0C7_TRACECTL_SMCADDR3_NAME, GPIO0C_GPIO0C7);
- gpio_pull_updown(gpio, PullDisable);
- gpio_direction_input(gpio);
- mdelay(50);
- return 0;
-};
-
-struct rk_headset_pdata rk_headset_info = {
- .Headset_gpio = RK30_PIN0_PC7,
- .headset_in_type = HEADSET_IN_LOW,
- .Hook_adc_chn = 2,
- .hook_key_code = KEY_MEDIA,
- .headset_io_init = rk_headset_io_init,
-};
-
-struct platform_device rk_device_headset = {
- .name = "rk_headsetdet",
- .id = 0,
- .dev = {
- .platform_data = &rk_headset_info,
- }
-};
-#endif
-
-#if defined (CONFIG_TOUCHSCREEN_SYNAPTICS_S3202)
-
-#define TOUCH_RESET_PIN RK30_PIN4_PD0
-#define TOUCH_INT_PIN RK30_PIN4_PC2
-#define TOUCH_POWER_PIN -1
-#define TOUCH_IO_POWER_PIN -1
-
-struct syna_gpio_data {
- u16 gpio_number;
- char* gpio_name;
-};
-
-int syna_init_platform_hw(void)
-{
- return 0;
-}
-
-static int synaptics_touchpad_gpio_setup(void *gpio_data, bool configure)
-{
- int retval=0;
- struct syna_gpio_data *data = gpio_data;
-
- if (configure) {
- retval = gpio_request(data->gpio_number, "rmi4_attn");
- if (retval) {
- pr_err("%s: Failed to get attn gpio %d. Code: %d.",
- __func__, data->gpio_number, retval);
- return retval;
- }
- rk30_mux_api_set(GPIO4C2_SMCDATA2_TRACEDATA2_NAME, 0);
- retval = gpio_direction_input(data->gpio_number);
- if (retval) {
- pr_err("%s: Failed to setup attn gpio %d. Code: %d.",
- __func__, data->gpio_number, retval);
- gpio_free(data->gpio_number);
- }
- } else {
- printk("%s: No way to deconfigure gpio %d.",
- __func__, data->gpio_number);
- }
-
- return retval;
-
-}
-
-static struct syna_gpio_data s3202_gpiodata = {
- .gpio_number = TOUCH_INT_PIN,
- .gpio_name = "GPIO4_C2",
-};
-static unsigned char s3202_key_array[4]={ KEY_BACK, KEY_MENU, KEY_HOMEPAGE, KEY_SEARCH };
-
-struct rmi_f1a_button_map s3202_buttons = {
- .nbuttons = 0,
- .map = s3202_key_array,
-};
-
-static struct rmi_device_platform_data s3202_platformdata = {
- .sensor_name = "Espresso",
- .driver_name = "rmi_generic",
- .attn_gpio = TOUCH_INT_PIN,
- .attn_polarity = RMI_ATTN_ACTIVE_LOW,
- .level_triggered = false, /* For testing */
- .gpio_data = &s3202_gpiodata,
- .gpio_config = synaptics_touchpad_gpio_setup,
- .init_hw = syna_init_platform_hw,
- .axis_align = {
- .swap_axes = 1,
- .flip_x = 0,
- .flip_y = 0,
- .clip_X_low = 0,
- .clip_Y_low = 0,
- .clip_X_high = 0,
- .clip_Y_high = 0,
- },
- .f1a_button_map = &s3202_buttons,
-};
-
-#endif
-
-
-#if defined(CONFIG_TOUCHSCREEN_GT8XX)
-#define TOUCH_RESET_PIN RK30_PIN4_PD0
-#define TOUCH_PWR_PIN INVALID_GPIO
-
-int goodix_init_platform_hw(void)
-{
- int ret;
-
- rk30_mux_api_set(GPIO4D0_SMCDATA8_TRACEDATA8_NAME, GPIO4D_GPIO4D0);
- rk30_mux_api_set(GPIO4C2_SMCDATA2_TRACEDATA2_NAME, GPIO4C_GPIO4C2);
- printk("%s:0x%x,0x%x\n",__func__,rk30_mux_api_get(GPIO4D0_SMCDATA8_TRACEDATA8_NAME),rk30_mux_api_get(GPIO4C2_SMCDATA2_TRACEDATA2_NAME));
-
- if (TOUCH_PWR_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_PWR_PIN, "goodix power pin");
- if (ret != 0) {
- gpio_free(TOUCH_PWR_PIN);
- printk("goodix power error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_PWR_PIN, 0);
- gpio_set_value(TOUCH_PWR_PIN, GPIO_LOW);
- msleep(100);
- }
-
- if (TOUCH_RESET_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_RESET_PIN, "goodix reset pin");
- if (ret != 0) {
- gpio_free(TOUCH_RESET_PIN);
- printk("goodix gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, 1);
- msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_LOW);
- //msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_HIGH);
- //msleep(500);
- }
- return 0;
-}
-
-struct goodix_platform_data goodix_info = {
- .model = 8105,
- .irq_pin = RK30_PIN4_PC2,
- .rest_pin = TOUCH_RESET_PIN,
- .init_platform_hw = goodix_init_platform_hw,
-};
-#endif
-
-#if defined(CONFIG_TOUCHSCREEN_FT5306)
-
-#define TOUCH_RESET_PIN RK30_PIN4_PD0
-#define TOUCH_INT_PIN RK30_PIN4_PC2
-int ft5306_init_platform_hw(void)
-{
- printk("ft5306_init_platform_hw\n");
-
- rk30_mux_api_set(GPIO4C2_SMCDATA2_TRACEDATA2_NAME, 0);
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("ft5406_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("ift5406_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- rk30_mux_api_set(GPIO4D0_SMCDATA8_TRACEDATA8_NAME, 0);
-
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- mdelay(10);
- gpio_direction_input(TOUCH_INT_PIN);
- mdelay(10);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- msleep(300);
- return 0;
-
-}
-
-void ft5306_exit_platform_hw(void)
-{
- printk("ft5306_exit_platform_hw\n");
- gpio_free(TOUCH_RESET_PIN);
- gpio_free(TOUCH_INT_PIN);
-}
-
-int ft5306_platform_sleep(void)
-{
- //printk("ft5306_platform_sleep\n");
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- return 0;
-}
-
-int ft5306_platform_wakeup(void)
-{
- //printk("ft5306_platform_wakeup\n");
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- msleep(300);
- return 0;
-}
-
-struct ft5x0x_platform_data ft5306_info = {
- .model = 5306,
- .max_x = 1024,
- .max_y = 768,
- .key_min_x = 1024,
- .xy_swap = 1,
- .x_revert = 1,
- .y_revert = 0,
- .init_platform_hw= ft5306_init_platform_hw,
- .exit_platform_hw= ft5306_exit_platform_hw,
- .ft5x0x_platform_sleep = ft5306_platform_sleep,
- .ft5x0x_platform_wakeup = ft5306_platform_wakeup,
-};
-
-
-#endif
-
-#if defined(CONFIG_TOUCHSCREEN_CT360_IIC)
-#define TOUCH_RESET_PIN RK30_PIN4_PD0
-#define TOUCH_INT_PIN RK30_PIN4_PC2
-
-static void ct360_hw_init(void)
-{
- int ret;
-
- printk("%s\n", __FUNCTION__);
-
- rk30_mux_api_set(GPIO4C2_SMCDATA2_TRACEDATA2_NAME, 0);
- rk30_mux_api_set(GPIO4D0_SMCDATA8_TRACEDATA8_NAME, 0);
-
- if(TOUCH_RESET_PIN != INVALID_GPIO){
- gpio_request(TOUCH_RESET_PIN, "ct360_reset");
- gpio_direction_output(TOUCH_RESET_PIN, GPIO_HIGH);
- }
-
- if(TOUCH_INT_PIN != INVALID_GPIO){
- ret = gpio_request(TOUCH_INT_PIN, "ct360_irq");
- if(ret != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("%s: ct360 irq request err\n", __func__);
- }
- else{
- gpio_direction_input(TOUCH_INT_PIN);
- gpio_pull_updown(TOUCH_INT_PIN, PullEnable);
- }
- }
-}
-
-static void ct360_hw_shutdown(int reset)
-{
- if(TOUCH_RESET_PIN != INVALID_GPIO){
- if(reset){
- gpio_set_value(TOUCH_RESET_PIN, GPIO_HIGH);
- }
- else{
- gpio_set_value(TOUCH_RESET_PIN, GPIO_LOW);
- }
- }
-}
-
-
-static struct ct360_platform_data ct360_info = {
- .model = 360,
- .x_max = 800,
- .y_max = 480,
- .hw_init = ct360_hw_init,
- .shutdown = ct360_hw_shutdown,
-};
-
-#endif
-
-
-#ifdef CONFIG_TOUCHSCREEN_GT8110
-#define TOUCH_ENABLE_PIN INVALID_GPIO
-#define TOUCH_INT_PIN RK30_PIN4_PC2
-#define TOUCH_RESET_PIN RK30_PIN4_PD0
-int goodix_init_platform_hw(void)
-{
-
- int ret;
- rk30_mux_api_set(GPIO4D0_SMCDATA8_TRACEDATA8_NAME, GPIO4D_GPIO4D0);
- rk30_mux_api_set(GPIO4C2_SMCDATA2_TRACEDATA2_NAME, GPIO4C_GPIO4C2);
- printk("%s:0x%x,0x%x\n",__func__,rk30_mux_api_get(GPIO4D0_SMCDATA8_TRACEDATA8_NAME),rk30_mux_api_get(GPIO4C2_SMCDATA2_TRACEDATA2_NAME));
-
- if (TOUCH_ENABLE_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_ENABLE_PIN, "goodix power pin");
- if (ret != 0) {
- gpio_free(TOUCH_ENABLE_PIN);
- printk("goodix power error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_ENABLE_PIN, 0);
- gpio_set_value(TOUCH_ENABLE_PIN, GPIO_LOW);
- msleep(100);
- }
-
- if (TOUCH_RESET_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_RESET_PIN, "goodix reset pin");
- if (ret != 0) {
- gpio_free(TOUCH_RESET_PIN);
- printk("goodix gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- //msleep(100);
- gpio_set_value(TOUCH_RESET_PIN, GPIO_LOW);
- msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_HIGH);
- //msleep(500);
- }
- return 0;
-}
-
-int goodix_exit_platform_hw(void)
-{
- return 0;
-}
-
-struct goodix_8110_platform_data goodix_info = {
- .irq_pin = TOUCH_INT_PIN,
- .reset= TOUCH_RESET_PIN,
- .hw_init = goodix_init_platform_hw,
- .hw_exit = goodix_exit_platform_hw,
-};
-#endif
-
-#if defined(CONFIG_TS_AUTO_I2C)
-#define TOUCH_RESET_PIN RK30_PIN4_PD0
-#define TOUCH_INT_PIN RK30_PIN4_PC2
-int ts_init_platform_hw(void)
-{
- rk30_mux_api_set(GPIO4C2_SMCDATA2_TRACEDATA2_NAME, 0);
- rk30_mux_api_set(GPIO4D0_SMCDATA8_TRACEDATA8_NAME, 0);
-
- gpio_request(TOUCH_INT_PIN, "ts_irq_pin");
- gpio_request(TOUCH_RESET_PIN, "ts_reset_pin");
- gpio_direction_output(TOUCH_RESET_PIN, GPIO_LOW);
- msleep(10);
- gpio_direction_output(TOUCH_RESET_PIN, GPIO_HIGH);
- msleep(200);
- printk("%s\n",__func__);
- return 0;
-}
-
-struct ts_platform_data auto_ts_info = {
- .irq = TOUCH_INT_PIN,
- .power_pin = INVALID_GPIO,
- .reset_pin = TOUCH_RESET_PIN,
- .init_platform_hw = ts_init_platform_hw,
-};
-
-#endif
-
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-#define PWM_ID 2
-#define PWM_MUX_NAME GPIO0D6_PWM2_NAME
-#define PWM_MUX_MODE GPIO0D_PWM2
-#define PWM_MUX_MODE_GPIO GPIO0A_GPIO0A3
-#define PWM_GPIO RK30_PIN0_PD6
-#define PWM_EFFECT_VALUE 1
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-//#define BL_EN_MUX_NAME GPIOF34_UART3_SEL_NAME
-//#define BL_EN_MUX_MODE IOMUXB_GPIO1_B34
-
-#define BL_EN_PIN RK30_PIN6_PB3
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
- //rk30_mux_api_set(GPIO0D6_PWM2_NAME, GPIO0D_GPIO0D6);
- //gpio_request(RK30_PIN0_PD6, NULL);
- //gpio_direction_output(RK30_PIN0_PD6, GPIO_HIGH);
-
- rk30_mux_api_set(GPIO0D6_PWM2_NAME, GPIO0D_PWM2);
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
-#ifdef LCD_DISP_ON_PIN
- // rk30_mux_api_set(BL_EN_MUX_NAME, BL_EN_MUX_MODE);
-
- ret = gpio_request(BL_EN_PIN, NULL);
- if (ret != 0) {
- gpio_free(BL_EN_PIN);
- }
-
- gpio_direction_output(BL_EN_PIN, BL_EN_VALUE);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0;
-#ifdef LCD_DISP_ON_PIN
- gpio_free(BL_EN_PIN);
-#endif
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret = 0;
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- if (gpio_request(PWM_GPIO, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- gpio_direction_output(PWM_GPIO, !PWM_EFFECT_VALUE);
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, !BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- gpio_free(PWM_GPIO);
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
-#ifdef LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, 1);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
- .pre_div = 20000,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-#endif
-
-#if defined (CONFIG_SND_SOC_RT3224) || defined (CONFIG_SND_SOC_RT3261)
-
-#define DIFFERENTIAL 1
-#define SINGLE_END 0
-#define TWO_SPK 2
-#define ONE_SPK 1
-
-enum {
- SPK_AMPLIFY_ZERO_POINT_FIVE_WATT=1,
- SPK_AMPLIFY_ZERO_POINT_SIX_WATT,
- SPK_AMPLIFY_ZERO_POINT_EIGHT_WATT,
- SPK_AMPLIFY_ONE_WATT,
-};
-
-enum {
- LR_NORMAL,
- LR_SWAP,
- LEFT_COPY_TO_RIGHT,
- RIGHT_COPY_LEFT,
-};
-
-static int rt3261_io_init(int gpio, char *iomux_name, int iomux_mode)
-{
- gpio_request(gpio,NULL);
- rk30_mux_api_set(iomux_name, iomux_mode);
- gpio_direction_output(gpio,1);
-
-};
-
-static struct rt3261_platform_data rt3261_info = {
- .codec_en_gpio = RK30_PIN4_PD7,
- .codec_en_gpio_info = {GPIO4D7_SMCDATA15_TRACEDATA15_NAME,GPIO4D_GPIO4D7},
- .io_init = rt3261_io_init,
- .spk_num = TWO_SPK,
- .modem_input_mode = DIFFERENTIAL,
- .lout_to_modem_mode = DIFFERENTIAL,
- .spk_amplify = SPK_AMPLIFY_ZERO_POINT_SIX_WATT,
- .playback_if1_data_control = LR_NORMAL,
- .playback_if2_data_control = LR_NORMAL,
-};
-#endif
-
-#ifdef CONFIG_RK29_SUPPORT_MODEM
-
-#define RK30_MODEM_POWER RK30_PIN4_PD1
-#define RK30_MODEM_POWER_IOMUX rk29_mux_api_set(GPIO4D1_SMCDATA9_TRACEDATA9_NAME, GPIO4D_GPIO4D1)
-
-static int rk30_modem_io_init(void)
-{
- printk("%s\n", __FUNCTION__);
- RK30_MODEM_POWER_IOMUX;
-
- return 0;
-}
-
-static struct rk29_io_t rk30_modem_io = {
- .io_addr = RK30_MODEM_POWER,
- .enable = GPIO_HIGH,
- .disable = GPIO_LOW,
- .io_init = rk30_modem_io_init,
-};
-
-static struct platform_device rk30_device_modem = {
- .name = "rk30_modem",
- .id = -1,
- .dev = {
- .platform_data = &rk30_modem_io,
- }
-};
-#endif
-#if defined(CONFIG_MU509)
-static int mu509_io_init(void)
-{
-
- rk30_mux_api_set(GPIO2B6_LCDC1DATA14_SMCADDR18_TSSYNC_NAME, GPIO2B_GPIO2B6);
- rk30_mux_api_set(GPIO4D2_SMCDATA10_TRACEDATA10_NAME, GPIO4D_GPIO4D2);
- rk30_mux_api_set(GPIO2B7_LCDC1DATA15_SMCADDR19_HSADCDATA7_NAME, GPIO2B_GPIO2B7);
- rk30_mux_api_set(GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME, GPIO2C_GPIO2C0);
- return 0;
-}
-
-static int mu509_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mu509_data rk29_mu509_info = {
- .io_init = mu509_io_init,
- .io_deinit = mu509_io_deinit,
- .modem_power_en = RK30_PIN6_PB2,//RK30_PIN4_PD1,
- .bp_power = RK30_PIN2_PB6,//RK30_PIN4_PD1,
- .bp_reset = RK30_PIN4_PD2,
- .ap_wakeup_bp = RK30_PIN2_PB7,
- .bp_wakeup_ap = RK30_PIN6_PA0,
-};
-struct platform_device rk29_device_mu509 = {
- .name = "mu509",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mu509_info,
- }
- };
-#endif
-#if defined(CONFIG_MW100)
-static int mw100_io_init(void)
-{
- rk30_mux_api_set(GPIO2B6_LCDC1DATA14_SMCADDR18_TSSYNC_NAME, GPIO2B_GPIO2B6);
- rk30_mux_api_set(GPIO4D2_SMCDATA10_TRACEDATA10_NAME, GPIO4D_GPIO4D2);
- rk30_mux_api_set(GPIO2B7_LCDC1DATA15_SMCADDR19_HSADCDATA7_NAME, GPIO2B_GPIO2B7);
- rk30_mux_api_set(GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME, GPIO2C_GPIO2C0);
- return 0;
-}
-
-static int mw100_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mw100_data rk29_mw100_info = {
- .io_init = mw100_io_init,
- .io_deinit = mw100_io_deinit,
- .modem_power_en = RK30_PIN6_PB2,
- .bp_power = RK30_PIN2_PB6,
- .bp_reset = RK30_PIN4_PD2,
- .ap_wakeup_bp = RK30_PIN2_PB7,
- .bp_wakeup_ap = RK30_PIN6_PA0,
-};
-struct platform_device rk29_device_mw100 = {
- .name = "mw100",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mw100_info,
- }
- };
-#endif
-#if defined(CONFIG_MT6229)
-static int mt6229_io_init(void)
-{
- rk30_mux_api_set(GPIO2B6_LCDC1DATA14_SMCADDR18_TSSYNC_NAME, GPIO2B_GPIO2B6);
- rk30_mux_api_set(GPIO4D2_SMCDATA10_TRACEDATA10_NAME, GPIO4D_GPIO4D2);
- rk30_mux_api_set(GPIO2B7_LCDC1DATA15_SMCADDR19_HSADCDATA7_NAME, GPIO2B_GPIO2B7);
- rk30_mux_api_set(GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME, GPIO2C_GPIO2C0);
- rk30_mux_api_set(GPIO2C1_LCDC1DATA17_SMCBLSN0_HSADCDATA6_NAME, GPIO2C_GPIO2C1);
- rk30_mux_api_set(GPIO2C1_LCDC1DATA17_SMCBLSN0_HSADCDATA6_NAME, GPIO2C_GPIO2C1);
-
- return 0;
-}
-
-static int mt6229_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mt6229_data rk29_mt6229_info = {
- .io_init = mt6229_io_init,
- .io_deinit = mt6229_io_deinit,
- .modem_power_en = RK30_PIN6_PB2, // 3g_power
- .bp_power = RK30_PIN2_PB6, // 3g_en
- .modem_usb_en = RK30_PIN2_PC0, //W_disable
- .modem_uart_en = RK30_PIN2_PC1, //EINT9
- .bp_wakeup_ap = RK30_PIN6_PA1, //
- .ap_ready = RK30_PIN2_PB7, //
-
-};
-struct platform_device rk29_device_mt6229 = {
- .name = "mt6229",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mt6229_info,
- }
- };
-#endif
-#if defined(CONFIG_SEW868)
-static int sew868_io_init(void)
-{
- rk30_mux_api_set(GPIO2B6_LCDC1DATA14_SMCADDR18_TSSYNC_NAME, GPIO2B_GPIO2B6);
- rk30_mux_api_set(GPIO4D2_SMCDATA10_TRACEDATA10_NAME, GPIO4D_GPIO4D2);
- rk30_mux_api_set(GPIO4D4_SMCDATA12_TRACEDATA12_NAME, GPIO4D_GPIO4D4);
- return 0;
-}
-static int sew868_io_deinit(void)
-{
- return 0;
-}
-struct rk30_sew868_data rk30_sew868_info = {
- .io_init = sew868_io_init,
- .io_deinit = sew868_io_deinit,
- .bp_power = RK30_PIN6_PB2,
- .bp_power_active_low = 1,
- .bp_sys = RK30_PIN2_PB6,
- .bp_reset = RK30_PIN4_PD2,
- .bp_reset_active_low = 1,
- .bp_wakeup_ap = RK30_PIN4_PD4,
- .ap_wakeup_bp = NULL,
-};
-
-struct platform_device rk30_device_sew868 = {
- .name = "sew868",
- .id = -1,
- .dev = {
- .platform_data = &rk30_sew868_info,
- }
- };
-#endif
-#if defined(CONFIG_MI700)
-#define BP_POWER RK29_PIN6_PB1
-#define BP_RESET RK29_PIN6_PC7
-static int mi700_io_init(void)
-{
- int result;
- result = gpio_request(BP_RESET, NULL);
- if (result)
- {
- gpio_free(BP_RESET);
- printk("failed to request BP_RESET gpio\n");
- }
- result = gpio_request(BP_POWER, NULL);
- if (result)
- {
- gpio_free(BP_POWER);
- printk("failed to request BP_POWER gpio\n");
- }
- return 0;
-}
-
-static int mi700_io_deinit(void)
-{
- gpio_free(BP_RESET);
- gpio_free(BP_POWER);
-
- return 0;
-}
-
-struct rk29_mi700_data rk29_mi700_info = {
- .io_init = mi700_io_init,
- .io_deinit = mi700_io_deinit,
- .bp_power = RK29_PIN6_PB1,//RK29_PIN0_PB4,
- .bp_reset = RK29_PIN6_PC7,//RK29_PIN0_PB3,
- .bp_wakeup_ap = RK29_PIN6_PC6,//RK29_PIN0_PC2,
- .ap_wakeup_bp = NULL,//RK29_PIN0_PB0,
-};
-struct platform_device rk29_device_mi700 = {
- .name = "MI700",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mi700_info,
- }
- };
-#endif
-
-#if defined(CONFIG_BP_AUTO)
-static int bp_io_init(void)
-{
- rk30_mux_api_set(GPIO2B6_LCDC1DATA14_SMCADDR18_TSSYNC_NAME, GPIO2B_GPIO2B6);
- rk30_mux_api_set(GPIO4D2_SMCDATA10_TRACEDATA10_NAME, GPIO4D_GPIO4D2);
- rk30_mux_api_set(GPIO2B7_LCDC1DATA15_SMCADDR19_HSADCDATA7_NAME, GPIO2B_GPIO2B7);
- rk30_mux_api_set(GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME, GPIO2C_GPIO2C0);
- rk30_mux_api_set(GPIO2C1_LCDC1DATA17_SMCBLSN0_HSADCDATA6_NAME, GPIO2C_GPIO2C1);
- rk30_mux_api_set(GPIO2C1_LCDC1DATA17_SMCBLSN0_HSADCDATA6_NAME, GPIO2C_GPIO2C1);
-
- return 0;
-}
-
-static int bp_io_deinit(void)
-{
-
- return 0;
-}
-
-static int bp_id_get(void)
-{
- int bp_id = 0;
- #if defined(CONFIG_BP_AUTO_MT6229)
- bp_id = BP_ID_MT6229;
- #elif defined(CONFIG_BP_AUTO_MU509)
- bp_id = BP_ID_MU509;
- #elif defined(CONFIG_BP_AUTO_MW100)
- bp_id = BP_ID_MW100;
- #elif defined(CONFIG_BP_AUTO_MI700)
- bp_id = BP_ID_MI700;
- #endif
- #elif defined(CONFIG_BP_AUTO_MI700)
- bp_id = BP_ID_SEW290;
- #endif
- return bp_id;
-}
-
-struct bp_platform_data bp_auto_info = {
- .init_platform_hw = bp_io_init,
- .exit_platform_hw = bp_io_deinit,
- .get_bp_id = bp_id_get,
- .bp_power = RK30_PIN6_PB2, // 3g_power,¸ù¾Ýʵ¼Ê½ÓÏßÅäÖÃ
- .bp_en = BP_UNKNOW_DATA, // 3g_en
- .bp_reset = BP_UNKNOW_DATA, //¸ù¾Ýʵ¼ÊÅäÖÃ
- .bp_usb_en = BP_UNKNOW_DATA, //W_disable
- .bp_uart_en = BP_UNKNOW_DATA, //EINT9
- .bp_wakeup_ap = RK30_PIN2_PC4, //¸ù¾Ýʵ¼Ê½ÓÏßÅäÖÃ
- .ap_wakeup_bp = RK30_PIN2_PC4, //¸ù¾Ýʵ¼ÊÅäÖÃ
- .ap_ready = BP_UNKNOW_DATA, //
- .bp_ready = BP_UNKNOW_DATA,
- .gpio_valid = 1, //if 1:gpio is define in bp_auto_info,if 0:is not use gpio in bp_auto_info
-};
-
-
-struct platform_device device_bp_auto = {
- .name = "bp-auto",
- .id = -1,
- .dev = {
- .platform_data = &bp_auto_info,
- }
- };
-#endif
-
-
-
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN RK30_PIN4_PC0
-
-static int mma8452_init_platform_hw(void)
-{
- rk30_mux_api_set(GPIO4C0_SMCDATA0_TRACEDATA0_NAME, GPIO4C_GPIO4C0);
-
- return 0;
-}
-
-static struct sensor_platform_data mma8452_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma8452_init_platform_hw,
- .orientation = {-1, 0, 0, 0, 0, 1, 0, -1, 0},
-};
-#endif
-#if defined (CONFIG_GS_LIS3DH)
-#define LIS3DH_INT_PIN RK30_PIN4_PC0
-
-static int lis3dh_init_platform_hw(void)
-{
- rk30_mux_api_set(GPIO4C0_SMCDATA0_TRACEDATA0_NAME, GPIO4C_GPIO4C0);
-
- return 0;
-}
-
-static struct sensor_platform_data lis3dh_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lis3dh_init_platform_hw,
- .orientation = {0, -1, 0, 0, 0, -1, -1, 0, 0},
-};
-#endif
-#if defined (CONFIG_GS_KXTIK)
-#define KXTIK_INT_PIN RK30_PIN4_PC0
-
-static int kxtik_init_platform_hw(void)
-{
- rk30_mux_api_set(GPIO4C0_SMCDATA0_TRACEDATA0_NAME, GPIO4C_GPIO4C0);
-
- return 0;
-}
-
-static struct sensor_platform_data kxtik_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = kxtik_init_platform_hw,
- .orientation = {0, 1, 0, 0, 0, -1, 1, 0, 0},
-};
-
-#endif
-
-/*MMA7660 gsensor*/
-#if defined (CONFIG_GS_MMA7660)
-#define MMA7660_INT_PIN RK30_PIN4_PC0
-
-static int mma7660_init_platform_hw(void)
-{
- rk30_mux_api_set(GPIO4C0_SMCDATA0_TRACEDATA0_NAME, GPIO4C_GPIO4C0);
-
- return 0;
-}
-
-static struct sensor_platform_data mma7660_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma7660_init_platform_hw,
- .orientation = {0, 1, 0, 0, 0, -1, 1, 0, 0},
-};
-#endif
-
-#if defined (CONFIG_COMPASS_AK8975)
-static struct sensor_platform_data akm8975_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {0, 1, 0},
- {1, 0, 0},
- {0, 0, -1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-#if defined(CONFIG_GYRO_L3G4200D)
-
-#include <linux/l3g4200d.h>
-#define L3G4200D_INT_PIN RK30_PIN4_PC3
-
-static int l3g4200d_init_platform_hw(void)
-{
- rk30_mux_api_set(GPIO4C3_SMCDATA3_TRACEDATA3_NAME, GPIO4C_GPIO4C3);
-
- return 0;
-}
-
-static struct sensor_platform_data l3g4200d_info = {
- .type = SENSOR_TYPE_GYROSCOPE,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .orientation = {0, 1, 0, -1, 0, 0, 0, 0, -1},
- .init_platform_hw = l3g4200d_init_platform_hw,
- .x_min = 40,//x_min,y_min,z_min = (0-100) according to hardware
- .y_min = 40,
- .z_min = 20,
-};
-
-#endif
-
-#ifdef CONFIG_LS_CM3217
-static struct sensor_platform_data cm3217_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 0,
- .poll_delay_ms = 500,
-};
-
-#endif
-
-
-#if defined(CONFIG_PS_AL3006)
-static struct sensor_platform_data proximity_al3006_info = {
- .type = SENSOR_TYPE_PROXIMITY,
- .irq_enable = 1,
- .poll_delay_ms = 200,
-};
-#endif
-
-#if defined(CONFIG_PS_STK3171)
-static struct sensor_platform_data proximity_stk3171_info = {
- .type = SENSOR_TYPE_PROXIMITY,
- .irq_enable = 1,
- .poll_delay_ms = 200,
-};
-#endif
-
-
-#if defined(CONFIG_LS_AL3006)
-static struct sensor_platform_data light_al3006_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 1,
- .poll_delay_ms = 200,
-};
-#endif
-
-#if defined(CONFIG_LS_STK3171)
-static struct sensor_platform_data light_stk3171_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 1,
- .poll_delay_ms = 200,
-};
-#endif
-
-#if defined(CONFIG_LS_ISL29023)
-static struct sensor_platform_data light_isl29023_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 1,
- .poll_delay_ms = 200,
-};
-#endif
-
-
-
-
-#ifdef CONFIG_FB_ROCKCHIP
-
-#define LCD_CS_MUX_NAME GPIO4C7_SMCDATA7_TRACEDATA7_NAME
-#define LCD_CS_PIN RK30_PIN4_PC7
-#define LCD_CS_VALUE GPIO_HIGH
-
-#define LCD_STANDBY_MUX_NAME GPIO4D2_SMCDATA10_TRACEDATA10_NAME
-#define LCD_STANDBY_PIN RK30_PIN4_PD2
-#define LCD_STANDBY_VALUE GPIO_HIGH
-
-#define LCD_RST_MUX_NAME GPIO4D1_SMCDATA9_TRACEDATA9_NAME
-#define LCD_RST_PIN RK30_PIN4_PD1
-#define LCD_RST_VALUE GPIO_HIGH
-
-#define LCD_EN_MUX_NAME GPIO4C7_SMCDATA7_TRACEDATA7_NAME
-#define LCD_EN_PIN RK30_PIN6_PB4
-#define LCD_EN_VALUE GPIO_LOW
-
-#define HDMI11_MUX_NAME GPIO3A6_SDMMC0RSTNOUT_NAME
-#define HDMI11_EN_PIN RK30_PIN3_PA6
-#define HDMI11_EN_VALUE GPIO_HIGH
-
-
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
-
- rk30_mux_api_set(GPIO3A6_SDMMC0RSTNOUT_NAME, GPIO3A_GPIO3A6);
- ret = gpio_request(HDMI11_EN_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(HDMI11_EN_PIN);
- printk(KERN_ERR "hdmi gpio fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(HDMI11_EN_PIN, HDMI11_EN_VALUE);
- }
-
- rk30_mux_api_set(LCD_CS_MUX_NAME, GPIO4C_GPIO4C7);
- ret = gpio_request(LCD_CS_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_CS_PIN);
- printk(KERN_ERR "request lcd cs pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_CS_PIN, LCD_CS_VALUE);
- }
- ret = gpio_request(LCD_EN_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_EN_PIN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_EN_PIN, LCD_EN_VALUE);
- }
-
- rk30_mux_api_set(LCD_STANDBY_MUX_NAME, GPIO4D_GPIO4D2);
- ret = gpio_request(LCD_STANDBY_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_STANDBY_PIN);
- printk(KERN_ERR "request lcd cs pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_STANDBY_PIN, LCD_STANDBY_VALUE);
- }
-
- rk30_mux_api_set(LCD_RST_MUX_NAME, GPIO4D_GPIO4D1);
- ret = gpio_request(LCD_RST_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_RST_PIN);
- printk(KERN_ERR "request lcd cs pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_RST_PIN, LCD_RST_VALUE);
- }
-
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
- msleep(30); //Response Time (Rising + Falling)
- gpio_set_value(HDMI11_EN_PIN, HDMI11_EN_VALUE? 0:1);
- gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE? 0:1);
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE? 0:1);
- gpio_set_value(LCD_RST_PIN, LCD_RST_VALUE? 0:1);
- gpio_set_value(LCD_STANDBY_PIN, LCD_STANDBY_VALUE? 0:1);
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
- gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE);
- gpio_set_value(HDMI11_EN_PIN, HDMI11_EN_VALUE);
- gpio_set_value(LCD_RST_PIN, LCD_RST_VALUE);
- gpio_set_value(LCD_STANDBY_PIN, LCD_STANDBY_VALUE);
- msleep(150); //wait for power stable
- return 0;
-}
-
-#if defined(CONFIG_LCDC0_RK30)
-struct rk29fb_info lcdc0_screen_info = {
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK30)
-struct rk29fb_info lcdc1_screen_info = {
- #if defined(CONFIG_HDMI_RK30)
- .prop = EXTEND, //extend display device
- .lcd_info = NULL,
- .set_screen_info = hdmi_init_lcdc,
- #endif
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-
-#if defined(CONFIG_LCDC0_RK30)
-static struct resource resource_lcdc0[] = {
- [0] = {
- .name = "lcdc0 reg",
- .start = RK30_LCDC0_PHYS,
- .end = RK30_LCDC0_PHYS + RK30_LCDC0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc0 irq",
- .start = IRQ_LCDC0,
- .end = IRQ_LCDC0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc0 = {
- .name = "rk30-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc0),
- .resource = resource_lcdc0,
- .dev = {
- .platform_data = &lcdc0_screen_info,
- },
-};
-#endif
-#if defined(CONFIG_LCDC1_RK30)
-extern struct rk29fb_info lcdc1_screen_info;
-static struct resource resource_lcdc1[] = {
- [0] = {
- .name = "lcdc1 reg",
- .start = RK30_LCDC1_PHYS,
- .end = RK30_LCDC1_PHYS + RK30_LCDC1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc1 irq",
- .start = IRQ_LCDC1,
- .end = IRQ_LCDC1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc1 = {
- .name = "rk30-lcdc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resource_lcdc1),
- .resource = resource_lcdc1,
- .dev = {
- .platform_data = &lcdc1_screen_info,
- },
-};
-#endif
-
-#ifdef CONFIG_ANDROID_TIMED_GPIO
-static struct timed_gpio timed_gpios[] = {
- {
- .name = "vibrator",
- .gpio = RK30_PIN0_PA4,
- .max_timeout = 1000,
- .active_low = 0,
- .adjust_time =20, //adjust for diff product
- },
-};
-
-static struct timed_gpio_platform_data rk29_vibrator_info = {
- .num_gpios = 1,
- .gpios = timed_gpios,
-};
-
-static struct platform_device rk29_device_vibrator = {
- .name = "timed-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_vibrator_info,
- },
-
-};
-#endif
-
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
-static struct gpio_led rk29_leds[] = {
- {
- .name = "button-backlight",
- .gpio = RK30_PIN4_PD7,
- .default_trigger = "timer",
- .active_low = 0,
- .retain_state_suspended = 0,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- },
-};
-
-static struct gpio_led_platform_data rk29_leds_pdata = {
- .leds = rk29_leds,
- .num_leds = ARRAY_SIZE(rk29_leds),
-};
-
-static struct platform_device rk29_device_gpio_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_leds_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_RK_IRDA
-#define IRDA_IRQ_PIN RK30_PIN6_PA1
-
-static int irda_iomux_init(void)
-{
- int ret = 0;
-
- //irda irq pin
- ret = gpio_request(IRDA_IRQ_PIN, NULL);
- if (ret != 0) {
- gpio_free(IRDA_IRQ_PIN);
- printk(">>>>>> IRDA_IRQ_PIN gpio_request err \n ");
- }
- gpio_pull_updown(IRDA_IRQ_PIN, PullDisable);
- gpio_direction_input(IRDA_IRQ_PIN);
-
- return 0;
-}
-
-static int irda_iomux_deinit(void)
-{
- gpio_free(IRDA_IRQ_PIN);
- return 0;
-}
-
-static struct irda_info rk29_irda_info = {
- .intr_pin = IRDA_IRQ_PIN,
- .iomux_init = irda_iomux_init,
- .iomux_deinit = irda_iomux_deinit,
- //.irda_pwr_ctl = bu92747guw_power_ctl,
-};
-
-static struct platform_device irda_device = {
-#ifdef CONFIG_RK_IRDA_NET
- .name = "rk_irda",
-#else
- .name = "bu92747_irda",
-#endif
- .id = -1,
- .dev = {
- .platform_data = &rk29_irda_info,
- }
-};
-#endif
-
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and sdio.noted by xbw at 2012-03-05
-**************************************************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "board-rk30-sdk-sdmmc.c"
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
-#define SDMMC0_WRITE_PROTECT_PIN RK30_PIN3_PB7 //According to your own project to set the value of write-protect-pin.
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
-#define SDMMC1_WRITE_PROTECT_PIN RK30_PIN3_PC7 //According to your own project to set the value of write-protect-pin.
-#endif
-
-#define RK29SDK_WIFI_SDIO_CARD_DETECT_N RK30_PIN6_PB2
-#define RK29SDK_WIFI_SDIO_CARD_INT RK30_PIN3_PD2
-
-#define RK29SDK_SD_CARD_DETECT_N RK30_PIN3_PB6 //According to your own project to set the value of card-detect-pin.
-#define RK29SDK_SD_CARD_INSERT_LEVEL GPIO_LOW // set the voltage of insert-card. Please pay attention to the default setting.
-#endif //endif ---#ifdef CONFIG_SDMMC_RK29
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- rk30_mux_api_set(GPIO3B1_SDMMC0CMD_NAME, GPIO3B_SDMMC0_CMD);
- rk30_mux_api_set(GPIO3B0_SDMMC0CLKOUT_NAME, GPIO3B_SDMMC0_CLKOUT);
- rk30_mux_api_set(GPIO3B2_SDMMC0DATA0_NAME, GPIO3B_SDMMC0_DATA0);
- rk30_mux_api_set(GPIO3B3_SDMMC0DATA1_NAME, GPIO3B_SDMMC0_DATA1);
- rk30_mux_api_set(GPIO3B4_SDMMC0DATA2_NAME, GPIO3B_SDMMC0_DATA2);
- rk30_mux_api_set(GPIO3B5_SDMMC0DATA3_NAME, GPIO3B_SDMMC0_DATA3);
-
- rk30_mux_api_set(GPIO3B6_SDMMC0DETECTN_NAME, GPIO3B_GPIO3B6);
-
- rk30_mux_api_set(GPIO3A7_SDMMC0PWREN_NAME, GPIO3A_GPIO3A7);
- gpio_request(RK30_PIN3_PA7, "sdmmc-power");
- gpio_direction_output(RK30_PIN3_PA7, GPIO_LOW);
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
-#if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- rk30_mux_api_set(GPIO3B6_SDMMC0DETECTN_NAME, GPIO3B_GPIO3B6);
-#else
- rk30_mux_api_set(GPIO3B6_SDMMC0DETECTN_NAME, GPIO3B_SDMMC0_DETECT_N);
-#endif
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- .status = rk29sdk_wifi_mmc0_status,
- .register_status_notify = rk29sdk_wifi_mmc0_status_register,
-#endif
-#if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- .detect_irq = RK29SDK_SD_CARD_DETECT_N,
- .insert_card_level = RK29SDK_SD_CARD_INSERT_LEVEL,
-#else
- .detect_irq = RK30_PIN3_PB6, // INVALID_GPIO
-#endif
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
-#else
- .write_prt = INVALID_GPIO,
-#endif
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- rk30_mux_api_set(GPIO3C0_SMMC1CMD_NAME, GPIO3C_SMMC1_CMD);
- rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_NAME, GPIO3C_SDMMC1_CLKOUT);
- rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_NAME, GPIO3C_SDMMC1_DATA0);
- rk30_mux_api_set(GPIO3C2_SDMMC1DATA1_NAME, GPIO3C_SDMMC1_DATA1);
- rk30_mux_api_set(GPIO3C3_SDMMC1DATA2_NAME, GPIO3C_SDMMC1_DATA2);
- rk30_mux_api_set(GPIO3C4_SDMMC1DATA3_NAME, GPIO3C_SDMMC1_DATA3);
- //rk30_mux_api_set(GPIO3C6_SDMMC1DETECTN_NAME, GPIO3C_SDMMC1_DETECT_N);
-
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
-#if defined(CONFIG_WIFI_CONTROL_FUNC) || defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-#if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- .detect_irq = INVALID_GPIO,//RK29SDK_WIFI_SDIO_CARD_DETECT_N,
-#else
- //.detect_irq = RK29SDK_WIFI_SDIO_CARD_DETECT_N,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
-#if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
- .sdio_INT_gpio = RK29SDK_WIFI_SDIO_CARD_INT,
-#endif
-
-#else
- .detect_irq = INVALID_GPIO,
- .enable_sd_wakeup = 0,
-#endif
-
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-/**************************************************************************************************
- * the end of setting for SDMMC devices
-**************************************************************************************************/
-
-#if (defined(CONFIG_BATTERY_RK30_ADC)||defined(CONFIG_BATTERY_RK30_ADC_FAC))
-static int batt_table[2*11+6] =
-{
- 0x4B434F52,0x7461625F,0x79726574,0,200,200,
- 3617,3630,3650,3670,3709,3749,3783,3828,3881,3930,4089,
- 3692,3906,3944,3978,4028,4091,4110,4125,4132,4140,4141
-};
-
-void charge_current_set(int on)
-{
- int ret = 0, value = 0;
- int charge_current_pin = RK30_PIN0_PC6;
-
- ret = gpio_request(charge_current_pin, NULL);
- if (ret) {
- printk("failed to request charge_current_pin gpio%d\n", charge_current_pin);
- return;
- }
- value = gpio_get_value(charge_current_pin);
- if(value != on){
- gpio_direction_output(charge_current_pin, on);
- // printk("charge_current_set %s\n", on ? "2000mA" : "500mA");
- }
- gpio_free(charge_current_pin);
-}
-
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = RK30_PIN6_PA5,
- .batt_low_pin = RK30_PIN6_PA0,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = RK30_PIN6_PA6,
-// .usb_det_pin = RK30_PIN6_PA3,
-
- .dc_det_level = GPIO_LOW,
- .charge_ok_level = GPIO_HIGH,
-// .usb_det_level = GPIO_LOW,
- .save_capacity = 1,
- .spport_usb_charging = 1,
- .is_reboot_charging = 1,
- .use_board_table = 1,
- .board_batt_table = batt_table,
- .control_usb_charging = charge_current_set,
-};
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-#ifdef CONFIG_RK30_PWM_REGULATOR
-const static int pwm_voltage_map[] = {
- 950000,975000,1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000, 1375000, 1400000
-};
-
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_core",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] =
-{
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
- .pwm_id = 3,
- .pwm_gpio = RK30_PIN0_PD7,
- .pwm_iomux_name = GPIO0D7_PWM3_NAME,
- .pwm_iomux_pwm = GPIO0D_PWM3,
- .pwm_iomux_gpio = GPIO0D_GPIO0D6,
- .pwm_voltage = 1100000,
- .suspend_voltage = 1050000,
- .min_uV = 950000,
- .max_uV = 1400000,
- .coefficient = 455, //45.5%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-#endif
-
-#ifdef CONFIG_RK29_VMAC
-#define PHY_PWR_EN_GPIO RK30_PIN1_PD6
-#include "board-rk30-sdk-vmac.c"
-#endif
-
-#ifdef CONFIG_RFKILL_RK
-// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
-static struct rfkill_rk_platform_data rfkill_rk_platdata = {
- .type = RFKILL_TYPE_BLUETOOTH,
-
- .poweron_gpio = { // BT_REG_ON
- .io = RK30_PIN3_PC7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C7_SDMMC1WRITEPRT_NAME,
- .fgpio = GPIO3C_GPIO3C7,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN3_PD1, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = GPIO3D1_SDMMC1BACKENDPWR_NAME,
- .fgpio = GPIO3D_GPIO3D1,
- },
- },
-
- .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
- .io = RK30_PIN3_PC6, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C6_SDMMC1DETECTN_NAME,
- .fgpio = GPIO3C_GPIO3C6,
- },
- },
-
- .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .gpio = {
- .io = RK30_PIN6_PA7, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
- .iomux = {
- .name = NULL,
- },
- },
- },
-
- .rts_gpio = { // UART_RTS, enable or disable BT's data coming
- .io = RK30_PIN1_PA3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = GPIO1A3_UART0RTSN_NAME,
- .fgpio = GPIO1A_GPIO1A3,
- .fmux = GPIO1A_UART0_RTS_N,
- },
- },
-};
-
-static struct platform_device device_rfkill_rk = {
- .name = "rfkill_rk",
- .id = -1,
- .dev = {
- .platform_data = &rfkill_rk_platdata,
- },
-};
-#endif
-
-#ifdef CONFIG_RK_BOARD_ID
-static int board_id_init_platform_hw(void)
-{
- rk30_mux_api_set(GPIO0D5_I2S22CHSDO_SMCADDR1_NAME, GPIO0D_GPIO0D5);
- rk30_mux_api_set(GPIO0D4_I2S22CHSDI_SMCADDR0_NAME, GPIO0D_GPIO0D4);
- rk30_mux_api_set(GPIO0D3_I2S22CHLRCKTX_SMCADVN_NAME, GPIO0D_GPIO0D3);
- rk30_mux_api_set(GPIO0D2_I2S22CHLRCKRX_SMCOEN_NAME, GPIO0D_GPIO0D2);
-
- return 0;
-}
-
-static int board_id_exit_platform_hw(void)
-{
-
- return 0;
-}
-
-//setting someting according to board id
-static int init_paramter_according_id(int id)
-{
- if(id < 0)
- return -1;
-
-#if defined(CONFIG_MACH_RK30_PHONE_PAD_C8003)
-
- signed char orientation[4][9] = {
- {0, -1, 0, 0, 0, 1, 1, 0, 0},
- {1, 0, 0, 0, 0, -1, 0, -1, 0},
- {0, 1, 0, 0, 0, -1, 1, 0, 0},
- {0, -1, 0, 0, 0, -1, -1, 0, 0},
- };
-
- u32 bl_ref[4] = {1, 0, 0, 0};
- int bp_id[4]={BP_ID_MT6229,BP_ID_MU509,BP_ID_MT6229,BP_ID_MT6229};
-
-#if defined (CONFIG_GS_MMA7660)
- memcpy(mma7660_info.orientation, orientation[id], 9);
-#endif
-#ifdef LCD_DISP_ON_PIN
- rk29_bl_info.bl_ref = bl_ref[id];
-#endif
-#if defined(CONFIG_BP_AUTO)
- bp_auto_info.bp_id=bp_id[id];
-#endif
- if(id == BOARD_ID_C8003)
- {
- //enable vccio_wl
- gpio_request(RK30_PIN0_PA6, "codec_en");
- rk30_mux_api_set(GPIO0A6_HOSTDRVVBUS_NAME, GPIO0A_GPIO0A6);
- gpio_direction_output(RK30_PIN0_PA6, GPIO_HIGH);
- }
-#else
-
-
-#endif
- return 0;
-}
-
-
-static struct board_id_platform_data rk30_board_id = {
- .gpio_pin = {RK30_PIN0_PD2,RK30_PIN0_PD3,RK30_PIN0_PD4,RK30_PIN0_PD5},
- .num_gpio = 4,
- .init_platform_hw = board_id_init_platform_hw,
- .exit_platform_hw = board_id_exit_platform_hw,
- .init_parameter = init_paramter_according_id,
-};
-
-
-static struct platform_device device_board_id = {
- .name = "rk-board-id",
- .id = -1,
- .dev = {
- .platform_data = &rk30_board_id,
- },
-};
-
-
-#endif
-
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_FB_ROCKCHIP
- &device_fb,
-#endif
-#if defined(CONFIG_LCDC0_RK30)
- &device_lcdc0,
-#endif
-#if defined(CONFIG_LCDC1_RK30)
- &device_lcdc1,
-#endif
-
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- &rk29_device_backlight,
-#endif
-
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_ANDROID_TIMED_GPIO
- &rk29_device_vibrator,
-#endif
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
- &rk29_device_gpio_leds,
-#endif
-#ifdef CONFIG_RK_IRDA
- &irda_device,
-#endif
-#if defined(CONFIG_WIFI_CONTROL_FUNC)||defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- &rk29sdk_wifi_device,
-#endif
-
-#if defined(CONFIG_MT6620)
- &mt3326_device_gps,
-#endif
-
-#ifdef CONFIG_RK29_SUPPORT_MODEM
- &rk30_device_modem,
-#endif
-#if defined(CONFIG_MU509)
- &rk29_device_mu509,
-#endif
-#if defined(CONFIG_MW100)
- &rk29_device_mw100,
-#endif
-#if defined(CONFIG_MT6229)
- &rk29_device_mt6229,
-#endif
-#if defined(CONFIG_SEW868)
- &rk30_device_sew868,
-#endif
-#if defined (CONFIG_RK_HEADSET_DET) || defined (CONFIG_RK_HEADSET_IRQ_HOOK_ADC_DET)
- &rk_device_headset,
-#endif
-#if defined(CONFIG_MI700)
- &rk29_device_mi700,
-#endif
-#if defined(CONFIG_BP_AUTO)
- &device_bp_auto,
-#endif
-
-#if (defined(CONFIG_BATTERY_RK30_ADC)||defined(CONFIG_BATTERY_RK30_ADC_FAC))
- &rk30_device_adc_battery,
-#endif
-#ifdef CONFIG_RFKILL_RK
- &device_rfkill_rk,
-#endif
-#ifdef CONFIG_RK_BOARD_ID
- &device_board_id,
-#endif
-
-};
-
-// i2c
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1d,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_GS_LIS3DH)
- {
- .type = "gs_lis3dh",
- .addr = 0x19, //0x19(SA0-->VCC), 0x18(SA0-->GND)
- .flags = 0,
- .irq = LIS3DH_INT_PIN,
- .platform_data = &lis3dh_info,
- },
-#endif
-
-#if defined (CONFIG_GS_KXTIK)
- {
- .type = "gs_kxtik",
- .addr = 0x0F,
- .flags = 0,
- .irq = KXTIK_INT_PIN,
- .platform_data = &kxtik_info,
- },
-#endif
-
-#if defined (CONFIG_GS_MMA7660)
- {
- .type = "gs_mma7660",
- .addr = 0x4c,
- .flags = 0,
- .irq = MMA7660_INT_PIN,
- .platform_data = &mma7660_info,
- },
-#endif
-
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN4_PC1,
- .platform_data = &akm8975_info,
- },
-#endif
-#if defined (CONFIG_GYRO_L3G4200D)
- {
- .type = "l3g4200d_gryo",
- .addr = 0x69,
- .flags = 0,
- .irq = L3G4200D_INT_PIN,
- .platform_data = &l3g4200d_info,
- },
-#endif
-#if defined (CONFIG_INPUT_LPSENSOR_AL3006)
- {
- .type = "al3006",
- .addr = 0x1c, //sel = 0; if sel =1, then addr = 0x1D
- .flags = 0,
- .irq = RK30_PIN6_PA2,
- },
-#endif
-
-#if defined (CONFIG_LS_AL3006)
- {
- .type = "light_al3006",
- .addr = 0x1c, //sel = 0; if sel =1, then addr = 0x1D
- .flags = 0,
- .irq = RK30_PIN6_PA2,
- .platform_data = &light_al3006_info,
- },
-#endif
-#if defined (CONFIG_LS_STK3171)
- {
- .type = "ls_stk3171",
- .addr = 0x48,
- .flags = 0,
- .irq = RK30_PIN6_PA2,
- .platform_data = &light_stk3171_info,
- },
-#endif
-
-
-#if defined (CONFIG_PS_AL3006)
- {
- .type = "proximity_al3006",
- .addr = 0x1c, //sel = 0; if sel =1, then addr = 0x1D
- .flags = 0,
- .irq = RK30_PIN6_PA2,
- .platform_data = &proximity_al3006_info,
- },
-#endif
-
-#if defined (CONFIG_PS_STK3171)
- {
- .type = "ps_stk3171",
- .addr = 0x48,
- .flags = 0,
- .irq = RK30_PIN6_PA2,
- .platform_data = &proximity_stk3171_info,
- },
-#endif
-
-
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-
-#if defined (CONFIG_SND_SOC_RT5623)
- {
- .type = "rt5623",
- .addr = 0x1a,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RT5631)
- {
- .type = "rt5631",
- .addr = 0x1a,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RT3224) || defined (CONFIG_SND_SOC_RT3261)
- {
- .type = "rt3261",
- .addr = 0x1c,
- .flags = 0,
- .platform_data = &rt3261_info,
- },
-#endif
-
-#ifdef CONFIG_MFD_RK610
- {
- .type = "rk610_ctl",
- .addr = 0x40,
- .flags = 0,
- },
-#ifdef CONFIG_RK610_TVOUT
- {
- .type = "rk610_tvout",
- .addr = 0x42,
- .flags = 0,
- },
-#endif
-#ifdef CONFIG_HDMI_RK610
- {
- .type = "rk610_hdmi",
- .addr = 0x46,
- .flags = 0,
- .irq = RK29_PIN5_PA2,
- },
-#endif
-#ifdef CONFIG_SND_SOC_RK610
- {//RK610_CODEC addr from 0x60 to 0x80 (0x60~0x80)
- .type = "rk610_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
-#endif
-#endif
-
-};
-#endif
-
-int __sramdata g_pmic_type = 0;
-#ifdef CONFIG_I2C1_RK30
-#ifdef CONFIG_MFD_WM831X_I2C
-#include "board-rk30-sdk-wm8326.c"
-#endif
-#ifdef CONFIG_MFD_TPS65910
-#define TPS65910_HOST_IRQ RK30_PIN6_PA4
-#include "board-rk30-sdk-tps65910.c"
-#endif
-
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_MFD_WM831X_I2C)
- {
- .type = "wm8326",
- .addr = 0x34,
- .flags = 0,
- .irq = RK30_PIN6_PA4,
- .platform_data = &wm831x_platdata,
- },
-#endif
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-};
-#endif
-
-
-void __sramfunc board_pmu_suspend(void)
-{
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_suspend();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_suspend();
- #endif
-}
-
-void __sramfunc board_pmu_resume(void)
-{
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_resume();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_resume();
- #endif
-}
-
- int __sramdata gpio0d7_iomux,gpio0d7_do,gpio0d7_dir,gpio0d7_en;
-
-void __sramfunc rk30_pwm_logic_suspend_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
-
-// int gpio0d7_iomux,gpio0d7_do,gpio0d7_dir,gpio0d7_en;
- sram_udelay(10000);
- gpio0d7_iomux = readl_relaxed(GRF_GPIO0D_IOMUX);
- gpio0d7_do = grf_readl(GRF_GPIO0H_DO);
- gpio0d7_dir = grf_readl(GRF_GPIO0H_DIR);
- gpio0d7_en = grf_readl(GRF_GPIO0H_EN);
-
- writel_relaxed((1<<30), GRF_GPIO0D_IOMUX);
- grf_writel((1<<31)|(1<<15), GRF_GPIO0H_DIR);
- grf_writel((1<<31)|(1<<15), GRF_GPIO0H_DO);
- grf_writel((1<<31)|(1<<15), GRF_GPIO0H_EN);
-#endif
-}
-void __sramfunc rk30_pwm_logic_resume_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- writel_relaxed((1<<30)|gpio0d7_iomux, GRF_GPIO0D_IOMUX);
- grf_writel((1<<31)|gpio0d7_en, GRF_GPIO0H_EN);
- grf_writel((1<<31)|gpio0d7_dir, GRF_GPIO0H_DIR);
- grf_writel((1<<31)|gpio0d7_do, GRF_GPIO0H_DO);
- sram_udelay(10000);
-
-#endif
-
-}
-extern void pwm_suspend_voltage(void);
-extern void pwm_resume_voltage(void);
-void rk30_pwm_suspend_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_suspend_voltage();
-#endif
-}
-void rk30_pwm_resume_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_resume_voltage();
-#endif
-}
-
-u32 gpio1a_iomux,gpio2c_iomux, gpio1b_pull,gpio2d_pull, gpio1b_dir,gpio2d_dir,gpio1b_en, gpio2d_en;
-void board_gpio_suspend(void) {
-
- gpio1a_iomux = readl_relaxed(GRF_GPIO1A_IOMUX);
- gpio2c_iomux = readl_relaxed(GRF_GPIO2C_IOMUX);
- writel_relaxed((0xf<< 26), GRF_GPIO1A_IOMUX);
- writel_relaxed((0x3 <<18), GRF_GPIO2C_IOMUX);
-
- gpio1b_pull = grf_readl(GRF_GPIO1L_PULL);
- gpio2d_pull = grf_readl(GRF_GPIO2H_PULL);
- grf_writel(gpio1b_pull |(0x3<<21)|(0x3<<5),GRF_GPIO1L_PULL);
- grf_writel( gpio2d_pull | (0x1<<17) |(0x1<<1),GRF_GPIO2H_PULL);
-
- gpio1b_dir = grf_readl(GRF_GPIO1L_DIR);
- gpio2d_dir = grf_readl(GRF_GPIO2H_DIR);
- grf_writel(gpio1b_dir |(0x1<<21),GRF_GPIO1L_DIR);
- grf_writel(gpio2d_dir | (0x1<<17) ,GRF_GPIO2H_DIR);
-
- gpio1b_en = grf_readl(GRF_GPIO1L_EN);
- gpio2d_en = grf_readl(GRF_GPIO2H_EN);
- grf_writel( gpio1b_en |(0x3<<21)|(0x3<<5),GRF_GPIO1L_EN);
- grf_writel( gpio2d_en | (0x1<<17) |(0x1<<1),GRF_GPIO2H_EN);
-
-}
- void board_gpio_resume(void) {
-
- writel_relaxed(0xffff0000|gpio1a_iomux, GRF_GPIO1A_IOMUX);
- writel_relaxed(0xffff0000|gpio2c_iomux, GRF_GPIO2C_IOMUX);
-
- grf_writel( 0xffff0000|gpio1b_pull,GRF_GPIO1L_PULL);
- grf_writel( 0xffff0000|gpio2d_pull,GRF_GPIO2H_PULL);
-
- grf_writel( 0xffff0000|gpio1b_dir,GRF_GPIO1L_DIR);
- grf_writel( 0xffff0000|gpio2d_dir,GRF_GPIO2H_DIR);
-
- grf_writel( 0xffff0000|gpio1b_en,GRF_GPIO1L_EN);
- grf_writel( 0xffff0000|gpio2d_en,GRF_GPIO2H_EN);
-
-}
-
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-#if defined (CONFIG_TOUCHSCREEN_GT8XX)
- {
- .type = "Goodix-TS",
- .addr = 0x55,
- .flags = 0,
- .irq = RK30_PIN4_PC2,
- .platform_data = &goodix_info,
- },
-#endif
-#if defined(CONFIG_TOUCHSCREEN_GT82X_IIC)
- {
- .type = "Goodix-TS-82X",
- .addr = 0x5D,
- .flags = 0,
- .irq = RK30_PIN4_PC2,
- .platform_data = &ts82x_pdata,
- },
-#endif
-#if defined (CONFIG_LS_CM3217)
- {
- .type = "light_cm3217",
- .addr = 0x10,
- .flags = 0,
- .platform_data = &cm3217_info,
- },
-#endif
-
-
-#if defined (CONFIG_TOUCHSCREEN_SYNAPTICS_S3202)
-{
- .type = "rmi_i2c",
- .addr = 0x20,
- .flags = 0,
- .irq = RK30_PIN4_PC2,
- .platform_data = &s3202_platformdata,
-},
-#endif
-
-#if defined (CONFIG_TOUCHSCREEN_FT5306)
-{
- .type = "ft5x0x_ts",
- .addr = 0x3e,
- .flags = 0,
- .irq = RK30_PIN4_PC2,
- .platform_data = &ft5306_info,
-},
-#endif
-
-#if defined (CONFIG_TOUCHSCREEN_CT360_IIC)
- {
- .type ="ct360_ts",
- .addr =0x01,
- .flags =0,
- .irq = RK30_PIN4_PC2,
- .platform_data = &ct360_info,
- },
-#endif
-
-#if defined(CONFIG_TOUCHSCREEN_GT8110)
- {
- .type = "Goodix-TS",
- .addr = 0x5c,
- .flags = 0,
- .irq = TOUCH_INT_PIN,
- .platform_data = &goodix_info,
- },
-#endif
-
-#if defined (CONFIG_TS_AUTO_I2C)
- {
- .type = "auto_ts_i2c",
- .addr = 0x01,
- .flags = 0,
- .irq = TOUCH_INT_PIN,
- .platform_data = &auto_ts_info,
- },
-#endif
-
-
-#if defined (CONFIG_LS_ISL29023)
- {
- .type = "ls_isl29023",
- .addr = 0x44,
- .flags = 0,
- .irq = RK30_PIN4_PC6,
- .platform_data = &light_isl29023_info,
- },
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C4_RK30
-static struct i2c_board_info __initdata i2c4_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO// RK30_PIN2_PD6 //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO//RK30_PIN2_PD7 //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- //set iomux (gpio) here
- //rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME, GPIO2D_GPIO2D7);
- //rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME, GPIO2D_GPIO2D6);
-
- return 0;
-}
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C4_RK30
- i2c_register_board_info(4, i2c4_info, ARRAY_SIZE(i2c4_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(5, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-
-static void dcr_en_low(void)
-{
- int ret;
- ret=gpio_request(RK30_PIN4_PB7,"dcr_en");
- if(ret<0){
- printk("dcr_en_low request io error");
- gpio_free(RK30_PIN4_PB7);
- return;
- }
- gpio_direction_output(RK30_PIN4_PB7, GPIO_LOW);
-}
-
-#define POWER_ON_PIN RK30_PIN6_PB0 //power_hold
-void rk30_pm_power_off(void)
-{
- int pwr_cnt;
-
- printk(KERN_ERR "rk30_pm_power_off start...\n");
-
-#if 0
-
- if(gpio_get_value (rk30_adc_battery_platdata.dc_det_pin) == rk30_adc_battery_platdata.dc_det_level){
- pwr_cnt=0;
- while(1){
- if(gpio_get_value (rk30_adc_battery_platdata.dc_det_pin) != rk30_adc_battery_platdata.dc_det_level){
- break;
- }
- if((gpio_get_value(RK30_PIN6_PA2)==GPIO_LOW)){
- if(pwr_cnt++>40)
- break;
- }else{
- //printk("0\n");
- pwr_cnt=0;
- }
- mdelay(50);
- }
- arm_pm_restart(0, NULL);
- }
-#endif
- #if defined(CONFIG_MFD_WM831X)
- if(pmic_is_wm8326())
- {
- wm831x_set_bits(Wm831x,WM831X_GPIO_LEVEL,0x0001,0x0000); //set sys_pwr 0
- wm831x_device_shutdown(Wm831x);//wm8326 shutdown
- }
- #endif
- #if defined(CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- {
- tps65910_device_shutdown();//tps65910 shutdown
- }
- #endif
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
- while(1);
-}
-EXPORT_SYMBOL_GPL(rk30_pm_power_off);
-static void __init machine_rk30_board_init(void)
-{
- avs_init();
- gpio_request(POWER_ON_PIN, "poweronpin");
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
- //add for codec_en
- gpio_request(RK30_PIN4_PD7, "codec_en");
- rk30_mux_api_set(GPIO4D7_SMCDATA15_TRACEDATA15_NAME, GPIO4D_GPIO4D7);
- gpio_direction_output(RK30_PIN4_PD7, GPIO_HIGH);
-
- pm_power_off = rk30_pm_power_off;
-
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- board_usb_detect_init(RK30_PIN6_PA3);
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- rk29sdk_wifi_bt_gpio_control_init();
-#endif
- dcr_en_low();
-
-#if defined(CONFIG_MT6620)
- clk_set_rate(clk_get_sys("rk_serial.0", "uart"), 48*1000000);
-#endif
-}
-
-static void __init rk30_reserve(void)
-{
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0", RK30_FB0_MEM_SIZE);
- resource_fb[0].end = resource_fb[0].start + RK30_FB0_MEM_SIZE - 1;
- #if 0
- resource_fb[1].start = board_mem_reserve_add("ipp buf", RK30_FB0_MEM_SIZE);
- resource_fb[1].end = resource_fb[1].start + RK30_FB0_MEM_SIZE - 1;
- resource_fb[2].start = board_mem_reserve_add("fb2", RK30_FB0_MEM_SIZE);
- resource_fb[2].end = resource_fb[2].start + RK30_FB0_MEM_SIZE - 1;
- #endif
-#endif
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
- board_mem_reserved();
-}
-
-/**
- * dvfs_cpu_logic_table: table for arm and logic dvfs
- * @frequency : arm frequency
- * @cpu_volt : arm voltage depend on frequency
- * @logic_volt : logic voltage arm requests depend on frequency
- * comments : min arm/logic voltage
- */
-static struct dvfs_arm_table dvfs_cpu_logic_table[] = {
- {.frequency = 252 * 1000, .cpu_volt = 1075 * 1000, .logic_volt = 1125 * 1000},//0.975V/1.000V
- {.frequency = 504 * 1000, .cpu_volt = 1100 * 1000, .logic_volt = 1125 * 1000},//0.975V/1.000V
- {.frequency = 816 * 1000, .cpu_volt = 1125 * 1000, .logic_volt = 1150 * 1000},//1.000V/1.025V
- {.frequency = 1008 * 1000, .cpu_volt = 1125 * 1000, .logic_volt = 1150 * 1000},//1.025V/1.050V
- {.frequency = 1200 * 1000, .cpu_volt = 1175 * 1000, .logic_volt = 1200 * 1000},//1.100V/1.050V
- {.frequency = 1272 * 1000, .cpu_volt = 1225 * 1000, .logic_volt = 1200 * 1000},//1.150V/1.100V
- {.frequency = 1416 * 1000, .cpu_volt = 1300 * 1000, .logic_volt = 1200 * 1000},//1.225V/1.100V
- {.frequency = 1512 * 1000, .cpu_volt = 1350 * 1000, .logic_volt = 1250 * 1000},//1.300V/1.150V
- {.frequency = 1608 * 1000, .cpu_volt = 1425 * 1000, .logic_volt = 1300 * 1000},//1.325V/1.175V
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- {.frequency = 266 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1275 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1125 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
-static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
-static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
-
-void __init board_clock_init(void)
-{
- //support uart 1-3Mbits/s
- rk30_clock_data_init(periph_pll_default, codec_pll_768mhz, RK30_CLOCKS_DEFAULT_FLAGS | CLK_FLG_UART_1_3M);
- dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
-}
-
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk30_fixup,
- .reserve = &rk30_reserve,
- .map_io = rk30_map_io,
- .init_irq = rk30_init_irq,
- .timer = &rk30_timer,
- .init_machine = machine_rk30_board_init,
-MACHINE_END
+++ /dev/null
-#ifdef CONFIG_VIDEO_RK29
-
-#include <plat/rk_camera.h>
-/* Notes:
-
-Simple camera device registration:
-
- new_camera_device(sensor_name,\ // sensor name, it is equal to CONFIG_SENSOR_X
- face,\ // sensor face information, it can be back or front
- pwdn_io,\ // power down gpio configuration, it is equal to CONFIG_SENSOR_POWERDN_PIN_XX
- flash_attach,\ // sensor is attach flash or not
- mir,\ // sensor image mirror and flip control information
- i2c_chl,\ // i2c channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_IIC_ADAPTER_ID_X
- cif_chl) \ // cif channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_CIF_INDEX_X
-
-Comprehensive camera device registration:
-
- new_camera_device_ex(sensor_name,\
- face,\
- ori,\ // sensor orientation, it is equal to CONFIG_SENSOR_ORIENTATION_X
- pwr_io,\ // sensor power gpio configuration, it is equal to CONFIG_SENSOR_POWER_PIN_XX
- pwr_active,\ // sensor power active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- rst_io,\ // sensor reset gpio configuration, it is equal to CONFIG_SENSOR_RESET_PIN_XX
- rst_active,\ // sensor reset active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- pwdn_io,\
- pwdn_active,\ // sensor power down active level, is equal to CONFIG_SENSOR_POWERDNACTIVE_LEVEL_X
- flash_attach,\
- res,\ // sensor resolution, this is real resolution or resoltuion after interpolate
- mir,\
- i2c_chl,\
- i2c_spd,\ // i2c speed , 100000 = 100KHz
- i2c_addr,\ // the i2c slave device address for sensor
- cif_chl,\
- mclk)\ // sensor input clock rate, 24 or 48
-
-*/
-static struct rkcamera_platform_data new_camera[] = {
- new_camera_device(RK29_CAM_SENSOR_OV5640,
- back,
- RK30_PIN1_PD6,
- 0,
- 0,
- 4,
- 1),
-
- /*
- new_camera_device(RK29_CAM_SENSOR_OV5642,
- back,
- RK30_PIN1_PD6,
- 0,
- 0,
- 4,
- 1),
-
- new_camera_device(RK29_CAM_SENSOR_HM5065,
- back,
- RK30_PIN1_PD6,
- 0,
- 0,
- 4,
- 1),
-
- */
- /*
- new_camera_device_ex(RK29_CAM_SENSOR_MT9P111,
- back,
- INVALID_VALUE,
- INVALID_VALUE,
- INVALID_VALUE,
- INVALID_VALUE,
- INVALID_VALUE,
- RK30_PIN1_PD6,
- CONS(RK29_CAM_SENSOR_MT9P111,_PWRDN_ACTIVE),
- 0,
- CONS(RK29_CAM_SENSOR_MT9P111,_FULL_RESOLUTION),
- 0x00,
- 4,
- 100000,
- CONS(RK29_CAM_SENSOR_MT9P111,_I2C_ADDR),
- 1,
- 24),
-
-
- */
- /*
- new_camera_device(RK29_CAM_SENSOR_SP2518,
- front,
- RK30_PIN1_PB7,
- 0,
- 0,
- 3,
- 0),
- */
- /*
- new_camera_device(RK29_CAM_SENSOR_GC2035,
- front,
- RK30_PIN1_PB7,
- 0,
- 0,
- 3,
- 0),
-
-
- */
- new_camera_device(RK29_CAM_SENSOR_OV2659,
- front,
- RK30_PIN1_PB7,
- 0,
- 0,
- 3,
- 0),
-
-
- new_camera_device_end
-};
-#endif //#ifdef CONFIG_VIDEO_RK29
-
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk30_camera.c"
-/*---------------- Camera Sensor Macro Define End ---------*/
-
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#define CONFIG_SENSOR_POWER_IOCTL_USR 1 //define this refer to your board layout
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- //#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
- struct regulator *ldo_18,*ldo_28;
-
- ldo_28 = regulator_get(NULL, "ldo7"); // vcc28_cif
- ldo_18 = regulator_get(NULL, "ldo1"); // vcc18_cif
- if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){
- printk("get cif ldo failed!\n");
- return -1;
- }
- if(on == 0){
- while(regulator_is_enabled(ldo_28)>0)
- regulator_disable(ldo_28);
- regulator_put(ldo_28);
- while(regulator_is_enabled(ldo_18)>0)
- regulator_disable(ldo_18);
- regulator_put(ldo_18);
- mdelay(10);
- } else {
- regulator_set_voltage(ldo_28, 2800000, 2800000);
- regulator_enable(ldo_28);
- //printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
- regulator_put(ldo_28);
-
- regulator_set_voltage(ldo_18, 1800000, 1800000);
- //regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(ldo_18);
- //printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
- regulator_put(ldo_18);
- }
-
- return 0;
-}
-#endif
-
-#if CONFIG_SENSOR_RESET_IOCTL_USR
-static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
-static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-
-
-static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] ;
-#include "../../../drivers/media/video/rk30_camera.c"
-
-#endif /* CONFIG_VIDEO_RK29 */
+++ /dev/null
-/*
- * Copyright (C) 2010 ROCKCHIP, Inc.
- * Author: roger_chen <cz@rock-chips.com>
- *
- * This program is the bluetooth device bcm4329's driver,
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/module.h>
-#include <linux/device.h>
-#include <linux/rfkill.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/interrupt.h>
-#include <linux/wakelock.h>
-#include <linux/fs.h>
-#include <asm/uaccess.h>
-#include <mach/gpio.h>
-#include <asm/irq.h>
-#include <mach/iomux.h>
-#include <linux/wakelock.h>
-#include <linux/timer.h>
-#include <mach/board.h>
-
-#if 0
-#define DBG(x...) printk(KERN_INFO "[BT_RFKILL]: "x)
-#else
-#define DBG(x...)
-#endif
-
-#define LOG(x...) printk(KERN_INFO "[BT_RFKILL]: "x)
-
-#ifdef CONFIG_BCM4329
-#define WIFI_BT_POWER_TOGGLE 1
-#else
-#define WIFI_BT_POWER_TOGGLE 0
-#endif
-
-#define BT_WAKE_LOCK_TIMEOUT 10 //s
-
-#define BT_AUTO_SLEEP_TIMEOUT 3
-
-/*
- * IO Configuration for RK29
- */
-#ifdef CONFIG_ARCH_RK29
-
-#define BT_WAKE_HOST_SUPPORT 0
-
-/* IO configuration */
-// BT power pin
-#define BT_GPIO_POWER RK29_PIN5_PD6
-#define IOMUX_BT_GPIO_POWER() rk29_mux_api_set(GPIO5D6_SDMMC1PWREN_NAME, GPIO5H_GPIO5D6);
-
-// BT reset pin
-#define BT_GPIO_RESET RK29_PIN6_PC4
-#define IOMUX_BT_GPIO_RESET()
-
-// BT wakeup pin
-#define BT_GPIO_WAKE_UP RK29_PIN6_PC5
-#define IOMUX_BT_GPIO_WAKE_UP()
-
-// BT wakeup host pin
-#define BT_GPIO_WAKE_UP_HOST
-#define IOMUX_BT_GPIO_WAKE_UP_HOST()
-
-//bt cts paired to uart rts
-#define UART_RTS RK29_PIN2_PA7
-#define IOMUX_UART_RTS_GPIO() rk29_mux_api_set(GPIO2A7_UART2RTSN_NAME, GPIO2L_GPIO2A7)
-#define IOMUX_UART_RTS() rk29_mux_api_set(GPIO2A7_UART2RTSN_NAME, GPIO2L_UART2_RTS_N)
-
-/*
- * IO Configuration for RK30
- */
-#elif defined (CONFIG_ARCH_RK30)
-
-#define BT_WAKE_HOST_SUPPORT 1
-
-/* IO configuration */
-// BT power pin
-#define BT_GPIO_POWER RK30_PIN3_PC7
-#define IOMUX_BT_GPIO_POWER() rk29_mux_api_set(GPIO3C7_SDMMC1WRITEPRT_NAME, GPIO3C_GPIO3C7);
-
-// BT reset pin
-#define BT_GPIO_RESET RK30_PIN3_PD1
-#define IOMUX_BT_GPIO_RESET() rk29_mux_api_set(GPIO3D1_SDMMC1BACKENDPWR_NAME, GPIO3D_GPIO3D1);
-
-// BT wakeup pin
-#define BT_GPIO_WAKE_UP RK30_PIN3_PC6
-#define IOMUX_BT_GPIO_WAKE_UP() rk29_mux_api_set(GPIO3C6_SDMMC1DETECTN_NAME, GPIO3C_GPIO3C6);
-
-// BT wakeup host pin
-#define BT_GPIO_WAKE_UP_HOST RK30_PIN6_PA7
-#define BT_IRQ_WAKE_UP_HOST gpio_to_irq(BT_GPIO_WAKE_UP_HOST)
-#define IOMUX_BT_GPIO_WAKE_UP_HOST()
-
-//bt cts paired to uart rts
-#define UART_RTS RK30_PIN1_PA3
-#define IOMUX_UART_RTS_GPIO() rk29_mux_api_set(GPIO1A3_UART0RTSN_NAME, GPIO1A_GPIO1A3)
-#define IOMUX_UART_RTS() rk29_mux_api_set(GPIO1A3_UART0RTSN_NAME, GPIO1A_UART0_RTS_N)
-
-#endif
-
-struct bt_ctrl
-{
- struct rfkill *bt_rfk;
-#if BT_WAKE_HOST_SUPPORT
- struct timer_list tl;
- bool b_HostWake;
- struct wake_lock bt_wakelock;
-#endif
-};
-
-static const char bt_name[] =
-#if defined(CONFIG_RKWIFI)
- #if defined(CONFIG_RKWIFI_26M)
- "rk903_26M"
- #else
- "rk903"
- #endif
-#elif defined(CONFIG_BCM4329)
- "bcm4329"
-#elif defined(CONFIG_MV8787)
- "mv8787"
-#else
- "bt_default"
-#endif
-;
-
-#if WIFI_BT_POWER_TOGGLE
-extern int rk29sdk_bt_power_state;
-extern int rk29sdk_wifi_power_state;
-#endif
-
-struct bt_ctrl gBtCtrl;
-struct timer_list bt_sleep_tl;
-
-void bcm4325_sleep(unsigned long bSleep);
-
-#if BT_WAKE_HOST_SUPPORT
-void resetBtHostSleepTimer(void)
-{
- mod_timer(&(gBtCtrl.tl),jiffies + BT_WAKE_LOCK_TIMEOUT*HZ);//ÔÙÖØÐÂÉèÖó¬Ê±Öµ¡£
-}
-
-void btWakeupHostLock(void)
-{
- if(gBtCtrl.b_HostWake == false){
- DBG("** Lock **\n");
- wake_lock(&(gBtCtrl.bt_wakelock));
- gBtCtrl.b_HostWake = true;
- }
-}
-
-void btWakeupHostUnlock(void)
-{
- if(gBtCtrl.b_HostWake == true){
- DBG("** UnLock **\n");
- wake_unlock(&(gBtCtrl.bt_wakelock)); //ÈÃϵͳ˯Ãß
- gBtCtrl.b_HostWake = false;
- }
-}
-
-static void timer_hostSleep(unsigned long arg)
-{
- DBG("b_HostWake=%d\n", gBtCtrl.b_HostWake);
- btWakeupHostUnlock();
-}
-
-#ifdef CONFIG_PM
-static irqreturn_t bcm4329_wake_host_irq(int irq, void *dev)
-{
- DBG("%s\n",__FUNCTION__);
-
- btWakeupHostLock();
- resetBtHostSleepTimer();
- return IRQ_HANDLED;
-}
-
-static void rfkill_do_wakeup(struct work_struct *work)
-{
- // disable bt wakeup host
- DBG("** free irq\n");
- free_irq(BT_IRQ_WAKE_UP_HOST, NULL);
-
- DBG("Enable UART_RTS\n");
- gpio_set_value(UART_RTS, GPIO_LOW);
- IOMUX_UART_RTS();
-}
-
-static DECLARE_DELAYED_WORK(wakeup_work, rfkill_do_wakeup);
-
-static int bcm4329_rfkill_suspend(struct platform_device *pdev, pm_message_t state)
-{
- DBG("%s\n",__FUNCTION__);
-
- cancel_delayed_work(&wakeup_work);
-
-#ifdef CONFIG_BT_AUTOSLEEP
- bcm4325_sleep(1);
-#endif
-
- DBG("Disable UART_RTS\n");
- //To prevent uart to receive bt data when suspended
- IOMUX_UART_RTS_GPIO();
- gpio_request(UART_RTS, "uart_rts");
- gpio_set_value(UART_RTS, GPIO_HIGH);
-
- // enable bt wakeup host
- DBG("Request irq for bt wakeup host\n");
- if (0 == request_irq(BT_IRQ_WAKE_UP_HOST,
- bcm4329_wake_host_irq,
- IRQF_TRIGGER_FALLING,
- "bt_wake",
- NULL))
- enable_irq_wake(BT_IRQ_WAKE_UP_HOST);
- else
- LOG("Failed to request BT_WAKE_UP_HOST irq\n");
-
-#ifdef CONFIG_RFKILL_RESET
- extern void rfkill_set_block(struct rfkill *rfkill, bool blocked);
- rfkill_set_block(gBtCtrl.bt_rfk, true);
-#endif
-
- return 0;
-}
-
-static int bcm4329_rfkill_resume(struct platform_device *pdev)
-{
- DBG("%s\n",__FUNCTION__);
-
- // ϵͳÍ˳ö¶þ¼¶Ë¯ÃߺóÐèÒªÀµÍRTS£¬´Ó¶ø²ÅÔÊÐíBT·¢Êý¾Ý¹ýÀ´
- // µ«ÊÇÄ¿Ç°·¢ÏÖÔÚresumeº¯ÊýÖÐÖ±½ÓÀµÍRTS»áµ¼ÖÂBTÊý¾Ý¶ªÊ§
- // ËùÒÔÑÓ³Ù1sºóÔÙÀµÍRTS
- // ϵͳÍ˳ö¶þ¼¶Ë¯ÃßʱÊͷŵôBT_IRQ_WAKE_UP_HOST£¬ÔÚ˯ÃßʱºòÔÙ
- // ´ÎÉêÇ룬Ŀǰ·¢ÏÖÖжϻص÷º¯Êý±Èresume¸üÍíÖ´ÐУ¬Èç¹ûresume
- // ʱֱ½ÓfreeµôIRQ£¬»áµ¼ÖÂÖжϻص÷º¯Êý²»»á±»Ö´ÐУ¬
- DBG("delay 1s\n");
- schedule_delayed_work(&wakeup_work, HZ);
-
- return 0;
-}
-#else
-#define bcm4329_rfkill_suspend NULL
-#define bcm4329_rfkill_resume NULL
-#endif
-
-#else
-#ifdef CONFIG_PM
-static int bcm4329_rfkill_suspend(struct platform_device *pdev, pm_message_t state)
-{
-#ifdef CONFIG_BT_AUTOSLEEP
- bcm4325_sleep(1);
-#endif
- return 0;
-}
-#else
-#define bcm4329_rfkill_suspend NULL
-#endif
-#define bcm4329_rfkill_resume NULL
-#endif
-
-void bcm4325_sleep(unsigned long bSleep)
-{
- DBG("*** bt sleep: %d ***\n", bSleep);
-#ifdef CONFIG_BT_AUTOSLEEP
- del_timer(&bt_sleep_tl);// cmy: È·±£ÔÚ»½ÐÑBTʱ£¬²»»áÒò´¥·¢bt_sleep_tl¶øÂíÉÏ˯Ãß
-#endif
-
- IOMUX_BT_GPIO_WAKE_UP();
- gpio_set_value(BT_GPIO_WAKE_UP, bSleep?GPIO_LOW:GPIO_HIGH);
-
-#ifdef CONFIG_BT_AUTOSLEEP
- if(!bSleep)
- mod_timer(&bt_sleep_tl, jiffies + BT_AUTO_SLEEP_TIMEOUT*HZ);//ÔÙÖØÐÂÉèÖó¬Ê±Öµ¡£
-#endif
-}
-
-static int bcm4329_set_block(void *data, bool blocked)
-{
- DBG("set blocked :%d\n", blocked);
-
- IOMUX_BT_GPIO_POWER();
- IOMUX_BT_GPIO_RESET();
-
- if (false == blocked) {
- gpio_set_value(BT_GPIO_POWER, GPIO_HIGH); /* bt power on */
- mdelay(20);
-
- gpio_set_value(BT_GPIO_RESET, GPIO_LOW);
- mdelay(20);
- gpio_set_value(BT_GPIO_RESET, GPIO_HIGH); /* bt reset deactive*/
-
- mdelay(20);
- bcm4325_sleep(0); // ensure bt is wakeup
-
- pr_info("bt turn on power\n");
- } else {
-#if WIFI_BT_POWER_TOGGLE
- if (!rk29sdk_wifi_power_state) {
-#endif
- gpio_set_value(BT_GPIO_POWER, GPIO_LOW); /* bt power off */
- mdelay(20);
- pr_info("bt shut off power\n");
-#if WIFI_BT_POWER_TOGGLE
- }else {
- pr_info("bt shouldn't shut off power, wifi is using it!\n");
- }
-#endif
-
- gpio_set_value(BT_GPIO_RESET, GPIO_LOW); /* bt reset active*/
- mdelay(20);
- }
-
-#if WIFI_BT_POWER_TOGGLE
- rk29sdk_bt_power_state = !blocked;
-#endif
- return 0;
-}
-
-static const struct rfkill_ops bcm4329_rfk_ops = {
- .set_block = bcm4329_set_block,
-};
-
-static int __devinit bcm4329_rfkill_probe(struct platform_device *pdev)
-{
- int rc = 0;
- bool default_state = true;
-
- DBG("Enter %s\n",__FUNCTION__);
-
- /* default to bluetooth off */
- bcm4329_set_block(NULL, default_state); /* blocked -> bt off */
-
- gBtCtrl.bt_rfk = rfkill_alloc(bt_name,
- NULL,
- RFKILL_TYPE_BLUETOOTH,
- &bcm4329_rfk_ops,
- NULL);
-
- if (!gBtCtrl.bt_rfk)
- {
- LOG("fail to rfkill_allocate\n");
- return -ENOMEM;
- }
-
- rfkill_set_states(gBtCtrl.bt_rfk, default_state, false);
-
- rc = rfkill_register(gBtCtrl.bt_rfk);
- if (rc)
- {
- LOG("failed to rfkill_register,rc=0x%x\n",rc);
- rfkill_destroy(gBtCtrl.bt_rfk);
- }
-
- gpio_request(BT_GPIO_POWER, NULL);
- gpio_request(BT_GPIO_RESET, NULL);
- gpio_request(BT_GPIO_WAKE_UP, NULL);
-
-#ifdef CONFIG_BT_AUTOSLEEP
- init_timer(&bt_sleep_tl);
- bt_sleep_tl.expires = 0;
- bt_sleep_tl.function = bcm4325_sleep;
- bt_sleep_tl.data = 1;
- add_timer(&bt_sleep_tl);
-#endif
-
-#if BT_WAKE_HOST_SUPPORT
- init_timer(&(gBtCtrl.tl));
- gBtCtrl.tl.expires = 0;
- gBtCtrl.tl.function = timer_hostSleep;
- add_timer(&(gBtCtrl.tl));
- gBtCtrl.b_HostWake = false;
-
- wake_lock_init(&(gBtCtrl.bt_wakelock), WAKE_LOCK_SUSPEND, "bt_wake");
-
- rc = gpio_request(BT_GPIO_WAKE_UP_HOST, "bt_wake");
- if (rc) {
- LOG("Failed to request BT_WAKE_UP_HOST\n");
- }
-
- IOMUX_BT_GPIO_WAKE_UP_HOST();
- gpio_pull_updown(BT_GPIO_WAKE_UP_HOST,GPIOPullUp);
- #endif
-
- LOG("bcm4329 module has been initialized,rc=0x%x\n",rc);
-
- return rc;
-}
-
-
-static int __devexit bcm4329_rfkill_remove(struct platform_device *pdev)
-{
- if (gBtCtrl.bt_rfk)
- rfkill_unregister(gBtCtrl.bt_rfk);
- gBtCtrl.bt_rfk = NULL;
-#if BT_WAKE_HOST_SUPPORT
- del_timer(&(gBtCtrl.tl));//ɾµô¶¨Ê±Æ÷
- btWakeupHostUnlock();
- wake_lock_destroy(&(gBtCtrl.bt_wakelock));
-#endif
-#ifdef CONFIG_BT_AUTOSLEEP
- del_timer(&bt_sleep_tl);
-#endif
-
- platform_set_drvdata(pdev, NULL);
-
- DBG("Enter %s\n",__FUNCTION__);
- return 0;
-}
-
-static struct platform_driver bcm4329_rfkill_driver = {
- .probe = bcm4329_rfkill_probe,
- .remove = __devexit_p(bcm4329_rfkill_remove),
- .driver = {
- .name = "rk29sdk_rfkill",
- .owner = THIS_MODULE,
- },
- .suspend = bcm4329_rfkill_suspend,
- .resume = bcm4329_rfkill_resume,
-};
-
-/*
- * Module initialization
- */
-static int __init bcm4329_mod_init(void)
-{
- int ret;
- DBG("Enter %s\n",__FUNCTION__);
- ret = platform_driver_register(&bcm4329_rfkill_driver);
- LOG("ret=0x%x\n", ret);
- return ret;
-}
-
-static void __exit bcm4329_mod_exit(void)
-{
- platform_driver_unregister(&bcm4329_rfkill_driver);
-}
-
-module_init(bcm4329_mod_init);
-module_exit(bcm4329_mod_exit);
-MODULE_DESCRIPTION("bcm4329 Bluetooth driver");
-MODULE_AUTHOR("roger_chen cz@rock-chips.com, cmy@rock-chips.com");
-MODULE_LICENSE("GPL");
-
+++ /dev/null
-/* arch/arm/mach-rk30/board-rk30-sdk-sdmmc.c
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * *
- * History:
- * ver1.0 add combo-wifi operateions. such as commit e049351a09c78db8a08aa5c49ce8eba0a3d6824e, at 2012-09-16
- * ver2.0 Unify all the file versions of board_xxxx_sdmmc.c, at 2012-11-05
- * ver3.0 Unify the interface functions of new-iomux-API due to the modify in IOMUX module, at 2013-01-17
- *
- * Content:
- * Part 1: define the gpio for SD-MMC-SDIO-Wifi functions according to your own projects.
- ***********************************************************************************
- * Please set the value according to your own project.
- ***********************************************************************************
- *
- * Part 2: define the gpio for the SDMMC controller. Based on the chip datasheet.
- ***********************************************************************************
- * Please do not change, each platform has a fixed set. !!!!!!!!!!!!!!!!!!
- * The system personnel will set the value depending on the specific arch datasheet,
- * such as RK29XX, RK30XX.
- * If you have any doubt, please consult BangWang Xie.
- ***********************************************************************************
- *
- *.Part 3: The various operations of the SDMMC-SDIO module
- ***********************************************************************************
- * Please do not change, each platform has a fixed set. !!!!!!!!!!!!!!!!!!
- * define the varaious operations for SDMMC module
- * Generally only the author of SDMMC module will modify this section.
- * If you have any doubt, please consult BangWang Xie.
- ***********************************************************************************
- *
- *.Part 4: The various operations of the Wifi-BT module
- ***********************************************************************************
- * Please do not change, each module has a fixed set. !!!!!!!!!!!!!!!!!!
- * define the varaious operations for Wifi module
- * Generally only the author of Wifi module will modify this section.
- * If you have any doubt, please consult BangWang Xie, Weiguo Hu, and Weilong Gao.
- ***********************************************************************************
- *
- */
-//use the new iomux-API
-#if defined(CONFIG_ARCH_RK3066B)||defined(CONFIG_ARCH_RK3168)||defined(CONFIG_ARCH_RK3188)
-#define SDMMC_USE_NEW_IOMUX_API 1
-#else
-#define SDMMC_USE_NEW_IOMUX_API 0
-#endif
-
-//1.Part 1: define the gpio for SD-MMC-SDIO-Wifi functions according to your own projects.
-
-/*************************************************************************
-* define the gpio for sd-sdio-wifi module
-*************************************************************************/
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
-#define SDMMC0_WRITE_PROTECT_PIN RK30_PIN3_PB2 //According to your own project to set the value of write-protect-pin.
-#define SDMMC0_WRITE_PROTECT_ENABLE_VALUE GPIO_HIGH
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
-#define SDMMC1_WRITE_PROTECT_PIN RK30_PIN3_PB3 //According to your own project to set the value of write-protect-pin.
-#define SDMMC1_WRITE_PROTECT_ENABLE_VALUE GPIO_HIGH
-#endif
-
-#if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
-#define RK29SDK_WIFI_SDIO_CARD_INT RK30_PIN3_PD2
-#endif
-
-//define the card-detect-pin.
-#if defined(CONFIG_ARCH_RK29)
-//refer to file /arch/arm/mach-rk29/include/mach/Iomux.h
-//define reset-pin
-#define RK29SDK_SD_CARD_DETECT_N RK29_PIN2_PA2 //According to your own project to set the value of card-detect-pin.
-#define RK29SDK_SD_CARD_INSERT_LEVEL GPIO_LOW // set the voltage of insert-card. Please pay attention to the default setting.
-#define RK29SDK_SD_CARD_DETECT_PIN_NAME GPIO2A2_SDMMC0DETECTN_NAME
-#define RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO GPIO2L_GPIO2A2
-#define RK29SDK_SD_CARD_DETECT_IOMUX_FMUX GPIO2L_SDMMC0_DETECT_N
-
-#elif defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
-//refer to file /arch/arm/mach-rk30/include/mach/iomux-rk3066b.h
-//define reset-pin
-#define RK29SDK_SD_CARD_DETECT_N RK30_PIN3_PB0 //According to your own project to set the value of card-detect-pin.
-#define RK29SDK_SD_CARD_INSERT_LEVEL GPIO_LOW // set the voltage of insert-card. Please pay attention to the default setting.
-#define RK29SDK_SD_CARD_DETECT_PIN_NAME "mmc0_detn"
-#define RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO GPIO3_B0
-#define RK29SDK_SD_CARD_DETECT_IOMUX_FMUX MMC0_DETN
-
-
-#elif defined(CONFIG_ARCH_RK2928)
-//refer to file ./arch/arm/mach-rk2928/include/mach/iomux.h
-//define reset-pin
- #if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- //use gpio-interupt to dectec card in RK2926. Please pay attention to modify the default setting.
- #define RK29SDK_SD_CARD_DETECT_N RK2928_PIN2_PA7 //According to your own project to set the value of card-detect-pin.
- #define RK29SDK_SD_CARD_INSERT_LEVEL GPIO_LOW // set the voltage of insert-card. Please pay attention to the default setting.
- #define RK29SDK_SD_CARD_DETECT_PIN_NAME GPIO2A7_NAND_DPS_EMMC_CLKOUT_NAME
- #define RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO GPIO2A_GPIO2A7
- #define RK29SDK_SD_CARD_DETECT_IOMUX_FMUX GPIO2A_EMMC_CLKOUT
- #else
- #define RK29SDK_SD_CARD_DETECT_N RK2928_PIN1_PC1 //According to your own project to set the value of card-detect-pin.
- #define RK29SDK_SD_CARD_INSERT_LEVEL GPIO_LOW // set the voltage of insert-card. Please pay attention to the default setting.
- #define RK29SDK_SD_CARD_DETECT_PIN_NAME GPIO1C1_MMC0_DETN_NAME
- #define RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO GPIO1C_GPIO1C1
- #define RK29SDK_SD_CARD_DETECT_IOMUX_FMUX GPIO1C_MMC0_DETN
- #endif
-
-#else //default for RK30,RK3066 SDK
-//refer to file /arch/arm/mach-rk30/include/mach/Iomux.h
-//define reset-pin
-#define RK29SDK_SD_CARD_DETECT_N RK30_PIN3_PB6 //According to your own project to set the value of card-detect-pin.
-#define RK29SDK_SD_CARD_INSERT_LEVEL GPIO_LOW // set the voltage of insert-card. Please pay attention to the default setting.
-#define RK29SDK_SD_CARD_DETECT_PIN_NAME GPIO3B6_SDMMC0DETECTN_NAME
-#define RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO GPIO3B_GPIO3B6
-#define RK29SDK_SD_CARD_DETECT_IOMUX_FMUX GPIO3B_SDMMC0_DETECT_N
-
-#endif
-
-
-//
-// Define wifi module's power and reset gpio, and gpio sensitive level.
-// Please set the value according to your own project.
-//
-
-#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)//refer to file /arch/arm/mach-rk30/include/mach/iomux-rk3066b.h
-
- #if defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU) || defined(CONFIG_RTL8723AU)
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_LOW//GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_POWER_PIN_NAME "wifi_power"
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO3_D0
-
- #elif defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319) || defined(CONFIG_RKWIFI) || defined(CONFIG_RTL8189ES)
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_POWER_PIN_NAME "wifi_power"
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO3_D0
-
- //wake up host gpio
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN2_PA7
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_RESET_PIN_NAME "wifi_reset"
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FGPIO GPIO2_A7
-
- #elif defined(CONFIG_MT5931_MT6622) || defined(CONFIG_MT5931)
-
- #ifdef CONFIG_MACH_RK3168_LR097
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_POWER_PIN_NAME "wifi_power"
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO3_D0
-
- //#define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- //#define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- //#define RK30SDK_WIFI_GPIO_RESET_PIN_NAME "wifi_reset"
- //#define RK30SDK_WIFI_GPIO_RESET_IOMUX_FGPIO GPIO3_D1
-
- #else
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN0_PA5
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- //#define RK30SDK_WIFI_GPIO_POWER_PIN_NAME "wifi_power"
- //#define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO3_D0
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_RESET_PIN_NAME "wifi_reset"
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FGPIO GPIO3_D1
- #endif
-
- #endif
-#elif defined(CONFIG_ARCH_RK2928) //refer to file ./arch/arm/mach-rk2928/include/mach/iomux.h
-
- #if defined(CONFIG_RKWIFI) || defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319) || defined(CONFIG_RTL8189ES)
- #define RK30SDK_WIFI_GPIO_POWER_N RK2928_PIN0_PD6
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_POWER_PIN_NAME GPIO0D6_MMC1_PWREN_NAME
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO0D_GPIO0D6
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK2928_PIN3_PC2
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- //wake up host gpio
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B RK2928_PIN3_PC0
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
- //You need not define the pin-iomux-name due to the pin only used gpio.
- //#define RK30SDK_WIFI_GPIO_RESET_PIN_NAME GPIO3C2_SDMMC1DATA1_NAME
- //#define RK30SDK_WIFI_GPIO_RESET_IOMUX_FGPIO GPIO3C_GPIO3C2
-
- #elif defined(CONFIG_RDA5990)
- #define RK30SDK_WIFI_GPIO_POWER_N INVALID_GPIO//RK2928_PIN0_PD6
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- //#define RK30SDK_WIFI_GPIO_POWER_PIN_NAME GPIO0B6_MMC1_PWREN_NAME
- //#define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO0B_GPIO0B6
-
- #define RK30SDK_WIFI_GPIO_RESET_N INVALID_GPIO//RK2928_PIN3_PC2
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- //#define RK30SDK_WIFI_GPIO_RESET_PIN_NAME GPIO3C2_SDMMC1DATA1_NAME
- //#define RK30SDK_WIFI_GPIO_RESET_IOMUX_FGPIO GPIO3C_GPIO3C2
-
-
- #elif defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU) || defined(CONFIG_RTL8723AU)
- #define RK30SDK_WIFI_GPIO_POWER_N RK2928_PIN0_PD6
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_LOW
- #define RK30SDK_WIFI_GPIO_POWER_PIN_NAME GPIO0D6_MMC1_PWREN_NAME
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO0D_GPIO0D6
-
- #endif
-
-#else //default for RK30,RK3066 SDK
- // refer to file /arch/arm/mach-rk30/include/mach/Iomux.h
-
- #if defined(CONFIG_RKWIFI) || defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU) || defined(CONFIG_RTL8723AU) \
- || defined(CONFIG_RTL8189ES)
- //power
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- //reset
- #define RK30SDK_WIFI_GPIO_POWER_PIN_NAME GPIO3D0_SDMMC1PWREN_NAME
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO3D_GPIO3D0
- //wake up host gpio
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
-
- #elif defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319)
- //power
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_POWER_PIN_NAME GPIO3D0_SDMMC1PWREN_NAME
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO3D_GPIO3D0
- //reset
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_RESET_PIN_NAME GPIO3D1_SDMMC1BACKENDPWR_NAME
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FGPIO GPIO3D_GPIO3D1
-
- #elif defined(CONFIG_MT5931) || defined(CONFIG_MT5931_MT6622)
- //power
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PC6 //RK30_PIN3_PD0 // huweiguo
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- //reset
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1 // huweiguo
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
-
- #elif defined(CONFIG_MT6620)
- #if !defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- #define USE_SDMMC_CONTROLLER_FOR_WIFI 1
-
- #if defined(CONFIG_MACH_RK30_PHONE_PAD) // define the gpio for MT6620 in RK30_PHONE_PAD project.
- #define COMBO_MODULE_MT6620_CDT 0 //- 1--use Cdtech chip; 0--unuse CDT chip
- //power, PMU_EN
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PC7
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_POWER_PIN_NAME GPIO3C7_SDMMC1WRITEPRT_NAME
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO3C_GPIO3C7
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FMUX GPIO3C_SDMMC1_WRITE_PRT
- //reset, DAIRST,SYSRST_B
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_RESET_PIN_NAME GPIO3D1_SDMMC1BACKENDPWR_NAME
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FGPIO GPIO3D_GPIO3D1
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FMUX GPIO3D_SDMMC1_BACKEND_PWR
- //VDDIO
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL RK30_PIN6_PB4
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_ENABLE_VALUE GPIO_HIGH
- //WIFI_INT_B
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN4_PD2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_PIN_NAME GPIO4D2_SMCDATA10_TRACEDATA10_NAME
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FGPIO GPIO4D_GPIO4D2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FMUX GPIO4D_SMC_DATA10
- //BGF_INT_B
- #define RK30SDK_WIFI_GPIO_BGF_INT_B RK30_PIN6_PA7
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_ENABLE_VALUE GPIO_HIGH
- //#define RK30SDK_WIFI_GPIO_BGF_INT_B_PIN_NAME GPIO3C6_SDMMC1DETECTN_NAME
- //#define RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FGPIO GPIO3C_GPIO3C6
- //#define RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FMUX GPIO3C_SDMMC1_DETECT_N
- //GPS_SYNC
- #define RK30SDK_WIFI_GPIO_GPS_SYNC RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_PIN_NAME GPIO3D0_SDMMC1PWREN_NAME
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FGPIO GPIO3D_GPIO3D0
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FMUX GPIO3D_SDMMC1_PWR_EN
-
- #elif defined(CONFIG_MACH_RK3066_M8000R) // define the gpio for MT6620 in CONFIG_MACH_RK3066_M8000R project.
- #define COMBO_MODULE_MT6620_CDT 1 //- 1--use Cdtech chip; 0--unuse CDT chip
- //power, PMU_EN
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PC7
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_POWER_PIN_NAME GPIO3C7_SDMMC1WRITEPRT_NAME
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO3C_GPIO3C7
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FMUX GPIO3C_SDMMC1_WRITE_PRT
- //reset, DAIRST,SYSRST_B
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_RESET_PIN_NAME GPIO3D1_SDMMC1BACKENDPWR_NAME
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FGPIO GPIO3D_GPIO3D1
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FMUX GPIO3D_SDMMC1_BACKEND_PWR
- //VDDIO
- #define RK30SDK_WIFI_GPIO_VCCIO_WL RK30_PIN0_PD2
- #define RK30SDK_WIFI_GPIO_VCCIO_WL_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_VCCIO_WL_PIN_NAME GPIO0D2_I2S22CHLRCKRX_SMCOEN_NAME
- #define RK30SDK_WIFI_GPIO_VCCIO_WL_IOMUX_FGPIO GPIO0D_GPIO0D2
- #define RK30SDK_WIFI_GPIO_VCCIO_WL_IOMUX_FMUX GPIO0D_I2S2_2CH_LRCK_RX
- //WIFI_INT_B
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_PIN_NAME GPIO3D2_SDMMC1INTN_NAME
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FGPIO GPIO3D_GPIO3D2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FMUX GPIO3D_SDMMC1_INT_N
- //BGF_INT_B
- #define RK30SDK_WIFI_GPIO_BGF_INT_B RK30_PIN6_PA7
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_ENABLE_VALUE GPIO_HIGH
- //#define RK30SDK_WIFI_GPIO_BGF_INT_B_PIN_NAME GPIO3C6_SDMMC1DETECTN_NAME
- //#define RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FGPIO GPIO3C_GPIO3C6
- // #define RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FMUX GPIO3C_SDMMC1_DETECT_N
- //GPS_SYNC
- #define RK30SDK_WIFI_GPIO_GPS_SYNC RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_PIN_NAME GPIO3D0_SDMMC1PWREN_NAME
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FGPIO GPIO3D_GPIO3D0
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FMUX GPIO3D_SDMMC1_PWR_EN
-
- #if COMBO_MODULE_MT6620_CDT
- //ANTSEL2
- //#define RK30SDK_WIFI_GPIO_ANTSEL2 RK30_PIN4_PD4
- //#define RK30SDK_WIFI_GPIO_ANTSEL2_ENABLE_VALUE GPIO_LOW //use 6620 in CDT chip, LOW--work; High--no work.
- //#define RK30SDK_WIFI_GPIO_ANTSEL2_PIN_NAME GPIO4D4_SMCDATA12_TRACEDATA12_NAME
- //#define RK30SDK_WIFI_GPIO_ANTSEL2_IOMUX_FGPIO GPIO4D_GPIO4D4
- //#define RK30SDK_WIFI_GPIO_ANTSEL2_IOMUX_FMUX GPIO4D_TRACE_DATA12
- //ANTSEL3
- //#define RK30SDK_WIFI_GPIO_ANTSEL3 RK30_PIN4_PD3
- //#define RK30SDK_WIFI_GPIO_ANTSEL3_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- //#define RK30SDK_WIFI_GPIO_ANTSEL3_PIN_NAME GPIO4D3_SMCDATA11_TRACEDATA11_NAME
- //#define RK30SDK_WIFI_GPIO_ANTSEL3_IOMUX_FGPIO GPIO4D_GPIO4D3
- //#define RK30SDK_WIFI_GPIO_ANTSEL3_IOMUX_FMUX GPIO4D_TRACE_DATA11
- //GPS_LAN
- //#define RK30SDK_WIFI_GPIO_GPS_LAN RK30_PIN4_PD6
- //#define RK30SDK_WIFI_GPIO_GPS_LAN_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- //#define RK30SDK_WIFI_GPIO_GPS_LAN_PIN_NAME GPIO4D6_SMCDATA14_TRACEDATA14_NAME
- //#define RK30SDK_WIFI_GPIO_GPS_LAN_IOMUX_FGPIO GPIO4D_GPIO4D6
- //#define RK30SDK_WIFI_GPIO_GPS_LAN_IOMUX_FMUX GPIO4D_TRACE_DATA14
- #endif // #if COMBO_MODULE_MT6620_CDT--#endif
-
- #elif defined(CONFIG_MACH_SKYWORTH_T10_SDK) // define the gpio for MT6620 in KYWORTH_T10 project.
- #define COMBO_MODULE_MT6620_CDT 0 //- 1--use Cdtech chip; 0--unuse CDT chip
- //power, PMU_EN
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_POWER_PIN_NAME GPIO3D0_SDMMC1PWREN_NAME
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO3D_GPIO3D0
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FMUX GPIO3D_SDMMC1_PWR_EN
- //reset, DAIRST,SYSRST_B
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_RESET_PIN_NAME GPIO3D1_SDMMC1BACKENDPWR_NAME
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FGPIO GPIO3D_GPIO3D1
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FMUX GPIO3D_SDMMC1_BACKEND_PWR
- //VDDIO
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL RK30_PIN6_PB4
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_ENABLE_VALUE GPIO_HIGH
- //WIFI_INT_B
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_PIN_NAME GPIO3D2_SDMMC1INTN_NAME
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FGPIO GPIO3D_GPIO3D2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FMUX GPIO3D_SDMMC1_INT_N
- //BGF_INT_B
- #define RK30SDK_WIFI_GPIO_BGF_INT_B RK30_PIN3_PC6
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_PIN_NAME GPIO3C6_SDMMC1DETECTN_NAME
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FGPIO GPIO3C_GPIO3C6
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FMUX GPIO3C_SDMMC1_DETECT_N
- //GPS_SYNC
- #define RK30SDK_WIFI_GPIO_GPS_SYNC RK30_PIN3_PC7
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_PIN_NAME GPIO3C7_SDMMC1WRITEPRT_NAME
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FGPIO GPIO3C_GPIO3C7
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FMUX GPIO3C_SDMMC1_WRITE_PRT
-
- #else //For exmpale, to define the gpio for MT6620 in RK30SDK project.
- #define COMBO_MODULE_MT6620_CDT 1 //- 1--use Cdtech chip; 0--unuse CDT chip
- //power
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_POWER_PIN_NAME GPIO3D0_SDMMC1PWREN_NAME
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO3D_GPIO3D0
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FMUX GPIO3D_SDMMC1_PWR_EN
- //reset
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_RESET_PIN_NAME GPIO3D1_SDMMC1BACKENDPWR_NAME
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FGPIO GPIO3D_GPIO3D1
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FMUX GPIO3D_SDMMC1_BACKEND_PWR
- //VDDIO
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL RK30_PIN0_PD2
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_ENABLE_VALUE GPIO_HIGH
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_PIN_NAME GPIO0D2_I2S22CHLRCKRX_SMCOEN_NAME
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_IOMUX_FGPIO GPIO0D_GPIO0D2
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_IOMUX_FMUX GPIO0D_I2S2_2CH_LRCK_RX
- //WIFI_INT_B
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_PIN_NAME GPIO3D2_SDMMC1INTN_NAME
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FGPIO GPIO3D_GPIO3D2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FMUX GPIO3D_SDMMC1_INT_N
- //BGF_INT_B
- #define RK30SDK_WIFI_GPIO_BGF_INT_B RK30_PIN3_PC6
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_PIN_NAME GPIO3C6_SDMMC1DETECTN_NAME
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FGPIO GPIO3C_GPIO3C6
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FMUX GPIO3C_SDMMC1_DETECT_N
- //GPS_SYNC
- #define RK30SDK_WIFI_GPIO_GPS_SYNC RK30_PIN3_PC7
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_PIN_NAME GPIO3C7_SDMMC1WRITEPRT_NAME
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FGPIO GPIO3C_GPIO3C7
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FMUX GPIO3C_SDMMC1_WRITE_PRT
-
- #if COMBO_MODULE_MT6620_CDT
- //ANTSEL2
- #define RK30SDK_WIFI_GPIO_ANTSEL2 RK30_PIN4_PD4
- #define RK30SDK_WIFI_GPIO_ANTSEL2_ENABLE_VALUE GPIO_LOW //use 6620 in CDT chip, LOW--work; High--no work.
- #define RK30SDK_WIFI_GPIO_ANTSEL2_PIN_NAME GPIO4D4_SMCDATA12_TRACEDATA12_NAME
- #define RK30SDK_WIFI_GPIO_ANTSEL2_IOMUX_FGPIO GPIO4D_GPIO4D4
- #define RK30SDK_WIFI_GPIO_ANTSEL2_IOMUX_FMUX GPIO4D_TRACE_DATA12
- //ANTSEL3
- #define RK30SDK_WIFI_GPIO_ANTSEL3 RK30_PIN4_PD3
- #define RK30SDK_WIFI_GPIO_ANTSEL3_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- #define RK30SDK_WIFI_GPIO_ANTSEL3_PIN_NAME GPIO4D3_SMCDATA11_TRACEDATA11_NAME
- #define RK30SDK_WIFI_GPIO_ANTSEL3_IOMUX_FGPIO GPIO4D_GPIO4D3
- #define RK30SDK_WIFI_GPIO_ANTSEL3_IOMUX_FMUX GPIO4D_TRACE_DATA11
- //GPS_LAN
- #define RK30SDK_WIFI_GPIO_GPS_LAN RK30_PIN4_PD6
- #define RK30SDK_WIFI_GPIO_GPS_LAN_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- #define RK30SDK_WIFI_GPIO_GPS_LAN_PIN_NAME GPIO4D6_SMCDATA14_TRACEDATA14_NAME
- #define RK30SDK_WIFI_GPIO_GPS_LAN_IOMUX_FGPIO GPIO4D_GPIO4D6
- //#define RK30SDK_WIFI_GPIO_GPS_LAN_IOMUX_FMUX GPIO4D_TRACE_DATA14
- #endif // #if COMBO_MODULE_MT6620_CDT--#endif
- #endif
- #endif// #endif --#if !defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- #endif
-#endif
-
-
-//1. Part 2: to define the gpio for the SDMMC controller. Based on the chip datasheet.
-/*************************************************************************
-* define the gpio for SDMMC module on various platforms
-* Generally only system personnel will modify this part
-*************************************************************************/
-#if defined(CONFIG_ARCH_RK29)
-//refer to file /arch/arm/mach-rk29/include/mach/Iomux.h
-//define PowerEn-pin
-#define RK29SDK_SD_CARD_PWR_EN RK29_PIN5_PD5
-#define RK29SDK_SD_CARD_PWR_EN_LEVEL GPIO_LOW
-#define RK29SDK_SD_CARD_PWR_EN_PIN_NAME GPIO5D5_SDMMC0PWREN_NAME
-#define RK29SDK_SD_CARD_PWR_EN_IOMUX_FGPIO GPIO5H_GPIO5D5
-#define RK29SDK_SD_CARD_PWR_EN_IOMUX_FMUX GPIO5H_SDMMC0_PWR_EN
-
-#elif defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
-//refer to file /arch/arm/mach-rk30/include/mach/iomux-rk3066b.h
-//define PowerEn-pin
-#define RK29SDK_SD_CARD_PWR_EN RK30_PIN3_PA1
-#define RK29SDK_SD_CARD_PWR_EN_LEVEL GPIO_LOW
-#define RK29SDK_SD_CARD_PWR_EN_PIN_NAME "mmc0_pwren"
-#define RK29SDK_SD_CARD_PWR_EN_IOMUX_FGPIO GPIO3_A1
-#define RK29SDK_SD_CARD_PWR_EN_IOMUX_FMUX MMC0_PWREN
-
-#elif defined(CONFIG_ARCH_RK2928)
-//refer to file ./arch/arm/mach-rk2928/include/mach/iomux.h
-//define PowerEn-pin
-#define RK29SDK_SD_CARD_PWR_EN RK2928_PIN1_PB6
-#define RK29SDK_SD_CARD_PWR_EN_LEVEL GPIO_LOW
-#define RK29SDK_SD_CARD_PWR_EN_PIN_NAME GPIO1B6_MMC0_PWREN_NAME
-#define RK29SDK_SD_CARD_PWR_EN_IOMUX_FGPIO GPIO1B_GPIO1B6
-#define RK29SDK_SD_CARD_PWR_EN_IOMUX_FMUX GPIO1B_MMC0_PWREN
-
-#else //defaul for RK30,RK3066 SDK
-//refer to file /arch/arm/mach-rk30/include/mach/Iomux.h
-//define PowerEn-pin
-#define RK29SDK_SD_CARD_PWR_EN RK30_PIN3_PA7
-#define RK29SDK_SD_CARD_PWR_EN_LEVEL GPIO_LOW
-#define RK29SDK_SD_CARD_PWR_EN_PIN_NAME GPIO3A7_SDMMC0PWREN_NAME
-#define RK29SDK_SD_CARD_PWR_EN_IOMUX_FGPIO GPIO3A_GPIO3A7
-#define RK29SDK_SD_CARD_PWR_EN_IOMUX_FMUX GPIO3A_SDMMC0_PWR_EN
-
-#endif
-
-
-#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
-/*
-* define the gpio for sdmmc0
-*/
-static struct rksdmmc_gpio_board rksdmmc0_gpio_init = {
-
- .clk_gpio = {
- .io = RK30_PIN3_PA2,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mmc0_clkout",
- .fgpio = GPIO3_A2,
- .fmux = MMC0_CLKOUT,
- },
- },
-
- .cmd_gpio = {
- .io = RK30_PIN3_PA3,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mmc0_cmd",
- .fgpio = GPIO3_A3,
- .fmux = MMC0_CMD,
- },
- },
-
- .data0_gpio = {
- .io = RK30_PIN3_PA4,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mmc0_d0",
- .fgpio = GPIO3_A4,
- .fmux = MMC0_D0,
- },
- },
-
- .data1_gpio = {
- .io = RK30_PIN3_PA5,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mmc0_d1",
- .fgpio = GPIO3_A5,
- .fmux = MMC0_D1,
- },
- },
-
- .data2_gpio = {
- .io = RK30_PIN3_PA6,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mmc0_d2",
- .fgpio = GPIO3_A6,
- .fmux = MMC0_D2,
- },
- },
-
- .data3_gpio = {
- .io = RK30_PIN3_PA7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mmc0_d3",
- .fgpio = GPIO3_A7,
- .fmux = MMC0_D3,
- },
- },
-
-
- .power_en_gpio = {
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .io = RK29SDK_SD_CARD_PWR_EN,
- .enable = RK29SDK_SD_CARD_PWR_EN_LEVEL,
- #ifdef RK29SDK_SD_CARD_PWR_EN_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_PWR_EN_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_PWR_EN_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_PWR_EN_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_PWR_EN_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_PWR_EN_IOMUX_FMUX,
- #endif
- },
- #endif
-#else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-
- .detect_irq = {
-#if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
-#else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-
-};
-
-
-/*
-* define the gpio for sdmmc1
-*/
-static struct rksdmmc_gpio_board rksdmmc1_gpio_init = {
-
- .clk_gpio = {
- .io = RK30_PIN3_PC5,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mmc1_clkout",
- .fgpio = GPIO3_C5,
- .fmux = MMC1_CLKOUT,
- },
- },
-
- .cmd_gpio = {
- .io = RK30_PIN3_PC0,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mmc1_cmd",
- .fgpio = GPIO3_C0,
- .fmux = MMC1_CMD,
- },
- },
-
- .data0_gpio = {
- .io = RK30_PIN3_PC1,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mmc1_d0",
- .fgpio = GPIO3_C1,
- .fmux = MMC1_D0,
- },
- },
-
- .data1_gpio = {
- .io = RK30_PIN3_PC2,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mmc1_d1",
- .fgpio = GPIO3_C2,
- .fmux = MMC1_D1,
- },
- },
-
- .data2_gpio = {
- .io = RK30_PIN3_PC3,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mmc1_d2",
- .fgpio = GPIO3_C3,
- .fmux = MMC1_D2,
- },
- },
-
- .data3_gpio = {
- .io = RK30_PIN3_PC4,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mmc1_d3",
- .fgpio = GPIO3_C4,
- .fmux = MMC1_D3,
- },
- },
-};
-// ---end -#if defined(CONFIG_ARCH_RK3066B)
-
-#elif defined(CONFIG_ARCH_RK2928)
-/*
-* define the gpio for sdmmc0
-*/
-static struct rksdmmc_gpio_board rksdmmc0_gpio_init = {
-
- .clk_gpio = {
- .io = RK2928_PIN1_PC0,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO1C0_MMC0_CLKOUT_NAME,
- .fgpio = GPIO1C_GPIO1C0,
- .fmux = GPIO1C_MMC0_CLKOUT,
- },
- },
-
- .cmd_gpio = {
- .io = RK2928_PIN1_PC7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO1B7_MMC0_CMD_NAME,
- .fgpio = GPIO1B_GPIO1B7,
- .fmux = GPIO1B_MMC0_CMD,
- },
- },
-
- .data0_gpio = {
- .io = RK2928_PIN1_PC2,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO1C2_MMC0_D0_NAME,
- .fgpio = GPIO1C_GPIO1C2,
- .fmux = GPIO1C_MMC0_D0,
- },
- },
-
- .data1_gpio = {
- .io = RK2928_PIN1_PC3,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO1C3_MMC0_D1_NAME,
- .fgpio = GPIO1C_GPIO1C3,
- .fmux = GPIO1C_MMC0_D1,
- },
- },
-
- .data2_gpio = {
- .io = RK2928_PIN1_PC4,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO1C4_MMC0_D2_NAME,
- .fgpio = GPIO1C_GPIO1C4,
- .fmux = GPIO1C_MMC0_D2,
- },
- },
-
- .data3_gpio = {
- .io = RK2928_PIN1_PC5,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO1C5_MMC0_D3_NAME,
- .fgpio = GPIO1C_GPIO1C5,
- .fmux = GPIO1C_MMC0_D3,
- },
- },
-
-
- .power_en_gpio = {
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .io = RK29SDK_SD_CARD_PWR_EN,
- .enable = RK29SDK_SD_CARD_PWR_EN_LEVEL,
- #ifdef RK29SDK_SD_CARD_PWR_EN_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_PWR_EN_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_PWR_EN_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_PWR_EN_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_PWR_EN_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_PWR_EN_IOMUX_FMUX,
- #endif
- },
- #endif
-#else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-
- .detect_irq = {
-#if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
-#else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-};
-
-
-/*
-* define the gpio for sdmmc1
-*/
-static struct rksdmmc_gpio_board rksdmmc1_gpio_init = {
-
- .clk_gpio = {
- .io = RK2928_PIN0_PB1,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO0B1_MMC1_CLKOUT_NAME,
- .fgpio = GPIO0B_GPIO0B1,
- .fmux = GPIO0B_MMC1_CLKOUT,
- },
- },
-
- .cmd_gpio = {
- .io = RK2928_PIN0_PB0,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO0B0_MMC1_CMD_NAME,
- .fgpio = GPIO0B_GPIO0B0,
- .fmux = GPIO0B_MMC1_CMD,
- },
- },
-
- .data0_gpio = {
- .io = RK2928_PIN0_PB3,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO0B3_MMC1_D0_NAME,
- .fgpio = GPIO0B_GPIO0B3,
- .fmux = GPIO0B_MMC1_D0,
- },
- },
-
- .data1_gpio = {
- .io = RK2928_PIN0_PB4,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO0B4_MMC1_D1_NAME,
- .fgpio = GPIO0B_GPIO0B4,
- .fmux = GPIO0B_MMC1_D1,
- },
- },
-
- .data2_gpio = {
- .io = RK2928_PIN0_PB5,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO0B5_MMC1_D2_NAME,
- .fgpio = GPIO0B_GPIO0B5,
- .fmux = GPIO0B_MMC1_D2,
- },
- },
-
- .data3_gpio = {
- .io = RK2928_PIN0_PB6,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO0B6_MMC1_D3_NAME,
- .fgpio = GPIO0B_GPIO0B6,
- .fmux = GPIO0B_MMC1_D3,
- },
- },
-
-
-};
-// ---end -#if defined(CONFIG_ARCH_RK2928)
-
-#else //default for RK30,RK3066 SDK
-/*
-* define the gpio for sdmmc0
-*/
-struct rksdmmc_gpio_board rksdmmc0_gpio_init = {
-
- .clk_gpio = {
- .io = RK30_PIN3_PB0,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3B0_SDMMC0CLKOUT_NAME,
- .fgpio = GPIO3B_GPIO3B0,
- .fmux = GPIO3B_SDMMC0_CLKOUT,
- },
- },
-
- .cmd_gpio = {
- .io = RK30_PIN3_PB1,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3B1_SDMMC0CMD_NAME,
- .fgpio = GPIO3B_GPIO3B1,
- .fmux = GPIO3B_SDMMC0_CMD,
- },
- },
-
- .data0_gpio = {
- .io = RK30_PIN3_PB2,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3B2_SDMMC0DATA0_NAME,
- .fgpio = GPIO3B_GPIO3B2,
- .fmux = GPIO3B_SDMMC0_DATA0,
- },
- },
-
- .data1_gpio = {
- .io = RK30_PIN3_PB3,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3B3_SDMMC0DATA1_NAME,
- .fgpio = GPIO3B_GPIO3B3,
- .fmux = GPIO3B_SDMMC0_DATA1,
- },
- },
-
- .data2_gpio = {
- .io = RK30_PIN3_PB4,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3B4_SDMMC0DATA2_NAME,
- .fgpio = GPIO3B_GPIO3B4,
- .fmux = GPIO3B_SDMMC0_DATA2,
- },
- },
-
- .data3_gpio = {
- .io = RK30_PIN3_PB5,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3B5_SDMMC0DATA3_NAME,
- .fgpio = GPIO3B_GPIO3B5,
- .fmux = GPIO3B_SDMMC0_DATA3,
- },
- },
-
- .power_en_gpio = {
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .io = RK29SDK_SD_CARD_PWR_EN,
- .enable = RK29SDK_SD_CARD_PWR_EN_LEVEL,
- #ifdef RK29SDK_SD_CARD_PWR_EN_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_PWR_EN_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_PWR_EN_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_PWR_EN_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_PWR_EN_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_PWR_EN_IOMUX_FMUX,
- #endif
- },
- #endif
-#else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-
- .detect_irq = {
-#if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
-#else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-};
-
-
-/*
-* define the gpio for sdmmc1
-*/
-static struct rksdmmc_gpio_board rksdmmc1_gpio_init = {
-
- .clk_gpio = {
- .io = RK30_PIN3_PC5,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C5_SDMMC1CLKOUT_NAME,
- .fgpio = GPIO3C_GPIO3C5,
- .fmux = GPIO3B_SDMMC0_CLKOUT,
- },
- },
-
- .cmd_gpio = {
- .io = RK30_PIN3_PC0,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C0_SMMC1CMD_NAME,
- .fgpio = GPIO3C_GPIO3C0,
- .fmux = GPIO3B_SDMMC0_CMD,
- },
- },
-
- .data0_gpio = {
- .io = RK30_PIN3_PC1,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C1_SDMMC1DATA0_NAME,
- .fgpio = GPIO3C_GPIO3C1,
- .fmux = GPIO3B_SDMMC0_DATA0,
- },
- },
-
- .data1_gpio = {
- .io = RK30_PIN3_PC2,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C2_SDMMC1DATA1_NAME,
- .fgpio = GPIO3C_GPIO3C2,
- .fmux = GPIO3B_SDMMC0_DATA1,
- },
- },
-
- .data2_gpio = {
- .io = RK30_PIN3_PC3,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C3_SDMMC1DATA2_NAME,
- .fgpio = GPIO3C_GPIO3C3,
- .fmux = GPIO3B_SDMMC0_DATA2,
- },
- },
-
- .data3_gpio = {
- .io = RK30_PIN3_PC4,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C4_SDMMC1DATA3_NAME,
- .fgpio = GPIO3C_GPIO3C4,
- .fmux = GPIO3B_SDMMC0_DATA3,
- },
- },
-};
- // ---end -defualt rk30sdk,rk3066sdk
-
-#endif
-
-
-
-//1.Part 3: The various operations of the SDMMC-SDIO module
-/*************************************************************************
-* define the varaious operations for SDMMC module
-* Generally only the author of SDMMC module will modify this section.
-*************************************************************************/
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
-void rk29_sdmmc_gpio_open(int device_id, int on)
-{
- switch(device_id)
- {
- case 0://mmc0
- {
- #ifdef CONFIG_SDMMC0_RK29
- if(on)
- {
- gpio_direction_output(rksdmmc0_gpio_init.clk_gpio.io, GPIO_HIGH);//set mmc0-clk to high
- gpio_direction_output(rksdmmc0_gpio_init.cmd_gpio.io, GPIO_HIGH);// set mmc0-cmd to high.
- gpio_direction_output(rksdmmc0_gpio_init.data0_gpio.io,GPIO_HIGH);//set mmc0-data0 to high.
- gpio_direction_output(rksdmmc0_gpio_init.data1_gpio.io,GPIO_HIGH);//set mmc0-data1 to high.
- gpio_direction_output(rksdmmc0_gpio_init.data2_gpio.io,GPIO_HIGH);//set mmc0-data2 to high.
- gpio_direction_output(rksdmmc0_gpio_init.data3_gpio.io,GPIO_HIGH);//set mmc0-data3 to high.
-
- mdelay(30);
- }
- else
- {
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(rksdmmc0_gpio_init.clk_gpio.iomux.fgpio);
- #else
- rk30_mux_api_set(rksdmmc0_gpio_init.clk_gpio.iomux.name, rksdmmc0_gpio_init.clk_gpio.iomux.fgpio);
- #endif
- gpio_request(rksdmmc0_gpio_init.clk_gpio.io, "mmc0-clk");
- gpio_direction_output(rksdmmc0_gpio_init.clk_gpio.io,GPIO_LOW);//set mmc0-clk to low.
-
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(rksdmmc0_gpio_init.cmd_gpio.iomux.fgpio);
- #else
- rk30_mux_api_set(rksdmmc0_gpio_init.cmd_gpio.iomux.name, rksdmmc0_gpio_init.cmd_gpio.iomux.fgpio);
- #endif
- gpio_request(rksdmmc0_gpio_init.cmd_gpio.io, "mmc0-cmd");
- gpio_direction_output(rksdmmc0_gpio_init.cmd_gpio.io,GPIO_LOW);//set mmc0-cmd to low.
-
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(rksdmmc0_gpio_init.data0_gpio.iomux.fgpio);
- #else
- rk30_mux_api_set(rksdmmc0_gpio_init.data0_gpio.iomux.name, rksdmmc0_gpio_init.data0_gpio.iomux.fgpio);
- #endif
- gpio_request(rksdmmc0_gpio_init.data0_gpio.io, "mmc0-data0");
- gpio_direction_output(rksdmmc0_gpio_init.data0_gpio.io,GPIO_LOW);//set mmc0-data0 to low.
-
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(rksdmmc0_gpio_init.data1_gpio.iomux.fgpio);
- #else
- rk30_mux_api_set(rksdmmc0_gpio_init.data1_gpio.iomux.name, rksdmmc0_gpio_init.data1_gpio.iomux.fgpio);
- #endif
- gpio_request(rksdmmc0_gpio_init.data1_gpio.io, "mmc0-data1");
- gpio_direction_output(rksdmmc0_gpio_init.data1_gpio.io,GPIO_LOW);//set mmc0-data1 to low.
-
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(rksdmmc0_gpio_init.data2_gpio.iomux.fgpio);
- #else
- rk30_mux_api_set(rksdmmc0_gpio_init.data2_gpio.iomux.name, rksdmmc0_gpio_init.data2_gpio.iomux.fgpio);
- #endif
- gpio_request(rksdmmc0_gpio_init.data2_gpio.io, "mmc0-data2");
- gpio_direction_output(rksdmmc0_gpio_init.data2_gpio.io,GPIO_LOW);//set mmc0-data2 to low.
-
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(rksdmmc0_gpio_init.data3_gpio.iomux.fgpio);
- #else
- rk30_mux_api_set(rksdmmc0_gpio_init.data3_gpio.iomux.name, rksdmmc0_gpio_init.data3_gpio.iomux.fgpio);
- #endif
- gpio_request(rksdmmc0_gpio_init.data3_gpio.io, "mmc0-data3");
- gpio_direction_output(rksdmmc0_gpio_init.data3_gpio.io,GPIO_LOW);//set mmc0-data3 to low.
-
- mdelay(30);
- }
- #endif
- }
- break;
-
- case 1://mmc1
- {
- #ifdef CONFIG_SDMMC1_RK29
- if(on)
- {
- gpio_direction_output(rksdmmc1_gpio_init.clk_gpio.io,GPIO_HIGH);//set mmc1-clk to high
- gpio_direction_output(rksdmmc1_gpio_init.cmd_gpio.io,GPIO_HIGH);//set mmc1-cmd to high.
- gpio_direction_output(rksdmmc1_gpio_init.data0_gpio.io,GPIO_HIGH);//set mmc1-data0 to high.
- gpio_direction_output(rksdmmc1_gpio_init.data1_gpio.io,GPIO_HIGH);//set mmc1-data1 to high.
- gpio_direction_output(rksdmmc1_gpio_init.data2_gpio.io,GPIO_HIGH);//set mmc1-data2 to high.
- gpio_direction_output(rksdmmc1_gpio_init.data3_gpio.io,GPIO_HIGH);//set mmc1-data3 to high.
- mdelay(100);
- }
- else
- {
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(rksdmmc1_gpio_init.clk_gpio.iomux.fgpio);
- #else
- rk30_mux_api_set(rksdmmc1_gpio_init.clk_gpio.iomux.name, rksdmmc1_gpio_init.clk_gpio.iomux.fgpio);
- #endif
- gpio_request(rksdmmc1_gpio_init.clk_gpio.io, "mmc1-clk");
- gpio_direction_output(rksdmmc1_gpio_init.clk_gpio.io,GPIO_LOW);//set mmc1-clk to low.
-
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(rksdmmc1_gpio_init.cmd_gpio.iomux.fgpio);
- #else
- rk30_mux_api_set(rksdmmc1_gpio_init.cmd_gpio.iomux.name, rksdmmc1_gpio_init.cmd_gpio.iomux.fgpio);
- #endif
- gpio_request(rksdmmc1_gpio_init.cmd_gpio.io, "mmc1-cmd");
- gpio_direction_output(rksdmmc1_gpio_init.cmd_gpio.io,GPIO_LOW);//set mmc1-cmd to low.
-
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(rksdmmc1_gpio_init.data0_gpio.iomux.fgpio);
- #else
- rk30_mux_api_set(rksdmmc1_gpio_init.data0_gpio.iomux.name, rksdmmc1_gpio_init.data0_gpio.iomux.fgpio);
- #endif
- gpio_request(rksdmmc1_gpio_init.data0_gpio.io, "mmc1-data0");
- gpio_direction_output(rksdmmc1_gpio_init.data0_gpio.io,GPIO_LOW);//set mmc1-data0 to low.
-
- #if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) || defined(CONFIG_MT5931) || defined(CONFIG_MT5931_MT6622)
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(rksdmmc1_gpio_init.data1_gpio.iomux.fgpio);
- #else
- rk29_mux_api_set(rksdmmc1_gpio_init.data1_gpio.iomux.name, rksdmmc1_gpio_init.data1_gpio.iomux.fgpio);
- #endif
- gpio_request(rksdmmc1_gpio_init.data1_gpio.io, "mmc1-data1");
- gpio_direction_output(rksdmmc1_gpio_init.data1_gpio.io,GPIO_LOW);//set mmc1-data1 to low.
-
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(rksdmmc1_gpio_init.data2_gpio.iomux.fgpio);
- #else
- rk29_mux_api_set(rksdmmc1_gpio_init.data2_gpio.iomux.name, rksdmmc1_gpio_init.data2_gpio.iomux.fgpio);
- #endif
- gpio_request(rksdmmc1_gpio_init.data2_gpio.io, "mmc1-data2");
- gpio_direction_output(rksdmmc1_gpio_init.data2_gpio.io,GPIO_LOW);//set mmc1-data2 to low.
-
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(rksdmmc1_gpio_init.data3_gpio.iomux.fgpio);
- #else
- rk29_mux_api_set(rksdmmc1_gpio_init.data3_gpio.iomux.name, rksdmmc1_gpio_init.data3_gpio.iomux.fgpio);
- #endif
- gpio_request(rksdmmc1_gpio_init.data3_gpio.io, "mmc1-data3");
- gpio_direction_output(rksdmmc1_gpio_init.data3_gpio.io,GPIO_LOW);//set mmc1-data3 to low.
- #endif
- mdelay(100);
- }
- #endif
- }
- break;
-
- case 2: //mmc2
- break;
-
- default:
- break;
- }
-}
-
-static void rk29_sdmmc_set_iomux_mmc0(unsigned int bus_width)
-{
- switch (bus_width)
- {
-
- case 1://SDMMC_CTYPE_4BIT:
- {
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(rksdmmc0_gpio_init.data1_gpio.iomux.fmux);
- iomux_set(rksdmmc0_gpio_init.data2_gpio.iomux.fmux);
- iomux_set(rksdmmc0_gpio_init.data3_gpio.iomux.fmux);
- #else
- rk30_mux_api_set(rksdmmc0_gpio_init.data1_gpio.iomux.name, rksdmmc0_gpio_init.data1_gpio.iomux.fmux);
- rk30_mux_api_set(rksdmmc0_gpio_init.data2_gpio.iomux.name, rksdmmc0_gpio_init.data2_gpio.iomux.fmux);
- rk30_mux_api_set(rksdmmc0_gpio_init.data3_gpio.iomux.name, rksdmmc0_gpio_init.data3_gpio.iomux.fmux);
- #endif
- }
- break;
-
- case 0x10000://SDMMC_CTYPE_8BIT:
- break;
- case 0xFFFF: //gpio_reset
- {
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(rksdmmc0_gpio_init.power_en_gpio.iomux.fgpio);
- #else
- rk30_mux_api_set(rksdmmc0_gpio_init.power_en_gpio.iomux.name, rksdmmc0_gpio_init.power_en_gpio.iomux.fgpio);
- #endif
- gpio_request(rksdmmc0_gpio_init.power_en_gpio.io,"sdmmc-power");
- gpio_direction_output(rksdmmc0_gpio_init.power_en_gpio.io, !(rksdmmc0_gpio_init.power_en_gpio.enable)); //power-off
-
- #if 0 //replace the power control into rk29_sdmmc_set_ios(); modifyed by xbw at 2012-08-12
- rk29_sdmmc_gpio_open(0, 0);
-
- gpio_direction_output(rksdmmc0_gpio_init.power_en_gpio.io, rksdmmc0_gpio_init.power_en_gpio.enable); //power-on
-
- rk29_sdmmc_gpio_open(0, 1);
- #endif
- }
- break;
-
- default: //case 0://SDMMC_CTYPE_1BIT:
- {
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(rksdmmc0_gpio_init.cmd_gpio.iomux.fmux);
- iomux_set(rksdmmc0_gpio_init.clk_gpio.iomux.fmux);
- iomux_set(rksdmmc0_gpio_init.data0_gpio.iomux.fmux);
- #else
- rk30_mux_api_set(rksdmmc0_gpio_init.cmd_gpio.iomux.name, rksdmmc0_gpio_init.cmd_gpio.iomux.fmux);
- rk30_mux_api_set(rksdmmc0_gpio_init.clk_gpio.iomux.name, rksdmmc0_gpio_init.clk_gpio.iomux.fmux);
- rk30_mux_api_set(rksdmmc0_gpio_init.data0_gpio.iomux.name, rksdmmc0_gpio_init.data0_gpio.iomux.fmux);
- #endif
-
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(rksdmmc0_gpio_init.data1_gpio.iomux.fgpio);
- #else
- rk30_mux_api_set(rksdmmc0_gpio_init.data1_gpio.iomux.name, rksdmmc0_gpio_init.data1_gpio.iomux.fgpio);
- #endif
- gpio_request(rksdmmc0_gpio_init.data1_gpio.io, "mmc0-data1");
- gpio_direction_output(rksdmmc0_gpio_init.data1_gpio.io,GPIO_HIGH);//set mmc0-data1 to high.
-
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(rksdmmc0_gpio_init.data2_gpio.iomux.fgpio);
- #else
- rk30_mux_api_set(rksdmmc0_gpio_init.data2_gpio.iomux.name, rksdmmc0_gpio_init.data2_gpio.iomux.fgpio);
- #endif
- gpio_request(rksdmmc0_gpio_init.data2_gpio.io, "mmc0-data2");
- gpio_direction_output(rksdmmc0_gpio_init.data2_gpio.io,GPIO_HIGH);//set mmc0-data2 to high.
-
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(rksdmmc0_gpio_init.data3_gpio.iomux.fgpio);
- #else
- rk30_mux_api_set(rksdmmc0_gpio_init.data3_gpio.iomux.name, rksdmmc0_gpio_init.data3_gpio.iomux.fgpio);
- #endif
- gpio_request(rksdmmc0_gpio_init.data3_gpio.io, "mmc0-data3");
- gpio_direction_output(rksdmmc0_gpio_init.data3_gpio.io,GPIO_HIGH);//set mmc0-data3 to high.
- }
- break;
- }
-}
-
-static void rk29_sdmmc_set_iomux_mmc1(unsigned int bus_width)
-{
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(rksdmmc1_gpio_init.cmd_gpio.iomux.fmux);
- iomux_set(rksdmmc1_gpio_init.clk_gpio.iomux.fmux);
- iomux_set(rksdmmc1_gpio_init.data0_gpio.iomux.fmux);
- iomux_set(rksdmmc1_gpio_init.data1_gpio.iomux.fmux);
- iomux_set(rksdmmc1_gpio_init.data2_gpio.iomux.fmux);
- iomux_set(rksdmmc1_gpio_init.data3_gpio.iomux.fmux);
- #else
- rk30_mux_api_set(rksdmmc1_gpio_init.cmd_gpio.iomux.name, rksdmmc1_gpio_init.cmd_gpio.iomux.fmux);
- rk30_mux_api_set(rksdmmc1_gpio_init.clk_gpio.iomux.name, rksdmmc1_gpio_init.clk_gpio.iomux.fmux);
- rk30_mux_api_set(rksdmmc1_gpio_init.data0_gpio.iomux.name, rksdmmc1_gpio_init.data0_gpio.iomux.fmux);
- rk30_mux_api_set(rksdmmc1_gpio_init.data1_gpio.iomux.name, rksdmmc1_gpio_init.data1_gpio.iomux.fmux);
- rk30_mux_api_set(rksdmmc1_gpio_init.data2_gpio.iomux.name, rksdmmc1_gpio_init.data2_gpio.iomux.fmux);
- rk30_mux_api_set(rksdmmc1_gpio_init.data3_gpio.iomux.name, rksdmmc1_gpio_init.data3_gpio.iomux.fmux);
- #endif
-}
-
-static void rk29_sdmmc_set_iomux_mmc2(unsigned int bus_width)
-{
- ;//
-}
-
-static void rk29_sdmmc_set_iomux(int device_id, unsigned int bus_width)
-{
- switch(device_id)
- {
- case 0:
- #ifdef CONFIG_SDMMC0_RK29
- rk29_sdmmc_set_iomux_mmc0(bus_width);
- #endif
- break;
- case 1:
- #ifdef CONFIG_SDMMC1_RK29
- rk29_sdmmc_set_iomux_mmc1(bus_width);
- #endif
- break;
- case 2:
- rk29_sdmmc_set_iomux_mmc2(bus_width);
- break;
- default:
- break;
- }
-}
-
-#endif
-
-
-
-//1.Part 4: The various operations of the Wifi-BT module
-/*************************************************************************
-* define the varaious operations for Wifi module
-* Generally only the author of Wifi module will modify this section.
-*************************************************************************/
-
-static int rk29sdk_wifi_status(struct device *dev);
-static int rk29sdk_wifi_status_register(void (*callback)(int card_presend, void *dev_id), void *dev_id);
-
-#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
-static int rk29sdk_wifi_mmc0_status(struct device *dev);
-static int rk29sdk_wifi_mmc0_status_register(void (*callback)(int card_presend, void *dev_id), void *dev_id);
-static int rk29sdk_wifi_mmc0_cd = 0; /* wifi virtual 'card detect' status */
-static void (*wifi_mmc0_status_cb)(int card_present, void *dev_id);
-static void *wifi_mmc0_status_cb_devid;
-
-int rk29sdk_wifi_power_state = 0;
-int rk29sdk_bt_power_state = 0;
-
- #if defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- /////////////////////////////////////////////////////////////////////////////////////
- // set the gpio to develop wifi EVB if you select the macro of CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD
- #define USE_SDMMC_CONTROLLER_FOR_WIFI 0
- #define COMBO_MODULE_MT6620_CDT 0 //- 1--use Cdtech chip; 0--unuse CDT chip
- //power
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_POWER_PIN_NAME GPIO3D0_SDMMC1PWREN_NAME
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO3D_GPIO3D0
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FMUX GPIO3D_SDMMC1_PWR_EN
- //reset
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_RESET_PIN_NAME GPIO3D1_SDMMC1BACKENDPWR_NAME
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FGPIO GPIO3D_GPIO3D1
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FMUX GPIO3D_SDMMC1_BACKEND_PWR
- //VDDIO
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL RK30_PIN2_PC5
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_ENABLE_VALUE GPIO_HIGH
- //WIFI_INT_B
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_PIN_NAME GPIO3D2_SDMMC1INTN_NAME
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FGPIO GPIO3D_GPIO3D2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FMUX GPIO3D_SDMMC1_INT_N
- //BGF_INT_B
- #define RK30SDK_WIFI_GPIO_BGF_INT_B RK30_PIN3_PC6
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_PIN_NAME GPIO3C6_SDMMC1DETECTN_NAME
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FGPIO GPIO3C_GPIO3C6
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FMUX GPIO3C_SDMMC1_DETECT_N
- //GPS_SYNC
- #define RK30SDK_WIFI_GPIO_GPS_SYNC RK30_PIN3_PC7
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_PIN_NAME GPIO3C7_SDMMC1WRITEPRT_NAME
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FGPIO GPIO3C_GPIO3C7
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FMUX GPIO3C_SDMMC1_WRITE_PRT
-
- #if COMBO_MODULE_MT6620_CDT
- //ANTSEL2
- #define RK30SDK_WIFI_GPIO_ANTSEL2 RK30_PIN4_PD4
- #define RK30SDK_WIFI_GPIO_ANTSEL2_ENABLE_VALUE GPIO_LOW //use 6620 in CDT chip, LOW--work; High--no work.
- #define RK30SDK_WIFI_GPIO_ANTSEL2_PIN_NAME GPIO4D4_SMCDATA12_TRACEDATA12_NAME
- #define RK30SDK_WIFI_GPIO_ANTSEL2_IOMUX_FGPIO GPIO4D_GPIO4D4
- #define RK30SDK_WIFI_GPIO_ANTSEL2_IOMUX_FMUX GPIO4D_TRACE_DATA12
- //ANTSEL3
- #define RK30SDK_WIFI_GPIO_ANTSEL3 RK30_PIN4_PD3
- #define RK30SDK_WIFI_GPIO_ANTSEL3_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- #define RK30SDK_WIFI_GPIO_ANTSEL3_PIN_NAME GPIO4D3_SMCDATA11_TRACEDATA11_NAME
- #define RK30SDK_WIFI_GPIO_ANTSEL3_IOMUX_FGPIO GPIO4D_GPIO4D3
- #define RK30SDK_WIFI_GPIO_ANTSEL3_IOMUX_FMUX GPIO4D_TRACE_DATA11
- //GPS_LAN
- #define RK30SDK_WIFI_GPIO_GPS_LAN RK30_PIN4_PD6
- #define RK30SDK_WIFI_GPIO_GPS_LAN_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- #define RK30SDK_WIFI_GPIO_GPS_LAN_PIN_NAME GPIO4D6_SMCDATA14_TRACEDATA14_NAME
- #define RK30SDK_WIFI_GPIO_GPS_LAN_IOMUX_FGPIO GPIO4D_GPIO4D6
- #define RK30SDK_WIFI_GPIO_GPS_LAN_IOMUX_FMUX GPIO4D_TRACE_DATA14
- #endif // #if COMBO_MODULE_MT6620_CDT--#endif
-
- #endif // #if defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)---#endif
-#endif // #if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) ---#endif
-
-static int rk29sdk_wifi_cd = 0; /* wifi virtual 'card detect' status */
-static void (*wifi_status_cb)(int card_present, void *dev_id);
-static void *wifi_status_cb_devid;
-
-#if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
-#define RK29SDK_WIFI_SDIO_CARD_INT RK30SDK_WIFI_GPIO_WIFI_INT_B
-#endif
-
-struct rksdmmc_gpio_wifi_moudle rk_platform_wifi_gpio = {
- .power_n = {
- .io = RK30SDK_WIFI_GPIO_POWER_N,
- .enable = RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE,
- #ifdef RK30SDK_WIFI_GPIO_POWER_PIN_NAME
- .iomux = {
- .name = RK30SDK_WIFI_GPIO_POWER_PIN_NAME,
- .fgpio = RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO,
- #ifdef RK30SDK_WIFI_GPIO_POWER_IOMUX_FMUX
- .fmux = RK30SDK_WIFI_GPIO_POWER_IOMUX_FMUX,
- #endif
- },
- #endif
- },
-
- #ifdef RK30SDK_WIFI_GPIO_RESET_N
- .reset_n = {
- .io = RK30SDK_WIFI_GPIO_RESET_N,
- .enable = RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE,
- #ifdef RK30SDK_WIFI_GPIO_RESET_PIN_NAME
- .iomux = {
- .name = RK30SDK_WIFI_GPIO_RESET_PIN_NAME,
- .fgpio = RK30SDK_WIFI_GPIO_RESET_IOMUX_FGPIO,
- #ifdef RK30SDK_WIFI_GPIO_RESET_IOMUX_FMUX
- .fmux = RK30SDK_WIFI_GPIO_RESET_IOMUX_FMUX,
- #endif
- },
- #endif
- },
- #endif
-
- #ifdef RK30SDK_WIFI_GPIO_WIFI_INT_B
- .wifi_int_b = {
- .io = RK30SDK_WIFI_GPIO_WIFI_INT_B,
- .enable = RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE,
- #ifdef RK30SDK_WIFI_GPIO_WIFI_INT_B_PIN_NAME
- .iomux = {
- .name = RK30SDK_WIFI_GPIO_WIFI_INT_B_PIN_NAME,
- .fgpio = RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FGPIO,
- #ifdef RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FMUX
- .fmux = RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FMUX,
- #endif
- },
- #endif
- },
- #endif
-
- #ifdef RK30SDK_WIFI_GPIO_VCCIO_WL
- .vddio = {
- .io = RK30SDK_WIFI_GPIO_VCCIO_WL,
- .enable = RK30SDK_WIFI_GPIO_VCCIO_WL_ENABLE_VALUE,
- #ifdef RK30SDK_WIFI_GPIO_VCCIO_WL_PIN_NAME
- .iomux = {
- .name = RK30SDK_WIFI_GPIO_VCCIO_WL_PIN_NAME,
- .fgpio = RK30SDK_WIFI_GPIO_VCCIO_WL_IOMUX_FGPIO,
- #ifdef RK30SDK_WIFI_GPIO_VCCIO_WL_IOMUX_FMUX
- .fmux = RK30SDK_WIFI_GPIO_VCCIO_WL_IOMUX_FMUX,
- #endif
- },
- #endif
- },
- #endif
-
- #ifdef RK30SDK_WIFI_GPIO_BGF_INT_B
- .bgf_int_b = {
- .io = RK30SDK_WIFI_GPIO_BGF_INT_B,
- .enable = RK30SDK_WIFI_GPIO_BGF_INT_B_ENABLE_VALUE,
- #ifdef RK30SDK_WIFI_GPIO_BGF_INT_B_PIN_NAME
- .iomux = {
- .name = RK30SDK_WIFI_GPIO_BGF_INT_B_PIN_NAME,
- .fgpio = RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FGPIO,
- #ifdef RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FMUX
- .fmux = RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FMUX,
- #endif
- },
- #endif
- },
- #endif
-
- #ifdef RK30SDK_WIFI_GPIO_GPS_SYNC
- .gps_sync = {
- .io = RK30SDK_WIFI_GPIO_GPS_SYNC,
- .enable = RK30SDK_WIFI_GPIO_GPS_SYNC_ENABLE_VALUE,
- #ifdef RK30SDK_WIFI_GPIO_GPS_SYNC_PIN_NAME
- .iomux = {
- .name = RK30SDK_WIFI_GPIO_GPS_SYNC_PIN_NAME,
- .fgpio = RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FGPIO,
- #ifdef RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FMUX
- .fmux = RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FMUX,
- #endif
- },
- #endif
- },
- #endif
-
-#if defined(COMBO_MODULE_MT6620_CDT) && COMBO_MODULE_MT6620_CDT
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL2
- .ANTSEL2 = {
- .io = RK30SDK_WIFI_GPIO_ANTSEL2,
- .enable = RK30SDK_WIFI_GPIO_ANTSEL2_ENABLE_VALUE,
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL2_PIN_NAME
- .iomux = {
- .name = RK30SDK_WIFI_GPIO_ANTSEL2_PIN_NAME,
- .fgpio = RK30SDK_WIFI_GPIO_ANTSEL2_IOMUX_FGPIO,
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL2_IOMUX_FMUX
- .fmux = RK30SDK_WIFI_GPIO_ANTSEL2_IOMUX_FMUX,
- #endif
- },
- #endif
- },
- #endif
-
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL3
- .ANTSEL3 = {
- .io = RK30SDK_WIFI_GPIO_ANTSEL3,
- .enable = RK30SDK_WIFI_GPIO_ANTSEL3_ENABLE_VALUE,
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL3_PIN_NAME
- .iomux = {
- .name = RK30SDK_WIFI_GPIO_ANTSEL3_PIN_NAME,
- .fgpio = RK30SDK_WIFI_GPIO_ANTSEL3_IOMUX_FGPIO,
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL3_IOMUX_FMUX
- .fmux = RK30SDK_WIFI_GPIO_ANTSEL3_IOMUX_FMUX,
- #endif
- },
- #endif
- },
- #endif
-
- #ifdef RK30SDK_WIFI_GPIO_GPS_LAN
- .GPS_LAN = {
- .io = RK30SDK_WIFI_GPIO_GPS_LAN,
- .enable = RK30SDK_WIFI_GPIO_GPS_LAN_ENABLE_VALUE,
- #ifdef RK30SDK_WIFI_GPIO_GPS_LAN_PIN_NAME
- .iomux = {
- .name = RK30SDK_WIFI_GPIO_GPS_LAN_PIN_NAME,
- .fgpio = RK30SDK_WIFI_GPIO_GPS_LAN_IOMUX_FGPIO,
- #ifdef RK30SDK_WIFI_GPIO_GPS_LAN_IOMUX_FMUX
- .fmux = RK30SDK_WIFI_GPIO_GPS_LAN_IOMUX_FMUX,
- #endif
- },
- #endif
- },
- #endif
-#endif // #if COMBO_MODULE_MT6620_CDT--#endif
-};
-
-
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
-#define PREALLOC_WLAN_SEC_NUM 4
-#define PREALLOC_WLAN_BUF_NUM 160
-#define PREALLOC_WLAN_SECTION_HEADER 24
-
-#define WLAN_SECTION_SIZE_0 (PREALLOC_WLAN_BUF_NUM * 128)
-#define WLAN_SECTION_SIZE_1 (PREALLOC_WLAN_BUF_NUM * 128)
-#define WLAN_SECTION_SIZE_2 (PREALLOC_WLAN_BUF_NUM * 512)
-#define WLAN_SECTION_SIZE_3 (PREALLOC_WLAN_BUF_NUM * 1024)
-
-#define WLAN_SKB_BUF_NUM 16
-
-static struct sk_buff *wlan_static_skb[WLAN_SKB_BUF_NUM];
-
-struct wifi_mem_prealloc {
- void *mem_ptr;
- unsigned long size;
-};
-
-static struct wifi_mem_prealloc wifi_mem_array[PREALLOC_WLAN_SEC_NUM] = {
- {NULL, (WLAN_SECTION_SIZE_0 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_1 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_2 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_3 + PREALLOC_WLAN_SECTION_HEADER)}
-};
-
-static void *rk29sdk_mem_prealloc(int section, unsigned long size)
-{
- if (section == PREALLOC_WLAN_SEC_NUM)
- return wlan_static_skb;
-
- if ((section < 0) || (section > PREALLOC_WLAN_SEC_NUM))
- return NULL;
-
- if (wifi_mem_array[section].size < size)
- return NULL;
-
- return wifi_mem_array[section].mem_ptr;
-}
-
-static int __init rk29sdk_init_wifi_mem(void)
-{
- int i;
- int j;
-
- for (i = 0 ; i < WLAN_SKB_BUF_NUM ; i++) {
- wlan_static_skb[i] = dev_alloc_skb(
- ((i < (WLAN_SKB_BUF_NUM / 2)) ? 4096 : 8192));
-
- if (!wlan_static_skb[i])
- goto err_skb_alloc;
- }
-
- for (i = 0 ; i < PREALLOC_WLAN_SEC_NUM ; i++) {
- wifi_mem_array[i].mem_ptr =
- kmalloc(wifi_mem_array[i].size, GFP_KERNEL);
-
- if (!wifi_mem_array[i].mem_ptr)
- goto err_mem_alloc;
- }
- return 0;
-
-err_mem_alloc:
- pr_err("Failed to mem_alloc for WLAN\n");
- for (j = 0 ; j < i ; j++)
- kfree(wifi_mem_array[j].mem_ptr);
-
- i = WLAN_SKB_BUF_NUM;
-
-err_skb_alloc:
- pr_err("Failed to skb_alloc for WLAN\n");
- for (j = 0 ; j < i ; j++)
- dev_kfree_skb(wlan_static_skb[j]);
-
- return -ENOMEM;
-}
-
-static int rk29sdk_wifi_status(struct device *dev)
-{
- return rk29sdk_wifi_cd;
-}
-
-static int rk29sdk_wifi_status_register(void (*callback)(int card_present, void *dev_id), void *dev_id)
-{
- if(wifi_status_cb)
- return -EAGAIN;
- wifi_status_cb = callback;
- wifi_status_cb_devid = dev_id;
- return 0;
-}
-
-static int __init rk29sdk_wifi_bt_gpio_control_init(void)
-{
- rk29sdk_init_wifi_mem();
- rk29_mux_api_set(rk_platform_wifi_gpio.power_n.iomux.name, rk_platform_wifi_gpio.power_n.iomux.fgpio);
-
- if (rk_platform_wifi_gpio.power_n.io != INVALID_GPIO) {
- if (gpio_request(rk_platform_wifi_gpio.power_n.io, "wifi_power")) {
- pr_info("%s: request wifi power gpio failed\n", __func__);
- return -1;
- }
- }
-
-#ifdef RK30SDK_WIFI_GPIO_RESET_N
- if (rk_platform_wifi_gpio.reset_n.io != INVALID_GPIO) {
- if (gpio_request(rk_platform_wifi_gpio.reset_n.io, "wifi reset")) {
- pr_info("%s: request wifi reset gpio failed\n", __func__);
- gpio_free(rk_platform_wifi_gpio.power_n.io);
- return -1;
- }
- }
-#endif
-
- if (rk_platform_wifi_gpio.power_n.io != INVALID_GPIO)
- gpio_direction_output(rk_platform_wifi_gpio.power_n.io, !(rk_platform_wifi_gpio.power_n.enable) );
-
-#ifdef RK30SDK_WIFI_GPIO_RESET_N
- if (rk_platform_wifi_gpio.reset_n.io != INVALID_GPIO)
- gpio_direction_output(rk_platform_wifi_gpio.reset_n.io, !(rk_platform_wifi_gpio.reset_n.enable) );
-#endif
-
- #if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
-
- #if !defined(CONFIG_MT5931) && !defined(CONFIG_MT5931_MT6622)
- rk29_mux_api_set(rksdmmc1_gpio_init.data1_gpio.iomux.name, rksdmmc1_gpio_init.data1_gpio.iomux.fgpio);
- gpio_request(rksdmmc1_gpio_init.data1_gpio.io, "mmc1-data1");
- gpio_direction_output(rksdmmc1_gpio_init.data1_gpio.io,GPIO_LOW);//set mmc1-data1 to low.
-
- rk29_mux_api_set(rksdmmc1_gpio_init.data2_gpio.iomux.name, rksdmmc1_gpio_init.data2_gpio.iomux.fgpio);
- gpio_request(rksdmmc1_gpio_init.data2_gpio.io, "mmc1-data2");
- gpio_direction_output(rksdmmc1_gpio_init.data2_gpio.io,GPIO_LOW);//set mmc1-data2 to low.
-
- rk29_mux_api_set(rksdmmc1_gpio_init.data3_gpio.iomux.name, rksdmmc1_gpio_init.data3_gpio.iomux.fgpio);
- gpio_request(rksdmmc1_gpio_init.data3_gpio.io, "mmc1-data3");
- gpio_direction_output(rksdmmc1_gpio_init.data3_gpio.io,GPIO_LOW);//set mmc1-data3 to low.
- #endif
-
- rk29_sdmmc_gpio_open(1, 0); //added by xbw at 2011-10-13
- #endif
- pr_info("%s: init finished\n",__func__);
-
- return 0;
-}
-
-#if (defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU) || defined(CONFIG_RTL8723AU)) \
- && defined(CONFIG_ARCH_RK2928)
-static int usbwifi_power_status = 1;
-int rk29sdk_wifi_power(int on)
-{
- pr_info("%s: %d\n", __func__, on);
- if (on){
- if(usbwifi_power_status == 1) {
- rkusb_wifi_power(0);
- mdelay(50);
- }
- rkusb_wifi_power(1);
- usbwifi_power_status = 1;
- pr_info("wifi turn on power\n");
- }else{
- rkusb_wifi_power(0);
- usbwifi_power_status = 0;
- pr_info("wifi shut off power\n");
- }
- return 0;
-}
-#else
-int rk29sdk_wifi_power(int on)
-{
- pr_info("%s: %d\n", __func__, on);
- if (on){
- gpio_set_value(rk_platform_wifi_gpio.power_n.io, rk_platform_wifi_gpio.power_n.enable);
- mdelay(50);
-
- #if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
- rk29_sdmmc_gpio_open(1, 1); //added by xbw at 2011-10-13
- #endif
-
- #ifdef RK30SDK_WIFI_GPIO_RESET_N
- if (rk_platform_wifi_gpio.reset_n.io != INVALID_GPIO)
- gpio_set_value(rk_platform_wifi_gpio.reset_n.io, rk_platform_wifi_gpio.reset_n.enable);
- #endif
- mdelay(100);
- pr_info("wifi turn on power\n");
- }else{
-// if (!rk29sdk_bt_power_state){
- gpio_set_value(rk_platform_wifi_gpio.power_n.io, !(rk_platform_wifi_gpio.power_n.enable));
-
- #if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
- rk29_sdmmc_gpio_open(1, 0); //added by xbw at 2011-10-13
- #endif
-
- mdelay(100);
- pr_info("wifi shut off power\n");
-// }else
-// {
-// pr_info("wifi shouldn't shut off power, bt is using it!\n");
-// }
-#ifdef RK30SDK_WIFI_GPIO_RESET_N
- if (rk_platform_wifi_gpio.reset_n.io != INVALID_GPIO)
- gpio_set_value(rk_platform_wifi_gpio.reset_n.io, !(rk_platform_wifi_gpio.reset_n.enable));
-#endif
- }
-
-// rk29sdk_wifi_power_state = on;
- return 0;
-}
-#endif
-EXPORT_SYMBOL(rk29sdk_wifi_power);
-
-static int rk29sdk_wifi_reset_state;
-static int rk29sdk_wifi_reset(int on)
-{
- pr_info("%s: %d\n", __func__, on);
- //mdelay(100);
- rk29sdk_wifi_reset_state = on;
- return 0;
-}
-
-int rk29sdk_wifi_set_carddetect(int val)
-{
- pr_info("%s:%d\n", __func__, val);
- rk29sdk_wifi_cd = val;
- if (wifi_status_cb){
- wifi_status_cb(val, wifi_status_cb_devid);
- }else {
- pr_warning("%s, nobody to notify\n", __func__);
- }
- return 0;
-}
-EXPORT_SYMBOL(rk29sdk_wifi_set_carddetect);
-
-
-static struct resource resources[] = {
- {
- .start = RK30SDK_WIFI_GPIO_WIFI_INT_B,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL | IORESOURCE_IRQ_SHAREABLE,
- .name = "bcmdhd_wlan_irq",
- },
-};
- //#if defined(CONFIG_WIFI_CONTROL_FUNC)----#elif
-
-///////////////////////////////////////////////////////////////////////////////////
-#elif defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
-
-#define debug_combo_system 0
-
-int rk29sdk_wifi_combo_get_BGFgpio(void)
-{
- return rk_platform_wifi_gpio.bgf_int_b.io;
-}
-EXPORT_SYMBOL(rk29sdk_wifi_combo_get_BGFgpio);
-
-
-int rk29sdk_wifi_combo_get_GPS_SYNC_gpio(void)
-{
- return rk_platform_wifi_gpio.gps_sync.io;
-}
-EXPORT_SYMBOL(rk29sdk_wifi_combo_get_GPS_SYNC_gpio);
-
-
-static int rk29sdk_wifi_combo_module_gpio_init(void)
-{
- //VDDIO
- #ifdef RK30SDK_WIFI_GPIO_VCCIO_WL
- #ifdef RK30SDK_WIFI_GPIO_VCCIO_WL_PIN_NAME
- rk30_mux_api_set(rk_platform_wifi_gpio.vddio.iomux.name, rk_platform_wifi_gpio.vddio.iomux.fgpio);
- #endif
- gpio_request(rk_platform_wifi_gpio.vddio.io, "combo-VDDIO");
- gpio_direction_output(rk_platform_wifi_gpio.vddio.io, !(rk_platform_wifi_gpio.power_n.enable));
- #endif
-
- //BGF_INT_B
- #ifdef RK30SDK_WIFI_GPIO_BGF_INT_B_PIN_NAME
- rk30_mux_api_set(rk_platform_wifi_gpio.bgf_int_b.iomux.name, rk_platform_wifi_gpio.bgf_int_b.iomux.fgpio);
- #endif
- gpio_request(rk_platform_wifi_gpio.bgf_int_b.io, "combo-BGFINT");
- gpio_pull_updown(rk_platform_wifi_gpio.bgf_int_b.io, GPIOPullUp);
- gpio_direction_input(rk_platform_wifi_gpio.bgf_int_b.io);
-
- //WIFI_INT_B
- #ifdef RK30SDK_WIFI_GPIO_WIFI_INT_B_PIN_NAME
- rk30_mux_api_set(rk_platform_wifi_gpio.bgf_int_b.iomux.name, rk_platform_wifi_gpio.bgf_int_b.iomux.fgpio);
- #endif
- gpio_request(rk_platform_wifi_gpio.wifi_int_b.io, "combo-WIFIINT");
- gpio_pull_updown(rk_platform_wifi_gpio.wifi_int_b.io, GPIOPullUp);
- gpio_direction_input(rk_platform_wifi_gpio.wifi_int_b.io);
-
- //reset
- #ifdef RK30SDK_WIFI_GPIO_RESET_PIN_NAME
- rk30_mux_api_set(rk_platform_wifi_gpio.reset_n.iomux.name, rk_platform_wifi_gpio.reset_n.iomux.fgpio);
- #endif
- gpio_request(rk_platform_wifi_gpio.reset_n.io, "combo-RST");
- gpio_direction_output(rk_platform_wifi_gpio.reset_n.io, !(rk_platform_wifi_gpio.reset_n.enable));
-
- //power
- #ifdef RK30SDK_WIFI_GPIO_POWER_PIN_NAME
- rk30_mux_api_set(rk_platform_wifi_gpio.power_n.iomux.name, rk_platform_wifi_gpio.power_n.iomux.fgpio);
- #endif
- gpio_request(rk_platform_wifi_gpio.power_n.io, "combo-PMUEN");
- gpio_direction_output(rk_platform_wifi_gpio.power_n.io, !(rk_platform_wifi_gpio.power_n.enable));
-
- #if defined(COMBO_MODULE_MT6620_CDT) && COMBO_MODULE_MT6620_CDT
- //ANTSEL2
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL2
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL2_PIN_NAME
- rk30_mux_api_set(rk_platform_wifi_gpio.ANTSEL2.iomux.name, rk_platform_wifi_gpio.ANTSEL2.iomux.fgpio);
- #endif
- gpio_request(rk_platform_wifi_gpio.ANTSEL2.io, "combo-ANTSEL2");
- gpio_direction_output(rk_platform_wifi_gpio.ANTSEL2.io, rk_platform_wifi_gpio.ANTSEL2.enable);
- #endif
-
- //ANTSEL3
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL3
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL3_PIN_NAME
- rk30_mux_api_set(rk_platform_wifi_gpio.ANTSEL3.iomux.name, rk_platform_wifi_gpio.ANTSEL3.iomux.fgpio);
- #endif
- gpio_request(rk_platform_wifi_gpio.ANTSEL3.io, "combo-ANTSEL3");
- gpio_direction_output(rk_platform_wifi_gpio.ANTSEL3.io, rk_platform_wifi_gpio.ANTSEL3.enable);
- #endif
-
- //GPS_LAN
- #ifdef RK30SDK_WIFI_GPIO_GPS_LAN
- #ifdef RK30SDK_WIFI_GPIO_GPS_LAN_PIN_NAME
- rk30_mux_api_set(rk_platform_wifi_gpio.GPS_LAN.iomux.name, rk_platform_wifi_gpio.GPS_LAN.iomux.fgpio);
- #endif
- gpio_request(rk_platform_wifi_gpio.GPS_LAN.io, "combo-GPSLAN");
- gpio_direction_output(rk_platform_wifi_gpio.GPS_LAN.io, rk_platform_wifi_gpio.GPS_LAN.enable);
- #endif
-
- #endif//#if COMBO_MODULE_MT6620_CDT ---#endif
-
- return 0;
-}
-
-
-int rk29sdk_wifi_combo_module_power(int on)
-{
- if(on)
- {
- #ifdef RK30SDK_WIFI_GPIO_VCCIO_WL
- gpio_set_value(rk_platform_wifi_gpio.vddio.io, rk_platform_wifi_gpio.vddio.enable);
- mdelay(10);
- #endif
-
- gpio_set_value(rk_platform_wifi_gpio.power_n.io, rk_platform_wifi_gpio.power_n.enable);
- mdelay(10);
- pr_info("combo-module turn on power\n");
- }
- else
- {
- gpio_set_value(rk_platform_wifi_gpio.power_n.io, !(rk_platform_wifi_gpio.power_n.enable) );
- mdelay(10);
-
- #ifdef RK30SDK_WIFI_GPIO_VCCIO_WL
- gpio_set_value(rk_platform_wifi_gpio.vddio.io, !(rk_platform_wifi_gpio.vddio.enable));
- #endif
-
- pr_info("combo-module turn off power\n");
- }
- return 0;
-
-}
-EXPORT_SYMBOL(rk29sdk_wifi_combo_module_power);
-
-
-int rk29sdk_wifi_combo_module_reset(int on)
-{
- if(on)
- {
- gpio_set_value(rk_platform_wifi_gpio.reset_n.io, rk_platform_wifi_gpio.reset_n.enable);
- pr_info("combo-module reset out 1\n");
- }
- else
- {
- gpio_set_value(rk_platform_wifi_gpio.reset_n.io, !(rk_platform_wifi_gpio.reset_n.enable) );
- pr_info("combo-module reset out 0\n");
- }
-
- return 0;
-}
-EXPORT_SYMBOL(rk29sdk_wifi_combo_module_reset);
-
-
-static int rk29sdk_wifi_mmc0_status(struct device *dev)
-{
- return rk29sdk_wifi_mmc0_cd;
-}
-
-static int rk29sdk_wifi_mmc0_status_register(void (*callback)(int card_present, void *dev_id), void *dev_id)
-{
- if(wifi_mmc0_status_cb)
- return -EAGAIN;
- wifi_mmc0_status_cb = callback;
- wifi_mmc0_status_cb_devid = dev_id;
- return 0;
-}
-
-
-static int rk29sdk_wifi_status(struct device *dev)
-{
- return rk29sdk_wifi_cd;
-}
-
-static int rk29sdk_wifi_status_register(void (*callback)(int card_present, void *dev_id), void *dev_id)
-{
- if(wifi_status_cb)
- return -EAGAIN;
- wifi_status_cb = callback;
- wifi_status_cb_devid = dev_id;
- return 0;
-}
-
-int rk29sdk_wifi_power(int on)
-{
- pr_info("%s: %d\n", __func__, on);
- if (on){
-
- #if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
-
- #if defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- rk29_sdmmc_gpio_open(0, 1);
- #else
- rk29_sdmmc_gpio_open(1, 0);
- mdelay(10);
- rk29_sdmmc_gpio_open(1, 1);
- #endif
- #endif
-
- mdelay(100);
- pr_info("wifi turn on power\n");
- }
- else
- {
-#if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
- #if defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- rk29_sdmmc_gpio_open(0, 0);
- #else
- rk29_sdmmc_gpio_open(1, 0);
- #endif
-#endif
- mdelay(100);
- pr_info("wifi shut off power\n");
-
- }
-
- rk29sdk_wifi_power_state = on;
- return 0;
-
-}
-EXPORT_SYMBOL(rk29sdk_wifi_power);
-
-
-int rk29sdk_wifi_reset(int on)
-{
- return 0;
-}
-EXPORT_SYMBOL(rk29sdk_wifi_reset);
-
-
-#if defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
-int rk29sdk_wifi_set_carddetect(int val)
-{
- pr_info("%s:%d\n", __func__, val);
- rk29sdk_wifi_mmc0_cd = val;
- if (wifi_mmc0_status_cb){
- wifi_mmc0_status_cb(val, wifi_mmc0_status_cb_devid);
- }else {
- pr_warning("%s,in mmc0 nobody to notify\n", __func__);
- }
- return 0;
-}
-
-#else
-int rk29sdk_wifi_set_carddetect(int val)
-{
- pr_info("%s:%d\n", __func__, val);
- rk29sdk_wifi_cd = val;
- if (wifi_status_cb){
- wifi_status_cb(val, wifi_status_cb_devid);
- }else {
- pr_warning("%s,in mmc1 nobody to notify\n", __func__);
- }
- return 0;
-}
-#endif
-
-EXPORT_SYMBOL(rk29sdk_wifi_set_carddetect);
-
-///////////////////////////////////////////////////////////////////////////////////
-#endif //#if defined(CONFIG_WIFI_CONTROL_FUNC)---#elif defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) --#endif
-
-
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC)
-static struct wifi_platform_data rk29sdk_wifi_control = {
- .set_power = rk29sdk_wifi_power,
- .set_reset = rk29sdk_wifi_reset,
- .set_carddetect = rk29sdk_wifi_set_carddetect,
- .mem_prealloc = rk29sdk_mem_prealloc,
-};
-
-static struct platform_device rk29sdk_wifi_device = {
- .name = "bcmdhd_wlan",
- .id = 1,
- .num_resources = ARRAY_SIZE(resources),
- .resource = resources,
- .dev = {
- .platform_data = &rk29sdk_wifi_control,
- },
-};
-
-#elif defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
-
- #if debug_combo_system
- static struct combo_module_platform_data rk29sdk_combo_module_control = {
- .set_power = rk29sdk_wifi_combo_module_power,
- .set_reset = rk29sdk_wifi_combo_module_reset,
- };
-
- static struct platform_device rk29sdk_combo_module_device = {
- .name = "combo-system",
- .id = 1,
- .dev = {
- .platform_data = &rk29sdk_combo_module_control,
- },
- };
- #endif
-
-static struct wifi_platform_data rk29sdk_wifi_control = {
- .set_power = rk29sdk_wifi_power,
- .set_reset = rk29sdk_wifi_reset,
- .set_carddetect = rk29sdk_wifi_set_carddetect,
-};
-
-static struct platform_device rk29sdk_wifi_device = {
- .name = "combo-wifi",
- .id = 1,
- .dev = {
- .platform_data = &rk29sdk_wifi_control,
- },
-};
-
-#endif
-
-
+++ /dev/null
-#include <linux/regulator/machine.h>
-#include <linux/i2c/twl.h>
-#include <linux/mfd/tps65910.h>
-#include <mach/sram.h>
-#include <linux/platform_device.h>
-
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-
-#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
-
-#define CRU_CLKGATE5_CON_ADDR 0x00e4
-#define GRF_GPIO6L_DIR_ADDR 0x0030
-#define GRF_GPIO6L_DO_ADDR 0x0068
-#define GRF_GPIO6L_EN_ADDR 0x00a0
-#define GPIO6_PB3_DIR_OUT 0x08000800
-#define GPIO6_PB3_DO_LOW 0x08000000
-#define GPIO6_PB3_DO_HIGH 0x08000800
-#define GPIO6_PB3_EN_MASK 0x08000800
-#define GPIO6_PB3_UNEN_MASK 0x08000000
-#define GPIO6_PB1_DIR_OUT 0x02000200
-#define GPIO6_PB1_DO_LOW 0x02000000
-#define GPIO6_PB1_DO_HIGH 0x02000200
-#define GPIO6_PB1_EN_MASK 0x02000200
-#define GPIO6_PB1_UNEN_MASK 0x02000000
-
-#ifdef CONFIG_MFD_TPS65910
-#define PMU_POWER_SLEEP RK30_PIN6_PB1
-extern int platform_device_register(struct platform_device *pdev);
-
-int tps65910_pre_init(struct tps65910 *tps65910){
-
- int val = 0;
- int i = 0;
- int err = -1;
-
- printk("%s,line=%d\n", __func__,__LINE__);
- //gpio_request(PMU_POWER_SLEEP, "NULL");
- //gpio_direction_output(PMU_POWER_SLEEP, GPIO_HIGH);
-
- val = tps65910_reg_read(tps65910, TPS65910_DEVCTRL2);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_DEVCTRL2 reg\n");
- return val;
- }
- /* Set sleep state active high and allow device turn-off after PWRON long press */
- val |= (DEVCTRL2_SLEEPSIG_POL_MASK | DEVCTRL2_PWON_LP_OFF_MASK);
-
- err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL2, val);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_DEVCTRL2 reg\n");
- return err;
- }
-
- #if 1
- /* set PSKIP=0 */
- val = tps65910_reg_read(tps65910, TPS65910_DCDCCTRL);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
- return val;
- }
-
- val &= ~DEVCTRL_DEV_OFF_MASK;
- val &= ~DEVCTRL_DEV_SLP_MASK;
- err = tps65910_reg_write(tps65910, TPS65910_DCDCCTRL, val);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_DCDCCTRL reg\n");
- return err;
- }
- #endif
- /* Set the maxinum load current */
- /* VDD1 */
- val = tps65910_reg_read(tps65910, TPS65910_VDD1);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_VDD1 reg\n");
- return val;
- }
-
- val |= (1<<5); //when 1: 1.5 A
- val |= (0x07<<2); //TSTEP[2:0] = 111 : 2.5 mV/¦Ìs(sampling 3 Mhz/5)
- err = tps65910_reg_write(tps65910, TPS65910_VDD1, val);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_VDD1 reg\n");
- return err;
- }
-
- /* VDD2 */
- val = tps65910_reg_read(tps65910, TPS65910_VDD2);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_VDD2 reg\n");
- return val;
- }
-
- val |= (1<<5); //when 1: 1.5 A
- err = tps65910_reg_write(tps65910, TPS65910_VDD2, val);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_VDD2 reg\n");
- return err;
- }
-
- /* VIO */
- val = tps65910_reg_read(tps65910, TPS65910_VIO);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_VIO reg\n");
- return -EIO;
- }
-
- val |= (1<<6); //when 01: 1.0 A
- err = tps65910_reg_write(tps65910, TPS65910_VIO, val);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_VIO reg\n");
- return err;
- }
- #if 1
- /* Mask ALL interrupts */
- err = tps65910_reg_write(tps65910,TPS65910_INT_MSK, 0xFF);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_INT_MSK reg\n");
- return err;
- }
-
- err = tps65910_reg_write(tps65910, TPS65910_INT_MSK2, 0x03);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_INT_MSK2 reg\n");
- return err;
- }
-
- /* Set RTC Power, disable Smart Reflex in DEVCTRL_REG */
- #if 1
- val = 0;
- val |= (DEVCTRL_SR_CTL_I2C_SEL_MASK);
- err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL, val);
- if (err) {
- printk(KERN_ERR "Unable to write TPS65910_DEVCTRL reg\n");
- return err;
- }
- printk(KERN_INFO "TPS65910 Set default voltage.\n");
- #endif
- #if 0
- //read sleep control register for debug
- for(i=0; i<6; i++)
- {
- err = tps65910_reg_read(tps65910, &val, TPS65910_DEVCTRL+i);
- if (err) {
- printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
- return -EIO;
- }
- else
- printk("%s.......is 0x%04x\n",__FUNCTION__,val);
- }
- #endif
-
- #if 1
- //sleep control register
- /*set func when in sleep mode */
- val = tps65910_reg_read(tps65910, TPS65910_DEVCTRL);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
- return val;
- }
-
- val |= (1 << 1);
- err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL, val);
- if (err) {
- printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
- \n", TPS65910_VDIG1);
- return err;
- }
-
- /* open ldo when in sleep mode */
- val = tps65910_reg_read(tps65910, TPS65910_SLEEP_KEEP_LDO_ON);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
- return val;
- }
-
- val &= 0;
- err = tps65910_reg_write(tps65910, TPS65910_SLEEP_KEEP_LDO_ON, val);
- if (err) {
- printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
- \n", TPS65910_VDIG1);
- return err;
- }
-
- /*set dc mode when in sleep mode */
- val = tps65910_reg_read(tps65910, TPS65910_SLEEP_KEEP_RES_ON);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
- return val;
- }
-
- val |= 0xff;
- val &= ~(0x07); //set vdd1 vdd2 vio in pfm mode when in sleep
- err = tps65910_reg_write(tps65910, TPS65910_SLEEP_KEEP_RES_ON, val);
- if (err) {
- printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
- \n", TPS65910_VDIG1);
- return err;
- }
-
- /*close ldo when in sleep mode */
- val = tps65910_reg_read(tps65910, TPS65910_SLEEP_SET_LDO_OFF);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
- return val;
- }
-
- val |= 0x0b;
- err = tps65910_reg_write(tps65910, TPS65910_SLEEP_SET_LDO_OFF, val);
- if (err) {
- printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
- \n", TPS65910_VDIG1);
- return err;
- }
- #endif
- #if 0
- //read sleep control register for debug
- for(i=0; i<6; i++)
- {
- err = tps65910_reg_read(tps65910, &val, TPS65910_DEVCTRL+i);
- if (err) {
- printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
- return -EIO;
- }
- else
- printk("%s.......is 0x%4x\n",__FUNCTION__,val);
- }
- #endif
- #endif
-
- /**********************set arm in pwm ****************/
- val = tps65910_reg_read(tps65910, TPS65910_DCDCCTRL);
- if (val<0) {
- printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
- return val;
- }
-
- val &= ~(1<<4);
- err = tps65910_reg_write(tps65910, TPS65910_DCDCCTRL, val);
- if (err) {
- printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
- \n", TPS65910_VDIG1);
- return err;
- }
- /************************************************/
-
- printk("%s,line=%d\n", __func__,__LINE__);
- return 0;
-
-}
-int tps65910_post_init(struct tps65910 *tps65910)
-{
- struct regulator *dcdc;
- struct regulator *ldo;
- printk("%s,line=%d\n", __func__,__LINE__);
-
- g_pmic_type = PMIC_TYPE_TPS65910;
- printk("%s:g_pmic_type=%d\n",__func__,g_pmic_type);
-
- #ifdef CONFIG_RK30_PWM_REGULATOR
- platform_device_register(&pwm_regulator_device[0]);
- #endif
-
- dcdc = regulator_get(NULL, "vio"); //vcc_io
- regulator_set_voltage(dcdc, 3000000, 3000000);
- regulator_enable(dcdc);
- printk("%s set vio vcc_io=%dmV end\n", __func__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- ldo = regulator_get(NULL, "vpll"); // vcc25
- regulator_set_voltage(ldo, 2500000, 2500000);
- regulator_enable(ldo);
- printk("%s set vpll vdd11=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "vdig2"); // vdd11
- regulator_set_voltage(ldo, 1100000, 1100000);
- regulator_enable(ldo);
- printk("%s set vdig2 vdd11=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "vaux33"); //vcc_tp
- regulator_set_voltage(ldo, 3300000, 3300000);
- regulator_enable(ldo);
- printk("%s set vaux33 vcc_tp=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- dcdc = regulator_get(NULL, "vdd_cpu"); //vdd_cpu
- regulator_set_voltage(dcdc, 1200000, 1200000);
- regulator_enable(dcdc);
- printk("%s set vdd1 vdd_cpu=%dmV end\n", __func__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- dcdc = regulator_get(NULL, "vdd2"); //vcc_ddr
- regulator_set_voltage(dcdc, 1200000, 1200000); // 1.5*4/5 = 1.2 and Vout=1.5v
- regulator_enable(dcdc);
- printk("%s set vdd2 vcc_ddr=%dmV end\n", __func__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- ldo = regulator_get(NULL, "vdig1"); //vcc18_cif
- regulator_set_voltage(ldo, 1800000, 1800000);
- regulator_enable(ldo);
- printk("%s set vdig1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- dcdc = regulator_get(NULL, "vaux1"); //vcc25_hdmi
- regulator_set_voltage(dcdc,2500000,2500000);
- regulator_enable(dcdc);
- printk("%s set vaux1 vcc25_hdmi=%dmV end\n", __func__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- ldo = regulator_get(NULL, "vaux2"); //vcca33
- regulator_set_voltage(ldo, 3300000, 3300000);
- regulator_enable(ldo);
- printk("%s set vaux2 vcca33=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "vdac"); // vccio_wl
- regulator_set_voltage(ldo,1800000,1800000);
- regulator_enable(ldo);
- printk("%s set vdac vccio_wl=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "vmmc"); //vcc28_cif
- regulator_set_voltage(ldo,2800000,2800000);
- regulator_enable(ldo);
- printk("%s set vmmc vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- printk("%s,line=%d END\n", __func__,__LINE__);
-
- return 0;
-}
-
-static struct regulator_consumer_supply tps65910_smps1_supply[] = {
- {
- .supply = "vdd1",
- },
- {
- .supply = "vdd_cpu",
- },
-};
-static struct regulator_consumer_supply tps65910_smps2_supply[] = {
- {
- .supply = "vdd2",
- },
-
-};
-static struct regulator_consumer_supply tps65910_smps3_supply[] = {
- {
- .supply = "vdd3",
- },
-};
-static struct regulator_consumer_supply tps65910_smps4_supply[] = {
- {
- .supply = "vio",
- },
-};
-static struct regulator_consumer_supply tps65910_ldo1_supply[] = {
- {
- .supply = "vdig1",
- },
-};
-static struct regulator_consumer_supply tps65910_ldo2_supply[] = {
- {
- .supply = "vdig2",
- },
-};
-
-static struct regulator_consumer_supply tps65910_ldo3_supply[] = {
- {
- .supply = "vaux1",
- },
-};
-static struct regulator_consumer_supply tps65910_ldo4_supply[] = {
- {
- .supply = "vaux2",
- },
-};
-static struct regulator_consumer_supply tps65910_ldo5_supply[] = {
- {
- .supply = "vaux33",
- },
-};
-static struct regulator_consumer_supply tps65910_ldo6_supply[] = {
- {
- .supply = "vmmc",
- },
-};
-static struct regulator_consumer_supply tps65910_ldo7_supply[] = {
- {
- .supply = "vdac",
- },
-};
-
-static struct regulator_consumer_supply tps65910_ldo8_supply[] = {
- {
- .supply = "vpll",
- },
-};
-
-static struct regulator_init_data tps65910_smps1 = {
- .constraints = {
- .name = "VDD1",
- .min_uV = 600000,
- .max_uV = 1500000,
- .apply_uV = 1,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_smps1_supply),
- .consumer_supplies = tps65910_smps1_supply,
-};
-
-/* */
-static struct regulator_init_data tps65910_smps2 = {
- .constraints = {
- .name = "VDD2",
- .min_uV = 600000,
- .max_uV = 1500000,
- .apply_uV = 1,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_smps2_supply),
- .consumer_supplies = tps65910_smps2_supply,
-};
-
-/* */
-static struct regulator_init_data tps65910_smps3 = {
- .constraints = {
- .name = "VDD3",
- .min_uV = 1000000,
- .max_uV = 1400000,
- .apply_uV = 1,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_smps3_supply),
- .consumer_supplies = tps65910_smps3_supply,
-};
-
-static struct regulator_init_data tps65910_smps4 = {
- .constraints = {
- .name = "VIO",
- .min_uV = 1800000,
- .max_uV = 3300000,
- .apply_uV = 1,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_smps4_supply),
- .consumer_supplies = tps65910_smps4_supply,
-};
-static struct regulator_init_data tps65910_ldo1 = {
- .constraints = {
- .name = "VDIG1",
- .min_uV = 1200000,
- .max_uV = 2700000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo1_supply),
- .consumer_supplies = tps65910_ldo1_supply,
-};
-
-/* */
-static struct regulator_init_data tps65910_ldo2 = {
- .constraints = {
- .name = "VDIG2",
- .min_uV = 1000000,
- .max_uV = 1800000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo2_supply),
- .consumer_supplies = tps65910_ldo2_supply,
-};
-
-/* */
-static struct regulator_init_data tps65910_ldo3 = {
- .constraints = {
- .name = "VAUX1",
- .min_uV = 1800000,
- .max_uV = 3300000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo3_supply),
- .consumer_supplies = tps65910_ldo3_supply,
-};
-
-/* */
-static struct regulator_init_data tps65910_ldo4 = {
- .constraints = {
- .name = "VAUX2",
- .min_uV = 1800000,
- .max_uV = 3300000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo4_supply),
- .consumer_supplies = tps65910_ldo4_supply,
-};
-
-/* */
-static struct regulator_init_data tps65910_ldo5 = {
- .constraints = {
- .name = "VAUX33",
- .min_uV = 1800000,
- .max_uV = 3300000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo5_supply),
- .consumer_supplies = tps65910_ldo5_supply,
-};
-
-/* */
-static struct regulator_init_data tps65910_ldo6 = {
- .constraints = {
- .name = "VMMC",
- .min_uV = 1800000,
- .max_uV = 3300000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo6_supply),
- .consumer_supplies = tps65910_ldo6_supply,
-};
-
-/* */
-static struct regulator_init_data tps65910_ldo7 = {
- .constraints = {
- .name = "VDAC",
- .min_uV = 1800000,
- .max_uV = 2850000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo7_supply),
- .consumer_supplies = tps65910_ldo7_supply,
-};
-
-/* */
-static struct regulator_init_data tps65910_ldo8 = {
- .constraints = {
- .name = "VPLL",
- .min_uV = 1000000,
- .max_uV = 2500000,
- .apply_uV = 1,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65910_ldo8_supply),
- .consumer_supplies = tps65910_ldo8_supply,
-};
-
-void __sramfunc board_pmu_tps65910_suspend(void)
-{
- grf_writel(GPIO6_PB1_DIR_OUT, GRF_GPIO6L_DIR_ADDR);
- grf_writel(GPIO6_PB1_DO_HIGH, GRF_GPIO6L_DO_ADDR); //set gpio6_b1 output low
- grf_writel(GPIO6_PB1_EN_MASK, GRF_GPIO6L_EN_ADDR);
-}
-void __sramfunc board_pmu_tps65910_resume(void)
-{
- grf_writel(GPIO6_PB1_DIR_OUT, GRF_GPIO6L_DIR_ADDR);
- grf_writel(GPIO6_PB1_DO_LOW, GRF_GPIO6L_DO_ADDR); //set gpio6_b1 output low
- grf_writel(GPIO6_PB1_EN_MASK, GRF_GPIO6L_EN_ADDR);
- #ifdef CONFIG_CLK_SWITCH_TO_32K //switch clk to 24M
- sram_32k_udelay(10000);
- #else
- sram_udelay(2000);
- #endif
-}
-
-static struct tps65910_board tps65910_data = {
- .irq = (unsigned)TPS65910_HOST_IRQ,
- .irq_base = IRQ_BOARD_BASE,
- .gpio_base = TPS65910_GPIO_EXPANDER_BASE,
-
- .pre_init = tps65910_pre_init,
- .post_init = tps65910_post_init,
-
- //TPS65910_NUM_REGS = 13
- // Regulators
- .tps65910_pmic_init_data[TPS65910_REG_VRTC] = NULL,
- .tps65910_pmic_init_data[TPS65910_REG_VIO] = &tps65910_smps4,
- .tps65910_pmic_init_data[TPS65910_REG_VDD1] = &tps65910_smps1,
- .tps65910_pmic_init_data[TPS65910_REG_VDD2] = &tps65910_smps2,
- .tps65910_pmic_init_data[TPS65910_REG_VDD3] = &tps65910_smps3,
- .tps65910_pmic_init_data[TPS65910_REG_VDIG1] = &tps65910_ldo1,
- .tps65910_pmic_init_data[TPS65910_REG_VDIG2] = &tps65910_ldo2,
- .tps65910_pmic_init_data[TPS65910_REG_VPLL] = &tps65910_ldo8,
- .tps65910_pmic_init_data[TPS65910_REG_VDAC] = &tps65910_ldo7,
- .tps65910_pmic_init_data[TPS65910_REG_VAUX1] = &tps65910_ldo3,
- .tps65910_pmic_init_data[TPS65910_REG_VAUX2] = &tps65910_ldo4,
- .tps65910_pmic_init_data[TPS65910_REG_VAUX33] = &tps65910_ldo5,
- .tps65910_pmic_init_data[TPS65910_REG_VMMC] = &tps65910_ldo6,
-
-
-};
-
-#endif
-
+++ /dev/null
-#include <linux/regulator/machine.h>
-#include <linux/i2c/twl.h>
-
-#include <mach/sram.h>
-
-#define TWL60xx_IRQ_BASE IRQ_BOARD_BASE
-#ifdef CONFIG_TWL4030_CORE
-#define TWL60xx_BASE_NR_IRQS 24
-#else
-#define TWL60xx_BASE_NR_IRQS 0
-#endif
-#define TWL60xx_IRQ_END (TWL60xx_IRQ_BASE + TWL60xx_BASE_NR_IRQS)
-
-
-#ifdef CONFIG_TWL4030_CORE
-#define VREG_VOLTAGE 3
-#define VREG_VOLTAGE_DVS_SMPS 3
-static inline int twl_reg_read(unsigned base, unsigned slave_subgp, unsigned offset)
-{
- u8 value;
- int status;
- status = twl_i2c_read_u8(slave_subgp,&value, base + offset);
- return (status < 0) ? status : value;
-}
-
-
-static inline int twl_reg_write(unsigned base, unsigned slave_subgp, unsigned offset,
- u8 value)
-{
- return twl_i2c_write_u8(slave_subgp,value, base + offset);
-}
-
-int tps80032_pre_init(void){
- int ret;
- u8 value;
- printk("%s\n", __func__);
-
- return 0;
-
-}
-int tps80032_set_init(void)
-{
- struct regulator *dcdc;
- struct regulator *ldo;
- printk("%s\n", __func__);
-
- ldo = regulator_get(NULL, "ldo1"); //vcca_33
- regulator_set_voltage(ldo, 3300000, 3300000);
- regulator_enable(ldo);
-// printk("%s set ldo1 vcca_33=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo4"); // vdd_11
- regulator_set_voltage(ldo, 1100000, 1100000);
- regulator_enable(ldo);
-// printk("%s set ldo4 vdd_11=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- dcdc = regulator_get(NULL, "smps4");
- regulator_set_voltage(dcdc,3000000,3000000);
- regulator_enable(dcdc);
-// printk("%s set dcdc4 vcc_io=%dmV end\n", __func__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo2"); // vdd_usb11
- regulator_set_voltage(ldo, 1100000, 1100000);
- regulator_enable(ldo);
-// printk("%s set ldo2 vdd_usb11=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo5"); // vcc_25
- regulator_set_voltage(ldo, 2500000, 2500000);
- regulator_enable(ldo);
-// printk("%s set ldo5 vcc_25=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldousb"); // vcc_usb33
- regulator_set_voltage(ldo, 3300000, 3300000);
- regulator_enable(ldo);
-// printk("%s set ldousb vcc_usb33=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- dcdc = regulator_get(NULL, "vdd_cpu"); // vdd_arm
- regulator_set_voltage(dcdc,1100000,1100000);
- regulator_enable(dcdc);
- printk("%s set dcdc1 vdd_cpu=%dmV end\n", __func__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- dcdc = regulator_get(NULL, "vdd_core"); //vdd_log
- regulator_set_voltage(dcdc,1100000,1100000);
- regulator_enable(dcdc);
- printk("%s set dcdc2 vdd_core=%dmV end\n", __func__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- dcdc = regulator_get(NULL, "smps3"); //vcc_ddr
- regulator_set_voltage(dcdc,1800000,1800000);
- regulator_enable(dcdc);
-// printk("%s set dcdc3 vcc_lpddr2_1v8=%dmV end\n", __func__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- dcdc = regulator_get(NULL, "smps5");
- regulator_set_voltage(dcdc,1200000,1200000);
- regulator_enable(dcdc);
-// printk("%s set dcdc5 vcc_lpddr2_1v2=%dmV end\n", __func__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
-
- ldo = regulator_get(NULL, "ldo3"); //vcc_nandflash
- regulator_set_voltage(ldo, 3300000, 3300000);
- regulator_enable(ldo);
-// printk("%s set ldo3 vcc_nandflash=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo6"); //codecvdd_1v8
- regulator_set_voltage(ldo, 1800000, 1800000);
- regulator_enable(ldo);
-// printk("%s set ldo6 codecvdd_1v8=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo7"); //vcc_lcd
- regulator_set_voltage(ldo, 3000000, 3000000);
- regulator_enable(ldo);
-// printk("%s set ldo7 vcc_lcd=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldoln"); //vcccodec_io
- regulator_set_voltage(ldo, 3300000, 3300000);
- regulator_enable(ldo);
-// printk("%s set ldoln vcccodec_io=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-/*
- ldo = regulator_get(NULL, "vana"); //vana_out
- regulator_set_voltage(ldo, 2500000, 2500000);
-// regulator_set_suspend_voltage(ldo, 2500000);
- regulator_enable(ldo);
- printk("%s set vana vana_out=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-*/
-
- printk("tps80032_set_init end.\n");
- return 0;
-}
-
-
-static struct regulator_consumer_supply tps80032_smps1_supply[] = {
- {
- .supply = "vdd_cpu",
- },
-};
-static struct regulator_consumer_supply tps80032_smps2_supply[] = {
- {
- .supply = "vdd_core",
- },
-};
-static struct regulator_consumer_supply tps80032_smps3_supply[] = {
- {
- .supply = "smps3",
- },
-};
-static struct regulator_consumer_supply tps80032_smps4_supply[] = {
- {
- .supply = "smps4",
- },
-};
-static struct regulator_consumer_supply tps80032_smps5_supply[] = {
- {
- .supply = "smps5",
- },
-};
-static struct regulator_consumer_supply tps80032_ldo1_supply[] = {
- {
- .supply = "ldo1",
- },
-};
-static struct regulator_consumer_supply tps80032_ldo2_supply[] = {
- {
- .supply = "ldo2",
- },
-};
-
-static struct regulator_consumer_supply tps80032_ldo3_supply[] = {
- {
- .supply = "ldo3",
- },
-};
-static struct regulator_consumer_supply tps80032_ldo4_supply[] = {
- {
- .supply = "ldo4",
- },
-};
-static struct regulator_consumer_supply tps80032_ldo5_supply[] = {
- {
- .supply = "ldo5",
- },
-};
-static struct regulator_consumer_supply tps80032_ldo6_supply[] = {
- {
- .supply = "ldo6",
- },
-};
-static struct regulator_consumer_supply tps80032_ldo7_supply[] = {
- {
- .supply = "ldo7",
- },
-};
-
-static struct regulator_consumer_supply tps80032_ldoln_supply[] = {
- {
- .supply = "ldoln",
- },
-};
-static struct regulator_consumer_supply tps80032_ldousb_supply[] = {
- {
- .supply = "ldousb",
- },
-};
-static struct regulator_consumer_supply tps80032_ldovana_supply[] = {
- {
- .supply = "vana",
- },
-};
-/* */
-static struct regulator_init_data tps80032_smps1 = {
- .constraints = {
- .name = "SMPS1",
- .min_uV = 600000,
- .max_uV = 2100000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps80032_smps1_supply),
- .consumer_supplies = tps80032_smps1_supply,
-};
-
-/* */
-static struct regulator_init_data tps80032_smps2 = {
- .constraints = {
- .name = "SMPS2",
- .min_uV = 600000,
- .max_uV = 2100000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps80032_smps2_supply),
- .consumer_supplies = tps80032_smps2_supply,
-};
-
-
-
-/* */
-static struct regulator_init_data tps80032_smps3 = {
- .constraints = {
- .name = "SMPS3",
- .min_uV = 600000,
- .max_uV = 2100000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps80032_smps3_supply),
- .consumer_supplies = tps80032_smps3_supply,
-};
-
-
-/* */
-static struct regulator_init_data tps80032_smps4 = {
- .constraints = {
- .name = "SMPS4",
- .min_uV = 600000,
- .max_uV = 2100000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps80032_smps4_supply),
- .consumer_supplies = tps80032_smps4_supply,
-};
-/* */
-static struct regulator_init_data tps80032_smps5 = {
- .constraints = {
- .name = "SMPS5",
- .min_uV = 600000,
- .max_uV = 2100000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps80032_smps5_supply),
- .consumer_supplies = tps80032_smps5_supply,
-};
-static struct regulator_init_data tps80032_ldo1 = {
- .constraints = {
- .name = "LDO1",
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps80032_ldo1_supply),
- .consumer_supplies = tps80032_ldo1_supply,
-};
-
-/* */
-static struct regulator_init_data tps80032_ldo2 = {
- .constraints = {
- .name = "LDO2",
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps80032_ldo2_supply),
- .consumer_supplies = tps80032_ldo2_supply,
-};
-
-/* */
-static struct regulator_init_data tps80032_ldo3 = {
- .constraints = {
- .name = "LDO3",
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps80032_ldo3_supply),
- .consumer_supplies = tps80032_ldo3_supply,
-};
-
-/* */
-static struct regulator_init_data tps80032_ldo4 = {
- .constraints = {
- .name = "LDO4",
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps80032_ldo4_supply),
- .consumer_supplies = tps80032_ldo4_supply,
-};
-
-/* */
-static struct regulator_init_data tps80032_ldo5 = {
- .constraints = {
- .name = "LDO5",
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps80032_ldo5_supply),
- .consumer_supplies = tps80032_ldo5_supply,
-};
-
-/* */
-static struct regulator_init_data tps80032_ldo6 = {
- .constraints = {
- .name = "LDO6",
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps80032_ldo6_supply),
- .consumer_supplies = tps80032_ldo6_supply,
-};
-
-/* */
-static struct regulator_init_data tps80032_ldo7 = {
- .constraints = {
- .name = "LDO7",
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps80032_ldo7_supply),
- .consumer_supplies = tps80032_ldo7_supply,
-};
-
-/* */
-static struct regulator_init_data tps80032_ldoln = {
- .constraints = {
- .name = "LDOLN",
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps80032_ldoln_supply),
- .consumer_supplies = tps80032_ldoln_supply,
-};
-
-/* */
-static struct regulator_init_data tps80032_ldousb = {
- .constraints = {
- .name = "LDOUSB",
- .min_uV = 3300000,
- .max_uV = 3300000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps80032_ldousb_supply),
- .consumer_supplies = tps80032_ldousb_supply,
-};
-
-/* */
-static struct regulator_init_data tps80032_ldovana = {
- .constraints = {
- .name = "LDOVANA",
- .min_uV = 600000,
- .max_uV = 2500000,
- .apply_uV = 1,
-
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
-
- },
- .num_consumer_supplies = ARRAY_SIZE(tps80032_ldovana_supply),
- .consumer_supplies = tps80032_ldovana_supply,
-};
-
-
-static struct twl4030_platform_data tps80032_data = {
- .irq_base = TWL60xx_IRQ_BASE,
- .irq_end = TWL60xx_IRQ_END,
- //.irq = RK29_PIN0_PA1,
- .pre_init = tps80032_pre_init,
- .set_init = tps80032_set_init,
-
- /* Regulators */
- .ldo1 = &tps80032_ldo1,
- .ldo2 = &tps80032_ldo2,
- .ldo3 = &tps80032_ldo3,
- .ldo4 = &tps80032_ldo4,
- .ldo5 = &tps80032_ldo5,
- .ldo6 = &tps80032_ldo6,
- .ldo7 = &tps80032_ldo7,
- .ldoln = &tps80032_ldoln,
- .ldousb =&tps80032_ldousb,
- .vana = &tps80032_ldovana,
-
- .smps1 = &tps80032_smps1,
- .smps2= &tps80032_smps2,
- .smps3 = &tps80032_smps3,
- .smps4 = &tps80032_smps4,
- .smps5 = &tps80032_smps5,
-
-};
-
-#endif
+++ /dev/null
-static rmii_extclk_sel = 0;
-static int rk30_vmac_register_set(void)
-{
- //config rk30 vmac as rmii
- writel_relaxed(0x3 << 16 | 0x2, RK30_GRF_BASE + GRF_SOC_CON1);
- return 0;
-}
-
-static int rk30_rmii_io_init(void)
-{
- int err;
- rk30_mux_api_set(GPIO1D6_CIF1DATA11_NAME, GPIO1D_GPIO1D6);
-
- rk30_mux_api_set(GPIO1D2_CIF1CLKIN_NAME, GPIO1D_GPIO1D2);
- rk30_mux_api_set(GPIO1D1_CIF1HREF_MIIMDCLK_NAME, GPIO1D_MII_MDCLK);
- rk30_mux_api_set(GPIO1D0_CIF1VSYNC_MIIMD_NAME, GPIO1D_MII_MD);
-
- rk30_mux_api_set(GPIO1C7_CIFDATA9_RMIIRXD0_NAME, GPIO1C_RMII_RXD0);
- rk30_mux_api_set(GPIO1C6_CIFDATA8_RMIIRXD1_NAME, GPIO1C_RMII_RXD1);
- rk30_mux_api_set(GPIO1C5_CIFDATA7_RMIICRSDVALID_NAME, GPIO1C_RMII_CRS_DVALID);
- rk30_mux_api_set(GPIO1C4_CIFDATA6_RMIIRXERR_NAME, GPIO1C_RMII_RX_ERR);
- rk30_mux_api_set(GPIO1C3_CIFDATA5_RMIITXD0_NAME, GPIO1C_RMII_TXD0);
- rk30_mux_api_set(GPIO1C2_CIF1DATA4_RMIITXD1_NAME, GPIO1C_RMII_TXD1);
- rk30_mux_api_set(GPIO1C1_CIFDATA3_RMIITXEN_NAME, GPIO1C_RMII_TX_EN);
- rk30_mux_api_set(GPIO1C0_CIF1DATA2_RMIICLKOUT_RMIICLKIN_NAME, GPIO1C_RMII_CLKOUT);
-
- //phy power gpio
- err = gpio_request(PHY_PWR_EN_GPIO, "phy_power_en");
- if (err) {
- return -1;
- }
- //phy power down
- gpio_direction_output(PHY_PWR_EN_GPIO, GPIO_LOW);
- gpio_set_value(PHY_PWR_EN_GPIO, GPIO_LOW);
- return 0;
-}
-
-static int rk30_rmii_io_deinit(void)
-{
- //phy power down
- gpio_direction_output(PHY_PWR_EN_GPIO, GPIO_LOW);
- gpio_set_value(PHY_PWR_EN_GPIO, GPIO_LOW);
- //free
- gpio_free(PHY_PWR_EN_GPIO);
- return 0;
-}
-
-static int rk30_rmii_power_control(int enable)
-{
- if (enable) {
- //enable phy power
- printk("power on phy\n");
- rk30_mux_api_set(GPIO1D6_CIF1DATA11_NAME, GPIO1D_GPIO1D6);
-
- rk30_mux_api_set(GPIO1D2_CIF1CLKIN_NAME, GPIO1D_GPIO1D2);
- rk30_mux_api_set(GPIO1D1_CIF1HREF_MIIMDCLK_NAME, GPIO1D_MII_MDCLK);
- rk30_mux_api_set(GPIO1D0_CIF1VSYNC_MIIMD_NAME, GPIO1D_MII_MD);
-
- rk30_mux_api_set(GPIO1C7_CIFDATA9_RMIIRXD0_NAME, GPIO1C_RMII_RXD0);
- rk30_mux_api_set(GPIO1C6_CIFDATA8_RMIIRXD1_NAME, GPIO1C_RMII_RXD1);
- rk30_mux_api_set(GPIO1C5_CIFDATA7_RMIICRSDVALID_NAME, GPIO1C_RMII_CRS_DVALID);
- rk30_mux_api_set(GPIO1C4_CIFDATA6_RMIIRXERR_NAME, GPIO1C_RMII_RX_ERR);
- rk30_mux_api_set(GPIO1C3_CIFDATA5_RMIITXD0_NAME, GPIO1C_RMII_TXD0);
- rk30_mux_api_set(GPIO1C2_CIF1DATA4_RMIITXD1_NAME, GPIO1C_RMII_TXD1);
- rk30_mux_api_set(GPIO1C1_CIFDATA3_RMIITXEN_NAME, GPIO1C_RMII_TX_EN);
- rk30_mux_api_set(GPIO1C0_CIF1DATA2_RMIICLKOUT_RMIICLKIN_NAME, GPIO1C_RMII_CLKOUT);
- gpio_direction_output(PHY_PWR_EN_GPIO, GPIO_HIGH);
- gpio_set_value(PHY_PWR_EN_GPIO, GPIO_HIGH);
- }else {
- gpio_direction_output(PHY_PWR_EN_GPIO, GPIO_LOW);
- gpio_set_value(PHY_PWR_EN_GPIO, GPIO_LOW);
- }
- return 0;
-}
-
-#define BIT_EMAC_SPEED (1 << 1)
-static int rk29_vmac_speed_switch(int speed)
-{
- //printk("%s--speed=%d\n", __FUNCTION__, speed);
- if (10 == speed) {
- writel_relaxed(readl_relaxed(RK30_GRF_BASE + GRF_SOC_CON1) & (~BIT_EMAC_SPEED), RK30_GRF_BASE + GRF_SOC_CON1);
- } else {
- writel_relaxed(readl_relaxed(RK30_GRF_BASE + GRF_SOC_CON1) | ( BIT_EMAC_SPEED), RK30_GRF_BASE + GRF_SOC_CON1);
- }
-}
-
-static int rk30_rmii_extclk_sel(void)
-{
-#ifdef RMII_EXT_CLK
- rmii_extclk_sel = 1; //0:select internal divider clock, 1:select external input clock
-#endif
- return rmii_extclk_sel;
-}
-
-struct rk29_vmac_platform_data board_vmac_data = {
- .vmac_register_set = rk30_vmac_register_set,
- .rmii_io_init = rk30_rmii_io_init,
- .rmii_io_deinit = rk30_rmii_io_deinit,
- .rmii_power_control = rk30_rmii_power_control,
- .rmii_speed_switch = rk29_vmac_speed_switch,
- .rmii_extclk_sel = rk30_rmii_extclk_sel,
-};
+++ /dev/null
-#include <linux/regulator/machine.h>
-#include <linux/mfd/wm831x/pdata.h>
-#include <linux/mfd/wm831x/core.h>
-#include <linux/mfd/wm831x/gpio.h>
-#include <linux/mfd/wm831x/pmu.h>
-
-#include <mach/sram.h>
-#include <linux/earlysuspend.h>
-
-#define cru_readl(offset) readl_relaxed(RK30_CRU_BASE + offset)
-#define cru_writel(v, offset) do { writel_relaxed(v, RK30_CRU_BASE + offset); dsb(); } while (0)
-
-#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
-
-#define CRU_CLKGATE5_CON_ADDR 0x00e4
-#define GRF_GPIO6L_DIR_ADDR 0x0030
-#define GRF_GPIO6L_DO_ADDR 0x0068
-#define GRF_GPIO6L_EN_ADDR 0x00a0
-#define CRU_CLKGATE5_GRFCLK_ON 0x00100000
-#define CRU_CLKGATE5_GRFCLK_OFF 0x00100010
-#define GPIO6_PB1_DIR_OUT 0x02000200
-#define GPIO6_PB1_DO_LOW 0x02000000
-#define GPIO6_PB1_DO_HIGH 0x02000200
-#define GPIO6_PB1_EN_MASK 0x02000200
-#define GPIO6_PB1_UNEN_MASK 0x02000000
-
-/* wm8326 pmu*/
-#if defined(CONFIG_GPIO_WM831X)
-static struct rk29_gpio_expander_info wm831x_gpio_settinginfo[] = {
- {
- .gpio_num = WM831X_P01, // tp3
- .pin_type = GPIO_OUT,
- .pin_value = GPIO_LOW,
- },
- {
- .gpio_num = WM831X_P02, //tp4
- .pin_type = GPIO_IN,
- },
- {
- .gpio_num = WM831X_P03, //tp2
- .pin_type = GPIO_OUT,
- .pin_value = GPIO_HIGH,
- },
- {
- .gpio_num = WM831X_P04, //tp1
- .pin_type = GPIO_IN,
- },
- {
- .gpio_num = WM831X_P05, //tp1
- .pin_type = GPIO_IN,
- },
- {
- .gpio_num = WM831X_P06, //tp1
- .pin_type = GPIO_OUT,
- .pin_value = GPIO_HIGH,
- },
- {
- .gpio_num = WM831X_P07, //tp1
- .pin_type = GPIO_IN,
- },
- {
- .gpio_num = WM831X_P08, //tp1
- .pin_type = GPIO_OUT,
- .pin_value = GPIO_HIGH,
- },
- {
- .gpio_num = WM831X_P09, //tp1
- .pin_type = GPIO_OUT,
- .pin_value = GPIO_HIGH,
- },
- {
- .gpio_num = WM831X_P10, //tp1
- .pin_type = GPIO_IN,
- },
- {
- .gpio_num = WM831X_P11, //tp1
- .pin_type = GPIO_OUT,
- .pin_value = GPIO_HIGH,
- },
- {
- .gpio_num = WM831X_P12,
- .pin_type = GPIO_OUT,
- .pin_value = GPIO_HIGH,
- },
-};
-#endif
-
-#if defined(CONFIG_MFD_WM831X)
-
-#define UNLOCK_SECURITY_KEY ~(0x1<<5)
-#define LOCK_SECURITY_KEY 0x00
-#define PMU_POWER_SLEEP RK30_PIN6_PB1
-static struct wm831x *Wm831x;
-
-static int wm831x_pre_init(struct wm831x *parm)
-{
- int ret;
- Wm831x = parm;
-// printk("%s\n", __func__);
- gpio_request(PMU_POWER_SLEEP, "NULL");
- gpio_direction_output(PMU_POWER_SLEEP, GPIO_LOW);
-
- #ifdef CONFIG_WM8326_VBAT_LOW_DETECTION
- #ifdef CONFIG_BATTERY_RK30_VOL3V8
- wm831x_set_bits(parm,WM831X_SYSVDD_CONTROL ,0xc077,0xc035); //pvdd power on dect vbat voltage
- printk("+++The vbat is too low+++\n");
- #endif
- #endif
-
- ret = wm831x_reg_read(parm, WM831X_POWER_STATE) & 0xffff;
- wm831x_reg_write(parm, WM831X_POWER_STATE, (ret & 0xfff8) | 0x04);
-
- wm831x_set_bits(parm, WM831X_RTC_CONTROL, WM831X_RTC_ALAM_ENA_MASK, 0x0400);//enable rtc alam
- //BATT_FET_ENA = 1
- wm831x_reg_write(parm, WM831X_SECURITY_KEY, 0x9716); // unlock security key
- wm831x_set_bits(parm, WM831X_RESET_CONTROL, 0x1003, 0x1001);
- ret = wm831x_reg_read(parm, WM831X_RESET_CONTROL) & 0xffff & UNLOCK_SECURITY_KEY; // enternal reset active in sleep
-// printk("%s:WM831X_RESET_CONTROL=0x%x\n", __func__, ret);
- wm831x_reg_write(parm, WM831X_RESET_CONTROL, ret);
-
- wm831x_set_bits(parm,WM831X_DC1_ON_CONFIG ,0x0300,0x0000); //set dcdc mode is FCCM
- wm831x_set_bits(parm,WM831X_DC2_ON_CONFIG ,0x0300,0x0000);
- wm831x_set_bits(parm,WM831X_DC3_ON_CONFIG ,0x0300,0x0000);
- wm831x_set_bits(parm,0x4066,0x0300,0x0000);
-
-#ifndef CONFIG_MACH_RK3066_SDK
- wm831x_set_bits(parm,WM831X_LDO10_CONTROL ,0x0040,0x0040);// set ldo10 in switch mode
-#endif
- wm831x_set_bits(parm,WM831X_STATUS_LED_1 ,0xc300,0xc100);// set led1 on(in manual mode)
- wm831x_set_bits(parm,WM831X_STATUS_LED_2 ,0xc300,0xc000);//set led2 off(in manual mode)
-
- wm831x_set_bits(parm,WM831X_LDO5_SLEEP_CONTROL ,0xe000,0x2000);// set ldo5 is disable in sleep mode
- wm831x_set_bits(parm,WM831X_LDO1_SLEEP_CONTROL ,0xe000,0x2000);// set ldo1 is disable in sleep mode
-
- wm831x_reg_write(parm, WM831X_SECURITY_KEY, LOCK_SECURITY_KEY); // lock security key
-
- return 0;
-}
-static int wm831x_mask_interrupt(struct wm831x *Wm831x)
-{
- /**************************clear interrupt********************/
- wm831x_reg_write(Wm831x,WM831X_INTERRUPT_STATUS_1,0xffff);
- wm831x_reg_write(Wm831x,WM831X_INTERRUPT_STATUS_2,0xffff);
- wm831x_reg_write(Wm831x,WM831X_INTERRUPT_STATUS_3,0xffff);
- wm831x_reg_write(Wm831x,WM831X_INTERRUPT_STATUS_4,0xffff);
- wm831x_reg_write(Wm831x,WM831X_INTERRUPT_STATUS_5,0xffff);
-
- wm831x_reg_write(Wm831x,WM831X_SYSTEM_INTERRUPTS_MASK,0xbedc); //mask interrupt which not used
- return 0;
- /*****************************************************************/
-}
-
-#ifdef CONFIG_WM8326_VBAT_LOW_DETECTION
-static int wm831x_low_power_detection(struct wm831x *wm831x)
-{
- #ifdef CONFIG_BATTERY_RK30_VOL3V8
- wm831x_reg_write(wm831x,WM831X_SYSTEM_INTERRUPTS_MASK,0xbe5c);
- wm831x_set_bits(wm831x,WM831X_INTERRUPT_STATUS_1_MASK,0x8000,0x0000);
- wm831x_set_bits(wm831x,WM831X_SYSVDD_CONTROL ,0xc077,0x0035); //set pvdd low voltage is 3.1v hi voltage is 3.3v
- #else
- wm831x_reg_write(wm831x,WM831X_AUXADC_CONTROL,0x803f); //open adc
- wm831x_reg_write(wm831x,WM831X_AUXADC_CONTROL,0xd03f);
- wm831x_reg_write(wm831x,WM831X_AUXADC_SOURCE,0x0001);
-
- wm831x_reg_write(wm831x,WM831X_COMPARATOR_CONTROL,0x0001);
- wm831x_reg_write(wm831x,WM831X_COMPARATOR_1,0x2844); //set the low power is 3.1v
-
- wm831x_reg_write(wm831x,WM831X_INTERRUPT_STATUS_1_MASK,0x99ee);
- wm831x_set_bits(wm831x,WM831X_SYSTEM_INTERRUPTS_MASK,0x0100,0x0000);
- if (wm831x_reg_read(wm831x,WM831X_AUXADC_DATA)< 0x1844){
- printk("The vbat is too low.\n");
- wm831x_device_shutdown(wm831x);
- }
- #endif
- return 0;
-}
-#endif
-
-#define AVS_BASE 172
-int wm831x_post_init(struct wm831x *Wm831x)
-{
- struct regulator *dcdc;
- struct regulator *ldo;
-
-
- g_pmic_type = PMIC_TYPE_WM8326;
- printk("%s:g_pmic_type=%d\n",__func__,g_pmic_type);
-
- ldo = regulator_get(NULL, "ldo6"); //vcc_33
- regulator_set_voltage(ldo, 3300000, 3300000);
- regulator_set_suspend_voltage(ldo, 3300000);
- regulator_enable(ldo);
-// printk("%s set ldo6 vcc_33=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo4"); // vdd_11
- regulator_set_voltage(ldo, 1100000, 1100000);
- regulator_set_suspend_voltage(ldo, 1000000);
- regulator_enable(ldo);
-// printk("%s set ldo4 vdd_11=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo5"); //vcc_25
- regulator_set_voltage(ldo, 2500000, 2500000);
- regulator_set_suspend_voltage(ldo, 2500000);
- regulator_enable(ldo);
-// printk("%s set ldo5 vcc_25=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
-
- dcdc = regulator_get(NULL, "dcdc4"); // vcc_io
-#ifdef CONFIG_MACH_RK3066_SDK
- regulator_set_voltage(dcdc, 3300000, 3300000);
- regulator_set_suspend_voltage(dcdc, 3100000);
-#else
- regulator_set_voltage(dcdc, 3000000, 3000000);
- regulator_set_suspend_voltage(dcdc, 2800000);
-#endif
- regulator_enable(dcdc);
-// printk("%s set dcdc4 vcc_io=%dmV end\n", __func__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- dcdc = regulator_get(NULL, "vdd_cpu"); // vdd_arm
- regulator_set_voltage(dcdc, 1100000, 1100000);
- regulator_set_suspend_voltage(dcdc, 1000000);
- regulator_enable(dcdc);
- printk("%s set dcdc2 vdd_cpu(vdd_arm)=%dmV end\n", __func__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- dcdc = regulator_get(NULL, "vdd_core"); // vdd_log
-
- /* Read avs value under logic 1.1V*/
- regulator_set_voltage(dcdc, 1100000, 1100000);
- avs_init_val_get(1,1100000,"wm8326 init");
- udelay(600);
- avs_set_scal_val(AVS_BASE);
-
- regulator_set_voltage(dcdc, 1150000, 1150000);
- regulator_set_suspend_voltage(dcdc, 1000000);
- regulator_enable(dcdc);
- printk("%s set dcdc1 vdd_core(vdd_log)=%dmV end\n", __func__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- dcdc = regulator_get(NULL, "dcdc3"); // vcc_ddr
- regulator_set_voltage(dcdc, 1150000, 1150000);
- regulator_set_suspend_voltage(dcdc, 1150000);
- regulator_enable(dcdc);
-// printk("%s set dcdc3 vcc_ddr=%dmV end\n", __func__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo7"); // vcc28_cif
- regulator_set_voltage(ldo, 2800000, 2800000);
- regulator_set_suspend_voltage(ldo, 2800000);
- regulator_enable(ldo);
-// printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo1"); // vcc18_cif
- regulator_set_voltage(ldo, 1800000, 1800000);
- regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(ldo);
-// printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo8"); // vcca_33
- regulator_set_voltage(ldo, 3300000, 3300000);
- regulator_set_suspend_voltage(ldo, 3300000);
- regulator_enable(ldo);
-// printk("%s set ldo8 vcca_33=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo2"); //vccio_wl
- regulator_set_voltage(ldo, 1800000, 1800000);
- regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(ldo);
-// printk("%s set ldo2 vccio_wl=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo10"); //flash io
- regulator_set_voltage(ldo, 1800000, 1800000);
- regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(ldo);
-// printk("%s set ldo10 vcca_wl=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
-#ifdef CONFIG_MACH_RK3066_SDK
- ldo = regulator_get(NULL, "ldo3"); //vdd11_hdmi
- regulator_set_voltage(ldo, 1100000, 1100000);
- regulator_set_suspend_voltage(ldo, 1100000);
-#else
- ldo = regulator_get(NULL, "ldo3"); //vdd_12
- regulator_set_voltage(ldo, 1200000, 1200000);
- regulator_set_suspend_voltage(ldo, 1200000);
-#endif
- regulator_enable(ldo);
-// printk("%s set ldo3 vdd_12=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo9"); //vcc_tp
- regulator_set_voltage(ldo, 3300000, 3300000);
- regulator_set_suspend_voltage(ldo, 3300000);
- regulator_enable(ldo);
-// printk("%s set ldo9 vcc_tp=%dmV end\n", __func__, regulator_get_voltage(ldo));
- regulator_put(ldo);
- udelay(100);
-
- wm831x_mask_interrupt(Wm831x);
-
- #ifdef CONFIG_WM8326_VBAT_LOW_DETECTION
- wm831x_low_power_detection(Wm831x);
- #endif
-
- printk("wm831x_post_init end");
- return 0;
-}
-
-static int wm831x_last_deinit(struct wm831x *Wm831x)
-{
- struct regulator *ldo;
-
- printk("%s\n", __func__);
- ldo = regulator_get(NULL, "ldo1");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo2");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo3");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo4");
- //regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo5");
-// regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo6");
-// regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo7");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo8");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo9");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- ldo = regulator_get(NULL, "ldo10");
- regulator_disable(ldo);
- regulator_put(ldo);
-
- return 0;
-}
-
-struct wm831x_status_pdata wm831x_status_platdata[WM831X_MAX_STATUS] = {
- {
- .default_src = WM831X_STATUS_OTP,
- .name = "wm831x_status0",
- .default_trigger = "wm831x_otp",
- },
- {
- .default_src = WM831X_STATUS_POWER,
- .name = "wm831x_status1",
- .default_trigger = "wm831x_power",
- },
-};
-
-static struct regulator_consumer_supply dcdc1_consumers[] = {
- {
- .supply = "vdd_core",
- }
-};
-
-static struct regulator_consumer_supply dcdc2_consumers[] = {
- {
- .supply = "vdd_cpu",
- }
-
-};
-
-static struct regulator_consumer_supply dcdc3_consumers[] = {
- {
- .supply = "dcdc3",
- }
-};
-
-static struct regulator_consumer_supply dcdc4_consumers[] = {
- {
- .supply = "dcdc4",
- }
-};
-
-#if 0
-static struct regulator_consumer_supply epe1_consumers[] = {
- {
- .supply = "epe1",
- }
-};
-
-static struct regulator_consumer_supply epe2_consumers[] = {
- {
- .supply = "epe2",
- }
-};
-#endif
-
-static struct regulator_consumer_supply ldo1_consumers[] = {
- {
- .supply = "ldo1",
- }
-};
-
-static struct regulator_consumer_supply ldo2_consumers[] = {
- {
- .supply = "ldo2",
- }
-};
-
-static struct regulator_consumer_supply ldo3_consumers[] = {
- {
- .supply = "ldo3",
- }
-};
-
-static struct regulator_consumer_supply ldo4_consumers[] = {
- {
- .supply = "ldo4",
- }
-};
-
-static struct regulator_consumer_supply ldo5_consumers[] = {
- {
- .supply = "ldo5",
- }
-};
-
-static struct regulator_consumer_supply ldo6_consumers[] = {
- {
- .supply = "ldo6",
- }
-};
-
-static struct regulator_consumer_supply ldo7_consumers[] = {
- {
- .supply = "ldo7",
- }
-};
-
-static struct regulator_consumer_supply ldo8_consumers[] = {
- {
- .supply = "ldo8",
- }
-};
-
-static struct regulator_consumer_supply ldo9_consumers[] = {
- {
- .supply = "ldo9",
- }
-};
-
-static struct regulator_consumer_supply ldo10_consumers[] = {
- {
- .supply = "ldo10",
- }
-};
-
-static struct regulator_consumer_supply ldo11_consumers[] = {
- {
- .supply = "ldo11",
- }
-};
-
-struct regulator_init_data wm831x_regulator_init_dcdc[WM831X_MAX_DCDC] = {
- {
- .constraints = {
- .name = "DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL | REGULATOR_MODE_FAST | REGULATOR_MODE_IDLE,
- },
- .num_consumer_supplies = ARRAY_SIZE(dcdc1_consumers),
- .consumer_supplies = dcdc1_consumers,
- },
- {
- .constraints = {
- .name = "DCDC2",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL | REGULATOR_MODE_FAST | REGULATOR_MODE_IDLE,
- },
- .num_consumer_supplies = ARRAY_SIZE(dcdc2_consumers),
- .consumer_supplies = dcdc2_consumers,
- },
- {
- .constraints = {
- .name = "DCDC3",
- .min_uV = 850000,
- .max_uV = 3400000, //0.85-3.4V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL | REGULATOR_MODE_FAST | REGULATOR_MODE_IDLE,
- },
- .num_consumer_supplies = ARRAY_SIZE(dcdc3_consumers),
- .consumer_supplies = dcdc3_consumers,
- },
- {
- .constraints = {
- .name = "DCDC4",
- .min_uV = 850000,
- .max_uV = 3400000, //0.85-3.4V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL | REGULATOR_MODE_FAST | REGULATOR_MODE_IDLE,
- },
- .num_consumer_supplies = ARRAY_SIZE(dcdc4_consumers),
- .consumer_supplies = dcdc4_consumers,
- },
-};
-
-#if 0
-struct regulator_init_data wm831x_regulator_init_epe[WM831X_MAX_EPE] = {
- {
- .constraints = {
- .name = "EPE1",
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(epe1_consumers),
- .consumer_supplies = epe1_consumers,
- },
- {
- .constraints = {
- .name = "EPE2",
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(epe2_consumers),
- .consumer_supplies = epe2_consumers,
- },
-};
-#endif
-
-struct regulator_init_data wm831x_regulator_init_ldo[WM831X_MAX_LDO] = {
- {
- .constraints = {
- .name = "LDO1",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_IDLE | REGULATOR_MODE_NORMAL,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo1_consumers),
- .consumer_supplies = ldo1_consumers,
- },
- {
- .constraints = {
- .name = "LDO2",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_IDLE | REGULATOR_MODE_NORMAL,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
- .consumer_supplies = ldo2_consumers,
- },
- {
- .constraints = {
- .name = "LDO3",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_IDLE | REGULATOR_MODE_NORMAL,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo3_consumers),
- .consumer_supplies = ldo3_consumers,
- },
- {
- .constraints = {
- .name = "LDO4",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_IDLE | REGULATOR_MODE_NORMAL,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo4_consumers),
- .consumer_supplies = ldo4_consumers,
- },
- {
- .constraints = {
- .name = "LDO5",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_IDLE | REGULATOR_MODE_NORMAL,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo5_consumers),
- .consumer_supplies = ldo5_consumers,
- },
- {
- .constraints = {
- .name = "LDO6",
- .min_uV = 900000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_IDLE | REGULATOR_MODE_NORMAL,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo6_consumers),
- .consumer_supplies = ldo6_consumers,
- },
- {
- .constraints = {
- .name = "LDO7",
- .min_uV = 1000000,
- .max_uV = 3500000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_IDLE | REGULATOR_MODE_NORMAL,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo7_consumers),
- .consumer_supplies = ldo7_consumers,
- },
- {
- .constraints = {
- .name = "LDO8",
- .min_uV = 1000000,
- .max_uV = 3500000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_IDLE | REGULATOR_MODE_NORMAL,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo8_consumers),
- .consumer_supplies = ldo8_consumers,
- },
- {
- .constraints = {
- .name = "LDO9",
- .min_uV = 1000000,
- .max_uV = 3500000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_IDLE | REGULATOR_MODE_NORMAL,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo9_consumers),
- .consumer_supplies = ldo9_consumers,
- },
- {
- .constraints = {
- .name = "LDO10",
- .min_uV = 1000000,
- .max_uV = 3500000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_IDLE | REGULATOR_MODE_NORMAL,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo10_consumers),
- .consumer_supplies = ldo10_consumers,
- },
- {
- .constraints = {
- .name = "LDO11",
- .min_uV = 800000,
- .max_uV = 1550000,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_IDLE | REGULATOR_MODE_NORMAL,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo11_consumers),
- .consumer_supplies = ldo11_consumers,
- },
-};
-
-static int wm831x_init_pin_type(struct wm831x *wm831x)
-{
- struct wm831x_pdata *pdata;
- struct rk29_gpio_expander_info *wm831x_gpio_settinginfo;
- uint16_t wm831x_settingpin_num;
- int i;
-
- if (!wm831x || !wm831x->dev)
- goto out;
-
- pdata = wm831x->dev->platform_data;
- if (!pdata)
- goto out;
-
- wm831x_gpio_settinginfo = pdata->settinginfo;
- if (!wm831x_gpio_settinginfo)
- goto out;
-
- wm831x_settingpin_num = pdata->settinginfolen;
- for (i = 0; i < wm831x_settingpin_num; i++) {
- if (wm831x_gpio_settinginfo[i].pin_type == GPIO_IN) {
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_DIR_MASK | WM831X_GPN_TRI_MASK,
- 1 << WM831X_GPN_DIR_SHIFT | 1 << WM831X_GPN_TRI_SHIFT);
- if (i == 1) {
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_POL_MASK,
- 0x0400);
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_FN_MASK,
- 0x0003);
- } // set gpio2 sleep/wakeup
-
- if (i == 9) {
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_PULL_MASK,
- 0x0000); //disable pullup/down
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_PWR_DOM_MASK,
- 0x0800);
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_ENA_MASK,
- 0x0000);
- } //set gpio10 as adc input
-
- } else {
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_DIR_MASK | WM831X_GPN_TRI_MASK,
- 1 << WM831X_GPN_TRI_SHIFT);
- if (wm831x_gpio_settinginfo[i].pin_value == GPIO_HIGH) {
- wm831x_set_bits(wm831x, WM831X_GPIO_LEVEL, 1 << i, 1 << i);
- } else {
- wm831x_set_bits(wm831x, WM831X_GPIO_LEVEL, 1 << i, 0 << i);
- }
- if (i == 2) {
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_PWR_DOM_MASK | WM831X_GPN_POL_MASK |WM831X_GPN_FN_MASK,
- 1 << WM831X_GPN_POL_SHIFT | 1 << WM831X_GPN_PWR_DOM_SHIFT | 1 << 0);
-
- } // set gpio3 as clkout output 32.768K
-
- }
- }
-
-#if 0
- for (i = 0; i < pdata->gpio_pin_num; i++) {
- wm831x_set_bits(wm831x,
- WM831X_GPIO1_CONTROL + i,
- WM831X_GPN_PULL_MASK | WM831X_GPN_POL_MASK | WM831X_GPN_OD_MASK | WM831X_GPN_TRI_MASK,
- 1 << WM831X_GPN_POL_SHIFT | 1 << WM831X_GPN_TRI_SHIFT);
-
- ret = wm831x_reg_read(wm831x, WM831X_GPIO1_CONTROL + i);
- printk("Gpio%d Pin Configuration = %x\n", i, ret);
- }
-#endif
-
-out:
- return 0;
-}
-
-#ifdef CONFIG_HAS_EARLYSUSPEND
-void wm831x_pmu_early_suspend(struct early_suspend *h)
-{
- struct regulator *dcdc;
- struct regulator *ldo;
- printk("%s\n", __func__);
-
- dcdc = regulator_get(NULL, "dcdc4"); //vcc_io
- regulator_set_voltage(dcdc, 2800000, 2800000);
- regulator_set_mode(dcdc, REGULATOR_MODE_STANDBY);
- regulator_enable(dcdc);
- printk("%s set dcdc4 vcc_io=%dmV end\n", __func__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo1"); //
- regulator_set_mode(ldo, REGULATOR_MODE_IDLE);
- regulator_enable(ldo);
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo4");
- regulator_set_mode(ldo, REGULATOR_MODE_IDLE);
- regulator_enable(ldo);
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo6");
- regulator_set_mode(ldo, REGULATOR_MODE_IDLE);
- regulator_enable(ldo);
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo8");
- regulator_set_mode(ldo, REGULATOR_MODE_IDLE);
- regulator_enable(ldo);
- regulator_put(ldo);
- udelay(100);
-
-}
-void wm831x_pmu_early_resume(struct early_suspend *h)
-{
- struct regulator *dcdc;
- struct regulator *ldo;
- printk("%s\n", __func__);
-
- dcdc = regulator_get(NULL, "dcdc4"); //vcc_io
- #ifdef CONFIG_MACH_RK3066_SDK
- regulator_set_voltage(dcdc, 3300000, 3300000);
- #else
- regulator_set_voltage(dcdc, 3000000, 3000000);
- #endif
- regulator_set_mode(dcdc, REGULATOR_MODE_FAST);
- regulator_enable(dcdc);
- printk("%s set dcdc4 vcc_io=%dmV end\n", __func__, regulator_get_voltage(dcdc));
- regulator_put(dcdc);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo1"); //
- regulator_set_mode(ldo, REGULATOR_MODE_NORMAL);
- regulator_enable(ldo);
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo4");
- regulator_set_mode(ldo, REGULATOR_MODE_NORMAL);
- regulator_enable(ldo);
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo6");
- regulator_set_mode(ldo, REGULATOR_MODE_NORMAL);
- regulator_enable(ldo);
- regulator_put(ldo);
- udelay(100);
-
- ldo = regulator_get(NULL, "ldo8");
- regulator_set_mode(ldo, REGULATOR_MODE_NORMAL);
- regulator_enable(ldo);
- regulator_put(ldo);
- udelay(100);
-}
-#else
-void wm831x_pmu_early_suspend(struct regulator_dev *rdev)
-{
-}
-void wm831x_pmu_early_resume(struct regulator_dev *rdev)
-{
-}
-#endif
-
-void __sramfunc board_pmu_wm8326_suspend(void)
-{
- cru_writel(CRU_CLKGATE5_GRFCLK_ON,CRU_CLKGATE5_CON_ADDR); //open grf clk
- grf_writel(GPIO6_PB1_DIR_OUT, GRF_GPIO6L_DIR_ADDR);
- grf_writel(GPIO6_PB1_DO_HIGH, GRF_GPIO6L_DO_ADDR); //set gpio6_b1 output low
- grf_writel(GPIO6_PB1_EN_MASK, GRF_GPIO6L_EN_ADDR);
-}
-void __sramfunc board_pmu_wm8326_resume(void)
-{
- grf_writel(GPIO6_PB1_DIR_OUT, GRF_GPIO6L_DIR_ADDR);
- grf_writel(GPIO6_PB1_DO_LOW, GRF_GPIO6L_DO_ADDR); //set gpio6_b1 output high
- grf_writel(GPIO6_PB1_EN_MASK, GRF_GPIO6L_EN_ADDR);
-#ifdef CONFIG_CLK_SWITCH_TO_32K
- sram_32k_udelay(10000);
-#else
- sram_udelay(10000);
-#endif
-}
-
-static struct wm831x_pdata wm831x_platdata = {
-
- /** Called before subdevices are set up */
- .pre_init = wm831x_pre_init,
- /** Called after subdevices are set up */
- .post_init = wm831x_post_init,
- /** Called before subdevices are power down */
- .last_deinit = wm831x_last_deinit,
-
-#if defined(CONFIG_GPIO_WM831X)
- .gpio_base = WM831X_GPIO_EXPANDER_BASE,
- .gpio_pin_num = WM831X_TOTOL_GPIO_NUM,
- .settinginfo = wm831x_gpio_settinginfo,
- .settinginfolen = ARRAY_SIZE(wm831x_gpio_settinginfo),
- .pin_type_init = wm831x_init_pin_type,
- .irq_base = IRQ_BOARD_BASE,
-#endif
-
- /** LED1 = 0 and so on */
- .status = { &wm831x_status_platdata[0], &wm831x_status_platdata[1] },
-
- /** DCDC1 = 0 and so on */
- .dcdc = {
- &wm831x_regulator_init_dcdc[0],
- &wm831x_regulator_init_dcdc[1],
- &wm831x_regulator_init_dcdc[2],
- &wm831x_regulator_init_dcdc[3],
- },
-
- /** EPE1 = 0 and so on */
- //.epe = { &wm831x_regulator_init_epe[0], &wm831x_regulator_init_epe[1] },
-
- /** LDO1 = 0 and so on */
- .ldo = {
- &wm831x_regulator_init_ldo[0],
- &wm831x_regulator_init_ldo[1],
- &wm831x_regulator_init_ldo[2],
- &wm831x_regulator_init_ldo[3],
- &wm831x_regulator_init_ldo[4],
- &wm831x_regulator_init_ldo[5],
- &wm831x_regulator_init_ldo[6],
- &wm831x_regulator_init_ldo[7],
- &wm831x_regulator_init_ldo[8],
- &wm831x_regulator_init_ldo[9],
- &wm831x_regulator_init_ldo[10],
- },
-};
-#endif
+++ /dev/null
-/* arch/arm/mach-rk30/board-rk30-sdk.c
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <mach/dvfs.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-
-#include "../../../drivers/headset_observe/rk_headset.h"
-#if defined(CONFIG_MFD_RK610)
-#include <linux/mfd/rk610_core.h>
-#endif
-
-#if defined(CONFIG_RK_HDMI)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-#if defined(CONFIG_MU509)
-#include <linux/mu509.h>
-#endif
-#if defined(CONFIG_MT6229)
-#include <linux/mt6229.h>
-#endif
-#if defined(CONFIG_MW100)
-#include <linux/mw100.h>
-#endif
-#if defined (CONFIG_BP_AUTO)
-#include <linux/bp-auto.h>
-#endif
-#if defined(CONFIG_SEW868)
-#include <linux/sew868.h>
-#endif
-#if defined(CONFIG_ANDROID_TIMED_GPIO)
-#include "../../../drivers/staging/android/timed_gpio.h"
-#endif
-
-/* Android Parameter */
-static int ap_mdm = 0;
-module_param(ap_mdm, int, 0644);
-static int ap_has_alsa = 0;
-module_param(ap_has_alsa, int, 0644);
-static int ap_data_only = 2;
-module_param(ap_data_only, int, 0644);
-static int ap_has_earphone = 0;
-module_param(ap_has_earphone, int, 0644);
-
-#if defined(CONFIG_MT6620)
-#include <linux/gps.h>
-#endif
-
-#if defined(CONFIG_DP501) //for display port transmitter dp501
-#include<linux/dp501.h>
-#endif
-
-#include "board-rk30-sdk-camera.c"
-
-#include <plat/key.h>
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .gpio = RK30_PIN4_PC5,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK30_PIN6_PA2,
- .active_low = PRESS_LEV_LOW,
- //.code_long_press = EV_ENCALL,
- .wakeup = 1,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .adc_value = 1,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-#ifndef RK3000_SDK
- {
- .desc = "menu",
- .code = EV_MENU,
- .adc_value = 135,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .adc_value = 550,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .adc_value = 334,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "camera",
- .code = KEY_CAMERA,
- .adc_value = 743,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-#else
- {
- .desc = "menu",
- .code = EV_MENU,
- .adc_value = 155,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .adc_value = 630,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .adc_value = 386,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "camera",
- .code = KEY_CAMERA,
- .adc_value = 827,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-#endif
-};
-
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = 1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
-#if defined (CONFIG_RK_HEADSET_DET) || defined (CONFIG_RK_HEADSET_IRQ_HOOK_ADC_DET)
-
-static int rk_headset_io_init(int gpio)
-{
- int ret;
- ret = gpio_request(gpio, "headset_input");
- if(ret)
- return ret;
-
- rk30_mux_api_set(GPIO0C7_TRACECTL_SMCADDR3_NAME, GPIO0C_GPIO0C7);
- gpio_pull_updown(gpio, PullDisable);
- gpio_direction_input(gpio);
- mdelay(50);
- return 0;
-};
-
-struct rk_headset_pdata rk_headset_info = {
- .Headset_gpio = RK30_PIN0_PC7,
- .headset_in_type = HEADSET_IN_LOW,
- .Hook_adc_chn = 2,
- .hook_key_code = KEY_MEDIA,
- .headset_io_init = rk_headset_io_init,
-};
-
-struct platform_device rk_device_headset = {
- .name = "rk_headsetdet",
- .id = 0,
- .dev = {
- .platform_data = &rk_headset_info,
- }
-};
-#endif
-#if defined(CONFIG_TOUCHSCREEN_GT8XX)
-#define TOUCH_RESET_PIN RK30_PIN4_PD0
-#define TOUCH_PWR_PIN INVALID_GPIO
-int goodix_init_platform_hw(void)
-{
- int ret;
-
- rk30_mux_api_set(GPIO4D0_SMCDATA8_TRACEDATA8_NAME, GPIO4D_GPIO4D0);
- rk30_mux_api_set(GPIO4C2_SMCDATA2_TRACEDATA2_NAME, GPIO4C_GPIO4C2);
- printk("%s:0x%x,0x%x\n",__func__,rk30_mux_api_get(GPIO4D0_SMCDATA8_TRACEDATA8_NAME),rk30_mux_api_get(GPIO4C2_SMCDATA2_TRACEDATA2_NAME));
-
- if (TOUCH_PWR_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_PWR_PIN, "goodix power pin");
- if (ret != 0) {
- gpio_free(TOUCH_PWR_PIN);
- printk("goodix power error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_PWR_PIN, 0);
- gpio_set_value(TOUCH_PWR_PIN, GPIO_LOW);
- msleep(100);
- }
-
- if (TOUCH_RESET_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_RESET_PIN, "goodix reset pin");
- if (ret != 0) {
- gpio_free(TOUCH_RESET_PIN);
- printk("goodix gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, 1);
- msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_LOW);
- //msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_HIGH);
- //msleep(500);
- }
- return 0;
-}
-
-struct goodix_platform_data goodix_info = {
- .model = 8105,
- .irq_pin = RK30_PIN4_PC2,
- .rest_pin = TOUCH_RESET_PIN,
- .init_platform_hw = goodix_init_platform_hw,
-};
-#endif
-
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-#define PWM_ID 0
-#define PWM_MUX_NAME GPIO0A3_PWM0_NAME
-#define PWM_MUX_MODE GPIO0A_PWM0
-#define PWM_MUX_MODE_GPIO GPIO0A_GPIO0A3
-#define PWM_GPIO RK30_PIN0_PA3
-#define PWM_EFFECT_VALUE 1
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-//#define BL_EN_MUX_NAME GPIOF34_UART3_SEL_NAME
-//#define BL_EN_MUX_MODE IOMUXB_GPIO1_B34
-
-#define BL_EN_PIN RK30_PIN6_PB3
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
-#ifdef LCD_DISP_ON_PIN
- // rk30_mux_api_set(BL_EN_MUX_NAME, BL_EN_MUX_MODE);
-
- ret = gpio_request(BL_EN_PIN, NULL);
- if (ret != 0) {
- gpio_free(BL_EN_PIN);
- }
-
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0;
-#ifdef LCD_DISP_ON_PIN
- gpio_free(BL_EN_PIN);
-#endif
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret = 0;
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
- if (gpio_request(PWM_GPIO, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- gpio_direction_input(PWM_GPIO);
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, !BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- gpio_free(PWM_GPIO);
- rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
-#ifdef LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, 1);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-#endif
-
-#if defined (CONFIG_SND_SOC_RT3224) || defined (CONFIG_SND_SOC_RT3261)
-
-#define DIFFERENTIAL 1
-#define SINGLE_END 0
-#define TWO_SPK 2
-#define ONE_SPK 1
-
-enum {
- SPK_AMPLIFY_ZERO_POINT_FIVE_WATT=1,
- SPK_AMPLIFY_ZERO_POINT_SIX_WATT,
- SPK_AMPLIFY_ZERO_POINT_EIGHT_WATT,
- SPK_AMPLIFY_ONE_WATT,
-};
-
-enum {
- LR_NORMAL,
- LR_SWAP,
- LEFT_COPY_TO_RIGHT,
- RIGHT_COPY_LEFT,
-};
-
-static int rt3261_io_init(int gpio, char *iomux_name, int iomux_mode)
-{
- gpio_request(gpio,NULL);
- rk30_mux_api_set(iomux_name, iomux_mode);
- gpio_direction_output(gpio,1);
-
-};
-
-static struct rt3261_platform_data rt3261_info = {
- .codec_en_gpio = RK30_PIN4_PD7,
- .codec_en_gpio_info = {GPIO4D7_SMCDATA15_TRACEDATA15_NAME,GPIO4D_GPIO4D7},
- .io_init = rt3261_io_init,
- .spk_num = TWO_SPK,
- .modem_input_mode = DIFFERENTIAL,
- .lout_to_modem_mode = DIFFERENTIAL,
- .spk_amplify = SPK_AMPLIFY_ZERO_POINT_SIX_WATT,
- .playback_if1_data_control = LR_NORMAL,
- .playback_if2_data_control = LR_NORMAL,
-};
-#endif
-
-#if defined(CONFIG_BP_AUTO)
-static int bp_io_init(void)
-{
- rk30_mux_api_set(GPIO2B6_LCDC1DATA14_SMCADDR18_TSSYNC_NAME, GPIO2B_GPIO2B6);
- rk30_mux_api_set(GPIO4D2_SMCDATA10_TRACEDATA10_NAME, GPIO4D_GPIO4D2);
- rk30_mux_api_set(GPIO4C6_SMCDATA6_TRACEDATA6_NAME, GPIO4C_GPIO4C6);
- rk30_mux_api_set(GPIO4C4_SMCDATA4_TRACEDATA4_NAME, GPIO4C_GPIO4C4);
- //rk30_mux_api_set(GPIO2B7_LCDC1DATA15_SMCADDR19_HSADCDATA7_NAME, GPIO2B_GPIO2B7);
- //rk30_mux_api_set(GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME, GPIO2C_GPIO2C0);
- return 0;
-}
-
-static int bp_io_deinit(void)
-{
-
- return 0;
-}
-static int bp_id_get(void)
-{
- return ap_mdm; //internally 3G modem ID, defined in include\linux\Bp-auto.h
-}
-
-struct bp_platform_data bp_auto_info = {
- .init_platform_hw = bp_io_init,
- .exit_platform_hw = bp_io_deinit,
- .get_bp_id = bp_id_get,
- .bp_power = RK30_PIN6_PB2, // 3g_power
- .bp_en = RK30_PIN2_PB6, // 3g_en
- .bp_reset = RK30_PIN4_PD2,
- .bp_usb_en = BP_UNKNOW_DATA, //W_disable
- .bp_uart_en = BP_UNKNOW_DATA, //EINT9
- .bp_wakeup_ap = RK30_PIN4_PC6, //
- .ap_wakeup_bp = RK30_PIN4_PC4,
- .ap_ready = BP_UNKNOW_DATA, //
- .bp_ready = BP_UNKNOW_DATA,
- .gpio_valid = 1, //if 1:gpio is define in bp_auto_info,if 0:is not use gpio in bp_auto_info
-};
-
-struct platform_device device_bp_auto = {
- .name = "bp-auto",
- .id = -1,
- .dev = {
- .platform_data = &bp_auto_info,
- }
- };
-#endif
-#ifdef CONFIG_RK29_SUPPORT_MODEM
-
-#define RK30_MODEM_POWER RK30_PIN4_PD1
-#define RK30_MODEM_POWER_IOMUX rk29_mux_api_set(GPIO4D1_SMCDATA9_TRACEDATA9_NAME, GPIO4D_GPIO4D1)
-
-static int rk30_modem_io_init(void)
-{
- printk("%s\n", __FUNCTION__);
- RK30_MODEM_POWER_IOMUX;
-
- return 0;
-}
-
-static struct rk29_io_t rk30_modem_io = {
- .io_addr = RK30_MODEM_POWER,
- .enable = GPIO_HIGH,
- .disable = GPIO_LOW,
- .io_init = rk30_modem_io_init,
-};
-
-static struct platform_device rk30_device_modem = {
- .name = "rk30_modem",
- .id = -1,
- .dev = {
- .platform_data = &rk30_modem_io,
- }
-};
-#endif
-#if defined(CONFIG_MU509)
-static int mu509_io_init(void)
-{
-
- rk30_mux_api_set(GPIO2B6_LCDC1DATA14_SMCADDR18_TSSYNC_NAME, GPIO2B_GPIO2B6);
- rk30_mux_api_set(GPIO4D2_SMCDATA10_TRACEDATA10_NAME, GPIO4D_GPIO4D2);
- rk30_mux_api_set(GPIO2B7_LCDC1DATA15_SMCADDR19_HSADCDATA7_NAME, GPIO2B_GPIO2B7);
- rk30_mux_api_set(GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME, GPIO2C_GPIO2C0);
- return 0;
-}
-
-static int mu509_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mu509_data rk29_mu509_info = {
- .io_init = mu509_io_init,
- .io_deinit = mu509_io_deinit,
- .modem_power_en = RK30_PIN6_PB2,//RK30_PIN4_PD1,
- .bp_power = RK30_PIN2_PB6,//RK30_PIN4_PD1,
- .bp_reset = RK30_PIN4_PD2,
- .ap_wakeup_bp = RK30_PIN2_PB7,
- .bp_wakeup_ap = RK30_PIN6_PA0,
-};
-struct platform_device rk29_device_mu509 = {
- .name = "mu509",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mu509_info,
- }
- };
-#endif
-#if defined(CONFIG_MW100)
-static int mw100_io_init(void)
-{
- rk30_mux_api_set(GPIO2B6_LCDC1DATA14_SMCADDR18_TSSYNC_NAME, GPIO2B_GPIO2B6);
- rk30_mux_api_set(GPIO4D2_SMCDATA10_TRACEDATA10_NAME, GPIO4D_GPIO4D2);
- rk30_mux_api_set(GPIO2B7_LCDC1DATA15_SMCADDR19_HSADCDATA7_NAME, GPIO2B_GPIO2B7);
- rk30_mux_api_set(GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME, GPIO2C_GPIO2C0);
- return 0;
-}
-
-static int mw100_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mw100_data rk29_mw100_info = {
- .io_init = mw100_io_init,
- .io_deinit = mw100_io_deinit,
- .modem_power_en = RK30_PIN6_PB2,
- .bp_power = RK30_PIN2_PB6,
- .bp_reset = RK30_PIN4_PD2,
- .ap_wakeup_bp = RK30_PIN2_PB7,
- .bp_wakeup_ap = RK30_PIN6_PA0,
-};
-struct platform_device rk29_device_mw100 = {
- .name = "mw100",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mw100_info,
- }
- };
-#endif
-#if defined(CONFIG_MT6229)
-static int mt6229_io_init(void)
-{
- rk30_mux_api_set(GPIO2B6_LCDC1DATA14_SMCADDR18_TSSYNC_NAME, GPIO2B_GPIO2B6);
- rk30_mux_api_set(GPIO4D2_SMCDATA10_TRACEDATA10_NAME, GPIO4D_GPIO4D2);
- rk30_mux_api_set(GPIO2B7_LCDC1DATA15_SMCADDR19_HSADCDATA7_NAME, GPIO2B_GPIO2B7);
- rk30_mux_api_set(GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME, GPIO2C_GPIO2C0);
- rk30_mux_api_set(GPIO2C1_LCDC1DATA17_SMCBLSN0_HSADCDATA6_NAME, GPIO2C_GPIO2C1);
- rk30_mux_api_set(GPIO2C1_LCDC1DATA17_SMCBLSN0_HSADCDATA6_NAME, GPIO2C_GPIO2C1);
- return 0;
-
- return 0;
-}
-
-static int mt6229_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mt6229_data rk29_mt6229_info = {
- .io_init = mt6229_io_init,
- .io_deinit = mt6229_io_deinit,
- .modem_power_en = RK30_PIN6_PB2,
- .bp_power = RK30_PIN2_PB6,
- .modem_usb_en = RK30_PIN2_PC0,
- .modem_uart_en = RK30_PIN2_PC1,
- .bp_wakeup_ap = RK30_PIN6_PA1,
- .ap_ready = RK30_PIN2_PB7,
-
-};
-struct platform_device rk29_device_mt6229 = {
- .name = "mt6229",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mt6229_info,
- }
- };
-#endif
-#if defined(CONFIG_SEW868)
-static int sew868_io_init(void)
-{
- rk30_mux_api_set(GPIO2B6_LCDC1DATA14_SMCADDR18_TSSYNC_NAME, GPIO2B_GPIO2B6);
- rk30_mux_api_set(GPIO4D2_SMCDATA10_TRACEDATA10_NAME, GPIO4D_GPIO4D2);
- rk30_mux_api_set(GPIO4D4_SMCDATA12_TRACEDATA12_NAME, GPIO4D_GPIO4D4);
- return 0;
-}
-static int sew868_io_deinit(void)
-{
- return 0;
-}
-struct rk30_sew868_data rk30_sew868_info = {
- .io_init = sew868_io_init,
- .io_deinit = sew868_io_deinit,
- .bp_power = RK30_PIN6_PB2,
- .bp_power_active_low = 1,
- .bp_sys = RK30_PIN2_PB6,
- .bp_reset = RK30_PIN4_PD2,
- .bp_reset_active_low = 1,
- .bp_wakeup_ap = RK30_PIN4_PD4,
- .ap_wakeup_bp = NULL,
-};
-
-struct platform_device rk30_device_sew868 = {
- .name = "sew868",
- .id = -1,
- .dev = {
- .platform_data = &rk30_sew868_info,
- }
- };
-#endif
-
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN RK30_PIN4_PC0
-
-static int mma8452_init_platform_hw(void)
-{
- rk30_mux_api_set(GPIO4C0_SMCDATA0_TRACEDATA0_NAME, GPIO4C_GPIO4C0);
-
- return 0;
-}
-
-static struct sensor_platform_data mma8452_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma8452_init_platform_hw,
- .orientation = {-1, 0, 0, 0,-1, 0, 0, 0, 1},
-};
-#endif
-#if defined (CONFIG_GS_LIS3DH)
-#define LIS3DH_INT_PIN RK30_PIN4_PC0
-
-static int lis3dh_init_platform_hw(void)
-{
- rk30_mux_api_set(GPIO4C0_SMCDATA0_TRACEDATA0_NAME, GPIO4C_GPIO4C0);
-
- return 0;
-}
-
-static struct sensor_platform_data lis3dh_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lis3dh_init_platform_hw,
- .orientation = {-1, 0, 0, 0, -1, 0, 0, 0, 1},
-};
-#endif
-#if defined (CONFIG_GS_KXTIK)
-#define KXTIK_INT_PIN RK30_PIN4_PC0
-
-static int kxtik_init_platform_hw(void)
-{
- rk30_mux_api_set(GPIO4C0_SMCDATA0_TRACEDATA0_NAME, GPIO4C_GPIO4C0);
-
- return 0;
-}
-
-static struct sensor_platform_data kxtik_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = kxtik_init_platform_hw,
- .orientation = {0, 1, 0, 0, 0, -1, 1, 0, 0},
-};
-
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
-static struct sensor_platform_data akm8975_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-#if defined(CONFIG_GYRO_L3G4200D)
-
-#include <linux/l3g4200d.h>
-#define L3G4200D_INT_PIN RK30_PIN4_PC3
-
-static int l3g4200d_init_platform_hw(void)
-{
- rk30_mux_api_set(GPIO4C3_SMCDATA3_TRACEDATA3_NAME, GPIO4C_GPIO4C3);
-
- return 0;
-}
-
-static struct sensor_platform_data l3g4200d_info = {
- .type = SENSOR_TYPE_GYROSCOPE,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
- .init_platform_hw = l3g4200d_init_platform_hw,
- .x_min = 40,//x_min,y_min,z_min = (0-100) according to hardware
- .y_min = 40,
- .z_min = 20,
-};
-
-#endif
-
-#ifdef CONFIG_LS_CM3217
-static struct sensor_platform_data cm3217_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 0,
- .poll_delay_ms = 500,
-};
-
-#endif
-
-#if defined(CONFIG_PS_AL3006)
-static struct sensor_platform_data proximity_al3006_info = {
- .type = SENSOR_TYPE_PROXIMITY,
- .irq_enable = 1,
- .poll_delay_ms = 200,
-};
-#endif
-
-#if defined(CONFIG_PS_STK3171)
-static struct sensor_platform_data proximity_stk3171_info = {
- .type = SENSOR_TYPE_PROXIMITY,
- .irq_enable = 1,
- .poll_delay_ms = 200,
-};
-#endif
-
-
-#if defined(CONFIG_LS_AL3006)
-static struct sensor_platform_data light_al3006_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 1,
- .poll_delay_ms = 200,
-};
-#endif
-
-#if defined(CONFIG_LS_STK3171)
-static struct sensor_platform_data light_stk3171_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 1,
- .poll_delay_ms = 200,
-};
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
-
-#define LCD_CS_PIN RK30_PIN4_PC7
-#define LCD_CS_VALUE GPIO_HIGH
-
-#define LCD_EN_PIN RK30_PIN6_PB4
-#define LCD_EN_VALUE GPIO_LOW
-
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
-
- if(LCD_CS_PIN != INVALID_GPIO)
- {
- ret = gpio_request(LCD_CS_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_CS_PIN);
- printk(KERN_ERR "request lcd cs pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_CS_PIN, LCD_CS_VALUE);
- }
- }
-
- if(LCD_EN_PIN != INVALID_GPIO)
- {
- ret = gpio_request(LCD_EN_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_EN_PIN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_EN_PIN, LCD_EN_VALUE);
- }
- }
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
- if(LCD_CS_PIN != INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, !LCD_CS_VALUE);
- }
-
- if(LCD_EN_PIN != INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, !LCD_EN_VALUE);
- }
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- if(LCD_CS_PIN != INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE);
- }
- if(LCD_EN_PIN != INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
- }
- return 0;
-}
-
-#if defined(CONFIG_LCDC0_RK30)
-struct rk29fb_info lcdc0_screen_info = {
-#if defined(CONFIG_RK_HDMI) && defined(CONFIG_HDMI_SOURCE_LCDC0) && defined(CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL)
- .prop = EXTEND, //extend display device
- .io_init = NULL,
- .io_disable = NULL,
- .io_enable = NULL,
- .set_screen_info = hdmi_init_lcdc,
-#else
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-#endif
-
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK30)
-struct rk29fb_info lcdc1_screen_info = {
-#if defined(CONFIG_RK_HDMI) && defined(CONFIG_HDMI_SOURCE_LCDC1) && defined(CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL)
- .prop = EXTEND, //extend display device
- .io_init = NULL,
- .io_disable = NULL,
- .io_enable = NULL,
- .set_screen_info = hdmi_init_lcdc,
-#else
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-#endif
-
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-
-#if defined(CONFIG_LCDC0_RK30)
-static struct resource resource_lcdc0[] = {
- [0] = {
- .name = "lcdc0 reg",
- .start = RK30_LCDC0_PHYS,
- .end = RK30_LCDC0_PHYS + RK30_LCDC0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc0 irq",
- .start = IRQ_LCDC0,
- .end = IRQ_LCDC0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc0 = {
- .name = "rk30-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc0),
- .resource = resource_lcdc0,
- .dev = {
- .platform_data = &lcdc0_screen_info,
- },
-};
-#endif
-#if defined(CONFIG_LCDC1_RK30)
-extern struct rk29fb_info lcdc1_screen_info;
-static struct resource resource_lcdc1[] = {
- [0] = {
- .name = "lcdc1 reg",
- .start = RK30_LCDC1_PHYS,
- .end = RK30_LCDC1_PHYS + RK30_LCDC1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc1 irq",
- .start = IRQ_LCDC1,
- .end = IRQ_LCDC1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc1 = {
- .name = "rk30-lcdc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resource_lcdc1),
- .resource = resource_lcdc1,
- .dev = {
- .platform_data = &lcdc1_screen_info,
- },
-};
-#endif
-
-#if defined(CONFIG_DP501)
- #define DVDD33_EN_PIN RK30_PIN6_PB4
- #define DVDD33_EN_VALUE GPIO_LOW
-
- #define DVDD12_EN_PIN RK30_PIN4_PC7
- #define DVDD12_EN_VALUE GPIO_HIGH
-
- #define EDP_RST_PIN RK30_PIN2_PC4
- static int rk_edp_power_ctl(void)
- {
- int ret;
- ret = gpio_request(DVDD33_EN_PIN, "dvdd33_en_pin");
- if (ret != 0)
- {
- gpio_free(DVDD33_EN_PIN);
- printk(KERN_ERR "request dvdd33 en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(DVDD33_EN_PIN, DVDD33_EN_VALUE);
- }
-
- ret = gpio_request(DVDD12_EN_PIN, "dvdd18_en_pin");
- if (ret != 0)
- {
- gpio_free(DVDD12_EN_PIN);
- printk(KERN_ERR "request dvdd18 en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(DVDD12_EN_PIN, DVDD12_EN_VALUE);
- }
-
- ret = gpio_request(EDP_RST_PIN, "edp_rst_pin");
- if (ret != 0)
- {
- gpio_free(EDP_RST_PIN);
- printk(KERN_ERR "request rst pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(EDP_RST_PIN, GPIO_LOW);
- msleep(10);
- gpio_direction_output(EDP_RST_PIN, GPIO_HIGH);
- }
- return 0;
-
- }
- static struct dp501_platform_data dp501_platform_data = {
- .power_ctl = rk_edp_power_ctl,
- .dvdd33_en_pin = DVDD33_EN_PIN,
- .dvdd33_en_val = DVDD33_EN_VALUE,
- .dvdd18_en_pin = DVDD12_EN_PIN,
- .dvdd18_en_val = DVDD12_EN_VALUE,
- .edp_rst_pin = EDP_RST_PIN,
- };
-#endif
-
-#if defined(CONFIG_MFD_RK610)
-#define RK610_RST_PIN_MUX_NAME GPIO0C6_TRACECLK_SMCADDR2_NAME
-#define RK610_RST_PIN_MUX_MODE GPIO0C_GPIO0C6
-#define RK610_RST_PIN RK30_PIN0_PC6
-static int rk610_power_on_init(void)
-{
- int ret;
- if(RK610_RST_PIN != INVALID_GPIO)
- {
- rk30_mux_api_set(RK610_RST_PIN_MUX_NAME,RK610_RST_PIN_MUX_MODE);
- ret = gpio_request(RK610_RST_PIN, "rk610 reset");
- if (ret)
- {
- printk(KERN_ERR "rk610_control_probe request gpio fail\n");
- }
- else
- {
- gpio_direction_output(RK610_RST_PIN, GPIO_HIGH);
- msleep(100);
- gpio_direction_output(RK610_RST_PIN, GPIO_LOW);
- msleep(100);
- gpio_set_value(RK610_RST_PIN, GPIO_HIGH);
- }
- }
-
- return 0;
-
-}
-
-
-static struct rk610_ctl_platform_data rk610_ctl_pdata = {
- .rk610_power_on_init = rk610_power_on_init,
-};
-#endif
-#ifdef CONFIG_SND_SOC_RK610
-static int rk610_codec_io_init(void)
-{
-//if need iomux.
-//Must not gpio_request
- return 0;
-}
-
-static struct rk610_codec_platform_data rk610_codec_pdata = {
- .spk_ctl_io = RK30_PIN4_PC6,
- .io_init = rk610_codec_io_init,
-};
-#endif
-#ifdef CONFIG_ANDROID_TIMED_GPIO
-static struct timed_gpio timed_gpios[] = {
- {
- .name = "vibrator",
- .gpio = RK30_PIN0_PA4,
- .max_timeout = 1000,
- .active_low = 0,
- .adjust_time =20, //adjust for diff product
- },
-};
-
-static struct timed_gpio_platform_data rk29_vibrator_info = {
- .num_gpios = 1,
- .gpios = timed_gpios,
-};
-
-static struct platform_device rk29_device_vibrator = {
- .name = "timed-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_vibrator_info,
- },
-
-};
-#endif
-
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
-static struct gpio_led rk29_leds[] = {
- {
- .name = "button-backlight",
- .gpio = RK30_PIN4_PD7,
- .default_trigger = "timer",
- .active_low = 0,
- .retain_state_suspended = 0,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- },
-};
-
-static struct gpio_led_platform_data rk29_leds_pdata = {
- .leds = rk29_leds,
- .num_leds = ARRAY_SIZE(rk29_leds),
-};
-
-static struct platform_device rk29_device_gpio_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_leds_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_RK_IRDA
-#define IRDA_IRQ_PIN RK30_PIN6_PA1
-
-static int irda_iomux_init(void)
-{
- int ret = 0;
-
- //irda irq pin
- ret = gpio_request(IRDA_IRQ_PIN, NULL);
- if (ret != 0) {
- gpio_free(IRDA_IRQ_PIN);
- printk(">>>>>> IRDA_IRQ_PIN gpio_request err \n ");
- }
- gpio_pull_updown(IRDA_IRQ_PIN, PullDisable);
- gpio_direction_input(IRDA_IRQ_PIN);
-
- return 0;
-}
-
-static int irda_iomux_deinit(void)
-{
- gpio_free(IRDA_IRQ_PIN);
- return 0;
-}
-
-static struct irda_info rk29_irda_info = {
- .intr_pin = IRDA_IRQ_PIN,
- .iomux_init = irda_iomux_init,
- .iomux_deinit = irda_iomux_deinit,
- //.irda_pwr_ctl = bu92747guw_power_ctl,
-};
-
-static struct platform_device irda_device = {
-#ifdef CONFIG_RK_IRDA_NET
- .name = "rk_irda",
-#else
- .name = "bu92747_irda",
-#endif
- .id = -1,
- .dev = {
- .platform_data = &rk29_irda_info,
- }
-};
-#endif
-
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and SDIO.noted by xbw at 2012-03-05
-**************************************************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "board-rk30-sdk-sdmmc.c"
-#endif
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- rk30_mux_api_set(GPIO3B1_SDMMC0CMD_NAME, GPIO3B_SDMMC0_CMD);
- rk30_mux_api_set(GPIO3B0_SDMMC0CLKOUT_NAME, GPIO3B_SDMMC0_CLKOUT);
- rk30_mux_api_set(GPIO3B2_SDMMC0DATA0_NAME, GPIO3B_SDMMC0_DATA0);
- rk30_mux_api_set(GPIO3B3_SDMMC0DATA1_NAME, GPIO3B_SDMMC0_DATA1);
- rk30_mux_api_set(GPIO3B4_SDMMC0DATA2_NAME, GPIO3B_SDMMC0_DATA2);
- rk30_mux_api_set(GPIO3B5_SDMMC0DATA3_NAME, GPIO3B_SDMMC0_DATA3);
-
- rk30_mux_api_set(GPIO3B6_SDMMC0DETECTN_NAME, GPIO3B_GPIO3B6);
-
- rk30_mux_api_set(GPIO3A7_SDMMC0PWREN_NAME, GPIO3A_GPIO3A7);
- gpio_request(RK30_PIN3_PA7, "sdmmc-power");
- gpio_direction_output(RK30_PIN3_PA7, GPIO_LOW);
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- #if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO);
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FMUX);
- #endif
-
- #if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
- #endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) && defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- .status = rk29sdk_wifi_mmc0_status,
- .register_status_notify = rk29sdk_wifi_mmc0_status_register,
-#endif
-
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .power_en = RK29SDK_SD_CARD_PWR_EN,
- .power_en_level = RK29SDK_SD_CARD_PWR_EN_LEVEL,
-#else
- .power_en = INVALID_GPIO,
- .power_en_level = GPIO_LOW,
-#endif
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC0_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- .det_pin_info = {
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N, //INVALID_GPIO,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
- #endif
- },
-
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- rk30_mux_api_set(GPIO3C0_SMMC1CMD_NAME, GPIO3C_SMMC1_CMD);
- rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_NAME, GPIO3C_SDMMC1_CLKOUT);
- rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_NAME, GPIO3C_SDMMC1_DATA0);
- rk30_mux_api_set(GPIO3C2_SDMMC1DATA1_NAME, GPIO3C_SDMMC1_DATA1);
- rk30_mux_api_set(GPIO3C3_SDMMC1DATA2_NAME, GPIO3C_SDMMC1_DATA2);
- rk30_mux_api_set(GPIO3C4_SDMMC1DATA3_NAME, GPIO3C_SDMMC1_DATA3);
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC) || defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-
- #if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC1_WRITE_PROTECT_ENABLE_VALUE;
- #else
- .write_prt = INVALID_GPIO,
- #endif
-
- #if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
- .sdio_INT_gpio = RK29SDK_WIFI_SDIO_CARD_INT,
- #endif
-
- .det_pin_info = {
-#if defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- #else
- .io = INVALID_GPIO,
- #endif
-
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-
- .enable_sd_wakeup = 0,
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-/**************************************************************************************************
- * the end of setting for SDMMC devices
-**************************************************************************************************/
-
-#if defined(CONFIG_BATTERY_RK30_ADC)||defined(CONFIG_BATTERY_RK30_ADC_FAC)
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = RK30_PIN6_PA5,
- .batt_low_pin = RK30_PIN6_PA0,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = RK30_PIN6_PA6,
- .dc_det_level = GPIO_LOW,
- .charge_ok_level = GPIO_HIGH,
-};
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-
-#ifdef CONFIG_RK30_PWM_REGULATOR
-const static int pwm_voltage_map[] = {
- 950000,975000,1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000, 1375000, 1400000
-};
-
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_core",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] =
-{
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
- .pwm_id = 3,
- .pwm_gpio = RK30_PIN0_PD7,
- .pwm_iomux_name = GPIO0D7_PWM3_NAME,
- .pwm_iomux_pwm = GPIO0D_PWM3,
- .pwm_iomux_gpio = GPIO0D_GPIO0D6,
- .pwm_voltage = 1100000,
- .suspend_voltage = 1050000,
- .min_uV = 950000,
- .max_uV = 1400000,
- .coefficient = 455, //45.5%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-#endif
-
-#ifdef CONFIG_RK29_VMAC
-#define PHY_PWR_EN_GPIO RK30_PIN1_PD6
-#include "board-rk30-sdk-vmac.c"
-#endif
-
-#ifdef CONFIG_RFKILL_RK
-// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
-static struct rfkill_rk_platform_data rfkill_rk_platdata = {
- .type = RFKILL_TYPE_BLUETOOTH,
-
- .poweron_gpio = { // BT_REG_ON
- .io = RK30_PIN3_PC7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C7_SDMMC1WRITEPRT_NAME,
- .fgpio = GPIO3C_GPIO3C7,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN3_PD1, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = GPIO3D1_SDMMC1BACKENDPWR_NAME,
- .fgpio = GPIO3D_GPIO3D1,
- },
- },
-
- .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
- .io = RK30_PIN3_PC6, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = GPIO3C6_SDMMC1DETECTN_NAME,
- .fgpio = GPIO3C_GPIO3C6,
- },
- },
-
- .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .gpio = {
- .io = RK30_PIN6_PA7, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
- .iomux = {
- .name = NULL,
- },
- },
- },
-
- .rts_gpio = { // UART_RTS, enable or disable BT's data coming
- .io = RK30_PIN1_PA3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = GPIO1A3_UART0RTSN_NAME,
- .fgpio = GPIO1A_GPIO1A3,
- .fmux = GPIO1A_UART0_RTS_N,
- },
- },
-};
-
-static struct platform_device device_rfkill_rk = {
- .name = "rfkill_rk",
- .id = -1,
- .dev = {
- .platform_data = &rfkill_rk_platdata,
- },
-};
-#endif
-
-#if defined(CONFIG_MT5931_MT6622)
-static struct mt6622_platform_data mt6622_platdata = {
- .power_gpio = { // BT_REG_ON
- .io = RK30_PIN3_PC7, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN3_PD1,
- .enable = GPIO_LOW,
- .iomux = {
- .name = NULL,
- },
- },
-
- .irq_gpio = {
- .io = RK30_PIN6_PA7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- }
-};
-
-static struct platform_device device_mt6622 = {
- .name = "mt6622",
- .id = -1,
- .dev = {
- .platform_data = &mt6622_platdata,
- },
-};
-#endif
-
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_ANDROID_TIMED_GPIO
- &rk29_device_vibrator,
-#endif
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
- &rk29_device_gpio_leds,
-#endif
-#ifdef CONFIG_RK_IRDA
- &irda_device,
-#endif
-#if defined(CONFIG_WIFI_CONTROL_FUNC)||defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- &rk29sdk_wifi_device,
-#endif
-
-#if defined(CONFIG_MT6620)
- &mt3326_device_gps,
-#endif
-
-#ifdef CONFIG_RK29_SUPPORT_MODEM
- &rk30_device_modem,
-#endif
-#if defined(CONFIG_MU509)
- &rk29_device_mu509,
- #endif
-#if defined(CONFIG_MW100)
- &rk29_device_mw100,
-#endif
-#if defined(CONFIG_MT6229)
-&rk29_device_mt6229,
-#endif
-#if defined(CONFIG_SEW868)
-&rk30_device_sew868,
-#endif
-#if defined (CONFIG_RK_HEADSET_DET) || defined (CONFIG_RK_HEADSET_IRQ_HOOK_ADC_DET)
- &rk_device_headset,
-#endif
-
-#if defined(CONFIG_BATTERY_RK30_ADC)||defined(CONFIG_BATTERY_RK30_ADC_FAC)
- &rk30_device_adc_battery,
-#endif
-#ifdef CONFIG_RFKILL_RK
- &device_rfkill_rk,
-#endif
-#ifdef CONFIG_MT5931_MT6622
- &device_mt6622,
-#endif
-#if defined(CONFIG_BP_AUTO)
- &device_bp_auto,
-#endif
-};
-
-
-static int rk_platform_add_display_devices(void)
-{
- struct platform_device *fb = NULL; //fb
- struct platform_device *lcdc0 = NULL; //lcdc0
- struct platform_device *lcdc1 = NULL; //lcdc1
- struct platform_device *bl = NULL; //backlight
-#ifdef CONFIG_FB_ROCKCHIP
- fb = &device_fb;
-#endif
-
-#if defined(CONFIG_LCDC0_RK30)
- lcdc0 = &device_lcdc0,
-#endif
-
-#if defined(CONFIG_LCDC1_RK30)
- lcdc1 = &device_lcdc1,
-#endif
-
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- bl = &rk29_device_backlight,
-#endif
- __rk_platform_add_display_devices(fb,lcdc0,lcdc1,bl);
-
- return 0;
-
-}
-// i2c
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1d,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_GS_LIS3DH)
- {
- .type = "gs_lis3dh",
- .addr = 0x19, //0x19(SA0-->VCC), 0x18(SA0-->GND)
- .flags = 0,
- .irq = LIS3DH_INT_PIN,
- .platform_data = &lis3dh_info,
- },
-#endif
-#if defined (CONFIG_GS_KXTIK)
- {
- .type = "gs_kxtik",
- .addr = 0x0F,
- .flags = 0,
- .irq = KXTIK_INT_PIN,
- .platform_data = &kxtik_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN4_PC1,
- .platform_data = &akm8975_info,
- },
-#endif
-#if defined (CONFIG_GYRO_L3G4200D)
- {
- .type = "l3g4200d_gryo",
- .addr = 0x69,
- .flags = 0,
- .irq = L3G4200D_INT_PIN,
- .platform_data = &l3g4200d_info,
- },
-#endif
-#if defined (CONFIG_LS_AL3006)
- {
- .type = "light_al3006",
- .addr = 0x1c, //sel = 0; if sel =1, then addr = 0x1D
- .flags = 0,
- .irq = RK30_PIN6_PA2,
- .platform_data = &light_al3006_info,
- },
-#endif
-#if defined (CONFIG_LS_STK3171)
- {
- .type = "ls_stk3171",
- .addr = 0x48,
- .flags = 0,
- .irq = RK30_PIN6_PA2,
- .platform_data = &light_stk3171_info,
- },
-#endif
-
-
-#if defined (CONFIG_PS_AL3006)
- {
- .type = "proximity_al3006",
- .addr = 0x1c, //sel = 0; if sel =1, then addr = 0x1D
- .flags = 0,
- .irq = RK30_PIN6_PA2,
- .platform_data = &proximity_al3006_info,
- },
-#endif
-
-#if defined (CONFIG_PS_STK3171)
- {
- .type = "ps_stk3171",
- .addr = 0x48,
- .flags = 0,
- .irq = RK30_PIN6_PA2,
- .platform_data = &proximity_stk3171_info,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RT5631) || defined (CONFIG_SND_SOC_RT5631_PHONE)
- {
- .type = "rt5631",
- .addr = 0x1a,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RT3224) || defined (CONFIG_SND_SOC_RT3261)
- {
- .type = "rt3261",
- .addr = 0x1c,
- .flags = 0,
- .platform_data = &rt3261_info,
- },
-#endif
-
-#ifdef CONFIG_MFD_RK610
- {
- .type = "rk610_ctl",
- .addr = 0x40,
- .flags = 0,
- .platform_data = &rk610_ctl_pdata,
- },
-#ifdef CONFIG_RK610_TVOUT
- {
- .type = "rk610_tvout",
- .addr = 0x42,
- .flags = 0,
- },
-#endif
-#ifdef CONFIG_HDMI_RK610
- {
- .type = "rk610_hdmi",
- .addr = 0x46,
- .flags = 0,
- .irq = INVALID_GPIO,
- },
-#endif
-#ifdef CONFIG_SND_SOC_RK610
- {//RK610_CODEC addr from 0x60 to 0x80 (0x60~0x80)
- .type = "rk610_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- .platform_data = &rk610_codec_pdata,
- },
-#endif
-#endif
-
-};
-#endif
-int __sramdata g_pmic_type = 0;
-#ifdef CONFIG_I2C1_RK30
-#ifdef CONFIG_MFD_WM831X_I2C
-#include "board-rk30-sdk-wm8326.c"
-#endif
-#ifdef CONFIG_MFD_TPS65910
-#define TPS65910_HOST_IRQ RK30_PIN6_PA4
-#include "board-rk30-sdk-tps65910.c"
-#endif
-
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_MFD_WM831X_I2C)
- {
- .type = "wm8326",
- .addr = 0x34,
- .flags = 0,
- .irq = RK30_PIN6_PA4,
- .platform_data = &wm831x_platdata,
- },
-#endif
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-};
-#endif
-
-void __sramfunc board_pmu_suspend(void)
-{
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_suspend();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_suspend();
- #endif
-}
-
-void __sramfunc board_pmu_resume(void)
-{
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_resume();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_resume();
- #endif
-}
-
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-#if defined (CONFIG_TOUCHSCREEN_GT8XX)
- {
- .type = "Goodix-TS",
- .addr = 0x55,
- .flags = 0,
- .irq = RK30_PIN4_PC2,
- .platform_data = &goodix_info,
- },
-#endif
-#if defined (CONFIG_LS_CM3217)
- {
- .type = "light_cm3217",
- .addr = 0x10,
- .flags = 0,
- .platform_data = &cm3217_info,
- },
-#endif
-
-#if defined(CONFIG_DP501)
- {
- .type = "dp501",
- .addr = 0x30,
- .flags = 0,
- .platform_data = &dp501_platform_data,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C4_RK30
-static struct i2c_board_info __initdata i2c4_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO// RK30_PIN2_PD6 //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO//RK30_PIN2_PD7 //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- //set iomux (gpio) here
- //rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME, GPIO2D_GPIO2D7);
- //rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME, GPIO2D_GPIO2D6);
-
- return 0;
-}
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C4_RK30
- i2c_register_board_info(4, i2c4_info, ARRAY_SIZE(i2c4_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(5, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-
-#define POWER_ON_PIN RK30_PIN6_PB0 //power_hold
-static void rk30_pm_power_off(void)
-{
- printk(KERN_ERR "rk30_pm_power_off start...\n");
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
- #if defined(CONFIG_MFD_WM831X)
- if(pmic_is_wm8326())
- {
- wm831x_set_bits(Wm831x,WM831X_GPIO_LEVEL,0x0001,0x0000); //set sys_pwr 0
- wm831x_device_shutdown(Wm831x);//wm8326 shutdown
- }
- #endif
- #if defined(CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- {
- tps65910_device_shutdown();//tps65910 shutdown
- }
- #endif
-
- while (1);
-}
-
-static void __init machine_rk30_board_init(void)
-{
- avs_init();
- gpio_request(POWER_ON_PIN, "poweronpin");
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
- pm_power_off = rk30_pm_power_off;
-
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- rk_platform_add_display_devices();
- board_usb_detect_init(RK30_PIN6_PA3);
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC)
- rk29sdk_wifi_bt_gpio_control_init();
-#elif defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- rk29sdk_wifi_combo_module_gpio_init();
-#endif
-
-#if defined(CONFIG_MT6620)
- clk_set_rate(clk_get_sys("rk_serial.0", "uart"), 48*1000000);
-#endif
-#if defined(CONFIG_MT5931_MT6622)
- clk_set_rate(clk_get_sys("rk_serial.0", "uart"), 24*1000000);
-#endif
-#if defined (CONFIG_SND_SOC_RT3224) || defined (CONFIG_SND_SOC_RT3261)
- //add for codec_en
- gpio_request(RK30_PIN4_PD7, "codec_en");
- rk30_mux_api_set(GPIO4D7_SMCDATA15_TRACEDATA15_NAME, GPIO4D_GPIO4D7);
- gpio_direction_output(RK30_PIN4_PD7, GPIO_HIGH);
-#endif
-}
-
-static void __init rk30_reserve(void)
-{
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0 buf", get_fb_size());
- resource_fb[0].end = resource_fb[0].start + get_fb_size()- 1;
-#if 0
- resource_fb[1].start = board_mem_reserve_add("ipp buf", RK30_FB0_MEM_SIZE);
- resource_fb[1].end = resource_fb[1].start + RK30_FB0_MEM_SIZE - 1;
-#endif
-
-#if defined(CONFIG_FB_ROTATE) || !defined(CONFIG_THREE_FB_BUFFER)
- resource_fb[2].start = board_mem_reserve_add("fb2 buf",get_fb_size());
- resource_fb[2].end = resource_fb[2].start + get_fb_size() - 1;
-#endif
-#endif
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
- board_mem_reserved();
-}
-
-/**
- * dvfs_cpu_logic_table: table for arm and logic dvfs
- * @frequency : arm frequency
- * @cpu_volt : arm voltage depend on frequency
- * @logic_volt : logic voltage arm requests depend on frequency
- * comments : min arm/logic voltage
- */
-static struct dvfs_arm_table dvfs_cpu_logic_table[] = {
- {.frequency = 252 * 1000, .cpu_volt = 1075 * 1000, .logic_volt = 1125 * 1000},//0.975V/1.000V
- {.frequency = 504 * 1000, .cpu_volt = 1100 * 1000, .logic_volt = 1125 * 1000},//0.975V/1.000V
- {.frequency = 816 * 1000, .cpu_volt = 1125 * 1000, .logic_volt = 1150 * 1000},//1.000V/1.025V
- {.frequency = 1008 * 1000, .cpu_volt = 1125 * 1000, .logic_volt = 1150 * 1000},//1.025V/1.050V
- {.frequency = 1200 * 1000, .cpu_volt = 1175 * 1000, .logic_volt = 1200 * 1000},//1.100V/1.050V
- {.frequency = 1272 * 1000, .cpu_volt = 1225 * 1000, .logic_volt = 1200 * 1000},//1.150V/1.100V
- {.frequency = 1416 * 1000, .cpu_volt = 1300 * 1000, .logic_volt = 1200 * 1000},//1.225V/1.100V
- {.frequency = 1512 * 1000, .cpu_volt = 1350 * 1000, .logic_volt = 1250 * 1000},//1.300V/1.150V
- {.frequency = 1608 * 1000, .cpu_volt = 1425 * 1000, .logic_volt = 1300 * 1000},//1.325V/1.175V
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- {.frequency = 266 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1275 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 1050 * 1000},
- {.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = 1050 * 1000},
- {.frequency = 400 * 1000 + DDR_FREQ_NORMAL, .index = 1125 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
-static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
-static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
-
-void __init board_clock_init(void)
-{
- rk30_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
- dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
-}
-
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk30_fixup,
- .reserve = &rk30_reserve,
- .map_io = rk30_map_io,
- .init_irq = rk30_init_irq,
- .timer = &rk30_timer,
- .init_machine = machine_rk30_board_init,
-MACHINE_END
+++ /dev/null
-#ifdef CONFIG_VIDEO_RK29
-#include <plat/rk_camera.h>
-/* Notes:
-
-Simple camera device registration:
-
- new_camera_device(sensor_name,\ // sensor name, it is equal to CONFIG_SENSOR_X
- face,\ // sensor face information, it can be back or front
- pwdn_io,\ // power down gpio configuration, it is equal to CONFIG_SENSOR_POWERDN_PIN_XX
- flash_attach,\ // sensor is attach flash or not
- mir,\ // sensor image mirror and flip control information
- i2c_chl,\ // i2c channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_IIC_ADAPTER_ID_X
- cif_chl) \ // cif channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_CIF_INDEX_X
-
-Comprehensive camera device registration:
-
- new_camera_device_ex(sensor_name,\
- face,\
- ori,\ // sensor orientation, it is equal to CONFIG_SENSOR_ORIENTATION_X
- pwr_io,\ // sensor power gpio configuration, it is equal to CONFIG_SENSOR_POWER_PIN_XX
- pwr_active,\ // sensor power active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- rst_io,\ // sensor reset gpio configuration, it is equal to CONFIG_SENSOR_RESET_PIN_XX
- rst_active,\ // sensor reset active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- pwdn_io,\
- pwdn_active,\ // sensor power down active level, is equal to CONFIG_SENSOR_POWERDNACTIVE_LEVEL_X
- flash_attach,\
- res,\ // sensor resolution, this is real resolution or resoltuion after interpolate
- mir,\
- i2c_chl,\
- i2c_spd,\ // i2c speed , 100000 = 100KHz
- i2c_addr,\ // the i2c slave device address for sensor
- cif_chl,\
- mclk)\ // sensor input clock rate, 24 or 48
-
-*/
-static struct rkcamera_platform_data new_camera[] = {
- new_camera_device(RK29_CAM_SENSOR_GC2035,
- back,
- RK30_PIN0_PB3,
- 0,
- 0,
- 1,
- 0),
- new_camera_device(RK29_CAM_SENSOR_GC0308,
- front,
- RK30_PIN0_PB2,
- 0,
- 0,
- 1,
- 0),
- new_camera_device_end
-};
-
-/*---------------- Camera Sensor Macro Define Begin ------------------------*/
-/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
-#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_GC2035 /* back camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_0 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 1
-#define CONFIG_SENSOR_ORIENTATION_0 90
-#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 RK30_PIN0_PB3
-#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO//RK30_PIN0_PD5 //INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_H
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000
-
-#define CONFIG_SENSOR_01 RK29_CAM_SENSOR_OV5642 /* back camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_01 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 4
-#define CONFIG_SENSOR_ORIENTATION_01 90
-#define CONFIG_SENSOR_POWER_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_01 RK30_PIN1_PD6
-#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_01 30000
-
-#define CONFIG_SENSOR_02 RK29_CAM_SENSOR_OV5640 /* back camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_02 0x00
-#define CONFIG_SENSOR_CIF_INDEX_02 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 4
-#define CONFIG_SENSOR_ORIENTATION_02 90
-#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000
-
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_GC0308 /* front camera sensor 0 */
-#define CONFIG_SENSOR_IIC_ADDR_1 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 1
-#define CONFIG_SENSOR_ORIENTATION_1 270
-#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_1 RK30_PIN0_PB2
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000
-
-#define CONFIG_SENSOR_11 RK29_CAM_SENSOR_OV2659 /* front camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_11 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 3
-#define CONFIG_SENSOR_ORIENTATION_11 270
-#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_11 INVALID_GPIO//RK30_PIN1_PB7
-#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_11 30000
-
-#define CONFIG_SENSOR_12 RK29_CAM_SENSOR_OV2659//RK29_CAM_SENSOR_OV2655 /* front camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_12 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 3
-#define CONFIG_SENSOR_ORIENTATION_12 270
-#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_12 INVALID_GPIO//RK30_PIN1_PB7
-#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_12 30000
-
-
-#endif //#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk30_camera.c"
-/*---------------- Camera Sensor Macro Define End ---------*/
-
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#define CONFIG_SENSOR_POWER_IOCTL_USR 0 //define this refer to your board layout
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 1
-
-static void rk_cif_power(int on)
-{
- struct regulator *ldo_18,*ldo_28;
- ldo_28 = regulator_get(NULL, "ldo7"); // vcc28_cif
- ldo_18 = regulator_get(NULL, "ldo1"); // vcc18_cif
- if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){
- printk("get cif ldo failed!\n");
- return;
- }
- if(on == 0){
- regulator_disable(ldo_28);
- regulator_put(ldo_28);
- regulator_disable(ldo_18);
- regulator_put(ldo_18);
- mdelay(500);
- }
- else{
- regulator_set_voltage(ldo_28, 2800000, 2800000);
- regulator_enable(ldo_28);
- // printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
- regulator_put(ldo_28);
-
- regulator_set_voltage(ldo_18, 1800000, 1800000);
- // regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(ldo_18);
- // printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
- regulator_put(ldo_18);
- }
-}
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- //#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
- rk_cif_power(on);
- return 0;
-}
-#endif
-
-#if CONFIG_SENSOR_RESET_IOCTL_USR
-static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
-static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-
-#define CONFIG_SENSOR_FALSH_EN_PIN_0 RK30_PIN0_PD5 //high:enable
-#define CONFIG_SENSOR_FALSH_EN_MUX_0 GPIO0D5_SPI1TXD_NAME
-#define CONFIG_SENSOR_FALSH_MODE_PIN_0 RK30_PIN0_PD4 //high:FLASH, low:torch
-#define CONFIG_SENSOR_FALSH_MODE_MUX_0 GPIO0D4_SPI1RXD_NAME
-
-static int sensor_init_flags = 0;
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- if(sensor_init_flags == 0){
- rk30_mux_api_set(CONFIG_SENSOR_FALSH_MODE_MUX_0, 0);
- int ret = gpio_request(CONFIG_SENSOR_FALSH_MODE_PIN_0, "camera_flash_mode");
- if (ret != 0) {
- printk(">>>>gpio request camera_flash_mode faile !!\n");
- }
-
- gpio_direction_output(CONFIG_SENSOR_FALSH_MODE_PIN_0, 0);
- sensor_init_flags = 1 ;
- }
- switch (on) {
- case Flash_Off: {
- gpio_set_value(CONFIG_SENSOR_FALSH_EN_PIN_0, 0);
- gpio_set_value(CONFIG_SENSOR_FALSH_MODE_PIN_0, 0);
- break;
- }
-
- case Flash_On: {
- gpio_set_value(CONFIG_SENSOR_FALSH_EN_PIN_0, 1);
- gpio_set_value(CONFIG_SENSOR_FALSH_MODE_PIN_0, 1);
- break;
- }
-
- case Flash_Torch: {
- gpio_set_value(CONFIG_SENSOR_FALSH_EN_PIN_0, 1);
- gpio_set_value(CONFIG_SENSOR_FALSH_MODE_PIN_0, 0);
- break;
- }
-
- default: {
- printk("%s..Flash command(%d) is invalidate \n",__FUNCTION__, on);
- gpio_set_value(CONFIG_SENSOR_FALSH_EN_PIN_0, 0);
- break;
- }
- }
- return 0;
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-
-#if CONFIG_SENSOR_IIC_ADDR_0
-static struct reginfo_t rk_init_data_sensor_reg_0[] =
-{
- {0x0000, 0x00,0,0}
- };
-static struct reginfo_t rk_init_data_sensor_winseqreg_0[] ={
- {0x0000, 0x00,0,0}
- };
-#endif
-
-#if CONFIG_SENSOR_IIC_ADDR_1
-static struct reginfo_t rk_init_data_sensor_reg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_01
-static struct reginfo_t rk_init_data_sensor_reg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_02
-static struct reginfo_t rk_init_data_sensor_reg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_11
-static struct reginfo_t rk_init_data_sensor_reg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_12
-static struct reginfo_t rk_init_data_sensor_reg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] =
-{
- #if CONFIG_SENSOR_IIC_ADDR_0
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_0,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_1
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_1,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_01
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_01,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_02
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_02,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_11
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_11,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_12
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_12,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
-
- };
-#include "../../../drivers/media/video/rk30_camera.c"
-
-#endif /* CONFIG_VIDEO_RK29 */
+++ /dev/null
-/*****************************************************************************************
- * arch/arm/mach-rkxx/baord-xxx-sdmmc-config.c
- *
- * Copyright (C) 2013 ROCKCHIP, Inc.
- *
- * Description:
- * define the gpio for SD-MMC-SDIO-Wifi functions according to your own projects.
- *
- * Author: Michael Xie
- * 15 Jan,2013
- * E-mail: xbw@rock-chips.com
- *
- ******************************************************************************************/
-
-/*
-** If you select the macro of CONFIG_SDMMC0_RK29_WRITE_PROTECT, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define SDMMC0_WRITE_PROTECT_PIN RK30_PIN3_PB2 //According to your own project to set the value of write-protect-pin.
-//#define SDMMC0_WRITE_PROTECT_ENABLE_VALUE GPIO_HIGH
-
-/*
-** If you select the macro of CONFIG_SDMMC1_RK29_WRITE_PROTECT, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define SDMMC1_WRITE_PROTECT_PIN RK30_PIN3_PB3 //According to your own project to set the value of write-protect-pin.
-//#define SDMMC1_WRITE_PROTECT_ENABLE_VALUE GPIO_HIGH
-
-/*
-** If you select the macro of CONFIG_RK29_SDIO_IRQ_FROM_GPIO, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define RK29SDK_WIFI_SDIO_CARD_INT RK30_PIN3_PD2
-
-
-/*
-* define sdcard PowerEn-pin
-*/
-#define RK29SDK_SD_CARD_PWR_EN INVALID_GPIO
-#define RK29SDK_SD_CARD_PWR_EN_LEVEL GPIO_LOW
-int rk31sdk_get_sdmmc0_pin_io_voltage(void)
-{
- int voltage;
-#define RK31SDK_SET_SDMMC0_PIN_VOLTAGE
-
- /**************************************************************************************
- ** Please tell me how much voltage of your SDMMC0-pin in your project.
- **
- ** ÀýÈç: ÓеÄÏîÄ¿£¬ËüµÄSDMMC0ËùÔÚµÄRKÖ÷¿ØµÄIO×飬ÏëÓÃ1.8V, ¶ø¿¨±¾ÉíÓÃ3.3V,
- ** ¶øÖмäͨ¹ý¸öµçƽת»».ÄÇô£¬Äú´Ëʱ£¬Ó¦¸ÃÉèÖÃÏÂÃæµÄvoltageֵΪ 1.8V(¼´1800mv)
- ***************************************************************************************/
- voltage = 3300; //default the voltage 3300mv.
-
- return voltage;
-}
-
-/*
-* define the card-detect-pin.
-*/
-#define RK29SDK_SD_CARD_DETECT_N RK30_PIN1_PC1 //According to your own project to set the value of card-detect-pin.
-#define RK29SDK_SD_CARD_INSERT_LEVEL GPIO_LOW // set the voltage of insert-card. Please pay attention to the default setting.
-
-//wake up host gpio
-#define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
-#define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
-
-/*
-* Define wifi module's power and reset gpio, and gpio sensitive level.
-* Please set the value according to your own project.
-*
-* Well, you just own engineering module to set the value in the corresponding module branch.
-* Otherwise, you do not define this macro, eliminate it.
-*
-*/
-#if defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU) || defined(CONFIG_RTL8723AU) || defined(CONFIG_MT7601)
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN0_PB0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_LOW//GPIO_HIGH
-
-#elif defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319) || defined(CONFIG_RKWIFI) || defined(CONFIG_RTL8189ES)
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN0_PC2 // RK30_PIN2_PA7
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
-
-#elif defined(CONFIG_MT5931_MT6622) || defined(CONFIG_MT5931)
-
- #ifdef CONFIG_MACH_RK3168_LR097
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- //#define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- //#define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
-
- #else
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN0_PA5
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #endif
-
-#elif defined(CONFIG_MT6620)
- #define COMBO_MODULE_MT6620_CDT 0 // to control antsel2,antsel3 and gps_lan foot when using AcSip or Cdtech chip.
- //- 1--use Cdtech chip; 0--unuse CDT chip
-
- //power, PMU_EN//hjc test
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN0_PB5
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- //reset, DAIRST,SYSRST_B
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- //VDDIO
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL RK30_PIN0_PD2 //You do not get control of the foot, and you do not need to define the macro
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_ENABLE_VALUE GPIO_HIGH
- //WIFI_INT_B
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
- //BGF_INT_B
- #define RK30SDK_WIFI_GPIO_BGF_INT_B RK30_PIN0_PA5
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_ENABLE_VALUE GPIO_HIGH
- //GPS_SYNC
- #define RK30SDK_WIFI_GPIO_GPS_SYNC RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_ENABLE_VALUE GPIO_HIGH
-
- #if COMBO_MODULE_MT6620_CDT
- //ANTSEL2
- #define RK30SDK_WIFI_GPIO_ANTSEL2 RK30_PIN4_PD4
- #define RK30SDK_WIFI_GPIO_ANTSEL2_ENABLE_VALUE GPIO_LOW //use 6620 in CDT chip, LOW--work; High--no work.
- //ANTSEL3
- #define RK30SDK_WIFI_GPIO_ANTSEL3 RK30_PIN4_PD3
- #define RK30SDK_WIFI_GPIO_ANTSEL3_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- //GPS_LAN
- #define RK30SDK_WIFI_GPIO_GPS_LAN RK30_PIN4_PD6
- #define RK30SDK_WIFI_GPIO_GPS_LAN_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- #endif // #if COMBO_MODULE_MT6620_CDT--#endif
-#endif
-
-#ifndef RK30SDK_WIFI_GPIO_WIFI_INT_B
-#define RK30SDK_WIFI_GPIO_WIFI_INT_B INVALID_GPIO
-#define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
-#endif
-
-int rk31sdk_get_sdio_wifi_voltage(void)
-{
- int voltage;
-
- /******************************************************************************
- ** Please tell me how much wifi-module uses voltage in your project.
- ******************************************************************************/
-#if defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319) || defined(CONFIG_RKWIFI)
- voltage = 1800 ; //power 1800mV
-
-#elif defined(CONFIG_MT5931_MT6622)||defined(CONFIG_MT5931)
- voltage = 1800 ; //power 1800V
-#elif defined(CONFIG_MT6620)
- voltage = 1800 ; //power 2800V
-#elif defined(CONFIG_RDA5990)||defined(CONFIG_RTL8723AS)
- voltage = 3300 ; //power 3300V
-#else
- //default, sdio use 3.0V
- voltage = 3000 ; //power 3000V
-#endif
-
- return voltage;
-}
-
-
-
+++ /dev/null
-/*
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <mach/dvfs.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <linux/rk_fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/mfd/tps65910.h>
-#include <linux/regulator/act8846.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-#include <linux/regulator/act8931.h>
-
-#if defined(CONFIG_MFD_RK610)
-#include <linux/mfd/rk610_core.h>
-#endif
-
-#if defined(CONFIG_RK_HDMI)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-#if defined(CONFIG_GPS_RK)
-#include "../../../drivers/misc/gps/rk_gps/rk_gps.h"
-#endif
-
-#if defined(CONFIG_MU509)
-#include <linux/mu509.h>
-#endif
-#if defined(CONFIG_MW100)
-#include <linux/mw100.h>
-#endif
-#if defined(CONFIG_MT6229)
-#include <linux/mt6229.h>
-#endif
-#if defined(CONFIG_ANDROID_TIMED_GPIO)
-#include "../../../drivers/staging/android/timed_gpio.h"
-#endif
-
-#if defined(CONFIG_MT6620)
-#include <linux/gps.h>
-#endif
-#include "../mach-rk30/board-rk3028-86v-camera.c"
-#if defined(CONFIG_TOUCHSCREEN_GSLX680_RK3028)
-#define TOUCH_RESET_PIN RK30_PIN0_PC1
-#define TOUCH_EN_PIN NULL
-#define TOUCH_INT_PIN RK30_PIN0_PB4
-
-int gslx680_init_platform_hw(void)
-{
-
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("gslx680_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("gslx680_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, GPIO_HIGH);
- mdelay(10);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- mdelay(10);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- msleep(300);
- return 0;
-
-}
-
-struct ts_hw_data gslx680_info = {
- .reset_gpio = TOUCH_RESET_PIN,
- .touch_en_gpio = TOUCH_INT_PIN,
- .init_platform_hw = gslx680_init_platform_hw,
-};
-#endif
-
-#if defined (CONFIG_TOUCHSCREEN_86V_GT811_IIC)
-#define TOUCH_RESET_PIN RK30_PIN0_PB6
-#define TOUCH_INT_PIN RK30_PIN1_PB7
-int gt811_init_platform_hw(void)
-{
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("gt811_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("gt811_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- //gpio_pull_updown(TOUCH_INT_PIN, 1);
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- mdelay(100);
-
- return 0;
-}
-
-
-static struct goodix_platform_data gt811_info = {
- .model= 811,
- .init_platform_hw= gt811_init_platform_hw,
-
-};
-#endif
-
-#if defined(CONFIG_TOUCHSCREEN_GT8XX)
-#define TOUCH_RESET_PIN RK30_PIN0_PC1//RK30_PIN0_PB6
-#define TOUCH_PWR_PIN INVALID_GPIO//RK30_PIN0_PC5 // need to fly line by hardware engineer
-static int goodix_init_platform_hw(void)
-{
- int ret;
-
- if (TOUCH_PWR_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_PWR_PIN, "goodix power pin");
- if (ret != 0) {
- gpio_free(TOUCH_PWR_PIN);
- printk("goodix power error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_PWR_PIN, 0);
- gpio_set_value(TOUCH_PWR_PIN, GPIO_LOW);
- msleep(100);
- }
-
- if (TOUCH_RESET_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_RESET_PIN, "goodix reset pin");
- if (ret != 0) {
- gpio_free(TOUCH_RESET_PIN);
- printk("goodix gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, 1);
- msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_LOW);
- //msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_HIGH);
- //msleep(500);
- }
- return 0;
-}
-
-struct goodix_platform_data goodix_info = {
- .model = 8105,
- .irq_pin = RK30_PIN0_PB4,
- .rest_pin = TOUCH_RESET_PIN,
- .init_platform_hw = goodix_init_platform_hw,
-};
-#endif
-
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-#define PWM_ID 0
-#define PWM_MODE PWM0
-#define PWM_EFFECT_VALUE GPIO_LOW
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-#define BL_EN_PIN RK30_PIN0_PC0
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
- ret = gpio_request(BL_EN_PIN, NULL);
- if (ret != 0) {
- gpio_free(BL_EN_PIN);
- }
- gpio_direction_output(BL_EN_PIN, BL_EN_VALUE);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0, pwm_gpio;
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, !BL_EN_VALUE);
- gpio_free(BL_EN_PIN);
-#endif
- pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
- iomux_set(pwm_gpio);
- gpio_request(pwm_gpio, "bl_pwm");
- gpio_direction_output(pwm_gpio, !PWM_EFFECT_VALUE);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret, pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
- iomux_set(pwm_gpio);
-
- ret = gpio_request(pwm_gpio, "bl_pwm");
- if (ret) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return ret;
- }
- gpio_direction_output(pwm_gpio, !PWM_EFFECT_VALUE);
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, !BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- int pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
- gpio_free(pwm_gpio);
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .min_brightness = 100,
- .max_brightness=255,
- .brightness_mode =BRIGHTNESS_MODE_CONIC,
- .pre_div = 20 * 1000, // pwm output clk: 20k;
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-#endif
-
-#ifdef CONFIG_RK29_SUPPORT_MODEM
-
-#define RK30_MODEM_POWER RK30_PIN0_PC6
-#define RK30_MODEM_POWER_IOMUX iomux_set(GPIO0_C6)
-
-static int rk30_modem_io_init(void)
-{
- printk("%s\n", __FUNCTION__);
- RK30_MODEM_POWER_IOMUX;
-
- return 0;
-}
-
-static struct rk29_io_t rk30_modem_io = {
- .io_addr = RK30_MODEM_POWER,
- .enable = GPIO_HIGH,
- .disable = GPIO_LOW,
- .io_init = rk30_modem_io_init,
-};
-
-static struct platform_device rk30_device_modem = {
- .name = "rk30_modem",
- .id = -1,
- .dev = {
- .platform_data = &rk30_modem_io,
- }
-};
-#endif
-#if defined(CONFIG_MU509)
-static int mu509_io_init(void)
-{
-
- iomux_set(GPIO2_D5);
- iomux_set(GPIO0_C6);
- iomux_set(GPIO2_D4);
- iomux_set(GPIO0_C4);
- iomux_set(GPIO0_C5);
- return 0;
-}
-
-static int mu509_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mu509_data rk29_mu509_info = {
- .io_init = mu509_io_init,
- .io_deinit = mu509_io_deinit,
- .modem_power_en = RK30_PIN2_PD5,
- .bp_power = RK30_PIN0_PC6,
- .bp_reset = RK30_PIN2_PD4,
- .ap_wakeup_bp = RK30_PIN0_PC4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
-};
-struct platform_device rk29_device_mu509 = {
- .name = "mu509",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mu509_info,
- }
- };
-#endif
-#if defined(CONFIG_MW100)
-static int mw100_io_init(void)
-{
- iomux_set(GPIO2_D5);
- iomux_set(GPIO0_C6);
- iomux_set(GPIO2_D4);
- iomux_set(GPIO0_C4);
- iomux_set(GPIO0_C5);
- return 0;
-}
-
-static int mw100_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mw100_data rk29_mw100_info = {
- .io_init = mw100_io_init,
- .io_deinit = mw100_io_deinit,
- .modem_power_en = RK30_PIN2_PD5,
- .bp_power = RK30_PIN0_PC6,
- .bp_reset = RK30_PIN2_PD4,
- .ap_wakeup_bp = RK30_PIN0_PC4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
-};
-struct platform_device rk29_device_mw100 = {
- .name = "mw100",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mw100_info,
- }
- };
-#endif
-#if defined(CONFIG_MT6229)
-static int mt6229_io_init(void)
-{
- iomux_set(GPIO2_D5);
- iomux_set(GPIO0_C6);
- iomux_set(GPIO2_D4);
- iomux_set(GPIO0_C4);
- iomux_set(GPIO0_C5);
- return 0;
-}
-
-static int mt6229_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mt6229_data rk29_mt6229_info = {
- .io_init = mt6229_io_init,
- .io_deinit = mt6229_io_deinit,
- .modem_power_en = RK30_PIN2_PD5,
- .bp_power = RK30_PIN0_PC6,
- .bp_reset = RK30_PIN2_PD4,
- .ap_wakeup_bp = RK30_PIN0_PC4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
-};
-struct platform_device rk29_device_mt6229 = {
- .name = "mt6229",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mt6229_info,
- }
- };
-#endif
-
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN RK30_PIN0_PB7
-
-static int mma8452_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data mma8452_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma8452_init_platform_hw,
- .orientation = {-1, 0, 0, 0, 0, 1, 0, 1, 0},
-};
-#endif
-
-/*MMA7660 gsensor*/
-#if defined (CONFIG_GS_MMA7660)
-#define MMA7660_INT_PIN RK30_PIN0_PB7
-
-static int mma7660_init_platform_hw(void)
-{
- //rk30_mux_api_set(GPIO1B2_SPI_RXD_UART1_SIN_NAME, GPIO1B_GPIO1B2);
-
- return 0;
-}
-
-static struct sensor_platform_data mma7660_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma7660_init_platform_hw,
- #ifdef CONFIG_TOUCHSCREEN_GSLX680_RK3028
- .orientation = {-1, 0, 0, 0, -1, 0, 0, 0, 1},
- #else
- .orientation = {0, -1, 0, -1, 0, 0, 0, 0, -1},
- #endif
-};
-#endif
-
-#if defined (CONFIG_GS_MXC6225)
-#define MXC6225_INT_PIN RK30_PIN0_PB1
-
-static int mxc6225_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data mxc6225_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 0,
- .poll_delay_ms = 30,
- .init_platform_hw = mxc6225_init_platform_hw,
- .orientation = { 0, -1, 0, 1, 0, 0, 0, 0, 0},
-};
-#endif
-
-#if defined (CONFIG_GS_LIS3DH)
-#define LIS3DH_INT_PIN RK30_PIN0_PB7
-
-static int lis3dh_init_platform_hw(void)
-{
-
- return 0;
-}
-
-static struct sensor_platform_data lis3dh_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lis3dh_init_platform_hw,
- .orientation = {-1, 0, 0, 0, 0, 1, 0, -1, 0},
-};
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
-static struct sensor_platform_data akm8975_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-#if defined(CONFIG_GYRO_L3G4200D)
-
-#include <linux/l3g4200d.h>
-#define L3G4200D_INT_PIN RK30_PIN0_PB4
-
-static int l3g4200d_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data l3g4200d_info = {
- .type = SENSOR_TYPE_GYROSCOPE,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
- .init_platform_hw = l3g4200d_init_platform_hw,
- .x_min = 40,//x_min,y_min,z_min = (0-100) according to hardware
- .y_min = 40,
- .z_min = 20,
-};
-
-#endif
-
-#ifdef CONFIG_LS_CM3217
-static struct sensor_platform_data cm3217_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 0,
- .poll_delay_ms = 500,
-};
-
-#endif
-
-#ifdef CONFIG_FB_ROCKCHIP
-
-#define LCD_CS_PIN INVALID_GPIO
-#define LCD_CS_VALUE GPIO_HIGH
-
-#define LCD_EN_PIN RK30_PIN0_PB6
-#define LCD_EN_VALUE GPIO_LOW
-
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
-
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_CS_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_CS_PIN);
- printk(KERN_ERR "request lcd cs pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_CS_PIN, LCD_CS_VALUE);
- }
- }
-
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_EN_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_EN_PIN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_EN_PIN, LCD_EN_VALUE);
- }
- }
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, !LCD_CS_VALUE);
- }
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, !LCD_EN_VALUE);
- }
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE);
- }
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
- }
- return 0;
-}
-
-#if defined(CONFIG_LCDC0_RK3066B)
-struct rk29fb_info lcdc0_screen_info = {
- .prop = EXTEND, //extend display device
- .io_init = NULL,
- .io_disable = NULL,
- .io_enable = NULL,
- .set_screen_info = hdmi_init_lcdc,
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B)
-struct rk29fb_info lcdc1_screen_info = {
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B)
-static struct resource resource_lcdc0[] = {
- [0] = {
- .name = "lcdc0 reg",
- .start = RK30_LCDC0_PHYS,
- .end = RK30_LCDC0_PHYS + RK30_LCDC0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc0 irq",
- .start = IRQ_LCDC0,
- .end = IRQ_LCDC0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc0 = {
- .name = "rk30-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc0),
- .resource = resource_lcdc0,
- .dev = {
- .platform_data = &lcdc0_screen_info,
- },
-};
-#endif
-#if defined(CONFIG_LCDC1_RK3066B)
-static struct resource resource_lcdc1[] = {
- [0] = {
- .name = "lcdc1 reg",
- .start = RK30_LCDC1_PHYS,
- .end = RK30_LCDC1_PHYS + RK30_LCDC1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc1 irq",
- .start = IRQ_LCDC1,
- .end = IRQ_LCDC1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc1 = {
- .name = "rk30-lcdc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resource_lcdc1),
- .resource = resource_lcdc1,
- .dev = {
- .platform_data = &lcdc1_screen_info,
- },
-};
-#endif
-
-#if defined(CONFIG_MFD_RK610)
-#define RK610_RST_PIN RK30_PIN2_PD5
-#define RK610_TEST_PIN RK30_PIN2_PD6
-#define RK610_ENABLE_PIN RK30_PIN0_PC5
-static int rk610_power_on_init(void)
-{
- int ret;
- if(RK610_ENABLE_PIN != INVALID_GPIO)
- {
- ret = gpio_request(RK610_ENABLE_PIN, "rk610 reset");
- if (ret)
- {
- printk(KERN_ERR "rk610_control_probe request gpio fail\n");
- }
- else
- {
- gpio_direction_output(RK610_ENABLE_PIN, GPIO_HIGH);
- msleep(100);
- }
- }
- if(RK610_TEST_PIN != INVALID_GPIO)
- {
- ret = gpio_request(RK610_TEST_PIN, "rk610 reset");
- if (ret)
- {
- printk(KERN_ERR "rk610_control_probe request gpio fail\n");
- }
- else
- {
- gpio_direction_output(RK610_TEST_PIN, GPIO_LOW);
- msleep(100);
- }
- }
- if(RK610_RST_PIN != INVALID_GPIO)
- {
- ret = gpio_request(RK610_RST_PIN, "rk610 reset");
- if (ret)
- {
- printk(KERN_ERR "rk610_control_probe request gpio fail\n");
- }
- else
- {
- gpio_direction_output(RK610_RST_PIN, GPIO_HIGH);
- msleep(100);
- gpio_direction_output(RK610_RST_PIN, GPIO_LOW);
- msleep(100);
- gpio_set_value(RK610_RST_PIN, GPIO_HIGH);
- }
- }
-
- return 0;
-
-}
-
-
-static struct rk610_ctl_platform_data rk610_ctl_pdata = {
- .rk610_power_on_init = rk610_power_on_init,
-};
-#endif
-
-#ifdef CONFIG_SND_SOC_RK610
-static int rk610_codec_io_init(void)
-{
-//if need iomux.
-//Must not gpio_request
- return 0;
-}
-
-static struct rk610_codec_platform_data rk610_codec_pdata = {
- .spk_ctl_io = RK30_PIN3_PC7,
- .io_init = rk610_codec_io_init,
- .boot_depop = 1,
-};
-#endif
-
-#ifdef CONFIG_ANDROID_TIMED_GPIO
-static struct timed_gpio timed_gpios[] = {
- {
- .name = "vibrator",
- .gpio = INVALID_GPIO,
- .max_timeout = 1000,
- .active_low = 0,
- .adjust_time =20, //adjust for diff product
- },
-};
-
-static struct timed_gpio_platform_data rk29_vibrator_info = {
- .num_gpios = 1,
- .gpios = timed_gpios,
-};
-
-static struct platform_device rk29_device_vibrator = {
- .name = "timed-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_vibrator_info,
- },
-
-};
-#endif
-
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
-static struct gpio_led rk29_leds[] = {
- {
- .name = "button-backlight",
- .gpio = INVALID_GPIO,
- .default_trigger = "timer",
- .active_low = 0,
- .retain_state_suspended = 0,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- },
-};
-
-static struct gpio_led_platform_data rk29_leds_pdata = {
- .leds = rk29_leds,
- .num_leds = ARRAY_SIZE(rk29_leds),
-};
-
-static struct platform_device rk29_device_gpio_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_leds_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_RK_IRDA
-#define IRDA_IRQ_PIN INVALID_GPIO //RK30_PIN0_PA3
-
-static int irda_iomux_init(void)
-{
- int ret = 0;
-
- //irda irq pin
- ret = gpio_request(IRDA_IRQ_PIN, NULL);
- if (ret != 0) {
- gpio_free(IRDA_IRQ_PIN);
- printk(">>>>>> IRDA_IRQ_PIN gpio_request err \n ");
- }
- gpio_pull_updown(IRDA_IRQ_PIN, PullDisable);
- gpio_direction_input(IRDA_IRQ_PIN);
-
- return 0;
-}
-
-static int irda_iomux_deinit(void)
-{
- gpio_free(IRDA_IRQ_PIN);
- return 0;
-}
-
-static struct irda_info rk29_irda_info = {
- .intr_pin = IRDA_IRQ_PIN,
- .iomux_init = irda_iomux_init,
- .iomux_deinit = irda_iomux_deinit,
- //.irda_pwr_ctl = bu92747guw_power_ctl,
-};
-
-static struct platform_device irda_device = {
-#ifdef CONFIG_RK_IRDA_NET
- .name = "rk_irda",
-#else
- .name = "bu92747_irda",
-#endif
- .id = -1,
- .dev = {
- .platform_data = &rk29_irda_info,
- }
-};
-#endif
-
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and sdio.noted by xbw at 2012-03-05
-**************************************************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "board-rk3028-86v-sdmmc-conifg.c"
-#include "../plat-rk/rk-sdmmc-ops.c"
-#include "../plat-rk/rk-sdmmc-wifi.c"
-#endif //endif ---#ifdef CONFIG_SDMMC_RK29
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- iomux_set(MMC0_CMD);
- iomux_set(MMC0_CLKOUT);
- iomux_set(MMC0_D0);
- iomux_set(MMC0_D1);
- iomux_set(MMC0_D2);
- iomux_set(MMC0_D3);
-
- iomux_set_gpio_mode(iomux_mode_to_gpio(MMC0_DETN));
-
- gpio_request(RK30_PIN3_PA7, "sdmmc-power");
- gpio_direction_output(RK30_PIN3_PA7, GPIO_LOW);
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- #if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set_gpio_mode(iomux_gpio_to_mode(RK29SDK_SD_CARD_DETECT_N));
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO);
- #endif
- #else
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(MMC0_DETN);
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FMUX);
- #endif
- #endif
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) && defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- .status = rk29sdk_wifi_mmc0_status,
- .register_status_notify = rk29sdk_wifi_mmc0_status_register,
-#endif
-
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .power_en = RK29SDK_SD_CARD_PWR_EN,
- .power_en_level = RK29SDK_SD_CARD_PWR_EN_LEVEL,
-#else
- .power_en = INVALID_GPIO,
- .power_en_level = GPIO_LOW,
-#endif
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC0_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- .det_pin_info = {
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N, //INVALID_GPIO,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
- #endif
- },
-
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- iomux_set(MMC1_CMD);
- iomux_set(MMC1_CLKOUT);
- iomux_set(MMC1_D0);
- iomux_set(MMC1_D1);
- iomux_set(MMC1_D2);
- iomux_set(MMC1_D3);
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC) || defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC1_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- #if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
- .sdio_INT_gpio = RK29SDK_WIFI_SDIO_CARD_INT,
- #ifdef USE_SDIO_INT_LEVEL
- .sdio_INT_level = RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE,
- #endif
- #endif
-
- .det_pin_info = {
-#if defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- #else
- .io = INVALID_GPIO,
- #endif
-
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-
- .enable_sd_wakeup = 0,
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-/**************************************************************************************************
- * the end of setting for SDMMC devices
-**************************************************************************************************/
-
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = RK30_PIN0_PB7,
- .batt_low_pin = INVALID_GPIO,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = RK30_PIN1_PB2,
- .usb_det_pin = INVALID_GPIO,
- .dc_det_level = GPIO_LOW,
- .charge_ok_level = GPIO_HIGH,
-
- .reference_voltage = 1800, // the rK2928 is 3300;RK3066 and rk29 are 2500;rk3066B is 1800;
- .pull_up_res = 200, //divider resistance , pull-up resistor
- .pull_down_res = 120, //divider resistance , pull-down resistor
-
- .is_reboot_charging = 1,
- .save_capacity = 1 ,
- .low_voltage_protection = 3600,
-};
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-#ifdef CONFIG_RK30_PWM_REGULATOR
-static int pwm_voltage_map[] = {
- 950000,975000,1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000, 1375000, 1400000
-};
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_cpu",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] =
-{
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
- #if defined (CONFIG_MACH_RK3028_TB)
- .pwm_id = 2,
- .pwm_gpio = RK30_PIN3_PD5,
- .pwm_iomux_pwm = PWM2,
- .pwm_iomux_gpio = GPIO3_D5,
- #else
- .pwm_id = 1,
- .pwm_gpio = RK30_PIN3_PD4,
- .pwm_iomux_pwm = PWM1,
- .pwm_iomux_gpio = GPIO3_D4,
-
- #endif
- .pwm_voltage = 1100000,
- .suspend_voltage = 1000000,
- .min_uV = 950000,
- .max_uV = 1400000,
- .coefficient = 504, //57.5%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-#endif
-
-#ifdef CONFIG_RK29_VMAC
-#define PHY_PWR_EN_GPIO RK30_PIN1_PD6
-#include "board-rk30-sdk-vmac.c"
-#endif
-
-#ifdef CONFIG_RFKILL_RK
-// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
-static struct rfkill_rk_platform_data rfkill_rk_platdata = {
- .type = RFKILL_TYPE_BLUETOOTH,
-
- .poweron_gpio = { // BT_REG_ON
- .io = INVALID_GPIO, //RK30_PIN3_PC7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_poweron",
- .fgpio = GPIO3_C7,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN3_PC7, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_reset",
- .fgpio = GPIO3_C7,
- },
- },
-
- .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
- .io = RK30_PIN3_PC6, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_wake",
- .fgpio = GPIO3_C6,
- },
- },
-
- .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .gpio = {
- .io = RK30_PIN0_PA5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
- .iomux = {
- .name = NULL,
- },
- },
- },
-
- .rts_gpio = { // UART_RTS, enable or disable BT's data coming
- .io = RK30_PIN1_PA3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_rts",
- .fgpio = GPIO1_A3,
- .fmux = UART0_RTSN,
- },
- },
-};
-
-static struct platform_device device_rfkill_rk = {
- .name = "rfkill_rk",
- .id = -1,
- .dev = {
- .platform_data = &rfkill_rk_platdata,
- },
-};
-#endif
-
-#if defined(CONFIG_GPS_RK)
-int rk_gps_io_init(void)
-{
- printk("%s \n", __FUNCTION__);
-
- gpio_request(RK30_PIN1_PB5, NULL);
- gpio_direction_output(RK30_PIN1_PB5, GPIO_LOW);
-
- iomux_set(GPS_RFCLK);//GPS_CLK
- iomux_set(GPS_MAG);//GPS_MAG
- iomux_set(GPS_SIG);//GPS_SIGN
-
- gpio_request(RK30_PIN1_PA6, NULL);
- gpio_direction_output(RK30_PIN1_PA6, GPIO_LOW);
-
- gpio_request(RK30_PIN1_PA5, NULL);
- gpio_direction_output(RK30_PIN1_PA5, GPIO_LOW);
-
- gpio_request(RK30_PIN1_PA7, NULL);
- gpio_direction_output(RK30_PIN1_PA7, GPIO_LOW);
- return 0;
-}
-int rk_gps_power_up(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_power_down(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_reset_set(int level)
-{
- return 0;
-}
-int rk_enable_hclk_gps(void)
-{
- struct clk *gps_aclk = NULL;
- gps_aclk = clk_get(NULL, "aclk_gps");
- if(gps_aclk) {
- clk_enable(gps_aclk);
- clk_put(gps_aclk);
- printk("%s \n", __FUNCTION__);
- }
- else
- printk("get gps aclk fail\n");
- return 0;
-}
-int rk_disable_hclk_gps(void)
-{
- struct clk *gps_aclk = NULL;
- gps_aclk = clk_get(NULL, "aclk_gps");
- if(gps_aclk) {
- //TO wait long enough until GPS ISR is finished.
- msleep(5);
- clk_disable(gps_aclk);
- clk_put(gps_aclk);
- printk("%s \n", __FUNCTION__);
- }
- else
- printk("get gps aclk fail\n");
- return 0;
-}
-struct rk_gps_data rk_gps_info = {
- .io_init = rk_gps_io_init,
- .power_up = rk_gps_power_up,
- .power_down = rk_gps_power_down,
- .reset = rk_gps_reset_set,
- .enable_hclk_gps = rk_enable_hclk_gps,
- .disable_hclk_gps = rk_disable_hclk_gps,
- .GpsSign = RK30_PIN1_PB3,
- .GpsMag = RK30_PIN1_PB2, //GPIO index
- .GpsClk = RK30_PIN1_PB4, //GPIO index
- .GpsVCCEn = RK30_PIN1_PB5, //GPIO index
- .GpsSpi_CSO = RK30_PIN1_PA4, //GPIO index
- .GpsSpiClk = RK30_PIN1_PA5, //GPIO index
- .GpsSpiMOSI = RK30_PIN1_PA7, //GPIO index
- .GpsIrq = IRQ_GPS,
- .GpsSpiEn = 0,
- .GpsAdcCh = 2,
- .u32GpsPhyAddr = RK30_GPS_PHYS,
- .u32GpsPhySize = RK30_GPS_SIZE,
-};
-
-struct platform_device rk_device_gps = {
- .name = "gps_hv5820b",
- .id = -1,
- .dev = {
- .platform_data = &rk_gps_info,
- }
- };
-#endif
-
-#if defined(CONFIG_MT5931_MT6622)
-static struct mt6622_platform_data mt6622_platdata = {
- .power_gpio = { // BT_REG_ON
- .io = RK30_PIN3_PD5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN0_PD7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .irq_gpio = {
- .io = RK30_PIN0_PA5,
- .enable = GPIO_LOW,
- .iomux = {
- .name = NULL,
- },
- },
-
- .rts_gpio = { // UART_RTS
- .io = RK30_PIN1_PA3,
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_rts",
- .fgpio = GPIO1_A3,
- .fmux = UART0_RTSN,
- },
- },
-};
-
-static struct platform_device device_mt6622 = {
- .name = "mt6622",
- .id = -1,
- .dev = {
- .platform_data = &mt6622_platdata,
- },
-};
-#endif
-
-#if defined CONFIG_TCC_BT_DEV
-static struct tcc_bt_platform_data tcc_bt_platdata = {
-
- .power_gpio = { // ldoon
- .io = RK30_PIN3_PC0,//difined depend on your harware
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .wake_host_gpio = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .io = RK30_PIN0_PC5, // set io to INVALID_GPIO for disable it,it's depend on your hardware
- .enable = IRQF_TRIGGER_RISING,// set IRQF_TRIGGER_FALLING for falling, set IRQF_TRIGGER_RISING for rising
- .iomux = {
- .name = NULL,
- },
- },
-};
-
-static struct platform_device device_tcc_bt = {
- .name = "tcc_bt_dev",
- .id = -1,
- .dev = {
- .platform_data = &tcc_bt_platdata,
- },
-};
-#endif
-
-
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_ANDROID_TIMED_GPIO
- &rk29_device_vibrator,
-#endif
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
- &rk29_device_gpio_leds,
-#endif
-#ifdef CONFIG_RK_IRDA
- &irda_device,
-#endif
-#if defined(CONFIG_WIFI_CONTROL_FUNC)||defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- &rk29sdk_wifi_device,
-#endif
-
-#if defined(CONFIG_MT6620)
- &mt3326_device_gps,
-#endif
-
-#ifdef CONFIG_RK29_SUPPORT_MODEM
- &rk30_device_modem,
-#endif
-#if defined(CONFIG_MU509)
- &rk29_device_mu509,
-#endif
-#if defined(CONFIG_MW100)
- &rk29_device_mw100,
-#endif
-#if defined(CONFIG_MT6229)
- &rk29_device_mt6229,
-#endif
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
- &rk30_device_adc_battery,
-#endif
-#ifdef CONFIG_RFKILL_RK
- &device_rfkill_rk,
-#endif
-#ifdef CONFIG_GPS_RK
- &rk_device_gps,
-#endif
-
-#ifdef CONFIG_MT5931_MT6622
- &device_mt6622,
-#endif
-#ifdef CONFIG_TCC_BT_DEV
- &device_tcc_bt,
-#endif
-};
-
-static int rk_platform_add_display_devices(void)
-{
- struct platform_device *fb = NULL; //fb
- struct platform_device *lcdc0 = NULL; //lcdc0
- struct platform_device *lcdc1 = NULL; //lcdc1
- struct platform_device *bl = NULL; //backlight
-#ifdef CONFIG_FB_ROCKCHIP
- fb = &device_fb;
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B)
- lcdc0 = &device_lcdc0,
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B)
- lcdc1 = &device_lcdc1,
-#endif
-
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- bl = &rk29_device_backlight,
-#endif
- __rk_platform_add_display_devices(fb,lcdc0,lcdc1,bl);
-
- return 0;
-
-}
-
-#ifdef CONFIG_MFD_TPS65910
-#define TPS65910_HOST_IRQ RK30_PIN0_PB5
-
-#define PMU_POWER_SLEEP RK30_PIN1_PB5
-
-static struct pmu_info tps65910_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1100000,
- .max_uv = 1100000,
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1100000,
- .max_uv = 1100000,
- },
- {
- .name = "vio", //vcc_io
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
-
-};
-static struct pmu_info tps65910_ldo_info[] = {
- /*{
- .name = "vpll", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- },*/
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "vdig2", //vdd11
- .min_uv = 1100000,
- .max_uv = 1100000,
- },
- {
- .name = "vaux1", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "vaux2", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vaux33", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vmmc", //vcca30
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
- {
- .name = "vdac", //vcc18
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- };
-
-#include "board-pmu-tps65910.c"
-#endif
-#ifdef CONFIG_REGULATOR_ACT8931
-#define ACT8931_HOST_IRQ RK30_PIN0_PB5//depend on your hardware
-
-
-#define ACT8931_CHGSEL_PIN RK30_PIN0_PD0 //depend on your hardware
-
-
-static struct pmu_info act8931_dcdc_info[] = {
- {
- .name = "vdd_core", //vdd_logic
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "act_dcdc2", //ddr
- .min_uv = 1500000,
- .max_uv = 1500000,
- },
- {
- .name = "vdd_cpu", //vdd_arm
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
-
-};
-static struct pmu_info act8931_ldo_info[] = {
- {
- .name = "act_ldo1", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "act_ldo2", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo3", //vcca30
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
- {
- .name = "act_ldo4", //vcc_wl
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
-};
-#include "board-rk30-sdk-act8931.c"
-#endif
-
-// i2c
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-#if defined (CONFIG_REGULATOR_ACT8931)
- {
- .type = "act8931",
- .addr = 0x5b,
- .flags = 0,
- .irq = ACT8931_HOST_IRQ,
- .platform_data=&act8931_data,
- },
-#endif
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1d,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_GS_LIS3DH)
- {
- .type = "gs_lis3dh",
- .addr = 0x19, //0x19(SA0-->VCC), 0x18(SA0-->GND)
- .flags = 0,
- .irq = LIS3DH_INT_PIN,
- .platform_data = &lis3dh_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8975_info,
- },
-#endif
-#if defined (CONFIG_GYRO_L3G4200D)
- {
- .type = "l3g4200d_gryo",
- .addr = 0x69,
- .flags = 0,
- .irq = L3G4200D_INT_PIN,
- .platform_data = &l3g4200d_info,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RT5631)
- {
- .type = "rt5631",
- .addr = 0x1a,
- .flags = 0,
- },
-#endif
-
-
-};
-#endif
-
-int __sramdata g_pmic_type = 0;
-#ifdef CONFIG_I2C1_RK30
-#ifdef CONFIG_MFD_WM831X_I2C
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info wm8326_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "dcdc3", //ddr
- .min_uv = 1150000,
- .max_uv = 1150000,
- .suspend_vol = 1150000,
- },
- #ifdef CONFIG_MACH_RK3066_SDK
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3000000,
- },
- #else
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3000000,
- .max_uv = 3000000,
- .suspend_vol = 2800000,
- },
- #endif
-};
-
-static struct pmu_info wm8326_ldo_info[] = {
- {
- .name = "ldo1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo2", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo3", //
- .min_uv = 1100000,
- .max_uv = 1100000,
- .suspend_vol = 1100000,
- },
- {
- .name = "ldo4", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 1000000,
- },
- {
- .name = "ldo5", //vcc25
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo6", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo7", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- .suspend_vol = 2800000,
- },
- {
- .name = "ldo8", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo9", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo10", //flash_io
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
-};
-
-#include "../mach-rk30/board-pmu-wm8326.c"
-#endif
-
-#ifdef CONFIG_REGULATOR_ACT8846
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-#define PMU_VSEL RK30_PIN3_PD3
-static struct pmu_info act8846_dcdc_info[] = {
- {
- .name = "act_dcdc1", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- .suspend_vol = 1200000,
- },
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 1200000,
- #else
- .suspend_vol = 900000,
- #endif
-
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 1200000,
- #else
- .suspend_vol = 900000,
- #endif
-
- },
- {
- .name = "act_dcdc4", //vccio
- .min_uv = 3000000,
- .max_uv = 3000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 3000000,
- #else
- .suspend_vol = 2800000,
- #endif
-
- },
-
-};
-static struct pmu_info act8846_ldo_info[] = {
- {
- .name = "act_ldo1", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "act_ldo2", //vdd12
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "act_ldo3", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo4", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo5", //vcctp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo6", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo7", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo8", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- };
-
-#include "../mach-rk30/board-pmu-act8846.c"
-#endif
-
-
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_MFD_WM831X_I2C)
- {
- .type = "wm8326",
- .addr = 0x34,
- .flags = 0,
- .irq = RK30_PIN0_PB3,
- .platform_data = &wm831x_platdata,
- },
-#endif
-#if defined (CONFIG_REGULATOR_ACT8846)
- {
- .type = "act8846",
- .addr = 0x5a,
- .flags = 0,
- // .irq = ACT8846_HOST_IRQ,
- .platform_data=&act8846_data,
- },
-#endif
-#if defined (CONFIG_RTC_HYM8563)
- {
- .type = "rtc_hym8563",
- .addr = 0x51,
- .flags = 0,
- .irq = RK30_PIN1_PA4,
- },
-#endif
-#if defined (CONFIG_GS_MXC6225)
- {
- .type = "gs_mxc6225",
- .addr = 0x15,
- .flags = 0,
- .irq = MXC6225_INT_PIN,
- .platform_data = &mxc6225_info,
- },
-#endif
-};
-#endif
-
-void __sramfunc board_pmu_suspend(void)
-{
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_suspend();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_suspend();
- #endif
- #if defined (CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- board_pmu_act8846_suspend();
- #endif
-
-}
-
-void __sramfunc board_pmu_resume(void)
-{
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_resume();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_resume();
- #endif
- #if defined (CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- board_pmu_act8846_resume();
- #endif
-}
-
- int __sramdata gpio3d6_iomux,gpio3d6_do,gpio3d6_dir,gpio3d6_en;
-
-#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
-
-void __sramfunc rk30_pwm_logic_suspend_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
-
-// int gpio0d7_iomux,gpio0d7_do,gpio0d7_dir,gpio0d7_en;
- sram_udelay(10000);
- gpio3d6_iomux = grf_readl(GRF_GPIO3D_IOMUX);
- gpio3d6_do = grf_readl(GRF_GPIO3H_DO);
- gpio3d6_dir = grf_readl(GRF_GPIO3H_DIR);
- gpio3d6_en = grf_readl(GRF_GPIO3H_EN);
-
- grf_writel((1<<28), GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DIR);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DO);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_EN);
-#endif
-}
-void __sramfunc rk30_pwm_logic_resume_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- grf_writel((1<<28)|gpio3d6_iomux, GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|gpio3d6_en, GRF_GPIO3H_EN);
- grf_writel((1<<30)|gpio3d6_dir, GRF_GPIO3H_DIR);
- grf_writel((1<<30)|gpio3d6_do, GRF_GPIO3H_DO);
- sram_udelay(10000);
-
-#endif
-
-}
-extern void pwm_suspend_voltage(void);
-extern void pwm_resume_voltage(void);
-void rk30_pwm_suspend_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_suspend_voltage();
-#endif
-}
-void rk30_pwm_resume_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_resume_voltage();
-#endif
-}
-
-
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-#if defined (CONFIG_TOUCHSCREEN_GT8XX)
- {
- .type = "Goodix-TS",
- .addr = 0x55,
- .flags = 0,
- .irq = RK30_PIN0_PB4,
- .platform_data = &goodix_info,
- },
-#endif
-#if defined (CONFIG_LS_CM3217)
- {
- .type = "lightsensor",
- .addr = 0x10,
- .flags = 0,
- .platform_data = &cm3217_info,
- },
-#endif
-#if defined (CONFIG_TOUCHSCREEN_GSLX680_RK3028)
- {
- .type = "gslX680",
- .addr = 0x40,
- .flags = 0,
- .platform_data =&gslx680_info,
- },
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C4_RK30
-static struct i2c_board_info __initdata i2c4_info[] = {
-#ifdef CONFIG_MFD_RK610
- {
- .type = "rk610_ctl",
- .addr = 0x40,
- .flags = 0,
- .platform_data = &rk610_ctl_pdata,
- },
-#ifdef CONFIG_RK610_TVOUT
- {
- .type = "rk610_tvout",
- .addr = 0x42,
- .flags = 0,
- },
-#endif
-#ifdef CONFIG_HDMI_RK610
- {
- .type = "rk610_hdmi",
- .addr = 0x46,
- .flags = 0,
- .irq = INVALID_GPIO,
- },
-#endif
-#ifdef CONFIG_SND_SOC_RK610
- {//RK610_CODEC addr from 0x60 to 0x80 (0x60~0x80)
- .type = "rk610_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- .platform_data = &rk610_codec_pdata,
- },
-#endif
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO// RK30_PIN2_PD6 //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO//RK30_PIN2_PD7 //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- //set iomux (gpio) here
- //rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME, GPIO2D_GPIO2D7);
- //rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME, GPIO2D_GPIO2D6);
-
- return 0;
-}
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C4_RK30
- i2c_register_board_info(4, i2c4_info, ARRAY_SIZE(i2c4_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(5, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-
-// ========== Begin of rk3168 top board keypad defination ============
-
-#include <plat/key.h>
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK30_PIN1_PB4,
- .active_low = PRESS_LEV_LOW,
- .wakeup = 1,
- },
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = 1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
-// =========== End of rk3168 top board keypad defination =============
-
-
-#define POWER_ON_PIN RK30_PIN0_PD5 //power_hold
-static void rk30_pm_power_off(void)
-{
- printk(KERN_ERR "rk30_pm_power_off start...\n");
- #if defined(CONFIG_MFD_WM831X)
- if(pmic_is_wm8326()){
- wm831x_set_bits(Wm831x,WM831X_GPIO_LEVEL,0x0001,0x0000); //set sys_pwr 0
- wm831x_device_shutdown(Wm831x);//wm8326 shutdown
- }
- #endif
-
- #if defined(CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- {
- act8846_device_shutdown();
- }
- #endif
-
- #if defined(CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- {
- tps65910_device_shutdown();//tps65910 shutdown
- }
- #endif
- #if defined(CONFIG_REGULATOR_ACT8931)
- if(pmic_is_act8931())
- {
- act8931_device_shutdown();//act8931 shutdown
- }
- #endif
-
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
- while (1);
-}
-
-static void __init machine_rk30_board_init(void)
-{
- avs_init();
- gpio_request(POWER_ON_PIN, "poweronpin");
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
- pm_power_off = rk30_pm_power_off;
-
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
-
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- rk_platform_add_display_devices();
- board_usb_detect_init(RK30_PIN0_PA4);
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC)
- rk29sdk_wifi_bt_gpio_control_init();
-#elif defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- rk29sdk_wifi_combo_module_gpio_init();
-#endif
-
-#if defined(CONFIG_MT6620)
- clk_set_rate(clk_get_sys("rk_serial.0", "uart"), 48*1000000);
-#endif
-
-#if defined(CONFIG_MT5931_MT6622)
- clk_set_rate(clk_get_sys("rk_serial.0", "uart"), 24*1000000);
-#endif
-}
-
-static void __init rk30_reserve(void)
-{
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0 buf", get_fb_size());
- resource_fb[0].end = resource_fb[0].start + get_fb_size()- 1;
-#if 0
- resource_fb[1].start = board_mem_reserve_add("ipp buf", RK30_FB0_MEM_SIZE);
- resource_fb[1].end = resource_fb[1].start + RK30_FB0_MEM_SIZE - 1;
-#endif
-
-#if defined(CONFIG_FB_ROTATE) || !defined(CONFIG_THREE_FB_BUFFER)
- resource_fb[2].start = board_mem_reserve_add("fb2 buf",get_fb_size());
- resource_fb[2].end = resource_fb[2].start + get_fb_size() - 1;
-#endif
-#endif
-
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
-
-#ifdef CONFIG_GPS_RK
- //it must be more than 8MB
- rk_gps_info.u32MemoryPhyAddr = board_mem_reserve_add("gps", SZ_8M);
-#endif
- board_mem_reserved();
-}
-
-/**
- * dvfs_cpu_logic_table: table for arm and logic dvfs
- * @frequency : arm frequency
- * @cpu_volt : arm voltage depend on frequency
- * @logic_volt : logic voltage arm requests depend on frequency
- * comments : min arm/logic voltage
- */
-#ifdef CONFIG_DVFS_WITH_UOC
-//chenxing uoc
-static struct cpufreq_frequency_table dvfs_arm_table[] = {
- {.frequency = 312 * 1000, .index = 950 * 1000},
- {.frequency = 504 * 1000, .index = 1000 * 1000},
- {.frequency = 816 * 1000, .index = 1050 * 1000},
- {.frequency = 1008 * 1000, .index = 1125 * 1000},
- {.frequency = 1200 * 1000, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- {.frequency = 100 * 1000, .index = 1000 * 1000},
- {.frequency = 200 * 1000, .index = 1000 * 1000},
- {.frequency = 266 * 1000, .index = 1050 * 1000},
- //{.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1125 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 1000 * 1000},
- {.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = 1050 * 1000},
- {.frequency = 400 * 1000 + DDR_FREQ_NORMAL, .index = 1100 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-#else
-//chenliang
-static struct cpufreq_frequency_table dvfs_arm_table[] = {
- {.frequency = 312 * 1000, .index = 1000 * 1000},
- {.frequency = 504 * 1000, .index = 1050 * 1000},
- {.frequency = 816 * 1000, .index = 1100 * 1000},
- {.frequency = 1008 * 1000, .index = 1150 * 1000},
- //{.frequency = 1200 * 1000, .index = 1200 * 1000},
- //{.frequency = 1416 * 1000, .index = 1250 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- {.frequency = 100 * 1000, .index = 1000 * 1000},
- {.frequency = 200 * 1000, .index = 1000 * 1000},
- {.frequency = 266 * 1000, .index = 1050 * 1000},
- {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1125 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- //{.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 1000 * 1000},
- //{.frequency = 240 * 1000 + DDR_FREQ_VIDEO, .index = 1050 * 1000},
- {.frequency = 336 * 1000 + DDR_FREQ_NORMAL, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-#endif
-//#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
-//static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
-//static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
-int get_max_freq(struct cpufreq_frequency_table *table)
-{
- int i,temp=0;
-
- for(i=0;table[i].frequency!= CPUFREQ_TABLE_END;i++)
- {
- if(temp<table[i].frequency)
- temp=table[i].frequency;
- }
- printk("get_max_freq=%d\n",temp);
- return temp;
-}
-
-void __init board_clock_init(void)
-{
- u32 flags=RK30_CLOCKS_DEFAULT_FLAGS;
-#if !defined(CONFIG_ARCH_RK3188)
- if(get_max_freq(dvfs_gpu_table)<=(400*1000))
- {
- flags=RK30_CLOCKS_DEFAULT_FLAGS|CLK_GPU_GPLL;
- }
- else
- flags=RK30_CLOCKS_DEFAULT_FLAGS|CLK_GPU_CPLL;
-#endif
- rk30_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
- //dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "cpu"), dvfs_arm_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
-}
-
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk30_fixup,
- .reserve = &rk30_reserve,
- .map_io = rk30_map_io,
- .init_irq = rk30_init_irq,
- .timer = &rk30_timer,
- .init_machine = machine_rk30_board_init,
-MACHINE_END
+++ /dev/null
-/*****************************************************************************************
- * arch/arm/mach-rkxx/baord-xxx-sdmmc-config.c
- *
- * Copyright (C) 2013 ROCKCHIP, Inc.
- *
- * Description:
- * define the gpio for SD-MMC-SDIO-Wifi functions according to your own projects.
- *
- * Author: Michael Xie
- * 15 Jan,2013
- * E-mail: xbw@rock-chips.com
- *
- ******************************************************************************************/
-
-/*
-** If you select the macro of CONFIG_SDMMC0_RK29_WRITE_PROTECT, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define SDMMC0_WRITE_PROTECT_PIN RK30_PIN3_PB2 //According to your own project to set the value of write-protect-pin.
-//#define SDMMC0_WRITE_PROTECT_ENABLE_VALUE GPIO_HIGH
-
-/*
-** If you select the macro of CONFIG_SDMMC1_RK29_WRITE_PROTECT, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define SDMMC1_WRITE_PROTECT_PIN RK30_PIN3_PB3 //According to your own project to set the value of write-protect-pin.
-//#define SDMMC1_WRITE_PROTECT_ENABLE_VALUE GPIO_HIGH
-
-/*
-** If you select the macro of CONFIG_RK29_SDIO_IRQ_FROM_GPIO, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define RK29SDK_WIFI_SDIO_CARD_INT RK30_PIN3_PD2
-
-
-/*
-* define sdcard PowerEn-pin
-*/
-#define RK29SDK_SD_CARD_PWR_EN RK30_PIN3_PA1
-#define RK29SDK_SD_CARD_PWR_EN_LEVEL GPIO_LOW
-int rk31sdk_get_sdmmc0_pin_io_voltage(void)
-{
- int voltage;
-#define RK31SDK_SET_SDMMC0_PIN_VOLTAGE
-
- /**************************************************************************************
- ** Please tell me how much voltage of your SDMMC0-pin in your project.
- **
- ** ÀýÈç: ÓеÄÏîÄ¿£¬ËüµÄSDMMC0ËùÔÚµÄRKÖ÷¿ØµÄIO×飬ÏëÓÃ1.8V, ¶ø¿¨±¾ÉíÓÃ3.3V,
- ** ¶øÖмäͨ¹ý¸öµçƽת»».ÄÇô£¬Äú´Ëʱ£¬Ó¦¸ÃÉèÖÃÏÂÃæµÄvoltageֵΪ 1.8V(¼´1800mv)
- ***************************************************************************************/
- voltage = 3300; //default the voltage 3300mv.
-
- return voltage;
-}
-
-/*
-* define the card-detect-pin.
-*/
-#define RK29SDK_SD_CARD_DETECT_N RK30_PIN3_PB0 //According to your own project to set the value of card-detect-pin.
-#define RK29SDK_SD_CARD_INSERT_LEVEL GPIO_LOW // set the voltage of insert-card. Please pay attention to the default setting.
-
-//wake up host gpio
-#define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
-#define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
-
-/*
-* Define wifi module's power and reset gpio, and gpio sensitive level.
-* Please set the value according to your own project.
-*
-* Well, you just own engineering module to set the value in the corresponding module branch.
-* Otherwise, you do not define this macro, eliminate it.
-*
-*/
-#if defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU)
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_LOW//GPIO_HIGH
-
-#elif defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319) || defined(CONFIG_RK903) || defined(CONFIG_RK901)
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN0_PC2 // RK30_PIN2_PA7
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
-
-#elif defined(CONFIG_MT5931_MT6622) || defined(CONFIG_MT5931)
-
- #ifdef CONFIG_MACH_RK3168_LR097
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- //#define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- //#define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
-
- #else
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN0_PA5
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #endif
-
-#elif defined(CONFIG_MT6620)
- #define COMBO_MODULE_MT6620_CDT 0 // to control antsel2,antsel3 and gps_lan foot when using AcSip or Cdtech chip.
- //- 1--use Cdtech chip; 0--unuse CDT chip
-
- //power, PMU_EN//hjc test
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN0_PB5
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- //reset, DAIRST,SYSRST_B
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- //VDDIO
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL RK30_PIN0_PD2 //You do not get control of the foot, and you do not need to define the macro
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_ENABLE_VALUE GPIO_HIGH
- //WIFI_INT_B
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
- //BGF_INT_B
- #define RK30SDK_WIFI_GPIO_BGF_INT_B RK30_PIN0_PA5
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_ENABLE_VALUE GPIO_HIGH
- //GPS_SYNC
- #define RK30SDK_WIFI_GPIO_GPS_SYNC RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_ENABLE_VALUE GPIO_HIGH
-
- #if COMBO_MODULE_MT6620_CDT
- //ANTSEL2
- #define RK30SDK_WIFI_GPIO_ANTSEL2 RK30_PIN4_PD4
- #define RK30SDK_WIFI_GPIO_ANTSEL2_ENABLE_VALUE GPIO_LOW //use 6620 in CDT chip, LOW--work; High--no work.
- //ANTSEL3
- #define RK30SDK_WIFI_GPIO_ANTSEL3 RK30_PIN4_PD3
- #define RK30SDK_WIFI_GPIO_ANTSEL3_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- //GPS_LAN
- #define RK30SDK_WIFI_GPIO_GPS_LAN RK30_PIN4_PD6
- #define RK30SDK_WIFI_GPIO_GPS_LAN_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- #endif // #if COMBO_MODULE_MT6620_CDT--#endif
-#endif
-
-#ifndef RK30SDK_WIFI_GPIO_WIFI_INT_B
-#define RK30SDK_WIFI_GPIO_WIFI_INT_B INVALID_GPIO
-#define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
-#endif
-
-int rk31sdk_get_sdio_wifi_voltage(void)
-{
- int voltage;
-
- /******************************************************************************
- ** Please tell me how much wifi-module uses voltage in your project.
- ******************************************************************************/
-#if defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319) || defined(CONFIG_RK903) || defined(CONFIG_RK901)
- voltage = 1800 ; //power 1800mV
-
-#elif defined(CONFIG_MT5931_MT6622)||defined(CONFIG_MT5931)
- voltage = 1800 ; //power 1800V
-#elif defined(CONFIG_MT6620)
- voltage = 1800 ; //power 2800V
-#elif defined(CONFIG_RDA5990)||defined(CONFIG_RTL8723AS)
- voltage = 3300 ; //power 3300V
-#else
- //default, sdio use 3.0V
- voltage = 3000 ; //power 3000V
-#endif
-
- return voltage;
-}
-
-
-
+++ /dev/null
-/*
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <mach/dvfs.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <linux/rk_fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/mfd/tps65910.h>
-#include <linux/regulator/act8846.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-
-#if defined(CONFIG_MFD_RK610)
-#include <linux/mfd/rk610_core.h>
-#endif
-
-#if defined(CONFIG_RK_HDMI)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-#if defined(CONFIG_GPS_RK)
-#include "../../../drivers/misc/gps/rk_gps/rk_gps.h"
-#endif
-
-#if defined(CONFIG_MU509)
-#include <linux/mu509.h>
-#endif
-#if defined(CONFIG_MW100)
-#include <linux/mw100.h>
-#endif
-#if defined(CONFIG_MT6229)
-#include <linux/mt6229.h>
-#endif
-#if defined(CONFIG_ANDROID_TIMED_GPIO)
-#include "../../../drivers/staging/android/timed_gpio.h"
-#endif
-
-#if defined(CONFIG_MT6620)
-#include <linux/gps.h>
-#endif
-#include "../mach-rk30/board-rk3168-tb-camera.c"
-
-#if defined(CONFIG_TOUCHSCREEN_GT8XX)
-#define TOUCH_RESET_PIN RK30_PIN0_PC1//RK30_PIN0_PB6
-#define TOUCH_PWR_PIN INVALID_GPIO//RK30_PIN0_PC5 // need to fly line by hardware engineer
-static int goodix_init_platform_hw(void)
-{
- int ret;
-
- if (TOUCH_PWR_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_PWR_PIN, "goodix power pin");
- if (ret != 0) {
- gpio_free(TOUCH_PWR_PIN);
- printk("goodix power error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_PWR_PIN, 0);
- gpio_set_value(TOUCH_PWR_PIN, GPIO_LOW);
- msleep(100);
- }
-
- if (TOUCH_RESET_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_RESET_PIN, "goodix reset pin");
- if (ret != 0) {
- gpio_free(TOUCH_RESET_PIN);
- printk("goodix gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, 1);
- msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_LOW);
- //msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_HIGH);
- //msleep(500);
- }
- return 0;
-}
-
-struct goodix_platform_data goodix_info = {
- .model = 8105,
- .irq_pin = RK30_PIN0_PB4,
- .rest_pin = TOUCH_RESET_PIN,
- .init_platform_hw = goodix_init_platform_hw,
-};
-#endif
-
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-#define PWM_ID 0// 3
-#define PWM_MODE PWM0// PWM3
-#define PWM_EFFECT_VALUE 1
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-#define BL_EN_PIN RK30_PIN0_PC0
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
-
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
- ret = gpio_request(BL_EN_PIN, "bl_en");
- if (ret == 0) {
- gpio_direction_output(BL_EN_PIN, BL_EN_VALUE);
- }
-#endif
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0, pwm_gpio;
-#ifdef LCD_DISP_ON_PIN
- gpio_free(BL_EN_PIN);
-#endif
- pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
- gpio_request(pwm_gpio, "bl_pwm");
- gpio_direction_output(pwm_gpio, GPIO_LOW);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret, pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
-
- ret = gpio_request(pwm_gpio, "bl_pwm");
- if (ret) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return ret;
- }
- gpio_direction_output(pwm_gpio, GPIO_LOW);
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, !BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- int pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
-
- gpio_free(pwm_gpio);
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .min_brightness=20,
- .max_brightness=255,
- .brightness_mode =BRIGHTNESS_MODE_CONIC,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-#endif
-
-#ifdef CONFIG_RK29_SUPPORT_MODEM
-
-#define RK30_MODEM_POWER RK30_PIN0_PC6
-#define RK30_MODEM_POWER_IOMUX iomux_set(GPIO0_C6)
-
-static int rk30_modem_io_init(void)
-{
- printk("%s\n", __FUNCTION__);
- RK30_MODEM_POWER_IOMUX;
-
- return 0;
-}
-
-static struct rk29_io_t rk30_modem_io = {
- .io_addr = RK30_MODEM_POWER,
- .enable = GPIO_HIGH,
- .disable = GPIO_LOW,
- .io_init = rk30_modem_io_init,
-};
-
-static struct platform_device rk30_device_modem = {
- .name = "rk30_modem",
- .id = -1,
- .dev = {
- .platform_data = &rk30_modem_io,
- }
-};
-#endif
-#if defined(CONFIG_MU509)
-static int mu509_io_init(void)
-{
-
- iomux_set(GPIO2_D5);
- iomux_set(GPIO0_C6);
- iomux_set(GPIO2_D4);
- iomux_set(GPIO0_C4);
- iomux_set(GPIO0_C5);
- return 0;
-}
-
-static int mu509_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mu509_data rk29_mu509_info = {
- .io_init = mu509_io_init,
- .io_deinit = mu509_io_deinit,
- .modem_power_en = RK30_PIN2_PD5,
- .bp_power = RK30_PIN0_PC6,
- .bp_reset = RK30_PIN2_PD4,
- .ap_wakeup_bp = RK30_PIN0_PC4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
-};
-struct platform_device rk29_device_mu509 = {
- .name = "mu509",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mu509_info,
- }
- };
-#endif
-#if defined(CONFIG_MW100)
-static int mw100_io_init(void)
-{
- iomux_set(GPIO2_D5);
- iomux_set(GPIO0_C6);
- iomux_set(GPIO2_D4);
- iomux_set(GPIO0_C4);
- iomux_set(GPIO0_C5);
- return 0;
-}
-
-static int mw100_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mw100_data rk29_mw100_info = {
- .io_init = mw100_io_init,
- .io_deinit = mw100_io_deinit,
- .modem_power_en = RK30_PIN2_PD5,
- .bp_power = RK30_PIN0_PC6,
- .bp_reset = RK30_PIN2_PD4,
- .ap_wakeup_bp = RK30_PIN0_PC4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
-};
-struct platform_device rk29_device_mw100 = {
- .name = "mw100",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mw100_info,
- }
- };
-#endif
-#if defined(CONFIG_MT6229)
-static int mt6229_io_init(void)
-{
- iomux_set(GPIO2_D5);
- iomux_set(GPIO0_C6);
- iomux_set(GPIO2_D4);
- iomux_set(GPIO0_C4);
- iomux_set(GPIO0_C5);
- return 0;
-}
-
-static int mt6229_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mt6229_data rk29_mt6229_info = {
- .io_init = mt6229_io_init,
- .io_deinit = mt6229_io_deinit,
- .modem_power_en = RK30_PIN2_PD5,
- .bp_power = RK30_PIN0_PC6,
- .bp_reset = RK30_PIN2_PD4,
- .ap_wakeup_bp = RK30_PIN0_PC4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
-};
-struct platform_device rk29_device_mt6229 = {
- .name = "mt6229",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mt6229_info,
- }
- };
-#endif
-
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN RK30_PIN0_PB7
-
-static int mma8452_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data mma8452_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma8452_init_platform_hw,
- .orientation = {-1, 0, 0, 0, 1, 0, 0, 0, -1},
-};
-#endif
-#if defined (CONFIG_GS_LIS3DH)
-#define LIS3DH_INT_PIN RK30_PIN0_PB7
-
-static int lis3dh_init_platform_hw(void)
-{
-
- return 0;
-}
-
-static struct sensor_platform_data lis3dh_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lis3dh_init_platform_hw,
- .orientation = {-1, 0, 0, 0, 0, 1, 0, -1, 0},
-};
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
-static struct sensor_platform_data akm8975_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-#if defined(CONFIG_GYRO_L3G4200D)
-
-#include <linux/l3g4200d.h>
-#define L3G4200D_INT_PIN RK30_PIN0_PB4
-
-static int l3g4200d_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data l3g4200d_info = {
- .type = SENSOR_TYPE_GYROSCOPE,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
- .init_platform_hw = l3g4200d_init_platform_hw,
- .x_min = 40,//x_min,y_min,z_min = (0-100) according to hardware
- .y_min = 40,
- .z_min = 20,
-};
-
-#endif
-
-#ifdef CONFIG_LS_CM3217
-static struct sensor_platform_data cm3217_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 0,
- .poll_delay_ms = 500,
-};
-
-#endif
-
-#ifdef CONFIG_FB_ROCKCHIP
-
-#define LCD_CS_PIN INVALID_GPIO
-#define LCD_CS_VALUE GPIO_HIGH
-
-#define LCD_EN_PIN RK30_PIN0_PB6
-#define LCD_EN_VALUE GPIO_HIGH
-
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
-
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_CS_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_CS_PIN);
- printk(KERN_ERR "request lcd cs pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_CS_PIN, LCD_CS_VALUE);
- }
- }
-
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_EN_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_EN_PIN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_EN_PIN, LCD_EN_VALUE);
- }
- }
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, !LCD_CS_VALUE);
- }
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, !LCD_EN_VALUE);
- }
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE);
- }
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
- }
- return 0;
-}
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
-struct rk29fb_info lcdc0_screen_info = {
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
-struct rk29fb_info lcdc1_screen_info = {
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-
-
- #if 0 // defined(CONFIG_RK_HDMI)
- .prop = EXTEND, //extend display device
- .lcd_info = NULL,
- .set_screen_info = hdmi_init_lcdc,
- #endif
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
-static struct resource resource_lcdc0[] = {
- [0] = {
- .name = "lcdc0 reg",
- .start = RK30_LCDC0_PHYS,
- .end = RK30_LCDC0_PHYS + RK30_LCDC0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc0 irq",
- .start = IRQ_LCDC0,
- .end = IRQ_LCDC0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc0 = {
- .name = "rk30-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc0),
- .resource = resource_lcdc0,
- .dev = {
- .platform_data = &lcdc0_screen_info,
- },
-};
-#endif
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
-static struct resource resource_lcdc1[] = {
- [0] = {
- .name = "lcdc1 reg",
- .start = RK30_LCDC1_PHYS,
- .end = RK30_LCDC1_PHYS + RK30_LCDC1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc1 irq",
- .start = IRQ_LCDC1,
- .end = IRQ_LCDC1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc1 = {
- .name = "rk30-lcdc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resource_lcdc1),
- .resource = resource_lcdc1,
- .dev = {
- .platform_data = &lcdc1_screen_info,
- },
-};
-#endif
-
-#if defined(CONFIG_MFD_RK610)
-#define RK610_RST_PIN RK30_PIN2_PD5
-#define RK610_TEST_PIN RK30_PIN2_PD6
-#define RK610_ENABLE_PIN RK30_PIN0_PC5
-static int rk610_power_on_init(void)
-{
- int ret;
- if(RK610_ENABLE_PIN != INVALID_GPIO)
- {
- ret = gpio_request(RK610_ENABLE_PIN, "rk610 reset");
- if (ret)
- {
- printk(KERN_ERR "rk610_control_probe request gpio fail\n");
- }
- else
- {
- gpio_direction_output(RK610_ENABLE_PIN, GPIO_HIGH);
- msleep(100);
- }
- }
- if(RK610_TEST_PIN != INVALID_GPIO)
- {
- ret = gpio_request(RK610_TEST_PIN, "rk610 reset");
- if (ret)
- {
- printk(KERN_ERR "rk610_control_probe request gpio fail\n");
- }
- else
- {
- gpio_direction_output(RK610_TEST_PIN, GPIO_LOW);
- msleep(100);
- }
- }
- if(RK610_RST_PIN != INVALID_GPIO)
- {
- ret = gpio_request(RK610_RST_PIN, "rk610 reset");
- if (ret)
- {
- printk(KERN_ERR "rk610_control_probe request gpio fail\n");
- }
- else
- {
- gpio_direction_output(RK610_RST_PIN, GPIO_HIGH);
- msleep(100);
- gpio_direction_output(RK610_RST_PIN, GPIO_LOW);
- msleep(100);
- gpio_set_value(RK610_RST_PIN, GPIO_HIGH);
- }
- }
-
- return 0;
-
-}
-
-
-static struct rk610_ctl_platform_data rk610_ctl_pdata = {
- .rk610_power_on_init = rk610_power_on_init,
-};
-#endif
-
-#ifdef CONFIG_SND_SOC_RK610
-static int rk610_codec_io_init(void)
-{
-//if need iomux.
-//Must not gpio_request
- return 0;
-}
-
-static struct rk610_codec_platform_data rk610_codec_pdata = {
- .spk_ctl_io = RK30_PIN3_PC7,//RK30_PIN2_PD7,
- .io_init = rk610_codec_io_init,
-};
-#endif
-
-#ifdef CONFIG_ANDROID_TIMED_GPIO
-static struct timed_gpio timed_gpios[] = {
- {
- .name = "vibrator",
- .gpio = INVALID_GPIO,
- .max_timeout = 1000,
- .active_low = 0,
- .adjust_time =20, //adjust for diff product
- },
-};
-
-static struct timed_gpio_platform_data rk29_vibrator_info = {
- .num_gpios = 1,
- .gpios = timed_gpios,
-};
-
-static struct platform_device rk29_device_vibrator = {
- .name = "timed-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_vibrator_info,
- },
-
-};
-#endif
-
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
-static struct gpio_led rk29_leds[] = {
- {
- .name = "button-backlight",
- .gpio = INVALID_GPIO,
- .default_trigger = "timer",
- .active_low = 0,
- .retain_state_suspended = 0,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- },
-};
-
-static struct gpio_led_platform_data rk29_leds_pdata = {
- .leds = rk29_leds,
- .num_leds = ARRAY_SIZE(rk29_leds),
-};
-
-static struct platform_device rk29_device_gpio_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_leds_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_RK_IRDA
-#define IRDA_IRQ_PIN INVALID_GPIO //RK30_PIN0_PA3
-
-static int irda_iomux_init(void)
-{
- int ret = 0;
-
- //irda irq pin
- ret = gpio_request(IRDA_IRQ_PIN, NULL);
- if (ret != 0) {
- gpio_free(IRDA_IRQ_PIN);
- printk(">>>>>> IRDA_IRQ_PIN gpio_request err \n ");
- }
- gpio_pull_updown(IRDA_IRQ_PIN, PullDisable);
- gpio_direction_input(IRDA_IRQ_PIN);
-
- return 0;
-}
-
-static int irda_iomux_deinit(void)
-{
- gpio_free(IRDA_IRQ_PIN);
- return 0;
-}
-
-static struct irda_info rk29_irda_info = {
- .intr_pin = IRDA_IRQ_PIN,
- .iomux_init = irda_iomux_init,
- .iomux_deinit = irda_iomux_deinit,
- //.irda_pwr_ctl = bu92747guw_power_ctl,
-};
-
-static struct platform_device irda_device = {
-#ifdef CONFIG_RK_IRDA_NET
- .name = "rk_irda",
-#else
- .name = "bu92747_irda",
-#endif
- .id = -1,
- .dev = {
- .platform_data = &rk29_irda_info,
- }
-};
-#endif
-
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and sdio.noted by xbw at 2012-03-05
-**************************************************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "board-rk3028-tb-sdmmc-conifg.c"
-#include "../plat-rk/rk-sdmmc-ops.c"
-#include "../plat-rk/rk-sdmmc-wifi.c"
-#endif //endif ---#ifdef CONFIG_SDMMC_RK29
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- iomux_set(MMC0_CMD);
- iomux_set(MMC0_CLKOUT);
- iomux_set(MMC0_D0);
- iomux_set(MMC0_D1);
- iomux_set(MMC0_D2);
- iomux_set(MMC0_D3);
-
- iomux_set_gpio_mode(iomux_mode_to_gpio(MMC0_DETN));
-
- gpio_request(RK30_PIN3_PA7, "sdmmc-power");
- gpio_direction_output(RK30_PIN3_PA7, GPIO_LOW);
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- #if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set_gpio_mode(iomux_gpio_to_mode(RK29SDK_SD_CARD_DETECT_N));
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO);
- #endif
- #else
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(MMC0_DETN);
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FMUX);
- #endif
- #endif
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) && defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- .status = rk29sdk_wifi_mmc0_status,
- .register_status_notify = rk29sdk_wifi_mmc0_status_register,
-#endif
-
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .power_en = RK29SDK_SD_CARD_PWR_EN,
- .power_en_level = RK29SDK_SD_CARD_PWR_EN_LEVEL,
-#else
- .power_en = INVALID_GPIO,
- .power_en_level = GPIO_LOW,
-#endif
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC0_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- .det_pin_info = {
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N, //INVALID_GPIO,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
- #endif
- },
-
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- iomux_set(MMC1_CMD);
- iomux_set(MMC1_CLKOUT);
- iomux_set(MMC1_D0);
- iomux_set(MMC1_D1);
- iomux_set(MMC1_D2);
- iomux_set(MMC1_D3);
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC) || defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC1_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- #if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
- .sdio_INT_gpio = RK29SDK_WIFI_SDIO_CARD_INT,
- #endif
-
- .det_pin_info = {
-#if defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- #else
- .io = INVALID_GPIO,
- #endif
-
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-
- .enable_sd_wakeup = 0,
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-/**************************************************************************************************
- * the end of setting for SDMMC devices
-**************************************************************************************************/
-
-#ifdef CONFIG_BATTERY_RK30_ADC
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = RK30_PIN0_PB2,
- .batt_low_pin = RK30_PIN0_PB1,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = RK30_PIN0_PA6,
- .dc_det_level = GPIO_LOW,
- .charge_ok_level = GPIO_HIGH,
-};
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-#ifdef CONFIG_RK30_PWM_REGULATOR
-static int pwm_voltage_map[] = {
- /*
- 800000,825000,850000, 875000,900000, 925000 ,950000, 975000,1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000,1375000*/
- 950000,975000,1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000, 1375000, 1400000
-};
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_core",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] =
-{
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
- #if defined (CONFIG_MACH_RK3028_TB)
- .pwm_id = 2,
- .pwm_gpio = RK30_PIN3_PD5,
- .pwm_iomux_pwm = PWM2,
- .pwm_iomux_gpio = GPIO3_D5,
- #else
- .pwm_id = 1,
- .pwm_gpio = RK30_PIN3_PD4,
- .pwm_iomux_pwm = PWM1,
- .pwm_iomux_gpio = GPIO3_D4,
-
- #endif
- .pwm_voltage = 1100000,
- .suspend_voltage = 1000000,
- .min_uV = 950000,
- .max_uV = 1400000,
- .coefficient = 504, //57.5%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-#endif
-
-#ifdef CONFIG_RK29_VMAC
-#define PHY_PWR_EN_GPIO RK30_PIN1_PD6
-#include "board-rk30-sdk-vmac.c"
-#endif
-
-#ifdef CONFIG_RFKILL_RK
-// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
-static struct rfkill_rk_platform_data rfkill_rk_platdata = {
- .type = RFKILL_TYPE_BLUETOOTH,
-
- .poweron_gpio = { // BT_REG_ON
- .io = INVALID_GPIO, //RK30_PIN3_PC7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_poweron",
- .fgpio = GPIO3_C7,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN3_PC7, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_reset",
- .fgpio = GPIO3_C7,
- },
- },
-
- .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
- .io = RK30_PIN3_PC6, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_wake",
- .fgpio = GPIO3_C6,
- },
- },
-
- .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .gpio = {
- .io = RK30_PIN0_PA5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
- .iomux = {
- .name = NULL,
- },
- },
- },
-
- .rts_gpio = { // UART_RTS, enable or disable BT's data coming
- .io = RK30_PIN1_PA3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_rts",
- .fgpio = GPIO1_A3,
- .fmux = UART0_RTSN,
- },
- },
-};
-
-static struct platform_device device_rfkill_rk = {
- .name = "rfkill_rk",
- .id = -1,
- .dev = {
- .platform_data = &rfkill_rk_platdata,
- },
-};
-#endif
-
-#if defined(CONFIG_GPS_RK)
-int rk_gps_io_init(void)
-{
- printk("%s \n", __FUNCTION__);
-
- gpio_request(RK30_PIN1_PB5, NULL);
- gpio_direction_output(RK30_PIN1_PB5, GPIO_LOW);
-
- iomux_set(GPS_RFCLK);//GPS_CLK
- iomux_set(GPS_MAG);//GPS_MAG
- iomux_set(GPS_SIG);//GPS_SIGN
-
- gpio_request(RK30_PIN1_PA6, NULL);
- gpio_direction_output(RK30_PIN1_PA6, GPIO_LOW);
-
- gpio_request(RK30_PIN1_PA5, NULL);
- gpio_direction_output(RK30_PIN1_PA5, GPIO_LOW);
-
- gpio_request(RK30_PIN1_PA7, NULL);
- gpio_direction_output(RK30_PIN1_PA7, GPIO_LOW);
- return 0;
-}
-int rk_gps_power_up(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_power_down(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_reset_set(int level)
-{
- return 0;
-}
-int rk_enable_hclk_gps(void)
-{
- struct clk *gps_aclk = NULL;
- gps_aclk = clk_get(NULL, "aclk_gps");
- if(gps_aclk) {
- clk_enable(gps_aclk);
- clk_put(gps_aclk);
- printk("%s \n", __FUNCTION__);
- }
- else
- printk("get gps aclk fail\n");
- return 0;
-}
-int rk_disable_hclk_gps(void)
-{
- struct clk *gps_aclk = NULL;
- gps_aclk = clk_get(NULL, "aclk_gps");
- if(gps_aclk) {
- //TO wait long enough until GPS ISR is finished.
- msleep(5);
- clk_disable(gps_aclk);
- clk_put(gps_aclk);
- printk("%s \n", __FUNCTION__);
- }
- else
- printk("get gps aclk fail\n");
- return 0;
-}
-struct rk_gps_data rk_gps_info = {
- .io_init = rk_gps_io_init,
- .power_up = rk_gps_power_up,
- .power_down = rk_gps_power_down,
- .reset = rk_gps_reset_set,
- .enable_hclk_gps = rk_enable_hclk_gps,
- .disable_hclk_gps = rk_disable_hclk_gps,
- .GpsSign = RK30_PIN1_PB3,
- .GpsMag = RK30_PIN1_PB2, //GPIO index
- .GpsClk = RK30_PIN1_PB4, //GPIO index
- .GpsVCCEn = RK30_PIN1_PB5, //GPIO index
- .GpsSpi_CSO = RK30_PIN1_PA4, //GPIO index
- .GpsSpiClk = RK30_PIN1_PA5, //GPIO index
- .GpsSpiMOSI = RK30_PIN1_PA7, //GPIO index
- .GpsIrq = IRQ_GPS,
- .GpsSpiEn = 0,
- .GpsAdcCh = 2,
- .u32GpsPhyAddr = RK30_GPS_PHYS,
- .u32GpsPhySize = RK30_GPS_SIZE,
-};
-
-struct platform_device rk_device_gps = {
- .name = "gps_hv5820b",
- .id = -1,
- .dev = {
- .platform_data = &rk_gps_info,
- }
- };
-#endif
-
-#if defined(CONFIG_MT5931_MT6622)
-static struct mt6622_platform_data mt6622_platdata = {
- .power_gpio = { // BT_REG_ON
- .io = RK30_PIN3_PD5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN0_PD7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .irq_gpio = {
- .io = RK30_PIN3_PD2,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- }
-};
-
-static struct platform_device device_mt6622 = {
- .name = "mt6622",
- .id = -1,
- .dev = {
- .platform_data = &mt6622_platdata,
- },
-};
-#endif
-
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_ANDROID_TIMED_GPIO
- &rk29_device_vibrator,
-#endif
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
- &rk29_device_gpio_leds,
-#endif
-#ifdef CONFIG_RK_IRDA
- &irda_device,
-#endif
-#if defined(CONFIG_WIFI_CONTROL_FUNC)||defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- &rk29sdk_wifi_device,
-#endif
-
-#if defined(CONFIG_MT6620)
- &mt3326_device_gps,
-#endif
-
-#ifdef CONFIG_RK29_SUPPORT_MODEM
- &rk30_device_modem,
-#endif
-#if defined(CONFIG_MU509)
- &rk29_device_mu509,
-#endif
-#if defined(CONFIG_MW100)
- &rk29_device_mw100,
-#endif
-#if defined(CONFIG_MT6229)
- &rk29_device_mt6229,
-#endif
-#ifdef CONFIG_BATTERY_RK30_ADC
- &rk30_device_adc_battery,
-#endif
-#ifdef CONFIG_RFKILL_RK
- &device_rfkill_rk,
-#endif
-#ifdef CONFIG_GPS_RK
- &rk_device_gps,
-#endif
-
-#ifdef CONFIG_MT5931_MT6622
- &device_mt6622,
-#endif
-};
-
-static int rk_platform_add_display_devices(void)
-{
- struct platform_device *fb = NULL; //fb
- struct platform_device *lcdc0 = NULL; //lcdc0
- struct platform_device *lcdc1 = NULL; //lcdc1
- struct platform_device *bl = NULL; //backlight
-#ifdef CONFIG_FB_ROCKCHIP
- fb = &device_fb;
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
- lcdc0 = &device_lcdc0,
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
- lcdc1 = &device_lcdc1,
-#endif
-
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- bl = &rk29_device_backlight,
-#endif
- __rk_platform_add_display_devices(fb,lcdc0,lcdc1,bl);
-
- return 0;
-
-}
-
-// i2c
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1d,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_GS_LIS3DH)
- {
- .type = "gs_lis3dh",
- .addr = 0x19, //0x19(SA0-->VCC), 0x18(SA0-->GND)
- .flags = 0,
- .irq = LIS3DH_INT_PIN,
- .platform_data = &lis3dh_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8975_info,
- },
-#endif
-#if defined (CONFIG_GYRO_L3G4200D)
- {
- .type = "l3g4200d_gryo",
- .addr = 0x69,
- .flags = 0,
- .irq = L3G4200D_INT_PIN,
- .platform_data = &l3g4200d_info,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RT5631)
- {
- .type = "rt5631",
- .addr = 0x1a,
- .flags = 0,
- },
-#endif
-
-
-};
-#endif
-
-int __sramdata g_pmic_type = 0;
-#ifdef CONFIG_I2C1_RK30
-#ifdef CONFIG_MFD_WM831X_I2C
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info wm8326_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "dcdc3", //ddr
- .min_uv = 1150000,
- .max_uv = 1150000,
- .suspend_vol = 1150000,
- },
- #ifdef CONFIG_MACH_RK3066_SDK
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3000000,
- },
- #else
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3000000,
- .max_uv = 3000000,
- .suspend_vol = 2800000,
- },
- #endif
-};
-
-static struct pmu_info wm8326_ldo_info[] = {
- {
- .name = "ldo1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo2", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo3", //
- .min_uv = 1100000,
- .max_uv = 1100000,
- .suspend_vol = 1100000,
- },
- {
- .name = "ldo4", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 1000000,
- },
- {
- .name = "ldo5", //vcc25
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo6", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo7", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- .suspend_vol = 2800000,
- },
- {
- .name = "ldo8", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo9", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo10", //flash_io
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
-};
-
-#include "../mach-rk30/board-pmu-wm8326.c"
-#endif
-
-#ifdef CONFIG_MFD_TPS65910
-#define TPS65910_HOST_IRQ RK30_PIN0_PB5//RK30_PIN0_PB3
-
-#define PMU_POWER_SLEEP RK30_PIN1_PB5
-
-static struct pmu_info tps65910_dcdc_info[] = {
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1100000,
- .max_uv = 1100000,
- },
- {
- .name = "vdd2", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vio", //vcc_io
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
-
-};
-static struct pmu_info tps65910_ldo_info[] = {
- {
- .name = "vpll", //vdd10
- .min_uv = 2500000,
- .max_uv = 2500000,
- },
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "vdig2", //vdd_jetta
- .min_uv = 1100000,
- .max_uv = 1100000,
- },
- {
- .name = "vaux1", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "vaux2", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vaux33", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vmmc", //vcc30
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
- {
- .name = "vdac", //vcc18
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- };
-
-#include "../mach-rk30/board-pmu-tps65910.c"
-#endif
-
-#ifdef CONFIG_REGULATOR_ACT8846
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-#define PMU_VSEL RK30_PIN3_PD3
-static struct pmu_info act8846_dcdc_info[] = {
- {
- .name = "act_dcdc1", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- .suspend_vol = 1200000,
- },
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 1200000,
- #else
- .suspend_vol = 900000,
- #endif
-
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 1200000,
- #else
- .suspend_vol = 900000,
- #endif
-
- },
- {
- .name = "act_dcdc4", //vccio
- .min_uv = 3000000,
- .max_uv = 3000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 3000000,
- #else
- .suspend_vol = 2800000,
- #endif
-
- },
-
-};
-static struct pmu_info act8846_ldo_info[] = {
- {
- .name = "act_ldo1", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "act_ldo2", //vdd12
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "act_ldo3", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo4", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo5", //vcctp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo6", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo7", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo8", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- };
-
-#include "../mach-rk30/board-pmu-act8846.c"
-#endif
-
-
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_MFD_WM831X_I2C)
- {
- .type = "wm8326",
- .addr = 0x34,
- .flags = 0,
- .irq = RK30_PIN0_PB3,
- .platform_data = &wm831x_platdata,
- },
-#endif
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-
-#if defined (CONFIG_REGULATOR_ACT8846)
- {
- .type = "act8846",
- .addr = 0x5a,
- .flags = 0,
- // .irq = ACT8846_HOST_IRQ,
- .platform_data=&act8846_data,
- },
-#endif
-#if defined (CONFIG_RTC_HYM8563)
- {
- .type = "rtc_hym8563",
- .addr = 0x51,
- .flags = 0,
- .irq = RK30_PIN1_PA4,
- },
-#endif
-
-};
-#endif
-
-void __sramfunc board_pmu_suspend(void)
-{
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_suspend();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_suspend();
- #endif
- #if defined (CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- board_pmu_act8846_suspend();
- #endif
-
-}
-
-void __sramfunc board_pmu_resume(void)
-{
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_resume();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_resume();
- #endif
- #if defined (CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- board_pmu_act8846_resume();
- #endif
-}
-
- int __sramdata gpio3d6_iomux,gpio3d6_do,gpio3d6_dir,gpio3d6_en;
-
-#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
-
-void __sramfunc rk30_pwm_logic_suspend_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
-
-// int gpio0d7_iomux,gpio0d7_do,gpio0d7_dir,gpio0d7_en;
- sram_udelay(10000);
- gpio3d6_iomux = grf_readl(GRF_GPIO3D_IOMUX);
- gpio3d6_do = grf_readl(GRF_GPIO3H_DO);
- gpio3d6_dir = grf_readl(GRF_GPIO3H_DIR);
- gpio3d6_en = grf_readl(GRF_GPIO3H_EN);
-
- grf_writel((1<<28), GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DIR);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DO);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_EN);
-#endif
-}
-void __sramfunc rk30_pwm_logic_resume_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- grf_writel((1<<28)|gpio3d6_iomux, GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|gpio3d6_en, GRF_GPIO3H_EN);
- grf_writel((1<<30)|gpio3d6_dir, GRF_GPIO3H_DIR);
- grf_writel((1<<30)|gpio3d6_do, GRF_GPIO3H_DO);
- sram_udelay(10000);
-
-#endif
-
-}
-extern void pwm_suspend_voltage(void);
-extern void pwm_resume_voltage(void);
-void rk30_pwm_suspend_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_suspend_voltage();
-#endif
-}
-void rk30_pwm_resume_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_resume_voltage();
-#endif
-}
-
-
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-#if defined (CONFIG_TOUCHSCREEN_GT8XX)
- {
- .type = "Goodix-TS",
- .addr = 0x55,
- .flags = 0,
- .irq = RK30_PIN0_PB4,
- .platform_data = &goodix_info,
- },
-#endif
-#if defined (CONFIG_LS_CM3217)
- {
- .type = "lightsensor",
- .addr = 0x10,
- .flags = 0,
- .platform_data = &cm3217_info,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C4_RK30
-static struct i2c_board_info __initdata i2c4_info[] = {
-#ifdef CONFIG_MFD_RK610
- {
- .type = "rk610_ctl",
- .addr = 0x40,
- .flags = 0,
- .platform_data = &rk610_ctl_pdata,
- },
-#ifdef CONFIG_RK610_TVOUT
- {
- .type = "rk610_tvout",
- .addr = 0x42,
- .flags = 0,
- },
-#endif
-#ifdef CONFIG_HDMI_RK610
- {
- .type = "rk610_hdmi",
- .addr = 0x46,
- .flags = 0,
- .irq = INVALID_GPIO,
- },
-#endif
-#ifdef CONFIG_SND_SOC_RK610
- {//RK610_CODEC addr from 0x60 to 0x80 (0x60~0x80)
- .type = "rk610_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- .platform_data = &rk610_codec_pdata,
- },
-#endif
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO// RK30_PIN2_PD6 //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO//RK30_PIN2_PD7 //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- //set iomux (gpio) here
- //rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME, GPIO2D_GPIO2D7);
- //rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME, GPIO2D_GPIO2D6);
-
- return 0;
-}
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C4_RK30
- i2c_register_board_info(4, i2c4_info, ARRAY_SIZE(i2c4_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(5, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-
-// ========== Begin of rk3168 top board keypad defination ============
-
-#include <plat/key.h>
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .gpio = RK30_PIN0_PD6,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK30_PIN1_PB4,
- .active_low = PRESS_LEV_LOW,
- .wakeup = 1,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .adc_value = 1,//133
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "menu",
- .code = EV_MENU,
- .adc_value = 135,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .adc_value = 550,//550
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .adc_value = 334,//333
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "camera",
- .code = KEY_CAMERA,
- .adc_value = 700,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = 1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
-// =========== End of rk3168 top board keypad defination =============
-
-
-#define POWER_ON_PIN RK30_PIN0_PD5 //power_hold
-static void rk30_pm_power_off(void)
-{
- printk(KERN_ERR "rk30_pm_power_off start...\n");
- #if defined(CONFIG_MFD_WM831X)
- if(pmic_is_wm8326()){
- wm831x_set_bits(Wm831x,WM831X_GPIO_LEVEL,0x0001,0x0000); //set sys_pwr 0
- wm831x_device_shutdown(Wm831x);//wm8326 shutdown
- }
- #endif
-
- #if defined(CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- {
- act8846_device_shutdown();
- }
- #endif
-
- #if defined(CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- {
- tps65910_device_shutdown();//tps65910 shutdown
- }
- #endif
-
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
- while (1);
-}
-
-static void __init machine_rk30_board_init(void)
-{
- //avs_init();
- gpio_request(POWER_ON_PIN, "poweronpin");
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
- pm_power_off = rk30_pm_power_off;
-
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
-
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- rk_platform_add_display_devices();
- board_usb_detect_init(RK30_PIN0_PA7);
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC)
- rk29sdk_wifi_bt_gpio_control_init();
-#elif defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- rk29sdk_wifi_combo_module_gpio_init();
-#endif
-
-#if defined(CONFIG_MT6620)
- clk_set_rate(clk_get_sys("rk_serial.0", "uart"), 48*1000000);
-#endif
-
-#if defined(CONFIG_MT5931_MT6622)
- clk_set_rate(clk_get_sys("rk_serial.0", "uart"), 24*1000000);
-#endif
-}
-
-static void __init rk30_reserve(void)
-{
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0 buf", get_fb_size());
- resource_fb[0].end = resource_fb[0].start + get_fb_size()- 1;
-#if 0
- resource_fb[1].start = board_mem_reserve_add("ipp buf", RK30_FB0_MEM_SIZE);
- resource_fb[1].end = resource_fb[1].start + RK30_FB0_MEM_SIZE - 1;
-#endif
-
-#if defined(CONFIG_FB_ROTATE) || !defined(CONFIG_THREE_FB_BUFFER)
- resource_fb[2].start = board_mem_reserve_add("fb2 buf",get_fb_size());
- resource_fb[2].end = resource_fb[2].start + get_fb_size() - 1;
-#endif
-#endif
-
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
-
-#ifdef CONFIG_GPS_RK
- //it must be more than 8MB
- rk_gps_info.u32MemoryPhyAddr = board_mem_reserve_add("gps", SZ_8M);
-#endif
- board_mem_reserved();
-}
-
-/**
- * dvfs_cpu_logic_table: table for arm and logic dvfs
- * @frequency : arm frequency
- * @cpu_volt : arm voltage depend on frequency
- */
-static struct cpufreq_frequency_table dvfs_arm_table[] = {
- {.frequency = 312 * 1000, .index = 900 * 1000},
- {.frequency = 504 * 1000, .index = 950 * 1000},
- {.frequency = 816 * 1000, .index = 1000 * 1000},
- {.frequency = 1008 * 1000, .index = 1100 * 1000},
- //{.frequency = 1200 * 1000, .index = 1100 * 1000},
- //{.frequency = 1416 * 1000, .index = 1200 * 1000},
- //{.frequency = 1608 * 1000, .index = 1300 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
-#if defined(CONFIG_ARCH_RK3188)
- {.frequency = 133 * 1000, .index = 975 * 1000},//the mininum rate is limited 133M for rk3188
-#elif defined(CONFIG_ARCH_RK3066B)
- {.frequency = 100 * 1000, .index = 950 * 1000},//the minimum rate is no limit for rk3168 rk3066B
-#endif
-
- {.frequency = 200 * 1000, .index = 975 * 1000},
- {.frequency = 266 * 1000, .index = 1000 * 1000},
- {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1100 * 1000},
- //{.frequency = 600 * 1000, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
-#if defined(CONFIG_ARCH_RK3188)
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 950 * 1000},
- {.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = 1000 * 1000},
-#endif
- {.frequency = 396 * 1000 + DDR_FREQ_NORMAL, .index = 1100 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-//#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
-//static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
-//static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
-int get_max_freq(struct cpufreq_frequency_table *table)
-{
- int i,temp=0;
-
- for(i=0;table[i].frequency!= CPUFREQ_TABLE_END;i++)
- {
- if(temp<table[i].frequency)
- temp=table[i].frequency;
- }
- printk("get_max_freq=%d\n",temp);
- return temp;
-}
-
-void __init board_clock_init(void)
-{
-
- u32 flags=RK30_CLOCKS_DEFAULT_FLAGS;
-#if !defined(CONFIG_ARCH_RK3188)
- if(get_max_freq(dvfs_gpu_table)<=(400*1000))
- {
- flags=RK30_CLOCKS_DEFAULT_FLAGS|CLK_GPU_GPLL;
- }
- else
- flags=RK30_CLOCKS_DEFAULT_FLAGS|CLK_GPU_CPLL;
-#endif
- rk30_clock_data_init(periph_pll_default, codec_pll_default, flags);
- //dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "cpu"), dvfs_arm_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
-}
-
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk30_fixup,
- .reserve = &rk30_reserve,
- .map_io = rk30_map_io,
- .init_irq = rk30_init_irq,
- .timer = &rk30_timer,
- .init_machine = machine_rk30_board_init,
-MACHINE_END
+++ /dev/null
-/*
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <linux/fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-
-
-#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Macro Define Begin ------------------------*/
-/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
-#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_OV5642 /* back camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_0 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 4
-#define CONFIG_SENSOR_ORIENTATION_0 90
-#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000
-
-#define CONFIG_SENSOR_01 RK29_CAM_SENSOR_OV5642 /* back camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_01 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 4
-#define CONFIG_SENSOR_ORIENTATION_01 90
-#define CONFIG_SENSOR_POWER_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_01 30000
-
-#define CONFIG_SENSOR_02 RK29_CAM_SENSOR_OV5640 /* back camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_02 0x00
-#define CONFIG_SENSOR_CIF_INDEX_02 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 4
-#define CONFIG_SENSOR_ORIENTATION_02 90
-#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000
-
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_OV2659 /* front camera sensor 0 */
-#define CONFIG_SENSOR_IIC_ADDR_1 0x60
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 1
-#define CONFIG_SENSOR_ORIENTATION_1 270
-#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000
-
-#define CONFIG_SENSOR_11 RK29_CAM_SENSOR_OV2659 /* front camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_11 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 3
-#define CONFIG_SENSOR_ORIENTATION_11 270
-#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_11 30000
-
-#define CONFIG_SENSOR_12 RK29_CAM_SENSOR_OV2659//RK29_CAM_SENSOR_OV2655 /* front camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_12 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 3
-#define CONFIG_SENSOR_ORIENTATION_12 270
-#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_12 30000
-
-
-#endif //#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk30_camera.c"
-/*---------------- Camera Sensor Macro Define End ---------*/
-
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#define CONFIG_SENSOR_POWER_IOCTL_USR 0 //define this refer to your board layout
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
-
-static void rk_cif_power(int on)
-{
- struct regulator *ldo_18,*ldo_28;
-
- ldo_28 = regulator_get(NULL, "ldo7"); // vcc28_cif
- ldo_18 = regulator_get(NULL, "ldo1"); // vcc18_cif
- if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)) {
- printk("get cif ldo failed!\n");
- return;
- }
- if(on == 0) {
- regulator_disable(ldo_28);
- regulator_put(ldo_28);
- regulator_disable(ldo_18);
- regulator_put(ldo_18);
- mdelay(500);
- } else {
- regulator_set_voltage(ldo_28, 2800000, 2800000);
- regulator_enable(ldo_28);
- // printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
- regulator_put(ldo_28);
-
- regulator_set_voltage(ldo_18, 1800000, 1800000);
- // regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(ldo_18);
- // printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
- regulator_put(ldo_18);
- }
-}
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- //#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
- rk_cif_power(on);
-}
-#endif
-
-#if CONFIG_SENSOR_RESET_IOCTL_USR
-static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
-static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-
-#if CONFIG_SENSOR_IIC_ADDR_0
-static struct reginfo_t rk_init_data_sensor_reg_0[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_0[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-
-#if CONFIG_SENSOR_IIC_ADDR_1
-static struct reginfo_t rk_init_data_sensor_reg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_01
-static struct reginfo_t rk_init_data_sensor_reg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_02
-static struct reginfo_t rk_init_data_sensor_reg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_11
-static struct reginfo_t rk_init_data_sensor_reg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_12
-static struct reginfo_t rk_init_data_sensor_reg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] =
-{
- #if CONFIG_SENSOR_IIC_ADDR_0
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_0,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_1
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_1,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_01
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_01,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_02
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_02,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_11
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_11,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_12
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_12,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
-
- };
-#include "../../../drivers/media/video/rk30_camera.c"
-
-#endif /* CONFIG_VIDEO_RK29 */
-
-
-
-#define RK_FB_MEM_SIZE 3*SZ_1M
-
-#if defined(CONFIG_FB_ROCKCHIP)
-#define LCD_CS_MUX_NAME GPIO2A7_LCDC1DATA7_SMCDATA7_TRACEDATA7_NAME
-#define LCD_CS_PIN RK30_PIN2_PA7
-#define LCD_CS_VALUE GPIO_HIGH
-
-#define LCD_EN_MUX_NAME GPIO2D7_TESTCLOCKOUT_NAME
-#define LCD_EN_PIN RK30_PIN2_PD7
-#define LCD_EN_VALUE GPIO_LOW
-
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
- rk30_mux_api_set(LCD_CS_MUX_NAME, GPIO2A_GPIO2A7);
- ret = gpio_request(LCD_CS_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_CS_PIN);
- printk(KERN_ERR "request lcd cs pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_CS_PIN, LCD_CS_VALUE);
- }
- ret = gpio_request(LCD_EN_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_EN_PIN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_EN_PIN, LCD_EN_VALUE);
- }
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
- gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE? 0:1);
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE? 0:1);
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE);
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
- return 0;
-}
-
-#if defined(CONFIG_LCDC0_RK31)
-struct rk29fb_info lcdc0_screen_info = {
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK31)
-struct rk29fb_info lcdc1_screen_info = {
- #if defined(CONFIG_HDMI_RK30)
- .prop = EXTEND, //extend display device
- .lcd_info = NULL,
- .set_screen_info = hdmi_init_lcdc,
- #endif
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-
-//i2c
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-};
-#endif
-#ifdef CONFIG_I2C1_RK30
-static struct i2c_board_info __initdata i2c1_info[] = {
-};
-#endif
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-};
-#endif
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(4, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-#define PWM_ID 1
-#define PWM_MUX_NAME GPIO0A3_PWM0_NAME
-#define PWM_MUX_MODE GPIO0A_PWM0
-#define PWM_MUX_MODE_GPIO GPIO0A_GPIO0A3
-#define PWM_GPIO RK30_PIN0_PA3
-#define PWM_EFFECT_VALUE 1
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-
-#define BL_EN_PIN RK30_PIN6_PB3
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0;
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret = 0;
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-#endif
-
-/***********************************************************
-* rk30 ion device
-************************************************************/
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (8 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-static struct platform_device *devices[] __initdata = {
-#if defined(CONFIG_FB_ROCKCHIP)
- &device_fb,
-#endif
-
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- &rk29_device_backlight,
-#endif
-
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-
-};
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and sdio.noted by xbw at 2012-03-05
-**************************************************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "board-rk3066b-sdk-sdmmc.c"
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
-#define SDMMC0_WRITE_PROTECT_PIN RK30_PIN3_PB7 //According to your own project to set the value of write-protect-pin.
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
-#define SDMMC1_WRITE_PROTECT_PIN RK30_PIN3_PC7 //According to your own project to set the value of write-protect-pin.
-#endif
-
-#define RK29SDK_WIFI_SDIO_CARD_DETECT_N RK30_PIN6_PB2
-
-#endif //endif ---#ifdef CONFIG_SDMMC_RK29
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- rk30_mux_api_set(GPIO3A3_SDMMC0CMD_NAME, GPIO3A_SDMMC0CMD);
- rk30_mux_api_set(GPIO3A2_SDMMC0CLKOUT_NAME, GPIO3A_SDMMC0CLKOUT);
- rk30_mux_api_set(GPIO3A4_SDMMC0DATA0_NAME, GPIO3A_SDMMC0DATA0);
- rk30_mux_api_set(GPIO3A5_SDMMC0DATA1_NAME, GPIO3A_SDMMC0DATA1);
- rk30_mux_api_set(GPIO3A6_SDMMC0DATA2_NAME, GPIO3A_SDMMC0DATA2);
- rk30_mux_api_set(GPIO3A7_SDMMC0DATA3_NAME, GPIO3A_SDMMC0DATA3);
-
- rk30_mux_api_set(GPIO3B0_SDMMC0DETECTN_NAME, GPIO3B_GPIO3B0);
-
- rk30_mux_api_set(GPIO3A1_SDMMC0PWREN_NAME, GPIO3A_GPIO3A1);
- gpio_request(RK30_PIN3_PA1, "sdmmc-power");
- gpio_direction_output(RK30_PIN3_PA1, GPIO_LOW);
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- rk30_mux_api_set(GPIO3B0_SDMMC0DETECTN_NAME, GPIO3B_SDMMC0DETECTN);
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
- .detect_irq = RK30_PIN3_PB6, // INVALID_GPIO
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
-#else
- .write_prt = INVALID_GPIO,
-#endif
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- rk30_mux_api_set(GPIO3C0_SMMC1CMD_NAME, GPIO3C_SMMC1_CMD);
- rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_NAME, GPIO3C_SDMMC1_CLKOUT);
- rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_NAME, GPIO3C_SDMMC1_DATA0);
- rk30_mux_api_set(GPIO3C2_SDMMC1DATA1_NAME, GPIO3C_SDMMC1_DATA1);
- rk30_mux_api_set(GPIO3C3_SDMMC1DATA2_NAME, GPIO3C_SDMMC1_DATA2);
- rk30_mux_api_set(GPIO3C4_SDMMC1DATA3_NAME, GPIO3C_SDMMC1_DATA3);
- //rk30_mux_api_set(GPIO3C6_SDMMC1DETECTN_NAME, GPIO3C_SDMMC1_DETECT_N);
-
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-#if 0
- .detect_irq = RK29SDK_WIFI_SDIO_CARD_DETECT_N,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
-#else
- .detect_irq = INVALID_GPIO,
- .enable_sd_wakeup = 0,
-#endif
-
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-/**************************************************************************************************
- * the end of setting for SDMMC devices
-**************************************************************************************************/
-
-static void __init rk31_board_init(void)
-{
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
-}
-
-static void __init rk31_reserve(void)
-{
-#if defined(CONFIG_FB_ROCKCHIP)
- resource_fb[0].start = board_mem_reserve_add("fb0", RK_FB_MEM_SIZE);
- resource_fb[0].end = resource_fb[0].start + RK_FB_MEM_SIZE - 1;
-#endif
-
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
- board_mem_reserved();
-}
-
-#include <linux/clkdev.h>
-
-struct clk {
- const char *name;
- unsigned long rate;
-};
-
-static struct clk xin24m = {
- .name = "xin24m",
- .rate = 24000000,
-};
-
-static struct clk xin12m = {
- .name = "xin12m",
- .rate = 12000000,
-};
-
-#define CLK(dev, con, ck) \
- { \
- .dev_id = dev, \
- .con_id = con, \
- .clk = ck, \
- }
-
-static struct clk_lookup clks[] = {
- CLK("rk30_i2c.0", "i2c", &xin24m),
- CLK("rk30_i2c.1", "i2c", &xin24m),
- CLK("rk30_i2c.2", "i2c", &xin24m),
- CLK("rk30_i2c.3", "i2c", &xin24m),
- CLK("rk30_i2c.4", "i2c", &xin24m),
- CLK("rk29xx_spim.0", "spi", &xin24m),
- CLK("rk29xx_spim.1", "spi", &xin24m),
-
- CLK("rk_serial.0", "uart_div", &xin24m),
- CLK("rk_serial.0", "uart_frac_div", &xin24m),
- CLK("rk_serial.0", "uart", &xin24m),
- CLK("rk_serial.0", "pclk_uart", &xin24m),
- CLK("rk_serial.1", "uart_div", &xin24m),
- CLK("rk_serial.1", "uart_frac_div", &xin24m),
- CLK("rk_serial.1", "uart", &xin24m),
- CLK("rk_serial.1", "pclk_uart", &xin24m),
- CLK("rk_serial.2", "uart_div", &xin24m),
- CLK("rk_serial.2", "uart_frac_div", &xin24m),
- CLK("rk_serial.2", "uart", &xin24m),
- CLK("rk_serial.2", "pclk_uart", &xin24m),
-
- CLK("rk29_i2s.1", "i2s_div", &xin24m),
- CLK("rk29_i2s.1", "i2s_frac_div", &xin24m),
- CLK("rk29_i2s.1", "i2s", &xin12m),
- CLK("rk29_i2s.1", "hclk_i2s", &xin24m),
-
- CLK("rk29_sdmmc.0","mmc",&xin24m),
- CLK("rk29_sdmmc.0","hclk_mmc",&xin24m),
- CLK("rk29_sdmmc.1","mmc",&xin24m),
- CLK("rk29_sdmmc.1","hclk_mmc",&xin24m),
-
- CLK(NULL,"pd_lcdc0",&xin24m),
- CLK(NULL,"hclk_lcdc0",&xin24m),
- CLK(NULL,"aclk_lcdc0",&xin24m),
- CLK(NULL,"dclk_lcdc0",&xin24m),
- CLK(NULL,"pd_lcdc1",&xin24m),
- CLK(NULL,"hclk_lcdc1",&xin24m),
- CLK(NULL,"aclk_lcdc1",&xin24m),
- CLK(NULL,"dclk_lcdc1",&xin24m),
-
- CLK(NULL,"pd_cif0",&xin24m),
- CLK(NULL,"aclk_cif0",&xin24m),
- CLK(NULL,"hclk_cif0",&xin24m),
- CLK(NULL,"cif0_in",&xin24m),
- CLK(NULL,"cif0_out",&xin24m),
-
- CLK(NULL,"pwm01",&xin24m),
-};
-
-static void __init rk30_clock_init(void)
-{
- struct clk_lookup *lk;
-
- for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) {
- clkdev_add(lk);
- }
-}
-
-void __init board_clock_init(void)
-{
- rk30_clock_init();
-}
-
-int __init clk_disable_unused(void)
-{
- return 0;
-}
-
-int clk_enable(struct clk *clk)
-{
- return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
- if(clk)
- return clk->rate;
- else
- return 24000000;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
- return 0;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
- return 0;
-}
-EXPORT_SYMBOL(clk_set_parent);
-
-#include <mach/gpio.h>
-#include <plat/key.h>
-
-#define EV_ENCALL KEY_F4
-#define EV_MENU KEY_F1
-
-#define PRESS_LEV_LOW 1
-#define PRESS_LEV_HIGH 0
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "menu",
- .code = EV_MENU,
- .gpio = RK30_PIN3_PB2,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .gpio = RK30_PIN3_PB1,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .gpio = RK30_PIN3_PB0,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .gpio = RK30_PIN3_PB3,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .gpio = RK30_PIN3_PB4,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "key6",
- .code = KEY_CAMERA,
- .gpio = RK30_PIN3_PB5,
- .active_low = PRESS_LEV_LOW,
- },
-};
-
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = -1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
-static void __init fpga_fixup(struct machine_desc *desc, struct tag *tags,
- char **cmdline, struct meminfo *mi)
-{
- mi->nr_banks = 1;
- mi->bank[0].start = PLAT_PHYS_OFFSET;
- mi->bank[0].size = SZ_128M;
-}
-
-#include <mach/system.h>
-static void fpga_reset(char mode, const char *cmd)
-{
- while (1);
-}
-
-static void __init fpga_map_io(void)
-{
- arch_reset = fpga_reset;
- rk30_map_common_io();
- rk29_setup_early_printk();
- rk29_sram_init();
- board_clock_init();
- rk30_iomux_init();
-}
-
-MACHINE_START(RK31, "RK31board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = fpga_fixup,
- .reserve = &rk31_reserve,
- .map_io = fpga_map_io,
- .init_irq = rk30_init_irq,
- .timer = &rk30_timer,
- .init_machine = rk31_board_init,
-MACHINE_END
+++ /dev/null
-#ifdef CONFIG_VIDEO_RK29
-
-#include <plat/rk_camera.h>
-/* Notes:
-
-Simple camera device registration:
-
- new_camera_device(sensor_name,\ // sensor name, it is equal to CONFIG_SENSOR_X
- face,\ // sensor face information, it can be back or front
- pwdn_io,\ // power down gpio configuration, it is equal to CONFIG_SENSOR_POWERDN_PIN_XX
- flash_attach,\ // sensor is attach flash or not
- mir,\ // sensor image mirror and flip control information
- i2c_chl,\ // i2c channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_IIC_ADAPTER_ID_X
- cif_chl) \ // cif channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_CIF_INDEX_X
-
-Comprehensive camera device registration:
-
- new_camera_device_ex(sensor_name,\
- face,\
- ori,\ // sensor orientation, it is equal to CONFIG_SENSOR_ORIENTATION_X
- pwr_io,\ // sensor power gpio configuration, it is equal to CONFIG_SENSOR_POWER_PIN_XX
- pwr_active,\ // sensor power active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- rst_io,\ // sensor reset gpio configuration, it is equal to CONFIG_SENSOR_RESET_PIN_XX
- rst_active,\ // sensor reset active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- pwdn_io,\
- pwdn_active,\ // sensor power down active level, is equal to CONFIG_SENSOR_POWERDNACTIVE_LEVEL_X
- flash_attach,\
- res,\ // sensor resolution, this is real resolution or resoltuion after interpolate
- mir,\
- i2c_chl,\
- i2c_spd,\ // i2c speed , 100000 = 100KHz
- i2c_addr,\ // the i2c slave device address for sensor
- cif_chl,\
- mclk)\ // sensor input clock rate, 24 or 48
-
-*/
-static struct rkcamera_platform_data new_camera[] = {
- new_camera_device(RK29_CAM_SENSOR_HI253,
- back,
- RK30_PIN3_PB5,
- 0,
- 0,
- 4,
- 0),
- new_camera_device(RK29_CAM_SENSOR_HI704,
- front,
- RK30_PIN3_PB4,
- 0,
- 0,
- 4,
- 0),
- new_camera_device_end
-};
-
-/*---------------- Camera Sensor Macro Define Begin ------------------------*/
-/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
-#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_HI253 /* back camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_0 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 4
-#define CONFIG_SENSOR_ORIENTATION_0 90
-#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 RK30_PIN3_PB5
-#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000
-
-#define CONFIG_SENSOR_01 RK29_CAM_SENSOR_OV5642 /* back camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_01 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 4
-#define CONFIG_SENSOR_ORIENTATION_01 90
-#define CONFIG_SENSOR_POWER_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_01 RK30_PIN1_PD6
-#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_01 30000
-
-#define CONFIG_SENSOR_02 RK29_CAM_SENSOR_OV5640 /* back camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_02 0x00
-#define CONFIG_SENSOR_CIF_INDEX_02 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 4
-#define CONFIG_SENSOR_ORIENTATION_02 90
-#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000
-
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_HI704 /* front camera sensor 0 */
-#define CONFIG_SENSOR_IIC_ADDR_1 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 4
-#define CONFIG_SENSOR_ORIENTATION_1 270
-#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_1 RK30_PIN3_PB4
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000
-
-#define CONFIG_SENSOR_11 RK29_CAM_SENSOR_OV2659 /* front camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_11 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 4
-#define CONFIG_SENSOR_ORIENTATION_11 270
-#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_11 INVALID_GPIO//RK30_PIN1_PB7
-#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_11 30000
-
-#define CONFIG_SENSOR_12 RK29_CAM_SENSOR_OV2659//RK29_CAM_SENSOR_OV2655 /* front camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_12 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 3
-#define CONFIG_SENSOR_ORIENTATION_12 270
-#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_12 INVALID_GPIO//RK30_PIN1_PB7
-#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_12 30000
-
-
-#endif //#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk30_camera.c"
-/*---------------- Camera Sensor Macro Define End ---------*/
-
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#define CONFIG_SENSOR_POWER_IOCTL_USR 1 //define this refer to your board layout
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
-
-static void rk_cif_power(int on)
-{
- struct regulator *ldo_18,*ldo_28;
- ldo_28 = regulator_get(NULL, "vmmc"); // vcc28_cif
- ldo_18 = regulator_get(NULL, "vdig1"); // vcc18_cif
- if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){
- printk("get cif ldo failed!\n");
- return;
- }
- if(on == 0){
- regulator_disable(ldo_28);
- regulator_put(ldo_28);
- regulator_disable(ldo_18);
- regulator_put(ldo_18);
- mdelay(500);
- }
- else{
- regulator_set_voltage(ldo_28, 2800000, 2800000);
- regulator_enable(ldo_28);
- // printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
- regulator_put(ldo_28);
-
- regulator_set_voltage(ldo_18, 1800000, 1800000);
- // regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(ldo_18);
- // printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
- regulator_put(ldo_18);
- }
-}
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- //#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
- rk_cif_power(on);
- return 0;
-}
-#endif
-
-#if CONFIG_SENSOR_RESET_IOCTL_USR
-static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
-static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-
-#if CONFIG_SENSOR_IIC_ADDR_0
-static struct reginfo_t rk_init_data_sensor_reg_0[] =
-{
- {0x0000, 0x00,0,0}
- };
-static struct reginfo_t rk_init_data_sensor_winseqreg_0[] ={
- {0x0000, 0x00,0,0}
- };
-#endif
-
-#if CONFIG_SENSOR_IIC_ADDR_1
-static struct reginfo_t rk_init_data_sensor_reg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_01
-static struct reginfo_t rk_init_data_sensor_reg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_02
-static struct reginfo_t rk_init_data_sensor_reg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_11
-static struct reginfo_t rk_init_data_sensor_reg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_12
-static struct reginfo_t rk_init_data_sensor_reg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] =
-{
- #if CONFIG_SENSOR_IIC_ADDR_0
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_0,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_1
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_1,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_01
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_01,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_02
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_02,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_11
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_11,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_12
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_12,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
-
- };
-#include "../../../drivers/media/video/rk30_camera.c"
-
-#endif /* CONFIG_VIDEO_RK29 */
+++ /dev/null
-/*
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <mach/dvfs.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <linux/fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/mfd/tps65910.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-
-#if defined(CONFIG_MFD_RK610)
-#include <linux/mfd/rk610_core.h>
-#endif
-
-#if defined(CONFIG_HDMI_RK30)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-#if defined(CONFIG_MU509)
-#include <linux/mu509.h>
-#endif
-#if defined(CONFIG_MW100)
-#include <linux/mw100.h>
-#endif
-#if defined(CONFIG_MT6229)
-#include <linux/mt6229.h>
-#endif
-#if defined(CONFIG_SEW868)
-#include <linux/sew868.h>
-#endif
-#if defined(CONFIG_ANDROID_TIMED_GPIO)
-#include "../../../drivers/staging/android/timed_gpio.h"
-#endif
-
-#include "board-rk3066b-m701-camera.c"
-
-#include <plat/key.h>
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .gpio = RK30_PIN0_PB5,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK30_PIN0_PA4,
- .active_low = PRESS_LEV_LOW,
- .wakeup = 1,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .adc_value = 1,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-};
-
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = 1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
-#if defined(CONFIG_TOUCHSCREEN_GT8XX)
-#define TOUCH_RESET_PIN RK30_PIN2_PC0
-#define TOUCH_PWR_PIN RK30_PIN2_PB4
-static int goodix_init_platform_hw(void)
-{
- int ret;
-
- if (TOUCH_PWR_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_PWR_PIN, "goodix power pin");
- if (ret != 0) {
- gpio_free(TOUCH_PWR_PIN);
- printk("goodix power error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_PWR_PIN, 0);
- gpio_set_value(TOUCH_PWR_PIN, GPIO_LOW);
- msleep(100);
- }
-
- if (TOUCH_RESET_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_RESET_PIN, "goodix reset pin");
- if (ret != 0) {
- gpio_free(TOUCH_RESET_PIN);
- printk("goodix gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, 1);
- msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_LOW);
- //msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_HIGH);
- //msleep(500);
- }
- return 0;
-}
-
-struct goodix_platform_data goodix_info = {
- .model = 8105,
- .irq_pin = RK30_PIN0_PD4,
- .rest_pin = TOUCH_RESET_PIN,
- .init_platform_hw = goodix_init_platform_hw,
-};
-#endif
-
-#if defined (CONFIG_TOUCHSCREEN_FT5306_AV)
-
-#define TOUCH_RESET_PIN RK30_PIN2_PC0
-#define TOUCH_INT_PIN RK30_PIN0_PD4
-
-static int ft5306_init_platform_hw(void)
-{
- printk("ft5306_init_platform_hw \n");
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("ft5306_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("ift5306_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- gpio_direction_output(TOUCH_RESET_PIN, 1);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- mdelay(50);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- mdelay(50);
- gpio_direction_input(TOUCH_INT_PIN);
- mdelay(10);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- msleep(300);
- return 0;
-}
-
-void ft5306_exit_platform_hw(void)
-{
- printk("ft5606_exit_platform_hw\n");
- gpio_free(TOUCH_RESET_PIN);
- gpio_free(TOUCH_INT_PIN);
-}
-
-int ft5306_platform_sleep(void)
-{
- printk("ft5606_platform_sleep\n");
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- return 0;
-}
-
-int ft5306_platform_wakeup(void)
-{
- printk("ft5606_platform_wakeup\n");
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- msleep(300);
- return 0;
-}
-
-struct ft5606_platform_data ft5306_info = {
-
- .init_platform_hw= ft5306_init_platform_hw,
- .exit_platform_hw= ft5306_exit_platform_hw,
- .platform_sleep= ft5306_platform_sleep,
- .platform_wakeup= ft5306_platform_wakeup,
-};
-#endif
-
-
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-#define PWM_ID 2
-#define PWM_MODE PWM2
-#define PWM_EFFECT_VALUE 0
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-#define BL_EN_PIN RK30_PIN0_PA2
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
-
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
- ret = gpio_request(BL_EN_PIN, "bl_en");
- if (ret == 0) {
- gpio_direction_output(BL_EN_PIN, BL_EN_VALUE);
- }
-#endif
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0, pwm_gpio;
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, !BL_EN_VALUE);
- gpio_free(BL_EN_PIN);
-#endif
- pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
- gpio_request(pwm_gpio, "bl_pwm");
- gpio_direction_input(pwm_gpio);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret, pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
-
- ret = gpio_request(pwm_gpio, "bl_pwm");
- if (ret) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return ret;
- }
- gpio_direction_input(pwm_gpio);
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, !BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- int pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
-
- gpio_free(pwm_gpio);
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .min_brightness = 40,
- .delay_ms = 0,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-#endif
-
-#ifdef CONFIG_RK29_SUPPORT_MODEM
-
-#define RK30_MODEM_POWER RK30_PIN2_PB0
-#define RK30_MODEM_POWER_IOMUX rk29_mux_api_set(GPIO2B0_LCDC1DATA8_SMCDATA8_TRACEDATA8_NAME, GPIO2B_GPIO2B0)
-
-static int rk30_modem_io_init(void)
-{
- printk("%s\n", __FUNCTION__);
- RK30_MODEM_POWER_IOMUX;
-
- return 0;
-}
-
-static struct rk29_io_t rk30_modem_io = {
- .io_addr = RK30_MODEM_POWER,
- .enable = GPIO_HIGH,
- .disable = GPIO_LOW,
- .io_init = rk30_modem_io_init,
-};
-
-static struct platform_device rk30_device_modem = {
- .name = "rk30_modem",
- .id = -1,
- .dev = {
- .platform_data = &rk30_modem_io,
- }
-};
-#endif
-#if defined(CONFIG_MU509)
-static int mu509_io_init(void)
-{
-
- rk30_mux_api_set(GPIO2B0_LCDC1DATA8_SMCDATA8_TRACEDATA8_NAME, GPIO2B_GPIO2B0);
- rk30_mux_api_set(GPIO2D1_LCDC1DEN_SMCWEN_NAME, GPIO2D_GPIO2D1);
- rk30_mux_api_set(GPIO2B7_LCDC1DATA15_SMCADDR19_HSADCDATA7_NAME, GPIO2B_GPIO2B7);
- rk30_mux_api_set(GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME, GPIO2C_GPIO2C0);
- return 0;
-}
-
-static int mu509_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mu509_data rk29_mu509_info = {
- .io_init = mu509_io_init,
- .io_deinit = mu509_io_deinit,
- .modem_power_en = RK30_PIN2_PB0,
- .bp_power = RK30_PIN2_PB0,
- .bp_reset = RK30_PIN2_PD1,
- .ap_wakeup_bp = RK30_PIN2_PB7,
- .bp_wakeup_ap = RK30_PIN6_PA0,
-};
-struct platform_device rk29_device_mu509 = {
- .name = "mu509",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mu509_info,
- }
- };
-#endif
-#if defined(CONFIG_MW100)
-static int mw100_io_init(void)
-{
- rk30_mux_api_set(GPIO2B0_LCDC1DATA8_SMCDATA8_TRACEDATA8_NAME, GPIO2B_GPIO2B0);
- rk30_mux_api_set(GPIO2D1_LCDC1DEN_SMCWEN_NAME, GPIO2D_GPIO2D1);
- rk30_mux_api_set(GPIO2B7_LCDC1DATA15_SMCADDR19_HSADCDATA7_NAME, GPIO2B_GPIO2B7);
- rk30_mux_api_set(GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME, GPIO2C_GPIO2C0);
- return 0;
-}
-
-static int mw100_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mw100_data rk29_mw100_info = {
- .io_init = mw100_io_init,
- .io_deinit = mw100_io_deinit,
- .modem_power_en = RK30_PIN6_PB0,
- .bp_power = RK30_PIN2_PB0,
- .bp_reset = RK30_PIN2_PD1,
- .ap_wakeup_bp = RK30_PIN2_PB7,
- .bp_wakeup_ap = RK30_PIN6_PA0,
-};
-struct platform_device rk29_device_mw100 = {
- .name = "mw100",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mw100_info,
- }
- };
-#endif
-#if defined(CONFIG_MT6229)
-static int mt6229_io_init(void)
-{
- rk30_mux_api_set(GPIO2B0_LCDC1DATA8_SMCDATA8_TRACEDATA8_NAME, GPIO2B_GPIO2B0);
- rk30_mux_api_set(GPIO2D1_LCDC1DEN_SMCWEN_NAME, GPIO2D_GPIO2D1);
- rk30_mux_api_set(GPIO2B7_LCDC1DATA15_SMCADDR19_HSADCDATA7_NAME, GPIO2B_GPIO2B7);
- rk30_mux_api_set(GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME, GPIO2C_GPIO2C0);
- return 0;
-}
-
-static int mt6229_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mt6229_data rk29_mt6229_info = {
- .io_init = mt6229_io_init,
- .io_deinit = mt6229_io_deinit,
- .modem_power_en = RK30_PIN2_PB0,
- .bp_power = RK30_PIN2_PB0,//RK30_PIN2_PB6,
- .bp_reset = RK30_PIN2_PD1,
- .ap_wakeup_bp = RK30_PIN2_PC0,
- .bp_wakeup_ap = RK30_PIN6_PA0,
-};
-struct platform_device rk29_device_mt6229 = {
- .name = "mt6229",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mt6229_info,
- }
- };
-#endif
-#if defined(CONFIG_SEW868)
-static int sew868_io_init(void)
-{
- rk30_mux_api_set(GPIO2B6_LCDC1DATA14_SMCADDR18_TSSYNC_NAME, GPIO2B_GPIO2B6);
- rk30_mux_api_set(GPIO4D2_SMCDATA10_TRACEDATA10_NAME, GPIO4D_GPIO4D2);
- rk30_mux_api_set(GPIO4D4_SMCDATA12_TRACEDATA12_NAME, GPIO4D_GPIO4D4);
- return 0;
-}
-static int sew868_io_deinit(void)
-{
- return 0;
-}
-struct rk30_sew868_data rk30_sew868_info = {
- .io_init = sew868_io_init,
- .io_deinit = sew868_io_deinit,
- .bp_power = RK30_PIN6_PB2,
- .bp_power_active_low = 1,
- .bp_sys = RK30_PIN2_PB6,
- .bp_reset = RK30_PIN4_PD2,
- .bp_reset_active_low = 1,
- .bp_wakeup_ap = RK30_PIN4_PD4,
- .ap_wakeup_bp = NULL,
-};
-
-struct platform_device rk30_device_sew868 = {
- .name = "sew868",
- .id = -1,
- .dev = {
- .platform_data = &rk30_sew868_info,
- }
- };
-#endif
-
-
-/*MMA7660 gsensor*/
-#if defined (CONFIG_GS_MMA7660)
-#define MMA7660_INT_PIN RK30_PIN3_PD7
-
-static int mma7660_init_platform_hw(void)
-{
- if(gpio_request(MMA7660_INT_PIN, NULL) != 0){
- gpio_free(MMA7660_INT_PIN);
- printk("gsensor gpio_request error\n");
- return -EIO;
- }
- //gpio_direction_input(MMA7660_INT_PIN);
- return 0;
-}
-
-static struct sensor_platform_data mma7660_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma7660_init_platform_hw,
- .orientation = {0, 1, 0, 0, 0, -1, 1, 0, 0},
-};
-#endif
-
-
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN RK30_PIN3_PD7
-
-static int mma8452_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data mma8452_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma8452_init_platform_hw,
- .orientation = {-1, 0, 0, 0, 0, 1, 0, -1, 0},
-};
-#endif
-#if defined (CONFIG_GS_LIS3DH)
-#define LIS3DH_INT_PIN RK30_PIN3_PD7
-
-static int lis3dh_init_platform_hw(void)
-{
-
- return 0;
-}
-
-static struct sensor_platform_data lis3dh_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lis3dh_init_platform_hw,
- .orientation = {-1, 0, 0, 0, 0, 1, 0, -1, 0},
-};
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
-static struct sensor_platform_data akm8975_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-#if defined(CONFIG_GYRO_L3G4200D)
-
-#include <linux/l3g4200d.h>
-#define L3G4200D_INT_PIN RK30_PIN0_PB4
-
-static int l3g4200d_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data l3g4200d_info = {
- .type = SENSOR_TYPE_GYROSCOPE,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
- .init_platform_hw = l3g4200d_init_platform_hw,
- .x_min = 40,//x_min,y_min,z_min = (0-100) according to hardware
- .y_min = 40,
- .z_min = 20,
-};
-
-#endif
-
-#ifdef CONFIG_LS_CM3217
-static struct sensor_platform_data cm3217_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 0,
- .poll_delay_ms = 500,
-};
-
-#endif
-
-#ifdef CONFIG_FB_ROCKCHIP
-
-#define LCD_CS_PIN RK30_PIN2_PB6
-#define LCD_CS_VALUE GPIO_HIGH
-
-#define LCD_EN_PIN RK30_PIN0_PB0
-#define LCD_EN_VALUE GPIO_LOW
-
-#define LCD_STB_PIN RK30_PIN2_PB3
-#define LCD_STB_VALUE GPIO_HIGH
-
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
-
- if(LCD_STB_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_STB_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_STB_PIN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_STB_PIN, LCD_STB_VALUE);
- }
- }
-
- msleep(100);
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_CS_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_CS_PIN);
- printk(KERN_ERR "request lcd cs pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_CS_PIN, LCD_CS_VALUE);
- }
- }
-
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_EN_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_EN_PIN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_EN_PIN, LCD_EN_VALUE);
- }
- }
-
-
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
- if(LCD_STB_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_STB_PIN, !LCD_STB_VALUE);
- }
- msleep(100);
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, !LCD_CS_VALUE);
- }
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, !LCD_EN_VALUE);
- }
-
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- if(LCD_STB_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_STB_PIN, LCD_STB_VALUE);
- }
- msleep(50);
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE);
- }
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
- }
- return 0;
-}
-
-#if defined(CONFIG_LCDC0_RK3066B)
-struct rk29fb_info lcdc0_screen_info = {
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B)
-struct rk29fb_info lcdc1_screen_info = {
- #if defined(CONFIG_HDMI_RK30)
- .prop = EXTEND, //extend display device
- .lcd_info = NULL,
- .set_screen_info = hdmi_init_lcdc,
- #endif
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B)
-static struct resource resource_lcdc0[] = {
- [0] = {
- .name = "lcdc0 reg",
- .start = RK30_LCDC0_PHYS,
- .end = RK30_LCDC0_PHYS + RK30_LCDC0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc0 irq",
- .start = IRQ_LCDC0,
- .end = IRQ_LCDC0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc0 = {
- .name = "rk30-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc0),
- .resource = resource_lcdc0,
- .dev = {
- .platform_data = &lcdc0_screen_info,
- },
-};
-#endif
-#if defined(CONFIG_LCDC1_RK3066B)
-static struct resource resource_lcdc1[] = {
- [0] = {
- .name = "lcdc1 reg",
- .start = RK30_LCDC1_PHYS,
- .end = RK30_LCDC1_PHYS + RK30_LCDC1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc1 irq",
- .start = IRQ_LCDC1,
- .end = IRQ_LCDC1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc1 = {
- .name = "rk30-lcdc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resource_lcdc1),
- .resource = resource_lcdc1,
- .dev = {
- .platform_data = &lcdc1_screen_info,
- },
-};
-#endif
-
-#if defined(CONFIG_MFD_RK610)
-#define RK610_RST_PIN_MUX_NAME GPIO2C5_LCDC1DATA21_SMCADDR5_NAME
-#define RK610_RST_PIN_MUX_MODE GPIO2C_GPIO2C5
-#define RK610_RST_PIN RK30_PIN2_PC5
-static int rk610_power_on_init(void)
-{
- int ret;
- if(RK610_RST_PIN != INVALID_GPIO)
- {
- ret = gpio_request(RK610_RST_PIN, "rk610 reset");
- if (ret)
- {
- printk(KERN_ERR "rk610_control_probe request gpio fail\n");
- }
- else
- {
- gpio_direction_output(RK610_RST_PIN, GPIO_HIGH);
- msleep(100);
- gpio_direction_output(RK610_RST_PIN, GPIO_LOW);
- msleep(100);
- gpio_set_value(RK610_RST_PIN, GPIO_HIGH);
- }
- }
-
- return 0;
-
-}
-
-
-static struct rk610_ctl_platform_data rk610_ctl_pdata = {
- .rk610_power_on_init = rk610_power_on_init,
-};
-#endif
-
-#ifdef CONFIG_SND_SOC_RK610
-static int rk610_codec_io_init(void)
-{
-//if need iomux.
-//Must not gpio_request
- return 0;
-}
-
-static struct rk610_codec_platform_data rk610_codec_pdata = {
- .spk_ctl_io = RK30_PIN2_PA0,
- .io_init = rk610_codec_io_init,
-};
-#endif
-
-#ifdef CONFIG_ANDROID_TIMED_GPIO
-static struct timed_gpio timed_gpios[] = {
- {
- .name = "vibrator",
- .gpio = RK30_PIN3_PD3,
- .max_timeout = 1000,
- .active_low = 0,
- .adjust_time =20, //adjust for diff product
- },
-};
-
-static struct timed_gpio_platform_data rk29_vibrator_info = {
- .num_gpios = 1,
- .gpios = timed_gpios,
-};
-
-static struct platform_device rk29_device_vibrator = {
- .name = "timed-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_vibrator_info,
- },
-
-};
-#endif
-
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
-static struct gpio_led rk29_leds[] = {
- {
- .name = "button-backlight",
- .gpio = RK30_PIN2_PB3,
- .default_trigger = "timer",
- .active_low = 0,
- .retain_state_suspended = 0,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- },
-};
-
-static struct gpio_led_platform_data rk29_leds_pdata = {
- .leds = rk29_leds,
- .num_leds = ARRAY_SIZE(rk29_leds),
-};
-
-static struct platform_device rk29_device_gpio_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_leds_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_RK_IRDA
-#define IRDA_IRQ_PIN RK30_PIN0_PA3
-
-static int irda_iomux_init(void)
-{
- int ret = 0;
-
- //irda irq pin
- ret = gpio_request(IRDA_IRQ_PIN, NULL);
- if (ret != 0) {
- gpio_free(IRDA_IRQ_PIN);
- printk(">>>>>> IRDA_IRQ_PIN gpio_request err \n ");
- }
- gpio_pull_updown(IRDA_IRQ_PIN, PullDisable);
- gpio_direction_input(IRDA_IRQ_PIN);
-
- return 0;
-}
-
-static int irda_iomux_deinit(void)
-{
- gpio_free(IRDA_IRQ_PIN);
- return 0;
-}
-
-static struct irda_info rk29_irda_info = {
- .intr_pin = IRDA_IRQ_PIN,
- .iomux_init = irda_iomux_init,
- .iomux_deinit = irda_iomux_deinit,
- //.irda_pwr_ctl = bu92747guw_power_ctl,
-};
-
-static struct platform_device irda_device = {
-#ifdef CONFIG_RK_IRDA_NET
- .name = "rk_irda",
-#else
- .name = "bu92747_irda",
-#endif
- .id = -1,
- .dev = {
- .platform_data = &rk29_irda_info,
- }
-};
-#endif
-
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and SDIO.noted by xbw at 2012-03-05
-**************************************************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "board-rk30-sdk-sdmmc.c"
-#endif
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- rk30_mux_api_set(GPIO3B1_SDMMC0CMD_NAME, GPIO3B_SDMMC0_CMD);
- rk30_mux_api_set(GPIO3B0_SDMMC0CLKOUT_NAME, GPIO3B_SDMMC0_CLKOUT);
- rk30_mux_api_set(GPIO3B2_SDMMC0DATA0_NAME, GPIO3B_SDMMC0_DATA0);
- rk30_mux_api_set(GPIO3B3_SDMMC0DATA1_NAME, GPIO3B_SDMMC0_DATA1);
- rk30_mux_api_set(GPIO3B4_SDMMC0DATA2_NAME, GPIO3B_SDMMC0_DATA2);
- rk30_mux_api_set(GPIO3B5_SDMMC0DATA3_NAME, GPIO3B_SDMMC0_DATA3);
-
- rk30_mux_api_set(GPIO3B6_SDMMC0DETECTN_NAME, GPIO3B_GPIO3B6);
-
- rk30_mux_api_set(GPIO3A7_SDMMC0PWREN_NAME, GPIO3A_GPIO3A7);
- gpio_request(RK30_PIN3_PA7, "sdmmc-power");
- gpio_direction_output(RK30_PIN3_PA7, GPIO_LOW);
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- #if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO);
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FMUX);
- #endif
-
- #if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
- #endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) && defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- .status = rk29sdk_wifi_mmc0_status,
- .register_status_notify = rk29sdk_wifi_mmc0_status_register,
-#endif
-
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .power_en = RK29SDK_SD_CARD_PWR_EN,
- .power_en_level = RK29SDK_SD_CARD_PWR_EN_LEVEL,
-#else
- .power_en = INVALID_GPIO,
- .power_en_level = GPIO_LOW,
-#endif
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC0_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- .det_pin_info = {
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N, //INVALID_GPIO,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
- #endif
- },
-
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- rk30_mux_api_set(GPIO3C0_SMMC1CMD_NAME, GPIO3C_SMMC1_CMD);
- rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_NAME, GPIO3C_SDMMC1_CLKOUT);
- rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_NAME, GPIO3C_SDMMC1_DATA0);
- rk30_mux_api_set(GPIO3C2_SDMMC1DATA1_NAME, GPIO3C_SDMMC1_DATA1);
- rk30_mux_api_set(GPIO3C3_SDMMC1DATA2_NAME, GPIO3C_SDMMC1_DATA2);
- rk30_mux_api_set(GPIO3C4_SDMMC1DATA3_NAME, GPIO3C_SDMMC1_DATA3);
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC) || defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-
- #if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC1_WRITE_PROTECT_ENABLE_VALUE;
- #else
- .write_prt = INVALID_GPIO,
- #endif
-
- #if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
- .sdio_INT_gpio = RK29SDK_WIFI_SDIO_CARD_INT,
- #endif
-
- .det_pin_info = {
-#if defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- #else
- .io = INVALID_GPIO,
- #endif
-
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-
- .enable_sd_wakeup = 0,
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-/**************************************************************************************************
- * the end of setting for SDMMC devices
-**************************************************************************************************/
-
-#if defined(CONFIG_BATTERY_RK30_ADC)
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = RK30_PIN0_PB2,
- .batt_low_pin = RK30_PIN0_PB1,
- .charge_set_pin = RK30_PIN2_PA7,
- .charge_ok_pin = RK30_PIN0_PA6,
- .dc_det_level = GPIO_LOW,
- .charge_ok_level = GPIO_HIGH,
- .charge_set_level = GPIO_HIGH,
- .save_capacity = 1,
-};
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-
-#elif defined(CONFIG_BATTERY_RK30_ADC_FAC)
-
-#define BOARD_BAT_DEFINE_VALUE (1800) /* bat_zx: the same with BAT_DEFINE_VALUE in RK3066B */
-#define BOARD_BATT_NUM (11) /* bat_zx: the same with BATT_NUM */
-#define BOARD_BATT_PULLUP_RES (200) /* bat_zx: the same with batt_table[4] */
-#define BOARD_BATT_PULLDOWN_RES (100) /* bat_zx: the same with batt_table[5] */
-#define BOARD_BATT_DISCHG_OFFSET (6)
-#define BOARD_BATT_CHG_OFFSET (BOARD_BATT_DISCHG_OFFSET + BOARD_BATT_NUM)
-
-static const int batt_table[2*BOARD_BATT_NUM+6] =
-{
- 0x4B434F52, 0x7461625F, 0x79726574, 0, 200, 100,
- 3400, 3469, 3566, 3642, 3660, 3680, 3728, 3815, 3878, 3957, 4082, //discharge
- 3703, 3848, 3931, 3956, 3993, 4074, 4145, 4154, 4159, 4160, 4166 //charge
-};
-
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = RK30_PIN0_PB2,
- .batt_low_pin = RK30_PIN0_PB1,
- .charge_set_pin = RK30_PIN2_PA7,
- .charge_ok_pin = RK30_PIN0_PA6,
- .dc_det_level = GPIO_LOW,
- .charge_ok_level = GPIO_HIGH,
- .charge_set_level = GPIO_HIGH,
-
- .is_reboot_charging = 1,
- .save_capacity = 1,
- .use_board_table = 1,
- .table_size = BOARD_BATT_NUM,
- .board_batt_table = batt_table,
- .discharge_table = &batt_table[BOARD_BATT_DISCHG_OFFSET],
- .charge_table = &batt_table[BOARD_BATT_CHG_OFFSET],
- .reference_voltage = BOARD_BAT_DEFINE_VALUE,
- .pull_up_res = BOARD_BATT_PULLUP_RES,
- .pull_down_res = BOARD_BATT_PULLDOWN_RES,
-};
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-#ifdef CONFIG_RK30_PWM_REGULATOR
-const static int pwm_voltage_map[] = {
- 950000, 975000,1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000, 1375000, 1400000
-};
-
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_core",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] =
-{
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
- .pwm_id = 3,
- .pwm_gpio = RK30_PIN3_PD6,
- .pwm_iomux_pwm = PWM3,
- .pwm_iomux_gpio = GPIO3_D6,
- .pwm_voltage = 1000000,
- .suspend_voltage = 1050000,
- .min_uV = 950000,
- .max_uV = 1400000,
- .coefficient = 455, //45.5%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-#endif
-
-#ifdef CONFIG_RK29_VMAC
-#define PHY_PWR_EN_GPIO RK30_PIN1_PD6
-#include "board-rk30-sdk-vmac.c"
-#endif
-
-#ifdef CONFIG_RFKILL_RK
-// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
-static struct rfkill_rk_platform_data rfkill_rk_platdata = {
- .type = RFKILL_TYPE_BLUETOOTH,
-
- .poweron_gpio = { // BT_REG_ON
- .io = RK30_PIN3_PC7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_poweron",
- .fgpio = GPIO3_C7,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN3_PD1, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_reset",
- .fgpio = GPIO3_D1,
- },
- },
-
- .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
- .io = RK30_PIN3_PC6, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_wake",
- .fgpio = GPIO3_C6,
- },
- },
-
- .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .gpio = {
- .io = RK30_PIN0_PA5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
- .iomux = {
- .name = NULL,
- },
- },
- },
-
- .rts_gpio = { // UART_RTS, enable or disable BT's data coming
- .io = RK30_PIN1_PA3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_rts",
- .fgpio = GPIO1_A3,
- .fmux = UART0_RTSN,
- },
- },
-};
-
-static struct platform_device device_rfkill_rk = {
- .name = "rfkill_rk",
- .id = -1,
- .dev = {
- .platform_data = &rfkill_rk_platdata,
- },
-};
-#endif
-
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_FB_ROCKCHIP
- &device_fb,
-#endif
-#if defined(CONFIG_LCDC0_RK3066B)
- &device_lcdc0,
-#endif
-#if defined(CONFIG_LCDC1_RK3066B)
- &device_lcdc1,
-#endif
-
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- &rk29_device_backlight,
-#endif
-
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_ANDROID_TIMED_GPIO
- &rk29_device_vibrator,
-#endif
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
- &rk29_device_gpio_leds,
-#endif
-#ifdef CONFIG_RK_IRDA
- &irda_device,
-#endif
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- &rk29sdk_wifi_device,
-#endif
-#ifdef CONFIG_RK29_SUPPORT_MODEM
- &rk30_device_modem,
-#endif
-#if defined(CONFIG_MU509)
- &rk29_device_mu509,
-#endif
-#if defined(CONFIG_MW100)
- &rk29_device_mw100,
-#endif
-#if defined(CONFIG_MT6229)
- &rk29_device_mt6229,
-#endif
-#if defined(CONFIG_SEW868)
- &rk30_device_sew868,
-#endif
-#if defined(CONFIG_BATTERY_RK30_ADC) || defined(CONFIG_BATTERY_RK30_ADC_FAC)
- &rk30_device_adc_battery,
-#endif
-#ifdef CONFIG_RFKILL_RK
- &device_rfkill_rk,
-#endif
-};
-
-// i2c
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_GS_MMA7660)
- {
- .type = "gs_mma7660",
- .addr = 0x4c,
- .flags = 0,
- .irq = MMA7660_INT_PIN,
- .platform_data = &mma7660_info,
- },
-#endif
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1d,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_GS_LIS3DH)
- {
- .type = "gs_lis3dh",
- .addr = 0x19, //0x19(SA0-->VCC), 0x18(SA0-->GND)
- .flags = 0,
- .irq = LIS3DH_INT_PIN,
- .platform_data = &lis3dh_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN0_PD5,
- .platform_data = &akm8975_info,
- },
-#endif
-#if defined (CONFIG_GYRO_L3G4200D)
- {
- .type = "l3g4200d_gryo",
- .addr = 0x69,
- .flags = 0,
- .irq = L3G4200D_INT_PIN,
- .platform_data = &l3g4200d_info,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RT5631)
- {
- .type = "rt5631",
- .addr = 0x1a,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_ES8323)
- {
- .type = "es8323",
- .addr = 0x10,
- .flags = 0,
- },
-#endif
-#ifdef CONFIG_MFD_RK610
- {
- .type = "rk610_ctl",
- .addr = 0x40,
- .flags = 0,
- .platform_data = &rk610_ctl_pdata,
- },
-#ifdef CONFIG_RK610_TVOUT
- {
- .type = "rk610_tvout",
- .addr = 0x42,
- .flags = 0,
- },
-#endif
-#ifdef CONFIG_HDMI_RK610
- {
- .type = "rk610_hdmi",
- .addr = 0x46,
- .flags = 0,
- .irq = RK30_PIN0_PB6,
- },
-#endif
-#ifdef CONFIG_SND_SOC_RK610
- {//RK610_CODEC addr from 0x60 to 0x80 (0x60~0x80)
- .type = "rk610_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- .platform_data = &rk610_codec_pdata,
- },
-#endif
-#endif
-
-};
-#endif
-
-int __sramdata g_pmic_type = 0;
-#ifdef CONFIG_I2C1_RK30
-#ifdef CONFIG_MFD_WM831X_I2C
-
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info wm8326_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "dcdc3", //ddr
- .min_uv = 1150000,
- .max_uv = 1150000,
- .suspend_vol = 1150000,
- },
- #ifdef CONFIG_MACH_RK3066_SDK
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3000000,
- },
- #else
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3000000,
- .max_uv = 3000000,
- .suspend_vol = 2800000,
- },
- #endif
-};
-
-static struct pmu_info wm8326_ldo_info[] = {
- {
- .name = "ldo1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo2", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo3", //
- .min_uv = 1100000,
- .max_uv = 1100000,
- .suspend_vol = 1100000,
- },
- {
- .name = "ldo4", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 1000000,
- },
- {
- .name = "ldo5", //vcc25
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo6", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo7", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- .suspend_vol = 2800000,
- },
- {
- .name = "ldo8", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo9", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo10", //flash_io
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
-};
-
-#include "board-pmu-wm8326.c"
-#endif
-
-#ifdef CONFIG_MFD_TPS65910
-#ifdef CONFIG_ARCH_RK3066B
-#define TPS65910_HOST_IRQ RK30_PIN0_PB3
-#else
-#define TPS65910_HOST_IRQ RK30_PIN6_PA4
-#endif
-
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info tps65910_dcdc_info[] = {
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "vdd2", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vio", //vcc_io
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
-
-};
-static struct pmu_info tps65910_ldo_info[] = {
- {
- .name = "vpll", //vcc25
- .min_uv = 2500000,
- .max_uv = 2500000,
- },
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "vdig2", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "vaux1", //vcc25_hdmi
- .min_uv = 2500000,
- .max_uv = 2500000,
- },
- {
- .name = "vaux2", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vaux33", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vmmc", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "vdac", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- };
-
-#include "board-pmu-tps65910.c"
-#endif
-
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_MFD_WM831X_I2C)
- {
- .type = "wm8326",
- .addr = 0x34,
- .flags = 0,
- .irq = RK30_PIN0_PB3,
- .platform_data = &wm831x_platdata,
- },
-#endif
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-};
-#endif
-
-void __sramfunc board_pmu_suspend(void)
-{
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_suspend();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_suspend();
- #endif
-}
-
-void __sramfunc board_pmu_resume(void)
-{
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_resume();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_resume();
- #endif
-}
-
- int __sramdata gpio0d7_iomux,gpio0d7_do,gpio0d7_dir,gpio0d7_en;
-
-#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
-
-void __sramfunc rk30_pwm_logic_suspend_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
-
-// int gpio0d7_iomux,gpio0d7_do,gpio0d7_dir,gpio0d7_en;
- sram_udelay(10000);
- gpio0d7_iomux = grf_readl(GRF_GPIO0D_IOMUX);
- gpio0d7_do = grf_readl(GRF_GPIO0H_DO);
- gpio0d7_dir = grf_readl(GRF_GPIO0H_DIR);
- gpio0d7_en = grf_readl(GRF_GPIO0H_EN);
-
- grf_writel((1<<30), GRF_GPIO0D_IOMUX);
- grf_writel((1<<31)|(1<<15), GRF_GPIO0H_DIR);
- grf_writel((1<<31)|(1<<15), GRF_GPIO0H_DO);
- grf_writel((1<<31)|(1<<15), GRF_GPIO0H_EN);
-#endif
-}
-void __sramfunc rk30_pwm_logic_resume_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- grf_writel((1<<30)|gpio0d7_iomux, GRF_GPIO0D_IOMUX);
- grf_writel((1<<31)|gpio0d7_en, GRF_GPIO0H_EN);
- grf_writel((1<<31)|gpio0d7_dir, GRF_GPIO0H_DIR);
- grf_writel((1<<31)|gpio0d7_do, GRF_GPIO0H_DO);
- sram_udelay(10000);
-
-#endif
-
-}
-extern void pwm_suspend_voltage(void);
-extern void pwm_resume_voltage(void);
-void rk30_pwm_suspend_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_suspend_voltage();
-#endif
-}
-void rk30_pwm_resume_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_resume_voltage();
-#endif
-}
-
-
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-#if defined (CONFIG_TOUCHSCREEN_GT8XX)
- {
- .type = "Goodix-TS",
- .addr = 0x55,
- .flags = 0,
- .irq = RK30_PIN0_PD4,
- .platform_data = &goodix_info,
- },
-#endif
-#if defined (CONFIG_TOUCHSCREEN_FT5306_AV)
- {
- .type = "ft5x0x_ts",
- .addr = 0x38,
- .flags = 0,
- .irq = RK30_PIN0_PD4,
- .platform_data = &ft5306_info,
- },
-#endif
-#if defined (CONFIG_LS_CM3217)
- {
- .type = "lightsensor",
- .addr = 0x10,
- .flags = 0,
- .platform_data = &cm3217_info,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C4_RK30
-static struct i2c_board_info __initdata i2c4_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO// RK30_PIN2_PD6 //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO//RK30_PIN2_PD7 //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- //set iomux (gpio) here
- //rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME, GPIO2D_GPIO2D7);
- //rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME, GPIO2D_GPIO2D6);
-
- return 0;
-}
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C4_RK30
- i2c_register_board_info(4, i2c4_info, ARRAY_SIZE(i2c4_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(5, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-
-#define POWER_ON_PIN RK30_PIN0_PA0 //power_hold
-#define DC_DET_PIN RK30_PIN0_PB2
-#define DC_DET_LEVEL GPIO_LOW
-
-extern void machine_restart(char *cmd);
-
-static void rk30_pm_power_off(void)
-{
-#if !(defined(CONFIG_MFD_TPS65910))
- if (gpio_get_value(DC_DET_PIN) == DC_DET_LEVEL) {
- printk("AC Charging, try to restart...\n");
- machine_restart(NULL);
- return ;
- }
-#endif
-
- printk("rk30_pm_power_off start...\n");
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
-#if defined(CONFIG_MFD_WM831X)
- wm831x_set_bits(Wm831x,WM831X_GPIO_LEVEL,0x0001,0x0000); //set sys_pwr 0
- wm831x_device_shutdown(Wm831x);//wm8326 shutdown
-#endif
-#if defined(CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- {
- tps65910_device_shutdown();//tps65910 shutdown
- }
-#endif
- while (1);
-}
-
-static void __init machine_rk30_board_init(void)
-{
- //avs_init();
- gpio_request(POWER_ON_PIN, "poweronpin");
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
- pm_power_off = rk30_pm_power_off;
-
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- board_usb_detect_init(RK30_PIN0_PA7);
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- rk29sdk_wifi_bt_gpio_control_init();
-#endif
-
- // spk and ear switch
- gpio_request(RK30_PIN2_PB1, NULL);
- gpio_direction_output(RK30_PIN2_PB1, GPIO_HIGH);
-}
-
-static void __init rk30_reserve(void)
-{
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0",get_fb_size());
- resource_fb[0].end = resource_fb[0].start + get_fb_size() - 1;
-#endif
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
- board_mem_reserved();
-}
-
-/**
- * dvfs_cpu_logic_table: table for arm and logic dvfs
- * @frequency : arm frequency
- * @cpu_volt : arm voltage depend on frequency
- * @logic_volt : logic voltage arm requests depend on frequency
- * comments : min arm/logic voltage
- */
-static struct dvfs_arm_table dvfs_cpu_logic_table[] = {
-#if 0
- {.frequency = 252 * 1000, .cpu_volt = 1075 * 1000, .logic_volt = 1125 * 1000},
-#endif
- {.frequency = 504 * 1000, .cpu_volt = 1100 * 1000, .logic_volt = 1100 * 1000},
- {.frequency = 816 * 1000, .cpu_volt = 1100 * 1000, .logic_volt = 1100 * 1000},
- {.frequency = 1200 * 1000, .cpu_volt = 1100 * 1000, .logic_volt = 1100 * 1000},
-#if 0
- {.frequency = 1008 * 1000, .cpu_volt = 1125 * 1000, .logic_volt = 1150 * 1000},
- {.frequency = 1272 * 1000, .cpu_volt = 1225 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 1416 * 1000, .cpu_volt = 1300 * 1000, .logic_volt = 1200 * 1000},
- {.frequency = 1512 * 1000, .cpu_volt = 1350 * 1000, .logic_volt = 1250 * 1000},
- {.frequency = 1608 * 1000, .cpu_volt = 1425 * 1000, .logic_volt = 1300 * 1000},
-#endif
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- {.frequency = 266 * 1000, .index = 1000 * 1000},
- {.frequency = 400 * 1000, .index = 1000 * 1000},
- {.frequency = 600 * 1000, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 300 * 1000, .index = 1000 * 1000},
- {.frequency = 400 * 1000, .index = 1000 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
-static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
-static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
-
-void __init board_clock_init(void)
-{
- rk30_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
- dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
-}
-
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk30_fixup,
- .reserve = &rk30_reserve,
- .map_io = rk30_map_io,
- .init_irq = rk30_init_irq,
- .timer = &rk30_timer,
- .init_machine = machine_rk30_board_init,
-MACHINE_END
+++ /dev/null
-#ifdef CONFIG_VIDEO_RK29
-#include <plat/rk_camera.h>
-/* Notes:
-
-Simple camera device registration:
-
- new_camera_device(sensor_name,\ // sensor name, it is equal to CONFIG_SENSOR_X
- face,\ // sensor face information, it can be back or front
- pwdn_io,\ // power down gpio configuration, it is equal to CONFIG_SENSOR_POWERDN_PIN_XX
- flash_attach,\ // sensor is attach flash or not
- mir,\ // sensor image mirror and flip control information
- i2c_chl,\ // i2c channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_IIC_ADAPTER_ID_X
- cif_chl) \ // cif channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_CIF_INDEX_X
-
-Comprehensive camera device registration:
-
- new_camera_device_ex(sensor_name,\
- face,\
- ori,\ // sensor orientation, it is equal to CONFIG_SENSOR_ORIENTATION_X
- pwr_io,\ // sensor power gpio configuration, it is equal to CONFIG_SENSOR_POWER_PIN_XX
- pwr_active,\ // sensor power active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- rst_io,\ // sensor reset gpio configuration, it is equal to CONFIG_SENSOR_RESET_PIN_XX
- rst_active,\ // sensor reset active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- pwdn_io,\
- pwdn_active,\ // sensor power down active level, is equal to CONFIG_SENSOR_POWERDNACTIVE_LEVEL_X
- flash_attach,\
- res,\ // sensor resolution, this is real resolution or resoltuion after interpolate
- mir,\
- i2c_chl,\
- i2c_spd,\ // i2c speed , 100000 = 100KHz
- i2c_addr,\ // the i2c slave device address for sensor
- cif_chl,\
- mclk)\ // sensor input clock rate, 24 or 48
-
-*/
-static struct rkcamera_platform_data new_camera[] = {
- new_camera_device(RK29_CAM_SENSOR_OV2659,
- front,
- RK30_PIN2_PC7,
- 0,
- 0,
- 3,
- 0),
- new_camera_device_end
-};
-
-/*---------------- Camera Sensor Macro Define Begin ------------------------*/
-/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
-#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_OV5642 /* back camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_0 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 4
-#define CONFIG_SENSOR_ORIENTATION_0 90
-#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 RK30_PIN1_PD6
-#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000
-
-#define CONFIG_SENSOR_01 RK29_CAM_SENSOR_OV5642 /* back camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_01 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 4
-#define CONFIG_SENSOR_ORIENTATION_01 90
-#define CONFIG_SENSOR_POWER_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_01 RK30_PIN1_PD6
-#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_01 30000
-
-#define CONFIG_SENSOR_02 RK29_CAM_SENSOR_OV5640 /* back camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_02 0x00
-#define CONFIG_SENSOR_CIF_INDEX_02 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 4
-#define CONFIG_SENSOR_ORIENTATION_02 90
-#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000
-
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_OV2659 /* front camera sensor 0 */
-#define CONFIG_SENSOR_IIC_ADDR_1 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 3
-#define CONFIG_SENSOR_ORIENTATION_1 270
-#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_1 RK30_PIN2_PC7
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000
-
-#define CONFIG_SENSOR_11 RK29_CAM_SENSOR_OV2659 /* front camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_11 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 3
-#define CONFIG_SENSOR_ORIENTATION_11 270
-#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_11 INVALID_GPIO//RK30_PIN1_PB7
-#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_11 30000
-
-#define CONFIG_SENSOR_12 RK29_CAM_SENSOR_OV2659//RK29_CAM_SENSOR_OV2655 /* front camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_12 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 3
-#define CONFIG_SENSOR_ORIENTATION_12 270
-#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_12 INVALID_GPIO//RK30_PIN1_PB7
-#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_12 30000
-
-
-#endif //#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk30_camera.c"
-/*---------------- Camera Sensor Macro Define End ---------*/
-
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#define CONFIG_SENSOR_POWER_IOCTL_USR 1 //define this refer to your board layout
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
-
-static void rk_cif_power(struct rk29camera_gpio_res *res,int on)
-{
- struct regulator *ldo_18,*ldo_28;
- int camera_power = res->gpio_power;
- int camera_ioflag = res->gpio_flag;
- int camera_io_init = res->gpio_init;
-
- ldo_28 = regulator_get(NULL, "ldo7"); // vcc28_cif
- ldo_18 = regulator_get(NULL, "ldo1"); // vcc18_cif
- if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){
- printk("get cif ldo failed!\n");
- return;
- }
- if(on == 0){
- while(regulator_is_enabled(ldo_28)>0)
- regulator_disable(ldo_28);
- regulator_put(ldo_28);
- while(regulator_is_enabled(ldo_18)>0)
- regulator_disable(ldo_18);
- regulator_put(ldo_18);
- mdelay(10);
- if (camera_power != INVALID_GPIO) {
- if (camera_io_init & RK29_CAM_POWERACTIVE_MASK) {
- gpio_set_value(camera_power, (((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
- // dprintk("%s..%s..PowerPin=%d ..PinLevel = %x \n",__FUNCTION__,res->dev_name, camera_power, (((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
- }
- }
- }
- else{
- regulator_set_voltage(ldo_28, 2800000, 2800000);
- regulator_enable(ldo_28);
- // printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
- regulator_put(ldo_28);
-
- regulator_set_voltage(ldo_18, 1800000, 1800000);
- // regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(ldo_18);
- // printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
- regulator_put(ldo_18);
- if (camera_power != INVALID_GPIO) {
- if (camera_io_init & RK29_CAM_POWERACTIVE_MASK) {
- gpio_set_value(camera_power, ((camera_ioflag&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
- //dprintk("%s..%s..PowerPin=%d ..PinLevel = %x \n",__FUNCTION__,res->dev_name, camera_power, ((camera_ioflag&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
- mdelay(10);
- }
- }
-
- }
-}
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- //#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
- rk_cif_power(res,on);
- return 0;
-}
-#endif
-
-#if CONFIG_SENSOR_RESET_IOCTL_USR
-static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
-static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-
-#if CONFIG_SENSOR_IIC_ADDR_0
-static struct reginfo_t rk_init_data_sensor_reg_0[] =
-{
- {0x0000, 0x00,0,0}
- };
-static struct reginfo_t rk_init_data_sensor_winseqreg_0[] ={
- {0x0000, 0x00,0,0}
- };
-#endif
-
-#if CONFIG_SENSOR_IIC_ADDR_1
-static struct reginfo_t rk_init_data_sensor_reg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_01
-static struct reginfo_t rk_init_data_sensor_reg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_02
-static struct reginfo_t rk_init_data_sensor_reg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_11
-static struct reginfo_t rk_init_data_sensor_reg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_12
-static struct reginfo_t rk_init_data_sensor_reg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] =
-{
- #if CONFIG_SENSOR_IIC_ADDR_0
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_0,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_1
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_1,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_01
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_01,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_02
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_02,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_11
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_11,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_12
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_12,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
-
- };
-#include "../../../drivers/media/video/rk30_camera.c"
-
-#endif /* CONFIG_VIDEO_RK29 */
+++ /dev/null
-#include <mach/gpio.h>
-#include <plat/key.h>
-
-#define EV_ENCALL KEY_F4
-#define EV_MENU KEY_F1
-
-#define PRESS_LEV_LOW 1
-#define PRESS_LEV_HIGH 0
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .gpio = RK30_PIN0_PB5,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK30_PIN0_PA4,
- .active_low = PRESS_LEV_LOW,
- .wakeup = 1,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .adc_value = 1,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "menu",
- .code = EV_MENU,
- .adc_value = 133,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .adc_value = 550,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .adc_value = 333,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "camera",
- .code = KEY_CAMERA,
- .adc_value = 742,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = 1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
+++ /dev/null
-/*
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <mach/dvfs.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <linux/fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/mfd/tps65910.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-
-#if defined(CONFIG_MFD_RK610)
-#include <linux/mfd/rk610_core.h>
-#endif
-
-#if defined(CONFIG_RK_HDMI)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-#if defined(CONFIG_GPS_RK)
-#include "../../../drivers/misc/gps/rk_gps/rk_gps.h"
-#endif
-
-#if defined(CONFIG_MU509)
-#include <linux/mu509.h>
-#endif
-#if defined(CONFIG_MW100)
-#include <linux/mw100.h>
-#endif
-#if defined(CONFIG_MT6229)
-#include <linux/mt6229.h>
-#endif
-#if defined(CONFIG_ANDROID_TIMED_GPIO)
-#include "../../../drivers/staging/android/timed_gpio.h"
-#endif
-
-#ifdef CONFIG_THREE_FB_BUFFER
-#define RK30_FB0_MEM_SIZE 12*SZ_1M
-#else
-#define RK30_FB0_MEM_SIZE 8*SZ_1M
-#endif
-
-#include "board-rk3066b-sdk-camera.c"
-#include "board-rk3066b-sdk-key.c"
-
-#if defined(CONFIG_TOUCHSCREEN_GT8XX)
-#define TOUCH_RESET_PIN RK30_PIN2_PC0
-#define TOUCH_PWR_PIN RK30_PIN2_PB4
-static int goodix_init_platform_hw(void)
-{
- int ret;
-
- if (TOUCH_PWR_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_PWR_PIN, "goodix power pin");
- if (ret != 0) {
- gpio_free(TOUCH_PWR_PIN);
- printk("goodix power error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_PWR_PIN, 0);
- gpio_set_value(TOUCH_PWR_PIN, GPIO_LOW);
- msleep(100);
- }
-
- if (TOUCH_RESET_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_RESET_PIN, "goodix reset pin");
- if (ret != 0) {
- gpio_free(TOUCH_RESET_PIN);
- printk("goodix gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, 1);
- msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_LOW);
- //msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_HIGH);
- //msleep(500);
- }
- return 0;
-}
-
-struct goodix_platform_data goodix_info = {
- .model = 8105,
- .irq_pin = RK30_PIN0_PD4,
- .rest_pin = TOUCH_RESET_PIN,
- .init_platform_hw = goodix_init_platform_hw,
-};
-#endif
-
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-#define PWM_ID 2
-#define PWM_MODE PWM2
-#define PWM_EFFECT_VALUE 1
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-#define BL_EN_PIN RK30_PIN0_PA2
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
-
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
- ret = gpio_request(BL_EN_PIN, "bl_en");
- if (ret == 0) {
- gpio_direction_output(BL_EN_PIN, BL_EN_VALUE);
- }
-#endif
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0, pwm_gpio;
-#ifdef LCD_DISP_ON_PIN
- gpio_free(BL_EN_PIN);
-#endif
- pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
- gpio_request(pwm_gpio, "bl_pwm");
- gpio_direction_input(pwm_gpio);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret, pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
-
- ret = gpio_request(pwm_gpio, "bl_pwm");
- if (ret) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return ret;
- }
- gpio_direction_input(pwm_gpio);
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, !BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- int pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
-
- gpio_free(pwm_gpio);
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-#endif
-
-#ifdef CONFIG_RK29_SUPPORT_MODEM
-
-#define RK30_MODEM_POWER RK30_PIN2_PB0
-#define RK30_MODEM_POWER_IOMUX rk29_mux_api_set(GPIO2B0_LCDC1DATA8_SMCDATA8_TRACEDATA8_NAME, GPIO2B_GPIO2B0)
-
-static int rk30_modem_io_init(void)
-{
- printk("%s\n", __FUNCTION__);
- RK30_MODEM_POWER_IOMUX;
-
- return 0;
-}
-
-static struct rk29_io_t rk30_modem_io = {
- .io_addr = RK30_MODEM_POWER,
- .enable = GPIO_HIGH,
- .disable = GPIO_LOW,
- .io_init = rk30_modem_io_init,
-};
-
-static struct platform_device rk30_device_modem = {
- .name = "rk30_modem",
- .id = -1,
- .dev = {
- .platform_data = &rk30_modem_io,
- }
-};
-#endif
-#if defined(CONFIG_MU509)
-static int mu509_io_init(void)
-{
-
- rk30_mux_api_set(GPIO2B0_LCDC1DATA8_SMCDATA8_TRACEDATA8_NAME, GPIO2B_GPIO2B0);
- rk30_mux_api_set(GPIO2D1_LCDC1DEN_SMCWEN_NAME, GPIO2D_GPIO2D1);
- rk30_mux_api_set(GPIO2B7_LCDC1DATA15_SMCADDR19_HSADCDATA7_NAME, GPIO2B_GPIO2B7);
- rk30_mux_api_set(GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME, GPIO2C_GPIO2C0);
- return 0;
-}
-
-static int mu509_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mu509_data rk29_mu509_info = {
- .io_init = mu509_io_init,
- .io_deinit = mu509_io_deinit,
- .modem_power_en = RK30_PIN2_PB0,
- .bp_power = RK30_PIN2_PB0,
- .bp_reset = RK30_PIN2_PD1,
- .ap_wakeup_bp = RK30_PIN2_PB7,
- .bp_wakeup_ap = RK30_PIN6_PA0,
-};
-struct platform_device rk29_device_mu509 = {
- .name = "mu509",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mu509_info,
- }
- };
-#endif
-#if defined(CONFIG_MW100)
-static int mw100_io_init(void)
-{
- rk30_mux_api_set(GPIO2B0_LCDC1DATA8_SMCDATA8_TRACEDATA8_NAME, GPIO2B_GPIO2B0);
- rk30_mux_api_set(GPIO2D1_LCDC1DEN_SMCWEN_NAME, GPIO2D_GPIO2D1);
- rk30_mux_api_set(GPIO2B7_LCDC1DATA15_SMCADDR19_HSADCDATA7_NAME, GPIO2B_GPIO2B7);
- rk30_mux_api_set(GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME, GPIO2C_GPIO2C0);
- return 0;
-}
-
-static int mw100_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mw100_data rk29_mw100_info = {
- .io_init = mw100_io_init,
- .io_deinit = mw100_io_deinit,
- .modem_power_en = RK30_PIN6_PB0,
- .bp_power = RK30_PIN2_PB0,
- .bp_reset = RK30_PIN2_PD1,
- .ap_wakeup_bp = RK30_PIN2_PB7,
- .bp_wakeup_ap = RK30_PIN6_PA0,
-};
-struct platform_device rk29_device_mw100 = {
- .name = "mw100",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mw100_info,
- }
- };
-#endif
-#if defined(CONFIG_MT6229)
-static int mt6229_io_init(void)
-{
- rk30_mux_api_set(GPIO2B0_LCDC1DATA8_SMCDATA8_TRACEDATA8_NAME, GPIO2B_GPIO2B0);
- rk30_mux_api_set(GPIO2D1_LCDC1DEN_SMCWEN_NAME, GPIO2D_GPIO2D1);
- rk30_mux_api_set(GPIO2B7_LCDC1DATA15_SMCADDR19_HSADCDATA7_NAME, GPIO2B_GPIO2B7);
- rk30_mux_api_set(GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME, GPIO2C_GPIO2C0);
- return 0;
-}
-
-static int mt6229_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mt6229_data rk29_mt6229_info = {
- .io_init = mt6229_io_init,
- .io_deinit = mt6229_io_deinit,
- .modem_power_en = RK30_PIN2_PB0,
- .bp_power = RK30_PIN2_PB0,//RK30_PIN2_PB6,
- .bp_reset = RK30_PIN2_PD1,
- .ap_wakeup_bp = RK30_PIN2_PC0,
- .bp_wakeup_ap = RK30_PIN6_PA0,
-};
-struct platform_device rk29_device_mt6229 = {
- .name = "mt6229",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mt6229_info,
- }
- };
-#endif
-
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN RK30_PIN3_PD7
-
-static int mma8452_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data mma8452_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma8452_init_platform_hw,
- .orientation = {-1, 0, 0, 0, 0, 1, 0, -1, 0},
-};
-#endif
-#if defined (CONFIG_GS_LIS3DH)
-#define LIS3DH_INT_PIN RK30_PIN3_PD7
-
-static int lis3dh_init_platform_hw(void)
-{
-
- return 0;
-}
-
-static struct sensor_platform_data lis3dh_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lis3dh_init_platform_hw,
- .orientation = {-1, 0, 0, 0, 0, 1, 0, -1, 0},
-};
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
-static struct sensor_platform_data akm8975_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-#if defined(CONFIG_GYRO_L3G4200D)
-
-#include <linux/l3g4200d.h>
-#define L3G4200D_INT_PIN RK30_PIN0_PB4
-
-static int l3g4200d_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data l3g4200d_info = {
- .type = SENSOR_TYPE_GYROSCOPE,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
- .init_platform_hw = l3g4200d_init_platform_hw,
- .x_min = 40,//x_min,y_min,z_min = (0-100) according to hardware
- .y_min = 40,
- .z_min = 20,
-};
-
-#endif
-
-#ifdef CONFIG_LS_CM3217
-static struct sensor_platform_data cm3217_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 0,
- .poll_delay_ms = 500,
-};
-
-#endif
-
-#ifdef CONFIG_FB_ROCKCHIP
-
-#define LCD_CS_PIN INVALID_GPIO
-#define LCD_CS_VALUE GPIO_HIGH
-
-#define LCD_EN_PIN RK30_PIN0_PB0
-#define LCD_EN_VALUE GPIO_HIGH
-
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
-
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_CS_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_CS_PIN);
- printk(KERN_ERR "request lcd cs pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_CS_PIN, LCD_CS_VALUE);
- }
- }
-
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_EN_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_EN_PIN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_EN_PIN, LCD_EN_VALUE);
- }
- }
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, !LCD_CS_VALUE);
- }
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, !LCD_EN_VALUE);
- }
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE);
- }
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
- }
- return 0;
-}
-
-#if defined(CONFIG_LCDC0_RK3066B)
-struct rk29fb_info lcdc0_screen_info = {
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B)
-struct rk29fb_info lcdc1_screen_info = {
- #if defined(CONFIG_RK_HDMI)
- .prop = EXTEND, //extend display device
- .lcd_info = NULL,
- .set_screen_info = hdmi_init_lcdc,
- #endif
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B)
-static struct resource resource_lcdc0[] = {
- [0] = {
- .name = "lcdc0 reg",
- .start = RK30_LCDC0_PHYS,
- .end = RK30_LCDC0_PHYS + RK30_LCDC0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc0 irq",
- .start = IRQ_LCDC0,
- .end = IRQ_LCDC0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc0 = {
- .name = "rk30-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc0),
- .resource = resource_lcdc0,
- .dev = {
- .platform_data = &lcdc0_screen_info,
- },
-};
-#endif
-#if defined(CONFIG_LCDC1_RK3066B)
-static struct resource resource_lcdc1[] = {
- [0] = {
- .name = "lcdc1 reg",
- .start = RK30_LCDC1_PHYS,
- .end = RK30_LCDC1_PHYS + RK30_LCDC1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc1 irq",
- .start = IRQ_LCDC1,
- .end = IRQ_LCDC1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc1 = {
- .name = "rk30-lcdc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resource_lcdc1),
- .resource = resource_lcdc1,
- .dev = {
- .platform_data = &lcdc1_screen_info,
- },
-};
-#endif
-
-#if defined(CONFIG_MFD_RK610)
-#if 1
-#define RK610_RST_PIN_MUX_NAME GPIO2C5_LCDC1DATA21_SMCADDR5_NAME
-#define RK610_RST_PIN_MUX_MODE GPIO2C_GPIO2C5
-#define RK610_RST_PIN RK30_PIN2_PC5
-#else
-#define RK610_RST_PIN_MUX_NAME GPIO2D6_SMCCSN1_NAME
-#define RK610_RST_PIN_MUX_MODE GPIO2D_GPIO2D6
-#define RK610_RST_PIN RK30_PIN2_PD6
-
-#endif
-static int rk610_power_on_init(void)
-{
- int ret;
- if(RK610_RST_PIN != INVALID_GPIO)
- {
- ret = gpio_request(RK610_RST_PIN, "rk610 reset");
- if (ret)
- {
- printk(KERN_ERR "rk610_control_probe request gpio fail\n");
- }
- else
- {
- gpio_direction_output(RK610_RST_PIN, GPIO_HIGH);
- msleep(100);
- gpio_direction_output(RK610_RST_PIN, GPIO_LOW);
- msleep(100);
- gpio_set_value(RK610_RST_PIN, GPIO_HIGH);
- }
- }
-
- return 0;
-
-}
-
-
-static struct rk610_ctl_platform_data rk610_ctl_pdata = {
- .rk610_power_on_init = rk610_power_on_init,
-};
-#endif
-#ifdef CONFIG_SND_SOC_RK610
-static int rk610_codec_io_init(void)
-{
-//if need iomux.
-//Must not gpio_request
- return 0;
-}
-
-static struct rk610_codec_platform_data rk610_codec_pdata = {
- .spk_ctl_io = RK30_PIN2_PA0,
- .io_init = rk610_codec_io_init,
-};
-#endif
-
-#ifdef CONFIG_ANDROID_TIMED_GPIO
-static struct timed_gpio timed_gpios[] = {
- {
- .name = "vibrator",
- .gpio = RK30_PIN3_PD3,
- .max_timeout = 1000,
- .active_low = 0,
- .adjust_time =20, //adjust for diff product
- },
-};
-
-static struct timed_gpio_platform_data rk29_vibrator_info = {
- .num_gpios = 1,
- .gpios = timed_gpios,
-};
-
-static struct platform_device rk29_device_vibrator = {
- .name = "timed-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_vibrator_info,
- },
-
-};
-#endif
-
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
-static struct gpio_led rk29_leds[] = {
- {
- .name = "button-backlight",
- .gpio = RK30_PIN2_PB3,
- .default_trigger = "timer",
- .active_low = 0,
- .retain_state_suspended = 0,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- },
-};
-
-static struct gpio_led_platform_data rk29_leds_pdata = {
- .leds = rk29_leds,
- .num_leds = ARRAY_SIZE(rk29_leds),
-};
-
-static struct platform_device rk29_device_gpio_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_leds_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_RK_IRDA
-#define IRDA_IRQ_PIN RK30_PIN0_PA3
-
-static int irda_iomux_init(void)
-{
- int ret = 0;
-
- //irda irq pin
- ret = gpio_request(IRDA_IRQ_PIN, NULL);
- if (ret != 0) {
- gpio_free(IRDA_IRQ_PIN);
- printk(">>>>>> IRDA_IRQ_PIN gpio_request err \n ");
- }
- gpio_pull_updown(IRDA_IRQ_PIN, PullDisable);
- gpio_direction_input(IRDA_IRQ_PIN);
-
- return 0;
-}
-
-static int irda_iomux_deinit(void)
-{
- gpio_free(IRDA_IRQ_PIN);
- return 0;
-}
-
-static struct irda_info rk29_irda_info = {
- .intr_pin = IRDA_IRQ_PIN,
- .iomux_init = irda_iomux_init,
- .iomux_deinit = irda_iomux_deinit,
- //.irda_pwr_ctl = bu92747guw_power_ctl,
-};
-
-static struct platform_device irda_device = {
-#ifdef CONFIG_RK_IRDA_NET
- .name = "rk_irda",
-#else
- .name = "bu92747_irda",
-#endif
- .id = -1,
- .dev = {
- .platform_data = &rk29_irda_info,
- }
-};
-#endif
-
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and SDIO.noted by xbw at 2012-03-05
-**************************************************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "board-rk30-sdk-sdmmc.c"
-#endif
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- rk30_mux_api_set(GPIO3B1_SDMMC0CMD_NAME, GPIO3B_SDMMC0_CMD);
- rk30_mux_api_set(GPIO3B0_SDMMC0CLKOUT_NAME, GPIO3B_SDMMC0_CLKOUT);
- rk30_mux_api_set(GPIO3B2_SDMMC0DATA0_NAME, GPIO3B_SDMMC0_DATA0);
- rk30_mux_api_set(GPIO3B3_SDMMC0DATA1_NAME, GPIO3B_SDMMC0_DATA1);
- rk30_mux_api_set(GPIO3B4_SDMMC0DATA2_NAME, GPIO3B_SDMMC0_DATA2);
- rk30_mux_api_set(GPIO3B5_SDMMC0DATA3_NAME, GPIO3B_SDMMC0_DATA3);
-
- rk30_mux_api_set(GPIO3B6_SDMMC0DETECTN_NAME, GPIO3B_GPIO3B6);
-
- rk30_mux_api_set(GPIO3A7_SDMMC0PWREN_NAME, GPIO3A_GPIO3A7);
- gpio_request(RK30_PIN3_PA7, "sdmmc-power");
- gpio_direction_output(RK30_PIN3_PA7, GPIO_LOW);
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- #if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- iomux_set_gpio_mode(iomux_mode_to_gpio(MMC0_DETN));
- #else
- iomux_set(MMC0_DETN);
- #endif
-
- #if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
- #endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) && defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- .status = rk29sdk_wifi_mmc0_status,
- .register_status_notify = rk29sdk_wifi_mmc0_status_register,
-#endif
-
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .power_en = RK29SDK_SD_CARD_PWR_EN,
- .power_en_level = RK29SDK_SD_CARD_PWR_EN_LEVEL,
-#else
- .power_en = INVALID_GPIO,
- .power_en_level = GPIO_LOW,
-#endif
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC0_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- .det_pin_info = {
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N, //INVALID_GPIO,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
- #endif
- },
-
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- rk30_mux_api_set(GPIO3C0_SMMC1CMD_NAME, GPIO3C_SMMC1_CMD);
- rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_NAME, GPIO3C_SDMMC1_CLKOUT);
- rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_NAME, GPIO3C_SDMMC1_DATA0);
- rk30_mux_api_set(GPIO3C2_SDMMC1DATA1_NAME, GPIO3C_SDMMC1_DATA1);
- rk30_mux_api_set(GPIO3C3_SDMMC1DATA2_NAME, GPIO3C_SDMMC1_DATA2);
- rk30_mux_api_set(GPIO3C4_SDMMC1DATA3_NAME, GPIO3C_SDMMC1_DATA3);
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC) || defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-
- #if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC1_WRITE_PROTECT_ENABLE_VALUE;
- #else
- .write_prt = INVALID_GPIO,
- #endif
-
- #if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
- .sdio_INT_gpio = RK29SDK_WIFI_SDIO_CARD_INT,
- #endif
-
- .det_pin_info = {
-#if defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- #else
- .io = INVALID_GPIO,
- #endif
-
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-
- .enable_sd_wakeup = 0,
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-/**************************************************************************************************
- * the end of setting for SDMMC devices
-**************************************************************************************************/
-
-#ifdef CONFIG_BATTERY_RK30_ADC
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = RK30_PIN0_PB2,
- .batt_low_pin = RK30_PIN0_PB1,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = RK30_PIN0_PA6,
- .dc_det_level = GPIO_LOW,
- .charge_ok_level = GPIO_HIGH,
-};
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-#ifdef CONFIG_RK30_PWM_REGULATOR
-const static int pwm_voltage_map[] = {
- 950000, 975000,1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000, 1375000, 1400000
-};
-
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_core",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] =
-{
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
- .pwm_id = 3,
- .pwm_gpio = RK30_PIN3_PD6,
- .pwm_iomux_pwm = PWM3,
- .pwm_iomux_gpio = GPIO3_D6,
- .pwm_voltage = 1100000,
- .suspend_voltage = 1050000,
- .min_uV = 950000,
- .max_uV = 1400000,
- .coefficient = 455, //45.5%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-#endif
-
-#ifdef CONFIG_RK29_VMAC
-#define PHY_PWR_EN_GPIO RK30_PIN1_PD6
-#include "board-rk30-sdk-vmac.c"
-#endif
-
-#ifdef CONFIG_RFKILL_RK
-// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
-static struct rfkill_rk_platform_data rfkill_rk_platdata = {
- .type = RFKILL_TYPE_BLUETOOTH,
-
- .poweron_gpio = { // BT_REG_ON
- .io = INVALID_GPIO, //RK30_PIN3_PC7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_poweron",
- .fgpio = GPIO3_C7,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN3_PD1, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_reset",
- .fgpio = GPIO3_D1,
- },
- },
-
- .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
- .io = RK30_PIN3_PC6, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_wake",
- .fgpio = GPIO3_C6,
- },
- },
-
- .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .gpio = {
- .io = RK30_PIN0_PA5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
- .iomux = {
- .name = NULL,
- },
- },
- },
-
- .rts_gpio = { // UART_RTS, enable or disable BT's data coming
- .io = RK30_PIN1_PA3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_rts",
- .fgpio = GPIO1_A3,
- .fmux = UART0_RTSN,
- },
- },
-};
-
-static struct platform_device device_rfkill_rk = {
- .name = "rfkill_rk",
- .id = -1,
- .dev = {
- .platform_data = &rfkill_rk_platdata,
- },
-};
-#endif
-
-#if defined(CONFIG_GPS_RK)
-int rk_gps_io_init(void)
-{
- printk("%s \n", __FUNCTION__);
-
- gpio_request(RK30_PIN1_PB5, NULL);
- gpio_direction_output(RK30_PIN1_PB5, GPIO_LOW);
-
- iomux_set(GPS_RFCLK);//GPS_CLK
- iomux_set(GPS_MAG);//GPS_MAG
- iomux_set(GPS_SIG);//GPS_SIGN
-
- gpio_request(RK30_PIN1_PA6, NULL);
- gpio_direction_output(RK30_PIN1_PA6, GPIO_LOW);
-
- gpio_request(RK30_PIN1_PA5, NULL);
- gpio_direction_output(RK30_PIN1_PA5, GPIO_LOW);
-
- gpio_request(RK30_PIN1_PA7, NULL);
- gpio_direction_output(RK30_PIN1_PA7, GPIO_LOW);
- return 0;
-}
-int rk_gps_power_up(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_power_down(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_reset_set(int level)
-{
- return 0;
-}
-int rk_enable_hclk_gps(void)
-{
- printk("%s \n", __FUNCTION__);
- clk_enable(clk_get(NULL, "hclk_gps"));
- return 0;
-}
-int rk_disable_hclk_gps(void)
-{
- printk("%s \n", __FUNCTION__);
- clk_disable(clk_get(NULL, "hclk_gps"));
- return 0;
-}
-struct rk_gps_data rk_gps_info = {
- .io_init = rk_gps_io_init,
- .power_up = rk_gps_power_up,
- .power_down = rk_gps_power_down,
- .reset = rk_gps_reset_set,
- .enable_hclk_gps = rk_enable_hclk_gps,
- .disable_hclk_gps = rk_disable_hclk_gps,
- .GpsSign = RK30_PIN1_PB3,
- .GpsMag = RK30_PIN1_PB2, //GPIO index
- .GpsClk = RK30_PIN1_PB4, //GPIO index
- .GpsVCCEn = RK30_PIN1_PB5, //GPIO index
- .GpsSpi_CSO = RK30_PIN1_PA4, //GPIO index
- .GpsSpiClk = RK30_PIN1_PA5, //GPIO index
- .GpsSpiMOSI = RK30_PIN1_PA7, //GPIO index
- .GpsIrq = IRQ_GPS,
- .GpsSpiEn = 0,
- .GpsAdcCh = 2,
- .u32GpsPhyAddr = RK30_GPS_PHYS,
- .u32GpsPhySize = RK30_GPS_SIZE,
-};
-
-struct platform_device rk_device_gps = {
- .name = "gps_hv5820b",
- .id = -1,
- .dev = {
- .platform_data = &rk_gps_info,
- }
- };
-#endif
-
-
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_FB_ROCKCHIP
- &device_fb,
-#endif
-#if defined(CONFIG_LCDC0_RK3066B)
- &device_lcdc0,
-#endif
-#if defined(CONFIG_LCDC1_RK3066B)
- &device_lcdc1,
-#endif
-
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- &rk29_device_backlight,
-#endif
-
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_ANDROID_TIMED_GPIO
- &rk29_device_vibrator,
-#endif
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
- &rk29_device_gpio_leds,
-#endif
-#ifdef CONFIG_RK_IRDA
- &irda_device,
-#endif
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- &rk29sdk_wifi_device,
-#endif
-#ifdef CONFIG_RK29_SUPPORT_MODEM
- &rk30_device_modem,
-#endif
-#if defined(CONFIG_MU509)
- &rk29_device_mu509,
-#endif
-#if defined(CONFIG_MW100)
- &rk29_device_mw100,
-#endif
-#if defined(CONFIG_MT6229)
- &rk29_device_mt6229,
-#endif
-#ifdef CONFIG_BATTERY_RK30_ADC
- &rk30_device_adc_battery,
-#endif
-#ifdef CONFIG_RFKILL_RK
- &device_rfkill_rk,
-#endif
-#ifdef CONFIG_GPS_RK
- &rk_device_gps,
-#endif
-
-};
-
-// i2c
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1d,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_GS_LIS3DH)
- {
- .type = "gs_lis3dh",
- .addr = 0x19, //0x19(SA0-->VCC), 0x18(SA0-->GND)
- .flags = 0,
- .irq = LIS3DH_INT_PIN,
- .platform_data = &lis3dh_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN0_PD5,
- .platform_data = &akm8975_info,
- },
-#endif
-#if defined (CONFIG_GYRO_L3G4200D)
- {
- .type = "l3g4200d_gryo",
- .addr = 0x69,
- .flags = 0,
- .irq = L3G4200D_INT_PIN,
- .platform_data = &l3g4200d_info,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RT5631)
- {
- .type = "rt5631",
- .addr = 0x1a,
- .flags = 0,
- },
-#endif
-
-#ifdef CONFIG_MFD_RK610
- {
- .type = "rk610_ctl",
- .addr = 0x40,
- .flags = 0,
- .platform_data = &rk610_ctl_pdata,
- },
-#ifdef CONFIG_RK610_TVOUT
- {
- .type = "rk610_tvout",
- .addr = 0x42,
- .flags = 0,
- },
-#endif
-#ifdef CONFIG_HDMI_RK610
- {
- .type = "rk610_hdmi",
- .addr = 0x46,
- .flags = 0,
- .irq = INVALID_GPIO,
- },
-#endif
-#ifdef CONFIG_SND_SOC_RK610
- {//RK610_CODEC addr from 0x60 to 0x80 (0x60~0x80)
- .type = "rk610_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- .platform_data = &rk610_codec_pdata,
- },
-#endif
-#endif
-
-};
-#endif
-
-int __sramdata g_pmic_type = 0;
-#ifdef CONFIG_I2C1_RK30
-#ifdef CONFIG_MFD_WM831X_I2C
-
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info wm8326_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "dcdc3", //ddr
- .min_uv = 1150000,
- .max_uv = 1150000,
- .suspend_vol = 1150000,
- },
- #ifdef CONFIG_MACH_RK3066_SDK
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3100000,
- },
- #else
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3000000,
- .max_uv = 3000000,
- .suspend_vol = 2800000,
- },
- #endif
-};
-
-static struct pmu_info wm8326_ldo_info[] = {
- {
- .name = "ldo1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo2", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo3", //
- .min_uv = 1100000,
- .max_uv = 1100000,
- .suspend_vol = 1100000,
- },
- {
- .name = "ldo4", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 1000000,
- },
- {
- .name = "ldo5", //vcc25
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo6", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo7", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- .suspend_vol = 2800000,
- },
- {
- .name = "ldo8", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo9", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo10", //flash_io
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
-};
-
-#include "board-pmu-wm8326.c"
-#endif
-
-#ifdef CONFIG_MFD_TPS65910
-#ifdef CONFIG_ARCH_RK3066B
-#define TPS65910_HOST_IRQ RK30_PIN0_PB3
-#else
-#define TPS65910_HOST_IRQ RK30_PIN6_PA4
-#endif
-
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info tps65910_dcdc_info[] = {
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "vdd2", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vio", //vcc_io
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
-
-};
-static struct pmu_info tps65910_ldo_info[] = {
- {
- .name = "vpll", //vcc25
- .min_uv = 2500000,
- .max_uv = 2500000,
- },
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "vdig2", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "vaux1", //vcc25_hdmi
- .min_uv = 2500000,
- .max_uv = 2500000,
- },
- {
- .name = "vaux2", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vaux33", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vmmc", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "vdac", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- };
-
-#include "board-pmu-tps65910.c"
-#endif
-
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_MFD_WM831X_I2C)
- {
- .type = "wm8326",
- .addr = 0x34,
- .flags = 0,
- .irq = RK30_PIN0_PB3,
- .platform_data = &wm831x_platdata,
- },
-#endif
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-#if defined(CONFIG_HDMI_CAT66121)
- {
- .type = "cat66121_hdmi",
- .addr = 0x4c,
- .flags = 0,
- .irq = RK30_PIN1_PB7,
- },
-#endif
-};
-#endif
-
-void __sramfunc board_pmu_suspend(void)
-{
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_suspend();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_suspend();
- #endif
-}
-
-void __sramfunc board_pmu_resume(void)
-{
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_resume();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_resume();
- #endif
-}
-
-int __sramdata gpio3d6_iomux,gpio3d6_do,gpio3d6_dir,gpio3d6_en;
-
-#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
-
-void __sramfunc rk30_pwm_logic_suspend_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
-
-// int gpio0d7_iomux,gpio0d7_do,gpio0d7_dir,gpio0d7_en;
- sram_udelay(10000);
- gpio3d6_iomux = grf_readl(GRF_GPIO3D_IOMUX);
- gpio3d6_do = grf_readl(GRF_GPIO3H_DO);
- gpio3d6_dir = grf_readl(GRF_GPIO3H_DIR);
- gpio3d6_en = grf_readl(GRF_GPIO3H_EN);
-
- grf_writel((1<<28), GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DIR);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DO);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_EN);
-#endif
-}
-void __sramfunc rk30_pwm_logic_resume_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- grf_writel((1<<28)|gpio3d6_iomux, GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|gpio3d6_en, GRF_GPIO3H_EN);
- grf_writel((1<<30)|gpio3d6_dir, GRF_GPIO3H_DIR);
- grf_writel((1<<30)|gpio3d6_do, GRF_GPIO3H_DO);
- sram_udelay(10000);
-#endif
-}
-
-extern void pwm_suspend_voltage(void);
-extern void pwm_resume_voltage(void);
-void rk30_pwm_suspend_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_suspend_voltage();
-#endif
-}
-void rk30_pwm_resume_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_resume_voltage();
-#endif
-}
-
-
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-#if defined (CONFIG_TOUCHSCREEN_GT8XX)
- {
- .type = "Goodix-TS",
- .addr = 0x55,
- .flags = 0,
- .irq = RK30_PIN0_PD4,
- .platform_data = &goodix_info,
- },
-#endif
-#if defined (CONFIG_LS_CM3217)
- {
- .type = "lightsensor",
- .addr = 0x10,
- .flags = 0,
- .platform_data = &cm3217_info,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C4_RK30
-static struct i2c_board_info __initdata i2c4_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO// RK30_PIN2_PD6 //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO//RK30_PIN2_PD7 //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- //set iomux (gpio) here
- //rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME, GPIO2D_GPIO2D7);
- //rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME, GPIO2D_GPIO2D6);
-
- return 0;
-}
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C4_RK30
- i2c_register_board_info(4, i2c4_info, ARRAY_SIZE(i2c4_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(5, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-
-#define POWER_ON_PIN RK30_PIN0_PA0 //power_hold
-static void rk30_pm_power_off(void)
-{
- printk(KERN_ERR "rk30_pm_power_off start...\n");
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
-#if defined(CONFIG_MFD_WM831X)
- wm831x_set_bits(Wm831x,WM831X_GPIO_LEVEL,0x0001,0x0000); //set sys_pwr 0
- wm831x_device_shutdown(Wm831x);//wm8326 shutdown
-#endif
- while (1);
-}
-
-static void __init machine_rk30_board_init(void)
-{
- //avs_init();
- gpio_request(POWER_ON_PIN, "poweronpin");
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
- pm_power_off = rk30_pm_power_off;
-
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- board_usb_detect_init(RK30_PIN0_PA7);
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- rk29sdk_wifi_bt_gpio_control_init();
-#endif
-}
-
-static void __init rk30_reserve(void)
-{
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0", RK30_FB0_MEM_SIZE);
- resource_fb[0].end = resource_fb[0].start + RK30_FB0_MEM_SIZE - 1;
- #if 0
- resource_fb[1].start = board_mem_reserve_add("ipp buf", RK30_FB0_MEM_SIZE);
- resource_fb[1].end = resource_fb[1].start + RK30_FB0_MEM_SIZE - 1;
- resource_fb[2].start = board_mem_reserve_add("fb2", RK30_FB0_MEM_SIZE);
- resource_fb[2].end = resource_fb[2].start + RK30_FB0_MEM_SIZE - 1;
- #endif
-#endif
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
-
-#ifdef CONFIG_GPS_RK
- //it must be more than 8MB
- rk_gps_info.u32MemoryPhyAddr = board_mem_reserve_add("gps", SZ_8M);
-#endif
- board_mem_reserved();
-}
-
-/**
- * dvfs_cpu_logic_table: table for arm and logic dvfs
- * @frequency : arm frequency
- * @cpu_volt : arm voltage depend on frequency
- * @logic_volt : logic voltage arm requests depend on frequency
- * comments : min arm/logic voltage
- */
-static struct cpufreq_frequency_table dvfs_arm_table[] = {
- {.frequency = 312 * 1000, .index = 750 * 1000},
- {.frequency = 504 * 1000, .index = 800 * 1000},
- {.frequency = 816 * 1000, .index = 850 * 1000},
- {.frequency = 1008 * 1000, .index = 925 * 1000},
- {.frequency = 1200 * 1000, .index = 1000 * 1000},
- {.frequency = 1416 * 1000, .index = 1100 * 1000},
- {.frequency = 1608 * 1000, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- {.frequency = 100 * 1000, .index = 900 * 1000},
- {.frequency = 200 * 1000, .index = 900 * 1000},
- {.frequency = 266 * 1000, .index = 900 * 1000},
- {.frequency = 300 * 1000, .index = 900 * 1000},
- {.frequency = 400 * 1000, .index = 950 * 1000},
- {.frequency = 600 * 1000, .index = 1100 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 300 * 1000, .index = 900 * 1000},
- {.frequency = 400 * 1000, .index = 950 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-//#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
-//static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
-//static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
-
-void __init board_clock_init(void)
-{
- rk30_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
- //dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "cpu"), dvfs_arm_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
-}
-
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk30_fixup,
- .reserve = &rk30_reserve,
- .map_io = rk30_map_io,
- .init_irq = rk30_init_irq,
- .timer = &rk30_timer,
- .init_machine = machine_rk30_board_init,
-MACHINE_END
+++ /dev/null
-static rmii_extclk_sel = 0;
-static int rk30_vmac_register_set(void)
-{
- //config rk30 vmac as rmii
- writel_relaxed(0x3 << 16 | 0x2, RK30_GRF_BASE + GRF_SOC_CON1);
- int val = readl_relaxed(RK30_GRF_BASE + GRF_IO_CON3);
- writel_relaxed(val | 0xf << 16 | 0xf, RK30_GRF_BASE + GRF_IO_CON3);
- val = readl(RK30_GRF_BASE + GRF_SOC_CON2);
- writel(0x1 << 6 | 0x1 << 22 | val, RK30_GRF_BASE + GRF_SOC_CON2);
-
- return 0;
-}
-
-static int rk30_rmii_io_init(void)
-{
- int err;
- printk("enter %s \n",__func__);
-
- iomux_set(RMII_TXEN);
- iomux_set(RMII_TXD1);
- iomux_set(RMII_TXD0);
- iomux_set(RMII_RXD0);
- iomux_set(RMII_RXD1);
-#ifdef RMII_EXT_CLK
- iomux_set(RMII_CLKIN);
-#else
- iomux_set(RMII_CLKOUT);
-#endif
- iomux_set(RMII_RXERR);
- iomux_set(RMII_CRS);
- iomux_set(RMII_MD);
- iomux_set(RMII_MDCLK);
-
- if(INVALID_GPIO != PHY_PWR_EN_GPIO)
- {
- //phy power gpio request
- iomux_set(PHY_PWR_EN_IOMUX);
- err = gpio_request(PHY_PWR_EN_GPIO, "phy_power_en");
- if (err) {
- printk("request phy power en pin faile ! \n");
- return -1;
- }
- //phy power down
- gpio_direction_output(PHY_PWR_EN_GPIO, !PHY_PWR_EN_VALUE);
- }
-
- return 0;
-}
-
-static int rk30_rmii_io_deinit(void)
-{
- //phy power down
- printk("enter %s \n",__func__);
-
- if(INVALID_GPIO != PHY_PWR_EN_GPIO)
- {
- gpio_direction_output(PHY_PWR_EN_GPIO, !PHY_PWR_EN_VALUE);
- //free
- gpio_free(PHY_PWR_EN_GPIO);
- }
-
- return 0;
-}
-
-static int rk30_rmii_power_control(int enable)
-{
- printk("enter %s ,enable = %d \n",__func__,enable);
-
- if (enable){
- iomux_set(RMII_TXEN);
- iomux_set(RMII_TXD1);
- iomux_set(RMII_TXD0);
- iomux_set(RMII_RXD0);
- iomux_set(RMII_RXD1);
-#ifdef RMII_EXT_CLK
- iomux_set(RMII_CLKIN);
-#else
- iomux_set(RMII_CLKOUT);
-#endif
- iomux_set(RMII_RXERR);
- iomux_set(RMII_CRS);
- iomux_set(RMII_MD);
- iomux_set(RMII_MDCLK);
-
- if(INVALID_GPIO != PHY_PWR_EN_GPIO)
- {
- //reset power
- gpio_direction_output(PHY_PWR_EN_GPIO, !PHY_PWR_EN_VALUE);
- msleep(20);
- gpio_direction_output(PHY_PWR_EN_GPIO, PHY_PWR_EN_VALUE);
- }
- }else {
- if(INVALID_GPIO != PHY_PWR_EN_GPIO)
- {
- gpio_direction_output(PHY_PWR_EN_GPIO, !PHY_PWR_EN_VALUE);
- }
- }
-
- return 0;
-}
-
-#define BIT_EMAC_SPEED (1 << 1)
-static int rk29_vmac_speed_switch(int speed)
-{
- //printk("%s--speed=%d\n", __FUNCTION__, speed);
- if (10 == speed) {
- writel_relaxed(readl_relaxed(RK30_GRF_BASE + GRF_SOC_CON1) & (~BIT_EMAC_SPEED) | (BIT_EMAC_SPEED << 16), RK30_GRF_BASE + GRF_SOC_CON1);
- } else {
- writel_relaxed(readl_relaxed(RK30_GRF_BASE + GRF_SOC_CON1) | ( BIT_EMAC_SPEED) | (BIT_EMAC_SPEED << 16), RK30_GRF_BASE + GRF_SOC_CON1);
- }
-}
-
-static int rk30_rmii_extclk_sel(void)
-{
-#ifdef RMII_EXT_CLK
- rmii_extclk_sel = 1; //0:select internal divider clock, 1:select external input clock
-#endif
- return rmii_extclk_sel;
-}
-
-struct rk29_vmac_platform_data board_vmac_data = {
- .vmac_register_set = rk30_vmac_register_set,
- .rmii_io_init = rk30_rmii_io_init,
- .rmii_io_deinit = rk30_rmii_io_deinit,
- .rmii_power_control = rk30_rmii_power_control,
- .rmii_speed_switch = rk29_vmac_speed_switch,
- .rmii_extclk_sel = rk30_rmii_extclk_sel,
-};
+++ /dev/null
-/*
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <mach/dvfs.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <linux/fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/mfd/tps65910.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-
-#if defined(CONFIG_MFD_RK610)
-#include <linux/mfd/rk610_core.h>
-#endif
-
-#if defined(CONFIG_RK_HDMI)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-#if defined(CONFIG_GPS_RK)
-#include "../../../drivers/misc/gps/rk_gps/rk_gps.h"
-#endif
-
-#if defined(CONFIG_MU509)
-#include <linux/mu509.h>
-#endif
-#if defined(CONFIG_MW100)
-#include <linux/mw100.h>
-#endif
-#if defined(CONFIG_MT6229)
-#include <linux/mt6229.h>
-#endif
-#if defined(CONFIG_ANDROID_TIMED_GPIO)
-#include "../../../drivers/staging/android/timed_gpio.h"
-#endif
-
-#ifdef CONFIG_THREE_FB_BUFFER
-#define RK30_FB0_MEM_SIZE 12*SZ_1M
-#else
-#define RK30_FB0_MEM_SIZE 8*SZ_1M
-#endif
-
-#include "board-rk3066b-sdk-camera.c"
-#include "board-rk3066b-sdk-key.c"
-
-#if defined(CONFIG_TOUCHSCREEN_GT8XX)
-#define TOUCH_RESET_PIN RK30_PIN2_PC0
-#define TOUCH_PWR_PIN RK30_PIN2_PB4
-static int goodix_init_platform_hw(void)
-{
- int ret;
-
- if (TOUCH_PWR_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_PWR_PIN, "goodix power pin");
- if (ret != 0) {
- gpio_free(TOUCH_PWR_PIN);
- printk("goodix power error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_PWR_PIN, 0);
- gpio_set_value(TOUCH_PWR_PIN, GPIO_LOW);
- msleep(100);
- }
-
- if (TOUCH_RESET_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_RESET_PIN, "goodix reset pin");
- if (ret != 0) {
- gpio_free(TOUCH_RESET_PIN);
- printk("goodix gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, 1);
- msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_LOW);
- //msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_HIGH);
- //msleep(500);
- }
- return 0;
-}
-
-struct goodix_platform_data goodix_info = {
- .model = 8105,
- .irq_pin = RK30_PIN0_PD4,
- .rest_pin = TOUCH_RESET_PIN,
- .init_platform_hw = goodix_init_platform_hw,
-};
-#endif
-
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-#define PWM_ID 2
-#define PWM_MODE PWM2
-#define PWM_EFFECT_VALUE 1
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-#define BL_EN_PIN RK30_PIN0_PA2
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
-
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
- ret = gpio_request(BL_EN_PIN, "bl_en");
- if (ret == 0) {
- gpio_direction_output(BL_EN_PIN, BL_EN_VALUE);
- }
-#endif
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0, pwm_gpio;
-#ifdef LCD_DISP_ON_PIN
- gpio_free(BL_EN_PIN);
-#endif
- pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
- gpio_request(pwm_gpio, "bl_pwm");
- gpio_direction_output(pwm_gpio, GPIO_LOW);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret, pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
-
- ret = gpio_request(pwm_gpio, "bl_pwm");
- if (ret) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return ret;
- }
- gpio_direction_output(pwm_gpio, GPIO_LOW);
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, !BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- int pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
-
- gpio_free(pwm_gpio);
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-#endif
-
-#ifdef CONFIG_RK29_SUPPORT_MODEM
-
-#define RK30_MODEM_POWER RK30_PIN2_PB0
-#define RK30_MODEM_POWER_IOMUX rk29_mux_api_set(GPIO2B0_LCDC1DATA8_SMCDATA8_TRACEDATA8_NAME, GPIO2B_GPIO2B0)
-
-static int rk30_modem_io_init(void)
-{
- printk("%s\n", __FUNCTION__);
- RK30_MODEM_POWER_IOMUX;
-
- return 0;
-}
-
-static struct rk29_io_t rk30_modem_io = {
- .io_addr = RK30_MODEM_POWER,
- .enable = GPIO_HIGH,
- .disable = GPIO_LOW,
- .io_init = rk30_modem_io_init,
-};
-
-static struct platform_device rk30_device_modem = {
- .name = "rk30_modem",
- .id = -1,
- .dev = {
- .platform_data = &rk30_modem_io,
- }
-};
-#endif
-#if defined(CONFIG_MU509)
-static int mu509_io_init(void)
-{
-
- rk30_mux_api_set(GPIO2B0_LCDC1DATA8_SMCDATA8_TRACEDATA8_NAME, GPIO2B_GPIO2B0);
- rk30_mux_api_set(GPIO2D1_LCDC1DEN_SMCWEN_NAME, GPIO2D_GPIO2D1);
- rk30_mux_api_set(GPIO2B7_LCDC1DATA15_SMCADDR19_HSADCDATA7_NAME, GPIO2B_GPIO2B7);
- rk30_mux_api_set(GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME, GPIO2C_GPIO2C0);
- return 0;
-}
-
-static int mu509_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mu509_data rk29_mu509_info = {
- .io_init = mu509_io_init,
- .io_deinit = mu509_io_deinit,
- .modem_power_en = RK30_PIN2_PB0,
- .bp_power = RK30_PIN2_PB0,
- .bp_reset = RK30_PIN2_PD1,
- .ap_wakeup_bp = RK30_PIN2_PB7,
- .bp_wakeup_ap = RK30_PIN6_PA0,
-};
-struct platform_device rk29_device_mu509 = {
- .name = "mu509",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mu509_info,
- }
- };
-#endif
-#if defined(CONFIG_MW100)
-static int mw100_io_init(void)
-{
- rk30_mux_api_set(GPIO2B0_LCDC1DATA8_SMCDATA8_TRACEDATA8_NAME, GPIO2B_GPIO2B0);
- rk30_mux_api_set(GPIO2D1_LCDC1DEN_SMCWEN_NAME, GPIO2D_GPIO2D1);
- rk30_mux_api_set(GPIO2B7_LCDC1DATA15_SMCADDR19_HSADCDATA7_NAME, GPIO2B_GPIO2B7);
- rk30_mux_api_set(GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME, GPIO2C_GPIO2C0);
- return 0;
-}
-
-static int mw100_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mw100_data rk29_mw100_info = {
- .io_init = mw100_io_init,
- .io_deinit = mw100_io_deinit,
- .modem_power_en = RK30_PIN6_PB0,
- .bp_power = RK30_PIN2_PB0,
- .bp_reset = RK30_PIN2_PD1,
- .ap_wakeup_bp = RK30_PIN2_PB7,
- .bp_wakeup_ap = RK30_PIN6_PA0,
-};
-struct platform_device rk29_device_mw100 = {
- .name = "mw100",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mw100_info,
- }
- };
-#endif
-#if defined(CONFIG_MT6229)
-static int mt6229_io_init(void)
-{
- rk30_mux_api_set(GPIO2B0_LCDC1DATA8_SMCDATA8_TRACEDATA8_NAME, GPIO2B_GPIO2B0);
- rk30_mux_api_set(GPIO2D1_LCDC1DEN_SMCWEN_NAME, GPIO2D_GPIO2D1);
- rk30_mux_api_set(GPIO2B7_LCDC1DATA15_SMCADDR19_HSADCDATA7_NAME, GPIO2B_GPIO2B7);
- rk30_mux_api_set(GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME, GPIO2C_GPIO2C0);
- return 0;
-}
-
-static int mt6229_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mt6229_data rk29_mt6229_info = {
- .io_init = mt6229_io_init,
- .io_deinit = mt6229_io_deinit,
- .modem_power_en = RK30_PIN2_PB0,
- .bp_power = RK30_PIN2_PB0,//RK30_PIN2_PB6,
- .bp_reset = RK30_PIN2_PD1,
- .ap_wakeup_bp = RK30_PIN2_PC0,
- .bp_wakeup_ap = RK30_PIN6_PA0,
-};
-struct platform_device rk29_device_mt6229 = {
- .name = "mt6229",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mt6229_info,
- }
- };
-#endif
-
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN RK30_PIN3_PD7
-
-static int mma8452_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data mma8452_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma8452_init_platform_hw,
- .orientation = {-1, 0, 0, 0, 0, 1, 0, -1, 0},
-};
-#endif
-#if defined (CONFIG_GS_LIS3DH)
-#define LIS3DH_INT_PIN RK30_PIN3_PD7
-
-static int lis3dh_init_platform_hw(void)
-{
-
- return 0;
-}
-
-static struct sensor_platform_data lis3dh_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lis3dh_init_platform_hw,
- .orientation = {-1, 0, 0, 0, 0, 1, 0, -1, 0},
-};
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
-static struct sensor_platform_data akm8975_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-#if defined(CONFIG_GYRO_L3G4200D)
-
-#include <linux/l3g4200d.h>
-#define L3G4200D_INT_PIN RK30_PIN0_PB4
-
-static int l3g4200d_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data l3g4200d_info = {
- .type = SENSOR_TYPE_GYROSCOPE,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
- .init_platform_hw = l3g4200d_init_platform_hw,
- .x_min = 40,//x_min,y_min,z_min = (0-100) according to hardware
- .y_min = 40,
- .z_min = 20,
-};
-
-#endif
-
-#ifdef CONFIG_LS_CM3217
-static struct sensor_platform_data cm3217_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 0,
- .poll_delay_ms = 500,
-};
-
-#endif
-
-#ifdef CONFIG_FB_ROCKCHIP
-
-#define LCD_CS_PIN INVALID_GPIO
-#define LCD_CS_VALUE GPIO_HIGH
-
-#define LCD_EN_PIN RK30_PIN0_PB0
-#define LCD_EN_VALUE GPIO_HIGH
-
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
-
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_CS_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_CS_PIN);
- printk(KERN_ERR "request lcd cs pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_CS_PIN, LCD_CS_VALUE);
- }
- }
-
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_EN_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_EN_PIN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_EN_PIN, LCD_EN_VALUE);
- }
- }
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, !LCD_CS_VALUE);
- }
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, !LCD_EN_VALUE);
- }
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE);
- }
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
- }
- return 0;
-}
-
-#if defined(CONFIG_LCDC0_RK3066B)
-struct rk29fb_info lcdc0_screen_info = {
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B)
-struct rk29fb_info lcdc1_screen_info = {
- #if defined(CONFIG_RK_HDMI)
- .prop = EXTEND, //extend display device
- .lcd_info = NULL,
- .set_screen_info = hdmi_init_lcdc,
- #endif
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B)
-static struct resource resource_lcdc0[] = {
- [0] = {
- .name = "lcdc0 reg",
- .start = RK30_LCDC0_PHYS,
- .end = RK30_LCDC0_PHYS + RK30_LCDC0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc0 irq",
- .start = IRQ_LCDC0,
- .end = IRQ_LCDC0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc0 = {
- .name = "rk30-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc0),
- .resource = resource_lcdc0,
- .dev = {
- .platform_data = &lcdc0_screen_info,
- },
-};
-#endif
-#if defined(CONFIG_LCDC1_RK3066B)
-static struct resource resource_lcdc1[] = {
- [0] = {
- .name = "lcdc1 reg",
- .start = RK30_LCDC1_PHYS,
- .end = RK30_LCDC1_PHYS + RK30_LCDC1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc1 irq",
- .start = IRQ_LCDC1,
- .end = IRQ_LCDC1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc1 = {
- .name = "rk30-lcdc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resource_lcdc1),
- .resource = resource_lcdc1,
- .dev = {
- .platform_data = &lcdc1_screen_info,
- },
-};
-#endif
-
-#if defined(CONFIG_MFD_RK610)
-#if 1
-#define RK610_RST_PIN_MUX_NAME GPIO2C5_LCDC1DATA21_SMCADDR5_NAME
-#define RK610_RST_PIN_MUX_MODE GPIO2C_GPIO2C5
-#define RK610_RST_PIN RK30_PIN2_PC5
-#else
-#define RK610_RST_PIN_MUX_NAME GPIO2D6_SMCCSN1_NAME
-#define RK610_RST_PIN_MUX_MODE GPIO2D_GPIO2D6
-#define RK610_RST_PIN RK30_PIN2_PD6
-
-#endif
-static int rk610_power_on_init(void)
-{
- int ret;
- if(RK610_RST_PIN != INVALID_GPIO)
- {
- rk30_mux_api_set(RK610_RST_PIN_MUX_NAME,RK610_RST_PIN_MUX_MODE);
- ret = gpio_request(RK610_RST_PIN, "rk610 reset");
- if (ret)
- {
- printk(KERN_ERR "rk610_control_probe request gpio fail\n");
- }
- else
- {
- gpio_direction_output(RK610_RST_PIN, GPIO_HIGH);
- msleep(100);
- gpio_direction_output(RK610_RST_PIN, GPIO_LOW);
- msleep(100);
- gpio_set_value(RK610_RST_PIN, GPIO_HIGH);
- }
- }
-
- return 0;
-
-}
-
-
-static struct rk610_ctl_platform_data rk610_ctl_pdata = {
- .rk610_power_on_init = rk610_power_on_init,
-};
-#endif
-
-#ifdef CONFIG_SND_SOC_RK610
-static int rk610_codec_io_init(void)
-{
-//if need iomux.
-//Must not gpio_request
- return 0;
-}
-
-static struct rk610_codec_platform_data rk610_codec_pdata = {
- .spk_ctl_io = RK30_PIN4_PC6,
- .io_init = rk610_codec_io_init,
-};
-#endif
-
-#ifdef CONFIG_ANDROID_TIMED_GPIO
-static struct timed_gpio timed_gpios[] = {
- {
- .name = "vibrator",
- .gpio = RK30_PIN3_PD3,
- .max_timeout = 1000,
- .active_low = 0,
- .adjust_time =20, //adjust for diff product
- },
-};
-
-static struct timed_gpio_platform_data rk29_vibrator_info = {
- .num_gpios = 1,
- .gpios = timed_gpios,
-};
-
-static struct platform_device rk29_device_vibrator = {
- .name = "timed-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_vibrator_info,
- },
-
-};
-#endif
-
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
-static struct gpio_led rk29_leds[] = {
- {
- .name = "button-backlight",
- .gpio = RK30_PIN2_PB3,
- .default_trigger = "timer",
- .active_low = 0,
- .retain_state_suspended = 0,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- },
-};
-
-static struct gpio_led_platform_data rk29_leds_pdata = {
- .leds = rk29_leds,
- .num_leds = ARRAY_SIZE(rk29_leds),
-};
-
-static struct platform_device rk29_device_gpio_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_leds_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_RK_IRDA
-#define IRDA_IRQ_PIN RK30_PIN0_PA3
-
-static int irda_iomux_init(void)
-{
- int ret = 0;
-
- //irda irq pin
- ret = gpio_request(IRDA_IRQ_PIN, NULL);
- if (ret != 0) {
- gpio_free(IRDA_IRQ_PIN);
- printk(">>>>>> IRDA_IRQ_PIN gpio_request err \n ");
- }
- gpio_pull_updown(IRDA_IRQ_PIN, PullDisable);
- gpio_direction_input(IRDA_IRQ_PIN);
-
- return 0;
-}
-
-static int irda_iomux_deinit(void)
-{
- gpio_free(IRDA_IRQ_PIN);
- return 0;
-}
-
-static struct irda_info rk29_irda_info = {
- .intr_pin = IRDA_IRQ_PIN,
- .iomux_init = irda_iomux_init,
- .iomux_deinit = irda_iomux_deinit,
- //.irda_pwr_ctl = bu92747guw_power_ctl,
-};
-
-static struct platform_device irda_device = {
-#ifdef CONFIG_RK_IRDA_NET
- .name = "rk_irda",
-#else
- .name = "bu92747_irda",
-#endif
- .id = -1,
- .dev = {
- .platform_data = &rk29_irda_info,
- }
-};
-#endif
-
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and sdio.noted by xbw at 2012-03-05
-**************************************************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "board-rk30-sdk-sdmmc.c"
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
-#define SDMMC0_WRITE_PROTECT_PIN RK30_PIN3_PB7 //According to your own project to set the value of write-protect-pin.
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
-#define SDMMC1_WRITE_PROTECT_PIN RK30_PIN3_PC7 //According to your own project to set the value of write-protect-pin.
-#endif
-
-#define RK29SDK_WIFI_SDIO_CARD_DETECT_N RK30_PIN6_PB2
-
-#endif //endif ---#ifdef CONFIG_SDMMC_RK29
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- rk30_mux_api_set(GPIO3B1_SDMMC0CMD_NAME, GPIO3B_SDMMC0_CMD);
- rk30_mux_api_set(GPIO3B0_SDMMC0CLKOUT_NAME, GPIO3B_SDMMC0_CLKOUT);
- rk30_mux_api_set(GPIO3B2_SDMMC0DATA0_NAME, GPIO3B_SDMMC0_DATA0);
- rk30_mux_api_set(GPIO3B3_SDMMC0DATA1_NAME, GPIO3B_SDMMC0_DATA1);
- rk30_mux_api_set(GPIO3B4_SDMMC0DATA2_NAME, GPIO3B_SDMMC0_DATA2);
- rk30_mux_api_set(GPIO3B5_SDMMC0DATA3_NAME, GPIO3B_SDMMC0_DATA3);
-
- rk30_mux_api_set(GPIO3B6_SDMMC0DETECTN_NAME, GPIO3B_GPIO3B6);
-
- rk30_mux_api_set(GPIO3A7_SDMMC0PWREN_NAME, GPIO3A_GPIO3A7);
- gpio_request(RK30_PIN3_PA7, "sdmmc-power");
- gpio_direction_output(RK30_PIN3_PA7, GPIO_LOW);
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- #if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- iomux_set_gpio_mode(iomux_mode_to_gpio(MMC0_DETN));
- #else
- iomux_set(MMC0_DETN);
- #endif
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
- .detect_irq = RK30_PIN3_PB6, // INVALID_GPIO
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
-#else
- .write_prt = INVALID_GPIO,
-#endif
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- rk30_mux_api_set(GPIO3C0_SMMC1CMD_NAME, GPIO3C_SMMC1_CMD);
- rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_NAME, GPIO3C_SDMMC1_CLKOUT);
- rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_NAME, GPIO3C_SDMMC1_DATA0);
- rk30_mux_api_set(GPIO3C2_SDMMC1DATA1_NAME, GPIO3C_SDMMC1_DATA1);
- rk30_mux_api_set(GPIO3C3_SDMMC1DATA2_NAME, GPIO3C_SDMMC1_DATA2);
- rk30_mux_api_set(GPIO3C4_SDMMC1DATA3_NAME, GPIO3C_SDMMC1_DATA3);
- //rk30_mux_api_set(GPIO3C6_SDMMC1DETECTN_NAME, GPIO3C_SDMMC1_DETECT_N);
-
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-#if 0
- .detect_irq = RK29SDK_WIFI_SDIO_CARD_DETECT_N,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
-#else
- .detect_irq = INVALID_GPIO,
- .enable_sd_wakeup = 0,
-#endif
-
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-/**************************************************************************************************
- * the end of setting for SDMMC devices
-**************************************************************************************************/
-
-#ifdef CONFIG_BATTERY_RK30_ADC
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = RK30_PIN0_PB2,
- .batt_low_pin = RK30_PIN0_PB1,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = RK30_PIN0_PA6,
- .dc_det_level = GPIO_LOW,
- .charge_ok_level = GPIO_HIGH,
-};
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-#ifdef CONFIG_RK30_PWM_REGULATOR
-const static int pwm_voltage_map[] = {
- 950000, 975000,1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000, 1375000, 1400000
-};
-
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_core",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] =
-{
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
- .pwm_id = 3,
- .pwm_gpio = RK30_PIN3_PD6,
- .pwm_iomux_pwm = PWM3,
- .pwm_iomux_gpio = GPIO3_D6,
- .pwm_voltage = 1100000,
- .suspend_voltage = 1050000,
- .min_uV = 950000,
- .max_uV = 1400000,
- .coefficient = 455, //45.5%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-#endif
-
-#ifdef CONFIG_RK29_VMAC
-#define PHY_PWR_EN_GPIO RK30_PIN1_PD6
-#include "board-rk30-sdk-vmac.c"
-#endif
-
-#ifdef CONFIG_RFKILL_RK
-// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
-static struct rfkill_rk_platform_data rfkill_rk_platdata = {
- .type = RFKILL_TYPE_BLUETOOTH,
-
- .poweron_gpio = { // BT_REG_ON
- .io = INVALID_GPIO, //RK30_PIN3_PC7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_poweron",
- .fgpio = GPIO3_C7,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN3_PD1, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_reset",
- .fgpio = GPIO3_D1,
- },
- },
-
- .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
- .io = RK30_PIN3_PC6, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_wake",
- .fgpio = GPIO3_C6,
- },
- },
-
- .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .gpio = {
- .io = RK30_PIN0_PA5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
- .iomux = {
- .name = NULL,
- },
- },
- },
-
- .rts_gpio = { // UART_RTS, enable or disable BT's data coming
- .io = RK30_PIN1_PA3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_rts",
- .fgpio = GPIO1_A3,
- .fmux = UART0_RTSN,
- },
- },
-};
-
-static struct platform_device device_rfkill_rk = {
- .name = "rfkill_rk",
- .id = -1,
- .dev = {
- .platform_data = &rfkill_rk_platdata,
- },
-};
-#endif
-
-#if defined(CONFIG_GPS_RK)
-int rk_gps_io_init(void)
-{
- printk("%s \n", __FUNCTION__);
-
- rk30_mux_api_set(GPIO1B5_UART3RTSN_NAME, GPIO1B_GPIO1B5);//VCC_EN
- gpio_request(RK30_PIN1_PB5, NULL);
- gpio_direction_output(RK30_PIN1_PB5, GPIO_LOW);
-
- rk30_mux_api_set(GPIO1B4_UART3CTSN_GPSRFCLK_NAME, GPIO1B_GPSRFCLK);//GPS_CLK
- rk30_mux_api_set(GPIO1B2_UART3SIN_GPSMAG_NAME, GPIO1B_GPSMAG);//GPS_MAG
- rk30_mux_api_set(GPIO1B3_UART3SOUT_GPSSIG_NAME, GPIO1B_GPSSIG);//GPS_SIGN
-
- rk30_mux_api_set(GPIO1A6_UART1CTSN_SPI0CLK_NAME, GPIO1A_GPIO1A6);//SPI_CLK
- gpio_request(RK30_PIN1_PA6, NULL);
- gpio_direction_output(RK30_PIN1_PA6, GPIO_LOW);
-
- rk30_mux_api_set(GPIO1A5_UART1SOUT_SPI0TXD_NAME, GPIO1A_GPIO1A5);//SPI_MOSI
- gpio_request(RK30_PIN1_PA5, NULL);
- gpio_direction_output(RK30_PIN1_PA5, GPIO_LOW);
-
- rk30_mux_api_set(GPIO1A7_UART1RTSN_SPI0CSN0_NAME, GPIO1A_GPIO1A7);//SPI_CS
- gpio_request(RK30_PIN1_PA7, NULL);
- gpio_direction_output(RK30_PIN1_PA7, GPIO_LOW);
- return 0;
-}
-int rk_gps_power_up(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_power_down(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_reset_set(int level)
-{
- return 0;
-}
-int rk_enable_hclk_gps(void)
-{
- printk("%s \n", __FUNCTION__);
- clk_enable(clk_get(NULL, "hclk_gps"));
- return 0;
-}
-int rk_disable_hclk_gps(void)
-{
- printk("%s \n", __FUNCTION__);
- clk_disable(clk_get(NULL, "hclk_gps"));
- return 0;
-}
-struct rk_gps_data rk_gps_info = {
- .io_init = rk_gps_io_init,
- .power_up = rk_gps_power_up,
- .power_down = rk_gps_power_down,
- .reset = rk_gps_reset_set,
- .enable_hclk_gps = rk_enable_hclk_gps,
- .disable_hclk_gps = rk_disable_hclk_gps,
- .GpsSign = RK30_PIN1_PB3,
- .GpsMag = RK30_PIN1_PB2, //GPIO index
- .GpsClk = RK30_PIN1_PB4, //GPIO index
- .GpsVCCEn = RK30_PIN1_PB5, //GPIO index
- .GpsSpi_CSO = RK30_PIN1_PA4, //GPIO index
- .GpsSpiClk = RK30_PIN1_PA5, //GPIO index
- .GpsSpiMOSI = RK30_PIN1_PA7, //GPIO index
- .GpsIrq = IRQ_GPS,
- .GpsSpiEn = 0,
- .GpsAdcCh = 2,
- .u32GpsPhyAddr = RK30_GPS_PHYS,
- .u32GpsPhySize = RK30_GPS_SIZE,
-};
-
-struct platform_device rk_device_gps = {
- .name = "gps_hv5820b",
- .id = -1,
- .dev = {
- .platform_data = &rk_gps_info,
- }
- };
-#endif
-
-
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_FB_ROCKCHIP
- &device_fb,
-#endif
-#if defined(CONFIG_LCDC0_RK3066B)
- &device_lcdc0,
-#endif
-#if defined(CONFIG_LCDC1_RK3066B)
- &device_lcdc1,
-#endif
-
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- &rk29_device_backlight,
-#endif
-
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_ANDROID_TIMED_GPIO
- &rk29_device_vibrator,
-#endif
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
- &rk29_device_gpio_leds,
-#endif
-#ifdef CONFIG_RK_IRDA
- &irda_device,
-#endif
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- &rk29sdk_wifi_device,
-#endif
-#ifdef CONFIG_RK29_SUPPORT_MODEM
- &rk30_device_modem,
-#endif
-#if defined(CONFIG_MU509)
- &rk29_device_mu509,
-#endif
-#if defined(CONFIG_MW100)
- &rk29_device_mw100,
-#endif
-#if defined(CONFIG_MT6229)
- &rk29_device_mt6229,
-#endif
-#ifdef CONFIG_BATTERY_RK30_ADC
- &rk30_device_adc_battery,
-#endif
-#ifdef CONFIG_RFKILL_RK
- &device_rfkill_rk,
-#endif
-#ifdef CONFIG_GPS_RK
- &rk_device_gps,
-#endif
-
-};
-
-// i2c
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1d,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_GS_LIS3DH)
- {
- .type = "gs_lis3dh",
- .addr = 0x19, //0x19(SA0-->VCC), 0x18(SA0-->GND)
- .flags = 0,
- .irq = LIS3DH_INT_PIN,
- .platform_data = &lis3dh_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN0_PD5,
- .platform_data = &akm8975_info,
- },
-#endif
-#if defined (CONFIG_GYRO_L3G4200D)
- {
- .type = "l3g4200d_gryo",
- .addr = 0x69,
- .flags = 0,
- .irq = L3G4200D_INT_PIN,
- .platform_data = &l3g4200d_info,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RT5631)
- {
- .type = "rt5631",
- .addr = 0x1a,
- .flags = 0,
- },
-#endif
-
-#ifdef CONFIG_MFD_RK610
- {
- .type = "rk610_ctl",
- .addr = 0x40,
- .flags = 0,
- .platform_data = &rk610_ctl_pdata,
- },
-#ifdef CONFIG_RK610_TVOUT
- {
- .type = "rk610_tvout",
- .addr = 0x42,
- .flags = 0,
- },
-#endif
-#ifdef CONFIG_HDMI_RK610
- {
- .type = "rk610_hdmi",
- .addr = 0x46,
- .flags = 0,
- .irq = INVALID_GPIO,
- },
-#endif
-#ifdef CONFIG_SND_SOC_RK610
- {//RK610_CODEC addr from 0x60 to 0x80 (0x60~0x80)
- .type = "rk610_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- .platform_data = &rk610_codec_pdata,
- },
-#endif
-#endif
-
-};
-#endif
-
-int __sramdata g_pmic_type = 0;
-#ifdef CONFIG_I2C1_RK30
-#ifdef CONFIG_MFD_WM831X_I2C
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info wm8326_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "dcdc3", //ddr
- .min_uv = 1150000,
- .max_uv = 1150000,
- .suspend_vol = 1150000,
- },
- #ifdef CONFIG_MACH_RK3066_SDK
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3000000,
- },
- #else
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3000000,
- .max_uv = 3000000,
- .suspend_vol = 2800000,
- },
- #endif
-};
-
-static struct pmu_info wm8326_ldo_info[] = {
- {
- .name = "ldo1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo2", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo3", //
- .min_uv = 1100000,
- .max_uv = 1100000,
- .suspend_vol = 1100000,
- },
- {
- .name = "ldo4", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 1000000,
- },
- {
- .name = "ldo5", //vcc25
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo6", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo7", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- .suspend_vol = 2800000,
- },
- {
- .name = "ldo8", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo9", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo10", //flash_io
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
-};
-
-#include "board-pmu-wm8326.c"
-#endif
-
-#ifdef CONFIG_MFD_TPS65910
-#ifdef CONFIG_ARCH_RK3066B
-#define TPS65910_HOST_IRQ RK30_PIN0_PB3
-#else
-#define TPS65910_HOST_IRQ RK30_PIN6_PA4
-#endif
-
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info tps65910_dcdc_info[] = {
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "vdd2", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vio", //vcc_io
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
-
-};
-static struct pmu_info tps65910_ldo_info[] = {
- {
- .name = "vpll", //vcc25
- .min_uv = 2500000,
- .max_uv = 2500000,
- },
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "vdig2", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "vaux1", //vcc25_hdmi
- .min_uv = 2500000,
- .max_uv = 2500000,
- },
- {
- .name = "vaux2", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vaux33", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vmmc", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "vdac", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- };
-
-#include "board-pmu-tps65910.c"
-#endif
-
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_MFD_WM831X_I2C)
- {
- .type = "wm8326",
- .addr = 0x34,
- .flags = 0,
- .irq = RK30_PIN0_PB3,
- .platform_data = &wm831x_platdata,
- },
-#endif
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-};
-#endif
-
-void __sramfunc board_pmu_suspend(void)
-{
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_suspend();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_suspend();
- #endif
-}
-
-void __sramfunc board_pmu_resume(void)
-{
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_resume();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_resume();
- #endif
-}
-
- int __sramdata gpio3d6_iomux,gpio3d6_do,gpio3d6_dir,gpio3d6_en;
-
-#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
-
-void __sramfunc rk30_pwm_logic_suspend_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
-
-// int gpio0d7_iomux,gpio0d7_do,gpio0d7_dir,gpio0d7_en;
- sram_udelay(10000);
- gpio3d6_iomux = grf_readl(GRF_GPIO3D_IOMUX);
- gpio3d6_do = grf_readl(GRF_GPIO3H_DO);
- gpio3d6_dir = grf_readl(GRF_GPIO3H_DIR);
- gpio3d6_en = grf_readl(GRF_GPIO3H_EN);
-
- grf_writel((1<<28), GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DIR);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DO);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_EN);
-#endif
-}
-void __sramfunc rk30_pwm_logic_resume_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- grf_writel((1<<28)|gpio3d6_iomux, GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|gpio3d6_en, GRF_GPIO3H_EN);
- grf_writel((1<<30)|gpio3d6_dir, GRF_GPIO3H_DIR);
- grf_writel((1<<30)|gpio3d6_do, GRF_GPIO3H_DO);
- sram_udelay(10000);
-
-#endif
-
-}
-extern void pwm_suspend_voltage(void);
-extern void pwm_resume_voltage(void);
-void rk30_pwm_suspend_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_suspend_voltage();
-#endif
-}
-void rk30_pwm_resume_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_resume_voltage();
-#endif
-}
-
-
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-#if defined (CONFIG_TOUCHSCREEN_GT8XX)
- {
- .type = "Goodix-TS",
- .addr = 0x55,
- .flags = 0,
- .irq = RK30_PIN0_PD4,
- .platform_data = &goodix_info,
- },
-#endif
-#if defined (CONFIG_LS_CM3217)
- {
- .type = "lightsensor",
- .addr = 0x10,
- .flags = 0,
- .platform_data = &cm3217_info,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C4_RK30
-static struct i2c_board_info __initdata i2c4_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO// RK30_PIN2_PD6 //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO//RK30_PIN2_PD7 //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- //set iomux (gpio) here
- //rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME, GPIO2D_GPIO2D7);
- //rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME, GPIO2D_GPIO2D6);
-
- return 0;
-}
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C4_RK30
- i2c_register_board_info(4, i2c4_info, ARRAY_SIZE(i2c4_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(5, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-
-#define POWER_ON_PIN RK30_PIN0_PA0 //power_hold
-static void rk30_pm_power_off(void)
-{
- printk(KERN_ERR "rk30_pm_power_off start...\n");
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
-#if defined(CONFIG_MFD_WM831X)
- wm831x_set_bits(Wm831x,WM831X_GPIO_LEVEL,0x0001,0x0000); //set sys_pwr 0
- wm831x_device_shutdown(Wm831x);//wm8326 shutdown
-#endif
- while (1);
-}
-
-static void __init machine_rk30_board_init(void)
-{
- //avs_init();
- gpio_request(POWER_ON_PIN, "poweronpin");
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
- pm_power_off = rk30_pm_power_off;
-
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
- //test
- iomux_set(GPIO2_A2);
- gpio_request(RK30_PIN2_PA1, NULL);
- gpio_direction_output(RK30_PIN2_PA1, GPIO_HIGH);
-
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- board_usb_detect_init(RK30_PIN0_PA7);
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- rk29sdk_wifi_bt_gpio_control_init();
-#endif
-}
-
-static void __init rk30_reserve(void)
-{
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0", RK30_FB0_MEM_SIZE);
- resource_fb[0].end = resource_fb[0].start + RK30_FB0_MEM_SIZE - 1;
- #if 0
- resource_fb[1].start = board_mem_reserve_add("ipp buf", RK30_FB0_MEM_SIZE);
- resource_fb[1].end = resource_fb[1].start + RK30_FB0_MEM_SIZE - 1;
- resource_fb[2].start = board_mem_reserve_add("fb2", RK30_FB0_MEM_SIZE);
- resource_fb[2].end = resource_fb[2].start + RK30_FB0_MEM_SIZE - 1;
- #endif
-#endif
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
-
-#ifdef CONFIG_GPS_RK
- //it must be more than 8MB
- rk_gps_info.u32MemoryPhyAddr = board_mem_reserve_add("gps", SZ_8M);
-#endif
- board_mem_reserved();
-}
-
-/**
- * dvfs_cpu_logic_table: table for arm and logic dvfs
- * @frequency : arm frequency
- * @cpu_volt : arm voltage depend on frequency
- * @logic_volt : logic voltage arm requests depend on frequency
- * comments : min arm/logic voltage
- */
-static struct dvfs_arm_table dvfs_cpu_logic_table[] = {
- {.frequency = 312 * 1000, .cpu_volt = 850 * 1000, .logic_volt = 1000 * 1000},
- {.frequency = 504 * 1000, .cpu_volt = 900 * 1000, .logic_volt = 1000 * 1000},
- {.frequency = 816 * 1000, .cpu_volt = 950 * 1000, .logic_volt = 1000 * 1000},
- {.frequency = 1008 * 1000, .cpu_volt = 1025 * 1000, .logic_volt = 1000 * 1000},
- {.frequency = 1200 * 1000, .cpu_volt = 1100 * 1000, .logic_volt = 1050 * 1000},
- {.frequency = 1416 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1150 * 1000},
- {.frequency = 1608 * 1000, .cpu_volt = 1300 * 1000, .logic_volt = 1250 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- {.frequency = 100 * 1000, .index = 900 * 1000},
- {.frequency = 200 * 1000, .index = 900 * 1000},
- {.frequency = 266 * 1000, .index = 900 * 1000},
- {.frequency = 300 * 1000, .index = 900 * 1000},
- {.frequency = 400 * 1000, .index = 950 * 1000},
- {.frequency = 600 * 1000, .index = 1100 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 300 * 1000, .index = 900 * 1000},
- {.frequency = 400 * 1000, .index = 950 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
-static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
-static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
-
-void __init board_clock_init(void)
-{
- rk30_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
- dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
-}
-
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk30_fixup,
- .reserve = &rk30_reserve,
- .map_io = rk30_map_io,
- .init_irq = rk30_init_irq,
- .timer = &rk30_timer,
- .init_machine = machine_rk30_board_init,
-MACHINE_END
+++ /dev/null
-#ifdef CONFIG_VIDEO_RK29
-#include <plat/rk_camera.h>
-/* Notes:
-
-Simple camera device registration:
-
- new_camera_device(sensor_name,\ // sensor name, it is equal to CONFIG_SENSOR_X
- face,\ // sensor face information, it can be back or front
- pwdn_io,\ // power down gpio configuration, it is equal to CONFIG_SENSOR_POWERDN_PIN_XX
- flash_attach,\ // sensor is attach flash or not
- mir,\ // sensor image mirror and flip control information
- i2c_chl,\ // i2c channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_IIC_ADAPTER_ID_X
- cif_chl) \ // cif channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_CIF_INDEX_X
-
-Comprehensive camera device registration:
-
- new_camera_device_ex(sensor_name,\
- face,\
- ori,\ // sensor orientation, it is equal to CONFIG_SENSOR_ORIENTATION_X
- pwr_io,\ // sensor power gpio configuration, it is equal to CONFIG_SENSOR_POWER_PIN_XX
- pwr_active,\ // sensor power active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- rst_io,\ // sensor reset gpio configuration, it is equal to CONFIG_SENSOR_RESET_PIN_XX
- rst_active,\ // sensor reset active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- pwdn_io,\
- pwdn_active,\ // sensor power down active level, is equal to CONFIG_SENSOR_POWERDNACTIVE_LEVEL_X
- flash_attach,\
- res,\ // sensor resolution, this is real resolution or resoltuion after interpolate
- mir,\
- i2c_chl,\
- i2c_spd,\ // i2c speed , 100000 = 100KHz
- i2c_addr,\ // the i2c slave device address for sensor
- cif_chl,\
- mclk)\ // sensor input clock rate, 24 or 48
-
-*/
-static struct rkcamera_platform_data new_camera[] = {
- new_camera_device(RK29_CAM_SENSOR_GC2035,
- back,
- RK30_PIN3_PB5,
- 0,
- 0,
- 3,
- 0),
- new_camera_device(RK29_CAM_SENSOR_GC0308,
- front,
- RK30_PIN3_PB4,
- 0,
- 0,
- 3,
- 0),
- new_camera_device_end
-};
-
-/*---------------- Camera Sensor Macro Define Begin ------------------------*/
-/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
-#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_OV2659 /* back camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_0 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 3
-#define CONFIG_SENSOR_ORIENTATION_0 90
-#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 RK30_PIN3_PB5
-#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO//RK30_PIN0_PD5 //INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_H
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000
-
-#define CONFIG_SENSOR_01 RK29_CAM_SENSOR_OV5642 /* back camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_01 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 4
-#define CONFIG_SENSOR_ORIENTATION_01 90
-#define CONFIG_SENSOR_POWER_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_01 RK30_PIN1_PD6
-#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_01 30000
-
-#define CONFIG_SENSOR_02 RK29_CAM_SENSOR_OV5640 /* back camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_02 0x00
-#define CONFIG_SENSOR_CIF_INDEX_02 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 4
-#define CONFIG_SENSOR_ORIENTATION_02 90
-#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000
-
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_GC0308 /* front camera sensor 0 */
-#define CONFIG_SENSOR_IIC_ADDR_1 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 3
-#define CONFIG_SENSOR_ORIENTATION_1 270
-#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_1 RK30_PIN3_PB4
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000
-
-#define CONFIG_SENSOR_11 RK29_CAM_SENSOR_OV2659 /* front camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_11 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 3
-#define CONFIG_SENSOR_ORIENTATION_11 270
-#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_11 INVALID_GPIO//RK30_PIN1_PB7
-#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_11 30000
-
-#define CONFIG_SENSOR_12 RK29_CAM_SENSOR_OV2659//RK29_CAM_SENSOR_OV2655 /* front camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_12 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 3
-#define CONFIG_SENSOR_ORIENTATION_12 270
-#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_12 INVALID_GPIO//RK30_PIN1_PB7
-#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_12 30000
-
-
-#endif //#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk30_camera.c"
-/*---------------- Camera Sensor Macro Define End ---------*/
-
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#define CONFIG_SENSOR_POWER_IOCTL_USR 0 //define this refer to your board layout
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 1
-
-static void rk_cif_power(int on)
-{
- struct regulator *ldo_18,*ldo_28;
- ldo_28 = regulator_get(NULL, "ldo7"); // vcc28_cif
- ldo_18 = regulator_get(NULL, "ldo1"); // vcc18_cif
- if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){
- printk("get cif ldo failed!\n");
- return;
- }
- if(on == 0){
- regulator_disable(ldo_28);
- regulator_put(ldo_28);
- regulator_disable(ldo_18);
- regulator_put(ldo_18);
- mdelay(500);
- }
- else{
- regulator_set_voltage(ldo_28, 2800000, 2800000);
- regulator_enable(ldo_28);
- // printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
- regulator_put(ldo_28);
-
- regulator_set_voltage(ldo_18, 1800000, 1800000);
- // regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(ldo_18);
- // printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
- regulator_put(ldo_18);
- }
-}
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- //#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
- rk_cif_power(on);
- return 0;
-}
-#endif
-
-#if CONFIG_SENSOR_RESET_IOCTL_USR
-static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
-static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-
-#define CONFIG_SENSOR_FALSH_EN_PIN_0 RK30_PIN0_PD5 //high:enable
-#define CONFIG_SENSOR_FALSH_EN_MUX_0 GPIO0D5_SPI1TXD_NAME
-#define CONFIG_SENSOR_FALSH_MODE_PIN_0 RK30_PIN0_PD4 //high:FLASH, low:torch
-#define CONFIG_SENSOR_FALSH_MODE_MUX_0 GPIO0D4_SPI1RXD_NAME
-
-static int sensor_init_flags = 0;
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- if(sensor_init_flags == 0){
- rk30_mux_api_set(CONFIG_SENSOR_FALSH_MODE_MUX_0, 0);
- int ret = gpio_request(CONFIG_SENSOR_FALSH_MODE_PIN_0, "camera_flash_mode");
- if (ret != 0) {
- printk(">>>>gpio request camera_flash_mode faile !!\n");
- }
-
- gpio_direction_output(CONFIG_SENSOR_FALSH_MODE_PIN_0, 0);
- sensor_init_flags = 1 ;
- }
- switch (on) {
- case Flash_Off: {
- gpio_set_value(CONFIG_SENSOR_FALSH_EN_PIN_0, 0);
- gpio_set_value(CONFIG_SENSOR_FALSH_MODE_PIN_0, 0);
- break;
- }
-
- case Flash_On: {
- gpio_set_value(CONFIG_SENSOR_FALSH_EN_PIN_0, 1);
- gpio_set_value(CONFIG_SENSOR_FALSH_MODE_PIN_0, 1);
- break;
- }
-
- case Flash_Torch: {
- gpio_set_value(CONFIG_SENSOR_FALSH_EN_PIN_0, 1);
- gpio_set_value(CONFIG_SENSOR_FALSH_MODE_PIN_0, 0);
- break;
- }
-
- default: {
- printk("%s..Flash command(%d) is invalidate \n",__FUNCTION__, on);
- gpio_set_value(CONFIG_SENSOR_FALSH_EN_PIN_0, 0);
- break;
- }
- }
- return 0;
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-
-#if CONFIG_SENSOR_IIC_ADDR_0
-static struct reginfo_t rk_init_data_sensor_reg_0[] =
-{
- {0x0000, 0x00,0,0}
- };
-static struct reginfo_t rk_init_data_sensor_winseqreg_0[] ={
- {0x0000, 0x00,0,0}
- };
-#endif
-
-#if CONFIG_SENSOR_IIC_ADDR_1
-static struct reginfo_t rk_init_data_sensor_reg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_01
-static struct reginfo_t rk_init_data_sensor_reg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_02
-static struct reginfo_t rk_init_data_sensor_reg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_11
-static struct reginfo_t rk_init_data_sensor_reg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_12
-static struct reginfo_t rk_init_data_sensor_reg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] =
-{
- #if CONFIG_SENSOR_IIC_ADDR_0
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_0,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_1
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_1,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_01
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_01,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_02
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_02,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_11
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_11,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_12
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_12,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
-
- };
-#include "../../../drivers/media/video/rk30_camera.c"
-
-#endif /* CONFIG_VIDEO_RK29 */
+++ /dev/null
-/*****************************************************************************************
- * arch/arm/mach-rkxx/baord-xxx-sdmmc-config.c
- *
- * Copyright (C) 2013 ROCKCHIP, Inc.
- *
- * Description:
- * define the gpio for SD-MMC-SDIO-Wifi functions according to your own projects.
- *
- * Author: Michael Xie
- * 15 Jan,2013
- * E-mail: xbw@rock-chips.com
- *
- ******************************************************************************************/
-
-/*
-** If you select the macro of CONFIG_SDMMC0_RK29_WRITE_PROTECT, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define SDMMC0_WRITE_PROTECT_PIN RK30_PIN3_PB2 //According to your own project to set the value of write-protect-pin.
-//#define SDMMC0_WRITE_PROTECT_ENABLE_VALUE GPIO_HIGH
-
-/*
-** If you select the macro of CONFIG_SDMMC1_RK29_WRITE_PROTECT, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define SDMMC1_WRITE_PROTECT_PIN RK30_PIN3_PB3 //According to your own project to set the value of write-protect-pin.
-//#define SDMMC1_WRITE_PROTECT_ENABLE_VALUE GPIO_HIGH
-
-/*
-** If you select the macro of CONFIG_RK29_SDIO_IRQ_FROM_GPIO, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define RK29SDK_WIFI_SDIO_CARD_INT RK30_PIN3_PD2
-
-
-/*
-* define sdcard PowerEn-pin
-*/
-#define RK29SDK_SD_CARD_PWR_EN RK30_PIN3_PA1
-#define RK29SDK_SD_CARD_PWR_EN_LEVEL GPIO_LOW
-int rk31sdk_get_sdmmc0_pin_io_voltage(void)
-{
- int voltage;
-#define RK31SDK_SET_SDMMC0_PIN_VOLTAGE
-
- /**************************************************************************************
- ** Please tell me how much voltage of your SDMMC0-pin in your project.
- **
- ** ÀýÈç: ÓеÄÏîÄ¿£¬ËüµÄSDMMC0ËùÔÚµÄRKÖ÷¿ØµÄIO×飬ÏëÓÃ1.8V, ¶ø¿¨±¾ÉíÓÃ3.3V,
- ** ¶øÖмäͨ¹ý¸öµçƽת»».ÄÇô£¬Äú´Ëʱ£¬Ó¦¸ÃÉèÖÃÏÂÃæµÄvoltageֵΪ 1.8V(¼´1800mv)
- ***************************************************************************************/
- voltage = 3300; //default the voltage 3300mv.
-
- return voltage;
-}
-
-/*
-* define the card-detect-pin.
-*/
-#define RK29SDK_SD_CARD_DETECT_N RK30_PIN3_PB0 //According to your own project to set the value of card-detect-pin.
-#define RK29SDK_SD_CARD_INSERT_LEVEL GPIO_LOW // set the voltage of insert-card. Please pay attention to the default setting.
-
-//wake up host gpio
-#define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
-#define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
-
-/*
-* Define wifi module's power and reset gpio, and gpio sensitive level.
-* Please set the value according to your own project.
-*
-* Well, you just own engineering module to set the value in the corresponding module branch.
-* Otherwise, you do not define this macro, eliminate it.
-*
-*/
-#if defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU)
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN0_PD5//RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_LOW//GPIO_HIGH
-
-#elif defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319) || defined(CONFIG_RK903) || defined(CONFIG_RK901)
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN2_PA7
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
-
-#elif defined(CONFIG_MT5931_MT6622) || defined(CONFIG_MT5931)
-
- #ifdef CONFIG_MACH_RK3168_LR097
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- //#define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- //#define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
-
- #else
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN0_PA5
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #endif
-
-#elif defined(CONFIG_MT6620)
- #define COMBO_MODULE_MT6620_CDT 1 // to control antsel2,antsel3 and gps_lan foot when using AcSip or Cdtech chip.
- //- 1--use Cdtech chip; 0--unuse CDT chip
-
- //power, PMU_EN
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PC7
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- //reset, DAIRST,SYSRST_B
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- //VDDIO
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL RK30_PIN0_PD2 //You do not get control of the foot, and you do not need to define the macro
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_ENABLE_VALUE GPIO_HIGH
- //WIFI_INT_B
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
- //BGF_INT_B
- #define RK30SDK_WIFI_GPIO_BGF_INT_B RK30_PIN6_PA7
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_ENABLE_VALUE GPIO_HIGH
- //GPS_SYNC
- #define RK30SDK_WIFI_GPIO_GPS_SYNC RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_ENABLE_VALUE GPIO_HIGH
-
- #if COMBO_MODULE_MT6620_CDT
- //ANTSEL2
- #define RK30SDK_WIFI_GPIO_ANTSEL2 RK30_PIN4_PD4
- #define RK30SDK_WIFI_GPIO_ANTSEL2_ENABLE_VALUE GPIO_LOW //use 6620 in CDT chip, LOW--work; High--no work.
- //ANTSEL3
- #define RK30SDK_WIFI_GPIO_ANTSEL3 RK30_PIN4_PD3
- #define RK30SDK_WIFI_GPIO_ANTSEL3_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- //GPS_LAN
- #define RK30SDK_WIFI_GPIO_GPS_LAN RK30_PIN4_PD6
- #define RK30SDK_WIFI_GPIO_GPS_LAN_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- #endif // #if COMBO_MODULE_MT6620_CDT--#endif
-#endif
-
-int rk31sdk_get_sdio_wifi_voltage(void)
-{
- int voltage;
-
- /******************************************************************************
- ** Please tell me how much wifi-module uses voltage in your project.
- ******************************************************************************/
-#if defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319) || defined(CONFIG_RK903) || defined(CONFIG_RK901)
- voltage = 1800 ; //power 1800mV
-
-#elif defined(CONFIG_MT5931_MT6622)||defined(CONFIG_MT5931)
- voltage = 1800 ; //power 1800V
-#elif defined(CONFIG_MT6620)
- voltage = 2800 ; //power 2800V
-#elif defined(CONFIG_RDA5990)||defined(CONFIG_RTL8723AS)
- voltage = 3300 ; //power 3300V
-#else
- //default, sdio use 3.0V
- voltage = 3000 ; //power 3000V
-#endif
-
- return voltage;
-}
-
-
-
+++ /dev/null
-/*
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <mach/dvfs.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <linux/rk_fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/mfd/tps65910.h>
-#include <linux/regulator/act8846.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-#if defined(CONFIG_CT36X_TS)
-#include <linux/ct36x.h>
-#endif
-#if defined(CONFIG_MFD_RK610)
-#include <linux/mfd/rk610_core.h>
-#endif
-
-#if defined(CONFIG_RK_HDMI)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-#if defined(CONFIG_GPS_RK)
-#include "../../../drivers/misc/gps/rk_gps/rk_gps.h"
-#endif
-
-#if defined(CONFIG_MT6620)
-#include <linux/gps.h>
-#endif
-
-#include "board-rk3168-86v-camera.c"
-#include <plat/key.h>
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK30_PIN0_PA4,
- .active_low = PRESS_LEV_LOW,
- .wakeup = 1,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .adc_value = 150,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .adc_value = 1,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = 1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
-#if defined(CONFIG_CT36X_TS)
-
-#define TOUCH_MODEL 363
-#define TOUCH_MAX_X 1280
-#define TOUCH_MAX_y 800
-#define TOUCH_RESET_PIN RK30_PIN0_PB6
-#define TOUCH_INT_PIN RK30_PIN1_PB7
-
-static struct ct36x_platform_data ct36x_info = {
- .model = TOUCH_MODEL,
- .x_max = TOUCH_MAX_X,
- .y_max = TOUCH_MAX_y,
-
- .rst_io = {
- .gpio = TOUCH_RESET_PIN,
- .active_low = 1,
- },
- .irq_io = {
- .gpio = TOUCH_INT_PIN,
- .active_low = 1,
- },
- .orientation = {1, 0, 1, 0},
-};
-#endif
-
-#if defined(CONFIG_TOUCHSCREEN_GSLX680)
-#define TOUCH_RESET_PIN RK30_PIN0_PB6
-#define TOUCH_EN_PIN NULL
-#define TOUCH_INT_PIN RK30_PIN1_PB7
-
-int gslx680_init_platform_hw(void)
-{
-
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("gslx680_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("gslx680_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, GPIO_HIGH);
- mdelay(10);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- mdelay(10);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- msleep(300);
- return 0;
-
-}
-
-struct ts_hw_data gslx680_info = {
- .reset_gpio = TOUCH_RESET_PIN,
- .touch_en_gpio = TOUCH_INT_PIN,
- .init_platform_hw = gslx680_init_platform_hw,
-};
-#endif
-
-
-#if defined (CONFIG_TOUCHSCREEN_86V_GT811_IIC)
-#define TOUCH_RESET_PIN RK30_PIN0_PB6
-#define TOUCH_INT_PIN RK30_PIN1_PB7
-int gt811_init_platform_hw(void)
-{
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("gt811_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("gt811_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- //gpio_pull_updown(TOUCH_INT_PIN, 1);
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- mdelay(100);
-
- return 0;
-}
-
-
-static struct goodix_platform_data gt811_info = {
- .model= 811,
- .init_platform_hw= gt811_init_platform_hw,
-
-};
-#endif
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-#define PWM_ID 3
-#define PWM_MODE PWM3
-#define PWM_EFFECT_VALUE 0// 1
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-#define BL_EN_PIN RK30_PIN0_PA2
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
-
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
- ret = gpio_request(BL_EN_PIN, NULL);
- if (ret != 0) {
- gpio_free(BL_EN_PIN);
- }
-
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
-
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0, pwm_gpio;
-
-#ifdef LCD_DISP_ON_PIN
- gpio_free(BL_EN_PIN);
-#endif
-
- pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
- gpio_request(pwm_gpio, NULL);
- gpio_direction_output(pwm_gpio, GPIO_LOW);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret = 0, pwm_gpio;
-
- pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
- if (gpio_request(pwm_gpio, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- gpio_direction_output(pwm_gpio, GPIO_LOW);
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, !BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- int pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
-
- gpio_free(pwm_gpio);
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
- msleep(130);
- gpio_direction_output(BL_EN_PIN, 1);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .min_brightness = 30,
- .max_brightness=255,
- .brightness_mode =1,
- .pre_div = 20 * 1000, // pwm output clk: 20k;
- .pwm_id = PWM_ID,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-#endif
-
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN RK30_PIN0_PB7
-
-static int mma8452_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data mma8452_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma8452_init_platform_hw,
- .orientation = {-1, 0, 0, 0, 0, 1, 0, 1, 0},
-};
-#endif
-
-/*MMA7660 gsensor*/
-#if defined (CONFIG_GS_MMA7660)
-#define MMA7660_INT_PIN RK30_PIN0_PB7
-
-static int mma7660_init_platform_hw(void)
-{
- //rk30_mux_api_set(GPIO1B2_SPI_RXD_UART1_SIN_NAME, GPIO1B_GPIO1B2);
-
- return 0;
-}
-
-static struct sensor_platform_data mma7660_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma7660_init_platform_hw,
- .orientation = {0, -1, 0, 0, 0, -1, -1, 0, 0},
-
-};
-#endif
-
-#if defined (CONFIG_GS_LIS3DH)
-#define LIS3DH_INT_PIN RK30_PIN0_PB7
-
-static int lis3dh_init_platform_hw(void)
-{
-
- return 0;
-}
-
-static struct sensor_platform_data lis3dh_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lis3dh_init_platform_hw,
- .orientation = {-1, 0, 0, 0, 0, 1, 0, -1, 0},
-};
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
-static struct sensor_platform_data akm8975_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-#if defined(CONFIG_GYRO_L3G4200D)
-
-#include <linux/l3g4200d.h>
-#define L3G4200D_INT_PIN RK30_PIN0_PB4
-
-static int l3g4200d_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data l3g4200d_info = {
- .type = SENSOR_TYPE_GYROSCOPE,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
- .init_platform_hw = l3g4200d_init_platform_hw,
- .x_min = 40,//x_min,y_min,z_min = (0-100) according to hardware
- .y_min = 40,
- .z_min = 20,
-};
-
-#endif
-
-#ifdef CONFIG_LS_CM3217
-static struct sensor_platform_data cm3217_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 0,
- .poll_delay_ms = 500,
-};
-
-#endif
-
-#ifdef CONFIG_FB_ROCKCHIP
-
-#define LCD_CS_PIN INVALID_GPIO
-#define LCD_CS_VALUE GPIO_HIGH
-
-#define LCD_EN_PIN RK30_PIN0_PB0
-#define LCD_EN_VALUE GPIO_LOW
-
-#define LCD_STBYB_RXD_MODE SPI1_RXD
-
-
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
- int stbyb_gpio;
-
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_CS_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_CS_PIN);
- printk(KERN_ERR "request lcd cs pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_CS_PIN, LCD_CS_VALUE);
- }
- }
-
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_EN_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_EN_PIN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_EN_PIN, LCD_EN_VALUE);
- }
- }
-
- stbyb_gpio = iomux_mode_to_gpio(LCD_STBYB_RXD_MODE);
- gpio_request(stbyb_gpio, "stbyb");
- gpio_direction_output(stbyb_gpio, GPIO_HIGH);
- gpio_set_value(stbyb_gpio,GPIO_HIGH);
-
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, !LCD_CS_VALUE);
- }
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, !LCD_EN_VALUE);
- }
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE);
- }
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
- }
- return 0;
-}
-
-#if defined(CONFIG_LCDC0_RK3066B)
-struct rk29fb_info lcdc0_screen_info = {
- .prop = EXTEND, //primary display device
- .io_init = NULL,
- .io_disable = NULL,
- .io_enable = NULL,
- .set_screen_info = NULL,
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B)
-struct rk29fb_info lcdc1_screen_info = {
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B)
-static struct resource resource_lcdc0[] = {
- [0] = {
- .name = "lcdc0 reg",
- .start = RK30_LCDC0_PHYS,
- .end = RK30_LCDC0_PHYS + RK30_LCDC0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc0 irq",
- .start = IRQ_LCDC0,
- .end = IRQ_LCDC0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc0 = {
- .name = "rk30-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc0),
- .resource = resource_lcdc0,
- .dev = {
- .platform_data = &lcdc0_screen_info,
- },
-};
-#endif
-#if defined(CONFIG_LCDC1_RK3066B)
-static struct resource resource_lcdc1[] = {
- [0] = {
- .name = "lcdc1 reg",
- .start = RK30_LCDC1_PHYS,
- .end = RK30_LCDC1_PHYS + RK30_LCDC1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc1 irq",
- .start = IRQ_LCDC1,
- .end = IRQ_LCDC1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc1 = {
- .name = "rk30-lcdc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resource_lcdc1),
- .resource = resource_lcdc1,
- .dev = {
- .platform_data = &lcdc1_screen_info,
- },
-};
-#endif
-
-#if defined(CONFIG_MFD_RK610)
-#define RK610_RST_PIN RK30_PIN3_PB2
-static int rk610_power_on_init(void)
-{
- int ret;
- if(RK610_RST_PIN != INVALID_GPIO)
- {
- ret = gpio_request(RK610_RST_PIN, "rk610 reset");
- if (ret)
- {
- printk(KERN_ERR "rk610_control_probe request gpio fail\n");
- }
- else
- {
- gpio_direction_output(RK610_RST_PIN, GPIO_HIGH);
- msleep(100);
- gpio_direction_output(RK610_RST_PIN, GPIO_LOW);
- msleep(100);
- gpio_set_value(RK610_RST_PIN, GPIO_HIGH);
- }
- }
-
- return 0;
-
-}
-
-
-static struct rk610_ctl_platform_data rk610_ctl_pdata = {
- .rk610_power_on_init = rk610_power_on_init,
-};
-#endif
-
-#ifdef CONFIG_SND_SOC_RK610
-static int rk610_codec_io_init(void)
-{
-//if need iomux.
-//Must not gpio_request
- return 0;
-}
-
-static struct rk610_codec_platform_data rk610_codec_pdata = {
- .spk_ctl_io = RK30_PIN2_PD7,
- .io_init = rk610_codec_io_init,
- .boot_depop = 1,
-};
-#endif
-
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and sdio.noted by xbw at 2012-03-05
-**************************************************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "board-rk3168-86v-old-sdmmc-config.c"
-#include "../plat-rk/rk-sdmmc-ops.c"
-#include "../plat-rk/rk-sdmmc-wifi.c"
-#endif //endif ---#ifdef CONFIG_SDMMC_RK29
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- iomux_set(MMC0_CMD);
- iomux_set(MMC0_CLKOUT);
- iomux_set(MMC0_D0);
- iomux_set(MMC0_D1);
- iomux_set(MMC0_D2);
- iomux_set(MMC0_D3);
-
- iomux_set_gpio_mode(iomux_mode_to_gpio(MMC0_DETN));
-
- gpio_request(RK30_PIN3_PA7, "sdmmc-power");
- gpio_direction_output(RK30_PIN3_PA7, GPIO_LOW);
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- #if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set_gpio_mode(iomux_gpio_to_mode(RK29SDK_SD_CARD_DETECT_N));
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO);
- #endif
- #else
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(MMC0_DETN);
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FMUX);
- #endif
- #endif
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) && defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- .status = rk29sdk_wifi_mmc0_status,
- .register_status_notify = rk29sdk_wifi_mmc0_status_register,
-#endif
-
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .power_en = RK29SDK_SD_CARD_PWR_EN,
- .power_en_level = RK29SDK_SD_CARD_PWR_EN_LEVEL,
-#else
- .power_en = INVALID_GPIO,
- .power_en_level = GPIO_LOW,
-#endif
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC0_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- .det_pin_info = {
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N, //INVALID_GPIO,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
- #endif
- },
-
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- iomux_set(MMC1_CMD);
- iomux_set(MMC1_CLKOUT);
- iomux_set(MMC1_D0);
- iomux_set(MMC1_D1);
- iomux_set(MMC1_D2);
- iomux_set(MMC1_D3);
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC) || defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC1_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- #if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
- .sdio_INT_gpio = RK29SDK_WIFI_SDIO_CARD_INT,
- #endif
-
- .det_pin_info = {
-#if defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- #else
- .io = INVALID_GPIO,
- #endif
-
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-
- .enable_sd_wakeup = 0,
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-/**************************************************************************************************
- * the end of setting for SDMMC devices
-**************************************************************************************************/
-
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = RK30_PIN0_PB2,
- .batt_low_pin = INVALID_GPIO,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = RK30_PIN0_PA6,
- .usb_det_pin = INVALID_GPIO,
- .dc_det_level = GPIO_LOW,
- .charge_ok_level = GPIO_HIGH,
-
- .reference_voltage = 1800, // the rK2928 is 3300;RK3066 and rk29 are 2500;rk3066B is 1800;
- .pull_up_res = 200, //divider resistance , pull-up resistor
- .pull_down_res = 120, //divider resistance , pull-down resistor
-
- .is_reboot_charging = 1,
- .save_capacity = 1 ,
- .low_voltage_protection = 3600,
-};
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-#ifdef CONFIG_RK30_PWM_REGULATOR
-static int pwm_voltage_map[] = {
- 800000,825000,850000, 875000,900000, 925000 ,950000, 975000,1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000,1375000
-};
-
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_cpu",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] =
-{
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
- .pwm_id = 1,
- .pwm_gpio = RK30_PIN3_PD4,
- .pwm_iomux_pwm = PWM1,
- .pwm_iomux_gpio = GPIO3_D4,
- .pwm_voltage = 1100000,
- .suspend_voltage = 1000000,
- .min_uV = 800000,
- .max_uV = 1375000,
- .coefficient = 575, //55.0%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-#endif
-
-#ifdef CONFIG_RFKILL_RK
-// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
-static struct rfkill_rk_platform_data rfkill_rk_platdata = {
- .type = RFKILL_TYPE_BLUETOOTH,
-
- .poweron_gpio = { // BT_REG_ON
- .io = INVALID_GPIO, //RK30_PIN3_PC7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_poweron",
- .fgpio = GPIO3_C7,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN3_PD1, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_reset",
- .fgpio = GPIO3_D1,
- },
- },
-
- .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
- .io = RK30_PIN3_PC6, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_wake",
- .fgpio = GPIO3_C6,
- },
- },
-
- .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .gpio = {
- .io = RK30_PIN0_PA5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
- .iomux = {
- .name = NULL,
- },
- },
- },
-
- .rts_gpio = { // UART_RTS, enable or disable BT's data coming
- .io = RK30_PIN1_PA3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_rts",
- .fgpio = GPIO1_A3,
- .fmux = UART0_RTSN,
- },
- },
-};
-
-static struct platform_device device_rfkill_rk = {
- .name = "rfkill_rk",
- .id = -1,
- .dev = {
- .platform_data = &rfkill_rk_platdata,
- },
-};
-#endif
-
-#if defined(CONFIG_GPS_RK)
-int rk_gps_io_init(void)
-{
- printk("%s \n", __FUNCTION__);
-
- rk30_mux_api_set(GPIO1B5_UART3RTSN_NAME, GPIO1B_GPIO1B5);//VCC_EN
- gpio_request(RK30_PIN1_PB5, NULL);
- gpio_direction_output(RK30_PIN1_PB5, GPIO_LOW);
-
- rk30_mux_api_set(GPIO1B4_UART3CTSN_GPSRFCLK_NAME, GPIO1B_GPSRFCLK);//GPS_CLK
- rk30_mux_api_set(GPIO1B2_UART3SIN_GPSMAG_NAME, GPIO1B_GPSMAG);//GPS_MAG
- rk30_mux_api_set(GPIO1B3_UART3SOUT_GPSSIG_NAME, GPIO1B_GPSSIG);//GPS_SIGN
-
- rk30_mux_api_set(GPIO1A6_UART1CTSN_SPI0CLK_NAME, GPIO1A_GPIO1A6);//SPI_CLK
- gpio_request(RK30_PIN1_PA6, NULL);
- gpio_direction_output(RK30_PIN1_PA6, GPIO_LOW);
-
- rk30_mux_api_set(GPIO1A5_UART1SOUT_SPI0TXD_NAME, GPIO1A_GPIO1A5);//SPI_MOSI
- gpio_request(RK30_PIN1_PA5, NULL);
- gpio_direction_output(RK30_PIN1_PA5, GPIO_LOW);
-
- rk30_mux_api_set(GPIO1A7_UART1RTSN_SPI0CSN0_NAME, GPIO1A_GPIO1A7);//SPI_CS
- gpio_request(RK30_PIN1_PA7, NULL);
- gpio_direction_output(RK30_PIN1_PA7, GPIO_LOW);
- return 0;
-}
-int rk_gps_power_up(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_power_down(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_reset_set(int level)
-{
- return 0;
-}
-int rk_enable_hclk_gps(void)
-{
- printk("%s \n", __FUNCTION__);
- clk_enable(clk_get(NULL, "hclk_gps"));
- return 0;
-}
-int rk_disable_hclk_gps(void)
-{
- printk("%s \n", __FUNCTION__);
- clk_disable(clk_get(NULL, "hclk_gps"));
- return 0;
-}
-struct rk_gps_data rk_gps_info = {
- .io_init = rk_gps_io_init,
- .power_up = rk_gps_power_up,
- .power_down = rk_gps_power_down,
- .reset = rk_gps_reset_set,
- .enable_hclk_gps = rk_enable_hclk_gps,
- .disable_hclk_gps = rk_disable_hclk_gps,
- .GpsSign = RK30_PIN1_PB3,
- .GpsMag = RK30_PIN1_PB2, //GPIO index
- .GpsClk = RK30_PIN1_PB4, //GPIO index
- .GpsVCCEn = RK30_PIN1_PB5, //GPIO index
- .GpsSpi_CSO = RK30_PIN1_PA4, //GPIO index
- .GpsSpiClk = RK30_PIN1_PA5, //GPIO index
- .GpsSpiMOSI = RK30_PIN1_PA7, //GPIO index
- .GpsIrq = IRQ_GPS,
- .GpsSpiEn = 0,
- .GpsAdcCh = 2,
- .u32GpsPhyAddr = RK30_GPS_PHYS,
- .u32GpsPhySize = RK30_GPS_SIZE,
-};
-
-struct platform_device rk_device_gps = {
- .name = "gps_hv5820b",
- .id = -1,
- .dev = {
- .platform_data = &rk_gps_info,
- }
- };
-#endif
-
-#if defined(CONFIG_MT5931_MT6622)
-static struct mt6622_platform_data mt6622_platdata = {
- .power_gpio = { // BT_REG_ON
- .io = RK30_PIN3_PD5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN0_PD7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .irq_gpio = {
- .io = RK30_PIN3_PD2,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- }
-};
-
-static struct platform_device device_mt6622 = {
- .name = "mt6622",
- .id = -1,
- .dev = {
- .platform_data = &mt6622_platdata,
- },
-};
-#endif
-
-static struct platform_device *devices[] __initdata = {
-
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- &rk29sdk_wifi_device,
-#endif
-
-#if defined(CONFIG_MT6620)
- &mt3326_device_gps,
-#endif
-
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
- &rk30_device_adc_battery,
-#endif
-#ifdef CONFIG_RFKILL_RK
- &device_rfkill_rk,
-#endif
-#ifdef CONFIG_GPS_RK
- &rk_device_gps,
-#endif
-#ifdef CONFIG_MT5931_MT6622
- &device_mt6622,
-#endif
-};
-
-
-static int rk_platform_add_display_devices(void)
-{
- struct platform_device *fb = NULL; //fb
- struct platform_device *lcdc0 = NULL; //lcdc0
- struct platform_device *lcdc1 = NULL; //lcdc1
- struct platform_device *bl = NULL; //backlight
-#ifdef CONFIG_FB_ROCKCHIP
- fb = &device_fb;
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B)
- lcdc0 = &device_lcdc0,
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B)
- lcdc1 = &device_lcdc1,
-#endif
-
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- bl = &rk29_device_backlight,
-#endif
- __rk_platform_add_display_devices(fb,lcdc0,lcdc1,bl);
-
- return 0;
-
-}
-
-// i2c
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_GS_MMA7660)
- {
- .type = "gs_mma7660",//gs_mma7660
- .addr = 0x4c,
- .flags = 0,
- .irq = MMA7660_INT_PIN,
- .platform_data = &mma7660_info,
- },
-#endif
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1d,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_GS_LIS3DH)
- {
- .type = "gs_lis3dh",
- .addr = 0x19, //0x19(SA0-->VCC), 0x18(SA0-->GND)
- .flags = 0,
- .irq = LIS3DH_INT_PIN,
- .platform_data = &lis3dh_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8975_info,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8975_info,
- },
-#endif
-#if defined (CONFIG_GYRO_L3G4200D)
- {
- .type = "l3g4200d_gryo",
- .addr = 0x69,
- .flags = 0,
- .irq = L3G4200D_INT_PIN,
- .platform_data = &l3g4200d_info,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RT5631)
- {
- .type = "rt5631",
- .addr = 0x1a,
- .flags = 0,
- },
-#endif
-};
-#endif
-
-int __sramdata g_pmic_type = 0;
-#ifdef CONFIG_I2C1_RK30
-#ifdef CONFIG_REGULATOR_ACT8846
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-#define ACT8846_HOST_IRQ RK30_PIN0_PB3
-
-static struct pmu_info act8846_dcdc_info[] = {
- {
- .name = "act_dcdc1", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- .suspend_vol = 1200000,
- },
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 900000,
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 900000,
- },
- {
- .name = "act_dcdc4", //vccio
- .min_uv = 3000000,
- .max_uv = 3000000,
- .suspend_vol = 2800000,
- },
-
-};
-static struct pmu_info act8846_ldo_info[] = {
- {
- .name = "act_ldo1", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "act_ldo2", //vdd12
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "act_ldo3", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo4", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo5", //vcctp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo6", //vcc_jetta
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo7", //vcc18
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo8", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- };
-
-#include "board-pmu-act8846.c"
-#endif
-
-#ifdef CONFIG_MFD_WM831X_I2C
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info wm8326_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "dcdc3", //ddr
- .min_uv = 1150000,
- .max_uv = 1150000,
- .suspend_vol = 1150000,
- },
- #ifdef CONFIG_MACH_RK3066_SDK
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3000000,
- },
- #else
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3000000,
- .max_uv = 3000000,
- .suspend_vol = 2800000,
- },
- #endif
-};
-
-static struct pmu_info wm8326_ldo_info[] = {
- {
- .name = "ldo1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo2", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo3", //
- .min_uv = 1100000,
- .max_uv = 1100000,
- .suspend_vol = 1100000,
- },
- {
- .name = "ldo4", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 1000000,
- },
- {
- .name = "ldo5", //vcc25
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo6", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo7", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- .suspend_vol = 2800000,
- },
- {
- .name = "ldo8", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo9", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo10", //flash_io
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
-};
-
-#include "board-pmu-wm8326.c"
-#endif
-
-#ifdef CONFIG_MFD_TPS65910
-#ifdef CONFIG_ARCH_RK3066B
-#define TPS65910_HOST_IRQ RK30_PIN0_PB3
-#else
-#define TPS65910_HOST_IRQ RK30_PIN6_PA4
-#endif
-
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info tps65910_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1100000,
- .max_uv = 1100000,
- },
- {
- .name = "vdd2", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vio", //vcc_io
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
-
-};
-static struct pmu_info tps65910_ldo_info[] = {
- {
- .name = "vpll", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "vdig2", //vdd_jetta
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vaux1", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "vaux2", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vaux33", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vmmc", //vcc30
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
- {
- .name = "vdac", //vcc18
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- };
-
-#include "board-pmu-tps65910.c"
-#endif
-
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_REGULATOR_ACT8846)
- {
- .type = "act8846",
- .addr = 0x5a,
- .flags = 0,
- .irq = ACT8846_HOST_IRQ,
- .platform_data=&act8846_data,
- },
-#endif
-#if defined (CONFIG_RTC_HYM8563)
- {
- .type = "rtc_hym8563",
- .addr = 0x51,
- .flags = 0,
- .irq = RK30_PIN0_PB5,
- },
-#endif
-#if defined (CONFIG_MFD_WM831X_I2C)
- {
- .type = "wm8326",
- .addr = 0x34,
- .flags = 0,
- .irq = RK30_PIN0_PB3,
- .platform_data = &wm831x_platdata,
- },
-#endif
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-};
-#endif
-
-void __sramfunc board_pmu_suspend(void)
-{
- #if defined (CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- board_pmu_act8846_suspend();
- #endif
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_suspend();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_suspend();
- #endif
-}
-
-void __sramfunc board_pmu_resume(void)
-{
- #if defined (CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- board_pmu_act8846_resume();
- #endif
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_resume();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_resume();
- #endif
-}
-
- int __sramdata gpio3d6_iomux,gpio3d6_do,gpio3d6_dir,gpio3d6_en;
-
-#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
-
-void __sramfunc rk30_pwm_logic_suspend_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
-
-// int gpio0d7_iomux,gpio0d7_do,gpio0d7_dir,gpio0d7_en;
- sram_udelay(10000);
- gpio3d6_iomux = grf_readl(GRF_GPIO3D_IOMUX);
- gpio3d6_do = grf_readl(GRF_GPIO3H_DO);
- gpio3d6_dir = grf_readl(GRF_GPIO3H_DIR);
- gpio3d6_en = grf_readl(GRF_GPIO3H_EN);
-
- grf_writel((1<<28), GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DIR);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DO);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_EN);
-#endif
-}
-void __sramfunc rk30_pwm_logic_resume_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- grf_writel((1<<28)|gpio3d6_iomux, GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|gpio3d6_en, GRF_GPIO3H_EN);
- grf_writel((1<<30)|gpio3d6_dir, GRF_GPIO3H_DIR);
- grf_writel((1<<30)|gpio3d6_do, GRF_GPIO3H_DO);
- sram_udelay(10000);
-
-#endif
-
-}
-extern void pwm_suspend_voltage(void);
-extern void pwm_resume_voltage(void);
-void rk30_pwm_suspend_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_suspend_voltage();
-#endif
-}
-void rk30_pwm_resume_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_resume_voltage();
-#endif
-}
-
-
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-#if defined (CONFIG_CT36X_TS)
- {
- .type = CT36X_NAME,
- .addr = 0x01,
- .flags = 0,
- .platform_data = &ct36x_info,
- },
-#endif
-#if defined (CONFIG_LS_CM3217)
- {
- .type = "lightsensor",
- .addr = 0x10,
- .flags = 0,
- .platform_data = &cm3217_info,
- },
-#endif
-#if defined (CONFIG_TOUCHSCREEN_GSLX680)
- {
- .type = "gslX680",
- .addr = 0x40,
- .flags = 0,
- .platform_data =&gslx680_info,
- },
-#endif
-#if defined (CONFIG_TOUCHSCREEN_86V_GT811_IIC)
-{
- .type = "gt811_ts",
- .addr = 0x5d,
- .flags = 0,
- .irq = TOUCH_INT_PIN,
- .platform_data = >811_info,
-},
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C4_RK30
-static struct i2c_board_info __initdata i2c4_info[] = {
-#ifdef CONFIG_MFD_RK610
- {
- .type = "rk610_ctl",
- .addr = 0x40,
- .flags = 0,
- .platform_data = &rk610_ctl_pdata,
- },
-#ifdef CONFIG_RK610_TVOUT
- {
- .type = "rk610_tvout",
- .addr = 0x42,
- .flags = 0,
- },
-#endif
-#ifdef CONFIG_HDMI_RK610
- {
- .type = "rk610_hdmi",
- .addr = 0x46,
- .flags = 0,
- .irq = INVALID_GPIO,
- },
-#endif
-#ifdef CONFIG_SND_SOC_RK610
- {//RK610_CODEC addr from 0x60 to 0x80 (0x60~0x80)
- .type = "rk610_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- .platform_data = &rk610_codec_pdata,
- },
-#endif
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO// RK30_PIN2_PD6 //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO//RK30_PIN2_PD7 //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- //set iomux (gpio) here
- //rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME, GPIO2D_GPIO2D7);
- //rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME, GPIO2D_GPIO2D6);
-
- return 0;
-}
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C4_RK30
- i2c_register_board_info(4, i2c4_info, ARRAY_SIZE(i2c4_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(5, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-
-#define POWER_ON_PIN RK30_PIN0_PA0 //power_hold
-static void rk30_pm_power_off(void)
-{
- printk(KERN_ERR "rk30_pm_power_off start...\n");
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
-#if defined(CONFIG_MFD_WM831X)
- wm831x_set_bits(Wm831x,WM831X_GPIO_LEVEL,0x0001,0x0000); //set sys_pwr 0
- wm831x_device_shutdown(Wm831x);//wm8326 shutdown
-#endif
-#if defined(CONFIG_REGULATOR_ACT8846)
- if (pmic_is_tps65910()) {
- printk("enter dcdet===========\n");
- if((gpio_get_value (RK30_PIN0_PB2) == GPIO_LOW)||(gpio_get_value (RK30_PIN0_PA7) == GPIO_HIGH))
- {
- printk("enter restart===========\n");
- arm_pm_restart(0, NULL);
- }
- //act8931_device_shutdown();
- }
-#endif
- while (1);
-}
-
-static void __init machine_rk30_board_init(void)
-{
- //avs_init();
- gpio_request(POWER_ON_PIN, "poweronpin");
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
- pm_power_off = rk30_pm_power_off;
-
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
-
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- rk_platform_add_display_devices();
- board_usb_detect_init(RK30_PIN0_PA7);
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- rk29sdk_wifi_bt_gpio_control_init();
-#endif
-
-#if defined(CONFIG_MT6620)
- clk_set_rate(clk_get_sys("rk_serial.1", "uart"), 48*1000000);
-#endif
-
-#if defined(CONFIG_MT5931_MT6622)
- clk_set_rate(clk_get_sys("rk_serial.0", "uart"), 24*1000000);
-#endif
-}
-
-static void __init rk30_reserve(void)
-{
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0 buf", get_fb_size());
- resource_fb[0].end = resource_fb[0].start + get_fb_size()- 1;
-#if 0
- resource_fb[1].start = board_mem_reserve_add("ipp buf", RK30_FB0_MEM_SIZE);
- resource_fb[1].end = resource_fb[1].start + RK30_FB0_MEM_SIZE - 1;
-#endif
-
-#if defined(CONFIG_FB_ROTATE) || !defined(CONFIG_THREE_FB_BUFFER)
- resource_fb[2].start = board_mem_reserve_add("fb2 buf",get_fb_size());
- resource_fb[2].end = resource_fb[2].start + get_fb_size() - 1;
-#endif
-#endif
-
-
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
-
-#ifdef CONFIG_GPS_RK
- //it must be more than 8MB
- rk_gps_info.u32MemoryPhyAddr = board_mem_reserve_add("gps", SZ_8M);
-#endif
- board_mem_reserved();
-}
-
-/**
- * dvfs_cpu_logic_table: table for arm and logic dvfs
- * @frequency : arm frequency
- * @cpu_volt : arm voltage depend on frequency
- * @logic_volt : logic voltage arm requests depend on frequency
- * comments : min arm/logic voltage
- */
-static struct cpufreq_frequency_table dvfs_arm_table[] = {
- {.frequency = 312 * 1000, .index = 900 * 1000},
- {.frequency = 504 * 1000, .index = 950 * 1000},
- {.frequency = 816 * 1000, .index = 1000 * 1000},
- {.frequency = 1008 * 1000, .index = 1075 * 1000},
- {.frequency = 1200 * 1000, .index = 1150 * 1000},
- //{.frequency = 1416 * 1000, .index = 1250 * 1000},
- //{.frequency = 1608 * 1000, .index = 1300 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- {.frequency = 100 * 1000, .index = 1000 * 1000},
- {.frequency = 200 * 1000, .index = 1000 * 1000},
- {.frequency = 266 * 1000, .index = 1050 * 1000},
- {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1100 * 1000},
- //{.frequency = 600 * 1000, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 950 * 1000},
- {.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = 1000 * 1000},
- {.frequency = 400 * 1000 + DDR_FREQ_NORMAL, .index = 1100 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-//#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
-//static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
-//static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
-
-void __init board_clock_init(void)
-{
- rk30_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
- //dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "cpu"), dvfs_arm_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
-}
-
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk30_fixup,
- .reserve = &rk30_reserve,
- .map_io = rk30_map_io,
- .init_irq = rk30_init_irq,
- .timer = &rk30_timer,
- .init_machine = machine_rk30_board_init,
-MACHINE_END
+++ /dev/null
-/*****************************************************************************************
- * arch/arm/mach-rkxx/baord-xxx-sdmmc-config.c
- *
- * Copyright (C) 2013 ROCKCHIP, Inc.
- *
- * Description:
- * define the gpio for SD-MMC-SDIO-Wifi functions according to your own projects.
- *
- * Author: Michael Xie
- * 15 Jan,2013
- * E-mail: xbw@rock-chips.com
- *
- ******************************************************************************************/
-
-/*
-** If you select the macro of CONFIG_SDMMC0_RK29_WRITE_PROTECT, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define SDMMC0_WRITE_PROTECT_PIN RK30_PIN3_PB2 //According to your own project to set the value of write-protect-pin.
-//#define SDMMC0_WRITE_PROTECT_ENABLE_VALUE GPIO_HIGH
-
-/*
-** If you select the macro of CONFIG_SDMMC1_RK29_WRITE_PROTECT, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define SDMMC1_WRITE_PROTECT_PIN RK30_PIN3_PB3 //According to your own project to set the value of write-protect-pin.
-//#define SDMMC1_WRITE_PROTECT_ENABLE_VALUE GPIO_HIGH
-
-/*
-** If you select the macro of CONFIG_RK29_SDIO_IRQ_FROM_GPIO, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define RK29SDK_WIFI_SDIO_CARD_INT RK30_PIN3_PD2
-
-
-/*
-* define sdcard PowerEn-pin
-*/
-#define RK29SDK_SD_CARD_PWR_EN RK30_PIN3_PA1
-#define RK29SDK_SD_CARD_PWR_EN_LEVEL GPIO_LOW
-int rk31sdk_get_sdmmc0_pin_io_voltage(void)
-{
- int voltage;
-#define RK31SDK_SET_SDMMC0_PIN_VOLTAGE
-
- /**************************************************************************************
- ** Please tell me how much voltage of your SDMMC0-pin in your project.
- **
- ** ÀýÈç: ÓеÄÏîÄ¿£¬ËüµÄSDMMC0ËùÔÚµÄRKÖ÷¿ØµÄIO×飬ÏëÓÃ1.8V, ¶ø¿¨±¾ÉíÓÃ3.3V,
- ** ¶øÖмäͨ¹ý¸öµçƽת»».ÄÇô£¬Äú´Ëʱ£¬Ó¦¸ÃÉèÖÃÏÂÃæµÄvoltageֵΪ 1.8V(¼´1800mv)
- ***************************************************************************************/
- voltage = 3300; //default the voltage 3300mv.
-
- return voltage;
-}
-
-/*
-* define the card-detect-pin.
-*/
-#define RK29SDK_SD_CARD_DETECT_N RK30_PIN3_PB0 //According to your own project to set the value of card-detect-pin.
-#define RK29SDK_SD_CARD_INSERT_LEVEL GPIO_LOW // set the voltage of insert-card. Please pay attention to the default setting.
-
-//wake up host gpio
-#define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
-#define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
-
-/*
-* Define wifi module's power and reset gpio, and gpio sensitive level.
-* Please set the value according to your own project.
-*
-* Well, you just own engineering module to set the value in the corresponding module branch.
-* Otherwise, you do not define this macro, eliminate it.
-*
-*/
-#if defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU) || defined(CONFIG_RTL8723AU) || defined(CONFIG_MT7601)
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN0_PD5//RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_LOW//GPIO_HIGH
-
-#elif defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319) || defined(CONFIG_RKWIFI) || defined(CONFIG_RTL8189ES)
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN2_PA7
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
-
-#elif defined(CONFIG_MT5931_MT6622) || defined(CONFIG_MT5931)
-
- #ifdef CONFIG_MACH_RK3168_LR097
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- //#define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- //#define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
-
- #else
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
-// #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
-// #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #endif
-
-#elif defined(CONFIG_MT6620)
- #define COMBO_MODULE_MT6620_CDT 0 // to control antsel2,antsel3 and gps_lan foot when using AcSip or Cdtech chip.
- //- 1--use Cdtech chip; 0--unuse CDT chip
-
- //power, PMU_EN
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- //reset, DAIRST,SYSRST_B
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- //VDDIO
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL RK30_PIN0_PD2 //You do not get control of the foot, and you do not need to define the macro
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_ENABLE_VALUE GPIO_HIGH
- //WIFI_INT_B
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
- //BGF_INT_B
- #define RK30SDK_WIFI_GPIO_BGF_INT_B RK30_PIN0_PA5
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_ENABLE_VALUE GPIO_HIGH
- //GPS_SYNC
- #define RK30SDK_WIFI_GPIO_GPS_SYNC RK30_PIN3_PC6
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_ENABLE_VALUE GPIO_HIGH
-
- #if COMBO_MODULE_MT6620_CDT
- //ANTSEL2
- #define RK30SDK_WIFI_GPIO_ANTSEL2 RK30_PIN4_PD4
- #define RK30SDK_WIFI_GPIO_ANTSEL2_ENABLE_VALUE GPIO_LOW //use 6620 in CDT chip, LOW--work; High--no work.
- //ANTSEL3
- #define RK30SDK_WIFI_GPIO_ANTSEL3 RK30_PIN4_PD3
- #define RK30SDK_WIFI_GPIO_ANTSEL3_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- //GPS_LAN
- #define RK30SDK_WIFI_GPIO_GPS_LAN RK30_PIN4_PD6
- #define RK30SDK_WIFI_GPIO_GPS_LAN_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- #endif // #if COMBO_MODULE_MT6620_CDT--#endif
-#endif
-
-int rk31sdk_get_sdio_wifi_voltage(void)
-{
- int voltage;
-
- /******************************************************************************
- ** Please tell me how much wifi-module uses voltage in your project.
- ******************************************************************************/
-#if defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319) || defined(CONFIG_RKWIFI)
- voltage = 1800 ; //power 1800mV
-
-#elif defined(CONFIG_MT5931_MT6622)||defined(CONFIG_MT5931)
- voltage = 1800 ; //power 1800V
-#elif defined(CONFIG_MT6620)
- voltage = 2800 ; //power 2800V
-#elif defined(CONFIG_RDA5990)||defined(CONFIG_RTL8723AS)
- voltage = 3300 ; //power 3300V
-#else
- //default, sdio use 3.0V
- voltage = 3000 ; //power 3000V
-#endif
-
- return voltage;
-}
-
-
-
+++ /dev/null
-/*
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <mach/dvfs.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <linux/rk_fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/mfd/tps65910.h>
-#include <linux/regulator/act8846.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-#if defined(CONFIG_CT36X_TS)
-#include <linux/ct36x.h>
-#endif
-#include <linux/regulator/act8931.h>
-#if defined(CONFIG_MFD_RK610)
-#include <linux/mfd/rk610_core.h>
-#endif
-#if defined(CONFIG_MFD_RK616)
-#include <linux/mfd/rk616.h>
-#endif
-
-#ifdef CONFIG_TOUCHSCREEN_GT82X_IIC
-#include <linux/goodix_touch_82x.h>
-#endif
-
-#if defined(CONFIG_RK_HDMI)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-#if defined(CONFIG_GPS_RK)
-#include "../../../drivers/misc/gps/rk_gps/rk_gps.h"
-#endif
-
-#if defined(CONFIG_MT6620)
-#include <linux/gps.h>
-#endif
-
-#include "board-rk3168-86v-camera.c"
-#include <plat/key.h>
-
-
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK30_PIN0_PA4,
- .active_low = PRESS_LEV_LOW,
- .wakeup = 1,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .adc_value = 150,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .adc_value = 1,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = 1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
-#if defined(CONFIG_CT36X_TS)
-
-#define TOUCH_MODEL 363
-#define TOUCH_MAX_X 1280
-#define TOUCH_MAX_y 800
-#define TOUCH_RESET_PIN RK30_PIN0_PB6
-#define TOUCH_INT_PIN RK30_PIN1_PB7
-
-static struct ct36x_platform_data ct36x_info = {
- .model = TOUCH_MODEL,
- .x_max = TOUCH_MAX_X,
- .y_max = TOUCH_MAX_y,
-
- .rst_io = {
- .gpio = TOUCH_RESET_PIN,
- .active_low = 1,
- },
- .irq_io = {
- .gpio = TOUCH_INT_PIN,
- .active_low = 1,
- },
- .orientation = {1, 0, 1, 0},
-};
-#endif
-
-#if defined(CONFIG_TOUCHSCREEN_GSLX680)
-#define TOUCH_RESET_PIN RK30_PIN0_PB6
-#define TOUCH_EN_PIN NULL
-#define TOUCH_INT_PIN RK30_PIN1_PB7
-
-int gslx680_init_platform_hw(void)
-{
-
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("gslx680_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("gslx680_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, GPIO_HIGH);
- mdelay(10);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- mdelay(10);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- msleep(300);
- return 0;
-
-}
-
-struct ts_hw_data gslx680_info = {
- .reset_gpio = TOUCH_RESET_PIN,
- .touch_en_gpio = TOUCH_INT_PIN,
- .init_platform_hw = gslx680_init_platform_hw,
-};
-#endif
-
-
-#if defined(CONFIG_TOUCHSCREEN_GSLX680_RK3168)
-#define TOUCH_RESET_PIN RK30_PIN0_PB6
-#define TOUCH_EN_PIN NULL
-#define TOUCH_INT_PIN RK30_PIN1_PB7
-
-int gslx680_init_platform_hw(void)
-{
-
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("gslx680_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("gslx680_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, GPIO_HIGH);
- mdelay(10);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- mdelay(10);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- msleep(300);
- return 0;
-
-}
-
-struct ts_hw_data gslx680_info = {
- .reset_gpio = TOUCH_RESET_PIN,
- .touch_en_gpio = TOUCH_INT_PIN,
- .init_platform_hw = gslx680_init_platform_hw,
-};
-#endif
-
-#if defined (CONFIG_TOUCHSCREEN_86V_GT811_IIC)
-#define TOUCH_RESET_PIN RK30_PIN0_PB6
-#define TOUCH_INT_PIN RK30_PIN1_PB7
-int gt811_init_platform_hw(void)
-{
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("gt811_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("gt811_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- //gpio_pull_updown(TOUCH_INT_PIN, 1);
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- msleep(500);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- mdelay(100);
-
- return 0;
-}
-
-
-static struct goodix_platform_data gt811_info = {
- .model= 811,
- .init_platform_hw= gt811_init_platform_hw,
-
-};
-#endif
-
-#ifdef CONFIG_TOUCHSCREEN_GT82X_IIC
-#define TOUCH_ENABLE_PIN INVALID_GPIO
-#define TOUCH_RESET_PIN RK30_PIN0_PB6//RK30_PIN4_PD0
-#define TOUCH_INT_PIN RK30_PIN1_PB7//RK30_PIN4_PC2
-int goodix_init_platform_hw(void)
-{
- int ret;
-
- //rk30_mux_api_set(GPIO4D0_SMCDATA8_TRACEDATA8_NAME, GPIO4D_GPIO4D0); //hjc
- //rk30_mux_api_set(GPIO4C2_SMCDATA2_TRACEDATA2_NAME, GPIO4C_GPIO4C2); //hjc
- //printk("%s:0x%x,0x%x\n",__func__,rk30_mux_api_get(GPIO4D0_SMCDATA8_TRACEDATA8_NAME),rk30_mux_api_get(GPIO4C2_SMCDATA2_TRACEDATA2_NAME));
- if (TOUCH_ENABLE_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_ENABLE_PIN, "goodix power pin");
- if (ret != 0) {
- gpio_free(TOUCH_ENABLE_PIN);
- printk("goodix power error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_ENABLE_PIN, 0);
- gpio_set_value(TOUCH_ENABLE_PIN, GPIO_LOW);
- msleep(100);
- }
-
- if (TOUCH_RESET_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_RESET_PIN, "goodix reset pin");
- if (ret != 0) {
- gpio_free(TOUCH_RESET_PIN);
- printk("goodix gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- gpio_set_value(TOUCH_RESET_PIN, GPIO_LOW);
- msleep(10);
- gpio_set_value(TOUCH_RESET_PIN, GPIO_HIGH);
- msleep(500);
- }
- return 0;
-}
-u8 ts82x_config_data[] = {
- 0x65,0x00,0x04,0x00,0x03,0x00,0x0A,0x0D,0x1E,0xE7,
- 0x32,0x03,0x08,0x10,0x48,0x42,0x42,0x20,0x00,0x01,
- 0x60,0x60,0x4B,0x6E,0x0E,0x0D,0x0C,0x0B,0x0A,0x09,
- 0x08,0x07,0x06,0x05,0x04,0x03,0x02,0x01,0x00,0x1D,
- 0x1C,0x1B,0x1A,0x19,0x18,0x17,0x16,0x15,0x14,0x13,
- 0x12,0x11,0x10,0x0F,0x50,0x00,0x00,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2B,0x00,0x00,
- 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x00
-};
-static struct goodix_i2c_rmi_platform_data ts82x_pdata = {
- .gpio_shutdown = TOUCH_ENABLE_PIN,
- .gpio_irq = TOUCH_INT_PIN,
- .gpio_reset = TOUCH_RESET_PIN,
- .irq_edge = 1, /* 0:rising edge, 1:falling edge */
-
- .ypol = 1,
- .swap_xy = 1,
- .xpol = 0,
- .xmax = 800,
- .ymax = 600,
- .config_info_len =ARRAY_SIZE(ts82x_config_data),
- .config_info = ts82x_config_data,
- .init_platform_hw= goodix_init_platform_hw,
-};
-#endif
-
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-#define PWM_ID 3
-#define PWM_MODE PWM3
-#define PWM_EFFECT_VALUE 0// 1
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-#define BL_EN_PIN RK30_PIN0_PA2
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
-
- iomux_set(PWM_MODE);
- msleep(100);
-#ifdef LCD_DISP_ON_PIN
- ret = gpio_request(BL_EN_PIN, NULL);
- if (ret != 0) {
- gpio_free(BL_EN_PIN);
- }
-
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
-
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0, pwm_gpio;
-
-#ifdef LCD_DISP_ON_PIN
- gpio_free(BL_EN_PIN);
-#endif
-
- pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
- gpio_request(pwm_gpio, NULL);
- gpio_direction_output(pwm_gpio, GPIO_LOW);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret = 0, pwm_gpio;
-
- pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
- if (gpio_request(pwm_gpio, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- gpio_direction_output(pwm_gpio, GPIO_LOW);
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, !BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- int pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
-
- gpio_free(pwm_gpio);
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
- msleep(150);
- gpio_direction_output(BL_EN_PIN, 1);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .min_brightness = 33,
- .max_brightness=255,
- .brightness_mode =1,
- .pre_div = 20 * 1000, // pwm output clk: 20k;
- .pwm_id = PWM_ID,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-#endif
-
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN RK30_PIN0_PB7
-
-static int mma8452_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data mma8452_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma8452_init_platform_hw,
- .orientation = {-1, 0, 0, 0, 0, 1, 0, 1, 0},
-};
-#endif
-
-/*MMA7660 gsensor*/
-#if defined (CONFIG_GS_MMA7660)
-#define MMA7660_INT_PIN RK30_PIN0_PB7
-
-static int mma7660_init_platform_hw(void)
-{
- //rk30_mux_api_set(GPIO1B2_SPI_RXD_UART1_SIN_NAME, GPIO1B_GPIO1B2);
-
- return 0;
-}
-
-static struct sensor_platform_data mma7660_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma7660_init_platform_hw,
-#ifndef CONFIG_MFD_RK616
- #ifdef CONFIG_TOUCHSCREEN_GSLX680_RK3168
- .orientation = {-1, 0, 0, 0, -1, 0, 0, 0, 1},
- #else
- .orientation = {0, -1, 0, -1, 0, 0, 0, 0, -1},
- #endif
-#else
- .orientation = {1, 0, 0, 0, -1, 0, 0, 0, -1},
-#endif
-};
-#endif
-
-#if defined (CONFIG_GS_MXC6225)
-#define MXC6225_INT_PIN RK30_PIN0_PB7
-
-static int mxc6225_init_platform_hw(void)
-{
-// rk30_mux_api_set(GPIO1B1_SPI_TXD_UART1_SOUT_NAME, GPIO1B_GPIO1B1);
- return 0;
-}
-
-static struct sensor_platform_data mxc6225_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 0,
- .poll_delay_ms = 30,
- .init_platform_hw = mxc6225_init_platform_hw,
- .orientation = { -1, 0, 0, 0, -1, 0, 0, 0, 1},//mxc6225 only report x and y
-};
-#endif
-
-
-#if defined (CONFIG_GS_LIS3DH)
-#define LIS3DH_INT_PIN RK30_PIN0_PB7
-
-static int lis3dh_init_platform_hw(void)
-{
-
- return 0;
-}
-
-static struct sensor_platform_data lis3dh_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lis3dh_init_platform_hw,
- .orientation = {1, 0, 0, 0, 1, 0, 0, 0, 1},
-};
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
-static struct sensor_platform_data akm8975_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-#if defined (CONFIG_COMPASS_AK8963)
-static struct sensor_platform_data akm8963_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {0, 1, 0},
- {1, 0, 0},
- {0, 0, -1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {0, -1, 0},
- {-1, 0, 0},
- {0, 0, -1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-
-#if defined(CONFIG_GYRO_L3G4200D)
-
-#include <linux/l3g4200d.h>
-#define L3G4200D_INT_PIN RK30_PIN0_PB4
-
-static int l3g4200d_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data l3g4200d_info = {
- .type = SENSOR_TYPE_GYROSCOPE,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
- .init_platform_hw = l3g4200d_init_platform_hw,
- .x_min = 40,//x_min,y_min,z_min = (0-100) according to hardware
- .y_min = 40,
- .z_min = 20,
-};
-
-#endif
-
-#ifdef CONFIG_LS_CM3217
-static struct sensor_platform_data cm3217_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 0,
- .poll_delay_ms = 500,
-};
-
-#endif
-
-#ifdef CONFIG_FB_ROCKCHIP
-
-#define LCD_CS_PIN RK30_PIN3_PD4//INVALID_GPIO
-#define LCD_CS_VALUE GPIO_HIGH
-
-#define LCD_EN_PIN RK30_PIN0_PB0
-#define LCD_EN_VALUE GPIO_LOW
-
-#define LCD_STBYB_RXD_MODE SPI1_RXD
-
-
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
- int stbyb_gpio;
-
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_CS_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_CS_PIN);
- printk(KERN_ERR "request lcd cs pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_CS_PIN, LCD_CS_VALUE);
- }
- }
-
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_EN_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_EN_PIN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_EN_PIN, LCD_EN_VALUE);
- }
- }
-
- stbyb_gpio = iomux_mode_to_gpio(LCD_STBYB_RXD_MODE);
- gpio_request(stbyb_gpio, "stbyb");
- gpio_direction_output(stbyb_gpio, GPIO_HIGH);
- gpio_set_value(stbyb_gpio,GPIO_HIGH);
-
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, !LCD_CS_VALUE);
- }
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, !LCD_EN_VALUE);
- }
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE);
- }
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
- }
- return 0;
-}
-
-#if defined(CONFIG_LCDC0_RK3066B)
-struct rk29fb_info lcdc0_screen_info = {
-#if defined(CONFIG_RK_HDMI) && defined(CONFIG_HDMI_SOURCE_LCDC0)&& defined(CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL)
- .prop = EXTEND, //primary display device
- .io_init = NULL,
- .io_disable = NULL,
- .io_enable = NULL,
- .set_screen_info = hdmi_init_lcdc,
-#else
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-#endif
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B)
-struct rk29fb_info lcdc1_screen_info = {
-#if defined(CONFIG_RK_HDMI) && defined(CONFIG_HDMI_SOURCE_LCDC1) && defined(CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL)
- .prop = EXTEND, //primary display device
- .io_init = NULL,
- .io_disable = NULL,
- .io_enable = NULL,
- .set_screen_info = hdmi_init_lcdc,
-#else
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-#endif
-
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B)
-static struct resource resource_lcdc0[] = {
- [0] = {
- .name = "lcdc0 reg",
- .start = RK30_LCDC0_PHYS,
- .end = RK30_LCDC0_PHYS + RK30_LCDC0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc0 irq",
- .start = IRQ_LCDC0,
- .end = IRQ_LCDC0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc0 = {
- .name = "rk30-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc0),
- .resource = resource_lcdc0,
- .dev = {
- .platform_data = &lcdc0_screen_info,
- },
-};
-#endif
-#if defined(CONFIG_LCDC1_RK3066B)
-static struct resource resource_lcdc1[] = {
- [0] = {
- .name = "lcdc1 reg",
- .start = RK30_LCDC1_PHYS,
- .end = RK30_LCDC1_PHYS + RK30_LCDC1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc1 irq",
- .start = IRQ_LCDC1,
- .end = IRQ_LCDC1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc1 = {
- .name = "rk30-lcdc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resource_lcdc1),
- .resource = resource_lcdc1,
- .dev = {
- .platform_data = &lcdc1_screen_info,
- },
-};
-#endif
-
-#if defined(CONFIG_MFD_RK610)
-#define RK610_RST_PIN RK30_PIN3_PB2
-static int rk610_power_on_init(void)
-{
- int ret;
- if(RK610_RST_PIN != INVALID_GPIO)
- {
- ret = gpio_request(RK610_RST_PIN, "rk610 reset");
- if (ret)
- {
- printk(KERN_ERR "rk610_control_probe request gpio fail\n");
- }
- else
- {
- gpio_direction_output(RK610_RST_PIN, GPIO_HIGH);
- msleep(100);
- gpio_direction_output(RK610_RST_PIN, GPIO_LOW);
- msleep(100);
- gpio_set_value(RK610_RST_PIN, GPIO_HIGH);
- }
- }
-
- return 0;
-
-}
-
-
-static struct rk610_ctl_platform_data rk610_ctl_pdata = {
- .rk610_power_on_init = rk610_power_on_init,
-};
-#endif
-
-#ifdef CONFIG_SND_SOC_RK610
-static int rk610_codec_io_init(void)
-{
-//if need iomux.
-//Must not gpio_request
- return 0;
-}
-
-static struct rk610_codec_platform_data rk610_codec_pdata = {
- .spk_ctl_io = RK30_PIN2_PD7,
- .io_init = rk610_codec_io_init,
- .boot_depop = 1,
-};
-#endif
-
-#if defined(CONFIG_MFD_RK616)
-#define RK616_RST_PIN RK30_PIN3_PB2
-#define RK616_PWREN_PIN RK30_PIN0_PA3
-#define RK616_SCL_RATE (100*1000) //i2c scl rate
-static int rk616_power_on_init(void)
-{
- int ret;
-
- if(RK616_PWREN_PIN != INVALID_GPIO)
- {
- ret = gpio_request(RK616_PWREN_PIN, "rk616 pwren");
- if (ret)
- {
- printk(KERN_ERR "rk616 pwren gpio request fail\n");
- }
- else
- {
- gpio_direction_output(RK616_PWREN_PIN,GPIO_HIGH);
- }
- }
-
- if(RK616_RST_PIN != INVALID_GPIO)
- {
- ret = gpio_request(RK616_RST_PIN, "rk616 reset");
- if (ret)
- {
- printk(KERN_ERR "rk616 reset gpio request fail\n");
- }
- else
- {
- gpio_direction_output(RK616_RST_PIN, GPIO_HIGH);
- msleep(100);
- gpio_direction_output(RK616_RST_PIN, GPIO_LOW);
- msleep(100);
- gpio_set_value(RK616_RST_PIN, GPIO_HIGH);
- }
- }
-
- return 0;
-
-}
-
-
-static struct rk616_platform_data rk616_pdata = {
- .power_init = rk616_power_on_init,
- .scl_rate = RK616_SCL_RATE,
- .lcd0_func = INPUT, //port lcd0 as input
- .lcd1_func = OUTPUT, //port lcd1 as input
- .lvds_ch_nr = 1, //the number of used lvds channel
- .hdmi_irq = RK30_PIN2_PD6,
- .spk_ctl_gpio = RK30_PIN2_PD7,
-};
-#endif
-
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and sdio.noted by xbw at 2012-03-05
-**************************************************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "board-rk3168-86v-sdmmc-config.c"
-#include "../plat-rk/rk-sdmmc-ops.c"
-#include "../plat-rk/rk-sdmmc-wifi.c"
-#endif //endif ---#ifdef CONFIG_SDMMC_RK29
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- iomux_set(MMC0_CMD);
- iomux_set(MMC0_CLKOUT);
- iomux_set(MMC0_D0);
- iomux_set(MMC0_D1);
- iomux_set(MMC0_D2);
- iomux_set(MMC0_D3);
-
- iomux_set_gpio_mode(iomux_mode_to_gpio(MMC0_DETN));
-
- gpio_request(RK30_PIN3_PA7, "sdmmc-power");
- gpio_direction_output(RK30_PIN3_PA7, GPIO_LOW);
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- #if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set_gpio_mode(iomux_gpio_to_mode(RK29SDK_SD_CARD_DETECT_N));
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO);
- #endif
- #else
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(MMC0_DETN);
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FMUX);
- #endif
- #endif
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) && defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- .status = rk29sdk_wifi_mmc0_status,
- .register_status_notify = rk29sdk_wifi_mmc0_status_register,
-#endif
-
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .power_en = RK29SDK_SD_CARD_PWR_EN,
- .power_en_level = RK29SDK_SD_CARD_PWR_EN_LEVEL,
-#else
- .power_en = INVALID_GPIO,
- .power_en_level = GPIO_LOW,
-#endif
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC0_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- .det_pin_info = {
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N, //INVALID_GPIO,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
- #endif
- },
-
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- iomux_set(MMC1_CMD);
- iomux_set(MMC1_CLKOUT);
- iomux_set(MMC1_D0);
- iomux_set(MMC1_D1);
- iomux_set(MMC1_D2);
- iomux_set(MMC1_D3);
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC) || defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC1_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- #if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
- .sdio_INT_gpio = RK29SDK_WIFI_SDIO_CARD_INT,
- #ifdef USE_SDIO_INT_LEVEL
- .sdio_INT_level = RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE,
- #endif
- #endif
-
- .det_pin_info = {
-#if defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- #else
- .io = INVALID_GPIO,
- #endif
-
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-
- .enable_sd_wakeup = 0,
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-/**************************************************************************************************
- * the end of setting for SDMMC devices
-**************************************************************************************************/
-
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = RK30_PIN0_PB2,
- .batt_low_pin = INVALID_GPIO,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = RK30_PIN0_PA6,
- .usb_det_pin = INVALID_GPIO,
- .dc_det_level = GPIO_LOW,
- .charge_ok_level = GPIO_HIGH,
-
- .reference_voltage = 1800, // the rK2928 is 3300;RK3066 and rk29 are 2500;rk3066B is 1800;
- .pull_up_res = 200, //divider resistance , pull-up resistor
- .pull_down_res = 120, //divider resistance , pull-down resistor
-
- .is_reboot_charging = 1,
- .save_capacity = 1 ,
- .low_voltage_protection = 3600,
-};
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-#ifdef CONFIG_RK30_PWM_REGULATOR
-static int pwm_voltage_map[] = {
- 800000,825000,850000, 875000,900000, 925000 ,950000, 975000,1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000,1375000
-};
-
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_cpu",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] =
-{
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
- .pwm_id = 1,
- .pwm_gpio = RK30_PIN3_PD4,
- .pwm_iomux_pwm = PWM1,
- .pwm_iomux_gpio = GPIO3_D4,
- .pwm_voltage = 1100000,
- .suspend_voltage = 1000000,
- .min_uV = 800000,
- .max_uV = 1375000,
- .coefficient = 575, //55.0%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-#endif
-
-#ifdef CONFIG_RFKILL_RK
-// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
-static struct rfkill_rk_platform_data rfkill_rk_platdata = {
- .type = RFKILL_TYPE_BLUETOOTH,
-
- .poweron_gpio = { // BT_REG_ON
- .io = INVALID_GPIO, //RK30_PIN3_PC7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_poweron",
- .fgpio = GPIO3_C7,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN3_PD1, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_reset",
- .fgpio = GPIO3_D1,
- },
- },
-
- .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
- .io = RK30_PIN3_PC6, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_wake",
- .fgpio = GPIO3_C6,
- },
- },
-
- .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .gpio = {
- .io = RK30_PIN0_PA5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
- .iomux = {
- .name = NULL,
- },
- },
- },
-
- .rts_gpio = { // UART_RTS, enable or disable BT's data coming
- .io = RK30_PIN1_PA3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_rts",
- .fgpio = GPIO1_A3,
- .fmux = UART0_RTSN,
- },
- },
-};
-
-static struct platform_device device_rfkill_rk = {
- .name = "rfkill_rk",
- .id = -1,
- .dev = {
- .platform_data = &rfkill_rk_platdata,
- },
-};
-#endif
-
-#if defined(CONFIG_GPS_RK)
-int rk_gps_io_init(void)
-{
- printk("%s \n", __FUNCTION__);
-
- rk30_mux_api_set(GPIO1B5_UART3RTSN_NAME, GPIO1B_GPIO1B5);//VCC_EN
- gpio_request(RK30_PIN1_PB5, NULL);
- gpio_direction_output(RK30_PIN1_PB5, GPIO_LOW);
-
- rk30_mux_api_set(GPIO1B4_UART3CTSN_GPSRFCLK_NAME, GPIO1B_GPSRFCLK);//GPS_CLK
- rk30_mux_api_set(GPIO1B2_UART3SIN_GPSMAG_NAME, GPIO1B_GPSMAG);//GPS_MAG
- rk30_mux_api_set(GPIO1B3_UART3SOUT_GPSSIG_NAME, GPIO1B_GPSSIG);//GPS_SIGN
-
- rk30_mux_api_set(GPIO1A6_UART1CTSN_SPI0CLK_NAME, GPIO1A_GPIO1A6);//SPI_CLK
- gpio_request(RK30_PIN1_PA6, NULL);
- gpio_direction_output(RK30_PIN1_PA6, GPIO_LOW);
-
- rk30_mux_api_set(GPIO1A5_UART1SOUT_SPI0TXD_NAME, GPIO1A_GPIO1A5);//SPI_MOSI
- gpio_request(RK30_PIN1_PA5, NULL);
- gpio_direction_output(RK30_PIN1_PA5, GPIO_LOW);
-
- rk30_mux_api_set(GPIO1A7_UART1RTSN_SPI0CSN0_NAME, GPIO1A_GPIO1A7);//SPI_CS
- gpio_request(RK30_PIN1_PA7, NULL);
- gpio_direction_output(RK30_PIN1_PA7, GPIO_LOW);
- return 0;
-}
-int rk_gps_power_up(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_power_down(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_reset_set(int level)
-{
- return 0;
-}
-int rk_enable_hclk_gps(void)
-{
- printk("%s \n", __FUNCTION__);
- clk_enable(clk_get(NULL, "hclk_gps"));
- return 0;
-}
-int rk_disable_hclk_gps(void)
-{
- printk("%s \n", __FUNCTION__);
- clk_disable(clk_get(NULL, "hclk_gps"));
- return 0;
-}
-struct rk_gps_data rk_gps_info = {
- .io_init = rk_gps_io_init,
- .power_up = rk_gps_power_up,
- .power_down = rk_gps_power_down,
- .reset = rk_gps_reset_set,
- .enable_hclk_gps = rk_enable_hclk_gps,
- .disable_hclk_gps = rk_disable_hclk_gps,
- .GpsSign = RK30_PIN1_PB3,
- .GpsMag = RK30_PIN1_PB2, //GPIO index
- .GpsClk = RK30_PIN1_PB4, //GPIO index
- .GpsVCCEn = RK30_PIN1_PB5, //GPIO index
- .GpsSpi_CSO = RK30_PIN1_PA4, //GPIO index
- .GpsSpiClk = RK30_PIN1_PA5, //GPIO index
- .GpsSpiMOSI = RK30_PIN1_PA7, //GPIO index
- .GpsIrq = IRQ_GPS,
- .GpsSpiEn = 0,
- .GpsAdcCh = 2,
- .u32GpsPhyAddr = RK30_GPS_PHYS,
- .u32GpsPhySize = RK30_GPS_SIZE,
-};
-
-struct platform_device rk_device_gps = {
- .name = "gps_hv5820b",
- .id = -1,
- .dev = {
- .platform_data = &rk_gps_info,
- }
- };
-#endif
-
-#if defined(CONFIG_MT5931_MT6622)
-static struct mt6622_platform_data mt6622_platdata = {
- .power_gpio = { // BT_REG_ON
- .io = RK30_PIN3_PC7, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN3_PD1,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .irq_gpio = {
- .io = RK30_PIN0_PA5,
- .enable = GPIO_LOW,
- .iomux = {
- .name = NULL,
- },
- },
-
- .rts_gpio = { // UART_RTS
- .io = RK30_PIN1_PA3,
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_rts",
- .fgpio = GPIO1_A3,
- .fmux = UART0_RTSN,
- },
- },
-};
-
-static struct platform_device device_mt6622 = {
- .name = "mt6622",
- .id = -1,
- .dev = {
- .platform_data = &mt6622_platdata,
- },
-};
-#endif
-
-#if defined CONFIG_TCC_BT_DEV
-static struct tcc_bt_platform_data tcc_bt_platdata = {
-
- .power_gpio = { // ldoon
- .io = RK30_PIN3_PC0,//difined depend on your harware
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .wake_host_gpio = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .io = RK30_PIN0_PC5, // set io to INVALID_GPIO for disable it,it's depend on your hardware
- .enable = IRQF_TRIGGER_RISING,// set IRQF_TRIGGER_FALLING for falling, set IRQF_TRIGGER_RISING for rising
- .iomux = {
- .name = NULL,
- },
- },
-};
-
-static struct platform_device device_tcc_bt = {
- .name = "tcc_bt_dev",
- .id = -1,
- .dev = {
- .platform_data = &tcc_bt_platdata,
- },
-};
-#endif
-
-
-static struct platform_device *devices[] __initdata = {
-
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- &rk29sdk_wifi_device,
-#endif
-
-#if defined(CONFIG_MT6620)
- &mt3326_device_gps,
-#endif
-
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
- &rk30_device_adc_battery,
-#endif
-#ifdef CONFIG_RFKILL_RK
- &device_rfkill_rk,
-#endif
-#ifdef CONFIG_GPS_RK
- &rk_device_gps,
-#endif
-#ifdef CONFIG_MT5931_MT6622
- &device_mt6622,
-#endif
-#ifdef CONFIG_TCC_BT_DEV
- &device_tcc_bt,
-#endif
-};
-
-
-static int rk_platform_add_display_devices(void)
-{
- struct platform_device *fb = NULL; //fb
- struct platform_device *lcdc0 = NULL; //lcdc0
- struct platform_device *lcdc1 = NULL; //lcdc1
- struct platform_device *bl = NULL; //backlight
-#ifdef CONFIG_FB_ROCKCHIP
- fb = &device_fb;
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B)
- lcdc0 = &device_lcdc0,
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B)
- lcdc1 = &device_lcdc1,
-#endif
-
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- bl = &rk29_device_backlight,
-#endif
- __rk_platform_add_display_devices(fb,lcdc0,lcdc1,bl);
-
- return 0;
-
-}
-
-// i2c
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_GS_MMA7660)
- {
- .type = "gs_mma7660",//gs_mma7660
- .addr = 0x4c,
- .flags = 0,
- .irq = MMA7660_INT_PIN,
- .platform_data = &mma7660_info,
- },
-#endif
-#if defined (CONFIG_GS_MXC6225)
- {
- .type = "gs_mxc6225",
- .addr = 0x15,
- .flags = 0,
- .irq = MXC6225_INT_PIN,
- .platform_data = &mxc6225_info,
- },
-#endif
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1d,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_GS_LIS3DH)
- {
- .type = "gs_lis3dh",
- .addr = 0x19, //0x19(SA0-->VCC), 0x18(SA0-->GND)
- .flags = 0,
- .irq = LIS3DH_INT_PIN,
- .platform_data = &lis3dh_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8975_info,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8975_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8963)
- {
- .type = "ak8963",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8963_info,
- },
-#endif
-#if defined (CONFIG_GYRO_L3G4200D)
- {
- .type = "l3g4200d_gryo",
- .addr = 0x69,
- .flags = 0,
- .irq = L3G4200D_INT_PIN,
- .platform_data = &l3g4200d_info,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RT5631)
- {
- .type = "rt5631",
- .addr = 0x1a,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RT5616)
- {
- .type = "rt5616",
- .addr = 0x1b,
- .flags = 0,
- },
-#endif
-};
-#endif
-
-int __sramdata g_pmic_type = 0;
-#ifdef CONFIG_I2C1_RK30
-#ifdef CONFIG_REGULATOR_ACT8846
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-#define ACT8846_HOST_IRQ RK30_PIN0_PB3
-
-static struct pmu_info act8846_dcdc_info[] = {
- {
- .name = "act_dcdc1", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 1200000,
- #else
- .suspend_vol = 900000,
- #endif
- },
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 1200000,
- #else
- .suspend_vol = 900000,
- #endif
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 1200000,
- #else
- .suspend_vol = 900000,
- #endif
- },
- {
- .name = "act_dcdc4", //vccio
- .min_uv = 3000000,
- .max_uv = 3000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 3000000,
- #else
- .suspend_vol = 2800000,
- #endif
- },
-
-};
-static struct pmu_info act8846_ldo_info[] = {
- {
- .name = "act_ldo1", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "act_ldo2", //vdd12
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "act_ldo3", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo4", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo5", //vcctp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo6", //vcc_jetta
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo7", //vcc18
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo8", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- };
-
-#include "board-pmu-act8846.c"
-#endif
-
-#ifdef CONFIG_MFD_WM831X_I2C
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info wm8326_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "dcdc3", //ddr
- .min_uv = 1150000,
- .max_uv = 1150000,
- .suspend_vol = 1150000,
- },
- #ifdef CONFIG_MACH_RK3066_SDK
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3000000,
- },
- #else
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3000000,
- .max_uv = 3000000,
- .suspend_vol = 2800000,
- },
- #endif
-};
-
-static struct pmu_info wm8326_ldo_info[] = {
- {
- .name = "ldo1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo2", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo3", //
- .min_uv = 1100000,
- .max_uv = 1100000,
- .suspend_vol = 1100000,
- },
- {
- .name = "ldo4", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 1000000,
- },
- {
- .name = "ldo5", //vcc25
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo6", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo7", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- .suspend_vol = 2800000,
- },
- {
- .name = "ldo8", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo9", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo10", //flash_io
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
-};
-
-#include "board-pmu-wm8326.c"
-#endif
-
-#ifdef CONFIG_MFD_TPS65910
-#ifdef CONFIG_ARCH_RK3066B
-#define TPS65910_HOST_IRQ RK30_PIN0_PB3
-#else
-#define TPS65910_HOST_IRQ RK30_PIN6_PA4
-#endif
-
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info tps65910_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vio", //vcc_io
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
-
-};
-static struct pmu_info tps65910_ldo_info[] = {
-/* {
- .name = "vpll", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- },*/
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
-#ifdef CONFIG_MFD_RK616
- {
- .name = "vdig2", //vdd11//1.0->1.2 for rk616 vdd_core lch
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
-#else
- {
- .name = "vdig2", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
-#endif
- {
- .name = "vaux1", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "vaux2", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vaux33", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vmmc", //vcca30
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
- {
- .name = "vdac", //vcc18
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- };
-
-#include "board-pmu-tps65910.c"
-#endif
-#ifdef CONFIG_REGULATOR_ACT8931
-#define ACT8931_HOST_IRQ RK30_PIN0_PB5//depend on your hardware
-
-
-#define ACT8931_CHGSEL_PIN RK30_PIN0_PD0 //depend on your hardware
-
-
-static struct pmu_info act8931_dcdc_info[] = {
- {
- .name = "vdd_core", //vdd_logic
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "act_dcdc2", //ddr
- .min_uv = 1500000,
- .max_uv = 1500000,
- },
- {
- .name = "vdd_cpu", //vdd_arm
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
-
-};
-static struct pmu_info act8931_ldo_info[] = {
- {
- .name = "act_ldo1", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "act_ldo2", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo3", //vcca30
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
- {
- .name = "act_ldo4", //vcc_wl
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
-};
-#include "board-rk30-sdk-act8931.c"
-#endif
-
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_REGULATOR_ACT8846)
- {
- .type = "act8846",
- .addr = 0x5a,
- .flags = 0,
- .irq = ACT8846_HOST_IRQ,
- .platform_data=&act8846_data,
- },
-#endif
-#if defined (CONFIG_RTC_HYM8563)
- {
- .type = "rtc_hym8563",
- .addr = 0x51,
- .flags = 0,
- .irq = RK30_PIN0_PB5,
- },
-#endif
-#if defined (CONFIG_MFD_WM831X_I2C)
- {
- .type = "wm8326",
- .addr = 0x34,
- .flags = 0,
- .irq = RK30_PIN0_PB3,
- .platform_data = &wm831x_platdata,
- },
-#endif
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-#if defined (CONFIG_REGULATOR_ACT8931)
- {
- .type = "act8931",
- .addr = 0x5b,
- .flags = 0,
- .irq = ACT8931_HOST_IRQ,
- .platform_data=&act8931_data,
- },
-#endif
-};
-#endif
-
-void __sramfunc board_pmu_suspend(void)
-{
- #if defined (CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- board_pmu_act8846_suspend();
- #endif
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_suspend();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_suspend();
- #endif
-}
-
-void __sramfunc board_pmu_resume(void)
-{
- #if defined (CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- board_pmu_act8846_resume();
- #endif
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_resume();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_resume();
- #endif
-}
-
- int __sramdata gpio3d6_iomux,gpio3d6_do,gpio3d6_dir,gpio3d6_en;
-
-#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
-
-void __sramfunc rk30_pwm_logic_suspend_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
-
-// int gpio0d7_iomux,gpio0d7_do,gpio0d7_dir,gpio0d7_en;
- sram_udelay(10000);
- gpio3d6_iomux = grf_readl(GRF_GPIO3D_IOMUX);
- gpio3d6_do = grf_readl(GRF_GPIO3H_DO);
- gpio3d6_dir = grf_readl(GRF_GPIO3H_DIR);
- gpio3d6_en = grf_readl(GRF_GPIO3H_EN);
-
- grf_writel((1<<28), GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DIR);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DO);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_EN);
-#endif
-}
-void __sramfunc rk30_pwm_logic_resume_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- grf_writel((1<<28)|gpio3d6_iomux, GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|gpio3d6_en, GRF_GPIO3H_EN);
- grf_writel((1<<30)|gpio3d6_dir, GRF_GPIO3H_DIR);
- grf_writel((1<<30)|gpio3d6_do, GRF_GPIO3H_DO);
- sram_udelay(10000);
-
-#endif
-
-}
-extern void pwm_suspend_voltage(void);
-extern void pwm_resume_voltage(void);
-void rk30_pwm_suspend_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_suspend_voltage();
-#endif
-}
-void rk30_pwm_resume_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_resume_voltage();
-#endif
-}
-
-
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-#if defined (CONFIG_CT36X_TS)
- {
- .type = CT36X_NAME,
- .addr = 0x01,
- .flags = 0,
- .platform_data = &ct36x_info,
- },
-#endif
-#if defined (CONFIG_LS_CM3217)
- {
- .type = "lightsensor",
- .addr = 0x10,
- .flags = 0,
- .platform_data = &cm3217_info,
- },
-#endif
-#if defined (CONFIG_TOUCHSCREEN_GSLX680)
- {
- .type = "gslX680",
- .addr = 0x40,
- .flags = 0,
- .platform_data =&gslx680_info,
- },
-#endif
-#if defined (CONFIG_TOUCHSCREEN_GSLX680_RK3168)
- {
- .type = "gslX680",
- .addr = 0x40,
- .flags = 0,
- .platform_data =&gslx680_info,
- },
-#endif
-#if defined (CONFIG_TOUCHSCREEN_86V_GT811_IIC)
-{
- .type = "gt811_ts",
- .addr = 0x5d,
- .flags = 0,
- .irq = TOUCH_INT_PIN,
- .platform_data = >811_info,
-},
-#endif
-#if defined(CONFIG_TOUCHSCREEN_GT82X_IIC)
- {
- .type = "Goodix-TS-82X",
- .addr = 0x5D,
- .flags = 0,
- .irq = RK30_PIN1_PB7,
- .platform_data = &ts82x_pdata,
- },
-#endif
-#if defined(CONFIG_HDMI_CAT66121)
- {
- .type = "cat66121_hdmi",
- .addr = 0x4c,
- .flags = 0,
- .irq = RK30_PIN2_PD6,
- .platform_data = &rk_hdmi_pdata,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C4_RK30
-static struct i2c_board_info __initdata i2c4_info[] = {
-#ifdef CONFIG_MFD_RK610
- {
- .type = "rk610_ctl",
- .addr = 0x40,
- .flags = 0,
- .platform_data = &rk610_ctl_pdata,
- },
-#ifdef CONFIG_RK610_TVOUT
- {
- .type = "rk610_tvout",
- .addr = 0x42,
- .flags = 0,
- },
-#endif
-#ifdef CONFIG_HDMI_RK610
- {
- .type = "rk610_hdmi",
- .addr = 0x46,
- .flags = 0,
- .irq = INVALID_GPIO,
- },
-#endif
-#ifdef CONFIG_SND_SOC_RK610
- {//RK610_CODEC addr from 0x60 to 0x80 (0x60~0x80)
- .type = "rk610_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- .platform_data = &rk610_codec_pdata,
- },
-#endif
-#endif
-#if defined (CONFIG_MFD_RK616)
-{
- .type = "rk616",
- .addr = 0x50,
- .flags = 0,
- .platform_data = &rk616_pdata,
- },
-#endif
-
-#if defined (CONFIG_SND_RK29_SOC_ES8323)
- {
- .type = "es8323",//"es8323",
- .addr = 0x10,
- .flags = 0,
- },
-#endif
-};
-
-#if defined (CONFIG_SND_SOC_RT5616)
- {
- .type = "rt5616",
- .addr = 0x1b,
- .flags = 0,
- },
-#endif
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO// RK30_PIN2_PD6 //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO//RK30_PIN2_PD7 //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- //set iomux (gpio) here
- //rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME, GPIO2D_GPIO2D7);
- //rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME, GPIO2D_GPIO2D6);
-
- return 0;
-}
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C4_RK30
- i2c_register_board_info(4, i2c4_info, ARRAY_SIZE(i2c4_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(5, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-#define USB_INSERT_FAKE_SHUTDOWN
-#if defined(USB_INSERT_FAKE_SHUTDOWN)
-extern int rk30_pm_enter(suspend_state_t state);
-int __sramdata charge_power_off = 0;
-
-static void rk30_charge_deal(void)
-{
- struct regulator *ldo = NULL;
- int ret;
- charge_power_off = 1;
-
- //ldo = regulator_get(NULL, "ldo9"); // shutdown tp power
- //regulator_disable(ldo);
- //regulator_put(ldo);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_LOW);
- rk29_backlight_pwm_suspend();//shutdown backlight
- rk_fb_io_disable(); //shutdown lcd
-
- local_irq_disable();
- local_fiq_disable();
-
- rk30_pm_enter(PM_SUSPEND_MEM);
-
- if(charge_power_off == 1)
- {
- arm_pm_restart(0, NULL);
- }
-}
-#else
-static void rk30_charge_deal(void){
-}
-#endif
-
-
-#define POWER_ON_PIN RK30_PIN0_PA0 //power_hold
-static void rk30_pm_power_off(void)
-{
- printk(KERN_ERR "rk30_pm_power_off start...\n");
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
-
- if (pmic_is_tps65910()) {
- printk("enter dcdet pmic_is_tps65910===========\n");
- if(gpio_get_value (RK30_PIN0_PB2) == GPIO_LOW)
- {
- printk("enter restart===========\n");
- arm_pm_restart(0, "charge");
- }else if(gpio_get_value (RK30_PIN0_PA7) == GPIO_LOW){//usb in
- printk("debug: detect dc_det LOW, charging!\n");
- rk30_charge_deal();
- }
- tps65910_device_shutdown();
- }else if(pmic_is_act8846()){
- printk("enter dcdet pmic_is_act8846===========\n");
- if(gpio_get_value (RK30_PIN0_PB2) == GPIO_LOW)
- {
- printk("enter restart===========\n");
- arm_pm_restart(0, "charge");
- }
- act8846_device_shutdown();
- }else if(pmic_is_wm8326()){
- printk("enter dcdet pmic_is_wm8326===========\n");
- if(gpio_get_value (RK30_PIN0_PB2) == GPIO_LOW)
- {
- printk("enter restart===========\n");
- arm_pm_restart(0, "charge");
- }
- wm831x_set_bits(Wm831x,WM831X_GPIO_LEVEL,0x0001,0x0000); //set sys_pwr 0
- wm831x_device_shutdown(Wm831x);//wm8326 shutdown
- }else if(pmic_is_act8931()){
- printk("enter dcdet pmic_is_act8931===========\n");
- if(gpio_get_value (RK30_PIN0_PB2) == GPIO_LOW)
- {
- printk("enter restart===========\n");
- arm_pm_restart(0, "charge");
- }
- act8931_device_shutdown();
- }
- while (1);
-}
-
-static void __init machine_rk30_board_init(void)
-{
- avs_init();
- gpio_request(POWER_ON_PIN, "poweronpin");
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
- //pm_power_off = rk30_pm_power_off;
-
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
-
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- rk_platform_add_display_devices();
- board_usb_detect_init(RK30_PIN0_PA7);
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- rk29sdk_wifi_bt_gpio_control_init();
-#endif
-
-#if defined(CONFIG_MT6620)
- clk_set_rate(clk_get_sys("rk_serial.1", "uart"), 48*1000000);
-#endif
-
-#if defined(CONFIG_MT5931_MT6622)
- clk_set_rate(clk_get_sys("rk_serial.0", "uart"), 24*1000000);
-#endif
-}
-
-static void __init rk30_reserve(void)
-{
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0 buf", get_fb_size());
- resource_fb[0].end = resource_fb[0].start + get_fb_size()- 1;
-#if 0
- resource_fb[1].start = board_mem_reserve_add("ipp buf", RK30_FB0_MEM_SIZE);
- resource_fb[1].end = resource_fb[1].start + RK30_FB0_MEM_SIZE - 1;
-#endif
-
-#if defined(CONFIG_FB_ROTATE) || !defined(CONFIG_THREE_FB_BUFFER)
- resource_fb[2].start = board_mem_reserve_add("fb2 buf",get_fb_size());
- resource_fb[2].end = resource_fb[2].start + get_fb_size() - 1;
-#endif
-#endif
-
-
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
-
-#ifdef CONFIG_GPS_RK
- //it must be more than 8MB
- rk_gps_info.u32MemoryPhyAddr = board_mem_reserve_add("gps", SZ_8M);
-#endif
- board_mem_reserved();
-}
-
-/**
- * dvfs_cpu_logic_table: table for arm and logic dvfs
- * @frequency : arm frequency
- * @cpu_volt : arm voltage depend on frequency
- * @logic_volt : logic voltage arm requests depend on frequency
- * comments : min arm/logic voltage
- */
-#ifdef CONFIG_DVFS_WITH_UOC
-//chenxing uoc
-static struct cpufreq_frequency_table dvfs_arm_table[] = {
- {.frequency = 312 * 1000, .index = 950 * 1000},
- {.frequency = 504 * 1000, .index = 1000 * 1000},
- {.frequency = 816 * 1000, .index = 1050 * 1000},
- {.frequency = 1008 * 1000, .index = 1125 * 1000},
- {.frequency = 1200 * 1000, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- {.frequency = 100 * 1000, .index = 1000 * 1000},
- {.frequency = 200 * 1000, .index = 1000 * 1000},
- {.frequency = 266 * 1000, .index = 1050 * 1000},
- //{.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1125 * 1000},
- {.frequency = 600 * 1000, .index = 1250 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 1000 * 1000},
- {.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = 1050 * 1000},
- {.frequency = 400 * 1000 + DDR_FREQ_NORMAL, .index = 1100 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-#else
-//chenliang
-static struct cpufreq_frequency_table dvfs_arm_table[] = {
- {.frequency = 312 * 1000, .index = 1025 * 1000},
- {.frequency = 504 * 1000, .index = 1025 * 1000},
- {.frequency = 816 * 1000, .index = 1050 * 1000},
- {.frequency = 1008 * 1000, .index = 1125 * 1000},
- {.frequency = 1200 * 1000, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- {.frequency = 100 * 1000, .index = 1000 * 1000},
- {.frequency = 200 * 1000, .index = 1000 * 1000},
- {.frequency = 266 * 1000, .index = 1050 * 1000},
- {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1125 * 1000},
- {.frequency = 600 * 1000, .index = 1250 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 1000 * 1000},
- {.frequency = 240 * 1000 + DDR_FREQ_VIDEO, .index = 1050 * 1000},
- {.frequency = 300 * 1000 + DDR_FREQ_NORMAL, .index = 1075 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-#endif
-//#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
-//static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
-//static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
-int get_max_freq(struct cpufreq_frequency_table *table)
-{
- int i,temp=0;
-
- for(i=0;table[i].frequency!= CPUFREQ_TABLE_END;i++)
- {
- if(temp<table[i].frequency)
- temp=table[i].frequency;
- }
- printk("get_max_freq=%d\n",temp);
- return temp;
-}
-
-void __init board_clock_init(void)
-{
- u32 flags=RK30_CLOCKS_DEFAULT_FLAGS;
-#if !defined(CONFIG_ARCH_RK3188)
- if(get_max_freq(dvfs_gpu_table)<=(400*1000))
- {
- flags=RK30_CLOCKS_DEFAULT_FLAGS|CLK_GPU_GPLL;
- }
- else
- flags=RK30_CLOCKS_DEFAULT_FLAGS|CLK_GPU_CPLL;
-#endif
- rk30_clock_data_init(periph_pll_default, codec_pll_default, flags);
- //dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "cpu"), dvfs_arm_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
-}
-
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk30_fixup,
- .reserve = &rk30_reserve,
- .map_io = rk30_map_io,
- .init_irq = rk30_init_irq,
- .timer = &rk30_timer,
- .init_machine = machine_rk30_board_init,
-MACHINE_END
+++ /dev/null
-#ifdef CONFIG_VIDEO_RK29
-#include <plat/rk_camera.h>
-/* Notes:
-
-Simple camera device registration:
-
- new_camera_device(sensor_name,\ // sensor name, it is equal to CONFIG_SENSOR_X
- face,\ // sensor face information, it can be back or front
- pwdn_io,\ // power down gpio configuration, it is equal to CONFIG_SENSOR_POWERDN_PIN_XX
- flash_attach,\ // sensor is attach flash or not
- mir,\ // sensor image mirror and flip control information
- i2c_chl,\ // i2c channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_IIC_ADAPTER_ID_X
- cif_chl) \ // cif channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_CIF_INDEX_X
-
-Comprehensive camera device registration:
-
- new_camera_device_ex(sensor_name,\
- face,\
- ori,\ // sensor orientation, it is equal to CONFIG_SENSOR_ORIENTATION_X
- pwr_io,\ // sensor power gpio configuration, it is equal to CONFIG_SENSOR_POWER_PIN_XX
- pwr_active,\ // sensor power active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- rst_io,\ // sensor reset gpio configuration, it is equal to CONFIG_SENSOR_RESET_PIN_XX
- rst_active,\ // sensor reset active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- pwdn_io,\
- pwdn_active,\ // sensor power down active level, is equal to CONFIG_SENSOR_POWERDNACTIVE_LEVEL_X
- flash_attach,\
- res,\ // sensor resolution, this is real resolution or resoltuion after interpolate
- mir,\
- i2c_chl,\
- i2c_spd,\ // i2c speed , 100000 = 100KHz
- i2c_addr,\ // the i2c slave device address for sensor
- cif_chl,\
- mclk)\ // sensor input clock rate, 24 or 48
-
-*/
-static struct rkcamera_platform_data new_camera[] = {
- new_camera_device(RK29_CAM_SENSOR_OV2659,
- back,
- RK30_PIN3_PB5,
- 0,
- 0,
- 3,
- 0),
-
- new_camera_device(RK29_CAM_SENSOR_SP2518,
- back,
- RK30_PIN3_PB5,
- 0,
- 0,
- 3,
- 0),
-
- new_camera_device(RK29_CAM_SENSOR_GC2035,
- back,
- RK30_PIN3_PB5,
- 0,
- 0,
- 3,
- 0),
-
- new_camera_device(RK29_CAM_SENSOR_OV2659,
- front,
- RK30_PIN3_PB4,
- 0,
- 0,
- 3,
- 0),
-
- new_camera_device(RK29_CAM_SENSOR_SP2518,
- front,
- RK30_PIN3_PB4,
- 0,
- 0,
- 3,
- 0),
-
- new_camera_device(RK29_CAM_SENSOR_GC2035,
- front,
- RK30_PIN3_PB4,
- 0,
- 0,
- 3,
- 0),
- new_camera_device_end
-};
-/*---------------- Camera Sensor Macro Define Begin ------------------------*/
-/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
-#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_OV2659 /* back camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_0 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 3
-#define CONFIG_SENSOR_ORIENTATION_0 90
-#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 RK30_PIN3_PB5
-#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000
-
-#define CONFIG_SENSOR_01 RK29_CAM_SENSOR_SP2518 /* back camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_01 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 3
-#define CONFIG_SENSOR_ORIENTATION_01 90
-#define CONFIG_SENSOR_POWER_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_01 RK30_PIN3_PB5
-#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_01 30000
-
-#define CONFIG_SENSOR_02 RK29_CAM_SENSOR_GC2035 /* back camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_02 0x00
-#define CONFIG_SENSOR_CIF_INDEX_02 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 3
-#define CONFIG_SENSOR_ORIENTATION_02 90
-#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_02 RK30_PIN3_PB5
-#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000
-
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_OV2659 /* front camera sensor 0 */
-#define CONFIG_SENSOR_IIC_ADDR_1 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 3
-#define CONFIG_SENSOR_ORIENTATION_1 270
-#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_1 RK30_PIN3_PB4
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000
-
-#define CONFIG_SENSOR_11 RK29_CAM_SENSOR_SP2518 /* front camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_11 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 3
-#define CONFIG_SENSOR_ORIENTATION_11 270
-#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_11 RK30_PIN3_PB4//RK30_PIN1_PB7
-#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_11 30000
-
-#define CONFIG_SENSOR_12 RK29_CAM_SENSOR_GC2035//RK29_CAM_SENSOR_OV2655 /* front camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_12 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 3
-#define CONFIG_SENSOR_ORIENTATION_12 270
-#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_12 RK30_PIN3_PB4//RK30_PIN1_PB7
-#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_12 30000
-
-
-#endif //#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk30_camera.c"
-/*---------------- Camera Sensor Macro Define End ---------*/
-
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#define CONFIG_SENSOR_POWER_IOCTL_USR 1 //define this refer to your board layout
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
-
-static void rk_cif_power(struct rk29camera_gpio_res *res,int on)
-{
- struct regulator *ldo_18,*ldo_28;
- int camera_power = res->gpio_power;
- int camera_ioflag = res->gpio_flag;
- int camera_io_init = res->gpio_init;
-
- ldo_28 = regulator_get(NULL, "act_ldo8"); // vcc28_cif
- ldo_18 = regulator_get(NULL, "act_ldo3"); // vcc18_cif
- if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){
- printk("get cif ldo failed!\n");
- return;
- }
- if(on == 0){
- while(regulator_is_enabled(ldo_28)>0)
- regulator_disable(ldo_28);
- regulator_put(ldo_28);
-
- while(regulator_is_enabled(ldo_18)>0)
- regulator_disable(ldo_18);
- regulator_put(ldo_18);
-
- mdelay(10);
- if (camera_power != INVALID_GPIO) {
- if (camera_io_init & RK29_CAM_POWERACTIVE_MASK) {
- gpio_set_value(camera_power, (((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
- // dprintk("%s..%s..PowerPin=%d ..PinLevel = %x \n",__FUNCTION__,res->dev_name, camera_power, (((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
- }
- }
- }
- else{
- regulator_set_voltage(ldo_28, 2800000, 2800000);
- regulator_enable(ldo_28);
- // printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
- regulator_put(ldo_28);
-
- regulator_set_voltage(ldo_18, 1800000, 1800000);
- // regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(ldo_18);
- // printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
- regulator_put(ldo_18);
- if (camera_power != INVALID_GPIO) {
- if (camera_io_init & RK29_CAM_POWERACTIVE_MASK) {
- gpio_set_value(camera_power, ((camera_ioflag&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
- mdelay(10);
- }
-
-}
-
- }
-}
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- //#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
- rk_cif_power(res,on);
- return 0;
-}
-#endif
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-
-#if CONFIG_SENSOR_IIC_ADDR_0
-static struct reginfo_t rk_init_data_sensor_reg_0[] =
-{
- {0x0000, 0x00,0,0}
- };
-static struct reginfo_t rk_init_data_sensor_winseqreg_0[] ={
- {0x0000, 0x00,0,0}
- };
-#endif
-
-#if CONFIG_SENSOR_IIC_ADDR_1
-static struct reginfo_t rk_init_data_sensor_reg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_01
-static struct reginfo_t rk_init_data_sensor_reg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_02
-static struct reginfo_t rk_init_data_sensor_reg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_11
-static struct reginfo_t rk_init_data_sensor_reg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_12
-static struct reginfo_t rk_init_data_sensor_reg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] =
-{
- #if CONFIG_SENSOR_IIC_ADDR_0
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_0,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_1
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_1,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_01
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_01,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_02
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_02,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_11
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_11,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_12
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_12,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
-
- };
-#include "../../../drivers/media/video/rk30_camera.c"
-
-#endif /* CONFIG_VIDEO_RK29 */
+++ /dev/null
-/*
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <mach/dvfs.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <linux/rk_fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/mfd/tps65910.h>
-#include <linux/regulator/act8846.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-
-#if defined(CONFIG_MFD_RK610)
-#include <linux/mfd/rk610_core.h>
-#endif
-
-#if defined(CONFIG_DP_ANX6345)
- #include<linux/anx6345.h>
-#endif
-
-#if defined(CONFIG_CT36X_TS)
-#include <linux/ct36x.h>
-#endif
-
-#if defined(CONFIG_RK_HDMI)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-#if defined(CONFIG_GPS_RK)
-#include "../../../drivers/misc/gps/rk_gps/rk_gps.h"
-#endif
-
-#if defined(CONFIG_MU509)
-#include <linux/mu509.h>
-#endif
-#if defined(CONFIG_MW100)
-#include <linux/mw100.h>
-#endif
-#if defined(CONFIG_MT6229)
-#include <linux/mt6229.h>
-#endif
-#if defined(CONFIG_ANDROID_TIMED_GPIO)
-#include "../../../drivers/staging/android/timed_gpio.h"
-#endif
-
-
-#include "board-rk3168-LR097-camera.c"
-
-#if defined(CONFIG_TOUCHSCREEN_GT8XX)
-#define TOUCH_RESET_PIN RK30_PIN0_PB6
-#define TOUCH_PWR_PIN RK30_PIN0_PC5 // need to fly line by hardware engineer
-static int goodix_init_platform_hw(void)
-{
- int ret;
-
- if (TOUCH_PWR_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_PWR_PIN, "goodix power pin");
- if (ret != 0) {
- gpio_free(TOUCH_PWR_PIN);
- printk("goodix power error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_PWR_PIN, 0);
- gpio_set_value(TOUCH_PWR_PIN, GPIO_LOW);
- msleep(100);
- }
-
- if (TOUCH_RESET_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_RESET_PIN, "goodix reset pin");
- if (ret != 0) {
- gpio_free(TOUCH_RESET_PIN);
- printk("goodix gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, 1);
- msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_LOW);
- //msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_HIGH);
- //msleep(500);
- }
- return 0;
-}
-
-struct goodix_platform_data goodix_info = {
- .model = 8105,
- .irq_pin = RK30_PIN1_PB7,
- .rest_pin = TOUCH_RESET_PIN,
- .init_platform_hw = goodix_init_platform_hw,
-};
-#endif
-
-
-#if defined(CONFIG_CT36X_TS)
-
-#define TOUCH_MODEL 363
-#define TOUCH_MAX_X 1280
-#define TOUCH_MAX_y 800
-#define TOUCH_RESET_PIN RK30_PIN0_PB6
-#define TOUCH_INT_PIN RK30_PIN1_PB7
-
-static struct ct36x_platform_data ct36x_info = {
- .model = TOUCH_MODEL,
- .x_max = TOUCH_MAX_X,
- .y_max = TOUCH_MAX_y,
-
- .rst_io = {
- .gpio = TOUCH_RESET_PIN,
- .active_low = 1,
- },
- .irq_io = {
- .gpio = TOUCH_INT_PIN,
- .active_low = 1,
- },
- .orientation = {1, 0, 0, 1},
-};
-#endif
-
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-#define PWM_ID 3
-#define PWM_MODE PWM3
-#define PWM_EFFECT_VALUE 0
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-#define BL_EN_PIN RK30_PIN0_PA2
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
-
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
- ret = gpio_request(BL_EN_PIN, "bl_en");
- if (ret == 0) {
- gpio_direction_output(BL_EN_PIN, BL_EN_VALUE);
- }
-#endif
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0, pwm_gpio;
-#ifdef LCD_DISP_ON_PIN
- gpio_free(BL_EN_PIN);
-#endif
- pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
- gpio_request(pwm_gpio, "bl_pwm");
- gpio_direction_output(pwm_gpio, GPIO_LOW);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret, pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
-
- ret = gpio_request(pwm_gpio, "bl_pwm");
- if (ret) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return ret;
- }
- gpio_direction_output(pwm_gpio, GPIO_LOW);
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, !BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- int pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
-
- gpio_free(pwm_gpio);
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
- msleep(200);
- gpio_direction_output(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .min_brightness = 50,
- .max_brightness=200,
- .brightness_mode =BRIGHTNESS_MODE_CONIC,
- .pre_div = 30 * 1000,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-#endif
-
-#ifdef CONFIG_RK29_SUPPORT_MODEM
-
-#define RK30_MODEM_POWER RK30_PIN0_PC6
-#define RK30_MODEM_POWER_IOMUX iomux_set(GPIO0_C6)
-
-static int rk30_modem_io_init(void)
-{
- printk("%s\n", __FUNCTION__);
- RK30_MODEM_POWER_IOMUX;
-
- return 0;
-}
-
-static struct rk29_io_t rk30_modem_io = {
- .io_addr = RK30_MODEM_POWER,
- .enable = GPIO_HIGH,
- .disable = GPIO_LOW,
- .io_init = rk30_modem_io_init,
-};
-
-static struct platform_device rk30_device_modem = {
- .name = "rk30_modem",
- .id = -1,
- .dev = {
- .platform_data = &rk30_modem_io,
- }
-};
-#endif
-#if defined(CONFIG_MU509)
-static int mu509_io_init(void)
-{
-
- iomux_set(GPIO2_D5);
- iomux_set(GPIO0_C6);
- iomux_set(GPIO2_D4);
- iomux_set(GPIO0_C4);
- iomux_set(GPIO0_C5);
- return 0;
-}
-
-static int mu509_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mu509_data rk29_mu509_info = {
- .io_init = mu509_io_init,
- .io_deinit = mu509_io_deinit,
- .modem_power_en = RK30_PIN2_PD5,
- .bp_power = RK30_PIN0_PC6,
- .bp_reset = RK30_PIN2_PD4,
- .ap_wakeup_bp = RK30_PIN0_PC4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
-};
-struct platform_device rk29_device_mu509 = {
- .name = "mu509",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mu509_info,
- }
- };
-#endif
-#if defined(CONFIG_MW100)
-static int mw100_io_init(void)
-{
- iomux_set(GPIO2_D5);
- iomux_set(GPIO0_C6);
- iomux_set(GPIO2_D4);
- iomux_set(GPIO0_C4);
- iomux_set(GPIO0_C5);
- return 0;
-}
-
-static int mw100_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mw100_data rk29_mw100_info = {
- .io_init = mw100_io_init,
- .io_deinit = mw100_io_deinit,
- .modem_power_en = RK30_PIN2_PD5,
- .bp_power = RK30_PIN0_PC6,
- .bp_reset = RK30_PIN2_PD4,
- .ap_wakeup_bp = RK30_PIN0_PC4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
-};
-struct platform_device rk29_device_mw100 = {
- .name = "mw100",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mw100_info,
- }
- };
-#endif
-#if defined(CONFIG_MT6229)
-static int mt6229_io_init(void)
-{
- iomux_set(GPIO2_D5);
- iomux_set(GPIO0_C6);
- iomux_set(GPIO2_D4);
- iomux_set(GPIO0_C4);
- iomux_set(GPIO0_C5);
- return 0;
-}
-
-static int mt6229_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mt6229_data rk29_mt6229_info = {
- .io_init = mt6229_io_init,
- .io_deinit = mt6229_io_deinit,
- .modem_power_en = RK30_PIN2_PD5,
- .bp_power = RK30_PIN0_PC6,
- .bp_reset = RK30_PIN2_PD4,
- .ap_wakeup_bp = RK30_PIN0_PC4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
-};
-struct platform_device rk29_device_mt6229 = {
- .name = "mt6229",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mt6229_info,
- }
- };
-#endif
-
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN RK30_PIN0_PB7
-
-static int mma8452_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data mma8452_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma8452_init_platform_hw,
- .orientation = {1, 0, 0, 0, -1, 0, 0, 0, -1},
-};
-#endif
-#if defined (CONFIG_GS_LIS3DH)
-#define LIS3DH_INT_PIN RK30_PIN0_PB7
-
-static int lis3dh_init_platform_hw(void)
-{
-
- return 0;
-}
-
-static struct sensor_platform_data lis3dh_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lis3dh_init_platform_hw,
- .orientation = {1, 0, 0, 0, -1, 0, 0, 0, -1},
-};
-#endif
-#if defined(CONFIG_CHARGER_CW2015)
-struct cw2015_platform_data cw2015_info = {
- .dc_det_pin = RK30_PIN0_PB2,
- .batt_low_pin = RK30_PIN0_PB1,
- //.charge_ok_pin = RK30_PIN0_PA6,
- .dc_det_level = GPIO_LOW,
- .batt_low_level = GPIO_LOW,
- //.charge_ok_level = GPIO_HIGH,
-};
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
-static struct sensor_platform_data akm8975_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-#if defined(CONFIG_GYRO_L3G4200D)
-
-#include <linux/l3g4200d.h>
-#define L3G4200D_INT_PIN RK30_PIN0_PB4
-
-static int l3g4200d_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data l3g4200d_info = {
- .type = SENSOR_TYPE_GYROSCOPE,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
- .init_platform_hw = l3g4200d_init_platform_hw,
- .x_min = 40,//x_min,y_min,z_min = (0-100) according to hardware
- .y_min = 40,
- .z_min = 20,
-};
-
-#endif
-
-#ifdef CONFIG_LS_CM3217
-static struct sensor_platform_data cm3217_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 0,
- .poll_delay_ms = 500,
-};
-
-#endif
-
-#ifdef CONFIG_FB_ROCKCHIP
-
-#define LCD_CS_PIN INVALID_GPIO
-#define LCD_CS_VALUE GPIO_HIGH
-
-#define LCD_EN_PIN INVALID_GPIO
-#define LCD_EN_VALUE GPIO_HIGH
-
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
-
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_CS_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_CS_PIN);
- printk(KERN_ERR "request lcd cs pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_CS_PIN, LCD_CS_VALUE);
- }
- }
-
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_EN_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_EN_PIN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_EN_PIN, LCD_EN_VALUE);
- }
- }
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, !LCD_CS_VALUE);
- }
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, !LCD_EN_VALUE);
- }
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE);
- }
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
- }
- return 0;
-}
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
-struct rk29fb_info lcdc0_screen_info = {
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
-struct rk29fb_info lcdc1_screen_info = {
- #if defined(CONFIG_RK_HDMI)
- .prop = EXTEND, //extend display device
- .lcd_info = NULL,
- .set_screen_info = hdmi_init_lcdc,
- #endif
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-
-#if defined(CONFIG_ARCH_RK3188)
-static struct resource resource_mali[] = {
- [0] = {
- .name = "ump buf",
- .start = 0,
- .end = 0,
- .flags = IORESOURCE_MEM,
- },
-
-};
-
-static struct platform_device device_mali= {
- .name = "mali400_ump",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_mali),
- .resource = resource_mali,
-};
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
-static struct resource resource_lcdc0[] = {
- [0] = {
- .name = "lcdc0 reg",
- .start = RK30_LCDC0_PHYS,
- .end = RK30_LCDC0_PHYS + RK30_LCDC0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc0 irq",
- .start = IRQ_LCDC0,
- .end = IRQ_LCDC0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc0 = {
- .name = "rk30-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc0),
- .resource = resource_lcdc0,
- .dev = {
- .platform_data = &lcdc0_screen_info,
- },
-};
-#endif
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
-static struct resource resource_lcdc1[] = {
- [0] = {
- .name = "lcdc1 reg",
- .start = RK30_LCDC1_PHYS,
- .end = RK30_LCDC1_PHYS + RK30_LCDC1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc1 irq",
- .start = IRQ_LCDC1,
- .end = IRQ_LCDC1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc1 = {
- .name = "rk30-lcdc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resource_lcdc1),
- .resource = resource_lcdc1,
- .dev = {
- .platform_data = &lcdc1_screen_info,
- },
-};
-#endif
-
-#if defined(CONFIG_MFD_RK610)
-#define RK610_RST_PIN RK30_PIN2_PC5
-static int rk610_power_on_init(void)
-{
- int ret;
- if(RK610_RST_PIN != INVALID_GPIO)
- {
-// rk30_mux_api_set(RK610_RST_PIN_MUX_NAME,RK610_RST_PIN_MUX_MODE);
- ret = gpio_request(RK610_RST_PIN, "rk610 reset");
- if (ret)
- {
- printk(KERN_ERR "rk610_control_probe request gpio fail\n");
- }
- else
- {
- gpio_direction_output(RK610_RST_PIN, GPIO_HIGH);
- msleep(100);
- gpio_direction_output(RK610_RST_PIN, GPIO_LOW);
- msleep(100);
- gpio_set_value(RK610_RST_PIN, GPIO_HIGH);
- }
- printk("%s........rst ok\n",__func__);
- }
-
- return 0;
-
-}
-
-
-static struct rk610_ctl_platform_data rk610_ctl_pdata = {
- .rk610_power_on_init = rk610_power_on_init,
-};
-#endif
-
-#ifdef CONFIG_SND_SOC_RK610
-static int rk610_codec_io_init(void)
-{
-//if need iomux.
-//Must not gpio_request
- return 0;
-}
-
-static struct rk610_codec_platform_data rk610_codec_pdata = {
- .spk_ctl_io = RK30_PIN2_PD7,
- .io_init = rk610_codec_io_init,
-};
-#endif
-
-#ifdef CONFIG_RK_HDMI
-#define RK_HDMI_RST_PIN RK30_PIN3_PB2
-static int rk_hdmi_power_init(void)
-{
- int ret;
-
- if(RK_HDMI_RST_PIN != INVALID_GPIO)
- {
- if (gpio_request(RK_HDMI_RST_PIN, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- gpio_direction_output(RK_HDMI_RST_PIN, GPIO_LOW);
- gpio_set_value(RK_HDMI_RST_PIN, GPIO_LOW);
- msleep(100);
- gpio_set_value(RK_HDMI_RST_PIN, GPIO_HIGH);
- msleep(50);
- }
- return 0;
-}
-static struct rk_hdmi_platform_data rk_hdmi_pdata = {
- .io_init = rk_hdmi_power_init,
-};
-#endif
-
-#ifdef CONFIG_ANDROID_TIMED_GPIO
-static struct timed_gpio timed_gpios[] = {
- {
- .name = "vibrator",
- .gpio = INVALID_GPIO,
- .max_timeout = 1000,
- .active_low = 0,
- .adjust_time =20, //adjust for diff product
- },
-};
-
-static struct timed_gpio_platform_data rk29_vibrator_info = {
- .num_gpios = 1,
- .gpios = timed_gpios,
-};
-
-static struct platform_device rk29_device_vibrator = {
- .name = "timed-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_vibrator_info,
- },
-
-};
-#endif
-
-#ifdef CONFIG_DP_ANX6345
-
- #define DVDD33_EN_PIN RK30_PIN0_PB0
- #define DVDD33_EN_VALUE GPIO_LOW
-
- #define DVDD18_EN_PIN RK30_PIN3_PD4//RK30_PIN3_PD4//RK30_PIN1_PB6//RK30_PIN4_PC7
- #define DVDD18_EN_VALUE GPIO_HIGH
-
- #define EDP_RST_PIN RK30_PIN0_PB4
- static int rk_edp_power_ctl(void)
- {
- int ret;
- ret = gpio_request(DVDD33_EN_PIN, "dvdd33_en_pin");
- if (ret != 0)
- {
- gpio_free(DVDD33_EN_PIN);
- printk(KERN_ERR "request dvdd33 en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(DVDD33_EN_PIN, DVDD33_EN_VALUE);
- }
- msleep(5);
-
- ret = gpio_request(DVDD18_EN_PIN, "dvdd18_en_pin");
- if (ret != 0)
- {
- gpio_free(DVDD18_EN_PIN);
- printk(KERN_ERR "request dvdd18 en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(DVDD18_EN_PIN, DVDD18_EN_VALUE);
- }
-
- ret = gpio_request(EDP_RST_PIN, "edp_rst_pin");
- if (ret != 0)
- {
- gpio_free(EDP_RST_PIN);
- printk(KERN_ERR "request rst pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(EDP_RST_PIN, GPIO_LOW);
- msleep(50);
- gpio_direction_output(EDP_RST_PIN, GPIO_HIGH);
- }
- return 0;
-
- }
- static struct anx6345_platform_data anx6345_platform_data = {
- .power_ctl = rk_edp_power_ctl,
- .dvdd33_en_pin = DVDD33_EN_PIN,
- .dvdd33_en_val = DVDD33_EN_VALUE,
- .dvdd18_en_pin = DVDD18_EN_PIN,
- .dvdd18_en_val = DVDD18_EN_VALUE,
- .edp_rst_pin = EDP_RST_PIN,
- };
-#endif
-
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
-static struct gpio_led rk29_leds[] = {
- {
- .name = "button-backlight",
- .gpio = RK30_PIN2_PB3,
- .default_trigger = "timer",
- .active_low = 0,
- .retain_state_suspended = 0,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- },
-};
-
-static struct gpio_led_platform_data rk29_leds_pdata = {
- .leds = rk29_leds,
- .num_leds = ARRAY_SIZE(rk29_leds),
-};
-
-static struct platform_device rk29_device_gpio_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_leds_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_RK_IRDA
-#define IRDA_IRQ_PIN RK30_PIN0_PA3
-
-static int irda_iomux_init(void)
-{
- int ret = 0;
-
- //irda irq pin
- ret = gpio_request(IRDA_IRQ_PIN, NULL);
- if (ret != 0) {
- gpio_free(IRDA_IRQ_PIN);
- printk(">>>>>> IRDA_IRQ_PIN gpio_request err \n ");
- }
- gpio_pull_updown(IRDA_IRQ_PIN, PullDisable);
- gpio_direction_input(IRDA_IRQ_PIN);
-
- return 0;
-}
-
-static int irda_iomux_deinit(void)
-{
- gpio_free(IRDA_IRQ_PIN);
- return 0;
-}
-
-static struct irda_info rk29_irda_info = {
- .intr_pin = IRDA_IRQ_PIN,
- .iomux_init = irda_iomux_init,
- .iomux_deinit = irda_iomux_deinit,
- //.irda_pwr_ctl = bu92747guw_power_ctl,
-};
-
-static struct platform_device irda_device = {
-#ifdef CONFIG_RK_IRDA_NET
- .name = "rk_irda",
-#else
- .name = "bu92747_irda",
-#endif
- .id = -1,
- .dev = {
- .platform_data = &rk29_irda_info,
- }
-};
-#endif
-
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and sdio.noted by xbw at 2012-03-05
-**************************************************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "board-LR097-sdmmc-config.c"
-#include "../plat-rk/rk-sdmmc-ops.c"
-#include "../plat-rk/rk-sdmmc-wifi.c"
-#endif //endif ---#ifdef CONFIG_SDMMC_RK29
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- iomux_set(MMC0_CMD);
- iomux_set(MMC0_CLKOUT);
- iomux_set(MMC0_D0);
- iomux_set(MMC0_D1);
- iomux_set(MMC0_D2);
- iomux_set(MMC0_D3);
-
- iomux_set_gpio_mode(iomux_mode_to_gpio(MMC0_DETN));
-
- gpio_request(RK30_PIN3_PA7, "sdmmc-power");
- gpio_direction_output(RK30_PIN3_PA7, GPIO_LOW);
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- #if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set_gpio_mode(iomux_gpio_to_mode(RK29SDK_SD_CARD_DETECT_N));
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO);
- #endif
- #else
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(MMC0_DETN);
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FMUX);
- #endif
- #endif
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) && defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- .status = rk29sdk_wifi_mmc0_status,
- .register_status_notify = rk29sdk_wifi_mmc0_status_register,
-#endif
-
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .power_en = RK29SDK_SD_CARD_PWR_EN,
- .power_en_level = RK29SDK_SD_CARD_PWR_EN_LEVEL,
-#else
- .power_en = INVALID_GPIO,
- .power_en_level = GPIO_LOW,
-#endif
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC0_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- .det_pin_info = {
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N, //INVALID_GPIO,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
- #endif
- },
-
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- iomux_set(MMC1_CMD);
- iomux_set(MMC1_CLKOUT);
- iomux_set(MMC1_D0);
- iomux_set(MMC1_D1);
- iomux_set(MMC1_D2);
- iomux_set(MMC1_D3);
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC) || defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC1_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- #if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
- .sdio_INT_gpio = RK29SDK_WIFI_SDIO_CARD_INT,
- #endif
-
- .det_pin_info = {
-#if defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- #else
- .io = INVALID_GPIO,
- #endif
-
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-
- .enable_sd_wakeup = 0,
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-/**************************************************************************************************
- * the end of setting for SDMMC devices
-**************************************************************************************************/
-
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
-
-static int batt_table[2*11+6] =
-{
- 0x4B434F52,0x7461625F,0x79726574,1,470,100,
- 6800, 7242, 7332, 7404, 7470, 7520, 7610, 7744, 7848, 8016, 8284,//discharge
- 7630, 7754, 7852, 7908, 7956, 8024, 8112, 8220, 8306, 8318, 8458//charge
-};
-
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = RK30_PIN0_PB2,
- .batt_low_pin = INVALID_GPIO,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = RK30_PIN0_PA6,
- .dc_det_level = GPIO_LOW,
- .charge_ok_level = GPIO_HIGH,
-
- .reference_voltage = 1800,
- .pull_up_res = 470, //divider resistance , pull-up resistor
- .pull_down_res = 100, //divider resistance , pull-down resistor
- .is_reboot_charging = 1,
- .save_capacity = 1 ,
- .use_board_table = 1,
- .board_batt_table = batt_table,
-};
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-#ifdef CONFIG_RK30_PWM_REGULATOR
-static int pwm_voltage_map[] = {
- 800000,825000,850000, 875000,900000, 925000 ,950000, 975000,1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000,1375000
-};
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_cpu",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] =
-{
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
- .pwm_id = 1,
- .pwm_gpio = RK30_PIN3_PD4,
- .pwm_iomux_pwm = PWM1,
- .pwm_iomux_gpio = GPIO3_D4,
- .pwm_voltage = 1100000,
- .suspend_voltage = 1000000,
- .min_uV = 800000,
- .max_uV = 1375000,
- .coefficient = 575, //57.5%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-#endif
-
-#ifdef CONFIG_RK29_VMAC
-#define PHY_PWR_EN_GPIO RK30_PIN1_PD6
-#include "board-rk30-sdk-vmac.c"
-#endif
-
-#ifdef CONFIG_RFKILL_RK
-// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
-static struct rfkill_rk_platform_data rfkill_rk_platdata = {
- .type = RFKILL_TYPE_BLUETOOTH,
-
- .poweron_gpio = { // BT_REG_ON
- .io = INVALID_GPIO, //RK30_PIN3_PC7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_poweron",
- .fgpio = GPIO3_C7,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN3_PC7, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_reset",
- .fgpio = GPIO3_C7,
- },
- },
-
- .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
- .io = RK30_PIN3_PC6, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_wake",
- .fgpio = GPIO3_C6,
- },
- },
-
- .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .gpio = {
- .io = RK30_PIN0_PA5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
- .iomux = {
- .name = NULL,
- },
- },
- },
-
- .rts_gpio = { // UART_RTS, enable or disable BT's data coming
- .io = RK30_PIN1_PA3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_rts",
- .fgpio = GPIO1_A3,
- .fmux = UART0_RTSN,
- },
- },
-};
-
-static struct platform_device device_rfkill_rk = {
- .name = "rfkill_rk",
- .id = -1,
- .dev = {
- .platform_data = &rfkill_rk_platdata,
- },
-};
-#endif
-
-#if defined(CONFIG_GPS_RK)
-int rk_gps_io_init(void)
-{
- printk("%s \n", __FUNCTION__);
-
- gpio_request(RK30_PIN1_PB5, NULL);
- gpio_direction_output(RK30_PIN1_PB5, GPIO_LOW);
-
- iomux_set(GPS_RFCLK);//GPS_CLK
- iomux_set(GPS_MAG);//GPS_MAG
- iomux_set(GPS_SIG);//GPS_SIGN
-
- gpio_request(RK30_PIN1_PA6, NULL);
- gpio_direction_output(RK30_PIN1_PA6, GPIO_LOW);
-
- gpio_request(RK30_PIN1_PA5, NULL);
- gpio_direction_output(RK30_PIN1_PA5, GPIO_LOW);
-
- gpio_request(RK30_PIN1_PA7, NULL);
- gpio_direction_output(RK30_PIN1_PA7, GPIO_LOW);
- return 0;
-}
-int rk_gps_power_up(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_power_down(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_reset_set(int level)
-{
- return 0;
-}
-int rk_enable_hclk_gps(void)
-{
- printk("%s \n", __FUNCTION__);
- clk_enable(clk_get(NULL, "hclk_gps"));
- return 0;
-}
-int rk_disable_hclk_gps(void)
-{
- printk("%s \n", __FUNCTION__);
- clk_disable(clk_get(NULL, "hclk_gps"));
- return 0;
-}
-struct rk_gps_data rk_gps_info = {
- .io_init = rk_gps_io_init,
- .power_up = rk_gps_power_up,
- .power_down = rk_gps_power_down,
- .reset = rk_gps_reset_set,
- .enable_hclk_gps = rk_enable_hclk_gps,
- .disable_hclk_gps = rk_disable_hclk_gps,
- .GpsSign = RK30_PIN1_PB3,
- .GpsMag = RK30_PIN1_PB2, //GPIO index
- .GpsClk = RK30_PIN1_PB4, //GPIO index
- .GpsVCCEn = RK30_PIN1_PB5, //GPIO index
- .GpsSpi_CSO = RK30_PIN1_PA4, //GPIO index
- .GpsSpiClk = RK30_PIN1_PA5, //GPIO index
- .GpsSpiMOSI = RK30_PIN1_PA7, //GPIO index
- .GpsIrq = IRQ_GPS,
- .GpsSpiEn = 0,
- .GpsAdcCh = 2,
- .u32GpsPhyAddr = RK30_GPS_PHYS,
- .u32GpsPhySize = RK30_GPS_SIZE,
-};
-
-struct platform_device rk_device_gps = {
- .name = "gps_hv5820b",
- .id = -1,
- .dev = {
- .platform_data = &rk_gps_info,
- }
- };
-#endif
-
-#if defined(CONFIG_MT5931_MT6622)
-static struct mt6622_platform_data mt6622_platdata = {
- .power_gpio = { // BT_REG_ON
- .io = RK30_PIN3_PC7, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mt6622_power",
- .fgpio = GPIO3_C7,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN3_PD1,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .irq_gpio = {
- .io = RK30_PIN0_PA5,
- .enable = GPIO_LOW,
- .iomux = {
- .name = NULL,
- },
- },
-
- .rts_gpio = { // UART_RTS
- .io = RK30_PIN1_PA3,
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_rts",
- .fgpio = GPIO1_A3,
- .fmux = UART0_RTSN,
- },
- },
-};
-
-static struct platform_device device_mt6622 = {
- .name = "mt6622",
- .id = -1,
- .dev = {
- .platform_data = &mt6622_platdata,
- },
-};
-
-#endif
-
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_ANDROID_TIMED_GPIO
- &rk29_device_vibrator,
-#endif
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
- &rk29_device_gpio_leds,
-#endif
-#ifdef CONFIG_RK_IRDA
- &irda_device,
-#endif
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- &rk29sdk_wifi_device,
-#endif
-#ifdef CONFIG_RK29_SUPPORT_MODEM
- &rk30_device_modem,
-#endif
-#if defined(CONFIG_MU509)
- &rk29_device_mu509,
-#endif
-#if defined(CONFIG_MW100)
- &rk29_device_mw100,
-#endif
-#if defined(CONFIG_MT6229)
- &rk29_device_mt6229,
-#endif
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
- &rk30_device_adc_battery,
-#endif
-#ifdef CONFIG_RFKILL_RK
- &device_rfkill_rk,
-#endif
-#ifdef CONFIG_GPS_RK
- &rk_device_gps,
-#endif
-#ifdef CONFIG_MT5931_MT6622
- &device_mt6622,
-#endif
-#if defined(CONFIG_ARCH_RK3188)
- &device_mali,
-#endif
-
-};
-static int rk_platform_add_display_devices(void)
-{
- struct platform_device *fb = NULL; //fb
- struct platform_device *lcdc0 = NULL; //lcdc0
- struct platform_device *lcdc1 = NULL; //lcdc1
- struct platform_device *bl = NULL; //backlight
-#ifdef CONFIG_FB_ROCKCHIP
- fb = &device_fb;
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
- lcdc0 = &device_lcdc0,
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
- lcdc1 = &device_lcdc1,
-#endif
-
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- bl = &rk29_device_backlight,
-#endif
- __rk_platform_add_display_devices(fb,lcdc0,lcdc1,bl);
-
- return 0;
-
-}
-// i2c
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1d,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_GS_LIS3DH)
- {
- .type = "gs_lis3dh",
- .addr = 0x19, //0x19(SA0-->VCC), 0x18(SA0-->GND)
- .flags = 0,
- .irq = LIS3DH_INT_PIN,
- .platform_data = &lis3dh_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8975_info,
- },
-#endif
-#if defined (CONFIG_GYRO_L3G4200D)
- {
- .type = "l3g4200d_gryo",
- .addr = 0x69,
- .flags = 0,
- .irq = L3G4200D_INT_PIN,
- .platform_data = &l3g4200d_info,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_CHARGER_CW2015)
- {
- .type = "cw2015",
- .addr = 0x62,
- .flags = 0,
- .platform_data = &cw2015_info,
- },
-#endif
-};
-#endif
-
-int __sramdata g_pmic_type = 0;
-#ifdef CONFIG_I2C1_RK30
-
-#ifdef CONFIG_MFD_WM831X_I2C
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info wm8326_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "dcdc3", //ddr
- .min_uv = 1150000,
- .max_uv = 1150000,
- .suspend_vol = 1150000,
- },
- #ifdef CONFIG_MACH_RK3066_SDK
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3000000,
- },
- #else
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3000000,
- .max_uv = 3000000,
- .suspend_vol = 2800000,
- },
- #endif
-};
-
-static struct pmu_info wm8326_ldo_info[] = {
- {
- .name = "ldo1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo2", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo3", //
- .min_uv = 1100000,
- .max_uv = 1100000,
- .suspend_vol = 1100000,
- },
- {
- .name = "ldo4", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 1000000,
- },
- {
- .name = "ldo5", //vcc25
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo6", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo7", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- .suspend_vol = 2800000,
- },
- {
- .name = "ldo8", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo9", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo10", //flash_io
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
-};
-
-#include "board-pmu-wm8326.c"
-#endif
-
-#ifdef CONFIG_MFD_TPS65910
-
-#define TPS65910_HOST_IRQ RK30_PIN0_PB3
-
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info tps65910_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1100000,
- .max_uv = 1100000,
- },
- {
- .name = "vdd2", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vio", //vcc_io
- .min_uv = 2500000,
- .max_uv = 2500000,
- },
-
-};
-static struct pmu_info tps65910_ldo_info[] = {
- {
- .name = "vpll", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "vdig2", //vdd_jetta
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vaux1", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "vaux2", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vaux33", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vmmc", //vcc30
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
- {
- .name = "vdac", //vcc18
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- };
-
-#include "board-pmu-tps65910.c"
-#endif
-
-#ifdef CONFIG_REGULATOR_ACT8846
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-#define ACT8846_HOST_IRQ RK30_PIN0_PB3
-#define PMU_VSEL RK30_PIN3_PD3
-
-static struct pmu_info act8846_dcdc_info[] = {
- {
- .name = "act_dcdc1", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- .suspend_vol = 1200000,
- },
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 1200000,
- #else
- .suspend_vol = 900000,
- #endif
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 1200000,
- #else
- .suspend_vol = 900000,
- #endif
- },
- {
- .name = "act_dcdc4", //vccio
- .min_uv = 3300000,
- .max_uv = 3300000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 3000000,
- #else
- .suspend_vol = 2800000,
- #endif
- },
-
-};
-static struct pmu_info act8846_ldo_info[] = {
- {
- .name = "act_ldo1", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "act_ldo2", //vdd12
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "act_ldo3", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo4", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo5", //vcctp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo6", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo7", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo8", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- };
-
-#include "board-pmu-act8846.c"
-#endif
-
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_MFD_WM831X_I2C)
- {
- .type = "wm8326",
- .addr = 0x34,
- .flags = 0,
- .irq = RK30_PIN0_PB3,
- .platform_data = &wm831x_platdata,
- },
-#endif
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-#if defined (CONFIG_REGULATOR_ACT8846)
- {
- .type = "act8846",
- .addr = 0x5a,
- .flags = 0,
- // .irq = ACT8846_HOST_IRQ,
- .platform_data=&act8846_data,
- },
-#endif
-#if defined (CONFIG_RTC_HYM8563)
- {
- .type = "rtc_hym8563",
- .addr = 0x51,
- .flags = 0,
- .irq = RK30_PIN0_PB5,
- },
-#endif
-};
-#endif
-
-void __sramfunc board_pmu_suspend(void)
-{
-#if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_suspend();
-#endif
-#if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_suspend();
-#endif
-#if defined (CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- board_pmu_act8846_suspend();
-#endif
-}
-
-void __sramfunc board_pmu_resume(void)
-{
-#if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_resume();
-#endif
-#if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_resume();
-#endif
-#if defined (CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- board_pmu_act8846_resume();
-#endif
-
-}
-
- int __sramdata gpio3d6_iomux,gpio3d6_do,gpio3d6_dir,gpio3d6_en;
-
-#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
-
-void __sramfunc rk30_pwm_logic_suspend_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
-
-// int gpio0d7_iomux,gpio0d7_do,gpio0d7_dir,gpio0d7_en;
- sram_udelay(10000);
- gpio3d6_iomux = grf_readl(GRF_GPIO3D_IOMUX);
- gpio3d6_do = grf_readl(GRF_GPIO3H_DO);
- gpio3d6_dir = grf_readl(GRF_GPIO3H_DIR);
- gpio3d6_en = grf_readl(GRF_GPIO3H_EN);
-
- grf_writel((1<<28), GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DIR);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DO);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_EN);
-#endif
-}
-void __sramfunc rk30_pwm_logic_resume_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- grf_writel((1<<28)|gpio3d6_iomux, GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|gpio3d6_en, GRF_GPIO3H_EN);
- grf_writel((1<<30)|gpio3d6_dir, GRF_GPIO3H_DIR);
- grf_writel((1<<30)|gpio3d6_do, GRF_GPIO3H_DO);
- sram_udelay(10000);
-
-#endif
-
-}
-extern void pwm_suspend_voltage(void);
-extern void pwm_resume_voltage(void);
-void rk30_pwm_suspend_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_suspend_voltage();
-#endif
-}
-void rk30_pwm_resume_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_resume_voltage();
-#endif
-}
-
-
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-#if defined (CONFIG_TOUCHSCREEN_GT8XX)
- {
- .type = "Goodix-TS",
- .addr = 0x55,
- .flags = 0,
- .irq = RK30_PIN1_PB7,
- .platform_data = &goodix_info,
- },
-#endif
-#if defined (CONFIG_LS_CM3217)
- {
- .type = "lightsensor",
- .addr = 0x10,
- .flags = 0,
- .platform_data = &cm3217_info,
- },
-#endif
-
-#if defined (CONFIG_DP_ANX6345)
- {
- .type = "anx6345",
- .addr = 0x39,
- .flags = 0,
- .platform_data = &anx6345_platform_data,
- },
-#endif
-
-
-#if defined (CONFIG_CT36X_TS)
- {
- .type = CT36X_NAME,
- .addr = 0x01,
- .flags = 0,
- .platform_data = &ct36x_info,
- },
-#endif
-#if defined(CONFIG_HDMI_CAT66121)
- {
- .type = "cat66121_hdmi",
- .addr = 0x4c,
- .flags = 0,
- .irq = RK30_PIN2_PD6,
- .platform_data = &rk_hdmi_pdata,
- },
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C4_RK30
-static struct i2c_board_info __initdata i2c4_info[] = {
-#ifdef CONFIG_MFD_RK610
- {
- .type = "rk610_ctl",
- .addr = 0x40,
- .flags = 0,
- .platform_data = &rk610_ctl_pdata,
- },
-#ifdef CONFIG_RK610_TVOUT
- {
- .type = "rk610_tvout",
- .addr = 0x42,
- .flags = 0,
- },
-#endif
-#ifdef CONFIG_HDMI_RK610
- {
- .type = "rk610_hdmi",
- .addr = 0x46,
- .flags = 0,
- .irq = INVALID_GPIO,
- },
-#endif
-#ifdef CONFIG_SND_SOC_RK610
- {//RK610_CODEC addr from 0x60 to 0x80 (0x60~0x80)
- .type = "rk610_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- .platform_data = &rk610_codec_pdata,
- },
-#endif
-#endif
-#ifdef CONFIG_SND_SOC_RT5631
- {
- .type = "rt5631",
- .addr = 0x1a,
- .flags = 0,
- },
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO// RK30_PIN2_PD6 //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO//RK30_PIN2_PD7 //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- //set iomux (gpio) here
- //rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME, GPIO2D_GPIO2D7);
- //rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME, GPIO2D_GPIO2D6);
-
- return 0;
-}
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C4_RK30
- i2c_register_board_info(4, i2c4_info, ARRAY_SIZE(i2c4_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(5, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-
-// ========== Begin of rk3168 top board keypad defination ============
-
-#include <plat/key.h>
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .adc_value = 145,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK30_PIN0_PA4,
- .active_low = PRESS_LEV_LOW,
- .wakeup = 1,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .adc_value = 1,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- #if 0
- {
- .desc = "menu",
- .code = EV_MENU,
- .adc_value = 133,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- #endif
- {
- .desc = "home",
- .code = KEY_HOME,
- .adc_value = 355,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- #if 0
- {
- .desc = "esc",
- .code = KEY_BACK,
- .adc_value = 333,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-
- {
- .desc = "camera",
- .code = KEY_CAMERA,
- .adc_value = 742,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- #endif
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = 1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
-// =========== End of rk3168 top board keypad defination =============
-
-
-#define POWER_ON_PIN RK30_PIN0_PA0 //power_hold
-static void rk30_pm_power_off(void)
-{
- printk(KERN_ERR "rk30_pm_power_off start...\n");
- #if defined(CONFIG_MFD_WM831X)
- if(pmic_is_wm8326()){
- wm831x_set_bits(Wm831x,WM831X_GPIO_LEVEL,0x0001,0x0000); //set sys_pwr 0
- wm831x_device_shutdown(Wm831x);//wm8326 shutdown
- }
- #endif
-
- #if defined(CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- {
- printk("enter dcdet:");
- if(gpio_get_value (RK30_PIN0_PB2) == GPIO_LOW)
- {
- printk("with dc:enter restart system\n");
- arm_pm_restart(0, NULL);
- }
- else
- {
- printk("without dc,shutdown system\n");
- act8846_device_shutdown();
- //while(1);
- }
- }
- #endif
-
- #if defined(CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- {
- tps65910_device_shutdown();//tps65910 shutdown
- }
- #endif
-
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
- while (1);
-}
-
-static void __init machine_rk30_board_init(void)
-{
- //avs_init();
- gpio_request(POWER_ON_PIN, "poweronpin");
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
- pm_power_off = rk30_pm_power_off;
-
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
-
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- rk_platform_add_display_devices();
- board_usb_detect_init(RK30_PIN0_PA7);
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- rk29sdk_wifi_bt_gpio_control_init();
-#endif
-#if defined(CONFIG_MT5931_MT6622)
- clk_set_rate(clk_get_sys("rk_serial.0", "uart"), 24*1000000);
-#endif
-}
-
-#define HD_SCREEN_SIZE 1920UL*1200UL*4*3
-static void __init rk30_reserve(void)
-{
-#if defined(CONFIG_ARCH_RK3188)
- /*if lcd resolution great than or equal to 1920*1200,reserve the ump memory */
- if(!(get_fb_size() < ALIGN(HD_SCREEN_SIZE,SZ_1M)))
- {
- int ump_mem_phy_size=256UL*1024UL*1024UL;
- resource_mali[0].start = board_mem_reserve_add("ump buf", ump_mem_phy_size);
- resource_mali[0].end = resource_mali[0].start + ump_mem_phy_size -1;
- }
-#endif
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0 buf", get_fb_size());
- resource_fb[0].end = resource_fb[0].start + get_fb_size()- 1;
-#if 0
- resource_fb[1].start = board_mem_reserve_add("ipp buf", RK30_FB0_MEM_SIZE);
- resource_fb[1].end = resource_fb[1].start + RK30_FB0_MEM_SIZE - 1;
-#endif
-
-#if defined(CONFIG_FB_ROTATE) || !defined(CONFIG_THREE_FB_BUFFER)
- resource_fb[2].start = board_mem_reserve_add("fb2 buf",get_fb_size());
- resource_fb[2].end = resource_fb[2].start + get_fb_size() - 1;
-#endif
-#endif
-
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
-
-#ifdef CONFIG_GPS_RK
- //it must be more than 8MB
- rk_gps_info.u32MemoryPhyAddr = board_mem_reserve_add("gps", SZ_8M);
-#endif
- board_mem_reserved();
-}
-
-/**
- * dvfs_cpu_logic_table: table for arm and logic dvfs
- * @frequency : arm frequency
- * @cpu_volt : arm voltage depend on frequency
- * @logic_volt : logic voltage arm requests depend on frequency
- * comments : min arm/logic voltage
- */
-static struct cpufreq_frequency_table dvfs_arm_table[] = {
- {.frequency = 312 * 1000, .index = 850 * 1000},
- {.frequency = 504 * 1000, .index = 900 * 1000},
- {.frequency = 816 * 1000, .index = 950 * 1000},
- {.frequency = 1008 * 1000, .index = 1025 * 1000},
- {.frequency = 1200 * 1000, .index = 1100 * 1000},
- {.frequency = 1416 * 1000, .index = 1200 * 1000},
- {.frequency = 1608 * 1000, .index = 1300 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
-#if defined(CONFIG_ARCH_RK3188)
- {.frequency = 133 * 1000, .index = 975 * 1000},//the mininum rate is limited 133M for rk3188
-#elif defined(CONFIG_ARCH_RK3066B)
- {.frequency = 100 * 1000, .index = 950 * 1000},//the minimum rate is no limit for rk3168 rk3066B
-#endif
-
- {.frequency = 200 * 1000, .index = 975 * 1000},
- {.frequency = 266 * 1000, .index = 1000 * 1000},
- {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1100 * 1000},
- {.frequency = 600 * 1000, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 950 * 1000},
- //{.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = 1000 * 1000},
- {.frequency = 528 * 1000 + DDR_FREQ_NORMAL, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-//#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
-//static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
-//static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
-
-void __init board_clock_init(void)
-{
- rk30_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
- //dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "cpu"), dvfs_arm_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
-}
-
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk30_fixup,
- .reserve = &rk30_reserve,
- .map_io = rk30_map_io,
- .init_irq = rk30_init_irq,
- .timer = &rk30_timer,
- .init_machine = machine_rk30_board_init,
-MACHINE_END
+++ /dev/null
-#ifdef CONFIG_VIDEO_RK29
-#include <plat/rk_camera.h>
-/* Notes:
-
-Simple camera device registration:
-
- new_camera_device(sensor_name,\ // sensor name, it is equal to CONFIG_SENSOR_X
- face,\ // sensor face information, it can be back or front
- pwdn_io,\ // power down gpio configuration, it is equal to CONFIG_SENSOR_POWERDN_PIN_XX
- flash_attach,\ // sensor is attach flash or not
- mir,\ // sensor image mirror and flip control information
- i2c_chl,\ // i2c channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_IIC_ADAPTER_ID_X
- cif_chl) \ // cif channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_CIF_INDEX_X
-
-Comprehensive camera device registration:
-
- new_camera_device_ex(sensor_name,\
- face,\
- ori,\ // sensor orientation, it is equal to CONFIG_SENSOR_ORIENTATION_X
- pwr_io,\ // sensor power gpio configuration, it is equal to CONFIG_SENSOR_POWER_PIN_XX
- pwr_active,\ // sensor power active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- rst_io,\ // sensor reset gpio configuration, it is equal to CONFIG_SENSOR_RESET_PIN_XX
- rst_active,\ // sensor reset active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- pwdn_io,\
- pwdn_active,\ // sensor power down active level, is equal to CONFIG_SENSOR_POWERDNACTIVE_LEVEL_X
- flash_attach,\
- res,\ // sensor resolution, this is real resolution or resoltuion after interpolate
- mir,\
- i2c_chl,\
- i2c_spd,\ // i2c speed , 100000 = 100KHz
- i2c_addr,\ // the i2c slave device address for sensor
- cif_chl,\
- mclk)\ // sensor input clock rate, 24 or 48
-
-*/
-static struct rkcamera_platform_data new_camera[] = {
-
- new_camera_device_ex(RK29_CAM_SENSOR_OV5640,
- back,
- INVALID_VALUE,
- INVALID_VALUE,
- INVALID_VALUE,
- INVALID_VALUE,
- INVALID_VALUE,
- RK30_PIN3_PB5,
- CONS(RK29_CAM_SENSOR_OV5640,_PWRDN_ACTIVE),
- 1,
- CONS(RK29_CAM_SENSOR_OV5640,_FULL_RESOLUTION),
- 0x00,
- 3,
- 100000,
- CONS(RK29_CAM_SENSOR_OV5640,_I2C_ADDR),
- 0,
- 24),
- new_camera_device(RK29_CAM_SENSOR_OV2659,
- front,
- RK30_PIN3_PB4,
- 0,
- 0,
- 3,
- 0),
- new_camera_device_end
-};
-/*---------------- Camera Sensor Macro Define Begin ------------------------*/
-/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
-#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_OV5640 /* back camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_0 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 3
-#define CONFIG_SENSOR_ORIENTATION_0 90
-#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 RK30_PIN3_PB5
-#define CONFIG_SENSOR_FALSH_PIN_0 RK30_PIN0_PD5 //INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_H
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000
-
-#define CONFIG_SENSOR_01 RK29_CAM_SENSOR_OV5642 /* back camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_01 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 4
-#define CONFIG_SENSOR_ORIENTATION_01 90
-#define CONFIG_SENSOR_POWER_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_01 RK30_PIN1_PD6
-#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_01 30000
-
-#define CONFIG_SENSOR_02 RK29_CAM_SENSOR_OV5640 /* back camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_02 0x00
-#define CONFIG_SENSOR_CIF_INDEX_02 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 4
-#define CONFIG_SENSOR_ORIENTATION_02 90
-#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000
-
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_OV2659 /* front camera sensor 0 */
-#define CONFIG_SENSOR_IIC_ADDR_1 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 3
-#define CONFIG_SENSOR_ORIENTATION_1 270
-#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_1 RK30_PIN3_PB4
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000
-
-#define CONFIG_SENSOR_11 RK29_CAM_SENSOR_OV2659 /* front camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_11 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 3
-#define CONFIG_SENSOR_ORIENTATION_11 270
-#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_11 INVALID_GPIO//RK30_PIN1_PB7
-#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_11 30000
-
-#define CONFIG_SENSOR_12 RK29_CAM_SENSOR_OV2659//RK29_CAM_SENSOR_OV2655 /* front camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_12 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 3
-#define CONFIG_SENSOR_ORIENTATION_12 270
-#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_12 INVALID_GPIO//RK30_PIN1_PB7
-#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_12 30000
-
-
-#endif //#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk30_camera.c"
-/*---------------- Camera Sensor Macro Define End ---------*/
-
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#define CONFIG_SENSOR_POWER_IOCTL_USR 0 //define this refer to your board layout
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 1
-
-static void rk_cif_power(int on)
-{
- struct regulator *ldo_18,*ldo_28;
- ldo_28 = regulator_get(NULL, "ldo7"); // vcc28_cif
- ldo_18 = regulator_get(NULL, "ldo1"); // vcc18_cif
- if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){
- printk("get cif ldo failed!\n");
- return;
- }
- if(on == 0){
- regulator_disable(ldo_28);
- regulator_put(ldo_28);
- regulator_disable(ldo_18);
- regulator_put(ldo_18);
- mdelay(500);
- }
- else{
- regulator_set_voltage(ldo_28, 2800000, 2800000);
- regulator_enable(ldo_28);
- // printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
- regulator_put(ldo_28);
-
- regulator_set_voltage(ldo_18, 1800000, 1800000);
- // regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(ldo_18);
- // printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
- regulator_put(ldo_18);
- }
-}
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- //#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
- rk_cif_power(on);
- return 0;
-}
-#endif
-
-#if CONFIG_SENSOR_RESET_IOCTL_USR
-static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
-static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-
-#define CONFIG_SENSOR_FALSH_EN_PIN_0 RK30_PIN0_PD5 //high:enable
-#define CONFIG_SENSOR_FALSH_EN_MUX_0 GPIO0D5_SPI1TXD_NAME
-#define CONFIG_SENSOR_FALSH_MODE_PIN_0 RK30_PIN0_PD4 //high:FLASH, low:torch
-#define CONFIG_SENSOR_FALSH_MODE_MUX_0 GPIO0D4_SPI1RXD_NAME
-
-static int sensor_init_flags = 0;
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- if(sensor_init_flags == 0){
- rk30_mux_api_set(CONFIG_SENSOR_FALSH_MODE_MUX_0, 0);
- int ret = gpio_request(CONFIG_SENSOR_FALSH_MODE_PIN_0, "camera_flash_mode");
- if (ret != 0) {
- printk(">>>>gpio request camera_flash_mode faile !!\n");
- }
-
- gpio_direction_output(CONFIG_SENSOR_FALSH_MODE_PIN_0, 0);
- sensor_init_flags = 1 ;
- }
- switch (on) {
- case Flash_Off: {
- gpio_set_value(CONFIG_SENSOR_FALSH_EN_PIN_0, 0);
- gpio_set_value(CONFIG_SENSOR_FALSH_MODE_PIN_0, 0);
- break;
- }
-
- case Flash_On: {
- gpio_set_value(CONFIG_SENSOR_FALSH_EN_PIN_0, 1);
- gpio_set_value(CONFIG_SENSOR_FALSH_MODE_PIN_0, 1);
- break;
- }
-
- case Flash_Torch: {
- gpio_set_value(CONFIG_SENSOR_FALSH_EN_PIN_0, 1);
- gpio_set_value(CONFIG_SENSOR_FALSH_MODE_PIN_0, 0);
- break;
- }
-
- default: {
- printk("%s..Flash command(%d) is invalidate \n",__FUNCTION__, on);
- gpio_set_value(CONFIG_SENSOR_FALSH_EN_PIN_0, 0);
- break;
- }
- }
- return 0;
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-
-#if CONFIG_SENSOR_IIC_ADDR_0
-static struct reginfo_t rk_init_data_sensor_reg_0[] =
-{
- {0x0000, 0x00,0,0}
- };
-static struct reginfo_t rk_init_data_sensor_winseqreg_0[] ={
- {0x0000, 0x00,0,0}
- };
-#endif
-
-#if CONFIG_SENSOR_IIC_ADDR_1
-static struct reginfo_t rk_init_data_sensor_reg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_01
-static struct reginfo_t rk_init_data_sensor_reg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_02
-static struct reginfo_t rk_init_data_sensor_reg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_11
-static struct reginfo_t rk_init_data_sensor_reg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_12
-static struct reginfo_t rk_init_data_sensor_reg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] =
-{
- #if CONFIG_SENSOR_IIC_ADDR_0
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_0,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_1
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_1,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_01
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_01,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_02
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_02,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_11
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_11,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_12
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_12,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
-
- };
-#include "../../../drivers/media/video/rk30_camera.c"
-
-#endif /* CONFIG_VIDEO_RK29 */
+++ /dev/null
-/*****************************************************************************************
- * arch/arm/mach-rkxx/baord-xxx-sdmmc-config.c
- *
- * Copyright (C) 2013 ROCKCHIP, Inc.
- *
- * Description:
- * define the gpio for SD-MMC-SDIO-Wifi functions according to your own projects.
- *
- * Author: Michael Xie
- * 15 Jan,2013
- * E-mail: xbw@rock-chips.com
- *
- ******************************************************************************************/
-
-/*
-** If you select the macro of CONFIG_SDMMC0_RK29_WRITE_PROTECT, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define SDMMC0_WRITE_PROTECT_PIN RK30_PIN3_PB2 //According to your own project to set the value of write-protect-pin.
-//#define SDMMC0_WRITE_PROTECT_ENABLE_VALUE GPIO_HIGH
-
-/*
-** If you select the macro of CONFIG_SDMMC1_RK29_WRITE_PROTECT, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define SDMMC1_WRITE_PROTECT_PIN RK30_PIN3_PB3 //According to your own project to set the value of write-protect-pin.
-//#define SDMMC1_WRITE_PROTECT_ENABLE_VALUE GPIO_HIGH
-
-/*
-** If you select the macro of CONFIG_RK29_SDIO_IRQ_FROM_GPIO, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define RK29SDK_WIFI_SDIO_CARD_INT RK30_PIN3_PD2
-
-
-/*
-* define sdcard PowerEn-pin
-*/
-#define RK29SDK_SD_CARD_PWR_EN RK30_PIN3_PA1
-#define RK29SDK_SD_CARD_PWR_EN_LEVEL GPIO_LOW
-
-/*
-* define the card-detect-pin.
-*/
-#define RK29SDK_SD_CARD_DETECT_N RK30_PIN3_PB0 //According to your own project to set the value of card-detect-pin.
-#define RK29SDK_SD_CARD_INSERT_LEVEL GPIO_LOW // set the voltage of insert-card. Please pay attention to the default setting.
-
-/*
-* Define wifi module's power and reset gpio, and gpio sensitive level.
-* Please set the value according to your own project.
-*
-* Well, you just own engineering module to set the value in the corresponding module branch.
-* Otherwise, you do not define this macro, eliminate it.
-*
-*/
-#if defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU)
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_LOW//GPIO_HIGH
-
-#elif defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319) || defined(CONFIG_RK903) || defined(CONFIG_RK901)
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN2_PA7
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
-
-#elif defined(CONFIG_MT5931_MT6622) || defined(CONFIG_MT5931)
-
- #ifdef CONFIG_MACH_RK3168_LR097
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- //#define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- //#define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
-
- #else
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN0_PA5
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #endif
-
-#elif defined(CONFIG_MT6620)
- #define COMBO_MODULE_MT6620_CDT 1 // to control antsel2,antsel3 and gps_lan foot when using AcSip or Cdtech chip.
- //- 1--use Cdtech chip; 0--unuse CDT chip
-
- //power, PMU_EN
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PC7
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- //reset, DAIRST,SYSRST_B
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- //VDDIO
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL RK30_PIN0_PD2 //You do not get control of the foot, and you do not need to define the macro
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_ENABLE_VALUE GPIO_HIGH
- //WIFI_INT_B
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
- //BGF_INT_B
- #define RK30SDK_WIFI_GPIO_BGF_INT_B RK30_PIN6_PA7
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_ENABLE_VALUE GPIO_HIGH
- //GPS_SYNC
- #define RK30SDK_WIFI_GPIO_GPS_SYNC RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_ENABLE_VALUE GPIO_HIGH
-
- #if COMBO_MODULE_MT6620_CDT
- //ANTSEL2
- #define RK30SDK_WIFI_GPIO_ANTSEL2 RK30_PIN4_PD4
- #define RK30SDK_WIFI_GPIO_ANTSEL2_ENABLE_VALUE GPIO_LOW //use 6620 in CDT chip, LOW--work; High--no work.
- //ANTSEL3
- #define RK30SDK_WIFI_GPIO_ANTSEL3 RK30_PIN4_PD3
- #define RK30SDK_WIFI_GPIO_ANTSEL3_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- //GPS_LAN
- #define RK30SDK_WIFI_GPIO_GPS_LAN RK30_PIN4_PD6
- #define RK30SDK_WIFI_GPIO_GPS_LAN_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- #endif // #if COMBO_MODULE_MT6620_CDT--#endif
-#endif
-
-double rk31sdk_get_sdio_wifi_voltage(void)
-{
- double voltage;
-
- /******************************************************************************
- ** Please tell me how much wifi-module uses voltage in your project.
- ******************************************************************************/
-#if defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319) || defined(CONFIG_RK903) || defined(CONFIG_RK901)
- voltage = 1800 ; //power 1.8V
-
-#elif defined(CONFIG_MT5931_MT6622)||defined(CONFIG_MT5931)||defined(CONFIG_MT6620)
- voltage = 2800 ; //power 2.8V
-#elif defined(CONFIG_RDA5990)||defined(CONFIG_RTL8723AS)
- voltage = 3300 ; //power 3.3V
-#else
- //default, sdio use 3.0V
- voltage = 3000 ; //power 3.0V
-#endif
-
- return voltage;
-}
-
-
-
+++ /dev/null
-/*
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <mach/dvfs.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <linux/rk_fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/mfd/tps65910.h>
-#include <linux/regulator/act8846.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-#if defined(CONFIG_CT36X_TS)
-#include <linux/ct36x.h>
-#endif
-#if defined(CONFIG_MFD_RK610)
-#include <linux/mfd/rk610_core.h>
-#endif
-
-#if defined(CONFIG_RK_HDMI)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-#if defined(CONFIG_GPS_RK)
-#include "../../../drivers/misc/gps/rk_gps/rk_gps.h"
-#endif
-
-#if defined(CONFIG_MT6620)
-#include <linux/gps.h>
-#endif
-
-#include "board-rk3168-ds1006h-camera.c"
-#include <plat/key.h>
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK30_PIN0_PA4,
- .active_low = PRESS_LEV_LOW,
- .wakeup = 1,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .adc_value = 1,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = 1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
-#if defined(CONFIG_CT36X_TS)
-
-#define TOUCH_MODEL 363
-#define TOUCH_MAX_X 1280
-#define TOUCH_MAX_y 800
-#define TOUCH_RESET_PIN RK30_PIN0_PB6
-#define TOUCH_INT_PIN RK30_PIN1_PB7
-
-static struct ct36x_platform_data ct36x_info = {
- .model = TOUCH_MODEL,
- .x_max = TOUCH_MAX_X,
- .y_max = TOUCH_MAX_y,
-
- .rst_io = {
- .gpio = TOUCH_RESET_PIN,
- .active_low = 1,
- },
- .irq_io = {
- .gpio = TOUCH_INT_PIN,
- .active_low = 1,
- },
- .orientation = {1, 0, 1, 0},
-};
-#endif
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-#define PWM_ID 3
-#define PWM_MODE PWM3
-#define PWM_EFFECT_VALUE 1
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-#define BL_EN_PIN RK30_PIN0_PA2
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
-
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
- ret = gpio_request(BL_EN_PIN, NULL);
- if (ret != 0) {
- gpio_free(BL_EN_PIN);
- }
-
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
-
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0, pwm_gpio;
-
-#ifdef LCD_DISP_ON_PIN
- gpio_free(BL_EN_PIN);
-#endif
-
- pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
- gpio_request(pwm_gpio, NULL);
- gpio_direction_output(pwm_gpio, GPIO_LOW);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret = 0, pwm_gpio;
-
- pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
- if (gpio_request(pwm_gpio, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- gpio_direction_output(pwm_gpio, GPIO_LOW);
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, !BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- int pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
-
- gpio_free(pwm_gpio);
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, 1);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .min_brightness = 30,
- .pre_div = 20 * 1000, // pwm output clk: 20k;
- .pwm_id = PWM_ID,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-#endif
-
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN RK30_PIN0_PB7
-
-static int mma8452_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data mma8452_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma8452_init_platform_hw,
- .orientation = {-1, 0, 0, 0, 0, 1, 0, 1, 0},
-};
-#endif
-#if defined (CONFIG_GS_LIS3DH)
-#define LIS3DH_INT_PIN RK30_PIN0_PB7
-
-static int lis3dh_init_platform_hw(void)
-{
-
- return 0;
-}
-
-static struct sensor_platform_data lis3dh_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lis3dh_init_platform_hw,
- .orientation = {-1, 0, 0, 0, 0, 1, 0, -1, 0},
-};
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
-static struct sensor_platform_data akm8975_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-#if defined(CONFIG_GYRO_L3G4200D)
-
-#include <linux/l3g4200d.h>
-#define L3G4200D_INT_PIN RK30_PIN0_PB4
-
-static int l3g4200d_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data l3g4200d_info = {
- .type = SENSOR_TYPE_GYROSCOPE,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
- .init_platform_hw = l3g4200d_init_platform_hw,
- .x_min = 40,//x_min,y_min,z_min = (0-100) according to hardware
- .y_min = 40,
- .z_min = 20,
-};
-
-#endif
-
-#ifdef CONFIG_LS_CM3217
-static struct sensor_platform_data cm3217_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 0,
- .poll_delay_ms = 500,
-};
-
-#endif
-
-#ifdef CONFIG_FB_ROCKCHIP
-
-#define LCD_CS_PIN INVALID_GPIO
-#define LCD_CS_VALUE GPIO_HIGH
-
-#define LCD_EN_PIN RK30_PIN0_PB0
-#define LCD_EN_VALUE GPIO_LOW
-
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
-
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_CS_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_CS_PIN);
- printk(KERN_ERR "request lcd cs pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_CS_PIN, LCD_CS_VALUE);
- }
- }
-
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_EN_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_EN_PIN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_EN_PIN, LCD_EN_VALUE);
- }
- }
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, !LCD_CS_VALUE);
- }
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, !LCD_EN_VALUE);
- }
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE);
- }
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
- }
- return 0;
-}
-
-#if defined(CONFIG_LCDC0_RK3066B)
-struct rk29fb_info lcdc0_screen_info = {
- .prop = EXTEND, //primary display device
- .io_init = NULL,
- .io_disable = NULL,
- .io_enable = NULL,
- .set_screen_info = NULL,
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B)
-struct rk29fb_info lcdc1_screen_info = {
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B)
-static struct resource resource_lcdc0[] = {
- [0] = {
- .name = "lcdc0 reg",
- .start = RK30_LCDC0_PHYS,
- .end = RK30_LCDC0_PHYS + RK30_LCDC0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc0 irq",
- .start = IRQ_LCDC0,
- .end = IRQ_LCDC0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc0 = {
- .name = "rk30-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc0),
- .resource = resource_lcdc0,
- .dev = {
- .platform_data = &lcdc0_screen_info,
- },
-};
-#endif
-#if defined(CONFIG_LCDC1_RK3066B)
-static struct resource resource_lcdc1[] = {
- [0] = {
- .name = "lcdc1 reg",
- .start = RK30_LCDC1_PHYS,
- .end = RK30_LCDC1_PHYS + RK30_LCDC1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc1 irq",
- .start = IRQ_LCDC1,
- .end = IRQ_LCDC1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc1 = {
- .name = "rk30-lcdc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resource_lcdc1),
- .resource = resource_lcdc1,
- .dev = {
- .platform_data = &lcdc1_screen_info,
- },
-};
-#endif
-
-#if defined(CONFIG_MFD_RK610)
-#define RK610_RST_PIN RK30_PIN3_PB2
-static int rk610_power_on_init(void)
-{
- int ret;
- if(RK610_RST_PIN != INVALID_GPIO)
- {
- ret = gpio_request(RK610_RST_PIN, "rk610 reset");
- if (ret)
- {
- printk(KERN_ERR "rk610_control_probe request gpio fail\n");
- }
- else
- {
- gpio_direction_output(RK610_RST_PIN, GPIO_HIGH);
- msleep(100);
- gpio_direction_output(RK610_RST_PIN, GPIO_LOW);
- msleep(100);
- gpio_set_value(RK610_RST_PIN, GPIO_HIGH);
- }
- }
-
- return 0;
-
-}
-
-
-static struct rk610_ctl_platform_data rk610_ctl_pdata = {
- .rk610_power_on_init = rk610_power_on_init,
-};
-#endif
-
-#ifdef CONFIG_SND_SOC_RK610
-static int rk610_codec_io_init(void)
-{
-//if need iomux.
-//Must not gpio_request
- return 0;
-}
-
-static struct rk610_codec_platform_data rk610_codec_pdata = {
- .spk_ctl_io = RK30_PIN2_PD7,
- .io_init = rk610_codec_io_init,
- .boot_depop = 1,
-};
-#endif
-
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and sdio.noted by xbw at 2012-03-05
-**************************************************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "board-rk3168-ds1006h-sdmmc-config.c"
-#include "../plat-rk/rk-sdmmc-ops.c"
-#include "../plat-rk/rk-sdmmc-wifi.c"
-#endif //endif ---#ifdef CONFIG_SDMMC_RK29
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- iomux_set(MMC0_CMD);
- iomux_set(MMC0_CLKOUT);
- iomux_set(MMC0_D0);
- iomux_set(MMC0_D1);
- iomux_set(MMC0_D2);
- iomux_set(MMC0_D3);
-
- iomux_set_gpio_mode(iomux_mode_to_gpio(MMC0_DETN));
-
- gpio_request(RK30_PIN3_PA7, "sdmmc-power");
- gpio_direction_output(RK30_PIN3_PA7, GPIO_LOW);
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- #if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set_gpio_mode(iomux_gpio_to_mode(RK29SDK_SD_CARD_DETECT_N));
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO);
- #endif
- #else
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(MMC0_DETN);
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FMUX);
- #endif
- #endif
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) && defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- .status = rk29sdk_wifi_mmc0_status,
- .register_status_notify = rk29sdk_wifi_mmc0_status_register,
-#endif
-
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .power_en = RK29SDK_SD_CARD_PWR_EN,
- .power_en_level = RK29SDK_SD_CARD_PWR_EN_LEVEL,
-#else
- .power_en = INVALID_GPIO,
- .power_en_level = GPIO_LOW,
-#endif
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC0_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- .det_pin_info = {
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N, //INVALID_GPIO,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
- #endif
- },
-
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- iomux_set(MMC1_CMD);
- iomux_set(MMC1_CLKOUT);
- iomux_set(MMC1_D0);
- iomux_set(MMC1_D1);
- iomux_set(MMC1_D2);
- iomux_set(MMC1_D3);
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC) || defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC1_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- #if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
- .sdio_INT_gpio = RK29SDK_WIFI_SDIO_CARD_INT,
- #endif
-
- .det_pin_info = {
-#if defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- #else
- .io = INVALID_GPIO,
- #endif
-
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-
- .enable_sd_wakeup = 0,
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-/**************************************************************************************************
- * the end of setting for SDMMC devices
-**************************************************************************************************/
-
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = RK30_PIN0_PB2,
- .batt_low_pin = INVALID_GPIO,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = RK30_PIN0_PA6,
- .usb_det_pin = INVALID_GPIO,
- .dc_det_level = GPIO_LOW,
- .charge_ok_level = GPIO_HIGH,
-
- .reference_voltage = 1800, // the rK2928 is 3300;RK3066 and rk29 are 2500;rk3066B is 1800;
- .pull_up_res = 200, //divider resistance , pull-up resistor
- .pull_down_res = 120, //divider resistance , pull-down resistor
-
- .is_reboot_charging = 1,
- .save_capacity = 1 ,
- .low_voltage_protection = 3600,
-};
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-#ifdef CONFIG_RK30_PWM_REGULATOR
-static int pwm_voltage_map[] = {
- 800000,825000,850000, 875000,900000, 925000 ,950000, 975000,1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000,1375000
-};
-
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_cpu",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] =
-{
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
- .pwm_id = 1,
- .pwm_gpio = RK30_PIN3_PD4,
- .pwm_iomux_pwm = PWM1,
- .pwm_iomux_gpio = GPIO3_D4,
- .pwm_voltage = 1100000,
- .suspend_voltage = 1000000,
- .min_uV = 800000,
- .max_uV = 1375000,
- .coefficient = 575, //57.5%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-#endif
-
-#ifdef CONFIG_RFKILL_RK
-// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
-static struct rfkill_rk_platform_data rfkill_rk_platdata = {
- .type = RFKILL_TYPE_BLUETOOTH,
-
- .poweron_gpio = { // BT_REG_ON
- .io = INVALID_GPIO, //RK30_PIN3_PC7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_poweron",
- .fgpio = GPIO3_C7,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN3_PD1, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_reset",
- .fgpio = GPIO3_D1,
- },
- },
-
- .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
- .io = RK30_PIN3_PC6, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_wake",
- .fgpio = GPIO3_C6,
- },
- },
-
- .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .gpio = {
- .io = RK30_PIN0_PA5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
- .iomux = {
- .name = NULL,
- },
- },
- },
-
- .rts_gpio = { // UART_RTS, enable or disable BT's data coming
- .io = RK30_PIN1_PA3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_rts",
- .fgpio = GPIO1_A3,
- .fmux = UART0_RTSN,
- },
- },
-};
-
-static struct platform_device device_rfkill_rk = {
- .name = "rfkill_rk",
- .id = -1,
- .dev = {
- .platform_data = &rfkill_rk_platdata,
- },
-};
-#endif
-
-#if defined(CONFIG_GPS_RK)
-int rk_gps_io_init(void)
-{
- printk("%s \n", __FUNCTION__);
-
- rk30_mux_api_set(GPIO1B5_UART3RTSN_NAME, GPIO1B_GPIO1B5);//VCC_EN
- gpio_request(RK30_PIN1_PB5, NULL);
- gpio_direction_output(RK30_PIN1_PB5, GPIO_LOW);
-
- rk30_mux_api_set(GPIO1B4_UART3CTSN_GPSRFCLK_NAME, GPIO1B_GPSRFCLK);//GPS_CLK
- rk30_mux_api_set(GPIO1B2_UART3SIN_GPSMAG_NAME, GPIO1B_GPSMAG);//GPS_MAG
- rk30_mux_api_set(GPIO1B3_UART3SOUT_GPSSIG_NAME, GPIO1B_GPSSIG);//GPS_SIGN
-
- rk30_mux_api_set(GPIO1A6_UART1CTSN_SPI0CLK_NAME, GPIO1A_GPIO1A6);//SPI_CLK
- gpio_request(RK30_PIN1_PA6, NULL);
- gpio_direction_output(RK30_PIN1_PA6, GPIO_LOW);
-
- rk30_mux_api_set(GPIO1A5_UART1SOUT_SPI0TXD_NAME, GPIO1A_GPIO1A5);//SPI_MOSI
- gpio_request(RK30_PIN1_PA5, NULL);
- gpio_direction_output(RK30_PIN1_PA5, GPIO_LOW);
-
- rk30_mux_api_set(GPIO1A7_UART1RTSN_SPI0CSN0_NAME, GPIO1A_GPIO1A7);//SPI_CS
- gpio_request(RK30_PIN1_PA7, NULL);
- gpio_direction_output(RK30_PIN1_PA7, GPIO_LOW);
- return 0;
-}
-int rk_gps_power_up(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_power_down(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_reset_set(int level)
-{
- return 0;
-}
-int rk_enable_hclk_gps(void)
-{
- printk("%s \n", __FUNCTION__);
- clk_enable(clk_get(NULL, "hclk_gps"));
- return 0;
-}
-int rk_disable_hclk_gps(void)
-{
- printk("%s \n", __FUNCTION__);
- clk_disable(clk_get(NULL, "hclk_gps"));
- return 0;
-}
-struct rk_gps_data rk_gps_info = {
- .io_init = rk_gps_io_init,
- .power_up = rk_gps_power_up,
- .power_down = rk_gps_power_down,
- .reset = rk_gps_reset_set,
- .enable_hclk_gps = rk_enable_hclk_gps,
- .disable_hclk_gps = rk_disable_hclk_gps,
- .GpsSign = RK30_PIN1_PB3,
- .GpsMag = RK30_PIN1_PB2, //GPIO index
- .GpsClk = RK30_PIN1_PB4, //GPIO index
- .GpsVCCEn = RK30_PIN1_PB5, //GPIO index
- .GpsSpi_CSO = RK30_PIN1_PA4, //GPIO index
- .GpsSpiClk = RK30_PIN1_PA5, //GPIO index
- .GpsSpiMOSI = RK30_PIN1_PA7, //GPIO index
- .GpsIrq = IRQ_GPS,
- .GpsSpiEn = 0,
- .GpsAdcCh = 2,
- .u32GpsPhyAddr = RK30_GPS_PHYS,
- .u32GpsPhySize = RK30_GPS_SIZE,
-};
-
-struct platform_device rk_device_gps = {
- .name = "gps_hv5820b",
- .id = -1,
- .dev = {
- .platform_data = &rk_gps_info,
- }
- };
-#endif
-
-#if defined(CONFIG_MT5931_MT6622)
-static struct mt6622_platform_data mt6622_platdata = {
- .power_gpio = { // BT_REG_ON
- .io = RK30_PIN3_PD5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN0_PD7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .irq_gpio = {
- .io = RK30_PIN3_PD2,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- }
-};
-
-static struct platform_device device_mt6622 = {
- .name = "mt6622",
- .id = -1,
- .dev = {
- .platform_data = &mt6622_platdata,
- },
-};
-#endif
-
-static struct platform_device *devices[] __initdata = {
-
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- &rk29sdk_wifi_device,
-#endif
-
-#if defined(CONFIG_MT6620)
- &mt3326_device_gps,
-#endif
-
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
- &rk30_device_adc_battery,
-#endif
-#ifdef CONFIG_RFKILL_RK
- &device_rfkill_rk,
-#endif
-#ifdef CONFIG_GPS_RK
- &rk_device_gps,
-#endif
-#ifdef CONFIG_MT5931_MT6622
- &device_mt6622,
-#endif
-};
-
-
-static int rk_platform_add_display_devices(void)
-{
- struct platform_device *fb = NULL; //fb
- struct platform_device *lcdc0 = NULL; //lcdc0
- struct platform_device *lcdc1 = NULL; //lcdc1
- struct platform_device *bl = NULL; //backlight
-#ifdef CONFIG_FB_ROCKCHIP
- fb = &device_fb;
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B)
- lcdc0 = &device_lcdc0,
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B)
- lcdc1 = &device_lcdc1,
-#endif
-
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- bl = &rk29_device_backlight,
-#endif
- __rk_platform_add_display_devices(fb,lcdc0,lcdc1,bl);
-
- return 0;
-
-}
-
-// i2c
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1d,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_GS_LIS3DH)
- {
- .type = "gs_lis3dh",
- .addr = 0x19, //0x19(SA0-->VCC), 0x18(SA0-->GND)
- .flags = 0,
- .irq = LIS3DH_INT_PIN,
- .platform_data = &lis3dh_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8975_info,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8975_info,
- },
-#endif
-#if defined (CONFIG_GYRO_L3G4200D)
- {
- .type = "l3g4200d_gryo",
- .addr = 0x69,
- .flags = 0,
- .irq = L3G4200D_INT_PIN,
- .platform_data = &l3g4200d_info,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RT5631)
- {
- .type = "rt5631",
- .addr = 0x1a,
- .flags = 0,
- },
-#endif
-};
-#endif
-
-int __sramdata g_pmic_type = 0;
-#ifdef CONFIG_I2C1_RK30
-#ifdef CONFIG_REGULATOR_ACT8846
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-#define ACT8846_HOST_IRQ RK30_PIN0_PB3
-
-static struct pmu_info act8846_dcdc_info[] = {
- {
- .name = "act_dcdc1", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- .suspend_vol = 1200000,
- },
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 1200000,
- #else
- .suspend_vol = 900000,
- #endif
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 1200000,
- #else
- .suspend_vol = 900000,
- #endif
- },
- {
- .name = "act_dcdc4", //vccio
- .min_uv = 3000000,
- .max_uv = 3000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 3000000,
- #else
- .suspend_vol = 2800000,
- #endif
- },
-
-};
-static struct pmu_info act8846_ldo_info[] = {
- {
- .name = "act_ldo1", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "act_ldo2", //vdd12
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "act_ldo3", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo4", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo5", //vcctp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo6", //vcc_jetta
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo7", //vcc18
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo8", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- };
-
-#include "board-pmu-act8846.c"
-#endif
-
-#ifdef CONFIG_MFD_WM831X_I2C
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info wm8326_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "dcdc3", //ddr
- .min_uv = 1150000,
- .max_uv = 1150000,
- .suspend_vol = 1150000,
- },
- #ifdef CONFIG_MACH_RK3066_SDK
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3000000,
- },
- #else
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3000000,
- .max_uv = 3000000,
- .suspend_vol = 2800000,
- },
- #endif
-};
-
-static struct pmu_info wm8326_ldo_info[] = {
- {
- .name = "ldo1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo2", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo3", //
- .min_uv = 1100000,
- .max_uv = 1100000,
- .suspend_vol = 1100000,
- },
- {
- .name = "ldo4", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 1000000,
- },
- {
- .name = "ldo5", //vcc25
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo6", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo7", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- .suspend_vol = 2800000,
- },
- {
- .name = "ldo8", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo9", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo10", //flash_io
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
-};
-
-#include "board-pmu-wm8326.c"
-#endif
-
-#ifdef CONFIG_MFD_TPS65910
-#ifdef CONFIG_ARCH_RK3066B
-#define TPS65910_HOST_IRQ RK30_PIN0_PB3
-#else
-#define TPS65910_HOST_IRQ RK30_PIN6_PA4
-#endif
-
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info tps65910_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1100000,
- .max_uv = 1100000,
- },
- {
- .name = "vdd2", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vio", //vcc_io
- .min_uv = 2500000,
- .max_uv = 2500000,
- },
-
-};
-static struct pmu_info tps65910_ldo_info[] = {
- {
- .name = "vpll", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "vdig2", //vdd_jetta
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vaux1", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "vaux2", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vaux33", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vmmc", //vcc30
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
- {
- .name = "vdac", //vcc18
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- };
-
-#include "board-pmu-tps65910.c"
-#endif
-
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_REGULATOR_ACT8846)
- {
- .type = "act8846",
- .addr = 0x5a,
- .flags = 0,
- .irq = ACT8846_HOST_IRQ,
- .platform_data=&act8846_data,
- },
-#endif
-#if defined (CONFIG_RTC_HYM8563)
- {
- .type = "rtc_hym8563",
- .addr = 0x51,
- .flags = 0,
- .irq = RK30_PIN0_PB5,
- },
-#endif
-#if defined (CONFIG_MFD_WM831X_I2C)
- {
- .type = "wm8326",
- .addr = 0x34,
- .flags = 0,
- .irq = RK30_PIN0_PB3,
- .platform_data = &wm831x_platdata,
- },
-#endif
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-};
-#endif
-
-void __sramfunc board_pmu_suspend(void)
-{
- #if defined (CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- board_pmu_act8846_suspend();
- #endif
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_suspend();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_suspend();
- #endif
-}
-
-void __sramfunc board_pmu_resume(void)
-{
- #if defined (CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- board_pmu_act8846_resume();
- #endif
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_resume();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_resume();
- #endif
-}
-
- int __sramdata gpio3d6_iomux,gpio3d6_do,gpio3d6_dir,gpio3d6_en;
-
-#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
-
-void __sramfunc rk30_pwm_logic_suspend_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
-
-// int gpio0d7_iomux,gpio0d7_do,gpio0d7_dir,gpio0d7_en;
- sram_udelay(10000);
- gpio3d6_iomux = grf_readl(GRF_GPIO3D_IOMUX);
- gpio3d6_do = grf_readl(GRF_GPIO3H_DO);
- gpio3d6_dir = grf_readl(GRF_GPIO3H_DIR);
- gpio3d6_en = grf_readl(GRF_GPIO3H_EN);
-
- grf_writel((1<<28), GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DIR);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DO);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_EN);
-#endif
-}
-void __sramfunc rk30_pwm_logic_resume_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- grf_writel((1<<28)|gpio3d6_iomux, GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|gpio3d6_en, GRF_GPIO3H_EN);
- grf_writel((1<<30)|gpio3d6_dir, GRF_GPIO3H_DIR);
- grf_writel((1<<30)|gpio3d6_do, GRF_GPIO3H_DO);
- sram_udelay(10000);
-
-#endif
-
-}
-extern void pwm_suspend_voltage(void);
-extern void pwm_resume_voltage(void);
-void rk30_pwm_suspend_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_suspend_voltage();
-#endif
-}
-void rk30_pwm_resume_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_resume_voltage();
-#endif
-}
-
-
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-#if defined (CONFIG_CT36X_TS)
- {
- .type = CT36X_NAME,
- .addr = 0x01,
- .flags = 0,
- .platform_data = &ct36x_info,
- },
-#endif
-#if defined (CONFIG_LS_CM3217)
- {
- .type = "lightsensor",
- .addr = 0x10,
- .flags = 0,
- .platform_data = &cm3217_info,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C4_RK30
-static struct i2c_board_info __initdata i2c4_info[] = {
-#ifdef CONFIG_MFD_RK610
- {
- .type = "rk610_ctl",
- .addr = 0x40,
- .flags = 0,
- .platform_data = &rk610_ctl_pdata,
- },
-#ifdef CONFIG_RK610_TVOUT
- {
- .type = "rk610_tvout",
- .addr = 0x42,
- .flags = 0,
- },
-#endif
-#ifdef CONFIG_HDMI_RK610
- {
- .type = "rk610_hdmi",
- .addr = 0x46,
- .flags = 0,
- .irq = INVALID_GPIO,
- },
-#endif
-#ifdef CONFIG_SND_SOC_RK610
- {//RK610_CODEC addr from 0x60 to 0x80 (0x60~0x80)
- .type = "rk610_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- .platform_data = &rk610_codec_pdata,
- },
-#endif
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO// RK30_PIN2_PD6 //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO//RK30_PIN2_PD7 //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- //set iomux (gpio) here
- //rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME, GPIO2D_GPIO2D7);
- //rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME, GPIO2D_GPIO2D6);
-
- return 0;
-}
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C4_RK30
- i2c_register_board_info(4, i2c4_info, ARRAY_SIZE(i2c4_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(5, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-
-#define POWER_ON_PIN RK30_PIN0_PA0 //power_hold
-static void rk30_pm_power_off(void)
-{
- printk(KERN_ERR "rk30_pm_power_off start...\n");
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
-#if defined(CONFIG_MFD_WM831X)
- wm831x_set_bits(Wm831x,WM831X_GPIO_LEVEL,0x0001,0x0000); //set sys_pwr 0
- wm831x_device_shutdown(Wm831x);//wm8326 shutdown
-#endif
-#if defined(CONFIG_REGULATOR_ACT8846)
- if (pmic_is_act8846()) {
- printk("enter dcdet===========\n");
- if(gpio_get_value (RK30_PIN0_PB2) == GPIO_LOW)
- {
- printk("enter restart===========\n");
- arm_pm_restart(0, NULL);
- }
- //act8931_device_shutdown();
- }
-#endif
- while (1);
-}
-
-static void __init machine_rk30_board_init(void)
-{
- //avs_init();
- gpio_request(POWER_ON_PIN, "poweronpin");
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
- pm_power_off = rk30_pm_power_off;
-
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
-
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- rk_platform_add_display_devices();
- board_usb_detect_init(RK30_PIN0_PA7);
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- rk29sdk_wifi_bt_gpio_control_init();
-#endif
-
-#if defined(CONFIG_MT6620)
- clk_set_rate(clk_get_sys("rk_serial.1", "uart"), 48*1000000);
-#endif
-
-#if defined(CONFIG_MT5931_MT6622)
- clk_set_rate(clk_get_sys("rk_serial.0", "uart"), 24*1000000);
-#endif
-}
-
-static void __init rk30_reserve(void)
-{
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0 buf", get_fb_size());
- resource_fb[0].end = resource_fb[0].start + get_fb_size()- 1;
-#if 0
- resource_fb[1].start = board_mem_reserve_add("ipp buf", RK30_FB0_MEM_SIZE);
- resource_fb[1].end = resource_fb[1].start + RK30_FB0_MEM_SIZE - 1;
-#endif
-
-#if defined(CONFIG_FB_ROTATE) || !defined(CONFIG_THREE_FB_BUFFER)
- resource_fb[2].start = board_mem_reserve_add("fb2 buf",get_fb_size());
- resource_fb[2].end = resource_fb[2].start + get_fb_size() - 1;
-#endif
-#endif
-
-
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
-
-#ifdef CONFIG_GPS_RK
- //it must be more than 8MB
- rk_gps_info.u32MemoryPhyAddr = board_mem_reserve_add("gps", SZ_8M);
-#endif
- board_mem_reserved();
-}
-
-/**
- * dvfs_cpu_logic_table: table for arm and logic dvfs
- * @frequency : arm frequency
- * @cpu_volt : arm voltage depend on frequency
- * @logic_volt : logic voltage arm requests depend on frequency
- * comments : min arm/logic voltage
- */
-static struct cpufreq_frequency_table dvfs_arm_table[] = {
- {.frequency = 312 * 1000, .index = 850 * 1000},
- {.frequency = 504 * 1000, .index = 900 * 1000},
- {.frequency = 816 * 1000, .index = 950 * 1000},
- {.frequency = 1008 * 1000, .index = 1025 * 1000},
- {.frequency = 1200 * 1000, .index = 1100 * 1000},
- {.frequency = 1416 * 1000, .index = 1200 * 1000},
- //{.frequency = 1608 * 1000, .index = 1300 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- {.frequency = 100 * 1000, .index = 950 * 1000},
- {.frequency = 200 * 1000, .index = 975 * 1000},
- {.frequency = 266 * 1000, .index = 1000 * 1000},
- {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1100 * 1000},
- //{.frequency = 600 * 1000, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 950 * 1000},
- {.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = 1000 * 1000},
- {.frequency = 400 * 1000 + DDR_FREQ_NORMAL, .index = 1100 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-//#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
-//static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
-//static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
-
-void __init board_clock_init(void)
-{
- rk30_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
- //dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "cpu"), dvfs_arm_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
-}
-
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk30_fixup,
- .reserve = &rk30_reserve,
- .map_io = rk30_map_io,
- .init_irq = rk30_init_irq,
- .timer = &rk30_timer,
- .init_machine = machine_rk30_board_init,
-MACHINE_END
+++ /dev/null
-/*
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <mach/dvfs.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <linux/rk_fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/mfd/tps65910.h>
-#include <linux/regulator/act8846.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-#if defined(CONFIG_CT36X_TS)
-#include <linux/ct36x.h>
-#endif
-#include <linux/regulator/act8931.h>
-#include <plat/config.h>
-
-
-
-#if defined(CONFIG_MFD_RK610)
-#include <linux/mfd/rk610_core.h>
-#endif
-#if defined(CONFIG_MFD_RK616)
-#include <linux/mfd/rk616.h>
-#endif
-
-#ifdef CONFIG_TOUCHSCREEN_GT82X_IIC
-#include <linux/goodix_touch_82x.h>
-#endif
-
-#if defined(CONFIG_RK_HDMI)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-#if defined(CONFIG_GPS_RK)
-#include "../../../drivers/misc/gps/rk_gps/rk_gps.h"
-#endif
-
-#if defined(CONFIG_MT6620)
-#include <linux/gps.h>
-#endif
-
-#if 1
-#define INIT_ERR(name) do { printk("%s: %s init Failed: \n", __func__, (name)); } while(0)
-#else
-#define INIT_ERR(name)
-#endif
-
-#include "board-rk3168-86v-camera.c"
-#include "../plat-rk/rk-fac-config.c"
-#include <plat/key.h>
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "play",
- .code = KEY_POWER,
- .wakeup = 1,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- },
- {
- .desc = "menu",
- .code = EV_MENU,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- },
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .chn = -1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
-#if defined (CONFIG_TOUCHSCREEN_GSLX680_RK3168)
-int gslx680_init_platform_hw()
-{
- int ret;
- if(tp_rst!=-1){
- ret = port_output_init(tp_rst, 1, "tp_rst");
- if(ret<0)
- printk("%s: port output init faild\n", __func__);
- }
-
- port_output_on(tp_rst);
- mdelay(10);
- port_output_off(tp_rst);
- mdelay(10);
- port_output_on(tp_rst);
- msleep(300);
- return 0;
-}
-
-static struct tp_platform_data gslx680_data = {
-
- .init_platform_hw = gslx680_init_platform_hw,
-};
-struct i2c_board_info __initdata gslx680_info = {
- .type = "gslX680",
- .flags = 0,
- .platform_data = &gslx680_data,
-};
-#endif
-
-
-#if defined (CONFIG_TOUCHSCREEN_86V_GT811_IIC)
-int gt811_init_platform_hw(int irq,int reset)
-{
- int ret;
- if(tp_rst!=-1){
- ret = port_output_init(tp_rst, 1, "tp_rst");
- if(ret<0)
- printk("%s: port output init faild\n", __func__);
- }
-
- port_output_off(tp_rst);
- msleep(500);
- port_output_off(tp_rst);
- msleep(500);
- port_output_on(tp_rst);
- mdelay(100);
- return 0;
-}
-
-
-static struct tp_platform_data gt811_data = {
- .model= 811,
- .init_platform_hw= gt811_init_platform_hw,
-};
-
-struct i2c_board_info __initdata gt811_info = {
- .type = "gt811_ts",
- .flags = 0,
- .platform_data = >811_data,
-};
-#endif
-
-
-/***********************************************************
-* rk30 codec
-************************************************************/
-#if defined (CONFIG_SND_RK29_SOC_RT5631)
-static struct codec_platform_data rt5631_data = {
-};
-struct i2c_board_info __initdata rt5631_info = {
- .type = "rt5631",
- .flags = 0,
- .platform_data =&rt5631_data,
-};
-#endif
-
-#if defined (CONFIG_SND_RK29_SOC_ES8323)
-static struct codec_platform_data es8323_data = {
-};
-struct i2c_board_info __initdata es8323_info = {
- .type = "es8323",
- .flags = 0,
- .platform_data =&es8323_data,
-};
-#endif
-#ifdef CONFIG_TOUCHSCREEN_GT82X_IIC
-#define TOUCH_ENABLE_PIN INVALID_GPIO
-#define TOUCH_RESET_PIN RK30_PIN0_PB6//RK30_PIN4_PD0
-#define TOUCH_INT_PIN RK30_PIN1_PB7//RK30_PIN4_PC2
-int goodix_init_platform_hw(void)
-{
- int ret;
-
- //rk30_mux_api_set(GPIO4D0_SMCDATA8_TRACEDATA8_NAME, GPIO4D_GPIO4D0); //hjc
- //rk30_mux_api_set(GPIO4C2_SMCDATA2_TRACEDATA2_NAME, GPIO4C_GPIO4C2); //hjc
- //printk("%s:0x%x,0x%x\n",__func__,rk30_mux_api_get(GPIO4D0_SMCDATA8_TRACEDATA8_NAME),rk30_mux_api_get(GPIO4C2_SMCDATA2_TRACEDATA2_NAME));
- if (TOUCH_ENABLE_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_ENABLE_PIN, "goodix power pin");
- if (ret != 0) {
- gpio_free(TOUCH_ENABLE_PIN);
- printk("goodix power error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_ENABLE_PIN, 0);
- gpio_set_value(TOUCH_ENABLE_PIN, GPIO_LOW);
- msleep(100);
- }
-
- if (TOUCH_RESET_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_RESET_PIN, "goodix reset pin");
- if (ret != 0) {
- gpio_free(TOUCH_RESET_PIN);
- printk("goodix gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- gpio_set_value(TOUCH_RESET_PIN, GPIO_LOW);
- msleep(10);
- gpio_set_value(TOUCH_RESET_PIN, GPIO_HIGH);
- msleep(500);
- }
- return 0;
-}
-u8 ts82x_config_data[] = {
- 0x65,0x00,0x04,0x00,0x03,0x00,0x0A,0x0D,0x1E,0xE7,
- 0x32,0x03,0x08,0x10,0x48,0x42,0x42,0x20,0x00,0x01,
- 0x60,0x60,0x4B,0x6E,0x0E,0x0D,0x0C,0x0B,0x0A,0x09,
- 0x08,0x07,0x06,0x05,0x04,0x03,0x02,0x01,0x00,0x1D,
- 0x1C,0x1B,0x1A,0x19,0x18,0x17,0x16,0x15,0x14,0x13,
- 0x12,0x11,0x10,0x0F,0x50,0x00,0x00,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2B,0x00,0x00,
- 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x00
-};
-static struct goodix_i2c_rmi_platform_data ts82x_pdata = {
- .gpio_shutdown = TOUCH_ENABLE_PIN,
- .gpio_irq = TOUCH_INT_PIN,
- .gpio_reset = TOUCH_RESET_PIN,
- .irq_edge = 1, /* 0:rising edge, 1:falling edge */
-
- .ypol = 1,
- .swap_xy = 1,
- .xpol = 0,
- .xmax = 800,
- .ymax = 600,
- .config_info_len =ARRAY_SIZE(ts82x_config_data),
- .config_info = ts82x_config_data,
- .init_platform_hw= goodix_init_platform_hw,
-};
-#endif
-
-static struct spi_board_info board_spi_devices[] = {
-};
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
- iomux_set(bl_pwm_mode);
- msleep(100);
-
- if(bl_en== -1)
- return 0;
- ret = port_output_init(bl_en, 1, "bl_en");
- if(ret < 0){
- printk("%s: port output init faild\n", __func__);
- return ret;
- }
- port_output_on(bl_en);
-
- return ret;
-}
-
-
-static int rk29_backlight_io_deinit(void){
- int pwm_gpio;
-
- if(bl_en != -1)
- port_deinit(bl_en);
-
- pwm_gpio = iomux_mode_to_gpio(bl_pwm_mode);
- gpio_request(pwm_gpio, NULL);
- gpio_direction_output(pwm_gpio, GPIO_LOW);
- return 0;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret = 0, pwm_gpio;
-
- pwm_gpio = iomux_mode_to_gpio(bl_pwm_mode);
- if (gpio_request(pwm_gpio, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- gpio_direction_output(pwm_gpio, GPIO_LOW);
- port_output_off(bl_en);
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- int pwm_gpio = iomux_mode_to_gpio(bl_pwm_mode);
- gpio_free(pwm_gpio);
- iomux_set(bl_pwm_mode);
- msleep(150);
- port_output_on(bl_en);
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-#endif
-
-/*MMA7660 gsensor*/
-#if defined (CONFIG_GS_MMA7660)
-static int mma7660_init_platform_hw(void)
-{
- //rk30_mux_api_set(GPIO1B2_SPI_RXD_UART1_SIN_NAME, GPIO1B_GPIO1B2);
-
- return 0;
-}
-
-static struct sensor_platform_data mma7660_data = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma7660_init_platform_hw,
-};
-struct i2c_board_info __initdata mma7660_info = {
- .type = "gs_mma7660",
- .flags = 0,
- .platform_data =&mma7660_data,
-};
-#endif
-
-#if defined (CONFIG_GS_MXC6225)
-static int mxc6225_init_platform_hw(void)
-{
-// rk30_mux_api_set(GPIO1B1_SPI_TXD_UART1_SOUT_NAME, GPIO1B_GPIO1B1);
- return 0;
-}
-
-static struct sensor_platform_data mxc6225_data = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 0,
- .poll_delay_ms = 30,
- .init_platform_hw = mxc6225_init_platform_hw,
-};
-struct i2c_board_info __initdata mxc6225_info = {
- .type = "gs_mxc6225",
- .flags = 0,
- .platform_data =&mxc6225_data,
-};
-#endif
-
-#if defined (CONFIG_GS_DMT10)
-static int dmt10_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data dmt10_data = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 0,
- .poll_delay_ms = 30,
- .init_platform_hw = dmt10_init_platform_hw,
-};
-struct i2c_board_info __initdata dmt10_info = {
- .type = "gs_dmard10",
- .flags = 0,
- .platform_data =&dmt10_data,
-};
-#endif
-
-
-#if defined (CONFIG_GS_LIS3DH)
-static int lis3dh_init_platform_hw(void)
-{
- return 0;
-}
-static struct sensor_platform_data lis3dh_data = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lis3dh_init_platform_hw,
-};
-struct i2c_board_info __initdata lis3dh_info = {
- .type = "gs_lis3dh",
- .flags = 0,
- .platform_data =&lis3dh_data,
-};
-#endif
-
-#if defined (CONFIG_GS_LSM303D)
-static int lms303d_init_platform_hw(void)
-{
- return 0;
-}
-static struct sensor_platform_data lms303d_data = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lms303d_init_platform_hw,
-};
-struct i2c_board_info __initdata lms303d_info = {
- .type = "gs_lsm303d",
- .flags = 0,
- .platform_data =&lms303d_data,
-};
-#endif
-
-#if defined (CONFIG_GS_MMA8452)
-static int mma8452_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data mma8452_data = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma8452_init_platform_hw,
-};
-struct i2c_board_info __initdata mma8452_info = {
- .type = "gs_mma8452",
- .flags = 0,
- .platform_data =&mma8452_data,
-};
-#endif
-
-#if defined (CONFIG_COMPASS_AK8975)
-static struct sensor_platform_data akm8975_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-#if defined (CONFIG_COMPASS_AK8963)
-static struct sensor_platform_data akm8963_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {0, 1, 0},
- {1, 0, 0},
- {0, 0, -1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {0, -1, 0},
- {-1, 0, 0},
- {0, 0, -1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-
-#if defined(CONFIG_GYRO_L3G4200D)
-
-#include <linux/l3g4200d.h>
-#define L3G4200D_INT_PIN RK30_PIN0_PB4
-
-static int l3g4200d_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data l3g4200d_info = {
- .type = SENSOR_TYPE_GYROSCOPE,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
- .init_platform_hw = l3g4200d_init_platform_hw,
- .x_min = 40,//x_min,y_min,z_min = (0-100) according to hardware
- .y_min = 40,
- .z_min = 20,
-};
-
-#endif
-
-#ifdef CONFIG_LS_CM3217
-static struct sensor_platform_data cm3217_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 0,
- .poll_delay_ms = 500,
-};
-
-#endif
-
-
-#ifdef CONFIG_FB_ROCKCHIP
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
- printk("rk_fb_io_init %x,%x,%x\n",lcd_cs,lcd_en,lcd_std);
- if(lcd_cs != -1){
- ret = port_output_init(lcd_cs, 1, "lcd_cs");
- if(ret < 0)
- printk("%s: port output init faild\n", __func__);
- port_output_on(lcd_cs);
- }
-
- if(lcd_en != -1){
- ret = port_output_init(lcd_en, 1, "lcd_en");
- if(ret < 0)
- printk("%s: port output init faild\n", __func__);
- port_output_on(lcd_en);
- }
-
- if(lcd_std != -1){
- ret = port_output_init(lcd_std, 1, "lcd_std");
- if(ret < 0)
- printk("%s: port output init faild\n", __func__);
- port_output_on(lcd_std);
- }
-
- return ret;
-}
-
-static int rk_fb_io_disable(void){
- if(lcd_cs != -1)
- port_output_off(lcd_cs);
- if(lcd_en != -1)
- port_output_on(lcd_en);
- return 0;
-}
-
-static int rk_fb_io_enable(void){
- if(lcd_en != -1)
- port_output_on(lcd_en);
- if(lcd_cs != -1)
- port_output_on(lcd_cs);
- return 0;
-}
-
-#if defined(CONFIG_LCDC0_RK3066B)
-struct rk29fb_info lcdc0_screen_info = {
-#if defined(CONFIG_RK_HDMI) && defined(CONFIG_HDMI_SOURCE_LCDC0)&& defined(CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL)
- .prop = EXTEND, //primary display device
- .io_init = NULL,
- .io_disable = NULL,
- .io_enable = NULL,
- .set_screen_info = hdmi_init_lcdc,
-#else
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-#endif
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B)
-struct rk29fb_info lcdc1_screen_info = {
-#if defined(CONFIG_RK_HDMI) && defined(CONFIG_HDMI_SOURCE_LCDC1) && defined(CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL)
- .prop = EXTEND, //primary display device
- .io_init = NULL,
- .io_disable = NULL,
- .io_enable = NULL,
- .set_screen_info = hdmi_init_lcdc,
-#else
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-#endif
-
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B)
-static struct resource resource_lcdc0[] = {
- [0] = {
- .name = "lcdc0 reg",
- .start = RK30_LCDC0_PHYS,
- .end = RK30_LCDC0_PHYS + RK30_LCDC0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc0 irq",
- .start = IRQ_LCDC0,
- .end = IRQ_LCDC0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc0 = {
- .name = "rk30-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc0),
- .resource = resource_lcdc0,
- .dev = {
- .platform_data = &lcdc0_screen_info,
- },
-};
-#endif
-#if defined(CONFIG_LCDC1_RK3066B)
-static struct resource resource_lcdc1[] = {
- [0] = {
- .name = "lcdc1 reg",
- .start = RK30_LCDC1_PHYS,
- .end = RK30_LCDC1_PHYS + RK30_LCDC1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc1 irq",
- .start = IRQ_LCDC1,
- .end = IRQ_LCDC1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc1 = {
- .name = "rk30-lcdc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resource_lcdc1),
- .resource = resource_lcdc1,
- .dev = {
- .platform_data = &lcdc1_screen_info,
- },
-};
-#endif
-
-#if defined(CONFIG_MFD_RK610)
-#define RK610_RST_PIN RK30_PIN3_PB2
-static int rk610_power_on_init(void)
-{
- int ret;
- if(RK610_RST_PIN != INVALID_GPIO)
- {
- ret = gpio_request(RK610_RST_PIN, "rk610 reset");
- if (ret)
- {
- printk(KERN_ERR "rk610_control_probe request gpio fail\n");
- }
- else
- {
- gpio_direction_output(RK610_RST_PIN, GPIO_HIGH);
- msleep(100);
- gpio_direction_output(RK610_RST_PIN, GPIO_LOW);
- msleep(100);
- gpio_set_value(RK610_RST_PIN, GPIO_HIGH);
- }
- }
-
- return 0;
-
-}
-
-
-static struct rk610_ctl_platform_data rk610_ctl_pdata = {
- .rk610_power_on_init = rk610_power_on_init,
-};
-#endif
-
-#ifdef CONFIG_SND_SOC_RK610
-static int rk610_codec_io_init(void)
-{
-//if need iomux.
-//Must not gpio_request
- return 0;
-}
-
-static struct rk610_codec_platform_data rk610_codec_pdata = {
- .spk_ctl_io = RK30_PIN2_PD7,
- .io_init = rk610_codec_io_init,
- .boot_depop = 1,
-};
-#endif
-
-#if defined(CONFIG_MFD_RK616)
-//#define RK616_RST_PIN RK30_PIN3_PB2
-//#define RK616_PWREN_PIN RK30_PIN0_PA3
-#define RK616_SCL_RATE (100*1000) //i2c scl rate
-static int rk616_power_on_init(void)
-{
- int ret;
-
- if(codec_power!=-1)
- {
- ret = port_output_init(codec_power, 1, "codec_power");
- if(ret < 0)
- printk("%s: port output init faild\n", __func__);
- port_output_on(codec_power);
- }
-
- if(codec_rst!=-1)
- {
- ret = port_output_init(codec_rst, 1, "codec_rst");
- if(ret < 0)
- printk("%s: port output init faild\n", __func__);
- port_output_on(codec_rst);
- msleep(100);
- port_output_off(codec_rst);
- msleep(100);
- port_output_on(codec_rst);
- }
- return 0;
-
-}
-
-
-static struct rk616_platform_data rk616_pdata = {
- .power_init = rk616_power_on_init,
- .scl_rate = RK616_SCL_RATE,
- .lcd0_func = INPUT, //port lcd0 as input
- .lcd1_func = OUTPUT, //port lcd1 as input
- .lvds_ch_nr = 1, //the number of used lvds channel
- //.hdmi_irq = RK30_PIN2_PD6,
- //.spk_ctl_gpio = RK30_PIN2_PD7,
-};
-
-struct i2c_board_info __initdata rk616_info = {
- .type = "rk616",
- .flags = 0,
- .platform_data = &rk616_pdata,
-};
-
-#endif
-
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and sdio.noted by xbw at 2012-03-05
-**************************************************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "board-rk3168-86v-sdmmc-config.c"
-#include "../plat-rk/rk-sdmmc-ops.c"
-#include "../plat-rk/rk-sdmmc-wifi.c"
-#endif //endif ---#ifdef CONFIG_SDMMC_RK29
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- iomux_set(MMC0_CMD);
- iomux_set(MMC0_CLKOUT);
- iomux_set(MMC0_D0);
- iomux_set(MMC0_D1);
- iomux_set(MMC0_D2);
- iomux_set(MMC0_D3);
-
- iomux_set_gpio_mode(iomux_mode_to_gpio(MMC0_DETN));
-
- gpio_request(RK30_PIN3_PA7, "sdmmc-power");
- gpio_direction_output(RK30_PIN3_PA7, GPIO_LOW);
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- #if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set_gpio_mode(iomux_gpio_to_mode(RK29SDK_SD_CARD_DETECT_N));
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO);
- #endif
- #else
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(MMC0_DETN);
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FMUX);
- #endif
- #endif
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) && defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- .status = rk29sdk_wifi_mmc0_status,
- .register_status_notify = rk29sdk_wifi_mmc0_status_register,
-#endif
-
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .power_en = RK29SDK_SD_CARD_PWR_EN,
- .power_en_level = RK29SDK_SD_CARD_PWR_EN_LEVEL,
-#else
- .power_en = INVALID_GPIO,
- .power_en_level = GPIO_LOW,
-#endif
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC0_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- .det_pin_info = {
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N, //INVALID_GPIO,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
- #endif
- },
-
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- iomux_set(MMC1_CMD);
- iomux_set(MMC1_CLKOUT);
- iomux_set(MMC1_D0);
- iomux_set(MMC1_D1);
- iomux_set(MMC1_D2);
- iomux_set(MMC1_D3);
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC) || defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC1_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- #if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
- .sdio_INT_gpio = RK29SDK_WIFI_SDIO_CARD_INT,
- #ifdef USE_SDIO_INT_LEVEL
- .sdio_INT_level = RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE,
- #endif
- #endif
-
- .det_pin_info = {
-#if defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- #else
- .io = INVALID_GPIO,
- #endif
-
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-
- .enable_sd_wakeup = 0,
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-/**************************************************************************************************
- * the end of setting for SDMMC devices
-**************************************************************************************************/
-
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
-/*
- .dc_det_pin = RK30_PIN0_PB2,
- .batt_low_pin = INVALID_GPIO,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = RK30_PIN0_PA6,
- .usb_det_pin = INVALID_GPIO,
- .dc_det_level = GPIO_LOW,
- .charge_ok_level = GPIO_HIGH,
-
- .reference_voltage = 1800, // the rK2928 is 3300;RK3066 and rk29 are 2500;rk3066B is 1800;
- .pull_up_res = 200, //divider resistance , pull-up resistor
- .pull_down_res = 120, //divider resistance , pull-down resistor
-
- .is_reboot_charging = 1,
- .save_capacity = 1 ,
- .low_voltage_protection = 3600,
- */
-};
-
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-#ifdef CONFIG_RK30_PWM_REGULATOR
-static int pwm_voltage_map[] = {
- 800000,825000,850000, 875000,900000, 925000 ,950000, 975000,1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000,1375000
-};
-
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_cpu",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] =
-{
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
- .pwm_id = 1,
- .pwm_gpio = RK30_PIN3_PD4,
- .pwm_iomux_pwm = PWM1,
- .pwm_iomux_gpio = GPIO3_D4,
- .pwm_voltage = 1100000,
- .suspend_voltage = 1000000,
- .min_uV = 800000,
- .max_uV = 1375000,
- .coefficient = 575, //55.0%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-#endif
-
-#ifdef CONFIG_RFKILL_RK
-// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
-static struct rfkill_rk_platform_data rfkill_rk_platdata = {
- .type = RFKILL_TYPE_BLUETOOTH,
-
- .poweron_gpio = { // BT_REG_ON
- .io = INVALID_GPIO, //RK30_PIN3_PC7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_poweron",
- .fgpio = GPIO3_C7,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN3_PD1, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_reset",
- .fgpio = GPIO3_D1,
- },
- },
-
- .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
- .io = RK30_PIN3_PC6, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_wake",
- .fgpio = GPIO3_C6,
- },
- },
-
- .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .gpio = {
- .io = RK30_PIN0_PA5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
- .iomux = {
- .name = NULL,
- },
- },
- },
-
- .rts_gpio = { // UART_RTS, enable or disable BT's data coming
- .io = RK30_PIN1_PA3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_rts",
- .fgpio = GPIO1_A3,
- .fmux = UART0_RTSN,
- },
- },
-};
-
-static struct platform_device device_rfkill_rk = {
- .name = "rfkill_rk",
- .id = -1,
- .dev = {
- .platform_data = &rfkill_rk_platdata,
- },
-};
-#endif
-
-#if defined(CONFIG_GPS_RK)
-int rk_gps_io_init(void)
-{
- printk("%s \n", __FUNCTION__);
-
- rk30_mux_api_set(GPIO1B5_UART3RTSN_NAME, GPIO1B_GPIO1B5);//VCC_EN
- gpio_request(RK30_PIN1_PB5, NULL);
- gpio_direction_output(RK30_PIN1_PB5, GPIO_LOW);
-
- rk30_mux_api_set(GPIO1B4_UART3CTSN_GPSRFCLK_NAME, GPIO1B_GPSRFCLK);//GPS_CLK
- rk30_mux_api_set(GPIO1B2_UART3SIN_GPSMAG_NAME, GPIO1B_GPSMAG);//GPS_MAG
- rk30_mux_api_set(GPIO1B3_UART3SOUT_GPSSIG_NAME, GPIO1B_GPSSIG);//GPS_SIGN
-
- rk30_mux_api_set(GPIO1A6_UART1CTSN_SPI0CLK_NAME, GPIO1A_GPIO1A6);//SPI_CLK
- gpio_request(RK30_PIN1_PA6, NULL);
- gpio_direction_output(RK30_PIN1_PA6, GPIO_LOW);
-
- rk30_mux_api_set(GPIO1A5_UART1SOUT_SPI0TXD_NAME, GPIO1A_GPIO1A5);//SPI_MOSI
- gpio_request(RK30_PIN1_PA5, NULL);
- gpio_direction_output(RK30_PIN1_PA5, GPIO_LOW);
-
- rk30_mux_api_set(GPIO1A7_UART1RTSN_SPI0CSN0_NAME, GPIO1A_GPIO1A7);//SPI_CS
- gpio_request(RK30_PIN1_PA7, NULL);
- gpio_direction_output(RK30_PIN1_PA7, GPIO_LOW);
- return 0;
-}
-int rk_gps_power_up(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_power_down(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_reset_set(int level)
-{
- return 0;
-}
-int rk_enable_hclk_gps(void)
-{
- printk("%s \n", __FUNCTION__);
- clk_enable(clk_get(NULL, "hclk_gps"));
- return 0;
-}
-int rk_disable_hclk_gps(void)
-{
- printk("%s \n", __FUNCTION__);
- clk_disable(clk_get(NULL, "hclk_gps"));
- return 0;
-}
-struct rk_gps_data rk_gps_info = {
- .io_init = rk_gps_io_init,
- .power_up = rk_gps_power_up,
- .power_down = rk_gps_power_down,
- .reset = rk_gps_reset_set,
- .enable_hclk_gps = rk_enable_hclk_gps,
- .disable_hclk_gps = rk_disable_hclk_gps,
- .GpsSign = RK30_PIN1_PB3,
- .GpsMag = RK30_PIN1_PB2, //GPIO index
- .GpsClk = RK30_PIN1_PB4, //GPIO index
- .GpsVCCEn = RK30_PIN1_PB5, //GPIO index
- .GpsSpi_CSO = RK30_PIN1_PA4, //GPIO index
- .GpsSpiClk = RK30_PIN1_PA5, //GPIO index
- .GpsSpiMOSI = RK30_PIN1_PA7, //GPIO index
- .GpsIrq = IRQ_GPS,
- .GpsSpiEn = 0,
- .GpsAdcCh = 2,
- .u32GpsPhyAddr = RK30_GPS_PHYS,
- .u32GpsPhySize = RK30_GPS_SIZE,
-};
-
-struct platform_device rk_device_gps = {
- .name = "gps_hv5820b",
- .id = -1,
- .dev = {
- .platform_data = &rk_gps_info,
- }
- };
-#endif
-
-#if defined(CONFIG_MT5931_MT6622)
-static struct mt6622_platform_data mt6622_platdata = {
- .power_gpio = { // BT_REG_ON
- .io = RK30_PIN3_PC7, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN3_PD1,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .irq_gpio = {
- .io = RK30_PIN0_PA5,
- .enable = GPIO_LOW,
- .iomux = {
- .name = NULL,
- },
- },
-
- .rts_gpio = { // UART_RTS
- .io = RK30_PIN1_PA3,
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_rts",
- .fgpio = GPIO1_A3,
- .fmux = UART0_RTSN,
- },
- },
-};
-
-static struct platform_device device_mt6622 = {
- .name = "mt6622",
- .id = -1,
- .dev = {
- .platform_data = &mt6622_platdata,
- },
-};
-#endif
-#if defined CONFIG_TCC_BT_DEV
-static struct tcc_bt_platform_data tcc_bt_platdata = {
-
- .power_gpio = { // ldoon
- .io = RK30_PIN3_PC0,//difined depend on your harware
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .wake_host_gpio = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .io = RK30_PIN0_PC5, // set io to INVALID_GPIO for disable it,it's depend on your hardware
- .enable = IRQF_TRIGGER_RISING,// set IRQF_TRIGGER_FALLING for falling, set IRQF_TRIGGER_RISING for rising
- .iomux = {
- .name = NULL,
- },
- },
-};
-
-static struct platform_device device_tcc_bt = {
- .name = "tcc_bt_dev",
- .id = -1,
- .dev = {
- .platform_data = &tcc_bt_platdata,
- },
-};
-#endif
-
-static struct platform_device *devices[] __initdata = {
-
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- &rk29sdk_wifi_device,
-#endif
-
-#if defined(CONFIG_MT6620)
- &mt3326_device_gps,
-#endif
-
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
- &rk30_device_adc_battery,
-#endif
-#ifdef CONFIG_RFKILL_RK
- &device_rfkill_rk,
-#endif
-#ifdef CONFIG_GPS_RK
- &rk_device_gps,
-#endif
-#ifdef CONFIG_MT5931_MT6622
- &device_mt6622,
-#endif
-#ifdef CONFIG_TCC_BT_DEV
- &device_tcc_bt,
-#endif
-};
-
-
-static int rk_platform_add_display_devices(void)
-{
- struct platform_device *fb = NULL; //fb
- struct platform_device *lcdc0 = NULL; //lcdc0
- struct platform_device *lcdc1 = NULL; //lcdc1
- struct platform_device *bl = NULL; //backlight
-#ifdef CONFIG_FB_ROCKCHIP
- fb = &device_fb;
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B)
- lcdc0 = &device_lcdc0,
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B)
- lcdc1 = &device_lcdc1,
-#endif
-
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- bl = &rk29_device_backlight,
-#endif
- __rk_platform_add_display_devices(fb,lcdc0,lcdc1,bl);
-
- return 0;
-
-}
-
-// i2c
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8975_info,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8975_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8963)
- {
- .type = "ak8963",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8963_info,
- },
-#endif
-#if defined (CONFIG_GYRO_L3G4200D)
- {
- .type = "l3g4200d_gryo",
- .addr = 0x69,
- .flags = 0,
- .irq = L3G4200D_INT_PIN,
- .platform_data = &l3g4200d_info,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RT5616)
- {
- .type = "rt5616",
- .addr = 0x1b,
- .flags = 0,
- },
-#endif
-};
-#endif
-
-int __sramdata g_pmic_type = 0;
-#ifdef CONFIG_I2C1_RK30
-#ifdef CONFIG_REGULATOR_ACT8846
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-#define ACT8846_HOST_IRQ RK30_PIN0_PB3
-
-static struct pmu_info act8846_dcdc_info[] = {
- {
- .name = "act_dcdc1", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 1200000,
- #else
- .suspend_vol = 900000,
- #endif
- },
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 1200000,
- #else
- .suspend_vol = 900000,
- #endif
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 1200000,
- #else
- .suspend_vol = 900000,
- #endif
- },
- {
- .name = "act_dcdc4", //vccio
- .min_uv = 3000000,
- .max_uv = 3000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 3000000,
- #else
- .suspend_vol = 2800000,
- #endif
- },
-
-};
-static struct pmu_info act8846_ldo_info[] = {
- {
- .name = "act_ldo1", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "act_ldo2", //vdd12
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "act_ldo3", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo4", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo5", //vcctp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo6", //vcc_jetta
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo7", //vcc18
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo8", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- };
-
-#include "board-pmu-act8846.c"
-#endif
-
-#ifdef CONFIG_MFD_WM831X_I2C
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info wm8326_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "dcdc3", //ddr
- .min_uv = 1150000,
- .max_uv = 1150000,
- .suspend_vol = 1150000,
- },
- #ifdef CONFIG_MACH_RK3066_SDK
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3000000,
- },
- #else
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3000000,
- .max_uv = 3000000,
- .suspend_vol = 2800000,
- },
- #endif
-};
-
-static struct pmu_info wm8326_ldo_info[] = {
- {
- .name = "ldo1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo2", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo3", //
- .min_uv = 1100000,
- .max_uv = 1100000,
- .suspend_vol = 1100000,
- },
- {
- .name = "ldo4", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 1000000,
- },
- {
- .name = "ldo5", //vcc25
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo6", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo7", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- .suspend_vol = 2800000,
- },
- {
- .name = "ldo8", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo9", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo10", //flash_io
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
-};
-
-#include "board-pmu-wm8326.c"
-#endif
-
-#ifdef CONFIG_MFD_TPS65910
-#ifdef CONFIG_ARCH_RK3066B
-#define TPS65910_HOST_IRQ RK30_PIN0_PB3
-#else
-#define TPS65910_HOST_IRQ RK30_PIN6_PA4
-#endif
-
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info tps65910_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vio", //vcc_io
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
-
-};
-static struct pmu_info tps65910_ldo_info[] = {
-/* {
- .name = "vpll", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- },*/
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
-#ifdef CONFIG_MFD_RK616
- {
- .name = "vdig2", //vdd11//1.0->1.2 for rk616 vdd_core lch
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
-#else
- {
- .name = "vdig2", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
-#endif
- {
- .name = "vaux1", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "vaux2", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vaux33", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vmmc", //vcca30
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
- {
- .name = "vdac", //vcc18
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- };
-
-#include "board-pmu-tps65910.c"
-#endif
-#ifdef CONFIG_REGULATOR_ACT8931
-#define ACT8931_HOST_IRQ RK30_PIN0_PB5//depend on your hardware
-
-
-#define ACT8931_CHGSEL_PIN RK30_PIN0_PD0 //depend on your hardware
-
-
-static struct pmu_info act8931_dcdc_info[] = {
- {
- .name = "vdd_core", //vdd_logic
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "act_dcdc2", //ddr
- .min_uv = 1500000,
- .max_uv = 1500000,
- },
- {
- .name = "vdd_cpu", //vdd_arm
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
-
-};
-static struct pmu_info act8931_ldo_info[] = {
- {
- .name = "act_ldo1", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "act_ldo2", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo3", //vcca30
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
- {
- .name = "act_ldo4", //vcc_wl
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
-};
-#include "board-rk30-sdk-act8931.c"
-#endif
-
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_REGULATOR_ACT8846)
- {
- .type = "act8846",
- .addr = 0x5a,
- .flags = 0,
- .irq = ACT8846_HOST_IRQ,
- .platform_data=&act8846_data,
- },
-#endif
-#if defined (CONFIG_RTC_HYM8563)
- {
- .type = "rtc_hym8563",
- .addr = 0x51,
- .flags = 0,
- .irq = RK30_PIN0_PB5,
- },
-#endif
-#if defined (CONFIG_MFD_WM831X_I2C)
- {
- .type = "wm8326",
- .addr = 0x34,
- .flags = 0,
- .irq = RK30_PIN0_PB3,
- .platform_data = &wm831x_platdata,
- },
-#endif
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-#if defined (CONFIG_REGULATOR_ACT8931)
- {
- .type = "act8931",
- .addr = 0x5b,
- .flags = 0,
- .irq = ACT8931_HOST_IRQ,
- .platform_data=&act8931_data,
- },
-#endif
-};
-#endif
-
-void __sramfunc board_pmu_suspend(void)
-{
- #if defined (CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- board_pmu_act8846_suspend();
- #endif
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_suspend();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_suspend();
- #endif
-}
-
-void __sramfunc board_pmu_resume(void)
-{
- #if defined (CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- board_pmu_act8846_resume();
- #endif
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_resume();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_resume();
- #endif
-}
-
- int __sramdata gpio3d6_iomux,gpio3d6_do,gpio3d6_dir,gpio3d6_en;
-
-#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
-
-void __sramfunc rk30_pwm_logic_suspend_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
-
-// int gpio0d7_iomux,gpio0d7_do,gpio0d7_dir,gpio0d7_en;
- sram_udelay(10000);
- gpio3d6_iomux = grf_readl(GRF_GPIO3D_IOMUX);
- gpio3d6_do = grf_readl(GRF_GPIO3H_DO);
- gpio3d6_dir = grf_readl(GRF_GPIO3H_DIR);
- gpio3d6_en = grf_readl(GRF_GPIO3H_EN);
-
- grf_writel((1<<28), GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DIR);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DO);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_EN);
-#endif
-}
-void __sramfunc rk30_pwm_logic_resume_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- grf_writel((1<<28)|gpio3d6_iomux, GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|gpio3d6_en, GRF_GPIO3H_EN);
- grf_writel((1<<30)|gpio3d6_dir, GRF_GPIO3H_DIR);
- grf_writel((1<<30)|gpio3d6_do, GRF_GPIO3H_DO);
- sram_udelay(10000);
-
-#endif
-
-}
-extern void pwm_suspend_voltage(void);
-extern void pwm_resume_voltage(void);
-void rk30_pwm_suspend_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_suspend_voltage();
-#endif
-}
-void rk30_pwm_resume_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_resume_voltage();
-#endif
-}
-
-
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-#if defined (CONFIG_CT36X_TS)
- {
- .type = CT36X_NAME,
- .addr = 0x01,
- .flags = 0,
- .platform_data = &ct36x_info,
- },
-#endif
-#if defined (CONFIG_LS_CM3217)
- {
- .type = "lightsensor",
- .addr = 0x10,
- .flags = 0,
- .platform_data = &cm3217_info,
- },
-#endif
-#if defined(CONFIG_TOUCHSCREEN_GT82X_IIC)
- {
- .type = "Goodix-TS-82X",
- .addr = 0x5D,
- .flags = 0,
- .irq = RK30_PIN1_PB7,
- .platform_data = &ts82x_pdata,
- },
-#endif
-#if defined(CONFIG_HDMI_CAT66121)
- {
- .type = "cat66121_hdmi",
- .addr = 0x4c,
- .flags = 0,
- .irq = RK30_PIN2_PD6,
- .platform_data = &rk_hdmi_pdata,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C4_RK30
-static struct i2c_board_info __initdata i2c4_info[] = {
-#ifdef CONFIG_MFD_RK610
- {
- .type = "rk610_ctl",
- .addr = 0x40,
- .flags = 0,
- .platform_data = &rk610_ctl_pdata,
- },
-#ifdef CONFIG_RK610_TVOUT
- {
- .type = "rk610_tvout",
- .addr = 0x42,
- .flags = 0,
- },
-#endif
-#ifdef CONFIG_HDMI_RK610
- {
- .type = "rk610_hdmi",
- .addr = 0x46,
- .flags = 0,
- .irq = INVALID_GPIO,
- },
-#endif
-#ifdef CONFIG_SND_SOC_RK610
- {//RK610_CODEC addr from 0x60 to 0x80 (0x60~0x80)
- .type = "rk610_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- .platform_data = &rk610_codec_pdata,
- },
-#endif
-#endif
-
-};
-
-#if defined (CONFIG_SND_SOC_RT5616)
- {
- .type = "rt5616",
- .addr = 0x1b,
- .flags = 0,
- },
-#endif
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO// RK30_PIN2_PD6 //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO//RK30_PIN2_PD7 //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- //set iomux (gpio) here
- //rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME, GPIO2D_GPIO2D7);
- //rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME, GPIO2D_GPIO2D6);
-
- return 0;
-}
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C4_RK30
- i2c_register_board_info(4, i2c4_info, ARRAY_SIZE(i2c4_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(5, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-#define USB_INSERT_FAKE_SHUTDOWN
-#if defined(USB_INSERT_FAKE_SHUTDOWN)
-extern int rk30_pm_enter(suspend_state_t state);
-int __sramdata charge_power_off = 0;
-
-static void rk30_charge_deal(void)
-{
- struct regulator *ldo = NULL;
- int ret;
- charge_power_off = 1;
-
- //ldo = regulator_get(NULL, "ldo9"); // shutdown tp power
- //regulator_disable(ldo);
- //regulator_put(ldo);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_LOW);
- rk29_backlight_pwm_suspend();//shutdown backlight
- rk_fb_io_disable(); //shutdown lcd
-
- local_irq_disable();
- local_fiq_disable();
-
- rk30_pm_enter(PM_SUSPEND_MEM);
-
- if(charge_power_off == 1)
- {
- arm_pm_restart(0, NULL);
- }
-}
-#else
-static void rk30_charge_deal(void){
-}
-#endif
-
-
-#define POWER_ON_PIN RK30_PIN0_PA0 //power_hold
-static void rk30_pm_power_off(void)
-{
- printk(KERN_ERR "rk30_pm_power_off start...\n");
- gpio_direction_output(get_port_config(pwr_on).gpio, GPIO_LOW);
-
- if (pmic_is_tps65910()) {
- printk("enter dcdet pmic_is_tps65910===========\n");
- if(gpio_get_value (get_port_config(dc_det).gpio) == GPIO_LOW)
- {
- printk("enter restart===========\n");
- arm_pm_restart(0, "charge");
- }else if(gpio_get_value (RK30_PIN0_PA7) == GPIO_LOW){//usb in
- printk("debug: detect dc_det LOW, charging!\n");
- rk30_charge_deal();
- }
- tps65910_device_shutdown();
- }else if(pmic_is_act8846()){
- printk("enter dcdet pmic_is_act8846===========\n");
- if(gpio_get_value (get_port_config(dc_det).gpio) == GPIO_LOW)
- {
- printk("enter restart===========\n");
- arm_pm_restart(0, "charge");
- }
- act8846_device_shutdown();
- }else if(pmic_is_wm8326()){
- printk("enter dcdet pmic_is_wm8326===========\n");
- if(gpio_get_value (get_port_config(dc_det).gpio) == GPIO_LOW)
- {
- printk("enter restart===========\n");
- arm_pm_restart(0, "charge");
- }
- wm831x_set_bits(Wm831x,WM831X_GPIO_LEVEL,0x0001,0x0000); //set sys_pwr 0
- wm831x_device_shutdown(Wm831x);//wm8326 shutdown
- }else if(pmic_is_act8931()){
- printk("enter dcdet pmic_is_act8931===========\n");
- if(gpio_get_value (get_port_config(dc_det).gpio) == GPIO_LOW)
- {
- printk("enter restart===========\n");
- arm_pm_restart(0, "charge");
- }
- act8931_device_shutdown();
- }
- while (1);
-}
-
-static int __init tp_board_init(void)
-{
- struct port_config irq_port;
- struct port_config rst_port;
- int ret = check_tp_param();
-
- if(ret < 0)
- return ret;
-
- irq_port = get_port_config(tp_irq);
- rst_port = get_port_config(tp_rst);
-#if defined (CONFIG_TOUCHSCREEN_GSLX680_RK3168)
- if(tp_type == TP_TYPE_GSLX680){
- gslx680_data.irq_pin = irq_port.gpio;
- gslx680_info.addr = tp_addr;
- gslx680_data.reset_pin= rst_port.gpio;
- gslx680_data.x_max=tp_xmax;
- gslx680_data.y_max=tp_ymax;
- gslx680_data.firmVer=tp_firmVer;
- i2c_register_board_info(tp_i2c, &gslx680_info, 1);
- }
-#endif
-
-#if defined (CONFIG_TOUCHSCREEN_86V_GT811_IIC)
- if(tp_type == TP_TYPE_GT811_86V){
- gt811_data.irq_pin = irq_port.gpio;
- gt811_info.addr = tp_addr;
- gt811_data.reset_pin= rst_port.gpio;
- gt811_data.x_max=tp_xmax;
- gt811_data.y_max=tp_ymax;
- i2c_register_board_info(tp_i2c, >811_info, 1);
- }
-#endif
- return 0;
-}
-
-
-static int __init codec_board_init(void)
-{
- struct port_config spk_port;
- struct port_config hp_port;
- int ret = check_codec_param();
-
- if(ret < 0)
- return ret;
-
- spk_port = get_port_config(spk_ctl);
- hp_port = get_port_config(hp_det);
-
-#if defined (CONFIG_SND_RK29_SOC_RT5631)
- if(codec_type == CODEC_TYPE_RT5631){
- rt5631_data.spk_pin = spk_port.gpio;
- rt5631_info.addr = codec_addr;
- rt5631_data.hp_pin= hp_port.gpio;
- i2c_register_board_info(codec_i2c, &rt5631_info, 1);
- }
-#endif
-
-#if defined (CONFIG_SND_RK29_SOC_ES8323)
- if(codec_type == CODEC_TYPE_ES8323){
- es8323_data.spk_pin = spk_port.gpio;
- es8323_info.addr = codec_addr;
- es8323_data.hp_pin= hp_port.gpio;
- i2c_register_board_info(codec_i2c, &es8323_info, 1);
- }
-#endif
-
-#if defined (CONFIG_MFD_RK616)
-if(codec_type == CODEC_TYPE_RK616){
- rk616_pdata.spk_ctl_gpio = spk_port.gpio;
- rk616_info.addr = codec_addr;
- rk616_pdata.hdmi_irq= get_port_config(codec_hdmi_irq).gpio;
- i2c_register_board_info(codec_i2c, &rk616_info, 1);
- }
-#endif
- return 0;
-}
-
-static int __init chg_board_init(void)
-{
- int i;
- int ret = check_chg_param();
- if(ret < 0)
- return ret;
- //rk30_adc_battery_platdata.adc_channel = chg_adc;
- if(dc_det != -1){
- rk30_adc_battery_platdata.dc_det_pin = get_port_config(dc_det).gpio;
- printk("rk30_adc_battery_platdata.dc_det_pin %d %d",rk30_adc_battery_platdata.dc_det_pin,RK30_PIN0_PB2);
- rk30_adc_battery_platdata.dc_det_level = !get_port_config(dc_det).io.active_low;
- }
- else{
- rk30_adc_battery_platdata.dc_det_pin=INVALID_GPIO;
- }
- if(bat_low != -1){
- rk30_adc_battery_platdata.batt_low_pin = get_port_config(bat_low).gpio;
- rk30_adc_battery_platdata.batt_low_level = !get_port_config(bat_low).io.active_low;
- }
- else{
- rk30_adc_battery_platdata.batt_low_pin=INVALID_GPIO;
- }
- if(chg_ok != -1){
- rk30_adc_battery_platdata.charge_ok_pin = get_port_config(chg_ok).gpio;
- rk30_adc_battery_platdata.charge_ok_level = !get_port_config(chg_ok).io.active_low;
- }
- else{
- rk30_adc_battery_platdata.charge_ok_pin=INVALID_GPIO;
- }
- if(chg_set != -1){
- rk30_adc_battery_platdata.charge_set_pin = get_port_config(chg_set).gpio;
- rk30_adc_battery_platdata.charge_set_level = !get_port_config(chg_set).io.active_low;
- }
- else{
- rk30_adc_battery_platdata.charge_set_pin=INVALID_GPIO;
- }
- if(usb_det!= -1){
- rk30_adc_battery_platdata.usb_det_pin = get_port_config(chg_set).gpio;
- rk30_adc_battery_platdata.usb_det_level = !get_port_config(chg_set).io.active_low;
- }
- else{
- rk30_adc_battery_platdata.usb_det_pin=INVALID_GPIO;
- }
-
- if(ref_vol!= -1){
- rk30_adc_battery_platdata.reference_voltage=ref_vol;
- }
-
- if(up_res!= -1){
- rk30_adc_battery_platdata.pull_up_res=up_res;
- }
- if(down_res!= -1){
- rk30_adc_battery_platdata.pull_down_res=down_res;
- }
- if(root_chg!= -1){
- rk30_adc_battery_platdata.is_reboot_charging=root_chg;
- }
- if(save_cap!= -1){
- rk30_adc_battery_platdata.save_capacity=save_cap;
- }
- if(low_vol!= -1){
- rk30_adc_battery_platdata.low_voltage_protection=low_vol;
- }
-
- for(i=0;i<11;i++)
- {
- rk30_adc_battery_platdata.chargeArray[i]=bat_charge[i];
- rk30_adc_battery_platdata.dischargeArray[i]=bat_discharge[i];
- }
-
- return 0;
-}
-
-static int __init gs_board_init(void)
-{
- int i;
- struct port_config port;
- int ret = check_gs_param();
- if(ret < 0)
- return ret;
- port = get_port_config(gs_irq);
-//mma7660
-#if defined (CONFIG_GS_MMA7660)
- if(gs_type == GS_TYPE_MMA7660){
-
- mma7660_info.irq = port.gpio;
- mma7660_info.addr = gs_addr;
- for(i = 0; i < 9; i++)
- mma7660_data.orientation[i] = gs_orig[i];
- i2c_register_board_info(gs_i2c, &mma7660_info, 1);
- }
-#endif
-#if defined (CONFIG_GS_MMA8452)
- if(gs_type == GS_TYPE_MMA8452){
- mma8452_info.irq = port.gpio;
- mma8452_info.addr = gs_addr;
- for(i = 0; i < 9; i++)
- mma8452_data.orientation[i] = gs_orig[i];
- i2c_register_board_info(gs_i2c, &mma8452_info, 1);
- }
-#endif
-
-#if defined (CONFIG_GS_LIS3DH)
- if(gs_type == GS_TYPE_LIS3DH){
- lis3dh_info.irq = port.gpio;
- lis3dh_info.addr = gs_addr;
- for(i = 0; i < 9; i++)
- lis3dh_data.orientation[i] = gs_orig[i];
- i2c_register_board_info(gs_i2c, &lis3dh_info, 1);
- }
-#endif
-
-#if defined (CONFIG_GS_MXC6225)
- if(gs_type == GS_TYPE_MXC6225){
- mxc6225_info.irq = port.gpio;
- mxc6225_info.addr = gs_addr;
- for(i = 0; i < 9; i++)
- mxc6225_data.orientation[i] = gs_orig[i];
- i2c_register_board_info(gs_i2c, &mxc6225_info, 1);
- }
-#endif
-
-#if defined (CONFIG_GS_DMT10)
- if(gs_type == GS_TYPE_DMARAD10){
- dmt10_info.irq = port.gpio;
- dmt10_info.addr = gs_addr;
- for(i = 0; i < 9; i++)
- dmt10_data.orientation[i] = gs_orig[i];
- i2c_register_board_info(gs_i2c, &dmt10_info, 1);
- }
-#endif
-
-#if defined (CONFIG_GS_MMA8452)
- if(gs_type == GS_TYPE_MMA8452){
- mma8452_info.irq = port.gpio;
- mma8452_info.addr = gs_addr;
- for(i = 0; i < 9; i++)
- mma8452_data.orientation[i] = gs_orig[i];
- i2c_register_board_info(gs_i2c, &mma8452_info, 1);
- }
-#endif
-
-#if defined (CONFIG_GS_LSM303D)
- if(gs_type == GS_TYPE_LSM303D){
- lms303d_info.irq = port.gpio;
- lms303d_info.addr = gs_addr;
- for(i = 0; i < 9; i++)
- lms303d_data.orientation[i] = gs_orig[i];
- i2c_register_board_info(gs_i2c, &lms303d_info, 1);
- }
-#endif
-
-
- return 0;
-}
-
-static int __init bl_board_init(void){
- int ret = check_bl_param();
- if(ret < 0)
- return ret;
-
- switch(bl_pwmid)
- {
- case 0:
- bl_pwm_mode = PWM0;
- break;
- case 1:
- bl_pwm_mode = PWM1;
- break;
- case 2:
- bl_pwm_mode = PWM2;
- break;
- case 3:
- bl_pwm_mode = PWM3;
- break;
- }
-
- rk29_bl_info.pwm_id = bl_pwmid;
- rk29_bl_info.brightness_mode=bl_mode;
- rk29_bl_info.pre_div=bl_div;
- rk29_bl_info.bl_ref = bl_ref;
- rk29_bl_info.min_brightness=bl_min;
- rk29_bl_info.max_brightness=bl_max;
-
-
- return 0;
-}
-
-static int __init lcd_board_init(void)
-{
- return check_lcd_param();
-}
-
-static int __init key_board_init(void){
- int i;
- struct port_config port;
- for(i = 0; i < key_val_size; i++){
- if(key_val[i] & (1<<31)){
- key_button[i].adc_value = key_val[i] & 0xffff;
- key_button[i].gpio = INVALID_GPIO;
- }else{
- port = get_port_config(key_val[i]);
- key_button[i].gpio = port.gpio;
- key_button[i].active_low = port.io.active_low;
- }
- }
- rk29_keys_pdata.nbuttons = key_val_size;
- rk29_keys_pdata.chn = key_adc;
- return 0;
-}
-
-static int __init wifi_board_init(void)
-{
- return check_wifi_param();
-}
-
-
-static int __init rk_config_init(void)
-{
- int ret = 0;
- ret = lcd_board_init();
- if(ret < 0)
- INIT_ERR("lcd");
-
- ret = bl_board_init();
- if(ret < 0)
- INIT_ERR("backlight");
-
- ret = tp_board_init();
- if(ret < 0)
- INIT_ERR("tp");
-
- ret = gs_board_init();
- if(ret < 0)
- INIT_ERR("gsensor");
-
- ret = codec_board_init();
- if(ret < 0)
- INIT_ERR("codec");
-
- ret = key_board_init();
- if(ret < 0)
- INIT_ERR("key");
-
- ret = chg_board_init();
- if(ret < 0)
- INIT_ERR("charge");
-
- ret = wifi_board_init();
- if(ret < 0)
- INIT_ERR("wifi");
-
- return 0;
-}
-
-static void __init rk_board_init(void)
-{
- avs_init();
- rk_power_on();
- rk_config_init();
-
- //pm_power_off = rk30_pm_power_off;
-
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- rk_platform_add_display_devices();
- board_usb_detect_init(RK30_PIN0_PA7);
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- rk29sdk_wifi_bt_gpio_control_init();
-#endif
-
-#if defined(CONFIG_MT6620)
- clk_set_rate(clk_get_sys("rk_serial.1", "uart"), 48*1000000);
-#endif
-
-#if defined(CONFIG_MT5931_MT6622)
- clk_set_rate(clk_get_sys("rk_serial.0", "uart"), 24*1000000);
-#endif
-
-}
-
-static void __init rk30_reserve(void)
-{
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0 buf", get_fb_size());
- resource_fb[0].end = resource_fb[0].start + get_fb_size()- 1;
- #if 0
- resource_fb[1].start = board_mem_reserve_add("ipp buf", RK30_FB0_MEM_SIZE);
- resource_fb[1].end = resource_fb[1].start + RK30_FB0_MEM_SIZE - 1;
- #endif
-
-
- #if defined(CONFIG_FB_ROTATE) || !defined(CONFIG_THREE_FB_BUFFER)
- resource_fb[2].start = board_mem_reserve_add("fb2 buf",get_fb_size());
- resource_fb[2].end = resource_fb[2].start + get_fb_size() - 1;
- #endif
-#endif
-
-
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
-
-#ifdef CONFIG_GPS_RK
- //it must be more than 8MB
- rk_gps_info.u32MemoryPhyAddr = board_mem_reserve_add("gps", SZ_8M);
-#endif
- board_mem_reserved();
-
-}
-
-/**
- * dvfs_cpu_logic_table: table for arm and logic dvfs
- * @frequency : arm frequency
- * @cpu_volt : arm voltage depend on frequency
- * @logic_volt : logic voltage arm requests depend on frequency
- * comments : min arm/logic voltage
- */
-#ifdef CONFIG_DVFS_WITH_UOC
-//chenxing uoc
-static struct cpufreq_frequency_table dvfs_arm_table[] = {
- {.frequency = 312 * 1000, .index = 950 * 1000},
- {.frequency = 504 * 1000, .index = 1000 * 1000},
- {.frequency = 816 * 1000, .index = 1050 * 1000},
- {.frequency = 1008 * 1000, .index = 1125 * 1000},
- {.frequency = 1200 * 1000, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- {.frequency = 100 * 1000, .index = 1000 * 1000},
- {.frequency = 200 * 1000, .index = 1000 * 1000},
- {.frequency = 266 * 1000, .index = 1050 * 1000},
- //{.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1125 * 1000},
- {.frequency = 600 * 1000, .index = 1250 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 1000 * 1000},
- {.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = 1050 * 1000},
- {.frequency = 400 * 1000 + DDR_FREQ_NORMAL, .index = 1100 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-#else
-//chenliang
-static struct cpufreq_frequency_table dvfs_arm_table[] = {
- {.frequency = 312 * 1000, .index = 1025 * 1000},
- {.frequency = 504 * 1000, .index = 1025 * 1000},
- {.frequency = 816 * 1000, .index = 1050 * 1000},
- {.frequency = 1008 * 1000, .index = 1125 * 1000},
- {.frequency = 1200 * 1000, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- {.frequency = 100 * 1000, .index = 1000 * 1000},
- {.frequency = 200 * 1000, .index = 1000 * 1000},
- {.frequency = 266 * 1000, .index = 1050 * 1000},
- {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1125 * 1000},
- {.frequency = 600 * 1000, .index = 1250 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 1000 * 1000},
- {.frequency = 240 * 1000 + DDR_FREQ_VIDEO, .index = 1050 * 1000},
- {.frequency = 300 * 1000 + DDR_FREQ_NORMAL, .index = 1075 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-#endif
-//#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
-//static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
-//static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
-int get_max_freq(struct cpufreq_frequency_table *table)
-{
- int i,temp=0;
-
- for(i=0;table[i].frequency!= CPUFREQ_TABLE_END;i++)
- {
- if(temp<table[i].frequency)
- temp=table[i].frequency;
- }
- printk("get_max_freq=%d\n",temp);
- return temp;
-}
-
-void __init board_clock_init(void)
-{
- u32 flags=RK30_CLOCKS_DEFAULT_FLAGS;
-#if !defined(CONFIG_ARCH_RK3188)
- if(get_max_freq(dvfs_gpu_table)<=(400*1000))
- {
- flags=RK30_CLOCKS_DEFAULT_FLAGS|CLK_GPU_GPLL;
- }
- else
- flags=RK30_CLOCKS_DEFAULT_FLAGS|CLK_GPU_CPLL;
-#endif
- rk30_clock_data_init(periph_pll_default, codec_pll_default, flags);
- //dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "cpu"), dvfs_arm_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
-}
-
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk30_fixup,
- .reserve = &rk30_reserve,
- .map_io = rk30_map_io,
- .init_irq = rk30_init_irq,
- .timer = &rk30_timer,
- .init_machine = rk_board_init,
-MACHINE_END
+++ /dev/null
-#ifdef CONFIG_VIDEO_RK29
-#include <plat/rk_camera.h>
-/* Notes:
-
-Simple camera device registration:
-
- new_camera_device(sensor_name,\ // sensor name, it is equal to CONFIG_SENSOR_X
- face,\ // sensor face information, it can be back or front
- pwdn_io,\ // power down gpio configuration, it is equal to CONFIG_SENSOR_POWERDN_PIN_XX
- flash_attach,\ // sensor is attach flash or not
- mir,\ // sensor image mirror and flip control information
- i2c_chl,\ // i2c channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_IIC_ADAPTER_ID_X
- cif_chl) \ // cif channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_CIF_INDEX_X
-
-Comprehensive camera device registration:
-
- new_camera_device_ex(sensor_name,\
- face,\
- ori,\ // sensor orientation, it is equal to CONFIG_SENSOR_ORIENTATION_X
- pwr_io,\ // sensor power gpio configuration, it is equal to CONFIG_SENSOR_POWER_PIN_XX
- pwr_active,\ // sensor power active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- rst_io,\ // sensor reset gpio configuration, it is equal to CONFIG_SENSOR_RESET_PIN_XX
- rst_active,\ // sensor reset active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- pwdn_io,\
- pwdn_active,\ // sensor power down active level, is equal to CONFIG_SENSOR_POWERDNACTIVE_LEVEL_X
- flash_attach,\
- res,\ // sensor resolution, this is real resolution or resoltuion after interpolate
- mir,\
- i2c_chl,\
- i2c_spd,\ // i2c speed , 100000 = 100KHz
- i2c_addr,\ // the i2c slave device address for sensor
- cif_chl,\
- mclk)\ // sensor input clock rate, 24 or 48
-
-*/
-static struct rkcamera_platform_data new_camera[] = {
- new_camera_device(RK29_CAM_SENSOR_OV5640,
- back,
- RK30_PIN3_PB5,
- 0,
- 0,
- 4,
- 0),
- new_camera_device(RK29_CAM_SENSOR_OV2659,
- front,
- RK30_PIN3_PB4,
- 0,
- 0,
- 3,
- 0),
- new_camera_device_end
-};
-/*---------------- Camera Sensor Macro Define Begin ------------------------*/
-/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
-#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_OV5642 /* back camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_0 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 4
-#define CONFIG_SENSOR_ORIENTATION_0 90
-#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 RK30_PIN3_PB5
-#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000
-
-#define CONFIG_SENSOR_01 RK29_CAM_SENSOR_OV5642 /* back camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_01 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 4
-#define CONFIG_SENSOR_ORIENTATION_01 90
-#define CONFIG_SENSOR_POWER_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_01 RK30_PIN1_PD6
-#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_01 30000
-
-#define CONFIG_SENSOR_02 RK29_CAM_SENSOR_OV5640 /* back camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_02 0x00
-#define CONFIG_SENSOR_CIF_INDEX_02 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 4
-#define CONFIG_SENSOR_ORIENTATION_02 90
-#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000
-
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_OV2659 /* front camera sensor 0 */
-#define CONFIG_SENSOR_IIC_ADDR_1 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 3
-#define CONFIG_SENSOR_ORIENTATION_1 270
-#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_1 RK30_PIN3_PB4
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000
-
-#define CONFIG_SENSOR_11 RK29_CAM_SENSOR_OV2659 /* front camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_11 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 3
-#define CONFIG_SENSOR_ORIENTATION_11 270
-#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_11 INVALID_GPIO//RK30_PIN1_PB7
-#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_11 30000
-
-#define CONFIG_SENSOR_12 RK29_CAM_SENSOR_OV2659//RK29_CAM_SENSOR_OV2655 /* front camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_12 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 3
-#define CONFIG_SENSOR_ORIENTATION_12 270
-#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_12 INVALID_GPIO//RK30_PIN1_PB7
-#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_12 30000
-
-
-#endif //#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk30_camera.c"
-/*---------------- Camera Sensor Macro Define End ---------*/
-
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#define CONFIG_SENSOR_POWER_IOCTL_USR 1 //define this refer to your board layout
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
-
-static void rk_cif_power(struct rk29camera_gpio_res *res,int on)
-{
- struct regulator *ldo_18,*ldo_28;
- int camera_power = res->gpio_power;
- int camera_ioflag = res->gpio_flag;
- int camera_io_init = res->gpio_init;
-
- ldo_28 = regulator_get(NULL, "ldo7"); // vcc28_cif
- ldo_18 = regulator_get(NULL, "ldo1"); // vcc18_cif
- if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){
- printk("get cif ldo failed!\n");
- return;
- }
- if(on == 0){
- while(regulator_is_enabled(ldo_28)>0)
- regulator_disable(ldo_28);
- regulator_put(ldo_28);
- while(regulator_is_enabled(ldo_18)>0)
- regulator_disable(ldo_18);
- regulator_put(ldo_18);
- mdelay(10);
- if (camera_power != INVALID_GPIO) {
- if (camera_io_init & RK29_CAM_POWERACTIVE_MASK) {
- gpio_set_value(camera_power, (((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
- // dprintk("%s..%s..PowerPin=%d ..PinLevel = %x \n",__FUNCTION__,res->dev_name, camera_power, (((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
- }
- }
- }
- else{
- regulator_set_voltage(ldo_28, 2800000, 2800000);
- regulator_enable(ldo_28);
- // printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
- regulator_put(ldo_28);
-
- regulator_set_voltage(ldo_18, 1800000, 1800000);
- // regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(ldo_18);
- // printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
- regulator_put(ldo_18);
- if (camera_power != INVALID_GPIO) {
- if (camera_io_init & RK29_CAM_POWERACTIVE_MASK) {
- gpio_set_value(camera_power, ((camera_ioflag&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
- //dprintk("%s..%s..PowerPin=%d ..PinLevel = %x \n",__FUNCTION__,res->dev_name, camera_power, ((camera_ioflag&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
- mdelay(10);
- }
- }
-
- }
-}
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- //#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
- rk_cif_power(res,on);
- return 0;
-}
-#endif
-
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-
-#if CONFIG_SENSOR_IIC_ADDR_0
-static struct reginfo_t rk_init_data_sensor_reg_0[] =
-{
- {0x0000, 0x00,0,0}
- };
-static struct reginfo_t rk_init_data_sensor_winseqreg_0[] ={
- {0x0000, 0x00,0,0}
- };
-#endif
-
-#if CONFIG_SENSOR_IIC_ADDR_1
-static struct reginfo_t rk_init_data_sensor_reg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_01
-static struct reginfo_t rk_init_data_sensor_reg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_02
-static struct reginfo_t rk_init_data_sensor_reg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_11
-static struct reginfo_t rk_init_data_sensor_reg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_12
-static struct reginfo_t rk_init_data_sensor_reg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] =
-{
- #if CONFIG_SENSOR_IIC_ADDR_0
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_0,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_1
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_1,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_01
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_01,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_02
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_02,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_11
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_11,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_12
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_12,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
-
- };
-#include "../../../drivers/media/video/rk30_camera.c"
-
-#endif /* CONFIG_VIDEO_RK29 */
+++ /dev/null
-/*****************************************************************************************
- * arch/arm/mach-rkxx/baord-xxx-sdmmc-config.c
- *
- * Copyright (C) 2013 ROCKCHIP, Inc.
- *
- * Description:
- * define the gpio for SD-MMC-SDIO-Wifi functions according to your own projects.
- *
- * Author: Michael Xie
- * 15 Jan,2013
- * E-mail: xbw@rock-chips.com
- *
- ******************************************************************************************/
-
-/*
-** If you select the macro of CONFIG_SDMMC0_RK29_WRITE_PROTECT, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define SDMMC0_WRITE_PROTECT_PIN RK30_PIN3_PB2 //According to your own project to set the value of write-protect-pin.
-//#define SDMMC0_WRITE_PROTECT_ENABLE_VALUE GPIO_HIGH
-
-/*
-** If you select the macro of CONFIG_SDMMC1_RK29_WRITE_PROTECT, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define SDMMC1_WRITE_PROTECT_PIN RK30_PIN3_PB3 //According to your own project to set the value of write-protect-pin.
-//#define SDMMC1_WRITE_PROTECT_ENABLE_VALUE GPIO_HIGH
-
-/*
-** If you select the macro of CONFIG_RK29_SDIO_IRQ_FROM_GPIO, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define RK29SDK_WIFI_SDIO_CARD_INT RK30_PIN3_PD2
-
-
-/*
-* define sdcard PowerEn-pin
-*/
-#define RK29SDK_SD_CARD_PWR_EN RK30_PIN3_PA1
-#define RK29SDK_SD_CARD_PWR_EN_LEVEL GPIO_LOW
-int rk31sdk_get_sdmmc0_pin_io_voltage(void)
-{
- int voltage;
-#define RK31SDK_SET_SDMMC0_PIN_VOLTAGE
-
- /**************************************************************************************
- ** Please tell me how much voltage of your SDMMC0-pin in your project.
- **
- ** ÀýÈç: ÓеÄÏîÄ¿£¬ËüµÄSDMMC0ËùÔÚµÄRKÖ÷¿ØµÄIO×飬ÏëÓÃ1.8V, ¶ø¿¨±¾ÉíÓÃ3.3V,
- ** ¶øÖмäͨ¹ý¸öµçƽת»».ÄÇô£¬Äú´Ëʱ£¬Ó¦¸ÃÉèÖÃÏÂÃæµÄvoltageֵΪ 1.8V(¼´1800mv)
- ***************************************************************************************/
- voltage = 3300; //default the voltage 3300mv.
-
- return voltage;
-}
-
-/*
-* define the card-detect-pin.
-*/
-#define RK29SDK_SD_CARD_DETECT_N RK30_PIN3_PB0 //According to your own project to set the value of card-detect-pin.
-#define RK29SDK_SD_CARD_INSERT_LEVEL GPIO_LOW // set the voltage of insert-card. Please pay attention to the default setting.
-
-//wake up host gpio
-#define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
-#define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
-
-/*
-* Define wifi module's power and reset gpio, and gpio sensitive level.
-* Please set the value according to your own project.
-*
-* Well, you just own engineering module to set the value in the corresponding module branch.
-* Otherwise, you do not define this macro, eliminate it.
-*
-*/
-#if defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU)
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_LOW//GPIO_HIGH
-
-#elif defined(CONFIG_BCM4330) || defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319) || defined(CONFIG_RK903) || defined(CONFIG_RK901)
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN2_PA7
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
-
-#elif defined(CONFIG_MT5931_MT6622) || defined(CONFIG_MT5931)
-
- #ifdef CONFIG_MACH_RK3168_LR097
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- //#define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- //#define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
-
- #else
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN0_PA5
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #endif
-
-#elif defined(CONFIG_ESP8089)
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
-#elif defined(CONFIG_MT6620)
- #define COMBO_MODULE_MT6620_CDT 1 // to control antsel2,antsel3 and gps_lan foot when using AcSip or Cdtech chip.
- //- 1--use Cdtech chip; 0--unuse CDT chip
-
- //power, PMU_EN
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PC7
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- //reset, DAIRST,SYSRST_B
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- //VDDIO
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL RK30_PIN0_PD2 //You do not get control of the foot, and you do not need to define the macro
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_ENABLE_VALUE GPIO_HIGH
- //WIFI_INT_B
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
- //BGF_INT_B
- #define RK30SDK_WIFI_GPIO_BGF_INT_B RK30_PIN6_PA7
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_ENABLE_VALUE GPIO_HIGH
- //GPS_SYNC
- #define RK30SDK_WIFI_GPIO_GPS_SYNC RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_ENABLE_VALUE GPIO_HIGH
-
- #if COMBO_MODULE_MT6620_CDT
- //ANTSEL2
- #define RK30SDK_WIFI_GPIO_ANTSEL2 RK30_PIN4_PD4
- #define RK30SDK_WIFI_GPIO_ANTSEL2_ENABLE_VALUE GPIO_LOW //use 6620 in CDT chip, LOW--work; High--no work.
- //ANTSEL3
- #define RK30SDK_WIFI_GPIO_ANTSEL3 RK30_PIN4_PD3
- #define RK30SDK_WIFI_GPIO_ANTSEL3_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- //GPS_LAN
- #define RK30SDK_WIFI_GPIO_GPS_LAN RK30_PIN4_PD6
- #define RK30SDK_WIFI_GPIO_GPS_LAN_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- #endif // #if COMBO_MODULE_MT6620_CDT--#endif
-#endif
-
-#ifndef RK30SDK_WIFI_GPIO_WIFI_INT_B
-#define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
-#define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
-#endif
-
-int rk31sdk_get_sdio_wifi_voltage(void)
-{
- int voltage;
-
- /******************************************************************************
- ** Please tell me how much wifi-module uses voltage in your project.
- ******************************************************************************/
-#if defined(CONFIG_BCM4330) || defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319) || defined(CONFIG_RK903) || defined(CONFIG_RK901)
- voltage = 1800 ; //power 1800mV
-
-#elif defined(CONFIG_MT5931_MT6622)||defined(CONFIG_MT5931)
- voltage = 1800 ; //power 1800V
-#elif defined(CONFIG_ESP8089)
- voltage = 3000 ; //power 3000V
-#elif defined(CONFIG_MT6620)
- voltage = 2800 ; //power 2800V
-#elif defined(CONFIG_RDA5990)||defined(CONFIG_RTL8723AS)
- voltage = 3300 ; //power 3300V
-#else
- //default, sdio use 3.0V
- voltage = 3000 ; //power 3000V
-#endif
-
- return voltage;
-}
-
-
-
+++ /dev/null
-/*
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <mach/dvfs.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <linux/rk_fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/mfd/tps65910.h>
-#include <linux/regulator/act8846.h>
-#include <linux/mfd/rk808.h>
-#include <linux/mfd/ricoh619.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-#ifdef CONFIG_MFD_RT5025
-#include <linux/mfd/rt5025.h>
-#endif
-#include <plat/efuse.h>
-
-#ifdef CONFIG_CW2015_BATTERY
-#include <linux/power/cw2015_battery.h>
-#endif
-#if defined(CONFIG_MFD_RK610)
-#include <linux/mfd/rk610_core.h>
-#endif
-
-#if defined(CONFIG_MFD_RK616)
-#include <linux/mfd/rk616.h>
-#endif
-
-
-#if defined(CONFIG_RK_HDMI)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-#if defined(CONFIG_GPS_RK)
-#include "../../../drivers/misc/gps/rk_gps/rk_gps.h"
-#endif
-#if defined(CONFIG_MU509)
-#include <linux/mu509.h>
-#endif
-#if defined(CONFIG_MW100)
-#include <linux/mw100.h>
-#endif
-#if defined(CONFIG_MT6229)
-#include <linux/mt6229.h>
-#endif
-#if defined(CONFIG_ANDROID_TIMED_GPIO)
-#include "../../../drivers/staging/android/timed_gpio.h"
-#endif
-
-#if defined(CONFIG_MT6620)
-#include <linux/gps.h>
-#endif
-#include "board-rk3168-tb-camera.c"
-
-#if defined(CONFIG_TOUCHSCREEN_GT8XX)
-#define TOUCH_RESET_PIN RK30_PIN0_PB6
-#define TOUCH_PWR_PIN RK30_PIN0_PC5 // need to fly line by hardware engineer
-
-/* Android Parameter */
-static int ap_mdm = 0;
-module_param(ap_mdm, int, 0644);
-static int ap_has_alsa = 0;
-module_param(ap_has_alsa, int, 0644);
-static int ap_data_only = 2;
-module_param(ap_data_only, int, 0644);
-static int ap_has_earphone = 0;
-module_param(ap_has_earphone, int, 0644);
-
-
-static int goodix_init_platform_hw(void)
-{
- int ret;
-
- if (TOUCH_PWR_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_PWR_PIN, "goodix power pin");
- if (ret != 0) {
- gpio_free(TOUCH_PWR_PIN);
- printk("goodix power error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_PWR_PIN, 0);
- gpio_set_value(TOUCH_PWR_PIN, GPIO_LOW);
- msleep(100);
- }
-
- if (TOUCH_RESET_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_RESET_PIN, "goodix reset pin");
- if (ret != 0) {
- gpio_free(TOUCH_RESET_PIN);
- printk("goodix gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, 1);
- msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_LOW);
- //msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_HIGH);
- //msleep(500);
- }
- return 0;
-}
-
-struct goodix_platform_data goodix_info = {
- .model = 8105,
- .irq_pin = RK30_PIN1_PB7,
- .rest_pin = TOUCH_RESET_PIN,
- .init_platform_hw = goodix_init_platform_hw,
-};
-#endif
-
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-#define PWM_ID 3
-#define PWM_MODE PWM3
-#define PWM_EFFECT_VALUE 1
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-#define BL_EN_PIN RK30_PIN0_PA2
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
-
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
- ret = gpio_request(BL_EN_PIN, "bl_en");
- if (ret == 0) {
- gpio_direction_output(BL_EN_PIN, BL_EN_VALUE);
- }
-#endif
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0, pwm_gpio;
-#ifdef LCD_DISP_ON_PIN
- gpio_free(BL_EN_PIN);
-#endif
- pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
- gpio_request(pwm_gpio, "bl_pwm");
- gpio_direction_output(pwm_gpio, GPIO_LOW);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret, pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
-
- ret = gpio_request(pwm_gpio, "bl_pwm");
- if (ret) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return ret;
- }
- gpio_direction_output(pwm_gpio, GPIO_LOW);
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, !BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- int pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
-
- gpio_free(pwm_gpio);
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .min_brightness=20,
- .max_brightness=255,
- .brightness_mode =BRIGHTNESS_MODE_CONIC,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-#endif
-
-#ifdef CONFIG_RK29_SUPPORT_MODEM
-
-#define RK30_MODEM_POWER RK30_PIN0_PC6
-#define RK30_MODEM_POWER_IOMUX iomux_set(GPIO0_C6)
-
-static int rk30_modem_io_init(void)
-{
- printk("%s\n", __FUNCTION__);
- RK30_MODEM_POWER_IOMUX;
-
- return 0;
-}
-
-static struct rk29_io_t rk30_modem_io = {
- .io_addr = RK30_MODEM_POWER,
- .enable = GPIO_HIGH,
- .disable = GPIO_LOW,
- .io_init = rk30_modem_io_init,
-};
-
-static struct platform_device rk30_device_modem = {
- .name = "rk30_modem",
- .id = -1,
- .dev = {
- .platform_data = &rk30_modem_io,
- }
-};
-#endif
-#if defined(CONFIG_MU509)
-static int mu509_io_init(void)
-{
-
- iomux_set(GPIO2_D5);
- iomux_set(GPIO0_C6);
- iomux_set(GPIO2_D4);
- iomux_set(GPIO0_C4);
- iomux_set(GPIO0_C5);
- return 0;
-}
-
-static int mu509_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mu509_data rk29_mu509_info = {
- .io_init = mu509_io_init,
- .io_deinit = mu509_io_deinit,
- .modem_power_en = RK30_PIN2_PD5,
- .bp_power = RK30_PIN0_PC6,
- .bp_reset = RK30_PIN2_PD4,
- .ap_wakeup_bp = RK30_PIN0_PC4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
-};
-struct platform_device rk29_device_mu509 = {
- .name = "mu509",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mu509_info,
- }
- };
-#endif
-#if defined(CONFIG_MW100)
-static int mw100_io_init(void)
-{
- iomux_set(GPIO2_D5);
- iomux_set(GPIO0_C6);
- iomux_set(GPIO2_D4);
- iomux_set(GPIO0_C4);
- iomux_set(GPIO0_C5);
- return 0;
-}
-
-static int mw100_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mw100_data rk29_mw100_info = {
- .io_init = mw100_io_init,
- .io_deinit = mw100_io_deinit,
- .modem_power_en = RK30_PIN2_PD5,
- .bp_power = RK30_PIN0_PC6,
- .bp_reset = RK30_PIN2_PD4,
- .ap_wakeup_bp = RK30_PIN0_PC4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
-};
-struct platform_device rk29_device_mw100 = {
- .name = "mw100",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mw100_info,
- }
- };
-#endif
-#if defined(CONFIG_MT6229)
-static int mt6229_io_init(void)
-{
- iomux_set(GPIO2_D5);
- iomux_set(GPIO0_C6);
- iomux_set(GPIO2_D4);
- iomux_set(GPIO0_C4);
- iomux_set(GPIO0_C5);
- return 0;
-}
-
-static int mt6229_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mt6229_data rk29_mt6229_info = {
- .io_init = mt6229_io_init,
- .io_deinit = mt6229_io_deinit,
- .modem_power_en = RK30_PIN2_PD5,
- .bp_power = RK30_PIN0_PC6,
- .bp_reset = RK30_PIN2_PD4,
- .ap_wakeup_bp = RK30_PIN0_PC4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
-};
-struct platform_device rk29_device_mt6229 = {
- .name = "mt6229",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mt6229_info,
- }
- };
-#endif
-
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN RK30_PIN0_PB7
-
-static int mma8452_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data mma8452_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma8452_init_platform_hw,
- .orientation = {-1, 0, 0, 0, -1, 0, 0, 0, 1},
-};
-#endif
-#if defined (CONFIG_GS_LIS3DH)
-#define LIS3DH_INT_PIN RK30_PIN0_PB7
-
-static int lis3dh_init_platform_hw(void)
-{
-
- return 0;
-}
-
-static struct sensor_platform_data lis3dh_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lis3dh_init_platform_hw,
- .orientation = {-1, 0, 0, 0, -1, 0, 0, 0, 1},
-};
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
-static struct sensor_platform_data akm8975_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-#if defined(CONFIG_GYRO_L3G4200D)
-
-#include <linux/l3g4200d.h>
-#define L3G4200D_INT_PIN RK30_PIN0_PB4
-
-static int l3g4200d_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data l3g4200d_info = {
- .type = SENSOR_TYPE_GYROSCOPE,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
- .init_platform_hw = l3g4200d_init_platform_hw,
- .x_min = 40,//x_min,y_min,z_min = (0-100) according to hardware
- .y_min = 40,
- .z_min = 20,
-};
-
-#endif
-
-#ifdef CONFIG_LS_CM3217
-static struct sensor_platform_data cm3217_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 0,
- .poll_delay_ms = 500,
-};
-
-#endif
-
-#ifdef CONFIG_FB_ROCKCHIP
-
-#define LCD_CS_PIN INVALID_GPIO
-#define LCD_CS_VALUE GPIO_HIGH
-
-#define LCD_EN_PIN RK30_PIN0_PB0
-#define MIPI_LCD_RST_PIN RK30_PIN0_PC3 //mipi lcd's reset pin, if no reset pin, set's INVALID_GPIO
-#define LCD_EN_VALUE GPIO_HIGH
-
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
-
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_CS_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_CS_PIN);
- printk(KERN_ERR "request lcd cs pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_CS_PIN, LCD_CS_VALUE);
- }
- }
-
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_EN_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_EN_PIN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_EN_PIN, LCD_EN_VALUE);
- }
- }
-
- if(MIPI_LCD_RST_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(MIPI_LCD_RST_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(MIPI_LCD_RST_PIN);
- printk(KERN_ERR "request mipi lcd rst pin fail!\n");
- return -1;
- }
-
- else
- {
- gpio_set_value(MIPI_LCD_RST_PIN, !GPIO_LOW);
- msleep(20);
- }
- }
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, !LCD_CS_VALUE);
- }
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, !LCD_EN_VALUE);
- }
-
- if(MIPI_LCD_RST_PIN !=INVALID_GPIO)
- {
- gpio_set_value(MIPI_LCD_RST_PIN, GPIO_LOW);
- msleep(10);
- }
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE);
- }
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
- }
-
- if(MIPI_LCD_RST_PIN !=INVALID_GPIO)
- {
- gpio_set_value(MIPI_LCD_RST_PIN, !GPIO_LOW);
- msleep(10);
- }
- return 0;
-}
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
-struct rk29fb_info lcdc0_screen_info = {
-#if defined(CONFIG_RK_HDMI) && defined(CONFIG_HDMI_SOURCE_LCDC0) && defined(CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL)
- .prop = EXTEND, //extend display device
- .io_init = NULL,
- .io_disable = NULL,
- .io_enable = NULL,
- .set_screen_info = hdmi_init_lcdc,
-#else
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-#endif
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
-struct rk29fb_info lcdc1_screen_info = {
-#if defined(CONFIG_RK_HDMI) && defined(CONFIG_HDMI_SOURCE_LCDC1) && defined(CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL)
- .prop = EXTEND, //extend display device
- .io_init = NULL,
- .io_disable = NULL,
- .io_enable = NULL,
- .set_screen_info = hdmi_init_lcdc,
-#else
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-#endif
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-#if defined(CONFIG_ARCH_RK3188)
-static struct resource resource_mali[] = {
- [0] = {
- .name = "ump buf",
- .start = 0,
- .end = 0,
- .flags = IORESOURCE_MEM,
- },
-
-};
-
-static struct platform_device device_mali= {
- .name = "mali400_ump",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_mali),
- .resource = resource_mali,
-};
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
-static struct resource resource_lcdc0[] = {
- [0] = {
- .name = "lcdc0 reg",
- .start = RK30_LCDC0_PHYS,
- .end = RK30_LCDC0_PHYS + RK30_LCDC0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc0 irq",
- .start = IRQ_LCDC0,
- .end = IRQ_LCDC0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc0 = {
- .name = "rk30-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc0),
- .resource = resource_lcdc0,
- .dev = {
- .platform_data = &lcdc0_screen_info,
- },
-};
-#endif
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
-static struct resource resource_lcdc1[] = {
- [0] = {
- .name = "lcdc1 reg",
- .start = RK30_LCDC1_PHYS,
- .end = RK30_LCDC1_PHYS + RK30_LCDC1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc1 irq",
- .start = IRQ_LCDC1,
- .end = IRQ_LCDC1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc1 = {
- .name = "rk30-lcdc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resource_lcdc1),
- .resource = resource_lcdc1,
- .dev = {
- .platform_data = &lcdc1_screen_info,
- },
-};
-#endif
-
-#if defined(CONFIG_MFD_RK610)
-#define RK610_RST_PIN RK30_PIN2_PC5
-static int rk610_power_on_init(void)
-{
- int ret;
- if(RK610_RST_PIN != INVALID_GPIO)
- {
- ret = gpio_request(RK610_RST_PIN, "rk610 reset");
- if (ret)
- {
- printk(KERN_ERR "rk610_control_probe request gpio fail\n");
- }
- else
- {
- gpio_direction_output(RK610_RST_PIN, GPIO_HIGH);
- msleep(100);
- gpio_direction_output(RK610_RST_PIN, GPIO_LOW);
- msleep(100);
- gpio_set_value(RK610_RST_PIN, GPIO_HIGH);
- }
- }
-
- return 0;
-
-}
-
-
-static struct rk610_ctl_platform_data rk610_ctl_pdata = {
- .rk610_power_on_init = rk610_power_on_init,
-};
-#endif
-
-#if defined(CONFIG_MFD_RK616)
-#define RK616_RST_PIN RK30_PIN3_PB2
-#define RK616_PWREN_PIN RK30_PIN0_PA3
-#define RK616_SCL_RATE (100*1000) //i2c scl rate
-static int rk616_power_on_init(void)
-{
- int ret;
-
- if(RK616_PWREN_PIN != INVALID_GPIO)
- {
- ret = gpio_request(RK616_PWREN_PIN, "rk616 pwren");
- if (ret)
- {
- printk(KERN_ERR "rk616 pwren gpio request fail\n");
- }
- else
- {
- gpio_direction_output(RK616_PWREN_PIN,GPIO_HIGH);
- }
- }
-
- if(RK616_RST_PIN != INVALID_GPIO)
- {
- ret = gpio_request(RK616_RST_PIN, "rk616 reset");
- if (ret)
- {
- printk(KERN_ERR "rk616 reset gpio request fail\n");
- }
- else
- {
- gpio_direction_output(RK616_RST_PIN, GPIO_HIGH);
- msleep(2);
- gpio_direction_output(RK616_RST_PIN, GPIO_LOW);
- msleep(10);
- gpio_set_value(RK616_RST_PIN, GPIO_HIGH);
- }
- }
-
- return 0;
-
-}
-
-
-static int rk616_power_deinit(void)
-{
- gpio_set_value(RK616_PWREN_PIN,GPIO_LOW);
- gpio_set_value(RK616_RST_PIN,GPIO_LOW);
- gpio_free(RK616_PWREN_PIN);
- gpio_free(RK616_RST_PIN);
-
- return 0;
-}
-
-static struct rk616_platform_data rk616_pdata = {
- .power_init = rk616_power_on_init,
- .power_deinit = rk616_power_deinit,
- .scl_rate = RK616_SCL_RATE,
- .lcd0_func = INPUT, //port lcd0 as input
- .lcd1_func = INPUT, //port lcd1 as input
- .lvds_ch_nr = 1, //the number of used lvds channel
- .hdmi_irq = RK30_PIN2_PD6,
- .spk_ctl_gpio = RK30_PIN2_PD7,
- .hp_ctl_gpio = RK30_PIN2_PD7,
-};
-#endif
-
-
-#ifdef CONFIG_SND_SOC_RK610
-static int rk610_codec_io_init(void)
-{
-//if need iomux.
-//Must not gpio_request
- return 0;
-}
-
-static struct rk610_codec_platform_data rk610_codec_pdata = {
- .spk_ctl_io = RK30_PIN2_PD7,
- .io_init = rk610_codec_io_init,
-};
-#endif
-
-#ifdef CONFIG_ANDROID_TIMED_GPIO
-static struct timed_gpio timed_gpios[] = {
- {
- .name = "vibrator",
- .gpio = INVALID_GPIO,
- .max_timeout = 1000,
- .active_low = 0,
- .adjust_time =20, //adjust for diff product
- },
-};
-
-static struct timed_gpio_platform_data rk29_vibrator_info = {
- .num_gpios = 1,
- .gpios = timed_gpios,
-};
-
-static struct platform_device rk29_device_vibrator = {
- .name = "timed-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_vibrator_info,
- },
-
-};
-#endif
-
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
-static struct gpio_led rk29_leds[] = {
- {
- .name = "button-backlight",
- .gpio = INVALID_GPIO,
- .default_trigger = "timer",
- .active_low = 0,
- .retain_state_suspended = 0,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- },
-};
-
-static struct gpio_led_platform_data rk29_leds_pdata = {
- .leds = rk29_leds,
- .num_leds = ARRAY_SIZE(rk29_leds),
-};
-
-static struct platform_device rk29_device_gpio_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_leds_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_RK_IRDA
-#define IRDA_IRQ_PIN INVALID_GPIO //RK30_PIN0_PA3
-
-static int irda_iomux_init(void)
-{
- int ret = 0;
-
- //irda irq pin
- ret = gpio_request(IRDA_IRQ_PIN, NULL);
- if (ret != 0) {
- gpio_free(IRDA_IRQ_PIN);
- printk(">>>>>> IRDA_IRQ_PIN gpio_request err \n ");
- }
- gpio_pull_updown(IRDA_IRQ_PIN, PullDisable);
- gpio_direction_input(IRDA_IRQ_PIN);
-
- return 0;
-}
-
-static int irda_iomux_deinit(void)
-{
- gpio_free(IRDA_IRQ_PIN);
- return 0;
-}
-
-static struct irda_info rk29_irda_info = {
- .intr_pin = IRDA_IRQ_PIN,
- .iomux_init = irda_iomux_init,
- .iomux_deinit = irda_iomux_deinit,
- //.irda_pwr_ctl = bu92747guw_power_ctl,
-};
-
-static struct platform_device irda_device = {
-#ifdef CONFIG_RK_IRDA_NET
- .name = "rk_irda",
-#else
- .name = "bu92747_irda",
-#endif
- .id = -1,
- .dev = {
- .platform_data = &rk29_irda_info,
- }
-};
-#endif
-
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and sdio.noted by xbw at 2012-03-05
-**************************************************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "board-rk3168-tb-sdmmc-conifg.c"
-#include "../plat-rk/rk-sdmmc-ops.c"
-#include "../plat-rk/rk-sdmmc-wifi.c"
-#endif //endif ---#ifdef CONFIG_SDMMC_RK29
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- iomux_set(MMC0_CMD);
- iomux_set(MMC0_CLKOUT);
- iomux_set(MMC0_D0);
- iomux_set(MMC0_D1);
- iomux_set(MMC0_D2);
- iomux_set(MMC0_D3);
-
- iomux_set_gpio_mode(iomux_mode_to_gpio(MMC0_DETN));
-
- gpio_request(RK30_PIN3_PA7, "sdmmc-power");
- gpio_direction_output(RK30_PIN3_PA7, GPIO_LOW);
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- #if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set_gpio_mode(iomux_gpio_to_mode(RK29SDK_SD_CARD_DETECT_N));
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO);
- #endif
- #else
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(MMC0_DETN);
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FMUX);
- #endif
- #endif
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) && defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- .status = rk29sdk_wifi_mmc0_status,
- .register_status_notify = rk29sdk_wifi_mmc0_status_register,
-#endif
-
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .power_en = RK29SDK_SD_CARD_PWR_EN,
- .power_en_level = RK29SDK_SD_CARD_PWR_EN_LEVEL,
-#else
- .power_en = INVALID_GPIO,
- .power_en_level = GPIO_LOW,
-#endif
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC0_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- .det_pin_info = {
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N, //INVALID_GPIO,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
- #endif
- },
-
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- iomux_set(MMC1_CMD);
- iomux_set(MMC1_CLKOUT);
- iomux_set(MMC1_D0);
- iomux_set(MMC1_D1);
- iomux_set(MMC1_D2);
- iomux_set(MMC1_D3);
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC) || defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC1_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- #if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
- .sdio_INT_gpio = RK29SDK_WIFI_SDIO_CARD_INT,
- #endif
-
- .det_pin_info = {
-#if defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- #else
- .io = INVALID_GPIO,
- #endif
-
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-
- .enable_sd_wakeup = 0,
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-/**************************************************************************************************
- * the end of setting for SDMMC devices
-**************************************************************************************************/
-
-#ifdef CONFIG_BATTERY_RK30_ADC
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = RK30_PIN0_PB2,
- .batt_low_pin = RK30_PIN0_PB1,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = RK30_PIN0_PA6,
- .dc_det_level = GPIO_LOW,
- .charge_ok_level = GPIO_HIGH,
-};
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-#ifdef CONFIG_CW2015_BATTERY
-/*
- note the follow array must set depend on the battery that you use
- you must send the battery to cellwise-semi the contact information:
- name: chen gan; tel:13416876079; E-mail: ben.chen@cellwise-semi.com
- */
-static u8 config_info[SIZE_BATINFO] = {
- 0x15, 0x42, 0x60, 0x59, 0x52,
- 0x58, 0x4D, 0x48, 0x48, 0x44,
- 0x44, 0x46, 0x49, 0x48, 0x32,
- 0x24, 0x20, 0x17, 0x13, 0x0F,
- 0x19, 0x3E, 0x51, 0x45, 0x08,
- 0x76, 0x0B, 0x85, 0x0E, 0x1C,
- 0x2E, 0x3E, 0x4D, 0x52, 0x52,
- 0x57, 0x3D, 0x1B, 0x6A, 0x2D,
- 0x25, 0x43, 0x52, 0x87, 0x8F,
- 0x91, 0x94, 0x52, 0x82, 0x8C,
- 0x92, 0x96, 0xFF, 0x7B, 0xBB,
- 0xCB, 0x2F, 0x7D, 0x72, 0xA5,
- 0xB5, 0xC1, 0x46, 0xAE
-};
-
-static struct cw_bat_platform_data cw_bat_platdata = {
- .dc_det_pin = RK30_PIN0_PB2,
- .dc_det_level = GPIO_LOW,
-
- .bat_low_pin = RK30_PIN0_PB1,
- .bat_low_level = GPIO_LOW,
- .chg_ok_pin = INVALID_GPIO,
- .chg_ok_level = GPIO_HIGH,
-
- .is_usb_charge = 0,
- .chg_mode_sel_pin = INVALID_GPIO,
- .chg_mode_sel_level = GPIO_HIGH,
-
- .cw_bat_config_info = config_info,
-
-};
-
-#endif
-#ifdef CONFIG_RK30_PWM_REGULATOR
-static int pwm_voltage_map[] = {
- 800000,825000,850000, 875000,900000, 925000 ,950000, 975000,1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000,1375000
-};
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_cpu",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] =
-{
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
- .pwm_id = 1,
- .pwm_gpio = RK30_PIN3_PD4,
- .pwm_iomux_pwm = PWM1,
- .pwm_iomux_gpio = GPIO3_D4,
- .pwm_voltage = 1100000,
- .suspend_voltage = 1000000,
- .min_uV = 800000,
- .max_uV = 1375000,
- .coefficient = 575, //57.5%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-#endif
-
-#ifdef CONFIG_RK29_VMAC
-#define PHY_PWR_EN_GPIO RK30_PIN1_PD6
-#include "board-rk30-sdk-vmac.c"
-#endif
-
-#ifdef CONFIG_RFKILL_RK
-// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
-static struct rfkill_rk_platform_data rfkill_rk_platdata = {
- .type = RFKILL_TYPE_BLUETOOTH,
-
- .poweron_gpio = { // BT_REG_ON
- .io = INVALID_GPIO, //RK30_PIN3_PC7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_poweron",
- .fgpio = GPIO3_C7,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN3_PC7, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_reset",
- .fgpio = GPIO3_C7,
- },
- },
-
- .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
- .io = RK30_PIN3_PC6, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_wake",
- .fgpio = GPIO3_C6,
- },
- },
-
- .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .gpio = {
- .io = RK30_PIN0_PA5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
- .iomux = {
- .name = NULL,
- },
- },
- },
-
- .rts_gpio = { // UART_RTS, enable or disable BT's data coming
- .io = RK30_PIN1_PA3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_rts",
- .fgpio = GPIO1_A3,
- .fmux = UART0_RTSN,
- },
- },
-};
-
-static struct platform_device device_rfkill_rk = {
- .name = "rfkill_rk",
- .id = -1,
- .dev = {
- .platform_data = &rfkill_rk_platdata,
- },
-};
-#endif
-
-#if defined(CONFIG_GPS_RK)
-int rk_gps_io_init(void)
-{
- printk("%s \n", __FUNCTION__);
-
- gpio_request(RK30_PIN1_PB5, NULL);
- gpio_direction_output(RK30_PIN1_PB5, GPIO_LOW);
-
- iomux_set(GPS_RFCLK);//GPS_CLK
- iomux_set(GPS_MAG);//GPS_MAG
- iomux_set(GPS_SIG);//GPS_SIGN
-
- gpio_request(RK30_PIN1_PA6, NULL);
- gpio_direction_output(RK30_PIN1_PA6, GPIO_LOW);
-
- gpio_request(RK30_PIN1_PA5, NULL);
- gpio_direction_output(RK30_PIN1_PA5, GPIO_LOW);
-
- gpio_request(RK30_PIN1_PA7, NULL);
- gpio_direction_output(RK30_PIN1_PA7, GPIO_LOW);
- return 0;
-}
-int rk_gps_power_up(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_power_down(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_reset_set(int level)
-{
- return 0;
-}
-int rk_enable_hclk_gps(void)
-{
- struct clk *gps_aclk = NULL;
- gps_aclk = clk_get(NULL, "aclk_gps");
- if(gps_aclk) {
- clk_enable(gps_aclk);
- clk_put(gps_aclk);
- printk("%s \n", __FUNCTION__);
- }
- else
- printk("get gps aclk fail\n");
- return 0;
-}
-int rk_disable_hclk_gps(void)
-{
- struct clk *gps_aclk = NULL;
- gps_aclk = clk_get(NULL, "aclk_gps");
- if(gps_aclk) {
- //TO wait long enough until GPS ISR is finished.
- msleep(5);
- clk_disable(gps_aclk);
- clk_put(gps_aclk);
- printk("%s \n", __FUNCTION__);
- }
- else
- printk("get gps aclk fail\n");
- return 0;
-}
-struct rk_gps_data rk_gps_info = {
- .io_init = rk_gps_io_init,
- .power_up = rk_gps_power_up,
- .power_down = rk_gps_power_down,
- .reset = rk_gps_reset_set,
- .enable_hclk_gps = rk_enable_hclk_gps,
- .disable_hclk_gps = rk_disable_hclk_gps,
- .GpsSign = RK30_PIN1_PB3,
- .GpsMag = RK30_PIN1_PB2, //GPIO index
- .GpsClk = RK30_PIN1_PB4, //GPIO index
- .GpsVCCEn = RK30_PIN1_PB5, //GPIO index
- .GpsSpi_CSO = RK30_PIN1_PA4, //GPIO index
- .GpsSpiClk = RK30_PIN1_PA5, //GPIO index
- .GpsSpiMOSI = RK30_PIN1_PA7, //GPIO index
- .GpsIrq = IRQ_GPS,
- .GpsSpiEn = 0,
- .GpsAdcCh = 2,
- .u32GpsPhyAddr = RK30_GPS_PHYS,
- .u32GpsPhySize = RK30_GPS_SIZE,
-};
-
-struct platform_device rk_device_gps = {
- .name = "gps_hv5820b",
- .id = -1,
- .dev = {
- .platform_data = &rk_gps_info,
- }
- };
-#endif
-
-#if defined(CONFIG_MT5931_MT6622)
-static struct mt6622_platform_data mt6622_platdata = {
- .power_gpio = { // BT_REG_ON
- .io = RK30_PIN3_PD5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN0_PD7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .irq_gpio = {
- .io = RK30_PIN3_PD2,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .rts_gpio = { // UART_RTS
- .io = RK30_PIN1_PA3,
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_rts",
- .fgpio = GPIO1_A3,
- .fmux = UART0_RTSN,
- },
- },
-};
-
-static struct platform_device device_mt6622 = {
- .name = "mt6622",
- .id = -1,
- .dev = {
- .platform_data = &mt6622_platdata,
- },
-};
-#endif
-
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_ANDROID_TIMED_GPIO
- &rk29_device_vibrator,
-#endif
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
- &rk29_device_gpio_leds,
-#endif
-#ifdef CONFIG_RK_IRDA
- &irda_device,
-#endif
-#if defined(CONFIG_WIFI_CONTROL_FUNC)||defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- &rk29sdk_wifi_device,
-#endif
-
-#if defined(CONFIG_MT6620)
- &mt3326_device_gps,
-#endif
-
-#ifdef CONFIG_RK29_SUPPORT_MODEM
- &rk30_device_modem,
-#endif
-#if defined(CONFIG_MU509)
- &rk29_device_mu509,
-#endif
-#if defined(CONFIG_MW100)
- &rk29_device_mw100,
-#endif
-#if defined(CONFIG_MT6229)
- &rk29_device_mt6229,
-#endif
-#ifdef CONFIG_BATTERY_RK30_ADC
- &rk30_device_adc_battery,
-#endif
-#ifdef CONFIG_RFKILL_RK
- &device_rfkill_rk,
-#endif
-#ifdef CONFIG_GPS_RK
- &rk_device_gps,
-#endif
-#if defined(CONFIG_ARCH_RK3188)
- &device_mali,
-#endif
-#ifdef CONFIG_MT5931_MT6622
- &device_mt6622,
-#endif
-};
-
-static int rk_platform_add_display_devices(void)
-{
- struct platform_device *fb = NULL; //fb
- struct platform_device *lcdc0 = NULL; //lcdc0
- struct platform_device *lcdc1 = NULL; //lcdc1
- struct platform_device *bl = NULL; //backlight
-#ifdef CONFIG_FB_ROCKCHIP
- fb = &device_fb;
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
- lcdc0 = &device_lcdc0,
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
- lcdc1 = &device_lcdc1,
-#endif
-
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- bl = &rk29_device_backlight,
-#endif
- __rk_platform_add_display_devices(fb,lcdc0,lcdc1,bl);
-
- return 0;
-
-}
-
-// i2c
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1d,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_GS_LIS3DH)
- {
- .type = "gs_lis3dh",
- .addr = 0x19, //0x19(SA0-->VCC), 0x18(SA0-->GND)
- .flags = 0,
- .irq = LIS3DH_INT_PIN,
- .platform_data = &lis3dh_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8975_info,
- },
-#endif
-#if defined (CONFIG_GYRO_L3G4200D)
- {
- .type = "l3g4200d_gryo",
- .addr = 0x69,
- .flags = 0,
- .irq = L3G4200D_INT_PIN,
- .platform_data = &l3g4200d_info,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-
-#if defined (CONFIG_SND_SOC_RT5631)
- {
- .type = "rt5631",
- .addr = 0x1a,
- .flags = 0,
- },
-#endif
-
-#if defined (CONFIG_SND_SOC_RT5512)
- {
- .type = "rt5512",
- .addr = 0x18,
- .flags = 0,
- },
-#endif
-
-#if defined (CONFIG_SND_SOC_CX2070X)
- {
- .type = "cx2070x",
- .addr = 0x14,
- .flags = 0,
- },
-#endif
-
-#if defined (CONFIG_SND_SOC_RT5640)
- {
- .type = "rt5640",
- .addr = 0x1c,
- .flags = 0,
- },
-#endif
-
-#ifdef CONFIG_MFD_RK610
- {
- .type = "rk610_ctl",
- .addr = 0x40,
- .flags = 0,
- .platform_data = &rk610_ctl_pdata,
- },
-#ifdef CONFIG_RK610_TVOUT
- {
- .type = "rk610_tvout",
- .addr = 0x42,
- .flags = 0,
- },
-#endif
-#ifdef CONFIG_HDMI_RK610
- {
- .type = "rk610_hdmi",
- .addr = 0x46,
- .flags = 0,
- .irq = INVALID_GPIO,
- },
-#endif
-#ifdef CONFIG_SND_SOC_RK610
- {//RK610_CODEC addr from 0x60 to 0x80 (0x60~0x80)
- .type = "rk610_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- .platform_data = &rk610_codec_pdata,
- },
-#endif
-#endif
-
-};
-#endif
-
-int __sramdata g_pmic_type = 0;
-#ifdef CONFIG_I2C1_RK30
-#ifdef CONFIG_MFD_WM831X_I2C
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info wm8326_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "dcdc3", //ddr
- .min_uv = 1150000,
- .max_uv = 1150000,
- .suspend_vol = 1150000,
- },
- #ifdef CONFIG_MACH_RK3066_SDK
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3000000,
- },
- #else
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3000000,
- .max_uv = 3000000,
- .suspend_vol = 2800000,
- },
- #endif
-};
-
-static struct pmu_info wm8326_ldo_info[] = {
- {
- .name = "ldo1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo2", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo3", //
- .min_uv = 1100000,
- .max_uv = 1100000,
- .suspend_vol = 1100000,
- },
- {
- .name = "ldo4", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 1000000,
- },
- {
- .name = "ldo5", //vcc25
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo6", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo7", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- .suspend_vol = 2800000,
- },
- {
- .name = "ldo8", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo9", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo10", //flash_io
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
-};
-
-#include "board-pmu-wm8326.c"
-#endif
-
-#ifdef CONFIG_MFD_TPS65910
-#define TPS65910_HOST_IRQ RK30_PIN0_PB3
-
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info tps65910_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vdd2", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vio", //vcc_io
- .min_uv = 2500000,
- .max_uv = 2500000,
- },
-
-};
-static struct pmu_info tps65910_ldo_info[] = {
- {
- .name = "vpll", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "vdig2", //vdd_jetta
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vaux1", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "vaux2", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vaux33", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vmmc", //vcc30
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
- {
- .name = "vdac", //vcc18
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- };
-
-#include "board-pmu-tps65910.c"
-#endif
-
-#ifdef CONFIG_REGULATOR_ACT8846
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-#define PMU_VSEL RK30_PIN3_PD3
-static struct pmu_info act8846_dcdc_info[] = {
- {
- .name = "act_dcdc1", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- .suspend_vol = 1200000,
- },
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 1200000,
- #else
- .suspend_vol = 900000,
- #endif
-
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 1200000,
- #else
- .suspend_vol = 900000,
- #endif
-
- },
- {
- .name = "act_dcdc4", //vccio
- .min_uv = 3000000,
- .max_uv = 3000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 3000000,
- #else
- .suspend_vol = 2800000,
- #endif
-
- },
-
-};
-static struct pmu_info act8846_ldo_info[] = {
- {
- .name = "act_ldo1", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "act_ldo2", //vdd12
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "act_ldo3", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo4", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo5", //vcctp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo6", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo7", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo8", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- };
-
-#include "board-pmu-act8846.c"
-#endif
-
-#ifdef CONFIG_MFD_RK808
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-#define RK808_HOST_IRQ RK30_PIN0_PB3
-
-static struct pmu_info rk808_dcdc_info[] = {
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 900000,
- },
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 900000,
- },
- {
- .name = "rk_dcdc3", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- .suspend_vol = 1200000,
- },
- {
- .name = "rk_dcdc4", //vccio
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3000000,
- },
-
-};
-static struct pmu_info rk808_ldo_info[] = {
- {
- .name = "rk_ldo1", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "rk_ldo2", //vcctp
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
-
- },
- {
- .name = "rk_ldo3", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 1000000,
- },
- {
- .name = "rk_ldo4", //vcc18
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "rk_ldo5", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- .suspend_vol = 2800000,
- },
- {
- .name = "rk_ldo6", //vdd12
- .min_uv = 1200000,
- .max_uv = 1200000,
- .suspend_vol = 1200000,
- },
- {
- .name = "rk_ldo7", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "rk_ldo8", //vcca_33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- };
-
-#include "board-pmu-rk808.c"
-#endif
-#ifdef CONFIG_MFD_RICOH619
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-#define RICOH619_HOST_IRQ RK30_PIN0_PB3
-
-static struct pmu_info ricoh619_dcdc_info[] = {
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 900000,
- },
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 900000,
- },
-
- {
- .name = "ricoh_dc3", //vcc18
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
-
- {
- .name = "ricoh_dc4", //vccio
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
-
- {
- .name = "ricoh_dc5", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- .suspend_vol = 1200000,
- },
-
-};
-static struct pmu_info ricoh619_ldo_info[] = {
- {
- .name = "ricoh_ldo1", //vcc30
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
- {
- .name = "ricoh_ldo2", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "ricoh_ldo3", //vcctp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "ricoh_ldo4", //vccsd
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "ricoh_ldo5", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "ricoh_ldo6", //vdd12
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "ricoh_ldo7", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "ricoh_ldo8", //vcc25
- .min_uv = 2500000,
- .max_uv = 2500000,
- },
- {
- .name = "ricoh_ldo9", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "ricoh_ldo10", //vcca18
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
-
- };
-
-#include "board-pmu-ricoh619.c"
-#endif
-
-#ifdef CONFIG_MFD_RT5025
-#define RT5025_HOST_IRQ RK30_PIN0_PB3
-
-static struct pmu_info rt5025_dcdc_info[] = {
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
-
- {
- .name = "rt5025-dcdc3", //vccio
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
-
- {
- .name = "rt5025-dcdc4", //vccio
- .min_uv = 5000000,
- .max_uv = 5000000,
- },
-
-};
-static struct pmu_info rt5025_ldo_info[] = {
- {
- .name = "rt5025-ldo1", //vcc18
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "rt5025-ldo2", //vddjetta
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "rt5025-ldo3", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "rt5025-ldo4", //vccjetta
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "rt5025-ldo5", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "rt5025-ldo6", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
-
- };
-
-#include "board-pmu-rt5025.c"
-#endif
-
-
-
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_MFD_WM831X_I2C)
- {
- .type = "wm8326",
- .addr = 0x34,
- .flags = 0,
- .irq = RK30_PIN0_PB3,
- .platform_data = &wm831x_platdata,
- },
-#endif
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-
-#if defined (CONFIG_REGULATOR_ACT8846)
- {
- .type = "act8846",
- .addr = 0x5a,
- .flags = 0,
- // .irq = ACT8846_HOST_IRQ,
- .platform_data=&act8846_data,
- },
-#endif
-#if defined (CONFIG_MFD_RK808)
- {
- .type = "rk808",
- .addr = 0x1b,
- .flags = 0,
- // .irq = ACT8846_HOST_IRQ,
- .platform_data=&rk808_data,
- },
-#endif
-
-#if defined (CONFIG_MFD_RICOH619)
- {
- .type = "ricoh619",
- .addr = 0x32,
- .flags = 0,
- .irq = RICOH619_HOST_IRQ,
- .platform_data=&ricoh619_data,
- },
-#endif
-
-#if defined (CONFIG_MFD_RT5025)
- {
- .type = "RT5025",
- .addr = 0x35,
- .flags = 0,
- .irq = RT5025_HOST_IRQ,
- .platform_data=&rt5025_data,
- },
-#endif
-
-#if defined (CONFIG_RTC_HYM8563)
- {
- .type = "rtc_hym8563",
- .addr = 0x51,
- .flags = 0,
- .irq = RK30_PIN1_PA4,
- },
-#if defined (CONFIG_CW2015_BATTERY)
- {
- .type = "cw201x",
- .addr = 0x62,
- .flags = 0,
- .platform_data = &cw_bat_platdata,
- },
-#endif
-#endif
-
-};
-#endif
-
-void __sramfunc board_pmu_suspend(void)
-{
-#if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_suspend();
-#endif
-#if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_suspend();
-#endif
-#if defined (CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- board_pmu_act8846_suspend();
-#endif
-#if defined (CONFIG_MFD_RK808)
- if(pmic_is_rk808())
- board_pmu_rk808_suspend();
-#endif
-#if defined (CONFIG_MFD_RICOH619)
- if(pmic_is_ricoh619())
- board_pmu_ricoh619_suspend();
-#endif
-
-}
-
-void __sramfunc board_pmu_resume(void)
-{
-#if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_resume();
-#endif
-#if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_resume();
-#endif
-#if defined (CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- board_pmu_act8846_resume();
-#endif
-#if defined (CONFIG_MFD_RK808)
- if(pmic_is_rk808())
- board_pmu_rk808_resume();
-#endif
-#if defined (CONFIG_MFD_RICOH619)
- if(pmic_is_ricoh619())
- board_pmu_ricoh619_resume();
-#endif
-
-}
-
- int __sramdata gpio3d6_iomux,gpio3d6_do,gpio3d6_dir,gpio3d6_en;
-
-#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
-
-void __sramfunc rk30_pwm_logic_suspend_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
-
-// int gpio0d7_iomux,gpio0d7_do,gpio0d7_dir,gpio0d7_en;
- sram_udelay(10000);
- gpio3d6_iomux = grf_readl(GRF_GPIO3D_IOMUX);
- gpio3d6_do = grf_readl(GRF_GPIO3H_DO);
- gpio3d6_dir = grf_readl(GRF_GPIO3H_DIR);
- gpio3d6_en = grf_readl(GRF_GPIO3H_EN);
-
- grf_writel((0x03000300), GRF_GPIO3D_IOMUX);
- grf_writel((1<<28)|(1<<12), GRF_GPIO3H_DIR);
- grf_writel((1<<28)|(1<<12), GRF_GPIO3H_DO);
- grf_writel((1<<28)|(1<<12), GRF_GPIO3H_EN);
-#endif
-}
-void __sramfunc rk30_pwm_logic_resume_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- grf_writel((1<<28)|gpio3d6_iomux, GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|gpio3d6_en, GRF_GPIO3H_EN);
- grf_writel((1<<30)|gpio3d6_dir, GRF_GPIO3H_DIR);
- grf_writel((1<<30)|gpio3d6_do, GRF_GPIO3H_DO);
- sram_udelay(10000);
-
-#endif
-
-}
-extern void pwm_suspend_voltage(void);
-extern void pwm_resume_voltage(void);
-void rk30_pwm_suspend_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_suspend_voltage();
-#endif
-}
-void rk30_pwm_resume_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_resume_voltage();
-#endif
-}
-
-
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-#if defined (CONFIG_TOUCHSCREEN_GT8XX)
- {
- .type = "Goodix-TS",
- .addr = 0x55,
- .flags = 0,
- .irq = RK30_PIN1_PB7,
- .platform_data = &goodix_info,
- },
-#endif
-#if defined (CONFIG_LS_CM3217)
- {
- .type = "lightsensor",
- .addr = 0x10,
- .flags = 0,
- .platform_data = &cm3217_info,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C4_RK30
-static struct i2c_board_info __initdata i2c4_info[] = {
-#if defined (CONFIG_MFD_RK616)
- {
- .type = "rk616",
- .addr = 0x50,
- .flags = 0,
- .platform_data = &rk616_pdata,
- },
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO// RK30_PIN2_PD6 //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO//RK30_PIN2_PD7 //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- //set iomux (gpio) here
- //rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME, GPIO2D_GPIO2D7);
- //rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME, GPIO2D_GPIO2D6);
-
- return 0;
-}
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C4_RK30
- i2c_register_board_info(4, i2c4_info, ARRAY_SIZE(i2c4_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(5, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-
-// ========== Begin of rk3168 top board keypad defination ============
-
-#include <plat/key.h>
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .adc_value = 900,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK30_PIN0_PA4,
- .active_low = PRESS_LEV_LOW,
- .wakeup = 1,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .adc_value = 1,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "menu",
- .code = EV_MENU,
- .adc_value = 133,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .adc_value = 550,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .adc_value = 333,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "camera",
- .code = KEY_CAMERA,
- .adc_value = 742,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = 1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
-// =========== End of rk3168 top board keypad defination =============
-
-
-#define POWER_ON_PIN RK30_PIN0_PA0 //power_hold
-static void rk30_pm_power_off(void)
-{
- printk(KERN_ERR "rk30_pm_power_off start...\n");
- #if defined(CONFIG_MFD_WM831X)
- if(pmic_is_wm8326()){
- wm831x_set_bits(Wm831x,WM831X_GPIO_LEVEL,0x0001,0x0000); //set sys_pwr 0
- wm831x_device_shutdown(Wm831x);//wm8326 shutdown
- }
- #endif
-
- #if defined(CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- {
- act8846_device_shutdown();
- }
- #endif
-
- #if defined(CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- {
- tps65910_device_shutdown();//tps65910 shutdown
- }
- #endif
-
- #if defined(CONFIG_MFD_RK808)
- if(pmic_is_rk808())
- {
- rk808_device_shutdown();//rk808 shutdown
- }
- #endif
- #if defined(CONFIG_MFD_RICOH619)
- if(pmic_is_ricoh619()){
- ricoh619_power_off(); //ricoh619 shutdown
- }
- #endif
-
- #if defined(CONFIG_MFD_RT5025)
- if(pmic_is_rt5025()){
- rt5025_power_off(); //rt5025 shutdown
- }
- #endif
-
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
- while (1);
-}
-
-static void __init machine_rk30_board_init(void)
-{
- avs_init();
- gpio_request(POWER_ON_PIN, "poweronpin");
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
- pm_power_off = rk30_pm_power_off;
-
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
-
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- rk_platform_add_display_devices();
- board_usb_detect_init(RK30_PIN0_PA7);
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC)
- rk29sdk_wifi_bt_gpio_control_init();
-#elif defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- rk29sdk_wifi_combo_module_gpio_init();
-#endif
-
-#if defined(CONFIG_MT6620)
- clk_set_rate(clk_get_sys("rk_serial.0", "uart"), 48*1000000);
-#endif
-
-#if defined(CONFIG_MT5931_MT6622)
- clk_set_rate(clk_get_sys("rk_serial.0", "uart"), 24*1000000);
-#endif
-}
-#define HD_SCREEN_SIZE 1920UL*1200UL*4*3
-static void __init rk30_reserve(void)
-{
-#if defined(CONFIG_ARCH_RK3188)
- /*if lcd resolution great than or equal to 1920*1200,reserve the ump memory */
- if(!(get_fb_size() < ALIGN(HD_SCREEN_SIZE,SZ_1M)))
- {
- int ump_mem_phy_size=512UL*1024UL*1024UL;
- resource_mali[0].start = board_mem_reserve_add("ump buf", ump_mem_phy_size);
- resource_mali[0].end = resource_mali[0].start + ump_mem_phy_size -1;
- }
-#endif
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0 buf", get_fb_size());
- resource_fb[0].end = resource_fb[0].start + get_fb_size()- 1;
-#if 0
- resource_fb[1].start = board_mem_reserve_add("ipp buf", RK30_FB0_MEM_SIZE);
- resource_fb[1].end = resource_fb[1].start + RK30_FB0_MEM_SIZE - 1;
-#endif
-
-#if defined(CONFIG_FB_ROTATE) || !defined(CONFIG_THREE_FB_BUFFER)
- resource_fb[2].start = board_mem_reserve_add("fb2 buf",get_fb_size());
- resource_fb[2].end = resource_fb[2].start + get_fb_size() - 1;
-#endif
-#endif
-
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
-
-#ifdef CONFIG_GPS_RK
- //it must be more than 8MB
- rk_gps_info.u32MemoryPhyAddr = board_mem_reserve_add("gps", SZ_8M);
-#endif
- board_mem_reserved();
-}
-/******************************** arm dvfs frequency volt table **********************************/
-/**
- * dvfs_cpu_logic_table: table for arm and logic dvfs
- * @frequency : arm frequency
- * @cpu_volt : arm voltage depend on frequency
- */
-
-#if defined(CONFIG_ARCH_RK3188)
-#if 0
-//sdk
-static struct cpufreq_frequency_table dvfs_arm_table_volt_level0[] = {
- {.frequency = 312 * 1000, .index = 850 * 1000},
- {.frequency = 504 * 1000, .index = 900 * 1000},
- {.frequency = 816 * 1000, .index = 950 * 1000},
- {.frequency = 1008 * 1000, .index = 1025 * 1000},
- {.frequency = 1200 * 1000, .index = 1100 * 1000},
- {.frequency = 1416 * 1000, .index = 1200 * 1000},
- {.frequency = 1608 * 1000, .index = 1300 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-//default for rk sdk testing
-static struct cpufreq_frequency_table dvfs_arm_table_volt_level1[] = {
- {.frequency = 312 * 1000, .index = 875 * 1000},
- {.frequency = 504 * 1000, .index = 925 * 1000},
- {.frequency = 816 * 1000, .index = 975 * 1000},
- {.frequency = 1008 * 1000, .index = 1075 * 1000},
- {.frequency = 1200 * 1000, .index = 1150 * 1000},
- {.frequency = 1416 * 1000, .index = 1250 * 1000},
- {.frequency = 1608 * 1000, .index = 1350 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-#endif
-// for production , fixed: 2013.9.13
-static struct cpufreq_frequency_table dvfs_arm_table_volt_level2[] = {
- {.frequency = 312 * 1000, .index = 925 * 1000},
- {.frequency = 504 * 1000, .index = 950 * 1000},
- {.frequency = 816 * 1000, .index = 1000 * 1000},
- {.frequency = 1008 * 1000, .index = 1075 * 1000},
- {.frequency = 1200 * 1000, .index = 1200 * 1000},
- {.frequency = 1416 * 1000, .index = 1250 * 1000},
- {.frequency = 1608 * 1000, .index = 1350 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-/******************************** gpu dvfs frequency volt table **********************************/
-//sdk
-static struct cpufreq_frequency_table dvfs_gpu_table_volt_level0[] = {
- {.frequency = 133 * 1000, .index = 975 * 1000},//the mininum rate is limited 133M for rk3188
- {.frequency = 200 * 1000, .index = 975 * 1000},
- {.frequency = 266 * 1000, .index = 1000 * 1000},
- {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1100 * 1000},
- {.frequency = 600 * 1000, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-//cube 10'
-static struct cpufreq_frequency_table dvfs_gpu_table_volt_level1[] = {
- {.frequency = 133 * 1000, .index = 975 * 1000},//the mininum rate is limited 133M for rk3188
- {.frequency = 200 * 1000, .index = 1000 * 1000},
- {.frequency = 266 * 1000, .index = 1025 * 1000},
- {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1100 * 1000},
- {.frequency = 600 * 1000, .index = 1250 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-/******************************** ddr dvfs frequency volt table **********************************/
-static struct cpufreq_frequency_table dvfs_ddr_table_volt_level0[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 950 * 1000},
- {.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = 1000 * 1000},
- {.frequency = 396 * 1000 + DDR_FREQ_NORMAL, .index = 1100 * 1000},
- {.frequency = 460 * 1000 + DDR_FREQ_DUALVIEW, .index = 1150 * 1000},
- //{.frequency = 528 * 1000 + DDR_FREQ_NORMAL, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table_t[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 950 * 1000},
- {.frequency = 460 * 1000 + DDR_FREQ_NORMAL, .index = 1150 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-//if you board is good for volt quality,select dvfs_arm_table_volt_level0
-#define dvfs_arm_table dvfs_arm_table_volt_level2
-#define dvfs_gpu_table dvfs_gpu_table_volt_level1
-#define dvfs_ddr_table dvfs_ddr_table_volt_level0
-
-#else
-//for RK3168 && RK3066B
-static struct cpufreq_frequency_table dvfs_arm_table[] = {
- {.frequency = 312 * 1000, .index = 950 * 1000},
- {.frequency = 504 * 1000, .index = 1000 * 1000},
- {.frequency = 816 * 1000, .index = 1050 * 1000},
- {.frequency = 1008 * 1000, .index = 1125 * 1000},
- {.frequency = 1200 * 1000, .index = 1200 * 1000},
- //{.frequency = 1416 * 1000, .index = 1250 * 1000},
- //{.frequency = 1608 * 1000, .index = 1300 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- {.frequency = 100 * 1000, .index = 1000 * 1000},
- {.frequency = 200 * 1000, .index = 1000 * 1000},
- {.frequency = 266 * 1000, .index = 1050 * 1000},
- //{.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1125 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 1000 * 1000},
- {.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = 1050 * 1000},
- {.frequency = 400 * 1000 + DDR_FREQ_NORMAL, .index = 1100 * 1000},
- {.frequency = 450 * 1000, .index = 1150 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-#endif
-/******************************** arm dvfs frequency volt table end **********************************/
-//#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
-//static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
-//static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
-int get_max_freq(struct cpufreq_frequency_table *table)
-{
- int i,temp=0;
-
- for(i=0;table[i].frequency!= CPUFREQ_TABLE_END;i++)
- {
- if(temp<table[i].frequency)
- temp=table[i].frequency;
- }
- printk("get_max_freq=%d\n",temp);
- return temp;
-}
-
-void __init board_clock_init(void)
-{
- u32 flags=RK30_CLOCKS_DEFAULT_FLAGS;
-#if !defined(CONFIG_ARCH_RK3188)
- if(get_max_freq(dvfs_gpu_table)<=(400*1000))
- {
- flags=RK30_CLOCKS_DEFAULT_FLAGS|CLK_GPU_GPLL;
- }
- else
- flags=RK30_CLOCKS_DEFAULT_FLAGS|CLK_GPU_CPLL;
-#endif
- rk30_clock_data_init(periph_pll_default, codec_pll_default, flags);
- //dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "cpu"), dvfs_arm_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
-#if defined(CONFIG_ARCH_RK3188)
- if (rk_pll_flag() == 0)
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
- else
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table_t);
-#else
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
-#endif
-}
-
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk30_fixup,
- .reserve = &rk30_reserve,
- .map_io = rk30_map_io,
- .init_irq = rk30_init_irq,
- .timer = &rk30_timer,
- .init_machine = machine_rk30_board_init,
-MACHINE_END
+++ /dev/null
-#ifdef CONFIG_VIDEO_RK29
-#include <plat/rk_camera.h>
-/* Notes:
-
-Simple camera device registration:
-
- new_camera_device(sensor_name,\ // sensor name, it is equal to CONFIG_SENSOR_X
- face,\ // sensor face information, it can be back or front
- pwdn_io,\ // power down gpio configuration, it is equal to CONFIG_SENSOR_POWERDN_PIN_XX
- flash_attach,\ // sensor is attach flash or not
- mir,\ // sensor image mirror and flip control information
- i2c_chl,\ // i2c channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_IIC_ADAPTER_ID_X
- cif_chl) \ // cif channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_CIF_INDEX_X
-
-Comprehensive camera device registration:
-
- new_camera_device_ex(sensor_name,\
- face,\
- ori,\ // sensor orientation, it is equal to CONFIG_SENSOR_ORIENTATION_X
- pwr_io,\ // sensor power gpio configuration, it is equal to CONFIG_SENSOR_POWER_PIN_XX
- pwr_active,\ // sensor power active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- rst_io,\ // sensor reset gpio configuration, it is equal to CONFIG_SENSOR_RESET_PIN_XX
- rst_active,\ // sensor reset active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- pwdn_io,\
- pwdn_active,\ // sensor power down active level, is equal to CONFIG_SENSOR_POWERDNACTIVE_LEVEL_X
- flash_attach,\
- res,\ // sensor resolution, this is real resolution or resoltuion after interpolate
- mir,\
- i2c_chl,\
- i2c_spd,\ // i2c speed , 100000 = 100KHz
- i2c_addr,\ // the i2c slave device address for sensor
- cif_chl,\
- mclk)\ // sensor input clock rate, 24 or 48
-
-*/
-static struct rkcamera_platform_data new_camera[] = {
-
- new_camera_device(RK29_CAM_SENSOR_NT99340,
- back,
- RK30_PIN3_PB5,
- 0,
- 0,
- 3,
- 0),
- new_camera_device(RK29_CAM_SENSOR_NT99252,
- front,
- RK30_PIN3_PB4,
- 0,
- 0,
- 3,
- 0),
- new_camera_device_end
-};
-
-#endif //#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk30_camera.c"
-/*---------------- Camera Sensor Macro Define End ---------*/
-
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#define CONFIG_SENSOR_POWER_IOCTL_USR 1 //define this refer to your board layout
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
-
-static void rk_cif_power(struct rk29camera_gpio_res *res,int on)
-{
- struct regulator *ldo_18,*ldo_28;
- int camera_power = res->gpio_power;
- int camera_ioflag = res->gpio_flag;
- int camera_io_init = res->gpio_init;
-
- ldo_28 = regulator_get(NULL, "ricoh_ldo4"); // vcc28_cif
- ldo_18 = regulator_get(NULL, "ricoh_ldo5"); // vcc18_cif
- if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){
- printk("get cif ldo failed!\n");
- return;
- }
- if(on == 0){
- while(regulator_is_enabled(ldo_28)>0)
- regulator_disable(ldo_28);
- regulator_put(ldo_28);
- while(regulator_is_enabled(ldo_18)>0)
- regulator_disable(ldo_18);
- regulator_put(ldo_18);
- mdelay(10);
- if (camera_power != INVALID_GPIO) {
- if (camera_io_init & RK29_CAM_POWERACTIVE_MASK) {
- gpio_set_value(camera_power, (((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
- // dprintk("%s..%s..PowerPin=%d ..PinLevel = %x \n",__FUNCTION__,res->dev_name, camera_power, (((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
- }
- }
- }
- else{
- regulator_set_voltage(ldo_28, 2800000, 2800000);
- regulator_enable(ldo_28);
- printk("%s set vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
- regulator_put(ldo_28);
-
- regulator_set_voltage(ldo_18, 1800000, 1800000);
- // regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(ldo_18);
- printk("%s set vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
- regulator_put(ldo_18);
- if (camera_power != INVALID_GPIO) {
- if (camera_io_init & RK29_CAM_POWERACTIVE_MASK) {
- gpio_set_value(camera_power, ((camera_ioflag&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
- //dprintk("%s..%s..PowerPin=%d ..PinLevel = %x \n",__FUNCTION__,res->dev_name, camera_power, ((camera_ioflag&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
- mdelay(10);
- }
- }
-
- }
-}
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- //#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
- rk_cif_power(res,on);
- return 0;
-}
-#endif
-
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-
-
-static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] =
-{
- #if CONFIG_SENSOR_IIC_ADDR_0
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_0,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_1
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_1,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_01
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_01,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_02
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_02,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_11
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_11,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_12
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_12,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
-
- };
-#include "../../../drivers/media/video/rk30_camera.c"
-
-#endif /* CONFIG_VIDEO_RK29 */
+++ /dev/null
-/*
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <mach/dvfs.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <linux/rk_fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/mfd/tps65910.h>
-#include <linux/regulator/act8846.h>
-#include <linux/mfd/rk808.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-
-#ifdef CONFIG_CW2015_BATTERY
-#include <linux/power/cw2015_battery.h>
-#endif
-#if defined(CONFIG_MFD_RK610)
-#include <linux/mfd/rk610_core.h>
-#endif
-
-#if defined(CONFIG_MFD_RK616)
-#include <linux/mfd/rk616.h>
-#endif
-
-
-#if defined(CONFIG_RK_HDMI)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-#if defined(CONFIG_GPS_RK)
-#include "../../../drivers/misc/gps/rk_gps/rk_gps.h"
-#endif
-#if defined(CONFIG_MU509)
-#include <linux/mu509.h>
-#endif
-#if defined(CONFIG_MW100)
-#include <linux/mw100.h>
-#endif
-#if defined(CONFIG_MT6229)
-#include <linux/mt6229.h>
-#endif
-#if defined(CONFIG_ANDROID_TIMED_GPIO)
-#include "../../../drivers/staging/android/timed_gpio.h"
-#endif
-
-#if defined(CONFIG_MT6620)
-#include <linux/gps.h>
-#endif
-#include "../mach-rk30/board-rk3168m-f304-camera.c"
-
-#if defined(CONFIG_TOUCHSCREEN_GT8XX)
-#define TOUCH_RESET_PIN RK30_PIN0_PB6
-#define TOUCH_PWR_PIN RK30_PIN0_PC5 // need to fly line by hardware engineer
-
-/* Android Parameter */
-static int ap_mdm = 0;
-module_param(ap_mdm, int, 0644);
-static int ap_has_alsa = 0;
-module_param(ap_has_alsa, int, 0644);
-static int ap_data_only = 2;
-module_param(ap_data_only, int, 0644);
-static int ap_has_earphone = 0;
-module_param(ap_has_earphone, int, 0644);
-
-
-static int goodix_init_platform_hw(void)
-{
- int ret;
-
- if (TOUCH_PWR_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_PWR_PIN, "goodix power pin");
- if (ret != 0) {
- gpio_free(TOUCH_PWR_PIN);
- printk("goodix power error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_PWR_PIN, 0);
- gpio_set_value(TOUCH_PWR_PIN, GPIO_LOW);
- msleep(100);
- }
-
- if (TOUCH_RESET_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_RESET_PIN, "goodix reset pin");
- if (ret != 0) {
- gpio_free(TOUCH_RESET_PIN);
- printk("goodix gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, 1);
- msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_LOW);
- //msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_HIGH);
- //msleep(500);
- }
- return 0;
-}
-
-struct goodix_platform_data goodix_info = {
- .model = 8105,
- .irq_pin = RK30_PIN1_PB7,
- .rest_pin = TOUCH_RESET_PIN,
- .init_platform_hw = goodix_init_platform_hw,
-};
-#endif
-
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-#define PWM_ID 3
-#define PWM_MODE PWM3
-#define PWM_EFFECT_VALUE 0
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-#define BL_EN_PIN RK30_PIN0_PA2
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
-
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
- ret = gpio_request(BL_EN_PIN, "bl_en");
- if (ret == 0) {
- gpio_direction_output(BL_EN_PIN, BL_EN_VALUE);
- }
-#endif
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0, pwm_gpio;
-#ifdef LCD_DISP_ON_PIN
- gpio_free(BL_EN_PIN);
-#endif
- pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
- gpio_request(pwm_gpio, "bl_pwm");
- gpio_direction_output(pwm_gpio, GPIO_LOW);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret, pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
-
- ret = gpio_request(pwm_gpio, "bl_pwm");
- if (ret) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return ret;
- }
- gpio_direction_output(pwm_gpio, GPIO_LOW);
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, !BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- int pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
-
- gpio_free(pwm_gpio);
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .min_brightness=100,
- .max_brightness=255,
- .pre_div = 400 * 1000,
- .brightness_mode = BRIGHTNESS_MODE_CONIC,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-#endif
-
-#ifdef CONFIG_RK29_SUPPORT_MODEM
-
-#define RK30_MODEM_POWER RK30_PIN0_PC6
-#define RK30_MODEM_POWER_IOMUX iomux_set(GPIO0_C6)
-
-static int rk30_modem_io_init(void)
-{
- printk("%s\n", __FUNCTION__);
- RK30_MODEM_POWER_IOMUX;
-
- return 0;
-}
-
-static struct rk29_io_t rk30_modem_io = {
- .io_addr = RK30_MODEM_POWER,
- .enable = GPIO_HIGH,
- .disable = GPIO_LOW,
- .io_init = rk30_modem_io_init,
-};
-
-static struct platform_device rk30_device_modem = {
- .name = "rk30_modem",
- .id = -1,
- .dev = {
- .platform_data = &rk30_modem_io,
- }
-};
-#endif
-#if defined(CONFIG_MU509)
-static int mu509_io_init(void)
-{
-
- iomux_set(GPIO2_D5);
- iomux_set(GPIO0_C6);
- iomux_set(GPIO2_D4);
- iomux_set(GPIO0_C4);
- iomux_set(GPIO0_C5);
- return 0;
-}
-
-static int mu509_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mu509_data rk29_mu509_info = {
- .io_init = mu509_io_init,
- .io_deinit = mu509_io_deinit,
- .modem_power_en = RK30_PIN2_PD5,
- .bp_power = RK30_PIN0_PC6,
- .bp_reset = RK30_PIN2_PD4,
- .ap_wakeup_bp = RK30_PIN0_PC4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
-};
-struct platform_device rk29_device_mu509 = {
- .name = "mu509",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mu509_info,
- }
- };
-#endif
-#if defined(CONFIG_MW100)
-static int mw100_io_init(void)
-{
- iomux_set(GPIO2_D5);
- iomux_set(GPIO0_C6);
- iomux_set(GPIO2_D4);
- iomux_set(GPIO0_C4);
- iomux_set(GPIO0_C5);
- return 0;
-}
-
-static int mw100_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mw100_data rk29_mw100_info = {
- .io_init = mw100_io_init,
- .io_deinit = mw100_io_deinit,
- .modem_power_en = RK30_PIN2_PD5,
- .bp_power = RK30_PIN0_PC6,
- .bp_reset = RK30_PIN2_PD4,
- .ap_wakeup_bp = RK30_PIN0_PC4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
-};
-struct platform_device rk29_device_mw100 = {
- .name = "mw100",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mw100_info,
- }
- };
-#endif
-#if defined(CONFIG_MT6229)
-static int mt6229_io_init(void)
-{
- iomux_set(GPIO2_D5);
- iomux_set(GPIO0_C6);
- iomux_set(GPIO2_D4);
- iomux_set(GPIO0_C4);
- iomux_set(GPIO0_C5);
- return 0;
-}
-
-static int mt6229_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mt6229_data rk29_mt6229_info = {
- .io_init = mt6229_io_init,
- .io_deinit = mt6229_io_deinit,
- .modem_power_en = RK30_PIN2_PD5,
- .bp_power = RK30_PIN0_PC6,
- .bp_reset = RK30_PIN2_PD4,
- .ap_wakeup_bp = RK30_PIN0_PC4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
-};
-struct platform_device rk29_device_mt6229 = {
- .name = "mt6229",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mt6229_info,
- }
- };
-#endif
-
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN RK30_PIN0_PB7
-
-static int mma8452_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data mma8452_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma8452_init_platform_hw,
- // .orientation = {-1, 0, 0, 0, -1, 0, 0, 0, 1},
- .orientation = {1, 0, 0, 0, -1, 0, 0, 0, -1},
-};
-#endif
-#if defined (CONFIG_GS_LIS3DH)
-#define LIS3DH_INT_PIN RK30_PIN0_PB7
-
-static int lis3dh_init_platform_hw(void)
-{
-
- return 0;
-}
-
-static struct sensor_platform_data lis3dh_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lis3dh_init_platform_hw,
- .orientation = {-1, 0, 0, 0, -1, 0, 0, 0, 1},
-};
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
-static struct sensor_platform_data akm8975_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-#if defined(CONFIG_GYRO_L3G4200D)
-
-#include <linux/l3g4200d.h>
-#define L3G4200D_INT_PIN RK30_PIN0_PB4
-
-static int l3g4200d_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data l3g4200d_info = {
- .type = SENSOR_TYPE_GYROSCOPE,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
- .init_platform_hw = l3g4200d_init_platform_hw,
- .x_min = 40,//x_min,y_min,z_min = (0-100) according to hardware
- .y_min = 40,
- .z_min = 20,
-};
-
-#endif
-
-#ifdef CONFIG_LS_CM3217
-static struct sensor_platform_data cm3217_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 0,
- .poll_delay_ms = 500,
-};
-
-#endif
-
-#ifdef CONFIG_FB_ROCKCHIP
-
-#define LCD_CS_PIN INVALID_GPIO
-#define LCD_CS_VALUE GPIO_HIGH
-
-#define LCD_EN_PIN RK30_PIN0_PB0
-#define LCD_EN_VALUE GPIO_LOW
-
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
-
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_CS_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_CS_PIN);
- printk(KERN_ERR "request lcd cs pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_CS_PIN, LCD_CS_VALUE);
- }
- }
-
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_EN_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_EN_PIN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_EN_PIN, LCD_EN_VALUE);
- }
- }
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, !LCD_CS_VALUE);
- }
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, !LCD_EN_VALUE);
- }
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE);
- }
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
- }
- return 0;
-}
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
-struct rk29fb_info lcdc0_screen_info = {
- #if defined(CONFIG_RK_HDMI)
- .prop = EXTEND, //extend display device
- .lcd_info = NULL,
- .set_screen_info = hdmi_init_lcdc,
- #endif
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
-struct rk29fb_info lcdc1_screen_info = {
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-#if defined(CONFIG_ARCH_RK3188)
-static struct resource resource_mali[] = {
- [0] = {
- .name = "ump buf",
- .start = 0,
- .end = 0,
- .flags = IORESOURCE_MEM,
- },
-
-};
-
-static struct platform_device device_mali= {
- .name = "mali400_ump",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_mali),
- .resource = resource_mali,
-};
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
-static struct resource resource_lcdc0[] = {
- [0] = {
- .name = "lcdc0 reg",
- .start = RK30_LCDC0_PHYS,
- .end = RK30_LCDC0_PHYS + RK30_LCDC0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc0 irq",
- .start = IRQ_LCDC0,
- .end = IRQ_LCDC0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc0 = {
- .name = "rk30-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc0),
- .resource = resource_lcdc0,
- .dev = {
- .platform_data = &lcdc0_screen_info,
- },
-};
-#endif
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
-static struct resource resource_lcdc1[] = {
- [0] = {
- .name = "lcdc1 reg",
- .start = RK30_LCDC1_PHYS,
- .end = RK30_LCDC1_PHYS + RK30_LCDC1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc1 irq",
- .start = IRQ_LCDC1,
- .end = IRQ_LCDC1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc1 = {
- .name = "rk30-lcdc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resource_lcdc1),
- .resource = resource_lcdc1,
- .dev = {
- .platform_data = &lcdc1_screen_info,
- },
-};
-#endif
-
-#if defined(CONFIG_MFD_RK610)
-#define RK610_RST_PIN RK30_PIN2_PC5
-static int rk610_power_on_init(void)
-{
- int ret;
- if(RK610_RST_PIN != INVALID_GPIO)
- {
- ret = gpio_request(RK610_RST_PIN, "rk610 reset");
- if (ret)
- {
- printk(KERN_ERR "rk610_control_probe request gpio fail\n");
- }
- else
- {
- gpio_direction_output(RK610_RST_PIN, GPIO_HIGH);
- msleep(100);
- gpio_direction_output(RK610_RST_PIN, GPIO_LOW);
- msleep(100);
- gpio_set_value(RK610_RST_PIN, GPIO_HIGH);
- }
- }
-
- return 0;
-
-}
-
-
-static struct rk610_ctl_platform_data rk610_ctl_pdata = {
- .rk610_power_on_init = rk610_power_on_init,
-};
-#endif
-
-#if defined(CONFIG_MFD_RK616)
-#define RK616_RST_PIN RK30_PIN2_PD5
-#define RK616_PWREN_PIN RK30_PIN0_PB0
-#define RK616_SPK_CTL2 RK30_PIN2_PD7
-#define RK616_SCL_RATE (80*1000) //i2c scl rate
-static int rk616_power_on_init(void)
-{
- int ret;
-#if 0
- if(RK616_SPK_CTL2 != INVALID_GPIO)
- {
- ret = gpio_request(RK616_SPK_CTL2, "rk616 spk ctl2");
- if (ret)
- {
- printk(KERN_ERR "rk616 spk_ctl2 gpio request fail\n");
- }
- else
- {
- gpio_direction_output(RK616_SPK_CTL2,GPIO_HIGH);
- }
- }
-#endif
- if(RK616_PWREN_PIN != INVALID_GPIO)
- {
- ret = gpio_request(RK616_PWREN_PIN, "rk616 pwren");
- if (ret)
- {
- printk(KERN_ERR "rk616 pwren gpio request fail\n");
- }
- else
- {
- gpio_direction_output(RK616_PWREN_PIN,GPIO_LOW);
- mdelay(200);
- }
- }
-
- if(RK616_RST_PIN != INVALID_GPIO)
- {
- ret = gpio_request(RK616_RST_PIN, "rk616 reset");
- if (ret)
- {
- printk(KERN_ERR "rk616 reset gpio request fail\n");
- }
- else
- {
- gpio_direction_output(RK616_RST_PIN, GPIO_HIGH);
- mdelay(200);;
- gpio_direction_output(RK616_RST_PIN, GPIO_LOW);
- mdelay(200);
- gpio_set_value(RK616_RST_PIN, GPIO_HIGH);
- }
- }
-
- return 0;
-
-}
-
-
-static struct rk616_platform_data rk616_pdata = {
- .power_init = rk616_power_on_init,
- .scl_rate = RK616_SCL_RATE,
- .lcd0_func = INPUT, //port lcd0 as input
- .lcd1_func = INPUT, //port lcd1 as input
- .lvds_ch_nr = 0, //the number of used lvds channel
- .hdmi_irq = RK30_PIN2_PD4,
- .spk_ctl_gpio = RK30_PIN2_PD7,
-// .hp_ctl_gpio = RK30_PIN2_PD7,
-};
-#endif
-
-#ifdef CONFIG_SND_SOC_RK610
-static int rk610_codec_io_init(void)
-{
-//if need iomux.
-//Must not gpio_request
- return 0;
-}
-
-static struct rk610_codec_platform_data rk610_codec_pdata = {
- .spk_ctl_io = RK30_PIN2_PD7,
- .io_init = rk610_codec_io_init,
-};
-#endif
-
-#ifdef CONFIG_ANDROID_TIMED_GPIO
-static struct timed_gpio timed_gpios[] = {
- {
- .name = "vibrator",
- .gpio = INVALID_GPIO,
- .max_timeout = 1000,
- .active_low = 0,
- .adjust_time =20, //adjust for diff product
- },
-};
-
-static struct timed_gpio_platform_data rk29_vibrator_info = {
- .num_gpios = 1,
- .gpios = timed_gpios,
-};
-
-static struct platform_device rk29_device_vibrator = {
- .name = "timed-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_vibrator_info,
- },
-
-};
-#endif
-
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
-static struct gpio_led rk29_leds[] = {
- {
- .name = "button-backlight",
- .gpio = INVALID_GPIO,
- .default_trigger = "timer",
- .active_low = 0,
- .retain_state_suspended = 0,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- },
-};
-
-static struct gpio_led_platform_data rk29_leds_pdata = {
- .leds = rk29_leds,
- .num_leds = ARRAY_SIZE(rk29_leds),
-};
-
-static struct platform_device rk29_device_gpio_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_leds_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_RK_IRDA
-#define IRDA_IRQ_PIN INVALID_GPIO //RK30_PIN0_PA3
-
-static int irda_iomux_init(void)
-{
- int ret = 0;
-
- //irda irq pin
- ret = gpio_request(IRDA_IRQ_PIN, NULL);
- if (ret != 0) {
- gpio_free(IRDA_IRQ_PIN);
- printk(">>>>>> IRDA_IRQ_PIN gpio_request err \n ");
- }
- gpio_pull_updown(IRDA_IRQ_PIN, PullDisable);
- gpio_direction_input(IRDA_IRQ_PIN);
-
- return 0;
-}
-
-static int irda_iomux_deinit(void)
-{
- gpio_free(IRDA_IRQ_PIN);
- return 0;
-}
-
-static struct irda_info rk29_irda_info = {
- .intr_pin = IRDA_IRQ_PIN,
- .iomux_init = irda_iomux_init,
- .iomux_deinit = irda_iomux_deinit,
- //.irda_pwr_ctl = bu92747guw_power_ctl,
-};
-
-static struct platform_device irda_device = {
-#ifdef CONFIG_RK_IRDA_NET
- .name = "rk_irda",
-#else
- .name = "bu92747_irda",
-#endif
- .id = -1,
- .dev = {
- .platform_data = &rk29_irda_info,
- }
-};
-#endif
-
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and sdio.noted by xbw at 2012-03-05
-**************************************************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "../mach-rk30/board-rk3168-tb-sdmmc-conifg.c"
-#include "../plat-rk/rk-sdmmc-ops.c"
-#include "../plat-rk/rk-sdmmc-wifi.c"
-#endif //endif ---#ifdef CONFIG_SDMMC_RK29
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- iomux_set(MMC0_CMD);
- iomux_set(MMC0_CLKOUT);
- iomux_set(MMC0_D0);
- iomux_set(MMC0_D1);
- iomux_set(MMC0_D2);
- iomux_set(MMC0_D3);
-
- iomux_set_gpio_mode(iomux_mode_to_gpio(MMC0_DETN));
-
- gpio_request(RK30_PIN3_PA7, "sdmmc-power");
- gpio_direction_output(RK30_PIN3_PA7, GPIO_LOW);
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- #if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set_gpio_mode(iomux_gpio_to_mode(RK29SDK_SD_CARD_DETECT_N));
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO);
- #endif
- #else
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(MMC0_DETN);
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FMUX);
- #endif
- #endif
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) && defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- .status = rk29sdk_wifi_mmc0_status,
- .register_status_notify = rk29sdk_wifi_mmc0_status_register,
-#endif
-
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .power_en = RK29SDK_SD_CARD_PWR_EN,
- .power_en_level = RK29SDK_SD_CARD_PWR_EN_LEVEL,
-#else
- .power_en = INVALID_GPIO,
- .power_en_level = GPIO_LOW,
-#endif
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC0_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- .det_pin_info = {
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N, //INVALID_GPIO,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
- #endif
- },
-
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- iomux_set(MMC1_CMD);
- iomux_set(MMC1_CLKOUT);
- iomux_set(MMC1_D0);
- iomux_set(MMC1_D1);
- iomux_set(MMC1_D2);
- iomux_set(MMC1_D3);
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC) || defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC1_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- #if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
- .sdio_INT_gpio = RK29SDK_WIFI_SDIO_CARD_INT,
- #endif
-
- .det_pin_info = {
-#if defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- #else
- .io = INVALID_GPIO,
- #endif
-
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-
- .enable_sd_wakeup = 0,
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-/**************************************************************************************************
- * the end of setting for SDMMC devices
-**************************************************************************************************/
-
-#ifdef CONFIG_BATTERY_RK30_ADC
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = RK30_PIN0_PB2,
- .batt_low_pin = RK30_PIN0_PB1,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = RK30_PIN0_PA6,
- .dc_det_level = GPIO_LOW,
- .charge_ok_level = GPIO_HIGH,
-};
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-#ifdef CONFIG_CW2015_BATTERY
-/*
- note the follow array must set depend on the battery that you use
- you must send the battery to cellwise-semi the contact information:
- name: chen gan; tel:13416876079; E-mail: ben.chen@cellwise-semi.com
- */
-static u8 config_info[SIZE_BATINFO] = {
- 0x15, 0x42, 0x60, 0x59, 0x52,
- 0x58, 0x4D, 0x48, 0x48, 0x44,
- 0x44, 0x46, 0x49, 0x48, 0x32,
- 0x24, 0x20, 0x17, 0x13, 0x0F,
- 0x19, 0x3E, 0x51, 0x45, 0x08,
- 0x76, 0x0B, 0x85, 0x0E, 0x1C,
- 0x2E, 0x3E, 0x4D, 0x52, 0x52,
- 0x57, 0x3D, 0x1B, 0x6A, 0x2D,
- 0x25, 0x43, 0x52, 0x87, 0x8F,
- 0x91, 0x94, 0x52, 0x82, 0x8C,
- 0x92, 0x96, 0xFF, 0x7B, 0xBB,
- 0xCB, 0x2F, 0x7D, 0x72, 0xA5,
- 0xB5, 0xC1, 0x46, 0xAE
-};
-
-static struct cw_bat_platform_data cw_bat_platdata = {
- .dc_det_pin = RK30_PIN0_PB2,
- .bat_low_pin = RK30_PIN0_PB1,
- .chg_ok_pin = RK30_PIN0_PA6,
- .dc_det_level = GPIO_LOW,
- .bat_low_level = GPIO_LOW,
- .chg_ok_level = GPIO_HIGH,
-
- .cw_bat_config_info = config_info,
-
-};
-
-#endif
-#ifdef CONFIG_RK30_PWM_REGULATOR
-static int pwm_voltage_map[] = {
- 800000,825000,850000, 875000,900000, 925000 ,950000, 975000,1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000,1375000
-};
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_cpu",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] =
-{
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
- .pwm_id = 1,
- .pwm_gpio = RK30_PIN3_PD4,
- .pwm_iomux_pwm = PWM1,
- .pwm_iomux_gpio = GPIO3_D4,
- .pwm_voltage = 1100000,
- .suspend_voltage = 1000000,
- .min_uV = 800000,
- .max_uV = 1375000,
- .coefficient = 575, //57.5%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-#endif
-
-#ifdef CONFIG_RK29_VMAC
-#define PHY_PWR_EN_GPIO RK30_PIN1_PD6
-#include "board-rk30-sdk-vmac.c"
-#endif
-
-#ifdef CONFIG_RFKILL_RK
-// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
-static struct rfkill_rk_platform_data rfkill_rk_platdata = {
- .type = RFKILL_TYPE_BLUETOOTH,
-
- .poweron_gpio = { // BT_REG_ON
- .io = INVALID_GPIO, //RK30_PIN3_PC7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_poweron",
- .fgpio = GPIO3_C7,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN3_PC7, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_reset",
- .fgpio = GPIO3_C7,
- },
- },
-
- .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
- .io = RK30_PIN3_PC6, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_wake",
- .fgpio = GPIO3_C6,
- },
- },
-
- .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .gpio = {
- .io = RK30_PIN0_PA5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
- .iomux = {
- .name = NULL,
- },
- },
- },
-
- .rts_gpio = { // UART_RTS, enable or disable BT's data coming
- .io = RK30_PIN1_PA3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_rts",
- .fgpio = GPIO1_A3,
- .fmux = UART0_RTSN,
- },
- },
-};
-
-static struct platform_device device_rfkill_rk = {
- .name = "rfkill_rk",
- .id = -1,
- .dev = {
- .platform_data = &rfkill_rk_platdata,
- },
-};
-#endif
-
-#if defined(CONFIG_GPS_RK)
-int rk_gps_io_init(void)
-{
- printk("%s \n", __FUNCTION__);
-
- gpio_request(RK30_PIN1_PB5, NULL);
- gpio_direction_output(RK30_PIN1_PB5, GPIO_LOW);
-
- iomux_set(GPS_RFCLK);//GPS_CLK
- iomux_set(GPS_MAG);//GPS_MAG
- iomux_set(GPS_SIG);//GPS_SIGN
-
- gpio_request(RK30_PIN1_PA6, NULL);
- gpio_direction_output(RK30_PIN1_PA6, GPIO_LOW);
-
- gpio_request(RK30_PIN1_PA5, NULL);
- gpio_direction_output(RK30_PIN1_PA5, GPIO_LOW);
-
- gpio_request(RK30_PIN1_PA7, NULL);
- gpio_direction_output(RK30_PIN1_PA7, GPIO_LOW);
- return 0;
-}
-int rk_gps_power_up(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_power_down(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_reset_set(int level)
-{
- return 0;
-}
-int rk_enable_hclk_gps(void)
-{
- struct clk *gps_aclk = NULL;
- gps_aclk = clk_get(NULL, "aclk_gps");
- if(gps_aclk) {
- clk_enable(gps_aclk);
- clk_put(gps_aclk);
- printk("%s \n", __FUNCTION__);
- }
- else
- printk("get gps aclk fail\n");
- return 0;
-}
-int rk_disable_hclk_gps(void)
-{
- struct clk *gps_aclk = NULL;
- gps_aclk = clk_get(NULL, "aclk_gps");
- if(gps_aclk) {
- //TO wait long enough until GPS ISR is finished.
- msleep(5);
- clk_disable(gps_aclk);
- clk_put(gps_aclk);
- printk("%s \n", __FUNCTION__);
- }
- else
- printk("get gps aclk fail\n");
- return 0;
-}
-struct rk_gps_data rk_gps_info = {
- .io_init = rk_gps_io_init,
- .power_up = rk_gps_power_up,
- .power_down = rk_gps_power_down,
- .reset = rk_gps_reset_set,
- .enable_hclk_gps = rk_enable_hclk_gps,
- .disable_hclk_gps = rk_disable_hclk_gps,
- .GpsSign = RK30_PIN1_PB3,
- .GpsMag = RK30_PIN1_PB2, //GPIO index
- .GpsClk = RK30_PIN1_PB4, //GPIO index
- .GpsVCCEn = RK30_PIN1_PB5, //GPIO index
- .GpsSpi_CSO = RK30_PIN1_PA4, //GPIO index
- .GpsSpiClk = RK30_PIN1_PA5, //GPIO index
- .GpsSpiMOSI = RK30_PIN1_PA7, //GPIO index
- .GpsIrq = IRQ_GPS,
- .GpsSpiEn = 0,
- .GpsAdcCh = 2,
- .u32GpsPhyAddr = RK30_GPS_PHYS,
- .u32GpsPhySize = RK30_GPS_SIZE,
-};
-
-struct platform_device rk_device_gps = {
- .name = "gps_hv5820b",
- .id = -1,
- .dev = {
- .platform_data = &rk_gps_info,
- }
- };
-#endif
-
-#if defined(CONFIG_MT5931_MT6622)
-static struct mt6622_platform_data mt6622_platdata = {
- .power_gpio = { // BT_REG_ON
- .io = RK30_PIN3_PD5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN0_PD7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .irq_gpio = {
- .io = RK30_PIN3_PD2,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- }
-};
-
-static struct platform_device device_mt6622 = {
- .name = "mt6622",
- .id = -1,
- .dev = {
- .platform_data = &mt6622_platdata,
- },
-};
-#endif
-
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_ANDROID_TIMED_GPIO
- &rk29_device_vibrator,
-#endif
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
- &rk29_device_gpio_leds,
-#endif
-#ifdef CONFIG_RK_IRDA
- &irda_device,
-#endif
-#if defined(CONFIG_WIFI_CONTROL_FUNC)||defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- &rk29sdk_wifi_device,
-#endif
-
-#if defined(CONFIG_MT6620)
- &mt3326_device_gps,
-#endif
-
-#ifdef CONFIG_RK29_SUPPORT_MODEM
- &rk30_device_modem,
-#endif
-#if defined(CONFIG_MU509)
- &rk29_device_mu509,
-#endif
-#if defined(CONFIG_MW100)
- &rk29_device_mw100,
-#endif
-#if defined(CONFIG_MT6229)
- &rk29_device_mt6229,
-#endif
-#ifdef CONFIG_BATTERY_RK30_ADC
- &rk30_device_adc_battery,
-#endif
-#ifdef CONFIG_RFKILL_RK
- &device_rfkill_rk,
-#endif
-#ifdef CONFIG_GPS_RK
- &rk_device_gps,
-#endif
-#if defined(CONFIG_ARCH_RK3188)
- &device_mali,
-#endif
-#ifdef CONFIG_MT5931_MT6622
- &device_mt6622,
-#endif
-};
-
-static int rk_platform_add_display_devices(void)
-{
- struct platform_device *fb = NULL; //fb
- struct platform_device *lcdc0 = NULL; //lcdc0
- struct platform_device *lcdc1 = NULL; //lcdc1
- struct platform_device *bl = NULL; //backlight
-#ifdef CONFIG_FB_ROCKCHIP
- fb = &device_fb;
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
- lcdc0 = &device_lcdc0,
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
- lcdc1 = &device_lcdc1,
-#endif
-
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- bl = &rk29_device_backlight,
-#endif
- __rk_platform_add_display_devices(fb,lcdc0,lcdc1,bl);
-
- return 0;
-
-}
-
-// i2c
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1d,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_GS_LIS3DH)
- {
- .type = "gs_lis3dh",
- .addr = 0x19, //0x19(SA0-->VCC), 0x18(SA0-->GND)
- .flags = 0,
- .irq = LIS3DH_INT_PIN,
- .platform_data = &lis3dh_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8975_info,
- },
-#endif
-#if defined (CONFIG_GYRO_L3G4200D)
- {
- .type = "l3g4200d_gryo",
- .addr = 0x69,
- .flags = 0,
- .irq = L3G4200D_INT_PIN,
- .platform_data = &l3g4200d_info,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RT5631)
- {
- .type = "rt5631",
- .addr = 0x1a,
- .flags = 0,
- },
-#endif
-
-#if defined (CONFIG_SND_SOC_RT5640)
- {
- .type = "rt5640",
- .addr = 0x1c,
- .flags = 0,
- },
-#endif
-
-#ifdef CONFIG_MFD_RK610
- {
- .type = "rk610_ctl",
- .addr = 0x40,
- .flags = 0,
- .platform_data = &rk610_ctl_pdata,
- },
-#ifdef CONFIG_RK610_TVOUT
- {
- .type = "rk610_tvout",
- .addr = 0x42,
- .flags = 0,
- },
-#endif
-#ifdef CONFIG_HDMI_RK610
- {
- .type = "rk610_hdmi",
- .addr = 0x46,
- .flags = 0,
- .irq = INVALID_GPIO,
- },
-#endif
-#ifdef CONFIG_SND_SOC_RK610
- {//RK610_CODEC addr from 0x60 to 0x80 (0x60~0x80)
- .type = "rk610_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- .platform_data = &rk610_codec_pdata,
- },
-#endif
-#endif
-
-};
-#endif
-
-int __sramdata g_pmic_type = 0;
-#ifdef CONFIG_I2C1_RK30
-#ifdef CONFIG_MFD_WM831X_I2C
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info wm8326_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "dcdc3", //ddr
- .min_uv = 1150000,
- .max_uv = 1150000,
- .suspend_vol = 1150000,
- },
- #ifdef CONFIG_MACH_RK3066_SDK
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3000000,
- },
- #else
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3000000,
- .max_uv = 3000000,
- .suspend_vol = 2800000,
- },
- #endif
-};
-
-static struct pmu_info wm8326_ldo_info[] = {
- {
- .name = "ldo1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo2", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo3", //
- .min_uv = 1100000,
- .max_uv = 1100000,
- .suspend_vol = 1100000,
- },
- {
- .name = "ldo4", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 1000000,
- },
- {
- .name = "ldo5", //vcc25
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo6", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo7", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- .suspend_vol = 2800000,
- },
- {
- .name = "ldo8", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo9", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo10", //flash_io
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
-};
-
-#include "../mach-rk30/board-pmu-wm8326.c"
-#endif
-
-#ifdef CONFIG_MFD_TPS65910
-#define TPS65910_HOST_IRQ RK30_PIN0_PB3
-
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info tps65910_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1100000,
- .max_uv = 1100000,
- },
- {
- .name = "vdd2", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vio", //vcc_io
- .min_uv = 2500000,
- .max_uv = 2500000,
- },
-
-};
-static struct pmu_info tps65910_ldo_info[] = {
- {
- .name = "vpll", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "vdig2", //vdd_jetta
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vaux1", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "vaux2", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vaux33", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vmmc", //vcc30
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
- {
- .name = "vdac", //vcc18
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- };
-
-#include "../mach-rk30/board-pmu-tps65910.c"
-#endif
-
-#ifdef CONFIG_REGULATOR_ACT8846
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-#define PMU_VSEL RK30_PIN3_PD3
-static struct pmu_info act8846_dcdc_info[] = {
- {
- .name = "act_dcdc1", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- .suspend_vol = 1200000,
- },
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 1200000,
- #else
- .suspend_vol = 900000,
- #endif
-
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 1200000,
- #else
- .suspend_vol = 900000,
- #endif
-
- },
- {
- .name = "act_dcdc4", //vccio
- .min_uv = 3000000,
- .max_uv = 3000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 3000000,
- #else
- .suspend_vol = 2800000,
- #endif
-
- },
-
-};
-static struct pmu_info act8846_ldo_info[] = {
- {
- .name = "act_ldo1", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "act_ldo2", //vdd12
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "act_ldo3", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo4", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo5", //vcctp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo6", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo7", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo8", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- };
-
-#include "../mach-rk30/board-pmu-act8846.c"
-#endif
-
-#ifdef CONFIG_MFD_RK808
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-#define RK808_HOST_IRQ RK30_PIN0_PB3
-
-static struct pmu_info rk808_dcdc_info[] = {
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 900000,
- },
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 900000,
- },
- {
- .name = "rk_dcdc3", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- .suspend_vol = 1200000,
- },
- {
- .name = "rk_dcdc4", //vccio
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3000000,
- },
-
-};
-static struct pmu_info rk808_ldo_info[] = {
- {
- .name = "rk_ldo1", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "rk_ldo2", //vcctp
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
-
- },
- {
- .name = "rk_ldo3", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 1000000,
- },
- {
- .name = "rk_ldo4", //vcc18
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "rk_ldo5", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- .suspend_vol = 2800000,
- },
- {
- .name = "rk_ldo6", //vdd12
- .min_uv = 1200000,
- .max_uv = 1200000,
- .suspend_vol = 1200000,
- },
- {
- .name = "rk_ldo7", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "rk_ldo8", //vcca_33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- };
-
-#include "board-pmu-rk808.c"
-#endif
-
-#ifdef CONFIG_MFD_RICOH619
-#include <linux/mfd/ricoh619.h>
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-#define RICOH619_HOST_IRQ RK30_PIN0_PB3
-
-static struct pmu_info ricoh619_dcdc_info[] = {
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 900000,
- },
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 900000,
- },
-
- {
- .name = "ricoh_dc3", //vcc18
- .min_uv = 2000000,
- .max_uv = 2000000,
- .suspend_vol = 2000000,
- },
-
- {
- .name = "ricoh_dc4", //vccio
- .min_uv = 3100000,
- .max_uv = 3100000,
- .suspend_vol = 3000000,
- },
-
- {
- .name = "ricoh_dc5", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- .suspend_vol = 1200000,
- },
-
-};
-static struct pmu_info ricoh619_ldo_info[] = {
- {
- .name = "ricoh_ldo1", //vcc30
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
- {
- .name = "ricoh_ldo2", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "ricoh_ldo3", //vcctp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "ricoh_ldo4", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "ricoh_ldo5", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "ricoh_ldo6", //vdd12
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "ricoh_ldo7", //vccio_18
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "ricoh_ldo8", //vcca_25
- .min_uv = 2500000,
- .max_uv = 2500000,
- },
- {
- .name = "ricoh_ldo9", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "ricoh_ldo10", //vcca18
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
-
- };
-
-#include "../mach-rk30/board-pmu-ricoh619.c"
-#endif
-
-
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_MFD_WM831X_I2C)
- {
- .type = "wm8326",
- .addr = 0x34,
- .flags = 0,
- .irq = RK30_PIN0_PB3,
- .platform_data = &wm831x_platdata,
- },
-#endif
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-
-#if defined (CONFIG_REGULATOR_ACT8846)
- {
- .type = "act8846",
- .addr = 0x5a,
- .flags = 0,
- // .irq = ACT8846_HOST_IRQ,
- .platform_data=&act8846_data,
- },
-#endif
-#if defined (CONFIG_MFD_RK808)
- {
- .type = "rk808",
- .addr = 0x1b,
- .flags = 0,
- // .irq = ACT8846_HOST_IRQ,
- .platform_data=&rk808_data,
- },
-#endif
-
-#if defined (CONFIG_RTC_HYM8563)
- {
- .type = "rtc_hym8563",
- .addr = 0x51,
- .flags = 0,
- .irq = RK30_PIN1_PA4,
- },
-#if defined (CONFIG_CW2015_BATTERY)
- {
- .type = "cw201x",
- .addr = 0x62,
- .flags = 0,
- .platform_data = &cw_bat_platdata,
- },
-#endif
-#endif
-#if defined (CONFIG_MFD_RICOH619)
- {
- .type = "ricoh619",
- .addr = 0x32,
- .flags = 0,
- .irq = RICOH619_HOST_IRQ,
- .platform_data=&ricoh619_data,
- },
-#endif
-
-};
-#endif
-
-void __sramfunc board_pmu_suspend(void)
-{
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_suspend();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_suspend();
- #endif
- #if defined (CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- board_pmu_act8846_suspend();
- #endif
- #if defined (CONFIG_MFD_RK808)
- if(pmic_is_rk808())
- board_pmu_rk808_suspend();
- #endif
- #if defined (CONFIG_MFD_RICOH619)
- if(pmic_is_ricoh619())
- board_pmu_ricoh619_suspend();
- #endif
-}
-
-void __sramfunc board_pmu_resume(void)
-{
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_resume();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_resume();
- #endif
- #if defined (CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- board_pmu_act8846_resume();
- #endif
- #if defined (CONFIG_MFD_RK808)
- if(pmic_is_rk808())
- board_pmu_rk808_resume();
- #endif
- #if defined (CONFIG_MFD_RICOH619)
- if(pmic_is_ricoh619())
- board_pmu_ricoh619_resume();
- #endif
-}
-
- int __sramdata gpio3d6_iomux,gpio3d6_do,gpio3d6_dir,gpio3d6_en;
-
-#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
-
-void __sramfunc rk30_pwm_logic_suspend_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
-
-// int gpio0d7_iomux,gpio0d7_do,gpio0d7_dir,gpio0d7_en;
- sram_udelay(10000);
- gpio3d6_iomux = grf_readl(GRF_GPIO3D_IOMUX);
- gpio3d6_do = grf_readl(GRF_GPIO3H_DO);
- gpio3d6_dir = grf_readl(GRF_GPIO3H_DIR);
- gpio3d6_en = grf_readl(GRF_GPIO3H_EN);
-
- grf_writel((1<<28), GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DIR);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DO);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_EN);
-#endif
-}
-void __sramfunc rk30_pwm_logic_resume_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- grf_writel((1<<28)|gpio3d6_iomux, GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|gpio3d6_en, GRF_GPIO3H_EN);
- grf_writel((1<<30)|gpio3d6_dir, GRF_GPIO3H_DIR);
- grf_writel((1<<30)|gpio3d6_do, GRF_GPIO3H_DO);
- sram_udelay(10000);
-
-#endif
-
-}
-extern void pwm_suspend_voltage(void);
-extern void pwm_resume_voltage(void);
-void rk30_pwm_suspend_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_suspend_voltage();
-#endif
-}
-void rk30_pwm_resume_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_resume_voltage();
-#endif
-}
-
-
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-#if defined (CONFIG_TOUCHSCREEN_GT8XX)
- {
- .type = "Goodix-TS",
- .addr = 0x55,
- .flags = 0,
- .irq = RK30_PIN1_PB7,
- .platform_data = &goodix_info,
- },
-#endif
-#if defined (CONFIG_LS_CM3217)
- {
- .type = "lightsensor",
- .addr = 0x10,
- .flags = 0,
- .platform_data = &cm3217_info,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C4_RK30
-static struct i2c_board_info __initdata i2c4_info[] = {
-#if defined (CONFIG_MFD_RK616)
- {
- .type = "rk616",
- .addr = 0x50,
- .flags = 0,
- .platform_data = &rk616_pdata,
- },
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO// RK30_PIN2_PD6 //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO//RK30_PIN2_PD7 //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- //set iomux (gpio) here
- //rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME, GPIO2D_GPIO2D7);
- //rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME, GPIO2D_GPIO2D6);
-
- return 0;
-}
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C4_RK30
- i2c_register_board_info(4, i2c4_info, ARRAY_SIZE(i2c4_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(5, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-
-// ========== Begin of rk3168 top board keypad defination ============
-
-#include <plat/key.h>
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .adc_value = 1,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-#if 0
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK30_PIN0_PA4,
- .active_low = PRESS_LEV_LOW,
- .wakeup = 1,
- },
-#endif
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .adc_value = 200,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-#if 0
- {
- .desc = "menu",
- .code = EV_MENU,
- .adc_value = 133,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .adc_value = 550,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .adc_value = 333,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "camera",
- .code = KEY_CAMERA,
- .adc_value = 742,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-#endif
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = 1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
-// =========== End of rk3168 top board keypad defination =============
-
-
-#define POWER_ON_PIN RK30_PIN0_PA0 //power_hold
-static void rk30_pm_power_off(void)
-{
- printk(KERN_ERR "rk30_pm_power_off start...\n");
- #if defined(CONFIG_MFD_WM831X)
- if(pmic_is_wm8326()){
- wm831x_set_bits(Wm831x,WM831X_GPIO_LEVEL,0x0001,0x0000); //set sys_pwr 0
- wm831x_device_shutdown(Wm831x);//wm8326 shutdown
- }
- #endif
-
- #if defined(CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- {
- act8846_device_shutdown();
- }
- #endif
-
- #if defined(CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- {
- tps65910_device_shutdown();//tps65910 shutdown
- }
- #endif
-
- #if defined(CONFIG_MFD_RK808)
- if(pmic_is_rk808())
- {
- rk808_device_shutdown();//rk808 shutdown
- }
- #endif
- #if defined(CONFIG_MFD_RICOH619)
- if(pmic_is_ricoh619()){
- ricoh619_power_off(); //ricoh619 shutdown
- }
- #endif
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
- while (1);
-}
-
-static void __init machine_rk30_board_init(void)
-{
- //avs_init();
- gpio_request(POWER_ON_PIN, "poweronpin");
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
- pm_power_off = rk30_pm_power_off;
-
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
-
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- rk_platform_add_display_devices();
- board_usb_detect_init(RK30_PIN0_PA7);
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC)
- rk29sdk_wifi_bt_gpio_control_init();
-#elif defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- rk29sdk_wifi_combo_module_gpio_init();
-#endif
-
-#if defined(CONFIG_MT6620)
- clk_set_rate(clk_get_sys("rk_serial.0", "uart"), 48*1000000);
-#endif
-
-#if defined(CONFIG_MT5931_MT6622)
- clk_set_rate(clk_get_sys("rk_serial.0", "uart"), 24*1000000);
-#endif
-}
-#define HD_SCREEN_SIZE 1920UL*1200UL*4*3
-static void __init rk30_reserve(void)
-{
-#if defined(CONFIG_ARCH_RK3188)
- /*if lcd resolution great than or equal to 1920*1200,reserve the ump memory */
- if(!(get_fb_size() < ALIGN(HD_SCREEN_SIZE,SZ_1M)))
- {
- int ump_mem_phy_size=512UL*1024UL*1024UL;
- resource_mali[0].start = board_mem_reserve_add("ump buf", ump_mem_phy_size);
- resource_mali[0].end = resource_mali[0].start + ump_mem_phy_size -1;
- }
-#endif
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0 buf", get_fb_size());
- resource_fb[0].end = resource_fb[0].start + get_fb_size()- 1;
-#if 0
- resource_fb[1].start = board_mem_reserve_add("ipp buf", RK30_FB0_MEM_SIZE);
- resource_fb[1].end = resource_fb[1].start + RK30_FB0_MEM_SIZE - 1;
-#endif
-
-#if defined(CONFIG_FB_ROTATE) || !defined(CONFIG_THREE_FB_BUFFER)
- resource_fb[2].start = board_mem_reserve_add("fb2 buf",get_fb_size());
- resource_fb[2].end = resource_fb[2].start + get_fb_size() - 1;
-#endif
-#endif
-
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
-
-#ifdef CONFIG_GPS_RK
- //it must be more than 8MB
- rk_gps_info.u32MemoryPhyAddr = board_mem_reserve_add("gps", SZ_8M);
-#endif
- board_mem_reserved();
-}
-/******************************** arm dvfs frequency volt table **********************************/
-/**
- * dvfs_cpu_logic_table: table for arm and logic dvfs
- * @frequency : arm frequency
- * @cpu_volt : arm voltage depend on frequency
- */
-
-#if defined(CONFIG_ARCH_RK3188)
-//sdk
-static struct cpufreq_frequency_table dvfs_arm_table_volt_level0[] = {
- {.frequency = 312 * 1000, .index = 850 * 1000},
- {.frequency = 504 * 1000, .index = 900 * 1000},
- {.frequency = 816 * 1000, .index = 950 * 1000},
- {.frequency = 1008 * 1000, .index = 1025 * 1000},
- {.frequency = 1200 * 1000, .index = 1100 * 1000},
- {.frequency = 1416 * 1000, .index = 1200 * 1000},
- {.frequency = 1608 * 1000, .index = 1300 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-//default
-static struct cpufreq_frequency_table dvfs_arm_table_volt_level1[] = {
- {.frequency = 312 * 1000, .index = 875 * 1000},
- {.frequency = 504 * 1000, .index = 925 * 1000},
- {.frequency = 816 * 1000, .index = 975 * 1000},
- {.frequency = 1008 * 1000, .index = 1075 * 1000},
- {.frequency = 1200 * 1000, .index = 1150 * 1000},
- {.frequency = 1416 * 1000, .index = 1250 * 1000},
- {.frequency = 1608 * 1000, .index = 1350 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-// cube 10'
-static struct cpufreq_frequency_table dvfs_arm_table_volt_level2[] = {
- {.frequency = 312 * 1000, .index = 900 * 1000},
- {.frequency = 504 * 1000, .index = 925 * 1000},
- {.frequency = 816 * 1000, .index = 1000 * 1000},
- {.frequency = 1008 * 1000, .index = 1075 * 1000},
- {.frequency = 1200 * 1000, .index = 1200 * 1000},
- {.frequency = 1416 * 1000, .index = 1250 * 1000},
- {.frequency = 1608 * 1000, .index = 1350 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-/******************************** gpu dvfs frequency volt table **********************************/
-//sdk
-static struct cpufreq_frequency_table dvfs_gpu_table_volt_level0[] = {
- {.frequency = 133 * 1000, .index = 975 * 1000},//the mininum rate is limited 133M for rk3188
- {.frequency = 200 * 1000, .index = 975 * 1000},
- {.frequency = 266 * 1000, .index = 1000 * 1000},
- {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1100 * 1000},
- {.frequency = 600 * 1000, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-//cube 10'
-static struct cpufreq_frequency_table dvfs_gpu_table_volt_level1[] = {
- {.frequency = 133 * 1000, .index = 975 * 1000},//the mininum rate is limited 133M for rk3188
- {.frequency = 200 * 1000, .index = 1000 * 1000},
- {.frequency = 266 * 1000, .index = 1025 * 1000},
- {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1100 * 1000},
- {.frequency = 600 * 1000, .index = 1250 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-/******************************** ddr dvfs frequency volt table **********************************/
-static struct cpufreq_frequency_table dvfs_ddr_table_volt_level0[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 950 * 1000},
- {.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = 1000 * 1000},
- {.frequency = 396 * 1000 + DDR_FREQ_NORMAL, .index = 1100 * 1000},
- //{.frequency = 528 * 1000 + DDR_FREQ_NORMAL, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-//if you board is good for volt quality,select dvfs_arm_table_volt_level0
-#define dvfs_arm_table dvfs_arm_table_volt_level0
-#define dvfs_gpu_table dvfs_gpu_table_volt_level1
-#define dvfs_ddr_table dvfs_ddr_table_volt_level0
-
-#else
-//for RK3168 && RK3066B
-#if 0
-static struct cpufreq_frequency_table dvfs_arm_table[] = {
- {.frequency = 312 * 1000, .index = 950 * 1000},
- {.frequency = 504 * 1000, .index = 1000 * 1000},
- {.frequency = 816 * 1000, .index = 1050 * 1000},
- {.frequency = 1008 * 1000, .index = 1125 * 1000},
- {.frequency = 1200 * 1000, .index = 1200 * 1000},
- //{.frequency = 1416 * 1000, .index = 1250 * 1000},
- //{.frequency = 1608 * 1000, .index = 1300 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- {.frequency = 100 * 1000, .index = 1000 * 1000},
- {.frequency = 200 * 1000, .index = 1000 * 1000},
- {.frequency = 266 * 1000, .index = 1050 * 1000},
- //{.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1125 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 1000 * 1000},
- {.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = 1050 * 1000},
- {.frequency = 400 * 1000 + DDR_FREQ_NORMAL, .index = 1100 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-#else
-static struct cpufreq_frequency_table dvfs_arm_table[] = {
- {.frequency = 312 * 1000, .index = 1025 * 1000},
- {.frequency = 504 * 1000, .index = 1025 * 1000},
- {.frequency = 816 * 1000, .index = 1050 * 1000},
- {.frequency = 1008 * 1000, .index = 1125 * 1000},
- {.frequency = 1200 * 1000, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- {.frequency = 100 * 1000, .index = 1000 * 1000},
- {.frequency = 200 * 1000, .index = 1000 * 1000},
- {.frequency = 266 * 1000, .index = 1050 * 1000},
-// {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1125 * 1000},
- {.frequency = 600 * 1000, .index = 1250 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 1000 * 1000},
- {.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = 1075 * 1000},
- {.frequency = 456 * 1000 + DDR_FREQ_NORMAL, .index = 1150 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-#endif
-#endif
-/******************************** arm dvfs frequency volt table end **********************************/
-//#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
-//static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
-//static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
-
-void __init board_clock_init(void)
-{
- rk30_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
- //dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "cpu"), dvfs_arm_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
-}
-
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk30_fixup,
- .reserve = &rk30_reserve,
- .map_io = rk30_map_io,
- .init_irq = rk30_init_irq,
- .timer = &rk30_timer,
- .init_machine = machine_rk30_board_init,
-MACHINE_END
+++ /dev/null
-/*****************************************************************************************
- * arch/arm/mach-rkxx/baord-xxx-sdmmc-config.c
- *
- * Copyright (C) 2013 ROCKCHIP, Inc.
- *
- * Description:
- * define the gpio for SD-MMC-SDIO-Wifi functions according to your own projects.
- *
- * Author: Michael Xie
- * 15 Jan,2013
- * E-mail: xbw@rock-chips.com
- *
- ******************************************************************************************/
-
-/*
-** If you select the macro of CONFIG_SDMMC0_RK29_WRITE_PROTECT, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define SDMMC0_WRITE_PROTECT_PIN RK30_PIN3_PB2 //According to your own project to set the value of write-protect-pin.
-//#define SDMMC0_WRITE_PROTECT_ENABLE_VALUE GPIO_HIGH
-
-/*
-** If you select the macro of CONFIG_SDMMC1_RK29_WRITE_PROTECT, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define SDMMC1_WRITE_PROTECT_PIN RK30_PIN3_PB3 //According to your own project to set the value of write-protect-pin.
-//#define SDMMC1_WRITE_PROTECT_ENABLE_VALUE GPIO_HIGH
-
-/*
-** If you select the macro of CONFIG_RK29_SDIO_IRQ_FROM_GPIO, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define RK29SDK_WIFI_SDIO_CARD_INT RK30_PIN3_PD2
-
-
-/*
-* define sdcard PowerEn-pin
-*/
-#define RK29SDK_SD_CARD_PWR_EN RK30_PIN3_PA1
-#define RK29SDK_SD_CARD_PWR_EN_LEVEL GPIO_LOW
-int rk31sdk_get_sdmmc0_pin_io_voltage(void)
-{
- int voltage;
-#define RK31SDK_SET_SDMMC0_PIN_VOLTAGE
-
- /**************************************************************************************
- ** Please tell me how much voltage of your SDMMC0-pin in your project.
- **
- ** ÀýÈç: ÓеÄÏîÄ¿£¬ËüµÄSDMMC0ËùÔÚµÄRKÖ÷¿ØµÄIO×飬ÏëÓÃ1.8V, ¶ø¿¨±¾ÉíÓÃ3.3V,
- ** ¶øÖмäͨ¹ý¸öµçƽת»».ÄÇô£¬Äú´Ëʱ£¬Ó¦¸ÃÉèÖÃÏÂÃæµÄvoltageֵΪ 1.8V(¼´1800mv)
- ***************************************************************************************/
- voltage = 3300; //default the voltage 3300mv.
-
- return voltage;
-}
-
-/*
-* define the card-detect-pin.
-*/
-#define RK29SDK_SD_CARD_DETECT_N RK30_PIN3_PB0 //According to your own project to set the value of card-detect-pin.
-#define RK29SDK_SD_CARD_INSERT_LEVEL GPIO_LOW // set the voltage of insert-card. Please pay attention to the default setting.
-
-//wake up host gpio
-#define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
-#define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
-
-/*
-* Define wifi module's power and reset gpio, and gpio sensitive level.
-* Please set the value according to your own project.
-*
-* Well, you just own engineering module to set the value in the corresponding module branch.
-* Otherwise, you do not define this macro, eliminate it.
-*
-*/
-#if defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU)
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_LOW//GPIO_HIGH
-
-#elif defined(CONFIG_BCM4330) || defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319) || defined(CONFIG_RK903) || defined(CONFIG_RK901)
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN2_PA7
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
-
-#elif defined(CONFIG_MT5931_MT6622) || defined(CONFIG_MT5931)
-
- #ifdef CONFIG_MACH_RK3168_LR097
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- //#define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- //#define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
-
- #else
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN0_PA5
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #endif
-
-#elif defined(CONFIG_MT6620)
- #define COMBO_MODULE_MT6620_CDT 1 // to control antsel2,antsel3 and gps_lan foot when using AcSip or Cdtech chip.
- //- 1--use Cdtech chip; 0--unuse CDT chip
-
- //power, PMU_EN
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PC7
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- //reset, DAIRST,SYSRST_B
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- //VDDIO
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL RK30_PIN0_PD2 //You do not get control of the foot, and you do not need to define the macro
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_ENABLE_VALUE GPIO_HIGH
- //WIFI_INT_B
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
- //BGF_INT_B
- #define RK30SDK_WIFI_GPIO_BGF_INT_B RK30_PIN6_PA7
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_ENABLE_VALUE GPIO_HIGH
- //GPS_SYNC
- #define RK30SDK_WIFI_GPIO_GPS_SYNC RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_ENABLE_VALUE GPIO_HIGH
-
- #if COMBO_MODULE_MT6620_CDT
- //ANTSEL2
- #define RK30SDK_WIFI_GPIO_ANTSEL2 RK30_PIN4_PD4
- #define RK30SDK_WIFI_GPIO_ANTSEL2_ENABLE_VALUE GPIO_LOW //use 6620 in CDT chip, LOW--work; High--no work.
- //ANTSEL3
- #define RK30SDK_WIFI_GPIO_ANTSEL3 RK30_PIN4_PD3
- #define RK30SDK_WIFI_GPIO_ANTSEL3_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- //GPS_LAN
- #define RK30SDK_WIFI_GPIO_GPS_LAN RK30_PIN4_PD6
- #define RK30SDK_WIFI_GPIO_GPS_LAN_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- #endif // #if COMBO_MODULE_MT6620_CDT--#endif
-#endif
-
-#ifndef RK30SDK_WIFI_GPIO_WIFI_INT_B
-#define RK30SDK_WIFI_GPIO_WIFI_INT_B INVALID_GPIO
-#define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
-#endif
-
-int rk31sdk_get_sdio_wifi_voltage(void)
-{
- int voltage;
-
- /******************************************************************************
- ** Please tell me how much wifi-module uses voltage in your project.
- ******************************************************************************/
-#if defined(CONFIG_BCM4330) || defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319) || defined(CONFIG_RK903) || defined(CONFIG_RK901)
- voltage = 1800 ; //power 1800mV
-
-#elif defined(CONFIG_MT5931_MT6622)||defined(CONFIG_MT5931)
- voltage = 1800 ; //power 1800V
-#elif defined(CONFIG_MT6620)
- voltage = 2800 ; //power 2800V
-#elif defined(CONFIG_RDA5990)||defined(CONFIG_RTL8723AS)
- voltage = 3300 ; //power 3300V
-#else
- //default, sdio use 3.0V
- voltage = 3000 ; //power 3000V
-#endif
-
- return voltage;
-}
-
-
-
+++ /dev/null
-/*
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <mach/dvfs.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <linux/rk_fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/mfd/tps65910.h>
-#include <linux/regulator/act8846.h>
-#include <linux/mfd/rk808.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-
-#ifdef CONFIG_CW2015_BATTERY
-#include <linux/power/cw2015_battery.h>
-#endif
-#if defined(CONFIG_MFD_RK610)
-#include <linux/mfd/rk610_core.h>
-#endif
-
-#if defined(CONFIG_MFD_RK616)
-#include <linux/mfd/rk616.h>
-#endif
-
-
-#if defined(CONFIG_RK_HDMI)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-#if defined(CONFIG_GPS_RK)
-#include "../../../drivers/misc/gps/rk_gps/rk_gps.h"
-#endif
-#if defined(CONFIG_MU509)
-#include <linux/mu509.h>
-#endif
-#if defined(CONFIG_MW100)
-#include <linux/mw100.h>
-#endif
-#if defined(CONFIG_MT6229)
-#include <linux/mt6229.h>
-#endif
-#if defined(CONFIG_ANDROID_TIMED_GPIO)
-#include "../../../drivers/staging/android/timed_gpio.h"
-#endif
-
-#if defined(CONFIG_MT6620)
-#include <linux/gps.h>
-#endif
-#include "../mach-rk30/board-rk3168-tb-camera.c"
-
-#if defined(CONFIG_TOUCHSCREEN_GT8XX)
-#define TOUCH_RESET_PIN RK30_PIN0_PB6
-#define TOUCH_PWR_PIN RK30_PIN0_PC5 // need to fly line by hardware engineer
-
-/* Android Parameter */
-static int ap_mdm = 0;
-module_param(ap_mdm, int, 0644);
-static int ap_has_alsa = 0;
-module_param(ap_has_alsa, int, 0644);
-static int ap_data_only = 2;
-module_param(ap_data_only, int, 0644);
-static int ap_has_earphone = 0;
-module_param(ap_has_earphone, int, 0644);
-
-
-static int goodix_init_platform_hw(void)
-{
- int ret;
-
- if (TOUCH_PWR_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_PWR_PIN, "goodix power pin");
- if (ret != 0) {
- gpio_free(TOUCH_PWR_PIN);
- printk("goodix power error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_PWR_PIN, 0);
- gpio_set_value(TOUCH_PWR_PIN, GPIO_LOW);
- msleep(100);
- }
-
- if (TOUCH_RESET_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_RESET_PIN, "goodix reset pin");
- if (ret != 0) {
- gpio_free(TOUCH_RESET_PIN);
- printk("goodix gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, 1);
- msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_LOW);
- //msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_HIGH);
- //msleep(500);
- }
- return 0;
-}
-
-struct goodix_platform_data goodix_info = {
- .model = 8105,
- .irq_pin = RK30_PIN1_PB7,
- .rest_pin = TOUCH_RESET_PIN,
- .init_platform_hw = goodix_init_platform_hw,
-};
-#endif
-
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-#define PWM_ID 3
-#define PWM_MODE PWM3
-#define PWM_EFFECT_VALUE 1
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-#define BL_EN_PIN RK30_PIN0_PA2
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
-
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
- ret = gpio_request(BL_EN_PIN, "bl_en");
- if (ret == 0) {
- gpio_direction_output(BL_EN_PIN, BL_EN_VALUE);
- }
-#endif
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0, pwm_gpio;
-#ifdef LCD_DISP_ON_PIN
- gpio_free(BL_EN_PIN);
-#endif
- pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
- gpio_request(pwm_gpio, "bl_pwm");
- gpio_direction_output(pwm_gpio, GPIO_LOW);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret, pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
-
- ret = gpio_request(pwm_gpio, "bl_pwm");
- if (ret) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return ret;
- }
- gpio_direction_output(pwm_gpio, GPIO_LOW);
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, !BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- int pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
-
- gpio_free(pwm_gpio);
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .min_brightness=60,
- .max_brightness=220,
- //.pre_div = 30 * 1000, // pwm output clk: 30k;
- .brightness_mode = BRIGHTNESS_MODE_CONIC,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-#endif
-
-#ifdef CONFIG_RK29_SUPPORT_MODEM
-
-#define RK30_MODEM_POWER RK30_PIN0_PC6
-#define RK30_MODEM_POWER_IOMUX iomux_set(GPIO0_C6)
-
-static int rk30_modem_io_init(void)
-{
- printk("%s\n", __FUNCTION__);
- RK30_MODEM_POWER_IOMUX;
-
- return 0;
-}
-
-static struct rk29_io_t rk30_modem_io = {
- .io_addr = RK30_MODEM_POWER,
- .enable = GPIO_HIGH,
- .disable = GPIO_LOW,
- .io_init = rk30_modem_io_init,
-};
-
-static struct platform_device rk30_device_modem = {
- .name = "rk30_modem",
- .id = -1,
- .dev = {
- .platform_data = &rk30_modem_io,
- }
-};
-#endif
-#if defined(CONFIG_MU509)
-static int mu509_io_init(void)
-{
-
- iomux_set(GPIO2_D5);
- iomux_set(GPIO0_C6);
- iomux_set(GPIO2_D4);
- iomux_set(GPIO0_C4);
- iomux_set(GPIO0_C5);
- return 0;
-}
-
-static int mu509_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mu509_data rk29_mu509_info = {
- .io_init = mu509_io_init,
- .io_deinit = mu509_io_deinit,
- .modem_power_en = RK30_PIN2_PD5,
- .bp_power = RK30_PIN0_PC6,
- .bp_reset = RK30_PIN2_PD4,
- .ap_wakeup_bp = RK30_PIN0_PC4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
-};
-struct platform_device rk29_device_mu509 = {
- .name = "mu509",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mu509_info,
- }
- };
-#endif
-#if defined(CONFIG_MW100)
-static int mw100_io_init(void)
-{
- iomux_set(GPIO2_D5);
- iomux_set(GPIO0_C6);
- iomux_set(GPIO2_D4);
- iomux_set(GPIO0_C4);
- iomux_set(GPIO0_C5);
- return 0;
-}
-
-static int mw100_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mw100_data rk29_mw100_info = {
- .io_init = mw100_io_init,
- .io_deinit = mw100_io_deinit,
- .modem_power_en = RK30_PIN2_PD5,
- .bp_power = RK30_PIN0_PC6,
- .bp_reset = RK30_PIN2_PD4,
- .ap_wakeup_bp = RK30_PIN0_PC4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
-};
-struct platform_device rk29_device_mw100 = {
- .name = "mw100",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mw100_info,
- }
- };
-#endif
-#if defined(CONFIG_MT6229)
-static int mt6229_io_init(void)
-{
- iomux_set(GPIO2_D5);
- iomux_set(GPIO0_C6);
- iomux_set(GPIO2_D4);
- iomux_set(GPIO0_C4);
- iomux_set(GPIO0_C5);
- return 0;
-}
-
-static int mt6229_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mt6229_data rk29_mt6229_info = {
- .io_init = mt6229_io_init,
- .io_deinit = mt6229_io_deinit,
- .modem_power_en = RK30_PIN2_PD5,
- .bp_power = RK30_PIN0_PC6,
- .bp_reset = RK30_PIN2_PD4,
- .ap_wakeup_bp = RK30_PIN0_PC4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
-};
-struct platform_device rk29_device_mt6229 = {
- .name = "mt6229",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mt6229_info,
- }
- };
-#endif
-
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN RK30_PIN0_PB7
-
-static int mma8452_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data mma8452_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma8452_init_platform_hw,
- .orientation = {-1, 0, 0, 0, -1, 0, 0, 0, 1},
-};
-#endif
-#if defined (CONFIG_GS_LIS3DH)
-#define LIS3DH_INT_PIN RK30_PIN0_PB7
-
-static int lis3dh_init_platform_hw(void)
-{
-
- return 0;
-}
-
-static struct sensor_platform_data lis3dh_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lis3dh_init_platform_hw,
- .orientation = {-1, 0, 0, 0, -1, 0, 0, 0, 1},
-};
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
-static struct sensor_platform_data akm8975_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-#if defined(CONFIG_GYRO_L3G4200D)
-
-#include <linux/l3g4200d.h>
-#define L3G4200D_INT_PIN RK30_PIN0_PB4
-
-static int l3g4200d_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data l3g4200d_info = {
- .type = SENSOR_TYPE_GYROSCOPE,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
- .init_platform_hw = l3g4200d_init_platform_hw,
- .x_min = 40,//x_min,y_min,z_min = (0-100) according to hardware
- .y_min = 40,
- .z_min = 20,
-};
-
-#endif
-
-#ifdef CONFIG_LS_CM3217
-static struct sensor_platform_data cm3217_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 0,
- .poll_delay_ms = 500,
-};
-
-#endif
-
-#ifdef CONFIG_FB_ROCKCHIP
-
-#define LCD_CS_PIN INVALID_GPIO
-#define LCD_CS_VALUE GPIO_HIGH
-
-#define LCD_EN_PIN RK30_PIN0_PB0
-#define LCD_EN_VALUE GPIO_HIGH
-
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
-
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_CS_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_CS_PIN);
- printk(KERN_ERR "request lcd cs pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_CS_PIN, LCD_CS_VALUE);
- }
- }
-
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_EN_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_EN_PIN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_EN_PIN, LCD_EN_VALUE);
- }
- }
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, !LCD_CS_VALUE);
- }
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, !LCD_EN_VALUE);
- }
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE);
- }
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
- }
- return 0;
-}
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
-struct rk29fb_info lcdc0_screen_info = {
- #if defined(CONFIG_RK_HDMI)
- .prop = EXTEND, //extend display device
- .lcd_info = NULL,
- .set_screen_info = hdmi_init_lcdc,
- #endif
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
-struct rk29fb_info lcdc1_screen_info = {
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-#if defined(CONFIG_ARCH_RK3188)
-static struct resource resource_mali[] = {
- [0] = {
- .name = "ump buf",
- .start = 0,
- .end = 0,
- .flags = IORESOURCE_MEM,
- },
-
-};
-
-static struct platform_device device_mali= {
- .name = "mali400_ump",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_mali),
- .resource = resource_mali,
-};
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
-static struct resource resource_lcdc0[] = {
- [0] = {
- .name = "lcdc0 reg",
- .start = RK30_LCDC0_PHYS,
- .end = RK30_LCDC0_PHYS + RK30_LCDC0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc0 irq",
- .start = IRQ_LCDC0,
- .end = IRQ_LCDC0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc0 = {
- .name = "rk30-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc0),
- .resource = resource_lcdc0,
- .dev = {
- .platform_data = &lcdc0_screen_info,
- },
-};
-#endif
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
-static struct resource resource_lcdc1[] = {
- [0] = {
- .name = "lcdc1 reg",
- .start = RK30_LCDC1_PHYS,
- .end = RK30_LCDC1_PHYS + RK30_LCDC1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc1 irq",
- .start = IRQ_LCDC1,
- .end = IRQ_LCDC1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc1 = {
- .name = "rk30-lcdc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resource_lcdc1),
- .resource = resource_lcdc1,
- .dev = {
- .platform_data = &lcdc1_screen_info,
- },
-};
-#endif
-
-#if defined(CONFIG_MFD_RK610)
-#define RK610_RST_PIN RK30_PIN2_PC5
-static int rk610_power_on_init(void)
-{
- int ret;
- if(RK610_RST_PIN != INVALID_GPIO)
- {
- ret = gpio_request(RK610_RST_PIN, "rk610 reset");
- if (ret)
- {
- printk(KERN_ERR "rk610_control_probe request gpio fail\n");
- }
- else
- {
- gpio_direction_output(RK610_RST_PIN, GPIO_HIGH);
- msleep(100);
- gpio_direction_output(RK610_RST_PIN, GPIO_LOW);
- msleep(100);
- gpio_set_value(RK610_RST_PIN, GPIO_HIGH);
- }
- }
-
- return 0;
-
-}
-
-
-static struct rk610_ctl_platform_data rk610_ctl_pdata = {
- .rk610_power_on_init = rk610_power_on_init,
-};
-#endif
-
-#if defined(CONFIG_MFD_RK616)
-#define RK616_RST_PIN RK30_PIN3_PB2
-#define RK616_PWREN_PIN RK30_PIN0_PC5
-#define RK616_SPK_CTL2 RK30_PIN0_PD5
-#define RK616_SCL_RATE (80*1000) //i2c scl rate
-static int rk616_power_on_init(void)
-{
- int ret;
-#if 1
- if(RK616_SPK_CTL2 != INVALID_GPIO)
- {
- ret = gpio_request(RK616_SPK_CTL2, "rk616 spk ctl2");
- if (ret)
- {
- printk(KERN_ERR "rk616 spk_ctl2 gpio request fail\n");
- }
- else
- {
- gpio_direction_output(RK616_SPK_CTL2,GPIO_HIGH);
- }
- }
-#endif
- if(RK616_PWREN_PIN != INVALID_GPIO)
- {
- ret = gpio_request(RK616_PWREN_PIN, "rk616 pwren");
- if (ret)
- {
- printk(KERN_ERR "rk616 pwren gpio request fail\n");
- }
- else
- {
- gpio_direction_output(RK616_PWREN_PIN,GPIO_HIGH);
- }
- }
-
- if(RK616_RST_PIN != INVALID_GPIO)
- {
- ret = gpio_request(RK616_RST_PIN, "rk616 reset");
- if (ret)
- {
- printk(KERN_ERR "rk616 reset gpio request fail\n");
- }
- else
- {
- gpio_direction_output(RK616_RST_PIN, GPIO_HIGH);
- msleep(100);
- gpio_direction_output(RK616_RST_PIN, GPIO_LOW);
- msleep(100);
- gpio_set_value(RK616_RST_PIN, GPIO_HIGH);
- }
- }
-
- return 0;
-
-}
-
-
-static struct rk616_platform_data rk616_pdata = {
- .power_init = rk616_power_on_init,
- .scl_rate = RK616_SCL_RATE,
- .lcd0_func = INPUT, //port lcd0 as input
- .lcd1_func = INPUT, //port lcd1 as input
- .lvds_ch_nr = 0, //the number of used lvds channel
- .hdmi_irq = RK30_PIN2_PD4,
- .spk_ctl_gpio = RK30_PIN0_PD5,
- .hp_ctl_gpio = RK30_PIN0_PD5,
-};
-#endif
-
-#ifdef CONFIG_SND_SOC_RK610
-static int rk610_codec_io_init(void)
-{
-//if need iomux.
-//Must not gpio_request
- return 0;
-}
-
-static struct rk610_codec_platform_data rk610_codec_pdata = {
- .spk_ctl_io = RK30_PIN2_PD7,
- .io_init = rk610_codec_io_init,
-};
-#endif
-
-#ifdef CONFIG_ANDROID_TIMED_GPIO
-static struct timed_gpio timed_gpios[] = {
- {
- .name = "vibrator",
- .gpio = INVALID_GPIO,
- .max_timeout = 1000,
- .active_low = 0,
- .adjust_time =20, //adjust for diff product
- },
-};
-
-static struct timed_gpio_platform_data rk29_vibrator_info = {
- .num_gpios = 1,
- .gpios = timed_gpios,
-};
-
-static struct platform_device rk29_device_vibrator = {
- .name = "timed-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_vibrator_info,
- },
-
-};
-#endif
-
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
-static struct gpio_led rk29_leds[] = {
- {
- .name = "button-backlight",
- .gpio = INVALID_GPIO,
- .default_trigger = "timer",
- .active_low = 0,
- .retain_state_suspended = 0,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- },
-};
-
-static struct gpio_led_platform_data rk29_leds_pdata = {
- .leds = rk29_leds,
- .num_leds = ARRAY_SIZE(rk29_leds),
-};
-
-static struct platform_device rk29_device_gpio_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_leds_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_RK_IRDA
-#define IRDA_IRQ_PIN INVALID_GPIO //RK30_PIN0_PA3
-
-static int irda_iomux_init(void)
-{
- int ret = 0;
-
- //irda irq pin
- ret = gpio_request(IRDA_IRQ_PIN, NULL);
- if (ret != 0) {
- gpio_free(IRDA_IRQ_PIN);
- printk(">>>>>> IRDA_IRQ_PIN gpio_request err \n ");
- }
- gpio_pull_updown(IRDA_IRQ_PIN, PullDisable);
- gpio_direction_input(IRDA_IRQ_PIN);
-
- return 0;
-}
-
-static int irda_iomux_deinit(void)
-{
- gpio_free(IRDA_IRQ_PIN);
- return 0;
-}
-
-static struct irda_info rk29_irda_info = {
- .intr_pin = IRDA_IRQ_PIN,
- .iomux_init = irda_iomux_init,
- .iomux_deinit = irda_iomux_deinit,
- //.irda_pwr_ctl = bu92747guw_power_ctl,
-};
-
-static struct platform_device irda_device = {
-#ifdef CONFIG_RK_IRDA_NET
- .name = "rk_irda",
-#else
- .name = "bu92747_irda",
-#endif
- .id = -1,
- .dev = {
- .platform_data = &rk29_irda_info,
- }
-};
-#endif
-
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and sdio.noted by xbw at 2012-03-05
-**************************************************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "../mach-rk30/board-rk3168-tb-sdmmc-conifg.c"
-#include "../plat-rk/rk-sdmmc-ops.c"
-#include "../plat-rk/rk-sdmmc-wifi.c"
-#endif //endif ---#ifdef CONFIG_SDMMC_RK29
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- iomux_set(MMC0_CMD);
- iomux_set(MMC0_CLKOUT);
- iomux_set(MMC0_D0);
- iomux_set(MMC0_D1);
- iomux_set(MMC0_D2);
- iomux_set(MMC0_D3);
-
- iomux_set_gpio_mode(iomux_mode_to_gpio(MMC0_DETN));
-
- gpio_request(RK30_PIN3_PA7, "sdmmc-power");
- gpio_direction_output(RK30_PIN3_PA7, GPIO_LOW);
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- #if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set_gpio_mode(iomux_gpio_to_mode(RK29SDK_SD_CARD_DETECT_N));
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO);
- #endif
- #else
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(MMC0_DETN);
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FMUX);
- #endif
- #endif
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) && defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- .status = rk29sdk_wifi_mmc0_status,
- .register_status_notify = rk29sdk_wifi_mmc0_status_register,
-#endif
-
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .power_en = RK29SDK_SD_CARD_PWR_EN,
- .power_en_level = RK29SDK_SD_CARD_PWR_EN_LEVEL,
-#else
- .power_en = INVALID_GPIO,
- .power_en_level = GPIO_LOW,
-#endif
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC0_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- .det_pin_info = {
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N, //INVALID_GPIO,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
- #endif
- },
-
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- iomux_set(MMC1_CMD);
- iomux_set(MMC1_CLKOUT);
- iomux_set(MMC1_D0);
- iomux_set(MMC1_D1);
- iomux_set(MMC1_D2);
- iomux_set(MMC1_D3);
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC) || defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC1_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- #if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
- .sdio_INT_gpio = RK29SDK_WIFI_SDIO_CARD_INT,
- #endif
-
- .det_pin_info = {
-#if defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- #else
- .io = INVALID_GPIO,
- #endif
-
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-
- .enable_sd_wakeup = 0,
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-/**************************************************************************************************
- * the end of setting for SDMMC devices
-**************************************************************************************************/
-
-#ifdef CONFIG_BATTERY_RK30_ADC
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = RK30_PIN0_PB2,
- .batt_low_pin = RK30_PIN0_PB1,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = RK30_PIN0_PA6,
- .dc_det_level = GPIO_LOW,
- .charge_ok_level = GPIO_HIGH,
-};
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-#ifdef CONFIG_CW2015_BATTERY
-/*
- note the follow array must set depend on the battery that you use
- you must send the battery to cellwise-semi the contact information:
- name: chen gan; tel:13416876079; E-mail: ben.chen@cellwise-semi.com
- */
-static u8 config_info[SIZE_BATINFO] = {
- 0x15, 0x42, 0x60, 0x59, 0x52,
- 0x58, 0x4D, 0x48, 0x48, 0x44,
- 0x44, 0x46, 0x49, 0x48, 0x32,
- 0x24, 0x20, 0x17, 0x13, 0x0F,
- 0x19, 0x3E, 0x51, 0x45, 0x08,
- 0x76, 0x0B, 0x85, 0x0E, 0x1C,
- 0x2E, 0x3E, 0x4D, 0x52, 0x52,
- 0x57, 0x3D, 0x1B, 0x6A, 0x2D,
- 0x25, 0x43, 0x52, 0x87, 0x8F,
- 0x91, 0x94, 0x52, 0x82, 0x8C,
- 0x92, 0x96, 0xFF, 0x7B, 0xBB,
- 0xCB, 0x2F, 0x7D, 0x72, 0xA5,
- 0xB5, 0xC1, 0x46, 0xAE
-};
-
-static struct cw_bat_platform_data cw_bat_platdata = {
- .dc_det_pin = RK30_PIN0_PB2,
- .bat_low_pin = RK30_PIN0_PB1,
- .chg_ok_pin = RK30_PIN0_PA6,
- .dc_det_level = GPIO_LOW,
- .bat_low_level = GPIO_LOW,
- .chg_ok_level = GPIO_HIGH,
-
- .cw_bat_config_info = config_info,
-
-};
-
-#endif
-#ifdef CONFIG_RK30_PWM_REGULATOR
-static int pwm_voltage_map[] = {
- 800000,825000,850000, 875000,900000, 925000 ,950000, 975000,1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000,1375000
-};
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_cpu",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] =
-{
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
- .pwm_id = 1,
- .pwm_gpio = RK30_PIN3_PD4,
- .pwm_iomux_pwm = PWM1,
- .pwm_iomux_gpio = GPIO3_D4,
- .pwm_voltage = 1100000,
- .suspend_voltage = 1000000,
- .min_uV = 800000,
- .max_uV = 1375000,
- .coefficient = 575, //57.5%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-#endif
-
-#ifdef CONFIG_RK29_VMAC
-#define PHY_PWR_EN_GPIO RK30_PIN1_PD6
-#include "board-rk30-sdk-vmac.c"
-#endif
-
-#ifdef CONFIG_RFKILL_RK
-// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
-static struct rfkill_rk_platform_data rfkill_rk_platdata = {
- .type = RFKILL_TYPE_BLUETOOTH,
-
- .poweron_gpio = { // BT_REG_ON
- .io = INVALID_GPIO, //RK30_PIN3_PC7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_poweron",
- .fgpio = GPIO3_C7,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN3_PC7, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_reset",
- .fgpio = GPIO3_C7,
- },
- },
-
- .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
- .io = RK30_PIN3_PC6, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_wake",
- .fgpio = GPIO3_C6,
- },
- },
-
- .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .gpio = {
- .io = RK30_PIN0_PA5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
- .iomux = {
- .name = NULL,
- },
- },
- },
-
- .rts_gpio = { // UART_RTS, enable or disable BT's data coming
- .io = RK30_PIN1_PA3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_rts",
- .fgpio = GPIO1_A3,
- .fmux = UART0_RTSN,
- },
- },
-};
-
-static struct platform_device device_rfkill_rk = {
- .name = "rfkill_rk",
- .id = -1,
- .dev = {
- .platform_data = &rfkill_rk_platdata,
- },
-};
-#endif
-
-#if defined(CONFIG_GPS_RK)
-int rk_gps_io_init(void)
-{
- printk("%s \n", __FUNCTION__);
-
- gpio_request(RK30_PIN1_PB5, NULL);
- gpio_direction_output(RK30_PIN1_PB5, GPIO_LOW);
-
- iomux_set(GPS_RFCLK);//GPS_CLK
- iomux_set(GPS_MAG);//GPS_MAG
- iomux_set(GPS_SIG);//GPS_SIGN
-
- gpio_request(RK30_PIN1_PA6, NULL);
- gpio_direction_output(RK30_PIN1_PA6, GPIO_LOW);
-
- gpio_request(RK30_PIN1_PA5, NULL);
- gpio_direction_output(RK30_PIN1_PA5, GPIO_LOW);
-
- gpio_request(RK30_PIN1_PA7, NULL);
- gpio_direction_output(RK30_PIN1_PA7, GPIO_LOW);
- return 0;
-}
-int rk_gps_power_up(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_power_down(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_reset_set(int level)
-{
- return 0;
-}
-int rk_enable_hclk_gps(void)
-{
- struct clk *gps_aclk = NULL;
- gps_aclk = clk_get(NULL, "aclk_gps");
- if(gps_aclk) {
- clk_enable(gps_aclk);
- clk_put(gps_aclk);
- printk("%s \n", __FUNCTION__);
- }
- else
- printk("get gps aclk fail\n");
- return 0;
-}
-int rk_disable_hclk_gps(void)
-{
- struct clk *gps_aclk = NULL;
- gps_aclk = clk_get(NULL, "aclk_gps");
- if(gps_aclk) {
- //TO wait long enough until GPS ISR is finished.
- msleep(5);
- clk_disable(gps_aclk);
- clk_put(gps_aclk);
- printk("%s \n", __FUNCTION__);
- }
- else
- printk("get gps aclk fail\n");
- return 0;
-}
-struct rk_gps_data rk_gps_info = {
- .io_init = rk_gps_io_init,
- .power_up = rk_gps_power_up,
- .power_down = rk_gps_power_down,
- .reset = rk_gps_reset_set,
- .enable_hclk_gps = rk_enable_hclk_gps,
- .disable_hclk_gps = rk_disable_hclk_gps,
- .GpsSign = RK30_PIN1_PB3,
- .GpsMag = RK30_PIN1_PB2, //GPIO index
- .GpsClk = RK30_PIN1_PB4, //GPIO index
- .GpsVCCEn = RK30_PIN1_PB5, //GPIO index
- .GpsSpi_CSO = RK30_PIN1_PA4, //GPIO index
- .GpsSpiClk = RK30_PIN1_PA5, //GPIO index
- .GpsSpiMOSI = RK30_PIN1_PA7, //GPIO index
- .GpsIrq = IRQ_GPS,
- .GpsSpiEn = 0,
- .GpsAdcCh = 2,
- .u32GpsPhyAddr = RK30_GPS_PHYS,
- .u32GpsPhySize = RK30_GPS_SIZE,
-};
-
-struct platform_device rk_device_gps = {
- .name = "gps_hv5820b",
- .id = -1,
- .dev = {
- .platform_data = &rk_gps_info,
- }
- };
-#endif
-
-#if defined(CONFIG_MT5931_MT6622)
-static struct mt6622_platform_data mt6622_platdata = {
- .power_gpio = { // BT_REG_ON
- .io = RK30_PIN3_PD5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN0_PD7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .irq_gpio = {
- .io = RK30_PIN3_PD2,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- }
-};
-
-static struct platform_device device_mt6622 = {
- .name = "mt6622",
- .id = -1,
- .dev = {
- .platform_data = &mt6622_platdata,
- },
-};
-#endif
-
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_ANDROID_TIMED_GPIO
- &rk29_device_vibrator,
-#endif
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
- &rk29_device_gpio_leds,
-#endif
-#ifdef CONFIG_RK_IRDA
- &irda_device,
-#endif
-#if defined(CONFIG_WIFI_CONTROL_FUNC)||defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- &rk29sdk_wifi_device,
-#endif
-
-#if defined(CONFIG_MT6620)
- &mt3326_device_gps,
-#endif
-
-#ifdef CONFIG_RK29_SUPPORT_MODEM
- &rk30_device_modem,
-#endif
-#if defined(CONFIG_MU509)
- &rk29_device_mu509,
-#endif
-#if defined(CONFIG_MW100)
- &rk29_device_mw100,
-#endif
-#if defined(CONFIG_MT6229)
- &rk29_device_mt6229,
-#endif
-#ifdef CONFIG_BATTERY_RK30_ADC
- &rk30_device_adc_battery,
-#endif
-#ifdef CONFIG_RFKILL_RK
- &device_rfkill_rk,
-#endif
-#ifdef CONFIG_GPS_RK
- &rk_device_gps,
-#endif
-#if defined(CONFIG_ARCH_RK3188)
- &device_mali,
-#endif
-#ifdef CONFIG_MT5931_MT6622
- &device_mt6622,
-#endif
-};
-
-static int rk_platform_add_display_devices(void)
-{
- struct platform_device *fb = NULL; //fb
- struct platform_device *lcdc0 = NULL; //lcdc0
- struct platform_device *lcdc1 = NULL; //lcdc1
- struct platform_device *bl = NULL; //backlight
-#ifdef CONFIG_FB_ROCKCHIP
- fb = &device_fb;
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
- lcdc0 = &device_lcdc0,
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
- lcdc1 = &device_lcdc1,
-#endif
-
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- bl = &rk29_device_backlight,
-#endif
- __rk_platform_add_display_devices(fb,lcdc0,lcdc1,bl);
-
- return 0;
-
-}
-
-// i2c
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1d,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_GS_LIS3DH)
- {
- .type = "gs_lis3dh",
- .addr = 0x19, //0x19(SA0-->VCC), 0x18(SA0-->GND)
- .flags = 0,
- .irq = LIS3DH_INT_PIN,
- .platform_data = &lis3dh_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8975_info,
- },
-#endif
-#if defined (CONFIG_GYRO_L3G4200D)
- {
- .type = "l3g4200d_gryo",
- .addr = 0x69,
- .flags = 0,
- .irq = L3G4200D_INT_PIN,
- .platform_data = &l3g4200d_info,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RT5631)
- {
- .type = "rt5631",
- .addr = 0x1a,
- .flags = 0,
- },
-#endif
-
-#if defined (CONFIG_SND_SOC_RT5640)
- {
- .type = "rt5640",
- .addr = 0x1c,
- .flags = 0,
- },
-#endif
-
-#ifdef CONFIG_MFD_RK610
- {
- .type = "rk610_ctl",
- .addr = 0x40,
- .flags = 0,
- .platform_data = &rk610_ctl_pdata,
- },
-#ifdef CONFIG_RK610_TVOUT
- {
- .type = "rk610_tvout",
- .addr = 0x42,
- .flags = 0,
- },
-#endif
-#ifdef CONFIG_HDMI_RK610
- {
- .type = "rk610_hdmi",
- .addr = 0x46,
- .flags = 0,
- .irq = INVALID_GPIO,
- },
-#endif
-#ifdef CONFIG_SND_SOC_RK610
- {//RK610_CODEC addr from 0x60 to 0x80 (0x60~0x80)
- .type = "rk610_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- .platform_data = &rk610_codec_pdata,
- },
-#endif
-#endif
-
-};
-#endif
-
-int __sramdata g_pmic_type = 0;
-#ifdef CONFIG_I2C1_RK30
-#ifdef CONFIG_MFD_WM831X_I2C
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info wm8326_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "dcdc3", //ddr
- .min_uv = 1150000,
- .max_uv = 1150000,
- .suspend_vol = 1150000,
- },
- #ifdef CONFIG_MACH_RK3066_SDK
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3000000,
- },
- #else
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3000000,
- .max_uv = 3000000,
- .suspend_vol = 2800000,
- },
- #endif
-};
-
-static struct pmu_info wm8326_ldo_info[] = {
- {
- .name = "ldo1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo2", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo3", //
- .min_uv = 1100000,
- .max_uv = 1100000,
- .suspend_vol = 1100000,
- },
- {
- .name = "ldo4", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 1000000,
- },
- {
- .name = "ldo5", //vcc25
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo6", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo7", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- .suspend_vol = 2800000,
- },
- {
- .name = "ldo8", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo9", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo10", //flash_io
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
-};
-
-#include "../mach-rk30/board-pmu-wm8326.c"
-#endif
-
-#ifdef CONFIG_MFD_TPS65910
-#define TPS65910_HOST_IRQ RK30_PIN0_PB3
-
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info tps65910_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1100000,
- .max_uv = 1100000,
- },
- {
- .name = "vdd2", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vio", //vcc_io
- .min_uv = 2500000,
- .max_uv = 2500000,
- },
-
-};
-static struct pmu_info tps65910_ldo_info[] = {
- {
- .name = "vpll", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "vdig2", //vdd_jetta
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vaux1", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "vaux2", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vaux33", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vmmc", //vcc30
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
- {
- .name = "vdac", //vcc18
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- };
-
-#include "../mach-rk30/board-pmu-tps65910.c"
-#endif
-
-#ifdef CONFIG_REGULATOR_ACT8846
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-#define PMU_VSEL RK30_PIN3_PD3
-static struct pmu_info act8846_dcdc_info[] = {
- {
- .name = "act_dcdc1", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- .suspend_vol = 1200000,
- },
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 1200000,
- #else
- .suspend_vol = 900000,
- #endif
-
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 1200000,
- #else
- .suspend_vol = 900000,
- #endif
-
- },
- {
- .name = "act_dcdc4", //vccio
- .min_uv = 3000000,
- .max_uv = 3000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 3000000,
- #else
- .suspend_vol = 2800000,
- #endif
-
- },
-
-};
-static struct pmu_info act8846_ldo_info[] = {
- {
- .name = "act_ldo1", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "act_ldo2", //vdd12
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "act_ldo3", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo4", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo5", //vcctp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo6", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo7", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo8", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- };
-
-#include "../mach-rk30/board-pmu-act8846.c"
-#endif
-
-#ifdef CONFIG_MFD_RK808
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-#define RK808_HOST_IRQ RK30_PIN0_PB3
-
-static struct pmu_info rk808_dcdc_info[] = {
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 900000,
- },
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 900000,
- },
- {
- .name = "rk_dcdc3", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- .suspend_vol = 1200000,
- },
- {
- .name = "rk_dcdc4", //vccio
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3000000,
- },
-
-};
-static struct pmu_info rk808_ldo_info[] = {
- {
- .name = "rk_ldo1", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "rk_ldo2", //vcctp
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
-
- },
- {
- .name = "rk_ldo3", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 1000000,
- },
- {
- .name = "rk_ldo4", //vcc18
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "rk_ldo5", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- .suspend_vol = 2800000,
- },
- {
- .name = "rk_ldo6", //vdd12
- .min_uv = 1200000,
- .max_uv = 1200000,
- .suspend_vol = 1200000,
- },
- {
- .name = "rk_ldo7", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "rk_ldo8", //vcca_33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- };
-
-#include "board-pmu-rk808.c"
-#endif
-
-
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_MFD_WM831X_I2C)
- {
- .type = "wm8326",
- .addr = 0x34,
- .flags = 0,
- .irq = RK30_PIN0_PB3,
- .platform_data = &wm831x_platdata,
- },
-#endif
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-
-#if defined (CONFIG_REGULATOR_ACT8846)
- {
- .type = "act8846",
- .addr = 0x5a,
- .flags = 0,
- // .irq = ACT8846_HOST_IRQ,
- .platform_data=&act8846_data,
- },
-#endif
-#if defined (CONFIG_MFD_RK808)
- {
- .type = "rk808",
- .addr = 0x1b,
- .flags = 0,
- // .irq = ACT8846_HOST_IRQ,
- .platform_data=&rk808_data,
- },
-#endif
-
-#if defined (CONFIG_RTC_HYM8563)
- {
- .type = "rtc_hym8563",
- .addr = 0x51,
- .flags = 0,
- .irq = RK30_PIN1_PA4,
- },
-#if defined (CONFIG_CW2015_BATTERY)
- {
- .type = "cw201x",
- .addr = 0x62,
- .flags = 0,
- .platform_data = &cw_bat_platdata,
- },
-#endif
-#endif
-
-};
-#endif
-
-void __sramfunc board_pmu_suspend(void)
-{
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_suspend();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_suspend();
- #endif
- #if defined (CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- board_pmu_act8846_suspend();
- #endif
- #if defined (CONFIG_MFD_RK808)
- if(pmic_is_rk808())
- board_pmu_rk808_suspend();
- #endif
-
-}
-
-void __sramfunc board_pmu_resume(void)
-{
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_resume();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_resume();
- #endif
- #if defined (CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- board_pmu_act8846_resume();
- #endif
- #if defined (CONFIG_MFD_RK808)
- if(pmic_is_rk808())
- board_pmu_rk808_resume();
- #endif
-
-}
-
- int __sramdata gpio3d6_iomux,gpio3d6_do,gpio3d6_dir,gpio3d6_en;
-
-#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
-
-void __sramfunc rk30_pwm_logic_suspend_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
-
-// int gpio0d7_iomux,gpio0d7_do,gpio0d7_dir,gpio0d7_en;
- sram_udelay(10000);
- gpio3d6_iomux = grf_readl(GRF_GPIO3D_IOMUX);
- gpio3d6_do = grf_readl(GRF_GPIO3H_DO);
- gpio3d6_dir = grf_readl(GRF_GPIO3H_DIR);
- gpio3d6_en = grf_readl(GRF_GPIO3H_EN);
-
- grf_writel((1<<28), GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DIR);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DO);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_EN);
-#endif
-}
-void __sramfunc rk30_pwm_logic_resume_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- grf_writel((1<<28)|gpio3d6_iomux, GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|gpio3d6_en, GRF_GPIO3H_EN);
- grf_writel((1<<30)|gpio3d6_dir, GRF_GPIO3H_DIR);
- grf_writel((1<<30)|gpio3d6_do, GRF_GPIO3H_DO);
- sram_udelay(10000);
-
-#endif
-
-}
-extern void pwm_suspend_voltage(void);
-extern void pwm_resume_voltage(void);
-void rk30_pwm_suspend_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_suspend_voltage();
-#endif
-}
-void rk30_pwm_resume_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_resume_voltage();
-#endif
-}
-
-
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-#if defined (CONFIG_TOUCHSCREEN_GT8XX)
- {
- .type = "Goodix-TS",
- .addr = 0x55,
- .flags = 0,
- .irq = RK30_PIN1_PB7,
- .platform_data = &goodix_info,
- },
-#endif
-#if defined (CONFIG_LS_CM3217)
- {
- .type = "lightsensor",
- .addr = 0x10,
- .flags = 0,
- .platform_data = &cm3217_info,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C4_RK30
-static struct i2c_board_info __initdata i2c4_info[] = {
-#if defined (CONFIG_MFD_RK616)
- {
- .type = "rk616",
- .addr = 0x50,
- .flags = 0,
- .platform_data = &rk616_pdata,
- },
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO// RK30_PIN2_PD6 //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO//RK30_PIN2_PD7 //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- //set iomux (gpio) here
- //rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME, GPIO2D_GPIO2D7);
- //rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME, GPIO2D_GPIO2D6);
-
- return 0;
-}
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C4_RK30
- i2c_register_board_info(4, i2c4_info, ARRAY_SIZE(i2c4_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(5, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-
-// ========== Begin of rk3168 top board keypad defination ============
-
-#include <plat/key.h>
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .adc_value = 900,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK30_PIN0_PA4,
- .active_low = PRESS_LEV_LOW,
- .wakeup = 1,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .adc_value = 1,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "menu",
- .code = EV_MENU,
- .adc_value = 133,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .adc_value = 550,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .adc_value = 333,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "camera",
- .code = KEY_CAMERA,
- .adc_value = 742,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = 1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
-// =========== End of rk3168 top board keypad defination =============
-
-
-#define POWER_ON_PIN RK30_PIN0_PA0 //power_hold
-static void rk30_pm_power_off(void)
-{
- printk(KERN_ERR "rk30_pm_power_off start...\n");
- #if defined(CONFIG_MFD_WM831X)
- if(pmic_is_wm8326()){
- wm831x_set_bits(Wm831x,WM831X_GPIO_LEVEL,0x0001,0x0000); //set sys_pwr 0
- wm831x_device_shutdown(Wm831x);//wm8326 shutdown
- }
- #endif
-
- #if defined(CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- {
- act8846_device_shutdown();
- }
- #endif
-
- #if defined(CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- {
- tps65910_device_shutdown();//tps65910 shutdown
- }
- #endif
-
- #if defined(CONFIG_MFD_RK808)
- if(pmic_is_rk808())
- {
- rk808_device_shutdown();//rk808 shutdown
- }
- #endif
-
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
- while (1);
-}
-
-static void __init machine_rk30_board_init(void)
-{
- //avs_init();
- gpio_request(POWER_ON_PIN, "poweronpin");
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
- pm_power_off = rk30_pm_power_off;
-
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
-
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- rk_platform_add_display_devices();
- board_usb_detect_init(RK30_PIN0_PA7);
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC)
- rk29sdk_wifi_bt_gpio_control_init();
-#elif defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- rk29sdk_wifi_combo_module_gpio_init();
-#endif
-
-#if defined(CONFIG_MT6620)
- clk_set_rate(clk_get_sys("rk_serial.0", "uart"), 48*1000000);
-#endif
-
-#if defined(CONFIG_MT5931_MT6622)
- clk_set_rate(clk_get_sys("rk_serial.0", "uart"), 24*1000000);
-#endif
-}
-#define HD_SCREEN_SIZE 1920UL*1200UL*4*3
-static void __init rk30_reserve(void)
-{
-#if defined(CONFIG_ARCH_RK3188)
- /*if lcd resolution great than or equal to 1920*1200,reserve the ump memory */
- if(!(get_fb_size() < ALIGN(HD_SCREEN_SIZE,SZ_1M)))
- {
- int ump_mem_phy_size=512UL*1024UL*1024UL;
- resource_mali[0].start = board_mem_reserve_add("ump buf", ump_mem_phy_size);
- resource_mali[0].end = resource_mali[0].start + ump_mem_phy_size -1;
- }
-#endif
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0 buf", get_fb_size());
- resource_fb[0].end = resource_fb[0].start + get_fb_size()- 1;
-#if 0
- resource_fb[1].start = board_mem_reserve_add("ipp buf", RK30_FB0_MEM_SIZE);
- resource_fb[1].end = resource_fb[1].start + RK30_FB0_MEM_SIZE - 1;
-#endif
-
-#if defined(CONFIG_FB_ROTATE) || !defined(CONFIG_THREE_FB_BUFFER)
- resource_fb[2].start = board_mem_reserve_add("fb2 buf",get_fb_size());
- resource_fb[2].end = resource_fb[2].start + get_fb_size() - 1;
-#endif
-#endif
-
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
-
-#ifdef CONFIG_GPS_RK
- //it must be more than 8MB
- rk_gps_info.u32MemoryPhyAddr = board_mem_reserve_add("gps", SZ_8M);
-#endif
- board_mem_reserved();
-}
-/******************************** arm dvfs frequency volt table **********************************/
-/**
- * dvfs_cpu_logic_table: table for arm and logic dvfs
- * @frequency : arm frequency
- * @cpu_volt : arm voltage depend on frequency
- */
-
-#if defined(CONFIG_ARCH_RK3188)
-//sdk
-static struct cpufreq_frequency_table dvfs_arm_table_volt_level0[] = {
- {.frequency = 312 * 1000, .index = 850 * 1000},
- {.frequency = 504 * 1000, .index = 900 * 1000},
- {.frequency = 816 * 1000, .index = 950 * 1000},
- {.frequency = 1008 * 1000, .index = 1025 * 1000},
- {.frequency = 1200 * 1000, .index = 1100 * 1000},
- {.frequency = 1416 * 1000, .index = 1200 * 1000},
- {.frequency = 1608 * 1000, .index = 1300 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-//default
-static struct cpufreq_frequency_table dvfs_arm_table_volt_level1[] = {
- {.frequency = 312 * 1000, .index = 875 * 1000},
- {.frequency = 504 * 1000, .index = 925 * 1000},
- {.frequency = 816 * 1000, .index = 975 * 1000},
- {.frequency = 1008 * 1000, .index = 1075 * 1000},
- {.frequency = 1200 * 1000, .index = 1150 * 1000},
- {.frequency = 1416 * 1000, .index = 1250 * 1000},
- {.frequency = 1608 * 1000, .index = 1350 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-// cube 10'
-static struct cpufreq_frequency_table dvfs_arm_table_volt_level2[] = {
- {.frequency = 312 * 1000, .index = 900 * 1000},
- {.frequency = 504 * 1000, .index = 925 * 1000},
- {.frequency = 816 * 1000, .index = 1000 * 1000},
- {.frequency = 1008 * 1000, .index = 1075 * 1000},
- {.frequency = 1200 * 1000, .index = 1200 * 1000},
- {.frequency = 1416 * 1000, .index = 1250 * 1000},
- {.frequency = 1608 * 1000, .index = 1350 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-/******************************** gpu dvfs frequency volt table **********************************/
-//sdk
-static struct cpufreq_frequency_table dvfs_gpu_table_volt_level0[] = {
- {.frequency = 133 * 1000, .index = 975 * 1000},//the mininum rate is limited 133M for rk3188
- {.frequency = 200 * 1000, .index = 975 * 1000},
- {.frequency = 266 * 1000, .index = 1000 * 1000},
- {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1100 * 1000},
- {.frequency = 600 * 1000, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-//cube 10'
-static struct cpufreq_frequency_table dvfs_gpu_table_volt_level1[] = {
- {.frequency = 133 * 1000, .index = 975 * 1000},//the mininum rate is limited 133M for rk3188
- {.frequency = 200 * 1000, .index = 1000 * 1000},
- {.frequency = 266 * 1000, .index = 1025 * 1000},
- {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1100 * 1000},
- {.frequency = 600 * 1000, .index = 1250 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-/******************************** ddr dvfs frequency volt table **********************************/
-static struct cpufreq_frequency_table dvfs_ddr_table_volt_level0[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 950 * 1000},
- {.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = 1000 * 1000},
- {.frequency = 396 * 1000 + DDR_FREQ_NORMAL, .index = 1100 * 1000},
- //{.frequency = 528 * 1000 + DDR_FREQ_NORMAL, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-//if you board is good for volt quality,select dvfs_arm_table_volt_level0
-#define dvfs_arm_table dvfs_arm_table_volt_level0
-#define dvfs_gpu_table dvfs_gpu_table_volt_level1
-#define dvfs_ddr_table dvfs_ddr_table_volt_level0
-
-#else
-//for RK3168 && RK3066B
-#if 0
-static struct cpufreq_frequency_table dvfs_arm_table[] = {
- {.frequency = 312 * 1000, .index = 950 * 1000},
- {.frequency = 504 * 1000, .index = 1000 * 1000},
- {.frequency = 816 * 1000, .index = 1050 * 1000},
- {.frequency = 1008 * 1000, .index = 1125 * 1000},
- {.frequency = 1200 * 1000, .index = 1200 * 1000},
- //{.frequency = 1416 * 1000, .index = 1250 * 1000},
- //{.frequency = 1608 * 1000, .index = 1300 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- {.frequency = 100 * 1000, .index = 1000 * 1000},
- {.frequency = 200 * 1000, .index = 1000 * 1000},
- {.frequency = 266 * 1000, .index = 1050 * 1000},
- //{.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1125 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 1000 * 1000},
- {.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = 1050 * 1000},
- {.frequency = 400 * 1000 + DDR_FREQ_NORMAL, .index = 1100 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-#else
-static struct cpufreq_frequency_table dvfs_arm_table[] = {
- {.frequency = 312 * 1000, .index = 1025 * 1000},
- {.frequency = 504 * 1000, .index = 1025 * 1000},
- {.frequency = 816 * 1000, .index = 1050 * 1000},
- {.frequency = 1008 * 1000, .index = 1125 * 1000},
- {.frequency = 1200 * 1000, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- {.frequency = 100 * 1000, .index = 1000 * 1000},
- {.frequency = 200 * 1000, .index = 1000 * 1000},
- {.frequency = 266 * 1000, .index = 1050 * 1000},
-// {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1125 * 1000},
- {.frequency = 600 * 1000, .index = 1250 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 1000 * 1000},
- {.frequency = 240 * 1000 + DDR_FREQ_VIDEO, .index = 1050 * 1000},
- {.frequency = 300 * 1000 + DDR_FREQ_NORMAL, .index = 1075 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-#endif
-#endif
-/******************************** arm dvfs frequency volt table end **********************************/
-//#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
-//static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
-//static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
-
-void __init board_clock_init(void)
-{
- rk30_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
- //dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "cpu"), dvfs_arm_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
-}
-
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk30_fixup,
- .reserve = &rk30_reserve,
- .map_io = rk30_map_io,
- .init_irq = rk30_init_irq,
- .timer = &rk30_timer,
- .init_machine = machine_rk30_board_init,
-MACHINE_END
+++ /dev/null
-/* linux/arch/arm/mach-rk30/clock_data.c
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/hardirq.h>
-#include <mach/cru.h>
-#include <mach/iomux.h>
-#include <mach/clock.h>
-#include <mach/pmu.h>
-#include <mach/dvfs.h>
-#include <mach/ddr.h>
-#include <mach/board.h>
-#include <plat/efuse.h>
-
-#define MHZ (1000*1000)
-#define KHZ (1000)
-#define CLK_LOOPS_JIFFY_REF 11996091ULL
-#define CLK_LOOPS_RATE_REF (1200) //Mhz
-#define CLK_LOOPS_RECALC(new_rate) div_u64(CLK_LOOPS_JIFFY_REF*(new_rate),CLK_LOOPS_RATE_REF*MHZ)
-void rk30_clk_dump_regs(void);
-#if 0
-//flags bit
-//has extern 27mhz
-#define CLK_FLG_EXT_27MHZ (1<<0)
-//max i2s rate
-#define CLK_FLG_MAX_I2S_12288KHZ (1<<1)
-#define CLK_FLG_MAX_I2S_22579_2KHZ (1<<2)
-#define CLK_FLG_MAX_I2S_24576KHZ (1<<3)
-#define CLK_FLG_MAX_I2S_49152KHZ (1<<4)
-//uart 1m\3m
-#define CLK_FLG_UART_1_3M (1<<5)
-#endif
-#define ARCH_RK31
-
-struct apll_clk_set {
- unsigned long rate;
- u32 pllcon0;
- u32 pllcon1;
- u32 pllcon2; //nb=bwadj+1;0:11;nb=nf/2
- u32 rst_dly;//us
- u32 clksel0;
- u32 clksel1;
- unsigned long lpj;
-};
-struct pll_clk_set {
- unsigned long rate;
- u32 pllcon0;
- u32 pllcon1;
- u32 pllcon2; //nb=bwadj+1;0:11;nb=nf/2
- u32 rst_dly;//us
-};
-
-#define SET_PLL_DATA(_pll_id,_table) \
-{\
- .id=(_pll_id),\
- .table=(_table),\
-}
-
-
-#define _PLL_SET_CLKS(_mhz, nr, nf, no) \
-{ \
- .rate = (_mhz) * KHZ, \
- .pllcon0 = PLL_CLKR_SET(nr)|PLL_CLKOD_SET(no), \
- .pllcon1 = PLL_CLKF_SET(nf),\
- .rst_dly=((nr*500)/24+1),\
-}
-
-
-#define _APLL_SET_LPJ(_mhz) \
- .lpj= (CLK_LOOPS_JIFFY_REF * _mhz)/CLK_LOOPS_RATE_REF
-
-
-#define _APLL_SET_CLKS(_mhz, nr, nf, no, _periph_div, _axi_core_div,\
- _axi_div,_ahb_div, _apb_div,_ahb2apb) \
-{ \
- .rate = _mhz * MHZ, \
- .pllcon0 = PLL_CLKR_SET(nr) | PLL_CLKOD_SET(no), \
- .pllcon1 = PLL_CLKF_SET(nf),\
- .clksel0 = CORE_PERIPH_W_MSK | CORE_PERIPH_##_periph_div,\
- .clksel1 = CORE_ACLK_W_MSK | CORE_ACLK_##_axi_core_div,\
- _APLL_SET_LPJ(_mhz),\
- .rst_dly=((nr*500)/24+1),\
-}
-
-#define CRU_DIV_SET(mask,shift,max) \
- .div_mask=(mask),\
-.div_shift=(shift),\
-.div_max=(max)
-
-
-#define CRU_SRC_SET(mask,shift ) \
- .src_mask=(mask),\
-.src_shift=(shift)
-
-#define CRU_PARENTS_SET(parents_array) \
- .parents=(parents_array),\
-.parents_num=ARRAY_SIZE((parents_array))
-
-#define CRU_GATE_MODE_SET(_func,_IDX) \
- .mode=_func,\
-.gate_idx=(_IDX)
-
-struct clk_src_sel {
- struct clk *parent;
- u8 value;//crt bit
- u8 flag;
- //selgate
-};
-
-#define GATE_CLK(NAME,PARENT,ID) \
- static struct clk clk_##NAME = { \
- .name = #NAME, \
- .parent = &PARENT, \
- .mode = gate_mode, \
- .gate_idx = CLK_GATE_##ID, \
- }
-#ifdef RK30_CLK_OFFBOARD_TEST
-u32 TEST_GRF_REG[0x240];
-u32 TEST_CRU_REG[0x240];
-#define cru_readl(offset) (TEST_CRU_REG[offset/4])
-
-u32 cru_writel_is_pr(u32 offset)
-{
- return (offset == 0x4000);
-}
-void cru_writel(u32 v, u32 offset)
-{
-
- u32 mask_v = v >> 16;
- TEST_CRU_REG[offset/4] &= (~mask_v);
-
- v &= (mask_v);
-
- TEST_CRU_REG[offset/4] |= v;
- TEST_CRU_REG[offset/4] &= 0x0000ffff;
-
- if(cru_writel_is_pr(offset)) {
- CLKDATA_DBG("cru w offset=%d,set=%x,reg=%x\n", offset, v, TEST_CRU_REG[offset/4]);
-
- }
-
-}
-void cru_writel_i2s(u32 v, u32 offset)
-{
- TEST_CRU_REG[offset/4] = v;
-}
-#define cru_writel_frac(v,offset) cru_writel_i2s((v),(offset))
-
-#define regfile_readl(offset) (0xffffffff)
-//#define pmu_readl(offset) readl(RK30_GRF_BASE + offset)
-void rk30_clkdev_add(struct clk_lookup *cl);
-#else
-#define regfile_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
-#define regfile_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
-#define cru_readl(offset) readl_relaxed(RK30_CRU_BASE + offset)
-#define cru_writel(v, offset) do { writel_relaxed(v, RK30_CRU_BASE + offset); dsb(); } while (0)
-
-#define cru_writel_frac(v,offset) cru_writel((v),(offset))
-#endif
-
-//#define DEBUG
-#ifdef DEBUG
-#define CLKDATA_DBG(fmt, args...) printk(KERN_DEBUG "CLKDATA_DBG:\t"fmt, ##args)
-#define CLKDATA_LOG(fmt, args...) printk(KERN_INFO "CLKDATA_LOG:\t"fmt, ##args)
-#else
-#define CLKDATA_DBG(fmt, args...) do {} while(0)
-#define CLKDATA_LOG(fmt, args...) do {} while(0)
-#endif
-#define CLKDATA_ERR(fmt, args...) printk(KERN_ERR "CLKDATA_ERR:\t"fmt, ##args)
-#define CLKDATA_WARNNING(fmt, args...) printk("CLKDATA_WANNING:\t"fmt, ##args)
-
-
-#define get_cru_bits(con,mask,shift)\
- ((cru_readl((con)) >> (shift)) & (mask))
-
-#define set_cru_bits_w_msk(val,mask,shift,con)\
- cru_writel(((mask)<<(shift+16))|((val)<<(shift)),(con))
-
-
-#define PLLS_IN_NORM(pll_id) (((cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id))==(PLL_MODE_NORM(pll_id)&PLL_MODE_MSK(pll_id)))\
- &&!(cru_readl(PLL_CONS(pll_id,3))&PLL_BYPASS))
-
-
-static u32 rk30_clock_flags = 0;
-static struct clk codec_pll_clk;
-static struct clk general_pll_clk;
-static struct clk arm_pll_clk;
-static unsigned long lpj_gpll;
-static unsigned int __initdata armclk = 504 * MHZ;
-
-
-/************************clk recalc div rate*********************************/
-
-//for free div
-static unsigned long clksel_recalc_div(struct clk *clk)
-{
- u32 div = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
-
- unsigned long rate = clk->parent->rate / div;
- pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, div);
- return rate;
-}
-
-//for div 1 2 4 2^n
-static unsigned long clksel_recalc_shift(struct clk *clk)
-{
- u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift);
- unsigned long rate = clk->parent->rate >> shift;
- pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
- return rate;
-}
-
-
-static unsigned long clksel_recalc_shift_2(struct clk *clk)
-{
- u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
- unsigned long rate = clk->parent->rate >> shift;
- pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
- return rate;
-}
-
-static unsigned long clksel_recalc_parent_rate(struct clk *clk)
-{
- unsigned long rate = clk->parent->rate;
- pr_debug("%s new clock rate is %lu\n", clk->name, rate);
- return rate;
-}
-/********************************set div rate***********************************/
-
-//for free div
-static int clksel_set_rate_freediv(struct clk *clk, unsigned long rate)
-{
- u32 div;
- for (div = 0; div < clk->div_max; div++) {
- u32 new_rate = clk->parent->rate / (div + 1);
- if (new_rate <= rate) {
- set_cru_bits_w_msk(div, clk->div_mask, clk->div_shift, clk->clksel_con);
- //clk->rate = new_rate;
- pr_debug("clksel_set_rate_freediv for clock %s to rate %ld (div %d)\n",
- clk->name, rate, div + 1);
- return 0;
- }
- }
- return -ENOENT;
-}
-
-//for div 1 2 4 2^n
-static int clksel_set_rate_shift(struct clk *clk, unsigned long rate)
-{
- u32 shift;
- for (shift = 0; (1 << shift) < clk->div_max; shift++) {
- u32 new_rate = clk->parent->rate >> shift;
- if (new_rate <= rate) {
- set_cru_bits_w_msk(shift, clk->div_mask, clk->div_shift, clk->clksel_con);
- clk->rate = new_rate;
- pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n",
- clk->name, rate, shift);
- return 0;
- }
- }
- return -ENOENT;
-}
-
-//for div 2 4 2^n
-static int clksel_set_rate_shift_2(struct clk *clk, unsigned long rate)
-{
- u32 shift;
-
- for (shift = 1; (1 << shift) < clk->div_max; shift++) {
- u32 new_rate = clk->parent->rate >> shift;
- if (new_rate <= rate) {
- set_cru_bits_w_msk(shift - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
- clk->rate = new_rate;
- pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n",
- clk->name, rate, shift);
- return 0;
- }
- }
- return -ENOENT;
-}
-
-
-//for div 1 2 4 2*n
-static int clksel_set_rate_even(struct clk *clk, unsigned long rate)
-{
- u32 div = 0, new_rate = 0;
- for (div = 1; div < clk->div_max; div++) {
- if (div >= 3 && div % 2 != 0)
- continue;
- new_rate = clk->parent->rate / div;
- if (new_rate <= rate) {
- set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
- clk->rate = new_rate;
- pr_debug("%s for clock %s to rate %ld (even div = %d)\n",
- __func__, clk->name, rate, div);
- return 0;
- }
- }
- return -ENOENT;
-}
-
-static u32 clk_get_evendiv(unsigned long rate_out, unsigned long rate , u32 div_max)
-{
- u32 div;
- unsigned long new_rate;
- for (div = 1; div < div_max; div += 2) {
- new_rate = rate / (div + 1);
- if (new_rate <= rate_out) {
- return div + 1;
- }
- }
- return div_max ? div_max : 1;
-}
-
-static u32 clk_get_freediv(unsigned long rate_out, unsigned long rate , u32 div_max)
-{
- u32 div;
- unsigned long new_rate;
- for (div = 0; div < div_max; div++) {
- new_rate = rate / (div + 1);
- if (new_rate <= rate_out) {
- return div + 1;
- }
- }
- return div_max ? div_max : 1;
-}
-
-struct clk *get_evendiv_parents_div(struct clk *clk, unsigned long rate, u32 *div_out) {
- u32 div[2] = {0, 0};
- unsigned long new_rate[2] = {0, 0};
- u32 i;
-
- if(clk->rate == rate)
- return clk->parent;
- for(i = 0; i < 2; i++) {
- div[i] = clk_get_evendiv(rate, clk->parents[i]->rate, clk->div_max);
- new_rate[i] = clk->parents[i]->rate / div[i];
- if(new_rate[i] == rate) {
- *div_out = div[i];
- return clk->parents[i];
- }
- }
- if(new_rate[0] < new_rate[1])
- i = 1;
- else
- i = 0;
- *div_out = div[i];
- return clk->parents[i];
-}
-
-struct clk *get_freediv_parents_div(struct clk *clk, unsigned long rate, u32 *div_out) {
- u32 div[2] = {0, 0};
- unsigned long new_rate[2] = {0, 0};
- u32 i;
-
- if(clk->rate == rate)
- return clk->parent;
- for(i = 0; i < 2; i++) {
- div[i] = clk_get_freediv(rate, clk->parents[i]->rate, clk->div_max);
- new_rate[i] = clk->parents[i]->rate / div[i];
- if(new_rate[i] == rate) {
- *div_out = div[i];
- return clk->parents[i];
- }
- }
- if(new_rate[0] < new_rate[1])
- i = 1;
- else
- i = 0;
- *div_out = div[i];
- return clk->parents[i];
-}
-
-static int clkset_rate_evendiv_autosel_parents(struct clk *clk, unsigned long rate)
-{
- struct clk *p_clk;
- u32 div, old_div;
- int ret = 0;
- if(clk->rate == rate)
- return 0;
- p_clk = get_evendiv_parents_div(clk, rate, &div);
-
- if(!p_clk)
- return -ENOENT;
-
- CLKDATA_DBG("%s %lu,form %s\n", clk->name, rate, p_clk->name);
- if (clk->parent != p_clk) {
- old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con), clk->div_shift, clk->div_mask) + 1;
-
- if(div > old_div) {
- set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
- }
- ret = clk_set_parent_nolock(clk, p_clk);
- if(ret) {
- CLKDATA_ERR("%s can't set %lu,reparent err\n", clk->name, rate);
- return -ENOENT;
- }
- }
- //set div
- set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
- return 0;
-}
-
-static int clkset_rate_freediv_autosel_parents(struct clk *clk, unsigned long rate)
-{
- struct clk *p_clk;
- u32 div, old_div;
- int ret = 0;
- if(clk->rate == rate)
- return 0;
- p_clk = get_freediv_parents_div(clk, rate, &div);
-
- if(!p_clk)
- return -ENOENT;
-
- CLKDATA_DBG("%s %lu,form %s\n", clk->name, rate, p_clk->name);
- if (clk->parent != p_clk) {
- old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con), clk->div_shift, clk->div_mask) + 1;
-
- if(div > old_div) {
- set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
- }
- ret = clk_set_parent_nolock(clk, p_clk);
- if(ret) {
- CLKDATA_ERR("%s can't set %lu,reparent err\n", clk->name, rate);
- return -ENOENT;
- }
- }
- //set div
- set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
- return 0;
-}
-
-//rate==div rate //hdmi
-static int clk_freediv_autosel_parents_set_fixed_rate(struct clk *clk, unsigned long rate)
-{
- struct clk *p_clk;
- u32 div, old_div;
- int ret;
- p_clk = get_freediv_parents_div(clk, rate, &div);
-
- if(!p_clk)
- return -ENOENT;
-
- if((p_clk->rate / div) != rate || (p_clk->rate % div))
- return -ENOENT;
-
- if (clk->parent != p_clk) {
- old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con),
- clk->div_shift, clk->div_mask) + 1;
- if(div > old_div) {
- set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
- }
- ret = clk_set_parent_nolock(clk, p_clk);
- if (ret) {
- CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
- return ret;
- }
- }
- //set div
- set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
- return 0;
-}
-
-/***************************round********************************/
-
-static long clksel_freediv_round_rate(struct clk *clk, unsigned long rate)
-{
- return clk->parent->rate / clk_get_freediv(rate, clk->parent->rate, clk->div_max);
-}
-
-static long clk_freediv_round_autosel_parents_rate(struct clk *clk, unsigned long rate)
-{
- u32 div;
- struct clk *p_clk;
- if(clk->rate == rate)
- return clk->rate;
- p_clk = get_freediv_parents_div(clk, rate, &div);
- if(!p_clk)
- return 0;
- return p_clk->rate / div;
-}
-
-/**************************************others seting************************************/
-
-static struct clk *clksel_get_parent(struct clk *clk) {
- return clk->parents[(cru_readl(clk->clksel_con) >> clk->src_shift) & clk->src_mask];
-}
-static int clksel_set_parent(struct clk *clk, struct clk *parent)
-{
- u32 i;
- if (unlikely(!clk->parents))
- return -EINVAL;
- for (i = 0; (i < clk->parents_num); i++) {
- if (clk->parents[i] != parent)
- continue;
- set_cru_bits_w_msk(i, clk->src_mask, clk->src_shift, clk->clksel_con);
- return 0;
- }
- return -EINVAL;
-}
-
-static int gate_mode(struct clk *clk, int on)
-{
- int idx = clk->gate_idx;
- if (idx >= CLK_GATE_MAX)
- return -EINVAL;
- if(on) {
- cru_writel(CLK_GATE_W_MSK(idx) | CLK_UN_GATE(idx), CLK_GATE_CLKID_CONS(idx));
- //CLKDATA_DBG("un gate id=%d %s(%x),con %x\n",idx,clk->name,
- // CLK_GATE_W_MSK(idx)|CLK_UN_GATE(idx),CLK_GATE_CLKID_CONS(idx));
- } else {
- cru_writel(CLK_GATE_W_MSK(idx) | CLK_GATE(idx), CLK_GATE_CLKID_CONS(idx));
- // CLKDATA_DBG("gate id=%d %s(%x),con%x\n",idx,clk->name,
- // CLK_GATE_W_MSK(idx)|CLK_GATE(idx),CLK_GATE_CLKID_CONS(idx));
- }
- return 0;
-}
-/*****************************frac set******************************************/
-
-static unsigned long clksel_recalc_frac(struct clk *clk)
-{
- unsigned long rate;
- u64 rate64;
- u32 r = cru_readl(clk->clksel_con), numerator, denominator;
- if (r == 0) // FPGA ?
- return clk->parent->rate;
- numerator = r >> 16;
- denominator = r & 0xFFFF;
- rate64 = (u64)clk->parent->rate * numerator;
- do_div(rate64, denominator);
- rate = rate64;
- pr_debug("%s new clock rate is %lu (frac %u/%u)\n", clk->name, rate, numerator, denominator);
- return rate;
-}
-
-static u32 clk_gcd(u32 numerator, u32 denominator)
-{
- u32 a, b;
-
- if (!numerator || !denominator)
- return 0;
- if (numerator > denominator) {
- a = numerator;
- b = denominator;
- } else {
- a = denominator;
- b = numerator;
- }
- while (b != 0) {
- int r = b;
- b = a % b;
- a = r;
- }
-
- return a;
-}
-
-static int frac_div_get_seting(unsigned long rate_out, unsigned long rate,
- u32 *numerator, u32 *denominator)
-{
- u32 gcd_vl;
- gcd_vl = clk_gcd(rate, rate_out);
- CLKDATA_DBG("frac_get_seting rate=%lu,parent=%lu,gcd=%d\n", rate_out, rate, gcd_vl);
-
- if (!gcd_vl) {
- CLKDATA_ERR("gcd=0, i2s frac div is not be supported\n");
- return -ENOENT;
- }
-
- *numerator = rate_out / gcd_vl;
- *denominator = rate / gcd_vl;
-
- CLKDATA_DBG("frac_get_seting numerator=%d,denominator=%d,times=%d\n",
- *numerator, *denominator, *denominator / *numerator);
-
- if (*numerator > 0xffff || *denominator > 0xffff ||
- (*denominator / (*numerator)) < 20) {
- CLKDATA_ERR("can't get a available nume and deno\n");
- return -ENOENT;
- }
-
- return 0;
-
-}
-/* *********************pll **************************/
-
-#define rk30_clock_udelay(a) udelay(a);
-
-/*********************pll lock status**********************************/
-//#define GRF_SOC_CON0 0x15c
-static int pll_wait_lock(int pll_idx)
-{
- u32 pll_state[4] = {1, 0, 2, 3};
- u32 bit = 0x20u << pll_state[pll_idx];
- int delay = 24000000;
-
- while (delay > 0) {
- if (regfile_readl(GRF_SOC_STATUS0) & bit)
- break;
- delay--;
- }
-
- if (delay == 0) {
- CLKDATA_ERR("PLL_ID=%d\npll_con0=%08x\npll_con1=%08x\npll_con2=%08x\npll_con3=%08x\n", pll_idx,
- cru_readl(PLL_CONS(pll_idx, 0)),
- cru_readl(PLL_CONS(pll_idx, 1)),
- cru_readl(PLL_CONS(pll_idx, 2)),
- cru_readl(PLL_CONS(pll_idx, 3)));
- CLKDATA_ERR("wait pll stat:%8x bit 0x%x time out!\n", regfile_readl(GRF_SOC_STATUS0), bit);
-
- rk30_clock_udelay(1000);
- return -1;
- }
-
- return 0;
-}
-
-
-
-/***************************pll function**********************************/
-static unsigned long pll_clk_recalc(u32 pll_id, unsigned long parent_rate)
-{
- unsigned long rate;
-
- if (PLLS_IN_NORM(pll_id)) {
- u32 pll_con0 = cru_readl(PLL_CONS(pll_id, 0));
- u32 pll_con1 = cru_readl(PLL_CONS(pll_id, 1));
-
-
- u64 rate64 = (u64)parent_rate * PLL_NF(pll_con1);
-
- /*
- CLKDATA_DBG("selcon con0(%x) %x,con1(%x)%x, rate64 %llu\n",PLL_CONS(pll_id,0),pll_con0
- ,PLL_CONS(pll_id,1),pll_con1, rate64);
- */
-
-
- //CLKDATA_DBG("pll id=%d con0=%x,con1=%x,parent=%lu\n",pll_id,pll_con0,pll_con1,parent_rate);
- //CLKDATA_DBG("first pll id=%d rate is %lu (NF %d NR %d NO %d)\n",
- //pll_id, rate, PLL_NF(pll_con1), PLL_NR(pll_con0), 1 << PLL_NO(pll_con0));
-
- do_div(rate64, PLL_NR(pll_con0));
- do_div(rate64, PLL_NO(pll_con0));
-
- rate = rate64;
- /*
- CLKDATA_DBG("pll_clk_recalc id=%d rate=%lu (NF %d NR %d NO %d) rate64=%llu\n",
- pll_id, rate, PLL_NF(pll_con1), PLL_NR(pll_con0),PLL_NO(pll_con0), rate64);
- */
- } else {
- rate = parent_rate;
- CLKDATA_DBG("pll_clk_recalc id=%d rate=%lu by pass mode\n", pll_id, rate);
- }
- return rate;
-}
-static unsigned long plls_clk_recalc(struct clk *clk)
-{
- return pll_clk_recalc(clk->pll->id, clk->parent->rate);
-}
-
-static int pll_clk_set_rate(struct pll_clk_set *clk_set, u8 pll_id)
-{
- //enter slowmode
- cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
- cru_writel((0x1<<(16+1))|(0x1<<1), PLL_CONS(pll_id, 3));
- dsb();
- dsb();
- dsb();
- dsb();
- dsb();
- dsb();
- cru_writel(clk_set->pllcon0, PLL_CONS(pll_id, 0));
- cru_writel(clk_set->pllcon1, PLL_CONS(pll_id, 1));
-
- rk30_clock_udelay(1);
- cru_writel((0x1<<(16+1)), PLL_CONS(pll_id, 3));
-
- pll_wait_lock(pll_id);
-
- //return form slow
- cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
-
- /*
- CLKDATA_ERR("pll reg id=%d,con0=%x,con1=%x,mode=%x\n",pll_id,
- cru_readl(PLL_CONS(pll_id,0)),(PLL_CONS(pll_id,1)),cru_readl(CRU_MODE_CON));
- */
-
- return 0;
-}
-static int gpll_clk_set_rate(struct clk *c, unsigned long rate)
-{
- struct _pll_data *pll_data = c->pll;
- struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
-
- while(clk_set->rate) {
- if (clk_set->rate == rate) {
- break;
- }
- clk_set++;
- }
- if(clk_set->rate == rate) {
- pll_clk_set_rate(clk_set, pll_data->id);
- lpj_gpll = CLK_LOOPS_RECALC(rate);
- } else {
- CLKDATA_ERR("gpll is no corresponding rate=%lu\n", rate);
- return -1;
- }
- return 0;
-}
-
-#define PLL_FREF_MIN (183*KHZ)
-#define PLL_FREF_MAX (1500*MHZ)
-
-#define PLL_FVCO_MIN (300*MHZ)
-#define PLL_FVCO_MAX (1500*MHZ)
-
-#define PLL_FOUT_MIN (18750*KHZ)
-#define PLL_FOUT_MAX (1500*MHZ)
-
-#define PLL_NF_MAX (65536)
-#define PLL_NR_MAX (64)
-#define PLL_NO_MAX (64)
-
-static int pll_clk_get_set(unsigned long fin_hz, unsigned long fout_hz, u32 *clk_nr, u32 *clk_nf, u32 *clk_no)
-{
- u32 nr, nf, no, nonr;
- u32 n;
- u32 YFfenzi;
- u32 YFfenmu;
- unsigned long fref, fvco, fout;
- u32 gcd_val = 0;
-
- CLKDATA_DBG("pll_clk_get_set fin=%lu,fout=%lu\n", fin_hz, fout_hz);
- if(!fin_hz || !fout_hz || fout_hz == fin_hz)
- return 0;
- gcd_val = clk_gcd(fin_hz, fout_hz);
- YFfenzi = fout_hz / gcd_val;
- YFfenmu = fin_hz / gcd_val;
-
- for(n = 1;; n++) {
- nf = YFfenzi * n;
- nonr = YFfenmu * n;
- if(nf > PLL_NF_MAX || nonr > (PLL_NO_MAX * PLL_NR_MAX))
- break;
- for(no = 1; no <= PLL_NO_MAX; no++) {
- if(!(no == 1 || !(no % 2)))
- continue;
-
- if(nonr % no)
- continue;
- nr = nonr / no;
-
- if(nr > PLL_NR_MAX) //PLL_NR_MAX
- continue;
-
- fref = fin_hz / nr;
- if(fref < PLL_FREF_MIN || fref > PLL_FREF_MAX)
- continue;
-
- fvco = (fin_hz / nr) * nf;
- if(fvco < PLL_FVCO_MIN || fvco > PLL_FVCO_MAX)
- continue;
- fout = fvco / no;
- if(fout < PLL_FOUT_MIN || fout > PLL_FOUT_MAX)
- continue;
- *clk_nr = nr;
- *clk_no = no;
- *clk_nf = nf;
- return 1;
-
- }
-
- }
- return 0;
-}
-
-static int pll_clk_mode(struct clk *clk, int on)
-{
- u8 pll_id = clk->pll->id;
- u32 nr = PLL_NR(cru_readl(PLL_CONS(pll_id, 0)));
- u32 dly = (nr * 500) / 24 + 1;
- CLKDATA_DBG("pll_mode %s(%d)\n", clk->name, on);
- if (on) {
- cru_writel(PLL_PWR_ON | PLL_PWR_DN_W_MSK, PLL_CONS(pll_id, 3));
- rk30_clock_udelay(dly);
- pll_wait_lock(pll_id);
- cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
- } else {
- cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
- cru_writel(PLL_PWR_DN | PLL_PWR_DN_W_MSK, PLL_CONS(pll_id, 3));
- }
- return 0;
-}
-
-static int cpll_clk_set_rate(struct clk *c, unsigned long rate)
-{
- struct _pll_data *pll_data = c->pll;
- struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
- struct pll_clk_set temp_clk_set;
- u32 clk_nr, clk_nf, clk_no;
-
-
- while(clk_set->rate) {
- if (clk_set->rate == rate) {
- break;
- }
- clk_set++;
- }
- if(clk_set->rate == rate) {
- CLKDATA_DBG("cpll get a rate\n");
- pll_clk_set_rate(clk_set, pll_data->id);
-
- } else {
- CLKDATA_DBG("cpll get auto calc a rate\n");
- if(pll_clk_get_set(c->parent->rate, rate, &clk_nr, &clk_nf, &clk_no) == 0) {
- pr_err("cpll auto set rate error\n");
- return -ENOENT;
- }
- CLKDATA_DBG("cpll auto ger rate set nr=%d,nf=%d,no=%d\n", clk_nr, clk_nf, clk_no);
- temp_clk_set.pllcon0 = PLL_CLKR_SET(clk_nr) | PLL_CLKOD_SET(clk_no);
- temp_clk_set.pllcon1 = PLL_CLKF_SET(clk_nf);
- temp_clk_set.rst_dly = (clk_nr * 500) / 24 + 1;
- pll_clk_set_rate(&temp_clk_set, pll_data->id);
-
- }
- return 0;
-}
-
-
-/* ******************fixed input clk ***********************************************/
-static struct clk xin24m = {
- .name = "xin24m",
- .rate = 24 * MHZ,
- .flags = RATE_FIXED,
-};
-#if 0
-static struct clk xin27m = {
- .name = "xin27m",
- .rate = 27 * MHZ,
- //CLK_GATE_XIN27M
- .flags = RATE_FIXED,
-
-};
-#endif
-static struct clk clk_12m = {
- .name = "clk_12m",
- .parent = &xin24m,
- .rate = 12 * MHZ,
- .flags = RATE_FIXED,
-};
-
-/************************************pll func***************************/
-static const struct apll_clk_set *arm_pll_clk_get_best_pll_set(unsigned long rate,
- struct apll_clk_set *tables) {
- const struct apll_clk_set *ps, *pt;
-
- /* find the arm_pll we want. */
- ps = pt = tables;
- while (pt->rate) {
- if (pt->rate == rate) {
- ps = pt;
- break;
- }
- // we are sorted, and ps->rate > pt->rate.
- if ((pt->rate > rate || (rate - pt->rate < ps->rate - rate)))
- ps = pt;
- if (pt->rate < rate)
- break;
- pt++;
- }
- //CLKDATA_DBG("arm pll best rate=%lu\n",ps->rate);
- return ps;
-}
-static long arm_pll_clk_round_rate(struct clk *clk, unsigned long rate)
-{
- return arm_pll_clk_get_best_pll_set(rate, clk->pll->table)->rate;
-}
-#if 1
-struct arm_clks_div_set {
- u32 rate;
- u32 clksel0;
- u32 clksel1;
-};
-
-#define _arm_clks_div_set(_mhz,_periph_div,_axi_div,_ahb_div, _apb_div,_ahb2apb) \
-{ \
- .rate =_mhz,\
- .clksel0 = CORE_PERIPH_W_MSK|CORE_PERIPH_##_periph_div,\
- .clksel1 = CORE_ACLK_W_MSK|CORE_ACLK_##_axi_div\
- |ACLK_HCLK_W_MSK|ACLK_HCLK_##_ahb_div\
- |ACLK_PCLK_W_MSK|ACLK_PCLK_##_apb_div\
- |AHB2APB_W_MSK |AHB2APB_##_ahb2apb,\
-}
-struct arm_clks_div_set arm_clk_div_tlb[] = {
- _arm_clks_div_set(50 , 2, 11, 11, 11, 11),//25,50,50,50,50
- _arm_clks_div_set(100 , 4, 11, 21, 21, 11),//25,100,50,50,50
- _arm_clks_div_set(150 , 4, 11, 21, 21, 11),//37,150,75,75,75
- _arm_clks_div_set(200 , 8, 21, 21, 21, 11),//25,100,50,50,50
- _arm_clks_div_set(300 , 8, 21, 21, 21, 11),//37,150,75,75,75
- _arm_clks_div_set(400 , 8, 21, 21, 41, 21),//50,200,100,50,50
- _arm_clks_div_set(0 , 2, 11, 11, 11, 11),//25,50,50,50,50
-};
-struct arm_clks_div_set *arm_clks_get_div(u32 rate) {
- int i = 0;
- for(i = 0; arm_clk_div_tlb[i].rate != 0; i++) {
- if(arm_clk_div_tlb[i].rate >= rate)
- return &arm_clk_div_tlb[i];
- }
- return NULL;
-}
-
-#endif
-
-static int arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
-{
- unsigned long flags;
- const struct apll_clk_set *ps;
- u32 pll_id = clk->pll->id;
- u32 temp_div;
- u32 old_aclk_div = 0, new_aclk_div;
-
- ps = arm_pll_clk_get_best_pll_set(rate, (struct apll_clk_set *)clk->pll->table);
-
- old_aclk_div = GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
- new_aclk_div = GET_CORE_ACLK_VAL(ps->clksel1 & CORE_ACLK_MSK);
-
- CLKDATA_LOG("apll will set rate(%lu) tlb con(%x,%x,%x),sel(%x,%x)\n",
- ps->rate, ps->pllcon0, ps->pllcon1, ps->pllcon2, ps->clksel0, ps->clksel1);
-
- if(general_pll_clk.rate > clk->rate) {
- temp_div = clk_get_freediv(clk->rate, general_pll_clk.rate, 10);
- } else {
- temp_div = 1;
- }
-
- // ungating cpu gpll path
- //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_UN_GATE(CLK_GATE_CPU_GPLL_PATH),
- // CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
-
- local_irq_save(flags);
- //div arm clk for gpll
-
- cru_writel(CORE_CLK_DIV_W_MSK|CORE_CLK_DIV(temp_div), CRU_CLKSELS_CON(0));
- cru_writel(CORE_SEL_PLL_W_MSK|CORE_SEL_GPLL, CRU_CLKSELS_CON(0));
-
- loops_per_jiffy = lpj_gpll / temp_div;
- smp_wmb();
-
- /*if core src don't select gpll ,apll neet to enter slow mode */
- //cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
- do{
- cru_writel(ps->pllcon0, PLL_CONS(pll_id, 0));
- cru_writel(ps->pllcon1, PLL_CONS(pll_id, 1));
-
- cru_writel((0x1<<(16+1))|(0x1<<1), PLL_CONS(pll_id, 3));
-
- if (!(0x02 & cru_readl(PLL_CONS(pll_id, 3))))
- CLKDATA_ERR("enter pll pwdn err: pll_id(%d), PLL_CONS3(%x)\n", pll_id, cru_readl(PLL_CONS(pll_id, 3)));
-
-
- cru_writel(ps->pllcon0, PLL_CONS(pll_id, 0));
- cru_writel(ps->pllcon1, PLL_CONS(pll_id, 1));
-
- if (((ps->pllcon0&0xffff) != cru_readl(PLL_CONS(pll_id, 0)))
- ||((ps->pllcon1&0xffff) != cru_readl(PLL_CONS(pll_id, 1)))){
- CLKDATA_ERR("set pll err:pllcon0:%x,pllcon1:%x\n", ps->pllcon0, ps->pllcon1);
- CLKDATA_ERR("set pll err:id(%d),con0(%x), con1(%x)\n",
- pll_id, cru_readl(PLL_CONS(pll_id, 0)), cru_readl(PLL_CONS(pll_id, 1)));
- }
-
- rk30_clock_udelay(1);
-
- cru_writel((0x1<<(16+1)), PLL_CONS(pll_id, 3));
-
- if (0x02 & cru_readl(PLL_CONS(pll_id, 3)))
- printk("quit pwdn err:pll_id(%d), PLL_CONS3:(%x)\n", pll_id, cru_readl(PLL_CONS(pll_id, 3)));
- } while (pll_wait_lock(pll_id));
-
- //return form slow
- //cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
- //reparent to apll
-
- if(new_aclk_div>=old_aclk_div) {
- cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
- cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
- }
-
- cru_writel(CORE_SEL_PLL_W_MSK | CORE_SEL_APLL, CRU_CLKSELS_CON(0));
- if(old_aclk_div>new_aclk_div) {
- cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
- cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
- }
-
- cru_writel(CORE_CLK_DIV_W_MSK|CORE_CLK_DIV(1), CRU_CLKSELS_CON(0));
-
- loops_per_jiffy = ps->lpj;
- smp_wmb();
-
- //CLKDATA_DBG("apll set loops_per_jiffy =%lu,rate(%lu)\n",loops_per_jiffy,ps->rate);
-
- local_irq_restore(flags);
-
- //gate gpll path
- // FIXME
- //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_GATE(CLK_GATE_CPU_GPLL_PATH)
- // , CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
-
- CLKDATA_LOG("apll set over con(%x,%x,%x,%x),sel(%x,%x)\n", cru_readl(PLL_CONS(pll_id, 0)),
- cru_readl(PLL_CONS(pll_id, 1)), cru_readl(PLL_CONS(pll_id, 2)),
- cru_readl(PLL_CONS(pll_id, 3)), cru_readl(CRU_CLKSELS_CON(0)),
- cru_readl(CRU_CLKSELS_CON(1)));
- return 0;
-}
-
-
-/************************************pll clocks***************************/
-
-static const struct apll_clk_set apll_clks[] = {
- //_APLL_SET_CLKS(_mhz, nr, nf, no, _periph_div,
- // _axi_core_div, _axi_div, _ahb_div, _apb_div, _ahb2apb)
- _APLL_SET_CLKS(1992, 1, 83, 1, 8, 81, 81, 21, 41, 21),
- _APLL_SET_CLKS(1896, 1, 79, 1, 8, 81, 81, 21, 41, 21),
- _APLL_SET_CLKS(1800, 1, 75, 1, 8, 81, 81, 21, 41, 21),
- _APLL_SET_CLKS(1704, 1, 71, 1, 8, 81, 81, 21, 41, 21),
- _APLL_SET_CLKS(1608, 1, 67, 1, 8, 41, 41, 21, 41, 21),
- _APLL_SET_CLKS(1560, 1, 65, 1, 8, 41, 41, 21, 41, 21),
- _APLL_SET_CLKS(1512, 1, 63, 1, 8, 41, 41, 21, 41, 21),
- _APLL_SET_CLKS(1464, 1, 61, 1, 8, 41, 41, 21, 41, 21),
- _APLL_SET_CLKS(1416, 1, 59, 1, 8, 41, 41, 21, 41, 21),
- _APLL_SET_CLKS(1368, 1, 57, 1, 8, 41, 41, 21, 41, 21),
- _APLL_SET_CLKS(1320, 1, 55, 1, 8, 41, 41, 21, 41, 21),
- _APLL_SET_CLKS(1296, 1, 54, 1, 8, 41, 41, 21, 41, 21),
- _APLL_SET_CLKS(1272, 1, 53, 1, 8, 41, 41, 21, 41, 21),
- _APLL_SET_CLKS(1200, 1, 50, 1, 8, 41, 41, 21, 41, 21),
- _APLL_SET_CLKS(1176, 1, 49, 1, 8, 41, 41, 21, 41, 21),
- _APLL_SET_CLKS(1128, 1, 47, 1, 8, 41, 41, 21, 41, 21),
- _APLL_SET_CLKS(1104, 1, 46, 1, 8, 41, 41, 21, 41, 21),
- _APLL_SET_CLKS(1008, 1, 84, 2, 8, 41, 31, 21, 41, 21),
- _APLL_SET_CLKS(912, 1, 76, 2, 8, 41, 31, 21, 41, 21),
- _APLL_SET_CLKS(888, 1, 74, 2, 8, 41, 31, 21, 41, 21),
- _APLL_SET_CLKS(816 , 1, 68, 2, 8, 41, 31, 21, 41, 21),
- _APLL_SET_CLKS(792 , 1, 66, 2, 8, 41, 31, 21, 41, 21),
- _APLL_SET_CLKS(696 , 1, 58, 2, 8, 41, 31, 21, 41, 21),
- _APLL_SET_CLKS(600 , 1, 50, 2, 4, 41, 31, 21, 41, 21),
- _APLL_SET_CLKS(552 , 1, 92, 4, 4, 41, 21, 21, 41, 21),
- _APLL_SET_CLKS(504 , 1, 84, 4, 4, 41, 21, 21, 41, 21),
- _APLL_SET_CLKS(408 , 1, 68, 4, 4, 21, 21, 21, 41, 21),
- _APLL_SET_CLKS(312 , 1, 52, 4, 2, 21, 21, 21, 21, 11),
- _APLL_SET_CLKS(252 , 1, 84, 8, 2, 21, 21, 21, 21, 11),
- _APLL_SET_CLKS(216 , 1, 72, 8, 2, 21, 21, 21, 21, 11),
- _APLL_SET_CLKS(126 , 1, 84, 16, 2, 11, 21, 11, 11, 11),
- _APLL_SET_CLKS(48 , 1, 64, 32, 2, 11, 11, 11, 11, 11),
- _APLL_SET_CLKS(0 , 1, 21, 4, 2, 11, 11, 11, 11, 11),
-
-};
-static struct _pll_data apll_data = SET_PLL_DATA(APLL_ID, (void *)apll_clks);
-static struct clk arm_pll_clk = {
- .name = "arm_pll",
- .parent = &xin24m,
- .mode = pll_clk_mode,
- .recalc = plls_clk_recalc,
- .set_rate = arm_pll_clk_set_rate,
- .round_rate = arm_pll_clk_round_rate,
- .pll = &apll_data,
-};
-
-static int ddr_pll_clk_set_rate(struct clk *clk, unsigned long rate)
-{
- /* do nothing here */
- return 0;
-}
-static struct _pll_data dpll_data = SET_PLL_DATA(DPLL_ID, NULL);
-static struct clk ddr_pll_clk = {
- .name = "ddr_pll",
- .parent = &xin24m,
- .recalc = plls_clk_recalc,
- .set_rate = ddr_pll_clk_set_rate,
- .pll = &dpll_data,
-};
-
-static const struct pll_clk_set cpll_clks[] = {
- _PLL_SET_CLKS(360000, 1, 60, 4),
- _PLL_SET_CLKS(408000, 1, 68, 4),
- _PLL_SET_CLKS(456000, 1, 76, 4),
- _PLL_SET_CLKS(504000, 1, 84, 4),
- _PLL_SET_CLKS(552000, 1, 46, 2),
- _PLL_SET_CLKS(594000, 2, 198, 4),
- _PLL_SET_CLKS(600000, 1, 50, 2),
- _PLL_SET_CLKS(742500, 8, 495, 2),
- _PLL_SET_CLKS(768000, 1, 64, 2),
- _PLL_SET_CLKS(798000, 2, 133, 2),
- _PLL_SET_CLKS(1188000, 2, 99, 1),
- _PLL_SET_CLKS( 0, 4, 133, 1),
-};
-static struct _pll_data cpll_data = SET_PLL_DATA(CPLL_ID, (void *)cpll_clks);
-static struct clk codec_pll_clk = {
- .name = "codec_pll",
- .parent = &xin24m,
- .mode = pll_clk_mode,
- .recalc = plls_clk_recalc,
- .set_rate = cpll_clk_set_rate,
- .pll = &cpll_data,
-};
-
-static const struct pll_clk_set gpll_clks[] = {
- _PLL_SET_CLKS(148500, 2, 99, 8),
- _PLL_SET_CLKS(297000, 2, 198, 8),
- _PLL_SET_CLKS(300000, 1, 50, 4),
- _PLL_SET_CLKS(384000, 2, 128, 4),
- _PLL_SET_CLKS(594000, 2, 198, 4),
- _PLL_SET_CLKS(1188000, 2, 99, 1),
- _PLL_SET_CLKS(1200000, 1, 50, 1),
- _PLL_SET_CLKS(0, 0, 0, 0),
-};
-static struct _pll_data gpll_data = SET_PLL_DATA(GPLL_ID, (void *)gpll_clks);
-static struct clk general_pll_clk = {
- .name = "general_pll",
- .parent = &xin24m,
- .recalc = plls_clk_recalc,
- .set_rate = gpll_clk_set_rate,
- .pll = &gpll_data
-};
-/********************************clocks***********************************/
-/* core and cpu setting */
-static int ddr_clk_set_rate(struct clk *c, unsigned long rate)
-{
- return 0;
-}
-
-static long ddr_clk_round_rate(struct clk *clk, unsigned long rate)
-{
- return ddr_set_pll_rk3066b(rate / MHZ, 0) * MHZ;
-}
-static unsigned long ddr_clk_recalc_rate(struct clk *clk)
-{
- u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift);
- unsigned long rate = 0;
-
- clk->parent = clk->get_parent(clk);
- clk->parent->rate = clk->parent->recalc(clk->parent);
- rate = clk->parent->rate >> shift;
-
- pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
- return rate;
-}
-static struct clk *clk_ddr_parents[2] = {&ddr_pll_clk, &general_pll_clk};
-static struct clk clk_ddr = {
- .name = "ddr",
- .parent = &ddr_pll_clk,
- .get_parent = clksel_get_parent,
- .set_parent = clksel_set_parent,
- .recalc = ddr_clk_recalc_rate,
- .set_rate = ddr_clk_set_rate,
- .round_rate = ddr_clk_round_rate,
- .clksel_con = CRU_CLKSELS_CON(26),
- CRU_DIV_SET(0x3, 0, 4),
- CRU_SRC_SET(1, 8),
- CRU_PARENTS_SET(clk_ddr_parents),
-};
-static int arm_core_clk_set_rate(struct clk *c, unsigned long rate)
-{
- int ret;
-
- ret = clk_set_rate_nolock(c->parent, rate);
- if (ret) {
- CLKDATA_ERR("Failed to change clk pll %s to %lu\n", c->name, rate);
- return ret;
- }
- //set arm pll div 1
- set_cru_bits_w_msk(0, c->div_mask, c->div_shift, c->clksel_con);
- return 0;
-}
-static unsigned long arm_core_clk_get_rate(struct clk *c)
-{
- u32 div = (get_cru_bits(c->clksel_con, c->div_mask, c->div_shift) + 1);
- //c->parent->rate=c->parent->recalc(c->parent);
- return c->parent->rate / div;
-}
-static long core_clk_round_rate(struct clk *clk, unsigned long rate)
-{
- u32 div = (get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1);
- return clk_round_rate_nolock(clk->parent, rate) / div;
-}
-
-static int core_clksel_set_parent(struct clk *clk, struct clk *new_prt)
-{
-
- u32 temp_div;
- struct clk *old_prt;
-
- if(clk->parent == new_prt)
- return 0;
- if (unlikely(!clk->parents))
- return -EINVAL;
- CLKDATA_DBG("%s,reparent %s\n", clk->name, new_prt->name);
- //arm
- old_prt = clk->parent;
-
- if(clk->parents[0] == new_prt) {
- new_prt->set_rate(new_prt, 300 * MHZ);
- set_cru_bits_w_msk(0, clk->div_mask, clk->div_shift, clk->clksel_con);
- } else if(clk->parents[1] == new_prt) {
-
- if(new_prt->rate > old_prt->rate) {
- temp_div = clk_get_freediv(old_prt->rate, new_prt->rate, clk->div_max);
- set_cru_bits_w_msk(temp_div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
- }
- set_cru_bits_w_msk(1, clk->src_mask, clk->src_shift, clk->clksel_con);
- new_prt->set_rate(new_prt, 300 * MHZ);
- } else
- return -1;
-
-
- return 0;
-
-}
-
-static int core_gpll_clk_set_rate(struct clk *c, unsigned long rate)
-{
- u32 temp_div;
- u32 old_aclk_div = 0, new_aclk_div;
- struct arm_clks_div_set *temp_clk_div;
- unsigned long arm_gpll_rate, arm_gpll_lpj;
- temp_div = clk_get_freediv(rate, c->parent->rate, c->div_max);
- arm_gpll_rate = c->parent->rate / temp_div;
-
- temp_clk_div = arm_clks_get_div(arm_gpll_rate / MHZ);
- if(!temp_clk_div)
- temp_clk_div = &arm_clk_div_tlb[4];
-
- old_aclk_div = GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
- new_aclk_div = GET_CORE_ACLK_VAL(temp_clk_div->clksel1 & CORE_ACLK_MSK);
- if(c->rate >= rate) {
- arm_gpll_lpj = lpj_gpll / temp_div;
- set_cru_bits_w_msk(temp_div - 1, c->div_mask, c->div_shift, c->clksel_con);
- }
-
- cru_writel((temp_clk_div->clksel1), CRU_CLKSELS_CON(1));
- cru_writel((temp_clk_div->clksel0) | CORE_CLK_DIV(temp_div) | CORE_CLK_DIV_W_MSK,
- CRU_CLKSELS_CON(0));
- if((c->rate < rate)) {
- arm_gpll_lpj = lpj_gpll / temp_div;
- set_cru_bits_w_msk(temp_div - 1, c->div_mask, c->div_shift, c->clksel_con);
- }
- return 0;
-}
-static unsigned long arm_core_gpll_clk_get_rate(struct clk *c)
-{
- return c->parent->rate;
-}
-static struct clk clk_core_gpll_path = {
- .name = "cpu_gpll_path",
- .parent = &general_pll_clk,
- .gate_idx = CLK_GATE_CPU_GPLL_PATH,
- .recalc = arm_core_gpll_clk_get_rate,
- .set_rate = core_gpll_clk_set_rate,
- CRU_GATE_MODE_SET(gate_mode, CLK_GATE_CPU_GPLL_PATH),
-};
-
-
-static struct clk *clk_cpu_parents[2] = {&arm_pll_clk, &clk_core_gpll_path};
-
-static struct clk clk_core = {
- .name = "core",
- .parent = &arm_pll_clk,
- .set_rate = arm_core_clk_set_rate,
- .recalc = arm_core_clk_get_rate,
- .round_rate = core_clk_round_rate,
- .set_parent = core_clksel_set_parent,
- .clksel_con = CRU_CLKSELS_CON(0),
- CRU_DIV_SET(0x1f, 9, 32),
- CRU_SRC_SET(1, 8),
- CRU_PARENTS_SET(clk_cpu_parents),
-};
-#ifdef ARCH_RK31
-static struct clk *clk_cpu_div_parents[2] = {&arm_pll_clk, &general_pll_clk};
-static struct clk clk_cpu_div = {
- .name = "cpu_div",
- .parent = &arm_pll_clk,
- .set_rate = clksel_set_rate_freediv,
- .recalc = clksel_recalc_div,
- .clksel_con = CRU_CLKSELS_CON(0),
- CRU_DIV_SET(0x1f, 0, 32),
- CRU_SRC_SET(1, 5),
- CRU_PARENTS_SET(clk_cpu_div_parents),
-};
-
-#endif
-#ifdef ARCH_RK31
-GATE_CLK(l2c, clk_core, CLK_L2C);
-GATE_CLK(core_dbg, clk_core, CLK_CORE_DBG);
-#endif
-static unsigned long aclk_recalc(struct clk *clk)
-{
- unsigned long rate;
- u32 div = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
-
- BUG_ON(div > 5);
- if (div >= 5)
- div = 8;
- rate = clk->parent->rate / div;
- pr_debug("%s new clock rate is %ld (div %d)\n", clk->name, rate, div);
-
- return rate;
-};
-static struct clk core_periph = {
- .name = "core_periph",
- .parent = &clk_core,
- .gate_idx = CLK_GATE_CORE_PERIPH,
- .recalc = clksel_recalc_shift_2,
- .clksel_con = CRU_CLKSELS_CON(0),
- CRU_DIV_SET(0x3, 6, 16),
-};
-#ifdef ARCH_RK31
-static struct clk aclk_core = {
- .name = "aclk_core",
- .parent = &clk_core,
- .gate_idx = CLK_GATE_ACLK_CORE,
- .recalc = aclk_recalc,
- .clksel_con = CRU_CLKSELS_CON(1),
- CRU_DIV_SET(0x7, 3, 8),
-};
-#endif
-
-static struct clk aclk_cpu = {
- .name = "aclk_cpu",
- .parent = &clk_cpu_div,
- .gate_idx = CLK_GATE_ACLK_CPU,
- .recalc = aclk_recalc,
- .set_rate = clksel_set_rate_shift,
- .clksel_con = CRU_CLKSELS_CON(1),
- CRU_DIV_SET(0x7, 0, 8),
-};
-
-static struct clk hclk_cpu = {
- .name = "hclk_cpu",
- .parent = &aclk_cpu,
- .gate_idx = CLK_GATE_HCLK_CPU,
- .recalc = clksel_recalc_shift,
- .set_rate = clksel_set_rate_shift,
- .clksel_con = CRU_CLKSELS_CON(1),
- CRU_DIV_SET(0x3, 8, 4),
-
-};
-
-static struct clk pclk_cpu = {
- .name = "pclk_cpu",
- .parent = &aclk_cpu,
- .gate_idx = CLK_GATE_PCLK_CPU,
- .recalc = clksel_recalc_shift,
- .set_rate = clksel_set_rate_shift,
- .clksel_con = CRU_CLKSELS_CON(1),
- CRU_DIV_SET(0x3, 12, 8),
-};
-
-static struct clk ahb2apb_cpu = {
- .name = "ahb2apb",
- .parent = &hclk_cpu,
- .recalc = clksel_recalc_shift,
- .set_rate = clksel_set_rate_shift,
- .clksel_con = CRU_CLKSELS_CON(1),
- CRU_DIV_SET(0x3, 14, 4),
-};
-
-
-static struct clk atclk_cpu = {
- .name = "atclk_cpu",
- .parent = &pclk_cpu,
- .gate_idx = CLK_GATE_ATCLK_CPU,
-};
-
-/* GPU setting test */
-#if 0 //for gpu rate test
-
-static int clk_gpu_set_rate(struct clk *clk, unsigned long rate)
-{
- printk("gpu dbg clk %s set %lu\n",clk->name,rate);
- return clksel_set_rate_freediv(clk, rate);
-};
-
-#define clk_gpu_set_rate_callback clk_gpu_set_rate
-#else
-#define clk_gpu_set_rate(clk,rate) clksel_set_rate_freediv((clk),(rate))
-#define clk_gpu_set_rate_callback clksel_set_rate_freediv
-#endif
-
-#define GPU_CORE_ACLK_CTR_TOGETHER
-
-#ifdef GPU_CORE_ACLK_CTR_TOGETHER
-static struct clk aclk_gpu;
-static struct clk clk_gpu;
-
-static int clk_gpu_ref_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret = 0;
- ret=clk_gpu_set_rate(clk, rate);
- if(ret<0)
- return ret;
- ret=clk_set_rate_nolock(&aclk_gpu, rate);
- return ret;
-};
-static long clk_gpu_ref_round_rate(struct clk *clk, unsigned long rate)
-{
- unsigned long rate_gpu;
- rate_gpu=clksel_freediv_round_rate(clk,rate);
-/*
- if(rate_gpu!=clksel_freediv_round_rate(&aclk_gpu,rate))
- {
- CLKDATA_ERR("gpu rate is not equal ack gpu rate in %s\n",__FUNCTION__);
- }
-*/
- return rate_gpu;
-}
-#endif
-
-static struct clk *gpu_parents[2] = {&codec_pll_clk, &general_pll_clk};
-
-static struct clk clk_gpu = {
- .name = "gpu",
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
-#ifdef GPU_CORE_ACLK_CTR_TOGETHER
- .round_rate = clk_gpu_ref_round_rate,
- .set_rate = clk_gpu_ref_set_rate,
-#else
- .round_rate = clksel_freediv_round_rate,
- .set_rate = clk_gpu_set_rate_callback,
-#endif
- .clksel_con = CRU_CLKSELS_CON(33),
- .gate_idx = CLK_GATE_CLK_GPU,
- CRU_DIV_SET(0x1f, 0, 32),
- CRU_SRC_SET(0x1, 7),
- CRU_PARENTS_SET(gpu_parents),
-};
-#ifdef ARCH_RK31
-static struct clk *gpu_aclk_parents[2] = {&codec_pll_clk, &general_pll_clk};
-static struct clk aclk_gpu = {
- .name = "aclk_gpu",
- .recalc = clksel_recalc_div,
- .round_rate = clksel_freediv_round_rate,
- .set_rate = clk_gpu_set_rate_callback,
- .clksel_con = CRU_CLKSELS_CON(34),
- CRU_DIV_SET(0x1f, 0, 32),
- CRU_SRC_SET(0x1, 7),
- CRU_PARENTS_SET(gpu_parents),
-};
-
-#ifdef GPU_CORE_ACLK_CTR_TOGETHER
-static int clk_aclk_gpu_null_set_rate(struct clk *clk, unsigned long rate)
-{
- return 0;
-};
-
-static long clk_aclk_gpu_null_round_rate(struct clk *clk, unsigned long rate)
-{
- return clk->parent->round_rate(clk->parent,rate);
-}
-static unsigned long clk_aclk_gpu_null_recalc_div(struct clk *clk)
-{
- return clk->parent->rate;
-}
-//gpu and gpu together ctr,this clk is following aclk gpu.
-static struct clk aclk_gpu_null = {
- .name = "aclk_gpu_null",
- .parent = &aclk_gpu,
- .recalc = clk_aclk_gpu_null_recalc_div,
- .round_rate = clk_aclk_gpu_null_round_rate,
- .set_rate = clk_aclk_gpu_null_set_rate,
-};
-#endif
-static struct clk aclk_gpu_slv = {
- .name = "aclk_gpu_slv",
- .parent = &aclk_gpu,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_ACLK_GPU_SLV,
-};
-
-static struct clk aclk_gpu_mst = {
- .name = "aclk_gpu_mst",
- .parent = &aclk_gpu,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_ACLK_GPU_MST,
-};
-#endif
-
-/* vcodec setting */
-static unsigned long clksel_recalc_vpu_hclk(struct clk *clk)
-{
- unsigned long rate = clk->parent->rate / 4;
- pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, 4);
- return rate;
-}
-
-static struct clk *aclk_vepu_parents[2] = {&codec_pll_clk, &general_pll_clk};
-
-static struct clk aclk_vepu = {
- .name = "aclk_vepu",
- .parent = &codec_pll_clk,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- //.set_rate = clksel_set_rate_freediv,
- .set_rate = clkset_rate_freediv_autosel_parents,
- .clksel_con = CRU_CLKSELS_CON(32),
- .gate_idx = CLK_GATE_ACLK_VEPU,
- CRU_DIV_SET(0x1f, 0, 32),
- CRU_SRC_SET(0x1, 7),
- CRU_PARENTS_SET(aclk_vepu_parents),
-};
-
-static struct clk *aclk_vdpu_parents[2] = {&codec_pll_clk, &general_pll_clk};
-
-static struct clk aclk_vdpu = {
- .name = "aclk_vdpu",
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- //.set_rate = clksel_set_rate_freediv,
- .set_rate = clkset_rate_freediv_autosel_parents,
- .clksel_con = CRU_CLKSELS_CON(32),
- .gate_idx = CLK_GATE_ACLK_VDPU,
- CRU_DIV_SET(0x1f, 8, 32),
- CRU_SRC_SET(0x1, 15),
- CRU_PARENTS_SET(aclk_vdpu_parents),
-};
-static struct clk hclk_vepu = {
- .name = "hclk_vepu",
- .parent = &aclk_vepu,
- .mode = gate_mode,
- .recalc = clksel_recalc_vpu_hclk,
- .gate_idx = CLK_GATE_HCLK_VEPU,
-};
-
-static struct clk hclk_vdpu = {
- .name = "hclk_vdpu",
- .parent = &aclk_vdpu,
- .mode = gate_mode,
- .recalc = clksel_recalc_vpu_hclk,
- .gate_idx = CLK_GATE_HCLK_VDPU,
-};
-
-/* aclk lcdc setting */
-static struct clk *aclk_lcdc0_parents[] = {&codec_pll_clk, &general_pll_clk};
-
-static struct clk aclk_lcdc0_pre = {
- .name = "aclk_lcdc0_pre",
- .parent = &codec_pll_clk,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clkset_rate_freediv_autosel_parents,
- //.set_rate = clksel_set_rate_freediv,
- .gate_idx = CLK_GATE_ACLK_LCDC0_SRC,
- .clksel_con = CRU_CLKSELS_CON(31),
- CRU_DIV_SET(0x1f, 0, 32),
- CRU_SRC_SET(0x1, 7),
- CRU_PARENTS_SET(aclk_lcdc0_parents),
-};
-
-static struct clk *aclk_lcdc1_parents[] = {&codec_pll_clk, &general_pll_clk};
-
-static struct clk aclk_lcdc1_pre = {
- .name = "aclk_lcdc1_pre",
- .parent = &codec_pll_clk,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clkset_rate_freediv_autosel_parents,
- .gate_idx = CLK_GATE_ACLK_LCDC1_SRC,
- .clksel_con = CRU_CLKSELS_CON(31),
- CRU_DIV_SET(0x1f, 8, 32),
- CRU_SRC_SET(0x1, 15),
- CRU_PARENTS_SET(aclk_lcdc1_parents),
-};
-
-/* aclk/hclk/pclk periph setting */
-static struct clk *aclk_periph_parents[2] = {&general_pll_clk, &codec_pll_clk};
-
-static struct clk aclk_periph = {
- .name = "aclk_periph",
- .parent = &general_pll_clk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_ACLK_PERIPH,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(10),
- CRU_DIV_SET(0x1f, 0, 32),
- CRU_SRC_SET(1, 15),
- CRU_PARENTS_SET(aclk_periph_parents),
-};
-GATE_CLK(periph_src, aclk_periph, PERIPH_SRC);
-
-static struct clk pclk_periph = {
- .name = "pclk_periph",
- .parent = &aclk_periph,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_PCLK_PERIPH,
- .recalc = clksel_recalc_shift,
- .set_rate = clksel_set_rate_shift,
- .clksel_con = CRU_CLKSELS_CON(10),
- CRU_DIV_SET(0x3, 12, 8),
-};
-
-static struct clk hclk_periph = {
- .name = "hclk_periph",
- .parent = &aclk_periph,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_HCLK_PERIPH,
- .recalc = clksel_recalc_shift,
- .set_rate = clksel_set_rate_shift,
- .clksel_con = CRU_CLKSELS_CON(10),
- CRU_DIV_SET(0x3, 8, 4),
-};
-/* dclk lcdc setting */
-// FIXME
-static int clksel_set_rate_hdmi(struct clk *clk, unsigned long rate)
-{
- u32 div, old_div;
- int i;
- unsigned long new_rate;
- int ret = 0;
-
- if(clk->rate == rate)
- return 0;
- for(i = 0; i < 2; i++) {
- div = clk_get_freediv(rate, clk->parents[i]->rate, clk->div_max);
- new_rate = clk->parents[i]->rate / div;
- if((rate == new_rate) && !(clk->parents[i]->rate % div)) {
- break;
- }
- }
- if(i >= 2) {
- CLKDATA_ERR("%s can't set fixed rate%lu\n", clk->name, rate);
- return -1;
- }
-
- //CLKDATA_DBG("%s set rate %lu(from %s)\n",clk->name,rate,clk->parents[i]->name);
-
- old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con),
- clk->div_shift, clk->div_mask) + 1;
- if(div > old_div)
- set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
-
- if(clk->parents[i] != clk->parent) {
- ret = clk_set_parent_nolock(clk, clk->parents[i]);
- }
-
- if (ret) {
- CLKDATA_ERR("lcdc1 %s can't get rate%lu,reparent%s(now %s) err\n",
- clk->name, rate, clk->parents[i]->name, clk->parent->name);
- return ret;
- }
- set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
- return 0;
-}
-
-static int dclk_lcdc_set_rate(struct clk *clk, unsigned long rate)
-{
- if (rate == 27 * MHZ)
- return clkset_rate_freediv_autosel_parents(clk, rate);
- else
- return clkset_rate_evendiv_autosel_parents(clk, rate);
-
-#if 0
-
- int ret = 0;
- struct clk *parent;
-
- if (rate == 27 * MHZ && (rk30_clock_flags & CLK_FLG_EXT_27MHZ)) {
- parent = clk->parents[1];
- //CLKDATA_DBG(" %s from=%s\n",clk->name,parent->name);
- } else {
- parent = clk->parents[0];
- }
- //CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
- //clk->name,rate,parent->name,clk->parent->name);
-
- if(parent != clk->parents[1]) {
- ret = clk_set_rate_nolock(parent, rate); //div 1:1
- if (ret) {
- CLKDATA_DBG("%s set rate=%lu err\n", clk->name, rate);
- return ret;
- }
- }
- if (clk->parent != parent) {
- ret = clk_set_parent_nolock(clk, parent);
- if (ret) {
- CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
- return ret;
- }
- }
- return ret;
-#endif
-}
-
-static struct clk *dclk_lcdc0_parents[2] = {&codec_pll_clk, &general_pll_clk};
-static struct clk dclk_lcdc0 = {
- .name = "dclk_lcdc0",
- .mode = gate_mode,
- .set_rate = dclk_lcdc_set_rate,
- .recalc = clksel_recalc_div,
- .gate_idx = CLK_GATE_DCLK_LCDC0_SRC,
- .clksel_con = CRU_CLKSELS_CON(27),
- CRU_SRC_SET(0x1, 0),
- CRU_DIV_SET(0xff, 8, 256),
- CRU_PARENTS_SET(dclk_lcdc0_parents),
-};
-
-static struct clk *dclk_lcdc1_parents[2] = {&codec_pll_clk, &general_pll_clk};
-static struct clk dclk_lcdc1 = {
- .name = "dclk_lcdc1",
- .mode = gate_mode,
- .set_rate = dclk_lcdc_set_rate,
- .recalc = clksel_recalc_div,
- .gate_idx = CLK_GATE_DCLK_LCDC1_SRC,
- .clksel_con = CRU_CLKSELS_CON(28),
- CRU_SRC_SET(0x1, 0),
- CRU_DIV_SET(0xff, 8, 256),
- CRU_PARENTS_SET(dclk_lcdc1_parents),
-};
-
-/* cif setting */
-// FIXME
-static struct clk *cifout_sel_pll_parents[2] = {&codec_pll_clk, &general_pll_clk};
-static struct clk cif_out_pll = {
- .name = "cif_out_pll",
- .parent = &general_pll_clk,
- .clksel_con = CRU_CLKSELS_CON(29),
- CRU_SRC_SET(0x1, 0),
- CRU_PARENTS_SET(cifout_sel_pll_parents),
-};
-
-static struct clk cif0_out_div = {
- .name = "cif0_out_div",
- .parent = &cif_out_pll,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .gate_idx = CLK_GATE_CIF0_OUT,
- .clksel_con = CRU_CLKSELS_CON(29),
- CRU_DIV_SET(0x1f, 1, 32),
-};
-
-static int cif_out_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret = 0;
- struct clk *parent;
-
- if (rate == 24 * MHZ) {
- parent = clk->parents[1];
- } else {
- parent = clk->parents[0];
- ret = clk_set_rate_nolock(parent, rate);
- if (ret)
- return ret;
- }
- if (clk->parent != parent)
- ret = clk_set_parent_nolock(clk, parent);
-
- return ret;
-}
-
-static struct clk *cif0_out_parents[2] = {&cif0_out_div, &xin24m};
-static struct clk cif0_out = {
- .name = "cif0_out",
- .parent = &cif0_out_div,
- .set_rate = cif_out_set_rate,
- .clksel_con = CRU_CLKSELS_CON(29),
- CRU_SRC_SET(0x1, 7),
- CRU_PARENTS_SET(cif0_out_parents),
-};
-
-static struct clk pclkin_cif0 = {
- .name = "pclkin_cif0",
- .mode = gate_mode,
- .gate_idx = CLK_GATE_PCLKIN_CIF0,
-};
-
-static struct clk inv_cif0 = {
- .name = "inv_cif0",
- .parent = &pclkin_cif0,
-};
-
-static struct clk *cif0_in_parents[2] = {&pclkin_cif0, &inv_cif0};
-static struct clk cif0_in = {
- .name = "cif0_in",
- .parent = &pclkin_cif0,
- .clksel_con = CRU_CLKSELS_CON(30),
- CRU_SRC_SET(0x1, 8),
- CRU_PARENTS_SET(cif0_in_parents),
-};
-
-/* i2s/spdif setting */
-static struct clk *clk_i2s_div_parents[] = {&general_pll_clk, &codec_pll_clk};
-static struct clk clk_i2s_pll = {
- .name = "i2s_pll",
- .parent = &general_pll_clk,
- .clksel_con = CRU_CLKSELS_CON(2),
- CRU_SRC_SET(0x1, 15),
- CRU_PARENTS_SET(clk_i2s_div_parents),
-};
-
-static struct clk clk_i2s0_div = {
- .name = "i2s0_div",
- .parent = &clk_i2s_pll,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .round_rate = clksel_freediv_round_rate,
- .gate_idx = CLK_GATE_I2S0_SRC,
- .clksel_con = CRU_CLKSELS_CON(3),
- CRU_DIV_SET(0x7f, 0, 64),
-};
-
-static struct clk clk_spdif_div = {
- .name = "spdif_div",
- .parent = &clk_i2s_pll,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .round_rate = clksel_freediv_round_rate,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_SPDIF_SRC,
- .clksel_con = CRU_CLKSELS_CON(5),
- CRU_DIV_SET(0x7f, 0, 64),
-};
-static int clk_i2s_fracdiv_set_rate(struct clk *clk, unsigned long rate)
-{
- u32 numerator, denominator;
- //clk_i2s_div->clk_i2s_pll->gpll/cpll
- //clk->parent->parent
- if(frac_div_get_seting(rate, clk->parent->parent->rate,
- &numerator, &denominator) == 0) {
- clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
- cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
- CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
- } else {
- CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
- return -ENOENT;
- }
- return 0;
-}
-
-static struct clk clk_i2s0_frac_div = {
- .name = "i2s0_frac_div",
- .parent = &clk_i2s0_div,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_I2S0_FRAC,
- .recalc = clksel_recalc_frac,
- .set_rate = clk_i2s_fracdiv_set_rate,
- .clksel_con = CRU_CLKSELS_CON(7),
-};
-
-static struct clk clk_spdif_frac_div = {
- .name = "spdif_frac_div",
- .parent = &clk_spdif_div,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_SPDIF_FRAC,
- .recalc = clksel_recalc_frac,
- .set_rate = clk_i2s_fracdiv_set_rate,
- .clksel_con = CRU_CLKSELS_CON(9),
-};
-
-#define I2S_SRC_DIV (0x0)
-#define I2S_SRC_FRAC (0x1)
-#define I2S_SRC_12M (0x2)
-
-static int i2s_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret = -EINVAL;
- struct clk *parent;
-
- if (rate == clk->parents[I2S_SRC_12M]->rate) {
- parent = clk->parents[I2S_SRC_12M];
- } else if((long)clk_round_rate_nolock(clk->parents[I2S_SRC_DIV], rate) == rate) {
- parent = clk->parents[I2S_SRC_DIV];
- } else {
- parent = clk->parents[I2S_SRC_FRAC];
- }
-
- CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
- clk->name, rate, parent->name, clk->parent->name);
-
- if(parent != clk->parents[I2S_SRC_12M]) {
- ret = clk_set_rate_nolock(parent, rate); //div 1:1
- if (ret) {
- CLKDATA_DBG("%s set rate%lu err\n", clk->name, rate);
- return ret;
- }
- }
-
- if (clk->parent != parent) {
- ret = clk_set_parent_nolock(clk, parent);
- if (ret) {
- CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
- return ret;
- }
- }
-
- return ret;
-};
-
-static struct clk *clk_i2s0_parents[3] = {&clk_i2s0_div, &clk_i2s0_frac_div, &clk_12m};
-
-static struct clk clk_i2s0 = {
- .name = "i2s0",
- .set_rate = i2s_set_rate,
- .clksel_con = CRU_CLKSELS_CON(3),
- CRU_SRC_SET(0x3, 8),
- CRU_PARENTS_SET(clk_i2s0_parents),
-};
-
-static struct clk *clk_spdif_parents[3] = {&clk_spdif_div, &clk_spdif_frac_div, &clk_12m};
-
-static struct clk clk_spdif = {
- .name = "spdif",
- .parent = &clk_spdif_frac_div,
- .set_rate = i2s_set_rate,
- .clksel_con = CRU_CLKSELS_CON(5),
- CRU_SRC_SET(0x3, 8),
- CRU_PARENTS_SET(clk_spdif_parents),
-};
-
-/* otgphy setting */
-GATE_CLK(otgphy0, xin24m, OTGPHY0);
-GATE_CLK(otgphy1, xin24m, OTGPHY1);
-
-static struct clk clk_otgphy0_480m = {
- .name = "otgphy0_480m",
- .parent = &clk_otgphy0,
-};
-static struct clk clk_otgphy1_480m = {
- .name = "otgphy1_480m",
- .parent = &clk_otgphy1,
-};
-
-/* hsicphy setting */
-#ifdef ARCH_RK31
-static struct clk *clk_hsicphy_parents[4] = {&clk_otgphy0_480m, &clk_otgphy1_480m, &general_pll_clk, &codec_pll_clk};
-static struct clk clk_hsicphy_480m = {
- .name = "hsicphy_480m",
- .parent = &clk_otgphy0_480m,
- .clksel_con = CRU_CLKSELS_CON(30),
- CRU_SRC_SET(0x3, 0),
- CRU_PARENTS_SET(clk_hsicphy_parents),
-};
-static struct clk clk_hsicphy_12m = {
- .name = "hsicphy_12m",
- .parent = &clk_hsicphy_480m,
- .clksel_con = CRU_CLKSELS_CON(11),
- CRU_DIV_SET(0x3f, 8, 64),
-};
-#endif
-
-/* mac and rmii setting */
-// FIXME
-static struct clk rmii_clkin = {
- .name = "rmii_clkin",
-};
-static struct clk *clk_mac_ref_div_parents[2] = {&general_pll_clk, &ddr_pll_clk};
-static struct clk clk_mac_pll_div = {
- .name = "mac_pll_div",
- .parent = &general_pll_clk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_MAC_SRC,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(21),
- CRU_DIV_SET(0x1f, 8, 32),
- CRU_SRC_SET(0x1, 0),
- CRU_PARENTS_SET(clk_mac_ref_div_parents),
-};
-
-static int clksel_mac_ref_set_rate(struct clk *clk, unsigned long rate)
-{
- if(clk->parent == clk->parents[1]) {
- CLKDATA_DBG("mac_ref clk is form mii clkin,can't set it\n" );
- return -ENOENT;
- } else if(clk->parent == clk->parents[0]) {
- return clk_set_rate_nolock(clk->parents[0], rate);
- }
- return -ENOENT;
-}
-
-static struct clk *clk_mac_ref_parents[2] = {&clk_mac_pll_div, &rmii_clkin};
-
-static struct clk clk_mac_ref = {
- .name = "mac_ref",
- .parent = &clk_mac_pll_div,
- .set_rate = clksel_mac_ref_set_rate,
- .clksel_con = CRU_CLKSELS_CON(21),
- CRU_SRC_SET(0x1, 4),
- CRU_PARENTS_SET(clk_mac_ref_parents),
-};
-
-static int clk_set_mii_tx_parent(struct clk *clk, struct clk *parent)
-{
- return clk_set_parent_nolock(clk->parent, parent);
-}
-
-static struct clk clk_mii_tx = {
- .name = "mii_tx",
- .parent = &clk_mac_ref,
- //.set_parent = clk_set_mii_tx_parent,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_MAC_LBTEST,
-};
-
-/* hsadc and saradc */
-static struct clk *clk_hsadc_pll_parents[2] = {&general_pll_clk, &codec_pll_clk};
-static struct clk clk_hsadc_pll_div = {
- .name = "hsadc_pll_div",
- .parent = &general_pll_clk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_HSADC_SRC,
- .recalc = clksel_recalc_div,
- .round_rate = clk_freediv_round_autosel_parents_rate,
- .set_rate = clkset_rate_freediv_autosel_parents,
- //.round_rate = clksel_freediv_round_rate,
- //.set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(22),
- CRU_DIV_SET(0xff, 8, 256),
- CRU_SRC_SET(0x1, 0),
- CRU_PARENTS_SET(clk_hsadc_pll_parents),
-};
-static int clk_hsadc_fracdiv_set_rate_fixed_parent(struct clk *clk, unsigned long rate)
-{
- u32 numerator, denominator;
- // clk_hsadc_pll_div->gpll/cpll
- //clk->parent->parent
- if(frac_div_get_seting(rate, clk->parent->parent->rate,
- &numerator, &denominator) == 0) {
- clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
-
- cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
-
- CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
- } else {
- CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
- return -ENOENT;
- }
- return 0;
-}
-static int clk_hsadc_fracdiv_set_rate_auto_parents(struct clk *clk, unsigned long rate)
-{
- u32 numerator, denominator;
- u32 i, ret = 0;
- // clk_hsadc_pll_div->gpll/cpll
- //clk->parent->parent
- for(i = 0; i < 2; i++) {
- if(frac_div_get_seting(rate, clk->parent->parents[i]->rate,
- &numerator, &denominator) == 0)
- break;
- }
- if(i >= 2)
- return -ENOENT;
-
- if(clk->parent->parent != clk->parent->parents[i])
- ret = clk_set_parent_nolock(clk->parent, clk->parent->parents[i]);
- if(ret == 0) {
- clk_set_rate_nolock(clk->parent, clk->parent->parents[i]->rate); //PLL:DIV 1:
-
- cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
-
- CLKDATA_DBG("clk_frac_div %s, rate=%lu\n", clk->name, rate);
- } else {
- CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
- return -ENOENT;
- }
- return 0;
-}
-
-static long clk_hsadc_fracdiv_round_rate(struct clk *clk, unsigned long rate)
-{
- u32 numerator, denominator;
-
- CLKDATA_ERR("clk_hsadc_fracdiv_round_rate\n");
- if(frac_div_get_seting(rate, clk->parent->parent->rate,
- &numerator, &denominator) == 0)
- return rate;
-
- return 0;
-}
-static struct clk clk_hsadc_frac_div = {
- .name = "hsadc_frac_div",
- .parent = &clk_hsadc_pll_div,
- .mode = gate_mode,
- .recalc = clksel_recalc_frac,
- .set_rate = clk_hsadc_fracdiv_set_rate_auto_parents,
- .round_rate = clk_hsadc_fracdiv_round_rate,
- .gate_idx = CLK_GATE_HSADC_FRAC_SRC,
- .clksel_con = CRU_CLKSELS_CON(23),
-};
-
-#define HSADC_SRC_DIV 0x0
-#define HSADC_SRC_FRAC 0x1
-#define HSADC_SRC_EXT 0x2
-static int clk_hsadc_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret = -EINVAL;
- struct clk *parent;
-
- if(clk->parent == clk->parents[HSADC_SRC_EXT]) {
- CLKDATA_DBG("hsadc clk is form ext\n");
- return 0;
- } else if((long)clk_round_rate_nolock(clk->parents[HSADC_SRC_DIV], rate) == rate) {
- parent = clk->parents[HSADC_SRC_DIV];
- } else if((long)clk_round_rate_nolock(clk->parents[HSADC_SRC_FRAC], rate) == rate) {
- parent = clk->parents[HSADC_SRC_FRAC];
- } else
- parent = clk->parents[HSADC_SRC_DIV];
-
- CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
- clk->name, rate, parent->name, clk->parent->name);
-
- ret = clk_set_rate_nolock(parent, rate);
- if (ret) {
- CLKDATA_ERR("%s set rate%lu err\n", clk->name, rate);
- return ret;
- }
- if (clk->parent != parent) {
- ret = clk_set_parent_nolock(clk, parent);
- if (ret) {
- CLKDATA_ERR("%s can't get rate%lu,reparent err\n", clk->name, rate);
- return ret;
- }
- }
- return ret;
-}
-
-static struct clk clk_hsadc_ext = {
- .name = "hsadc_ext",
-};
-
-static struct clk *clk_hsadc_out_parents[3] = {&clk_hsadc_pll_div, &clk_hsadc_frac_div, &clk_hsadc_ext};
-static struct clk clk_hsadc_out = {
- .name = "hsadc_out",
- .parent = &clk_hsadc_pll_div,
- .set_rate = clk_hsadc_set_rate,
- .clksel_con = CRU_CLKSELS_CON(22),
- CRU_SRC_SET(0x3, 4),
- CRU_PARENTS_SET(clk_hsadc_out_parents),
-};
-static struct clk clk_hsadc_out_inv = {
- .name = "hsadc_out_inv",
- .parent = &clk_hsadc_pll_div,
-};
-
-static struct clk *clk_hsadc_parents[3] = {&clk_hsadc_out, &clk_hsadc_out_inv};
-static struct clk clk_hsadc = {
- .name = "hsadc",
- .parent = &clk_hsadc_out,
- .clksel_con = CRU_CLKSELS_CON(22),
- CRU_SRC_SET(0x1, 7),
- CRU_PARENTS_SET(clk_hsadc_parents),
-};
-
-static struct clk clk_saradc = {
- .name = "saradc",
- .parent = &xin24m,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .gate_idx = CLK_GATE_SARADC_SRC,
- .clksel_con = CRU_CLKSELS_CON(24),
- CRU_DIV_SET(0xff, 8, 256),
-};
-
-/* smc setting */
-GATE_CLK(smc, hclk_periph, SMC_SRC);//smc
-static struct clk clkn_smc = {
- .name = "smc_inv",
- .parent = &clk_smc,
-};
-
-/* spi setting */
-static struct clk clk_spi0 = {
- .name = "spi0",
- .parent = &pclk_periph,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .gate_idx = CLK_GATE_SPI0_SRC,
- .clksel_con = CRU_CLKSELS_CON(25),
- CRU_DIV_SET(0x7f, 0, 128),
-};
-
-static struct clk clk_spi1 = {
- .name = "spi1",
- .parent = &pclk_periph,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .gate_idx = CLK_GATE_SPI1_SRC,
- .clksel_con = CRU_CLKSELS_CON(25),
- CRU_DIV_SET(0x7f, 8, 128),
-};
-
-/* sdmmc/sdio/emmc setting */
-static struct clk clk_sdmmc = {
- .name = "sdmmc",
- .parent = &hclk_periph,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_even,
- .gate_idx = CLK_GATE_MMC0_SRC,
- .clksel_con = CRU_CLKSELS_CON(11),
- CRU_DIV_SET(0x3f, 0, 64),
-};
-
-static struct clk clk_sdio = {
- .name = "sdio",
- .parent = &hclk_periph,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_even,
- .gate_idx = CLK_GATE_SDIO_SRC,
- .clksel_con = CRU_CLKSELS_CON(12),
- CRU_DIV_SET(0x3f, 0, 64),
-
-};
-
-static struct clk clk_emmc = {
- .name = "emmc",
- .parent = &hclk_periph,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_even,
- .gate_idx = CLK_GATE_EMMC_SRC,
- .clksel_con = CRU_CLKSELS_CON(12),
- CRU_DIV_SET(0x3f, 8, 64),
-};
-
-/* uart setting */
-static struct clk *clk_uart_src_parents[2] = {&general_pll_clk, &codec_pll_clk};
-static struct clk clk_uart_pll = {
- .name = "uart_pll",
- .parent = &general_pll_clk,
- .clksel_con = CRU_CLKSELS_CON(12),
- CRU_SRC_SET(0x1, 15),
- CRU_PARENTS_SET(clk_uart_src_parents),
-};
-static struct clk clk_uart0_div = {
- .name = "uart0_div",
- .parent = &clk_uart_pll,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_UART0_SRC,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .round_rate = clksel_freediv_round_rate,
- .clksel_con = CRU_CLKSELS_CON(13),
- CRU_DIV_SET(0x7f, 0, 64),
-};
-static struct clk clk_uart1_div = {
- .name = "uart1_div",
- .parent = &clk_uart_pll,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_UART1_SRC,
- .recalc = clksel_recalc_div,
- .round_rate = clksel_freediv_round_rate,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(14),
- CRU_DIV_SET(0x7f, 0, 64),
-};
-
-static struct clk clk_uart2_div = {
- .name = "uart2_div",
- .parent = &clk_uart_pll,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_UART2_SRC,
- .recalc = clksel_recalc_div,
- .round_rate = clksel_freediv_round_rate,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(15),
- CRU_DIV_SET(0x7f, 0, 64),
-};
-
-static struct clk clk_uart3_div = {
- .name = "uart3_div",
- .parent = &clk_uart_pll,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_UART3_SRC,
- .recalc = clksel_recalc_div,
- .round_rate = clksel_freediv_round_rate,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(16),
- CRU_DIV_SET(0x7f, 0, 64),
-};
-static int clk_uart_fracdiv_set_rate(struct clk *clk, unsigned long rate)
-{
- u32 numerator, denominator;
- //clk_uart0_div->clk_uart_pll->gpll/cpll
- //clk->parent->parent
- if(frac_div_get_seting(rate, clk->parent->parent->rate,
- &numerator, &denominator) == 0) {
- clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
-
- cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
-
- CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
- } else {
- CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
- return -ENOENT;
- }
- return 0;
-}
-
-static struct clk clk_uart0_frac_div = {
- .name = "uart0_frac_div",
- .parent = &clk_uart0_div,
- .mode = gate_mode,
- .recalc = clksel_recalc_frac,
- .set_rate = clk_uart_fracdiv_set_rate,
- .gate_idx = CLK_GATE_UART0_FRAC_SRC,
- .clksel_con = CRU_CLKSELS_CON(17),
-};
-static struct clk clk_uart1_frac_div = {
- .name = "uart1_frac_div",
- .parent = &clk_uart1_div,
- .mode = gate_mode,
- .recalc = clksel_recalc_frac,
- .set_rate = clk_uart_fracdiv_set_rate,
- .gate_idx = CLK_GATE_UART1_FRAC_SRC,
- .clksel_con = CRU_CLKSELS_CON(18),
-};
-static struct clk clk_uart2_frac_div = {
- .name = "uart2_frac_div",
- .mode = gate_mode,
- .parent = &clk_uart2_div,
- .recalc = clksel_recalc_frac,
- .set_rate = clk_uart_fracdiv_set_rate,
- .gate_idx = CLK_GATE_UART2_FRAC_SRC,
- .clksel_con = CRU_CLKSELS_CON(19),
-};
-static struct clk clk_uart3_frac_div = {
- .name = "uart3_frac_div",
- .parent = &clk_uart3_div,
- .mode = gate_mode,
- .recalc = clksel_recalc_frac,
- .set_rate = clk_uart_fracdiv_set_rate,
- .gate_idx = CLK_GATE_UART3_FRAC_SRC,
- .clksel_con = CRU_CLKSELS_CON(20),
-};
-
-#define UART_SRC_DIV 0
-#define UART_SRC_FRAC 1
-#define UART_SRC_24M 2
-
-static int clk_uart_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret = 0;
- struct clk *parent;
-
- if(rate == clk->parents[UART_SRC_24M]->rate) { //24m
- parent = clk->parents[UART_SRC_24M];
- } else if((long)clk_round_rate_nolock(clk->parents[UART_SRC_DIV], rate) == rate) {
- parent = clk->parents[UART_SRC_DIV];
- } else {
- parent = clk->parents[UART_SRC_FRAC];
- }
-
- CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
- clk->name, rate, parent->name, clk->parent->name);
-
- if(parent != clk->parents[UART_SRC_24M]) {
- ret = clk_set_rate_nolock(parent, rate);
- if (ret) {
- CLKDATA_DBG("%s set rate%lu err\n", clk->name, rate);
- return ret;
- }
- }
-
- if (clk->parent != parent) {
- ret = clk_set_parent_nolock(clk, parent);
- if (ret) {
- CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
- return ret;
- }
- }
-
- return ret;
-}
-
-static struct clk *clk_uart0_parents[3] = {&clk_uart0_div, &clk_uart0_frac_div, &xin24m};
-static struct clk clk_uart0 = {
- .name = "uart0",
- .set_rate = clk_uart_set_rate,
- .clksel_con = CRU_CLKSELS_CON(13),
- CRU_SRC_SET(0x3, 8),
- CRU_PARENTS_SET(clk_uart0_parents),
-};
-
-static struct clk *clk_uart1_parents[3] = {&clk_uart1_div, &clk_uart1_frac_div, &xin24m};
-static struct clk clk_uart1 = {
- .name = "uart1",
- .set_rate = clk_uart_set_rate,
- .clksel_con = CRU_CLKSELS_CON(14),
- CRU_SRC_SET(0x3, 8),
- CRU_PARENTS_SET(clk_uart1_parents),
-};
-
-static struct clk *clk_uart2_parents[3] = {&clk_uart2_div, &clk_uart2_frac_div, &xin24m};
-static struct clk clk_uart2 = {
- .name = "uart2",
- .set_rate = clk_uart_set_rate,
- .clksel_con = CRU_CLKSELS_CON(15),
- CRU_SRC_SET(0x3, 8),
- CRU_PARENTS_SET(clk_uart2_parents),
-};
-static struct clk *clk_uart3_parents[3] = {&clk_uart3_div, &clk_uart3_frac_div, &xin24m};
-static struct clk clk_uart3 = {
- .name = "uart3",
- .set_rate = clk_uart_set_rate,
- .clksel_con = CRU_CLKSELS_CON(16),
- CRU_SRC_SET(0x3, 8),
- CRU_PARENTS_SET(clk_uart3_parents),
-};
-
-/* timer setting */
-GATE_CLK(timer0, xin24m, TIMER0);
-GATE_CLK(timer1, xin24m, TIMER1);
-GATE_CLK(timer2, xin24m, TIMER2);
-
-/*********************power domain*******************************/
-#if 1
-#ifdef RK30_CLK_OFFBOARD_TEST
-void pmu_set_power_domain_test(enum pmu_power_domain pd, bool on) {};
-#define _pmu_set_power_domain pmu_set_power_domain_test//rk30_pmu_set_power_domain
-#else
-void pmu_set_power_domain(enum pmu_power_domain pd, bool on);
-#define _pmu_set_power_domain pmu_set_power_domain
-#endif
-
-static int pd_video_mode(struct clk *clk, int on)
-{
- u32 gate[3];
- gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
- gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
- //gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
- //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
- pmu_set_power_domain(PD_VIDEO, on);
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
- //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
- return 0;
-}
-
-static struct clk pd_video = {
- .name = "pd_video",
- .flags = IS_PD,
- .mode = pd_video_mode,
- .gate_idx = PD_VIDEO,
-};
-static int pd_display_mode(struct clk *clk, int on)
-{
- u32 gate[10];
- gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
- gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
- gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
- gate[3] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
- gate[4] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
- //gate[5] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
- gate[6] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
- gate[7] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
- gate[8] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
- gate[9] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
- //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
- pmu_set_power_domain(PD_VIO, on);
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1) | gate[3], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0) | gate[4], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
- //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1) | gate[5], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0) | gate[6], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1) | gate[7], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP) | gate[8], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA) | gate[9], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
- return 0;
-}
-
-static struct clk pd_display = {
- .name = "pd_vio",
- .flags = IS_PD,
- .mode = pd_display_mode,
- .gate_idx = PD_VIO,
-};
-static struct clk pd_lcdc0 = {
- .parent = &pd_display,
- .name = "pd_lcdc0",
-};
-static struct clk pd_lcdc1 = {
- .parent = &pd_display,
- .name = "pd_lcdc1",
-};
-static struct clk pd_cif0 = {
- .parent = &pd_display,
- .name = "pd_cif0",
-};
-static struct clk pd_rga = {
- .parent = &pd_display,
- .name = "pd_rga",
-};
-static struct clk pd_ipp = {
- .parent = &pd_display,
- .name = "pd_ipp",
-};
-static struct clk pd_hdmi = {
- .parent = &pd_display,
- .name = "pd_hdmi",
-};
-
-
-static int pd_gpu_mode(struct clk *clk, int on)
-{
- u32 gate[3];
- gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_CLK_GPU));
- gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU_MST));
- gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU_SLV));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_CLK_GPU), CLK_GATE_CLKID_CONS(CLK_GATE_CLK_GPU));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU_SLV), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU_SLV));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU_MST), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU_MST));
- pmu_set_power_domain(PD_GPU, on);
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_CLK_GPU) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_CLK_GPU));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU_SLV) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU_SLV));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU_MST) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU_MST));
- return 0;
-}
-
-static struct clk pd_gpu = {
- .name = "pd_gpu",
- .flags = IS_PD,
- .mode = pd_gpu_mode,
- .gate_idx = PD_GPU,
-};
-
-static int pm_off_mode(struct clk *clk, int on)
-{
- _pmu_set_power_domain(clk->gate_idx, on); //on 1
- return 0;
-}
-static struct clk pd_peri = {
- .name = "pd_peri",
- .flags = IS_PD,
- .mode = pm_off_mode,
- .gate_idx = PD_PERI,
-};
-
-
-#define PD_CLK(name) \
-{\
- .dev_id = NULL,\
- .con_id = #name,\
- .clk = &name,\
-}
-
-#endif
-/************************rk30 fixed div clock****************************************/
-
-/*************************aclk_cpu***********************/
-
-GATE_CLK(dma1, aclk_cpu, ACLK_DMAC1);
-GATE_CLK(l2mem_con, aclk_cpu, ACLK_L2MEM_CON);
-GATE_CLK(intmem, aclk_cpu, ACLK_INTMEM);
-GATE_CLK(aclk_strc_sys, aclk_cpu, ACLK_STRC_SYS);
-
-/*************************hclk_cpu***********************/
-
-GATE_CLK(rom, hclk_cpu, HCLK_ROM);
-GATE_CLK(hclk_i2s0_2ch, hclk_cpu, HCLK_I2S0_2CH);
-GATE_CLK(hclk_spdif, hclk_cpu, HCLK_SPDIF);
-GATE_CLK(hclk_cpubus, hclk_cpu, HCLK_CPUBUS);
-GATE_CLK(hclk_ahb2apb, hclk_cpu, HCLK_AHB2APB);
-GATE_CLK(hclk_vio_bus, hclk_cpu, HCLK_VIO_BUS);
-GATE_CLK(hclk_lcdc0, hclk_cpu, HCLK_LCDC0);
-GATE_CLK(hclk_lcdc1, hclk_cpu, HCLK_LCDC1);
-GATE_CLK(hclk_cif0, hclk_cpu, HCLK_CIF0);
-GATE_CLK(hclk_ipp, hclk_cpu, HCLK_IPP);
-GATE_CLK(hclk_rga, hclk_cpu, HCLK_RGA);
-GATE_CLK(hclk_l2mem, hclk_cpu, HCLK_L2MEM);
-GATE_CLK(hclk_video_h2h, hclk_cpu, HCLK_VIDEO_H2H);
-/*************************pclk_cpu***********************/
-GATE_CLK(pwm01, pclk_cpu, PCLK_PWM01);//pwm 0¡¢1
-GATE_CLK(pclk_timer0, pclk_cpu, PCLK_TIMER0);
-GATE_CLK(pclk_timer1, pclk_cpu, PCLK_TIMER1);
-GATE_CLK(pclk_timer2, pclk_cpu, PCLK_TIMER2);
-GATE_CLK(i2c0, pclk_cpu, PCLK_I2C0);
-GATE_CLK(i2c1, pclk_cpu, PCLK_I2C1);
-GATE_CLK(gpio0, pclk_cpu, PCLK_GPIO0);
-GATE_CLK(gpio1, pclk_cpu, PCLK_GPIO1);
-GATE_CLK(gpio2, pclk_cpu, PCLK_GPIO2);
-GATE_CLK(efuse, pclk_cpu, PCLK_EFUSE);
-GATE_CLK(tzpc, pclk_cpu, PCLK_TZPC);
-GATE_CLK(pclk_uart0, pclk_cpu, PCLK_UART0);
-GATE_CLK(pclk_uart1, pclk_cpu, PCLK_UART1);
-GATE_CLK(pclk_ddrupctl, pclk_cpu, PCLK_DDRUPCTL);
-GATE_CLK(pclk_ddrpubl, pclk_cpu, PCLK_PUBL);
-GATE_CLK(dbg, pclk_cpu, PCLK_DBG);
-GATE_CLK(grf, pclk_cpu, PCLK_GRF);
-GATE_CLK(pmu, pclk_cpu, PCLK_PMU);
-
-/*************************aclk_periph***********************/
-
-GATE_CLK(dma2, aclk_periph, ACLK_DMAC2);
-GATE_CLK(aclk_smc, aclk_periph, ACLK_SMC);
-GATE_CLK(aclk_peri_niu, aclk_periph, ACLK_PEI_NIU);
-GATE_CLK(aclk_cpu_peri, aclk_periph, ACLK_CPU_PERI);
-GATE_CLK(aclk_peri_axi_matrix, aclk_periph, ACLK_PERI_AXI_MATRIX);
-
-/*************************hclk_periph***********************/
-GATE_CLK(hclk_peri_axi_matrix, hclk_periph, HCLK_PERI_AXI_MATRIX);
-GATE_CLK(hclk_peri_ahb_arbi, hclk_periph, HCLK_PERI_AHB_ARBI);
-GATE_CLK(hclk_emem_peri, hclk_periph, HCLK_EMEM_PERI);
-GATE_CLK(hclk_mac, hclk_periph, HCLK_EMAC);
-GATE_CLK(nandc, hclk_periph, HCLK_NANDC);
-GATE_CLK(hclk_usb_peri, hclk_periph, HCLK_USB_PERI);
-GATE_CLK(hclk_otg0, clk_hclk_usb_peri, HCLK_OTG0);
-GATE_CLK(hclk_otg1, clk_hclk_usb_peri, HCLK_OTG1);
-GATE_CLK(hclk_hsic, hclk_periph, HCLK_HSIC);
-GATE_CLK(hclk_gps, hclk_periph, HCLK_GPS);
-GATE_CLK(hclk_hsadc, hclk_periph, HCLK_HSADC);
-GATE_CLK(hclk_pidfilter, hclk_periph, HCLK_PIDF);
-GATE_CLK(hclk_sdmmc, hclk_periph, HCLK_SDMMC0);
-GATE_CLK(hclk_sdio, hclk_periph, HCLK_SDIO);
-GATE_CLK(hclk_emmc, hclk_periph, HCLK_EMMC);
-/*************************pclk_periph***********************/
-GATE_CLK(pclk_peri_axi_matrix, pclk_periph, PCLK_PERI_AXI_MATRIX);
-GATE_CLK(pwm23, pclk_periph, PCLK_PWM23);
-GATE_CLK(wdt, pclk_periph, PCLK_WDT);
-GATE_CLK(pclk_spi0, pclk_periph, PCLK_SPI0);
-GATE_CLK(pclk_spi1, pclk_periph, PCLK_SPI1);
-GATE_CLK(pclk_uart2, pclk_periph, PCLK_UART2);
-GATE_CLK(pclk_uart3, pclk_periph, PCLK_UART3);
-GATE_CLK(i2c2, pclk_periph, PCLK_I2C2);
-GATE_CLK(i2c3, pclk_periph, PCLK_I2C3);
-GATE_CLK(i2c4, pclk_periph, PCLK_I2C4);
-GATE_CLK(gpio3, pclk_periph, PCLK_GPIO3);
-GATE_CLK(pclk_saradc, pclk_periph, PCLK_SARADC);
-/*************************aclk_lcdc0***********************/
-
-GATE_CLK(aclk_vio0, aclk_lcdc0_pre, ACLK_VIO0);
-
-GATE_CLK(aclk_lcdc0, clk_aclk_vio0, ACLK_LCDC0);
-GATE_CLK(aclk_cif0, clk_aclk_vio0, ACLK_CIF0);
-GATE_CLK(aclk_ipp, clk_aclk_vio0, ACLK_IPP);
-
-/*************************aclk_lcdc0***********************/
-
-GATE_CLK(aclk_vio1, aclk_lcdc1_pre, ACLK_VIO1);
-GATE_CLK(aclk_lcdc1, clk_aclk_vio1, ACLK_LCDC1);
-GATE_CLK(aclk_rga, clk_aclk_vio1, ACLK_RGA);
-
-
-#if 1
-#define CLK(dev, con, ck) \
-{\
- .dev_id = dev,\
- .con_id = con,\
- .clk = ck,\
-}
-
-
-#define CLK1(name) \
-{\
- .dev_id = NULL,\
- .con_id = #name,\
- .clk = &clk_##name,\
-}
-
-#endif
-
-static struct clk_lookup clks[] = {
- CLK(NULL, "xin24m", &xin24m),
- //CLK(NULL, "xin27m", &xin27m),
- CLK(NULL, "xin12m", &clk_12m),
- CLK(NULL, "arm_pll", &arm_pll_clk),
- CLK(NULL, "ddr_pll", &ddr_pll_clk),
- CLK(NULL, "codec_pll", &codec_pll_clk),
- CLK(NULL, "general_pll", &general_pll_clk),
-
- CLK(NULL, "ddr", &clk_ddr),
- CLK(NULL, "cpu", &clk_core),
- CLK(NULL, "logic", &clk_cpu_div),
- CLK(NULL, "arm_gpll", &clk_core_gpll_path),
- CLK1(l2c),
- CLK1(core_dbg),
- CLK("smp_twd", NULL, &core_periph),
- CLK(NULL, "aclk_core", &aclk_core),
- CLK(NULL, "aclk_cpu", &aclk_cpu),
- CLK(NULL, "pclk_cpu", &pclk_cpu),
- CLK(NULL, "atclk_cpu", &atclk_cpu),
- CLK(NULL, "hclk_cpu", &hclk_cpu),
- CLK(NULL, "ahb2apb_cpu", &ahb2apb_cpu),
-
- CLK1(gpu),
- #ifdef GPU_CORE_ACLK_CTR_TOGETHER
- CLK(NULL, "aclk_gpu_real",&aclk_gpu),
- CLK(NULL, "aclk_gpu", &aclk_gpu_null),
- #else
- CLK(NULL, "aclk_gpu", &aclk_gpu),
- #endif
- CLK(NULL, "gpu_slv", &aclk_gpu_slv),
- CLK(NULL, "gpu_mst", &aclk_gpu_mst),
-
- CLK(NULL, "aclk_vepu", &aclk_vepu),
- CLK(NULL, "hclk_vepu", &hclk_vepu),
- CLK(NULL, "aclk_vdpu", &aclk_vdpu),
- CLK(NULL, "hclk_vdpu", &hclk_vdpu),
-
- CLK(NULL, "aclk_lcdc0_pre", &aclk_lcdc0_pre),
- CLK(NULL, "aclk_lcdc1_pre", &aclk_lcdc1_pre),
-
- CLK(NULL, "aclk_periph", &aclk_periph),
- CLK(NULL, "pclk_periph", &pclk_periph),
- CLK(NULL, "hclk_periph", &hclk_periph),
-
- CLK(NULL, "dclk_lcdc0", &dclk_lcdc0),
- CLK(NULL, "dclk_lcdc1", &dclk_lcdc1),
-
- CLK(NULL, "cif_out_pll", &cif_out_pll),
- CLK(NULL, "cif0_out_div", &cif0_out_div),
-
- CLK(NULL, "cif0_out", &cif0_out),
- CLK(NULL, "pclkin_cif0", &pclkin_cif0),
- CLK(NULL, "inv_cif0", &inv_cif0),
- CLK(NULL, "cif0_in", &cif0_in),
-
- CLK1(i2s_pll),
- CLK("rk29_i2s.0", "i2s_div", &clk_i2s0_div),
- CLK("rk29_i2s.0", "i2s_frac_div", &clk_i2s0_frac_div),
- CLK("rk29_i2s.0", "i2s", &clk_i2s0),
-
- // actually no i2s1
- CLK("rk29_i2s.1", "i2s_div", &clk_i2s0_div),
- CLK("rk29_i2s.1", "i2s_frac_div", &clk_i2s0_frac_div),
- CLK("rk29_i2s.1", "i2s", &clk_i2s0),
-
-
- CLK1(spdif_div),
- CLK1(spdif_frac_div),
- CLK1(spdif),
-
- CLK1(otgphy0),
- CLK1(otgphy1),
- CLK1(otgphy0_480m),
- CLK1(otgphy1_480m),
- CLK1(hsicphy_480m),
- CLK1(hsicphy_12m),
-
- CLK(NULL, "rmii_clkin", &rmii_clkin),
- CLK(NULL, "mac_ref_div", &clk_mac_pll_div), // compatible with rk29
- CLK1(mac_ref),
- CLK1(mii_tx),
-
- CLK1(hsadc_pll_div),
- CLK1(hsadc_frac_div),
- CLK1(hsadc_ext),
- CLK1(hsadc_out),
- CLK1(hsadc_out_inv),
- CLK1(hsadc),
-
- CLK1(saradc),
-
- CLK1(smc),
- CLK(NULL, "smc_inv", &clkn_smc),
-
- CLK("rk29xx_spim.0", "spi", &clk_spi0),
- CLK("rk29xx_spim.1", "spi", &clk_spi1),
-
- CLK("rk29_sdmmc.0", "mmc", &clk_sdmmc),
- CLK("rk29_sdmmc.1", "mmc", &clk_sdio),
- CLK1(emmc),
-
- CLK1(uart_pll),
- CLK("rk_serial.0", "uart_div", &clk_uart0_div),
- CLK("rk_serial.0", "uart_frac_div", &clk_uart0_frac_div),
- CLK("rk_serial.0", "uart", &clk_uart0),
- CLK("rk_serial.1", "uart_div", &clk_uart1_div),
- CLK("rk_serial.1", "uart_frac_div", &clk_uart1_frac_div),
- CLK("rk_serial.1", "uart", &clk_uart1),
- CLK("rk_serial.2", "uart_div", &clk_uart2_div),
- CLK("rk_serial.2", "uart_frac_div", &clk_uart2_frac_div),
- CLK("rk_serial.2", "uart", &clk_uart2),
- CLK("rk_serial.3", "uart_div", &clk_uart3_div),
- CLK("rk_serial.3", "uart_frac_div", &clk_uart3_frac_div),
- CLK("rk_serial.3", "uart", &clk_uart3),
-
- CLK1(timer0),
- CLK1(timer1),
- CLK1(timer2),
-
- /*************************aclk_cpu***********************/
- CLK1(dma1),
- CLK1(l2mem_con),
- CLK1(intmem),
- CLK1(aclk_strc_sys),
-
- /*************************hclk_cpu***********************/
- CLK1(rom),
- CLK("rk29_i2s.0", "hclk_i2s", &clk_hclk_i2s0_2ch),
- // actually no i2s1
- CLK("rk29_i2s.1", "hclk_i2s", &clk_hclk_i2s0_2ch),
- CLK1(hclk_spdif),
- CLK1(hclk_cpubus),
- CLK1(hclk_ahb2apb),
- CLK1(hclk_vio_bus),
- CLK1(hclk_lcdc0),
- CLK1(hclk_lcdc1),
- CLK1(hclk_cif0),
- CLK1(hclk_ipp),
- CLK1(hclk_rga),
- CLK1(hclk_video_h2h),
- CLK1(hclk_l2mem),
-
- /*************************pclk_cpu***********************/
- CLK1(pwm01),
- CLK1(pclk_timer0),
- CLK1(pclk_timer1),
- CLK1(pclk_timer2),
- CLK("rk30_i2c.0", "i2c", &clk_i2c0),
- CLK("rk30_i2c.1", "i2c", &clk_i2c1),
- CLK1(gpio0),
- CLK1(gpio1),
- CLK1(gpio2),
- CLK1(efuse),
- CLK1(tzpc),
- CLK("rk_serial.0", "pclk_uart", &clk_pclk_uart0),
- CLK("rk_serial.1", "pclk_uart", &clk_pclk_uart1),
- CLK1(pclk_ddrupctl),
- CLK1(pclk_ddrpubl),
- CLK1(dbg),
- CLK1(grf),
- CLK1(pmu),
-
- /*************************aclk_periph***********************/
- CLK1(dma2),
- CLK1(aclk_smc),
- CLK1(aclk_peri_niu),
- CLK1(aclk_cpu_peri),
- CLK1(aclk_peri_axi_matrix),
-
- /*************************hclk_periph***********************/
- CLK1(hclk_peri_axi_matrix),
- CLK1(hclk_peri_ahb_arbi),
- CLK1(hclk_emem_peri),
- CLK1(hclk_mac),
- CLK1(nandc),
- CLK1(hclk_usb_peri),
- CLK1(hclk_otg0),
- CLK1(hclk_otg1),
- CLK1(hclk_hsic),
- CLK1(hclk_gps),
- CLK1(hclk_hsadc),
- CLK1(hclk_pidfilter),
- CLK("rk29_sdmmc.0", "hclk_mmc", &clk_hclk_sdmmc),
- CLK("rk29_sdmmc.1", "hclk_mmc", &clk_hclk_sdio),
- CLK1(hclk_emmc),
-
- /*************************pclk_periph***********************/
- CLK1(pclk_peri_axi_matrix),
- CLK1(pwm23),
- CLK1(wdt),
- CLK("rk29xx_spim.0", "pclk_spi", &clk_pclk_spi0),
- CLK("rk29xx_spim.1", "pclk_spi", &clk_pclk_spi1),
- CLK("rk_serial.2", "pclk_uart", &clk_pclk_uart2),
- CLK("rk_serial.3", "pclk_uart", &clk_pclk_uart3),
- CLK("rk30_i2c.2", "i2c", &clk_i2c2),
- CLK("rk30_i2c.3", "i2c", &clk_i2c3),
- CLK("rk30_i2c.4", "i2c", &clk_i2c4),
- CLK1(gpio3),
- CLK1(pclk_saradc),
-
- /*************************aclk_lcdc0***********************/
- CLK1(aclk_vio0),
- CLK(NULL, "aclk_lcdc0", &clk_aclk_lcdc0),
- CLK1(aclk_cif0),
- CLK1(aclk_ipp),
-
- /*************************aclk_lcdc1***********************/
- CLK1(aclk_vio1),
- CLK(NULL, "aclk_lcdc1", &clk_aclk_lcdc1),
- CLK1(aclk_rga),
- /************************power domain**********************/
-
- PD_CLK(pd_peri),
- PD_CLK(pd_display),
- PD_CLK(pd_video),
- PD_CLK(pd_lcdc0),
- PD_CLK(pd_lcdc1),
- PD_CLK(pd_cif0),
- //PD_CLK(pd_cif1),
- PD_CLK(pd_rga),
- PD_CLK(pd_ipp),
- PD_CLK(pd_video),
- PD_CLK(pd_gpu),
- //PD_CLK(pd_dbg),
-};
-static void __init rk30_init_enable_clocks(void)
-{
- #if 0
- //clk_enable_nolock(&xin24m);
- //clk_enable_nolock(&clk_12m);
- //clk_enable_nolock(&arm_pll_clk);
- //clk_enable_nolock(&ddr_pll_clk);
- //clk_enable_nolock(&codec_pll_clk);
- //clk_enable_nolock(&general_pll_clk);
- #endif
- clk_enable_nolock(&clk_ddr);
- //clk_enable_nolock(&clk_core);
- clk_enable_nolock(&clk_cpu_div);
- clk_enable_nolock(&clk_core_gpll_path);
- clk_enable_nolock(&clk_l2c);
- clk_enable_nolock(&clk_core_dbg);
- clk_enable_nolock(&core_periph);
- clk_enable_nolock(&aclk_core);
- //clk_enable_nolock(&aclk_cpu);
- //clk_enable_nolock(&pclk_cpu);
- clk_enable_nolock(&atclk_cpu);
- //clk_enable_nolock(&hclk_cpu);
- clk_enable_nolock(&ahb2apb_cpu);
- #if 0
- clk_enable_nolock(&clk_gpu);
- clk_enable_nolock(&aclk_gpu);
- clk_enable_nolock(&aclk_gpu_slv);
- clk_enable_nolock(&aclk_gpu_mst);
-
- clk_enable_nolock(&aclk_vepu);
- clk_enable_nolock(&hclk_vepu);
- clk_enable_nolock(&aclk_vdpu);
- clk_enable_nolock(&hclk_vdpu);
-
- clk_enable_nolock(&aclk_lcdc0_pre);
- clk_enable_nolock(&aclk_lcdc1_pre);
-
- clk_enable_nolock(&aclk_periph);
- clk_enable_nolock(&pclk_periph);
- clk_enable_nolock(&hclk_periph);
- #endif
- #if 0
- clk_enable_nolock(&dclk_lcdc0);
- clk_enable_nolock(&dclk_lcdc1);
-
- clk_enable_nolock(&cif_out_pll);
- clk_enable_nolock(&cif0_out_div);
-
- clk_enable_nolock(&cif0_out);
- clk_enable_nolock(&pclkin_cif0);
- clk_enable_nolock(&inv_cif0);
- clk_enable_nolock(&cif0_in);
-
- clk_enable_nolock(&clk_i2s_pll);
- clk_enable_nolock(&clk_i2s0_div);
- clk_enable_nolock(&clk_i2s0_frac_div);
- clk_enable_nolock(&clk_i2s0);
-
- actually no i2s1
- clk_enable_nolock(&clk_i2s0_div);
- clk_enable_nolock(&clk_i2s0_frac_div);
- clk_enable_nolock(&clk_i2s0);
-
- clk_enable_nolock(&clk_spdif_div);
- clk_enable_nolock(&clk_spdif_frac_div);
- clk_enable_nolock(&clk_spdif);
- #endif
- #if 0
- clk_enable_nolock(&clk_otgphy0);
- clk_enable_nolock(&clk_otgphy1);
- clk_enable_nolock(&clk_otgphy0_480m);
- clk_enable_nolock(&clk_otgphy1_480m);
- clk_enable_nolock(&clk_hsicphy_480m);
- clk_enable_nolock(&clk_hsicphy_12m);
- #endif
-
- #if 0
- clk_enable_nolock(&rmii_clkin);
- clk_enable_nolock(&clk_mac_pll_div); // compatible with rk29
- clk_enable_nolock(&clk_mac_ref);
- clk_enable_nolock(&clk_mii_tx);
- #endif
-
- #if 0
- clk_enable_nolock(&clk_hsadc_pll_div);
- clk_enable_nolock(&clk_hsadc_frac_div);
- clk_enable_nolock(&clk_hsadc_ext);
- clk_enable_nolock(&clk_hsadc_out);
- clk_enable_nolock(&clk_hsadc_out_inv);
- clk_enable_nolock(&clk_hsadc);
-
- clk_enable_nolock(&clk_saradc);
- #endif
- /*
- clk_enable_nolock(&clk_smc);
- clk_enable_nolock(&clkn_smc);
- */
- /*
- clk_enable_nolock(&clk_spi0);
- clk_enable_nolock(&clk_spi1);
- */
- /*
- clk_enable_nolock(&clk_sdmmc);
- clk_enable_nolock(&clk_sdio);
- clk_enable_nolock(&clk_emmc);
- */
- #if 0
- clk_enable_nolock(&clk_uart_pll);
- clk_enable_nolock(&clk_uart0_div);
- clk_enable_nolock(&clk_uart0_frac_div);
- clk_enable_nolock(&clk_uart0);
- clk_enable_nolock(&clk_uart1_div);
- clk_enable_nolock(&clk_uart1_frac_div);
- clk_enable_nolock(&clk_uart1);
- clk_enable_nolock(&clk_uart2_div);
- clk_enable_nolock(&clk_uart2_frac_div);
- clk_enable_nolock(&clk_uart2);
- clk_enable_nolock(&clk_uart3_div);
- clk_enable_nolock(&clk_uart3_frac_div);
- clk_enable_nolock(&clk_uart3);
- #endif
- #if CONFIG_RK_DEBUG_UART == 0
- clk_enable_nolock(&clk_uart0);
- clk_enable_nolock(&clk_pclk_uart0);
- #elif CONFIG_RK_DEBUG_UART == 1
- clk_enable_nolock(&clk_uart1);
- clk_enable_nolock(&clk_pclk_uart1);
-
- #elif CONFIG_RK_DEBUG_UART == 2
- clk_enable_nolock(&clk_uart2);
- clk_enable_nolock(&clk_pclk_uart2);
-
- #elif CONFIG_RK_DEBUG_UART == 3
- clk_enable_nolock(&clk_uart3);
- clk_enable_nolock(&clk_pclk_uart3);
-
- #endif
- #if 0
- clk_enable_nolock(&clk_timer0);
- clk_enable_nolock(&clk_timer1);
- clk_enable_nolock(&clk_timer2);
- #endif
-
- /*************************aclk_cpu***********************/
- clk_enable_nolock(&clk_dma1);
- clk_enable_nolock(&clk_l2mem_con);
- clk_enable_nolock(&clk_intmem);
- clk_enable_nolock(&clk_aclk_strc_sys);
-
- /*************************hclk_cpu***********************/
- clk_enable_nolock(&clk_rom);
- #if 0
- clk_enable_nolock(&clk_hclk_i2s0_2ch);
- // actually no i2s1
- clk_enable_nolock(&clk_hclk_i2s0_2ch);
- clk_enable_nolock(&clk_hclk_spdif);
- #endif
- clk_enable_nolock(&clk_hclk_cpubus);
- clk_enable_nolock(&clk_hclk_ahb2apb);
- clk_enable_nolock(&clk_hclk_vio_bus);
- #if 0
- clk_enable_nolock(&clk_hclk_lcdc0);
- clk_enable_nolock(&clk_hclk_lcdc1);
- clk_enable_nolock(&clk_hclk_cif0);
- clk_enable_nolock(&clk_hclk_ipp);
- clk_enable_nolock(&clk_hclk_rga);
- #endif
- clk_enable_nolock(&clk_hclk_video_h2h);
- clk_enable_nolock(&clk_hclk_l2mem);
-
- /*************************pclk_cpu***********************/
- #if 0
- clk_enable_nolock(&clk_pwm01);
- clk_enable_nolock(&clk_pclk_timer0);
- clk_enable_nolock(&clk_pclk_timer1);
- clk_enable_nolock(&clk_pclk_timer2);
- clk_enable_nolock(&clk_i2c0);
- clk_enable_nolock(&clk_i2c1);
- clk_enable_nolock(&clk_gpio0);
- clk_enable_nolock(&clk_gpio1);
- clk_enable_nolock(&clk_gpio2);
- clk_enable_nolock(&clk_efuse);
- #endif
- clk_enable_nolock(&clk_tzpc);
- //clk_enable_nolock(&clk_pclk_uart0);
- //clk_enable_nolock(&clk_pclk_uart1);
- clk_enable_nolock(&clk_pclk_ddrupctl);
- clk_enable_nolock(&clk_pclk_ddrpubl);
- clk_enable_nolock(&clk_dbg);
- clk_enable_nolock(&clk_grf);
- clk_enable_nolock(&clk_pmu);
-
- /*************************aclk_periph***********************/
- clk_enable_nolock(&clk_dma2);
- clk_enable_nolock(&clk_aclk_smc);
- clk_enable_nolock(&clk_aclk_peri_niu);
- clk_enable_nolock(&clk_aclk_cpu_peri);
- clk_enable_nolock(&clk_aclk_peri_axi_matrix);
-
- /*************************hclk_periph***********************/
- clk_enable_nolock(&clk_hclk_peri_axi_matrix);
- clk_enable_nolock(&clk_hclk_peri_ahb_arbi);
- clk_enable_nolock(&clk_hclk_emem_peri);
- //clk_enable_nolock(&clk_hclk_mac);
- clk_enable_nolock(&clk_nandc);
- clk_enable_nolock(&clk_hclk_usb_peri);
- #if 0
- clk_enable_nolock(&clk_hclk_otg0);
- clk_enable_nolock(&clk_hclk_otg1);
- clk_enable_nolock(&clk_hclk_hsic);
- clk_enable_nolock(&clk_hclk_gps);
- clk_enable_nolock(&clk_hclk_hsadc);
- clk_enable_nolock(&clk_hclk_pidfilter);
- clk_enable_nolock(&clk_hclk_sdmmc);
- clk_enable_nolock(&clk_hclk_sdio);
- clk_enable_nolock(&clk_hclk_emmc);
- #endif
-
- /*************************pclk_periph***********************/
- clk_enable_nolock(&clk_pclk_peri_axi_matrix);
- #if 0
- clk_enable_nolock(&clk_pwm23);
- clk_enable_nolock(&clk_wdt);
- clk_enable_nolock(&clk_pclk_spi0);
- clk_enable_nolock(&clk_pclk_spi1);
- clk_enable_nolock(&clk_pclk_uart2);
- clk_enable_nolock(&clk_pclk_uart3);
- #endif
- #if 0
- clk_enable_nolock(&clk_i2c2);
- clk_enable_nolock(&clk_i2c3);
- clk_enable_nolock(&clk_i2c4);
- clk_enable_nolock(&clk_gpio3);
- clk_enable_nolock(&clk_pclk_saradc);
- #endif
- /*************************aclk_lcdc0***********************/
-#if 1
- //clk_enable_nolock(&clk_aclk_vio0);
- //clk_enable_nolock(&clk_aclk_lcdc0);
- //clk_enable_nolock(&clk_aclk_cif0);
- //clk_enable_nolock(&clk_aclk_ipp);
-#endif
- /*************************aclk_lcdc1***********************/
-#if 1
- //clk_enable_nolock(&clk_aclk_vio1);
- //clk_enable_nolock(&clk_aclk_lcdc1);
- //clk_enable_nolock(&clk_aclk_rga);
-#endif
- /************************power domain**********************/
-
-}
-static void periph_clk_set_init(void)
-{
- unsigned long aclk_p, hclk_p, pclk_p;
- unsigned long ppll_rate = general_pll_clk.rate;
- //aclk 148.5
-
- /* general pll */
- switch (ppll_rate) {
- case 148500* KHZ:
- aclk_p = 148500 * KHZ;
- hclk_p = aclk_p >> 1;
- pclk_p = aclk_p >> 2;
- break;
- case 1188*MHZ:
- aclk_p = aclk_p >> 3; // 0
- hclk_p = aclk_p >> 1;
- pclk_p = aclk_p >> 2;
-
- case 297 * MHZ:
- aclk_p = ppll_rate >> 1;
- hclk_p = aclk_p >> 0;
- pclk_p = aclk_p >> 1;
- break;
-
- case 300 * MHZ:
- aclk_p = ppll_rate >> 1;
- hclk_p = aclk_p >> 0;
- pclk_p = aclk_p >> 1;
- break;
- case 384 * MHZ:
- aclk_p = ppll_rate >> 1;
- hclk_p = aclk_p >> 1;
- pclk_p = aclk_p >> 2;
- break;
- case 594 * MHZ:
- aclk_p = ppll_rate >> 2;
- hclk_p = aclk_p >> 0;
- pclk_p = aclk_p >> 1;
- break;
- default:
- aclk_p = 150 * MHZ;
- hclk_p = 150 * MHZ;
- pclk_p = 75 * MHZ;
- break;
- }
- clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
- clk_set_rate_nolock(&aclk_periph, aclk_p);
- clk_set_rate_nolock(&hclk_periph, hclk_p);
- clk_set_rate_nolock(&pclk_periph, pclk_p);
-}
-
-static void cpu_axi_init(void)
-{
- unsigned long cpu_div_rate, aclk_cpu_rate, hclk_cpu_rate, pclk_cpu_rate, ahb2apb_cpu_rate;
- unsigned long gpll_rate = general_pll_clk.rate;
-
- switch (gpll_rate) {
- case 297 * MHZ:
- cpu_div_rate = gpll_rate;
- aclk_cpu_rate = cpu_div_rate >> 0;
- hclk_cpu_rate = aclk_cpu_rate >> 1;
- pclk_cpu_rate = aclk_cpu_rate >> 2;
- break;
- case 384 * MHZ:
- cpu_div_rate = gpll_rate >> 1;
- aclk_cpu_rate = cpu_div_rate >> 0;
- hclk_cpu_rate = aclk_cpu_rate >> 1;
- pclk_cpu_rate = aclk_cpu_rate >> 2;
- break;
-
- case 594 * MHZ:
- cpu_div_rate = gpll_rate >> 1;
- aclk_cpu_rate = cpu_div_rate >> 0;
- hclk_cpu_rate = aclk_cpu_rate >> 1;
- pclk_cpu_rate = aclk_cpu_rate >> 2;
- break;
- default:
- cpu_div_rate = 150 * MHZ;
- aclk_cpu_rate = 150 * MHZ;
- hclk_cpu_rate = 150 * MHZ;
- pclk_cpu_rate = 75 * MHZ;
- break;
- }
- ahb2apb_cpu_rate = pclk_cpu_rate;
-
- clk_set_parent_nolock(&clk_cpu_div, &general_pll_clk);
- clk_set_rate_nolock(&clk_cpu_div, cpu_div_rate);
- clk_set_rate_nolock(&aclk_cpu, aclk_cpu_rate);
- clk_set_rate_nolock(&hclk_cpu, hclk_cpu_rate);
- clk_set_rate_nolock(&pclk_cpu, pclk_cpu_rate);
- clk_set_rate_nolock(&ahb2apb_cpu, ahb2apb_cpu_rate);
-}
-
-void rk30_clock_common_i2s_init(void)
-{
- unsigned long i2s_rate;
- //20 times
- if(rk30_clock_flags & CLK_FLG_MAX_I2S_49152KHZ) {
- i2s_rate = 49152000;
- } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_24576KHZ) {
- i2s_rate = 24576000;
- } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_22579_2KHZ) {
- i2s_rate = 22579000;
- } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_12288KHZ) {
- i2s_rate = 12288000;
- } else {
- i2s_rate = 49152000;
- }
-
- if(((i2s_rate * 20) <= general_pll_clk.rate) || !(general_pll_clk.rate % i2s_rate)) {
- clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
- } else if(((i2s_rate * 20) <= codec_pll_clk.rate) || !(codec_pll_clk.rate % i2s_rate)) {
- clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
- } else {
- if(general_pll_clk.rate > codec_pll_clk.rate)
- clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
- else
- clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
- }
-}
-
-void rk_clock_common_uart_init(struct clk *cpll_clk,struct clk *gpll_clk)
-{
- struct clk *p_clk;
- unsigned long rate;
- if(!(gpll_clk->rate%(48*MHZ)))
- {
- p_clk=gpll_clk;
- rate=48*MHZ;
- }
- else if(!(cpll_clk->rate%(48*MHZ)))
- {
- p_clk=cpll_clk;
- rate=48*MHZ;
- }
- else if(!(gpll_clk->rate%(49500*KHZ)))
- {
- p_clk=gpll_clk;
- rate=(49500*KHZ);
- }
- else if(!(cpll_clk->rate%(49500*KHZ)))
- {
- p_clk=cpll_clk;
- rate=(49500*KHZ);
- }
- else
- {
- if(cpll_clk->rate>gpll_clk->rate)
- {
- p_clk=cpll_clk;
- }
- else
- {
- p_clk=gpll_clk;
- }
- rate=50*MHZ;
- }
- clk_set_parent_nolock(&clk_uart_pll, p_clk);
- clk_set_rate_nolock(&clk_uart0_div,rate);
- clk_set_rate_nolock(&clk_uart1_div,rate);
- clk_set_rate_nolock(&clk_uart2_div,rate);
- clk_set_rate_nolock(&clk_uart3_div,rate);
- clk_set_rate_nolock(&clk_uart1,rate);
-}
-static void __init rk30_clock_common_init(unsigned long gpll_rate, unsigned long cpll_rate)
-{
-
- //general
- clk_set_rate_nolock(&general_pll_clk, gpll_rate);
- lpj_gpll = CLK_LOOPS_RECALC(general_pll_clk.rate);
-
- //code pll
- clk_set_rate_nolock(&codec_pll_clk, cpll_rate);
-
- cpu_axi_init();
- clk_set_rate_nolock(&clk_core, 312 * MHZ);
- //periph clk
- periph_clk_set_init();
-
- //i2s
- rk30_clock_common_i2s_init();
-
- // spi
- clk_set_rate_nolock(&clk_spi0, clk_spi0.parent->rate);
- clk_set_rate_nolock(&clk_spi1, clk_spi1.parent->rate);
-
- // uart
-
- rk_clock_common_uart_init(&codec_pll_clk,&general_pll_clk);
-
- //mac
- if(!(gpll_rate % (50 * MHZ)))
- clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
- else if(!(ddr_pll_clk.rate % (50 * MHZ)))
- clk_set_parent_nolock(&clk_mac_pll_div, &ddr_pll_clk);
- else
- CLKDATA_ERR("mac can't get 50mhz\n");
-
- //hsadc
- //auto pll sel
- //clk_set_parent_nolock(&clk_hsadc_pll_div, &general_pll_clk);
-
- //lcdc0 lcd auto sel pll
- clk_set_parent_nolock(&dclk_lcdc0, &general_pll_clk);
- clk_set_parent_nolock(&dclk_lcdc1, &general_pll_clk);
-
- //cif
- clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
-
- //axi lcdc auto sel
- clk_set_parent_nolock(&aclk_lcdc0_pre, &general_pll_clk);
- clk_set_parent_nolock(&aclk_lcdc1_pre, &general_pll_clk);
- clk_set_rate_nolock(&aclk_lcdc0_pre, 300 * MHZ);
- clk_set_rate_nolock(&aclk_lcdc1_pre, 300 * MHZ);
-
- //axi vepu auto sel
- //clk_set_parent_nolock(&aclk_vepu, &general_pll_clk);
- //clk_set_parent_nolock(&aclk_vdpu, &general_pll_clk);
-
- clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
- clk_set_rate_nolock(&aclk_vdpu, 300 * MHZ);
-
- if(rk30_clock_flags&CLK_GPU_GPLL)
- {
- clk_set_parent_nolock(&clk_gpu, &general_pll_clk);
- clk_set_parent_nolock(&aclk_gpu, &general_pll_clk);
-
- }
- else
- {
- clk_set_parent_nolock(&clk_gpu, &codec_pll_clk);
- clk_set_parent_nolock(&aclk_gpu, &codec_pll_clk);
- }
- clk_set_rate_nolock(&clk_gpu, 200 * MHZ);
- clk_set_rate_nolock(&aclk_gpu, 200 * MHZ);
-
- clk_set_rate_nolock(&clk_uart0, 49500000);
- clk_set_rate_nolock(&clk_sdmmc, 24750000);
- clk_set_rate_nolock(&clk_sdio, 24750000);
-}
-
-static struct clk def_ops_clk = {
- .get_parent = clksel_get_parent,
- .set_parent = clksel_set_parent,
-};
-
-#ifdef CONFIG_PROC_FS
-struct clk_dump_ops dump_ops;
-#endif
-void rk_dump_clock_info(void);
-
-void __init _rk30_clock_data_init(unsigned long gpll, unsigned long cpll, int flags)
-{
- struct clk_lookup *lk;
-
- rk_efuse_init();
- clk_register_dump_ops(&dump_ops);
- clk_register_default_ops_clk(&def_ops_clk);
- rk30_clock_flags = flags;
- for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) {
-#ifdef RK30_CLK_OFFBOARD_TEST
- rk30_clkdev_add(lk);
-#else
- clkdev_add(lk);
-#endif
- clk_register(lk->clk);
- }
- clk_recalculate_root_clocks_nolock();
-
- loops_per_jiffy = CLK_LOOPS_RECALC(arm_pll_clk.rate);
-
- /*
- * Only enable those clocks we will need, let the drivers
- * enable other clocks as necessary
- */
- rk30_init_enable_clocks();
-#if 0
- // print loader config
- rk_dump_clock_info();
- while(1);
-#endif
- /*
- * Disable any unused clocks left on by the bootloader
- */
- //clk_disable_unused();
- rk30_clock_common_init(gpll, cpll);
- preset_lpj = loops_per_jiffy;
-
- //gpio6_b7
- //regfile_writel(0xc0004000,0x10c);
- //cru_writel(0x07000000,CRU_MISC_CON);
-
-}
-
-void __init rk30_clock_data_init(unsigned long gpll, unsigned long cpll, u32 flags)
-{
- _rk30_clock_data_init(gpll, cpll, flags);
- rk_dvfs_init();
-}
-
-/*
- * You can override arm_clk rate with armclk= cmdline option.
- */
-static int __init armclk_setup(char *str)
-{
- get_option(&str, &armclk);
-
- if (!armclk)
- return 0;
- if (armclk < 10000)
- armclk *= MHZ;
- //clk_set_rate_nolock(&arm_pll_clk, armclk);
- return 0;
-}
-#ifndef RK30_CLK_OFFBOARD_TEST
-early_param("armclk", armclk_setup);
-#endif
-
-
-static void rk_dump_clock(struct clk *clk, int deep, const struct list_head *root_clocks)
-{
- struct clk *ck;
- int i;
- unsigned long rate = clk->rate;
- //CLKDATA_DBG("dump_clock %s\n",clk->name);
- for (i = 0; i < deep; i++)
- printk(" ");
-
- printk("%-11s ", clk->name);
-#ifndef RK30_CLK_OFFBOARD_TEST
- if (clk->flags & IS_PD) {
- printk("%s ", pmu_power_domain_is_on(clk->gate_idx) ? "on " : "off");
- }
-#endif
- if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
- int idx = clk->gate_idx;
- u32 v;
- v = cru_readl(CLK_GATE_CLKID_CONS(idx)) & ((0x1) << (idx % 16));
- printk("%s ", v ? "off" : "on ");
- }
-
- if (clk->pll) {
- u32 pll_mode;
- u32 pll_id = clk->pll->id;
- pll_mode = cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id);
- if (pll_mode == (PLL_MODE_SLOW(pll_id) & PLL_MODE_MSK(pll_id)))
- printk("slow ");
- else if (pll_mode == (PLL_MODE_NORM(pll_id) & PLL_MODE_MSK(pll_id)))
- printk("normal ");
- else if (pll_mode == (PLL_MODE_DEEP(pll_id) & PLL_MODE_MSK(pll_id)))
- printk("deep ");
-
- if(cru_readl(PLL_CONS(pll_id, 3)) & PLL_BYPASS)
- printk("bypass ");
- } else if(clk == &clk_ddr) {
- rate = clk->recalc(clk);
- }
-
- if (rate >= MHZ) {
- if (rate % MHZ)
- printk("%ld.%06ld MHz", rate / MHZ, rate % MHZ);
- else
- printk("%ld MHz", rate / MHZ);
- } else if (rate >= KHZ) {
- if (rate % KHZ)
- printk("%ld.%03ld KHz", rate / KHZ, rate % KHZ);
- else
- printk("%ld KHz", rate / KHZ);
- } else {
- printk("%ld Hz", rate);
- }
-
- printk(" usecount = %d", clk->usecount);
-
- if (clk->parent)
- printk(" parent = %s", clk->parent->name);
-
- printk("\n");
-
- list_for_each_entry(ck, root_clocks, node) {
- if (ck->parent == clk)
- rk_dump_clock(ck, deep + 1, root_clocks);
- }
-}
-
-#if 1
-struct list_head *get_rk_clocks_head(void);
-
-void rk_dump_clock_info(void)
-{
- struct clk* clk;
- list_for_each_entry(clk, get_rk_clocks_head(), node) {
- if (!clk->parent)
- rk_dump_clock(clk, 0,get_rk_clocks_head());
- }
-}
-#endif
-
-#ifdef CONFIG_PROC_FS
-
-static void dump_clock(struct seq_file *s, struct clk *clk, int deep, const struct list_head *root_clocks)
-{
- struct clk *ck;
- int i;
- unsigned long rate = clk->rate;
- //CLKDATA_DBG("dump_clock %s\n",clk->name);
- for (i = 0; i < deep; i++)
- seq_printf(s, " ");
-
- seq_printf(s, "%-11s ", clk->name);
-#ifndef RK30_CLK_OFFBOARD_TEST
- if (clk->flags & IS_PD) {
- seq_printf(s, "%s ", pmu_power_domain_is_on(clk->gate_idx) ? "on " : "off");
- }
-#endif
- if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
- int idx = clk->gate_idx;
- u32 v;
- v = cru_readl(CLK_GATE_CLKID_CONS(idx)) & ((0x1) << (idx % 16));
- seq_printf(s, "%s ", v ? "off" : "on ");
- }
-
- if (clk->pll) {
- u32 pll_mode;
- u32 pll_id = clk->pll->id;
- pll_mode = cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id);
- if (pll_mode == (PLL_MODE_SLOW(pll_id) & PLL_MODE_MSK(pll_id)))
- seq_printf(s, "slow ");
- else if (pll_mode == (PLL_MODE_NORM(pll_id) & PLL_MODE_MSK(pll_id)))
- seq_printf(s, "normal ");
- else if (pll_mode == (PLL_MODE_DEEP(pll_id) & PLL_MODE_MSK(pll_id)))
- seq_printf(s, "deep ");
-
- if(cru_readl(PLL_CONS(pll_id, 3)) & PLL_BYPASS)
- seq_printf(s, "bypass ");
- } else if(clk == &clk_ddr) {
- rate = clk->recalc(clk);
- }
-
- if (rate >= MHZ) {
- if (rate % MHZ)
- seq_printf(s, "%ld.%06ld MHz", rate / MHZ, rate % MHZ);
- else
- seq_printf(s, "%ld MHz", rate / MHZ);
- } else if (rate >= KHZ) {
- if (rate % KHZ)
- seq_printf(s, "%ld.%03ld KHz", rate / KHZ, rate % KHZ);
- else
- seq_printf(s, "%ld KHz", rate / KHZ);
- } else {
- seq_printf(s, "%ld Hz", rate);
- }
-
- seq_printf(s, " usecount = %d", clk->usecount);
-
- if (clk->parent)
- seq_printf(s, " parent = %s", clk->parent->name);
-
- seq_printf(s, "\n");
-
- list_for_each_entry(ck, root_clocks, node) {
- if (ck->parent == clk)
- dump_clock(s, ck, deep + 1, root_clocks);
- }
-}
-
-static void dump_regs(struct seq_file *s)
-{
- int i = 0;
- seq_printf(s, "\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
- seq_printf(s, "\nPLLRegisters:\n");
- for(i = 0; i < END_PLL_ID; i++) {
- seq_printf(s, "pll%d :cons:%x,%x,%x,%x\n", i,
- cru_readl(PLL_CONS(i, 0)),
- cru_readl(PLL_CONS(i, 1)),
- cru_readl(PLL_CONS(i, 2)),
- cru_readl(PLL_CONS(i, 3))
- );
- }
- seq_printf(s, "MODE :%x\n", cru_readl(CRU_MODE_CON));
-
- for(i = 0; i < CRU_CLKSELS_CON_CNT; i++) {
- seq_printf(s, "CLKSEL%d :%x\n", i, cru_readl(CRU_CLKSELS_CON(i)));
- }
- for(i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
- seq_printf(s, "CLKGATE%d :%x\n", i, cru_readl(CRU_CLKGATES_CON(i)));
- }
- seq_printf(s, "GLB_SRST_FST:%x\n", cru_readl(CRU_GLB_SRST_FST));
- seq_printf(s, "GLB_SRST_SND:%x\n", cru_readl(CRU_GLB_SRST_SND));
-
- for(i = 0; i < CRU_SOFTRSTS_CON_CNT; i++) {
- seq_printf(s, "CLKGATE%d :%x\n", i, cru_readl(CRU_SOFTRSTS_CON(i)));
- }
- seq_printf(s, "CRU MISC :%x\n", cru_readl(CRU_MISC_CON));
- seq_printf(s, "GLB_CNT_TH :%x\n", cru_readl(CRU_GLB_CNT_TH));
-
-}
-
-void rk30_clk_dump_regs(void)
-{
- int i = 0;
- printk("\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
- printk("\nPLLRegisters:\n");
- for(i = 0; i < END_PLL_ID; i++) {
- printk("pll%d :cons:%x,%x,%x,%x\n", i,
- cru_readl(PLL_CONS(i, 0)),
- cru_readl(PLL_CONS(i, 1)),
- cru_readl(PLL_CONS(i, 2)),
- cru_readl(PLL_CONS(i, 3))
- );
- }
- printk("MODE :%x\n", cru_readl(CRU_MODE_CON));
-
- for(i = 0; i < CRU_CLKSELS_CON_CNT; i++) {
- printk("CLKSEL%d :%x\n", i, cru_readl(CRU_CLKSELS_CON(i)));
- }
- for(i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
- printk("CLKGATE%d :%x\n", i, cru_readl(CRU_CLKGATES_CON(i)));
- }
- printk("GLB_SRST_FST:%x\n", cru_readl(CRU_GLB_SRST_FST));
- printk("GLB_SRST_SND:%x\n", cru_readl(CRU_GLB_SRST_SND));
-
- for(i = 0; i < CRU_SOFTRSTS_CON_CNT; i++) {
- printk("SOFTRST%d :%x\n", i, cru_readl(CRU_SOFTRSTS_CON(i)));
- }
- printk("CRU MISC :%x\n", cru_readl(CRU_MISC_CON));
- printk("GLB_CNT_TH :%x\n", cru_readl(CRU_GLB_CNT_TH));
-
-}
-
-
-#ifdef CONFIG_PROC_FS
-static void dump_clock(struct seq_file *s, struct clk *clk, int deep, const struct list_head *root_clocks);
-struct clk_dump_ops dump_ops = {
- .dump_clk = dump_clock,
- .dump_regs = dump_regs,
-};
-#endif
-
-
-#endif /* CONFIG_PROC_FS */
-
-
-
-
-#ifdef RK30_CLK_OFFBOARD_TEST
-struct clk *test_get_parent(struct clk *clk) {
- return clk->parent;
-}
-
-void i2s_test(void)
-{
- struct clk *i2s_clk = &clk_i2s0;
-
- clk_enable_nolock(i2s_clk);
-
- clk_set_rate_nolock(i2s_clk, 12288000);
- printk("int %s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
- clk_set_rate_nolock(i2s_clk, 297 * MHZ / 2);
- printk("int%s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
- clk_set_rate_nolock(i2s_clk, 12 * MHZ);
- printk("int%s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
-
-}
-
-void uart_test(void)
-{
- struct clk *uart_clk = &clk_uart0;
-
- clk_enable_nolock(uart_clk);
-
- clk_set_rate_nolock(uart_clk, 12288000);
- printk("int %s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
- clk_set_rate_nolock(uart_clk, 297 * MHZ / 2);
- printk("int%s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
- clk_set_rate_nolock(uart_clk, 12 * MHZ);
- printk("int%s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
-
-}
-void hsadc_test(void)
-{
- struct clk *hsadc_clk = &clk_hsadc;
-
- printk("******************hsadc_test**********************\n");
- clk_enable_nolock(hsadc_clk);
-
- clk_set_rate_nolock(hsadc_clk, 12288000);
- printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
-
-
- clk_set_rate_nolock(hsadc_clk, 297 * MHZ / 2);
- printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
-
- clk_set_rate_nolock(hsadc_clk, 300 * MHZ / 2);
-
- clk_set_rate_nolock(hsadc_clk, 296 * MHZ / 2);
-
- printk("******************hsadc out clock**********************\n");
-
- clk_set_parent_nolock(hsadc_clk, &clk_hsadc_ext);
- printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
- clk_set_rate_nolock(hsadc_clk, 297 * MHZ / 2);
- printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
-
-
-
-}
-
-static void __init rk30_clock_test_init(unsigned long ppll_rate)
-{
- //arm
- printk("*********arm_pll_clk***********\n");
- clk_set_rate_nolock(&arm_pll_clk, 816 * MHZ);
-
- printk("*********set clk_core parent***********\n");
- clk_set_parent_nolock(&clk_core, &arm_pll_clk);
- clk_set_rate_nolock(&clk_core, 504 * MHZ);
-
- //general
- printk("*********general_pll_clk***********\n");
- clk_set_rate_nolock(&general_pll_clk, ppll_rate);
-
- //code pll
- printk("*********codec_pll_clk***********\n");
- clk_set_rate_nolock(&codec_pll_clk, 600 * MHZ);
-
-
- printk("*********periph_clk_set_init***********\n");
- clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
- periph_clk_set_init();
-
-#if 0 //
- clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
-#else
- printk("*********clk i2s***********\n");
- clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
- printk("common %s parent is %s\n", clk_i2s_pll.name, test_get_parent(&clk_i2s_pll)->name);
- i2s_test();
-#endif
- // spi
- clk_enable_nolock(&clk_spi0);
- clk_set_rate_nolock(&clk_spi0, 30 * MHZ);
- printk("common %s parent is %s\n", clk_spi0.name, test_get_parent(&clk_spi0)->name);
- //saradc
- clk_enable_nolock(&clk_saradc);
- clk_set_rate_nolock(&clk_saradc, 6 * MHZ);
- printk("common %s parent is %s\n", clk_saradc.name, test_get_parent(&clk_saradc)->name);
- //sdio
- clk_enable_nolock(&clk_sdio);
- clk_set_rate_nolock(&clk_sdio, 50 * MHZ);
- printk("common %s parent is %s\n", clk_sdio.name, test_get_parent(&clk_sdio)->name);
- // uart
- clk_set_parent_nolock(&clk_uart_pll, &general_pll_clk);
- uart_test();
- //mac
- printk("*********mac***********\n");
-
- clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
- printk("common %s parent is %s\n", clk_mac_pll_div.name, test_get_parent(&clk_mac_pll_div)->name);
-
- //clk_set_parent_nolock(&clk_mac_ref, &clk_mac_pll_div);
- clk_set_rate_nolock(&clk_mac_ref, 50 * MHZ);
- printk("common %s parent is %s\n", clk_mac_ref.name, test_get_parent(&clk_mac_ref)->name);
-
- printk("*********mac mii set***********\n");
- clk_set_parent_nolock(&clk_mac_ref, &rmii_clkin);
- clk_set_rate_nolock(&clk_mac_ref, 20 * MHZ);
- printk("common %s parent is %s\n", clk_mac_ref.name, test_get_parent(&clk_mac_ref)->name);
- //hsadc
- printk("*********hsadc 1***********\n");
- //auto pll
- hsadc_test();
- //lcdc
- clk_enable_nolock(&dclk_lcdc0);
-
- clk_set_rate_nolock(&dclk_lcdc0, 60 * MHZ);
- clk_set_rate_nolock(&dclk_lcdc0, 27 * MHZ);
-
- //cif
- clk_enable_nolock(&cif0_out);
-
- clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
- printk("common %s parent is %s\n", cif_out_pll.name, test_get_parent(&cif_out_pll)->name);
-
- clk_set_rate_nolock(&cif0_out, 60 * MHZ);
- printk("common %s parent is %s\n", cif0_out.name, test_get_parent(&cif0_out)->name);
-
- clk_set_rate_nolock(&cif0_out, 24 * MHZ);
- printk("common %s parent is %s\n", cif0_out.name, test_get_parent(&cif0_out)->name);
- //cif_in
- clk_enable_nolock(&cif0_in);
- clk_set_rate_nolock(&cif0_in, 24 * MHZ);
- //axi lcdc
- clk_enable_nolock(&aclk_lcdc0);
- clk_set_rate_nolock(&aclk_lcdc0, 150 * MHZ);
- printk("common %s parent is %s\n", aclk_lcdc0.name, test_get_parent(&aclk_lcdc0)->name);
- //axi vepu
- clk_enable_nolock(&aclk_vepu);
- clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
- printk("common %s parent is %s\n", aclk_vepu.name, test_get_parent(&aclk_vepu)->name);
-
- clk_set_rate_nolock(&hclk_vepu, 300 * MHZ);
- printk("common %s parent is %s\n", hclk_vepu.name, test_get_parent(&hclk_vepu)->name);
-
- printk("test end\n");
-
- /* arm pll
- clk_set_rate_nolock(&arm_pll_clk, armclk);
- clk_set_rate_nolock(&clk_core, armclk);//pll:core =1:1
- */
- //
- //clk_set_rate_nolock(&codec_pll_clk, ppll_rate*2);
- //
- //clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
- //clk_set_rate_nolock(&clk_gpu, 300 * MHZ);
-
-}
-
-
-
-
-
-static LIST_HEAD(rk30_clocks);
-static DEFINE_MUTEX(rk30_clocks_mutex);
-
-static inline int __rk30clk_get(struct clk *clk)
-{
- return 1;
-}
-void rk30_clkdev_add(struct clk_lookup *cl)
-{
- mutex_lock(&rk30_clocks_mutex);
- list_add_tail(&cl->node, &rk30_clocks);
- mutex_unlock(&rk30_clocks_mutex);
-}
-static struct clk_lookup *rk30_clk_find(const char *dev_id, const char *con_id) {
- struct clk_lookup *p, *cl = NULL;
- int match, best = 0;
-
- list_for_each_entry(p, &rk30_clocks, node) {
- match = 0;
- if (p->dev_id) {
- if (!dev_id || strcmp(p->dev_id, dev_id))
- continue;
- match += 2;
- }
- if (p->con_id) {
- if (!con_id || strcmp(p->con_id, con_id))
- continue;
- match += 1;
- }
-
- if (match > best) {
- cl = p;
- if (match != 3)
- best = match;
- else
- break;
- }
- }
- return cl;
-}
-
-struct clk *rk30_clk_get_sys(const char *dev_id, const char *con_id) {
- struct clk_lookup *cl;
-
- mutex_lock(&rk30_clocks_mutex);
- cl = rk30_clk_find(dev_id, con_id);
- if (cl && !__rk30clk_get(cl->clk))
- cl = NULL;
- mutex_unlock(&rk30_clocks_mutex);
-
- return cl ? cl->clk : ERR_PTR(-ENOENT);
-}
-//EXPORT_SYMBOL(rk30_clk_get_sys);
-
-struct clk *rk30_clk_get(struct device *dev, const char *con_id) {
- const char *dev_id = dev ? dev_name(dev) : NULL;
- return rk30_clk_get_sys(dev_id, con_id);
-}
-//EXPORT_SYMBOL(rk30_clk_get);
-
-
-int rk30_clk_set_rate(struct clk *clk, unsigned long rate);
-
-void rk30_clocks_test(void)
-{
- struct clk *test_gpll;
- test_gpll = rk30_clk_get(NULL, "general_pll");
- if(test_gpll) {
- rk30_clk_set_rate(test_gpll, 297 * 2 * MHZ);
- printk("gpll rate=%lu\n", test_gpll->rate);
- }
- //while(1);
-}
-
-void __init rk30_clock_init_test(void)
-{
-
- rk30_clock_init(periph_pll_297mhz, codec_pll_360mhz, max_i2s_12288khz);
- //while(1);
-}
-
-
-#endif
-
-
+++ /dev/null
-/* linux/arch/arm/mach-rk30/clock_data.c
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/hardirq.h>
-#include <mach/cru.h>
-#include <mach/iomux.h>
-#include <mach/clock.h>
-#include <mach/pmu.h>
-#include <mach/dvfs.h>
-#include <mach/ddr.h>
-
-#define MHZ (1000*1000)
-#define KHZ (1000)
-#define CLK_LOOPS_JIFFY_REF 11996091ULL
-#define CLK_LOOPS_RATE_REF (1200) //Mhz
-#define CLK_LOOPS_RECALC(new_rate) div_u64(CLK_LOOPS_JIFFY_REF*(new_rate),CLK_LOOPS_RATE_REF*MHZ)
-
-//flags bit
-//has extern 27mhz
-#define CLK_FLG_EXT_27MHZ (1<<0)
-//max i2s rate
-#define CLK_FLG_MAX_I2S_12288KHZ (1<<1)
-#define CLK_FLG_MAX_I2S_22579_2KHZ (1<<2)
-#define CLK_FLG_MAX_I2S_24576KHZ (1<<3)
-#define CLK_FLG_MAX_I2S_49152KHZ (1<<4)
-//uart 1m\3m
-#define CLK_FLG_UART_1_3M (1<<5)
-#define CLK_CPU_HPCLK_11 (1<<6)
-
-
-
-struct apll_clk_set {
- unsigned long rate;
- u32 pllcon0;
- u32 pllcon1;
- u32 pllcon2; //nb=bwadj+1;0:11;nb=nf/2
- u32 rst_dly;//us
- u32 clksel0;
- u32 clksel1;
- unsigned long lpj;
-};
-struct pll_clk_set {
- unsigned long rate;
- u32 pllcon0;
- u32 pllcon1;
- u32 pllcon2; //nb=bwadj+1;0:11;nb=nf/2
- u32 rst_dly;//us
-};
-
-#define SET_PLL_DATA(_pll_id,_table) \
-{\
- .id=(_pll_id),\
- .table=(_table),\
-}
-
-
-#define _PLL_SET_CLKS(_mhz, nr, nf, no) \
-{ \
- .rate = (_mhz) * KHZ, \
- .pllcon0 = PLL_CLKR_SET(nr)|PLL_CLKOD_SET(no), \
- .pllcon1 = PLL_CLKF_SET(nf),\
- .pllcon2 = PLL_CLK_BWADJ_SET(nf/2-1),\
- .rst_dly=((nr*500)/24+1),\
- }
-
-
-#define _APLL_SET_LPJ(_mhz) \
- .lpj= (CLK_LOOPS_JIFFY_REF * _mhz)/CLK_LOOPS_RATE_REF
-
-
-#define _APLL_SET_CLKS(_mhz, nr, nf, no, _periph_div,_axi_div,_ahb_div, _apb_div,_ahb2apb) \
- { \
- .rate = _mhz * MHZ, \
- .pllcon0 = PLL_CLKR_SET(nr)|PLL_CLKOD_SET(no),\
- .pllcon1 = PLL_CLKF_SET(nf),\
- .pllcon2 = PLL_CLK_BWADJ_SET(nf>>1),\
- .clksel0 = CORE_PERIPH_W_MSK|CORE_PERIPH_##_periph_div,\
- .clksel1 = CORE_ACLK_W_MSK|CORE_ACLK_##_axi_div\
- |ACLK_HCLK_W_MSK|ACLK_HCLK_##_ahb_div\
- |ACLK_PCLK_W_MSK|ACLK_PCLK_##_apb_div\
- |AHB2APB_W_MSK |AHB2APB_##_ahb2apb,\
- _APLL_SET_LPJ(_mhz),\
- .rst_dly=((nr*500)/24+1),\
- }
-
-#define CRU_DIV_SET(mask,shift,max) \
- .div_mask=(mask),\
- .div_shift=(shift),\
- .div_max=(max)
-
-
-#define CRU_SRC_SET(mask,shift ) \
- .src_mask=(mask),\
- .src_shift=(shift)
-
-#define CRU_PARENTS_SET(parents_array) \
- .parents=(parents_array),\
- .parents_num=ARRAY_SIZE((parents_array))
-
-#define CRU_GATE_MODE_SET(_func,_IDX) \
- .mode=_func,\
- .gate_idx=(_IDX)
-
-struct clk_src_sel {
- struct clk *parent;
- u8 value;//crt bit
- u8 flag;
-//selgate
-};
-
-#define GATE_CLK(NAME,PARENT,ID) \
-static struct clk clk_##NAME = { \
- .name = #NAME, \
- .parent = &PARENT, \
- .mode = gate_mode, \
- .gate_idx = CLK_GATE_##ID, \
-}
-#ifdef RK30_CLK_OFFBOARD_TEST
-u32 TEST_GRF_REG[0x240];
-u32 TEST_CRU_REG[0x240];
-#define cru_readl(offset) (TEST_CRU_REG[offset/4])
-
-u32 cru_writel_is_pr(u32 offset)
-{
- return (offset==0x4000);
-}
-void cru_writel(u32 v, u32 offset)
-{
-
- u32 mask_v=v>>16;
- TEST_CRU_REG[offset/4]&=(~mask_v);
-
- v&=(mask_v);
-
- TEST_CRU_REG[offset/4]|=v;
- TEST_CRU_REG[offset/4]&=0x0000ffff;
-
- if(cru_writel_is_pr(offset))
- {
- CRU_PRINTK_DBG("cru w offset=%d,set=%x,reg=%x\n",offset,v,TEST_CRU_REG[offset/4]);
-
- }
-
-}
-void cru_writel_i2s(u32 v, u32 offset)
-{
- TEST_CRU_REG[offset/4]=v;
-}
-#define cru_writel_frac(v,offset) cru_writel_i2s((v),(offset))
-
-#define regfile_readl(offset) (0xffffffff)
-//#define pmu_readl(offset) readl(RK30_GRF_BASE + offset)
-void rk30_clkdev_add(struct clk_lookup *cl);
-#else
-#define regfile_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
-#define regfile_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
-#define cru_readl(offset) readl_relaxed(RK30_CRU_BASE + offset)
-#define cru_writel(v, offset) do { writel_relaxed(v, RK30_CRU_BASE + offset); dsb(); } while (0)
-
-#define cru_writel_frac(v,offset) cru_writel((v),(offset))
-#endif
-
-#ifdef DEBUG
-#define CRU_PRINTK_DBG(fmt, args...) pr_debug(fmt, ## args)
-#define CRU_PRINTK_LOG(fmt, args...) pr_debug(fmt, ## args)
-#else
-#define CRU_PRINTK_DBG(fmt, args...) do {} while(0)
-#define CRU_PRINTK_LOG(fmt, args...) do {} while(0)
-#endif
-#define CRU_PRINTK_ERR(fmt, args...) pr_err(fmt, ## args)
-
-
-#define get_cru_bits(con,mask,shift)\
- ((cru_readl((con)) >> (shift)) & (mask))
-
-#define set_cru_bits_w_msk(val,mask,shift,con)\
- cru_writel(((mask)<<(shift+16))|((val)<<(shift)),(con))
-
-
-#define PLLS_IN_NORM(pll_id) (((cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id))==(PLL_MODE_NORM(pll_id)&PLL_MODE_MSK(pll_id)))\
- &&!(cru_readl(PLL_CONS(pll_id,3))&PLL_BYPASS))
-
-
-static u32 rk30_clock_flags=0;
-static struct clk codec_pll_clk;
-static struct clk general_pll_clk;
-static struct clk arm_pll_clk;
-static unsigned long lpj_gpll;
-static unsigned int __initdata armclk = 504*MHZ;
-
-
-/************************clk recalc div rate*********************************/
-
-//for free div
-static unsigned long clksel_recalc_div(struct clk *clk)
-{
- u32 div = get_cru_bits(clk->clksel_con,clk->div_mask,clk->div_shift) + 1;
-
- unsigned long rate = clk->parent->rate / div;
- pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, div);
- return rate;
-}
-
-//for div 1 2 4 2^n
-static unsigned long clksel_recalc_shift(struct clk *clk)
-{
- u32 shift = get_cru_bits(clk->clksel_con,clk->div_mask,clk->div_shift);
- unsigned long rate = clk->parent->rate >> shift;
- pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
- return rate;
-}
-
-
-static unsigned long clksel_recalc_shift_2(struct clk *clk)
-{
- u32 shift = get_cru_bits(clk->clksel_con,clk->div_mask,clk->div_shift)+1;
- unsigned long rate = clk->parent->rate >> shift;
- pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
- return rate;
-}
-
-static unsigned long clksel_recalc_parent_rate(struct clk *clk)
-{
- unsigned long rate = clk->parent->rate;
- pr_debug("%s new clock rate is %lu\n", clk->name, rate);
- return rate;
-}
-/********************************set div rate***********************************/
-
-//for free div
-static int clksel_set_rate_freediv(struct clk *clk, unsigned long rate)
-{
- u32 div;
- for (div = 0; div < clk->div_max; div++) {
- u32 new_rate = clk->parent->rate / (div + 1);
- if (new_rate <= rate) {
- set_cru_bits_w_msk(div,clk->div_mask,clk->div_shift,clk->clksel_con);
- //clk->rate = new_rate;
- pr_debug("clksel_set_rate_freediv for clock %s to rate %ld (div %d)\n", clk->name, rate, div + 1);
- return 0;
- }
- }
- return -ENOENT;
-}
-
-//for div 1 2 4 2^n
-static int clksel_set_rate_shift(struct clk *clk, unsigned long rate)
-{
- u32 shift;
- for (shift = 0; (1 << shift) < clk->div_max; shift++) {
- u32 new_rate = clk->parent->rate >> shift;
- if (new_rate <= rate) {
- set_cru_bits_w_msk(shift,clk->div_mask,clk->div_shift,clk->clksel_con);
- clk->rate = new_rate;
- pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n", clk->name, rate, shift);
- return 0;
- }
- }
- return -ENOENT;
-}
-
-//for div 2 4 2^n
-static int clksel_set_rate_shift_2(struct clk *clk, unsigned long rate)
-{
- u32 shift;
-
- for (shift = 1; (1 << shift) < clk->div_max; shift++) {
- u32 new_rate = clk->parent->rate >> shift;
- if (new_rate <= rate) {
- set_cru_bits_w_msk(shift-1,clk->div_mask,clk->div_shift,clk->clksel_con);
- clk->rate = new_rate;
- pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n", clk->name, rate, shift);
- return 0;
- }
- }
- return -ENOENT;
-}
-
-//for div 1 2 4 2*n
-static int clksel_set_rate_even(struct clk *clk, unsigned long rate)
-{
- u32 div = 0, new_rate = 0;
- for (div = 1; div < clk->div_max; div++) {
- if (div >= 3 && div % 2 != 0)
- continue;
- new_rate = clk->parent->rate / div;
- if (new_rate <= rate) {
- set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
- clk->rate = new_rate;
- pr_debug("%s for clock %s to rate %ld (even div = %d)\n",
- __func__, clk->name, rate, div);
- return 0;
- }
- }
- return -ENOENT;
-}
-
-static u32 clk_get_freediv(unsigned long rate_out, unsigned long rate ,u32 div_max)
-{
- u32 div;
- unsigned long new_rate;
- for (div = 0; div <div_max; div++) {
- new_rate = rate / (div + 1);
- if (new_rate <= rate_out) {
- return div+1;
- }
- }
- return div_max?div_max:1;
-}
-struct clk *get_freediv_parents_div(struct clk *clk,unsigned long rate,u32 *div_out)
-{
- u32 div[2]={0,0};
- unsigned long new_rate[2]={0,0};
- u32 i;
-
- if(clk->rate==rate)
- return clk->parent;
- for(i=0;i<2;i++)
- {
- div[i]=clk_get_freediv(rate,clk->parents[i]->rate,clk->div_max);
- new_rate[i] = clk->parents[i]->rate/div[i];
- if(new_rate[i]==rate)
- {
- *div_out=div[i];
- return clk->parents[i];
- }
- }
- if(new_rate[0]<new_rate[1])
- i=1;
- else
- i=0;
- *div_out=div[i];
- return clk->parents[i];
-}
-
-static int clkset_rate_freediv_autosel_parents(struct clk *clk, unsigned long rate)
-{
- struct clk *p_clk;
- u32 div,old_div;
- int ret=0;
- if(clk->rate==rate)
- return 0;
- p_clk=get_freediv_parents_div(clk,rate,&div);
-
- if(!p_clk)
- return -ENOENT;
-
- CRU_PRINTK_DBG("%s %lu,form %s\n",clk->name,rate,p_clk->name);
- if (clk->parent != p_clk)
- {
- old_div=CRU_GET_REG_BIYS_VAL(cru_readl(clk->clksel_con),clk->div_shift,clk->div_mask)+1;
-
- if(div>old_div)
- {
- set_cru_bits_w_msk(div-1,clk->div_mask,clk->div_shift,clk->clksel_con);
- }
- ret=clk_set_parent_nolock(clk,p_clk);
- if(ret)
- {
- CRU_PRINTK_ERR("%s can't set %lu,reparent err\n",clk->name,rate);
- return -ENOENT;
- }
- }
- //set div
- set_cru_bits_w_msk(div-1,clk->div_mask,clk->div_shift,clk->clksel_con);
- return 0;
-}
-
-//rate==div rate //hdmi
-static int clk_freediv_autosel_parents_set_fixed_rate(struct clk *clk, unsigned long rate)
-{
- struct clk *p_clk;
- u32 div,old_div;
- int ret;
- p_clk=get_freediv_parents_div(clk,rate,&div);
-
- if(!p_clk)
- return -ENOENT;
-
- if((p_clk->rate/div)!=rate||(p_clk->rate%div))
- return -ENOENT;
-
- if (clk->parent != p_clk)
- {
- old_div=CRU_GET_REG_BIYS_VAL(cru_readl(clk->clksel_con),
- clk->div_shift,clk->div_mask)+1;
- if(div>old_div)
- {
- set_cru_bits_w_msk(div-1,clk->div_mask,clk->div_shift,clk->clksel_con);
- }
- ret=clk_set_parent_nolock(clk,p_clk);
- if (ret)
- {
- CRU_PRINTK_DBG("%s can't get rate%lu,reparent err\n",clk->name,rate);
- return ret;
- }
- }
- //set div
- set_cru_bits_w_msk(div-1,clk->div_mask,clk->div_shift,clk->clksel_con);
- return 0;
-}
-
-/***************************round********************************/
-
-static long clksel_freediv_round_rate(struct clk *clk, unsigned long rate)
-{
- return clk->parent->rate/clk_get_freediv(rate,clk->parent->rate,clk->div_max);
-}
-
-static long clk_freediv_round_autosel_parents_rate(struct clk *clk, unsigned long rate)
-{
- u32 div;
- struct clk *p_clk;
- if(clk->rate == rate)
- return clk->rate;
- p_clk=get_freediv_parents_div(clk,rate,&div);
- if(!p_clk)
- return 0;
- return p_clk->rate/div;
-}
-
-/**************************************others seting************************************/
-
-static struct clk* clksel_get_parent(struct clk *clk)
-{
- return clk->parents[(cru_readl(clk->clksel_con) >> clk->src_shift) & clk->src_mask];
-}
-static int clksel_set_parent(struct clk *clk, struct clk *parent)
-{
- u32 i;
- if (unlikely(!clk->parents))
- return -EINVAL;
- for (i = 0; (i <clk->parents_num); i++) {
- if (clk->parents[i]!= parent)
- continue;
- set_cru_bits_w_msk(i,clk->src_mask,clk->src_shift,clk->clksel_con);
- return 0;
- }
- return -EINVAL;
-}
-
-static int gate_mode(struct clk *clk, int on)
-{
- int idx = clk->gate_idx;
- if (idx >= CLK_GATE_MAX)
- return -EINVAL;
- if(on)
- {
- cru_writel(CLK_GATE_W_MSK(idx)|CLK_UN_GATE(idx), CLK_GATE_CLKID_CONS(idx));
- //CRU_PRINTK_DBG("un gate id=%d %s(%x),con %x\n",idx,clk->name,
- // CLK_GATE_W_MSK(idx)|CLK_UN_GATE(idx),CLK_GATE_CLKID_CONS(idx));
- }
- else
- {
- cru_writel(CLK_GATE_W_MSK(idx)|CLK_GATE(idx), CLK_GATE_CLKID_CONS(idx));
- // CRU_PRINTK_DBG("gate id=%d %s(%x),con%x\n",idx,clk->name,
- // CLK_GATE_W_MSK(idx)|CLK_GATE(idx),CLK_GATE_CLKID_CONS(idx));
- }
- return 0;
-}
-/*****************************frac set******************************************/
-
-static unsigned long clksel_recalc_frac(struct clk *clk)
-{
- unsigned long rate;
- u64 rate64;
- u32 r = cru_readl(clk->clksel_con), numerator, denominator;
- if (r == 0) // FPGA ?
- return clk->parent->rate;
- numerator = r >> 16;
- denominator = r & 0xFFFF;
- rate64 = (u64)clk->parent->rate * numerator;
- do_div(rate64, denominator);
- rate = rate64;
- pr_debug("%s new clock rate is %lu (frac %u/%u)\n", clk->name, rate, numerator, denominator);
- return rate;
-}
-
-static u32 clk_gcd(u32 numerator, u32 denominator)
-{
- u32 a, b;
-
- if (!numerator || !denominator)
- return 0;
- if (numerator > denominator) {
- a = numerator;
- b = denominator;
- } else {
- a = denominator;
- b = numerator;
- }
- while (b != 0) {
- int r = b;
- b = a % b;
- a = r;
- }
-
- return a;
-}
-
-static int frac_div_get_seting(unsigned long rate_out,unsigned long rate,
- u32 *numerator,u32 *denominator)
-{
- u32 gcd_vl;
- gcd_vl = clk_gcd(rate, rate_out);
- CRU_PRINTK_DBG("frac_get_seting rate=%lu,parent=%lu,gcd=%d\n",rate_out,rate, gcd_vl);
-
- if (!gcd_vl) {
- CRU_PRINTK_ERR("gcd=0, i2s frac div is not be supported\n");
- return -ENOENT;
- }
-
- *numerator = rate_out / gcd_vl;
- *denominator = rate/ gcd_vl;
-
- CRU_PRINTK_DBG("frac_get_seting numerator=%d,denominator=%d,times=%d\n",
- *numerator, *denominator, *denominator / *numerator);
-
- if (*numerator > 0xffff || *denominator > 0xffff||
- (*denominator/(*numerator))<20) {
- CRU_PRINTK_ERR("can't get a available nume and deno\n");
- return -ENOENT;
- }
-
- return 0;
-
-}
-/* *********************pll **************************/
-
-#define rk30_clock_udelay(a) udelay(a);
-
-/*********************pll lock status**********************************/
-//#define GRF_SOC_CON0 0x15c
-static void pll_wait_lock(int pll_idx)
-{
- u32 pll_state[4]={1,0,2,3};
- u32 bit = 0x10u << pll_state[pll_idx];
- int delay = 24000000;
- while (delay > 0) {
- if (regfile_readl(GRF_SOC_STATUS0) & bit)
- break;
- delay--;
- }
- if (delay == 0) {
- CRU_PRINTK_ERR("PLL_ID=%d\npll_con0=%08x\npll_con1=%08x\npll_con2=%08x\npll_con3=%08x\n", pll_idx,
- cru_readl(PLL_CONS(pll_idx, 0)),
- cru_readl(PLL_CONS(pll_idx, 1)),
- cru_readl(PLL_CONS(pll_idx, 2)),
- cru_readl(PLL_CONS(pll_idx, 3)));
-
- CRU_PRINTK_ERR("wait pll bit 0x%x time out!\n", bit);
- while(1);
- }
-}
-
-
-
-/***************************pll function**********************************/
-static unsigned long pll_clk_recalc(u32 pll_id,unsigned long parent_rate)
-{
- unsigned long rate;
-
- if (PLLS_IN_NORM(pll_id)) {
- u32 pll_con0 = cru_readl(PLL_CONS(pll_id,0));
- u32 pll_con1 = cru_readl(PLL_CONS(pll_id,1));
-
-
- u64 rate64 = (u64)parent_rate*PLL_NF(pll_con1);
-
- /*
- CRU_PRINTK_DBG("selcon con0(%x) %x,con1(%x)%x, rate64 %llu\n",PLL_CONS(pll_id,0),pll_con0
- ,PLL_CONS(pll_id,1),pll_con1, rate64);
- */
-
-
- //CRU_PRINTK_DBG("pll id=%d con0=%x,con1=%x,parent=%lu\n",pll_id,pll_con0,pll_con1,parent_rate);
- //CRU_PRINTK_DBG("first pll id=%d rate is %lu (NF %d NR %d NO %d)\n",
- //pll_id, rate, PLL_NF(pll_con1), PLL_NR(pll_con0), 1 << PLL_NO(pll_con0));
-
- do_div(rate64, PLL_NR(pll_con0));
- do_div(rate64, PLL_NO(pll_con0));
-
- rate = rate64;
- /*
- CRU_PRINTK_DBG("pll_clk_recalc id=%d rate=%lu (NF %d NR %d NO %d) rate64=%llu\n",
- pll_id, rate, PLL_NF(pll_con1), PLL_NR(pll_con0),PLL_NO(pll_con0), rate64);
- */
- } else {
- rate = parent_rate;
- CRU_PRINTK_DBG("pll_clk_recalc id=%d rate=%lu by pass mode\n",pll_id,rate);
- }
- return rate;
-}
-static unsigned long plls_clk_recalc(struct clk *clk)
-{
- return pll_clk_recalc(clk->pll->id,clk->parent->rate);
-}
-
-static int pll_clk_set_rate(struct pll_clk_set *clk_set,u8 pll_id)
-{
- //enter slowmode
- cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
- //enter rest
- cru_writel(PLL_REST_W_MSK|PLL_REST, PLL_CONS(pll_id,3));
- cru_writel(clk_set->pllcon0, PLL_CONS(pll_id,0));
- cru_writel(clk_set->pllcon1, PLL_CONS(pll_id,1));
- cru_writel(clk_set->pllcon2, PLL_CONS(pll_id,2));
- rk30_clock_udelay(5);
-
- //return form rest
- cru_writel(PLL_REST_W_MSK|PLL_REST_RESM, PLL_CONS(pll_id,3));
-
- //wating lock state
- rk30_clock_udelay(clk_set->rst_dly);
- pll_wait_lock(pll_id);
-
- //return form slow
- cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
-
- /*
- CRU_PRINTK_ERR("pll reg id=%d,con0=%x,con1=%x,mode=%x\n",pll_id,
- cru_readl(PLL_CONS(pll_id,0)),(PLL_CONS(pll_id,1)),cru_readl(CRU_MODE_CON));
- */
-
-
- return 0;
-}
-static int gpll_clk_set_rate(struct clk *c, unsigned long rate)
-{
- struct _pll_data *pll_data=c->pll;
- struct pll_clk_set *clk_set=(struct pll_clk_set*)pll_data->table;
-
- while(clk_set->rate)
- {
- if (clk_set->rate == rate) {
- break;
- }
- clk_set++;
- }
- if(clk_set->rate== rate)
- {
- pll_clk_set_rate(clk_set,pll_data->id);
- lpj_gpll = CLK_LOOPS_RECALC(rate);
- }
- else
- {
- CRU_PRINTK_ERR("gpll is no corresponding rate=%lu\n", rate);
- return -1;
- }
- return 0;
-}
-
-#define PLL_FREF_MIN (183*KHZ)
-#define PLL_FREF_MAX (1500*MHZ)
-
-#define PLL_FVCO_MIN (300*MHZ)
-#define PLL_FVCO_MAX (1500*MHZ)
-
-#define PLL_FOUT_MIN (18750*KHZ)
-#define PLL_FOUT_MAX (1500*MHZ)
-
-#define PLL_NF_MAX (4096)
-#define PLL_NR_MAX (64)
-#define PLL_NO_MAX (16)
-
-static int pll_clk_get_set(unsigned long fin_hz,unsigned long fout_hz,u32 *clk_nr,u32 *clk_nf,u32 *clk_no)
-{
- u32 nr,nf,no,nonr;
- u32 n;
- u32 YFfenzi;
- u32 YFfenmu;
- unsigned long fref,fvco,fout;
- u32 gcd_val=0;
-
- CRU_PRINTK_DBG("pll_clk_get_set fin=%lu,fout=%lu\n",fin_hz,fout_hz);
- if(!fin_hz||!fout_hz||fout_hz==fin_hz)
- return 0;
- gcd_val=clk_gcd(fin_hz,fout_hz);
- YFfenzi=fout_hz/gcd_val;
- YFfenmu=fin_hz/gcd_val;
-
- for(n=1;;n++)
- {
- nf=YFfenzi*n;
- nonr=YFfenmu*n;
- if(nf>PLL_NF_MAX||nonr>(PLL_NO_MAX*PLL_NR_MAX))
- break;
- for(no=1;no<=PLL_NO_MAX;no++)
- {
- if(!(no==1||!(no%2)))
- continue;
-
- if(nonr%no)
- continue;
- nr=nonr/no;
-
- if(nr>PLL_NR_MAX)//PLL_NR_MAX
- continue;
-
- fref=fin_hz/nr;
- if(fref<PLL_FREF_MIN||fref>PLL_FREF_MAX)
- continue;
-
- fvco=(fin_hz/nr)*nf;
- if(fvco<PLL_FVCO_MIN||fvco>PLL_FVCO_MAX)
- continue;
- fout=fvco/no;
- if(fout<PLL_FOUT_MIN||fout>PLL_FOUT_MAX)
- continue;
- *clk_nr=nr;
- *clk_no=no;
- *clk_nf=nf;
- return 1;
-
- }
-
- }
- return 0;
-}
-
-static int pll_clk_mode(struct clk *clk, int on)
-{
- u8 pll_id=clk->pll->id;
- u32 nr=PLL_NR(cru_readl(PLL_CONS(pll_id,0)));
- u32 dly= (nr*500)/24+1;
- CRU_PRINTK_DBG("pll_mode %s(%d)",clk->name,on);
- if (on) {
- cru_writel(PLL_PWR_ON|PLL_PWR_DN_W_MSK,PLL_CONS(pll_id,3));
- rk30_clock_udelay(dly);
- pll_wait_lock(pll_id);
- cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
- } else {
- cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
- cru_writel(PLL_PWR_DN|PLL_PWR_DN_W_MSK, PLL_CONS(pll_id,3));
- }
- return 0;
-}
-
-static int cpll_clk_set_rate(struct clk *c, unsigned long rate)
-{
- struct _pll_data *pll_data=c->pll;
- struct pll_clk_set *clk_set=(struct pll_clk_set*)pll_data->table;
- struct pll_clk_set temp_clk_set;
- u32 clk_nr,clk_nf,clk_no;
-
-
- while(clk_set->rate)
- {
- if (clk_set->rate == rate) {
- break;
- }
- clk_set++;
- }
- if(clk_set->rate==rate)
- {
- CRU_PRINTK_DBG("cpll get a rate\n");
- pll_clk_set_rate(clk_set,pll_data->id);
-
- }
- else
- {
- CRU_PRINTK_DBG("cpll get auto calc a rate\n");
- if(pll_clk_get_set(c->parent->rate,rate,&clk_nr,&clk_nf,&clk_no)==0)
- {
- pr_err("cpll auto set rate error\n");
- return -ENOENT;
- }
- CRU_PRINTK_DBG("cpll auto ger rate set nr=%d,nf=%d,no=%d\n",clk_nr,clk_nf,clk_no);
- temp_clk_set.pllcon0=PLL_CLKR_SET(clk_nr)|PLL_CLKOD_SET(clk_no);
- temp_clk_set.pllcon1=PLL_CLKF_SET(clk_nf);
- temp_clk_set.pllcon2=PLL_CLK_BWADJ_SET(clk_nf/2-1);
- temp_clk_set.rst_dly=(clk_nr*500)/24+1;
- pll_clk_set_rate(&temp_clk_set,pll_data->id);
-
- }
- return 0;
-}
-
-
-/* ******************fixed input clk ***********************************************/
-static struct clk xin24m = {
- .name = "xin24m",
- .rate = 24 * MHZ,
- .flags = RATE_FIXED,
-};
-static struct clk xin27m = {
- .name = "xin27m",
- .rate = 27 * MHZ,
- //CLK_GATE_XIN27M
- .flags = RATE_FIXED,
-
-};
-static struct clk clk_12m = {
- .name = "clk_12m",
- .parent =&xin24m,
- .rate = 12 * MHZ,
- .flags = RATE_FIXED,
-};
-
-/************************************pll func***************************/
-static const struct apll_clk_set* arm_pll_clk_get_best_pll_set(unsigned long rate,
- struct apll_clk_set *tables)
-{
- const struct apll_clk_set *ps, *pt;
-
- /* find the arm_pll we want. */
- ps = pt = tables;
- while (pt->rate) {
- if (pt->rate == rate) {
- ps = pt;
- break;
- }
- // we are sorted, and ps->rate > pt->rate.
- if ((pt->rate > rate || (rate - pt->rate < ps->rate - rate)))
- ps = pt;
- if (pt->rate < rate)
- break;
- pt++;
- }
- //CRU_PRINTK_DBG("arm pll best rate=%lu\n",ps->rate);
- return ps;
-}
-static long arm_pll_clk_round_rate(struct clk *clk, unsigned long rate)
-{
- return arm_pll_clk_get_best_pll_set(rate,clk->pll->table)->rate;
-}
-#if 1
-struct arm_clks_div_set {
- u32 rate;
- u32 clksel0;
- u32 clksel1;
-};
-
-#define _arm_clks_div_set(_mhz,_periph_div,_axi_div,_ahb_div, _apb_div,_ahb2apb) \
- { \
- .rate =_mhz,\
- .clksel0 = CORE_PERIPH_W_MSK|CORE_PERIPH_##_periph_div,\
- .clksel1 = CORE_ACLK_W_MSK|CORE_ACLK_##_axi_div\
- |ACLK_HCLK_W_MSK|ACLK_HCLK_##_ahb_div\
- |ACLK_PCLK_W_MSK|ACLK_PCLK_##_apb_div\
- |AHB2APB_W_MSK |AHB2APB_##_ahb2apb,\
-}
-struct arm_clks_div_set arm_clk_div_tlb[]={
- _arm_clks_div_set(50 , 2, 11, 11, 11, 11),//25,50,50,50,50
- _arm_clks_div_set(100 , 4, 11, 21, 21, 11),//25,100,50,50,50
- _arm_clks_div_set(150 , 4, 11, 21, 21, 11),//37,150,75,75,75
- _arm_clks_div_set(200 , 8, 21, 21, 21, 11),//25,100,50,50,50
- _arm_clks_div_set(300 , 8, 21, 21, 21, 11),//37,150,75,75,75
- _arm_clks_div_set(400 , 8, 21, 21, 41, 21),//50,200,100,50,50
- _arm_clks_div_set(0 , 2, 11, 11, 11, 11),//25,50,50,50,50
-};
-struct arm_clks_div_set * arm_clks_get_div(u32 rate)
-{
- int i=0;
- for(i=0;arm_clk_div_tlb[i].rate!=0;i++)
- {
- if(arm_clk_div_tlb[i].rate>=rate)
- return &arm_clk_div_tlb[i];
- }
- return NULL;
-}
-
-#endif
-
-static u32 force_cpu_hpclk_11(u32 clksel1)
-{
- u8 p_bits=(clksel1&ACLK_PCLK_MSK)>>ACLK_PCLK_OFF;
- if(p_bits<3)
- {
- return ((clksel1&(~(ACLK_HCLK_MSK|AHB2APB_MSK)))|AHB2APB_11|(p_bits<<ACLK_HCLK_OFF));
- }
- else
- {
- return clksel1;
- }
-
-}
-static int arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
-{
- unsigned long flags;
- const struct apll_clk_set *ps;
- u32 pll_id=clk->pll->id;
- u32 temp_div;
- u32 old_aclk_div=0,new_aclk_div,gpll_arm_aclk_div;
- struct arm_clks_div_set *temp_clk_div;
- unsigned long arm_gpll_rate, arm_gpll_lpj;
- u32 ps_clksel1;
-
- ps = arm_pll_clk_get_best_pll_set(rate,(struct apll_clk_set *)clk->pll->table);
-
- old_aclk_div=GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
- new_aclk_div=GET_CORE_ACLK_VAL(ps->clksel1&CORE_ACLK_MSK);
-
- CRU_PRINTK_LOG("apll will set rate(%lu) tlb con(%x,%x,%x),sel(%x,%x)\n",
- ps->rate,ps->pllcon0,ps->pllcon1,ps->pllcon2,ps->clksel0,ps->clksel1);
-
- //rk30_l2_cache_latency(ps->rate/MHZ);
-
- if(general_pll_clk.rate>clk->rate)
- {
- temp_div=clk_get_freediv(clk->rate,general_pll_clk.rate,10);
- }
- else
- {
- temp_div=1;
- }
- //sel gpll
- //cru_writel(CORE_CLK_DIV(temp_div)|CORE_CLK_DIV_W_MSK, CRU_CLKSELS_CON(0));
-
- arm_gpll_rate=general_pll_clk.rate/temp_div;
- arm_gpll_lpj = lpj_gpll / temp_div;
- temp_clk_div=arm_clks_get_div(arm_gpll_rate/MHZ);
- if(!temp_clk_div)
- temp_clk_div=&arm_clk_div_tlb[4];
- if(rk30_clock_flags&CLK_CPU_HPCLK_11)
- {
- temp_clk_div->clksel1=force_cpu_hpclk_11(temp_clk_div->clksel1);
- }
-
- gpll_arm_aclk_div=GET_CORE_ACLK_VAL(temp_clk_div->clksel1&CORE_ACLK_MSK);
-
- CRU_PRINTK_LOG("gpll_arm_rate=%lu,sel rate%u,sel0%x,sel1%x\n",arm_gpll_rate,temp_clk_div->rate,
- temp_clk_div->clksel0,temp_clk_div->clksel1);
-
- local_irq_save(flags);
- //new div max first
- if(gpll_arm_aclk_div>=old_aclk_div)
- {
- if((old_aclk_div==3||gpll_arm_aclk_div==3)&&(gpll_arm_aclk_div!=old_aclk_div))
- {
- cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
- cru_writel((temp_clk_div->clksel1), CRU_CLKSELS_CON(1));
- cru_writel((temp_clk_div->clksel0|CORE_CLK_DIV(temp_div)|CORE_CLK_DIV_W_MSK),
- CRU_CLKSELS_CON(0));
- cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
- }
- else
- {
- cru_writel((temp_clk_div->clksel1), CRU_CLKSELS_CON(1));
- cru_writel((temp_clk_div->clksel0)|CORE_CLK_DIV(temp_div)|CORE_CLK_DIV_W_MSK,
- CRU_CLKSELS_CON(0));
- }
- }
- // open gpu gpll path
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH)|CLK_UN_GATE(CLK_GATE_CPU_GPLL_PATH),CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
- cru_writel(CORE_SEL_GPLL|CORE_SEL_PLL_W_MSK, CRU_CLKSELS_CON(0));
- loops_per_jiffy = arm_gpll_lpj;
- smp_wmb();
- //new div max late
- if(gpll_arm_aclk_div<old_aclk_div)
- {
- if((old_aclk_div==3||gpll_arm_aclk_div==3)&&(gpll_arm_aclk_div!=old_aclk_div))
- {
- cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
- cru_writel((temp_clk_div->clksel1), CRU_CLKSELS_CON(1));
- cru_writel((temp_clk_div->clksel0|CORE_CLK_DIV(temp_div)|CORE_CLK_DIV_W_MSK),
- CRU_CLKSELS_CON(0));
- cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
- }
- else
- {
- cru_writel((temp_clk_div->clksel1), CRU_CLKSELS_CON(1));
- cru_writel((temp_clk_div->clksel0)|CORE_CLK_DIV(temp_div)|CORE_CLK_DIV_W_MSK,
- CRU_CLKSELS_CON(0));
- }
- }
-
- /*if core src don't select gpll ,apll neet to enter slow mode */
- //cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
-
- //enter rest
- cru_writel(PLL_REST_W_MSK|PLL_REST, PLL_CONS(pll_id,3));
- cru_writel(ps->pllcon0, PLL_CONS(pll_id,0));
- cru_writel(ps->pllcon1, PLL_CONS(pll_id,1));
- cru_writel(ps->pllcon2, PLL_CONS(pll_id,2));
-
- rk30_clock_udelay(5);
-
- //return form rest
- cru_writel(PLL_REST_W_MSK|PLL_REST_RESM, PLL_CONS(pll_id,3));
-
- //wating lock state
- ///rk30_clock_udelay(ps->rst_dly);//lcdc flash
-
- pll_wait_lock(pll_id);
-
- if(rk30_clock_flags&CLK_CPU_HPCLK_11)
- {
- ps_clksel1=force_cpu_hpclk_11(ps->clksel1);
- }
- else
- {
- ps_clksel1=ps->clksel1;
- }
- //return form slow
- //cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
- //a/h/p clk sel
- if(new_aclk_div>=gpll_arm_aclk_div)
- {
- if((gpll_arm_aclk_div==3||new_aclk_div==3)&&(new_aclk_div!=gpll_arm_aclk_div))
- {
- cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
- cru_writel((ps_clksel1), CRU_CLKSELS_CON(1));
- cru_writel((ps->clksel0)|CORE_CLK_DIV(1)|CORE_CLK_DIV_W_MSK, CRU_CLKSELS_CON(0));
- cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
- }
- else
- {
- cru_writel((ps_clksel1), CRU_CLKSELS_CON(1));
- cru_writel((ps->clksel0)|CORE_CLK_DIV(1)|CORE_CLK_DIV_W_MSK, CRU_CLKSELS_CON(0));
- }
- }
-
- //reparent to apll
- cru_writel(CORE_SEL_PLL_W_MSK|CORE_SEL_APLL, CRU_CLKSELS_CON(0));
- loops_per_jiffy = ps->lpj;
- smp_wmb();
-
- if(new_aclk_div<gpll_arm_aclk_div)
- {
- if((gpll_arm_aclk_div==3||new_aclk_div==3)&&(new_aclk_div!=gpll_arm_aclk_div))
- {
- cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
- cru_writel((ps_clksel1), CRU_CLKSELS_CON(1));
- cru_writel((ps->clksel0)|CORE_CLK_DIV(1)|CORE_CLK_DIV_W_MSK, CRU_CLKSELS_CON(0));
- cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
- }
- else
- {
- cru_writel((ps_clksel1), CRU_CLKSELS_CON(1));
- cru_writel((ps->clksel0)|CORE_CLK_DIV(1)|CORE_CLK_DIV_W_MSK, CRU_CLKSELS_CON(0));
- }
- }
- //CRU_PRINTK_DBG("apll set loops_per_jiffy =%lu,rate(%lu)\n",loops_per_jiffy,ps->rate);
-
- local_irq_restore(flags);
-
- //gate gpll path
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH)|CLK_GATE(CLK_GATE_CPU_GPLL_PATH)
- , CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
-
- CRU_PRINTK_LOG("apll set over con(%x,%x,%x,%x),sel(%x,%x)\n",cru_readl(PLL_CONS(pll_id,0)),
- cru_readl(PLL_CONS(pll_id,1)),cru_readl(PLL_CONS(pll_id,2)),
- cru_readl(PLL_CONS(pll_id,3)),cru_readl(CRU_CLKSELS_CON(0)),
- cru_readl(CRU_CLKSELS_CON(1)));
- return 0;
-}
-
-
-/************************************pll clocks***************************/
-
-static const struct apll_clk_set apll_clks[] = {
- //rate, nr ,nf ,no,core_div,peri,axi,hclk,pclk,_ahb2apb
- //_APLL_SET_CLKS(1800, 1, 75, 1, 8, 41, 41, 81,21),
- //_APLL_SET_CLKS(1752, 1, 73, 1, 8, 41, 41, 81,21),
- //_APLL_SET_CLKS(1704, 1, 71, 1, 8, 41, 41, 81,21),
- //_APLL_SET_CLKS(1656, 1, 69, 1, 8, 41, 41, 81,21),
- _APLL_SET_CLKS(1608, 1, 67, 1, 8, 41, 21, 41, 21),
- _APLL_SET_CLKS(1560, 1, 65, 1, 8, 41, 21, 41, 21),
- _APLL_SET_CLKS(1512, 1, 63, 1, 8, 41, 21, 41, 21),
- _APLL_SET_CLKS(1464, 1, 61, 1, 8, 41, 21, 41, 21),
- _APLL_SET_CLKS(1416, 1, 59, 1, 8, 41, 21, 41, 21),
- _APLL_SET_CLKS(1368, 1, 57, 1, 8, 41, 21, 41, 21),
- _APLL_SET_CLKS(1320, 1, 55, 1, 8, 41, 21, 41, 21),
- _APLL_SET_CLKS(1296, 1, 54, 1, 8, 41, 21, 41, 21),
- _APLL_SET_CLKS(1272, 1, 53, 1, 8, 41, 21, 41, 21),
- _APLL_SET_CLKS(1200, 1, 50, 1, 8, 41, 21, 41, 21),
- _APLL_SET_CLKS(1176, 1, 49, 1, 8, 41, 21, 41, 21),
- _APLL_SET_CLKS(1128, 1, 47, 1, 8, 41, 21, 41, 21),
- _APLL_SET_CLKS(1104, 1, 46, 1, 8, 41, 21, 41, 21),
- _APLL_SET_CLKS(1008, 1, 42, 1, 8, 31, 21, 41, 21),
- _APLL_SET_CLKS(888, 1, 37, 1, 8, 31, 21, 41, 21),
- _APLL_SET_CLKS(816 , 1, 34, 1, 8, 31, 21, 41, 21),
- _APLL_SET_CLKS(792 , 1, 33, 1, 8, 31, 21, 41, 21),
- _APLL_SET_CLKS(696 , 1, 29, 1, 8, 31, 21, 41, 21),
- _APLL_SET_CLKS(600 , 1, 25, 1, 4, 31, 21, 41, 21),
- _APLL_SET_CLKS(504 , 1, 21, 1, 4, 21, 21, 41, 21),
- _APLL_SET_CLKS(408 , 1, 17, 1, 4, 21, 21, 41, 21),
- _APLL_SET_CLKS(312 , 1, 13, 1, 2, 21, 21, 21, 11),
- _APLL_SET_CLKS(252 , 1, 21, 2, 2, 21, 21, 21, 11),
- _APLL_SET_CLKS(216 , 1, 18, 2, 2, 21, 21, 21, 11),
- _APLL_SET_CLKS(126 , 1, 21, 4, 2, 21, 11, 11, 11),
- _APLL_SET_CLKS(48 , 1, 16, 8, 2, 11, 11, 11, 11),
- _APLL_SET_CLKS(0 , 1, 21, 4, 2, 21, 21, 41, 21),
-
-};
-static struct _pll_data apll_data=SET_PLL_DATA(APLL_ID,(void *)apll_clks);
-static struct clk arm_pll_clk ={
- .name = "arm_pll",
- .parent = &xin24m,
- .mode = pll_clk_mode,
- .recalc = plls_clk_recalc,
- .set_rate = arm_pll_clk_set_rate,
- .round_rate = arm_pll_clk_round_rate,
- .pll=&apll_data,
- };
-
-static int ddr_pll_clk_set_rate(struct clk *clk, unsigned long rate)
-{
- /* do nothing here */
- return 0;
-}
-static struct _pll_data dpll_data=SET_PLL_DATA(DPLL_ID,NULL);
-static struct clk ddr_pll_clk = {
- .name = "ddr_pll",
- .parent = &xin24m,
- .recalc = plls_clk_recalc,
- .set_rate = ddr_pll_clk_set_rate,
- .pll=&dpll_data,
-};
-
-static const struct pll_clk_set cpll_clks[] = {
- _PLL_SET_CLKS(360000, 1, 15, 1),
- _PLL_SET_CLKS(408000, 1, 17, 1),
- _PLL_SET_CLKS(456000, 1, 19, 1),
- _PLL_SET_CLKS(504000, 1, 21, 1),
- _PLL_SET_CLKS(552000, 1, 23, 1),
- _PLL_SET_CLKS(600000, 1, 25, 1),
- _PLL_SET_CLKS(742500, 8, 495, 2),
- _PLL_SET_CLKS(768000, 1, 32, 1),
- _PLL_SET_CLKS(798000, 4, 133, 1),
- _PLL_SET_CLKS(1188000,2, 99, 1),
- _PLL_SET_CLKS( 0, 4, 133, 1),
-};
-static struct _pll_data cpll_data=SET_PLL_DATA(CPLL_ID,(void *)cpll_clks);
-static struct clk codec_pll_clk = {
- .name = "codec_pll",
- .parent = &xin24m,
- .mode = pll_clk_mode,
- .recalc = plls_clk_recalc,
- .set_rate = cpll_clk_set_rate,
- .pll= &cpll_data,
-};
-
-static const struct pll_clk_set gpll_clks[] = {
- _PLL_SET_CLKS(148500, 4, 99, 4),
- _PLL_SET_CLKS(297000, 2, 99, 4),
- _PLL_SET_CLKS(300000, 1, 25, 2),
- _PLL_SET_CLKS(1188000, 2, 99, 1),
- _PLL_SET_CLKS(0, 0, 0, 0),
-};
-static struct _pll_data gpll_data=SET_PLL_DATA(GPLL_ID,(void *)gpll_clks);
-static struct clk general_pll_clk = {
- .name = "general_pll",
- .parent = &xin24m,
- .recalc = plls_clk_recalc,
- .set_rate = gpll_clk_set_rate,
- .pll= &gpll_data
-};
-/********************************clocks***********************************/
-static int ddr_clk_set_rate(struct clk *c, unsigned long rate)
-{
- return 0;
-}
-
-static long ddr_clk_round_rate(struct clk *clk, unsigned long rate)
-{
- return ddr_set_pll(rate/MHZ,0)*MHZ;
-}
-static unsigned long ddr_clk_recalc_rate(struct clk *clk)
-{
- u32 shift = get_cru_bits(clk->clksel_con,clk->div_mask,clk->div_shift);
- unsigned long rate = clk->parent->recalc(clk->parent)>> shift;
- pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
- return rate;
-}
-static struct clk *clk_ddr_parents[2] = {&ddr_pll_clk, &general_pll_clk};
-static struct clk clk_ddr = {
- .name = "ddr",
- .parent = &ddr_pll_clk,
- .recalc = ddr_clk_recalc_rate,
- .set_rate = ddr_clk_set_rate,
- .round_rate = ddr_clk_round_rate,
- .clksel_con = CRU_CLKSELS_CON(26),
- //CRU_DIV_SET(0x3,0,4),
- //CRU_SRC_SET(1,8),
- //CRU_PARENTS_SET(clk_ddr_parents),
-};
-static int arm_core_clk_set_rate(struct clk *c, unsigned long rate)
-{
- int ret;
- //set arm pll div 1
- //set_cru_bits_w_msk(0,c->div_mask,c->div_shift,c->clksel_con);
-
- ret = clk_set_rate_nolock(c->parent, rate);
- if (ret) {
- CRU_PRINTK_ERR("Failed to change clk pll %s to %lu\n",c->name,rate);
- return ret;
- }
- return 0;
-}
-static unsigned long arm_core_clk_get_rate(struct clk *c)
-{
- u32 div=(get_cru_bits(c->clksel_con,c->div_mask,c->div_shift)+1);
- //c->parent->rate=c->parent->recalc(c->parent);
- return c->parent->rate/div;
-}
-static long core_clk_round_rate(struct clk *clk, unsigned long rate)
-{
- u32 div=(get_cru_bits(clk->clksel_con,clk->div_mask,clk->div_shift)+1);
- return clk_round_rate_nolock(clk->parent,rate)/div;
-}
-
-static int core_clksel_set_parent(struct clk *clk, struct clk *new_prt)
-{
-
- u32 temp_div;
- struct clk *old_prt;
-
- if(clk->parent==new_prt)
- return 0;
- if (unlikely(!clk->parents))
- return -EINVAL;
- CRU_PRINTK_DBG("%s,reparent %s\n",clk->name,new_prt->name);
- //arm
- old_prt=clk->parent;
-
- if(clk->parents[0]==new_prt)
- {
- new_prt->set_rate(new_prt,300*MHZ);
- set_cru_bits_w_msk(0,clk->div_mask,clk->div_shift,clk->clksel_con);
- }
- else if(clk->parents[1]==new_prt)
- {
-
- if(new_prt->rate>old_prt->rate)
- {
- temp_div=clk_get_freediv(old_prt->rate,new_prt->rate,clk->div_max);
- set_cru_bits_w_msk(temp_div-1,clk->div_mask,clk->div_shift,clk->clksel_con);
- }
- set_cru_bits_w_msk(1,clk->src_mask,clk->src_shift,clk->clksel_con);
- new_prt->set_rate(new_prt,300*MHZ);
- }
- else
- return -1;
-
-
- return 0;
-
-}
-
-static int core_gpll_clk_set_rate(struct clk *c, unsigned long rate)
-{
- //unsigned long flags;
- //u32 pll_id=APLL_ID;
- u32 temp_div;
- u32 old_aclk_div=0,new_aclk_div;
- struct arm_clks_div_set *temp_clk_div;
- unsigned long arm_gpll_rate, arm_gpll_lpj;
- temp_div=clk_get_freediv(rate,c->parent->rate,c->div_max);
- arm_gpll_rate=c->parent->rate/temp_div;
-
- temp_clk_div=arm_clks_get_div(arm_gpll_rate/MHZ);
- if(!temp_clk_div)
- temp_clk_div=&arm_clk_div_tlb[4];
-
- old_aclk_div=GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
- new_aclk_div=GET_CORE_ACLK_VAL(temp_clk_div->clksel1&CORE_ACLK_MSK);
- if(c->rate>=rate)
- {
- arm_gpll_lpj = lpj_gpll / temp_div;
- set_cru_bits_w_msk(temp_div-1,c->div_mask,c->div_shift,c->clksel_con);
- }
-
- cru_writel((temp_clk_div->clksel1), CRU_CLKSELS_CON(1));
- cru_writel((temp_clk_div->clksel0)|CORE_CLK_DIV(temp_div)|CORE_CLK_DIV_W_MSK,
- CRU_CLKSELS_CON(0));
- if((c->rate<rate))
- {
- arm_gpll_lpj = lpj_gpll / temp_div;
- set_cru_bits_w_msk(temp_div-1,c->div_mask,c->div_shift,c->clksel_con);
- }
- return 0;
-}
-static unsigned long arm_core_gpll_clk_get_rate(struct clk *c)
-{
- return c->parent->rate;
-}
-
-static struct clk clk_cpu_gpll_path = {
- .name = "cpu_gpll_path",
- .parent = &general_pll_clk,
- .recalc = arm_core_gpll_clk_get_rate,
- .set_rate = core_gpll_clk_set_rate,
- CRU_DIV_SET(0x1f,0,32),
- CRU_GATE_MODE_SET(gate_mode,CLK_GATE_CPU_GPLL_PATH),
-};
-
-
-static struct clk *clk_cpu_parents[2] = {&arm_pll_clk,&clk_cpu_gpll_path};
-
-static struct clk clk_cpu = {
- .name = "cpu",
- .parent = &arm_pll_clk,
- .set_rate = arm_core_clk_set_rate,
- .recalc = arm_core_clk_get_rate,
- .round_rate = core_clk_round_rate,
- .set_parent = core_clksel_set_parent,
- .clksel_con = CRU_CLKSELS_CON(0),
- CRU_DIV_SET(0x1f,0,32),
- CRU_SRC_SET(1,8),
- CRU_PARENTS_SET(clk_cpu_parents),
-};
-static unsigned long aclk_cpu_recalc(struct clk *clk)
-{
- unsigned long rate;
- u32 div = get_cru_bits(clk->clksel_con,clk->div_mask,clk->div_shift)+1;
-
- BUG_ON(div > 5);
- if (div >= 5)
- div = 8;
- rate = clk->parent->rate / div;
- pr_debug("%s new clock rate is %ld (div %d)\n", clk->name, rate, div);
-
- return rate;
-};
-static struct clk core_periph = {
- .name = "core_periph",
- .parent = &clk_cpu,
- .recalc = clksel_recalc_shift_2,
- .clksel_con = CRU_CLKSELS_CON(0),
- CRU_DIV_SET(0x3,6,16),
-};
-
-static struct clk aclk_cpu = {
- .name = "aclk_cpu",
- .parent = &clk_cpu,
- .recalc = aclk_cpu_recalc,
- .clksel_con = CRU_CLKSELS_CON(1),
- CRU_DIV_SET(0x7,0,8),
-};
-
-static struct clk hclk_cpu = {
- .name = "hclk_cpu",
- .parent = &aclk_cpu,
- .recalc = clksel_recalc_shift,
- //.set_rate = clksel_set_rate_shift,
- .clksel_con = CRU_CLKSELS_CON(1),
- CRU_DIV_SET(0x3,8,4),
-
-};
-
-static struct clk pclk_cpu = {
- .name = "pclk_cpu",
- .parent = &aclk_cpu,
- .recalc = clksel_recalc_shift,
- //.set_rate = clksel_set_rate_shift,
- .clksel_con = CRU_CLKSELS_CON(1),
- CRU_DIV_SET(0x3,12,8),
-};
-static struct clk ahb2apb_cpu = {
- .name = "ahb2apb",
- .parent = &hclk_cpu,
- .recalc = clksel_recalc_shift,
- .clksel_con = CRU_CLKSELS_CON(1),
- CRU_DIV_SET(0x3,14,4),
-};
-
-
-static struct clk atclk_cpu = {
- .name = "atclk_cpu",
- .parent = &pclk_cpu,
-};
-
-static struct clk *clk_i2s_div_parents[]={&general_pll_clk,&codec_pll_clk};
-static struct clk clk_i2s_pll = {
- .name = "i2s_pll",
- .parent = &general_pll_clk,
- .clksel_con = CRU_CLKSELS_CON(2),
- CRU_SRC_SET(0x1, 15),
- CRU_PARENTS_SET(clk_i2s_div_parents),
-};
-
-static struct clk clk_i2s0_div = {
- .name = "i2s0_div",
- .parent = &clk_i2s_pll,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .round_rate =clksel_freediv_round_rate,
- .gate_idx = CLK_GATE_I2S0,
- .clksel_con = CRU_CLKSELS_CON(2),
- CRU_DIV_SET(0x7f,0,64),
-};
-
-static struct clk clk_i2s1_div = {
- .name = "i2s1_div",
- .parent = &clk_i2s_pll,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .round_rate =clksel_freediv_round_rate,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_I2S1,
- .clksel_con = CRU_CLKSELS_CON(3),
- CRU_DIV_SET(0x7f,0,64),
-};
-
-
-static struct clk clk_i2s2_div = {
- .name = "i2s2_div",
- .parent = &clk_i2s_pll,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .round_rate =clksel_freediv_round_rate,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_I2S2,
- .clksel_con = CRU_CLKSELS_CON(4),
- CRU_DIV_SET(0x7f,0,64),
-};
-static struct clk clk_spdif_div = {
- .name = "spdif_div",
- .parent = &clk_i2s_pll,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .round_rate =clksel_freediv_round_rate,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_SPDIF,
- .clksel_con = CRU_CLKSELS_CON(5),
- CRU_DIV_SET(0x7f,0,64),
-};
-static int clk_i2s_fracdiv_set_rate(struct clk *clk, unsigned long rate)
-{
- u32 numerator, denominator;
- int i = 10;
- //clk_i2s_div->clk_i2s_pll->gpll/cpll
- //clk->parent->parent
- if(frac_div_get_seting(rate,clk->parent->parent->rate,
- &numerator,&denominator)==0)
- {
- clk_set_rate_nolock(clk->parent,clk->parent->parent->rate);//PLL:DIV 1:
-
- while (i--) {
- cru_writel_frac((numerator - 1) << 16 | denominator, clk->clksel_con);
- mdelay(1);
- cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
- mdelay(1);
- }
- CRU_PRINTK_DBG("%s set rate=%lu,is ok\n",clk->name,rate);
- }
- else
- {
- CRU_PRINTK_ERR("clk_frac_div can't get rate=%lu,%s\n",rate,clk->name);
- return -ENOENT;
- }
- return 0;
-}
-
-
-static struct clk clk_i2s0_frac_div = {
- .name = "i2s0_frac_div",
- .parent = &clk_i2s0_div,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_I2S0_FRAC,
- .recalc = clksel_recalc_frac,
- .set_rate = clk_i2s_fracdiv_set_rate,
- .clksel_con = CRU_CLKSELS_CON(6),
-};
-
-static struct clk clk_i2s1_frac_div = {
- .name = "i2s1_frac_div",
- .parent = &clk_i2s1_div,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_I2S1_FRAC,
- .recalc = clksel_recalc_frac,
- .set_rate = clk_i2s_fracdiv_set_rate,
- .clksel_con = CRU_CLKSELS_CON(7),
-};
-
-static struct clk clk_i2s2_frac_div = {
- .name = "i2s2_frac_div",
- .mode = gate_mode,
- .gate_idx = CLK_GATE_I2S2_FRAC,
- .parent = &clk_i2s2_div,
- .recalc = clksel_recalc_frac,
- .set_rate = clk_i2s_fracdiv_set_rate,
- .clksel_con = CRU_CLKSELS_CON(8),
-};
-static struct clk clk_spdif_frac_div = {
- .name = "spdif_frac_div",
- .parent = &clk_spdif_div,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_SPDIF_FRAC,
- .recalc = clksel_recalc_frac,
- .set_rate = clk_i2s_fracdiv_set_rate,
- .clksel_con = CRU_CLKSELS_CON(9),
-};
-
-#define I2S_SRC_DIV (0x0)
-#define I2S_SRC_FRAC (0x1)
-#define I2S_SRC_12M (0x2)
-
-static int i2s_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret = -EINVAL;
- struct clk *parent;
-
- if (rate == clk->parents[I2S_SRC_12M]->rate){
- parent = clk->parents[I2S_SRC_12M];
- }else if((long)clk_round_rate_nolock(clk->parents[I2S_SRC_DIV],rate)==rate)
- {
- parent = clk->parents[I2S_SRC_DIV];
- }
- else
- {
- parent =clk->parents[I2S_SRC_FRAC];
- }
-
- CRU_PRINTK_DBG(" %s set rate=%lu parent %s(old %s)\n",
- clk->name,rate,parent->name,clk->parent->name);
-
- if(parent!=clk->parents[I2S_SRC_12M])
- {
- ret = clk_set_rate_nolock(parent,rate);//div 1:1
- if (ret)
- {
- CRU_PRINTK_DBG("%s set rate%lu err\n",clk->name,rate);
- return ret;
- }
- }
-
- if (clk->parent != parent)
- {
- ret = clk_set_parent_nolock(clk, parent);
- if (ret)
- {
- CRU_PRINTK_DBG("%s can't get rate%lu,reparent err\n",clk->name,rate);
- return ret;
- }
- }
-
- return ret;
-};
-
-static struct clk *clk_i2s0_parents[3]={&clk_i2s0_div,&clk_i2s0_frac_div,&clk_12m};
-
-static struct clk clk_i2s0 = {
- .name = "i2s0",
- .set_rate = i2s_set_rate,
- .clksel_con = CRU_CLKSELS_CON(2),
- CRU_SRC_SET(0x3,8),
- CRU_PARENTS_SET(clk_i2s0_parents),
-};
-
-static struct clk *clk_i2s1_parents[3]={&clk_i2s1_div,&clk_i2s1_frac_div,&clk_12m};
-
-static struct clk clk_i2s1 = {
- .name = "i2s1",
- .set_rate = i2s_set_rate,
- .clksel_con = CRU_CLKSELS_CON(3),
- CRU_SRC_SET(0x3,8),
- CRU_PARENTS_SET(clk_i2s1_parents),
-};
-
-static struct clk *clk_i2s2_parents[3]={&clk_i2s2_div,&clk_i2s2_frac_div,&clk_12m};
-
-static struct clk clk_i2s2 = {
- .name = "i2s2",
- .set_rate = i2s_set_rate,
- .clksel_con = CRU_CLKSELS_CON(4),
- CRU_SRC_SET(0x3,8),
- CRU_PARENTS_SET(clk_i2s2_parents),
-};
-
-static struct clk *clk_spdif_parents[3]={&clk_spdif_div,&clk_spdif_frac_div,&clk_12m};
-
-static struct clk clk_spdif = {
- .name = "spdif",
- .parent = &clk_spdif_frac_div,
- .set_rate = i2s_set_rate,
- .clksel_con = CRU_CLKSELS_CON(5),
- CRU_SRC_SET(0x3,8),
- CRU_PARENTS_SET(clk_spdif_parents),
-};
-
-static struct clk *aclk_periph_parents[2]={&general_pll_clk,&codec_pll_clk};
-
-static struct clk aclk_periph = {
- .name = "aclk_periph",
- .parent = &general_pll_clk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_ACLK_PERIPH,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(10),
- CRU_DIV_SET(0x1f,0,32),
- CRU_SRC_SET(1,15),
- CRU_PARENTS_SET(aclk_periph_parents),
-};
-GATE_CLK(periph_src, aclk_periph, PERIPH_SRC);
-
-static struct clk pclk_periph = {
- .name = "pclk_periph",
- .parent = &aclk_periph,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_PCLK_PERIPH,
- .recalc = clksel_recalc_shift,
- .set_rate = clksel_set_rate_shift,
- .clksel_con = CRU_CLKSELS_CON(10),
- CRU_DIV_SET(0x3,12,8),
-};
-
-static struct clk hclk_periph = {
- .name = "hclk_periph",
- .parent = &aclk_periph,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_HCLK_PERIPH,
- .recalc = clksel_recalc_shift,
- .set_rate = clksel_set_rate_shift,
- .clksel_con = CRU_CLKSELS_CON(10),
- CRU_DIV_SET(0x3,8,4),
-};
-
-static struct clk clk_spi0 = {
- .name = "spi0",
- .parent = &pclk_periph,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .gate_idx = CLK_GATE_SPI0,
- .clksel_con = CRU_CLKSELS_CON(25),
- CRU_DIV_SET(0x7f,0,128),
-};
-
-static struct clk clk_spi1 = {
- .name = "spi1",
- .parent = &pclk_periph,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .gate_idx = CLK_GATE_SPI1,
- .clksel_con = CRU_CLKSELS_CON(25),
- CRU_DIV_SET(0x7f,8,128),
-};
-
-static struct clk clk_saradc = {
- .name = "saradc",
- .parent = &xin24m,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .gate_idx = CLK_GATE_SARADC,
- .clksel_con =CRU_CLKSELS_CON(24),
- CRU_DIV_SET(0xff,8,256),
-};
-static struct clk clk_tsadc = {
- .name = "tsadc",
- .parent = &xin24m,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .gate_idx = CLK_GATE_TSADC,
- .clksel_con =CRU_CLKSELS_CON(34),
- CRU_DIV_SET(0xffff,0,65536),
-};
-GATE_CLK(otgphy0, xin24m, OTGPHY0);
-GATE_CLK(otgphy1, xin24m, OTGPHY1);
-
-
-GATE_CLK(smc, pclk_periph, SMC);//smc
-
-static struct clk clk_sdmmc = {
- .name = "sdmmc",
- .parent = &hclk_periph,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_even,
- .gate_idx = CLK_GATE_MMC0,
- .clksel_con =CRU_CLKSELS_CON(11),
- CRU_DIV_SET(0x3f,0,64),
-};
-
-static struct clk clk_sdio = {
- .name = "sdio",
- .parent = &hclk_periph,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_even,
- .gate_idx = CLK_GATE_SDIO,
- .clksel_con =CRU_CLKSELS_CON(12),
- CRU_DIV_SET(0x3f,0,64),
-
-};
-
-static struct clk clk_emmc = {
- .name = "emmc",
- .parent = &hclk_periph,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_even,
- .gate_idx = CLK_GATE_EMMC,
- .clksel_con =CRU_CLKSELS_CON(12),
- CRU_DIV_SET(0x3f,8,64),
-};
-
-static struct clk *clk_uart_src_parents[2]={&general_pll_clk,&codec_pll_clk};
-static struct clk clk_uart_pll = {
- .name = "uart_pll",
- .parent = &general_pll_clk,
- .clksel_con =CRU_CLKSELS_CON(12),
- CRU_SRC_SET(0x1,15),
- CRU_PARENTS_SET(clk_uart_src_parents),
-};
-static struct clk clk_uart0_div = {
- .name = "uart0_div",
- .parent = &clk_uart_pll,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_UART0,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .round_rate =clksel_freediv_round_rate,
- .clksel_con = CRU_CLKSELS_CON(13),
- CRU_DIV_SET(0x7f,0,64),
-};
-static struct clk clk_uart1_div = {
- .name = "uart1_div",
- .parent = &clk_uart_pll,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_UART1,
- .recalc = clksel_recalc_div,
- .round_rate =clksel_freediv_round_rate,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(14),
- CRU_DIV_SET(0x7f,0,64),
-};
-
-static struct clk clk_uart2_div = {
- .name = "uart2_div",
- .parent = &clk_uart_pll,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_UART2,
- .recalc = clksel_recalc_div,
- .round_rate =clksel_freediv_round_rate,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(15),
- CRU_DIV_SET(0x7f,0,64),
-};
-
-static struct clk clk_uart3_div = {
- .name = "uart3_div",
- .parent = &clk_uart_pll,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_UART3,
- .recalc = clksel_recalc_div,
- .round_rate =clksel_freediv_round_rate,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(16),
- CRU_DIV_SET(0x7f,0,64),
-};
-static int clk_uart_fracdiv_set_rate(struct clk *clk, unsigned long rate)
-{
- u32 numerator, denominator;
- //clk_uart0_div->clk_uart_pll->gpll/cpll
- //clk->parent->parent
- if(frac_div_get_seting(rate,clk->parent->parent->rate,
- &numerator,&denominator)==0)
- {
- clk_set_rate_nolock(clk->parent,clk->parent->parent->rate);//PLL:DIV 1:
-
- cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
-
- CRU_PRINTK_DBG("%s set rate=%lu,is ok\n",clk->name,rate);
- }
- else
- {
- CRU_PRINTK_ERR("clk_frac_div can't get rate=%lu,%s\n",rate,clk->name);
- return -ENOENT;
- }
- return 0;
-}
-
-static struct clk clk_uart0_frac_div = {
- .name = "uart0_frac_div",
- .parent = &clk_uart0_div,
- .mode = gate_mode,
- .recalc = clksel_recalc_frac,
- .set_rate = clk_uart_fracdiv_set_rate,
- .gate_idx = CLK_GATE_FRAC_UART0,
- .clksel_con = CRU_CLKSELS_CON(17),
-};
-static struct clk clk_uart1_frac_div = {
- .name = "uart1_frac_div",
- .parent = &clk_uart1_div,
- .mode = gate_mode,
- .recalc = clksel_recalc_frac,
- .set_rate = clk_uart_fracdiv_set_rate,
- .gate_idx = CLK_GATE_FRAC_UART1,
- .clksel_con = CRU_CLKSELS_CON(18),
-};
-static struct clk clk_uart2_frac_div = {
- .name = "uart2_frac_div",
- .mode = gate_mode,
- .parent = &clk_uart2_div,
- .recalc = clksel_recalc_frac,
- .set_rate = clk_uart_fracdiv_set_rate,
- .gate_idx = CLK_GATE_FRAC_UART2,
- .clksel_con = CRU_CLKSELS_CON(19),
-};
-static struct clk clk_uart3_frac_div = {
- .name = "uart3_frac_div",
- .parent = &clk_uart3_div,
- .mode = gate_mode,
- .recalc = clksel_recalc_frac,
- .set_rate = clk_uart_fracdiv_set_rate,
- .gate_idx = CLK_GATE_FRAC_UART3,
- .clksel_con = CRU_CLKSELS_CON(20),
-};
-
-
-#define UART_SRC_DIV 0
-#define UART_SRC_FRAC 1
-#define UART_SRC_24M 2
-
-static int clk_uart_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret = 0;
- struct clk *parent;
-
- if(rate==clk->parents[UART_SRC_24M]->rate)//24m
- {
- parent = clk->parents[UART_SRC_24M];
- }
- else if((long)clk_round_rate_nolock(clk->parents[UART_SRC_DIV], rate)==rate)
- {
- parent = clk->parents[UART_SRC_DIV];
- }
- else
- {
- parent = clk->parents[UART_SRC_FRAC];
- }
-
- CRU_PRINTK_DBG(" %s set rate=%lu parent %s(old %s)\n",
- clk->name,rate,parent->name,clk->parent->name);
-
-
- if(parent!=clk->parents[UART_SRC_24M])
- {
- ret = clk_set_rate_nolock(parent,rate);
- if (ret)
- {
- CRU_PRINTK_DBG("%s set rate%lu err\n",clk->name,rate);
- return ret;
- }
- }
-
- if (clk->parent != parent)
- {
- ret = clk_set_parent_nolock(clk, parent);
- if (ret)
- {
- CRU_PRINTK_DBG("%s can't get rate%lu,reparent err\n",clk->name,rate);
- return ret;
- }
- }
-
-
- return ret;
-}
-
-
-static struct clk *clk_uart0_parents[3]={&clk_uart0_div,&clk_uart0_frac_div,&xin24m};
-static struct clk clk_uart0 = {
- .name = "uart0",
- .set_rate = clk_uart_set_rate,
- .clksel_con = CRU_CLKSELS_CON(13),
- CRU_SRC_SET(0x3,8),
- CRU_PARENTS_SET(clk_uart0_parents),
-};
-
-static struct clk *clk_uart1_parents[3]={&clk_uart1_div,&clk_uart1_frac_div,&xin24m};
-static struct clk clk_uart1 = {
- .name = "uart1",
- .set_rate = clk_uart_set_rate,
- .clksel_con = CRU_CLKSELS_CON(14),
- CRU_SRC_SET(0x3,8),
- CRU_PARENTS_SET(clk_uart1_parents),
-};
-
-static struct clk *clk_uart2_parents[3]={&clk_uart2_div,&clk_uart2_frac_div,&xin24m};
-static struct clk clk_uart2 = {
- .name = "uart2",
- .set_rate = clk_uart_set_rate,
- .clksel_con = CRU_CLKSELS_CON(15),
- CRU_SRC_SET(0x3,8),
- CRU_PARENTS_SET(clk_uart2_parents),
-};
-static struct clk *clk_uart3_parents[3]={&clk_uart3_div,&clk_uart3_frac_div,&xin24m};
-static struct clk clk_uart3 = {
- .name = "uart3",
- .set_rate = clk_uart_set_rate,
- .clksel_con = CRU_CLKSELS_CON(16),
- CRU_SRC_SET(0x3,8),
- CRU_PARENTS_SET(clk_uart3_parents),
-};
-
-GATE_CLK(timer0, xin24m, TIMER0);
-GATE_CLK(timer1, xin24m, TIMER1);
-GATE_CLK(timer2, xin24m, TIMER2);
-
-static struct clk rmii_clkin = {
- .name = "rmii_clkin",
-};
-static struct clk *clk_mac_ref_div_parents[2]={&general_pll_clk,&ddr_pll_clk};
-static struct clk clk_mac_pll_div = {
- .name = "mac_pll_div",
- .parent = &ddr_pll_clk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_MAC,
- .recalc = clksel_recalc_div,
- .set_rate =clksel_set_rate_freediv,
- //.set_rate = clksel_set_rate_freediv,
- .clksel_con =CRU_CLKSELS_CON(21),
- CRU_DIV_SET(0x1f,8,32),
- CRU_SRC_SET(0x1,0),
- CRU_PARENTS_SET(clk_mac_ref_div_parents),
-};
-
-static int clksel_mac_ref_set_rate(struct clk *clk, unsigned long rate)
-{
-
- if(clk->parent==clk->parents[1])
- {
- CRU_PRINTK_DBG("mac_ref clk is form mii clkin,can't set it\n" );
- return -ENOENT;
- }
- else if(clk->parent==clk->parents[0])
- {
- return clk_set_rate_nolock(clk->parents[0],rate);
- }
- return -ENOENT;
-}
-
-static struct clk *clk_mac_ref_parents[2]={&clk_mac_pll_div,&rmii_clkin};
-
-static struct clk clk_mac_ref = {
- .name = "mac_ref",
- .parent = &clk_mac_pll_div,
- .set_rate = clksel_mac_ref_set_rate,
- .clksel_con =CRU_CLKSELS_CON(21),
- CRU_SRC_SET(0x1,4),
- CRU_PARENTS_SET(clk_mac_ref_parents),
-};
-
-static int clk_set_mii_tx_parent(struct clk *clk, struct clk *parent)
-{
- return clk_set_parent_nolock(clk->parent,parent);
-}
-
-static struct clk clk_mii_tx = {
- .name = "mii_tx",
- .parent = &clk_mac_ref,
- //.set_parent = clk_set_mii_tx_parent,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_MAC_LBTEST,//???
-};
-
-static struct clk *clk_hsadc_pll_parents[2]={&general_pll_clk,&codec_pll_clk};
-static struct clk clk_hsadc_pll_div = {
- .name = "hsadc_pll_div",
- .parent = &general_pll_clk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_SARADC,
- .recalc = clksel_recalc_div,
- .round_rate =clk_freediv_round_autosel_parents_rate,
- .set_rate = clkset_rate_freediv_autosel_parents,
- //.round_rate =clksel_freediv_round_rate,
- //.set_rate = clksel_set_rate_freediv,
- .clksel_con =CRU_CLKSELS_CON(22),
- CRU_DIV_SET(0xff,8,256),
- CRU_SRC_SET(0x1,0),
- CRU_PARENTS_SET(clk_hsadc_pll_parents),
-};
-
-static int clk_hsadc_fracdiv_set_rate_fixed_parent(struct clk *clk, unsigned long rate)
-{
- u32 numerator, denominator;
- // clk_hsadc_pll_div->gpll/cpll
- //clk->parent->parent
- if(frac_div_get_seting(rate,clk->parent->parent->rate,
- &numerator,&denominator)==0)
- {
- clk_set_rate_nolock(clk->parent,clk->parent->parent->rate);//PLL:DIV 1:
-
- cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
-
- CRU_PRINTK_DBG("%s set rate=%lu,is ok\n",clk->name,rate);
- }
- else
- {
- CRU_PRINTK_ERR("clk_frac_div can't get rate=%lu,%s\n",rate,clk->name);
- return -ENOENT;
- }
- return 0;
-}
-static int clk_hsadc_fracdiv_set_rate_auto_parents(struct clk *clk, unsigned long rate)
-{
- u32 numerator, denominator;
- u32 i,ret=0;
- // clk_hsadc_pll_div->gpll/cpll
- //clk->parent->parent
- for(i=0;i<2;i++)
- {
- if(frac_div_get_seting(rate,clk->parent->parents[i]->rate,
- &numerator,&denominator)==0)
- break;
- }
- if(i>=2)
- return -ENOENT;
-
- if(clk->parent->parent!=clk->parent->parents[i])
- ret=clk_set_parent_nolock(clk->parent, clk->parent->parents[i]);
- if(ret==0)
- {
- clk_set_rate_nolock(clk->parent,clk->parent->parents[i]->rate);//PLL:DIV 1:
-
- cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
-
- CRU_PRINTK_DBG("clk_frac_div %s, rate=%lu\n",clk->name,rate);
- }
- else
- {
- CRU_PRINTK_ERR("clk_frac_div can't get rate=%lu,%s\n",rate,clk->name);
- return -ENOENT;
- }
- return 0;
-}
-
-static long clk_hsadc_fracdiv_round_rate(struct clk *clk, unsigned long rate)
-{
- u32 numerator, denominator;
-
- CRU_PRINTK_ERR("clk_hsadc_fracdiv_round_rate\n");
- if(frac_div_get_seting(rate,clk->parent->parent->rate,
- &numerator,&denominator)==0)
- return rate;
-
- return 0;
-}
-static struct clk clk_hsadc_frac_div = {
- .name = "hsadc_frac_div",
- .parent = &clk_hsadc_pll_div,
- .mode = gate_mode,
- .recalc = clksel_recalc_frac,
- .set_rate = clk_hsadc_fracdiv_set_rate_auto_parents,
- .round_rate =clk_hsadc_fracdiv_round_rate,
- .gate_idx = CLK_GATE_HSADC_FRAC,
- .clksel_con = CRU_CLKSELS_CON(23),
-};
-
-#define HSADC_SRC_DIV 0x0
-#define HSADC_SRC_FRAC 0x1
-#define HSADC_SRC_EXT 0x2
-static int clk_hsadc_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret = -EINVAL;
- struct clk *parent;
-
- if(clk->parent == clk->parents[HSADC_SRC_EXT]){
- CRU_PRINTK_DBG("hsadc clk is form ext\n");
- return 0;
- }
- else if((long)clk_round_rate_nolock(clk->parents[HSADC_SRC_DIV],rate)==rate)
- {
- parent =clk->parents[HSADC_SRC_DIV];
- }
- else if((long)clk_round_rate_nolock(clk->parents[HSADC_SRC_FRAC],rate)==rate)
- {
- parent = clk->parents[HSADC_SRC_FRAC];
- }
- else
- parent =clk->parents[HSADC_SRC_DIV];
-
- CRU_PRINTK_DBG(" %s set rate=%lu parent %s(old %s)\n",
- clk->name,rate,parent->name,clk->parent->name);
-
- ret = clk_set_rate_nolock(parent,rate);
- if (ret)
- {
- CRU_PRINTK_ERR("%s set rate%lu err\n",clk->name,rate);
- return ret;
- }
- if (clk->parent != parent)
- {
- ret = clk_set_parent_nolock(clk, parent);
- if (ret)
- {
- CRU_PRINTK_ERR("%s can't get rate%lu,reparent err\n",clk->name,rate);
- return ret;
- }
- }
- return ret;
-}
-
-static struct clk clk_hsadc_ext = {
- .name = "hsadc_ext",
-};
-
-static struct clk *clk_hsadc_parents[3]={&clk_hsadc_pll_div,&clk_hsadc_frac_div,&clk_hsadc_ext};
-static struct clk clk_hsadc = {
- .name = "hsadc",
- .parent = &clk_hsadc_pll_div,
- .set_rate = clk_hsadc_set_rate,
- .clksel_con = CRU_CLKSELS_CON(22),
- CRU_SRC_SET(0x3,4),
- CRU_PARENTS_SET(clk_hsadc_parents),
-};
-
-static struct clk *dclk_lcdc_div_parents[]={&codec_pll_clk,&general_pll_clk};
-static struct clk dclk_lcdc0_div = {
- .name = "dclk_lcdc0_div",
- .parent = &general_pll_clk,
- .recalc = clksel_recalc_div,
- .set_rate = clkset_rate_freediv_autosel_parents,
- .clksel_con = CRU_CLKSELS_CON(27),
- CRU_DIV_SET(0xff,8,256),
- CRU_SRC_SET(0x1,0),
- CRU_PARENTS_SET(dclk_lcdc_div_parents),
-};
-
-static int clksel_set_rate_hdmi(struct clk *clk, unsigned long rate)
-{
- u32 div,old_div;
- int i;
- unsigned long new_rate;
- int ret=0;
-
- if(clk->rate==rate)
- return 0;
- for(i=0;i<2;i++)
- {
- div=clk_get_freediv(rate,clk->parents[i]->rate,clk->div_max);
- new_rate= clk->parents[i]->rate/div;
- if((rate==new_rate)&&!(clk->parents[i]->rate%div))
- {
- break;
- }
- }
- if(i>=2)
- {
- CRU_PRINTK_ERR("%s can't set fixed rate%lu\n",clk->name,rate);
- return -1;
- }
-
- //CRU_PRINTK_DBG("%s set rate %lu(from %s)\n",clk->name,rate,clk->parents[i]->name);
-
- old_div=CRU_GET_REG_BIYS_VAL(cru_readl(clk->clksel_con),
- clk->div_shift,clk->div_mask)+1;
- if(div>old_div)
- set_cru_bits_w_msk(div-1,clk->div_mask,clk->div_shift,clk->clksel_con);
-
- if(clk->parents[i]!=clk->parent)
- {
- ret=clk_set_parent_nolock(clk,clk->parents[i]);
- }
-
- if (ret)
- {
- CRU_PRINTK_ERR("lcdc1 %s can't get rate%lu,reparent%s(now %s) err\n",
- clk->name,rate,clk->parents[i]->name,clk->parent->name);
- return ret;
- }
- set_cru_bits_w_msk(div-1,clk->div_mask,clk->div_shift,clk->clksel_con);
- return 0;
-}
-//hdmi
-static struct clk dclk_lcdc1_div = {
- .name = "dclk_lcdc1_div",
- .parent = &general_pll_clk,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_hdmi,//clk_freediv_autosel_parents_set_fixed_rate
- .clksel_con = CRU_CLKSELS_CON(28),
- CRU_DIV_SET(0xff,8,256),
- CRU_SRC_SET(0x1,0),
- CRU_PARENTS_SET(dclk_lcdc_div_parents),
-};
-
-static int dclk_lcdc_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret = 0;
- struct clk *parent;
-
- if (rate == 27 * MHZ&&(rk30_clock_flags&CLK_FLG_EXT_27MHZ)) {
- parent =clk->parents[1];
- //CRU_PRINTK_DBG(" %s from=%s\n",clk->name,parent->name);
- } else {
- parent=clk->parents[0];
- }
- //CRU_PRINTK_DBG(" %s set rate=%lu parent %s(old %s)\n",
- //clk->name,rate,parent->name,clk->parent->name);
-
- if(parent!=clk->parents[1])
- {
- ret = clk_set_rate_nolock(parent,rate);//div 1:1
- if (ret)
- {
- CRU_PRINTK_DBG("%s set rate=%lu err\n",clk->name,rate);
- return ret;
- }
- }
- if (clk->parent != parent)
- {
- ret = clk_set_parent_nolock(clk, parent);
- if (ret)
- {
- CRU_PRINTK_DBG("%s can't get rate%lu,reparent err\n",clk->name,rate);
- return ret;
- }
- }
- return ret;
-}
-
-static struct clk *dclk_lcdc0_parents[2]={&dclk_lcdc0_div,&xin27m};
-static struct clk dclk_lcdc0 = {
- .name = "dclk_lcdc0",
- .mode = gate_mode,
- .set_rate = dclk_lcdc_set_rate,
- .gate_idx = CLK_GATE_DCLK_LCDC0,
- .clksel_con = CRU_CLKSELS_CON(27),
- CRU_SRC_SET(0x1,4),
- CRU_PARENTS_SET(dclk_lcdc0_parents),
-};
-
-static struct clk *dclk_lcdc1_parents[2]={&dclk_lcdc1_div,&xin27m};
-static struct clk dclk_lcdc1 = {
- .name = "dclk_lcdc1",
- .mode = gate_mode,
- .set_rate = dclk_lcdc_set_rate,
- .gate_idx = CLK_GATE_DCLK_LCDC1,
- .clksel_con = CRU_CLKSELS_CON(28),
- CRU_SRC_SET(0x1,4),
- CRU_PARENTS_SET(dclk_lcdc1_parents),
-};
-
-static struct clk *cifout_sel_pll_parents[2]={&codec_pll_clk,&general_pll_clk};
-static struct clk cif_out_pll = {
- .name = "cif_out_pll",
- .parent = &general_pll_clk,
- .clksel_con = CRU_CLKSELS_CON(29),
- CRU_SRC_SET(0x1,0),
- CRU_PARENTS_SET(cifout_sel_pll_parents),
-};
-
-static struct clk cif0_out_div = {
- .name = "cif0_out_div",
- .parent = &cif_out_pll,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .gate_idx =CLK_GATE_CIF0_OUT,
- .clksel_con = CRU_CLKSELS_CON(29),
- CRU_DIV_SET(0x1f,1,32),
-};
-
-static struct clk cif1_out_div = {
- .name = "cif1_out_div",
- .parent = &cif_out_pll,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .gate_idx = CLK_GATE_CIF1_OUT,
- .clksel_con = CRU_CLKSELS_CON(29),
- CRU_DIV_SET(0x1f,8,32),
-};
-
-
-static int cif_out_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret = 0;
- struct clk *parent;
-
- if (rate == 24 * MHZ) {
- parent =clk->parents[1];
- } else {
- parent=clk->parents[0];
- ret = clk_set_rate_nolock(parent, rate);
- if (ret)
- return ret;
- }
- if (clk->parent != parent)
- ret = clk_set_parent_nolock(clk, parent);
-
- return ret;
-}
-
-static struct clk *cif0_out_parents[2]={&cif0_out_div,&xin24m};
-static struct clk cif0_out = {
- .name = "cif0_out",
- .parent = &cif0_out_div,
- .set_rate = cif_out_set_rate,
- .clksel_con = CRU_CLKSELS_CON(29),
- CRU_SRC_SET(0x1,7),
- CRU_PARENTS_SET(cif0_out_parents),
-};
-static struct clk *cif1_out_parents[2]={&cif1_out_div,&xin24m};
-
-static struct clk cif1_out = {
- .name = "cif1_out",
- .parent = &cif1_out_div,
- .set_rate = cif_out_set_rate,
- .clksel_con = CRU_CLKSELS_CON(29),
- CRU_SRC_SET(0x1,15),
- CRU_PARENTS_SET(cif1_out_parents),
-};
-
-static struct clk pclkin_cif0 = {
- .name = "pclkin_cif0",
- .mode = gate_mode,
- .gate_idx =CLK_GATE_PCLKIN_CIF0,
-};
-
-static struct clk inv_cif0 = {
- .name = "inv_cif0",
- .parent = &pclkin_cif0,
-};
-
-static struct clk *cif0_in_parents[2]={&pclkin_cif0,&inv_cif0};
-static struct clk cif0_in = {
- .name = "cif0_in",
- .parent = &pclkin_cif0,
- .clksel_con = CRU_CLKSELS_CON(30),
- CRU_SRC_SET(0x1,8),
- CRU_PARENTS_SET(cif0_in_parents),
-};
-
-static struct clk pclkin_cif1 = {
- .name = "pclkin_cif1",
- .mode = gate_mode,
- .gate_idx =CLK_GATE_PCLKIN_CIF1,
-};
-
-static struct clk inv_cif1 = {
- .name = "inv_cif1",
- .parent = &pclkin_cif1,
-};
-static struct clk *cif1_in_parents[2]={&pclkin_cif1,&inv_cif1};
-
-static struct clk cif1_in = {
- .name = "cif1_in",
- .parent = &pclkin_cif1,
- .clksel_con = CRU_CLKSELS_CON(30),
- CRU_SRC_SET(0x1,12),
- CRU_PARENTS_SET(cif1_in_parents),
-};
-
-static struct clk *aclk_lcdc0_ipp_parents[]={&codec_pll_clk,&general_pll_clk};
-
-static struct clk aclk_lcdc0_ipp_parent = {
- .name = "aclk_lcdc0_ipp_parent",
- .parent = &codec_pll_clk,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clkset_rate_freediv_autosel_parents,
- //.set_rate = clksel_set_rate_freediv,
- .gate_idx = CLK_GATE_ACLK_LCDC0_SRC,
- .clksel_con = CRU_CLKSELS_CON(31),
- CRU_DIV_SET(0x1f,0,32),
- CRU_SRC_SET(0x1,7),
- CRU_PARENTS_SET(aclk_lcdc0_ipp_parents),
-};
-
-static struct clk *aclk_lcdc1_rga_parents[]={&codec_pll_clk,&general_pll_clk};
-
-static struct clk aclk_lcdc1_rga_parent = {
- .name = "aclk_lcdc1_rga_parent",
- .parent = &codec_pll_clk,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clkset_rate_freediv_autosel_parents,
- .gate_idx = CLK_GATE_ACLK_LCDC1_SRC,
- .clksel_con = CRU_CLKSELS_CON(31),
- CRU_DIV_SET(0x1f,8,32),
- CRU_SRC_SET(0x1,15),
- CRU_PARENTS_SET(aclk_lcdc1_rga_parents),
-};
-
-
-//for free div
-static unsigned long clksel_recalc_vpu_hclk(struct clk *clk)
-{
- unsigned long rate = clk->parent->rate / 4;
- pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, 4);
- return rate;
-}
-
-static struct clk *aclk_vepu_parents[2]={&codec_pll_clk,&general_pll_clk};
-
-static struct clk aclk_vepu = {
- .name = "aclk_vepu",
- .parent = &codec_pll_clk,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- //.set_rate = clksel_set_rate_freediv,
- .set_rate =clkset_rate_freediv_autosel_parents,
- .clksel_con = CRU_CLKSELS_CON(32),
- .gate_idx = CLK_GATE_ACLK_VEPU,
- CRU_DIV_SET(0x1f,0,32),
- CRU_SRC_SET(0x1,7),
- CRU_PARENTS_SET(aclk_vepu_parents),
-};
-
-static struct clk hclk_vepu = {
- .name = "hclk_vepu",
- .parent = &aclk_vepu,
- .mode = gate_mode,
- .recalc = clksel_recalc_vpu_hclk,
- .clksel_con = CRU_CLKSELS_CON(32),
- .gate_idx = CLK_GATE_HCLK_VEPU,
-};
-
-static struct clk *aclk_vdpu_parents[2]={&codec_pll_clk,&general_pll_clk};
-
-static struct clk aclk_vdpu = {
- .name = "aclk_vdpu",
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- //.set_rate = clksel_set_rate_freediv,
- .set_rate =clkset_rate_freediv_autosel_parents,
- .clksel_con = CRU_CLKSELS_CON(32),
- .gate_idx = CLK_GATE_ACLK_VDPU,
- CRU_DIV_SET(0x1f,8,32),
- CRU_SRC_SET(0x1,15),
- CRU_PARENTS_SET(aclk_vdpu_parents),
-};
-static struct clk hclk_vdpu = {
- .name = "hclk_vdpu",
- .parent = &aclk_vdpu,
- .mode = gate_mode,
- .recalc = clksel_recalc_vpu_hclk,
- .clksel_con = CRU_CLKSELS_CON(32),
- .gate_idx = CLK_GATE_HCLK_VDPU,
-};
-
-
-static int clk_gpu_set_rate(struct clk *clk, unsigned long rate)
-{
- unsigned long max_rate = rate / 100 * 105; /* +5% */
- return clkset_rate_freediv_autosel_parents(clk,max_rate);
-};
-
-static struct clk *gpu_parents[2]={&codec_pll_clk,&general_pll_clk};
-
-static struct clk clk_gpu = {
- .name = "gpu",
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .round_rate = clk_freediv_round_autosel_parents_rate,
- .set_rate = clkset_rate_freediv_autosel_parents,
- .clksel_con = CRU_CLKSELS_CON(33),
- .gate_idx = CLK_GATE_GPU_SRC,
- CRU_DIV_SET(0x1f,0,32),
- CRU_SRC_SET(0x1,8),
- CRU_PARENTS_SET(gpu_parents),
-};
-
-/*********************power domain*******************************/
-#ifdef RK30_CLK_OFFBOARD_TEST
-void pmu_set_power_domain_test(enum pmu_power_domain pd, bool on){};
- #define _pmu_set_power_domain pmu_set_power_domain_test//rk30_pmu_set_power_domain
-#else
-void pmu_set_power_domain(enum pmu_power_domain pd, bool on);
- #define _pmu_set_power_domain pmu_set_power_domain
-#endif
-static int pm_off_mode(struct clk *clk, int on)
-{
- _pmu_set_power_domain(clk->gate_idx,on);//on 1
- return 0;
-}
-static struct clk pd_peri = {
- .name = "pd_peri",
- .flags = IS_PD,
- .mode = pm_off_mode,
- .gate_idx = PD_PERI,
-};
-
-static int pd_display_mode(struct clk *clk, int on)
-{
- u32 gate[10];
-
- gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
- gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
- gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
- gate[3] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
- gate[4] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
- gate[5] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
- gate[6] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
- gate[7] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
- gate[8] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
- gate[9] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
- pmu_set_power_domain(PD_VIO, on);
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1) | gate[3], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0) | gate[4], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1) | gate[5], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0) | gate[6], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1) | gate[7], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP) | gate[8], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA) | gate[9], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
-
- return 0;
-}
-
-static struct clk pd_display = {
- .name = "pd_display",
- .flags = IS_PD,
- .mode = pd_display_mode,
- .gate_idx = PD_VIO,
-};
-
-static struct clk pd_lcdc0 = {
- .parent = &pd_display,
- .name = "pd_lcdc0",
-};
-static struct clk pd_lcdc1 = {
- .parent = &pd_display,
- .name = "pd_lcdc1",
-};
-static struct clk pd_cif0 = {
- .parent = &pd_display,
- .name = "pd_cif0",
-};
-static struct clk pd_cif1 = {
- .parent = &pd_display,
- .name = "pd_cif1",
-};
-static struct clk pd_rga = {
- .parent = &pd_display,
- .name = "pd_rga",
-};
-static struct clk pd_ipp = {
- .parent = &pd_display,
- .name = "pd_ipp",
-};
-
-static int pd_video_mode(struct clk *clk, int on)
-{
- u32 gate[3];
-
- gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
- gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
- gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
- pmu_set_power_domain(PD_VIDEO, on);
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
-
- return 0;
-}
-
-static struct clk pd_video = {
- .name = "pd_video",
- .flags = IS_PD,
- .mode = pd_video_mode,
- .gate_idx = PD_VIDEO,
-};
-
-static int pd_gpu_mode(struct clk *clk, int on)
-{
- u32 gate[2];
-
- gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_GPU_SRC));
- gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_GPU_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_GPU_SRC));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
- pmu_set_power_domain(PD_GPU, on);
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_GPU_SRC) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_GPU_SRC));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
-
- return 0;
-}
-
-static struct clk pd_gpu = {
- .name = "pd_gpu",
- .flags = IS_PD,
- .mode = pd_gpu_mode,
- .gate_idx = PD_GPU,
-};
-static struct clk pd_dbg = {
- .name = "pd_dbg",
- .flags = IS_PD,
- .mode = pm_off_mode,
- .gate_idx = PD_DBG,
-};
-
-#define PD_CLK(name) \
-{\
- .dev_id = NULL,\
- .con_id = #name,\
- .clk = &name,\
-}
-
-
-/************************rk30 fixed div clock****************************************/
-
-/*************************aclk_cpu***********************/
-
-GATE_CLK(dma1, aclk_cpu, ACLK_DMAC1);
-GATE_CLK(l2mem_con, aclk_cpu, ACLK_L2MEM_CON);
-GATE_CLK(intmem, aclk_cpu, ACLK_INTMEM);
-GATE_CLK(aclk_strc_sys, aclk_cpu, ACLK_STRC_SYS);
-
-/*************************hclk_cpu***********************/
-
-GATE_CLK(rom, hclk_cpu, HCLK_ROM);
-GATE_CLK(hclk_i2s0_2ch, hclk_cpu, HCLK_I2S0_2CH);
-GATE_CLK(hclk_i2s1_2ch, hclk_cpu, HCLK_I2S1_2CH);
-GATE_CLK(hclk_spdif, hclk_cpu, HCLK_SPDIF);
-GATE_CLK(hclk_i2s_8ch, hclk_cpu, HCLK_I2S_8CH);
-GATE_CLK(hclk_cpubus, hclk_cpu, HCLK_CPUBUS);
-GATE_CLK(hclk_ahb2apb, hclk_cpu, HCLK_AHB2APB);
-GATE_CLK(hclk_vio_bus, hclk_cpu, HCLK_VIO_BUS);
-GATE_CLK(hclk_lcdc0, hclk_cpu, HCLK_LCDC0);
-GATE_CLK(hclk_lcdc1, hclk_cpu, HCLK_LCDC1);
-GATE_CLK(hclk_cif0, hclk_cpu, HCLK_CIF0);
-GATE_CLK(hclk_cif1, hclk_cpu, HCLK_CIF1);
-GATE_CLK(hclk_ipp, hclk_cpu, HCLK_IPP);
-GATE_CLK(hclk_rga, hclk_cpu, HCLK_RGA);
-GATE_CLK(hclk_hdmi, hclk_cpu, HCLK_HDMI);
-//GATE_CLK(hclk_vidoe_h2h, hclk_cpu, ); ???
-/*************************pclk_cpu***********************/
-GATE_CLK(pwm01, pclk_cpu, PCLK_PWM01);//pwm 0¡¢1
-//GATE_CLK(pclk_pwm1, pclk_cpu, PCLK_PWM01);//pwm 0¡¢1
-GATE_CLK(pclk_timer0, pclk_cpu, PCLK_TIMER0);
-GATE_CLK(pclk_timer1, pclk_cpu, PCLK_TIMER1);
-GATE_CLK(pclk_timer2, pclk_cpu, PCLK_TIMER2);
-GATE_CLK(i2c0, pclk_cpu, PCLK_I2C0);
-GATE_CLK(i2c1, pclk_cpu, PCLK_I2C1);
-GATE_CLK(gpio0, pclk_cpu, PCLK_GPIO0);
-GATE_CLK(gpio1, pclk_cpu, PCLK_GPIO1);
-GATE_CLK(gpio2, pclk_cpu, PCLK_GPIO2);
-GATE_CLK(gpio6, pclk_cpu, PCLK_GPIO6);
-GATE_CLK(efuse, pclk_cpu, PCLK_EFUSE);
-GATE_CLK(tzpc, pclk_cpu, PCLK_TZPC);
-GATE_CLK(pclk_uart0, pclk_cpu, PCLK_UART0);
-GATE_CLK(pclk_uart1, pclk_cpu, PCLK_UART1);
-GATE_CLK(pclk_ddrupctl, pclk_cpu, PCLK_DDRUPCTL);
-GATE_CLK(pclk_ddrpubl, pclk_cpu, PCLK_PUBL);
-GATE_CLK(dbg, pclk_cpu, PCLK_DBG);
-GATE_CLK(grf, pclk_cpu, PCLK_GRF);
-GATE_CLK(pmu, pclk_cpu, PCLK_PMU);
-
-/*************************aclk_periph***********************/
-
-GATE_CLK(dma2, aclk_periph,ACLK_DMAC2);
-GATE_CLK(aclk_smc, aclk_periph, ACLK_SMC);
-GATE_CLK(aclk_peri_niu, aclk_periph, ACLK_PEI_NIU);
-GATE_CLK(aclk_cpu_peri, aclk_periph, ACLK_CPU_PERI);
-GATE_CLK(aclk_peri_axi_matrix, aclk_periph, ACLK_PERI_AXI_MATRIX);
-
-/*************************hclk_periph***********************/
-GATE_CLK(hclk_peri_axi_matrix, hclk_periph, HCLK_PERI_AXI_MATRIX);
-GATE_CLK(hclk_peri_ahb_arbi, hclk_periph, HCLK_PERI_AHB_ARBI);
-GATE_CLK(hclk_emem_peri, hclk_periph, HCLK_EMEM_PERI);
-GATE_CLK(hclk_mac, hclk_periph, HCLK_EMAC);
-GATE_CLK(nandc, hclk_periph, HCLK_NANDC);
-GATE_CLK(hclk_usb_peri, hclk_periph, HCLK_USB_PERI);
-GATE_CLK(hclk_otg0, clk_hclk_usb_peri, HCLK_OTG0);
-GATE_CLK(hclk_otg1, clk_hclk_usb_peri, HCLK_OTG1);
-GATE_CLK(hclk_hsadc, hclk_periph, HCLK_HSADC);
-GATE_CLK(hclk_pidfilter, hclk_periph, HCLK_PIDF);
-GATE_CLK(hclk_sdmmc, hclk_periph, HCLK_SDMMC0);
-GATE_CLK(hclk_sdio, hclk_periph, HCLK_SDIO);
-GATE_CLK(hclk_emmc, hclk_periph, HCLK_EMMC);
-/*************************pclk_periph***********************/
-GATE_CLK(pclk_peri_axi_matrix, pclk_periph, PCLK_PERI_AXI_MATRIX);
-GATE_CLK(pwm23, pclk_periph, PCLK_PWM23);
-//GATE_CLK(pclk_pwm3, pclk_periph, PCLK_PWM3);
-GATE_CLK(wdt, pclk_periph, PCLK_WDT);
-GATE_CLK(pclk_spi0, pclk_periph, PCLK_SPI0);
-GATE_CLK(pclk_spi1, pclk_periph, PCLK_SPI1);
-GATE_CLK(pclk_uart2, pclk_periph, PCLK_UART2);
-GATE_CLK(pclk_uart3, pclk_periph, PCLK_UART3);
-GATE_CLK(i2c2, pclk_periph, PCLK_I2C2);
-GATE_CLK(i2c3, pclk_periph, PCLK_I2C3);
-GATE_CLK(i2c4, pclk_periph, PCLK_I2C4);
-GATE_CLK(gpio3, pclk_periph, PCLK_GPIO3);
-GATE_CLK(gpio4, pclk_periph, PCLK_GPIO4);
-GATE_CLK(pclk_saradc, pclk_periph, PCLK_SARADC);
-GATE_CLK(pclk_tsadc, pclk_periph, PCLK_TSADC);
-/*************************aclk_lcdc0***********************/
-GATE_CLK(aclk_lcdc0, aclk_lcdc0_ipp_parent, ACLK_LCDC0);
-GATE_CLK(aclk_vio0, aclk_lcdc0_ipp_parent, ACLK_VIO0);
-GATE_CLK(aclk_cif0, aclk_lcdc0_ipp_parent, ACLK_CIF0);
-GATE_CLK(aclk_ipp, aclk_lcdc0_ipp_parent, ACLK_IPP);
-
-/*************************aclk_lcdc0***********************/
-
-GATE_CLK(aclk_lcdc1, aclk_lcdc1_rga_parent, ACLK_LCDC1);
-GATE_CLK(aclk_vio1, aclk_lcdc1_rga_parent, ACLK_VIO1);
-GATE_CLK(aclk_cif1, aclk_lcdc1_rga_parent, ACLK_CIF0);
-GATE_CLK(aclk_rga, aclk_lcdc1_rga_parent, ACLK_RGA);
-
-
-#if 1
-#define CLK(dev, con, ck) \
- {\
- .dev_id = dev,\
- .con_id = con,\
- .clk = ck,\
- }
-
-
-#define CLK1(name) \
- {\
- .dev_id = NULL,\
- .con_id = #name,\
- .clk = &clk_##name,\
- }
-
-#endif
-
-
-
-
-static struct clk_lookup clks[] = {
- CLK(NULL, "xin24m", &xin24m),
- CLK(NULL, "xin27m", &xin27m),
- CLK(NULL, "xin12m", &clk_12m),
- CLK(NULL, "arm_pll", &arm_pll_clk),
- CLK(NULL, "ddr_pll", &ddr_pll_clk),
- CLK(NULL, "codec_pll", &codec_pll_clk),
- CLK(NULL, "general_pll", &general_pll_clk),
-
- CLK(NULL, "ddr", &clk_ddr),
- //CLK(NULL, "core_gpll_path", &clk_cpu_gpll_path),
- CLK(NULL, "cpu", &clk_cpu),
- CLK(NULL, "arm_gpll", &clk_cpu_gpll_path),
- CLK("smp_twd", NULL, &core_periph),
- CLK(NULL, "aclk_cpu", &aclk_cpu),
- CLK(NULL, "hclk_cpu", &hclk_cpu),
- CLK(NULL, "pclk_cpu", &pclk_cpu),
- CLK(NULL, "atclk_cpu", &atclk_cpu),
-
-
- CLK1(i2s_pll),
- CLK("rk29_i2s.0", "i2s_div", &clk_i2s0_div),
- CLK("rk29_i2s.0", "i2s_frac_div", &clk_i2s0_frac_div),
- CLK("rk29_i2s.0", "i2s", &clk_i2s0),
- CLK("rk29_i2s.0", "hclk_i2s", &clk_hclk_i2s_8ch),
-
- CLK("rk29_i2s.1", "i2s_div", &clk_i2s1_div),
- CLK("rk29_i2s.1", "i2s_frac_div", &clk_i2s1_frac_div),
- CLK("rk29_i2s.1", "i2s", &clk_i2s1),
- CLK("rk29_i2s.1", "hclk_i2s", &clk_hclk_i2s0_2ch),
-
- CLK("rk29_i2s.2", "i2s_div", &clk_i2s2_div),
- CLK("rk29_i2s.2", "i2s_frac_div", &clk_i2s2_frac_div),
- CLK("rk29_i2s.2", "i2s", &clk_i2s2),
- CLK("rk29_i2s.2", "hclk_i2s", &clk_hclk_i2s1_2ch),
-
- CLK1(spdif_div),
- CLK1(spdif_frac_div),
- CLK1(spdif),
- CLK1(hclk_spdif),
-
- CLK(NULL, "aclk_periph", &aclk_periph),
- CLK(NULL, "pclk_periph", &pclk_periph),
- CLK(NULL, "hclk_periph", &hclk_periph),
-
- CLK("rk29xx_spim.0", "spi", &clk_spi0),
- CLK("rk29xx_spim.0", "pclk_spi", &clk_pclk_spi0),
-
- CLK("rk29xx_spim.1", "spi", &clk_spi1),
- CLK("rk29xx_spim.1", "pclk_spi", &clk_pclk_spi1),
-
- CLK1(saradc),
- CLK1(pclk_saradc),
- CLK1(tsadc),
- CLK1(pclk_tsadc),
- CLK1(otgphy0),
- CLK1(otgphy1),
- CLK1(hclk_usb_peri),
- CLK1(hclk_otg0),
- CLK1(hclk_otg1),
-
-
-
-
-
- CLK1(smc),
- CLK1(aclk_smc),
-
- CLK("rk29_sdmmc.0", "mmc", &clk_sdmmc),
- CLK("rk29_sdmmc.0", "hclk_mmc", &clk_hclk_sdmmc),
- CLK("rk29_sdmmc.1", "mmc", &clk_sdio),
- CLK("rk29_sdmmc.1", "hclk_mmc", &clk_hclk_sdio),
-
- CLK1(emmc),
- CLK1(hclk_emmc),
-
-
- CLK1(uart_pll),
- CLK("rk_serial.0", "uart_div", &clk_uart0_div),
- CLK("rk_serial.0", "uart_frac_div", &clk_uart0_frac_div),
- CLK("rk_serial.0", "uart", &clk_uart0),
- CLK("rk_serial.0", "pclk_uart", &clk_pclk_uart0),
- CLK("rk_serial.1", "uart_div", &clk_uart1_div),
- CLK("rk_serial.1", "uart_frac_div", &clk_uart1_frac_div),
- CLK("rk_serial.1", "uart", &clk_uart1),
- CLK("rk_serial.1", "pclk_uart", &clk_pclk_uart1),
- CLK("rk_serial.2", "uart_div", &clk_uart2_div),
- CLK("rk_serial.2", "uart_frac_div", &clk_uart2_frac_div),
- CLK("rk_serial.2", "uart", &clk_uart2),
- CLK("rk_serial.2", "pclk_uart", &clk_pclk_uart2),
- CLK("rk_serial.3", "uart_div", &clk_uart3_div),
- CLK("rk_serial.3", "uart_frac_div", &clk_uart3_frac_div),
- CLK("rk_serial.3", "uart", &clk_uart3),
- CLK("rk_serial.3", "pclk_uart", &clk_pclk_uart3),
-
- CLK1(timer0),
- CLK1(pclk_timer0),
-
- CLK1(timer1),
- CLK1(pclk_timer1),
-
- CLK1(timer2),
- CLK1(pclk_timer2),
-
- CLK(NULL, "rmii_clkin", &rmii_clkin),
- CLK(NULL, "mac_ref_div", &clk_mac_pll_div), // compatible with rk29
- CLK1(mac_ref),
- CLK1(mii_tx),
- CLK1(hsadc_pll_div),
- CLK1(hsadc_frac_div),
- CLK1(hsadc_ext),
- CLK1(hsadc),
- CLK1(hclk_hsadc),
-
- CLK(NULL, "aclk_lcdc0_ipp_parent", &aclk_lcdc0_ipp_parent),
- CLK(NULL, "aclk_lcdc1_rga_parent", &aclk_lcdc1_rga_parent),
-
- CLK(NULL, "dclk_lcdc0_div", &dclk_lcdc0_div),
- CLK(NULL, "dclk_lcdc1_div", &dclk_lcdc1_div),
-
- CLK(NULL, "dclk_lcdc0", &dclk_lcdc0),
- CLK(NULL, "aclk_lcdc0", &clk_aclk_lcdc0),
- CLK1(hclk_lcdc0),
-
- CLK(NULL, "dclk_lcdc1", &dclk_lcdc1),
- CLK(NULL, "aclk_lcdc1", &clk_aclk_lcdc1),
- CLK1(hclk_lcdc1),
-
- CLK(NULL, "cif_out_pll", &cif_out_pll),
- CLK(NULL, "cif0_out_div", &cif0_out_div),
- CLK(NULL, "cif1_out_div", &cif1_out_div),
-
- CLK(NULL, "cif0_out", &cif0_out),
- CLK1(hclk_cif0),
-
- CLK(NULL, "cif1_out", &cif1_out),
- CLK1(hclk_cif1),
-
- CLK1(hclk_ipp),
- CLK1(hclk_rga),
- CLK1(hclk_hdmi),
-
- CLK(NULL, "pclkin_cif0", &pclkin_cif0),
- CLK(NULL, "inv_cif0", &inv_cif0),
- CLK(NULL, "cif0_in", &cif0_in),
- CLK(NULL, "pclkin_cif1", &pclkin_cif1),
- CLK(NULL, "inv_cif1", &inv_cif1),
- CLK(NULL, "cif1_in", &cif1_in),
- //CLK(NULL, "aclk_lcdc0", &aclk_lcdc0),
- //CLK(NULL, "aclk_lcdc1", &aclk_lcdc1),
- CLK(NULL, "aclk_vepu", &aclk_vepu),
- CLK(NULL, "hclk_vepu", &hclk_vepu),
- CLK(NULL, "aclk_vdpu", &aclk_vdpu),
- CLK(NULL, "hclk_vdpu", &hclk_vdpu),
- CLK1(gpu),
- CLK1(dma1),
- CLK1(l2mem_con),
- CLK1(intmem),
-
- CLK1(aclk_strc_sys),
-
- /*************************hclk_cpu***********************/
-
- CLK1(rom),
- //CLK1(hclk_i2s0_2ch),
- //CLK1(hclk_i2s1_2ch),
- //CLK1(hclk_spdif),
- //CLK1(hclk_i2s_8ch),
- CLK1(hclk_cpubus),
- CLK1(hclk_ahb2apb),
- CLK1(hclk_vio_bus),
- //CLK1(hclk_lcdc0),
- //CLK1(hclk_lcdc1),
- //CLK1(hclk_cif0),
- //CLK1(hclk_cif1),
- //CLK1(hclk_ipp),
- //CLK1(hclk_rga),
- //CLK1(hclk_hdmi),
- //CLK1(hclk_vidoe_h2h, hclk_cpu, ); ???
- /*************************pclk_cpu***********************/
- CLK1(pwm01),//pwm 0¡¢1
-
- //CLK1(pclk_timer0),
- //CLK1(pclk_timer1),
- //CLK1(pclk_timer2),
-
- CLK("rk30_i2c.0", "i2c", &clk_i2c0),
- CLK("rk30_i2c.1", "i2c", &clk_i2c1),
-
- CLK1(gpio0),
- CLK1(gpio1),
- CLK1(gpio2),
- CLK1(gpio6),
- CLK1(efuse),
- CLK1(tzpc),
- //CLK1(pclk_uart0),
- //CLK1(pclk_uart1),
- CLK1(pclk_ddrupctl),
- CLK1(pclk_ddrpubl),
- CLK1(dbg),
- CLK1(grf),
- CLK1(pmu),
-
- /*************************aclk_periph***********************/
-
- CLK1(dma2),
- //CLK1(aclk_smc),
- CLK1(aclk_peri_niu),
- CLK1(aclk_cpu_peri),
- CLK1(aclk_peri_axi_matrix),
-
- /*************************hclk_periph***********************/
- CLK1(hclk_peri_axi_matrix),
- CLK1(hclk_peri_ahb_arbi),
- CLK1(hclk_emem_peri),
- CLK1(hclk_mac),
- CLK1(nandc),
- //CLK1(hclk_usb_peri),
- //CLK1(hclk_usbotg0),
- //CLK1(hclk_usbotg1),
- //CLK1(hclk_hsadc),
- CLK1(hclk_pidfilter),
-
- //CLK1(hclk_emmc),
- /*************************pclk_periph***********************/
- CLK1(pclk_peri_axi_matrix),
- CLK1(pwm23),
-
- CLK1(wdt),
- //CLK1(pclk_spi0),
- //CLK1(pclk_spi1),
- //CLK1(pclk_uart2),
- //CLK1(pclk_uart3),
-
- CLK("rk30_i2c.2", "i2c", &clk_i2c2),
- CLK("rk30_i2c.3", "i2c", &clk_i2c3),
- CLK("rk30_i2c.4", "i2c", &clk_i2c4),
-
- CLK1(gpio3),
- CLK1(gpio4),
-
- /*************************aclk_lcdc0***********************/
- //CLK1(aclk_vio0),
- CLK1(aclk_cif0),
- CLK1(aclk_ipp),
-
- /*************************aclk_lcdc0***********************/
- //CLK1(aclk_vio1),
- CLK1(aclk_cif1),
- CLK1(aclk_rga),
- /************************power domain**********************/
- PD_CLK(pd_peri),
- PD_CLK(pd_display),
- PD_CLK(pd_video),
- PD_CLK(pd_lcdc0),
- PD_CLK(pd_lcdc1),
- PD_CLK(pd_cif0),
- PD_CLK(pd_cif1),
- PD_CLK(pd_rga),
- PD_CLK(pd_ipp),
- PD_CLK(pd_video),
- PD_CLK(pd_gpu),
- PD_CLK(pd_dbg),
-};
-static void __init rk30_init_enable_clocks(void)
-{
- //clk_enable_nolock(&xin24m);
- //clk_enable_nolock(&xin27m);
- //clk_enable_nolock(&clk_12m);
- //clk_enable_nolock(&arm_pll_clk);
- //clk_enable_nolock(&ddr_pll_clk);
- //clk_enable_nolock(&codec_pll_clk);
- //clk_enable_nolock(&general_pll_clk);
- //clk_enable_nolock(&clk_ddr);
-
- clk_enable_nolock(&clk_cpu);
- clk_enable_nolock(&core_periph);
- clk_enable_nolock(&aclk_cpu);
- clk_enable_nolock(&hclk_cpu);
- clk_enable_nolock(&pclk_cpu);
- clk_enable_nolock(&atclk_cpu);
-
- #if 0
- clk_enable_nolock(&clk_i2s_pll);
- clk_enable_nolock(&clk_i2s0_div);
- clk_enable_nolock(&clk_i2s0_frac_div);
- clk_enable_nolock(&clk_i2s0);
- clk_enable_nolock(&clk_hclk_i2s_8ch);
-
- clk_enable_nolock(&clk_i2s1_div);
- clk_enable_nolock(&clk_i2s1_frac_div);
- clk_enable_nolock(&clk_i2s1);
- clk_enable_nolock(&clk_hclk_i2s0_2ch);
-
- clk_enable_nolock(&clk_i2s2_div);
- clk_enable_nolock(&clk_i2s2_frac_div);
- clk_enable_nolock(&clk_i2s2);
- clk_enable_nolock(&clk_hclk_i2s1_2ch);
-
- clk_enable_nolock(&clk_spdif_div);
- clk_enable_nolock(&clk_spdif_frac_div);
- clk_enable_nolock(&clk_spdif);
- clk_enable_nolock(&clk_hclk_spdif);
- #endif
- clk_enable_nolock(&aclk_periph);
- clk_enable_nolock(&pclk_periph);
- clk_enable_nolock(&hclk_periph);
-
- #if 0
- clk_enable_nolock(&clk_spi0);
- clk_enable_nolock(&clk_pclk_spi0);
-
- clk_enable_nolock(&clk_spi1);
- clk_enable_nolock(&clk_pclk_spi1);
- clk_enable_nolock(&clk_saradc);
- clk_enable_nolock(&clk_pclk_saradc);
- clk_enable_nolock(&clk_tsadc);
- clk_enable_nolock(&clk_pclk_tsadc);
- #endif
- #if 0
- clk_enable_nolock(&clk_otgphy0);
- clk_enable_nolock(&clk_otgphy1);
- clk_enable_nolock(&clk_hclk_usb_peri);
- clk_enable_nolock(&clk_hclk_otg0);
- clk_enable_nolock(&clk_hclk_otg1);
- #endif
- #if 0
- clk_enable_nolock(&clk_smc);
- clk_enable_nolock(&clk_aclk_smc);
-
- clk_enable_nolock(&clk_sdmmc);
- clk_enable_nolock(&clk_hclk_sdmmc);
- clk_enable_nolock(&clk_sdio);
- clk_enable_nolock(&clk_hclk_sdio);
-
- clk_enable_nolock(&clk_emmc);
- clk_enable_nolock(&clk_hclk_emmc);
-
- #endif
-
- #if CONFIG_RK_DEBUG_UART == 0
- clk_enable_nolock(&clk_uart0);
- clk_enable_nolock(&clk_pclk_uart0);
- #elif CONFIG_RK_DEBUG_UART == 1
- clk_enable_nolock(&clk_uart1);
- clk_enable_nolock(&clk_pclk_uart1);
-
- #elif CONFIG_RK_DEBUG_UART == 2
- clk_enable_nolock(&clk_uart2);
- clk_enable_nolock(&clk_pclk_uart2);
-
- #elif CONFIG_RK_DEBUG_UART == 3
- clk_enable_nolock(&clk_uart3);
- clk_enable_nolock(&clk_pclk_uart3);
-
- #endif
-
- #if 0
- clk_enable_nolock(&clk_timer0);
- clk_enable_nolock(&clk_pclk_timer0);
-
- clk_enable_nolock(&clk_timer1);
- clk_enable_nolock(&clk_pclk_timer1);
-
- clk_enable_nolock(&clk_timer2);
- clk_enable_nolock(&clk_pclk_timer2);
- #endif
- #if 0
- clk_enable_nolock(&rmii_clkin);
- clk_enable_nolock(&clk_mac_pll_div);
- clk_enable_nolock(&clk_mac_ref);
- clk_enable_nolock(&clk_mii_tx);
- #endif
-
- #if 0
- clk_enable_nolock(&clk_hsadc_pll_div);
- clk_enable_nolock(&clk_hsadc_frac_div);
- clk_enable_nolock(&clk_hsadc_ext);
- clk_enable_nolock(&clk_hsadc);
- clk_enable_nolock(&clk_hclk_hsadc);
- #endif
-
- #if 0
- clk_enable_nolock(&aclk_lcdc0_ipp_parent);
- clk_enable_nolock(&aclk_lcdc1_rga_parent);
-
- clk_enable_nolock(&dclk_lcdc0_div);
- clk_enable_nolock(&dclk_lcdc1_div);
-
- clk_enable_nolock(&dclk_lcdc0);
- clk_enable_nolock(&clk_aclk_lcdc0);
- clk_enable_nolock(&clk_hclk_lcdc0);
-
- clk_enable_nolock(&dclk_lcdc1);
- clk_enable_nolock(&clk_aclk_lcdc1);
- clk_enable_nolock(&clk_hclk_lcdc1);
-
- clk_enable_nolock(&cif_out_pll);
- clk_enable_nolock(&cif0_out_div);
- clk_enable_nolock(&cif1_out_div);
-
- clk_enable_nolock(&cif0_out);
- clk_enable_nolock(&clk_hclk_cif0);
-
- clk_enable_nolock(&cif1_out);
- clk_enable_nolock(&clk_hclk_cif1);
-
- clk_enable_nolock(&clk_hclk_ipp);
- clk_enable_nolock(&clk_hclk_rga);
- clk_enable_nolock(&clk_hclk_hdmi);
-
- clk_enable_nolock(&pclkin_cif0);
- clk_enable_nolock(&inv_cif0);
- clk_enable_nolock(&cif0_in);
- clk_enable_nolock(&pclkin_cif1);
- clk_enable_nolock(&inv_cif1);
- clk_enable_nolock(&cif1_in);
- //CLK(NULL, "aclk_lcdc0", &aclk_lcdc0),
- //CLK(NULL, "aclk_lcdc1", &aclk_lcdc1),
- clk_enable_nolock(&aclk_vepu);
- clk_enable_nolock(&hclk_vepu);
- clk_enable_nolock(&aclk_vdpu);
- clk_enable_nolock(&hclk_vdpu);
- clk_enable_nolock(&clk_gpu);
- #endif
-
- clk_enable_nolock(&clk_dma1);
- clk_enable_nolock(&clk_l2mem_con);
- clk_enable_nolock(&clk_intmem);
-
- clk_enable_nolock(&clk_aclk_strc_sys);
-
- /*************************hclk_cpu***********************/
-
- clk_enable_nolock(&clk_rom);
-
- clk_enable_nolock(&clk_hclk_cpubus);
- clk_enable_nolock(&clk_hclk_ahb2apb);
- clk_enable_nolock(&clk_hclk_vio_bus);
-
- /*************************pclk_cpu***********************/
-
- //clk_enable_nolock(&clk_pwm01);//pwm 0¡¢1
- #if 0
-
-
- clk_enable_nolock(&clk_i2c0);
- clk_enable_nolock(&clk_i2c1);
-
- clk_enable_nolock(&clk_gpio0);
- clk_enable_nolock(&clk_gpio1);
- clk_enable_nolock(&clk_gpio2);
- clk_enable_nolock(&clk_gpio6);
- clk_enable_nolock(&clk_efuse);
- #endif
- clk_enable_nolock(&clk_tzpc);
-
- //CLK1(pclk_uart0),
- //CLK1(pclk_uart1),
- clk_enable_nolock(&clk_pclk_ddrupctl);
- clk_enable_nolock(&clk_pclk_ddrpubl);
- clk_enable_nolock(&clk_dbg);
- clk_enable_nolock(&clk_grf);
- clk_enable_nolock(&clk_pmu);
-
- /*************************aclk_periph***********************/
-
- clk_enable_nolock(&clk_dma2);
- //CLK1(aclk_smc),
- clk_enable_nolock(&clk_aclk_peri_niu);
- clk_enable_nolock(&clk_aclk_cpu_peri);
- clk_enable_nolock(&clk_aclk_peri_axi_matrix);
-
- /*************************hclk_periph***********************/
- clk_enable_nolock(&clk_hclk_peri_axi_matrix);
- clk_enable_nolock(&clk_hclk_peri_ahb_arbi);
- clk_enable_nolock(&clk_hclk_emem_peri);
- clk_enable_nolock(&clk_hclk_mac);
- clk_enable_nolock(&clk_nandc);
- //CLK1(hclk_usb_peri),
- //CLK1(hclk_usbotg0),
- //CLK1(hclk_usbotg1),
- //CLK1(hclk_hsadc),
- clk_enable_nolock(&clk_hclk_pidfilter);
-
- /*************************pclk_periph***********************/
- clk_enable_nolock(&clk_pclk_peri_axi_matrix);
- //clk_enable_nolock(&clk_pwm23);
-
- //clk_enable_nolock(&clk_wdt);
-
- #if 0
-
- clk_enable_nolock(&clk_i2c2);
- clk_enable_nolock(&clk_i2c3);
- clk_enable_nolock(&clk_i2c4);
-
- clk_enable_nolock(&clk_gpio3);
- clk_enable_nolock(&clk_gpio4);
- #endif
- /*************************aclk_lcdc0***********************/
- //clk_enable_nolock(&clk_aclk_vio0);
- //clk_enable_nolock(&clk_aclk_cif0);
- //clk_enable_nolock(&clk_aclk_ipp);
-
- /*************************aclk_lcdc0***********************/
- //clk_enable_nolock(&clk_aclk_vio1);
- //clk_enable_nolock(&clk_aclk_cif1);
- //clk_enable_nolock(&clk_aclk_rga);
- /************************power domain**********************/
-}
-static void periph_clk_set_init(void)
-{
- unsigned long aclk_p, hclk_p, pclk_p;
- unsigned long ppll_rate=general_pll_clk.rate;
- //aclk 148.5
-
- /* general pll */
- switch (ppll_rate) {
- case 148500* KHZ:
- aclk_p = 148500*KHZ;
- hclk_p = aclk_p>>1;
- pclk_p = aclk_p>>2;
- break;
- case 1188*MHZ:
- aclk_p = aclk_p>>3;// 0
- hclk_p = aclk_p>>1;
- pclk_p = aclk_p>>2;
-
- case 297 * MHZ:
- aclk_p = ppll_rate>>1;
- hclk_p = aclk_p>>0;
- pclk_p = aclk_p>>1;
- break;
-
- case 300 * MHZ:
- aclk_p = ppll_rate>>1;
- hclk_p = aclk_p>>0;
- pclk_p = aclk_p>>1;
- break;
- default:
- aclk_p = 150 * MHZ;
- hclk_p = 150 * MHZ;
- pclk_p = 75 * MHZ;
- break;
- }
- clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
- clk_set_rate_nolock(&aclk_periph, aclk_p);
- clk_set_rate_nolock(&hclk_periph, hclk_p);
- clk_set_rate_nolock(&pclk_periph, pclk_p);
-}
-
-
-void rk30_clock_common_i2s_init(void)
-{
- //struct clk *max_clk,*min_clk;
- unsigned long i2s_rate;
- //20 times
- if(rk30_clock_flags&CLK_FLG_MAX_I2S_49152KHZ)
- {
- i2s_rate=49152000;
- }else if(rk30_clock_flags&CLK_FLG_MAX_I2S_24576KHZ)
- {
- i2s_rate=24576000;
- }
- else if(rk30_clock_flags&CLK_FLG_MAX_I2S_22579_2KHZ)
- {
- i2s_rate=22579000;
- }
- else if(rk30_clock_flags&CLK_FLG_MAX_I2S_12288KHZ)
- {
- i2s_rate=12288000;
- }
- else
- {
- i2s_rate=49152000;
- }
-
- if (((i2s_rate * 20) <= codec_pll_clk.rate) || !(codec_pll_clk.rate % i2s_rate)) {
- clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
- } else if (((i2s_rate * 20) <= general_pll_clk.rate) || !(general_pll_clk.rate % i2s_rate)) {
- clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
- } else {
- if (general_pll_clk.rate > codec_pll_clk.rate)
- clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
- else
- clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
- }
-}
-static void __init rk30_clock_common_init(unsigned long gpll_rate,unsigned long cpll_rate)
-{
-
- clk_set_rate_nolock(&clk_cpu, 816*MHZ);//816
- //general
-#ifdef CONFIG_RK29_VMAC
- /* because loader gpll_rate = 300M, but config(nr, nf, no) is not fit for VMAC,
- * board with VMAC need gpll 300, so it will do nothing when gpll init,
- * DO below to make sure gpll's config use (nr = 1, nf = 25, no = 2)
- */
- clk_set_rate_nolock(&general_pll_clk, 297 * MHZ);
-#endif
- clk_set_rate_nolock(&general_pll_clk, gpll_rate);
- lpj_gpll = CLK_LOOPS_RECALC(general_pll_clk.rate);
-
- //code pll
- clk_set_rate_nolock(&codec_pll_clk, cpll_rate);
-
- //periph clk
- periph_clk_set_init();
-
- //i2s
- rk30_clock_common_i2s_init();
-
- // spi
- clk_set_rate_nolock(&clk_spi0, clk_spi0.parent->rate);
- clk_set_rate_nolock(&clk_spi1, clk_spi1.parent->rate);
-
- // uart
- if(rk30_clock_flags&CLK_FLG_UART_1_3M)
- clk_set_parent_nolock(&clk_uart_pll, &codec_pll_clk);
- else
- clk_set_parent_nolock(&clk_uart_pll, &general_pll_clk);
- //mac
- if(!(gpll_rate%(50*MHZ)))
- clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
- else if(!(ddr_pll_clk.rate%(50*MHZ)))
- clk_set_parent_nolock(&clk_mac_pll_div, &ddr_pll_clk);
- else
- CRU_PRINTK_ERR("mac can't get 50mhz\n");
-
- //hsadc
- //auto pll sel
- //clk_set_parent_nolock(&clk_hsadc_pll_div, &general_pll_clk);
-
- //lcdc1 hdmi
- clk_set_parent_nolock(&dclk_lcdc1_div, &general_pll_clk);
-
- //lcdc0 lcd auto sel pll
- //clk_set_parent_nolock(&dclk_lcdc0_div, &general_pll_clk);
-
- //cif
- clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
-
- //axi lcdc auto sel
- //clk_set_parent_nolock(&aclk_lcdc0, &general_pll_clk);
- //clk_set_parent_nolock(&aclk_lcdc1, &general_pll_clk);
- clk_set_rate_nolock(&aclk_lcdc0_ipp_parent, 300*MHZ);
- clk_set_rate_nolock(&aclk_lcdc1_rga_parent, 300*MHZ);
-
- //axi vepu auto sel
- //clk_set_parent_nolock(&aclk_vepu, &general_pll_clk);
- //clk_set_parent_nolock(&aclk_vdpu, &general_pll_clk);
-
- clk_set_rate_nolock(&aclk_vepu, 300*MHZ);
- clk_set_rate_nolock(&aclk_vdpu, 300*MHZ);
- //gpu auto sel
- //clk_set_parent_nolock(&clk_gpu, &general_pll_clk);
-
- clk_set_rate_nolock(&clk_uart0, 49500000);
- clk_set_rate_nolock(&clk_sdmmc, 24750000);
- clk_set_rate_nolock(&clk_sdio, 24750000);
-}
-
-static struct clk def_ops_clk={
- .get_parent=clksel_get_parent,
- .set_parent=clksel_set_parent,
-};
-
-#ifdef CONFIG_PROC_FS
-struct clk_dump_ops dump_ops;
-#endif
-
-static void clk_dump_regs(void);
-
-void __init _rk30_clock_data_init(unsigned long gpll,unsigned long cpll,int flags)
-{
- struct clk_lookup *lk;
-
- clk_register_dump_ops(&dump_ops);
- clk_register_default_ops_clk(&def_ops_clk);
- rk30_clock_flags=flags;
- for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) {
- #ifdef RK30_CLK_OFFBOARD_TEST
- rk30_clkdev_add(lk);
- #else
- clkdev_add(lk);
- #endif
- clk_register(lk->clk);
- }
- clk_recalculate_root_clocks_nolock();
-
- loops_per_jiffy = CLK_LOOPS_RECALC(arm_pll_clk.rate);
-
- /*
- * Only enable those clocks we will need, let the drivers
- * enable other clocks as necessary
- */
- rk30_init_enable_clocks();
-
- /*
- * Disable any unused clocks left on by the bootloader
- */
- //clk_disable_unused();
- rk30_clock_common_init(gpll,cpll);
- preset_lpj = loops_per_jiffy;
-
- //gpio6_b7
- //regfile_writel(0xc0004000,0x10c);
- //cru_writel(0x07000000,CRU_MISC_CON);
-
-}
-int rk_dvfs_init(void);
-
-void __init rk30_clock_data_init(unsigned long gpll,unsigned long cpll,u32 flags)
-{
- _rk30_clock_data_init(gpll,cpll,flags);
- rk_dvfs_init();
-}
-
-/*
- * You can override arm_clk rate with armclk= cmdline option.
- */
-static int __init armclk_setup(char *str)
-{
- get_option(&str, &armclk);
-
- if (!armclk)
- return 0;
- if (armclk < 10000)
- armclk *= MHZ;
- //clk_set_rate_nolock(&arm_pll_clk, armclk);
- return 0;
-}
-#ifndef RK30_CLK_OFFBOARD_TEST
-early_param("armclk", armclk_setup);
-#endif
-
-
-
-#ifdef CONFIG_PROC_FS
-
-static void dump_clock(struct seq_file *s, struct clk *clk, int deep,const struct list_head *root_clocks)
-{
- struct clk* ck;
- int i;
- unsigned long rate = clk->rate;
- //CRU_PRINTK_DBG("dump_clock %s\n",clk->name);
- for (i = 0; i < deep; i++)
- seq_printf(s, " ");
-
- seq_printf(s, "%-11s ", clk->name);
-#ifndef RK30_CLK_OFFBOARD_TEST
- if (clk->flags & IS_PD) {
- seq_printf(s, "%s ", pmu_power_domain_is_on(clk->gate_idx) ? "on " : "off");
- }
-#endif
- if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
- int idx = clk->gate_idx;
- u32 v;
- v = cru_readl(CLK_GATE_CLKID_CONS(idx))&((0x1)<<(idx%16));
- seq_printf(s, "%s ", v ? "off" : "on ");
- }
-
- if (clk->pll)
- {
- u32 pll_mode;
- u32 pll_id=clk->pll->id;
- pll_mode=cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id);
- if (pll_mode == (PLL_MODE_SLOW(pll_id) & PLL_MODE_MSK(pll_id)))
- seq_printf(s, "slow ");
- else if (pll_mode == (PLL_MODE_NORM(pll_id) & PLL_MODE_MSK(pll_id)))
- seq_printf(s, "normal ");
- else if (pll_mode == (PLL_MODE_DEEP(pll_id) & PLL_MODE_MSK(pll_id)))
- seq_printf(s, "deep ");
-
- if(cru_readl(PLL_CONS(pll_id,3)) & PLL_BYPASS)
- seq_printf(s, "bypass ");
- }
- else if(clk == &clk_ddr) {
- rate = clk->recalc(clk);
- }
-
- if (rate >= MHZ) {
- if (rate % MHZ)
- seq_printf(s, "%ld.%06ld MHz", rate / MHZ, rate % MHZ);
- else
- seq_printf(s, "%ld MHz", rate / MHZ);
- } else if (rate >= KHZ) {
- if (rate % KHZ)
- seq_printf(s, "%ld.%03ld KHz", rate / KHZ, rate % KHZ);
- else
- seq_printf(s, "%ld KHz", rate / KHZ);
- } else {
- seq_printf(s, "%ld Hz", rate);
- }
-
- seq_printf(s, " usecount = %d", clk->usecount);
-
- if (clk->parent)
- seq_printf(s, " parent = %s", clk->parent->name);
-
- seq_printf(s, "\n");
-
- list_for_each_entry(ck, root_clocks, node) {
- if (ck->parent == clk)
- dump_clock(s, ck, deep + 1,root_clocks);
- }
-}
-
-static void dump_regs(struct seq_file *s)
-{
- int i=0;
- seq_printf(s, "\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
- seq_printf(s, "\nPLLRegisters:\n");
- for(i=0;i<END_PLL_ID;i++)
- {
- seq_printf(s,"pll%d :cons:%x,%x,%x,%x\n",i,
- cru_readl(PLL_CONS(i,0)),
- cru_readl(PLL_CONS(i,1)),
- cru_readl(PLL_CONS(i,2)),
- cru_readl(PLL_CONS(i,3))
- );
- }
- seq_printf(s, "MODE :%x\n", cru_readl(CRU_MODE_CON));
-
- for(i=0;i<CRU_CLKSELS_CON_CNT;i++)
- {
- seq_printf(s,"CLKSEL%d :%x\n",i,cru_readl(CRU_CLKSELS_CON(i)));
- }
- for(i=0;i<CRU_CLKGATES_CON_CNT;i++)
- {
- seq_printf(s,"CLKGATE%d :%x\n",i,cru_readl(CRU_CLKGATES_CON(i)));
- }
- seq_printf(s,"GLB_SRST_FST:%x\n",cru_readl(CRU_GLB_SRST_FST));
- seq_printf(s,"GLB_SRST_SND:%x\n",cru_readl(CRU_GLB_SRST_SND));
-
- for(i=0;i<CRU_SOFTRSTS_CON_CNT;i++)
- {
- seq_printf(s,"CLKGATE%d :%x\n",i,cru_readl(CRU_SOFTRSTS_CON(i)));
- }
- seq_printf(s,"CRU MISC :%x\n",cru_readl(CRU_MISC_CON));
- seq_printf(s,"GLB_CNT_TH :%x\n",cru_readl(CRU_GLB_CNT_TH));
-
-}
-
-void rk30_clk_dump_regs(void)
-{
- int i=0;
- printk("\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
- printk("\nPLLRegisters:\n");
- for(i=0;i<END_PLL_ID;i++)
- {
- printk("pll%d :cons:%x,%x,%x,%x\n",i,
- cru_readl(PLL_CONS(i,0)),
- cru_readl(PLL_CONS(i,1)),
- cru_readl(PLL_CONS(i,2)),
- cru_readl(PLL_CONS(i,3))
- );
- }
- printk("MODE :%x\n", cru_readl(CRU_MODE_CON));
-
- for(i=0;i<CRU_CLKSELS_CON_CNT;i++)
- {
- printk("CLKSEL%d :%x\n",i,cru_readl(CRU_CLKSELS_CON(i)));
- }
- for(i=0;i<CRU_CLKGATES_CON_CNT;i++)
- {
- printk("CLKGATE%d :%x\n",i,cru_readl(CRU_CLKGATES_CON(i)));
- }
- printk("GLB_SRST_FST:%x\n",cru_readl(CRU_GLB_SRST_FST));
- printk("GLB_SRST_SND:%x\n",cru_readl(CRU_GLB_SRST_SND));
-
- for(i=0;i<CRU_SOFTRSTS_CON_CNT;i++)
- {
- printk("SOFTRST%d :%x\n",i,cru_readl(CRU_SOFTRSTS_CON(i)));
- }
- printk("CRU MISC :%x\n",cru_readl(CRU_MISC_CON));
- printk("GLB_CNT_TH :%x\n",cru_readl(CRU_GLB_CNT_TH));
-
-}
-
-
-#ifdef CONFIG_PROC_FS
-static void dump_clock(struct seq_file *s, struct clk *clk, int deep,const struct list_head *root_clocks);
-struct clk_dump_ops dump_ops={
- .dump_clk=dump_clock,
- .dump_regs=dump_regs,
-};
-#endif
-
-
-#endif /* CONFIG_PROC_FS */
-
-
-
-
-#ifdef RK30_CLK_OFFBOARD_TEST
-struct clk *test_get_parent(struct clk *clk)
-{
- return clk->parent;
-}
-
-void i2s_test(void)
-{
- struct clk *i2s_clk=&clk_i2s0;
-
- clk_enable_nolock(i2s_clk);
-
- clk_set_rate_nolock(i2s_clk, 12288000);
- printk("int %s parent is %s\n",i2s_clk->name,test_get_parent(i2s_clk)->name);
- clk_set_rate_nolock(i2s_clk, 297*MHZ/2);
- printk("int%s parent is %s\n",i2s_clk->name,test_get_parent(i2s_clk)->name);
- clk_set_rate_nolock(i2s_clk, 12*MHZ);
- printk("int%s parent is %s\n",i2s_clk->name,test_get_parent(i2s_clk)->name);
-
-}
-
-void uart_test(void)
-{
- struct clk *uart_clk=&clk_uart0;
-
- clk_enable_nolock(uart_clk);
-
- clk_set_rate_nolock(uart_clk, 12288000);
- printk("int %s parent is %s\n",uart_clk->name,test_get_parent(uart_clk)->name);
- clk_set_rate_nolock(uart_clk, 297*MHZ/2);
- printk("int%s parent is %s\n",uart_clk->name,test_get_parent(uart_clk)->name);
- clk_set_rate_nolock(uart_clk, 12*MHZ);
- printk("int%s parent is %s\n",uart_clk->name,test_get_parent(uart_clk)->name);
-
-}
-void hsadc_test(void)
-{
- struct clk *hsadc_clk=&clk_hsadc;
-
- printk("******************hsadc_test**********************\n");
- clk_enable_nolock(hsadc_clk);
-
- clk_set_rate_nolock(hsadc_clk, 12288000);
- printk("****end %s parent is %s\n",hsadc_clk->name,test_get_parent(hsadc_clk)->name);
-
-
- clk_set_rate_nolock(hsadc_clk, 297*MHZ/2);
- printk("****end %s parent is %s\n",hsadc_clk->name,test_get_parent(hsadc_clk)->name);
-
- clk_set_rate_nolock(hsadc_clk, 300*MHZ/2);
-
- clk_set_rate_nolock(hsadc_clk, 296*MHZ/2);
-
- printk("******************hsadc out clock**********************\n");
-
- clk_set_parent_nolock(hsadc_clk, &clk_hsadc_ext);
- printk("****end %s parent is %s\n",hsadc_clk->name,test_get_parent(hsadc_clk)->name);
- clk_set_rate_nolock(hsadc_clk, 297*MHZ/2);
- printk("****end %s parent is %s\n",hsadc_clk->name,test_get_parent(hsadc_clk)->name);
-
-
-
-}
-
-static void __init rk30_clock_test_init(unsigned long ppll_rate)
-{
- //arm
- printk("*********arm_pll_clk***********\n");
- clk_set_rate_nolock(&arm_pll_clk, 816*MHZ);
-
- printk("*********set clk_cpu parent***********\n");
- clk_set_parent_nolock(&clk_cpu, &arm_pll_clk);
- clk_set_rate_nolock(&clk_cpu, 504*MHZ);
-
- //general
- printk("*********general_pll_clk***********\n");
- clk_set_rate_nolock(&general_pll_clk, ppll_rate);
-
- //code pll
- printk("*********codec_pll_clk***********\n");
- clk_set_rate_nolock(&codec_pll_clk, 600*MHZ);
-
-
- printk("*********periph_clk_set_init***********\n");
- clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
- periph_clk_set_init();
-
- #if 0 //
- clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
- #else
- printk("*********clk i2s***********\n");
- clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
- printk("common %s parent is %s\n",clk_i2s_pll.name,test_get_parent(&clk_i2s_pll)->name);
- i2s_test();
- #endif
-// spi
- clk_enable_nolock(&clk_spi0);
- clk_set_rate_nolock(&clk_spi0, 30*MHZ);
- printk("common %s parent is %s\n",clk_spi0.name,test_get_parent(&clk_spi0)->name);
-//saradc
- clk_enable_nolock(&clk_saradc);
- clk_set_rate_nolock(&clk_saradc, 6*MHZ);
- printk("common %s parent is %s\n",clk_saradc.name,test_get_parent(&clk_saradc)->name);
-//sdio
- clk_enable_nolock(&clk_sdio);
- clk_set_rate_nolock(&clk_sdio, 50*MHZ);
- printk("common %s parent is %s\n",clk_sdio.name,test_get_parent(&clk_sdio)->name);
-// uart
- clk_set_parent_nolock(&clk_uart_pll, &general_pll_clk);
- uart_test();
-//mac
- printk("*********mac***********\n");
-
- clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
- printk("common %s parent is %s\n",clk_mac_pll_div.name,test_get_parent(&clk_mac_pll_div)->name);
-
- //clk_set_parent_nolock(&clk_mac_ref, &clk_mac_pll_div);
- clk_set_rate_nolock(&clk_mac_ref, 50*MHZ);
- printk("common %s parent is %s\n",clk_mac_ref.name,test_get_parent(&clk_mac_ref)->name);
-
- printk("*********mac mii set***********\n");
- clk_set_parent_nolock(&clk_mac_ref, &rmii_clkin);
- clk_set_rate_nolock(&clk_mac_ref, 20*MHZ);
- printk("common %s parent is %s\n",clk_mac_ref.name,test_get_parent(&clk_mac_ref)->name);
-//hsadc
- printk("*********hsadc 1***********\n");
- //auto pll
- hsadc_test();
-//lcdc
- clk_enable_nolock(&dclk_lcdc0);
-
- clk_set_rate_nolock(&dclk_lcdc0, 60*MHZ);
- clk_set_rate_nolock(&dclk_lcdc0, 27*MHZ);
-
-//cif
- clk_enable_nolock(&cif0_out);
-
- clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
- printk("common %s parent is %s\n",cif_out_pll.name,test_get_parent(&cif_out_pll)->name);
-
- clk_set_rate_nolock(&cif0_out, 60*MHZ);
- printk("common %s parent is %s\n",cif0_out.name,test_get_parent(&cif0_out)->name);
-
- clk_set_rate_nolock(&cif0_out, 24*MHZ);
- printk("common %s parent is %s\n",cif0_out.name,test_get_parent(&cif0_out)->name);
-//cif_in
- clk_enable_nolock(&cif0_in);
- clk_set_rate_nolock(&cif0_in, 24*MHZ);
-//axi lcdc
- clk_enable_nolock(&aclk_lcdc0);
- clk_set_rate_nolock(&aclk_lcdc0, 150*MHZ);
- printk("common %s parent is %s\n",aclk_lcdc0.name,test_get_parent(&aclk_lcdc0)->name);
-//axi vepu
- clk_enable_nolock(&aclk_vepu);
- clk_set_rate_nolock(&aclk_vepu, 300*MHZ);
- printk("common %s parent is %s\n",aclk_vepu.name,test_get_parent(&aclk_vepu)->name);
-
- clk_set_rate_nolock(&hclk_vepu, 300*MHZ);
- printk("common %s parent is %s\n",hclk_vepu.name,test_get_parent(&hclk_vepu)->name);
-
- printk("test end\n");
-
- /* arm pll
- clk_set_rate_nolock(&arm_pll_clk, armclk);
- clk_set_rate_nolock(&clk_cpu, armclk);//pll:core =1:1
- */
- //
- //clk_set_rate_nolock(&codec_pll_clk, ppll_rate*2);
- //
- //clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
- //clk_set_rate_nolock(&clk_gpu, 300 * MHZ);
-
-}
-
-
-
-
-
-static LIST_HEAD(rk30_clocks);
-static DEFINE_MUTEX(rk30_clocks_mutex);
-
-static inline int __rk30clk_get(struct clk *clk)
-{
- return 1;
-}
-void rk30_clkdev_add(struct clk_lookup *cl)
-{
- mutex_lock(&rk30_clocks_mutex);
- list_add_tail(&cl->node, &rk30_clocks);
- mutex_unlock(&rk30_clocks_mutex);
-}
-static struct clk_lookup *rk30_clk_find(const char *dev_id, const char *con_id)
-{
- struct clk_lookup *p, *cl = NULL;
- int match, best = 0;
-
- list_for_each_entry(p, &rk30_clocks, node) {
- match = 0;
- if (p->dev_id) {
- if (!dev_id || strcmp(p->dev_id, dev_id))
- continue;
- match += 2;
- }
- if (p->con_id) {
- if (!con_id || strcmp(p->con_id, con_id))
- continue;
- match += 1;
- }
-
- if (match > best) {
- cl = p;
- if (match != 3)
- best = match;
- else
- break;
- }
- }
- return cl;
-}
-
-struct clk *rk30_clk_get_sys(const char *dev_id, const char *con_id)
-{
- struct clk_lookup *cl;
-
- mutex_lock(&rk30_clocks_mutex);
- cl = rk30_clk_find(dev_id, con_id);
- if (cl && !__rk30clk_get(cl->clk))
- cl = NULL;
- mutex_unlock(&rk30_clocks_mutex);
-
- return cl ? cl->clk : ERR_PTR(-ENOENT);
-}
-//EXPORT_SYMBOL(rk30_clk_get_sys);
-
-struct clk *rk30_clk_get(struct device *dev, const char *con_id)
-{
- const char *dev_id = dev ? dev_name(dev) : NULL;
- return rk30_clk_get_sys(dev_id, con_id);
-}
-//EXPORT_SYMBOL(rk30_clk_get);
-
-
-int rk30_clk_set_rate(struct clk *clk, unsigned long rate);
-
-void rk30_clocks_test(void)
-{
- struct clk *test_gpll;
- test_gpll=rk30_clk_get(NULL,"general_pll");
- if(test_gpll)
- {
- rk30_clk_set_rate(test_gpll,297*2*MHZ);
- printk("gpll rate=%lu\n",test_gpll->rate);
- }
- //while(1);
-}
-
-void __init rk30_clock_init_test(void){
-
- rk30_clock_init(periph_pll_297mhz,codec_pll_360mhz,max_i2s_12288khz);
- //while(1);
-}
-
-
-#endif
-
-
+++ /dev/null
-#include <linux/clk.h>
-#include <linux/cpufreq.h>
-#include <linux/err.h>
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-
-#include <asm/pgtable-hwdef.h>
-#include <asm/hardware/gic.h>
-#include <asm/mach/arch.h>
-#include <asm/hardware/cache-l2x0.h>
-
-#include <plat/sram.h>
-#include <mach/board.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <mach/fiq.h>
-#include <mach/pmu.h>
-#include <mach/loader.h>
-#include <mach/ddr.h>
-#include <mach/dvfs.h>
-#include <mach/cpu_axi.h>
-#include <mach/debug_uart.h>
-
-static void __init rk30_cpu_axi_init(void)
-{
- CPU_AXI_SET_QOS_PRIORITY(0, 0, DMAC);
- CPU_AXI_SET_QOS_PRIORITY(0, 0, CPU0);
- CPU_AXI_SET_QOS_PRIORITY(0, 0, CPU1R);
- CPU_AXI_SET_QOS_PRIORITY(0, 0, CPU1W);
-#ifdef CONFIG_RK29_VMAC
- CPU_AXI_SET_QOS_PRIORITY(2, 2, PERI);
-#else
- CPU_AXI_SET_QOS_PRIORITY(0, 0, PERI);
-#endif
- CPU_AXI_SET_QOS_PRIORITY(3, 3, LCDC0);
- CPU_AXI_SET_QOS_PRIORITY(3, 3, LCDC1);
- CPU_AXI_SET_QOS_PRIORITY(2, 1, GPU);
-
- writel_relaxed(0x3f, RK30_CPU_AXI_BUS_BASE + 0x0014); // memory scheduler read latency
- dsb();
-}
-
-#define L2_LY_SP_OFF (0)
-#define L2_LY_SP_MSK (0x7)
-
-#define L2_LY_RD_OFF (4)
-#define L2_LY_RD_MSK (0x7)
-
-#define L2_LY_WR_OFF (8)
-#define L2_LY_WR_MSK (0x7)
-#define L2_LY_SET(ly,off) (((ly)-1)<<(off))
-
-#define L2_LATENCY(setup_cycles, read_cycles, write_cycles) \
- L2_LY_SET(setup_cycles, L2_LY_SP_OFF) | \
- L2_LY_SET(read_cycles, L2_LY_RD_OFF) | \
- L2_LY_SET(write_cycles, L2_LY_WR_OFF)
-
-static void __init rk30_l2_cache_init(void)
-{
-#ifdef CONFIG_CACHE_L2X0
- u32 aux_ctrl, aux_ctrl_mask, data_latency_ctrl;
-#if defined(CONFIG_ARCH_RK3188) || defined(CONFIG_ARCH_RK319X)
- data_latency_ctrl = L2_LATENCY(2, 3, 1);
-#else
- unsigned int max_cpu_freq = 1608000; // kHz
- struct cpufreq_frequency_table *table = NULL;
- struct clk *clk_cpu;
- int i;
-
- clk_cpu = clk_get(NULL, "cpu");
- if (!IS_ERR(clk_cpu)) {
- table = dvfs_get_freq_volt_table(clk_cpu);
- if (!table)
- pr_err("failed to get cpu freq volt table\n");
- } else
- pr_err("failed to get clk cpu\n");
- for (i = 0; table && table[i].frequency != CPUFREQ_TABLE_END; i++) {
- if (max_cpu_freq < table[i].frequency)
- max_cpu_freq = table[i].frequency;
- }
-
- if (max_cpu_freq <= 1608000)
- data_latency_ctrl = L2_LATENCY(4, 6, 1);
- else if (max_cpu_freq <= 1800000)
- data_latency_ctrl = L2_LATENCY(5, 7, 1);
- else if (max_cpu_freq <= 1992000)
- data_latency_ctrl = L2_LATENCY(5, 8, 1);
- else
- data_latency_ctrl = L2_LATENCY(6, 8, 1);
-#endif
-
- writel_relaxed(L2_LATENCY(1, 1, 1), RK30_L2C_BASE + L2X0_TAG_LATENCY_CTRL);
- writel_relaxed(data_latency_ctrl, RK30_L2C_BASE + L2X0_DATA_LATENCY_CTRL);
-
- /* L2X0 Prefetch Control */
- writel_relaxed(0x70000003, RK30_L2C_BASE + L2X0_PREFETCH_CTRL);
-
- /* L2X0 Power Control */
- writel_relaxed(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, RK30_L2C_BASE + L2X0_POWER_CTRL);
-
- aux_ctrl = (
- (0x1 << 25) | // round-robin
- (0x1 << 0) | // Full Line of Zero Enable
- (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
- (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
- (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
- (0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT) );
-
- aux_ctrl_mask = ~(
- (0x1 << 25) | // round-robin
- (0x1 << 0) | // Full Line of Zero Enable
- (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
- (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
- (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
- (0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT) );
-
- l2x0_init(RK30_L2C_BASE, aux_ctrl, aux_ctrl_mask);
-#endif
-}
-
-static int boot_mode;
-
-static void __init rk30_boot_mode_init(void)
-{
- u32 boot_flag = readl_relaxed(RK30_PMU_BASE + PMU_SYS_REG0);
- boot_mode = readl_relaxed(RK30_PMU_BASE + PMU_SYS_REG1);
-
- if (boot_flag == (SYS_KERNRL_REBOOT_FLAG | BOOT_RECOVER)) {
- boot_mode = BOOT_MODE_RECOVERY;
- }
- if (boot_mode || ((boot_flag & 0xff) && ((boot_flag & 0xffffff00) == SYS_KERNRL_REBOOT_FLAG)))
- printk("Boot mode: %s (%d) flag: %s (0x%08x)\n", boot_mode_name(boot_mode), boot_mode, boot_flag_name(boot_flag), boot_flag);
-#ifdef CONFIG_RK29_WATCHDOG
- writel_relaxed(BOOT_MODE_WATCHDOG, RK30_PMU_BASE + PMU_SYS_REG1);
-#endif
-}
-
-int board_boot_mode(void)
-{
- return boot_mode;
-}
-EXPORT_SYMBOL(board_boot_mode);
-
-void __init rk30_init_irq(void)
-{
- gic_init(0, IRQ_LOCALTIMER, RK30_GICD_BASE, RK30_GICC_BASE);
-#ifdef CONFIG_FIQ
- rk_fiq_init();
-#endif
- rk30_gpio_init();
-}
-
-static void usb_uart_init(void)
-{
-#if defined(CONFIG_ARCH_RK3188) && (CONFIG_RK_DEBUG_UART == 2)
-#ifdef CONFIG_RK_USB_UART
- if (!(readl_relaxed(RK30_GRF_BASE + GRF_SOC_STATUS0) & (1 << 13))) { //detect id
- writel_relaxed((0x0300 << 16), RK30_GRF_BASE + GRF_UOC0_CON0);
- } else {
- if (!(readl_relaxed(RK30_GRF_BASE + GRF_SOC_STATUS0) & (1 << 10))) { //detect vbus
- writel_relaxed(((0x01 << 2) | ((0x01 << 2) << 16)), RK30_GRF_BASE + GRF_UOC0_CON2); //software control usb phy enable
- writel_relaxed((0x2A | (0x3F << 16)), RK30_GRF_BASE + GRF_UOC0_CON3); //usb phy enter suspend
- writel_relaxed((0x0300 | (0x0300 << 16)), RK30_GRF_BASE + GRF_UOC0_CON0);
- } else {
- writel_relaxed((0x0300 << 16), RK30_GRF_BASE + GRF_UOC0_CON0);
- }
- }
-#else
- writel_relaxed((0x0300 << 16), RK30_GRF_BASE + GRF_UOC0_CON0);
-#endif
-#endif
-}
-
-void __init rk30_map_io(void)
-{
- rk30_map_common_io();
- usb_uart_init();
- rk29_setup_early_printk();
- rk30_cpu_axi_init();
- rk29_sram_init();
- board_clock_init();
- rk30_l2_cache_init();
- ddr_init(DDR_TYPE, DDR_FREQ);
- clk_disable_unused();
- rk30_iomux_init();
- rk30_boot_mode_init();
-#if defined(CONFIG_EMMC_IO_3_3V)
- grf_set_io_power_domain_voltage(IO_PD_FLASH, IO_PD_VOLTAGE_3_3V);
-#endif
-}
-
-static __init u32 rk30_get_ddr_size(void)
-{
- u32 size;
- u32 v[3], a[3];
- u32 pgtbl = PAGE_OFFSET + TEXT_OFFSET - 0x4000;
- u32 flag = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ;
-
- a[0] = pgtbl + (((u32)RK30_CPU_AXI_BUS_BASE >> 20) << 2);
- a[1] = pgtbl + (((u32)RK30_DDR_PUBL_BASE >> 20) << 2);
- a[2] = pgtbl + (((u32)RK30_GRF_BASE >> 20) << 2);
- v[0] = readl_relaxed(a[0]);
- v[1] = readl_relaxed(a[1]);
- v[2] = readl_relaxed(a[2]);
- writel_relaxed(flag | ((RK30_CPU_AXI_BUS_PHYS >> 20) << 20), a[0]);
- writel_relaxed(flag | ((RK30_DDR_PUBL_PHYS >> 20) << 20), a[1]);
- writel_relaxed(flag | ((RK30_GRF_PHYS >> 20) << 20), a[2]);
-
- size = ddr_get_cap();
-
- writel_relaxed(v[0], a[0]);
- writel_relaxed(v[1], a[1]);
- writel_relaxed(v[2], a[2]);
-
- return size;
-}
-
-void __init rk30_fixup(struct machine_desc *desc, struct tag *tags,
- char **cmdline, struct meminfo *mi)
-{
- mi->nr_banks = 1;
- mi->bank[0].start = PLAT_PHYS_OFFSET;
- mi->bank[0].size = rk30_get_ddr_size();
-}
-
+++ /dev/null
-/*
- * Copyright (C) 2012-2013 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-//#define DEBUG 1
-#define pr_fmt(fmt) "cpufreq: " fmt
-#include <linux/clk.h>
-#include <linux/cpufreq.h>
-#include <linux/err.h>
-#include <linux/kernel_stat.h>
-#include <linux/init.h>
-#include <linux/reboot.h>
-#include <linux/suspend.h>
-#include <linux/tick.h>
-#include <linux/workqueue.h>
-#include <asm/smp_plat.h>
-#include <asm/cpu.h>
-#include <mach/dvfs.h>
-#include <linux/delay.h>
-#include <linux/regulator/consumer.h>
-#include <linux/fs.h>
-#include <linux/miscdevice.h>
-#include <linux/string.h>
-#include <linux/earlysuspend.h>
-#include <asm/unistd.h>
-#include <asm/uaccess.h>
-#include <mach/ddr.h>
-#include <linux/cpu.h>
-#ifdef DEBUG
-#define FREQ_PRINTK_DBG(fmt, args...) pr_debug(fmt, ## args)
-#define FREQ_PRINTK_LOG(fmt, args...) pr_debug(fmt, ## args)
-#else
-#define FREQ_PRINTK_DBG(fmt, args...) do {} while(0)
-#define FREQ_PRINTK_LOG(fmt, args...) do {} while(0)
-#endif
-#define FREQ_PRINTK_ERR(fmt, args...) pr_err(fmt, ## args)
-
-/* Frequency table index must be sequential starting at 0 */
-static struct cpufreq_frequency_table default_freq_table[] = {
- {.frequency = 816 * 1000, .index = 1100 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table *freq_table = default_freq_table;
-static unsigned int max_freq = -1;
-
-/*********************************************************/
-
-/* additional symantics for "relation" in cpufreq with pm */
-#define DISABLE_FURTHER_CPUFREQ 0x10
-#define ENABLE_FURTHER_CPUFREQ 0x20
-#define MASK_FURTHER_CPUFREQ 0x30
-/* With 0x00(NOCHANGE), it depends on the previous "further" status */
-#define CPUFREQ_PRIVATE 0x100
-static int no_cpufreq_access;
-static unsigned int suspend_freq = 816 * 1000;
-
-static struct workqueue_struct *freq_wq;
-static struct clk *cpu_clk;
-static struct clk *cpu_pll;
-static struct clk *cpu_gpll;
-
-
-static DEFINE_MUTEX(cpufreq_mutex);
-
-static struct clk *gpu_clk;
-static struct clk *ddr_clk;
-#if !defined(CONFIG_ARCH_RK3066B) && !defined(CONFIG_ARCH_RK3188)
-#define GPU_MAX_RATE 350*1000*1000
-#endif
-
-static int cpufreq_scale_rate_for_dvfs(struct clk *clk, unsigned long rate, dvfs_set_rate_callback set_rate);
-
-/*******************************************************/
-static unsigned int rk30_getspeed(unsigned int cpu)
-{
- unsigned long rate;
-
- if (cpu >= NR_CPUS)
- return 0;
-
- rate = clk_get_rate(cpu_clk) / 1000;
- return rate;
-}
-
-static bool rk30_cpufreq_is_ondemand_policy(struct cpufreq_policy *policy)
-{
- char c = 0;
- if (policy && policy->governor)
- c = policy->governor->name[0];
- return (c == 'o' || c == 'i' || c == 'c' || c == 'h');
-}
-
-/**********************thermal limit**************************/
-#if !defined(CONFIG_ARCH_RK3066B) && !defined(CONFIG_ARCH_RK3188)
-#define CONFIG_RK30_CPU_FREQ_LIMIT_BY_TEMP
-#endif
-
-#ifdef CONFIG_RK30_CPU_FREQ_LIMIT_BY_TEMP
-static void rk30_cpufreq_temp_limit_work_func(struct work_struct *work);
-
-static DECLARE_DELAYED_WORK(rk30_cpufreq_temp_limit_work, rk30_cpufreq_temp_limit_work_func);
-
-static unsigned int temp_limt_freq = -1;
-module_param(temp_limt_freq, uint, 0444);
-
-#define TEMP_LIMIT_FREQ 816000
-
-static const struct cpufreq_frequency_table temp_limits[] = {
- {.frequency = 1416 * 1000, .index = 50},
- {.frequency = 1200 * 1000, .index = 55},
- {.frequency = 1008 * 1000, .index = 60},
- {.frequency = 816 * 1000, .index = 75},
-};
-
-static const struct cpufreq_frequency_table temp_limits_high[] = {
- {.frequency = 816 * 1000, .index = 100},
-};
-
-extern int rk30_tsadc_get_temp(unsigned int chn);
-
-static char sys_state;
-static ssize_t sys_state_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
-{
- char state;
-
- if (count < 1)
- return count;
- if (copy_from_user(&state, buffer, 1)) {
- return -EFAULT;
- }
-
- sys_state = state;
- return count;
-}
-
-static const struct file_operations sys_state_fops = {
- .owner = THIS_MODULE,
- .write = sys_state_write,
-};
-
-static struct miscdevice sys_state_dev = {
- .fops = &sys_state_fops,
- .name = "sys_state",
- .minor = MISC_DYNAMIC_MINOR,
-};
-
-static void rk30_cpufreq_temp_limit_work_func(struct work_struct *work)
-{
- struct cpufreq_policy *policy;
- int temp, i;
- unsigned int new = -1;
- unsigned long delay = HZ;
- const struct cpufreq_frequency_table *limits_table = temp_limits;
- size_t limits_size = ARRAY_SIZE(temp_limits);
- unsigned int gpu_irqs[2];
- gpu_irqs[0] = kstat_irqs(IRQ_GPU_GP);
-
- temp = rk30_tsadc_get_temp(0);
- FREQ_PRINTK_LOG("cpu_thermal(%d)\n", temp);
-
- gpu_irqs[1] = kstat_irqs(IRQ_GPU_GP);
- if (sys_state == '1' || clk_get_rate(gpu_clk) > GPU_MAX_RATE) {
- delay = HZ / 20;
- if ((gpu_irqs[1] - gpu_irqs[0]) < 3) {
- limits_table = temp_limits_high;
- limits_size = ARRAY_SIZE(temp_limits_high);
- }
- }
- for (i = 0; i < limits_size; i++) {
- if (temp > limits_table[i].index) {
- new = limits_table[i].frequency;
- }
- }
- if (temp_limt_freq != new) {
- temp_limt_freq = new;
- FREQ_PRINTK_DBG("temp_limit set rate %d kHz\n", temp_limt_freq);
- policy = cpufreq_cpu_get(0);
- cpufreq_driver_target(policy, policy->cur, CPUFREQ_RELATION_L | CPUFREQ_PRIVATE);
- cpufreq_cpu_put(policy);
- }
-
- queue_delayed_work(freq_wq, &rk30_cpufreq_temp_limit_work, delay);
-}
-
-static int rk30_cpufreq_notifier_policy(struct notifier_block *nb,
- unsigned long val, void *data)
-{
- struct cpufreq_policy *policy = data;
-
- if (val != CPUFREQ_NOTIFY)
- return 0;
-
- if (rk30_cpufreq_is_ondemand_policy(policy)) {
- FREQ_PRINTK_DBG("queue work\n");
- queue_delayed_work(freq_wq, &rk30_cpufreq_temp_limit_work, 0);
- } else {
- FREQ_PRINTK_DBG("cancel work\n");
- cancel_delayed_work_sync(&rk30_cpufreq_temp_limit_work);
- }
-
- return 0;
-}
-
-static struct notifier_block notifier_policy_block = {
- .notifier_call = rk30_cpufreq_notifier_policy
-};
-#endif
-
-/************************************dvfs tst************************************/
-//#define CPU_FREQ_DVFS_TST
-#ifdef CPU_FREQ_DVFS_TST
-static unsigned int freq_dvfs_tst_rate;
-static void rk30_cpufreq_dvsf_tst_work_func(struct work_struct *work);
-static DECLARE_DELAYED_WORK(rk30_cpufreq_dvsf_tst_work, rk30_cpufreq_dvsf_tst_work_func);
-static int test_count;
-#define TEST_FRE_NUM 11
-static int test_tlb_rate[TEST_FRE_NUM] = { 504, 1008, 504, 1200, 252, 816, 1416, 252, 1512, 252, 816 };
-//static int test_tlb_rate[TEST_FRE_NUM]={504,1008,504,1200,252,816,1416,126,1512,126,816};
-
-#define TEST_GPU_NUM 3
-
-static int test_tlb_gpu[TEST_GPU_NUM] = { 360, 400, 180 };
-static int test_tlb_ddr[TEST_GPU_NUM] = { 401, 200, 500 };
-
-static int gpu_ddr = 0;
-
-static void rk30_cpufreq_dvsf_tst_work_func(struct work_struct *work)
-{
- struct cpufreq_policy *policy = cpufreq_cpu_get(0);
-
- gpu_ddr++;
-
-#if 0
- FREQ_PRINTK_LOG("cpufreq_dvsf_tst,ddr%u,gpu%u\n",
- test_tlb_ddr[gpu_ddr % TEST_GPU_NUM],
- test_tlb_gpu[gpu_ddr % TEST_GPU_NUM]);
- clk_set_rate(ddr_clk, test_tlb_ddr[gpu_ddr % TEST_GPU_NUM] * 1000 * 1000);
- clk_set_rate(gpu_clk, test_tlb_gpu[gpu_ddr % TEST_GPU_NUM] * 1000 * 1000);
-#endif
-
- test_count++;
- freq_dvfs_tst_rate = test_tlb_rate[test_count % TEST_FRE_NUM] * 1000;
- FREQ_PRINTK_LOG("cpufreq_dvsf_tst,cpu set rate %d\n", freq_dvfs_tst_rate);
- cpufreq_driver_target(policy, policy->cur, CPUFREQ_RELATION_L);
- cpufreq_cpu_put(policy);
-
- queue_delayed_work(freq_wq, &rk30_cpufreq_dvsf_tst_work, msecs_to_jiffies(1000));
-}
-#endif /* CPU_FREQ_DVFS_TST */
-
-/***********************************************************************/
-static int rk30_verify_speed(struct cpufreq_policy *policy)
-{
- if (!freq_table)
- return -EINVAL;
- return cpufreq_frequency_table_verify(policy, freq_table);
-}
-static int rk30_cpu_init(struct cpufreq_policy *policy)
-{
- if (policy->cpu == 0) {
- int i;
-
- gpu_clk = clk_get(NULL, "gpu");
- if (!IS_ERR(gpu_clk))
- clk_enable_dvfs(gpu_clk);
-
- ddr_clk = clk_get(NULL, "ddr");
- if (!IS_ERR(ddr_clk))
- clk_enable_dvfs(ddr_clk);
-
- cpu_clk = clk_get(NULL, "cpu");
-
- cpu_pll = clk_get(NULL, "arm_pll");
-
- cpu_gpll = clk_get(NULL, "arm_gpll");
- if (IS_ERR(cpu_clk))
- return PTR_ERR(cpu_clk);
-
- dvfs_clk_register_set_rate_callback(cpu_clk, cpufreq_scale_rate_for_dvfs);
- freq_table = dvfs_get_freq_volt_table(cpu_clk);
- if (freq_table == NULL) {
- freq_table = default_freq_table;
- }
- max_freq = freq_table[0].frequency;
- for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
- max_freq = max(max_freq, freq_table[i].frequency);
- }
- clk_enable_dvfs(cpu_clk);
-
-#if !defined(CONFIG_ARCH_RK3066B)
-#if defined(CONFIG_ARCH_RK30)
- /* Limit gpu frequency between 133M to 400M */
- dvfs_clk_enable_limit(gpu_clk, 133000000, 400000000);
-#endif
-#endif
-
- freq_wq = create_singlethread_workqueue("rk30_cpufreqd");
-#ifdef CONFIG_RK30_CPU_FREQ_LIMIT_BY_TEMP
- misc_register(&sys_state_dev);
- if (rk30_cpufreq_is_ondemand_policy(policy)) {
- queue_delayed_work(freq_wq, &rk30_cpufreq_temp_limit_work, 0*HZ);
- }
- cpufreq_register_notifier(¬ifier_policy_block, CPUFREQ_POLICY_NOTIFIER);
-#endif
-#ifdef CPU_FREQ_DVFS_TST
- queue_delayed_work(freq_wq, &rk30_cpufreq_dvsf_tst_work, msecs_to_jiffies(20 * 1000));
-#endif
- }
- //set freq min max
- cpufreq_frequency_table_cpuinfo(policy, freq_table);
- //sys nod
- cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
-
- policy->cur = rk30_getspeed(0);
-
- policy->cpuinfo.transition_latency = 40 * NSEC_PER_USEC; // make ondemand default sampling_rate to 40000
-
- /*
- * On rk30 SMP configuartion, both processors share the voltage
- * and clock. So both CPUs needs to be scaled together and hence
- * needs software co-ordination. Use cpufreq affected_cpus
- * interface to handle this scenario. Additional is_smp() check
- * is to keep SMP_ON_UP build working.
- */
- if (is_smp())
- cpumask_setall(policy->cpus);
-
- return 0;
-}
-
-static int rk30_cpu_exit(struct cpufreq_policy *policy)
-{
- if (policy->cpu != 0)
- return 0;
-
- cpufreq_frequency_table_cpuinfo(policy, freq_table);
- clk_put(cpu_clk);
-#ifdef CONFIG_RK30_CPU_FREQ_LIMIT_BY_TEMP
- cpufreq_unregister_notifier(¬ifier_policy_block, CPUFREQ_POLICY_NOTIFIER);
- if (freq_wq)
- cancel_delayed_work(&rk30_cpufreq_temp_limit_work);
- misc_deregister(&sys_state_dev);
-#endif
- if (freq_wq) {
- flush_workqueue(freq_wq);
- destroy_workqueue(freq_wq);
- freq_wq = NULL;
- }
-
- return 0;
-}
-
-static struct freq_attr *rk30_cpufreq_attr[] = {
- &cpufreq_freq_attr_scaling_available_freqs,
- NULL,
-};
-
-/**************************earlysuspend freeze cpu frequency******************************/
-static struct early_suspend ff_early_suspend;
-
-#define FILE_GOV_MODE "/sys/devices/system/cpu/cpu0/cpufreq/scaling_governor"
-#define FILE_SETSPEED "/sys/devices/system/cpu/cpu0/cpufreq/scaling_setspeed"
-#define FILE_CUR_FREQ "/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq"
-
-#define FF_DEBUG(fmt, args...) printk(KERN_DEBUG "FREEZE FREQ DEBUG:\t"fmt, ##args)
-#define FF_ERROR(fmt, args...) printk(KERN_ERR "FREEZE FREQ ERROR:\t"fmt, ##args)
-
-static int ff_read(char *file_path, char *buf)
-{
- struct file *file = NULL;
- mm_segment_t old_fs;
- loff_t offset = 0;
-
- FF_DEBUG("read %s\n", file_path);
- file = filp_open(file_path, O_RDONLY, 0);
-
- if (IS_ERR(file)) {
- FF_ERROR("%s error open file %s\n", __func__, file_path);
- return -1;
- }
-
- old_fs = get_fs();
- set_fs(KERNEL_DS);
-
- file->f_op->read(file, (char *)buf, 32, &offset);
- sscanf(buf, "%s", buf);
-
- set_fs(old_fs);
- filp_close(file, NULL);
-
- file = NULL;
-
- return 0;
-
-}
-
-static int ff_write(char *file_path, char *buf)
-{
- struct file *file = NULL;
- mm_segment_t old_fs;
- loff_t offset = 0;
-
- FF_DEBUG("write %s %s size = %d\n", file_path, buf, strlen(buf));
- file = filp_open(file_path, O_RDWR, 0);
-
- if (IS_ERR(file)) {
- FF_ERROR("%s error open file %s\n", __func__, file_path);
- return -1;
- }
-
- old_fs = get_fs();
- set_fs(KERNEL_DS);
-
- file->f_op->write(file, (char *)buf, strlen(buf), &offset);
-
- set_fs(old_fs);
- filp_close(file, NULL);
-
- file = NULL;
-
- return 0;
-
-}
-
-static void ff_scale_votlage(char *name, int volt)
-{
- struct regulator* regulator;
- int ret = 0;
-
- FF_DEBUG("enter %s\n", __func__);
- regulator = dvfs_get_regulator(name);
- if (!regulator) {
- FF_ERROR("get regulator %s ERROR\n", name);
- return ;
- }
-
- ret = regulator_set_voltage(regulator, volt, volt);
- if (ret != 0) {
- FF_ERROR("set voltage error %s %d, ret = %d\n", name, volt, ret);
- }
-
-}
-int clk_set_parent_force(struct clk *clk, struct clk *parent);
-static void ff_early_suspend_func(struct early_suspend *h)
-{
- char buf[32];
- FF_DEBUG("enter %s\n", __func__);
- if (ff_read(FILE_GOV_MODE, buf) != 0) {
- FF_ERROR("read current governor error\n");
- return ;
- } else {
- FF_DEBUG("current governor = %s\n", buf);
- }
-
- strcpy(buf, "userspace");
- if (ff_write(FILE_GOV_MODE, buf) != 0) {
- FF_ERROR("set current governor error\n");
- return ;
- }
-
- strcpy(buf, "252000");
- if (ff_write(FILE_SETSPEED, buf) != 0) {
- FF_ERROR("set speed to 252MHz error\n");
- return ;
- }
-
- if (!IS_ERR(cpu_pll)&&!IS_ERR(cpu_gpll)&&!IS_ERR(cpu_clk))
- {
- clk_set_parent_force(cpu_clk,cpu_gpll);
- clk_set_rate(cpu_clk,300*1000*1000);
-
- clk_disable_dvfs(cpu_clk);
- }
- if (!IS_ERR(gpu_clk))
- dvfs_clk_enable_limit(gpu_clk,75*1000*1000,133*1000*1000);
-
- //ff_scale_votlage("vdd_cpu", 1000000);
- //ff_scale_votlage("vdd_core", 1000000);
-#ifdef CONFIG_HOTPLUG_CPU
- cpu_down(1);
-#endif
-}
-
-static void ff_early_resume_func(struct early_suspend *h)
-{
- char buf[32];
- FF_DEBUG("enter %s\n", __func__);
-
- if (!IS_ERR(cpu_pll)&&!IS_ERR(cpu_gpll)&&!IS_ERR(cpu_clk))
- {
- clk_set_parent_force(cpu_clk,cpu_pll);
- clk_set_rate(cpu_clk,300*1000*1000);
- clk_enable_dvfs(cpu_clk);
- }
-
- if (!IS_ERR(gpu_clk))
- dvfs_clk_disable_limit(gpu_clk);
-#ifdef CONFIG_HOTPLUG_CPU
- cpu_up(1);
-#endif
- if (ff_read(FILE_GOV_MODE, buf) != 0) {
- FF_ERROR("read current governor error\n");
- return ;
- } else {
- FF_DEBUG("current governor = %s\n", buf);
- }
-
- if (ff_read(FILE_CUR_FREQ, buf) != 0) {
- FF_ERROR("read current frequency error\n");
- return ;
- } else {
- FF_DEBUG("current frequency = %s\n", buf);
- }
-
- strcpy(buf, "interactive");
- if (ff_write(FILE_GOV_MODE, buf) != 0) {
- FF_ERROR("set current governor error\n");
- return ;
- }
-
- strcpy(buf, "interactive");
- if (ff_write(FILE_GOV_MODE, buf) != 0) {
- FF_ERROR("set current governor error\n");
- return ;
- }
-}
-
-static int __init ff_init(void)
-{
- FF_DEBUG("enter %s\n", __func__);
-#ifdef CONFIG_HAS_EARLYSUSPEND
- ff_early_suspend.suspend = ff_early_suspend_func;
- ff_early_suspend.resume = ff_early_resume_func;
- ff_early_suspend.level = EARLY_SUSPEND_LEVEL_DISABLE_FB + 100;
-#endif
- register_early_suspend(&ff_early_suspend);
- return 0;
-}
-
-static void __exit ff_exit(void)
-{
- FF_DEBUG("enter %s\n", __func__);
- unregister_early_suspend(&ff_early_suspend);
-}
-
-/**************************target freq******************************/
-static unsigned int cpufreq_scale_limt(unsigned int target_freq, struct cpufreq_policy *policy, bool is_private)
-{
- bool is_ondemand = rk30_cpufreq_is_ondemand_policy(policy);
- static bool is_booting = true;
- unsigned int i;
-
- if (!is_ondemand)
- goto out;
-
-#if !defined(CONFIG_ARCH_RK3066B) && !defined(CONFIG_ARCH_RK3188)
- if (is_booting && target_freq >= 1600 * 1000) {
- s64 boottime_ms = ktime_to_ms(ktime_get_boottime());
- if (boottime_ms > 30 * MSEC_PER_SEC) {
- is_booting = false;
- } else {
- target_freq = 1416 * 1000;
- }
- }
-#endif
-
-#ifdef CONFIG_RK30_CPU_FREQ_LIMIT_BY_TEMP
- {
- static unsigned int ondemand_target = TEMP_LIMIT_FREQ;
- if (is_private)
- target_freq = ondemand_target;
- else
- ondemand_target = target_freq;
- }
-
- if (target_freq != policy->max && target_freq > policy->cur && policy->cur >= TEMP_LIMIT_FREQ) {
- if (cpufreq_frequency_table_target(policy, freq_table, policy->cur + 1, CPUFREQ_RELATION_L, &i) == 0) {
- unsigned int f = freq_table[i].frequency;
- if (f < target_freq) {
- target_freq = f;
- }
- }
- }
- /*
- * If the new frequency is more than the thermal max allowed
- * frequency, go ahead and scale the mpu device to proper frequency.
- */
- target_freq = min(target_freq, temp_limt_freq);
-#endif
-out:
-#ifdef CPU_FREQ_DVFS_TST
- if (freq_dvfs_tst_rate) {
- target_freq = freq_dvfs_tst_rate;
- freq_dvfs_tst_rate = 0;
- }
-#endif
- return target_freq;
-}
-
-int cpufreq_scale_rate_for_dvfs(struct clk *clk, unsigned long rate, dvfs_set_rate_callback set_rate)
-{
- unsigned int i;
- int ret = -EINVAL;
- struct cpufreq_freqs freqs;
-
- freqs.new = rate / 1000;
- freqs.old = rk30_getspeed(0);
-
- for_each_online_cpu(freqs.cpu) {
- cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
- }
- FREQ_PRINTK_DBG("cpufreq_scale_rate_for_dvfs(%lu)\n", rate);
- ret = set_rate(clk, rate);
-
-#ifdef CONFIG_SMP
- /*
- * Note that loops_per_jiffy is not updated on SMP systems in
- * cpufreq driver. So, update the per-CPU loops_per_jiffy value
- * on frequency transition. We need to update all dependent CPUs.
- */
- for_each_possible_cpu(i) {
- per_cpu(cpu_data, i).loops_per_jiffy = loops_per_jiffy;
- }
-#endif
-
- freqs.new = rk30_getspeed(0);
- /* notifiers */
- for_each_online_cpu(freqs.cpu) {
- cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
- }
- return ret;
-
-}
-
-static int rk30_target(struct cpufreq_policy *policy, unsigned int target_freq, unsigned int relation)
-{
- unsigned int i, new_rate = 0;
- int ret = 0;
- bool is_private;
-
- if (!freq_table) {
- FREQ_PRINTK_ERR("no freq table!\n");
- return -EINVAL;
- }
-
- mutex_lock(&cpufreq_mutex);
-
- is_private = relation & CPUFREQ_PRIVATE;
- relation &= ~CPUFREQ_PRIVATE;
-
- if (relation & ENABLE_FURTHER_CPUFREQ)
- no_cpufreq_access--;
- if (no_cpufreq_access) {
-#ifdef CONFIG_PM_VERBOSE
- pr_err("denied access to %s as it is disabled temporarily\n", __func__);
-#endif
- ret = -EINVAL;
- goto out;
- }
- if (relation & DISABLE_FURTHER_CPUFREQ)
- no_cpufreq_access++;
- relation &= ~MASK_FURTHER_CPUFREQ;
-
- ret = cpufreq_frequency_table_target(policy, freq_table, target_freq, relation, &i);
- if (ret) {
- FREQ_PRINTK_ERR("no freq match for %d(ret=%d)\n", target_freq, ret);
- goto out;
- }
- new_rate = freq_table[i].frequency;
- if (!no_cpufreq_access)
- new_rate = cpufreq_scale_limt(new_rate, policy, is_private);
-
- FREQ_PRINTK_LOG("cpufreq req=%u,new=%u(was=%u)\n", target_freq, new_rate, rk30_getspeed(0));
- if (new_rate == rk30_getspeed(0))
- goto out;
- ret = clk_set_rate(cpu_clk, new_rate * 1000);
-out:
- mutex_unlock(&cpufreq_mutex);
- FREQ_PRINTK_DBG("cpureq set rate (%u) end\n", new_rate);
- return ret;
-}
-
-static int rk30_cpufreq_pm_notifier_event(struct notifier_block *this,
- unsigned long event, void *ptr)
-{
- int ret = NOTIFY_DONE;
- struct cpufreq_policy *policy = cpufreq_cpu_get(0);
-
- if (!policy)
- return ret;
-
- if (!rk30_cpufreq_is_ondemand_policy(policy))
- goto out;
-
- switch (event) {
- case PM_SUSPEND_PREPARE:
- ret = cpufreq_driver_target(policy, suspend_freq, DISABLE_FURTHER_CPUFREQ | CPUFREQ_RELATION_H);
- if (ret < 0) {
- ret = NOTIFY_BAD;
- goto out;
- }
- ret = NOTIFY_OK;
- break;
- case PM_POST_RESTORE:
- case PM_POST_SUSPEND:
- cpufreq_driver_target(policy, suspend_freq, ENABLE_FURTHER_CPUFREQ | CPUFREQ_RELATION_H);
- ret = NOTIFY_OK;
- break;
- }
-out:
- cpufreq_cpu_put(policy);
- return ret;
-}
-
-static struct notifier_block rk30_cpufreq_pm_notifier = {
- .notifier_call = rk30_cpufreq_pm_notifier_event,
-};
-
-static int rk30_cpufreq_reboot_notifier_event(struct notifier_block *this,
- unsigned long event, void *ptr)
-{
- struct cpufreq_policy *policy = cpufreq_cpu_get(0);
-
- if (policy) {
- cpufreq_driver_target(policy, suspend_freq, DISABLE_FURTHER_CPUFREQ | CPUFREQ_RELATION_H);
- cpufreq_cpu_put(policy);
- }
-
- return NOTIFY_OK;
-}
-
-static struct notifier_block rk30_cpufreq_reboot_notifier = {
- .notifier_call = rk30_cpufreq_reboot_notifier_event,
-};
-
-static struct cpufreq_driver rk30_cpufreq_driver = {
- .flags = CPUFREQ_CONST_LOOPS,
- .verify = rk30_verify_speed,
- .target = rk30_target,
- .get = rk30_getspeed,
- .init = rk30_cpu_init,
- .exit = rk30_cpu_exit,
- .name = "rk30",
- .attr = rk30_cpufreq_attr,
-};
-
-static int __init rk30_cpufreq_init(void)
-{
- register_pm_notifier(&rk30_cpufreq_pm_notifier);
- register_reboot_notifier(&rk30_cpufreq_reboot_notifier);
- return cpufreq_register_driver(&rk30_cpufreq_driver);
-}
-
-static void __exit rk30_cpufreq_exit(void)
-{
- cpufreq_unregister_driver(&rk30_cpufreq_driver);
-}
-
-MODULE_DESCRIPTION("cpufreq driver for rock chip rk30");
-MODULE_LICENSE("GPL");
-device_initcall(rk30_cpufreq_init);
-module_exit(rk30_cpufreq_exit);
+++ /dev/null
-/*
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#define pr_fmt(fmt) "cpuidle: %s: " fmt, __func__
-
-#include <linux/pm.h>
-#include <linux/cpuidle.h>
-#include <linux/suspend.h>
-#include <linux/err.h>
-
-#include <asm/hardware/gic.h>
-#include <asm/io.h>
-
-static bool rk30_gic_interrupt_pending(void)
-{
- return (readl_relaxed(GIC_CPU_BASE + GIC_CPU_HIGHPRI) != 0x3FF);
-}
-
-static void rk30_wfi_until_interrupt(void)
-{
-retry:
- cpu_do_idle();
-
- if (!rk30_gic_interrupt_pending())
- goto retry;
-}
-
-static int rk30_idle(struct cpuidle_device *dev, struct cpuidle_state *state)
-{
- ktime_t preidle, postidle;
-
- local_fiq_disable();
-
- preidle = ktime_get();
-
- rk30_wfi_until_interrupt();
-
- postidle = ktime_get();
-
- local_fiq_enable();
- local_irq_enable();
-
- return ktime_to_us(ktime_sub(postidle, preidle));
-}
-
-static DEFINE_PER_CPU(struct cpuidle_device, rk30_cpuidle_device);
-
-static __initdata struct cpuidle_state rk30_cpuidle_states[] = {
- {
- .name = "C1",
- .desc = "idle",
- .flags = CPUIDLE_FLAG_TIME_VALID,
- .exit_latency = 0,
- .target_residency = 0,
- .enter = rk30_idle,
- },
-};
-
-static struct cpuidle_driver rk30_cpuidle_driver = {
- .name = "rk30_cpuidle",
- .owner = THIS_MODULE,
-};
-
-static int __init rk30_cpuidle_init(void)
-{
- struct cpuidle_device *dev;
- unsigned int cpu;
- int ret;
-
- ret = cpuidle_register_driver(&rk30_cpuidle_driver);
- if (ret) {
- pr_err("failed to register cpuidle driver: %d\n", ret);
- return ret;
- }
-
- for_each_possible_cpu(cpu) {
- dev = &per_cpu(rk30_cpuidle_device, cpu);
- dev->cpu = cpu;
- dev->state_count = ARRAY_SIZE(rk30_cpuidle_states);
- memcpy(dev->states, rk30_cpuidle_states, sizeof(rk30_cpuidle_states));
- dev->safe_state = &dev->states[0];
-
- ret = cpuidle_register_device(dev);
- if (ret) {
- pr_err("failed to register cpuidle device for cpu %u: %d\n", cpu, ret);
- return ret;
- }
- }
-
- return 0;
-}
-late_initcall(rk30_cpuidle_init);
+++ /dev/null
-/*
- * arch/arm/mach-rk30/ddr.c
- *
- * Function Driver for DDR controller
- *
- * Copyright (C) 2011 Fuzhou Rockchip Electronics Co.,Ltd
- * Author:
- * hcy@rock-chips.com
- * yk@rock-chips.com
- *
- * v1.00
- */
-
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/clk.h>
-
-#include <asm/cacheflush.h>
-#include <asm/tlbflush.h>
-
-#include <mach/sram.h>
-#include <mach/ddr.h>
-#include <mach/cpu.h>
-#include <plat/efuse.h>
-#include <linux/rk_fb.h>
-//#include <linux/delay.h>
-
-typedef uint32_t uint32;
-
-//#define ENABLE_DDR_CLCOK_GPLL_PATH //for RK3188
-
-#define DDR3_DDR2_ODT_DLL_DISABLE_FREQ (333)
-#define SR_IDLE (0x1) //unit:32*DDR clk cycle, and 0 for disable auto self-refresh
-#define PD_IDLE (0X40) //unit:DDR clk cycle, and 0 for disable auto power-down
-
-#if (DDR3_DDR2_ODT_DLL_DISABLE_FREQ > 333)
-#error
-#endif
-
-#define PMU_BASE_ADDR RK30_PMU_BASE
-#define SDRAMC_BASE_ADDR RK30_DDR_PCTL_BASE
-#define DDR_PUBL_BASE RK30_DDR_PUBL_BASE
-#define CRU_BASE_ADDR RK30_CRU_BASE
-#define REG_FILE_BASE_ADDR RK30_GRF_BASE
-#define SysSrv_DdrConf (RK30_CPU_AXI_BUS_BASE+0x08)
-#define SysSrv_DdrTiming (RK30_CPU_AXI_BUS_BASE+0x0c)
-#define SysSrv_DdrMode (RK30_CPU_AXI_BUS_BASE+0x10)
-#define SysSrv_ReadLatency (RK30_CPU_AXI_BUS_BASE+0x14)
-
-#if defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK3066B)
-#define SRAM_SIZE RK30_IMEM_SIZE
-#elif defined(CONFIG_ARCH_RK3188)
-#define SRAM_SIZE RK3188_IMEM_SIZE
-#endif
-
-#define ddr_print(x...) printk( "DDR DEBUG: " x )
-
-/***********************************
- * LPDDR2 define
- ***********************************/
-//MR0 (Device Information)
-#define LPDDR2_DAI (0x1) // 0:DAI complete, 1:DAI still in progress
-#define LPDDR2_DI (0x1<<1) // 0:S2 or S4 SDRAM, 1:NVM
-#define LPDDR2_DNVI (0x1<<2) // 0:DNV not supported, 1:DNV supported
-#define LPDDR2_RZQI (0x3<<3) // 00:RZQ self test not supported, 01:ZQ-pin may connect to VDDCA or float
- // 10:ZQ-pin may short to GND. 11:ZQ-pin self test completed, no error condition detected.
-
-//MR1 (Device Feature)
-#define LPDDR2_BL4 (0x2)
-#define LPDDR2_BL8 (0x3)
-#define LPDDR2_BL16 (0x4)
-#define LPDDR2_nWR(n) (((n)-2)<<5)
-
-//MR2 (Device Feature 2)
-#define LPDDR2_RL3_WL1 (0x1)
-#define LPDDR2_RL4_WL2 (0x2)
-#define LPDDR2_RL5_WL2 (0x3)
-#define LPDDR2_RL6_WL3 (0x4)
-#define LPDDR2_RL7_WL4 (0x5)
-#define LPDDR2_RL8_WL4 (0x6)
-
-//MR3 (IO Configuration 1)
-#define LPDDR2_DS_34 (0x1)
-#define LPDDR2_DS_40 (0x2)
-#define LPDDR2_DS_48 (0x3)
-#define LPDDR2_DS_60 (0x4)
-#define LPDDR2_DS_80 (0x6)
-#define LPDDR2_DS_120 (0x7) //optional
-
-//MR4 (Device Temperature)
-#define LPDDR2_tREF_MASK (0x7)
-#define LPDDR2_4_tREF (0x1)
-#define LPDDR2_2_tREF (0x2)
-#define LPDDR2_1_tREF (0x3)
-#define LPDDR2_025_tREF (0x5)
-#define LPDDR2_025_tREF_DERATE (0x6)
-
-#define LPDDR2_TUF (0x1<<7)
-
-//MR8 (Basic configuration 4)
-#define LPDDR2_S4 (0x0)
-#define LPDDR2_S2 (0x1)
-#define LPDDR2_N (0x2)
-#define LPDDR2_Density(mr8) (8<<(((mr8)>>2)&0xf)) // Unit:MB
-#define LPDDR2_IO_Width(mr8) (32>>(((mr8)>>6)&0x3))
-
-//MR10 (Calibration)
-#define LPDDR2_ZQINIT (0xFF)
-#define LPDDR2_ZQCL (0xAB)
-#define LPDDR2_ZQCS (0x56)
-#define LPDDR2_ZQRESET (0xC3)
-
-//MR16 (PASR Bank Mask)
-// S2 SDRAM Only
-#define LPDDR2_PASR_Full (0x0)
-#define LPDDR2_PASR_1_2 (0x1)
-#define LPDDR2_PASR_1_4 (0x2)
-#define LPDDR2_PASR_1_8 (0x3)
-
-//MR17 (PASR Segment Mask) 1Gb-8Gb S4 SDRAM only
-
-//MR32 (DQ Calibration Pattern A)
-
-//MR40 (DQ Calibration Pattern B)
-
-/***********************************
- * DDR3 define
- ***********************************/
-//mr0 for ddr3
-#define DDR3_BL8 (0)
-#define DDR3_BC4_8 (1)
-#define DDR3_BC4 (2)
-#define DDR3_CL(n) (((((n)-4)&0x7)<<4)|((((n)-4)&0x8)>>1))
-#define DDR3_WR(n) (((n)&0x7)<<9)
-#define DDR3_DLL_RESET (1<<8)
-#define DDR3_DLL_DeRESET (0<<8)
-
-//mr1 for ddr3
-#define DDR3_DLL_ENABLE (0)
-#define DDR3_DLL_DISABLE (1)
-#define DDR3_MR1_AL(n) (((n)&0x3)<<3)
-
-#define DDR3_DS_40 (0)
-#define DDR3_DS_34 (1<<1)
-#define DDR3_Rtt_Nom_DIS (0)
-#define DDR3_Rtt_Nom_60 (1<<2)
-#define DDR3_Rtt_Nom_120 (1<<6)
-#define DDR3_Rtt_Nom_40 ((1<<2)|(1<<6))
-
- //mr2 for ddr3
-#define DDR3_MR2_CWL(n) ((((n)-5)&0x7)<<3)
-#define DDR3_Rtt_WR_DIS (0)
-#define DDR3_Rtt_WR_60 (1<<9)
-#define DDR3_Rtt_WR_120 (2<<9)
-
-/***********************************
- * DDR2 define
- ***********************************/
-//MR; //Mode Register
-#define DDR2_BL4 (2)
-#define DDR2_BL8 (3)
-#define DDR2_CL(n) (((n)&0x7)<<4)
-#define DDR2_WR(n) ((((n)-1)&0x7)<<9)
-#define DDR2_DLL_RESET (1<<8)
-#define DDR2_DLL_DeRESET (0<<8)
-
-//EMR; //Extended Mode Register
-#define DDR2_DLL_ENABLE (0)
-#define DDR2_DLL_DISABLE (1)
-
-#define DDR2_STR_FULL (0)
-#define DDR2_STR_REDUCE (1<<1)
-#define DDR2_AL(n) (((n)&0x7)<<3)
-#define DDR2_Rtt_Nom_DIS (0)
-#define DDR2_Rtt_Nom_150 (0x40)
-#define DDR2_Rtt_Nom_75 (0x4)
-#define DDR2_Rtt_Nom_50 (0x44)
-
-/***********************************
- * LPDDR define
- ***********************************/
-#define mDDR_BL2 (1)
-#define mDDR_BL4 (2)
-#define mDDR_BL8 (3)
-#define mDDR_CL(n) (((n)&0x7)<<4)
-
-#define mDDR_DS_Full (0)
-#define mDDR_DS_1_2 (1<<5)
-#define mDDR_DS_1_4 (2<<5)
-#define mDDR_DS_1_8 (3<<5)
-#define mDDR_DS_3_4 (4<<5)
-
-
-//PMU_MISC_CON1
-#define idle_req_cpu_cfg (1<<1)
-#define idle_req_peri_cfg (1<<2)
-#define idle_req_gpu_cfg (1<<3)
-#define idle_req_video_cfg (1<<4)
-#define idle_req_vio_cfg (1<<5)
-#define idle_req_core_cfg (1<<14)
-#define idle_req_dma_cfg (1<<16)
-
-//PMU_PWRDN_ST
-#define idle_cpu (1<<26)
-#define idle_peri (1<<25)
-#define idle_gpu (1<<24)
-#define idle_video (1<<23)
-#define idle_vio (1<<22)
-#define idle_core (1<<15)
-#define idle_dma (1<<14)
-
-#define pd_a9_0_pwr_st (1<<0)
-#define pd_a9_1_pwr_st (1<<1)
-#define pd_peri_pwr_st (1<<6)
-#define pd_vio_pwr_st (1<<7)
-#define pd_video_pwr_st (1<<8)
-#define pd_gpu_pwr_st (1<<9)
-
-
-//PMU registers
-typedef volatile struct tagPMU_FILE
-{
- uint32 PMU_WAKEUP_CFG[2];
- uint32 PMU_PWRDN_CON;
- uint32 PMU_PWRDN_ST;
- uint32 PMU_INT_CON;
- uint32 PMU_INT_ST;
- uint32 PMU_MISC_CON;
- uint32 PMU_OSC_CNT;
- uint32 PMU_PLL_CNT;
- uint32 PMU_PMU_CNT;
- uint32 PMU_DDRIO_PWRON_CNT;
- uint32 PMU_WAKEUP_RST_CLR_CNT;
- uint32 PMU_SCU_PWRDWN_CNT;
- uint32 PMU_SCU_PWRUP_CNT;
- uint32 PMU_MISC_CON1;
- uint32 PMU_GPIO6_CON;
- uint32 PMU_PMU_SYS_REG[4];
-} PMU_FILE, *pPMU_FILE;
-
-#define pPMU_Reg ((pPMU_FILE)PMU_BASE_ADDR)
-
-#define PLL_RESET (((0x1<<5)<<16) | (0x1<<5))
-#define PLL_DE_RESET (((0x1<<5)<<16) | (0x0<<5))
-#define NR(n) ((0x3F<<(8+16)) | (((n)-1)<<8))
-#define NO(n) ((0xF<<16) | ((n)-1))
-#define NF(n) ((0x1FFF<<16) | ((n)-1))
-#define NB(n) ((0xFFF<<16) | ((n)-1))
-
-//RK3066B
-#define PLL_RESET_RK3066B (((0x1<<1)<<16) | (0x1<<1))
-#define PLL_DE_RESET_RK3066B (((0x1<<1)<<16) | (0x0<<1))
-#define NR_RK3066B(n) ((0x3F<<(8+16)) | (((n)-1)<<8))
-#define NO_RK3066B(n) ((0x3F<<16) | ((n)-1))
-#define NF_RK3066B(n) ((0xFFFF<<16) | ((n)-1))
-
- //CRU Registers
-typedef volatile struct tagCRU_STRUCT
-{
- uint32 CRU_PLL_CON[4][4];
- uint32 CRU_MODE_CON;
- uint32 CRU_CLKSEL_CON[35];
- uint32 CRU_CLKGATE_CON[10];
- uint32 reserved1[2];
- uint32 CRU_GLB_SRST_FST_VALUE;
- uint32 CRU_GLB_SRST_SND_VALUE;
- uint32 reserved2[2];
- uint32 CRU_SOFTRST_CON[9];
- uint32 CRU_MISC_CON;
- uint32 reserved3[2];
- uint32 CRU_GLB_CNT_TH;
-} CRU_REG, *pCRU_REG;
-
-#define pCRU_Reg ((pCRU_REG)CRU_BASE_ADDR)
-
-#define bank2_to_rank_en ((1<<2) | ((1<<2)<<16))
-#define bank2_to_rank_dis ((0<<2) | ((1<<2)<<16))
-#define rank_to_row15_en ((1<<1) | ((1<<1)<<16))
-#define rank_to_row15_dis ((0<<1) | ((1<<1)<<16))
-
-typedef struct tagGPIO_LH
-{
- uint32 GPIOL;
- uint32 GPIOH;
-}GPIO_LH_T;
-
-typedef struct tagGPIO_IOMUX
-{
- uint32 GPIOA_IOMUX;
- uint32 GPIOB_IOMUX;
- uint32 GPIOC_IOMUX;
- uint32 GPIOD_IOMUX;
-}GPIO_IOMUX_T;
-
-//REG FILE registers
-typedef volatile struct tagREG_FILE
-{
- GPIO_LH_T GRF_GPIO_DIR[7];
- GPIO_LH_T GRF_GPIO_DO[7];
- GPIO_LH_T GRF_GPIO_EN[7];
- GPIO_IOMUX_T GRF_GPIO_IOMUX[7];
- GPIO_LH_T GRF_GPIO_PULL[7];
- uint32 GRF_SOC_CON[3];
- uint32 GRF_SOC_STATUS0;
- uint32 GRF_DMAC1_CON[3];
- uint32 GRF_DMAC2_CON[4];
- uint32 GRF_UOC0_CON[3];
- uint32 GRF_UOC1_CON[4];
- uint32 GRF_DDRC_CON0;
- uint32 GRF_DDRC_STAT;
- uint32 reserved[(0x1c8-0x1a0)/4];
- uint32 GRF_OS_REG[4];
-} REG_FILE, *pREG_FILE;
-
-#define pGRF_Reg ((pREG_FILE)REG_FILE_BASE_ADDR)
-
-//REG FILE registers
-typedef volatile struct tagREG_FILE_RK3066B
-{
- GPIO_LH_T GRF_GPIO_DIR[4];
- GPIO_LH_T GRF_GPIO_DO[4];
- GPIO_LH_T GRF_GPIO_EN[4];
- GPIO_IOMUX_T GRF_GPIO_IOMUX[4];
- uint32 GRF_SOC_CON[3];
- uint32 GRF_SOC_STATUS0;
- uint32 GRF_DMAC0_CON[3];
- uint32 GRF_DMAC1_CON[4];
- uint32 reserved0[(0xec-0xcc)/4];
- uint32 GRF_DDRC_CON0;
- uint32 GRF_DDRC_STAT;
- uint32 GRF_IO_CON[5];
- uint32 reserved1;
- uint32 GRF_UOC0_CON[4];
- uint32 GRF_UOC1_CON[4];
- uint32 GRF_UOC2_CON[2];
- uint32 reserved2;
- uint32 GRF_UOC3_CON[2];
- uint32 GRF_HSIC_STAT;
- uint32 GRF_OS_REG[8];
-} REG_FILE_RK3066B, *pREG_FILE_RK3066B;
-
-#define pGRF_Reg_RK3066B ((pREG_FILE_RK3066B)REG_FILE_BASE_ADDR)
-
-//SCTL
-#define INIT_STATE (0)
-#define CFG_STATE (1)
-#define GO_STATE (2)
-#define SLEEP_STATE (3)
-#define WAKEUP_STATE (4)
-
-//STAT
-#define Init_mem (0)
-#define Config (1)
-#define Config_req (2)
-#define Access (3)
-#define Access_req (4)
-#define Low_power (5)
-#define Low_power_entry_req (6)
-#define Low_power_exit_req (7)
-
-//MCFG
-#define mddr_lpddr2_clk_stop_idle(n) ((n)<<24)
-#define pd_idle(n) ((n)<<8)
-#define mddr_en (2<<22)
-#define lpddr2_en (3<<22)
-#define ddr2_en (0<<5)
-#define ddr3_en (1<<5)
-#define lpddr2_s2 (0<<6)
-#define lpddr2_s4 (1<<6)
-#define mddr_lpddr2_bl_2 (0<<20)
-#define mddr_lpddr2_bl_4 (1<<20)
-#define mddr_lpddr2_bl_8 (2<<20)
-#define mddr_lpddr2_bl_16 (3<<20)
-#define ddr2_ddr3_bl_4 (0)
-#define ddr2_ddr3_bl_8 (1)
-#define tfaw_cfg(n) (((n)-4)<<18)
-#define pd_exit_slow (0<<17)
-#define pd_exit_fast (1<<17)
-#define pd_type(n) ((n)<<16)
-#define two_t_en(n) ((n)<<3)
-#define bl8int_en(n) ((n)<<2)
-#define cke_or_en(n) ((n)<<1)
-
-//POWCTL
-#define power_up_start (1<<0)
-
-//POWSTAT
-#define power_up_done (1<<0)
-
-//DFISTSTAT0
-#define dfi_init_complete (1<<0)
-
-//CMDTSTAT
-#define cmd_tstat (1<<0)
-
-//CMDTSTATEN
-#define cmd_tstat_en (1<<1)
-
-//MCMD
-#define Deselect_cmd (0)
-#define PREA_cmd (1)
-#define REF_cmd (2)
-#define MRS_cmd (3)
-#define ZQCS_cmd (4)
-#define ZQCL_cmd (5)
-#define RSTL_cmd (6)
-#define MRR_cmd (8)
-#define DPDE_cmd (9)
-
-#define lpddr2_op(n) ((n)<<12)
-#define lpddr2_ma(n) ((n)<<4)
-
-#define bank_addr(n) ((n)<<17)
-#define cmd_addr(n) ((n)<<4)
-
-#define start_cmd (1u<<31)
-
-typedef union STAT_Tag
-{
- uint32 d32;
- struct
- {
- unsigned ctl_stat : 3;
- unsigned reserved3 : 1;
- unsigned lp_trig : 3;
- unsigned reserved7_31 : 25;
- }b;
-}STAT_T;
-
-typedef union SCFG_Tag
-{
- uint32 d32;
- struct
- {
- unsigned hw_low_power_en : 1;
- unsigned reserved1_5 : 5;
- unsigned nfifo_nif1_dis : 1;
- unsigned reserved7 : 1;
- unsigned bbflags_timing : 4;
- unsigned reserved12_31 : 20;
- } b;
-}SCFG_T;
-
-/* DDR Controller register struct */
-typedef volatile struct DDR_REG_Tag
-{
- //Operational State, Control, and Status Registers
- SCFG_T SCFG; //State Configuration Register
- volatile uint32 SCTL; //State Control Register
- STAT_T STAT; //State Status Register
- volatile uint32 INTRSTAT; //Interrupt Status Register
- uint32 reserved0[(0x40-0x10)/4];
- //Initailization Control and Status Registers
- volatile uint32 MCMD; //Memory Command Register
- volatile uint32 POWCTL; //Power Up Control Registers
- volatile uint32 POWSTAT; //Power Up Status Register
- volatile uint32 CMDTSTAT; //Command Timing Status Register
- volatile uint32 CMDTSTATEN; //Command Timing Status Enable Register
- uint32 reserved1[(0x60-0x54)/4];
- volatile uint32 MRRCFG0; //MRR Configuration 0 Register
- volatile uint32 MRRSTAT0; //MRR Status 0 Register
- volatile uint32 MRRSTAT1; //MRR Status 1 Register
- uint32 reserved2[(0x7c-0x6c)/4];
- //Memory Control and Status Registers
- volatile uint32 MCFG1; //Memory Configuration 1 Register
- volatile uint32 MCFG; //Memory Configuration Register
- volatile uint32 PPCFG; //Partially Populated Memories Configuration Register
- volatile uint32 MSTAT; //Memory Status Register
- volatile uint32 LPDDR2ZQCFG; //LPDDR2 ZQ Configuration Register
- uint32 reserved3;
- //DTU Control and Status Registers
- volatile uint32 DTUPDES; //DTU Status Register
- volatile uint32 DTUNA; //DTU Number of Random Addresses Created Register
- volatile uint32 DTUNE; //DTU Number of Errors Register
- volatile uint32 DTUPRD0; //DTU Parallel Read 0
- volatile uint32 DTUPRD1; //DTU Parallel Read 1
- volatile uint32 DTUPRD2; //DTU Parallel Read 2
- volatile uint32 DTUPRD3; //DTU Parallel Read 3
- volatile uint32 DTUAWDT; //DTU Address Width
- uint32 reserved4[(0xc0-0xb4)/4];
- //Memory Timing Registers
- volatile uint32 TOGCNT1U; //Toggle Counter 1U Register
- volatile uint32 TINIT; //t_init Timing Register
- volatile uint32 TRSTH; //Reset High Time Register
- volatile uint32 TOGCNT100N; //Toggle Counter 100N Register
- volatile uint32 TREFI; //t_refi Timing Register
- volatile uint32 TMRD; //t_mrd Timing Register
- volatile uint32 TRFC; //t_rfc Timing Register
- volatile uint32 TRP; //t_rp Timing Register
- volatile uint32 TRTW; //t_rtw Timing Register
- volatile uint32 TAL; //AL Latency Register
- volatile uint32 TCL; //CL Timing Register
- volatile uint32 TCWL; //CWL Register
- volatile uint32 TRAS; //t_ras Timing Register
- volatile uint32 TRC; //t_rc Timing Register
- volatile uint32 TRCD; //t_rcd Timing Register
- volatile uint32 TRRD; //t_rrd Timing Register
- volatile uint32 TRTP; //t_rtp Timing Register
- volatile uint32 TWR; //t_wr Timing Register
- volatile uint32 TWTR; //t_wtr Timing Register
- volatile uint32 TEXSR; //t_exsr Timing Register
- volatile uint32 TXP; //t_xp Timing Register
- volatile uint32 TXPDLL; //t_xpdll Timing Register
- volatile uint32 TZQCS; //t_zqcs Timing Register
- volatile uint32 TZQCSI; //t_zqcsi Timing Register
- volatile uint32 TDQS; //t_dqs Timing Register
- volatile uint32 TCKSRE; //t_cksre Timing Register
- volatile uint32 TCKSRX; //t_cksrx Timing Register
- volatile uint32 TCKE; //t_cke Timing Register
- volatile uint32 TMOD; //t_mod Timing Register
- volatile uint32 TRSTL; //Reset Low Timing Register
- volatile uint32 TZQCL; //t_zqcl Timing Register
- volatile uint32 TMRR; //t_mrr Timing Register
- volatile uint32 TCKESR; //t_ckesr Timing Register
- volatile uint32 TDPD; //t_dpd Timing Register
- uint32 reserved5[(0x180-0x148)/4];
- //ECC Configuration, Control, and Status Registers
- volatile uint32 ECCCFG; //ECC Configuration Register
- volatile uint32 ECCTST; //ECC Test Register
- volatile uint32 ECCCLR; //ECC Clear Register
- volatile uint32 ECCLOG; //ECC Log Register
- uint32 reserved6[(0x200-0x190)/4];
- //DTU Control and Status Registers
- volatile uint32 DTUWACTL; //DTU Write Address Control Register
- volatile uint32 DTURACTL; //DTU Read Address Control Register
- volatile uint32 DTUCFG; //DTU Configuration Control Register
- volatile uint32 DTUECTL; //DTU Execute Control Register
- volatile uint32 DTUWD0; //DTU Write Data 0
- volatile uint32 DTUWD1; //DTU Write Data 1
- volatile uint32 DTUWD2; //DTU Write Data 2
- volatile uint32 DTUWD3; //DTU Write Data 3
- volatile uint32 DTUWDM; //DTU Write Data Mask
- volatile uint32 DTURD0; //DTU Read Data 0
- volatile uint32 DTURD1; //DTU Read Data 1
- volatile uint32 DTURD2; //DTU Read Data 2
- volatile uint32 DTURD3; //DTU Read Data 3
- volatile uint32 DTULFSRWD; //DTU LFSR Seed for Write Data Generation
- volatile uint32 DTULFSRRD; //DTU LFSR Seed for Read Data Generation
- volatile uint32 DTUEAF; //DTU Error Address FIFO
- //DFI Control Registers
- volatile uint32 DFITCTRLDELAY; //DFI tctrl_delay Register
- volatile uint32 DFIODTCFG; //DFI ODT Configuration Register
- volatile uint32 DFIODTCFG1; //DFI ODT Configuration 1 Register
- volatile uint32 DFIODTRANKMAP; //DFI ODT Rank Mapping Register
- //DFI Write Data Registers
- volatile uint32 DFITPHYWRDATA; //DFI tphy_wrdata Register
- volatile uint32 DFITPHYWRLAT; //DFI tphy_wrlat Register
- uint32 reserved7[(0x260-0x258)/4];
- volatile uint32 DFITRDDATAEN; //DFI trddata_en Register
- volatile uint32 DFITPHYRDLAT; //DFI tphy_rddata Register
- uint32 reserved8[(0x270-0x268)/4];
- //DFI Update Registers
- volatile uint32 DFITPHYUPDTYPE0; //DFI tphyupd_type0 Register
- volatile uint32 DFITPHYUPDTYPE1; //DFI tphyupd_type1 Register
- volatile uint32 DFITPHYUPDTYPE2; //DFI tphyupd_type2 Register
- volatile uint32 DFITPHYUPDTYPE3; //DFI tphyupd_type3 Register
- volatile uint32 DFITCTRLUPDMIN; //DFI tctrlupd_min Register
- volatile uint32 DFITCTRLUPDMAX; //DFI tctrlupd_max Register
- volatile uint32 DFITCTRLUPDDLY; //DFI tctrlupd_dly Register
- uint32 reserved9;
- volatile uint32 DFIUPDCFG; //DFI Update Configuration Register
- volatile uint32 DFITREFMSKI; //DFI Masked Refresh Interval Register
- volatile uint32 DFITCTRLUPDI; //DFI tctrlupd_interval Register
- uint32 reserved10[(0x2ac-0x29c)/4];
- volatile uint32 DFITRCFG0; //DFI Training Configuration 0 Register
- volatile uint32 DFITRSTAT0; //DFI Training Status 0 Register
- volatile uint32 DFITRWRLVLEN; //DFI Training dfi_wrlvl_en Register
- volatile uint32 DFITRRDLVLEN; //DFI Training dfi_rdlvl_en Register
- volatile uint32 DFITRRDLVLGATEEN; //DFI Training dfi_rdlvl_gate_en Register
- //DFI Status Registers
- volatile uint32 DFISTSTAT0; //DFI Status Status 0 Register
- volatile uint32 DFISTCFG0; //DFI Status Configuration 0 Register
- volatile uint32 DFISTCFG1; //DFI Status configuration 1 Register
- uint32 reserved11;
- volatile uint32 DFITDRAMCLKEN; //DFI tdram_clk_enalbe Register
- volatile uint32 DFITDRAMCLKDIS; //DFI tdram_clk_disalbe Register
- volatile uint32 DFISTCFG2; //DFI Status configuration 2 Register
- volatile uint32 DFISTPARCLR; //DFI Status Parity Clear Register
- volatile uint32 DFISTPARLOG; //DFI Status Parity Log Register
- uint32 reserved12[(0x2f0-0x2e4)/4];
- //DFI Low Power Registers
- volatile uint32 DFILPCFG0; //DFI Low Power Configuration 0 Register
- uint32 reserved13[(0x300-0x2f4)/4];
- //DFI Training 2 Registers
- volatile uint32 DFITRWRLVLRESP0; //DFI Training dif_wrlvl_resp Status 0 Register
- volatile uint32 DFITRWRLVLRESP1; //DFI Training dif_wrlvl_resp Status 1 Register
- volatile uint32 DFITRWRLVLRESP2; //DFI Training dif_wrlvl_resp Status 2 Register
- volatile uint32 DFITRRDLVLRESP0; //DFI Training dif_rdlvl_resp Status 0 Register
- volatile uint32 DFITRRDLVLRESP1; //DFI Training dif_rdlvl_resp Status 1 Register
- volatile uint32 DFITRRDLVLRESP2; //DFI Training dif_rdlvl_resp Status 2 Register
- volatile uint32 DFITRWRLVLDELAY0; //DFI Training dif_wrlvl_delay Configuration 0 Register
- volatile uint32 DFITRWRLVLDELAY1; //DFI Training dif_wrlvl_delay Configuration 1 Register
- volatile uint32 DFITRWRLVLDELAY2; //DFI Training dif_wrlvl_delay Configuration 2 Register
- volatile uint32 DFITRRDLVLDELAY0; //DFI Training dif_rdlvl_delay Configuration 0 Register
- volatile uint32 DFITRRDLVLDELAY1; //DFI Training dif_rdlvl_delay Configuration 1 Register
- volatile uint32 DFITRRDLVLDELAY2; //DFI Training dif_rdlvl_delay Configuration 2 Register
- volatile uint32 DFITRRDLVLGATEDELAY0; //DFI Training dif_rdlvl_gate_delay Configuration 0 Register
- volatile uint32 DFITRRDLVLGATEDELAY1; //DFI Training dif_rdlvl_gate_delay Configuration 1 Register
- volatile uint32 DFITRRDLVLGATEDELAY2; //DFI Training dif_rdlvl_gate_delay Configuration 2 Register
- volatile uint32 DFITRCMD; //DFI Training Command Register
- uint32 reserved14[(0x3f8-0x340)/4];
- //IP Status Registers
- volatile uint32 IPVR; //IP Version Register
- volatile uint32 IPTR; //IP Type Register
-}DDR_REG_T, *pDDR_REG_T;
-
-#define pDDR_Reg ((pDDR_REG_T)SDRAMC_BASE_ADDR)
-
-//PIR
-#define INIT (1<<0)
-#define DLLSRST (1<<1)
-#define DLLLOCK (1<<2)
-#define ZCAL (1<<3)
-#define ITMSRST (1<<4)
-#define DRAMRST (1<<5)
-#define DRAMINIT (1<<6)
-#define QSTRN (1<<7)
-#define EYETRN (1<<8)
-#define ICPC (1<<16)
-#define DLLBYP (1<<17)
-#define CTLDINIT (1<<18)
-#define CLRSR (1<<28)
-#define LOCKBYP (1<<29)
-#define ZCALBYP (1<<30)
-#define INITBYP (1u<<31)
-
-//PGCR
-#define DFTLMT(n) ((n)<<3)
-#define DFTCMP(n) ((n)<<2)
-#define DQSCFG(n) ((n)<<1)
-#define ITMDMD(n) ((n)<<0)
-#define RANKEN(n) ((n)<<18)
-
-//PGSR
-#define IDONE (1<<0)
-#define DLDONE (1<<1)
-#define ZCDONE (1<<2)
-#define DIDONE (1<<3)
-#define DTDONE (1<<4)
-#define DTERR (1<<5)
-#define DTIERR (1<<6)
-#define DFTERR (1<<7)
-#define TQ (1u<<31)
-
-//PTR0
-#define tITMSRST(n) ((n)<<18)
-#define tDLLLOCK(n) ((n)<<6)
-#define tDLLSRST(n) ((n)<<0)
-
-//PTR1
-#define tDINIT1(n) ((n)<<19)
-#define tDINIT0(n) ((n)<<0)
-
-//PTR2
-#define tDINIT3(n) ((n)<<17)
-#define tDINIT2(n) ((n)<<0)
-
-//DSGCR
-#define DQSGE(n) ((n)<<8)
-#define DQSGX(n) ((n)<<5)
-
-typedef union DCR_Tag
-{
- uint32 d32;
- struct
- {
- unsigned DDRMD : 3;
- unsigned DDR8BNK : 1;
- unsigned PDQ : 3;
- unsigned MPRDQ : 1;
- unsigned DDRTYPE : 2;
- unsigned reserved10_26 : 17;
- unsigned NOSRA : 1;
- unsigned DDR2T : 1;
- unsigned UDIMM : 1;
- unsigned RDIMM : 1;
- unsigned TPD : 1;
- } b;
-}DCR_T;
-
-
-typedef volatile struct DATX8_REG_Tag
-{
- volatile uint32 DXGCR; //DATX8 General Configuration Register
- volatile uint32 DXGSR[2]; //DATX8 General Status Register
- volatile uint32 DXDLLCR; //DATX8 DLL Control Register
- volatile uint32 DXDQTR; //DATX8 DQ Timing Register
- volatile uint32 DXDQSTR; //DATX8 DQS Timing Register
- uint32 reserved[0x80-0x76];
-}DATX8_REG_T;
-
-/* DDR PHY register struct */
-typedef volatile struct DDRPHY_REG_Tag
-{
- volatile uint32 RIDR; //Revision Identification Register
- volatile uint32 PIR; //PHY Initialization Register
- volatile uint32 PGCR; //PHY General Configuration Register
- volatile uint32 PGSR; //PHY General Status Register
- volatile uint32 DLLGCR; //DLL General Control Register
- volatile uint32 ACDLLCR; //AC DLL Control Register
- volatile uint32 PTR[3]; //PHY Timing Registers 0-2
- volatile uint32 ACIOCR; //AC I/O Configuration Register
- volatile uint32 DXCCR; //DATX8 Common Configuration Register
- volatile uint32 DSGCR; //DDR System General Configuration Register
- DCR_T DCR; //DRAM Configuration Register
- volatile uint32 DTPR[3]; //DRAM Timing Parameters Register 0-2
- volatile uint32 MR[4]; //Mode Register 0-3
- volatile uint32 ODTCR; //ODT Configuration Register
- volatile uint32 DTAR; //Data Training Address Register
- volatile uint32 DTDR[2]; //Data Training Data Register 0-1
-
- uint32 reserved1[0x30-0x18];
- uint32 DCU[0x38-0x30];
- uint32 reserved2[0x40-0x38];
- uint32 BIST[0x51-0x40];
- uint32 reserved3[0x60-0x51];
-
- volatile uint32 ZQ0CR[2]; //ZQ 0 Impedance Control Register 0-1
- volatile uint32 ZQ0SR[2]; //ZQ 0 Impedance Status Register 0-1
- volatile uint32 ZQ1CR[2]; //ZQ 1 Impedance Control Register 0-1
- volatile uint32 ZQ1SR[2]; //ZQ 1 Impedance Status Register 0-1
- volatile uint32 ZQ2CR[2]; //ZQ 2 Impedance Control Register 0-1
- volatile uint32 ZQ2SR[2]; //ZQ 2 Impedance Status Register 0-1
- volatile uint32 ZQ3CR[2]; //ZQ 3 Impedance Control Register 0-1
- volatile uint32 ZQ3SR[2]; //ZQ 3 Impedance Status Register 0-1
-
- DATX8_REG_T DATX8[9]; //DATX8 Register
-}DDRPHY_REG_T, *pDDRPHY_REG_T;
-
-#define pPHY_Reg ((pDDRPHY_REG_T)DDR_PUBL_BASE)
-
-typedef enum DRAM_TYPE_Tag
-{
- LPDDR = 0,
- DDR,
- DDR2,
- DDR3,
- LPDDR2,
-
- DRAM_MAX
-}DRAM_TYPE;
-
-typedef struct PCTRL_TIMING_Tag
-{
- uint32 ddrFreq;
- //Memory Timing Registers
- uint32 togcnt1u; //Toggle Counter 1U Register
- uint32 tinit; //t_init Timing Register
- uint32 trsth; //Reset High Time Register
- uint32 togcnt100n; //Toggle Counter 100N Register
- uint32 trefi; //t_refi Timing Register
- uint32 tmrd; //t_mrd Timing Register
- uint32 trfc; //t_rfc Timing Register
- uint32 trp; //t_rp Timing Register
- uint32 trtw; //t_rtw Timing Register
- uint32 tal; //AL Latency Register
- uint32 tcl; //CL Timing Register
- uint32 tcwl; //CWL Register
- uint32 tras; //t_ras Timing Register
- uint32 trc; //t_rc Timing Register
- uint32 trcd; //t_rcd Timing Register
- uint32 trrd; //t_rrd Timing Register
- uint32 trtp; //t_rtp Timing Register
- uint32 twr; //t_wr Timing Register
- uint32 twtr; //t_wtr Timing Register
- uint32 texsr; //t_exsr Timing Register
- uint32 txp; //t_xp Timing Register
- uint32 txpdll; //t_xpdll Timing Register
- uint32 tzqcs; //t_zqcs Timing Register
- uint32 tzqcsi; //t_zqcsi Timing Register
- uint32 tdqs; //t_dqs Timing Register
- uint32 tcksre; //t_cksre Timing Register
- uint32 tcksrx; //t_cksrx Timing Register
- uint32 tcke; //t_cke Timing Register
- uint32 tmod; //t_mod Timing Register
- uint32 trstl; //Reset Low Timing Register
- uint32 tzqcl; //t_zqcl Timing Register
- uint32 tmrr; //t_mrr Timing Register
- uint32 tckesr; //t_ckesr Timing Register
- uint32 tdpd; //t_dpd Timing Register
-}PCTL_TIMING_T;
-
-typedef union DTPR_0_Tag
-{
- uint32 d32;
- struct
- {
- unsigned tMRD : 2;
- unsigned tRTP : 3;
- unsigned tWTR : 3;
- unsigned tRP : 4;
- unsigned tRCD : 4;
- unsigned tRAS : 5;
- unsigned tRRD : 4;
- unsigned tRC : 6;
- unsigned tCCD : 1;
- } b;
-}DTPR_0_T;
-
-typedef union DTPR_1_Tag
-{
- uint32 d32;
- struct
- {
- unsigned tAOND : 2;
- unsigned tRTW : 1;
- unsigned tFAW : 6;
- unsigned tMOD : 2;
- unsigned tRTODT : 1;
- unsigned reserved12_15 : 4;
- unsigned tRFC : 8;
- unsigned tDQSCK : 3;
- unsigned tDQSCKmax : 3;
- unsigned reserved30_31 : 2;
- } b;
-}DTPR_1_T;
-
-typedef union DTPR_2_Tag
-{
- uint32 d32;
- struct
- {
- unsigned tXS : 10;
- unsigned tXP : 5;
- unsigned tCKE : 4;
- unsigned tDLLK : 10;
- unsigned reserved29_31 : 3;
- } b;
-}DTPR_2_T;
-
-typedef struct PHY_TIMING_Tag
-{
- DTPR_0_T dtpr0;
- DTPR_1_T dtpr1;
- DTPR_2_T dtpr2;
- uint32 mr[4]; //LPDDR2 no MR0, mr[2] is mDDR MR1
-}PHY_TIMING_T;
-
-typedef union NOC_TIMING_Tag
-{
- uint32 d32;
- struct
- {
- unsigned ActToAct : 6;
- unsigned RdToMiss : 6;
- unsigned WrToMiss : 6;
- unsigned BurstLen : 3;
- unsigned RdToWr : 5;
- unsigned WrToRd : 5;
- unsigned BwRatio : 1;
- } b;
-}NOC_TIMING_T;
-
-typedef struct PCTL_REG_Tag
-{
- uint32 SCFG;
- uint32 CMDTSTATEN;
- uint32 MCFG1;
- uint32 MCFG;
- PCTL_TIMING_T pctl_timing;
- //DFI Control Registers
- uint32 DFITCTRLDELAY;
- uint32 DFIODTCFG;
- uint32 DFIODTCFG1;
- uint32 DFIODTRANKMAP;
- //DFI Write Data Registers
- uint32 DFITPHYWRDATA;
- uint32 DFITPHYWRLAT;
- //DFI Read Data Registers
- uint32 DFITRDDATAEN;
- uint32 DFITPHYRDLAT;
- //DFI Update Registers
- uint32 DFITPHYUPDTYPE0;
- uint32 DFITPHYUPDTYPE1;
- uint32 DFITPHYUPDTYPE2;
- uint32 DFITPHYUPDTYPE3;
- uint32 DFITCTRLUPDMIN;
- uint32 DFITCTRLUPDMAX;
- uint32 DFITCTRLUPDDLY;
- uint32 DFIUPDCFG;
- uint32 DFITREFMSKI;
- uint32 DFITCTRLUPDI;
- //DFI Status Registers
- uint32 DFISTCFG0;
- uint32 DFISTCFG1;
- uint32 DFITDRAMCLKEN;
- uint32 DFITDRAMCLKDIS;
- uint32 DFISTCFG2;
- //DFI Low Power Register
- uint32 DFILPCFG0;
-}PCTL_REG_T;
-
-typedef struct PUBL_REG_Tag
-{
- uint32 PIR;
- uint32 PGCR;
- uint32 DLLGCR;
- uint32 ACDLLCR;
- uint32 PTR[3];
- uint32 ACIOCR;
- uint32 DXCCR;
- uint32 DSGCR;
- uint32 DCR;
- PHY_TIMING_T phy_timing;
- uint32 ODTCR;
- uint32 DTAR;
- uint32 ZQ0CR0;
- uint32 ZQ1CR0;
-
- uint32 DX0GCR;
- uint32 DX0DLLCR;
- uint32 DX0DQTR;
- uint32 DX0DQSTR;
-
- uint32 DX1GCR;
- uint32 DX1DLLCR;
- uint32 DX1DQTR;
- uint32 DX1DQSTR;
-
- uint32 DX2GCR;
- uint32 DX2DLLCR;
- uint32 DX2DQTR;
- uint32 DX2DQSTR;
-
- uint32 DX3GCR;
- uint32 DX3DLLCR;
- uint32 DX3DQTR;
- uint32 DX3DQSTR;
-}PUBL_REG_T;
-
-typedef struct BACKUP_REG_Tag
-{
- PCTL_REG_T pctl;
- PUBL_REG_T publ;
- uint32 DdrConf;
- NOC_TIMING_T noc_timing;
- uint32 DdrMode;
- uint32 ReadLatency;
-}BACKUP_REG_T;
-
-#define READ_CS_INFO() ((((pPMU_Reg->PMU_PMU_SYS_REG[2])>>11)&0x1)+1)
-#define READ_BW_INFO() (2>>(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>2)&0x3))
-#define READ_COL_INFO() (9+(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>9)&0x3))
-#define READ_BK_INFO() (3-(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>8)&0x1))
-#define READ_CS0_ROW_INFO() (13+(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>6)&0x3))
-#define READ_CS1_ROW_INFO() (13+(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>4)&0x3))
-#define READ_DIE_BW_INFO() (2>>(pPMU_Reg->PMU_PMU_SYS_REG[2]&0x3))
-
-__sramdata BACKUP_REG_T ddr_reg;
-
-uint8_t ddr_cfg_2_rbc[] =
-{
- /****************************/
- // [7:6] bank(n:n bit bank)
- // [5:4] row(13+n)
- // [3:2] bank(n:n bit bank)
- // [1:0] col(9+n)
- /****************************/
- //bank, row, bank, col
- ((3<<6)|(2<<4)|(0<<2)|2), // 0 bank ahead
- ((0<<6)|(2<<4)|(3<<2)|1), // 1
- ((0<<6)|(1<<4)|(3<<2)|1), // 2
- ((0<<6)|(0<<4)|(3<<2)|1), // 3
- ((0<<6)|(2<<4)|(3<<2)|2), // 4
- ((0<<6)|(1<<4)|(3<<2)|2), // 5
- ((0<<6)|(0<<4)|(3<<2)|2), // 6
- ((0<<6)|(1<<4)|(3<<2)|0), // 7
- ((0<<6)|(0<<4)|(3<<2)|0), // 8
- ((1<<6)|(2<<4)|(2<<2)|2), // 9
- ((1<<6)|(1<<4)|(2<<2)|2), // 10
- ((1<<6)|(2<<4)|(2<<2)|1), // 11
- ((1<<6)|(1<<4)|(2<<2)|1), // 12
- ((1<<6)|(2<<4)|(2<<2)|0), // 13
- ((1<<6)|(1<<4)|(2<<2)|0), // 14
- ((3<<6)|(2<<4)|(0<<2)|1), // 15 bank ahead
-};
-
-__attribute__((aligned(4096))) uint32_t ddr_data_training_buf[32];
-
-uint8_t __sramdata ddr3_cl_cwl[22][4]={
-/* 0~330 330~400 400~533 speed
-* tCK >3 2.5~3 1.875~2.5 1.5~1.875
-* cl<<4, cwl cl<<4, cwl cl<<4, cwl */
- {((5<<4)|5), ((5<<4)|5), 0 , 0}, //DDR3_800D
- {((5<<4)|5), ((6<<4)|5), 0 , 0}, //DDR3_800E
-
- {((5<<4)|5), ((5<<4)|5), ((6<<4)|6), 0}, //DDR3_1066E
- {((5<<4)|5), ((6<<4)|5), ((7<<4)|6), 0}, //DDR3_1066F
- {((5<<4)|5), ((6<<4)|5), ((8<<4)|6), 0}, //DDR3_1066G
-
- {((5<<4)|5), ((5<<4)|5), ((6<<4)|6), ((7<<4)|7)}, //DDR3_1333F
- {((5<<4)|5), ((5<<4)|5), ((7<<4)|6), ((8<<4)|7)}, //DDR3_1333G
- {((5<<4)|5), ((6<<4)|5), ((8<<4)|6), ((9<<4)|7)}, //DDR3_1333H
- {((5<<4)|5), ((6<<4)|5), ((8<<4)|6), ((10<<4)|7)}, //DDR3_1333J
-
- {((5<<4)|5), ((5<<4)|5), ((6<<4)|6), ((7<<4)|7)}, //DDR3_1600G
- {((5<<4)|5), ((5<<4)|5), ((6<<4)|6), ((8<<4)|7)}, //DDR3_1600H
- {((5<<4)|5), ((5<<4)|5), ((7<<4)|6), ((9<<4)|7)}, //DDR3_1600J
- {((5<<4)|5), ((6<<4)|5), ((7<<4)|6), ((10<<4)|7)}, //DDR3_1600K
-
- {((5<<4)|5), ((5<<4)|5), ((6<<4)|6), ((8<<4)|7)}, //DDR3_1866J
- {((5<<4)|5), ((5<<4)|5), ((7<<4)|6), ((8<<4)|7)}, //DDR3_1866K
- {((6<<4)|5), ((6<<4)|5), ((7<<4)|6), ((9<<4)|7)}, //DDR3_1866L
- {((6<<4)|5), ((6<<4)|5), ((8<<4)|6), ((10<<4)|7)}, //DDR3_1866M
-
- {((5<<4)|5), ((5<<4)|5), ((6<<4)|6), ((7<<4)|7)}, //DDR3_2133K
- {((5<<4)|5), ((5<<4)|5), ((6<<4)|6), ((8<<4)|7)}, //DDR3_2133L
- {((5<<4)|5), ((5<<4)|5), ((7<<4)|6), ((9<<4)|7)}, //DDR3_2133M
- {((6<<4)|5), ((6<<4)|5), ((7<<4)|6), ((9<<4)|7)}, //DDR3_2133N
-
- {((6<<4)|5), ((6<<4)|5), ((8<<4)|6), ((10<<4)|7)} //DDR3_DEFAULT
-};
-
-uint16_t __sramdata ddr3_tRC_tFAW[22]={
-/** tRC tFAW */
- ((50<<8)|50), //DDR3_800D
- ((53<<8)|50), //DDR3_800E
-
- ((49<<8)|50), //DDR3_1066E
- ((51<<8)|50), //DDR3_1066F
- ((53<<8)|50), //DDR3_1066G
-
- ((47<<8)|45), //DDR3_1333F
- ((48<<8)|45), //DDR3_1333G
- ((50<<8)|45), //DDR3_1333H
- ((51<<8)|45), //DDR3_1333J
-
- ((45<<8)|40), //DDR3_1600G
- ((47<<8)|40), //DDR3_1600H
- ((48<<8)|40), //DDR3_1600J
- ((49<<8)|40), //DDR3_1600K
-
- ((45<<8)|35), //DDR3_1866J
- ((46<<8)|35), //DDR3_1866K
- ((47<<8)|35), //DDR3_1866L
- ((48<<8)|35), //DDR3_1866M
-
- ((44<<8)|35), //DDR3_2133K
- ((45<<8)|35), //DDR3_2133L
- ((46<<8)|35), //DDR3_2133M
- ((47<<8)|35), //DDR3_2133N
-
- ((53<<8)|50) //DDR3_DEFAULT
-};
-
-__sramdata uint32_t mem_type; // 0:LPDDR, 1:DDR, 2:DDR2, 3:DDR3, 4:LPDDR2
-static __sramdata uint32_t ddr_speed_bin; // used for ddr3 only
-static __sramdata uint32_t ddr_capability_per_die; // one chip cs capability
-static __sramdata uint32_t ddr_freq;
-static __sramdata uint32_t ddr_sr_idle;
-
-/****************************************************************************
-Internal sram us delay function
-Cpu highest frequency is 1.6 GHz
-1 cycle = 1/1.6 ns
-1 us = 1000 ns = 1000 * 1.6 cycles = 1600 cycles
-*****************************************************************************/
-static __sramdata volatile uint32_t loops_per_us;
-
-#define LPJ_100MHZ 999456UL
-
-/*static*/ void __sramlocalfunc ddr_delayus(uint32_t us)
-{
- do
- {
- unsigned int i = (loops_per_us*us);
- if (i < 7) i = 7;
- barrier();
- asm volatile(".align 4; 1: subs %0, %0, #1; bne 1b;" : "+r" (i));
- } while (0);
-}
-
-__sramfunc void ddr_copy(uint32 *pDest, uint32 *pSrc, uint32 words)
-{
- uint32 i;
-
- for(i=0; i<words; i++)
- {
- pDest[i] = pSrc[i];
- }
-}
-
-uint32 ddr_get_row(void)
-{
- uint32 i;
- uint32 row;
-
- if(pPMU_Reg->PMU_PMU_SYS_REG[2])
- {
- row=READ_CS0_ROW_INFO();
- }
- else
- {
- i = *(volatile uint32*)SysSrv_DdrConf;
- row = 13+((ddr_cfg_2_rbc[i]>>4)&0x3);
-#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
- if(pGRF_Reg_RK3066B->GRF_SOC_CON[2] & (1<<1))
- {
- row += 1;
- }
-#else
- if(pGRF_Reg->GRF_SOC_CON[2] & (1<<1))
- {
- row += 1;
- }
-#endif
- }
- return row;
-}
-
-uint32 ddr_get_bank(void)
-{
- uint32 i;
- uint32 bank;
-
- if(pPMU_Reg->PMU_PMU_SYS_REG[2])
- {
- bank = READ_BK_INFO();
- }
- else
- {
- i = *(volatile uint32*)SysSrv_DdrConf;
- bank = ((ddr_cfg_2_rbc[i]>>6)&0x3) + ((ddr_cfg_2_rbc[i]>>2)&0x3);
-#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
- if(pGRF_Reg_RK3066B->GRF_SOC_CON[2] & (1<<2))
- {
- bank -= 1;
- }
-#else
- if(pGRF_Reg->GRF_SOC_CON[2] & (1<<2))
- {
- bank -= 1;
- }
-#endif
- }
- return bank;
-}
-
-uint32 ddr_get_col(void)
-{
- uint32 i;
- uint32 col;
-
- if(pPMU_Reg->PMU_PMU_SYS_REG[2])
- {
- col=READ_COL_INFO();
- }
- else
- {
- i = *(volatile uint32*)SysSrv_DdrConf;
- col = 9+(ddr_cfg_2_rbc[i]&0x3);
- if(pDDR_Reg->PPCFG & 1)
- {
- col +=1;
- }
- }
- return col;
-}
-
-uint32 ddr_get_bw(void)
-{
- uint32 bw;
-
- if(pDDR_Reg->PPCFG & 1)
- {
- bw=1;
- }
- else
- {
- bw=2;
- }
- return bw;
-}
-
-uint32 ddr_get_cs(void)
-{
- uint32 cs;
-
- switch((pPHY_Reg->PGCR>>18) & 0xF)
- {
- case 0xF:
- cs = 4;
- case 7:
- cs = 3;
- break;
- case 3:
- cs = 2;
- break;
- default:
- cs = 1;
- break;
- }
- return cs;
-}
-
-uint32_t ddr_get_datatraing_addr(void)
-{
- uint32_t value=0;
- uint32_t addr;
- uint32_t col = 0;
- uint32_t row = 0;
- uint32_t bank = 0;
- uint32_t bw = 0;
- uint32_t i;
-
- // caculate aglined physical address
- addr = __pa((unsigned long)ddr_data_training_buf);
- if(addr&0x3F)
- {
- addr += (64-(addr&0x3F));
- }
- addr -= 0x60000000;
- // find out col£¬row£¬bank
- row = ddr_get_row();
- bank = ddr_get_bank();
- col = ddr_get_col();
- bw = ddr_get_bw();
- // according different address mapping, caculate DTAR register value
- i = (*(volatile uint32*)SysSrv_DdrConf);
- value |= (addr>>bw) & ((0x1<<col)-1); // col
- if(row==16)
- {
- value |= ((addr>>(bw+col+((ddr_cfg_2_rbc[i]>>2)&0x3))) & 0x7FFF) << 12; // row
- value |= (((addr>>(bw+col+bank+15))&0x1)<<15)<<12;
- row = 15; //use for bank
- }
- else
- {
- value |= ((addr>>(bw+col+((ddr_cfg_2_rbc[i]>>2)&0x3))) & ((0x1<<row)-1)) << 12; // row
- }
- if(((ddr_cfg_2_rbc[i]>>6)&0x3)==1)
- {
- value |= (((addr>>(bw+col)) & 0x3) << 28)
- | (((addr>>(bw+col+2+row)) & (bank-2)) << 30); // bank
- }
- else if(((ddr_cfg_2_rbc[i]>>6)&0x3)==3)
- {
- value |= (((addr>>(bw+col+row)) & ((0x1<<bank)-1)) << 28); // bank
- }
- else
- {
- value |= (((addr>>(bw+col)) & 0x7) << 28); // bank
- }
-
- return value;
-}
-
-__sramlocalfunc void ddr_reset_dll(void)
-{
- pPHY_Reg->ACDLLCR &= ~0x40000000;
- pPHY_Reg->DATX8[0].DXDLLCR &= ~0x40000000;
- pPHY_Reg->DATX8[1].DXDLLCR &= ~0x40000000;
- if(!(pDDR_Reg->PPCFG & 1))
- {
- pPHY_Reg->DATX8[2].DXDLLCR &= ~0x40000000;
- pPHY_Reg->DATX8[3].DXDLLCR &= ~0x40000000;
- }
- ddr_delayus(1);
- pPHY_Reg->ACDLLCR |= 0x40000000;
- pPHY_Reg->DATX8[0].DXDLLCR |= 0x40000000;
- pPHY_Reg->DATX8[1].DXDLLCR |= 0x40000000;
- if(!(pDDR_Reg->PPCFG & 1))
- {
- pPHY_Reg->DATX8[2].DXDLLCR |= 0x40000000;
- pPHY_Reg->DATX8[3].DXDLLCR |= 0x40000000;
- }
- ddr_delayus(1);
-}
-
-__sramfunc void ddr_move_to_Lowpower_state(void)
-{
- volatile uint32 value;
-
- while(1)
- {
- value = pDDR_Reg->STAT.b.ctl_stat;
- if(value == Low_power)
- {
- break;
- }
- switch(value)
- {
- case Init_mem:
- pDDR_Reg->SCTL = CFG_STATE;
- dsb();
- while((pDDR_Reg->STAT.b.ctl_stat) != Config);
- case Config:
- pDDR_Reg->SCTL = GO_STATE;
- dsb();
- while((pDDR_Reg->STAT.b.ctl_stat) != Access);
- case Access:
- pDDR_Reg->SCTL = SLEEP_STATE;
- dsb();
- while((pDDR_Reg->STAT.b.ctl_stat) != Low_power);
- break;
- default: //Transitional state
- break;
- }
- }
-}
-
-__sramfunc void ddr_move_to_Access_state(void)
-{
- volatile uint32 value;
-
- //set auto self-refresh idle
- pDDR_Reg->MCFG1=(pDDR_Reg->MCFG1&0xffffff00)|ddr_sr_idle | (1<<31);
- dsb();
-
- while(1)
- {
- value = pDDR_Reg->STAT.b.ctl_stat;
- if((value == Access)
- || ((pDDR_Reg->STAT.b.lp_trig == 1) && ((pDDR_Reg->STAT.b.ctl_stat) == Low_power)))
- {
- break;
- }
- switch(value)
- {
- case Low_power:
- pDDR_Reg->SCTL = WAKEUP_STATE;
- dsb();
- while((pDDR_Reg->STAT.b.ctl_stat) != Access);
- while((pPHY_Reg->PGSR & DLDONE) != DLDONE); //wait DLL lock
- break;
- case Init_mem:
- pDDR_Reg->SCTL = CFG_STATE;
- dsb();
- while((pDDR_Reg->STAT.b.ctl_stat) != Config);
- case Config:
- pDDR_Reg->SCTL = GO_STATE;
- dsb();
- while(!(((pDDR_Reg->STAT.b.ctl_stat) == Access)
- || ((pDDR_Reg->STAT.b.lp_trig == 1) && ((pDDR_Reg->STAT.b.ctl_stat) == Low_power))));
- break;
- default: //Transitional state
- break;
- }
- }
-#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
- pGRF_Reg_RK3066B->GRF_SOC_CON[2] = (1<<16 | 0);//de_hw_wakeup :enable auto sr if sr_idle != 0
-#else
- pGRF_Reg->GRF_SOC_CON[2] = (1<<16 | 0);//de_hw_wakeup :enable auto sr if sr_idle != 0
-#endif
-
-}
-
-__sramfunc void ddr_move_to_Config_state(void)
-{
- volatile uint32 value;
-#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
- pGRF_Reg_RK3066B->GRF_SOC_CON[2] = (1<<16 | 1); //hw_wakeup :disable auto sr
-#else
- pGRF_Reg->GRF_SOC_CON[2] = (1<<16 | 1); //hw_wakeup :disable auto sr
-#endif
- dsb();
-
- while(1)
- {
- value = pDDR_Reg->STAT.b.ctl_stat;
- if(value == Config)
- {
- break;
- }
- switch(value)
- {
- case Low_power:
- pDDR_Reg->SCTL = WAKEUP_STATE;
- dsb();
- while((pDDR_Reg->STAT.b.ctl_stat) != Access);
- while((pPHY_Reg->PGSR & DLDONE) != DLDONE); //wait DLL lock
- case Access:
- case Init_mem:
- pDDR_Reg->SCTL = CFG_STATE;
- dsb();
- while((pDDR_Reg->STAT.b.ctl_stat) != Config);
- break;
- default: //Transitional state
- break;
- }
- }
-}
-
-//arg°üÀ¨bank_addrºÍcmd_addr
-void __sramlocalfunc ddr_send_command(uint32 rank, uint32 cmd, uint32 arg)
-{
- pDDR_Reg->MCMD = (start_cmd | (rank<<20) | arg | cmd);
- dsb();
- while(pDDR_Reg->MCMD & start_cmd);
-}
-
-//¶ÔtypeÀàÐ͵ÄDDRµÄ¼¸¸öcs½øÐÐDTT
-//0 DTT³É¹¦
-//!0 DTTʧ°Ü
-uint32_t __sramlocalfunc ddr_data_training(void)
-{
- uint32 value,cs,i,byte=2;
-
- // disable auto refresh
- value = pDDR_Reg->TREFI;
- pDDR_Reg->TREFI = 0;
- dsb();
- if(mem_type != LPDDR2)
- {
- // passive window
- pPHY_Reg->PGCR |= (1<<1);
- }
- // clear DTDONE status
- pPHY_Reg->PIR |= CLRSR;
- cs = ((pPHY_Reg->PGCR>>18) & 0xF);
- pPHY_Reg->PGCR = (pPHY_Reg->PGCR & (~(0xF<<18))) | (1<<18); //use cs0 dtt
- // trigger DTT
- pPHY_Reg->PIR |= INIT | QSTRN | LOCKBYP | ZCALBYP | CLRSR | ICPC;
- dsb();
- // wait echo byte DTDONE
- while((pPHY_Reg->DATX8[0].DXGSR[0] & 1) != 1);
- while((pPHY_Reg->DATX8[1].DXGSR[0] & 1) != 1);
- if(!(pDDR_Reg->PPCFG & 1))
- {
- while((pPHY_Reg->DATX8[2].DXGSR[0] & 1) != 1);
- while((pPHY_Reg->DATX8[3].DXGSR[0] & 1) != 1);
- byte=4;
- }
- pPHY_Reg->PGCR = (pPHY_Reg->PGCR & (~(0xF<<18))) | (cs<<18); //restore cs
- for(i=0;i<byte;i++)
- {
- pPHY_Reg->DATX8[i].DXDQSTR = (pPHY_Reg->DATX8[i].DXDQSTR & (~((0x7<<3)|(0x3<<14))))
- | ((pPHY_Reg->DATX8[i].DXDQSTR & 0x7)<<3)
- | (((pPHY_Reg->DATX8[i].DXDQSTR>>12) & 0x3)<<14);
- }
- // send some auto refresh to complement the lost while DTT£¬//²âµ½1¸öCSµÄDTT×ʱ¼äÊÇ10.7us¡£×î¶à²¹2´ÎË¢ÐÂ
- if(cs > 1)
- {
- ddr_send_command(cs, REF_cmd, 0);
- ddr_send_command(cs, REF_cmd, 0);
- ddr_send_command(cs, REF_cmd, 0);
- ddr_send_command(cs, REF_cmd, 0);
- }
- else
- {
- ddr_send_command(cs, REF_cmd, 0);
- ddr_send_command(cs, REF_cmd, 0);
- }
- if(mem_type != LPDDR2)
- {
- // active window
- pPHY_Reg->PGCR &= ~(1<<1);
- }
- // resume auto refresh
- pDDR_Reg->TREFI = value;
-
- if(pPHY_Reg->PGSR & DTERR)
- {
- return (-1);
- }
- else
- {
- return 0;
- }
-}
-
-void __sramlocalfunc ddr_set_dll_bypass(uint32 freq)
-{
- if(freq<=150)
- {
- pPHY_Reg->DLLGCR &= ~(1<<23);
- pPHY_Reg->ACDLLCR |= 0x80000000;
- pPHY_Reg->DATX8[0].DXDLLCR |= 0x80000000;
- pPHY_Reg->DATX8[1].DXDLLCR |= 0x80000000;
- pPHY_Reg->DATX8[2].DXDLLCR |= 0x80000000;
- pPHY_Reg->DATX8[3].DXDLLCR |= 0x80000000;
- pPHY_Reg->PIR |= DLLBYP;
- }
- else if(freq<=250)
- {
- pPHY_Reg->DLLGCR |= (1<<23);
- pPHY_Reg->ACDLLCR |= 0x80000000;
- pPHY_Reg->DATX8[0].DXDLLCR |= 0x80000000;
- pPHY_Reg->DATX8[1].DXDLLCR |= 0x80000000;
- pPHY_Reg->DATX8[2].DXDLLCR |= 0x80000000;
- pPHY_Reg->DATX8[3].DXDLLCR |= 0x80000000;
- pPHY_Reg->PIR |= DLLBYP;
- }
- else
- {
- pPHY_Reg->DLLGCR &= ~(1<<23);
- pPHY_Reg->ACDLLCR &= ~0x80000000;
- pPHY_Reg->DATX8[0].DXDLLCR &= ~0x80000000;
- pPHY_Reg->DATX8[1].DXDLLCR &= ~0x80000000;
- if(!(pDDR_Reg->PPCFG & 1))
- {
- pPHY_Reg->DATX8[2].DXDLLCR &= ~0x80000000;
- pPHY_Reg->DATX8[3].DXDLLCR &= ~0x80000000;
- }
- pPHY_Reg->PIR &= ~DLLBYP;
- }
-}
-
-static __sramdata uint32_t clkr;
-static __sramdata uint32_t clkf;
-static __sramdata uint32_t clkod;
-
-static __sramdata uint32_t dpllvaluel=0,gpllvaluel=0;
-static __sramdata uint32_t ddr_select_gpll_div=0; // 0-Disable, 1-1:1, 2-2:1, 4-4:1
-
-static __sramdata bool ddr_soc_is_rk3188_plus=false;
-
-typedef enum PLL_ID_Tag
-{
- APLL=0,
- DPLL,
- CPLL,
- GPLL,
- PLL_MAX
-}PLL_ID;
-
-uint32_t __sramlocalfunc ddr_get_pll_freq(PLL_ID pll_id) //APLL-1;CPLL-2;DPLL-3;GPLL-4
-{
- uint32_t ret = 0;
-
- // freq = (Fin/NR)*NF/OD
- if(((pCRU_Reg->CRU_MODE_CON>>(pll_id*4))&3) == 1) // DPLL Normal mode
- ret= 24 *((pCRU_Reg->CRU_PLL_CON[pll_id][1]&0xffff)+1) // NF = 2*(CLKF+1)
- /((((pCRU_Reg->CRU_PLL_CON[pll_id][0]>>8)&0x3f)+1) // NR = CLKR+1
- *((pCRU_Reg->CRU_PLL_CON[pll_id][0]&0x3F)+1)); // OD = 2^CLKOD
- else
- ret = 24;
-
- return ret;
-}
-
-static __sramdata bool ddr_rk3188_dpll_is_good=true;
-#if defined(CONFIG_ARCH_RK3188)
-bool ddr_get_dpll_status(void) //CPLL or DPLL bad rerurn false;good return true;
-{
- if (rk_pll_flag() & 0x3)
- return false;
- else
- return true;
-}
-#endif
-
-#if defined(CONFIG_ARCH_RK30)
-/*****************************************
-NR NO NF Fout freq Step finally use
-1 8 12.5 - 62.5 37.5MHz - 187.5MHz 3MHz 50MHz <= 150MHz
-1 6 12.5 - 62.5 50MHz - 250MHz 4MHz 150MHz <= 200MHz
-1 4 12.5 - 62.5 75MHz - 375MHz 6MHz 200MHz <= 300MHz
-1 2 12.5 - 62.5 150MHz - 750MHz 12MHz 300MHz <= 600MHz
-1 1 12.5 - 62.5 300MHz - 1500MHz 24MHz 600MHz <= 1200MHz
-******************************************/
-uint32_t __sramlocalfunc ddr_set_pll_3066(uint32_t nMHz, uint32_t set)
-{
- uint32_t ret = 0;
- int delay = 1000;
- uint32_t pll_id=1; //DPLL
- //NOÒ»¶¨ÒªÅ¼Êý,NR¾¡Á¿Ð¡£¬jitter¾Í»áС
-
- if(nMHz == 24)
- {
- ret = 24;
- goto out;
- }
-
- if(!set)
- {
- if(nMHz <= 150)
- {
- clkod = 8;
- }
- else if(nMHz <= 200)
- {
- clkod = 6;
- }
- else if(nMHz <= 300)
- {
- clkod = 4;
- }
- else if(nMHz <= 600)
- {
- clkod = 2;
- }
- else
- {
- clkod = 1;
- }
- clkr = 1;
- clkf=(nMHz*clkr*clkod)/24;
- ret = (24*clkf)/(clkr*clkod);
- }
- else
- {
- pCRU_Reg->CRU_MODE_CON = (0x3<<((pll_id*4) + 16)) | (0x0<<(pll_id*4)); //PLL slow-mode
- dsb();
- pCRU_Reg->CRU_PLL_CON[pll_id][3] = PLL_RESET;
- pCRU_Reg->CRU_PLL_CON[pll_id][0] = NR(clkr) | NO(clkod);
- pCRU_Reg->CRU_PLL_CON[pll_id][1] = NF(clkf);
- pCRU_Reg->CRU_PLL_CON[pll_id][2] = NB(clkf>>1);
- ddr_delayus(1);
- pCRU_Reg->CRU_PLL_CON[pll_id][3] = PLL_DE_RESET;
- dsb();
- while (delay > 0)
- {
- ddr_delayus(1);
- if (pGRF_Reg->GRF_SOC_STATUS0 & (0x1<<4))
- break;
- delay--;
- }
- pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
- | (0x0<<8) //clk_ddr_src = DDR PLL
- | 0; //clk_ddr_src:clk_ddrphy = 1:1
-
- pCRU_Reg->CRU_MODE_CON = (0x3<<((pll_id*4) + 16)) | (0x1<<(pll_id*4)); //PLL normal
- dsb();
- }
-out:
- return ret;
-}
-#endif
-
-/*****************************************
-RK3066B
-NR NO NF Fout freq Step finally use
-1 14 46 - 91 78MHz - 157MHz 1.7MHz 78MHz<= 150MHz
-1 8 46 - 91 137MHz - 275MHz 3MHz 150MHz<= 200MHz
-1 6 46 - 91 183MHz - 366MHz 4MHz 200MHz<= 300MHz
-1 4 46 - 91 275MHz - 550MHz 6MHz 300MHz<= 550MHz
-1 2 46 - 91 550MHz - 1100MHz 12MHz 550MHz<= 1100MHz
-1 1 46 - 91 1100MHz - 2200MHz 24MHz 1100MHz<= 2200MHz
-******************************************/
-uint32_t __sramlocalfunc ddr_set_pll_rk3066b(uint32_t nMHz, uint32_t set)
-{
- uint32_t ret = 0;
- int delay = 1000;
- uint32_t pll_id=1; //DPLL
-
- if(nMHz == 24)
- {
- ret = 24;
- goto out;
- }
-
- if(!set)
- {
- dpllvaluel = ddr_get_pll_freq(DPLL);
- gpllvaluel = ddr_get_pll_freq(GPLL);
-
- if(ddr_rk3188_dpll_is_good == false) //if rk3188 DPLL is bad,use GPLL
- {
- if( (gpllvaluel < 200) ||(gpllvaluel > 2000))
- {
- ddr_print("DPLL is bad and GPLL freq = %dMHz,Not suitable for ddr_clock\n",gpllvaluel);
- return 0;
- }
-
- if(gpllvaluel > 1000) //GPLL:1000MHz-2000MHz
- {
- ddr_select_gpll_div=4; //DDR_CLCOK:250MHz-500MHz
- }
- else if(gpllvaluel > 800) //GPLL:800MHz-1000MHz
- {
- if(nMHz > 250)
- ddr_select_gpll_div=2; //DDR_CLCOK:400MHz-500MHz
- else
- ddr_select_gpll_div=4; //DDR_CLCOK:200MHz-250MHz
- }
- else if(gpllvaluel > 500) //GPLL:500MHz-800MHz
- {
- ddr_select_gpll_div=2; //DDR_CLCOK:250MHz-400MHz
- }
- else //GPLL:200MHz-500MHz
- {
- ddr_select_gpll_div=1; //DDR_CLCOK:200MHz-500MHz
- }
- }
-
- if(ddr_select_gpll_div > 0)
- {
- if(ddr_select_gpll_div == 4)
- ret = gpllvaluel/4;
- else if(ddr_select_gpll_div == 2)
- ret = gpllvaluel/2;
- else
- ret=gpllvaluel;
- }
- else
- {
- if(nMHz <= 150)
- {
- clkod = 14;
- }
- else if(nMHz <= 200)
- {
- clkod = 8;
- }
- else if(nMHz <= 300)
- {
- clkod = 6;
- }
- else if(nMHz <= 550)
- {
- clkod = 4;
- }
- else if(nMHz <= 1100)
- {
- clkod = 2;
- }
- else
- {
- clkod = 1;
- }
- clkr = 1;
- clkf=(nMHz*clkr*clkod)/24;
- ret = (24*clkf)/(clkr*clkod);
- }
-
- }
- else
- {
- if(ddr_select_gpll_div > 0)
- {
- if(ddr_select_gpll_div == 4)
- {
- pCRU_Reg->CRU_CLKGATE_CON[1] = 0x00800000;
- pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
- | (0x1<<8) //clk_ddr_src = G PLL
- | 2; //clk_ddr_src:clk_ddrphy = 4:1
- dsb();
- }
- else if(ddr_select_gpll_div == 2)
- {
- pCRU_Reg->CRU_CLKGATE_CON[1] = 0x00800000;
- pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
- | (0x1<<8) //clk_ddr_src = G PLL
- | 1; //clk_ddr_src:clk_ddrphy = 2:1
- dsb();
- }
- else
- {
- pCRU_Reg->CRU_CLKGATE_CON[1] = 0x00800000;
- pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
- | (0x1<<8) //clk_ddr_src = G PLL
- | 0; //clk_ddr_src:clk_ddrphy = 1:1
- dsb();
- }
- }
- else if((nMHz==dpllvaluel) && (set == 1))
- {
- // ddr_pll_clk: clk_ddr=1:1
- pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
- | (0x0<<8) //clk_ddr_src = DDR PLL
- | 0; //clk_ddr_src:clk_ddrphy = 1:1
- dsb();
- }
- else
- {
- pCRU_Reg->CRU_MODE_CON = (0x3<<((pll_id*4) + 16)) | (0x0<<(pll_id*4)); //PLL slow-mode
- dsb();
-
- pCRU_Reg->CRU_PLL_CON[pll_id][3] = PLL_RESET_RK3066B;
- ddr_delayus(1);
- pCRU_Reg->CRU_PLL_CON[pll_id][0] = NR_RK3066B(clkr) | NO_RK3066B(clkod);
- pCRU_Reg->CRU_PLL_CON[pll_id][1] = NF_RK3066B(clkf);
- // pCRU_Reg->CRU_PLL_CON[pll_id][2] = NB(clkf>>1);
- ddr_delayus(1);
- pCRU_Reg->CRU_PLL_CON[pll_id][3] = PLL_DE_RESET_RK3066B;
- dsb();
- while (delay > 0)
- {
- ddr_delayus(1);
- if (pGRF_Reg_RK3066B->GRF_SOC_STATUS0 & (0x1<<5))
- break;
- delay--;
- }
-
- if(set == 1)
- pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
- | (0x0<<8) //clk_ddr_src = DDR PLL
- | 0; //clk_ddr_src:clk_ddrphy = 1:1
-
- pCRU_Reg->CRU_MODE_CON = (0x3<<((pll_id*4) + 16)) | (0x1<<(pll_id*4)); //PLL normal
- dsb();
- }
- }
- dsb();
-out:
- return ret;
-}
-
-/*****************************************
-NR NO NF Fout freq Step finally use
-1 8 12.5 - 62.5 37.5MHz - 187.5MHz 3MHz 50MHz <= 150MHz
-1 6 12.5 - 62.5 50MHz - 250MHz 4MHz 150MHz <= 200MHz
-1 4 12.5 - 62.5 75MHz - 375MHz 6MHz 200MHz <= 300MHz
-1 2 12.5 - 62.5 150MHz - 750MHz 12MHz 300MHz <= 600MHz
-1 1 12.5 - 62.5 300MHz - 1500MHz 24MHz 600MHz <= 1200MHz
-******************************************/
-uint32_t __sramlocalfunc ddr_set_pll_rk3188_plus(uint32_t nMHz, uint32_t set)
-{
- uint32_t ret = 0;
- int delay = 1000;
- uint32_t pll_id=1; //DPLL
-
- if(nMHz == 24)
- {
- ret = 24;
- goto out;
- }
-
- if(!set)
- {
- dpllvaluel = ddr_get_pll_freq(DPLL);
- gpllvaluel = ddr_get_pll_freq(GPLL);
-
- if(ddr_select_gpll_div > 0)
- {
- if(ddr_select_gpll_div == 4)
- ret = gpllvaluel/4;
- else if(ddr_select_gpll_div == 2)
- ret = gpllvaluel/2;
- else
- ret=gpllvaluel;
- }
- else
- {
- if(nMHz <= 150)
- {
- clkod = 8;
- }
- else if(nMHz <= 200)
- {
- clkod = 6;
- }
- else if(nMHz <= 300)
- {
- clkod = 4;
- }
- else if(nMHz <= 600)
- {
- clkod = 2;
- }
- else
- {
- clkod = 1;
- }
- clkr = 1;
- clkf=(nMHz*clkr*clkod)/24;
- ret = (24*clkf)/(clkr*clkod);
- }
-
- }
- else
- {
- if(ddr_select_gpll_div > 0)
- {
- if(ddr_select_gpll_div == 4)
- {
- pCRU_Reg->CRU_CLKGATE_CON[1] = 0x00800000;
- pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
- | (0x1<<8) //clk_ddr_src = G PLL
- | 2; //clk_ddr_src:clk_ddrphy = 4:1
- dsb();
- }
- if(ddr_select_gpll_div == 2)
- {
- pCRU_Reg->CRU_CLKGATE_CON[1] = 0x00800000;
- pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
- | (0x1<<8) //clk_ddr_src = G PLL
- | 1; //clk_ddr_src:clk_ddrphy = 2:1
- dsb();
- }
- else
- {
- pCRU_Reg->CRU_CLKGATE_CON[1] = 0x00800000;
- pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
- | (0x1<<8) //clk_ddr_src = G PLL
- | 0; //clk_ddr_src:clk_ddrphy = 1:1
- dsb();
- }
- }
- else if((nMHz==dpllvaluel) && (set == 1))
- {
- // ddr_pll_clk: clk_ddr=1:1
- pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
- | (0x0<<8) //clk_ddr_src = DDR PLL
- | 0; //clk_ddr_src:clk_ddrphy = 1:1
- dsb();
- }
- else
- {
- pCRU_Reg->CRU_MODE_CON = (0x3<<((pll_id*4) + 16)) | (0x0<<(pll_id*4)); //PLL slow-mode
- dsb();
-
- pCRU_Reg->CRU_PLL_CON[pll_id][3] = PLL_RESET;
- ddr_delayus(1);
- pCRU_Reg->CRU_PLL_CON[pll_id][0] = NR(clkr) | NO(clkod);
- pCRU_Reg->CRU_PLL_CON[pll_id][1] = NF(clkf);
- pCRU_Reg->CRU_PLL_CON[pll_id][2] = NB(clkf>>1);
- ddr_delayus(1);
- pCRU_Reg->CRU_PLL_CON[pll_id][3] = PLL_DE_RESET;
- dsb();
- while (delay > 0)
- {
- ddr_delayus(1);
- if (pGRF_Reg_RK3066B->GRF_SOC_STATUS0 & (0x1<<5))
- break;
- delay--;
- }
-
- if(set == 1)
- pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
- | (0x0<<8) //clk_ddr_src = DDR PLL
- | 0; //clk_ddr_src:clk_ddrphy = 1:1
-
- pCRU_Reg->CRU_MODE_CON = (0x3<<((pll_id*4) + 16)) | (0x1<<(pll_id*4)); //PLL normal
- dsb();
- }
- }
- dsb();
-out:
- return ret;
-}
-
-uint32_t __sramlocalfunc ddr_set_pll(uint32_t nMHz, uint32_t set)
-{
-#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
- if(ddr_soc_is_rk3188_plus == true)
- return ddr_set_pll_rk3188_plus(nMHz,set);
- else
- return ddr_set_pll_rk3066b(nMHz,set);
-#else
- return ddr_set_pll_3066(nMHz,set);
-#endif
-}
-
-uint32_t ddr_get_parameter(uint32_t nMHz)
-{
- uint32_t tmp;
- uint32_t ret = 0;
- uint32_t al;
- uint32_t bl,bl_tmp;
- uint32_t cl;
- uint32_t cwl;
- PCTL_TIMING_T *p_pctl_timing=&(ddr_reg.pctl.pctl_timing);
- PHY_TIMING_T *p_publ_timing=&(ddr_reg.publ.phy_timing);
- NOC_TIMING_T *p_noc_timing=&(ddr_reg.noc_timing);
-
- p_pctl_timing->togcnt1u = nMHz;
- p_pctl_timing->togcnt100n = nMHz/10;
- p_pctl_timing->tinit = 200;
- p_pctl_timing->trsth = 500;
-
- if(mem_type == DDR3)
- {
- if(ddr_speed_bin > DDR3_DEFAULT){
- ret = -1;
- goto out;
- }
-
- #define DDR3_tREFI_7_8_us (78) //unit 100ns
- #define DDR3_tMRD (4) //tCK
- #define DDR3_tRFC_512Mb (90) //ns
- #define DDR3_tRFC_1Gb (110) //ns
- #define DDR3_tRFC_2Gb (160) //ns
- #define DDR3_tRFC_4Gb (300) //ns
- #define DDR3_tRFC_8Gb (350) //ns
- #define DDR3_tRTW (2) //register min valid value
- #define DDR3_tRAS (37) //ns
- #define DDR3_tRRD (10) //ns
- #define DDR3_tRTP (7) //ns
- #define DDR3_tWR (15) //ns
- #define DDR3_tWTR (7) //ns
- #define DDR3_tXP (7) //ns
- #define DDR3_tXPDLL (24) //ns
- #define DDR3_tZQCS (80) //ns
- #define DDR3_tZQCSI (0) //ns
- #define DDR3_tDQS (1) //tCK
- #define DDR3_tCKSRE (10) //ns
- #define DDR3_tCKE_400MHz (7) //ns
- #define DDR3_tCKE_533MHz (6) //ns
- #define DDR3_tMOD (15) //ns
- #define DDR3_tRSTL (100) //ns
- #define DDR3_tZQCL (320) //ns
- #define DDR3_tDLLK (512) //tCK
-
- al = 0;
- bl = 8;
- if(nMHz <= 330)
- {
- tmp = 0;
- }
- else if(nMHz<=400)
- {
- tmp = 1;
- }
- else if(nMHz<=533)
- {
- tmp = 2;
- }
- else //666MHz
- {
- tmp = 3;
- }
- if(nMHz < DDR3_DDR2_ODT_DLL_DISABLE_FREQ) //when dll bypss cl = cwl = 6;
- {
- cl = 6;
- cwl = 6;
- }
- else
- {
- cl = (ddr3_cl_cwl[ddr_speed_bin][tmp] >> 4)&0xf;
- cwl = ddr3_cl_cwl[ddr_speed_bin][tmp] & 0xf;
- }
- if(cl == 0)
- ret = -4;
- if(nMHz <= DDR3_DDR2_ODT_DLL_DISABLE_FREQ)
- {
- p_publ_timing->mr[1] = DDR3_DS_40 | DDR3_Rtt_Nom_DIS;
- }
- else
- {
- p_publ_timing->mr[1] = DDR3_DS_40 | DDR3_Rtt_Nom_120;
- }
- p_publ_timing->mr[2] = DDR3_MR2_CWL(cwl) /* | DDR3_Rtt_WR_60 */;
- p_publ_timing->mr[3] = 0;
- /**************************************************
- * PCTL Timing
- **************************************************/
- /*
- * tREFI, average periodic refresh interval, 7.8us
- */
- p_pctl_timing->trefi = DDR3_tREFI_7_8_us;
- /*
- * tMRD, 4 tCK
- */
- p_pctl_timing->tmrd = DDR3_tMRD & 0x7;
- p_publ_timing->dtpr0.b.tMRD = DDR3_tMRD-4;
- /*
- * tRFC, 90ns(512Mb),110ns(1Gb),160ns(2Gb),300ns(4Gb),350ns(8Gb)
- */
- if(ddr_capability_per_die <= 0x4000000) // 512Mb 90ns
- {
- tmp = DDR3_tRFC_512Mb;
- }
- else if(ddr_capability_per_die <= 0x8000000) // 1Gb 110ns
- {
- tmp = DDR3_tRFC_1Gb;
- }
- else if(ddr_capability_per_die <= 0x10000000) // 2Gb 160ns
- {
- tmp = DDR3_tRFC_2Gb;
- }
- else if(ddr_capability_per_die <= 0x20000000) // 4Gb 300ns
- {
- tmp = DDR3_tRFC_4Gb;
- }
- else // 8Gb 350ns
- {
- tmp = DDR3_tRFC_8Gb;
- }
- p_pctl_timing->trfc = (tmp*nMHz+999)/1000;
- p_publ_timing->dtpr1.b.tRFC = ((tmp*nMHz+999)/1000)&0xFF;
- /*
- * tXSR, =tDLLK=512 tCK
- */
- p_pctl_timing->texsr = DDR3_tDLLK;
- p_publ_timing->dtpr2.b.tXS = DDR3_tDLLK;
- /*
- * tRP=CL
- */
- p_pctl_timing->trp = cl;
- p_publ_timing->dtpr0.b.tRP = cl;
- /*
- * WrToMiss=WL*tCK + tWR + tRP + tRCD
- */
- p_noc_timing->b.WrToMiss = ((cwl+((DDR3_tWR*nMHz+999)/1000)+cl+cl)&0x3F);
- /*
- * tRC=tRAS+tRP
- */
- p_pctl_timing->trc = ((((ddr3_tRC_tFAW[ddr_speed_bin]>>8)*nMHz+999)/1000)&0x3F);
- p_noc_timing->b.ActToAct = ((((ddr3_tRC_tFAW[ddr_speed_bin]>>8)*nMHz+999)/1000)&0x3F);
- p_publ_timing->dtpr0.b.tRC = (((ddr3_tRC_tFAW[ddr_speed_bin]>>8)*nMHz+999)/1000)&0xF;
-
- p_pctl_timing->trtw = (cl+2-cwl);//DDR3_tRTW;
- p_publ_timing->dtpr1.b.tRTW = 0;
- p_noc_timing->b.RdToWr = ((cl+2-cwl)&0x1F);
- p_pctl_timing->tal = al;
- p_pctl_timing->tcl = cl;
- p_pctl_timing->tcwl = cwl;
- /*
- * tRAS, 37.5ns(400MHz) 37.5ns(533MHz)
- */
- p_pctl_timing->tras = (((DDR3_tRAS*nMHz+(nMHz>>1)+999)/1000)&0x3F);
- p_publ_timing->dtpr0.b.tRAS = ((DDR3_tRAS*nMHz+(nMHz>>1)+999)/1000)&0x1F;
- /*
- * tRCD=CL
- */
- p_pctl_timing->trcd = cl;
- p_publ_timing->dtpr0.b.tRCD = cl;
- /*
- * tRRD = max(4nCK, 7.5ns), DDR3-1066(1K), DDR3-1333(2K), DDR3-1600(2K)
- * max(4nCK, 10ns), DDR3-800(1K,2K), DDR3-1066(2K)
- * max(4nCK, 6ns), DDR3-1333(1K), DDR3-1600(1K)
- *
- */
- tmp = ((DDR3_tRRD*nMHz+999)/1000);
- if(tmp < 4)
- {
- tmp = 4;
- }
- p_pctl_timing->trrd = (tmp&0xF);
- p_publ_timing->dtpr0.b.tRRD = tmp&0xF;
- /*
- * tRTP, max(4 tCK,7.5ns)
- */
- tmp = ((DDR3_tRTP*nMHz+(nMHz>>1)+999)/1000);
- if(tmp < 4)
- {
- tmp = 4;
- }
- p_pctl_timing->trtp = tmp&0xF;
- p_publ_timing->dtpr0.b.tRTP = tmp;
- /*
- * RdToMiss=tRTP+tRP + tRCD - (BL/2 * tCK)
- */
- p_noc_timing->b.RdToMiss = ((tmp+cl+cl-(bl>>1))&0x3F);
- /*
- * tWR, 15ns
- */
- tmp = ((DDR3_tWR*nMHz+999)/1000);
- p_pctl_timing->twr = tmp&0x1F;
- if(tmp<9)
- tmp = tmp - 4;
- else
- tmp = tmp>>1;
- bl_tmp = (bl == 8) ? DDR3_BL8 : DDR3_BC4;
- p_publ_timing->mr[0] = bl_tmp | DDR3_CL(cl) | DDR3_WR(tmp);
-
- /*
- * tWTR, max(4 tCK,7.5ns)
- */
- tmp = ((DDR3_tWTR*nMHz+(nMHz>>1)+999)/1000);
- if(tmp < 4)
- {
- tmp = 4;
- }
- p_pctl_timing->twtr = tmp&0xF;
- p_publ_timing->dtpr0.b.tWTR = tmp&0x7;
- p_noc_timing->b.WrToRd = ((tmp+cwl)&0x1F);
- /*
- * tXP, max(3 tCK, 7.5ns)(<933MHz)
- */
- tmp = ((DDR3_tXP*nMHz+(nMHz>>1)+999)/1000);
- if(tmp < 3)
- {
- tmp = 3;
- }
- p_pctl_timing->txp = tmp&0x7;
- /*
- * tXPDLL, max(10 tCK,24ns)
- */
- tmp = ((DDR3_tXPDLL*nMHz+999)/1000);
- if(tmp < 10)
- {
- tmp = 10;
- }
- p_pctl_timing->txpdll = tmp & 0x3F;
- p_publ_timing->dtpr2.b.tXP = tmp&0x1F;
- /*
- * tZQCS, max(64 tCK, 80ns)
- */
- tmp = ((DDR3_tZQCS*nMHz+999)/1000);
- if(tmp < 64)
- {
- tmp = 64;
- }
- p_pctl_timing->tzqcs = tmp&0x7F;
- /*
- * tZQCSI,
- */
- p_pctl_timing->tzqcsi = DDR3_tZQCSI;
- /*
- * tDQS,
- */
- p_pctl_timing->tdqs = DDR3_tDQS;
- /*
- * tCKSRE, max(5 tCK, 10ns)
- */
- tmp = ((DDR3_tCKSRE*nMHz+999)/1000);
- if(tmp < 5)
- {
- tmp = 5;
- }
- p_pctl_timing->tcksre = tmp & 0x1F;
- /*
- * tCKSRX, max(5 tCK, 10ns)
- */
- p_pctl_timing->tcksrx = tmp & 0x1F;
- /*
- * tCKE, max(3 tCK,7.5ns)(400MHz) max(3 tCK,5.625ns)(533MHz)
- */
- if(nMHz>=533)
- {
- tmp = ((DDR3_tCKE_533MHz*nMHz+999)/1000);
- }
- else
- {
- tmp = ((DDR3_tCKE_400MHz*nMHz+(nMHz>>1)+999)/1000);
- }
- if(tmp < 3)
- {
- tmp = 3;
- }
- p_pctl_timing->tcke = tmp & 0x7;
- p_publ_timing->dtpr2.b.tCKE = tmp;
- /*
- * tCKESR, =tCKE + 1tCK
- */
- p_pctl_timing->tckesr = (tmp+1)&0xF;
- /*
- * tMOD, max(12 tCK,15ns)
- */
- tmp = ((DDR3_tMOD*nMHz+999)/1000);
- if(tmp < 12)
- {
- tmp = 12;
- }
- p_pctl_timing->tmod = tmp&0x1F;
- p_publ_timing->dtpr1.b.tMOD = tmp;
- /*
- * tRSTL, 100ns
- */
- p_pctl_timing->trstl = ((DDR3_tRSTL*nMHz+999)/1000)&0x7F;
- /*
- * tZQCL, max(256 tCK, 320ns)
- */
- tmp = ((DDR3_tZQCL*nMHz+999)/1000);
- if(tmp < 256)
- {
- tmp = 256;
- }
- p_pctl_timing->tzqcl = tmp&0x3FF;
- /*
- * tMRR, 0 tCK
- */
- p_pctl_timing->tmrr = 0;
- /*
- * tDPD, 0
- */
- p_pctl_timing->tdpd = 0;
-
- /**************************************************
- * PHY Timing
- **************************************************/
- /*
- * tCCD, BL/2 for DDR2 and 4 for DDR3
- */
- p_publ_timing->dtpr0.b.tCCD = 0;
- /*
- * tDQSCKmax,5.5ns
- */
- p_publ_timing->dtpr1.b.tDQSCKmax = 0;
- /*
- * tRTODT, 0:ODT may be turned on immediately after read post-amble
- * 1:ODT may not be turned on until one clock after the read post-amble
- */
- p_publ_timing->dtpr1.b.tRTODT = 1;
- /*
- * tFAW,40ns(400MHz 1KB page) 37.5ns(533MHz 1KB page) 50ns(400MHz 2KB page) 50ns(533MHz 2KB page)
- */
- p_publ_timing->dtpr1.b.tFAW = (((ddr3_tRC_tFAW[ddr_speed_bin]&0x0ff)*nMHz+999)/1000)&0x7F;
- /*
- * tAOND_tAOFD
- */
- p_publ_timing->dtpr1.b.tAOND = 0;
- /*
- * tDLLK,512 tCK
- */
- p_publ_timing->dtpr2.b.tDLLK = DDR3_tDLLK;
- /**************************************************
- * NOC Timing
- **************************************************/
- p_noc_timing->b.BurstLen = ((bl>>1)&0x7);
- }
- else if(mem_type == LPDDR2)
- {
- #define LPDDR2_tREFI_3_9_us (38) //unit 100ns
- #define LPDDR2_tREFI_7_8_us (78) //unit 100ns
- #define LPDDR2_tMRD (5) //tCK
- #define LPDDR2_tRFC_8Gb (210) //ns
- #define LPDDR2_tRFC_4Gb (130) //ns
- #define LPDDR2_tRP_4_BANK (24) //ns
- #define LPDDR2_tRPab_SUB_tRPpb_4_BANK (0)
- #define LPDDR2_tRP_8_BANK (27) //ns
- #define LPDDR2_tRPab_SUB_tRPpb_8_BANK (3)
- #define LPDDR2_tRTW (1) //tCK register min valid value
- #define LPDDR2_tRAS (42) //ns
- #define LPDDR2_tRCD (24) //ns
- #define LPDDR2_tRRD (10) //ns
- #define LPDDR2_tRTP (7) //ns
- #define LPDDR2_tWR (15) //ns
- #define LPDDR2_tWTR_GREAT_200MHz (7) //ns
- #define LPDDR2_tWTR_LITTLE_200MHz (10) //ns
- #define LPDDR2_tXP (7) //ns
- #define LPDDR2_tXPDLL (0)
- #define LPDDR2_tZQCS (90) //ns
- #define LPDDR2_tZQCSI (0)
- #define LPDDR2_tDQS (1)
- #define LPDDR2_tCKSRE (1) //tCK
- #define LPDDR2_tCKSRX (2) //tCK
- #define LPDDR2_tCKE (3) //tCK
- #define LPDDR2_tMOD (0)
- #define LPDDR2_tRSTL (0)
- #define LPDDR2_tZQCL (360) //ns
- #define LPDDR2_tMRR (2) //tCK
- #define LPDDR2_tCKESR (15) //ns
- #define LPDDR2_tDPD_US (500)
- #define LPDDR2_tFAW_GREAT_200MHz (50) //ns
- #define LPDDR2_tFAW_LITTLE_200MHz (60) //ns
- #define LPDDR2_tDLLK (2) //tCK
- #define LPDDR2_tDQSCK_MAX (3) //tCK
- #define LPDDR2_tDQSCK_MIN (0) //tCK
- #define LPDDR2_tDQSS (1) //tCK
-
- uint32 trp_tmp;
- uint32 trcd_tmp;
- uint32 tras_tmp;
- uint32 trtp_tmp;
- uint32 twr_tmp;
-
- al = 0;
- if(nMHz>=200)
- {
- bl = 4; //you can change burst here
- }
- else
- {
- bl = 8; // freq < 200MHz, BL fixed 8
- }
- /* 1066 933 800 667 533 400 333
- * RL, 8 7 6 5 4 3 3
- * WL, 4 4 3 2 2 1 1
- */
- if(nMHz<=200)
- {
- cl = 3;
- cwl = 1;
- p_publ_timing->mr[2] = LPDDR2_RL3_WL1;
- }
- else if(nMHz<=266)
- {
- cl = 4;
- cwl = 2;
- p_publ_timing->mr[2] = LPDDR2_RL4_WL2;
- }
- else if(nMHz<=333)
- {
- cl = 5;
- cwl = 2;
- p_publ_timing->mr[2] = LPDDR2_RL5_WL2;
- }
- else if(nMHz<=400)
- {
- cl = 6;
- cwl = 3;
- p_publ_timing->mr[2] = LPDDR2_RL6_WL3;
- }
- else if(nMHz<=466)
- {
- cl = 7;
- cwl = 4;
- p_publ_timing->mr[2] = LPDDR2_RL7_WL4;
- }
- else //(nMHz<=1066)
- {
- cl = 8;
- cwl = 4;
- p_publ_timing->mr[2] = LPDDR2_RL8_WL4;
- }
- p_publ_timing->mr[3] = LPDDR2_DS_34;
- p_publ_timing->mr[0] = 0;
- /**************************************************
- * PCTL Timing
- **************************************************/
- /*
- * tREFI, average periodic refresh interval, 15.6us(<256Mb) 7.8us(256Mb-1Gb) 3.9us(2Gb-8Gb)
- */
- if(ddr_capability_per_die >= 0x10000000) // 2Gb
- {
- p_pctl_timing->trefi = LPDDR2_tREFI_3_9_us;
- }
- else
- {
- p_pctl_timing->trefi = LPDDR2_tREFI_7_8_us;
- }
-
- /*
- * tMRD, (=tMRW), 5 tCK
- */
- p_pctl_timing->tmrd = LPDDR2_tMRD & 0x7;
- p_publ_timing->dtpr0.b.tMRD = 3;
- /*
- * tRFC, 90ns(<=512Mb) 130ns(1Gb-4Gb) 210ns(8Gb)
- */
- if(ddr_capability_per_die >= 0x40000000) // 8Gb
- {
- p_pctl_timing->trfc = (LPDDR2_tRFC_8Gb*nMHz+999)/1000;
- p_publ_timing->dtpr1.b.tRFC = ((LPDDR2_tRFC_8Gb*nMHz+999)/1000)&0xFF;
- /*
- * tXSR, max(2tCK,tRFC+10ns)
- */
- tmp=(((LPDDR2_tRFC_8Gb+10)*nMHz+999)/1000);
- }
- else
- {
- p_pctl_timing->trfc = (LPDDR2_tRFC_4Gb*nMHz+999)/1000;
- p_publ_timing->dtpr1.b.tRFC = ((LPDDR2_tRFC_4Gb*nMHz+999)/1000)&0xFF;
- tmp=(((LPDDR2_tRFC_4Gb+10)*nMHz+999)/1000);
- }
- if(tmp<2)
- {
- tmp=2;
- }
- p_pctl_timing->texsr = tmp&0x3FF;
- p_publ_timing->dtpr2.b.tXS = tmp&0x3FF;
-
- /*
- * tRP, max(3tCK, 4-bank:15ns(Fast) 18ns(Typ) 24ns(Slow), 8-bank:18ns(Fast) 21ns(Typ) 27ns(Slow))
- */
- if(pPHY_Reg->DCR.b.DDR8BNK)
- {
- trp_tmp = ((LPDDR2_tRP_8_BANK*nMHz+999)/1000);
- if(trp_tmp<3)
- {
- trp_tmp=3;
- }
- p_pctl_timing->trp = ((((LPDDR2_tRPab_SUB_tRPpb_8_BANK*nMHz+999)/1000) & 0x3)<<16) | (trp_tmp&0xF);
- }
- else
- {
- trp_tmp = ((LPDDR2_tRP_4_BANK*nMHz+999)/1000);
- if(trp_tmp<3)
- {
- trp_tmp=3;
- }
- p_pctl_timing->trp = (LPDDR2_tRPab_SUB_tRPpb_4_BANK<<16) | (trp_tmp&0xF);
- }
- p_publ_timing->dtpr0.b.tRP = trp_tmp;
- /*
- * tRAS, max(3tCK,42ns)
- */
- tras_tmp=((LPDDR2_tRAS*nMHz+999)/1000);
- if(tras_tmp<3)
- {
- tras_tmp=3;
- }
- p_pctl_timing->tras = (tras_tmp&0x3F);
- p_publ_timing->dtpr0.b.tRAS = tras_tmp&0x1F;
-
- /*
- * tRCD, max(3tCK, 15ns(Fast) 18ns(Typ) 24ns(Slow))
- */
- trcd_tmp = ((LPDDR2_tRCD*nMHz+999)/1000);
- if(trcd_tmp<3)
- {
- trcd_tmp=3;
- }
- p_pctl_timing->trcd = (trcd_tmp&0xF);
- p_publ_timing->dtpr0.b.tRCD = trcd_tmp&0xF;
-
- /*
- * tRTP, max(2tCK, 7.5ns)
- */
- trtp_tmp = ((LPDDR2_tRTP*nMHz+(nMHz>>1)+999)/1000);
- if(trtp_tmp<2)
- {
- trtp_tmp = 2;
- }
- p_pctl_timing->trtp = trtp_tmp&0xF;
- p_publ_timing->dtpr0.b.tRTP = trtp_tmp;
-
- /*
- * tWR, max(3tCK,15ns)
- */
- twr_tmp=((LPDDR2_tWR*nMHz+999)/1000);
- if(twr_tmp<3)
- {
- twr_tmp=3;
- }
- p_pctl_timing->twr = twr_tmp&0x1F;
- bl_tmp = (bl == 16) ? LPDDR2_BL16 : ((bl == 8) ? LPDDR2_BL8 : LPDDR2_BL4);
- p_publ_timing->mr[1] = bl_tmp | LPDDR2_nWR(twr_tmp);
-
- /*
- * WrToMiss=WL*tCK + tDQSS + tWR + tRP + tRCD
- */
- p_noc_timing->b.WrToMiss = ((cwl+LPDDR2_tDQSS+twr_tmp+trp_tmp+trcd_tmp)&0x3F);
- /*
- * RdToMiss=tRTP + tRP + tRCD - (BL/2 * tCK)
- */
- p_noc_timing->b.RdToMiss = ((trtp_tmp+trp_tmp+trcd_tmp-(bl>>1))&0x3F);
- /*
- * tRC=tRAS+tRP
- */
- p_pctl_timing->trc = ((tras_tmp+trp_tmp)&0x3F);
- p_noc_timing->b.ActToAct = ((tras_tmp+trp_tmp)&0x3F);
- p_publ_timing->dtpr0.b.tRC = (tras_tmp+trp_tmp)&0xF;
-
- /*
- * RdToWr=RL+tDQSCK-WL
- */
- p_pctl_timing->trtw = (cl+LPDDR2_tDQSCK_MAX+(bl/2)+1-cwl);//LPDDR2_tRTW;
- p_publ_timing->dtpr1.b.tRTW = 0;
- p_noc_timing->b.RdToWr = ((cl+LPDDR2_tDQSCK_MAX+1-cwl)&0x1F);
- p_pctl_timing->tal = al;
- p_pctl_timing->tcl = cl;
- p_pctl_timing->tcwl = cwl;
- /*
- * tRRD, max(2tCK,10ns)
- */
- tmp=((LPDDR2_tRRD*nMHz+999)/1000);
- if(tmp<2)
- {
- tmp=2;
- }
- p_pctl_timing->trrd = (tmp&0xF);
- p_publ_timing->dtpr0.b.tRRD = tmp&0xF;
- /*
- * tWTR, max(2tCK, 7.5ns(533-266MHz) 10ns(200-166MHz))
- */
- if(nMHz > 200)
- {
- tmp=((LPDDR2_tWTR_GREAT_200MHz*nMHz+(nMHz>>1)+999)/1000);
- }
- else
- {
- tmp=((LPDDR2_tWTR_LITTLE_200MHz*nMHz+999)/1000);
- }
- if(tmp<2)
- {
- tmp=2;
- }
- p_pctl_timing->twtr = tmp&0xF;
- p_publ_timing->dtpr0.b.tWTR = tmp&0x7;
- /*
- * WrToRd=WL+tDQSS+tWTR
- */
- p_noc_timing->b.WrToRd = ((cwl+LPDDR2_tDQSS+tmp)&0x1F);
- /*
- * tXP, max(2tCK,7.5ns)
- */
- tmp=((LPDDR2_tXP*nMHz+(nMHz>>1)+999)/1000);
- if(tmp<2)
- {
- tmp=2;
- }
- p_pctl_timing->txp = tmp&0x7;
- p_publ_timing->dtpr2.b.tXP = tmp&0x1F;
- /*
- * tXPDLL, 0ns
- */
- p_pctl_timing->txpdll = LPDDR2_tXPDLL;
- /*
- * tZQCS, 90ns
- */
- p_pctl_timing->tzqcs = ((LPDDR2_tZQCS*nMHz+999)/1000)&0x7F;
- /*
- * tZQCSI,
- */
- if(pDDR_Reg->MCFG &= lpddr2_s4)
- {
- p_pctl_timing->tzqcsi = LPDDR2_tZQCSI;
- }
- else
- {
- p_pctl_timing->tzqcsi = 0;
- }
- /*
- * tDQS,
- */
- p_pctl_timing->tdqs = LPDDR2_tDQS;
- /*
- * tCKSRE, 1 tCK
- */
- p_pctl_timing->tcksre = LPDDR2_tCKSRE;
- /*
- * tCKSRX, 2 tCK
- */
- p_pctl_timing->tcksrx = LPDDR2_tCKSRX;
- /*
- * tCKE, 3 tCK
- */
- p_pctl_timing->tcke = LPDDR2_tCKE;
- p_publ_timing->dtpr2.b.tCKE = LPDDR2_tCKE;
- /*
- * tMOD, 0 tCK
- */
- p_pctl_timing->tmod = LPDDR2_tMOD;
- p_publ_timing->dtpr1.b.tMOD = LPDDR2_tMOD;
- /*
- * tRSTL, 0 tCK
- */
- p_pctl_timing->trstl = LPDDR2_tRSTL;
- /*
- * tZQCL, 360ns
- */
- p_pctl_timing->tzqcl = ((LPDDR2_tZQCL*nMHz+999)/1000)&0x3FF;
- /*
- * tMRR, 2 tCK
- */
- p_pctl_timing->tmrr = LPDDR2_tMRR;
- /*
- * tCKESR, max(3tCK,15ns)
- */
- tmp = ((LPDDR2_tCKESR*nMHz+999)/1000);
- if(tmp < 3)
- {
- tmp = 3;
- }
- p_pctl_timing->tckesr = tmp&0xF;
- /*
- * tDPD, 500us
- */
- p_pctl_timing->tdpd = LPDDR2_tDPD_US;
-
- /**************************************************
- * PHY Timing
- **************************************************/
- /*
- * tCCD, BL/2 for DDR2 and 4 for DDR3
- */
- p_publ_timing->dtpr0.b.tCCD = 0;
- /*
- * tDQSCKmax,5.5ns
- */
- p_publ_timing->dtpr1.b.tDQSCKmax = LPDDR2_tDQSCK_MAX;
- /*
- * tDQSCKmin,2.5ns
- */
- p_publ_timing->dtpr1.b.tDQSCK = LPDDR2_tDQSCK_MIN;
- /*
- * tRTODT, 0:ODT may be turned on immediately after read post-amble
- * 1:ODT may not be turned on until one clock after the read post-amble
- */
- p_publ_timing->dtpr1.b.tRTODT = 1;
- /*
- * tFAW,max(8tCK, 50ns(200-533MHz) 60ns(166MHz))
- */
- if(nMHz>=200)
- {
- tmp=((LPDDR2_tFAW_GREAT_200MHz*nMHz+999)/1000);
- }
- else
- {
- tmp=((LPDDR2_tFAW_LITTLE_200MHz*nMHz+999)/1000);
- }
- if(tmp<8)
- {
- tmp=8;
- }
- p_publ_timing->dtpr1.b.tFAW = tmp&0x7F;
- /*
- * tAOND_tAOFD
- */
- p_publ_timing->dtpr1.b.tAOND = 0;
- /*
- * tDLLK,0
- */
- p_publ_timing->dtpr2.b.tDLLK = LPDDR2_tDLLK;
- /**************************************************
- * NOC Timing
- **************************************************/
- p_noc_timing->b.BurstLen = ((bl>>1)&0x7);
- }
-
-out:
- return ret;
-}
-
-uint32_t __sramlocalfunc ddr_update_timing(void)
-{
- uint32_t i,bl_tmp=0;
- PCTL_TIMING_T *p_pctl_timing=&(ddr_reg.pctl.pctl_timing);
- PHY_TIMING_T *p_publ_timing=&(ddr_reg.publ.phy_timing);
- NOC_TIMING_T *p_noc_timing=&(ddr_reg.noc_timing);
-
- ddr_copy((uint32_t *)&(pDDR_Reg->TOGCNT1U), (uint32_t*)&(p_pctl_timing->togcnt1u), 34);
- ddr_copy((uint32_t *)&(pPHY_Reg->DTPR[0]), (uint32_t*)&(p_publ_timing->dtpr0), 3);
- *(volatile uint32_t *)SysSrv_DdrTiming = p_noc_timing->d32;
- // Update PCTL BL
- if(mem_type == DDR3)
- {
- bl_tmp = ((p_publ_timing->mr[0] & 0x3) == DDR3_BL8) ? ddr2_ddr3_bl_8 : ddr2_ddr3_bl_4;
- pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~(0x1|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(5)|pd_exit_slow|pd_type(1);
- if((ddr_freq <= DDR3_DDR2_ODT_DLL_DISABLE_FREQ) && ddr_soc_is_rk3188_plus)
- {
- pDDR_Reg->DFITRDDATAEN = pDDR_Reg->TCL-3;
- }
- else
- {
- pDDR_Reg->DFITRDDATAEN = pDDR_Reg->TCL-2;
- }
- pDDR_Reg->DFITPHYWRLAT = pDDR_Reg->TCWL-1;
- }
- else if(mem_type == LPDDR2)
- {
- if(((p_publ_timing->mr[1]) & 0x7) == LPDDR2_BL8)
- {
- bl_tmp = mddr_lpddr2_bl_8;
- }
- else if(((p_publ_timing->mr[1]) & 0x7) == LPDDR2_BL4)
- {
- bl_tmp = mddr_lpddr2_bl_4;
- }
- else //if(((p_publ_timing->mr[1]) & 0x7) == LPDDR2_BL16)
- {
- bl_tmp = mddr_lpddr2_bl_16;
- }
- if(ddr_freq>=200)
- {
- pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~((0x3<<20)|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(5)|pd_exit_fast|pd_type(1);
- }
- else
- {
- pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~((0x3<<20)|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | mddr_lpddr2_bl_8 | tfaw_cfg(6)|pd_exit_fast|pd_type(1);
- }
- i = ((pPHY_Reg->DTPR[1] >> 27) & 0x7) - ((pPHY_Reg->DTPR[1] >> 24) & 0x7);
- pPHY_Reg->DSGCR = (pPHY_Reg->DSGCR & (~(0x3F<<5))) | (i<<5) | (i<<8); //tDQSCKmax-tDQSCK
- pDDR_Reg->DFITRDDATAEN = pDDR_Reg->TCL-1;
- pDDR_Reg->DFITPHYWRLAT = pDDR_Reg->TCWL;
- }
-
- return 0;
-}
-
-uint32_t __sramlocalfunc ddr_update_mr(void)
-{
- PHY_TIMING_T *p_publ_timing=&(ddr_reg.publ.phy_timing);
- uint32_t cs,dll_off;
-
- cs = ((pPHY_Reg->PGCR>>18) & 0xF);
- dll_off = (pPHY_Reg->MR[1] & DDR3_DLL_DISABLE) ? 1:0;
- ddr_copy((uint32_t *)&(pPHY_Reg->MR[0]), (uint32_t*)&(p_publ_timing->mr[0]), 4);
- if((mem_type == DDR3) || (mem_type == DDR2))
- {
- if(ddr_freq>DDR3_DDR2_ODT_DLL_DISABLE_FREQ)
- {
- if(dll_off) // off -> on
- {
- ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr((p_publ_timing->mr[1]))); //DLL enable
- ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr(((p_publ_timing->mr[0]))| DDR3_DLL_RESET)); //DLL reset
- ddr_delayus(2); //at least 200 DDR cycle
- ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
- }
- else // on -> on
- {
- ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr((p_publ_timing->mr[1])));
- ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
- }
- }
- else
- {
- pPHY_Reg->MR[1] = (((p_publ_timing->mr[1])) | DDR3_DLL_DISABLE);
- ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr(((p_publ_timing->mr[1])) | DDR3_DLL_DISABLE)); //DLL disable
- ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
- }
- ddr_send_command(cs, MRS_cmd, bank_addr(0x2) | cmd_addr((p_publ_timing->mr[2])));
- }
- else if(mem_type == LPDDR2)
- {
- ddr_send_command(cs, MRS_cmd, lpddr2_ma(0x1) | lpddr2_op((p_publ_timing->mr[1])));
- ddr_send_command(cs, MRS_cmd, lpddr2_ma(0x2) | lpddr2_op((p_publ_timing->mr[2])));
- ddr_send_command(cs, MRS_cmd, lpddr2_ma(0x3) | lpddr2_op((p_publ_timing->mr[3])));
- }
- else //mDDR
- {
- ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
- ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr((p_publ_timing->mr[2]))); //mr[2] is mDDR MR1
- }
- return 0;
-}
-
-void __sramlocalfunc ddr_update_odt(void)
-{
- uint32_t cs,tmp;
-
- //adjust DRV and ODT
- if((mem_type == DDR3) || (mem_type == DDR2))
- {
- if(ddr_freq <= DDR3_DDR2_ODT_DLL_DISABLE_FREQ)
- {
- pPHY_Reg->DATX8[0].DXGCR &= ~(0x3<<9); //dynamic RTT disable
- pPHY_Reg->DATX8[1].DXGCR &= ~(0x3<<9);
- if(!(pDDR_Reg->PPCFG & 1))
- {
- pPHY_Reg->DATX8[2].DXGCR &= ~(0x3<<9);
- pPHY_Reg->DATX8[3].DXGCR &= ~(0x3<<9);
- }
- }
- else
- {
- pPHY_Reg->DATX8[0].DXGCR |= (0x3<<9); //dynamic RTT enable
- pPHY_Reg->DATX8[1].DXGCR |= (0x3<<9);
- if(!(pDDR_Reg->PPCFG & 1))
- {
- pPHY_Reg->DATX8[2].DXGCR |= (0x3<<9);
- pPHY_Reg->DATX8[3].DXGCR |= (0x3<<9);
- }
- }
- }
- else
- {
- pPHY_Reg->DATX8[0].DXGCR &= ~(0x3<<9); //dynamic RTT disable
- pPHY_Reg->DATX8[1].DXGCR &= ~(0x3<<9);
- if(!(pDDR_Reg->PPCFG & 1))
- {
- pPHY_Reg->DATX8[2].DXGCR &= ~(0x3<<9);
- pPHY_Reg->DATX8[3].DXGCR &= ~(0x3<<9);
- }
- }
- tmp = (0x1<<28) | (0x2<<15) | (0x2<<10) | (0xb<<5) | 0xb; //DS=34ohm,ODT=171ohm
- cs = ((pPHY_Reg->PGCR>>18) & 0xF);
- if(cs > 1)
- {
- pPHY_Reg->ZQ1CR[0] = tmp;
- dsb();
- }
- pPHY_Reg->ZQ0CR[0] = tmp;
- dsb();
-}
-
-__sramfunc void ddr_adjust_config(uint32_t dram_type)
-{
- uint32 value;
- unsigned long save_sp;
- u32 i;
- volatile u32 n;
- volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
-
- //get data training address before idle port
- value = ddr_get_datatraing_addr();
-
- /** 1. Make sure there is no host access */
- flush_cache_all();
- outer_flush_all();
- flush_tlb_all();
- isb();
- DDR_SAVE_SP(save_sp);
-
- for(i=0;i<SRAM_SIZE/4096;i++)
- {
- n=temp[1024*i];
- barrier();
- }
- n= pDDR_Reg->SCFG.d32;
- n= pPHY_Reg->RIDR;
- n= pCRU_Reg->CRU_PLL_CON[0][0];
- n= pPMU_Reg->PMU_WAKEUP_CFG[0];
- n= *(volatile uint32_t *)SysSrv_DdrConf;
-#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
- n= pGRF_Reg_RK3066B->GRF_SOC_STATUS0;
-#else
- n= pGRF_Reg->GRF_SOC_STATUS0;
-#endif
- dsb();
-
- //enter config state
- ddr_move_to_Config_state();
-
- //set data training address
- pPHY_Reg->DTAR = value;
-
- //set auto power down idle
- pDDR_Reg->MCFG=(pDDR_Reg->MCFG&0xffff00ff)|(PD_IDLE<<8);
-
- //CKDV=00
- pPHY_Reg->PGCR &= ~(0x3<<12);
-
- //enable the hardware low-power interface
- pDDR_Reg->SCFG.b.hw_low_power_en = 1;
-
- if(pDDR_Reg->PPCFG & 1)
- {
- pPHY_Reg->DATX8[2].DXGCR &= ~(1); //disable byte
- pPHY_Reg->DATX8[3].DXGCR &= ~(1);
- pPHY_Reg->DATX8[2].DXDLLCR |= 0x80000000; //disable DLL
- pPHY_Reg->DATX8[3].DXDLLCR |= 0x80000000;
- }
-
- ddr_update_odt();
-
- //enter access state
- ddr_move_to_Access_state();
-
- DDR_RESTORE_SP(save_sp);
-}
-
-
-void __sramlocalfunc idle_port(void)
-{
- int i;
- uint32 clk_gate[10];
-
- //save clock gate status
- for(i=0;i<10;i++)
- clk_gate[i]=pCRU_Reg->CRU_CLKGATE_CON[i];
-
- //enable all clock gate for request idle
- for(i=0;i<10;i++)
- pCRU_Reg->CRU_CLKGATE_CON[i]=0xffff0000;
-
- if ( (pPMU_Reg->PMU_PWRDN_ST & pd_a9_0_pwr_st) == 0 )
- {
-#ifdef CONFIG_ARCH_RK3188
- pPMU_Reg->PMU_MISC_CON1 |= idle_req_dma_cfg;
- dsb();
- while( (pPMU_Reg->PMU_PWRDN_ST & idle_dma) == 0 );
-#else
- pPMU_Reg->PMU_MISC_CON1 |= idle_req_cpu_cfg;
- dsb();
- while( (pPMU_Reg->PMU_PWRDN_ST & idle_cpu) == 0 );
-#endif
- }
-
- if ( (pPMU_Reg->PMU_PWRDN_ST & pd_peri_pwr_st) == 0 )
- {
- pPMU_Reg->PMU_MISC_CON1 |= idle_req_peri_cfg;
- dsb();
- while( (pPMU_Reg->PMU_PWRDN_ST & idle_peri) == 0 );
- }
-
- if ( (pPMU_Reg->PMU_PWRDN_ST & pd_vio_pwr_st) == 0 )
- {
- pPMU_Reg->PMU_MISC_CON1 |= idle_req_vio_cfg;
- dsb();
- while( (pPMU_Reg->PMU_PWRDN_ST & idle_vio) == 0 );
- }
-
- if ( (pPMU_Reg->PMU_PWRDN_ST & pd_video_pwr_st) == 0 )
- {
- pPMU_Reg->PMU_MISC_CON1 |= idle_req_video_cfg;
- dsb();
- while( (pPMU_Reg->PMU_PWRDN_ST & idle_video) == 0 );
- }
-
- if ( (pPMU_Reg->PMU_PWRDN_ST & pd_gpu_pwr_st) == 0 )
- {
- pPMU_Reg->PMU_MISC_CON1 |= idle_req_gpu_cfg;
- dsb();
- while( (pPMU_Reg->PMU_PWRDN_ST & idle_gpu) == 0 );
- }
-
- //resume clock gate status
- for(i=0;i<10;i++)
- pCRU_Reg->CRU_CLKGATE_CON[i]= (clk_gate[i] | 0xffff0000);
-}
-
-void __sramlocalfunc deidle_port(void)
-{
- int i;
- uint32 clk_gate[10];
-
- //save clock gate status
- for(i=0;i<10;i++)
- clk_gate[i]=pCRU_Reg->CRU_CLKGATE_CON[i];
-
- //enable all clock gate for request idle
- for(i=0;i<10;i++)
- pCRU_Reg->CRU_CLKGATE_CON[i]=0xffff0000;
-
- if ( (pPMU_Reg->PMU_PWRDN_ST & pd_a9_0_pwr_st) == 0 )
- {
-
-#ifdef CONFIG_ARCH_RK3188
- pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_dma_cfg;
- dsb();
- while( (pPMU_Reg->PMU_PWRDN_ST & idle_dma) != 0 );
-#else
- pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_cpu_cfg;
- dsb();
- while( (pPMU_Reg->PMU_PWRDN_ST & idle_cpu) != 0 );
-#endif
- }
- if ( (pPMU_Reg->PMU_PWRDN_ST & pd_peri_pwr_st) == 0 )
- {
- pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_peri_cfg;
- dsb();
- while( (pPMU_Reg->PMU_PWRDN_ST & idle_peri) != 0 );
- }
-
- if ( (pPMU_Reg->PMU_PWRDN_ST & pd_vio_pwr_st) == 0 )
- {
- pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_vio_cfg;
- dsb();
- while( (pPMU_Reg->PMU_PWRDN_ST & idle_vio) != 0 );
- }
-
- if ( (pPMU_Reg->PMU_PWRDN_ST & pd_video_pwr_st) == 0 )
- {
- pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_video_cfg;
- dsb();
- while( (pPMU_Reg->PMU_PWRDN_ST & idle_video) != 0 );
- }
-
- if ( (pPMU_Reg->PMU_PWRDN_ST & pd_gpu_pwr_st) == 0 )
- {
- pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_gpu_cfg;
- dsb();
- while( (pPMU_Reg->PMU_PWRDN_ST & idle_gpu) != 0 );
- }
-
- //resume clock gate status
- for(i=0;i<10;i++)
- pCRU_Reg->CRU_CLKGATE_CON[i]= (clk_gate[i] | 0xffff0000);
-
-}
-
-void __sramlocalfunc ddr_selfrefresh_enter(uint32 nMHz)
-{
- PHY_TIMING_T *p_publ_timing=&(ddr_reg.publ.phy_timing);
- uint32 cs;
-
- ddr_move_to_Config_state();
- pDDR_Reg->TZQCSI = 0;
- if((nMHz<=DDR3_DDR2_ODT_DLL_DISABLE_FREQ) && ((mem_type == DDR3) || (mem_type == DDR2))) // DLL disable
- {
- cs = ((pPHY_Reg->PGCR>>18) & 0xF);
- pPHY_Reg->MR[1] = (((p_publ_timing->mr[1])) | DDR3_DLL_DISABLE);
- ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr(((p_publ_timing->mr[1])) | DDR3_DLL_DISABLE));
- }
- ddr_move_to_Lowpower_state();
-
- ddr_set_dll_bypass(0); //dll bypass
- pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1<<2)<<16) | (1<<2); //disable DDR PHY clock
- ddr_delayus(1);
-}
-
-void __sramlocalfunc ddr_selfrefresh_exit(void)
-{
- uint32 n;
-
- pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1<<2)<<16) | (0<<2); //enable DDR PHY clock
- dsb();
- ddr_set_dll_bypass(ddr_freq);
- ddr_reset_dll();
- //ddr_delayus(10); //wait DLL lock
-
- ddr_move_to_Config_state();
- ddr_update_timing();
- ddr_update_mr();
- ddr_update_odt();
- n = ddr_data_training();
- ddr_move_to_Access_state();
- if(n!=0)
- {
- sram_printascii("DTT failed!\n");
- }
-}
-
-#if defined(CONFIG_ARCH_RK3066B)
-static __sramdata uint32_t data8_dqstr[25][4];
-static __sramdata uint32_t min_ddr_freq,dqstr_flag=false;
-
-int ddr_get_datatraing_value_3168(bool end_flag,uint32_t dqstr_value,uint32_t min_freq)
-{
- if(end_flag == true)
- {
- dqstr_flag = true; //complete learn data training value flag
- min_ddr_freq = min_freq;
- return 0;
- }
-
- data8_dqstr[dqstr_value][0]=pPHY_Reg->DATX8[0].DXDQSTR;
- data8_dqstr[dqstr_value][1]=pPHY_Reg->DATX8[0].DXDQSTR;
- data8_dqstr[dqstr_value][2]=pPHY_Reg->DATX8[0].DXDQSTR;
- data8_dqstr[dqstr_value][3]=pPHY_Reg->DATX8[0].DXDQSTR;
-
- ddr_print("training %luMhz[%d]:0x%x-0x%x-0x%x-0x%x\n",
- clk_get_rate(clk_get(NULL, "ddr"))/1000000,dqstr_value,data8_dqstr[dqstr_value][0],data8_dqstr[dqstr_value][1],
- data8_dqstr[dqstr_value][2],data8_dqstr[dqstr_value][3]);
- return 0;
-}
-EXPORT_SYMBOL(ddr_get_datatraing_value_3168);
-
-void __sramlocalfunc ddr_set_pll_enter_3168(uint32_t freq_slew)
-{
- uint32_t value_1u,value_100n;
- ddr_move_to_Config_state();
-
- if(freq_slew == 1)
- {
- value_100n = ddr_reg.pctl.pctl_timing.togcnt100n;
- value_1u = ddr_reg.pctl.pctl_timing.togcnt1u;
- ddr_reg.pctl.pctl_timing.togcnt1u = pDDR_Reg->TOGCNT1U;
- ddr_reg.pctl.pctl_timing.togcnt100n = pDDR_Reg->TOGCNT100N;
- ddr_update_timing();
- ddr_update_mr();
- ddr_reg.pctl.pctl_timing.togcnt100n = value_100n;
- ddr_reg.pctl.pctl_timing.togcnt1u = value_1u;
- }
- else
- {
- pDDR_Reg->TOGCNT100N = ddr_reg.pctl.pctl_timing.togcnt100n;
- pDDR_Reg->TOGCNT1U = ddr_reg.pctl.pctl_timing.togcnt1u;
- }
-
- pDDR_Reg->TZQCSI = 0;
- ddr_move_to_Lowpower_state();
-
- ddr_set_dll_bypass(0); //dll bypass
- pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1<<2)<<16) | (1<<2); //disable DDR PHY clock
- dsb();
-}
-
-void __sramlocalfunc ddr_set_pll_exit_3168(uint32 freq_slew,uint32_t dqstr_value)
-{
- pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1<<2)<<16) | (0<<2); //enable DDR PHY clock
- dsb();
- ddr_set_dll_bypass(ddr_freq);
- ddr_reset_dll();
-
- if(dqstr_flag==true)
- {
- pPHY_Reg->DATX8[0].DXDQSTR=data8_dqstr[dqstr_value][0];
- pPHY_Reg->DATX8[1].DXDQSTR=data8_dqstr[dqstr_value][1];
- pPHY_Reg->DATX8[2].DXDQSTR=data8_dqstr[dqstr_value][2];
- pPHY_Reg->DATX8[3].DXDQSTR=data8_dqstr[dqstr_value][3];
- }
-
- ddr_update_odt();
- ddr_move_to_Config_state();
- if(freq_slew == 1)
- {
- pDDR_Reg->TOGCNT100N = ddr_reg.pctl.pctl_timing.togcnt100n;
- pDDR_Reg->TOGCNT1U = ddr_reg.pctl.pctl_timing.togcnt1u;
- pDDR_Reg->TZQCSI = ddr_reg.pctl.pctl_timing.tzqcsi;
- }
- else
- {
- ddr_update_timing();
- ddr_update_mr();
- }
- ddr_data_training();
- ddr_move_to_Access_state();
-}
-#endif
-
-uint32_t __sramfunc ddr_change_freq_sram(uint32_t nMHz , struct ddr_freq_t ddr_freq_t)
-{
- uint32_t ret;
- u32 i;
- volatile u32 n;
- unsigned long flags;
- volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
- unsigned long save_sp;
- uint32_t freq;
-
-#if defined(CONFIG_ARCH_RK3066B)
- uint32_t freq_slew=0,dqstr_value=0;
- if(dqstr_flag==true)
- {
- dqstr_value=((nMHz-min_ddr_freq+1)/25 + 1) /2;
- freq_slew = (nMHz>ddr_freq)? 1 : 0;
- }
-#endif
-
- freq = ddr_get_pll_freq(APLL); //APLL
-
- loops_per_us = LPJ_100MHZ*freq / 1000000;
-
- ret=ddr_set_pll(nMHz,0);
-
- ddr_get_parameter(ret);
-
- /** 1. Make sure there is no host access */
- local_irq_save(flags);
- local_fiq_disable();
- flush_cache_all();
- outer_flush_all();
- flush_tlb_all();
- isb();
- DDR_SAVE_SP(save_sp);
-
- for(i=0;i<SRAM_SIZE/4096;i++)
- {
- n=temp[1024*i];
- barrier();
- }
-
- n= pDDR_Reg->SCFG.d32;
- n= pPHY_Reg->RIDR;
- n= pCRU_Reg->CRU_PLL_CON[0][0];
- n= pPMU_Reg->PMU_WAKEUP_CFG[0];
- n= *(volatile uint32_t *)SysSrv_DdrConf;
-#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
- n= pGRF_Reg_RK3066B->GRF_SOC_STATUS0;
-#else
- n= pGRF_Reg->GRF_SOC_STATUS0;
-#endif
- dsb();
-
-#if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
- n = ddr_freq_t.screen_ft_us;
- n = ddr_freq_t.t0;
- dsb();
-
- if(ddr_freq_t.screen_ft_us > 0)
- {
- ddr_freq_t.t1 = cpu_clock(0);
- ddr_freq_t.t2 = (u32)(ddr_freq_t.t1 - ddr_freq_t.t0); //ns
-
- //if test_count exceed maximum test times,ddr_freq_t.screen_ft_us == 0xfefefefe by ddr_freq.c
- if( (ddr_freq_t.t2 > ddr_freq_t.screen_ft_us*1000) && (ddr_freq_t.screen_ft_us != 0xfefefefe))
- {
- DDR_RESTORE_SP(save_sp);
- local_fiq_enable();
- local_irq_restore(flags);
- return 0;
- }
- else
- {
- rk_fb_poll_wait_frame_complete();
- }
- }
-#endif
-
- /** 2. ddr enter self-refresh mode or precharge power-down mode */
- idle_port();
-#if defined(CONFIG_ARCH_RK3066B)
- ddr_set_pll_enter_3168(freq_slew);
-#else
- ddr_selfrefresh_enter(ret);
-#endif
-
- /** 3. change frequence */
- ddr_set_pll(ret,1);
- ddr_freq = ret;
-
- /** 5. Issues a Mode Exit command */
-#if defined(CONFIG_ARCH_RK3066B)
- ddr_set_pll_exit_3168(freq_slew,dqstr_value);
-#else
- ddr_selfrefresh_exit();
-#endif
- deidle_port();
- dsb();
- DDR_RESTORE_SP(save_sp);
- local_fiq_enable();
- local_irq_restore(flags);
- return ret;
-}
-
-uint32_t ddr_change_freq_gpll_dpll(uint32_t nMHz)
-{
- uint32_t gpll_freq,gpll_div;
- struct ddr_freq_t ddr_freq_t;
- ddr_freq_t.screen_ft_us = 0;
-
- gpllvaluel = ddr_get_pll_freq(GPLL);
-
- if((200 < gpllvaluel) ||( gpllvaluel <1600)) //GPLL:200MHz~1600MHz
- {
- if( gpllvaluel > 800) //800-1600MHz /4:200MHz-400MHz
- {
- gpll_freq = gpllvaluel/4;
- gpll_div = 4;
- }
- else if( gpllvaluel > 400) //400-800MHz /2:200MHz-400MHz
- {
- gpll_freq = gpllvaluel/2;
- gpll_div = 2;
- }
- else //200-400MHz /1:200MHz-400MHz
- {
- gpll_freq = gpllvaluel;
- gpll_div = 1;
- }
-
- ddr_select_gpll_div=gpll_div; //select GPLL
- ddr_change_freq_sram(gpll_freq,ddr_freq_t);
- ddr_select_gpll_div=0;
-
- ddr_set_pll(nMHz,0); //count DPLL
- ddr_set_pll(nMHz,2); //lock DPLL only,but not select DPLL
- }
- else
- {
- ddr_print("GPLL frequency = %dMHz,Not suitable for ddr_clock \n",gpllvaluel);
- }
-
- return ddr_change_freq_sram(nMHz,ddr_freq_t);
-
-}
-
-/*****************************************
-if rk3188 DPLL is bad,use GPLL
- GPLL DDR_CLCOK
-1000MHz-2000MHz 4:250MHz-500MHz
-800MHz-1000MHz 4:200MHz-250MHz 2:400MHz-500MHz
-500MHz-800MHz 2:250MHz-400MHz
-200MHz-500MHz 1:200MHz-500MHz
-******************************************/
-uint32_t ddr_change_freq(uint32_t nMHz)
-{
- struct ddr_freq_t ddr_freq_t;
- ddr_freq_t.screen_ft_us = 0;
-
-#if defined(ENABLE_DDR_CLCOK_GPLL_PATH) && defined(CONFIG_ARCH_RK3188)
- return ddr_change_freq_gpll_dpll(nMHz);
-#else
- return ddr_change_freq_sram(nMHz,ddr_freq_t);
-#endif
-}
-EXPORT_SYMBOL(ddr_change_freq);
-
-void ddr_set_auto_self_refresh(bool en)
-{
- //set auto self-refresh idle
- ddr_sr_idle = en ? SR_IDLE : 0;
-}
-EXPORT_SYMBOL(ddr_set_auto_self_refresh);
-
-enum rk_plls_id {
- APLL_IDX = 0,
- DPLL_IDX,
- CPLL_IDX,
- GPLL_IDX,
- END_PLL_IDX,
-};
-#define PLL_MODE_SLOW(id) ((0x0<<((id)*4))|(0x3<<(16+(id)*4)))
-#define PLL_MODE_NORM(id) ((0x1<<((id)*4))|(0x3<<(16+(id)*4)))
-
-#define CRU_W_MSK(bits_shift, msk) ((msk) << ((bits_shift) + 16))
-#define CRU_SET_BITS(val,bits_shift, msk) (((val)&(msk)) << (bits_shift))
-
-#define CRU_W_MSK_SETBITS(val,bits_shift,msk) (CRU_W_MSK(bits_shift, msk)|CRU_SET_BITS(val,bits_shift, msk))
-
-#define PERI_ACLK_DIV_MASK 0x1f
-#define PERI_ACLK_DIV_OFF 0
-
-#define PERI_HCLK_DIV_MASK 0x3
-#define PERI_HCLK_DIV_OFF 8
-
-#define PERI_PCLK_DIV_MASK 0x3
-#define PERI_PCLK_DIV_OFF 12
-static __sramdata u32 cru_sel32_sram;
-void __sramfunc ddr_suspend(void)
-{
- u32 i;
- volatile u32 n;
- volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
- int pll_idx;
-
-if(pCRU_Reg->CRU_CLKSEL_CON[26]&(1<<8))
- pll_idx=GPLL_IDX;
-else
- pll_idx=DPLL_IDX;
- /** 1. Make sure there is no host access */
- flush_cache_all();
- outer_flush_all();
- //flush_tlb_all();
-
- for(i=0;i<SRAM_SIZE/4096;i++)
- {
- n=temp[1024*i];
- barrier();
- }
-
- n= pDDR_Reg->SCFG.d32;
- n= pPHY_Reg->RIDR;
- n= pCRU_Reg->CRU_PLL_CON[0][0];
- n= pPMU_Reg->PMU_WAKEUP_CFG[0];
- n= *(volatile uint32_t *)SysSrv_DdrConf;
-#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
- n= pGRF_Reg_RK3066B->GRF_SOC_STATUS0;
-#else
- n= pGRF_Reg->GRF_SOC_STATUS0;
-#endif
- dsb();
-
- ddr_selfrefresh_enter(0);
-
- pCRU_Reg->CRU_MODE_CON = PLL_MODE_SLOW(pll_idx); //PLL slow-mode
- dsb();
- ddr_delayus(1);
- pCRU_Reg->CRU_PLL_CON[pll_idx][3] = ((0x1<<1)<<16) | (0x1<<1); //PLL power-down
- dsb();
- ddr_delayus(1);
- if(pll_idx==GPLL_IDX)
- {
- cru_sel32_sram= pCRU_Reg->CRU_CLKSEL_CON[10];
-
- pCRU_Reg->CRU_CLKSEL_CON[10]=CRU_W_MSK_SETBITS(0, PERI_ACLK_DIV_OFF, PERI_ACLK_DIV_MASK)
- | CRU_W_MSK_SETBITS(0, PERI_HCLK_DIV_OFF, PERI_HCLK_DIV_MASK)
- |CRU_W_MSK_SETBITS(0, PERI_PCLK_DIV_OFF, PERI_PCLK_DIV_MASK);
- }
- pPHY_Reg->DSGCR = pPHY_Reg->DSGCR&(~((0x1<<28)|(0x1<<29))); //CKOE
-}
-EXPORT_SYMBOL(ddr_suspend);
-
-void __sramfunc ddr_resume(void)
-{
- int delay=1000;
- int pll_idx;
-#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
- u32 bit = 0x20 ;
-#else
- u32 bit = 0x10;
-#endif
-
- if(pCRU_Reg->CRU_CLKSEL_CON[26]&(1<<8))
- {
- pll_idx=GPLL_IDX;
- bit =bit<<3;
- }
- else
- {
- pll_idx=DPLL_IDX;
- bit=bit<<0;
- }
-
- pPHY_Reg->DSGCR = pPHY_Reg->DSGCR|((0x1<<28)|(0x1<<29)); //CKOE
- dsb();
-
- if(pll_idx==GPLL_IDX)
- pCRU_Reg->CRU_CLKSEL_CON[10]=0xffff0000|cru_sel32_sram;
-
-
-
- pCRU_Reg->CRU_PLL_CON[pll_idx][3] = ((0x1<<1)<<16) | (0x0<<1); //PLL no power-down
- dsb();
- while (delay > 0)
- {
- ddr_delayus(1);
-#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
- if (pGRF_Reg_RK3066B->GRF_SOC_STATUS0 & (1<<5))
- break;
-#else
- if (pGRF_Reg->GRF_SOC_STATUS0 & (1<<4))
- break;
-#endif
- delay--;
- }
-
- pCRU_Reg->CRU_MODE_CON = PLL_MODE_NORM(pll_idx); //PLL normal
- dsb();
-
- ddr_selfrefresh_exit();
-}
-EXPORT_SYMBOL(ddr_resume);
-
-//»ñÈ¡ÈÝÁ¿£¬·µ»Ø×Ö½ÚÊý
-uint32 ddr_get_cap(void)
-{
- uint32 cap;
-
- if(pPMU_Reg->PMU_PMU_SYS_REG[2])
- {
- cap = (1 << (READ_CS0_ROW_INFO()+READ_COL_INFO()+READ_BK_INFO()+READ_BW_INFO()));
- if(READ_CS_INFO()>1)
- {
- cap +=(1 << (READ_CS1_ROW_INFO()+READ_COL_INFO()+READ_BK_INFO()+READ_BW_INFO()));
- }
- }
- else
- {
- cap = (1 << (ddr_get_row()+ddr_get_col()+ddr_get_bank()+ddr_get_bw()))*ddr_get_cs();
- }
-
- return cap;
-}
-EXPORT_SYMBOL(ddr_get_cap);
-
-void ddr_reg_save(void)
-{
- //PCTLR
- ddr_reg.pctl.SCFG = pDDR_Reg->SCFG.d32;
- ddr_reg.pctl.CMDTSTATEN = pDDR_Reg->CMDTSTATEN;
- ddr_reg.pctl.MCFG1 = pDDR_Reg->MCFG1;
- ddr_reg.pctl.MCFG = pDDR_Reg->MCFG;
- ddr_reg.pctl.pctl_timing.ddrFreq = ddr_freq;
- ddr_reg.pctl.DFITCTRLDELAY = pDDR_Reg->DFITCTRLDELAY;
- ddr_reg.pctl.DFIODTCFG = pDDR_Reg->DFIODTCFG;
- ddr_reg.pctl.DFIODTCFG1 = pDDR_Reg->DFIODTCFG1;
- ddr_reg.pctl.DFIODTRANKMAP = pDDR_Reg->DFIODTRANKMAP;
- ddr_reg.pctl.DFITPHYWRDATA = pDDR_Reg->DFITPHYWRDATA;
- ddr_reg.pctl.DFITPHYWRLAT = pDDR_Reg->DFITPHYWRLAT;
- ddr_reg.pctl.DFITRDDATAEN = pDDR_Reg->DFITRDDATAEN;
- ddr_reg.pctl.DFITPHYRDLAT = pDDR_Reg->DFITPHYRDLAT;
- ddr_reg.pctl.DFITPHYUPDTYPE0 = pDDR_Reg->DFITPHYUPDTYPE0;
- ddr_reg.pctl.DFITPHYUPDTYPE1 = pDDR_Reg->DFITPHYUPDTYPE1;
- ddr_reg.pctl.DFITPHYUPDTYPE2 = pDDR_Reg->DFITPHYUPDTYPE2;
- ddr_reg.pctl.DFITPHYUPDTYPE3 = pDDR_Reg->DFITPHYUPDTYPE3;
- ddr_reg.pctl.DFITCTRLUPDMIN = pDDR_Reg->DFITCTRLUPDMIN;
- ddr_reg.pctl.DFITCTRLUPDMAX = pDDR_Reg->DFITCTRLUPDMAX;
- ddr_reg.pctl.DFITCTRLUPDDLY = pDDR_Reg->DFITCTRLUPDDLY;
-
- ddr_reg.pctl.DFIUPDCFG = pDDR_Reg->DFIUPDCFG;
- ddr_reg.pctl.DFITREFMSKI = pDDR_Reg->DFITREFMSKI;
- ddr_reg.pctl.DFITCTRLUPDI = pDDR_Reg->DFITCTRLUPDI;
- ddr_reg.pctl.DFISTCFG0 = pDDR_Reg->DFISTCFG0;
- ddr_reg.pctl.DFISTCFG1 = pDDR_Reg->DFISTCFG1;
- ddr_reg.pctl.DFITDRAMCLKEN = pDDR_Reg->DFITDRAMCLKEN;
- ddr_reg.pctl.DFITDRAMCLKDIS = pDDR_Reg->DFITDRAMCLKDIS;
- ddr_reg.pctl.DFISTCFG2 = pDDR_Reg->DFISTCFG2;
- ddr_reg.pctl.DFILPCFG0 = pDDR_Reg->DFILPCFG0;
-
- //PUBL
- ddr_reg.publ.PIR = pPHY_Reg->PIR;
- ddr_reg.publ.PGCR = pPHY_Reg->PGCR;
- ddr_reg.publ.DLLGCR = pPHY_Reg->DLLGCR;
- ddr_reg.publ.ACDLLCR = pPHY_Reg->ACDLLCR;
- ddr_reg.publ.PTR[0] = pPHY_Reg->PTR[0];
- ddr_reg.publ.PTR[1] = pPHY_Reg->PTR[1];
- ddr_reg.publ.PTR[2] = pPHY_Reg->PTR[2];
- ddr_reg.publ.ACIOCR = pPHY_Reg->ACIOCR;
- ddr_reg.publ.DXCCR = pPHY_Reg->DXCCR;
- ddr_reg.publ.DSGCR = pPHY_Reg->DSGCR;
- ddr_reg.publ.DCR = pPHY_Reg->DCR.d32;
- ddr_reg.publ.ODTCR = pPHY_Reg->ODTCR;
- ddr_reg.publ.DTAR = pPHY_Reg->DTAR;
- ddr_reg.publ.ZQ0CR0 = (pPHY_Reg->ZQ0SR[0] & 0x0FFFFFFF) | (0x1<<28);
- ddr_reg.publ.ZQ1CR0 = (pPHY_Reg->ZQ1SR[0] & 0x0FFFFFFF) | (0x1<<28);
-
- ddr_reg.publ.DX0GCR = pPHY_Reg->DATX8[0].DXGCR;
- ddr_reg.publ.DX0DLLCR = pPHY_Reg->DATX8[0].DXDLLCR;
- ddr_reg.publ.DX0DQTR = pPHY_Reg->DATX8[0].DXDQTR;
- ddr_reg.publ.DX0DQSTR = pPHY_Reg->DATX8[0].DXDQSTR;
-
- ddr_reg.publ.DX1GCR = pPHY_Reg->DATX8[1].DXGCR;
- ddr_reg.publ.DX1DLLCR = pPHY_Reg->DATX8[1].DXDLLCR;
- ddr_reg.publ.DX1DQTR = pPHY_Reg->DATX8[1].DXDQTR;
- ddr_reg.publ.DX1DQSTR = pPHY_Reg->DATX8[1].DXDQSTR;
-
- ddr_reg.publ.DX2GCR = pPHY_Reg->DATX8[2].DXGCR;
- ddr_reg.publ.DX2DLLCR = pPHY_Reg->DATX8[2].DXDLLCR;
- ddr_reg.publ.DX2DQTR = pPHY_Reg->DATX8[2].DXDQTR;
- ddr_reg.publ.DX2DQSTR = pPHY_Reg->DATX8[2].DXDQSTR;
-
- ddr_reg.publ.DX3GCR = pPHY_Reg->DATX8[3].DXGCR;
- ddr_reg.publ.DX3DLLCR = pPHY_Reg->DATX8[3].DXDLLCR;
- ddr_reg.publ.DX3DQTR = pPHY_Reg->DATX8[3].DXDQTR;
- ddr_reg.publ.DX3DQSTR = pPHY_Reg->DATX8[3].DXDQSTR;
-
- //NOC
- ddr_reg.DdrConf = *(volatile uint32_t *)SysSrv_DdrConf;
- ddr_reg.DdrMode = *(volatile uint32_t *)SysSrv_DdrMode;
- ddr_reg.ReadLatency = *(volatile uint32_t *)SysSrv_ReadLatency;
-}
-EXPORT_SYMBOL(ddr_reg_save);
-
-__attribute__((aligned(4))) __sramdata uint32 ddr_reg_resume[] =
-{
-#include "ddr_reg_resume.inc"
-};
-
-int ddr_init(uint32_t dram_speed_bin, uint32_t freq)
-{
- volatile uint32_t value = 0;
- uint32_t die=1;
- uint32_t gsr,dqstr;
-
- ddr_print("version 1.00 20131106 \n");
-
- mem_type = pPHY_Reg->DCR.b.DDRMD;
- ddr_speed_bin = dram_speed_bin;
-
- if(freq != 0)
- ddr_freq = freq;
- else
- ddr_freq = clk_get_rate(clk_get(NULL, "ddr"))/1000000;
-
- ddr_sr_idle = 0;
-
-#if defined(CONFIG_ARCH_RK3188)
- ddr_soc_is_rk3188_plus = soc_is_rk3188plus();
- ddr_rk3188_dpll_is_good = ddr_get_dpll_status();
-#endif
- switch(mem_type)
- {
- case DDR3:
- if(pPMU_Reg->PMU_PMU_SYS_REG[2])
- {
- die = (8<<READ_BW_INFO())/(8<<READ_DIE_BW_INFO());
- }
- else
- {
- if(pDDR_Reg->PPCFG & 1)
- {
- die=1;
- }
- else
- {
- die = 2;
- }
- }
- ddr_print("DDR3 Device\n");
- break;
- case LPDDR2:
- ddr_print("LPDDR2 Device\n");
- break;
- case DDR2:
- ddr_print("DDR2 Device\n");
- break;
- case DDR:
- ddr_print("DDR Device\n");
- break;
- default:
- ddr_print("LPDDR Device\n");
- break;
- }
- //get capability per chip, not total size, used for calculate tRFC
- ddr_capability_per_die = ddr_get_cap()/(ddr_get_cs()*die);
- ddr_print("Bus Width=%d Col=%d Bank=%d Row=%d CS=%d Total Capability=%dMB\n",
- ddr_get_bw()*16,\
- ddr_get_col(), \
- (0x1<<(ddr_get_bank())), \
- ddr_get_row(), \
- ddr_get_cs(), \
- (ddr_get_cap()>>20));
- ddr_adjust_config(mem_type);
-
- if(ddr_rk3188_dpll_is_good == true)
- {
- if(freq != 0)
- value=ddr_change_freq(freq);
- else
- value=ddr_change_freq(clk_get_rate(clk_get(NULL, "ddr"))/1000000);
- }
- clk_set_rate(clk_get(NULL, "ddr"), 0);
- ddr_print("init success!!! freq=%luMHz\n", clk_get_rate(clk_get(NULL, "ddr"))/1000000);
-
- for(value=0;value<4;value++)
- {
- gsr = pPHY_Reg->DATX8[value].DXGSR[0];
- dqstr = pPHY_Reg->DATX8[value].DXDQSTR;
- ddr_print("DTONE=0x%x, DTERR=0x%x, DTIERR=0x%x, DTPASS=0x%x, DGSL=%d extra clock, DGPS=%d\n", \
- (gsr&0xF), ((gsr>>4)&0xF), ((gsr>>8)&0xF), ((gsr>>13)&0xFFF), (dqstr&0x7), ((((dqstr>>12)&0x3)+1)*90));
- }
- ddr_print("ZERR=%x, ZDONE=%x, ZPD=0x%x, ZPU=0x%x, OPD=0x%x, OPU=0x%x\n", \
- (pPHY_Reg->ZQ0SR[0]>>30)&0x1, \
- (pPHY_Reg->ZQ0SR[0]>>31)&0x1, \
- pPHY_Reg->ZQ0SR[1]&0x3,\
- (pPHY_Reg->ZQ0SR[1]>>2)&0x3,\
- (pPHY_Reg->ZQ0SR[1]>>4)&0x3,\
- (pPHY_Reg->ZQ0SR[1]>>6)&0x3);
- ddr_print("DRV Pull-Up=0x%x, DRV Pull-Dwn=0x%x\n", pPHY_Reg->ZQ0SR[0]&0x1F, (pPHY_Reg->ZQ0SR[0]>>5)&0x1F);
- ddr_print("ODT Pull-Up=0x%x, ODT Pull-Dwn=0x%x\n", (pPHY_Reg->ZQ0SR[0]>>10)&0x1F, (pPHY_Reg->ZQ0SR[0]>>15)&0x1F);
-
- return 0;
-}
-EXPORT_SYMBOL(ddr_init);
-
+++ /dev/null
- 0xea00008e ,
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- 0x200200c0 ,
- 0x10128000 ,
+++ /dev/null
-/* arch/arm/mach-rk30/devices.c
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/fs.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/dma-mapping.h>
-#include <asm/pmu.h>
-#include <mach/irqs.h>
-#include <mach/board.h>
-#include <plat/dma-pl330.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <mach/debug_uart.h>
-#include <plat/rk_fiq_debugger.h>
-
-#ifdef CONFIG_ADC_RK30
-static struct adc_platform_data rk30_adc_pdata = {
- #if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
- .ref_volt = 1800, //1800mV
- #else
- .ref_volt = 2500, //2500mV
- #endif
- .base_chn = -1,
-};
-static struct resource rk30_adc_resource[] = {
- {
- .start = IRQ_SARADC,
- .end = IRQ_SARADC,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK30_SARADC_PHYS,
- .end = RK30_SARADC_PHYS + RK30_SARADC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-struct platform_device device_adc = {
- .name = "rk30-adc",
- .id = -1,
- .num_resources = ARRAY_SIZE(rk30_adc_resource),
- .resource = rk30_adc_resource,
- .dev = {
- .platform_data = &rk30_adc_pdata,
- },
-};
-#endif
-
-#if !defined(CONFIG_ARCH_RK3066B) && defined(IRQ_TSADC)
-static struct resource rk30_tsadc_resource[] = {
- {
- .start = IRQ_TSADC,
- .end = IRQ_TSADC,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK30_TSADC_PHYS,
- .end = RK30_TSADC_PHYS + RK30_TSADC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_tsadc = {
- .name = "rk30-tsadc",
- .id = -1,
- .num_resources = ARRAY_SIZE(rk30_tsadc_resource),
- .resource = rk30_tsadc_resource,
-};
-
-static void __init rk30_init_tsadc(void)
-{
- platform_device_register(&device_tsadc);
-}
-#else
-static void __init rk30_init_tsadc(void) {}
-#endif
-
-static u64 dma_dmamask = DMA_BIT_MASK(32);
-
-static struct resource resource_dmac1[] = {
- [0] = {
- .start = RK30_DMACS1_PHYS,
- .end = RK30_DMACS1_PHYS + RK30_DMACS1_SIZE -1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_DMAC1_0,
- .end = IRQ_DMAC1_1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
-
-static struct rk29_pl330_platdata dmac1_pdata = {
- .peri = {
- [0] = DMACH_UART0_TX,
- [1] = DMACH_UART0_RX,
- [2] = DMACH_UART1_TX,
- [3] = DMACH_UART1_RX,
- [4] = DMACH_MAX,
- [5] = DMACH_MAX,
- [6] = DMACH_I2S1_2CH_TX,
- [7] = DMACH_I2S1_2CH_RX,
- [8] = DMACH_SPDIF_TX,
- [9] = DMACH_DMAC0_MEMTOMEM,
- [10] = DMACH_MAX,
- [11] = DMACH_MAX,
- [12] = DMACH_MAX,
- [13] = DMACH_MAX,
- [14] = DMACH_MAX,
- [15] = DMACH_MAX,
- [16] = DMACH_MAX,
- [17] = DMACH_MAX,
- [18] = DMACH_MAX,
- [19] = DMACH_MAX,
- [20] = DMACH_MAX,
- [21] = DMACH_MAX,
- [22] = DMACH_MAX,
- [23] = DMACH_MAX,
- [24] = DMACH_MAX,
- [25] = DMACH_MAX,
- [26] = DMACH_MAX,
- [27] = DMACH_MAX,
- [28] = DMACH_MAX,
- [29] = DMACH_MAX,
- [30] = DMACH_MAX,
- [31] = DMACH_MAX,
- },
-};
-
-#elif defined(CONFIG_ARCH_RK319X)
-
-static struct rk29_pl330_platdata dmac1_pdata = {
- .peri = {
- [0] = DMACH_MAX,
- [1] = DMACH_MAX,
- [2] = DMACH_MAX,
- [3] = DMACH_MAX,
- [4] = DMACH_I2S1_2CH_TX,
- [5] = DMACH_I2S1_2CH_RX,
- [6] = DMACH_SPDIF_TX,
- [7] = DMACH_DMAC0_MEMTOMEM,
- [8] = DMACH_MAX,
- [9] = DMACH_MAX,
- [10] = DMACH_MAX,
- [11] = DMACH_MAX,
- [12] = DMACH_MAX,
- [13] = DMACH_MAX,
- [14] = DMACH_MAX,
- [15] = DMACH_MAX,
- [16] = DMACH_MAX,
- [17] = DMACH_MAX,
- [18] = DMACH_MAX,
- [19] = DMACH_MAX,
- [20] = DMACH_MAX,
- [21] = DMACH_MAX,
- [22] = DMACH_MAX,
- [23] = DMACH_MAX,
- [24] = DMACH_MAX,
- [25] = DMACH_MAX,
- [26] = DMACH_MAX,
- [27] = DMACH_MAX,
- [28] = DMACH_MAX,
- [29] = DMACH_MAX,
- [30] = DMACH_MAX,
- [31] = DMACH_MAX,
- },
-};
-
-#else
-
-static struct rk29_pl330_platdata dmac1_pdata = {
- .peri = {
- [0] = DMACH_UART0_TX,
- [1] = DMACH_UART0_RX,
- [2] = DMACH_UART1_TX,
- [3] = DMACH_UART1_RX,
- [4] = DMACH_I2S0_8CH_TX,
- [5] = DMACH_I2S0_8CH_RX,
- [6] = DMACH_I2S1_2CH_TX,
- [7] = DMACH_I2S1_2CH_RX,
- [8] = DMACH_SPDIF_TX,
- [9] = DMACH_I2S2_2CH_TX,
- [10] = DMACH_I2S2_2CH_RX,
- [11] = DMACH_DMAC0_MEMTOMEM,
- [12] = DMACH_MAX,
- [13] = DMACH_MAX,
- [14] = DMACH_MAX,
- [15] = DMACH_MAX,
- [16] = DMACH_MAX,
- [17] = DMACH_MAX,
- [18] = DMACH_MAX,
- [19] = DMACH_MAX,
- [20] = DMACH_MAX,
- [21] = DMACH_MAX,
- [22] = DMACH_MAX,
- [23] = DMACH_MAX,
- [24] = DMACH_MAX,
- [25] = DMACH_MAX,
- [26] = DMACH_MAX,
- [27] = DMACH_MAX,
- [28] = DMACH_MAX,
- [29] = DMACH_MAX,
- [30] = DMACH_MAX,
- [31] = DMACH_MAX,
- },
-};
-
-#endif
-
-static struct platform_device device_dmac1 = {
- .name = "rk29-pl330",
- .id = 1,
- .num_resources = ARRAY_SIZE(resource_dmac1),
- .resource = resource_dmac1,
- .dev = {
- .dma_mask = &dma_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &dmac1_pdata,
- },
-};
-
-static struct resource resource_dmac2[] = {
- [0] = {
- .start = RK30_DMAC2_PHYS,
- .end = RK30_DMAC2_PHYS + RK30_DMAC2_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_DMAC2_0,
- .end = IRQ_DMAC2_1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-#if defined(CONFIG_ARCH_RK319X)
-
-static struct rk29_pl330_platdata dmac2_pdata = {
- .peri = {
- [0] = DMACH_HSADC,
- [1] = DMACH_SDMMC,
- [2] = DMACH_SDIO,
- [3] = DMACH_EMMC,
- [4] = DMACH_UART0_TX,
- [5] = DMACH_UART0_RX,
- [6] = DMACH_UART1_TX,
- [7] = DMACH_UART1_RX,
- [8] = DMACH_UART2_TX,
- [9] = DMACH_UART2_RX,
- [10] = DMACH_UART3_TX,
- [11] = DMACH_UART3_RX,
- [12] = DMACH_SPI0_TX,
- [13] = DMACH_SPI0_RX,
- [14] = DMACH_SPI1_TX,
- [15] = DMACH_SPI1_RX,
- [16] = DMACH_DMAC1_MEMTOMEM,
- [17] = DMACH_MAX,
- [18] = DMACH_MAX,
- [19] = DMACH_MAX,
- [20] = DMACH_MAX,
- [21] = DMACH_MAX,
- [22] = DMACH_MAX,
- [23] = DMACH_MAX,
- [24] = DMACH_MAX,
- [25] = DMACH_MAX,
- [26] = DMACH_MAX,
- [27] = DMACH_MAX,
- [28] = DMACH_MAX,
- [29] = DMACH_MAX,
- [30] = DMACH_MAX,
- [31] = DMACH_MAX,
- },
-};
-
-#else
-
-static struct rk29_pl330_platdata dmac2_pdata = {
- .peri = {
- [0] = DMACH_HSADC,
- [1] = DMACH_SDMMC,
- [2] = DMACH_MAX,
- [3] = DMACH_SDIO,
- [4] = DMACH_EMMC,
- [5] = DMACH_PID_FILTER,
- [6] = DMACH_UART2_TX,
- [7] = DMACH_UART2_RX,
- [8] = DMACH_UART3_TX,
- [9] = DMACH_UART3_RX,
- [10] = DMACH_SPI0_TX,
- [11] = DMACH_SPI0_RX,
- [12] = DMACH_SPI1_TX,
- [13] = DMACH_SPI1_RX,
- [14] = DMACH_DMAC1_MEMTOMEM,
- [15] = DMACH_MAX,
- [16] = DMACH_MAX,
- [17] = DMACH_MAX,
- [18] = DMACH_MAX,
- [19] = DMACH_MAX,
- [20] = DMACH_MAX,
- [21] = DMACH_MAX,
- [22] = DMACH_MAX,
- [23] = DMACH_MAX,
- [24] = DMACH_MAX,
- [25] = DMACH_MAX,
- [26] = DMACH_MAX,
- [27] = DMACH_MAX,
- [28] = DMACH_MAX,
- [29] = DMACH_MAX,
- [30] = DMACH_MAX,
- [31] = DMACH_MAX,
- },
-};
-
-#endif
-
-static struct platform_device device_dmac2 = {
- .name = "rk29-pl330",
- .id = 2,
- .num_resources = ARRAY_SIZE(resource_dmac2),
- .resource = resource_dmac2,
- .dev = {
- .dma_mask = &dma_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &dmac2_pdata,
- },
-};
-
-static struct platform_device *rk30_dmacs[] __initdata = {
- &device_dmac1,
- &device_dmac2,
-};
-
-static void __init rk30_init_dma(void)
-{
- platform_add_devices(rk30_dmacs, ARRAY_SIZE(rk30_dmacs));
-}
-
-#ifdef CONFIG_UART0_RK29
-static struct resource resources_uart0[] = {
- {
- .start = IRQ_UART0,
- .end = IRQ_UART0,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK30_UART0_PHYS,
- .end = RK30_UART0_PHYS + RK30_UART0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_uart0 = {
- .name = "rk_serial",
- .id = 0,
- .num_resources = ARRAY_SIZE(resources_uart0),
- .resource = resources_uart0,
-};
-#endif
-
-#ifdef CONFIG_UART1_RK29
-static struct resource resources_uart1[] = {
- {
- .start = IRQ_UART1,
- .end = IRQ_UART1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK30_UART1_PHYS,
- .end = RK30_UART1_PHYS + RK30_UART1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_uart1 = {
- .name = "rk_serial",
- .id = 1,
- .num_resources = ARRAY_SIZE(resources_uart1),
- .resource = resources_uart1,
-};
-#endif
-
-#ifdef CONFIG_UART2_RK29
-static struct resource resources_uart2[] = {
- {
- .start = IRQ_UART2,
- .end = IRQ_UART2,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK30_UART2_PHYS,
- .end = RK30_UART2_PHYS + RK30_UART2_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_uart2 = {
- .name = "rk_serial",
- .id = 2,
- .num_resources = ARRAY_SIZE(resources_uart2),
- .resource = resources_uart2,
-};
-#endif
-
-#ifdef CONFIG_UART3_RK29
-static struct resource resources_uart3[] = {
- {
- .start = IRQ_UART3,
- .end = IRQ_UART3,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK30_UART3_PHYS,
- .end = RK30_UART3_PHYS + RK30_UART3_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_uart3 = {
- .name = "rk_serial",
- .id = 3,
- .num_resources = ARRAY_SIZE(resources_uart3),
- .resource = resources_uart3,
-};
-#endif
-
-static void __init rk30_init_uart(void)
-{
-#ifdef CONFIG_UART0_RK29
- platform_device_register(&device_uart0);
-#endif
-#ifdef CONFIG_UART1_RK29
- platform_device_register(&device_uart1);
-#endif
-#ifdef CONFIG_UART2_RK29
- platform_device_register(&device_uart2);
-#endif
-#ifdef CONFIG_UART3_RK29
- platform_device_register(&device_uart3);
-#endif
-}
-
-#ifdef CONFIG_I2C0_CONTROLLER_RK29
-#define I2C0_ADAP_TYPE I2C_RK29_ADAP
-#define I2C0_START RK30_I2C0_PHYS
-#define I2C0_END RK30_I2C0_PHYS + SZ_4K - 1
-#endif
-#ifdef CONFIG_I2C0_CONTROLLER_RK30
-#define I2C0_ADAP_TYPE I2C_RK30_ADAP
-#define I2C0_START RK30_I2C0_PHYS + SZ_4K
-#define I2C0_END RK30_I2C0_PHYS + SZ_8K - 1
-#endif
-
-#ifdef CONFIG_I2C1_CONTROLLER_RK29
-#define I2C1_ADAP_TYPE I2C_RK29_ADAP
-#define I2C1_START RK30_I2C1_PHYS
-#define I2C1_END RK30_I2C1_PHYS + SZ_4K - 1
-#endif
-#ifdef CONFIG_I2C1_CONTROLLER_RK30
-#define I2C1_ADAP_TYPE I2C_RK30_ADAP
-#define I2C1_START RK30_I2C1_PHYS + SZ_4K
-#define I2C1_END RK30_I2C1_PHYS + SZ_8K - 1
-#endif
-
-#ifdef CONFIG_I2C2_CONTROLLER_RK29
-#define I2C2_ADAP_TYPE I2C_RK29_ADAP
-#define I2C2_START RK30_I2C2_PHYS
-#define I2C2_END RK30_I2C2_PHYS + SZ_8K - 1
-#endif
-#ifdef CONFIG_I2C2_CONTROLLER_RK30
-#define I2C2_ADAP_TYPE I2C_RK30_ADAP
-#define I2C2_START RK30_I2C2_PHYS + SZ_8K
-#define I2C2_END RK30_I2C2_PHYS + SZ_16K - 1
-#endif
-
-#ifdef CONFIG_I2C3_CONTROLLER_RK29
-#define I2C3_ADAP_TYPE I2C_RK29_ADAP
-#define I2C3_START RK30_I2C3_PHYS
-#define I2C3_END RK30_I2C3_PHYS + SZ_8K - 1
-#endif
-#ifdef CONFIG_I2C3_CONTROLLER_RK30
-#define I2C3_ADAP_TYPE I2C_RK30_ADAP
-#define I2C3_START RK30_I2C3_PHYS + SZ_8K
-#define I2C3_END RK30_I2C3_PHYS + SZ_16K - 1
-#endif
-
-#ifdef CONFIG_I2C4_CONTROLLER_RK29
-#define I2C4_ADAP_TYPE I2C_RK29_ADAP
-#define I2C4_START RK30_I2C4_PHYS
-#define I2C4_END RK30_I2C4_PHYS + SZ_8K - 1
-#endif
-#ifdef CONFIG_I2C4_CONTROLLER_RK30
-#define I2C4_ADAP_TYPE I2C_RK30_ADAP
-#define I2C4_START RK30_I2C4_PHYS + SZ_8K
-#define I2C4_END RK30_I2C4_PHYS + SZ_16K - 1
-#endif
-
-#if defined(CONFIG_ARCH_RK319X)
-#define I2C0_ADAP_TYPE I2C_RK30_ADAP
-#define I2C0_START RK319X_I2C0_PHYS
-#define I2C0_END RK319X_I2C0_PHYS + RK319X_I2C0_SIZE - 1
-#define I2C1_ADAP_TYPE I2C_RK30_ADAP
-#define I2C1_START RK319X_I2C1_PHYS
-#define I2C1_END RK319X_I2C1_PHYS + RK319X_I2C1_SIZE - 1
-#define I2C2_ADAP_TYPE I2C_RK30_ADAP
-#define I2C2_START RK319X_I2C2_PHYS
-#define I2C2_END RK319X_I2C2_PHYS + RK319X_I2C2_SIZE - 1
-#define I2C3_ADAP_TYPE I2C_RK30_ADAP
-#define I2C3_START RK319X_I2C3_PHYS
-#define I2C3_END RK319X_I2C3_PHYS + RK319X_I2C3_SIZE - 1
-#define I2C4_ADAP_TYPE I2C_RK30_ADAP
-#define I2C4_START RK319X_I2C4_PHYS
-#define I2C4_END RK319X_I2C4_PHYS + RK319X_I2C4_SIZE - 1
-#endif
-
-#ifdef CONFIG_I2C0_RK30
-static struct rk30_i2c_platform_data default_i2c0_data = {
- .bus_num = 0,
-#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188) || defined(CONFIG_ARCH_RK319X)
- .is_div_from_arm = 0,
-#else
- .is_div_from_arm = 1,
-#endif
- .adap_type = I2C0_ADAP_TYPE,
- .sda_mode = I2C0_SDA,
- .scl_mode = I2C0_SCL,
-};
-
-static struct resource resources_i2c0[] = {
- {
- .start = IRQ_I2C0,
- .end = IRQ_I2C0,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = I2C0_START,
- .end = I2C0_END,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_i2c0 = {
- .name = "rk30_i2c",
- .id = 0,
- .num_resources = ARRAY_SIZE(resources_i2c0),
- .resource = resources_i2c0,
- .dev = {
- .platform_data = &default_i2c0_data,
- },
-};
-#endif
-
-#ifdef CONFIG_I2C1_RK30
-static struct rk30_i2c_platform_data default_i2c1_data = {
- .bus_num = 1,
-#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188) || defined(CONFIG_ARCH_RK319X)
- .is_div_from_arm = 0,
-#else
- .is_div_from_arm = 1,
-#endif
- .adap_type = I2C1_ADAP_TYPE,
- .sda_mode = I2C1_SDA,
- .scl_mode = I2C1_SCL,
-};
-
-static struct resource resources_i2c1[] = {
- {
- .start = IRQ_I2C1,
- .end = IRQ_I2C1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = I2C1_START,
- .end = I2C1_END,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_i2c1 = {
- .name = "rk30_i2c",
- .id = 1,
- .num_resources = ARRAY_SIZE(resources_i2c1),
- .resource = resources_i2c1,
- .dev = {
- .platform_data = &default_i2c1_data,
- },
-};
-#endif
-
-#ifdef CONFIG_I2C2_RK30
-static struct rk30_i2c_platform_data default_i2c2_data = {
- .bus_num = 2,
- .is_div_from_arm = 0,
- .adap_type = I2C2_ADAP_TYPE,
- .sda_mode = I2C2_SDA,
- .scl_mode = I2C2_SCL,
-};
-
-static struct resource resources_i2c2[] = {
- {
- .start = IRQ_I2C2,
- .end = IRQ_I2C2,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = I2C2_START,
- .end = I2C2_END,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_i2c2 = {
- .name = "rk30_i2c",
- .id = 2,
- .num_resources = ARRAY_SIZE(resources_i2c2),
- .resource = resources_i2c2,
- .dev = {
- .platform_data = &default_i2c2_data,
- },
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-static struct rk30_i2c_platform_data default_i2c3_data = {
- .bus_num = 3,
- .is_div_from_arm = 0,
- .adap_type = I2C3_ADAP_TYPE,
- .sda_mode = I2C3_SDA,
- .scl_mode = I2C3_SCL,
-};
-
-static struct resource resources_i2c3[] = {
- {
- .start = IRQ_I2C3,
- .end = IRQ_I2C3,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = I2C3_START,
- .end = I2C3_END,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_i2c3 = {
- .name = "rk30_i2c",
- .id = 3,
- .num_resources = ARRAY_SIZE(resources_i2c3),
- .resource = resources_i2c3,
- .dev = {
- .platform_data = &default_i2c3_data,
- },
-};
-#endif
-
-#ifdef CONFIG_I2C4_RK30
-static struct rk30_i2c_platform_data default_i2c4_data = {
- .bus_num = 4,
- .is_div_from_arm = 0,
- .adap_type = I2C4_ADAP_TYPE,
- .sda_mode = I2C4_SDA,
- .scl_mode = I2C4_SCL,
-};
-
-static struct resource resources_i2c4[] = {
- {
- .start = IRQ_I2C4,
- .end = IRQ_I2C4,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = I2C4_START,
- .end = I2C4_END,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_i2c4 = {
- .name = "rk30_i2c",
- .id = 4,
- .num_resources = ARRAY_SIZE(resources_i2c4),
- .resource = resources_i2c4,
- .dev = {
- .platform_data = &default_i2c4_data,
- },
-};
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-static struct platform_device device_i2c_gpio = {
- .name = "i2c-gpio",
- .id = 5,
- .dev = {
- .platform_data = &default_i2c_gpio_data,
- },
-};
-#endif
-
-static void __init rk30_init_i2c(void)
-{
-#ifdef CONFIG_I2C0_RK30
- platform_device_register(&device_i2c0);
-#endif
-#ifdef CONFIG_I2C1_RK30
- platform_device_register(&device_i2c1);
-#endif
-#ifdef CONFIG_I2C2_RK30
- platform_device_register(&device_i2c2);
-#endif
-#ifdef CONFIG_I2C3_RK30
- platform_device_register(&device_i2c3);
-#endif
-#ifdef CONFIG_I2C4_RK30
- platform_device_register(&device_i2c4);
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- platform_device_register(&device_i2c_gpio);
-#endif
-}
-
-#if defined(CONFIG_SPIM0_RK29) || defined(CONFIG_SPIM1_RK29)
-/*****************************************************************************************
- * spi devices
- * author: cmc@rock-chips.com
- *****************************************************************************************/
-#define SPI_CHIPSELECT_NUM 2
-
-static int spi_io_init(struct spi_cs_gpio *cs_gpios, int cs_num)
-{
- int i;
- if (cs_gpios) {
- for (i = 0; i < cs_num; i++) {
- rk30_mux_api_set(cs_gpios[i].cs_iomux_name, cs_gpios[i].cs_iomux_mode);
- }
- }
- return 0;
-}
-
-static int spi_io_deinit(struct spi_cs_gpio *cs_gpios, int cs_num)
-{
- return 0;
-}
-
-static int spi_io_fix_leakage_bug(void)
-{
-#if 0
- gpio_direction_output(RK29_PIN2_PC1, GPIO_LOW);
-#endif
- return 0;
-}
-
-static int spi_io_resume_leakage_bug(void)
-{
-#if 0
- gpio_direction_output(RK29_PIN2_PC1, GPIO_HIGH);
-#endif
- return 0;
-}
-#endif
-
-/*
- * rk29xx spi master device
- */
-#ifdef CONFIG_SPIM0_RK29
-static struct spi_cs_gpio rk29xx_spi0_cs_gpios[SPI_CHIPSELECT_NUM] = {
-#if 0
-#if defined(CONFIG_ARCH_RK3066B)
- {
- .name = "spi0 cs0",
- .cs_gpio = RK30_PIN1_PA7,
- .cs_iomux_name = GPIO1A7_UART1RTSN_SPI0CSN0_NAME,
- .cs_iomux_mode = GPIO1A_SPI0CSN0,
- },
- {
- .name = "spi0 cs1",
- .cs_gpio = RK30_PIN1_PB7,
- .cs_iomux_name = GPIO1B7_SPI0CSN1_NAME,//if no iomux,set it NULL
- .cs_iomux_mode = GPIO1B_SPI0CSN1,
- }
-
-#else
- {
- .name = "spi0 cs0",
- .cs_gpio = RK30_PIN1_PA4,
- .cs_iomux_name = GPIO1A4_UART1SIN_SPI0CSN0_NAME,
- .cs_iomux_mode = GPIO1A_SPI0_CSN0,
- },
- {
- .name = "spi0 cs1",
- .cs_gpio = RK30_PIN4_PB7,
- .cs_iomux_name = GPIO4B7_SPI0CSN1_NAME,//if no iomux,set it NULL
- .cs_iomux_mode = GPIO4B_SPI0_CSN1,
- }
-#endif
-#endif
-};
-
-static struct rk29xx_spi_platform_data rk29xx_spi0_platdata = {
- .num_chipselect = SPI_CHIPSELECT_NUM,
- .chipselect_gpios = rk29xx_spi0_cs_gpios,
- .io_init = spi_io_init,
- .io_deinit = spi_io_deinit,
- .io_fix_leakage_bug = spi_io_fix_leakage_bug,
- .io_resume_leakage_bug = spi_io_resume_leakage_bug,
-};
-
-static struct resource rk29_spi0_resources[] = {
- {
- .start = IRQ_SPI0,
- .end = IRQ_SPI0,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK30_SPI0_PHYS,
- .end = RK30_SPI0_PHYS + RK30_SPI0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DMACH_SPI0_TX,
- .end = DMACH_SPI0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = DMACH_SPI0_RX,
- .end = DMACH_SPI0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-struct platform_device rk29xx_device_spi0m = {
- .name = "rk29xx_spim",
- .id = 0,
- .num_resources = ARRAY_SIZE(rk29_spi0_resources),
- .resource = rk29_spi0_resources,
- .dev = {
- .dma_mask = &dma_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &rk29xx_spi0_platdata,
- },
-};
-#endif
-
-#ifdef CONFIG_SPIM1_RK29
-static struct spi_cs_gpio rk29xx_spi1_cs_gpios[SPI_CHIPSELECT_NUM] = {
-#if 0
-#if defined(CONFIG_ARCH_RK3066B)
- {
- .name = "spi1 cs0",
- .cs_gpio = RK30_PIN0_PD7,
- .cs_iomux_name = GPIO0D7_SPI1CSN0_NAME,
- .cs_iomux_mode = GPIO0D_SPI1CSN0,
- },
- {
- .name = "spi1 cs1",
- .cs_gpio = RK30_PIN1_PB6,
- .cs_iomux_name = GPIO1B6_SPDIFTX_SPI1CSN1_NAME,//if no iomux,set it NULL
- .cs_iomux_mode = GPIO1B_SPI1CSN1,
- }
-
-#else
- {
- .name = "spi1 cs0",
- .cs_gpio = RK30_PIN2_PC4,
- .cs_iomux_name = GPIO2C4_LCDC1DATA20_SPI1CSN0_HSADCDATA1_NAME,
- .cs_iomux_mode = GPIO2C_SPI1_CSN0,
- },
- {
- .name = "spi1 cs1",
- .cs_gpio = RK30_PIN2_PC7,
- .cs_iomux_name = GPIO2C7_LCDC1DATA23_SPI1CSN1_HSADCDATA4_NAME,//if no iomux,set it NULL
- .cs_iomux_mode = GPIO2C_SPI1_CSN1,
- }
-#endif
-#endif
-};
-
-static struct rk29xx_spi_platform_data rk29xx_spi1_platdata = {
- .num_chipselect = SPI_CHIPSELECT_NUM,
- .chipselect_gpios = rk29xx_spi1_cs_gpios,
- .io_init = spi_io_init,
- .io_deinit = spi_io_deinit,
- .io_fix_leakage_bug = spi_io_fix_leakage_bug,
- .io_resume_leakage_bug = spi_io_resume_leakage_bug,
-};
-
-static struct resource rk29_spi1_resources[] = {
- {
- .start = IRQ_SPI1,
- .end = IRQ_SPI1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK30_SPI1_PHYS,
- .end = RK30_SPI1_PHYS + RK30_SPI1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DMACH_SPI1_TX,
- .end = DMACH_SPI1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = DMACH_SPI1_RX,
- .end = DMACH_SPI1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-struct platform_device rk29xx_device_spi1m = {
- .name = "rk29xx_spim",
- .id = 1,
- .num_resources = ARRAY_SIZE(rk29_spi1_resources),
- .resource = rk29_spi1_resources,
- .dev = {
- .dma_mask = &dma_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &rk29xx_spi1_platdata,
- },
-};
-#endif
-
-static void __init rk30_init_spim(void)
-{
-#ifdef CONFIG_SPIM0_RK29
- platform_device_register(&rk29xx_device_spi0m);
-#endif
-#ifdef CONFIG_SPIM1_RK29
- platform_device_register(&rk29xx_device_spi1m);
-#endif
-}
-
-#ifdef CONFIG_MTD_NAND_RK29XX
-static struct resource resources_nand[] = {
- {
- .start = RK30_NANDC_PHYS,
- .end = RK30_NANDC_PHYS + RK30_NANDC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- }
-};
-
-static struct platform_device device_nand = {
- .name = "rk29xxnand",
- .id = -1,
- .resource = resources_nand,
- .num_resources = ARRAY_SIZE(resources_nand),
-};
-#endif
-
-#ifdef CONFIG_HDMI_RK30
-static struct resource resource_hdmi[] = {
- [0] = {
- .start = RK30_HDMI_PHYS,
- .end = RK30_HDMI_PHYS + RK30_HDMI_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_HDMI,
- .end = IRQ_HDMI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_hdmi = {
- .name = "rk30-hdmi",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_hdmi),
- .resource = resource_hdmi,
-};
-#endif
-
-#ifdef CONFIG_RGA_RK30
-static struct resource resource_rga[] = {
- [0] = {
- .start = RK30_RGA_PHYS,
- .end = RK30_RGA_PHYS + RK30_RGA_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_RGA,
- .end = IRQ_RGA,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_rga = {
- .name = "rga",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_rga),
- .resource = resource_rga,
-};
-#endif
-
-#ifdef IRQ_IPP
-static struct resource resource_ipp[] = {
- [0] = {
- .start = RK30_IPP_PHYS,
- .end = RK30_IPP_PHYS + RK30_IPP_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_IPP,
- .end = IRQ_IPP,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_ipp = {
- .name = "rk29-ipp",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_ipp),
- .resource = resource_ipp,
-};
-#endif
-
-#ifdef CONFIG_SND_RK29_SOC_I2S
-#ifdef CONFIG_SND_RK29_SOC_I2S_8CH
-static struct resource resource_iis0_8ch[] = {
- [0] = {
- .start = RK30_I2S0_8CH_PHYS,
- .end = RK30_I2S0_8CH_PHYS + RK30_I2S0_8CH_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = DMACH_I2S0_8CH_TX,
- .end = DMACH_I2S0_8CH_TX,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = DMACH_I2S0_8CH_RX,
- .end = DMACH_I2S0_8CH_RX,
- .flags = IORESOURCE_DMA,
- },
- [3] = {
- .start = IRQ_I2S0_8CH,
- .end = IRQ_I2S0_8CH,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_iis0_8ch = {
- .name = "rk29_i2s",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_iis0_8ch),
- .resource = resource_iis0_8ch,
-};
-#endif
-#ifdef CONFIG_SND_RK29_SOC_I2S_2CH
-static struct resource resource_iis1_2ch[] = {
- [0] = {
- .start = RK30_I2S1_2CH_PHYS,
- .end = RK30_I2S1_2CH_PHYS + RK30_I2S1_2CH_SIZE -1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = DMACH_I2S1_2CH_TX,
- .end = DMACH_I2S1_2CH_TX,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = DMACH_I2S1_2CH_RX,
- .end = DMACH_I2S1_2CH_RX,
- .flags = IORESOURCE_DMA,
- },
- [3] = {
- .start = IRQ_I2S1_2CH,
- .end = IRQ_I2S1_2CH,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_iis1_2ch = {
- .name = "rk29_i2s",
- .id = 1,
- .num_resources = ARRAY_SIZE(resource_iis1_2ch),
- .resource = resource_iis1_2ch,
-};
-#endif
-#ifdef CONFIG_SND_RK_SOC_I2S2_2CH
-static struct resource resource_iis2_2ch[] = {
- [0] = {
- .start = RK30_I2S2_2CH_PHYS,
- .end = RK30_I2S2_2CH_PHYS + RK30_I2S2_2CH_SIZE -1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = DMACH_I2S2_2CH_TX,
- .end = DMACH_I2S2_2CH_TX,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = DMACH_I2S2_2CH_RX,
- .end = DMACH_I2S2_2CH_RX,
- .flags = IORESOURCE_DMA,
- },
- [3] = {
- .start = IRQ_I2S2_2CH,
- .end = IRQ_I2S2_2CH,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_iis2_2ch = {
- .name = "rk29_i2s",
- .id = 2,
- .num_resources = ARRAY_SIZE(resource_iis2_2ch),
- .resource = resource_iis2_2ch,
-};
-#endif
-#endif
-
-static struct platform_device device_pcm = {
- .name = "rockchip-audio",
- .id = -1,
-};
-
-static void __init rk30_init_i2s(void)
-{
-#ifdef CONFIG_SND_RK29_SOC_I2S_8CH
- platform_device_register(&device_iis0_8ch);
-#endif
-#ifdef CONFIG_SND_RK29_SOC_I2S_2CH
- platform_device_register(&device_iis1_2ch);
-#endif
-#ifdef CONFIG_SND_RK_SOC_I2S2_2CH
- platform_device_register(&device_iis2_2ch);
-#endif
- platform_device_register(&device_pcm);
-}
-
-
-
-#ifdef CONFIG_KEYS_RK29
-extern struct rk29_keys_platform_data rk29_keys_pdata;
-static struct platform_device device_keys = {
- .name = "rk29-keypad",
- .id = -1,
- .dev = {
- .platform_data = &rk29_keys_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_EMMC_RK
-static struct resource resources_emmc[] = {
- {
- .start = IRQ_EMMC,
- .end = IRQ_EMMC,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK30_EMMC_PHYS,
- .end = RK30_EMMC_PHYS + RK30_EMMC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- }
-};
-
-static struct platform_device device_emmc = {
- .name = "emmc",
- .id = -1,
- .num_resources = ARRAY_SIZE(resources_emmc),
- .resource = resources_emmc,
- .dev = {
- .platform_data = NULL,
- },
-};
-#endif
-
-#ifdef CONFIG_SDMMC0_RK29
-static struct resource resources_sdmmc0[] = {
- {
- .start = IRQ_SDMMC,
- .end = IRQ_SDMMC,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK30_SDMMC0_PHYS,
- .end = RK30_SDMMC0_PHYS + RK30_SDMMC0_SIZE -1,
- .flags = IORESOURCE_MEM,
- }
-};
-
-static struct platform_device device_sdmmc0 = {
- .name = "rk29_sdmmc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resources_sdmmc0),
- .resource = resources_sdmmc0,
- .dev = {
- .platform_data = &default_sdmmc0_data,
- },
-};
-#endif
-
-#ifdef CONFIG_SDMMC1_RK29
-static struct resource resources_sdmmc1[] = {
- {
- .start = IRQ_SDIO,
- .end = IRQ_SDIO,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK30_SDIO_PHYS,
- .end = RK30_SDIO_PHYS + RK30_SDIO_SIZE - 1,
- .flags = IORESOURCE_MEM,
- }
-};
-
-static struct platform_device device_sdmmc1 = {
- .name = "rk29_sdmmc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resources_sdmmc1),
- .resource = resources_sdmmc1,
- .dev = {
- .platform_data = &default_sdmmc1_data,
- },
-};
-#endif
-
-static void __init rk30_init_sdmmc(void)
-{
-#ifdef CONFIG_EMMC_RK
- platform_device_register(&device_emmc);
-#endif
-#ifdef CONFIG_SDMMC0_RK29
- platform_device_register(&device_sdmmc0);
-#endif
-#ifdef CONFIG_SDMMC1_RK29
- platform_device_register(&device_sdmmc1);
-#endif
-}
-
-#ifdef CONFIG_SND_RK_SOC_SPDIF
-static struct resource resources_spdif[] = {
- [0] = {
- .name = "spdif_base",
- .start = RK30_SPDIF_PHYS,
- .end = RK30_SPDIF_PHYS + RK30_SPDIF_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "spdif_irq",
- .start = IRQ_SPDIF,
- .end = IRQ_SPDIF,
- .flags = IORESOURCE_IRQ,
- },
- [2] = {
- .name = "spdif_dma",
- .start = DMACH_SPDIF_TX,
- .end = DMACH_SPDIF_TX,
- .flags = IORESOURCE_DMA,
- },
-};
-struct platform_device rk29_device_spdif = {
- .name = "rk-spdif",
- .id = -1,
- .num_resources = ARRAY_SIZE(resources_spdif),
- .resource = resources_spdif,
-};
-#endif
-
-#ifdef CONFIG_RK29_VMAC
-static u64 eth_dmamask = DMA_BIT_MASK(32);
-static struct resource resources_vmac[] = {
- [0] = {
- .start = RK30_MAC_PHYS,
- .end = RK30_MAC_PHYS + RK30_MAC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_MAC,
- .end = IRQ_MAC,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static struct platform_device device_vmac = {
- .name = "rk29 vmac",
- .id = 0,
- .dev = {
- .dma_mask = ð_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &board_vmac_data,
- },
- .num_resources = ARRAY_SIZE(resources_vmac),
- .resource = resources_vmac,
-};
-#endif
-
-#ifdef CONFIG_RK29_WATCHDOG
-static struct resource resources_wdt[] = {
- {
- .start = IRQ_WDT,
- .end = IRQ_WDT,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = RK30_WDT_PHYS,
- .end = RK30_WDT_PHYS + RK30_WDT_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_wdt = {
- .name = "rk29-wdt",
- .id = 0,
- .num_resources = ARRAY_SIZE(resources_wdt),
- .resource = resources_wdt,
-};
-#endif
-
-static struct resource resource_arm_pmu[] = {
- {
- .start = IRQ_ARM_PMU,
- .end = IRQ_ARM_PMU,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_ARM_PMU + 1,
- .end = IRQ_ARM_PMU + 1,
- .flags = IORESOURCE_IRQ,
- },
-#if defined(CONFIG_ARCH_RK3188) || defined(CONFIG_ARCH_RK319X)
- {
- .start = IRQ_ARM_PMU + 2,
- .end = IRQ_ARM_PMU + 2,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_ARM_PMU + 3,
- .end = IRQ_ARM_PMU + 3,
- .flags = IORESOURCE_IRQ,
- },
-#endif
-};
-
-struct platform_device device_arm_pmu = {
- .name = "arm-pmu",
- .id = ARM_PMU_DEVICE_CPU,
- .num_resources = ARRAY_SIZE(resource_arm_pmu),
- .resource = resource_arm_pmu,
-};
-
-static int __init rk30_init_devices(void)
-{
- rk30_init_dma();
- rk30_init_uart();
- rk30_init_i2c();
- rk30_init_spim();
-#ifdef CONFIG_RGA_RK30
- platform_device_register(&device_rga);
-#endif
-#ifdef IRQ_IPP
- platform_device_register(&device_ipp);
-#endif
-
-#ifdef CONFIG_HDMI_RK30
- platform_device_register(&device_hdmi);
-#endif
-#ifdef CONFIG_ADC_RK30
- platform_device_register(&device_adc);
-#endif
-#ifdef CONFIG_KEYS_RK29
- platform_device_register(&device_keys);
-#endif
- rk30_init_tsadc();
- rk30_init_sdmmc();
-#if defined(CONFIG_FIQ_DEBUGGER) && defined(DEBUG_UART_PHYS)
- rk_serial_debug_init(DEBUG_UART_BASE, IRQ_DEBUG_UART, IRQ_UART_SIGNAL, -1);
-#endif
- rk30_init_i2s();
-
-#ifdef CONFIG_SND_RK_SOC_SPDIF
- platform_device_register(&rk29_device_spdif);
-#endif
-#ifdef CONFIG_RK29_VMAC
- platform_device_register(&device_vmac);
-#endif
-#ifdef CONFIG_RK29_WATCHDOG
- platform_device_register(&device_wdt);
-#endif
- platform_device_register(&device_arm_pmu);
-#ifdef CONFIG_MTD_NAND_RK29XX
- platform_device_register(&device_nand);
-#endif
-
- return 0;
-}
-arch_initcall(rk30_init_devices);
+++ /dev/null
-/* arch/arm/mach-rk30/rk30_dvfs.c\r
- *\r
- * Copyright (C) 2012 ROCKCHIP, Inc.\r
- *\r
- * This software is licensed under the terms of the GNU General Public\r
- * License version 2, as published by the Free Software Foundation, and\r
- * may be copied, distributed, and modified under those terms.\r
- *\r
- * This program is distributed in the hope that it will be useful,\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- * GNU General Public License for more details.\r
- *\r
- */\r
-\r
-#include <linux/kernel.h>\r
-#include <linux/err.h>\r
-#include <linux/spinlock.h>\r
-#include <linux/list.h>\r
-#include <linux/slab.h>\r
-#include <linux/clk.h>\r
-#include <linux/cpufreq.h>\r
-#include <mach/dvfs.h>\r
-#include <mach/clock.h>\r
-#include <linux/regulator/consumer.h>\r
-#include <linux/delay.h>\r
-#include <linux/io.h>\r
-#include <linux/hrtimer.h>\r
-\r
-#include <mach/io.h>\r
-#include <mach/cru.h>\r
-#include <mach/grf-rk3066b.h>\r
-\r
-#define MHZ (1000 * 1000)\r
-#define KHZ (1000)\r
-#define CLK_LOOPS_JIFFY_REF 11996091ULL\r
-#define CLK_LOOPS_RATE_REF (1200) //Mhz\r
-#define CLK_LOOPS_RECALC(new_rate) div_u64(CLK_LOOPS_JIFFY_REF*(new_rate),CLK_LOOPS_RATE_REF*MHZ)\r
-static struct clk *clk_cpu = NULL, *clk_cpu_div = NULL, *arm_pll_clk = NULL, *general_pll_clk = NULL;\r
-static unsigned long lpj_24m;\r
-\r
-struct gate_delay_table {\r
- unsigned long arm_perf;\r
- unsigned long log_perf;\r
- unsigned long delay;\r
-};\r
-\r
-struct cycle_by_rate {\r
- unsigned long rate_khz;\r
- unsigned long cycle_ns;\r
-};\r
-\r
-struct uoc_val_xx2delay {\r
- unsigned long volt;\r
- unsigned long perf;\r
- unsigned long uoc_val_01;\r
- unsigned long uoc_val_11;\r
-};\r
-\r
-struct dvfs_volt_performance {\r
- unsigned long volt;\r
- unsigned long perf; // Gate performance\r
-};\r
-static int rk_dvfs_clk_notifier_event(struct notifier_block *this,\r
- unsigned long event, void *ptr)\r
-{\r
- struct clk_notifier_data *noti_info;\r
- struct clk *clk;\r
- struct clk_node *dvfs_clk;\r
- noti_info = (struct clk_notifier_data *)ptr;\r
- clk = noti_info->clk;\r
- dvfs_clk = clk->dvfs_info;\r
-\r
- switch (event) {\r
- case CLK_PRE_RATE_CHANGE:\r
- DVFS_DBG("%s CLK_PRE_RATE_CHANGE\n", __func__);\r
- break;\r
- case CLK_POST_RATE_CHANGE:\r
- DVFS_DBG("%s CLK_POST_RATE_CHANGE\n", __func__);\r
- break;\r
- case CLK_ABORT_RATE_CHANGE:\r
- DVFS_DBG("%s CLK_ABORT_RATE_CHANGE\n", __func__);\r
- break;\r
- case CLK_PRE_ENABLE:\r
- DVFS_DBG("%s CLK_PRE_ENABLE\n", __func__);\r
- break;\r
- case CLK_POST_ENABLE:\r
- DVFS_DBG("%s CLK_POST_ENABLE\n", __func__);\r
- break;\r
- case CLK_ABORT_ENABLE:\r
- DVFS_DBG("%s CLK_ABORT_ENABLE\n", __func__);\r
- break;\r
- case CLK_PRE_DISABLE:\r
- DVFS_DBG("%s CLK_PRE_DISABLE\n", __func__);\r
- break;\r
- case CLK_POST_DISABLE:\r
- DVFS_DBG("%s CLK_POST_DISABLE\n", __func__);\r
- dvfs_clk->set_freq = 0;\r
- break;\r
- case CLK_ABORT_DISABLE:\r
- DVFS_DBG("%s CLK_ABORT_DISABLE\n", __func__);\r
-\r
- break;\r
- default:\r
- break;\r
- }\r
- return 0;\r
-}\r
-\r
-static struct notifier_block rk_dvfs_clk_notifier = {\r
- .notifier_call = rk_dvfs_clk_notifier_event,\r
-};\r
-\r
-static unsigned long dvfs_volt_arm_support_table[] = {\r
- 850 * 1000,\r
- 875 * 1000,\r
- 900 * 1000,\r
- 925 * 1000,\r
- 950 * 1000,\r
- 975 * 1000,\r
- 1000 * 1000,\r
- 1025 * 1000,\r
- 1050 * 1000,\r
- 1075 * 1000,\r
- 1100 * 1000,\r
- 1125 * 1000,\r
- 1150 * 1000,\r
- 1175 * 1000,\r
- 1200 * 1000,\r
- 1225 * 1000,\r
- 1250 * 1000,\r
- 1275 * 1000,\r
- 1300 * 1000,\r
-};\r
-static unsigned long dvfs_volt_log_support_table[] = {\r
- 850 * 1000,\r
- 875 * 1000,\r
- 900 * 1000,\r
- 925 * 1000,\r
- 950 * 1000,\r
- 975 * 1000,\r
- 1000 * 1000,\r
- 1025 * 1000,\r
- 1050 * 1000,\r
- 1075 * 1000,\r
- 1100 * 1000,\r
- 1125 * 1000,\r
- 1150 * 1000,\r
- 1175 * 1000,\r
- 1200 * 1000,\r
- 1225 * 1000,\r
- 1250 * 1000,\r
- 1275 * 1000,\r
- 1300 * 1000,\r
-};\r
-\r
-/*\r
- * 电压 dly_line 每增加0.1V的增量 每增加0.1V增加的比例 与1v对比增加的比例\r
- * 1.00 128\r
- * 1.10 157 29 1.23 1.23\r
- * 1.20 184 27 1.17 1.44\r
- * 1.30 209 25 1.14 1.63\r
- * 1.40 231 22 1.11 1.80\r
- * 1.50 251 20 1.09 1.96\r
- * This table is calc form func:\r
- * dly_line = 536 * volt - 116 * volt * volt - 292\r
- * volt unit: V\r
- * dly_line unit: Gate\r
- *\r
- * The table standard voltage is 1.0V, delay_line = 128(Gates)\r
- * \r
- * */\r
-\r
-#define VP_TABLE_END (~0)\r
-static struct dvfs_volt_performance dvfs_vp_table[] = {\r
- {.volt = 850 * 1000, .perf = 350}, //623\r
- {.volt = 875 * 1000, .perf = 350}, //689\r
- {.volt = 900 * 1000, .perf = 350}, //753 make low arm freq uoc as small as posible\r
- {.volt = 925 * 1000, .perf = 450}, //817\r
- {.volt = 950 * 1000, .perf = 550}, //879\r
- {.volt = 975 * 1000, .perf = 650}, //940\r
- {.volt = 1000 * 1000, .perf = 750},\r
- {.volt = 1025 * 1000, .perf = 1100},\r
- {.volt = 1050 * 1000, .perf = 1125},\r
- {.volt = 1075 * 1000, .perf = 1173},\r
- {.volt = 1100 * 1000, .perf = 1230},\r
- {.volt = 1125 * 1000, .perf = 1283},\r
- {.volt = 1150 * 1000, .perf = 1336},\r
- {.volt = 1175 * 1000, .perf = 1388},\r
- {.volt = 1200 * 1000, .perf = 1440},\r
- {.volt = 1225 * 1000, .perf = 1620}, //1489\r
- {.volt = 1250 * 1000, .perf = 1660}, //1537\r
- {.volt = 1275 * 1000, .perf = 1700}, //1585\r
- {.volt = 1300 * 1000, .perf = 1720}, //1630 1.6Garm 600Mgpu, make uoc=2b'01\r
- {.volt = 1325 * 1000, .perf = 1740}, //1676\r
- {.volt = 1350 * 1000, .perf = 1760}, //1720\r
- {.volt = 1375 * 1000, .perf = 1780}, //1763\r
- {.volt = 1400 * 1000, .perf = 1800},\r
- {.volt = 1425 * 1000, .perf = 1846},\r
- {.volt = 1450 * 1000, .perf = 1885},\r
- {.volt = 1475 * 1000, .perf = 1924},\r
- {.volt = 1500 * 1000, .perf = 1960},\r
- {.volt = VP_TABLE_END},\r
-};\r
-//>1.2V step = 50mV\r
-//ns (Magnified 10^6 times)\r
-#define VD_DELAY_ZOOM (1000UL * 1000UL)\r
-#define VD_ARM_DELAY 1350000UL\r
-#define VD_LOG_DELAY 877500UL\r
-int uoc_val = 0;\r
-#define L2_HOLD 40UL //located at 40%\r
-#define L2_SETUP 70UL //located at 70%\r
-\r
-#define UOC_VAL_00 0UL\r
-#define UOC_VAL_01 165000UL //0.9V(125`C):220000\r
-#define UOC_VAL_11 285000UL //0.9V(125`C):380000\r
-#define UOC_VAL_MIN 100UL //to work around get_delay=0\r
-\r
-#define SIZE_SUPPORT_ARM_VOLT ARRAY_SIZE(dvfs_volt_arm_support_table)\r
-#define SIZE_SUPPORT_LOG_VOLT ARRAY_SIZE(dvfs_volt_log_support_table)\r
-#define SIZE_VP_TABLE ARRAY_SIZE(dvfs_vp_table)\r
-#define SIZE_ARM_FREQ_TABLE 10\r
-static struct cycle_by_rate rate_cycle[SIZE_ARM_FREQ_TABLE];\r
-static int size_dvfs_arm_table = 0;\r
-\r
-static struct clk_node *dvfs_clk_cpu;\r
-static struct vd_node vd_core;\r
-static struct vd_node vd_cpu;\r
-\r
-static struct uoc_val_xx2delay uoc_val_xx[SIZE_VP_TABLE];\r
-static struct gate_delay_table gate_delay[SIZE_VP_TABLE][SIZE_VP_TABLE];\r
-\r
-static unsigned long dvfs_get_perf_byvolt(unsigned long volt)\r
-{\r
- int i = 0;\r
- for (i = 0; dvfs_vp_table[i].volt != VP_TABLE_END; i++) {\r
- if (volt <= dvfs_vp_table[i].volt)\r
- return dvfs_vp_table[i].perf;\r
- }\r
- return 0;\r
-}\r
-\r
-static unsigned long dvfs_get_gate_delay_per_volt(unsigned long arm_perf, unsigned long log_perf)\r
-{\r
- unsigned long gate_arm_delay, gate_log_delay;\r
- if (arm_perf == 0)\r
- arm_perf = 1;\r
- if (log_perf == 0)\r
- log_perf = 1;\r
- gate_arm_delay = VD_ARM_DELAY * 1000 / arm_perf;\r
- gate_log_delay = VD_LOG_DELAY * 1000 / log_perf;\r
-\r
- return (gate_arm_delay > gate_log_delay ? (gate_arm_delay - gate_log_delay) : 0);\r
-}\r
-\r
-static int dvfs_gate_delay_init(void)\r
-{\r
-\r
- int i = 0, j = 0;\r
- for (i = 0; i < SIZE_VP_TABLE - 1; i++)\r
- for (j = 0; j < SIZE_VP_TABLE - 1; j++) {\r
- gate_delay[i][j].arm_perf = dvfs_vp_table[i].perf;\r
- gate_delay[i][j].log_perf = dvfs_vp_table[j].perf;\r
- gate_delay[i][j].delay = dvfs_get_gate_delay_per_volt(gate_delay[i][j].arm_perf,\r
- gate_delay[i][j].log_perf);\r
-\r
- //DVFS_DBG("%s: arm_perf=%lu, log_perf=%lu, delay=%lu\n", __func__,\r
- // gate_delay[i][j].arm_perf, gate_delay[i][j].log_perf,\r
- // gate_delay[i][j].delay);\r
- }\r
- return 0;\r
-}\r
-\r
-static unsigned long dvfs_get_gate_delay(unsigned long arm_perf, unsigned long log_perf)\r
-{\r
- int i = 0, j = 0;\r
- for (i = 0; i < SIZE_VP_TABLE - 1; i++) {\r
- if (gate_delay[i][0].arm_perf == arm_perf)\r
- break;\r
- }\r
- for (j = 0; j < SIZE_VP_TABLE - 1; j++) {\r
- if (gate_delay[i][j].log_perf == log_perf)\r
- break;\r
- }\r
-\r
- //DVFS_DBG("%s index_arm=%d, index_log=%d, delay=%lu\n", __func__, i, j, gate_delay[i][j].delay);\r
- //DVFS_DBG("%s perf_arm=%d, perf_log=%d, delay=%lu\n",\r
- // __func__, gate_delay[i][j].arm_perf , gate_delay[i][j].log_perf , gate_delay[i][j].delay);\r
- return gate_delay[i][j].delay;\r
-}\r
-static int dvfs_uoc_val_delay_init(void)\r
-{\r
- int i = 0;\r
- for (i = 0; i < SIZE_VP_TABLE - 1; i++) {\r
- uoc_val_xx[i].volt = dvfs_vp_table[i].volt;\r
- uoc_val_xx[i].perf = dvfs_vp_table[i].perf;\r
- uoc_val_xx[i].uoc_val_01 = UOC_VAL_01 * 1000 / uoc_val_xx[i].perf;\r
- uoc_val_xx[i].uoc_val_11 = UOC_VAL_11 * 1000 / uoc_val_xx[i].perf;\r
- //DVFS_DBG("volt=%lu, perf=%lu, uoc_01=%lu, uoc_11=%lu\n", uoc_val_xx[i].volt, uoc_val_xx[i].perf,\r
- // uoc_val_xx[i].uoc_val_01, uoc_val_xx[i].uoc_val_11);\r
- }\r
- return 0;\r
-}\r
-static unsigned long dvfs_get_uoc_val_xx_by_volt(unsigned long uoc_val_xx_delay, unsigned long volt)\r
-{\r
- int i = 0;\r
- if (uoc_val_xx_delay == UOC_VAL_01) {\r
- for (i = 0; i < SIZE_VP_TABLE - 1; i++) {\r
- if (uoc_val_xx[i].volt == volt)\r
- return uoc_val_xx[i].uoc_val_01;\r
- }\r
-\r
- } else if (uoc_val_xx_delay == UOC_VAL_11) {\r
- for (i = 0; i < SIZE_VP_TABLE - 1; i++) {\r
- if (uoc_val_xx[i].volt == volt)\r
- return uoc_val_xx[i].uoc_val_11;\r
- }\r
-\r
- } else {\r
- DVFS_ERR("%s UNKNOWN uoc_val_xx\n", __func__);\r
- }\r
- DVFS_ERR("%s can not find uoc_val_xx=%lu, with volt=%lu\n", __func__, uoc_val_xx_delay, volt);\r
- return uoc_val_xx_delay;\r
-}\r
-struct dvfs_volt_uoc {\r
- unsigned long volt_log;\r
- unsigned long volt_arm_new;\r
- unsigned long volt_log_new;\r
- int uoc_val;\r
-};\r
-struct dvfs_uoc_val_table {\r
- unsigned long rate_arm;\r
- unsigned long volt_arm;\r
- struct dvfs_volt_uoc vu_list[SIZE_SUPPORT_LOG_VOLT];\r
-};\r
-static struct dvfs_uoc_val_table dvfs_uoc_val_list[SIZE_ARM_FREQ_TABLE];\r
-\r
-static int dvfs_get_uoc_val_init(unsigned long *p_volt_arm_new, unsigned long *p_volt_log_new, \r
- unsigned long rate_khz);\r
-static int dvfs_with_uoc_init(void)\r
-{\r
- struct cpufreq_frequency_table *dvfs_arm_table;\r
- struct clk *cpu_clk;\r
- int i = 0, j = 0;\r
- unsigned long arm_volt_save = 0;\r
- cpu_clk = clk_get(NULL, "cpu");\r
- if (IS_ERR(cpu_clk))\r
- return PTR_ERR(cpu_clk);\r
-\r
- dvfs_arm_table = dvfs_get_freq_volt_table(cpu_clk);\r
- lpj_24m = CLK_LOOPS_RECALC(24 * MHZ);\r
- DVFS_DBG("24M=%lu cur_rate=%lu lpj=%lu\n", lpj_24m, arm_pll_clk->rate, loops_per_jiffy);\r
- dvfs_gate_delay_init();\r
- dvfs_uoc_val_delay_init();\r
-\r
- for (i = 0; dvfs_arm_table[i].frequency != CPUFREQ_TABLE_END; i++) {\r
- if (i > SIZE_ARM_FREQ_TABLE - 1) {\r
- DVFS_WARNING("mach-rk30/dvfs.c:%s:%d: dvfs arm table to large, use only [%d] frequency\n",\r
- __func__, __LINE__, SIZE_ARM_FREQ_TABLE);\r
- break;\r
- }\r
- rate_cycle[i].rate_khz = dvfs_arm_table[i].frequency;\r
- rate_cycle[i].cycle_ns = (1000UL * VD_DELAY_ZOOM) / (rate_cycle[i].rate_khz / 1000);\r
- DVFS_DBG("%s: rate=%lu, cycle_ns=%lu\n",\r
- __func__, rate_cycle[i].rate_khz, rate_cycle[i].cycle_ns);\r
- }\r
- size_dvfs_arm_table = i + 1;\r
-\r
- //dvfs_uoc_val_list[];\r
- for (i = 0; dvfs_arm_table[i].frequency != CPUFREQ_TABLE_END; i++) {\r
- dvfs_uoc_val_list[i].rate_arm = dvfs_arm_table[i].frequency;\r
- dvfs_uoc_val_list[i].volt_arm = dvfs_arm_table[i].index;\r
- arm_volt_save = dvfs_uoc_val_list[i].volt_arm;\r
- for (j = 0; j < SIZE_SUPPORT_LOG_VOLT - 1; j++) {\r
- dvfs_uoc_val_list[i].vu_list[j].volt_log = dvfs_volt_log_support_table[j];\r
- dvfs_uoc_val_list[i].vu_list[j].volt_arm_new = arm_volt_save;\r
- dvfs_uoc_val_list[i].vu_list[j].volt_log_new = dvfs_uoc_val_list[i].vu_list[j].volt_log;\r
- //DVFS_DBG("%s: Rarm=%lu,Varm=%lu,Vlog=%lu\n", __func__,\r
- // dvfs_uoc_val_list[i].rate_arm, dvfs_uoc_val_list[i].volt_arm,\r
- // dvfs_uoc_val_list[i].vu_list[j].volt_log);\r
-\r
- dvfs_uoc_val_list[i].vu_list[j].uoc_val = dvfs_get_uoc_val_init(\r
- &dvfs_uoc_val_list[i].vu_list[j].volt_arm_new, \r
- &dvfs_uoc_val_list[i].vu_list[j].volt_log_new, \r
- dvfs_uoc_val_list[i].rate_arm);\r
- DVFS_DBG("%s: Rarm=%lu,(Varm=%lu,Vlog=%lu)--->(Vn_arm=%lu,Vn_log=%lu), uoc=%d\n", __func__,\r
- dvfs_uoc_val_list[i].rate_arm, dvfs_uoc_val_list[i].volt_arm,\r
- dvfs_uoc_val_list[i].vu_list[j].volt_log,\r
- dvfs_uoc_val_list[i].vu_list[j].volt_arm_new, \r
- dvfs_uoc_val_list[i].vu_list[j].volt_log_new, \r
- dvfs_uoc_val_list[i].vu_list[j].uoc_val);\r
- mdelay(10);\r
- }\r
- }\r
-\r
- return 0;\r
-}\r
-arch_initcall(dvfs_with_uoc_init);\r
-\r
-static unsigned long dvfs_get_cycle_by_rate(unsigned long rate_khz)\r
-{\r
- int i = 0;\r
- for (i = 0; i < size_dvfs_arm_table - 1; i++) {\r
- if (rate_khz == rate_cycle[i].rate_khz)\r
- return rate_cycle[i].cycle_ns;\r
- }\r
- DVFS_ERR("%s, %d: can not find rate=%lu KHz in list\n", __func__, __LINE__, rate_khz);\r
- return -1;\r
-}\r
-#define UOC_NEED_INCREASE_ARM 0\r
-#define UOC_NEED_INCREASE_LOG 1\r
-static unsigned long get_uoc_delay(unsigned long hold, unsigned long uoc_val_xx)\r
-{\r
- // hold - uoc_val_11; make sure not smaller than UOC_VAL_MIN\r
- return hold > uoc_val_xx ? (hold - uoc_val_xx) : UOC_VAL_MIN;\r
-}\r
-static unsigned long dvfs_recalc_volt(unsigned long *p_volt_arm_new, unsigned long *p_volt_log_new,\r
- unsigned long arm_perf, unsigned long log_perf,\r
- unsigned long hold, unsigned long setup, unsigned long flag)\r
-{\r
- int i = 0;\r
- unsigned long volt_arm = *p_volt_arm_new, volt_log = *p_volt_log_new;\r
- unsigned long curr_delay = 0;\r
- unsigned long uoc_val_11 = dvfs_get_uoc_val_xx_by_volt(UOC_VAL_11, *p_volt_log_new);\r
-\r
- if (flag == UOC_NEED_INCREASE_LOG) {\r
- for (i = 0; i < ARRAY_SIZE(dvfs_volt_log_support_table); i++) {\r
- if (dvfs_volt_log_support_table[i] <= volt_log)\r
- continue;\r
-\r
- volt_log = dvfs_volt_log_support_table[i];\r
- log_perf = dvfs_get_perf_byvolt(volt_log);\r
- uoc_val_11 = dvfs_get_uoc_val_xx_by_volt(UOC_VAL_11, volt_log);\r
- curr_delay = dvfs_get_gate_delay(arm_perf, log_perf);\r
- DVFS_DBG("\t%s line:%d get volt=%lu; arm_perf=%lu, log_perf=%lu, curr_delay=%lu\n",\r
- __func__, __LINE__, dvfs_volt_log_support_table[i],\r
- arm_perf, log_perf, curr_delay);\r
- if (curr_delay > get_uoc_delay(hold, uoc_val_11)) {\r
- *p_volt_log_new = volt_log;\r
- break;\r
- }\r
- }\r
- } else if (flag == UOC_NEED_INCREASE_ARM) {\r
- for (i = 0; i < ARRAY_SIZE(dvfs_volt_arm_support_table); i++) {\r
- if (dvfs_volt_arm_support_table[i] <= volt_arm)\r
- continue;\r
-\r
- volt_arm = dvfs_volt_arm_support_table[i];\r
- arm_perf = dvfs_get_perf_byvolt(volt_arm);\r
- curr_delay = dvfs_get_gate_delay(arm_perf, log_perf);\r
- DVFS_DBG("\t%s line:%d get volt=%lu; arm_perf=%lu, log_perf=%lu, curr_delay=%lu\n",\r
- __func__, __LINE__, dvfs_volt_log_support_table[i],\r
- arm_perf, log_perf, curr_delay);\r
- if (curr_delay < setup) {\r
- *p_volt_arm_new = volt_arm;\r
- break;\r
- }\r
- }\r
-\r
- } else {\r
- DVFS_ERR("Oops, some bugs here, %s Unknown flag:%08lx\n", __func__, flag);\r
- }\r
- return curr_delay;\r
-}\r
-\r
-static int dvfs_get_uoc_val_init(unsigned long *p_volt_arm_new, unsigned long *p_volt_log_new, unsigned long rate_khz)\r
-{\r
- int uoc_val = 0;\r
- unsigned long arm_perf = 0, log_perf = 0;\r
- unsigned long cycle = 0, hold = 0, setup = 0;\r
- unsigned long curr_delay = 0; // arm slow than log\r
- //unsigned long volt_arm_new = *p_volt_arm_new;\r
- //unsigned long volt_log_new = *p_volt_log_new;\r
- unsigned long uoc_val_01 , uoc_val_11;\r
- //unsigned long rate_MHz;\r
- //DVFS_DBG("enter %s\n", __func__);\r
- arm_perf = dvfs_get_perf_byvolt(*p_volt_arm_new);\r
- log_perf = dvfs_get_perf_byvolt(*p_volt_log_new);\r
- uoc_val_01 = dvfs_get_uoc_val_xx_by_volt(UOC_VAL_01, *p_volt_log_new);\r
- uoc_val_11 = dvfs_get_uoc_val_xx_by_volt(UOC_VAL_11, *p_volt_log_new);\r
- DVFS_DBG("%s volt:arm(%lu), log(%lu);\tget perf arm(%lu), log(%lu)\n", __func__,\r
- *p_volt_arm_new, *p_volt_log_new, arm_perf, log_perf);\r
-\r
- // warning: this place may cause div 0 warning, DO NOT take place\r
- // rate_MHz with (rate / DVFS_MHZ)\r
- // rate_MHz = rate_khz / 1000;\r
- // cycle = (1000UL * VD_DELAY_ZOOM) / (rate_khz / 1000); // ns = 1 / rate(GHz), Magnified 1000 times\r
- cycle = dvfs_get_cycle_by_rate(rate_khz);\r
-\r
- hold = cycle * L2_HOLD / 100UL;\r
- setup = cycle * L2_SETUP / 100UL;\r
-\r
- curr_delay = dvfs_get_gate_delay(arm_perf, log_perf);\r
- DVFS_DBG("%s cycle=%lu, curr_delay=%lu, (hold=%lu, setup=%lu)\n",\r
- __func__, cycle, curr_delay, hold, setup);\r
-\r
- if (curr_delay <= get_uoc_delay(hold, uoc_val_11)) {\r
- DVFS_DBG("%s Need to increase log voltage\n", __func__);\r
- curr_delay = dvfs_recalc_volt(p_volt_arm_new, p_volt_log_new, arm_perf, log_perf,\r
- hold, setup, UOC_NEED_INCREASE_LOG);\r
-\r
- //log_perf = dvfs_get_perf_byvolt(*p_volt_log_new);\r
- uoc_val_01 = dvfs_get_uoc_val_xx_by_volt(UOC_VAL_01, *p_volt_log_new);\r
- uoc_val_11 = dvfs_get_uoc_val_xx_by_volt(UOC_VAL_11, *p_volt_log_new);\r
-\r
- } else if (curr_delay >= setup) {\r
- DVFS_DBG("%s Need to increase arm voltage\n", __func__);\r
- curr_delay = dvfs_recalc_volt(p_volt_arm_new, p_volt_log_new, arm_perf, log_perf,\r
- hold, setup, UOC_NEED_INCREASE_ARM);\r
- //arm_perf = dvfs_get_perf_byvolt(*p_volt_arm_new);\r
- }\r
-\r
- DVFS_DBG("TARGET VOLT:arm(%lu), log(%lu);\tget perf arm(%lu), log(%lu)\n",\r
- *p_volt_arm_new, *p_volt_log_new, \r
- dvfs_get_perf_byvolt(*p_volt_arm_new), dvfs_get_perf_byvolt(*p_volt_log_new));\r
- // update uoc_val_01/11 with new volt\r
- DVFS_DBG("cycle=%lu, hold-val11=%lu, hold-val01=%lu, (hold=%lu, setup=%lu), curr_delay=%lu\n",\r
- cycle, get_uoc_delay(hold, uoc_val_11), get_uoc_delay(hold, uoc_val_01),\r
- hold, setup, curr_delay);\r
- if (curr_delay > hold && curr_delay < setup)\r
- uoc_val = 0;\r
- else if (curr_delay <= hold && curr_delay > get_uoc_delay(hold, uoc_val_01))\r
- uoc_val = 1;\r
- else if (curr_delay <= get_uoc_delay(hold, uoc_val_01) && curr_delay > get_uoc_delay(hold, uoc_val_11))\r
- uoc_val = 3;\r
-\r
- DVFS_DBG("%s curr_delay=%lu, uoc_val=%d\n", __func__, curr_delay, uoc_val);\r
-\r
- return uoc_val;\r
-}\r
-static int dvfs_get_uoc_val(unsigned long *p_volt_arm_new, unsigned long *p_volt_log_new, \r
- unsigned long rate_khz)\r
-{ \r
- int i = 0, j = 0;\r
- for (i = 0; i < size_dvfs_arm_table; i++) {\r
- if (dvfs_uoc_val_list[i].rate_arm != rate_khz)\r
- continue;\r
- for (j = 0; j < SIZE_SUPPORT_LOG_VOLT - 1; j++) {\r
- if (dvfs_uoc_val_list[i].vu_list[j].volt_log < *p_volt_log_new)\r
- continue;\r
- *p_volt_arm_new = dvfs_uoc_val_list[i].vu_list[j].volt_arm_new;\r
- *p_volt_log_new = dvfs_uoc_val_list[i].vu_list[j].volt_log_new;\r
- DVFS_DBG("%s: Varm_set=%lu, Vlog_set=%lu, uoc=%d\n", __func__,\r
- *p_volt_arm_new, *p_volt_log_new,\r
- dvfs_uoc_val_list[i].vu_list[j].uoc_val);\r
- return dvfs_uoc_val_list[i].vu_list[j].uoc_val;\r
- }\r
- }\r
- DVFS_ERR("%s: can not get uoc_val(Va=%lu, Vl=%lu, Ra=%lu)\n", __func__, \r
- *p_volt_arm_new, *p_volt_log_new, rate_khz);\r
- return -1;\r
-}\r
-static int dvfs_set_uoc_val(int uoc_val)\r
-{\r
- DVFS_DBG("%s set UOC = %d\n", __func__, uoc_val);\r
- writel_relaxed(\r
- ((readl_relaxed(RK30_GRF_BASE + GRF_UOC3_CON0) | (3 << (12 + 16)))\r
- & (~(3 << 12))) | (uoc_val << 12), RK30_GRF_BASE + GRF_UOC3_CON0);\r
-\r
- DVFS_DBG("read UOC=0x%08x\n", readl_relaxed(RK30_GRF_BASE + GRF_UOC3_CON0));\r
- return 0;\r
-}\r
-\r
-static int target_set_rate(struct clk_node *dvfs_clk, unsigned long rate_new)\r
-{\r
- int ret = 0;\r
-\r
- if (dvfs_clk->clk_dvfs_target) {\r
- ret = dvfs_clk->clk_dvfs_target(dvfs_clk->clk, rate_new, clk_set_rate_locked);\r
- } else {\r
- ret = clk_set_rate_locked(dvfs_clk->clk, rate_new);\r
- }\r
- if (!ret)\r
- dvfs_clk->set_freq = rate_new / 1000;\r
- return ret;\r
-\r
-}\r
-static int dvfs_balance_volt(unsigned long volt_arm_old, unsigned long volt_log_old)\r
-{\r
- int ret = 0;\r
- if (volt_arm_old > volt_log_old)\r
- ret = dvfs_scale_volt_direct(&vd_core, volt_arm_old);\r
- if (volt_arm_old < volt_log_old)\r
- ret = dvfs_scale_volt_direct(&vd_cpu, volt_log_old);\r
- if (ret)\r
- DVFS_ERR("%s error, volt_arm_old=%lu, volt_log_old=%lu\n", __func__, volt_arm_old, volt_log_old);\r
- return ret;\r
-}\r
-#if 0\r
-// use 24M to switch uoc bits\r
-static int uoc_pre = 0;\r
-static int dvfs_scale_volt_rate_with_uoc(\r
- unsigned long volt_arm_new, unsigned long volt_log_new,\r
- unsigned long volt_arm_old, unsigned long volt_log_old,\r
- unsigned long rate_arm_new)\r
-{\r
- int uoc_val = 0;\r
- unsigned int axi_div = 0x0;\r
- unsigned long flags, lpj_save;\r
- DVFS_DBG("Va_new=%lu uV, Vl_new=%lu uV;(was Va_old=%lu uV, Vl_old=%lu uV); Ra_new=%luHz\n",\r
- volt_arm_new, volt_log_new, volt_arm_old, volt_log_old,\r
- rate_arm_new);\r
- axi_div = readl_relaxed(RK30_CRU_BASE + CRU_CLKSELS_CON(1));\r
- uoc_val = dvfs_get_uoc_val(&volt_arm_new, &volt_log_new, rate_arm_new);\r
- if (uoc_val == uoc_pre) {\r
- dvfs_scale_volt_bystep(&vd_cpu, &vd_core, volt_arm_new, volt_log_new,\r
- 100 * 1000, 100 * 1000,\r
- volt_arm_new > volt_log_new ? (volt_arm_new - volt_log_new) : 0,\r
- volt_log_new > volt_arm_new ? (volt_log_new - volt_arm_new) : 0);\r
- } else {\r
-\r
- //local_irq_save(flags);\r
- preempt_disable();\r
- u32 t[10];\r
- t[0] = readl_relaxed(RK30_TIMER1_BASE + 4);\r
- lpj_save = loops_per_jiffy;\r
-\r
- //arm slow mode\r
- writel_relaxed(PLL_MODE_SLOW(APLL_ID), RK30_CRU_BASE + CRU_MODE_CON);\r
- loops_per_jiffy = lpj_24m;\r
- smp_wmb();\r
-\r
- arm_pll_clk->rate = arm_pll_clk->recalc(arm_pll_clk);\r
-\r
- //cpu_axi parent to apll\r
- //writel_relaxed(0x00200000, RK30_CRU_BASE + CRU_CLKSELS_CON(0));\r
- clk_set_parent_nolock(clk_cpu_div, arm_pll_clk);\r
-\r
- //set axi/ahb/apb to 1:1:1\r
- writel_relaxed(axi_div & (~(0x3 << 0)) & (~(0x3 << 8)) & (~(0x3 << 12)), RK30_CRU_BASE + CRU_CLKSELS_CON(1));\r
-\r
- t[1] = readl_relaxed(RK30_TIMER1_BASE + 4);\r
- /*********************/\r
- //balance voltage before set UOC bits\r
- dvfs_balance_volt(volt_arm_old, volt_log_old);\r
- t[2] = readl_relaxed(RK30_TIMER1_BASE + 4);\r
-\r
- //set UOC bits\r
- dvfs_set_uoc_val(uoc_val);\r
- t[3] = readl_relaxed(RK30_TIMER1_BASE + 4);\r
-\r
- //voltage up\r
- dvfs_scale_volt_bystep(&vd_cpu, &vd_core, volt_arm_new, volt_log_new,\r
- 100 * 1000, 100 * 1000,\r
- volt_arm_new > volt_log_new ? (volt_arm_new - volt_log_new) : 0,\r
- volt_log_new > volt_arm_new ? (volt_log_new - volt_arm_new) : 0);\r
- t[4] = readl_relaxed(RK30_TIMER1_BASE + 4);\r
-\r
- /*********************/\r
- //set axi/ahb/apb to default\r
- writel_relaxed(axi_div, RK30_CRU_BASE + CRU_CLKSELS_CON(1));\r
-\r
- //cpu_axi parent to gpll\r
- //writel_relaxed(0x00200020, RK30_CRU_BASE + CRU_CLKSELS_CON(0));\r
- clk_set_parent_nolock(clk_cpu_div, general_pll_clk);\r
-\r
- //arm normal mode\r
- writel_relaxed(PLL_MODE_NORM(APLL_ID), RK30_CRU_BASE + CRU_MODE_CON);\r
- loops_per_jiffy = lpj_save;\r
- smp_wmb();\r
-\r
- arm_pll_clk->rate = arm_pll_clk->recalc(arm_pll_clk);\r
-\r
- t[5] = readl_relaxed(RK30_TIMER1_BASE + 4);\r
- preempt_enable();\r
- //local_irq_restore(flags);\r
- DVFS_DBG(KERN_DEBUG "T %d %d %d %d %d\n", t[0] - t[1], t[1] - t[2], t[2] - t[3], t[3] - t[4], t[4] - t[5]);\r
- uoc_pre = uoc_val;\r
- }\r
- return 0;\r
-}\r
-#else\r
-// use 312M to switch uoc bits\r
-static int uoc_pre = 0;\r
-static int dvfs_scale_volt_rate_with_uoc(\r
- unsigned long volt_arm_new, unsigned long volt_log_new,\r
- unsigned long volt_arm_old, unsigned long volt_log_old,\r
- unsigned long rate_arm_new)\r
-{\r
- int uoc_val = 0;\r
- unsigned long arm_freq = 0;\r
- uoc_val = dvfs_get_uoc_val(&volt_arm_new, &volt_log_new, rate_arm_new);\r
- DVFS_DBG("Va_new=%lu uV, Vl_new=%lu uV;(was Va_old=%lu uV, Vl_old=%lu uV); Ra_new=%luHz, uoc=%d\n",\r
- volt_arm_new, volt_log_new, volt_arm_old, volt_log_old, rate_arm_new, uoc_val);\r
- if (uoc_val == uoc_pre) {\r
- dvfs_scale_volt_bystep(&vd_cpu, &vd_core, volt_arm_new, volt_log_new,\r
- 100 * 1000, 100 * 1000,\r
- volt_arm_new > volt_log_new ? (volt_arm_new - volt_log_new) : 0,\r
- volt_log_new > volt_arm_new ? (volt_log_new - volt_arm_new) : 0);\r
- } else {\r
- //save arm freq\r
- arm_freq = clk_get_rate(clk_cpu);\r
- target_set_rate(dvfs_clk_cpu, 312 * MHZ);\r
-\r
- //cpu_axi parent to apll\r
- //writel_relaxed(0x00200000, RK30_CRU_BASE + CRU_CLKSELS_CON(0));\r
- clk_set_parent_nolock(clk_cpu_div, arm_pll_clk);\r
-\r
- /*********************/\r
- //balance voltage before set UOC bits\r
- dvfs_balance_volt(volt_arm_old, volt_log_old);\r
-\r
- //set UOC bits\r
- dvfs_set_uoc_val(uoc_val);\r
-\r
- //voltage up\r
- dvfs_scale_volt_bystep(&vd_cpu, &vd_core, volt_arm_new, volt_log_new,\r
- 100 * 1000, 100 * 1000,\r
- volt_arm_new > volt_log_new ? (volt_arm_new - volt_log_new) : 0,\r
- volt_log_new > volt_arm_new ? (volt_log_new - volt_arm_new) : 0);\r
-\r
- /*********************/\r
- //cpu_axi parent to gpll\r
- //writel_relaxed(0x00200020, RK30_CRU_BASE + CRU_CLKSELS_CON(0));\r
- clk_set_parent_nolock(clk_cpu_div, general_pll_clk);\r
-\r
- //reset arm freq as normal freq\r
- target_set_rate(dvfs_clk_cpu, arm_freq);\r
-\r
- uoc_pre = uoc_val;\r
- }\r
- return 0;\r
-}\r
-#endif\r
-int dvfs_target_cpu(struct clk *clk, unsigned long rate_hz)\r
-{\r
- struct clk_node *dvfs_clk;\r
- int ret = 0;\r
- int volt_new = 0, volt_dep_new = 0, volt_old = 0, volt_dep_old = 0;\r
- struct cpufreq_frequency_table clk_fv;\r
- unsigned long rate_new, rate_old;\r
-\r
- if (!clk) {\r
- DVFS_ERR("%s is not a clk\n", __func__);\r
- return -1;\r
- }\r
- dvfs_clk = clk_get_dvfs_info(clk);\r
- DVFS_DBG("enter %s: clk(%s) rate = %lu Hz\n", __func__, dvfs_clk->name, rate_hz);\r
-\r
- if (!dvfs_clk || dvfs_clk->vd == NULL || IS_ERR_OR_NULL(dvfs_clk->vd->regulator)) {\r
- DVFS_ERR("dvfs(%s) is not register regulator\n", dvfs_clk->name);\r
- return -1;\r
- }\r
-\r
- if (dvfs_clk->vd->volt_set_flag == DVFS_SET_VOLT_FAILURE) {\r
- /* It means the last time set voltage error */\r
- ret = dvfs_reset_volt(dvfs_clk->vd);\r
- if (ret < 0) {\r
- return -1;\r
- }\r
- }\r
-\r
- /* Check limit rate */\r
- if (rate_hz < dvfs_clk->min_rate) {\r
- rate_hz = dvfs_clk->min_rate;\r
- } else if (rate_hz > dvfs_clk->max_rate) {\r
- rate_hz = dvfs_clk->max_rate;\r
- }\r
-\r
- /* need round rate */\r
- volt_old = vd_cpu.cur_volt;\r
- volt_dep_old = vd_core.cur_volt;\r
-\r
- rate_old = clk_get_rate(clk);\r
- rate_new = clk_round_rate_nolock(clk, rate_hz);\r
- if(rate_new == rate_old)\r
- return 0;\r
-\r
- DVFS_DBG("dvfs(%s) round rate (%lu)(rount %lu) old (%lu)\n",\r
- dvfs_clk->name, rate_hz, rate_new, rate_old);\r
-\r
- /* find the clk corresponding voltage */\r
- if (0 != dvfs_clk_get_ref_volt(dvfs_clk, rate_new / 1000, &clk_fv)) {\r
- DVFS_ERR("dvfs(%s) rate %luhz is larger,not support\n", dvfs_clk->name, rate_hz);\r
- return -1;\r
- }\r
- dvfs_clk->set_volt = clk_fv.index;\r
-\r
- // target\r
- volt_new = dvfs_vd_get_newvolt_byclk(dvfs_clk);\r
- volt_dep_new = dvfs_vd_get_newvolt_bypd(&vd_core);\r
-\r
- if (volt_dep_new <= 0)\r
- goto fail_roll_back;\r
-\r
- if (rate_new < rate_old)\r
- target_set_rate(dvfs_clk, rate_new);\r
-\r
- dvfs_scale_volt_rate_with_uoc(volt_new, volt_dep_new, volt_old, volt_dep_old,\r
- rate_new / 1000);\r
-\r
- if (rate_new > rate_old)\r
- target_set_rate(dvfs_clk, rate_new);\r
-\r
-\r
- DVFS_DBG("UOC VOLT OK\n");\r
-\r
- return 0;\r
-fail_roll_back:\r
- //dvfs_clk = clk_get_rate(dvfs_clk->clk);\r
- return -1;\r
-}\r
-\r
-int dvfs_target_core(struct clk *clk, unsigned long rate_hz)\r
-{\r
- struct clk_node *dvfs_clk;\r
- int ret = 0;\r
- int volt_new = 0, volt_dep_new = 0, volt_old = 0, volt_dep_old = 0;\r
- struct cpufreq_frequency_table clk_fv;\r
- unsigned long rate_new, rate_old;\r
-\r
- if (!clk) {\r
- DVFS_ERR("%s is not a clk\n", __func__);\r
- return -1;\r
- }\r
- dvfs_clk = clk_get_dvfs_info(clk);\r
- DVFS_DBG("enter %s: clk(%s) rate = %lu Hz\n", __func__, dvfs_clk->name, rate_hz);\r
-\r
- if (!dvfs_clk || dvfs_clk->vd == NULL || IS_ERR_OR_NULL(dvfs_clk->vd->regulator)) {\r
- DVFS_ERR("dvfs(%s) is not register regulator\n", dvfs_clk->name);\r
- return -1;\r
- }\r
-\r
- if (dvfs_clk->vd->volt_set_flag == DVFS_SET_VOLT_FAILURE) {\r
- /* It means the last time set voltage error */\r
- ret = dvfs_reset_volt(dvfs_clk->vd);\r
- if (ret < 0) {\r
- return -1;\r
- }\r
- }\r
-\r
- /* Check limit rate */\r
- if (rate_hz < dvfs_clk->min_rate) {\r
- rate_hz = dvfs_clk->min_rate;\r
- } else if (rate_hz > dvfs_clk->max_rate) {\r
- rate_hz = dvfs_clk->max_rate;\r
- }\r
-\r
- /* need round rate */\r
- volt_old = vd_cpu.cur_volt;\r
- volt_dep_old = vd_core.cur_volt;\r
-\r
- rate_old = clk_get_rate(clk);\r
- rate_new = clk_round_rate_nolock(clk, rate_hz);\r
- if(rate_new == rate_old)\r
- return 0;\r
-\r
- DVFS_DBG("dvfs(%s) round rate (%lu)(rount %lu) old (%lu)\n",\r
- dvfs_clk->name, rate_hz, rate_new, rate_old);\r
-\r
- /* find the clk corresponding voltage */\r
- if (0 != dvfs_clk_get_ref_volt(dvfs_clk, rate_new / 1000, &clk_fv)) {\r
- DVFS_ERR("dvfs(%s) rate %luhz is larger,not support\n", dvfs_clk->name, rate_hz);\r
- return -1;\r
- }\r
- dvfs_clk->set_volt = clk_fv.index;\r
-\r
- // target arm:volt_new/old, log:volt_dep_new/old\r
- volt_dep_new = dvfs_vd_get_newvolt_byclk(dvfs_clk);\r
- volt_new = dvfs_vd_get_newvolt_bypd(&vd_cpu);\r
-\r
- if (volt_dep_new <= 0)\r
- goto fail_roll_back;\r
-\r
- if (rate_new < rate_old)\r
- target_set_rate(dvfs_clk, rate_new);\r
-\r
- dvfs_scale_volt_rate_with_uoc(volt_new, volt_dep_new, volt_old, volt_dep_old,\r
- dvfs_clk_cpu->set_freq);\r
-\r
- if (rate_new > rate_old)\r
- target_set_rate(dvfs_clk, rate_new);\r
-\r
- DVFS_DBG("UOC VOLT OK\n");\r
-\r
- return 0;\r
-fail_roll_back:\r
- //dvfs_clk = clk_get_rate(dvfs_clk->clk);\r
- return -1;\r
-}\r
-\r
-/*****************************init**************************/\r
-/**\r
- * rate must be raising sequence\r
- */\r
-static struct cpufreq_frequency_table cpu_dvfs_table[] = {\r
- // {.frequency = 48 * DVFS_KHZ, .index = 920*DVFS_MV},\r
- // {.frequency = 126 * DVFS_KHZ, .index = 970 * DVFS_MV},\r
- // {.frequency = 252 * DVFS_KHZ, .index = 1040 * DVFS_MV},\r
- // {.frequency = 504 * DVFS_KHZ, .index = 1050 * DVFS_MV},\r
- {.frequency = 816 * DVFS_KHZ, .index = 1050 * DVFS_MV},\r
- // {.frequency = 1008 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
- {.frequency = CPUFREQ_TABLE_END},\r
-};\r
-\r
-static struct cpufreq_frequency_table ddr_dvfs_table[] = {\r
- // {.frequency = 100 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
- {.frequency = 200 * DVFS_KHZ, .index = 1000 * DVFS_MV},\r
- {.frequency = 300 * DVFS_KHZ, .index = 1050 * DVFS_MV},\r
- {.frequency = 400 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
- {.frequency = 500 * DVFS_KHZ, .index = 1150 * DVFS_MV},\r
- {.frequency = 600 * DVFS_KHZ, .index = 1200 * DVFS_MV},\r
- {.frequency = CPUFREQ_TABLE_END},\r
-};\r
-\r
-static struct cpufreq_frequency_table gpu_dvfs_table[] = {\r
- {.frequency = 90 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
- {.frequency = 180 * DVFS_KHZ, .index = 1150 * DVFS_MV},\r
- {.frequency = 300 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
- {.frequency = 400 * DVFS_KHZ, .index = 1150 * DVFS_MV},\r
- {.frequency = 500 * DVFS_KHZ, .index = 1200 * DVFS_MV},\r
- {.frequency = CPUFREQ_TABLE_END},\r
-};\r
-\r
-static struct cpufreq_frequency_table peri_aclk_dvfs_table[] = {\r
- {.frequency = 100 * DVFS_KHZ, .index = 1000 * DVFS_MV},\r
- {.frequency = 200 * DVFS_KHZ, .index = 1050 * DVFS_MV},\r
- {.frequency = 300 * DVFS_KHZ, .index = 1070 * DVFS_MV},\r
- {.frequency = 500 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
- {.frequency = CPUFREQ_TABLE_END},\r
-};\r
-\r
-static struct cpufreq_frequency_table dep_cpu2core_table[] = {\r
- // {.frequency = 252 * DVFS_KHZ, .index = 1025 * DVFS_MV},\r
- // {.frequency = 504 * DVFS_KHZ, .index = 1025 * DVFS_MV},\r
- {.frequency = 816 * DVFS_KHZ, .index = 1050 * DVFS_MV},//logic 1.050V\r
- // {.frequency = 1008 * DVFS_KHZ,.index = 1050 * DVFS_MV},\r
- // {.frequency = 1200 * DVFS_KHZ,.index = 1050 * DVFS_MV},\r
- // {.frequency = 1272 * DVFS_KHZ,.index = 1050 * DVFS_MV},//logic 1.050V\r
- // {.frequency = 1416 * DVFS_KHZ,.index = 1100 * DVFS_MV},//logic 1.100V\r
- // {.frequency = 1512 * DVFS_KHZ,.index = 1125 * DVFS_MV},//logic 1.125V\r
- // {.frequency = 1608 * DVFS_KHZ,.index = 1175 * DVFS_MV},//logic 1.175V\r
- {.frequency = CPUFREQ_TABLE_END},\r
-};\r
-\r
-static struct vd_node vd_cpu = {\r
- .name = "vd_cpu",\r
- .regulator_name = "vdd_cpu",\r
- .volt_set_flag = DVFS_SET_VOLT_FAILURE,\r
- .vd_dvfs_target = dvfs_target_cpu,\r
-};\r
-\r
-static struct vd_node vd_core = {\r
- .name = "vd_core",\r
- .regulator_name = "vdd_core",\r
- .volt_set_flag = DVFS_SET_VOLT_FAILURE,\r
- .vd_dvfs_target = dvfs_target_core,\r
-};\r
-\r
-static struct vd_node vd_rtc = {\r
- .name = "vd_rtc",\r
- .regulator_name = "vdd_rtc",\r
- .volt_set_flag = DVFS_SET_VOLT_FAILURE,\r
- .vd_dvfs_target = NULL,\r
-};\r
-\r
-static struct vd_node *rk30_vds[] = {&vd_cpu, &vd_core, &vd_rtc};\r
-\r
-static struct pd_node pd_a9_0 = {\r
- .name = "pd_a9_0",\r
- .vd = &vd_cpu,\r
-};\r
-static struct pd_node pd_a9_1 = {\r
- .name = "pd_a9_1",\r
- .vd = &vd_cpu,\r
-};\r
-static struct pd_node pd_debug = {\r
- .name = "pd_debug",\r
- .vd = &vd_cpu,\r
-};\r
-static struct pd_node pd_scu = {\r
- .name = "pd_scu",\r
- .vd = &vd_cpu,\r
-};\r
-static struct pd_node pd_video = {\r
- .name = "pd_video",\r
- .vd = &vd_core,\r
-};\r
-static struct pd_node pd_vio = {\r
- .name = "pd_vio",\r
- .vd = &vd_core,\r
-};\r
-static struct pd_node pd_gpu = {\r
- .name = "pd_gpu",\r
- .vd = &vd_core,\r
-};\r
-static struct pd_node pd_peri = {\r
- .name = "pd_peri",\r
- .vd = &vd_core,\r
-};\r
-static struct pd_node pd_cpu = {\r
- .name = "pd_cpu",\r
- .vd = &vd_core,\r
-};\r
-static struct pd_node pd_alive = {\r
- .name = "pd_alive",\r
- .vd = &vd_core,\r
-};\r
-static struct pd_node pd_rtc = {\r
- .name = "pd_rtc",\r
- .vd = &vd_rtc,\r
-};\r
-#define LOOKUP_PD(_ppd) \\r
-{ \\r
- .pd = _ppd, \\r
-}\r
-static struct pd_node_lookup rk30_pds[] = {\r
- LOOKUP_PD(&pd_a9_0),\r
- LOOKUP_PD(&pd_a9_1),\r
- LOOKUP_PD(&pd_debug),\r
- LOOKUP_PD(&pd_scu),\r
- LOOKUP_PD(&pd_video),\r
- LOOKUP_PD(&pd_vio),\r
- LOOKUP_PD(&pd_gpu),\r
- LOOKUP_PD(&pd_peri),\r
- LOOKUP_PD(&pd_cpu),\r
- LOOKUP_PD(&pd_alive),\r
- LOOKUP_PD(&pd_rtc),\r
-};\r
-\r
-#define CLK_PDS(_ppd) \\r
-{ \\r
- .pd = _ppd, \\r
-}\r
-\r
-static struct pds_list cpu_pds[] = {\r
- CLK_PDS(&pd_a9_0),\r
- CLK_PDS(&pd_a9_1),\r
- CLK_PDS(NULL),\r
-};\r
-\r
-static struct pds_list ddr_pds[] = {\r
- CLK_PDS(&pd_cpu),\r
- CLK_PDS(NULL),\r
-};\r
-\r
-static struct pds_list gpu_pds[] = {\r
- CLK_PDS(&pd_gpu),\r
- CLK_PDS(NULL),\r
-};\r
-\r
-static struct pds_list aclk_periph_pds[] = {\r
- CLK_PDS(&pd_peri),\r
- CLK_PDS(NULL),\r
-};\r
-\r
-#define RK_CLKS(_clk_name, _ppds, _dvfs_table, _dvfs_nb) \\r
-{ \\r
- .name = _clk_name, \\r
- .pds = _ppds,\\r
- .dvfs_table = _dvfs_table, \\r
- .dvfs_nb = _dvfs_nb, \\r
-}\r
-\r
-static struct clk_node rk30_clks[] = {\r
- RK_CLKS("cpu", cpu_pds, cpu_dvfs_table, &rk_dvfs_clk_notifier),\r
- RK_CLKS("ddr", ddr_pds, ddr_dvfs_table, &rk_dvfs_clk_notifier),\r
- RK_CLKS("gpu", gpu_pds, gpu_dvfs_table, &rk_dvfs_clk_notifier),\r
- RK_CLKS("aclk_periph", aclk_periph_pds, peri_aclk_dvfs_table, &rk_dvfs_clk_notifier),\r
-};\r
-\r
-#define RK_DEPPENDS(_clk_name, _pvd, _dep_table) \\r
-{ \\r
- .clk_name = _clk_name, \\r
- .dep_vd = _pvd,\\r
- .dep_table = _dep_table, \\r
-}\r
-\r
-static struct depend_lookup rk30_depends[] = {\r
-#ifndef CONFIG_ARCH_RK3066B\r
- RK_DEPPENDS("cpu", &vd_core, dep_cpu2core_table),\r
-#endif\r
- //RK_DEPPENDS("gpu", &vd_cpu, NULL),\r
- //RK_DEPPENDS("gpu", &vd_cpu, NULL),\r
-};\r
-static struct avs_ctr_st rk30_avs_ctr;\r
-\r
-int rk_dvfs_init(void)\r
-{\r
- int i = 0;\r
- for (i = 0; i < ARRAY_SIZE(rk30_vds); i++) {\r
- rk_regist_vd(rk30_vds[i]);\r
- }\r
- for (i = 0; i < ARRAY_SIZE(rk30_pds); i++) {\r
- rk_regist_pd(&rk30_pds[i]);\r
- }\r
- for (i = 0; i < ARRAY_SIZE(rk30_clks); i++) {\r
- rk_regist_clk(&rk30_clks[i]);\r
- }\r
- for (i = 0; i < ARRAY_SIZE(rk30_depends); i++) {\r
- rk_regist_depends(&rk30_depends[i]);\r
- }\r
- dvfs_clk_cpu = dvfs_get_dvfs_clk_byname("cpu");\r
- clk_cpu = clk_get(NULL, "cpu");\r
- if (IS_ERR_OR_NULL(clk_cpu)) {\r
- DVFS_ERR("%s get clk_cpu error\n", __func__);\r
- return -1;\r
- }\r
-\r
- clk_cpu_div = clk_get(NULL, "logic");\r
- if (IS_ERR_OR_NULL(clk_cpu_div)) {\r
- DVFS_ERR("%s get clk_cpu_div error\n", __func__);\r
- return -1;\r
- }\r
-\r
- arm_pll_clk = clk_get(NULL, "arm_pll");\r
- if (IS_ERR_OR_NULL(arm_pll_clk)) {\r
- DVFS_ERR("%s get arm_pll_clk error\n", __func__);\r
- return -1;\r
- }\r
-\r
- general_pll_clk = clk_get(NULL, "general_pll");\r
- if (IS_ERR_OR_NULL(general_pll_clk)) {\r
- DVFS_ERR("%s get general_pll_clk error\n", __func__);\r
- return -1;\r
- }\r
-\r
- avs_board_init(&rk30_avs_ctr);\r
- DVFS_DBG("rk30_dvfs_init\n");\r
- return 0;\r
-}\r
-\r
-\r
-\r
-/******************************rk30 avs**************************************************/\r
-\r
-#ifdef CONFIG_ARCH_RK3066B\r
-\r
-static void __iomem *rk30_nandc_base = NULL;\r
-\r
-#define nandc_readl(offset) readl_relaxed(rk30_nandc_base + offset)\r
-#define nandc_writel(v, offset) do { writel_relaxed(v, rk30_nandc_base + offset); dsb(); } while (0)\r
-static u8 rk30_get_avs_val(void)\r
-{\r
- u32 nanc_save_reg[4];\r
- unsigned long flags;\r
- u32 paramet = 0;\r
- u32 count = 100;\r
- if(rk30_nandc_base == NULL)\r
- return 0;\r
-\r
- preempt_disable();\r
- local_irq_save(flags);\r
-\r
- nanc_save_reg[0] = nandc_readl(0);\r
- nanc_save_reg[1] = nandc_readl(0x130);\r
- nanc_save_reg[2] = nandc_readl(0x134);\r
- nanc_save_reg[3] = nandc_readl(0x158);\r
-\r
- nandc_writel(nanc_save_reg[0] | 0x1 << 14, 0);\r
- nandc_writel(0x5, 0x130);\r
-\r
- /* Just break lock status */\r
- nandc_writel(0x1, 0x158);\r
- nandc_writel(3, 0x158);\r
- nandc_writel(1, 0x134);\r
-\r
- while(count--) {\r
- paramet = nandc_readl(0x138);\r
- if((paramet & 0x1))\r
- break;\r
- udelay(1);\r
- };\r
- paramet = (paramet >> 1) & 0xff;\r
- nandc_writel(nanc_save_reg[0], 0);\r
- nandc_writel(nanc_save_reg[1], 0x130);\r
- nandc_writel(nanc_save_reg[2], 0x134);\r
- nandc_writel(nanc_save_reg[3], 0x158);\r
-\r
- local_irq_restore(flags);\r
- preempt_enable();\r
- return (u8)paramet;\r
-\r
-}\r
-\r
-void rk30_avs_init(void)\r
-{\r
- rk30_nandc_base = ioremap(RK30_NANDC_PHYS, RK30_NANDC_SIZE);\r
-}\r
-static struct avs_ctr_st rk30_avs_ctr = {\r
- .avs_init = rk30_avs_init,\r
- .avs_get_val = rk30_get_avs_val,\r
-};\r
-#endif\r
-\r
-\r
+++ /dev/null
-/* arch/arm/mach-rk30/rk30_dvfs.c\r
- *\r
- * Copyright (C) 2012 ROCKCHIP, Inc.\r
- *\r
- * This software is licensed under the terms of the GNU General Public\r
- * License version 2, as published by the Free Software Foundation, and\r
- * may be copied, distributed, and modified under those terms.\r
- *\r
- * This program is distributed in the hope that it will be useful,\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- * GNU General Public License for more details.\r
- *\r
- */\r
-\r
-#include <linux/kernel.h>\r
-#include <linux/err.h>\r
-#include <linux/spinlock.h>\r
-#include <linux/list.h>\r
-#include <linux/slab.h>\r
-#include <linux/clk.h>\r
-#include <linux/cpufreq.h>\r
-#include <mach/dvfs.h>\r
-#include <mach/clock.h>\r
-#include <linux/regulator/consumer.h>\r
-#include <linux/delay.h>\r
-#include <linux/io.h>\r
-#include <linux/hrtimer.h>\r
-#include <plat/efuse.h>\r
-\r
-static int rk_dvfs_clk_notifier_event(struct notifier_block *this,\r
- unsigned long event, void *ptr)\r
-{\r
- struct clk_notifier_data *noti_info;\r
- struct clk *clk;\r
- struct clk_node *dvfs_clk;\r
- noti_info = (struct clk_notifier_data *)ptr;\r
- clk = noti_info->clk;\r
- dvfs_clk = clk->dvfs_info;\r
-\r
- switch (event) {\r
- case CLK_PRE_RATE_CHANGE:\r
- DVFS_DBG("%s CLK_PRE_RATE_CHANGE\n", __func__);\r
- break;\r
- case CLK_POST_RATE_CHANGE:\r
- DVFS_DBG("%s CLK_POST_RATE_CHANGE\n", __func__);\r
- break;\r
- case CLK_ABORT_RATE_CHANGE:\r
- DVFS_DBG("%s CLK_ABORT_RATE_CHANGE\n", __func__);\r
- break;\r
- case CLK_PRE_ENABLE:\r
- DVFS_DBG("%s CLK_PRE_ENABLE\n", __func__);\r
- break;\r
- case CLK_POST_ENABLE:\r
- DVFS_DBG("%s CLK_POST_ENABLE\n", __func__);\r
- break;\r
- case CLK_ABORT_ENABLE:\r
- DVFS_DBG("%s CLK_ABORT_ENABLE\n", __func__);\r
- break;\r
- case CLK_PRE_DISABLE:\r
- DVFS_DBG("%s CLK_PRE_DISABLE\n", __func__);\r
- break;\r
- case CLK_POST_DISABLE:\r
- DVFS_DBG("%s CLK_POST_DISABLE\n", __func__);\r
- dvfs_clk->set_freq = 0;\r
- break;\r
- case CLK_ABORT_DISABLE:\r
- DVFS_DBG("%s CLK_ABORT_DISABLE\n", __func__);\r
-\r
- break;\r
- default:\r
- break;\r
- }\r
- return 0;\r
-}\r
-\r
-static struct notifier_block rk_dvfs_clk_notifier = {\r
- .notifier_call = rk_dvfs_clk_notifier_event,\r
-};\r
-\r
-struct lkg_maxvolt {\r
- int leakage_level;\r
- unsigned int maxvolt;\r
-};\r
-static struct lkg_maxvolt lkg_volt_table[] = {\r
- {.leakage_level = 3, .maxvolt = 1350 * 1000},\r
- {.leakage_level = 6, .maxvolt = 1300 * 1000},\r
- {.leakage_level = 15, .maxvolt = 1250 * 1000},\r
-};\r
-static int leakage_level = 0;\r
-#define MHZ (1000 * 1000)\r
-#define KHZ (1000)\r
-// Delayline bound for nandc = 148.5MHz, Varm = Vlog = 1.00V\r
-#define HIGH_DELAYLINE 125\r
-#define LOW_DELAYLINE 125\r
-static u8 rk30_get_avs_val(void);\r
-void dvfs_adjust_table_lmtvolt(struct clk *clk, struct cpufreq_frequency_table *table)\r
-{\r
- int i = 0;\r
- unsigned int maxvolt = 0;\r
- if (IS_ERR_OR_NULL(clk) || IS_ERR_OR_NULL(table)) {\r
- DVFS_ERR("%s: clk error OR table error\n", __func__);\r
- return ;\r
- }\r
-\r
- leakage_level = rk_leakage_val();\r
- printk("DVFS MSG: %s: %s get leakage_level = %d\n", clk->name, __func__, leakage_level);\r
- if (leakage_level == 0) {\r
-\r
- /*\r
- * This is for delayline auto scale voltage,\r
- * FIXME: HIGH_DELAYLINE / LOW_DELAYLINE value maybe redefined under\r
- * Varm = Vlog = 1.00V.\r
- * Warning: this value is frequency/voltage sensitive, care\r
- * about Freq nandc/Volt log.\r
- *\r
- */\r
-\r
- unsigned long delayline_val = 0;\r
- unsigned long high_delayline = 0, low_delayline = 0;\r
- unsigned long rate_nandc = 0;\r
-\r
- // rk3168: do nothing\r
- return;\r
-\r
- rate_nandc = clk_get_rate(clk_get(NULL, "nandc")) / KHZ;\r
- printk("Get nandc rate = %lu KHz\n", rate_nandc);\r
- high_delayline = HIGH_DELAYLINE * 148500 / rate_nandc;\r
- low_delayline = LOW_DELAYLINE * 148500 / rate_nandc;\r
- delayline_val = rk30_get_avs_val();\r
- printk("This chip no leakage msg, use delayline instead, val = %lu.(HDL=%lu, LDL=%lu)\n",\r
- delayline_val, high_delayline, low_delayline);\r
-\r
- if (delayline_val >= high_delayline) {\r
- leakage_level = 4; //same as leakage_level > 4\r
-\r
- } else if (delayline_val <= low_delayline) {\r
- leakage_level = 1;\r
- printk("Delayline TOO LOW, high voltage request\n");\r
-\r
- } else\r
- leakage_level = 2; //same as leakage_level = 3\r
- }\r
-\r
- for (i = 0; i < ARRAY_SIZE(lkg_volt_table); i++) {\r
- if (leakage_level <= lkg_volt_table[i].leakage_level) {\r
- maxvolt = lkg_volt_table[i].maxvolt;\r
- break;\r
- }\r
- }\r
-\r
- for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) {\r
- if (table[i].index > maxvolt) {\r
- printk("\t\tadjust table freq=%d KHz, index=%d mV", table[i].frequency, table[i].index);\r
- table[i].index = maxvolt;\r
- printk(" to index=%d mV\n", table[i].index);\r
- }\r
- }\r
-}\r
-#ifdef CONFIG_ARCH_RK3066B\r
-static int g_arm_high_logic = 0 * 1000;\r
-static int g_logic_high_arm = 50 * 1000;\r
-#else\r
-static int g_arm_high_logic = 150 * 1000;\r
-static int g_logic_high_arm = 100 * 1000;\r
-#endif\r
-\r
-#if defined(CONFIG_SOC_RK3168) || defined(CONFIG_SOC_RK3028)\r
-static struct cpufreq_frequency_table arm_high_logic_table[] = {\r
- {.frequency = 1416 * DVFS_KHZ, .index = 0 * DVFS_MV},\r
- {.frequency = 1608 * DVFS_KHZ, .index = 0 * DVFS_MV},\r
- {.frequency = CPUFREQ_TABLE_END},\r
-};\r
-\r
-static struct cpufreq_frequency_table logic_high_arm_table[] = {\r
- {.frequency = 1008 * DVFS_KHZ, .index = 50 * DVFS_MV},\r
- {.frequency = 1608 * DVFS_KHZ, .index = 50 * DVFS_MV},\r
- {.frequency = CPUFREQ_TABLE_END},\r
-};\r
-#elif defined(CONFIG_ARCH_RK30XX)\r
-static struct cpufreq_frequency_table arm_high_logic_table[] = {\r
- {.frequency = 1416 * DVFS_KHZ, .index = 50 * DVFS_MV},\r
- {.frequency = 1608 * DVFS_KHZ, .index = 100 * DVFS_MV},\r
- {.frequency = CPUFREQ_TABLE_END},\r
-};\r
-static struct cpufreq_frequency_table logic_high_arm_table[] = {\r
- {.frequency = 816 * DVFS_KHZ, .index = 200 * DVFS_MV},\r
- {.frequency = 1416 * DVFS_KHZ, .index = 150 * DVFS_MV},\r
- {.frequency = 1608 * DVFS_KHZ, .index = 100 * DVFS_MV},\r
-};\r
-#else\r
-static struct cpufreq_frequency_table arm_high_logic_table[] = {\r
- {.frequency = 1416 * DVFS_KHZ, .index = 0 * DVFS_MV},\r
- {.frequency = 1608 * DVFS_KHZ, .index = 0 * DVFS_MV},\r
- {.frequency = CPUFREQ_TABLE_END},\r
-};\r
-\r
-static struct cpufreq_frequency_table logic_high_arm_table[] = {\r
- {.frequency = 1008 * DVFS_KHZ, .index = 50 * DVFS_MV},\r
- {.frequency = 1608 * DVFS_KHZ, .index = 50 * DVFS_MV},\r
- {.frequency = CPUFREQ_TABLE_END},\r
-};\r
-#endif\r
-\r
-int get_arm_logic_limit(unsigned long arm_rate, int *arm_high_logic, int *logic_high_arm)\r
-{\r
- int i;\r
-\r
- for (i = 0; arm_high_logic_table[i].frequency != CPUFREQ_TABLE_END; i++) {\r
- if (arm_rate <= arm_high_logic_table[i].frequency) {\r
- *arm_high_logic = arm_high_logic_table[i].index;\r
- break;\r
- }\r
- }\r
-\r
- if (arm_high_logic_table[i].frequency == CPUFREQ_TABLE_END) {\r
- *arm_high_logic = arm_high_logic_table[i-1].index;\r
- }\r
-\r
- for (i = 0; logic_high_arm_table[i].frequency != CPUFREQ_TABLE_END; i++) {\r
- if (arm_rate <= logic_high_arm_table[i].frequency) {\r
- *logic_high_arm = logic_high_arm_table[i].index;\r
- break;\r
- }\r
- }\r
- if (logic_high_arm_table[i].frequency == CPUFREQ_TABLE_END)\r
- *logic_high_arm = logic_high_arm_table[i-1].index;\r
-\r
- return 0;\r
-}\r
-\r
-static struct clk_node *dvfs_clk_cpu;\r
-static struct vd_node vd_core;\r
-int dvfs_target_cpu(struct clk *clk, unsigned long rate_hz)\r
-{\r
- struct clk_node *dvfs_clk;\r
- int volt_new = 0, volt_dep_new = 0, clk_volt_store = 0;\r
- struct cpufreq_frequency_table clk_fv;\r
- int ret = 0;\r
- unsigned long rate_new, rate_old;\r
- int cur_arm_high_logic, cur_logic_high_arm;\r
-\r
- if (!clk) {\r
- DVFS_ERR("%s is not a clk\n", __func__);\r
- return -1;\r
- }\r
- dvfs_clk = clk_get_dvfs_info(clk);\r
- DVFS_DBG("enter %s: clk(%s) rate = %lu Hz\n", __func__, dvfs_clk->name, rate_hz);\r
-\r
- if (!dvfs_clk || dvfs_clk->vd == NULL || IS_ERR_OR_NULL(dvfs_clk->vd->regulator)) {\r
- DVFS_ERR("dvfs(%s) is not register regulator\n", dvfs_clk->name);\r
- return -1;\r
- }\r
-\r
- if (dvfs_clk->vd->volt_set_flag == DVFS_SET_VOLT_FAILURE) {\r
- /* It means the last time set voltage error */\r
- ret = dvfs_reset_volt(dvfs_clk->vd);\r
- if (ret < 0) {\r
- return -1;\r
- }\r
- }\r
-\r
- /* Check limit rate */\r
- //if (dvfs_clk->freq_limit_en) {\r
- if (rate_hz < dvfs_clk->min_rate) {\r
- rate_hz = dvfs_clk->min_rate;\r
- } else if (rate_hz > dvfs_clk->max_rate) {\r
- rate_hz = dvfs_clk->max_rate;\r
- }\r
- //}\r
-\r
- /* need round rate */\r
- rate_old = clk_get_rate(clk);\r
- rate_new = clk_round_rate_nolock(clk, rate_hz);\r
- if(rate_new == rate_old)\r
- return 0;\r
-\r
- DVFS_DBG("dvfs(%s) round rate (%lu)(rount %lu) old (%lu)\n",\r
- dvfs_clk->name, rate_hz, rate_new, rate_old);\r
-\r
- /* find the clk corresponding voltage */\r
- if (0 != dvfs_clk_get_ref_volt(dvfs_clk, rate_new / 1000, &clk_fv)) {\r
- DVFS_ERR("dvfs(%s) rate %luhz is larger,not support\n", dvfs_clk->name, rate_hz);\r
- return -1;\r
- }\r
- clk_volt_store = dvfs_clk->set_volt;\r
- dvfs_clk->set_volt = clk_fv.index;\r
- volt_new = dvfs_vd_get_newvolt_byclk(dvfs_clk);\r
-\r
- /* if up the rate */\r
- if (rate_new > rate_old) {\r
- if (!list_empty(&dvfs_clk->depend_list)) {\r
- // update depend's req_volt\r
- ret = dvfs_get_depend_volt(dvfs_clk, &vd_core, rate_new);\r
- if (ret <= 0)\r
- goto fail_roll_back;\r
- }\r
- volt_dep_new = dvfs_vd_get_newvolt_bypd(&vd_core);\r
- if (volt_dep_new <= 0)\r
- goto fail_roll_back;\r
-\r
- cur_arm_high_logic = g_arm_high_logic;\r
- cur_logic_high_arm = g_logic_high_arm;\r
-\r
-#ifdef CONFIG_ARCH_RK3066B\r
- get_arm_logic_limit(rate_new / 1000, &g_arm_high_logic, &g_logic_high_arm);\r
-#endif\r
-\r
- ret = dvfs_scale_volt_bystep(dvfs_clk->vd, &vd_core, volt_new, volt_dep_new,\r
- cur_arm_high_logic, cur_logic_high_arm, g_arm_high_logic, g_logic_high_arm);\r
- if (ret < 0)\r
- goto fail_roll_back;\r
-\r
- }\r
-\r
- /* scale rate */\r
- if (dvfs_clk->clk_dvfs_target) {\r
- ret = dvfs_clk->clk_dvfs_target(clk, rate_new, clk_set_rate_locked);\r
- } else {\r
- ret = clk_set_rate_locked(clk, rate_new);\r
- }\r
-\r
- if (ret < 0) {\r
- DVFS_ERR("%s set rate err\n", __func__);\r
- goto fail_roll_back;\r
- }\r
- dvfs_clk->set_freq = rate_new / 1000;\r
-\r
- DVFS_DBG("dvfs %s set rate %lu ok\n", dvfs_clk->name, clk_get_rate(clk));\r
-\r
- /* if down the rate */\r
- if (rate_new < rate_old) {\r
- if (!list_empty(&dvfs_clk->depend_list)) {\r
- // update depend's req_volt\r
- ret = dvfs_get_depend_volt(dvfs_clk, &vd_core, rate_new);\r
- if (ret <= 0)\r
- goto out;\r
- }\r
-\r
- volt_dep_new = dvfs_vd_get_newvolt_bypd(&vd_core);\r
- if (volt_dep_new <= 0)\r
- goto out;\r
-\r
-#ifdef CONFIG_ARCH_RK3066B\r
- get_arm_logic_limit(rate_new / 1000, &g_arm_high_logic, &g_logic_high_arm);\r
-#endif\r
- cur_arm_high_logic = g_arm_high_logic;\r
- cur_logic_high_arm = g_logic_high_arm;\r
-\r
- ret = dvfs_scale_volt_bystep(dvfs_clk->vd, &vd_core, volt_new, volt_dep_new,\r
- cur_arm_high_logic, cur_logic_high_arm, g_arm_high_logic, g_logic_high_arm);\r
- if (ret < 0)\r
- goto out;\r
-\r
- }\r
-\r
- return ret;\r
-fail_roll_back:\r
- dvfs_clk->set_volt = clk_volt_store;\r
- ret = dvfs_get_depend_volt(dvfs_clk, &vd_core, rate_old);\r
- if (ret <= 0) {\r
- DVFS_ERR("%s dvfs_get_depend_volt error when roll back!\n", __func__);\r
- }\r
-out:\r
- return -1;\r
-}\r
-\r
-int dvfs_target_core(struct clk *clk, unsigned long rate_hz)\r
-{\r
- struct clk_node *dvfs_clk;\r
- int volt_new = 0, volt_dep_new = 0, clk_volt_store = 0;\r
- struct cpufreq_frequency_table clk_fv;\r
- int ret = 0;\r
- unsigned long rate_new, rate_old;\r
-\r
- if (!clk) {\r
- DVFS_ERR("%s is not a clk\n", __func__);\r
- return -1;\r
- }\r
- dvfs_clk = clk_get_dvfs_info(clk);\r
- DVFS_DBG("enter %s: clk(%s) rate = %lu Hz\n", __func__, dvfs_clk->name, rate_hz);\r
-\r
- if (!dvfs_clk || dvfs_clk->vd == NULL || IS_ERR_OR_NULL(dvfs_clk->vd->regulator)) {\r
- DVFS_ERR("dvfs(%s) is not register regulator\n", dvfs_clk->name);\r
- return -1;\r
- }\r
-\r
- if (dvfs_clk->vd->volt_set_flag == DVFS_SET_VOLT_FAILURE) {\r
- /* It means the last time set voltage error */\r
- ret = dvfs_reset_volt(dvfs_clk->vd);\r
- if (ret < 0) {\r
- return -1;\r
- }\r
- }\r
-\r
- /* Check limit rate */\r
- //if (dvfs_clk->freq_limit_en) {\r
- if (rate_hz < dvfs_clk->min_rate) {\r
- rate_hz = dvfs_clk->min_rate;\r
- } else if (rate_hz > dvfs_clk->max_rate) {\r
- rate_hz = dvfs_clk->max_rate;\r
- }\r
- //}\r
-\r
- /* need round rate */\r
- rate_old = clk_get_rate(clk);\r
- rate_new = clk_round_rate_nolock(clk, rate_hz);\r
- if(rate_new == rate_old)\r
- return 0;\r
- DVFS_DBG("dvfs(%s) round rate (%lu)(rount %lu) old (%lu)\n",\r
- dvfs_clk->name, rate_hz, rate_new, rate_old);\r
-\r
- /* find the clk corresponding voltage */\r
- if (0 != dvfs_clk_get_ref_volt(dvfs_clk, rate_new / 1000, &clk_fv)) {\r
- DVFS_ERR("dvfs(%s) rate %luhz is larger,not support\n", dvfs_clk->name, rate_hz);\r
- return -1;\r
- }\r
- clk_volt_store = dvfs_clk->set_volt;\r
- dvfs_clk->set_volt = clk_fv.index;\r
- volt_new = dvfs_vd_get_newvolt_byclk(dvfs_clk);\r
-\r
- /* if up the rate */\r
- if (rate_new > rate_old) {\r
- DVFS_DBG("-----------------------------rate_new > rate_old\n");\r
- volt_dep_new = dvfs_vd_get_newvolt_byclk(dvfs_clk_cpu);\r
-\r
- if (volt_dep_new < 0)\r
- goto fail_roll_back;\r
- ret = dvfs_scale_volt_bystep(dvfs_clk->vd, dvfs_clk_cpu->vd, volt_new, volt_dep_new,\r
- g_logic_high_arm, g_arm_high_logic, g_logic_high_arm, g_arm_high_logic);\r
- if (ret < 0)\r
- goto fail_roll_back;\r
- }\r
-\r
- /* scale rate */\r
- if (dvfs_clk->clk_dvfs_target) {\r
- ret = dvfs_clk->clk_dvfs_target(clk, rate_new, clk_set_rate_locked);\r
- } else {\r
- ret = clk_set_rate_locked(clk, rate_new);\r
- }\r
-\r
- if (ret < 0) {\r
- DVFS_ERR("%s set rate err\n", __func__);\r
- goto fail_roll_back;\r
- }\r
- dvfs_clk->set_freq = rate_new / 1000;\r
-\r
- DVFS_DBG("dvfs %s set rate %lu ok\n", dvfs_clk->name, clk_get_rate(clk));\r
-\r
- /* if down the rate */\r
- if (rate_new < rate_old) {\r
- DVFS_DBG("-----------------------------rate_new < rate_old\n");\r
- volt_dep_new = dvfs_vd_get_newvolt_byclk(dvfs_clk_cpu);\r
-\r
- if (volt_dep_new < 0)\r
- goto out;\r
- ret = dvfs_scale_volt_bystep(dvfs_clk->vd, dvfs_clk_cpu->vd, volt_new, volt_dep_new,\r
- g_logic_high_arm, g_arm_high_logic, g_logic_high_arm, g_arm_high_logic);\r
- if (ret < 0)\r
- goto out;\r
- }\r
-\r
- return ret;\r
-fail_roll_back:\r
- dvfs_clk->set_volt = clk_volt_store;\r
- ret = dvfs_get_depend_volt(dvfs_clk, &vd_core, rate_old);\r
- if (ret <= 0) {\r
- DVFS_ERR("%s dvfs_get_depend_volt error when roll back!\n", __func__);\r
- }\r
-\r
-out:\r
- return -1;\r
-}\r
-\r
-/*****************************init**************************/\r
-/**\r
- * rate must be raising sequence\r
- */\r
-static struct cpufreq_frequency_table cpu_dvfs_table[] = {\r
- // {.frequency = 48 * DVFS_KHZ, .index = 920*DVFS_MV},\r
- // {.frequency = 126 * DVFS_KHZ, .index = 970 * DVFS_MV},\r
- // {.frequency = 252 * DVFS_KHZ, .index = 1040 * DVFS_MV},\r
- // {.frequency = 504 * DVFS_KHZ, .index = 1050 * DVFS_MV},\r
- {.frequency = 816 * DVFS_KHZ, .index = 1050 * DVFS_MV},\r
- // {.frequency = 1008 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
- {.frequency = CPUFREQ_TABLE_END},\r
-};\r
-\r
-static struct cpufreq_frequency_table ddr_dvfs_table[] = {\r
- // {.frequency = 100 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
- {.frequency = 200 * DVFS_KHZ, .index = 1000 * DVFS_MV},\r
- {.frequency = 300 * DVFS_KHZ, .index = 1050 * DVFS_MV},\r
- {.frequency = 400 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
- {.frequency = 500 * DVFS_KHZ, .index = 1150 * DVFS_MV},\r
- {.frequency = 600 * DVFS_KHZ, .index = 1200 * DVFS_MV},\r
- {.frequency = CPUFREQ_TABLE_END},\r
-};\r
-\r
-static struct cpufreq_frequency_table gpu_dvfs_table[] = {\r
- {.frequency = 90 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
- {.frequency = 180 * DVFS_KHZ, .index = 1150 * DVFS_MV},\r
- {.frequency = 300 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
- {.frequency = 400 * DVFS_KHZ, .index = 1150 * DVFS_MV},\r
- {.frequency = 500 * DVFS_KHZ, .index = 1200 * DVFS_MV},\r
- {.frequency = CPUFREQ_TABLE_END},\r
-};\r
-\r
-static struct cpufreq_frequency_table peri_aclk_dvfs_table[] = {\r
- {.frequency = 100 * DVFS_KHZ, .index = 1000 * DVFS_MV},\r
- {.frequency = 200 * DVFS_KHZ, .index = 1050 * DVFS_MV},\r
- {.frequency = 300 * DVFS_KHZ, .index = 1070 * DVFS_MV},\r
- {.frequency = 500 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
- {.frequency = CPUFREQ_TABLE_END},\r
-};\r
-\r
-static struct cpufreq_frequency_table dep_cpu2core_table[] = {\r
- // {.frequency = 252 * DVFS_KHZ, .index = 1025 * DVFS_MV},\r
- // {.frequency = 504 * DVFS_KHZ, .index = 1025 * DVFS_MV},\r
- {.frequency = 816 * DVFS_KHZ, .index = 1050 * DVFS_MV},//logic 1.050V\r
- // {.frequency = 1008 * DVFS_KHZ,.index = 1050 * DVFS_MV},\r
- // {.frequency = 1200 * DVFS_KHZ,.index = 1050 * DVFS_MV},\r
- // {.frequency = 1272 * DVFS_KHZ,.index = 1050 * DVFS_MV},//logic 1.050V\r
- // {.frequency = 1416 * DVFS_KHZ,.index = 1100 * DVFS_MV},//logic 1.100V\r
- // {.frequency = 1512 * DVFS_KHZ,.index = 1125 * DVFS_MV},//logic 1.125V\r
- // {.frequency = 1608 * DVFS_KHZ,.index = 1175 * DVFS_MV},//logic 1.175V\r
- {.frequency = CPUFREQ_TABLE_END},\r
-};\r
-\r
-static struct vd_node vd_cpu = {\r
- .name = "vd_cpu",\r
- .regulator_name = "vdd_cpu",\r
- .volt_set_flag = DVFS_SET_VOLT_FAILURE,\r
- .vd_dvfs_target = dvfs_target_cpu,\r
-};\r
-\r
-static struct vd_node vd_core = {\r
- .name = "vd_core",\r
- .regulator_name = "vdd_core",\r
- .volt_set_flag = DVFS_SET_VOLT_FAILURE,\r
- .vd_dvfs_target = dvfs_target_core,\r
-};\r
-\r
-static struct vd_node vd_rtc = {\r
- .name = "vd_rtc",\r
- .regulator_name = "vdd_rtc",\r
- .volt_set_flag = DVFS_SET_VOLT_FAILURE,\r
- .vd_dvfs_target = NULL,\r
-};\r
-\r
-static struct vd_node *rk30_vds[] = {&vd_cpu, &vd_core, &vd_rtc};\r
-\r
-static struct pd_node pd_a9_0 = {\r
- .name = "pd_a9_0",\r
- .vd = &vd_cpu,\r
-};\r
-static struct pd_node pd_a9_1 = {\r
- .name = "pd_a9_1",\r
- .vd = &vd_cpu,\r
-};\r
-static struct pd_node pd_debug = {\r
- .name = "pd_debug",\r
- .vd = &vd_cpu,\r
-};\r
-static struct pd_node pd_scu = {\r
- .name = "pd_scu",\r
- .vd = &vd_cpu,\r
-};\r
-static struct pd_node pd_video = {\r
- .name = "pd_video",\r
- .vd = &vd_core,\r
-};\r
-static struct pd_node pd_vio = {\r
- .name = "pd_vio",\r
- .vd = &vd_core,\r
-};\r
-static struct pd_node pd_gpu = {\r
- .name = "pd_gpu",\r
- .vd = &vd_core,\r
-};\r
-static struct pd_node pd_peri = {\r
- .name = "pd_peri",\r
- .vd = &vd_core,\r
-};\r
-static struct pd_node pd_cpu = {\r
- .name = "pd_cpu",\r
- .vd = &vd_core,\r
-};\r
-static struct pd_node pd_alive = {\r
- .name = "pd_alive",\r
- .vd = &vd_core,\r
-};\r
-static struct pd_node pd_rtc = {\r
- .name = "pd_rtc",\r
- .vd = &vd_rtc,\r
-};\r
-#define LOOKUP_PD(_ppd) \\r
-{ \\r
- .pd = _ppd, \\r
-}\r
-static struct pd_node_lookup rk30_pds[] = {\r
- LOOKUP_PD(&pd_a9_0),\r
- LOOKUP_PD(&pd_a9_1),\r
- LOOKUP_PD(&pd_debug),\r
- LOOKUP_PD(&pd_scu),\r
- LOOKUP_PD(&pd_video),\r
- LOOKUP_PD(&pd_vio),\r
- LOOKUP_PD(&pd_gpu),\r
- LOOKUP_PD(&pd_peri),\r
- LOOKUP_PD(&pd_cpu),\r
- LOOKUP_PD(&pd_alive),\r
- LOOKUP_PD(&pd_rtc),\r
-};\r
-\r
-#define CLK_PDS(_ppd) \\r
-{ \\r
- .pd = _ppd, \\r
-}\r
-\r
-static struct pds_list cpu_pds[] = {\r
- CLK_PDS(&pd_a9_0),\r
- CLK_PDS(&pd_a9_1),\r
- CLK_PDS(NULL),\r
-};\r
-\r
-static struct pds_list ddr_pds[] = {\r
- CLK_PDS(&pd_cpu),\r
- CLK_PDS(NULL),\r
-};\r
-\r
-static struct pds_list gpu_pds[] = {\r
- CLK_PDS(&pd_gpu),\r
- CLK_PDS(NULL),\r
-};\r
-\r
-static struct pds_list aclk_periph_pds[] = {\r
- CLK_PDS(&pd_peri),\r
- CLK_PDS(NULL),\r
-};\r
-\r
-#define RK_CLKS(_clk_name, _ppds, _dvfs_table, _dvfs_nb) \\r
-{ \\r
- .name = _clk_name, \\r
- .pds = _ppds,\\r
- .dvfs_table = _dvfs_table, \\r
- .dvfs_nb = _dvfs_nb, \\r
-}\r
-\r
-static struct clk_node rk30_clks[] = {\r
- RK_CLKS("cpu", cpu_pds, cpu_dvfs_table, &rk_dvfs_clk_notifier),\r
- RK_CLKS("ddr", ddr_pds, ddr_dvfs_table, &rk_dvfs_clk_notifier),\r
- RK_CLKS("gpu", gpu_pds, gpu_dvfs_table, &rk_dvfs_clk_notifier),\r
- RK_CLKS("aclk_periph", aclk_periph_pds, peri_aclk_dvfs_table, &rk_dvfs_clk_notifier),\r
-};\r
-\r
-#define RK_DEPPENDS(_clk_name, _pvd, _dep_table) \\r
-{ \\r
- .clk_name = _clk_name, \\r
- .dep_vd = _pvd,\\r
- .dep_table = _dep_table, \\r
-}\r
-\r
-static struct depend_lookup rk30_depends[] = {\r
-#ifndef CONFIG_ARCH_RK3066B\r
- RK_DEPPENDS("cpu", &vd_core, dep_cpu2core_table),\r
-#endif\r
- //RK_DEPPENDS("gpu", &vd_cpu, NULL),\r
- //RK_DEPPENDS("gpu", &vd_cpu, NULL),\r
-};\r
-static struct avs_ctr_st rk30_avs_ctr;\r
-\r
-int rk_dvfs_init(void)\r
-{\r
- int i = 0;\r
- for (i = 0; i < ARRAY_SIZE(rk30_vds); i++) {\r
- rk_regist_vd(rk30_vds[i]);\r
- }\r
- for (i = 0; i < ARRAY_SIZE(rk30_pds); i++) {\r
- rk_regist_pd(&rk30_pds[i]);\r
- }\r
- for (i = 0; i < ARRAY_SIZE(rk30_clks); i++) {\r
- rk_regist_clk(&rk30_clks[i]);\r
- }\r
- for (i = 0; i < ARRAY_SIZE(rk30_depends); i++) {\r
- rk_regist_depends(&rk30_depends[i]);\r
- }\r
- dvfs_clk_cpu = dvfs_get_dvfs_clk_byname("cpu");\r
- avs_board_init(&rk30_avs_ctr);\r
- printk("rk30_dvfs_init\n");\r
- return 0;\r
-}\r
-\r
-\r
-\r
-/******************************rk30 avs**************************************************/\r
-\r
-\r
-static void __iomem *rk30_nandc_base=NULL;\r
-\r
-#define nandc_readl(offset) readl_relaxed(rk30_nandc_base + offset)\r
-#define nandc_writel(v, offset) do { writel_relaxed(v, rk30_nandc_base + offset); dsb(); } while (0)\r
-static u8 rk30_get_avs_val(void)\r
-{\r
- u32 nanc_save_reg[4];\r
- unsigned long flags;\r
- u32 paramet = 0;\r
- u32 count = 100;\r
- if(rk30_nandc_base==NULL) \r
- return 0;\r
- \r
- preempt_disable();\r
- local_irq_save(flags);\r
-\r
- nanc_save_reg[0] = nandc_readl(0);\r
- nanc_save_reg[1] = nandc_readl(0x130);\r
- nanc_save_reg[2] = nandc_readl(0x134);\r
- nanc_save_reg[3] = nandc_readl(0x158);\r
-\r
- nandc_writel(nanc_save_reg[0] | 0x1 << 14, 0);\r
- nandc_writel(0x5, 0x130);\r
-\r
- /* Just break lock status */\r
- nandc_writel(0x1, 0x158);\r
-#ifdef CONFIG_ARCH_RK3066B\r
- nandc_writel(3, 0x158);\r
-#else\r
- nandc_writel(7, 0x158);\r
-#endif\r
- nandc_writel(1, 0x134);\r
-\r
- while(count--) {\r
- paramet = nandc_readl(0x138);\r
- if((paramet & 0x1))\r
- break;\r
- udelay(1);\r
- };\r
- paramet = (paramet >> 1) & 0xff;\r
- nandc_writel(nanc_save_reg[0], 0);\r
- nandc_writel(nanc_save_reg[1], 0x130);\r
- nandc_writel(nanc_save_reg[2], 0x134);\r
- nandc_writel(nanc_save_reg[3], 0x158);\r
-\r
- local_irq_restore(flags);\r
- preempt_enable();\r
- return (u8)paramet;\r
-\r
-}\r
-\r
-void rk30_avs_init(void)\r
-{\r
- rk30_nandc_base = ioremap(RK30_NANDC_PHYS, RK30_NANDC_SIZE);\r
-}\r
-static struct avs_ctr_st rk30_avs_ctr= {\r
- .avs_init =rk30_avs_init,\r
- .avs_get_val = rk30_get_avs_val,\r
-};\r
-\r
-\r
+++ /dev/null
-#include <linux/linkage.h>
-#include <linux/init.h>
-#include <asm/memory.h>
-
- .section ".text.head", "ax"
- __CPUINIT
-
-/*
- * The secondary kernel init calls v7_flush_dcache_all before it enables
- * the L1; however, the L1 comes out of reset in an undefined state, so
- * the clean + invalidate performed by v7_flush_dcache_all causes a bunch
- * of cache lines with uninitialized data and uninitialized tags to get
- * written out to memory, which does really unpleasant things to the main
- * processor. We fix this by performing an invalidate, rather than a
- * clean + invalidate, before jumping into the kernel.
- */
-ENTRY(v7_invalidate_l1)
- mov r0, #0
- mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
- mcr p15, 2, r0, c0, c0, 0
- mrc p15, 1, r0, c0, c0, 0
-
- ldr r1, =0x7fff
- and r2, r1, r0, lsr #13
-
- ldr r1, =0x3ff
-
- and r3, r1, r0, lsr #3 @ NumWays - 1
- add r2, r2, #1 @ NumSets
-
- and r0, r0, #0x7
- add r0, r0, #4 @ SetShift
-
- clz r1, r3 @ WayShift
- add r4, r3, #1 @ NumWays
-1: sub r2, r2, #1 @ NumSets--
- mov r3, r4 @ Temp = NumWays
-2: subs r3, r3, #1 @ Temp--
- mov r5, r3, lsl r1
- mov r6, r2, lsl r0
- orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
- mcr p15, 0, r5, c7, c6, 2
- bgt 2b
- cmp r2, #0
- bgt 1b
- dsb
- isb
- mov pc, lr
-ENDPROC(v7_invalidate_l1)
-
-ENTRY(rk30_secondary_startup)
- bl v7_invalidate_l1
- b secondary_startup
-ENDPROC(rk30_secondary_startup)
-
-ENTRY(rk30_sram_secondary_startup)
- ldr pc, 1f
-1: .long rk30_secondary_startup - PAGE_OFFSET + PLAT_PHYS_OFFSET
-ENDPROC(rk30_sram_secondary_startup)
+++ /dev/null
-/*
- * RK30 SMP cpu-hotplug support
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- * Copyright (C) 2002 ARM Ltd.
- * All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/smp.h>
-#include <linux/delay.h>
-
-#include <asm/cacheflush.h>
-#include <asm/smp_plat.h>
-#include <asm/system.h>
-
-#include <mach/pmu.h>
-
-static cpumask_t dead_cpus;
-
-int platform_cpu_kill(unsigned int cpu)
-{
- int k;
-
- /* this function is running on another CPU than the offline target,
- * here we need wait for shutdown code in platform_cpu_die() to
- * finish before asking SoC-specific code to power off the CPU core.
- */
- for (k = 0; k < 1000; k++) {
- if (cpumask_test_cpu(cpu, &dead_cpus)) {
- mdelay(1);
- pmu_set_power_domain(PD_A9_0 + cpu, false);
- return 1;
- }
-
- mdelay(1);
- }
-
- return 0;
-}
-
-/*
- * platform-specific code to shutdown a CPU
- *
- * Called with IRQs disabled
- */
-void platform_cpu_die(unsigned int cpu)
-{
- unsigned int v;
-
- /* hardware shutdown code running on the CPU that is being offlined */
- flush_cache_all();
- dsb();
-
- /* notify platform_cpu_kill() that hardware shutdown is finished */
- cpumask_set_cpu(cpu, &dead_cpus);
- clean_dcache_area(&dead_cpus, sizeof(dead_cpus));
-
- asm volatile(
- " mcr p15, 0, %1, c7, c5, 0\n"
- " mcr p15, 0, %1, c7, c10, 4\n"
- /*
- * Turn off coherency
- */
- " mrc p15, 0, %0, c1, c0, 1\n"
- " bic %0, %0, %3\n" // clear ACTLR.SMP | ACTLR.FW
- " mcr p15, 0, %0, c1, c0, 1\n"
- " mrc p15, 0, %0, c1, c0, 0\n"
- " bic %0, %0, %2\n"
- " mcr p15, 0, %0, c1, c0, 0\n"
- : "=&r" (v)
- : "r" (0), "Ir" (CR_C), "Ir" ((1 << 6) | (1 << 0))
- : "cc");
-
- /* wait for SoC code in platform_cpu_kill() to shut off CPU core
- * power. CPU bring up starts from the reset vector.
- */
- while (1) {
- dsb();
- wfi();
- }
-}
-
-int platform_cpu_disable(unsigned int cpu)
-{
- cpumask_clear_cpu(cpu, &dead_cpus);
- /*
- * we don't allow CPU 0 to be shutdown (it is still too special
- * e.g. clock tick interrupts)
- */
- return cpu == 0 ? -EPERM : 0;
-}
+++ /dev/null
-#include <linux/io.h>
-#include <mach/board.h>
-#include <mach/sram.h>
-#include <mach/iomux.h>
-#include <mach/cru.h>
-#include <asm/io.h>
-#include <mach/gpio.h>
-
-#define cru_readl(offset) readl_relaxed(RK30_CRU_BASE + offset)
-#define cru_writel(v, offset) do { writel_relaxed(v, RK30_CRU_BASE + offset); dsb(); } while (0)
-
-#if defined(CONFIG_RK30_I2C_INSRAM)
-
-/******************need set when you use i2c*************************/
-#define I2C_SPEED 100
-#define I2C_SADDR (0x2D) /* slave address ,wm8310 addr is 0x34*/
-#define SRAM_I2C_CH 1 //CH==0, i2c0,CH==1, i2c1,CH==2, i2c2,CH==3, i2c3
-#define SRAM_I2C_ADDRBASE (RK30_I2C1_BASE + SZ_4K )//RK29_I2C0_BASE\RK29_I2C2_BASE\RK29_I2C3_BASE
-#define I2C_SLAVE_ADDR_LEN 1 // 2:slav addr is 10bit ,1:slav addr is 7bit
-#define I2C_SLAVE_REG_LEN 1 // 2:slav reg addr is 16 bit ,1:is 8 bit
-#define SRAM_I2C_DATA_BYTE 1 //i2c transmission data is 1bit(8wei) or 2bit(16wei)
-#define GRF_GPIO_IOMUX 0xd4 //GRF_GPIO2D_IOMUX
-/*ch=0:GRF_GPIO2L_IOMUX,ch=1:GRF_GPIO1L_IOMUX,ch=2:GRF_GPIO5H_IOMUX,ch=3:GRF_GPIO2L_IOMUX*/
-#define I2C_GRF_GPIO_IOMUX (0x01<<14)|(0x01<<12)
-/*CH=0:(~(0x03<<30))&(~(0x03<<28))|(0x01<<30)|(0x01<<28),CH=1:(~(0x03<<14))&(~(0x03<<12))|(0x01<<14)|(0x01<<12),
-CH=2:(~(0x03<<24))&(~(0x03<<22))|(0x01<<24)|(0x01<<22),CH=3:(~(0x03<<26))&(~(0x03<<24))|(0x02<<26)|(0x02<<24)*/
-/***************************************/
-
-#define I2C_SLAVE_TYPE (((I2C_SLAVE_ADDR_LEN-1)<<4)|((I2C_SLAVE_REG_LEN-1)))
-
-#define uint8 unsigned char
-#define uint16 unsigned short
-#define uint32 unsigned int
-uint32 __sramdata data[5];
-uint8 __sramdata arm_voltage = 0;
-
-#define CRU_CLKGATE0_CON 0xd0
-#define CRU_CLKGATE8_CON 0xf0
-#define CRU_CLKSEL1_CON 0x48
-#define GRF_GPIO5H_IOMUX 0x74
-#define GRF_GPIO2L_IOMUX 0x58
-#define GRF_GPIO1L_IOMUX 0x50
-
-#define COMPLETE_READ (1<<STATE_START|1<<STATE_READ|1<<STATE_STOP)
-#define COMPLETE_WRITE (1<<STATE_START|1<<STATE_WRITE|1<<STATE_STOP)
-
-/* Control register */
-#define I2C_CON 0x0000
-#define I2C_CON_EN (1 << 0)
-#define I2C_CON_MOD(mod) ((mod) << 1)
-#define I2C_CON_MASK (3 << 1)
-enum{
- I2C_CON_MOD_TX = 0,
- I2C_CON_MOD_TRX,
- I2C_CON_MOD_RX,
- I2C_CON_MOD_RRX,
-};
-#define I2C_CON_START (1 << 3)
-#define I2C_CON_STOP (1 << 4)
-#define I2C_CON_LASTACK (1 << 5)
-#define I2C_CON_ACTACK (1 << 6)
-
-/* Clock dividor register */
-#define I2C_CLKDIV 0x0004
-#define I2C_CLKDIV_VAL(divl, divh) (((divl) & 0xffff) | (((divh) << 16) & 0xffff0000))
-#define rk30_ceil(x, y) \
- ({ unsigned long __x = (x), __y = (y); (__x + __y - 1) / __y; })
-
-/* the slave address accessed for master rx mode */
-#define I2C_MRXADDR 0x0008
-#define I2C_MRXADDR_LOW (1 << 24)
-#define I2C_MRXADDR_MID (1 << 25)
-#define I2C_MRXADDR_HIGH (1 << 26)
-
-/* the slave register address accessed for master rx mode */
-#define I2C_MRXRADDR 0x000c
-#define I2C_MRXRADDR_LOW (1 << 24)
-#define I2C_MRXRADDR_MID (1 << 25)
-#define I2C_MRXRADDR_HIGH (1 << 26)
-
-/* master tx count */
-#define I2C_MTXCNT 0x0010
-
-/* master rx count */
-#define I2C_MRXCNT 0x0014
-
-/* interrupt enable register */
-#define I2C_IEN 0x0018
-#define I2C_BTFIEN (1 << 0)
-#define I2C_BRFIEN (1 << 1)
-#define I2C_MBTFIEN (1 << 2)
-#define I2C_MBRFIEN (1 << 3)
-#define I2C_STARTIEN (1 << 4)
-#define I2C_STOPIEN (1 << 5)
-#define I2C_NAKRCVIEN (1 << 6)
-#define IRQ_MST_ENABLE (I2C_MBTFIEN | I2C_MBRFIEN | I2C_NAKRCVIEN | I2C_STARTIEN | I2C_STOPIEN)
-#define IRQ_ALL_DISABLE 0
-
-/* interrupt pending register */
-#define I2C_IPD 0x001c
-#define I2C_BTFIPD (1 << 0)
-#define I2C_BRFIPD (1 << 1)
-#define I2C_MBTFIPD (1 << 2)
-#define I2C_MBRFIPD (1 << 3)
-#define I2C_STARTIPD (1 << 4)
-#define I2C_STOPIPD (1 << 5)
-#define I2C_NAKRCVIPD (1 << 6)
-#define I2C_IPD_ALL_CLEAN 0x7f
-
-/* finished count */
-#define I2C_FCNT 0x0020
-
-/* I2C tx data register */
-#define I2C_TXDATA_BASE 0X0100
-
-/* I2C rx data register */
-#define I2C_RXDATA_BASE 0x0200
-
-void __sramfunc sram_i2c_enable(void);
-void __sramfunc sram_i2c_disenable(void);
-
-void __sramfunc sram_printch(char byte);
-void __sramfunc sram_printhex(unsigned int hex);
-
-#define sram_udelay(usecs) SRAM_LOOP((usecs)*SRAM_LOOPS_PER_USEC)
-
-/*-------------------------------------------------------------------------------------------------------
-Name : sram_i2c_init
-Desc : initialize the necessary registers
-Params : channel-determine which I2C bus we used
-Return : none
-------------------------------------------------------------------------------------------------------*/
-
-void __sramfunc sram_i2c_init(void)
-{
- unsigned int div, divl, divh;
- //enable cru_clkgate8 clock
- data[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_CLKID(8)));
-
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_PCLK_I2C1)|CLK_UN_GATE(CLK_GATE_PCLK_I2C1),
- CLK_GATE_CLKID_CONS(CLK_GATE_PCLK_I2C1));
-
- data[2] = readl_relaxed(RK30_GRF_BASE + GRF_GPIO_IOMUX);
- writel_relaxed(data[2]| I2C_GRF_GPIO_IOMUX, RK30_GRF_BASE + GRF_GPIO_IOMUX);
-
- div = 0x1e;
- divh = divl = 0xf;
- writel_relaxed(I2C_CLKDIV_VAL(divl, divh), SRAM_I2C_ADDRBASE + I2C_CLKDIV);
- data[3] = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_CLKDIV);
-
-}
-
-
-/*-------------------------------------------------------------------------------------------------------
-Name : sram_i2c_deinit
-Desc : de-initialize the necessary registers
-Params : noe
-Return : none
-------------------------------------------------------------------------------------------------------*/
-void __sramfunc sram_i2c_deinit(void)
-{
- //restore iomux reg
- writel_relaxed(data[2], RK30_GRF_BASE + GRF_GPIO_IOMUX);
-
- //restore scu clock reg
- cru_writel(data[1], CLK_GATE_CLKID_CONS(CLK_GATE_PCLK_I2C1));
-
-
-}
-
-/*-------------------------------------------------------------------------------------------------------
-Name : sram_i2c_start
-Desc : start i2c
-Params : none
-Return : none
-------------------------------------------------------------------------------------------------------*/
-void __sramfunc sram_i2c_read_enable(void)
-{
- writel_relaxed(I2C_STARTIEN, SRAM_I2C_ADDRBASE + I2C_IEN);
- writel_relaxed(((((I2C_CON_EN | I2C_CON_MOD(1)) | I2C_CON_LASTACK) )| I2C_CON_START) & (~(I2C_CON_STOP)) , SRAM_I2C_ADDRBASE + I2C_CON);
-}
-void __sramfunc sram_i2c_write_enable(void)
-{
- writel_relaxed(I2C_STARTIEN, SRAM_I2C_ADDRBASE + I2C_IEN);
- writel_relaxed(((((I2C_CON_EN | I2C_CON_MOD(0)) | I2C_CON_LASTACK) )| I2C_CON_START) & (~(I2C_CON_STOP)) , SRAM_I2C_ADDRBASE + I2C_CON);
-}
-
-void __sramfunc sram_i2c_disenable(void)
-{
- writel_relaxed(0, SRAM_I2C_ADDRBASE + I2C_CON);
-}
-
-void __sramfunc sram_i2c_clean_start(void)
-{
- unsigned int con = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_CON);
-
- con = (con & (~I2C_CON_START)) ;
- writel_relaxed(con, SRAM_I2C_ADDRBASE + I2C_CON);
-}
-void __sramfunc sram_i2c_send_start(void)
-{
- unsigned int con = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_CON);
- con |= I2C_CON_START;
- if(con & I2C_CON_STOP)
- sram_printch('E');
- writel_relaxed(con, SRAM_I2C_ADDRBASE + I2C_CON);
-}
-void __sramfunc sram_i2c_send_stop(void)
-{
- unsigned int con = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_CON);
- con &= ~I2C_CON_START;
- con |= I2C_CON_STOP;
- if(con & I2C_CON_START)
- sram_printch('E');
- writel_relaxed(I2C_STOPIEN, SRAM_I2C_ADDRBASE + I2C_IEN);
- writel_relaxed(con, SRAM_I2C_ADDRBASE + I2C_CON);
-}
-void __sramfunc sram_i2c_clean_stop(void)
-{
- unsigned int con = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_CON);
-
- con = (con & (~I2C_CON_STOP)) ;
- writel_relaxed(con, SRAM_I2C_ADDRBASE + I2C_CON);
-}
-
-void __sramfunc sram_i2c_get_ipd_event(int type)
-{
- int time = 2000;
- unsigned int con = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_IPD);
-
- while((--time) && (!(con & type))){
- sram_udelay(10);
- con = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_IPD);
- }
- writel_relaxed(type,SRAM_I2C_ADDRBASE + I2C_IPD);
-
- if(time <= 0){
- if (type == I2C_STARTIPD){
- sram_printch('S');
- }else if (type == I2C_STOPIPD){
- sram_printch('P');
- }else if (type == I2C_MBTFIPD){
- sram_printch('W');
- }else if (type == I2C_MBRFIPD){
- sram_printch('R');
- }
- sram_printch('T');
- }
-}
-
-void __sramfunc sram_i2c_write_prepare(uint8 I2CSlaveAddr, uint8 regAddr,uint8 pdata)
-{
- u32 data = 0;
- unsigned int addr = (I2CSlaveAddr & 0x7f) << 1;
-
- writel_relaxed(I2C_MBTFIEN, SRAM_I2C_ADDRBASE + I2C_IEN);
- data = (addr | (regAddr << 8))|(pdata << 16);
- writel_relaxed(data , SRAM_I2C_ADDRBASE + I2C_TXDATA_BASE);
- writel_relaxed(3, SRAM_I2C_ADDRBASE + I2C_MTXCNT);
-}
-uint8 __sramfunc sram_i2c_read_prepare(uint8 I2CSlaveAddr, uint8 regAddr)
-{
- unsigned int addr = (I2CSlaveAddr & 0x7f) << 1;
-
- writel_relaxed(I2C_MBRFIEN, SRAM_I2C_ADDRBASE + I2C_IEN);
- writel_relaxed(addr | I2C_MRXADDR_LOW, SRAM_I2C_ADDRBASE + I2C_MRXADDR);
- writel_relaxed(regAddr | I2C_MRXADDR_LOW, SRAM_I2C_ADDRBASE + I2C_MRXRADDR);
- writel_relaxed(SRAM_I2C_DATA_BYTE, SRAM_I2C_ADDRBASE + I2C_MRXCNT);
- return 0;
-}
-
-uint8 __sramfunc sram_i2c_read_get_data(uint8 I2CSlaveAddr, uint8 regAddr)
-{
- unsigned int ret;
- ret = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_RXDATA_BASE);
- ret = ret & 0x000000ff;
- return ret;
-
-}
-uint8 __sramfunc sram_i2c_write(uint8 I2CSlaveAddr, uint8 regAddr,uint8 data)
-{
- sram_i2c_write_enable();
- sram_i2c_get_ipd_event(I2C_STARTIPD);
- sram_i2c_clean_start();
-
- sram_i2c_write_prepare(I2CSlaveAddr,regAddr,data);
- sram_i2c_get_ipd_event(I2C_MBTFIPD);
-
- sram_i2c_send_stop();
- sram_i2c_get_ipd_event(I2C_STOPIPD);
- sram_i2c_clean_stop();
- sram_i2c_disenable();
- return 0;
-
-}
-
-uint8 __sramfunc sram_i2c_read(uint8 I2CSlaveAddr, uint8 regAddr)
-{
- unsigned int data;
- sram_i2c_read_enable();
- sram_i2c_get_ipd_event(I2C_STARTIPD);
- sram_i2c_clean_start();
-
- sram_i2c_read_prepare(I2CSlaveAddr,regAddr);
- sram_i2c_get_ipd_event(I2C_MBRFIPD);
-
- data = sram_i2c_read_get_data(I2CSlaveAddr,regAddr);
-
- sram_i2c_send_stop();
- sram_i2c_get_ipd_event(I2C_STOPIPD);
- sram_i2c_clean_stop();
- sram_i2c_disenable();
- return data;
-}
-
-void __sramfunc rk30_suspend_voltage_set(unsigned int vol)
-{
- uint8 slaveaddr;
- uint16 slavereg;
- uint8 data,ret = 0;
- uint8 rtc_status_reg = 0x11;
- slaveaddr = I2C_SADDR; //slave device addr
- slavereg = 0x22; // reg addr
- data = 0x23; //set arm 1.0v
-
- sram_i2c_init(); //init i2c device
- ret = sram_i2c_read(slaveaddr, rtc_status_reg);
- sram_i2c_write(slaveaddr, rtc_status_reg, ret);
- arm_voltage = sram_i2c_read(slaveaddr, slavereg);
-// sram_printhex(ret);
- sram_i2c_write(slaveaddr, slavereg, data);//
- sram_i2c_deinit(); //deinit i2c device
-
-}
-
-void __sramfunc rk30_suspend_voltage_resume(unsigned int vol)
-{
- uint8 slaveaddr;
- uint16 slavereg;
- uint8 data;//,ret = 0;
- slaveaddr = I2C_SADDR; //slave device addr
- slavereg = 0x22; // reg addr
-
- sram_i2c_init(); //init i2c device
- if (arm_voltage >= 0x3b ){ // set arm <= 1.3v
- data = 0x3b;
- }
- else if(arm_voltage <= 0x1f){
- data = 0x1f; // set arm >= 0.95v
- }
- else
- data = arm_voltage;
- sram_i2c_write(slaveaddr, slavereg, data);
- sram_i2c_deinit(); //deinit i2c device
-}
-#else
-void __sramfunc rk30_suspend_voltage_set(unsigned int vol)
-{
-
-}
-void __sramfunc rk30_suspend_voltage_resume(unsigned int vol)
-{
-
-}
-#endif
-
-
-
+++ /dev/null
-#ifndef __MACH_BOARD_H
-#define __MACH_BOARD_H
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-#include <linux/types.h>
-#include <linux/timer.h>
-#include <linux/notifier.h>
-#include <asm/setup.h>
-#include <plat/board.h>
-#include <mach/sram.h>
-#include <linux/i2c-gpio.h>
-
-
-void __init rk30_map_common_io(void);
-void __init rk30_init_irq(void);
-void __init rk30_map_io(void);
-struct machine_desc;
-void __init rk30_fixup(struct machine_desc *desc, struct tag *tags, char **cmdline, struct meminfo *mi);
-void __init rk30_clock_data_init(unsigned long gpll,unsigned long cpll,u32 flags);
-
-#ifdef CONFIG_RK30_PWM_REGULATOR
-void rk30_pwm_suspend_voltage_set(void);
-void rk30_pwm_resume_voltage_set(void);
-void __sramfunc rk30_pwm_logic_suspend_voltage(void);
- void __sramfunc rk30_pwm_logic_resume_voltage(void);
-#endif
-
-extern struct sys_timer rk30_timer;
-
-enum _periph_pll {
- periph_pll_1485mhz = 148500000,
- periph_pll_297mhz = 297000000,
- periph_pll_300mhz = 300000000,
- periph_pll_384mhz = 384000000,
- periph_pll_594mhz = 594000000,
- periph_pll_1188mhz = 1188000000, /* for box*/
-};
-enum _codec_pll {
- codec_pll_360mhz = 360000000, /* for HDMI */
- codec_pll_408mhz = 408000000,
- codec_pll_456mhz = 456000000,
- codec_pll_504mhz = 504000000,
- codec_pll_552mhz = 552000000, /* for HDMI */
- codec_pll_594mhz = 594000000, /* for HDMI */
- codec_pll_600mhz = 600000000,
- codec_pll_742_5khz = 742500000,
- codec_pll_768mhz = 768000000,
- codec_pll_798mhz = 798000000,
- codec_pll_1188mhz = 1188000000,
- codec_pll_1200mhz = 1200000000,
-};
-
-//has extern 27mhz
-#define CLK_FLG_EXT_27MHZ (1<<0)
-//max i2s rate
-#define CLK_FLG_MAX_I2S_12288KHZ (1<<1)
-#define CLK_FLG_MAX_I2S_22579_2KHZ (1<<2)
-#define CLK_FLG_MAX_I2S_24576KHZ (1<<3)
-#define CLK_FLG_MAX_I2S_49152KHZ (1<<4)
-//uart 1m\3m
-#define CLK_FLG_UART_1_3M (1<<5)
-#define CLK_CPU_HPCLK_11 (1<<6)
-#define CLK_GPU_GPLL (1<<7)
-#define CLK_GPU_CPLL (1<<8)
-
-
-#ifdef CONFIG_RK29_VMAC
-
-#define RK30_CLOCKS_DEFAULT_FLAGS (CLK_FLG_MAX_I2S_12288KHZ/*|CLK_FLG_EXT_27MHZ*/)
-#define periph_pll_default periph_pll_300mhz
-#define codec_pll_default codec_pll_1188mhz
-
-#else
-
-
-#define RK30_CLOCKS_DEFAULT_FLAGS (CLK_FLG_MAX_I2S_12288KHZ/*|CLK_FLG_EXT_27MHZ*/)
-
-#if (RK30_CLOCKS_DEFAULT_FLAGS&CLK_FLG_UART_1_3M)
-#define codec_pll_default codec_pll_768mhz
-#define periph_pll_default periph_pll_297mhz
-
-#else
-
-#ifdef CONFIG_ARCH_RK3066B
-#define codec_pll_default codec_pll_594mhz
-#define periph_pll_default periph_pll_384mhz
-
-#else
-#define codec_pll_default codec_pll_1200mhz
-#define periph_pll_default periph_pll_297mhz
-#endif
-
-#endif
-
-#endif
-
-#endif
+++ /dev/null
-#include <plat/clkdev.h>
+++ /dev/null
-#include <plat/clock.h>
+++ /dev/null
-#include <plat/cpu.h>
+++ /dev/null
-#ifndef __MACH_CPU_AXI_H
-#define __MACH_CPU_AXI_H
-
-#include <plat/cpu_axi.h>
-
-#define CPU_AXI_BUS_BASE RK30_CPU_AXI_BUS_BASE
-
-#define CPU_AXI_CPU0_QOS_BASE (CPU_AXI_BUS_BASE + 0x0080)
-#define CPU_AXI_DMAC_QOS_BASE (CPU_AXI_BUS_BASE + 0x0100)
-#define CPU_AXI_CPU1R_QOS_BASE (CPU_AXI_BUS_BASE + 0x0180)
-#define CPU_AXI_CPU1W_QOS_BASE (CPU_AXI_BUS_BASE + 0x0380)
-#define CPU_AXI_PERI_QOS_BASE (CPU_AXI_BUS_BASE + 0x4000)
-#define CPU_AXI_GPU_QOS_BASE (CPU_AXI_BUS_BASE + 0x5000)
-#define CPU_AXI_VPU_QOS_BASE (CPU_AXI_BUS_BASE + 0x6000)
-#define CPU_AXI_LCDC0_QOS_BASE (CPU_AXI_BUS_BASE + 0x7000)
-#define CPU_AXI_CIF0_QOS_BASE (CPU_AXI_BUS_BASE + 0x7080)
-#define CPU_AXI_IPP_QOS_BASE (CPU_AXI_BUS_BASE + 0x7100)
-#define CPU_AXI_LCDC1_QOS_BASE (CPU_AXI_BUS_BASE + 0x7180)
-#define CPU_AXI_CIF1_QOS_BASE (CPU_AXI_BUS_BASE + 0x7200)
-#define CPU_AXI_RGA_QOS_BASE (CPU_AXI_BUS_BASE + 0x7280)
-
-#endif
+++ /dev/null
-enum rk_plls_id {
- APLL_ID = 0,
- DPLL_ID,
- CPLL_ID,
- GPLL_ID,
- END_PLL_ID,
-};
-
-/*****cru reg offset*****/
-
-#define CRU_MODE_CON 0x40
-#define CRU_CLKSEL_CON 0x44
-#define CRU_CLKGATE_CON 0xd0
-#define CRU_GLB_SRST_FST 0x100
-#define CRU_GLB_SRST_SND 0x104
-#define CRU_SOFTRST_CON 0x110
-
-#define PLL_CONS(id, i) ((id) * 0x10 + ((i) * 4))
-
-#define CRU_CLKSELS_CON_CNT (35)
-#define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON + ((i) * 4))
-
-#define CRU_CLKGATES_CON_CNT (10)
-#define CRU_CLKGATES_CON(i) (CRU_CLKGATE_CON + ((i) * 4))
-
-#define CRU_SOFTRSTS_CON_CNT (9)
-#define CRU_SOFTRSTS_CON(i) (CRU_SOFTRST_CON + ((i) * 4))
-
-#define CRU_MISC_CON (0x134)
-#define CRU_GLB_CNT_TH (0x140)
-
-/********************************************************************/
-#define CRU_GET_REG_BITS_VAL(reg,bits_shift, msk) (((reg) >> (bits_shift))&(msk))
-#define CRU_W_MSK(bits_shift, msk) ((msk) << ((bits_shift) + 16))
-#define CRU_SET_BITS(val,bits_shift, msk) (((val)&(msk)) << (bits_shift))
-
-#define CRU_W_MSK_SETBITS(val,bits_shift,msk) (CRU_W_MSK(bits_shift, msk)|CRU_SET_BITS(val,bits_shift, msk))
-
-/*******************PLL CON0 BITS***************************/
-
-#define PLL_CLKFACTOR_SET(val, shift, msk) \
- ((((val) - 1) & (msk)) << (shift))
-
-#define PLL_CLKFACTOR_GET(reg, shift, msk) \
- ((((reg) >> (shift)) & (msk)) + 1)
-
-#define PLL_OD_MSK (0x3f)
-#define PLL_OD_SHIFT (0x0)
-
-#define PLL_CLKOD(val) PLL_CLKFACTOR_SET(val, PLL_OD_SHIFT, PLL_OD_MSK)
-#define PLL_NO(reg) PLL_CLKFACTOR_GET(reg, PLL_OD_SHIFT, PLL_OD_MSK)
-
-#define PLL_NO_SHIFT(reg) PLL_CLKFACTOR_GET(reg, PLL_OD_SHIFT, PLL_OD_MSK)
-
-#define PLL_CLKOD_SET(val) (PLL_CLKOD(val) | CRU_W_MSK(PLL_OD_SHIFT, PLL_OD_MSK))
-
-#define PLL_NR_MSK (0x3f)
-#define PLL_NR_SHIFT (8)
-#define PLL_CLKR(val) PLL_CLKFACTOR_SET(val, PLL_NR_SHIFT, PLL_NR_MSK)
-#define PLL_NR(reg) PLL_CLKFACTOR_GET(reg, PLL_NR_SHIFT, PLL_NR_MSK)
-
-#define PLL_CLKR_SET(val) (PLL_CLKR(val) | CRU_W_MSK(PLL_NR_SHIFT, PLL_NR_MSK))
-
-/*******************PLL CON1 BITS***************************/
-
-#define PLL_NF_MSK (0xffff)
-#define PLL_NF_SHIFT (0)
-#define PLL_CLKF(val) PLL_CLKFACTOR_SET(val, PLL_NF_SHIFT, PLL_NF_MSK)
-#define PLL_NF(reg) PLL_CLKFACTOR_GET(reg, PLL_NF_SHIFT, PLL_NF_MSK)
-
-#define PLL_CLKF_SET(val) (PLL_CLKF(val) | CRU_W_MSK(PLL_NF_SHIFT, PLL_NF_MSK))
-
-/*******************PLL CON2 BITS***************************/
-// "BWADJ" Just compatible with RK3188 plus
-#define PLL_BWADJ_MSK (0xfff & 0x000)
-#define PLL_BWADJ_SHIFT (0)
-#define PLL_CLK_BWADJ_SET(val) ((val) | CRU_W_MSK(PLL_BWADJ_SHIFT, PLL_BWADJ_MSK))
-/*******************PLL CON3 BITS***************************/
-// "RESET" Just compatible with RK3188 plus
-#define PLL_RESET_MSK ((1 & 0x0) << 5)
-#define PLL_RESET_W_MSK (PLL_RESET_MSK << 16)
-#define PLL_RESET (1 << 5)
-#define PLL_RESET_RESUME (0 << 5)
-
-#define PLL_BYPASS_MSK (1 << 0)
-#define PLL_BYPASS (1 << 0)
-#define PLL_NO_BYPASS (0 << 0)
-
-#define PLL_PWR_DN_MSK (1 << 1)
-#define PLL_PWR_DN_W_MSK (PLL_PWR_DN_MSK << 16)
-#define PLL_PWR_DN (1 << 1)
-#define PLL_PWR_ON (0 << 1)
-
-#define PLL_STANDBY_MSK (1 << 2)
-#define PLL_STANDBY (1 << 2)
-#define PLL_NO_STANDBY (0 << 2)
-/*******************CLKSEL0 BITS***************************/
-//core preiph div
-#define CORE_PERIPH_W_MSK (3 << 22)
-#define CORE_PERIPH_MSK (3 << 6)
-#define CORE_PERIPH_2 (0 << 6)
-#define CORE_PERIPH_4 (1 << 6)
-#define CORE_PERIPH_8 (2 << 6)
-#define CORE_PERIPH_16 (3 << 6)
-//arm clk pll sel
-#define CORE_SEL_PLL_MSK (1 << 8)
-#define CORE_SEL_PLL_W_MSK (1 << 24)
-#define CORE_SEL_APLL (0 << 8)
-#define CORE_SEL_GPLL (1 << 8)
-
-#define CORE_CLK_DIV_W_MSK (0x1F << 25)
-#define CORE_CLK_DIV_MSK (0x1F << 9)
-#define CORE_CLK_DIV(i) ((((i) - 1) & 0x1F) << 9)
-
-#define CPU_SEL_PLL_MSK (1 << 5)
-#define CPU_SEL_PLL_W_MSK (1 << 21)
-#define CPU_SEL_APLL (0 << 5)
-#define CPU_SEL_GPLL (1 << 5)
-
-#define CPU_CLK_DIV_W_MSK (0x1F << 16)
-#define CPU_CLK_DIV_MSK (0x1F)
-#define CPU_CLK_DIV(i) (((i) - 1) & 0x1F)
-
-/*******************CLKSEL1 BITS***************************/
-//aclk div
-#define GET_CORE_ACLK_VAL(reg) ((reg)>=4 ?8:((reg)+1))
-
-#define CPU_ACLK_W_MSK (7 << 16)
-#define CPU_ACLK_MSK (7 << 0)
-#define CPU_ACLK_11 (0 << 0)
-#define CPU_ACLK_21 (1 << 0)
-#define CPU_ACLK_31 (2 << 0)
-#define CPU_ACLK_41 (3 << 0)
-#define CPU_ACLK_81 (4 << 0)
-
-#define CORE_ACLK_W_MSK (7 << 19)
-#define CORE_ACLK_MSK (7 << 3)
-#define CORE_ACLK_11 (0 << 3)
-#define CORE_ACLK_21 (1 << 3)
-#define CORE_ACLK_31 (2 << 3)
-#define CORE_ACLK_41 (3 << 3)
-#define CORE_ACLK_81 (4 << 3)
-//hclk div
-#define ACLK_HCLK_W_MSK (3 << 24)
-#define ACLK_HCLK_MSK (3 << 8)
-#define ACLK_HCLK_11 (0 << 8)
-#define ACLK_HCLK_21 (1 << 8)
-#define ACLK_HCLK_41 (2 << 8)
-// pclk div
-#define ACLK_PCLK_W_MSK (3 << 28)
-#define ACLK_PCLK_MSK (3 << 12)
-#define ACLK_PCLK_11 (0 << 12)
-#define ACLK_PCLK_21 (1 << 12)
-#define ACLK_PCLK_41 (2 << 12)
-#define ACLK_PCLK_81 (3 << 12)
-// ahb2apb div
-#define AHB2APB_W_MSK (3 << 30)
-#define AHB2APB_MSK (3 << 14)
-#define AHB2APB_11 (0 << 14)
-#define AHB2APB_21 (1 << 14)
-#define AHB2APB_41 (2 << 14)
-
-/*******************MODE BITS***************************/
-
-#define PLL_MODE_MSK(id) (0x3 << ((id) * 4))
-#define PLL_MODE_SLOW(id) ((0x0<<((id)*4))|(0x3<<(16+(id)*4)))
-#define PLL_MODE_NORM(id) ((0x1<<((id)*4))|(0x3<<(16+(id)*4)))
-#define PLL_MODE_DEEP(id) ((0x2<<((id)*4))|(0x3<<(16+(id)*4)))
-
-/*******************clksel10***************************/
-
-#define PERI_ACLK_DIV_MASK 0x1f
-#define PERI_ACLK_DIV_W_MSK (PERI_ACLK_DIV_MASK << 16)
-#define PERI_ACLK_DIV(i) (((i) - 1) & PERI_ACLK_DIV_MASK)
-#define PERI_ACLK_DIV_OFF 0
-
-#define PERI_HCLK_DIV_MASK 0x3
-#define PERI_HCLK_DIV_OFF 8
-
-#define PERI_PCLK_DIV_MASK 0x3
-#define PERI_PCLK_DIV_OFF 12
-
-/*******************gate BITS***************************/
-
-#define CLK_GATE_CLKID(i) (16 * (i))
-#define CLK_GATE_CLKID_CONS(i) CRU_CLKGATES_CON((i) / 16)
-
-#define CLK_GATE(i) (1 << ((i)%16))
-#define CLK_UN_GATE(i) (0)
-
-#define CLK_GATE_W_MSK(i) (1 << (((i) % 16) + 16))
-
-enum cru_clk_gate {
- /* SCU CLK GATE 0 CON */
- CLK_GATE_CORE_PERIPH = CLK_GATE_CLKID(0),
- CLK_GATE_CPU_GPLL_PATH,
- CLK_GATE_DDRPHY,
- CLK_GATE_ACLK_CPU,
-
- CLK_GATE_HCLK_CPU,
- CLK_GATE_PCLK_CPU,
- CLK_GATE_ATCLK_CPU,
- CLK_GATE_ACLK_CORE,
-
- CLK_GATE_0RES8,
- CLK_GATE_I2S0_SRC,
- CLK_GATE_I2S0_FRAC,
- CLK_GATE_0RES11,
-
- CLK_GATE_0RES12,
- CLK_GATE_SPDIF_SRC,
- CLK_GATE_SPDIF_FRAC,
- CLK_GATE_TESTCLK,
-
- CLK_GATE_TIMER0 = CLK_GATE_CLKID(1),
- CLK_GATE_TIMER1,
- CLK_GATE_TIMER2,
- CLK_GATE_JTAG,
-
- CLK_GATE_ACLK_LCDC1_SRC,
- CLK_GATE_OTGPHY0,
- CLK_GATE_OTGPHY1,
- CLK_GATE_DDR_GPLL,
-
- CLK_GATE_UART0_SRC,
- CLK_GATE_UART0_FRAC_SRC,
- CLK_GATE_UART1_SRC,
- CLK_GATE_UART1_FRAC_SRC,
-
- CLK_GATE_UART2_SRC,
- CLK_GATE_UART2_FRAC_SRC,
- CLK_GATE_UART3_SRC,
- CLK_GATE_UART3_FRAC_SRC,
-
- CLK_GATE_PERIPH_SRC = CLK_GATE_CLKID(2),
- CLK_GATE_ACLK_PERIPH,
- CLK_GATE_HCLK_PERIPH,
- CLK_GATE_PCLK_PERIPH,
-
- CLK_GATE_SMC_SRC,
- CLK_GATE_MAC_SRC,
- CLK_GATE_HSADC_SRC,
- CLK_GATE_HSADC_FRAC_SRC,
-
- CLK_GATE_SARADC_SRC,
- CLK_GATE_SPI0_SRC,
- CLK_GATE_SPI1_SRC,
- CLK_GATE_MMC0_SRC,
-
- CLK_GATE_MAC_LBTEST,
- CLK_GATE_SDIO_SRC,
- CLK_GATE_EMMC_SRC,
- CLK_GATE_2RES15,
-
- CLK_GATE_ACLK_LCDC0_SRC = CLK_GATE_CLKID(3),
- CLK_GATE_DCLK_LCDC0_SRC,
- CLK_GATE_DCLK_LCDC1_SRC,
- CLK_GATE_PCLKIN_CIF0,
-
- CLK_GATE_3RES4,
- CLK_GATE_3RES5,
- CLK_GATE_HSICPHY_SRC,
- CLK_GATE_CIF0_OUT,
-
- CLK_GATE_3RES8,
- CLK_GATE_ACLK_VEPU,
- CLK_GATE_HCLK_VEPU,
- CLK_GATE_ACLK_VDPU,
-
- CLK_GATE_HCLK_VDPU,
- CLK_GATE_3RES13,
- CLK_GATE_3RES14,
- CLK_GATE_3RES15,
-
- CLK_GATE_HCLK_PERI_AXI_MATRIX = CLK_GATE_CLKID(4),
- CLK_GATE_PCLK_PERI_AXI_MATRIX,
- CLK_GATE_ACLK_CPU_PERI,
- CLK_GATE_ACLK_PERI_AXI_MATRIX,
-
- CLK_GATE_ACLK_PEI_NIU,
- CLK_GATE_HCLK_USB_PERI,
- CLK_GATE_HCLK_PERI_AHB_ARBI,
- CLK_GATE_HCLK_EMEM_PERI,
-
- CLK_GATE_HCLK_CPUBUS,
- CLK_GATE_HCLK_AHB2APB,
- CLK_GATE_ACLK_STRC_SYS,
- CLK_GATE_ACLK_L2MEM_CON,
-
- CLK_GATE_ACLK_INTMEM,
- CLK_GATE_4RES13,
- CLK_GATE_4RES14,
- CLK_GATE_HCLK_L2MEM,
-
- CLK_GATE_ACLK_DMAC1 = CLK_GATE_CLKID(5),
- CLK_GATE_ACLK_DMAC2,
- CLK_GATE_PCLK_EFUSE,
- CLK_GATE_PCLK_TZPC,
-
- CLK_GATE_PCLK_GRF,
- CLK_GATE_PCLK_PMU,
- CLK_GATE_HCLK_ROM,
- CLK_GATE_PCLK_DDRUPCTL,
-
- CLK_GATE_ACLK_SMC,
- CLK_GATE_HCLK_NANDC,
- CLK_GATE_HCLK_SDMMC0,
- CLK_GATE_HCLK_SDIO,
-
- CLK_GATE_HCLK_EMMC,
- CLK_GATE_HCLK_OTG0,
- CLK_GATE_5RES14,
- CLK_GATE_5RES15,
-
- CLK_GATE_ACLK_LCDC0 = CLK_GATE_CLKID(6),
- CLK_GATE_HCLK_LCDC0,
- CLK_GATE_HCLK_LCDC1,
- CLK_GATE_ACLK_LCDC1,
-
- CLK_GATE_HCLK_CIF0,
- CLK_GATE_ACLK_CIF0,
- CLK_GATE_6RES6,
- CLK_GATE_6RES7,
-
- CLK_GATE_ACLK_IPP,
- CLK_GATE_HCLK_IPP,
- CLK_GATE_HCLK_RGA,
- CLK_GATE_ACLK_RGA,
-
- CLK_GATE_HCLK_VIO_BUS,
- CLK_GATE_ACLK_VIO0,
- CLK_GATE_ACLK_VCODEC,
- CLK_GATE_HCLK_VIDEO_H2H,
-
- CLK_GATE_HCLK_EMAC = CLK_GATE_CLKID(7),
- CLK_GATE_HCLK_SPDIF,
- CLK_GATE_HCLK_I2S0_2CH,
- CLK_GATE_HCLK_OTG1,
-
- CLK_GATE_HCLK_HSIC,
- CLK_GATE_HCLK_HSADC,
- CLK_GATE_HCLK_PIDF,
- CLK_GATE_PCLK_TIMER0,
-
- CLK_GATE_PCLK_TIMER1,
- CLK_GATE_PCLK_TIMER2,
- CLK_GATE_PCLK_PWM01,
- CLK_GATE_PCLK_PWM23,
-
- CLK_GATE_PCLK_SPI0,
- CLK_GATE_PCLK_SPI1,
- CLK_GATE_PCLK_SARADC,
- CLK_GATE_PCLK_WDT,
-
- CLK_GATE_PCLK_UART0 = CLK_GATE_CLKID(8),
- CLK_GATE_PCLK_UART1,
- CLK_GATE_PCLK_UART2,
- CLK_GATE_PCLK_UART3,
-
- CLK_GATE_PCLK_I2C0,
- CLK_GATE_PCLK_I2C1,
- CLK_GATE_PCLK_I2C2,
- CLK_GATE_PCLK_I2C3,
-
- CLK_GATE_PCLK_I2C4,
- CLK_GATE_PCLK_GPIO0,
- CLK_GATE_PCLK_GPIO1,
- CLK_GATE_PCLK_GPIO2,
-
- CLK_GATE_PCLK_GPIO3,
- CLK_GATE_HCLK_GPS,
- CLK_GATE_8RES14,
- CLK_GATE_8RES15,
-
- CLK_GATE_CLK_CORE_DBG = CLK_GATE_CLKID(9),
- CLK_GATE_PCLK_DBG,
- CLK_GATE_CLK_TRACE,
- CLK_GATE_ATCLK,
-
- CLK_GATE_CLK_L2C,
- CLK_GATE_ACLK_VIO1,
- CLK_GATE_PCLK_PUBL,
- CLK_GATE_ACLK_GPU_MST,
-
- CLK_GATE_ACLK_GPU_SLV,
- CLK_GATE_CLK_GPU,
- CLK_GATE_9RES10,
- CLK_GATE_9RES11,
-
- CLK_GATE_9RES12,
- CLK_GATE_9RES13,
- CLK_GATE_9RES14,
- CLK_GATE_9RES15,
-
- CLK_GATE_MAX,
-};
-
-/* for compatible with rk30xx */
-#define CLK_GATE_ACLK_CIF1 CLK_GATE_ACLK_CIF0
-#define CLK_GATE_ACLK_INTMEM0 CLK_GATE_CLK_L2C
-#define CLK_GATE_ACLK_INTMEM1 CLK_GATE_ACLK_INTMEM0
-#define CLK_GATE_ACLK_INTMEM2 CLK_GATE_ACLK_INTMEM0
-#define CLK_GATE_ACLK_INTMEM3 CLK_GATE_ACLK_INTMEM0
-
-#define SOFT_RST_ID(i) (16 * (i))
-
-enum cru_soft_reset {
- SOFT_RST_0RES0 = SOFT_RST_ID(0),
- SOFT_RST_0RES1,
- SOFT_RST_MCORE,
- SOFT_RST_CORE0,
-
- SOFT_RST_CORE1,
- SOFT_RST_0RES5,
- SOFT_RST_0RES6,
- SOFT_RST_MCORE_DBG,
-
- SOFT_RST_CORE0_DBG,
- SOFT_RST_CORE1_DBG,
- SOFT_RST_0RES10,
- SOFT_RST_0RES11,
-
- SOFT_RST_CORE0_WDT,
- SOFT_RST_CORE1_WDT,
- SOFT_RST_STRC_SYS_AXI,
- SOFT_RST_L2C,
-
- SOFT_RST_1RES0 = SOFT_RST_ID(1),
- SOFT_RST_CPUSYS_AHB,
- SOFT_RST_L2MEM_CON_AXI,
- SOFT_RST_AHB2APB,
-
- SOFT_RST_DMA1,
- SOFT_RST_INTMEM,
- SOFT_RST_ROM,
- SOFT_RST_1RES7,
-
- SOFT_RST_I2S,
- SOFT_RST_1RES9,
- SOFT_RST_SPDIF,
- SOFT_RST_TIMER0,
-
- SOFT_RST_TIMER1,
- SOFT_RST_TIMER2,
- SOFT_RST_EFUSE_APB,
- SOFT_RST_1RES15,
-
- SOFT_RST_GPIO0 = SOFT_RST_ID(2),
- SOFT_RST_GPIO1,
- SOFT_RST_GPIO2,
- SOFT_RST_GPIO3,
-
- SOFT_RST_2RES4,
- SOFT_RST_2RES5,
- SOFT_RST_2RES6,
- SOFT_RST_UART0,
-
- SOFT_RST_UART1,
- SOFT_RST_UART2,
- SOFT_RST_UART3,
- SOFT_RST_I2C0,
-
- SOFT_RST_I2C1,
- SOFT_RST_I2C2,
- SOFT_RST_I2C3,
- SOFT_RST_I2C4,
-
- SOFT_RST_PWM0 = SOFT_RST_ID(3),
- SOFT_RST_PWM1,
- SOFT_RST_DAP_PO,
- SOFT_RST_DAP,
-
- SOFT_RST_DAP_SYS,
- SOFT_RST_TPIU_ATB,
- SOFT_RST_PMU_APB,
- SOFT_RST_GRF,
-
- SOFT_RST_PMU,
- SOFT_RST_PERIPHSYS_AXI,
- SOFT_RST_PERIPHSYS_AHB,
- SOFT_RST_PERIPHSYS_APB,
-
- SOFT_RST_PERIPH_NIU,
- SOFT_RST_CPU_PERI,
- SOFT_RST_EMEM_PERI,
- SOFT_RST_USB_PERI,
-
- SOFT_RST_DMA2 = SOFT_RST_ID(4),
- SOFT_RST_SMC,
- SOFT_RST_MAC,
- SOFT_RST_GPS,
-
- SOFT_RST_NANDC,
- SOFT_RST_USBOTG0,
- SOFT_RST_USBPHY0,
- SOFT_RST_OTGC0,
-
- SOFT_RST_USBOTG1,
- SOFT_RST_USBPHY1,
- SOFT_RST_OTGC1,
- SOFT_RST_HSICPHY,
-
- SOFT_RST_HSADC,
- SOFT_RST_PIDFILTER,
- SOFT_RST_4RES14,
- SOFT_RST_DDRMSCH,
-
- SOFT_RST_TZPC = SOFT_RST_ID(5),
- SOFT_RST_MMC0,
- SOFT_RST_SDIO,
- SOFT_RST_EMMC,
-
- SOFT_RST_SPI0,
- SOFT_RST_SPI1,
- SOFT_RST_WDT,
- SOFT_RST_SARADC,
-
- SOFT_RST_DDRPHY,
- SOFT_RST_DDRPHY_APB,
- SOFT_RST_DDRCTRL,
- SOFT_RST_DDRCTRL_APB,
-
- SOFT_RST_5RES12,
- SOFT_RST_DDRPHY_CTL,
- SOFT_RST_5RES14,
- SOFT_RST_5RES15,
-
- SOFT_RST_6RES0 = SOFT_RST_ID(6),
- SOFT_RST_6RES1,
- SOFT_RST_VIO0_AXI,
- SOFT_RST_VIO_BUS_AHB,
-
- SOFT_RST_LCDC0_AXI,
- SOFT_RST_LCDC0_AHB,
- SOFT_RST_LCDC0_DCLK,
- SOFT_RST_LCDC1_AXI,
-
- SOFT_RST_LCDC1_AHB,
- SOFT_RST_LCDC1_DCLK,
- SOFT_RST_IPP_AXI,
- SOFT_RST_IPP_AHB,
-
- SOFT_RST_RGA_AXI,
- SOFT_RST_RGA_AHB,
- SOFT_RST_CIF0,
- SOFT_RST_CIF1,//SOFT_RST_6RES15,
-
- SOFT_RST_VCODEC_AXI = SOFT_RST_ID(7),
- SOFT_RST_VCODEC_AHB,
- SOFT_RST_VIO1_AXI,
- SOFT_RST_CPU_VCODEC,
-
- SOFT_RST_VCODEC_NIU_AXI,
- SOFT_RST_HSIC_AHB,
- SOFT_RST_7RES6,
- SOFT_RST_7RES7,
-
- SOFT_RST_GPU_CORE,
- SOFT_RST_7RES9,
- SOFT_RST_GPU_NIU_AXI,
- SOFT_RST_7RES11,
-
- SOFT_RST_7RES12,
- SOFT_RST_TFUN_ATB,
- SOFT_RST_TFUN_APB,
- SOFT_RST_CTI4_APB,
-
- SOFT_RST_TPIU_APB = SOFT_RST_ID(8),
- SOFT_RST_TRACE,
- SOFT_RST_CORE_DBG,
- SOFT_RST_DBG_APB,
-
- SOFT_RST_CTI0,
- SOFT_RST_CTI0_APB,
- SOFT_RST_CTI1,
- SOFT_RST_CTI1_APB,
-
- SOFT_RST_PTM_CORE0,
- SOFT_RST_PTM_CORE1,
- SOFT_RST_PTM0,
- SOFT_RST_PTM0_ATB,
-
- SOFT_RST_PTM1,
- SOFT_RST_PTM1_ATB,
- SOFT_RST_CTM,
- SOFT_RST_TS,
-
- SOFT_RST_MAX,
-};
-
-/*****cru reg end*****/
-
-static inline void cru_set_soft_reset(enum cru_soft_reset idx, bool on)
-{
- const void __iomem *reg = RK30_CRU_BASE + CRU_SOFTRSTS_CON(idx >> 4);
- u32 val = on ? 0x10001U << (idx & 0xf) : 0x10000U << (idx & 0xf);
- writel_relaxed(val, reg);
- dsb();
-}
+++ /dev/null
-#ifndef __MACH_CRU_H
-#define __MACH_CRU_H
-#if defined(CONFIG_ARCH_RK3066B)
-#include <mach/cru-rk3066b.h>
-#elif defined(CONFIG_ARCH_RK30)
-enum rk_plls_id {
- APLL_ID = 0,
- DPLL_ID,
- CPLL_ID,
- GPLL_ID,
- END_PLL_ID,
-};
-
-/*****cru reg offset*****/
-
-#define CRU_MODE_CON 0x40
-#define CRU_CLKSEL_CON 0x44
-#define CRU_CLKGATE_CON 0xd0
-#define CRU_GLB_SRST_FST 0x100
-#define CRU_GLB_SRST_SND 0x104
-#define CRU_SOFTRST_CON 0x110
-
-#define PLL_CONS(id, i) ((id) * 0x10 + ((i) * 4))
-
-#define CRU_CLKSELS_CON_CNT (35)
-#define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON + ((i) * 4))
-
-#define CRU_CLKGATES_CON_CNT (10)
-#define CRU_CLKGATES_CON(i) (CRU_CLKGATE_CON + ((i) * 4))
-
-#define CRU_SOFTRSTS_CON_CNT (9)
-#define CRU_SOFTRSTS_CON(i) (CRU_SOFTRST_CON + ((i) * 4))
-
-#define CRU_MISC_CON (0x134)
-#define CRU_GLB_CNT_TH (0x140)
-
-/********************************************************************/
-#define CRU_GET_REG_BIYS_VAL(reg,bits_shift, msk) (((reg) >> (bits_shift))&(msk))
-#define CRU_W_MSK(bits_shift, msk) ((msk) << ((bits_shift) + 16))
-#define CRU_SET_BITS(val,bits_shift, msk) (((val)&(msk)) << (bits_shift))
-
-#define CRU_W_MSK_SETBITS(val,bits_shift,msk) (CRU_W_MSK(bits_shift, msk)|CRU_SET_BITS(val,bits_shift, msk))
-
-/*******************PLL CON0 BITS***************************/
-
-#define PLL_CLKFACTOR_SET(val, shift, msk) \
- ((((val) - 1) & (msk)) << (shift))
-
-#define PLL_CLKFACTOR_GET(reg, shift, msk) \
- ((((reg) >> (shift)) & (msk)) + 1)
-
-#define PLL_OD_MSK (0xf)
-#define PLL_OD_SHIFT (0x0)
-
-#define PLL_CLKOD(val) PLL_CLKFACTOR_SET(val, PLL_OD_SHIFT, PLL_OD_MSK)
-#define PLL_NO(reg) PLL_CLKFACTOR_GET(reg, PLL_OD_SHIFT, PLL_OD_MSK)
-
-#define PLL_NO_SHIFT(reg) PLL_CLKFACTOR_GET(reg, PLL_OD_SHIFT, PLL_OD_MSK)
-
-#define PLL_CLKOD_SET(val) (PLL_CLKOD(val) | CRU_W_MSK(PLL_OD_SHIFT, PLL_OD_MSK))
-
-#define PLL_NR_MSK (0x3f)
-#define PLL_NR_SHIFT (8)
-#define PLL_CLKR(val) PLL_CLKFACTOR_SET(val, PLL_NR_SHIFT, PLL_NR_MSK)
-#define PLL_NR(reg) PLL_CLKFACTOR_GET(reg, PLL_NR_SHIFT, PLL_NR_MSK)
-
-#define PLL_CLKR_SET(val) (PLL_CLKR(val) | CRU_W_MSK(PLL_NR_SHIFT, PLL_NR_MSK))
-
-/*******************PLL CON1 BITS***************************/
-
-#define PLL_NF_MSK (0x1fff)
-#define PLL_NF_SHIFT (0)
-#define PLL_CLKF(val) PLL_CLKFACTOR_SET(val, PLL_NF_SHIFT, PLL_NF_MSK)
-#define PLL_NF(reg) PLL_CLKFACTOR_GET(reg, PLL_NF_SHIFT, PLL_NF_MSK)
-
-#define PLL_CLKF_SET(val) (PLL_CLKF(val) | CRU_W_MSK(PLL_NF_SHIFT, PLL_NF_MSK))
-
-/*******************PLL CON2 BITS***************************/
-
-#define PLL_BWADJ_MSK (0xfff)
-#define PLL_BWADJ_SHIFT (0)
-#define PLL_CLK_BWADJ_SET(val) ((val) | CRU_W_MSK(PLL_BWADJ_SHIFT, PLL_BWADJ_MSK))
-
-/*******************PLL CON3 BITS***************************/
-
-#define PLL_REST_MSK (1 << 5)
-#define PLL_REST_W_MSK (PLL_REST_MSK << 16)
-#define PLL_REST (1 << 5)
-#define PLL_REST_RESM (0 << 5)
-
-#define PLL_BYPASS_MSK (1 << 0)
-#define PLL_BYPASS (1 << 0)
-#define PLL_NO_BYPASS (0 << 0)
-
-#define PLL_PWR_DN_MSK (1 << 1)
-#define PLL_PWR_DN_W_MSK (PLL_PWR_DN_MSK << 16)
-#define PLL_PWR_DN (1 << 1)
-#define PLL_PWR_ON (0 << 1)
-
-/*******************CLKSEL0 BITS***************************/
-//core preiph div
-#define CORE_PERIPH_W_MSK (3 << 22)
-#define CORE_PERIPH_MSK (3 << 6)
-#define CORE_PERIPH_2 (0 << 6)
-#define CORE_PERIPH_4 (1 << 6)
-#define CORE_PERIPH_8 (2 << 6)
-#define CORE_PERIPH_16 (3 << 6)
-//arm clk pll sel
-#define CORE_SEL_PLL_MSK (1 << 8)
-#define CORE_SEL_PLL_W_MSK (1 << 24)
-#define CORE_SEL_APLL (0 << 8)
-#define CORE_SEL_GPLL (1 << 8)
-
-#define CORE_CLK_DIV_W_MSK (0x1F << 16)
-#define CORE_CLK_DIV_MSK (0x1F)
-#define CORE_CLK_DIV(i) (((i) - 1) & 0x1F)
-
-/* for compatible with rk3066b */
-#define CPU_SEL_PLL_MSK CORE_SEL_PLL_MSK
-#define CPU_SEL_PLL_W_MSK CORE_SEL_PLL_W_MSK
-#define CPU_SEL_APLL CORE_SEL_APLL
-#define CPU_SEL_GPLL CORE_SEL_GPLL
-
-#define CPU_CLK_DIV_W_MSK CORE_CLK_DIV_W_MSK
-#define CPU_CLK_DIV_MSK CORE_CLK_DIV_MSK
-#define CPU_CLK_DIV(i) CORE_CLK_DIV(i)
-
-/*******************CLKSEL1 BITS***************************/
-//aclk div
-
-#define GET_CORE_ACLK_VAL(reg) ((reg)>=4 ?8:((reg)+1))
-
-/* for compatible with rk3066b */
-#define CPU_ACLK_W_MSK CORE_ACLK_W_MSK
-#define CPU_ACLK_MSK CORE_ACLK_MSK
-#define CPU_ACLK_11 CORE_ACLK_11
-#define CPU_ACLK_21 CORE_ACLK_21
-#define CPU_ACLK_31 CORE_ACLK_31
-#define CPU_ACLK_41 CORE_ACLK_41
-#define CPU_ACLK_81 CORE_ACLK_81
-
-#define CORE_ACLK_W_MSK (7 << 16)
-#define CORE_ACLK_MSK (7 << 0)
-#define CORE_ACLK_11 (0 << 0)
-#define CORE_ACLK_21 (1 << 0)
-#define CORE_ACLK_31 (2 << 0)
-#define CORE_ACLK_41 (3 << 0)
-#define CORE_ACLK_81 (4 << 0)
-
-//hclk div
-#define ACLK_HCLK_W_MSK (3 << 24)
-#define ACLK_HCLK_MSK (3 << 8)
-#define ACLK_HCLK_OFF (8)
-#define ACLK_HCLK_11 (0 << 8)
-#define ACLK_HCLK_21 (1 << 8)
-#define ACLK_HCLK_41 (2 << 8)
-// pclk div
-#define ACLK_PCLK_W_MSK (3 << 28)
-#define ACLK_PCLK_MSK (3 << 12)
-#define ACLK_PCLK_OFF (12)
-#define ACLK_PCLK_11 (0 << 12)
-#define ACLK_PCLK_21 (1 << 12)
-#define ACLK_PCLK_41 (2 << 12)
-#define ACLK_PCLK_81 (3 << 12)
-// ahb2apb div
-#define AHB2APB_W_MSK (3 << 30)
-#define AHB2APB_MSK (3 << 14)
-#define AHB2APB_11 (0 << 14)
-#define AHB2APB_21 (1 << 14)
-#define AHB2APB_41 (2 << 14)
-
-/*******************MODE BITS***************************/
-
-#define PLL_MODE_MSK(id) (0x3 << ((id) * 4))
-#define PLL_MODE_SLOW(id) ((0x0<<((id)*4))|(0x3<<(16+(id)*4)))
-#define PLL_MODE_NORM(id) ((0x1<<((id)*4))|(0x3<<(16+(id)*4)))
-#define PLL_MODE_DEEP(id) ((0x2<<((id)*4))|(0x3<<(16+(id)*4)))
-
-/*******************clksel10***************************/
-
-#define PERI_ACLK_DIV_MASK 0x1f
-#define PERI_ACLK_DIV_W_MSK (PERI_ACLK_DIV_MASK << 16)
-#define PERI_ACLK_DIV(i) (((i) - 1) & PERI_ACLK_DIV_MASK)
-#define PERI_ACLK_DIV_OFF 0
-
-#define PERI_HCLK_DIV_MASK 0x3
-#define PERI_HCLK_DIV_OFF 8
-
-#define PERI_PCLK_DIV_MASK 0x3
-#define PERI_PCLK_DIV_OFF 12
-
-/*******************gate BITS***************************/
-
-#define CLK_GATE_CLKID(i) (16 * (i))
-#define CLK_GATE_CLKID_CONS(i) CRU_CLKGATES_CON((i) / 16)
-
-#define CLK_GATE(i) (1 << ((i)%16))
-#define CLK_UN_GATE(i) (0)
-
-#define CLK_GATE_W_MSK(i) (1 << (((i) % 16) + 16))
-
-enum cru_clk_gate {
- /* SCU CLK GATE 0 CON */
- CLK_GATE_CORE_PERIPH = CLK_GATE_CLKID(0),
- CLK_GATE_CPU_GPLL_PATH,
- CLK_GATE_DDRPHY,
- CLK_GATE_ACLK_CPU,
- CLK_GATE_HCLK_CPU,
- CLK_GATE_PCLK_CPU,
- CLK_GATE_ATCLK_CPU,
- CLK_GATE_I2S0,
- CLK_GATE_I2S0_FRAC,
- CLK_GATE_I2S1,
- CLK_GATE_I2S1_FRAC,
- CLK_GATE_I2S2,
- CLK_GATE_I2S2_FRAC,
- CLK_GATE_SPDIF,
- CLK_GATE_SPDIF_FRAC,
- CLK_GATE_TESTCLK,
-
- CLK_GATE_TIMER0 = CLK_GATE_CLKID(1),
- CLK_GATE_TIMER1,
- CLK_GATE_TIMER2,
- CLK_GATE_JTAG,
- CLK_GATE_ACLK_LCDC1_SRC,
- CLK_GATE_OTGPHY0,
- CLK_GATE_OTGPHY1,
- CLK_GATE_DDR_GPLL,
- CLK_GATE_UART0,
- CLK_GATE_FRAC_UART0,
- CLK_GATE_UART1,
- CLK_GATE_FRAC_UART1,
- CLK_GATE_UART2,
- CLK_GATE_FRAC_UART2,
- CLK_GATE_UART3,
- CLK_GATE_FRAC_UART3,
-
- CLK_GATE_PERIPH_SRC = CLK_GATE_CLKID(2),
- CLK_GATE_ACLK_PERIPH,
- CLK_GATE_HCLK_PERIPH,
- CLK_GATE_PCLK_PERIPH,
- CLK_GATE_SMC,
- CLK_GATE_MAC,
- CLK_GATE_HSADC,
- CLK_GATE_HSADC_FRAC,
- CLK_GATE_SARADC,
- CLK_GATE_SPI0,
- CLK_GATE_SPI1,
- CLK_GATE_MMC0,
- CLK_GATE_MAC_LBTEST,
- CLK_GATE_SDIO,
- CLK_GATE_EMMC,
- CLK_GATE_TSADC,
-
- CLK_GATE_ACLK_LCDC0_SRC = CLK_GATE_CLKID(3),
- CLK_GATE_DCLK_LCDC0,
- CLK_GATE_DCLK_LCDC1,
- CLK_GATE_PCLKIN_CIF0,
- CLK_GATE_PCLKIN_CIF1,
- CLK_GATE3_RES5,
- CLK_GATE3_RES6,
- CLK_GATE_CIF0_OUT,
- CLK_GATE_CIF1_OUT,
- CLK_GATE_ACLK_VEPU,
- CLK_GATE_HCLK_VEPU,
- CLK_GATE_ACLK_VDPU,
- CLK_GATE_HCLK_VDPU,
- CLK_GATE_GPU_SRC,
- CLK_GATE3_RES14,
- CLK_GATE_XIN27M,
-
- CLK_GATE_HCLK_PERI_AXI_MATRIX = CLK_GATE_CLKID(4),
- CLK_GATE_PCLK_PERI_AXI_MATRIX,
- CLK_GATE_ACLK_CPU_PERI,
- CLK_GATE_ACLK_PERI_AXI_MATRIX,
- CLK_GATE_ACLK_PEI_NIU,
- CLK_GATE_HCLK_USB_PERI,
- CLK_GATE_HCLK_PERI_AHB_ARBI,
- CLK_GATE_HCLK_EMEM_PERI,
- CLK_GATE_HCLK_CPUBUS,
- CLK_GATE_HCLK_AHB2APB,
- CLK_GATE_ACLK_STRC_SYS,
- CLK_GATE_ACLK_L2MEM_CON,
- CLK_GATE_ACLK_INTMEM,
- CLK_GATE_PCLK_TSADC,
- CLK_GATE_HCLK_HDMI,
-
- CLK_GATE_ACLK_DMAC1 = CLK_GATE_CLKID(5),
- CLK_GATE_ACLK_DMAC2,
- CLK_GATE_PCLK_EFUSE,
- CLK_GATE_PCLK_TZPC,
- CLK_GATE_PCLK_GRF,
- CLK_GATE_PCLK_PMU,
- CLK_GATE_HCLK_ROM,
- CLK_GATE_PCLK_DDRUPCTL,
- CLK_GATE_ACLK_SMC,
- CLK_GATE_HCLK_NANDC,
- CLK_GATE_HCLK_SDMMC0,
- CLK_GATE_HCLK_SDIO,
- CLK_GATE_HCLK_EMMC,
- CLK_GATE_HCLK_OTG0,
- CLK_GATE_HCLK_OTG1,
- CLK_GATE_ACLK_GPU,
-
- CLK_GATE_ACLK_LCDC0 = CLK_GATE_CLKID(6),
- CLK_GATE_HCLK_LCDC0,
- CLK_GATE_HCLK_LCDC1,
- CLK_GATE_ACLK_LCDC1,
- CLK_GATE_HCLK_CIF0,
- CLK_GATE_ACLK_CIF0,
- CLK_GATE_HCLK_CIF1,
- CLK_GATE_ACLK_CIF1,
- CLK_GATE_ACLK_IPP,
- CLK_GATE_HCLK_IPP,
- CLK_GATE_HCLK_RGA,
- CLK_GATE_ACLK_RGA,
- CLK_GATE_HCLK_VIO_BUS,
- CLK_GATE_ACLK_VIO0,
- CLK_GATE_ACLK_VCODEC,
- CLK_GATE_SHCLK_VIO_H2H,
-
- CLK_GATE_HCLK_EMAC = CLK_GATE_CLKID(7),
- CLK_GATE_HCLK_SPDIF,
- CLK_GATE_HCLK_I2S0_2CH,
- CLK_GATE_HCLK_I2S1_2CH,
- CLK_GATE_HCLK_I2S_8CH,
- CLK_GATE_HCLK_HSADC,
- CLK_GATE_HCLK_PIDF,
- CLK_GATE_PCLK_TIMER0,
- CLK_GATE_PCLK_TIMER1,
- CLK_GATE_PCLK_TIMER2,
- CLK_GATE_PCLK_PWM01,
- CLK_GATE_PCLK_PWM23,
- CLK_GATE_PCLK_SPI0,
- CLK_GATE_PCLK_SPI1,
- CLK_GATE_PCLK_SARADC,
- CLK_GATE_PCLK_WDT,
-
- CLK_GATE_PCLK_UART0 = CLK_GATE_CLKID(8),
- CLK_GATE_PCLK_UART1,
- CLK_GATE_PCLK_UART2,
- CLK_GATE_PCLK_UART3,
- CLK_GATE_PCLK_I2C0,
- CLK_GATE_PCLK_I2C1,
- CLK_GATE_PCLK_I2C2,
- CLK_GATE_PCLK_I2C3,
- CLK_GATE_PCLK_I2C4,
- CLK_GATE_PCLK_GPIO0,
- CLK_GATE_PCLK_GPIO1,
- CLK_GATE_PCLK_GPIO2,
- CLK_GATE_PCLK_GPIO3,
- CLK_GATE_PCLK_GPIO4,
- CLK_GATE8_RES14,
- CLK_GATE_PCLK_GPIO6,
-
- CLK_GATE_CLK_CORE_DBG = CLK_GATE_CLKID(9),
- CLK_GATE_PCLK_DBG,
- CLK_GATE_CLK_TRACE,
- CLK_GATE_ATCLK,
- CLK_GATE_CLK_L2C,
- CLK_GATE_ACLK_VIO1,
- CLK_GATE_PCLK_PUBL,
- CLK_GATE_ACLK_INTMEM0,
- CLK_GATE_ACLK_INTMEM1,
- CLK_GATE_ACLK_INTMEM2,
- CLK_GATE_ACLK_INTMEM3,
-
- CLK_GATE_MAX,
-};
-
-/* for compatible with rk3066b */
-#define CLK_GATE_ACLK_CORE CLK_GATE_ACLK_CPU
-#define CLK_GATE_HCLK_L2MEM CLK_GATE_ACLK_INTMEM
-
-#define SOFT_RST_ID(i) (16 * (i))
-
-enum cru_soft_reset {
- SOFT_RST_GLB1 = SOFT_RST_ID(0),
- SOFT_RST_GLB2,
- SOFT_RST_MCORE,
- SOFT_RST_CORE0,
- SOFT_RST_CORE1,
- SOFT_RST_0RES5,
- SOFT_RST_0RES6,
- SOFT_RST_MCORE_DBG,
- SOFT_RST_CORE0_DBG,
- SOFT_RST_CORE1_DBG,
- SOFT_RST_0RES10,
- SOFT_RST_0RES11,
- SOFT_RST_CORE0_WDT,
- SOFT_RST_CORE1_WDT,
- SOFT_RST_STRC_SYS_AXI,
- SOFT_RST_L2C,
-
- SOFT_RST_1RES0 = SOFT_RST_ID(1),
- SOFT_RST_CPUSYS_AHB,
- SOFT_RST_L2MEM_CON_AXI,
- SOFT_RST_AHB2APB,
- SOFT_RST_DMA0,
- SOFT_RST_INTMEM,
- SOFT_RST_ROM,
- SOFT_RST_I2S0,
- SOFT_RST_I2S1,
- SOFT_RST_I2S2,
- SOFT_RST_SPDIF,
- SOFT_RST_TIMER0,
- SOFT_RST_TIMER1,
- SOFT_RST_TIMER2,
- SOFT_RST_EFUSE_APB,
-
- SOFT_RST_GPIO0 = SOFT_RST_ID(2),
- SOFT_RST_GPIO1,
- SOFT_RST_GPIO2,
- SOFT_RST_GPIO3,
- SOFT_RST_GPIO4,
- SOFT_RST_2RES5,
- SOFT_RST_GPIO6,
- SOFT_RST_UART0,
- SOFT_RST_UART1,
- SOFT_RST_UART2,
- SOFT_RST_UART3,
- SOFT_RST_I2C0,
- SOFT_RST_I2C1,
- SOFT_RST_I2C2,
- SOFT_RST_I2C3,
- SOFT_RST_I2C4,
-
- SOFT_RST_PWM0 = SOFT_RST_ID(3),
- SOFT_RST_PWM1,
- SOFT_RST_DAP_PO,
- SOFT_RST_DAP,
- SOFT_RST_DAP_SYS,
- SOFT_RST_TPIU_ATB,
- SOFT_RST_PMU_APB,
- SOFT_RST_GRF,
- SOFT_RST_PMU,
- SOFT_RST_PERIPHSYS_AXI,
- SOFT_RST_PERIPHSYS_AHB,
- SOFT_RST_PERIPHSYS_APB,
- SOFT_RST_PERIPH_NIU,
- SOFT_RST_CPU_PERI,
- SOFT_RST_EMEM_PERI,
- SOFT_RST_USB_PERI,
-
- SOFT_RST_DMA1 = SOFT_RST_ID(4),
- SOFT_RST_SMC,
- SOFT_RST_MAC,
- SOFT_RST_4RES3,
- SOFT_RST_NANDC,
- SOFT_RST_USBOTG0,
- SOFT_RST_USBPHY0,
- SOFT_RST_OTGC0,
- SOFT_RST_USBOTG1,
- SOFT_RST_USBPHY1,
- SOFT_RST_OTGC1,
- SOFT_RST_4RES11,
- SOFT_RST_HSADC,
- SOFT_RST_PIDFILTER,
- SOFT_RST_4RES14,
- SOFT_RST_DDRMSCH,
-
- SOFT_RST_TZPC = SOFT_RST_ID(5),
- SOFT_RST_MMC0,
- SOFT_RST_SDIO,
- SOFT_RST_EMMC,
- SOFT_RST_SPI0,
- SOFT_RST_SPI1,
- SOFT_RST_WDT,
- SOFT_RST_SARADC,
- SOFT_RST_DDRPHY,
- SOFT_RST_DDRPHY_APB,
- SOFT_RST_DDRCTRL,
- SOFT_RST_DDRCTRL_APB,
- SOFT_RST_TSADC,
- SOFT_RST_DDRPHY_CTL,
-
- SOFT_RST_HDMI = SOFT_RST_ID(6),
- SOFT_RST_HDMI_AHB,
- SOFT_RST_VIO0_AXI,
- SOFT_RST_VIO_BUS_AHB,
- SOFT_RST_LCDC0_AXI,
- SOFT_RST_LCDC0_AHB,
- SOFT_RST_LCDC0_DCLK,
- SOFT_RST_LCDC1_AXI,
- SOFT_RST_LCDC1_AHB,
- SOFT_RST_LCDC1_DCLK,
- SOFT_RST_IPP_AXI,
- SOFT_RST_IPP_AHB,
- SOFT_RST_RGA_AXI,
- SOFT_RST_RGA_AHB,
- SOFT_RST_CIF0,
- SOFT_RST_CIF1,
-
- SOFT_RST_VCODEC_AXI = SOFT_RST_ID(7),
- SOFT_RST_VCODEC_AHB,
- SOFT_RST_VIO1_AXI,
- SOFT_RST_CPU_VCODEC,
- SOFT_RST_VCODEC_NIU_AXI,
- SOFT_RST_7RES5,
- SOFT_RST_7RES6,
- SOFT_RST_7RES7,
- SOFT_RST_GPU_AXI,
- SOFT_RST_7RES9,
- SOFT_RST_GPU_NIU_AXI,
- SOFT_RST_7RES11,
- SOFT_RST_7RES12,
- SOFT_RST_TFUN_ATB,
- SOFT_RST_TFUN_APB,
- SOFT_RST_CTI4_APB,
-
- SOFT_RST_TPIU_APB = SOFT_RST_ID(8),
- SOFT_RST_TRACE,
- SOFT_RST_CORE_DBG,
- SOFT_RST_DBG_APB,
- SOFT_RST_CTI0,
- SOFT_RST_CTI0_APB,
- SOFT_RST_CTI1,
- SOFT_RST_CTI1_APB,
- SOFT_RST_PTM_CORE0,
- SOFT_RST_PTM_CORE1,
- SOFT_RST_PTM0,
- SOFT_RST_PTM0_ATB,
- SOFT_RST_PTM1,
- SOFT_RST_PTM1_ATB,
- SOFT_RST_CTM,
- SOFT_RST_TS,
-
- SOFT_RST_MAX,
-};
-
-/*****cru reg end*****/
-
-static inline void cru_set_soft_reset(enum cru_soft_reset idx, bool on)
-{
- const void __iomem *reg = RK30_CRU_BASE + CRU_SOFTRSTS_CON(idx >> 4);
- u32 val = on ? 0x10001U << (idx & 0xf) : 0x10000U << (idx & 0xf);
- writel_relaxed(val, reg);
- dsb();
-}
-
-#endif
-#endif
+++ /dev/null
-#include <plat/ddr.h>
+++ /dev/null
-#include <plat/debug-macro.S>
+++ /dev/null
-#ifndef __MACH_DEBUG_UART
-#define __MACH_DEBUG_UART
-
-#if CONFIG_RK_DEBUG_UART >= 0 && CONFIG_RK_DEBUG_UART < 4
-
-#if CONFIG_RK_DEBUG_UART == 0
-#define DEBUG_UART_PHYS RK30_UART0_PHYS
-#define DEBUG_UART_BASE RK30_UART0_BASE
-#elif CONFIG_RK_DEBUG_UART == 1
-#define DEBUG_UART_PHYS RK30_UART1_PHYS
-#define DEBUG_UART_BASE RK30_UART1_BASE
-#elif CONFIG_RK_DEBUG_UART == 2
-#define DEBUG_UART_PHYS RK30_UART2_PHYS
-#define DEBUG_UART_BASE RK30_UART2_BASE
-#elif CONFIG_RK_DEBUG_UART == 3
-#define DEBUG_UART_PHYS RK30_UART3_PHYS
-#define DEBUG_UART_BASE RK30_UART3_BASE
-#endif
-
-#define IRQ_DEBUG_UART (IRQ_UART0 + CONFIG_RK_DEBUG_UART)
-
-#endif
-
-#endif
+++ /dev/null
-#include <plat/dma-pl330.h>
+++ /dev/null
-#ifndef RK_MACH_DVFS_H
-#define RK_MACH_DVFS_H
-
-#include <plat/dvfs.h>
-
-#ifdef CONFIG_DVFS
-int rk_dvfs_init(void);
-void dvfs_adjust_table_lmtvolt(struct clk *clk, struct cpufreq_frequency_table *table);
-#else
-static inline int rk_dvfs_init(void){ return 0; }
-static inline void dvfs_adjust_table_lmtvolt(struct clk *clk, struct cpufreq_frequency_table *table){}
-#endif
-
-#endif
-
+++ /dev/null
-#include <plat/entry-macro.S>
+++ /dev/null
-#include <plat/fiq.h>
+++ /dev/null
-#ifndef __MACH_GPIO_H
-#define __MACH_GPIO_H
-
-#include <mach/irqs.h>
-#include <linux/init.h>
-
-#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
-#define GPIO_BANKS 4
-#elif defined(CONFIG_ARCH_RK319X)
-#define GPIO_BANKS 5
-#else
-#define GPIO_BANKS 7
-#endif
-
-#define RK30_PIN0_PA0 (0*NUM_GROUP + PIN_BASE + 0)
-#define RK30_PIN0_PA1 (0*NUM_GROUP + PIN_BASE + 1)
-#define RK30_PIN0_PA2 (0*NUM_GROUP + PIN_BASE + 2)
-#define RK30_PIN0_PA3 (0*NUM_GROUP + PIN_BASE + 3)
-#define RK30_PIN0_PA4 (0*NUM_GROUP + PIN_BASE + 4)
-#define RK30_PIN0_PA5 (0*NUM_GROUP + PIN_BASE + 5)
-#define RK30_PIN0_PA6 (0*NUM_GROUP + PIN_BASE + 6)
-#define RK30_PIN0_PA7 (0*NUM_GROUP + PIN_BASE + 7)
-#define RK30_PIN0_PB0 (0*NUM_GROUP + PIN_BASE + 8)
-#define RK30_PIN0_PB1 (0*NUM_GROUP + PIN_BASE + 9)
-#define RK30_PIN0_PB2 (0*NUM_GROUP + PIN_BASE + 10)
-#define RK30_PIN0_PB3 (0*NUM_GROUP + PIN_BASE + 11)
-#define RK30_PIN0_PB4 (0*NUM_GROUP + PIN_BASE + 12)
-#define RK30_PIN0_PB5 (0*NUM_GROUP + PIN_BASE + 13)
-#define RK30_PIN0_PB6 (0*NUM_GROUP + PIN_BASE + 14)
-#define RK30_PIN0_PB7 (0*NUM_GROUP + PIN_BASE + 15)
-#define RK30_PIN0_PC0 (0*NUM_GROUP + PIN_BASE + 16)
-#define RK30_PIN0_PC1 (0*NUM_GROUP + PIN_BASE + 17)
-#define RK30_PIN0_PC2 (0*NUM_GROUP + PIN_BASE + 18)
-#define RK30_PIN0_PC3 (0*NUM_GROUP + PIN_BASE + 19)
-#define RK30_PIN0_PC4 (0*NUM_GROUP + PIN_BASE + 20)
-#define RK30_PIN0_PC5 (0*NUM_GROUP + PIN_BASE + 21)
-#define RK30_PIN0_PC6 (0*NUM_GROUP + PIN_BASE + 22)
-#define RK30_PIN0_PC7 (0*NUM_GROUP + PIN_BASE + 23)
-#define RK30_PIN0_PD0 (0*NUM_GROUP + PIN_BASE + 24)
-#define RK30_PIN0_PD1 (0*NUM_GROUP + PIN_BASE + 25)
-#define RK30_PIN0_PD2 (0*NUM_GROUP + PIN_BASE + 26)
-#define RK30_PIN0_PD3 (0*NUM_GROUP + PIN_BASE + 27)
-#define RK30_PIN0_PD4 (0*NUM_GROUP + PIN_BASE + 28)
-#define RK30_PIN0_PD5 (0*NUM_GROUP + PIN_BASE + 29)
-#define RK30_PIN0_PD6 (0*NUM_GROUP + PIN_BASE + 30)
-#define RK30_PIN0_PD7 (0*NUM_GROUP + PIN_BASE + 31)
-
-#define RK30_PIN1_PA0 (1*NUM_GROUP + PIN_BASE + 0)
-#define RK30_PIN1_PA1 (1*NUM_GROUP + PIN_BASE + 1)
-#define RK30_PIN1_PA2 (1*NUM_GROUP + PIN_BASE + 2)
-#define RK30_PIN1_PA3 (1*NUM_GROUP + PIN_BASE + 3)
-#define RK30_PIN1_PA4 (1*NUM_GROUP + PIN_BASE + 4)
-#define RK30_PIN1_PA5 (1*NUM_GROUP + PIN_BASE + 5)
-#define RK30_PIN1_PA6 (1*NUM_GROUP + PIN_BASE + 6)
-#define RK30_PIN1_PA7 (1*NUM_GROUP + PIN_BASE + 7)
-#define RK30_PIN1_PB0 (1*NUM_GROUP + PIN_BASE + 8)
-#define RK30_PIN1_PB1 (1*NUM_GROUP + PIN_BASE + 9)
-#define RK30_PIN1_PB2 (1*NUM_GROUP + PIN_BASE + 10)
-#define RK30_PIN1_PB3 (1*NUM_GROUP + PIN_BASE + 11)
-#define RK30_PIN1_PB4 (1*NUM_GROUP + PIN_BASE + 12)
-#define RK30_PIN1_PB5 (1*NUM_GROUP + PIN_BASE + 13)
-#define RK30_PIN1_PB6 (1*NUM_GROUP + PIN_BASE + 14)
-#define RK30_PIN1_PB7 (1*NUM_GROUP + PIN_BASE + 15)
-#define RK30_PIN1_PC0 (1*NUM_GROUP + PIN_BASE + 16)
-#define RK30_PIN1_PC1 (1*NUM_GROUP + PIN_BASE + 17)
-#define RK30_PIN1_PC2 (1*NUM_GROUP + PIN_BASE + 18)
-#define RK30_PIN1_PC3 (1*NUM_GROUP + PIN_BASE + 19)
-#define RK30_PIN1_PC4 (1*NUM_GROUP + PIN_BASE + 20)
-#define RK30_PIN1_PC5 (1*NUM_GROUP + PIN_BASE + 21)
-#define RK30_PIN1_PC6 (1*NUM_GROUP + PIN_BASE + 22)
-#define RK30_PIN1_PC7 (1*NUM_GROUP + PIN_BASE + 23)
-#define RK30_PIN1_PD0 (1*NUM_GROUP + PIN_BASE + 24)
-#define RK30_PIN1_PD1 (1*NUM_GROUP + PIN_BASE + 25)
-#define RK30_PIN1_PD2 (1*NUM_GROUP + PIN_BASE + 26)
-#define RK30_PIN1_PD3 (1*NUM_GROUP + PIN_BASE + 27)
-#define RK30_PIN1_PD4 (1*NUM_GROUP + PIN_BASE + 28)
-#define RK30_PIN1_PD5 (1*NUM_GROUP + PIN_BASE + 29)
-#define RK30_PIN1_PD6 (1*NUM_GROUP + PIN_BASE + 30)
-#define RK30_PIN1_PD7 (1*NUM_GROUP + PIN_BASE + 31)
-
-#define RK30_PIN2_PA0 (2*NUM_GROUP + PIN_BASE + 0)
-#define RK30_PIN2_PA1 (2*NUM_GROUP + PIN_BASE + 1)
-#define RK30_PIN2_PA2 (2*NUM_GROUP + PIN_BASE + 2)
-#define RK30_PIN2_PA3 (2*NUM_GROUP + PIN_BASE + 3)
-#define RK30_PIN2_PA4 (2*NUM_GROUP + PIN_BASE + 4)
-#define RK30_PIN2_PA5 (2*NUM_GROUP + PIN_BASE + 5)
-#define RK30_PIN2_PA6 (2*NUM_GROUP + PIN_BASE + 6)
-#define RK30_PIN2_PA7 (2*NUM_GROUP + PIN_BASE + 7)
-#define RK30_PIN2_PB0 (2*NUM_GROUP + PIN_BASE + 8)
-#define RK30_PIN2_PB1 (2*NUM_GROUP + PIN_BASE + 9)
-#define RK30_PIN2_PB2 (2*NUM_GROUP + PIN_BASE + 10)
-#define RK30_PIN2_PB3 (2*NUM_GROUP + PIN_BASE + 11)
-#define RK30_PIN2_PB4 (2*NUM_GROUP + PIN_BASE + 12)
-#define RK30_PIN2_PB5 (2*NUM_GROUP + PIN_BASE + 13)
-#define RK30_PIN2_PB6 (2*NUM_GROUP + PIN_BASE + 14)
-#define RK30_PIN2_PB7 (2*NUM_GROUP + PIN_BASE + 15)
-#define RK30_PIN2_PC0 (2*NUM_GROUP + PIN_BASE + 16)
-#define RK30_PIN2_PC1 (2*NUM_GROUP + PIN_BASE + 17)
-#define RK30_PIN2_PC2 (2*NUM_GROUP + PIN_BASE + 18)
-#define RK30_PIN2_PC3 (2*NUM_GROUP + PIN_BASE + 19)
-#define RK30_PIN2_PC4 (2*NUM_GROUP + PIN_BASE + 20)
-#define RK30_PIN2_PC5 (2*NUM_GROUP + PIN_BASE + 21)
-#define RK30_PIN2_PC6 (2*NUM_GROUP + PIN_BASE + 22)
-#define RK30_PIN2_PC7 (2*NUM_GROUP + PIN_BASE + 23)
-#define RK30_PIN2_PD0 (2*NUM_GROUP + PIN_BASE + 24)
-#define RK30_PIN2_PD1 (2*NUM_GROUP + PIN_BASE + 25)
-#define RK30_PIN2_PD2 (2*NUM_GROUP + PIN_BASE + 26)
-#define RK30_PIN2_PD3 (2*NUM_GROUP + PIN_BASE + 27)
-#define RK30_PIN2_PD4 (2*NUM_GROUP + PIN_BASE + 28)
-#define RK30_PIN2_PD5 (2*NUM_GROUP + PIN_BASE + 29)
-#define RK30_PIN2_PD6 (2*NUM_GROUP + PIN_BASE + 30)
-#define RK30_PIN2_PD7 (2*NUM_GROUP + PIN_BASE + 31)
-
-#define RK30_PIN3_PA0 (3*NUM_GROUP + PIN_BASE + 0)
-#define RK30_PIN3_PA1 (3*NUM_GROUP + PIN_BASE + 1)
-#define RK30_PIN3_PA2 (3*NUM_GROUP + PIN_BASE + 2)
-#define RK30_PIN3_PA3 (3*NUM_GROUP + PIN_BASE + 3)
-#define RK30_PIN3_PA4 (3*NUM_GROUP + PIN_BASE + 4)
-#define RK30_PIN3_PA5 (3*NUM_GROUP + PIN_BASE + 5)
-#define RK30_PIN3_PA6 (3*NUM_GROUP + PIN_BASE + 6)
-#define RK30_PIN3_PA7 (3*NUM_GROUP + PIN_BASE + 7)
-#define RK30_PIN3_PB0 (3*NUM_GROUP + PIN_BASE + 8)
-#define RK30_PIN3_PB1 (3*NUM_GROUP + PIN_BASE + 9)
-#define RK30_PIN3_PB2 (3*NUM_GROUP + PIN_BASE + 10)
-#define RK30_PIN3_PB3 (3*NUM_GROUP + PIN_BASE + 11)
-#define RK30_PIN3_PB4 (3*NUM_GROUP + PIN_BASE + 12)
-#define RK30_PIN3_PB5 (3*NUM_GROUP + PIN_BASE + 13)
-#define RK30_PIN3_PB6 (3*NUM_GROUP + PIN_BASE + 14)
-#define RK30_PIN3_PB7 (3*NUM_GROUP + PIN_BASE + 15)
-#define RK30_PIN3_PC0 (3*NUM_GROUP + PIN_BASE + 16)
-#define RK30_PIN3_PC1 (3*NUM_GROUP + PIN_BASE + 17)
-#define RK30_PIN3_PC2 (3*NUM_GROUP + PIN_BASE + 18)
-#define RK30_PIN3_PC3 (3*NUM_GROUP + PIN_BASE + 19)
-#define RK30_PIN3_PC4 (3*NUM_GROUP + PIN_BASE + 20)
-#define RK30_PIN3_PC5 (3*NUM_GROUP + PIN_BASE + 21)
-#define RK30_PIN3_PC6 (3*NUM_GROUP + PIN_BASE + 22)
-#define RK30_PIN3_PC7 (3*NUM_GROUP + PIN_BASE + 23)
-#define RK30_PIN3_PD0 (3*NUM_GROUP + PIN_BASE + 24)
-#define RK30_PIN3_PD1 (3*NUM_GROUP + PIN_BASE + 25)
-#define RK30_PIN3_PD2 (3*NUM_GROUP + PIN_BASE + 26)
-#define RK30_PIN3_PD3 (3*NUM_GROUP + PIN_BASE + 27)
-#define RK30_PIN3_PD4 (3*NUM_GROUP + PIN_BASE + 28)
-#define RK30_PIN3_PD5 (3*NUM_GROUP + PIN_BASE + 29)
-#define RK30_PIN3_PD6 (3*NUM_GROUP + PIN_BASE + 30)
-#define RK30_PIN3_PD7 (3*NUM_GROUP + PIN_BASE + 31)
-
-#if GPIO_BANKS > 4
-#define RK30_PIN4_PA0 (4*NUM_GROUP + PIN_BASE + 0)
-#define RK30_PIN4_PA1 (4*NUM_GROUP + PIN_BASE + 1)
-#define RK30_PIN4_PA2 (4*NUM_GROUP + PIN_BASE + 2)
-#define RK30_PIN4_PA3 (4*NUM_GROUP + PIN_BASE + 3)
-#define RK30_PIN4_PA4 (4*NUM_GROUP + PIN_BASE + 4)
-#define RK30_PIN4_PA5 (4*NUM_GROUP + PIN_BASE + 5)
-#define RK30_PIN4_PA6 (4*NUM_GROUP + PIN_BASE + 6)
-#define RK30_PIN4_PA7 (4*NUM_GROUP + PIN_BASE + 7)
-#define RK30_PIN4_PB0 (4*NUM_GROUP + PIN_BASE + 8)
-#define RK30_PIN4_PB1 (4*NUM_GROUP + PIN_BASE + 9)
-#define RK30_PIN4_PB2 (4*NUM_GROUP + PIN_BASE + 10)
-#define RK30_PIN4_PB3 (4*NUM_GROUP + PIN_BASE + 11)
-#define RK30_PIN4_PB4 (4*NUM_GROUP + PIN_BASE + 12)
-#define RK30_PIN4_PB5 (4*NUM_GROUP + PIN_BASE + 13)
-#define RK30_PIN4_PB6 (4*NUM_GROUP + PIN_BASE + 14)
-#define RK30_PIN4_PB7 (4*NUM_GROUP + PIN_BASE + 15)
-#define RK30_PIN4_PC0 (4*NUM_GROUP + PIN_BASE + 16)
-#define RK30_PIN4_PC1 (4*NUM_GROUP + PIN_BASE + 17)
-#define RK30_PIN4_PC2 (4*NUM_GROUP + PIN_BASE + 18)
-#define RK30_PIN4_PC3 (4*NUM_GROUP + PIN_BASE + 19)
-#define RK30_PIN4_PC4 (4*NUM_GROUP + PIN_BASE + 20)
-#define RK30_PIN4_PC5 (4*NUM_GROUP + PIN_BASE + 21)
-#define RK30_PIN4_PC6 (4*NUM_GROUP + PIN_BASE + 22)
-#define RK30_PIN4_PC7 (4*NUM_GROUP + PIN_BASE + 23)
-#define RK30_PIN4_PD0 (4*NUM_GROUP + PIN_BASE + 24)
-#define RK30_PIN4_PD1 (4*NUM_GROUP + PIN_BASE + 25)
-#define RK30_PIN4_PD2 (4*NUM_GROUP + PIN_BASE + 26)
-#define RK30_PIN4_PD3 (4*NUM_GROUP + PIN_BASE + 27)
-#define RK30_PIN4_PD4 (4*NUM_GROUP + PIN_BASE + 28)
-#define RK30_PIN4_PD5 (4*NUM_GROUP + PIN_BASE + 29)
-#define RK30_PIN4_PD6 (4*NUM_GROUP + PIN_BASE + 30)
-#define RK30_PIN4_PD7 (4*NUM_GROUP + PIN_BASE + 31)
-#endif
-
-#if GPIO_BANKS > 5
-#define RK30_PIN6_PA0 (6*NUM_GROUP + PIN_BASE + 0)
-#define RK30_PIN6_PA1 (6*NUM_GROUP + PIN_BASE + 1)
-#define RK30_PIN6_PA2 (6*NUM_GROUP + PIN_BASE + 2)
-#define RK30_PIN6_PA3 (6*NUM_GROUP + PIN_BASE + 3)
-#define RK30_PIN6_PA4 (6*NUM_GROUP + PIN_BASE + 4)
-#define RK30_PIN6_PA5 (6*NUM_GROUP + PIN_BASE + 5)
-#define RK30_PIN6_PA6 (6*NUM_GROUP + PIN_BASE + 6)
-#define RK30_PIN6_PA7 (6*NUM_GROUP + PIN_BASE + 7)
-#define RK30_PIN6_PB0 (6*NUM_GROUP + PIN_BASE + 8)
-#define RK30_PIN6_PB1 (6*NUM_GROUP + PIN_BASE + 9)
-#define RK30_PIN6_PB2 (6*NUM_GROUP + PIN_BASE + 10)
-#define RK30_PIN6_PB3 (6*NUM_GROUP + PIN_BASE + 11)
-#define RK30_PIN6_PB4 (6*NUM_GROUP + PIN_BASE + 12)
-#define RK30_PIN6_PB5 (6*NUM_GROUP + PIN_BASE + 13)
-#define RK30_PIN6_PB6 (6*NUM_GROUP + PIN_BASE + 14)
-#define RK30_PIN6_PB7 (6*NUM_GROUP + PIN_BASE + 15)
-#endif
-
-#include <plat/gpio.h>
-
-#endif
+++ /dev/null
-#ifndef __MACH_GRF_RK3066B_H
-#define __MACH_GRF_RK3066B_H
-
-#include <asm/io.h>
-
-#define GRF_GPIO0L_DIR 0x0000
-#define GRF_GPIO0H_DIR 0x0004
-#define GRF_GPIO1L_DIR 0x0008
-#define GRF_GPIO1H_DIR 0x000c
-#define GRF_GPIO2L_DIR 0x0010
-#define GRF_GPIO2H_DIR 0x0014
-#define GRF_GPIO3L_DIR 0x0018
-#define GRF_GPIO3H_DIR 0x001c
-#define GRF_GPIO0L_DO 0x0020
-#define GRF_GPIO0H_DO 0x0024
-#define GRF_GPIO1L_DO 0x0028
-#define GRF_GPIO1H_DO 0x002c
-#define GRF_GPIO2L_DO 0x0030
-#define GRF_GPIO2H_DO 0x0034
-#define GRF_GPIO3L_DO 0x0038
-#define GRF_GPIO3H_DO 0x003c
-#define GRF_GPIO0L_EN 0x0040
-#define GRF_GPIO0H_EN 0x0044
-#define GRF_GPIO1L_EN 0x0048
-#define GRF_GPIO1H_EN 0x004c
-#define GRF_GPIO2L_EN 0x0050
-#define GRF_GPIO2H_EN 0x0054
-#define GRF_GPIO3L_EN 0x0058
-#define GRF_GPIO3H_EN 0x005c
-#define GRF_GPIO0A_IOMUX 0x0060
-#define GRF_GPIO0B_IOMUX 0x0064
-#define GRF_GPIO0C_IOMUX 0x0068
-#define GRF_GPIO0D_IOMUX 0x006c
-#define GRF_GPIO1A_IOMUX 0x0070
-#define GRF_GPIO1B_IOMUX 0x0074
-#define GRF_GPIO1C_IOMUX 0x0078
-#define GRF_GPIO1D_IOMUX 0x007c
-#define GRF_GPIO2A_IOMUX 0x0080
-#define GRF_GPIO2B_IOMUX 0x0084
-#define GRF_GPIO2C_IOMUX 0x0088
-#define GRF_GPIO2D_IOMUX 0x008c
-#define GRF_GPIO3A_IOMUX 0x0090
-#define GRF_GPIO3B_IOMUX 0x0094
-#define GRF_GPIO3C_IOMUX 0x0098
-#define GRF_GPIO3D_IOMUX 0x009c
-#define GRF_SOC_CON0 0x00a0
-#define GRF_SOC_CON1 0x00a4
-#define GRF_SOC_CON2 0x00a8
-#define GRF_SOC_STATUS0 0x00ac
-#define GRF_DMAC1_CON0 0x00b0
-#define GRF_DMAC1_CON1 0x00b4
-#define GRF_DMAC1_CON2 0x00b8
-#define GRF_DMAC2_CON0 0x00bc
-#define GRF_DMAC2_CON1 0x00c0
-#define GRF_DMAC2_CON2 0x00c4
-#define GRF_DMAC2_CON3 0x00c8
-#define GRF_IO_CON0 0x00f4
-#define GRF_IO_CON1 0x00f8
-#define GRF_IO_CON2 0x00fc
-#define GRF_IO_CON3 0x0100
-#define GRF_IO_CON4 0x0104
-#define GRF_UOC0_CON0 0x010c
-#define GRF_UOC0_CON1 0x0110
-#define GRF_UOC0_CON2 0x0114
-#define GRF_UOC0_CON3 0x0118
-#define GRF_UOC1_CON0 0x011c
-#define GRF_UOC1_CON1 0x0120
-#define GRF_UOC1_CON2 0x0124
-#define GRF_UOC1_CON3 0x0128
-#define GRF_UOC2_CON0 0x012c
-#define GRF_UOC2_CON1 0x0130
-#define GRF_UOC3_CON0 0x0138
-#define GRF_UOC3_CON1 0x013c
-#define GRF_HSIC_STAT 0x0140
-#define GRF_DDRC_CON0 0x00ec
-#define GRF_DDRC_STAT 0x00f0
-#define GRF_OS_REG0 0x0144
-#define GRF_OS_REG1 0x0148
-#define GRF_OS_REG2 0x014c
-#define GRF_OS_REG3 0x0150
-#define GRF_OS_REG4 0x0154
-#define GRF_OS_REG5 0x0158
-#define GRF_OS_REG6 0x015c
-#define GRF_OS_REG7 0x0160
-
-enum grf_io_power_domain_voltage {
- IO_PD_VOLTAGE_3_3V = 0,
- IO_PD_VOLTAGE_1_8V = 1,
-};
-
-enum grf_io_power_domain {
- IO_PD_AP0 = 8,
- IO_PD_AP1,
- IO_PD_CIF,
- IO_PD_FLASH,
- IO_PD_VCCIO0,
- IO_PD_VCCIO1,
- IO_PD_LCDC0,
- IO_PD_LCDC1,
-};
-
-static inline void grf_set_io_power_domain_voltage(enum grf_io_power_domain pd, enum grf_io_power_domain_voltage volt)
-{
- writel_relaxed((0x10000 + volt) << pd, RK30_GRF_BASE + GRF_IO_CON4);
- dsb();
-}
-
-static inline enum grf_io_power_domain_voltage grf_get_io_power_domain_voltage(enum grf_io_power_domain pd)
-{
- return (readl_relaxed(RK30_GRF_BASE + GRF_IO_CON4) >> pd) & 1;
-}
-
-#endif
+++ /dev/null
-#ifndef __MACH_HARDWARE_H
-#define __MACH_HARDWARE_H
-
-#endif
+++ /dev/null
-#ifndef __MACH_IO_H
-#define __MACH_IO_H
-
-#include <plat/io.h>
-
-/*
- * RK30 IO memory map:
- *
- * Virt Phys Size What
- * ---------------------------------------------------------------------------
- * FEA00000 10000000 1M
- * FEB00000 10100000 1M
- * FEC00000 10200000 176K
- * 10300000 1M Peri AXI BUS
- * FEC80000 10500000 16K NANDC
- * FECE0000 1FFE0000 128K CPU Debug
- * FED00000 20000000 640K
- * FEF00000 10080000/0 64K SRAM
- */
-
-#define RK30_IO_TO_VIRT0(pa) IOMEM(pa + (0xFEA00000 - 0x10000000))
-#define RK30_IO_TO_VIRT1(pa) IOMEM(pa + (0xFED00000 - 0x20000000))
-
-#define RK30_L2MEM_PHYS 0x10000000
-#define RK30_L2MEM_SIZE SZ_512K
-#define RK30_IMEM_PHYS 0x10080000
-#define RK30_IMEM_BASE IOMEM(0xFEF00000)
-#define RK30_IMEM_NONCACHED RK30_IO_TO_VIRT0(RK30_IMEM_PHYS)
-#if defined(CONFIG_ARCH_RK3066B)
-#define RK30_IMEM_SIZE SZ_16K
-#else
-#define RK30_IMEM_SIZE SZ_64K
-#endif
-#define RK30_GPU_PHYS 0x10090000
-#define RK30_GPU_SIZE SZ_64K
-
-#define RK30_ROM_PHYS 0x10100000
-#define RK30_ROM_BASE RK30_IO_TO_VIRT0(RK30_ROM_PHYS)
-#define RK30_ROM_SIZE SZ_16K
-#define RK30_VCODEC_PHYS 0x10104000
-#define RK30_VCODEC_SIZE SZ_16K
-#define RK30_CIF0_PHYS 0x10108000
-#define RK30_CIF0_SIZE SZ_8K
-#define RK30_CIF1_PHYS 0x1010a000
-#define RK30_CIF1_SIZE SZ_8K
-#define RK30_LCDC0_PHYS 0x1010c000
-#define RK30_LCDC0_SIZE SZ_8K
-#define RK30_LCDC1_PHYS 0x1010e000
-#define RK30_LCDC1_SIZE SZ_8K
-#define RK30_IPP_PHYS 0x10110000
-#define RK30_IPP_SIZE SZ_16K
-#define RK30_RGA_PHYS 0x10114000
-#define RK30_RGA_SIZE SZ_8K
-#define RK30_HDMI_PHYS 0x10116000
-#define RK30_HDMI_SIZE SZ_8K
-#define RK30_I2S0_8CH_PHYS 0x10118000
-#define RK30_I2S0_8CH_SIZE SZ_8K
-#define RK30_I2S1_2CH_PHYS 0x1011a000
-#define RK30_I2S1_2CH_SIZE SZ_8K
-#define RK30_I2S2_2CH_PHYS 0x1011c000
-#define RK30_I2S2_2CH_SIZE SZ_8K
-#define RK30_SPDIF_PHYS 0x1011e000
-#define RK30_SPDIF_SIZE SZ_8K
-
-#define RK30_UART0_PHYS 0x10124000
-#define RK30_UART0_BASE RK30_IO_TO_VIRT0(RK30_UART0_PHYS)
-#define RK30_UART0_SIZE SZ_8K
-#define RK30_UART1_PHYS 0x10126000
-#define RK30_UART1_BASE RK30_IO_TO_VIRT0(RK30_UART1_PHYS)
-#define RK30_UART1_SIZE SZ_8K
-#define RK30_CPU_AXI_BUS_PHYS 0x10128000
-#define RK30_CPU_AXI_BUS_BASE RK30_IO_TO_VIRT0(RK30_CPU_AXI_BUS_PHYS)
-#define RK30_CPU_AXI_BUS_SIZE SZ_32K
-
-#define RK30_L2C_PHYS 0x10138000
-#define RK30_L2C_BASE RK30_IO_TO_VIRT0(RK30_L2C_PHYS)
-#define RK30_L2C_SIZE SZ_16K
-#define RK30_SCU_PHYS 0x1013c000
-#define RK30_SCU_BASE RK30_IO_TO_VIRT0(RK30_SCU_PHYS)
-#define RK30_SCU_SIZE SZ_256
-#define RK30_GICC_PHYS 0x1013c100
-#define RK30_GICC_BASE RK30_IO_TO_VIRT0(RK30_GICC_PHYS)
-#define RK30_GICC_SIZE SZ_256
-#define RK30_GTIMER_PHYS 0x1013c200
-#define RK30_GTIMER_BASE RK30_IO_TO_VIRT0(RK30_GTIMER_PHYS)
-#define RK30_GTIMER_SIZE SZ_1K
-#define RK30_PTIMER_PHYS 0x1013c600
-#define RK30_PTIMER_BASE RK30_IO_TO_VIRT0(RK30_PTIMER_PHYS)
-#define RK30_PTIMER_SIZE (SZ_2K + SZ_512)
-#define RK30_GICD_PHYS 0x1013d000
-#define RK30_GICD_BASE RK30_IO_TO_VIRT0(RK30_GICD_PHYS)
-#define RK30_GICD_SIZE SZ_2K
-
-#define RK30_CORE_PHYS RK30_L2C_PHYS
-#define RK30_CORE_BASE RK30_IO_TO_VIRT0(RK30_CORE_PHYS)
-#define RK30_CORE_SIZE (RK30_L2C_SIZE + SZ_8K)
-
-#define RK30_USBHOST11_PHYS 0x10140000
-#define RK30_USBHOST11_SIZE SZ_256K
-#define RK30_USBOTG20_PHYS 0x10180000
-#define RK30_USBOTG20_SIZE SZ_256K
-#define RK30_USBHOST20_PHYS 0x101c0000
-#define RK30_USBHOST20_SIZE SZ_256K
-
-#define RK30_MAC_PHYS 0x10204000
-#define RK30_MAC_SIZE SZ_16K
-
-#define RK30_HSADC_PHYS 0x10210000
-#define RK30_HSADC_SIZE SZ_16K
-#define RK30_SDMMC0_PHYS 0x10214000
-#define RK30_SDMMC0_SIZE SZ_16K
-#define RK30_SDIO_PHYS 0x10218000
-#define RK30_SDIO_SIZE SZ_16K
-#define RK30_EMMC_PHYS 0x1021c000
-#define RK30_EMMC_SIZE SZ_16K
-#define RK30_PIDF_PHYS 0x10220000
-#define RK30_PIDF_SIZE SZ_16K
-
-#define RK30_PERI_AXI_BUS_PHYS 0x10300000
-#define RK30_PERI_AXI_BUS_SIZE SZ_1M
-
-#define RK30_NANDC_PHYS 0x10500000
-#define RK30_NANDC_SIZE SZ_16K
-
-#define RK30_SMC_BANK0_PHYS 0x11000000
-#define RK30_SMC_BANK0_SIZE SZ_16M
-#define RK30_SMC_BANK1_PHYS 0x12000000
-#define RK30_SMC_BANK1_SIZE SZ_16M
-
-#define RK30_CPU_DEBUG_PHYS 0x1FFE0000
-#define RK30_CPU_DEBUG_SIZE SZ_128K
-#define RK30_CRU_PHYS 0x20000000
-#define RK30_CRU_BASE RK30_IO_TO_VIRT1(RK30_CRU_PHYS)
-#define RK30_CRU_SIZE SZ_16K
-#define RK30_PMU_PHYS 0x20004000
-#define RK30_PMU_BASE RK30_IO_TO_VIRT1(RK30_PMU_PHYS)
-#define RK30_PMU_SIZE SZ_16K
-#define RK30_GRF_PHYS 0x20008000
-#define RK30_GRF_BASE RK30_IO_TO_VIRT1(RK30_GRF_PHYS)
-#define RK30_GRF_SIZE SZ_8K
-#define RK30_GPIO6_PHYS 0x2000a000
-#define RK30_GPIO6_BASE RK30_IO_TO_VIRT1(RK30_GPIO6_PHYS)
-#define RK30_GPIO6_SIZE SZ_8K
-
-#define RK30_TIMER2_PHYS 0x2000e000
-#define RK30_TIMER2_BASE RK30_IO_TO_VIRT1(RK30_TIMER2_PHYS)
-#define RK30_TIMER2_SIZE SZ_8K
-#define RK30_EFUSE_PHYS 0x20010000
-#define RK30_EFUSE_BASE RK30_IO_TO_VIRT1(RK30_EFUSE_PHYS)
-#define RK30_EFUSE_SIZE SZ_16K
-#define RK30_TZPC_PHYS 0x20014000
-#define RK30_TZPC_SIZE SZ_16K
-#define RK30_DMACS1_PHYS 0x20018000
-#define RK30_DMACS1_SIZE SZ_16K
-#define RK30_DMAC1_PHYS 0x2001c000
-#define RK30_DMAC1_SIZE SZ_16K
-#define RK30_DDR_PCTL_PHYS 0x20020000
-#define RK30_DDR_PCTL_BASE RK30_IO_TO_VIRT1(RK30_DDR_PCTL_PHYS)
-#define RK30_DDR_PCTL_SIZE SZ_16K
-
-#define RK30_I2C0_PHYS 0x2002c000
-#define RK30_I2C0_SIZE SZ_8K
-#define RK30_I2C1_PHYS 0x2002e000
-#define RK30_I2C1_BASE RK30_IO_TO_VIRT1(RK30_I2C1_PHYS)
-#define RK30_I2C1_SIZE SZ_8K
-#define RK30_PWM01_PHYS 0x20030000
-#define RK30_PWM01_BASE RK30_IO_TO_VIRT1(RK30_PWM01_PHYS)
-#define RK30_PWM01_SIZE SZ_16K
-#if defined(CONFIG_ARCH_RK3066B)
-#define RK30_GPIO0_PHYS 0x2000a000
-#else
-#define RK30_GPIO0_PHYS 0x20034000
-#endif
-#define RK30_GPIO0_BASE RK30_IO_TO_VIRT1(RK30_GPIO0_PHYS)
-#define RK30_GPIO0_SIZE SZ_16K
-#define RK30_TIMER0_PHYS 0x20038000
-#define RK30_TIMER0_BASE RK30_IO_TO_VIRT1(RK30_TIMER0_PHYS)
-#define RK30_TIMER0_SIZE SZ_8K
-#define RK30_TIMER1_PHYS 0x2003a000
-#define RK30_TIMER1_BASE RK30_IO_TO_VIRT1(RK30_TIMER1_PHYS)
-#define RK30_TIMER1_SIZE SZ_8K
-#define RK30_GPIO1_PHYS 0x2003c000
-#define RK30_GPIO1_BASE RK30_IO_TO_VIRT1(RK30_GPIO1_PHYS)
-#define RK30_GPIO1_SIZE SZ_8K
-#define RK30_GPIO2_PHYS 0x2003e000
-#define RK30_GPIO2_BASE RK30_IO_TO_VIRT1(RK30_GPIO2_PHYS)
-#define RK30_GPIO2_SIZE SZ_8K
-#define RK30_DDR_PUBL_PHYS 0x20040000
-#define RK30_DDR_PUBL_BASE RK30_IO_TO_VIRT1(RK30_DDR_PUBL_PHYS)
-#define RK30_DDR_PUBL_SIZE SZ_16K
-
-#define RK30_WDT_PHYS 0x2004c000
-#define RK30_WDT_SIZE SZ_16K
-#define RK30_PWM23_PHYS 0x20050000
-#define RK30_PWM23_BASE RK30_IO_TO_VIRT1(RK30_PWM23_PHYS)
-#define RK30_PWM23_SIZE SZ_16K
-#define RK30_I2C2_PHYS 0x20054000
-#define RK30_I2C2_SIZE SZ_16K
-#define RK30_I2C3_PHYS 0x20058000
-#define RK30_I2C3_SIZE SZ_16K
-#define RK30_I2C4_PHYS 0x2005c000
-#define RK30_I2C4_SIZE SZ_16K
-#define RK30_TSADC_PHYS 0x20060000
-#define RK30_TSADC_SIZE SZ_16K
-#define RK30_UART2_PHYS 0x20064000
-#define RK30_UART2_BASE RK30_IO_TO_VIRT1(RK30_UART2_PHYS)
-#define RK30_UART2_SIZE SZ_16K
-#define RK30_UART3_PHYS 0x20068000
-#define RK30_UART3_BASE RK30_IO_TO_VIRT1(RK30_UART3_PHYS)
-#define RK30_UART3_SIZE SZ_16K
-#define RK30_SARADC_PHYS 0x2006c000
-#define RK30_SARADC_SIZE SZ_16K
-#define RK30_SPI0_PHYS 0x20070000
-#define RK30_SPI0_SIZE SZ_16K
-#define RK30_SPI1_PHYS 0x20074000
-#define RK30_SPI1_SIZE SZ_16K
-#define RK30_DMAC2_PHYS 0x20078000
-#define RK30_DMAC2_SIZE SZ_16K
-#define RK30_SMC_PHYS 0x2007c000
-#define RK30_SMC_SIZE SZ_16K
-#define RK30_GPIO3_PHYS 0x20080000
-#define RK30_GPIO3_BASE RK30_IO_TO_VIRT1(RK30_GPIO3_PHYS)
-#define RK30_GPIO3_SIZE SZ_16K
-#define RK30_GPIO4_PHYS 0x20084000
-#define RK30_GPIO4_BASE RK30_IO_TO_VIRT1(RK30_GPIO4_PHYS)
-#define RK30_GPIO4_SIZE SZ_16K
-
-#define RK30_GPS_PHYS 0x10230000
-#define RK30_GPS_SIZE SZ_64K
-#define RK30_HSIC_PHYS 0x10240000
-#define RK30_HSIC_SIZE SZ_256K
-
-#define GIC_DIST_BASE RK30_GICD_BASE
-#define GIC_CPU_BASE RK30_GICC_BASE
-
-#endif
+++ /dev/null
-#ifndef __MACH_RK30_IOMUX_H
-#define __MACH_RK30_IOMUX_H
-#include <mach/io.h>
-#include <plat/iomux.h>
-#if defined(CONFIG_ARCH_RK3066B)
-
-#define GRF_IOMUX_BASE (RK30_GRF_BASE + 0x0060)
-#define GPIO_BANKS 4
-enum{
- /* GPIO0_A */
- /* GPIO0_B */
- /* GPIO0_C */
- GPIO0_C0 = 0x0c00, NAND_D8,
- GPIO0_C1 = 0x0c10, NAND_D9,
- GPIO0_C2 = 0x0c20, NAND_D10,
- GPIO0_C3 = 0x0c30, NAND_D11,
- GPIO0_C4 = 0x0c40, NAND_D12,
- GPIO0_C5 = 0x0c50, NAND_D13,
- GPIO0_C6 = 0x0c60, NAND_D14,
- GPIO0_C7 = 0x0c70, NAND_D15,
-
- /* GPIO0_D */
- GPIO0_D0 = 0x0d00, NAND_DQS, EMMC_CLKOUT,
- GPIO0_D1 = 0x0d10, NAND_CS1,
- GPIO0_D2 = 0x0d20, NAND_CS2, EMMC_CMD,
- GPIO0_D3 = 0x0d30, NAND_CS3, EMMC_RSTNOUT,
- GPIO0_D4 = 0x0d40, SPI1_RXD,
- GPIO0_D5 = 0x0d50, SPI1_TXD,
- GPIO0_D6 = 0x0d60, SPI1_CLK,
- GPIO0_D7 = 0x0d70, SPI1_CS0,
-
- /* GPIO1_A */
- GPIO1_A0 = 0x1a00, UART0_SIN,
- GPIO1_A1 = 0x1a10, UART0_SOUT,
- GPIO1_A2 = 0x1a20, UART0_CTSN,
- GPIO1_A3 = 0x1a30, UART0_RTSN,
- GPIO1_A4 = 0x1a40, UART1_SIN, SPI0_RXD,
- GPIO1_A5 = 0x1a50, UART1_SOUT, SPI0_TXD,
- GPIO1_A6 = 0x1a60, UART1_CTSN, SPI0_CLK,
- GPIO1_A7 = 0x1a70, UART1_RTSN, SPI0_CS0,
-
- /* GPIO1_B */
- GPIO1_B0 = 0x1b00, UART2_SIN, JTAG_TDI,
- GPIO1_B1 = 0x1b10, UART2_SOUT, JTAG_TDO,
- GPIO1_B2 = 0x1b20, UART3_SIN, GPS_MAG,
- GPIO1_B3 = 0x1b30, UART3_SOUT, GPS_SIG,
- GPIO1_B4 = 0x1b40, UART3_CTSN, GPS_RFCLK,
- GPIO1_B5 = 0x1b50, UART3_RTSN,
- GPIO1_B6 = 0x1b60, SPDIF_TX, SPI1_CS1,
- GPIO1_B7 = 0x1b70, SPI0_CS1,
-
- /* GPIO1_C */
- GPIO1_C0 = 0x1c00, I2S0_MCLK,
- GPIO1_C1 = 0x1c10, I2S0_SCLK,
- GPIO1_C2 = 0x1c20, I2S0_LRCKRX,
- GPIO1_C3 = 0x1c30, I2S0_LRCKTX,
- GPIO1_C4 = 0x1c40, I2S0_SDI,
- GPIO1_C5 = 0x1c50, I2S0_SDO,
-
- /* GPIO1_D */
- GPIO1_D0 = 0x1d00, I2C0_SDA,
- GPIO1_D1 = 0x1d10, I2C0_SCL,
- GPIO1_D2 = 0x1d20, I2C1_SDA,
- GPIO1_D3 = 0x1d30, I2C1_SCL,
- GPIO1_D4 = 0x1d40, I2C2_SDA,
- GPIO1_D5 = 0x1d50, I2C2_SCL,
- GPIO1_D6 = 0x1d60, I2C4_SDA,
- GPIO1_D7 = 0x1d70, I2C4_SCL,
-
- /* GPIO2_A */
- GPIO2_A0 = 0x2a00, LCDC1_D0, SMC_D0, TRACE_D0,
- GPIO2_A1 = 0x2a10, LCDC1_D1, SMC_D1, TRACE_D1,
- GPIO2_A2 = 0x2a20, LCDC1_D2, SMC_D2, TRACE_D2,
- GPIO2_A3 = 0x2a30, LCDC1_D3, SMC_D3, TRACE_D3,
- GPIO2_A4 = 0x2a40, LCDC1_D4, SMC_D4, TRACE_D4,
- GPIO2_A5 = 0x2a50, LCDC1_D5, SMC_D5, TRACE_D5,
- GPIO2_A6 = 0x2a60, LCDC1_D6, SMC_D6, TRACE_D6,
- GPIO2_A7 = 0x2a70, LCDC1_D7, SMC_D7, TRACE_D7,
-
- /* GPIO2_B */
- GPIO2_B0 = 0x2b00, LCDC1_D8, SMC_D8, TRACE_D8,
- GPIO2_B1 = 0x2b10, LCDC1_D9, SMC_D9, TRACE_D9,
- GPIO2_B2 = 0x2b20, LCDC1_D10, SMC_D10, TRACE_D10,
- GPIO2_B3 = 0x2b30, LCDC1_D11, SMC_D11, TRACE_D11,
- GPIO2_B4 = 0x2b40, LCDC1_D12, SMC_D12, TRACE_D12,
- GPIO2_B5 = 0x2b50, LCDC1_D13, SMC_D13, TRACE_D13,
- GPIO2_B6 = 0x2b60, LCDC1_D14, SMC_D14, TRACE_D14,
- GPIO2_B7 = 0x2b70, LCDC1_D15, SMC_D15, TRACE_D15,
-
- /* GPIO2_C */
- GPIO2_C0 = 0x2c00, LCDC1_D16, SMC_R0, TRACE_CLK,
- GPIO2_C1 = 0x2c10, LCDC1_D17, SMC_R1, TRACE_CTL,
- GPIO2_C2 = 0x2c20, LCDC1_D18, SMC_R2,
- GPIO2_C3 = 0x2c30, LCDC1_D19, SMC_R3,
- GPIO2_C4 = 0x2c40, LCDC1_D20, SMC_R4,
- GPIO2_C5 = 0x2c50, LCDC1_D21, SMC_R5,
- GPIO2_C6 = 0x2c60, LCDC1_D22, SMC_R6,
- GPIO2_C7 = 0x2c70, LCDC1_D23, SMC_R7,
-
- /* GPIO2_D */
- GPIO2_D0 = 0x2d00, LCDC1_DCLK, SMC_CS0,
- GPIO2_D1 = 0x2d10, LCDC1_DEN, SMC_WEN,
- GPIO2_D2 = 0x2d20, LCDC1_HSYNC, SMC_OEN,
- GPIO2_D3 = 0x2d30, LCDC1_VSYNC, SMC_ADVN,
- GPIO2_D4 = 0x2d40, SMC_BLSN0,
- GPIO2_D5 = 0x2d50, SMC_BLSN1,
- GPIO2_D6 = 0x2d60, SMC_CS1,
- GPIO2_D7 = 0x2d70, TEST_CLK_OUT,
-
- /* GPIO3_A */
- GPIO3_A0 = 0x3a00, MMC0_RSTNOUT,
- GPIO3_A1 = 0x3a10, MMC0_PWREN,
- GPIO3_A2 = 0x3a20, MMC0_CLKOUT,
- GPIO3_A3 = 0x3a30, MMC0_CMD,
- GPIO3_A4 = 0x3a40, MMC0_D0,
- GPIO3_A5 = 0x3a50, MMC0_D1,
- GPIO3_A6 = 0x3a60, MMC0_D2,
- GPIO3_A7 = 0x3a70, MMC0_D3,
-
- /* GPIO3_B */
- GPIO3_B0 = 0x3b00, MMC0_DETN,
- GPIO3_B1 = 0x3b10, MMC0_WRPRT,
- GPIO3_B3 = 0x3b30, CIF0_CLKOUT,
- GPIO3_B4 = 0x3b40, CIF0_D0, HSADC_D8,
- GPIO3_B5 = 0x3b50, CIF0_D1, HSADC_D9,
- GPIO3_B6 = 0x3b60, CIF0_D10, I2C3_SDA,
- GPIO3_B7 = 0x3b70, CIF0_D11, I2C3_SCL,
-
- /* GPIO3_C */
- GPIO3_C0 = 0x3c00, MMC1_CMD, RMII_TXEN,
- GPIO3_C1 = 0x3c10, MMC1_D0, RMII_TXD1,
- GPIO3_C2 = 0x3c20, MMC1_D1, RMII_TXD0,
- GPIO3_C3 = 0x3c30, MMC1_D2, RMII_RXD0,
- GPIO3_C4 = 0x3c40, MMC1_D3, RMII_RXD1,
- GPIO3_C5 = 0x3c50, MMC1_CLKOUT, RMII_CLKOUT, RMII_CLKIN,
- GPIO3_C6 = 0x3c60, MMC1_DETN, RMII_RXERR,
- GPIO3_C7 = 0x3c70, MMC1_WRPRT, RMII_CRS,
-
- /* GPIO3_D */
- GPIO3_D0 = 0x3d00, MMC1_PWREN, RMII_MD,
- GPIO3_D1 = 0x3d10, MMC1_BKEPWR, RMII_MDCLK,
- GPIO3_D2 = 0x3d20, MMC1_INTN,
- GPIO3_D3 = 0x3d30, PWM0,
- GPIO3_D4 = 0x3d40, PWM1, JTAG_TRSTN,
- GPIO3_D5 = 0x3d50, PWM2, JTAG_TCK, OTG_DRV_VBUS,
- GPIO3_D6 = 0x3d60, PWM3, JTAG_TMS, HOST_DRV_VBUS,
-
-};
-#else
-
-#define GRF_IOMUX_BASE (RK30_GRF_BASE + 0x00a8)
-#define GPIO_BANKS 7
-enum{
- /* GPIO0_A */
- GPIO0_A0 = 0x0a00, HDMI_HOTPLUGIN,
- GPIO0_A1 = 0x0a10, HDMI_DDCSCL,
- GPIO0_A2 = 0x0a20, HDMI_DDCSDA,
- GPIO0_A3 = 0x0a30, PWM0,
- GPIO0_A4 = 0x0a40, PWM1,
- GPIO0_A5 = 0x0a50, OTG_DRV_VBUS,
- GPIO0_A6 = 0x0a60, HOST_DRV_VBUS,
- GPIO0_A7 = 0x0a70, I2S0_SDI,
-
- /* GPIO0_B */
- GPIO0_B0 = 0x0b00, I2S0_MCLK,
- GPIO0_B1 = 0x0b10, I2S0_SCLK,
- GPIO0_B2 = 0x0b20, I2S0_LRCKRX,
- GPIO0_B3 = 0x0b30, I2S0_LRCKTX,
- GPIO0_B4 = 0x0b40, I2S0_SDO0,
- GPIO0_B5 = 0x0b50, I2S0_SDO1,
- GPIO0_B6 = 0x0b60, I2S0_SDO2,
- GPIO0_B7 = 0x0b70, I2S0_SDO3,
-
- /* GPIO0_C */
- GPIO0_C0 = 0x0c00, I2S1_MCLK,
- GPIO0_C1 = 0x0c10, I2S1_SCLK,
- GPIO0_C2 = 0x0c20, I2S1_LRCKRX,
- GPIO0_C3 = 0x0c30, I2S1_LRCKTX,
- GPIO0_C4 = 0x0c40, I2S1_SDI,
- GPIO0_C5 = 0x0c50, I2S1_SDO,
- GPIO0_C6 = 0x0c60, TRACE_CLK, SMC_R2,
- GPIO0_C7 = 0x0c70, TRACE_CTL, SMC_R3,
-
- /* GPIO0_D */
- GPIO0_D0 = 0x0d00, I2S2_MCLK, SMC_CS0,
- GPIO0_D1 = 0x0d10, I2S2_SCLK, SMC_WEN,
- GPIO0_D2 = 0x0d20, I2S2_LRCKRX, SMC_OEN,
- GPIO0_D3 = 0x0d30, I2S2_LRCKTX, SMC_ADVN,
- GPIO0_D4 = 0x0d40, I2S2_SDI, SMC_R0,
- GPIO0_D5 = 0x0d50, I2S2_SDO, SMC_R1,
- GPIO0_D6 = 0x0d60, PWM2,
- GPIO0_D7 = 0x0d70, PWM3,
-
- /* GPIO1_A */
- GPIO1_A0 = 0x1a00, UART0_SIN,
- GPIO1_A1 = 0x1a10, UART0_SOUT,
- GPIO1_A2 = 0x1a20, UART0_CTSN,
- GPIO1_A3 = 0x1a30, UART0_RTSN,
- GPIO1_A4 = 0x1a40, UART1_SIN, SPI0_CS0,
- GPIO1_A5 = 0x1a50, UART1_SOUT, SPI0_CLK,
- GPIO1_A6 = 0x1a60, UART1_CTSN, SPI0_RXD,
- GPIO1_A7 = 0x1a70, UART1_RTSN, SPI0_TXD,
-
- /* GPIO1_B */
- GPIO1_B0 = 0x1b00, UART2_SIN,
- GPIO1_B1 = 0x1b10, UART2_SOUT,
- GPIO1_B2 = 0x1b20, SPDIF_TX,
- GPIO1_B3 = 0x1b30, CIF0_CLKOUT,
- GPIO1_B4 = 0x1b40, CIF0_D0,
- GPIO1_B5 = 0x1b50, CIF0_D1,
- GPIO1_B6 = 0x1b60, CIF0_D10,
- GPIO1_B7 = 0x1b70, CIF0_D11,
-
- /* GPIO1_C */
- GPIO1_C0 = 0x1c00, CIF1_D2, RMII_CLKOUT, RMII_CLKIN,
- GPIO1_C1 = 0x1c10, CIF1_D3, RMII_TXEN,
- GPIO1_C2 = 0x1c20, CIF1_D4, RMII_TXD1,
- GPIO1_C3 = 0x1c30, CIF1_D5, RMII_TXD0,
- GPIO1_C4 = 0x1c40, CIF1_D6, RMII_RXERR,
- GPIO1_C5 = 0x1c50, CIF1_D7, RMII_CRS,
- GPIO1_C6 = 0x1c60, CIF1_D8, RMII_RXD1,
- GPIO1_C7 = 0x1c70, CIF1_D9, RMII_RXD0,
-
- /* GPIO1_D */
- GPIO1_D0 = 0x1d00, CIF1_VSYNC, RMII_MD,
- GPIO1_D1 = 0x1d10, CIF1_HREF, RMII_MDCLK,
- GPIO1_D2 = 0x1d20, CIF1_CLKIN,
- GPIO1_D3 = 0x1d30, CIF1_D0,
- GPIO1_D4 = 0x1d40, CIF1_D1,
- GPIO1_D5 = 0x1d50, CIF1_D10,
- GPIO1_D6 = 0x1d60, CIF1_D11,
- GPIO1_D7 = 0x1d70, CIF1_CLKOUT,
-
- /* GPIO2_A */
- GPIO2_A0 = 0x2a00, LCDC1_D0, SMC_R4,
- GPIO2_A1 = 0x2a10, LCDC1_D1, SMC_R5,
- GPIO2_A2 = 0x2a20, LCDC1_D2, SMC_R6,
- GPIO2_A3 = 0x2a30, LCDC1_D3, SMC_R7,
- GPIO2_A4 = 0x2a40, LCDC1_D4, SMC_R8,
- GPIO2_A5 = 0x2a50, LCDC1_D5, SMC_R9,
- GPIO2_A6 = 0x2a60, LCDC1_D6, SMC_R10,
- GPIO2_A7 = 0x2a70, LCDC1_D7, SMC_R11,
-
- /* GPIO2_B */
- GPIO2_B0 = 0x2b00, LCDC1_D8, SMC_R12,
- GPIO2_B1 = 0x2b10, LCDC1_D9, SMC_R13,
- GPIO2_B2 = 0x2b20, LCDC1_D10, SMC_R14,
- GPIO2_B3 = 0x2b30, LCDC1_D11, SMC_R15,
- GPIO2_B4 = 0x2b40, LCDC1_D12, SMC_R16, HSADC_D9,
- GPIO2_B5 = 0x2b50, LCDC1_D13, SMC_R17, HSADC_D8,
- GPIO2_B6 = 0x2b60, LCDC1_D14, SMC_R18, TS_SYNC,
- GPIO2_B7 = 0x2b70, LCDC1_D15, SMC_R19, HSADC_D7,
-
- /* GPIO2_C */
- GPIO2_C0 = 0x2c00, LCDC1_D16, GPS_CLK, HSADC_CLKOUT,
- GPIO2_C1 = 0x2c10, LCDC1_D17, SMC_BLSN0, HSADC_D6,
- GPIO2_C2 = 0x2c20, LCDC1_D18, SMC_BLSN1, HSADC_D5,
- GPIO2_C3 = 0x2c30, LCDC1_D19, SPI1_CLK, HSADC_D0,
- GPIO2_C4 = 0x2c40, LCDC1_D20, SPI1_CS0, HSADC_D1,
- GPIO2_C5 = 0x2c50, LCDC1_D21, SPI1_TXD, HSADC_D2,
- GPIO2_C6 = 0x2c60, LCDC1_D22, SPI1_RXD, HSADC_D3,
- GPIO2_C7 = 0x2c70, LCDC1_D23, SPI1_CS1, HSADC_D4,
-
- /* GPIO2_D */
- GPIO2_D0 = 0x2d00, LCDC1_DCLK,
- GPIO2_D1 = 0x2d10, LCDC1_DEN, SMC_CS1,
- GPIO2_D2 = 0x2d20, LCDC1_HSYNC,
- GPIO2_D3 = 0x2d30, LCDC1_VSYNC,
- GPIO2_D4 = 0x2d40, I2C0_SDA,
- GPIO2_D5 = 0x2d50, I2C0_SCL,
- GPIO2_D6 = 0x2d60, I2C1_SDA,
- GPIO2_D7 = 0x2d70, I2C1_SCL,
-
- /* GPIO3_A */
- GPIO3_A0 = 0x3a00, I2C2_SDA,
- GPIO3_A1 = 0x3a10, I2C2_SCL,
- GPIO3_A2 = 0x3a20, I2C3_SDA,
- GPIO3_A3 = 0x3a30, I2C3_SCL,
- GPIO3_A4 = 0x3a40, I2C4_SDA,
- GPIO3_A5 = 0x3a50, I2C4_SCL,
- GPIO3_A6 = 0x3a60, MMC0_RSTNOUT,
- GPIO3_A7 = 0x3a70, MMC0_PWREN,
-
- /* GPIO3_B */
- GPIO3_B0 = 0x3b00, MMC0_CLKOUT,
- GPIO3_B1 = 0x3b10, MMC0_CMD,
- GPIO3_B2 = 0x3b20, MMC0_D0,
- GPIO3_B3 = 0x3b30, MMC0_D1,
- GPIO3_B4 = 0x3b40, MMC0_D2,
- GPIO3_B5 = 0x3b50, MMC0_D3,
- GPIO3_B6 = 0x3b60, MMC0_DETN,
- GPIO3_B7 = 0x3b70, MMC0_WRPRT,
-
- /* GPIO3_C */
- GPIO3_C0 = 0x3c00, MMC1_CMD,
- GPIO3_C1 = 0x3c10, MMC1_D0,
- GPIO3_C2 = 0x3c20, MMC1_D1,
- GPIO3_C3 = 0x3c30, MMC1_D2,
- GPIO3_C4 = 0x3c40, MMC1_D3,
- GPIO3_C5 = 0x3c50, MMC1_CLKOUT,
- GPIO3_C6 = 0x3c60, MMC1_DETN,
- GPIO3_C7 = 0x3c70, MMC1_WRPRT,
-
- /* GPIO3_D */
- GPIO3_D0 = 0x3d00, MMC1_PWREN,
- GPIO3_D1 = 0x3d10, MMC1_BKEPWR,
- GPIO3_D2 = 0x3d20, MMC1_INTN,
- GPIO3_D3 = 0x3d30, UART3_SIN,
- GPIO3_D4 = 0x3d40, UART3_SOUT,
- GPIO3_D5 = 0x3d50, UART3_CTSN,
- GPIO3_D6 = 0x3d60, UART3_RTSN,
- GPIO3_D7 = 0x3d70, NAND_DQS, EMMC_CLKOUT,
-
- /* GPIO4_A */
- GPIO4_A0 = 0x4a00, NAND_D8,
- GPIO4_A1 = 0x4a10, NAND_D9,
- GPIO4_A2 = 0x4a20, NAND_D10,
- GPIO4_A3 = 0x4a30, NAND_D11,
- GPIO4_A4 = 0x4a40, NAND_D12,
- GPIO4_A5 = 0x4a50, NAND_D13,
- GPIO4_A6 = 0x4a60, NAND_D14,
- GPIO4_A7 = 0x4a70, NAND_D15,
-
- /* GPIO4_B */
- GPIO4_B0 = 0x4b00, NAND_CS1,
- GPIO4_B1 = 0x4b10, NAND_CS2, EMMC_CMD,
- GPIO4_B2 = 0x4b20, NAND_CS3, EMMC_RSTNOUT,
- GPIO4_B3 = 0x4b30, NAND_CS4,
- GPIO4_B4 = 0x4b40, NAND_CS5,
- GPIO4_B5 = 0x4b50, NAND_CS6,
- GPIO4_B6 = 0x4b60, NAND_CS7,
- GPIO4_B7 = 0x4b70, SPI0_CS1,
-
- /* GPIO4_C */
- GPIO4_C0 = 0x4c00, SMC_D0, TRACE_D0,
- GPIO4_C1 = 0x4c10, SMC_D1, TRACE_D1,
- GPIO4_C2 = 0x4c20, SMC_D2, TRACE_D2,
- GPIO4_C3 = 0x4c30, SMC_D3, TRACE_D3,
- GPIO4_C4 = 0x4c40, SMC_D4, TRACE_D4,
- GPIO4_C5 = 0x4c50, SMC_D5, TRACE_D5,
- GPIO4_C6 = 0x4c60, SMC_D6, TRACE_D6,
- GPIO4_C7 = 0x4c70, SMC_D7, TRACE_D7,
-
- /* GPIO4_D */
- GPIO4_D0 = 0x4d00, SMC_D8, TRACE_D8,
- GPIO4_D1 = 0x4d10, SMC_D9, TRACE_D9,
- GPIO4_D2 = 0x4d20, SMC_D10, TRACE_D10,
- GPIO4_D3 = 0x4d30, SMC_D11, TRACE_D11,
- GPIO4_D4 = 0x4d40, SMC_D12, TRACE_D12,
- GPIO4_D5 = 0x4d50, SMC_D13, TRACE_D13,
- GPIO4_D6 = 0x4d60, SMC_D14, TRACE_D14,
- GPIO4_D7 = 0x4d70, SMC_D15, TRACE_D15,
-
- /* GPIO6_A */
- /* GPIO6_B */
- GPIO6_B7 = 0x6b70, TEST_CLK_OUT,
-
- /* GPIO6_C */
- /* GPIO6_D */
-};
-#endif
-
-#endif
+++ /dev/null
-#ifndef __MACH_IOMUX_H__
-#define __MACH_IOMUX_H__
-
-#include <linux/init.h>
-#include <mach/iomux-rk30.h>
-#if defined(CONFIG_ARCH_RK3066B)
-
-#include <mach/grf-rk3066b.h>
-#define rk29_mux_api_set(name, mode) iomux_set(mode)
-#define rk30_mux_api_set(name, mode) iomux_set(mode)
-#define rk30_iomux_init() iomux_init()
-
-#elif defined(CONFIG_ARCH_RK30)
-//GPIO0A
-#define GPIO0A_GPIO0A7 0
-#define GPIO0A_I2S_8CH_SDI 1
-#define GPIO0A_GPIO0A6 0
-#define GPIO0A_HOST_DRV_VBUS 1
-#define GPIO0A_GPIO0A5 0
-#define GPIO0A_OTG_DRV_VBUS 1
-#define GPIO0A_GPIO0A4 0
-#define GPIO0A_PWM1 1
-#define GPIO0A_GPIO0A3 0
-#define GPIO0A_PWM0 1
-#define GPIO0A_GPIO0A2 0
-#define GPIO0A_HDMI_I2C_SDA 1
-#define GPIO0A_GPIO0A1 0
-#define GPIO0A_HDMI_I2C_SCL 1
-#define GPIO0A_GPIO0A0 0
-#define GPIO0A_HDMI_HOT_PLUG_IN 1
-
-
-//GPIO0B
-#define GPIO0B_GPIO0B7 0
-#define GPIO0B_I2S_8CH_SDO3 1
-#define GPIO0B_GPIO0B6 0
-#define GPIO0B_I2S_8CH_SDO2 1
-#define GPIO0B_GPIO0B5 0
-#define GPIO0B_I2S_8CH_SDO1 1
-#define GPIO0B_GPIO0B4 0
-#define GPIO0B_I2S_8CH_SDO0 1
-#define GPIO0B_GPIO0B3 0
-#define GPIO0B_I2S_8CH_LRCK_TX 1
-#define GPIO0B_GPIO0B2 0
-#define GPIO0B_I2S_8CH_LRCK_RX 1
-#define GPIO0B_GPIO0B1 0
-#define GPIO0B_I2S_8CH_SCLK 1
-#define GPIO0B_GPIO0B0 0
-#define GPIO0B_I2S_8CH_CLK 1
-
-
-//GPIO0C
-#define GPIO0C_GPIO0C7 0
-#define GPIO0C_TRACE_CTL 1
-#define GPIO0C_SMC_ADDR3 2
-#define GPIO0C_GPIO0C6 0
-#define GPIO0C_TRACE_CLK 1
-#define GPIO0C_SMC_ADDR2 2
-#define GPIO0C_GPIO0C5 0
-#define GPIO0C_I2S1_2CH_SDO 1
-#define GPIO0C_GPIO0C4 0
-#define GPIO0C_I2S1_2CH_SDI 1
-#define GPIO0C_GPIO0C3 0
-#define GPIO0C_I2S1_2CH_LRCK_TX 1
-#define GPIO0C_GPIO0C2 0
-#define GPIO0C_I2S1_2CH_LRCK_RX 1
-#define GPIO0C_GPIO0C1 0
-#define GPIO0C_I2S1_2CH_SCLK 1
-#define GPIO0C_GPIO0C0 0
-#define GPIO0C_I2S1_2CH_CLK 1
-
-
-
-//GPIO0D
-#define GPIO0D_GPIO0D7 0
-#define GPIO0D_PWM3 1
-#define GPIO0D_GPIO0D6 0
-#define GPIO0D_PWM2 1
-#define GPIO0D_GPIO0D5 0
-#define GPIO0D_I2S2_2CH_SDO 1
-#define GPIO0D_SMC_ADDR1 2
-#define GPIO0D_GPIO0D4 0
-#define GPIO0D_I2S2_2CH_SDI 1
-#define GPIO0D_SMC_ADDR0 2
-#define GPIO0D_GPIO0D3 0
-#define GPIO0D_I2S2_2CH_LRCK_TX 1
-#define GPIO0D_SMC_ADV_N 2
-#define GPIO0D_GPIO0D2 0
-#define GPIO0D_I2S2_2CH_LRCK_RX 1
-#define GPIO0D_SMC_OE_N 2
-#define GPIO0D_GPIO0D1 0
-#define GPIO0D_I2S2_2CH_SCLK 1
-#define GPIO0D_SMC_WE_N 2
-#define GPIO0D_GPIO0D0 0
-#define GPIO0D_I2S2_2CH_CLK 1
-#define GPIO0D_SMC_CSN0 2
-
-
-//GPIO1A
-#define GPIO1A_GPIO1A7 0
-#define GPIO1A_UART1_RTS_N 1
-#define GPIO1A_SPI0_TXD 2
-#define GPIO1A_GPIO1A6 0
-#define GPIO1A_UART1_CTS_N 1
-#define GPIO1A_SPI0_RXD 2
-#define GPIO1A_GPIO1A5 0
-#define GPIO1A_UART1_SOUT 1
-#define GPIO1A_SPI0_CLK 2
-#define GPIO1A_GPIO1A4 0
-#define GPIO1A_UART1_SIN 1
-#define GPIO1A_SPI0_CSN0 2
-#define GPIO1A_GPIO1A3 0
-#define GPIO1A_UART0_RTS_N 1
-#define GPIO1A_GPIO1A2 0
-#define GPIO1A_UART0_CTS_N 1
-#define GPIO1A_GPIO1A1 0
-#define GPIO1A_UART0_SOUT 1
-#define GPIO1A_GPIO1A0 0
-#define GPIO1A_UART0_SIN 1
-
-
-//GPIO1B
-#define GPIO1B_GPIO1B7 0
-#define GPIO1B_CIF_DATA11 1
-#define GPIO1B_GPIO1B6 0
-#define GPIO1B_CIF_DATA10 1
-#define GPIO1B_GPIO1B5 0
-#define GPIO1B_CIF0_DATA1 1
-#define GPIO1B_GPIO1B4 0
-#define GPIO1B_CIF0_DATA0 1
-#define GPIO1B_GPIO1B3 0
-#define GPIO1B_CIF0_CLKOUT 1
-#define GPIO1B_GPIO1B2 0
-#define GPIO1B_SPDIF_TX 1
-#define GPIO1B_GPIO1B1 0
-#define GPIO1B_UART2_SOUT 1
-#define GPIO1B_GPIO1B0 0
-#define GPIO1B_UART2_SIN 1
-
-
-//GPIO1C
-#define GPIO1C_GPIO1C7 0
-#define GPIO1C_CIF_DATA9 1
-#define GPIO1C_RMII_RXD0 2
-#define GPIO1C_GPIO1C6 0
-#define GPIO1C_CIF_DATA8 1
-#define GPIO1C_RMII_RXD1 2
-#define GPIO1C_GPIO1C5 0
-#define GPIO1C_CIF_DATA7 1
-#define GPIO1C_RMII_CRS_DVALID 2
-#define GPIO1C_GPIO1C4 0
-#define GPIO1C_CIF_DATA6 1
-#define GPIO1C_RMII_RX_ERR 2
-#define GPIO1C_GPIO1C3 0
-#define GPIO1C_CIF_DATA5 1
-#define GPIO1C_RMII_TXD0 2
-#define GPIO1C_GPIO1C2 0
-#define GPIO1C_CIF1_DATA4 1
-#define GPIO1C_RMII_TXD1 2
-#define GPIO1C_GPIO1C1 0
-#define GPIO1C_CIF_DATA3 1
-#define GPIO1C_RMII_TX_EN 2
-#define GPIO1C_GPIO1C0 0
-#define GPIO1C_CIF1_DATA2 1
-#define GPIO1C_RMII_CLKOUT 2
-#define GPIO1C_RMII_CLKIN 3
-
-
-//GPIO1D
-#define GPIO1D_GPIO1D7 0
-#define GPIO1D_CIF1_CLKOUT 1
-#define GPIO1D_GPIO1D6 0
-#define GPIO1D_CIF1_DATA11 1
-#define GPIO1D_GPIO1D5 0
-#define GPIO1D_CIF1_DATA10 1
-#define GPIO1D_GPIO1D4 0
-#define GPIO1D_CIF1_DATA1 1
-#define GPIO1D_GPIO1D3 0
-#define GPIO1D_CIF1_DATA0 1
-#define GPIO1D_GPIO1D2 0
-#define GPIO1D_CIF1_CLKIN 1
-#define GPIO1D_GPIO1D1 0
-#define GPIO1D_CIF1_HREF 1
-#define GPIO1D_MII_MDCLK 2
-#define GPIO1D_GPIO1D0 0
-#define GPIO1D_CIF1_VSYNC 1
-#define GPIO1D_MII_MD 2
-
-
-//GPIO2A
-#define GPIO2A_GPIO2A7 0
-#define GPIO2A_LCDC1_DATA7 1
-#define GPIO2A_SMC_ADDR11 2
-#define GPIO2A_GPIO2A6 0
-#define GPIO2A_LCDC1_DATA6 1
-#define GPIO2A_SMC_ADDR10 2
-#define GPIO2A_GPIO2A5 0
-#define GPIO2A_LCDC1_DATA5 1
-#define GPIO2A_SMC_ADDR9 2
-#define GPIO2A_GPIO2A4 0
-#define GPIO2A_LCDC1_DATA4 1
-#define GPIO2A_SMC_ADDR8 2
-#define GPIO2A_GPIO2A3 0
-#define GPIO2A_LCDC_DATA3 1
-#define GPIO2A_SMC_ADDR7 2
-#define GPIO2A_GPIO2A2 0
-#define GPIO2A_LCDC_DATA2 1
-#define GPIO2A_SMC_ADDR6 2
-#define GPIO2A_GPIO2A1 0
-#define GPIO2A_LCDC1_DATA1 1
-#define GPIO2A_SMC_ADDR5 2
-#define GPIO2A_GPIO2A0 0
-#define GPIO2A_LCDC1_DATA0 1
-#define GPIO2A_SMC_ADDR4 2
-
-
-//GPIO2B
-#define GPIO2B_GPIO2B7 0
-#define GPIO2B_LCDC1_DATA15 1
-#define GPIO2B_SMC_ADDR19 2
-#define GPIO2B_HSADC_DATA7 3
-#define GPIO2B_GPIO2B6 0
-#define GPIO2B_LCDC1_DATA14 1
-#define GPIO2B_SMC_ADDR18 2
-#define GPIO2B_TS_SYNC 3
-#define GPIO2B_GPIO2B5 0
-#define GPIO2B_LCDC1_DATA13 1
-#define GPIO2B_SMC_ADDR17 2
-#define GPIO2B_HSADC_DATA8 3
-#define GPIO2B_GPIO2B4 0
-#define GPIO2B_LCDC1_DATA12 1
-#define GPIO2B_SMC_ADDR16 2
-#define GPIO2B_HSADC_DATA9 3
-#define GPIO2B_GPIO2B3 0
-#define GPIO2B_LCDC1_DATA11 1
-#define GPIO2B_SMC_ADDR15 2
-#define GPIO2B_GPIO2B2 0
-#define GPIO2B_LCDC1_DATA10 1
-#define GPIO2B_SMC_ADDR14 2
-#define GPIO2B_GPIO2B1 0
-#define GPIO2B_LCDC1_DATA9 1
-#define GPIO2B_SMC_ADDR13 2
-#define GPIO2B_GPIO2B0 0
-#define GPIO2B_LCDC1_DATA8 1
-#define GPIO2B_SMC_ADDR12 2
-
-
-//GPIO2C
-#define GPIO2C_GPIO2C7 0
-#define GPIO2C_LCDC1_DATA23 1
-#define GPIO2C_SPI1_CSN1 2
-#define GPIO2C_HSADC_DATA4 3
-#define GPIO2C_GPIO2C6 0
-#define GPIO2C_LCDC1_DATA22 1
-#define GPIO2C_SPI1_RXD 2
-#define GPIO2C_HSADC_DATA3 3
-#define GPIO2C_GPIO2C5 0
-#define GPIO2C_LCDC1_DATA21 1
-#define GPIO2C_SPI1_TXD 2
-#define GPIO2C_HSADC_DATA2 3
-#define GPIO2C_GPIO2C4 0
-#define GPIO2C_LCDC1_DATA20 1
-#define GPIO2C_SPI1_CSN0 2
-#define GPIO2C_HSADC_DATA1 3
-#define GPIO2C_GPIO2C3 0
-#define GPIO2C_LCDC1_DATA19 1
-#define GPIO2C_SPI1_CLK 2
-#define GPIO2C_HSADC_DATA0 3
-#define GPIO2C_GPIO2C2 0
-#define GPIO2C_LCDC1_DATA18 1
-#define GPIO2C_SMC_BLS_N1 2
-#define GPIO2C_HSADC_DATA5 3
-#define GPIO2C_GPIO2C1 0
-#define GPIO2C_LCDC1_DATA17 1
-#define GPIO2C_SMC_BLS_N0 2
-#define GPIO2C_HSADC_DATA6 3
-#define GPIO2C_GPIO2C0 0
-#define GPIO2C_LCDC_DATA16 1
-#define GPIO2C_GPS_CLK 2
-#define GPIO2C_HSADC_CLKOUT 3
-
-
-//GPIO2D
-#define GPIO2D_GPIO2D7 0
-#define GPIO2D_I2C1_SCL 1
-#define GPIO2D_GPIO2D6 0
-#define GPIO2D_I2C1_SDA 1
-#define GPIO2D_GPIO2D5 0
-#define GPIO2D_I2C0_SCL 1
-#define GPIO2D_GPIO2D4 0
-#define GPIO2D_I2C0_SDA 1
-#define GPIO2D_GPIO2D3 0
-#define GPIO2D_LCDC1_VSYNC 1
-#define GPIO2D_GPIO2D2 0
-#define GPIO2D_LCDC1_HSYNC 1
-#define GPIO2D_GPIO2D1 0
-#define GPIO2D_LCDC1_DEN 1
-#define GPIO2D_SMC_CSN1 2
-#define GPIO2D_GPIO2D0 0
-#define GPIO2D_LCDC1_DCLK 1
-
-
-//GPIO3A
-#define GPIO3A_GPIO3A7 0
-#define GPIO3A_SDMMC0_PWR_EN 1 //#define GPIO3A_SDMMC0_WRITE_PRT 1 //Modifyed by xbw,at 2012-03-05
-#define GPIO3A_GPIO3A6 0
-#define GPIO3A_SDMMC0_RSTN_OUT 1
-#define GPIO3A_GPIO3A5 0
-#define GPIO3A_I2C4_SCL 1
-#define GPIO3A_GPIO3A4 0
-#define GPIO3A_I2C4_SDA 1
-#define GPIO3A_GPIO3A3 0
-#define GPIO3A_I2C3_SCL 1
-#define GPIO3A_GPIO3A2 0
-#define GPIO3A_I2C3_SDA 1
-#define GPIO3A_GPIO3A1 0
-#define GPIO3A_I2C2_SCL 1
-#define GPIO3A_GPIO3A0 0
-#define GPIO3A_I2C2_SDA 1
-
-
-//GPIO3B
-#define GPIO3B_GPIO3B7 0
-#define GPIO3B_SDMMC0_WRITE_PRT 1
-#define GPIO3B_GPIO3B6 0
-#define GPIO3B_SDMMC0_DETECT_N 1
-#define GPIO3B_GPIO3B5 0
-#define GPIO3B_SDMMC0_DATA3 1
-#define GPIO3B_GPIO3B4 0
-#define GPIO3B_SDMMC0_DATA2 1
-#define GPIO3B_GPIO3B3 0
-#define GPIO3B_SDMMC0_DATA1 1
-#define GPIO3B_GPIO3B2 0
-#define GPIO3B_SDMMC0_DATA0 1
-#define GPIO3B_GPIO3B1 0
-#define GPIO3B_SDMMC0_CMD 1
-#define GPIO3B_GPIO3B0 0
-#define GPIO3B_SDMMC0_CLKOUT 1
-
-
-//GPIO3C
-#define GPIO3C_GPIO3C7 0
-#define GPIO3C_SDMMC1_WRITE_PRT 1
-#define GPIO3C_GPIO3C6 0
-#define GPIO3C_SDMMC1_DETECT_N 1
-#define GPIO3C_GPIO3C5 0
-#define GPIO3C_SDMMC1_CLKOUT 1
-#define GPIO3C_GPIO3C4 0
-#define GPIO3C_SDMMC1_DATA3 1
-#define GPIO3C_GPIO3C3 0
-#define GPIO3C_SDMMC1_DATA2 1
-#define GPIO3C_GPIO3C2 0
-#define GPIO3C_SDMMC1_DATA1 1
-#define GPIO3C_GPIO3C1 0
-#define GPIO3C_SDMMC1_DATA0 1
-#define GPIO3C_GPIO3C0 0
-#define GPIO3C_SMMC1_CMD 1
-
-
-//GPIO3D
-#define GPIO3D_GPIO3D7 0
-#define GPIO3D_FLASH_DQS 1
-#define GPIO3D_EMMC_CLKOUT 2
-#define GPIO3D_GPIO3D6 0
-#define GPIO3D_UART3_RTS_N 1
-#define GPIO3D_GPIO3D5 0
-#define GPIO3D_UART3_CTS_N 1
-#define GPIO3D_GPIO3D4 0
-#define GPIO3D_UART3_SOUT 1
-#define GPIO3D_GPIO3D3 0
-#define GPIO3D_UART3_SIN 1
-#define GPIO3D_GPIO3D2 0
-#define GPIO3D_SDMMC1_INT_N 1
-#define GPIO3D_GPIO3D1 0
-#define GPIO3D_SDMMC1_BACKEND_PWR 1
-#define GPIO3D_GPIO3D0 0
-#define GPIO3D_SDMMC1_PWR_EN 1
-
-
-//GPIO4A
-#define GPIO4A_GPIO4A7 0
-#define GPIO4A_FLASH_DATA15 1
-#define GPIO4A_GPIO4A6 0
-#define GPIO4A_FLASH_DATA14 1
-#define GPIO4A_GPIO4A5 0
-#define GPIO4A_FLASH_DATA13 1
-#define GPIO4A_GPIO4A4 0
-#define GPIO4A_FLASH_DATA12 1
-#define GPIO4A_GPIO4A3 0
-#define GPIO4A_FLASH_DATA11 1
-#define GPIO4A_GPIO4A2 0
-#define GPIO4A_FLASH_DATA10 1
-#define GPIO4A_GPIO4A1 0
-#define GPIO4A_FLASH_DATA9 1
-#define GPIO4A_GPIO4A0 0
-#define GPIO4A_FLASH_DATA8 1
-
-
-//GPIO4B
-#define GPIO4B_GPIO4B7 0
-#define GPIO4B_SPI0_CSN1 1
-#define GPIO4B_GPIO4B6 0
-#define GPIO4B_FLASH_CSN7 1
-#define GPIO4B_GPIO4B5 0
-#define GPIO4B_FLASH_CSN6 1
-#define GPIO4B_GPIO4B4 0
-#define GPIO4B_FLASH_CSN5 1
-#define GPIO4B_GPIO4B3 0
-#define GPIO4B_FLASH_CSN4 1
-#define GPIO4B_GPIO4B2 0
-#define GPIO4B_FLASH_CSN3 1
-#define GPIO4B_EMMC_RSTN_OUT 2
-#define GPIO4B_GPIO4B1 0
-#define GPIO4B_FLASH_CSN2 1
-#define GPIO4B_EMMC_CMD 2
-#define GPIO4B_GPIO4B0 0
-#define GPIO4B_FLASH_CSN1 1
-
-
-//GPIO4C
-#define GPIO4C_GPIO4C7 0
-#define GPIO4C_SMC_DATA7 1
-#define GPIO4C_TRACE_DATA7 2
-#define GPIO4C_GPIO4C6 0
-#define GPIO4C_SMC_DATA6 1
-#define GPIO4C_TRACE_DATA6 2
-#define GPIO4C_GPIO4C5 0
-#define GPIO4C_SMC_DATA5 1
-#define GPIO4C_TRACE_DATA5 2
-#define GPIO4C_GPIO4C4 0
-#define GPIO4C_SMC_DATA4 1
-#define GPIO4C_TRACE_DATA4 2
-#define GPIO4C_GPIO4C3 0
-#define GPIO4C_SMC_DATA3 1
-#define GPIO4C_TRACE_DATA3 2
-#define GPIO4C_GPIO4C2 0
-#define GPIO4C_SMC_DATA2 1
-#define GPIO4C_TRACE_DATA2 2
-#define GPIO4C_GPIO4C1 0
-#define GPIO4C_SMC_DATA1 1
-#define GPIO4C_TRACE_DATA1 2
-#define GPIO4C_GPIO4C0 0
-#define GPIO4C_SMC_DATA0 1
-#define GPIO4C_TRACE_DATA0 2
-
-
-//GPIO4D
-#define GPIO4D_GPIO4D7 0
-#define GPIO4D_SMC_DATA15 1
-#define GPIO4D_TRACE_DATA15 2
-#define GPIO4D_GPIO4D6 0
-#define GPIO4D_SMC_DATA14 1
-#define GPIO4D_TRACE_DATA14 2
-#define GPIO4D_GPIO4D5 0
-#define GPIO4D_SMC_DATA13 1
-#define GPIO4D_TRACE_DATA13 2
-#define GPIO4D_GPIO4D4 0
-#define GPIO4D_SMC_DATA12 1
-#define GPIO4D_TRACE_DATA12 2
-#define GPIO4D_GPIO4D3 0
-#define GPIO4D_SMC_DATA11 1
-#define GPIO4D_TRACE_DATA11 2
-#define GPIO4D_GPIO4D2 0
-#define GPIO4D_SMC_DATA10 1
-#define GPIO4D_TRACE_DATA10 2
-#define GPIO4D_GPIO4D1 0
-#define GPIO4D_SMC_DATA9 1
-#define GPIO4D_TRACE_DATA9 2
-#define GPIO4D_GPIO4D0 0
-#define GPIO4D_SMC_DATA8 1
-#define GPIO4D_TRACE_DATA8 2
-
-
-//GPIO6B
-#define GPIO6B_GPIO6B7 0
-#define GPIO6B_TEST_CLOCK_OUT 1
-
-#define GRF_GPIO0L_DIR 0x0000
-#define GRF_GPIO0H_DIR 0x0004
-#define GRF_GPIO1L_DIR 0x0008
-#define GRF_GPIO1H_DIR 0x000c
-#define GRF_GPIO2L_DIR 0x0010
-#define GRF_GPIO2H_DIR 0x0014
-#define GRF_GPIO3L_DIR 0x0018
-#define GRF_GPIO3H_DIR 0x001c
-#define GRF_GPIO4L_DIR 0x0020
-#define GRF_GPIO4H_DIR 0x0024
-#define GRF_GPIO6L_DIR 0x0030
-#define GRF_GPIO0L_DO 0x0038
-#define GRF_GPIO0H_DO 0x003c
-#define GRF_GPIO1L_DO 0x0040
-#define GRF_GPIO1H_DO 0x0044
-#define GRF_GPIO2L_DO 0x0048
-#define GRF_GPIO2H_DO 0x004c
-#define GRF_GPIO3L_DO 0x0050
-#define GRF_GPIO3H_DO 0x0054
-#define GRF_GPIO4L_DO 0x0058
-#define GRF_GPIO4H_DO 0x005c
-#define GRF_GPIO6L_DO 0x0068
-#define GRF_GPIO0L_EN 0x0070
-#define GRF_GPIO0H_EN 0x0074
-#define GRF_GPIO1L_EN 0x0078
-#define GRF_GPIO1H_EN 0x007c
-#define GRF_GPIO2L_EN 0x0080
-#define GRF_GPIO2H_EN 0x0084
-#define GRF_GPIO3L_EN 0x0088
-#define GRF_GPIO3H_EN 0x008c
-#define GRF_GPIO4L_EN 0x0090
-#define GRF_GPIO4H_EN 0x0094
-#define GRF_GPIO6L_EN 0x00a0
-#define GRF_GPIO0A_IOMUX RK30_GRF_BASE+0x00a8
-#define GRF_GPIO0B_IOMUX RK30_GRF_BASE+0x00ac
-#define GRF_GPIO0C_IOMUX RK30_GRF_BASE+0x00b0
-#define GRF_GPIO0D_IOMUX RK30_GRF_BASE+0x00b4
-#define GRF_GPIO1A_IOMUX RK30_GRF_BASE+0x00b8
-#define GRF_GPIO1B_IOMUX RK30_GRF_BASE+0x00bc
-#define GRF_GPIO1C_IOMUX RK30_GRF_BASE+0x00c0
-#define GRF_GPIO1D_IOMUX RK30_GRF_BASE+0x00c4
-#define GRF_GPIO2A_IOMUX RK30_GRF_BASE+0x00c8
-#define GRF_GPIO2B_IOMUX RK30_GRF_BASE+0x00cc
-#define GRF_GPIO2C_IOMUX RK30_GRF_BASE+0x00d0
-#define GRF_GPIO2D_IOMUX RK30_GRF_BASE+0x00d4
-#define GRF_GPIO3A_IOMUX RK30_GRF_BASE+0x00d8
-#define GRF_GPIO3B_IOMUX RK30_GRF_BASE+0x00dc
-#define GRF_GPIO3C_IOMUX RK30_GRF_BASE+0x00e0
-#define GRF_GPIO3D_IOMUX RK30_GRF_BASE+0x00e4
-#define GRF_GPIO4A_IOMUX RK30_GRF_BASE+0x00e8
-#define GRF_GPIO4B_IOMUX RK30_GRF_BASE+0x00ec
-#define GRF_GPIO4C_IOMUX RK30_GRF_BASE+0x00f0
-#define GRF_GPIO4D_IOMUX RK30_GRF_BASE+0x00f4
-#define GRF_GPIO6B_IOMUX RK30_GRF_BASE+0x010c
-#define GRF_GPIO0L_PULL 0x0118
-#define GRF_GPIO0H_PULL 0x011c
-#define GRF_GPIO1L_PULL 0x0120
-#define GRF_GPIO1H_PULL 0x0124
-#define GRF_GPIO2L_PULL 0x0128
-#define GRF_GPIO2H_PULL 0x012c
-#define GRF_GPIO3L_PULL 0x0130
-#define GRF_GPIO3H_PULL 0x0134
-#define GRF_GPIO4L_PULL 0x0138
-#define GRF_GPIO4H_PULL 0x013c
-#define GRF_GPIO6L_PULL 0x0148
-#define GRF_SOC_CON0 0x0150
-#define GRF_SOC_CON1 0x0154
-#define GRF_SOC_CON2 0x0158
-#define GRF_SOC_STATUS0 0x015c
-#define GRF_DMAC1_CON0 0x0160
-#define GRF_DMAC1_CON1 0x0164
-#define GRF_DMAC1_CON2 0x0168
-#define GRF_DMAC2_CON0 0x016c
-#define GRF_DMAC2_CON1 0x0170
-#define GRF_DMAC2_CON2 0x0174
-#define GRF_DMAC2_CON3 0x0178
-#define GRF_UOC0_CON0 0x017c
-#define GRF_UOC0_CON1 0x0180
-#define GRF_UOC0_CON2 0x0184
-#define GRF_UOC1_CON0 0x0188
-#define GRF_UOC1_CON1 0x018c
-#define GRF_UOC1_CON2 0x0190
-#define GRF_UOC1_CON3 0x0194
-#define GRF_DDRC_CON0 0x0198
-#define GRF_DDRC_STAT 0x019c
-#define GRF_OS_REG0 0x01c8
-#define GRF_OS_REG1 0x01cc
-#define GRF_OS_REG2 0x01d0
-#define GRF_OS_REG3 0x01d4
-
-
-//GPIO0A
-#define GPIO0A7_I2S8CHSDI_NAME "gpio0a7_i2s8chsdi_name"
-#define GPIO0A6_HOSTDRVVBUS_NAME "gpio0a6_hostdrvvbus_name"
-#define GPIO0A5_OTGDRVVBUS_NAME "gpio0a5_otgdrvvbus_name"
-#define GPIO0A4_PWM1_NAME "gpio0a4_pwm1_name"
-#define GPIO0A3_PWM0_NAME "gpio0a3_pwm0_name"
-#define GPIO0A2_HDMII2CSDA_NAME "gpio0a2_hdmii2csda_name"
-#define GPIO0A1_HDMII2CSCL_NAME "gpio0a1_hdmii2cscl_name"
-#define GPIO0A0_HDMIHOTPLUGIN_NAME "gpio0a0_hdmihotplugin_name"
-
-
-//GPIO0B
-#define GPIO0B7_I2S8CHSDO3_NAME "gpio0b7_i2s8chsdo3_name"
-#define GPIO0B6_I2S8CHSDO2_NAME "gpio0b6_i2s8chsdo2_name"
-#define GPIO0B5_I2S8CHSDO1_NAME "gpio0b5_i2s8chsdo1_name"
-#define GPIO0B4_I2S8CHSDO0_NAME "gpio0b4_i2s8chsdo0_name"
-#define GPIO0B3_I2S8CHLRCKTX_NAME "gpio0b3_i2s8chlrcktx_name"
-#define GPIO0B2_I2S8CHLRCKRX_NAME "gpio0b2_i2s8chlrckrx_name"
-#define GPIO0B1_I2S8CHSCLK_NAME "gpio0b1_i2s8chsclk_name"
-#define GPIO0B0_I2S8CHCLK_NAME "gpio0b0_i2s8chclk_name"
-
-
-//GPIO0C
-#define GPIO0C7_TRACECTL_SMCADDR3_NAME "gpio0c7_tracectl_smcaddr3_name"
-#define GPIO0C6_TRACECLK_SMCADDR2_NAME "gpio0c6_traceclk_smcaddr2_name"
-#define GPIO0C5_I2S12CHSDO_NAME "gpio0c5_i2s12chsdo_name"
-#define GPIO0C4_I2S12CHSDI_NAME "gpio0c4_i2s12chsdi_name"
-#define GPIO0C3_I2S12CHLRCKTX_NAME "gpio0c3_i2s12chlrcktx_name"
-#define GPIO0C2_I2S12CHLRCKRX_NAME "gpio0c2_i2s12chlrckrx_name"
-#define GPIO0C1_I2S12CHSCLK_NAME "gpio0c1_i2s12chsclk_name"
-#define GPIO0C0_I2S12CHCLK_NAME "gpio0c0_i2s12chclk_name"
-
-
-//GPIO0D
-#define GPIO0D7_PWM3_NAME "gpio0d7_pwm3_name"
-#define GPIO0D6_PWM2_NAME "gpio0d6_pwm2_name"
-#define GPIO0D5_I2S22CHSDO_SMCADDR1_NAME "gpio0d5_i2s22chsdo_smcaddr1_name"
-#define GPIO0D4_I2S22CHSDI_SMCADDR0_NAME "gpio0d4_i2s22chsdi_smcaddr0_name"
-#define GPIO0D3_I2S22CHLRCKTX_SMCADVN_NAME "gpio0d3_i2s22chlrcktx_smcadvn_name"
-#define GPIO0D2_I2S22CHLRCKRX_SMCOEN_NAME "gpio0d2_i2s22chlrckrx_smcoen_name"
-#define GPIO0D1_I2S22CHSCLK_SMCWEN_NAME "gpio0d1_i2s22chsclk_smcwen_name"
-#define GPIO0D0_I2S22CHCLK_SMCCSN0_NAME "gpio0d0_i2s22chclk_smccsn0_name"
-
-
-//GPIO1A
-#define GPIO1A7_UART1RTSN_SPI0TXD_NAME "gpio1a7_uart1rtsn_spi0txd_name"
-#define GPIO1A6_UART1CTSN_SPI0RXD_NAME "gpio1a6_uart1ctsn_spi0rxd_name"
-#define GPIO1A5_UART1SOUT_SPI0CLK_NAME "gpio1a5_uart1sout_spi0clk_name"
-#define GPIO1A4_UART1SIN_SPI0CSN0_NAME "gpio1a4_uart1sin_spi0csn0_name"
-#define GPIO1A3_UART0RTSN_NAME "gpio1a3_uart0rtsn_name"
-#define GPIO1A2_UART0CTSN_NAME "gpio1a2_uart0ctsn_name"
-#define GPIO1A1_UART0SOUT_NAME "gpio1a1_uart0sout_name"
-#define GPIO1A0_UART0SIN_NAME "gpio1a0_uart0sin_name"
-
-
-
-//GPIO1B
-#define GPIO1B7_CIFDATA11_NAME "gpio1b7_cifdata11_name"
-#define GPIO1B6_CIFDATA10_NAME "gpio1b6_cifdata10_name"
-#define GPIO1B5_CIF0DATA1_NAME "gpio1b5_cif0data1_name"
-#define GPIO1B4_CIF0DATA0_NAME "gpio1b4_cif0data0_name"
-#define GPIO1B3_CIF0CLKOUT_NAME "gpio1b3_cif0clkout_name"
-#define GPIO1B2_SPDIFTX_NAME "gpio1b2_spdiftx_name"
-#define GPIO1B1_UART2SOUT_NAME "gpio1b1_uart2sout_name"
-#define GPIO1B0_UART2SIN_NAME "gpio1b0_uart2sin_name"
-
-
-//GPIO1C
-#define GPIO1C7_CIFDATA9_RMIIRXD0_NAME "gpio1c7_cifdata9_rmiirxd0_name"
-#define GPIO1C6_CIFDATA8_RMIIRXD1_NAME "gpio1c6_cifdata8_rmiirxd1_name"
-#define GPIO1C5_CIFDATA7_RMIICRSDVALID_NAME "gpio1c5_cifdata7_rmiicrsdvalid_name"
-#define GPIO1C4_CIFDATA6_RMIIRXERR_NAME "gpio1c4_cifdata6_rmiirxerr_name"
-#define GPIO1C3_CIFDATA5_RMIITXD0_NAME "gpio1c3_cifdata5_rmiitxd0_name"
-#define GPIO1C2_CIF1DATA4_RMIITXD1_NAME "gpio1c2_cif1data4_rmiitxd1_name"
-#define GPIO1C1_CIFDATA3_RMIITXEN_NAME "gpio1c1_cifdata3_rmiitxen_name"
-#define GPIO1C0_CIF1DATA2_RMIICLKOUT_RMIICLKIN_NAME "gpio1c0_cif1data2_rmiiclkout_rmiiclkin_name"
-
-
-//GPIO1D
-#define GPIO1D7_CIF1CLKOUT_NAME "gpio1d7_cif1clkout_name"
-#define GPIO1D6_CIF1DATA11_NAME "gpio1d6_cif1data11_name"
-#define GPIO1D5_CIF1DATA10_NAME "gpio1d5_cif1data10_name"
-#define GPIO1D4_CIF1DATA1_NAME "gpio1d4_cif1data1_name"
-#define GPIO1D3_CIF1DATA0_NAME "gpio1d3_cif1data0_name"
-#define GPIO1D2_CIF1CLKIN_NAME "gpio1d2_cif1clkin_name"
-#define GPIO1D1_CIF1HREF_MIIMDCLK_NAME "gpio1d1_cif1href_miimdclk_name"
-#define GPIO1D0_CIF1VSYNC_MIIMD_NAME "gpio1d0_cif1vsync_miimd_name"
-
-
-//GPIO2A
-#define GPIO2A7_LCDC1DATA7_SMCADDR11_NAME "gpio2a7_lcdc1data7_smcaddr11_name"
-#define GPIO2A6_LCDC1DATA6_SMCADDR10_NAME "gpio2a6_lcdc1data6_smcaddr10_name"
-#define GPIO2A5_LCDC1DATA5_SMCADDR9_NAME "gpio2a5_lcdc1data5_smcaddr9_name"
-#define GPIO2A4_LCDC1DATA4_SMCADDR8_NAME "gpio2a4_lcdc1data4_smcaddr8_name"
-#define GPIO2A3_LCDCDATA3_SMCADDR7_NAME "gpio2a3_lcdcdata3_smcaddr7_name"
-#define GPIO2A2_LCDCDATA2_SMCADDR6_NAME "gpio2a2_lcdcdata2_smcaddr6_name"
-#define GPIO2A1_LCDC1DATA1_SMCADDR5_NAME "gpio2a1_lcdc1data1_smcaddr5_name"
-#define GPIO2A0_LCDC1DATA0_SMCADDR4_NAME "gpio2a0_lcdc1data0_smcaddr4_name"
-
-
-//GPIO2B
-#define GPIO2B7_LCDC1DATA15_SMCADDR19_HSADCDATA7_NAME "gpio2b7_lcdc1data15_smcaddr19_hsadcdata7_name"
-#define GPIO2B6_LCDC1DATA14_SMCADDR18_TSSYNC_NAME "gpio2b6_lcdc1data14_smcaddr18_tssync_name"
-#define GPIO2B5_LCDC1DATA13_SMCADDR17_HSADCDATA8_NAME "gpio2b5_lcdc1data13_smcaddr17_hsadcdata8_name"
-#define GPIO2B4_LCDC1DATA12_SMCADDR16_HSADCDATA9_NAME "gpio2b4_lcdc1data12_smcaddr16_hsadcdata9_name"
-#define GPIO2B3_LCDC1DATA11_SMCADDR15_NAME "gpio2b3_lcdc1data11_smcaddr15_name"
-#define GPIO2B2_LCDC1DATA10_SMCADDR14_NAME "gpio2b2_lcdc1data10_smcaddr14_name"
-#define GPIO2B1_LCDC1DATA9_SMCADDR13_NAME "gpio2b1_lcdc1data9_smcaddr13_name"
-#define GPIO2B0_LCDC1DATA8_SMCADDR12_NAME "gpio2b0_lcdc1data8_smcaddr12_name"
-
-
-//GPIO2C
-#define GPIO2C7_LCDC1DATA23_SPI1CSN1_HSADCDATA4_NAME "gpio2c7_lcdc1data23_spi1csn1_hsadcdata4_name"
-#define GPIO2C6_LCDC1DATA22_SPI1RXD_HSADCDATA3_NAME "gpio2c6_lcdc1data22_spi1rxd_hsadcdata3_name"
-#define GPIO2C5_LCDC1DATA21_SPI1TXD_HSADCDATA2_NAME "gpio2c5_lcdc1data21_spi1txd_hsadcdata2_name"
-#define GPIO2C4_LCDC1DATA20_SPI1CSN0_HSADCDATA1_NAME "gpio2c4_lcdc1data20_spi1csn0_hsadcdata1_name"
-#define GPIO2C3_LCDC1DATA19_SPI1CLK_HSADCDATA0_NAME "gpio2c3_lcdc1data19_spi1clk_hsadcdata0_name"
-#define GPIO2C2_LCDC1DATA18_SMCBLSN1_HSADCDATA5_NAME "gpio2c2_lcdc1data18_smcblsn1_hsadcdata5_name"
-#define GPIO2C1_LCDC1DATA17_SMCBLSN0_HSADCDATA6_NAME "gpio2c1_lcdc1data17_smcblsn0_hsadcdata6_name"
-#define GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME "gpio2c0_lcdcdata16_gpsclk_hsadcclkout_name"
-
-
-//GPIO2D
-#define GPIO2D7_I2C1SCL_NAME "gpio2d7_i2c1scl_name"
-#define GPIO2D6_I2C1SDA_NAME "gpio2d6_i2c1sda_name"
-#define GPIO2D5_I2C0SCL_NAME "gpio2d5_i2c0scl_name"
-#define GPIO2D4_I2C0SDA_NAME "gpio2d4_i2c0sda_name"
-#define GPIO2D3_LCDC1VSYNC_NAME "gpio2d3_lcdc1vsync_name"
-#define GPIO2D2_LCDC1HSYNC_NAME "gpio2d2_lcdc1hsync_name"
-#define GPIO2D1_LCDC1DEN_SMCCSN1_NAME "gpio2d1_lcdc1den_smccsn1_name"
-#define GPIO2D0_LCDC1DCLK_NAME "gpio2d0_lcdc1dclk_name"
-
-
-//GPIO3A
-//#define GPIO3A7_SDMMC0WRITEPRT_NAME "gpio3a7_sdmmc0writeprt_name"
-#define GPIO3A7_SDMMC0PWREN_NAME "gpio3a70_sdmmc0pwren_name" //Modifyed by xbw,at 2012-03-05
-#define GPIO3A6_SDMMC0RSTNOUT_NAME "gpio3a6_sdmmc0rstnout_name"
-#define GPIO3A5_I2C4SCL_NAME "gpio3a5_i2c4scl_name"
-#define GPIO3A4_I2C4SDA_NAME "gpio3a4_i2c4sda_name"
-#define GPIO3A3_I2C3SCL_NAME "gpio3a3_i2c3scl_name"
-#define GPIO3A2_I2C3SDA_NAME "gpio3a2_i2c3sda_name"
-#define GPIO3A1_I2C2SCL_NAME "gpio3a1_i2c2scl_name"
-#define GPIO3A0_I2C2SDA_NAME "gpio3a0_i2c2sda_name"
-
-
-
-//GPIO3B
-#define GPIO3B7_SDMMC0WRITEPRT_NAME "gpio3b7_sdmmc0writeprt_name"
-#define GPIO3B6_SDMMC0DETECTN_NAME "gpio3b6_sdmmc0detectn_name"
-#define GPIO3B5_SDMMC0DATA3_NAME "gpio3b5_sdmmc0data3_name"
-#define GPIO3B4_SDMMC0DATA2_NAME "gpio3b4_sdmmc0data2_name"
-#define GPIO3B3_SDMMC0DATA1_NAME "gpio3b3_sdmmc0data1_name"
-#define GPIO3B2_SDMMC0DATA0_NAME "gpio3b2_sdmmc0data0_name"
-#define GPIO3B1_SDMMC0CMD_NAME "gpio3b1_sdmmc0cmd_name"
-#define GPIO3B0_SDMMC0CLKOUT_NAME "gpio3b0_sdmmc0clkout_name"
-
-
-//GPIO3C
-#define GPIO3C7_SDMMC1WRITEPRT_NAME "gpio3c7_sdmmc1writeprt_name"
-#define GPIO3C6_SDMMC1DETECTN_NAME "gpio3c6_sdmmc1detectn_name"
-#define GPIO3C5_SDMMC1CLKOUT_NAME "gpio3c5_sdmmc1clkout_name"
-#define GPIO3C4_SDMMC1DATA3_NAME "gpio3c4_sdmmc1data3_name"
-#define GPIO3C3_SDMMC1DATA2_NAME "gpio3c3_sdmmc1data2_name"
-#define GPIO3C2_SDMMC1DATA1_NAME "gpio3c2_sdmmc1data1_name"
-#define GPIO3C1_SDMMC1DATA0_NAME "gpio3c1_sdmmc1data0_name"
-#define GPIO3C0_SMMC1CMD_NAME "gpio3c0_smmc1cmd_name"
-
-
-//GPIO3D
-#define GPIO3D7_FLASHDQS_EMMCCLKOUT_NAME "gpio3d7_flashdqs_emmcclkout_name"
-#define GPIO3D6_UART3RTSN_NAME "gpio3d6_uart3rtsn_name"
-#define GPIO3D5_UART3CTSN_NAME "gpio3d5_uart3ctsn_name"
-#define GPIO3D4_UART3SOUT_NAME "gpio3d4_uart3sout_name"
-#define GPIO3D3_UART3SIN_NAME "gpio3d3_uart3sin_name"
-#define GPIO3D2_SDMMC1INTN_NAME "gpio3d2_sdmmc1intn_name"
-#define GPIO3D1_SDMMC1BACKENDPWR_NAME "gpio3d1_sdmmc1backendpwr_name"
-#define GPIO3D0_SDMMC1PWREN_NAME "gpio3d0_sdmmc1pwren_name"
-
-
-//GPIO4A
-#define GPIO4A7_FLASHDATA15_NAME "gpio4a7_flashdata15_name"
-#define GPIO4A6_FLASHDATA14_NAME "gpio4a6_flashdata14_name"
-#define GPIO4A5_FLASHDATA13_NAME "gpio4a5_flashdata13_name"
-#define GPIO4A4_FLASHDATA12_NAME "gpio4a4_flashdata12_name"
-#define GPIO4A3_FLASHDATA11_NAME "gpio4a3_flashdata11_name"
-#define GPIO4A2_FLASHDATA10_NAME "gpio4a2_flashdata10_name"
-#define GPIO4A1_FLASHDATA9_NAME "gpio4a1_flashdata9_name"
-#define GPIO4A0_FLASHDATA8_NAME "gpio4a0_flashdata8_name"
-
-
-//GPIO4B
-#define GPIO4B7_SPI0CSN1_NAME "gpio4b7_spi0csn1_name"
-#define GPIO4B6_FLASHCSN7_NAME "gpio4b6_flashcsn7_name"
-#define GPIO4B5_FLASHCSN6_NAME "gpio4b5_flashcsn6_name"
-#define GPIO4B4_FLASHCSN5_NAME "gpio4b4_flashcsn5_name"
-#define GPIO4B3_FLASHCSN4_NAME "gpio4b3_flashcsn4_name"
-#define GPIO4B2_FLASHCSN3_EMMCRSTNOUT_NAME "gpio4b2_flashcsn3_emmcrstnout_name"
-#define GPIO4B1_FLASHCSN2_EMMCCMD_NAME "gpio4b1_flashcsn2_emmccmd_name"
-#define GPIO4B0_FLASHCSN1_NAME "gpio4b0_flashcsn1_name"
-
-
-//GPIO4C
-#define GPIO4C7_SMCDATA7_TRACEDATA7_NAME "gpio4c7_smcdata7_tracedata7_name"
-#define GPIO4C6_SMCDATA6_TRACEDATA6_NAME "gpio4c6_smcdata6_tracedata6_name"
-#define GPIO4C5_SMCDATA5_TRACEDATA5_NAME "gpio4c5_smcdata5_tracedata5_name"
-#define GPIO4C4_SMCDATA4_TRACEDATA4_NAME "gpio4c4_smcdata4_tracedata4_name"
-#define GPIO4C3_SMCDATA3_TRACEDATA3_NAME "gpio4c3_smcdata3_tracedata3_name"
-#define GPIO4C2_SMCDATA2_TRACEDATA2_NAME "gpio4c2_smcdata2_tracedata2_name"
-#define GPIO4C1_SMCDATA1_TRACEDATA1_NAME "gpio4c1_smcdata1_tracedata1_name"
-#define GPIO4C0_SMCDATA0_TRACEDATA0_NAME "gpio4c0_smcdata0_tracedata0_name"
-
-
-//GPIO4D
-#define GPIO4D7_SMCDATA15_TRACEDATA15_NAME "gpio4d7_smcdata15_tracedata15_name"
-#define GPIO4D6_SMCDATA14_TRACEDATA14_NAME "gpio4d6_smcdata14_tracedata14_name"
-#define GPIO4D5_SMCDATA13_TRACEDATA13_NAME "gpio4d5_smcdata13_tracedata13_name"
-#define GPIO4D4_SMCDATA12_TRACEDATA12_NAME "gpio4d4_smcdata12_tracedata12_name"
-#define GPIO4D3_SMCDATA11_TRACEDATA11_NAME "gpio4d3_smcdata11_tracedata11_name"
-#define GPIO4D2_SMCDATA10_TRACEDATA10_NAME "gpio4d2_smcdata10_tracedata10_name"
-#define GPIO4D1_SMCDATA9_TRACEDATA9_NAME "gpio4d1_smcdata9_tracedata9_name"
-#define GPIO4D0_SMCDATA8_TRACEDATA8_NAME "gpio4d0_smcdata8_tracedata8_name"
-
-
-
-//GPIO6B
-#define GPIO6B7_TESTCLOCKOUT_NAME "gpio6b7_testclockout_name"
-
-#define DEFAULT 0
-#define INITIAL 1
-
-#define MUX_CFG(desc,reg,off,interl,mux_mode,bflags) \
-{ \
- .name = desc, \
- .offset = off, \
- .interleave = interl, \
- .mux_reg = GRF_##reg##_IOMUX, \
- .mode = mux_mode, \
- .premode = mux_mode, \
- .flags = bflags, \
-},
-
-struct mux_config {
- char *name;
- const unsigned int offset;
- unsigned int mode;
- unsigned int premode;
- const void* __iomem mux_reg;
- const unsigned int interleave;
- unsigned int flags;
-};
-#define rk29_mux_api_set rk30_mux_api_set
-
-extern int __init rk30_iomux_init(void);
-extern void rk30_mux_api_set(char *name, unsigned int mode);
-extern int rk30_mux_api_get(char *name);
-
-#endif
-
-#endif
+++ /dev/null
-#ifndef __MACH_IRQS_H
-#define __MACH_IRQS_H
-
-#define FIQ_START 0
-
-#define IRQ_LOCALTIMER 29
-
-#define RK30XX_IRQ(x) (x + 32)
-
-#define IRQ_DMAC1_0 RK30XX_IRQ(0)
-#define IRQ_DMAC1_1 RK30XX_IRQ(1)
-#define IRQ_DMAC2_0 RK30XX_IRQ(2)
-#define IRQ_DMAC2_1 RK30XX_IRQ(3)
-#define IRQ_DDR_PCTL RK30XX_IRQ(4)
-#define IRQ_HSIC 37
-#define IRQ_GPU 39
-#define IRQ_GPU_GP RK30XX_IRQ(5)
-#define IRQ_GPU_MMU RK30XX_IRQ(6)
-#define IRQ_GPU_PP RK30XX_IRQ(7)
-
-#define IRQ_VEPU RK30XX_IRQ(9)
-#define IRQ_VDPU RK30XX_IRQ(10)
-#define IRQ_CIF0 RK30XX_IRQ(11)
-#define IRQ_CIF1 RK30XX_IRQ(12)
-#define IRQ_LCDC0 RK30XX_IRQ(13)
-#define IRQ_LCDC1 RK30XX_IRQ(14)
-#define IRQ_IPP RK30XX_IRQ(15)
-#define IRQ_USB_OTG RK30XX_IRQ(16)
-#define IRQ_USB_HOST RK30XX_IRQ(17)
-#define IRQ_GPS 50
-#define IRQ_MAC RK30XX_IRQ(19)
-#define IRQ_I2S2_2CH RK30XX_IRQ(20)
-#define IRQ_TSADC RK30XX_IRQ(21)
-#define IRQ_HSADC RK30XX_IRQ(22)
-#define IRQ_SDMMC RK30XX_IRQ(23)
-#define IRQ_SDIO RK30XX_IRQ(24)
-#define IRQ_EMMC RK30XX_IRQ(25)
-#define IRQ_SARADC RK30XX_IRQ(26)
-#define IRQ_NANDC RK30XX_IRQ(27)
-
-#define IRQ_SMC RK30XX_IRQ(29)
-#define IRQ_PIDF RK30XX_IRQ(30)
-#define IRQ_I2S0_8CH RK30XX_IRQ(31)
-#define IRQ_I2S1_2CH RK30XX_IRQ(32)
-#define IRQ_SPDIF RK30XX_IRQ(33)
-#define IRQ_UART0 RK30XX_IRQ(34)
-#define IRQ_UART1 RK30XX_IRQ(35)
-#define IRQ_UART2 RK30XX_IRQ(36)
-#define IRQ_UART3 RK30XX_IRQ(37)
-#define IRQ_SPI0 RK30XX_IRQ(38)
-#define IRQ_SPI1 RK30XX_IRQ(39)
-#define IRQ_I2C0 RK30XX_IRQ(40)
-#define IRQ_I2C1 RK30XX_IRQ(41)
-#define IRQ_I2C2 RK30XX_IRQ(42)
-#define IRQ_I2C3 RK30XX_IRQ(43)
-#define IRQ_TIMER0 RK30XX_IRQ(44)
-#define IRQ_TIMER1 RK30XX_IRQ(45)
-#define IRQ_TIMER2 RK30XX_IRQ(46)
-#define IRQ_PWM0 RK30XX_IRQ(47)
-#define IRQ_PWM1 RK30XX_IRQ(48)
-#define IRQ_PWM2 RK30XX_IRQ(49)
-#define IRQ_PWM3 RK30XX_IRQ(50)
-#define IRQ_WDT RK30XX_IRQ(51)
-#define IRQ_I2C4 RK30XX_IRQ(52)
-#define IRQ_PMU RK30XX_IRQ(53)
-#define IRQ_GPIO0 RK30XX_IRQ(54)
-#define IRQ_GPIO1 RK30XX_IRQ(55)
-#define IRQ_GPIO2 RK30XX_IRQ(56)
-#define IRQ_GPIO3 RK30XX_IRQ(57)
-#define IRQ_GPIO4 RK30XX_IRQ(58)
-
-#define IRQ_GPIO6 RK30XX_IRQ(60)
-#define IRQ_PERI_AHB_USB_ARBITER RK30XX_IRQ(61)
-#define IRQ_PERI_AHB_EMEM_ARBITER RK30XX_IRQ(62)
-#define IRQ_RGA RK30XX_IRQ(63)
-#define IRQ_HDMI RK30XX_IRQ(64)
-
-#define IRQ_SDMMC_DETECT RK30XX_IRQ(66)
-#define IRQ_SDIO_DETECT RK30XX_IRQ(67)
-#define IRQ_GPU_OBSRV_MAINFAULT RK30XX_IRQ(68)
-#define IRQ_PMU_STOP_EXIT_INT RK30XX_IRQ(69)
-#define IRQ_OBSERVER_MAINFAULT RK30XX_IRQ(70)
-#define IRQ_VPU_OBSRV_MAINFAULT RK30XX_IRQ(71)
-#define IRQ_PERI_OBSRV_MAINFAULT RK30XX_IRQ(72)
-#define IRQ_VIO1_OBSRV_MAINFAULT RK30XX_IRQ(73)
-#define IRQ_VIO0_OBSRV_MAINFAULT RK30XX_IRQ(74)
-#define IRQ_DMAC_OBSRV_MAINFAULT RK30XX_IRQ(75)
-
-//hhb@rock-chips.com this spi is used for fiq_debugger signal irq
-#define IRQ_UART_SIGNAL RK30XX_IRQ(80)
-
-#define IRQ_ARM_PMU RK30XX_IRQ(103)
-
-#define NR_GIC_IRQS (5 * 32)
-#define NR_GPIO_IRQS (7 * 32)
-#define NR_BOARD_IRQS 64
-#define NR_IRQS (NR_GIC_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS)
-
-#define IRQ_BOARD_BASE (NR_GIC_IRQS + NR_GPIO_IRQS)
-
-#endif
+++ /dev/null
-#include <plat/loader.h>
+++ /dev/null
-#ifndef __MACH_MEMORY_H
-#define __MACH_MEMORY_H
-
-#include <plat/memory.h>
-#include <mach/io.h>
-
-/*
- * SRAM memory whereabouts
- */
-#define SRAM_CODE_OFFSET (RK30_IMEM_BASE + 0x0010)
-#define SRAM_CODE_END (RK30_IMEM_BASE + 0x2FFF)
-#define SRAM_DATA_OFFSET (RK30_IMEM_BASE + 0x3000)
-#define SRAM_DATA_END (RK30_IMEM_BASE + 0x3FFF - 64)
-
-#endif
+++ /dev/null
-/*! \file
- \brief Declaration of library functions
-
- Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
-*/
-
-/*******************************************************************************
-* Copyright (c) 2009 MediaTek Inc.
-*
-* All rights reserved. Copying, compilation, modification, distribution
-* or any other use whatsoever of this material is strictly prohibited
-* except in accordance with a Software License Agreement with
-* MediaTek Inc.
-********************************************************************************
-*/
-
-/*******************************************************************************
-* LEGAL DISCLAIMER
-*
-* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND
-* AGREES THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK
-* SOFTWARE") RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE
-* PROVIDED TO BUYER ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY
-* DISCLAIMS ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT
-* LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-* PARTICULAR PURPOSE OR NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE
-* ANY WARRANTY WHATSOEVER WITH RESPECT TO THE SOFTWARE OF ANY THIRD PARTY
-* WHICH MAY BE USED BY, INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK
-* SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY
-* WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE
-* FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S SPECIFICATION OR TO
-* CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
-*
-* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
-* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL
-* BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT
-* ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY
-* BUYER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
-*
-* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
-* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT
-* OF LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING
-* THEREOF AND RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN
-* FRANCISCO, CA, UNDER THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE
-* (ICC).
-********************************************************************************
-*/
-
-#ifndef _MTK_WCN_CMB_STUB_H_
-#define _MTK_WCN_CMB_STUB_H_
-
-#include <linux/types.h>
- typedef enum {
- COMBO_AUDIO_STATE_0 = 0, /* 0000: BT_PCM_OFF & FM analog (line in/out) */
- COMBO_AUDIO_STATE_1 = 1, /* 0001: BT_PCM_ON & FM analog (in/out) */
- COMBO_AUDIO_STATE_2 = 2, /* 0010: BT_PCM_OFF & FM digital (I2S) */
- COMBO_AUDIO_STATE_3 = 3, /* 0011: BT_PCM_ON & FM digital (I2S) (invalid in 73evb & 1.2 phone configuration) */
- COMBO_AUDIO_STATE_MAX = 4,
- } COMBO_AUDIO_STATE;
-
- typedef enum {
- COMBO_FUNC_TYPE_BT = 0,
- COMBO_FUNC_TYPE_FM = 1,
- COMBO_FUNC_TYPE_GPS = 2,
- COMBO_FUNC_TYPE_WIFI = 3,
- COMBO_FUNC_TYPE_WMT = 4,
- COMBO_FUNC_TYPE_STP = 5,
- COMBO_FUNC_TYPE_NUM = 6
- } COMBO_FUNC_TYPE;
-
- typedef enum {
- COMBO_IF_UART = 0,
- COMBO_IF_MSDC = 1,
- COMBO_IF_MAX,
- } COMBO_IF;
-
-
- /******************************************************************************
- * F U N C T I O N D E C L A R A T I O N S
- *******************************************************************************
- */
-
-
- /* [GeorgeKuo] Stub functions for other kernel built-in modules to call.
- * Keep them unchanged temporarily. Move mt_combo functions to mtk_wcn_combo.
- */
- //extern int mt_combo_audio_ctrl_ex(COMBO_AUDIO_STATE state, u32 clt_ctrl);
- static inline int mt_combo_audio_ctrl(COMBO_AUDIO_STATE state) {
- //return mt_combo_audio_ctrl_ex(state, 1);
- return 0;
- }
- //extern int mt_combo_plt_enter_deep_idle(COMBO_IF src);
- //extern int mt_combo_plt_exit_deep_idle(COMBO_IF src);
-
- /* Use new mtk_wcn_stub APIs instead of old mt_combo ones for kernel to control
- * function on/off.
- */
- //extern void mtk_wcn_cmb_stub_func_ctrl (unsigned int type, unsigned int on);
- //extern int board_sdio_ctrl (unsigned int sdio_port_num, unsigned int on);
-//#include <mach/mt_combo.h> jake
-/*******************************************************************************
-* C O M P I L E R F L A G S
-********************************************************************************
-*/
-
-/*******************************************************************************
-* M A C R O S
-********************************************************************************
-*/
-
-
-/*******************************************************************************
-* E X T E R N A L R E F E R E N C E S
-********************************************************************************
-*/
-
-
-
-/*******************************************************************************
-* C O N S T A N T S
-********************************************************************************
-*/
-
-
-
-/*******************************************************************************
-* D A T A T Y P E S
-********************************************************************************
-*/
-typedef enum {
- CMB_STUB_AIF_0 = 0, /* 0000: BT_PCM_OFF & FM analog (line in/out) */
- CMB_STUB_AIF_1 = 1, /* 0001: BT_PCM_ON & FM analog (in/out) */
- CMB_STUB_AIF_2 = 2, /* 0010: BT_PCM_OFF & FM digital (I2S) */
- CMB_STUB_AIF_3 = 3, /* 0011: BT_PCM_ON & FM digital (I2S) (invalid in 73evb & 1.2 phone configuration) */
- CMB_STUB_AIF_MAX = 4,
-} CMB_STUB_AIF_X;
-
-/*COMBO_CHIP_AUDIO_PIN_CTRL*/
-typedef enum {
- CMB_STUB_AIF_CTRL_DIS = 0,
- CMB_STUB_AIF_CTRL_EN = 1,
- CMB_STUB_AIF_CTRL_MAX = 2,
-} CMB_STUB_AIF_CTRL;
-
-typedef void (*wmt_bgf_eirq_cb)(void);
-typedef int (*wmt_aif_ctrl_cb)(CMB_STUB_AIF_X, CMB_STUB_AIF_CTRL);
-typedef void (*wmt_func_ctrl_cb)(unsigned int, unsigned int);
-
-typedef struct _CMB_STUB_CB_ {
- unsigned int size; //structure size
- /*wmt_bgf_eirq_cb bgf_eirq_cb;*//* remove bgf_eirq_cb from stub. handle it in platform */
- wmt_aif_ctrl_cb aif_ctrl_cb;
- wmt_func_ctrl_cb func_ctrl_cb;
-} CMB_STUB_CB, *P_CMB_STUB_CB;
-
-/*******************************************************************************
-* P U B L I C D A T A
-********************************************************************************
-*/
-
-
-
-/*******************************************************************************
-* P R I V A T E D A T A
-********************************************************************************
-*/
-
-
-
-
-
-/*******************************************************************************
-* F U N C T I O N D E C L A R A T I O N S
-********************************************************************************
-*/
-
-extern int mtk_wcn_cmb_stub_reg (P_CMB_STUB_CB p_stub_cb);
-extern int mtk_wcn_cmb_stub_unreg (void);
-
-extern int mtk_wcn_cmb_stub_aif_ctrl (CMB_STUB_AIF_X state, CMB_STUB_AIF_CTRL ctrl);
-
-// TODO: [FixMe][GeorgeKuo]: put prototypes into mt_combo.h for board.c temporarily for non-finished porting
-// TODO: old: rfkill->board.c->mt_combo->wmt_lib_plat
-// TODO: new: rfkill->mtk_wcn_cmb_stub_alps->wmt_plat_alps
-#if 0
-extern int mtk_wcn_cmb_stub_func_ctrl(unsigned int type, unsigned int on);
-#endif
-
-/*******************************************************************************
-* F U N C T I O N S
-********************************************************************************
-*/
-
-
-#endif /* _MTK_WCN_CMB_STUB_H_ */
-
-
-
-
-
-
+++ /dev/null
-#ifndef __MACH_PMU_H
-#define __MACH_PMU_H
-
-#include <linux/io.h>
-
-#define PMU_WAKEUP_CFG0 0x00
-#define PMU_WAKEUP_CFG1 0x04
-#define PMU_PWRDN_CON 0x08
-#define PMU_PWRDN_ST 0x0c
-#define PMU_INT_CON 0x10
-#define PMU_INT_ST 0x14
-#define PMU_MISC_CON 0x18
-#define PMU_OSC_CNT 0x1c
-#define PMU_PLL_CNT 0x20
-#define PMU_PMU_CNT 0x24
-#define PMU_DDRIO_PWRON_CNT 0x28
-#define PMU_WAKEUP_RST_CLR_CNT 0x2c
-#define PMU_SCU_PWRDWN_CNT 0x30
-#define PMU_SCU_PWRUP_CNT 0x34
-#define PMU_MISC_CON1 0x38
-#define PMU_GPIO6_CON 0x3c
-#define PMU_GPIO0_CON PMU_GPIO6_CON
-#define PMU_SYS_REG0 0x40
-#define PMU_SYS_REG1 0x44
-#define PMU_SYS_REG2 0x48
-#define PMU_SYS_REG3 0x4c
-
-enum pmu_power_domain {
- PD_A9_0 = 0,
- PD_A9_1,
- PD_ALIVE,
- PD_RTC,
- PD_SCU,
- PD_CPU,
- PD_PERI = 6,
- PD_VIO,
- PD_VIDEO,
- PD_VCODEC = PD_VIDEO,
- PD_GPU,
- PD_DBG,
-};
-
-static inline bool pmu_power_domain_is_on(enum pmu_power_domain pd)
-{
- return !(readl_relaxed(RK30_PMU_BASE + PMU_PWRDN_ST) & (1 << pd));
-}
-
-void pmu_set_power_domain(enum pmu_power_domain pd, bool on);
-
-enum pmu_idle_req {
- IDLE_REQ_CPU = 0,
- IDLE_REQ_PERI,
- IDLE_REQ_GPU,
- IDLE_REQ_VIDEO,
- IDLE_REQ_VIO,
-};
-
-void pmu_set_idle_request(enum pmu_idle_req req, bool idle);
-
-#endif
+++ /dev/null
-/*
- camera.h - PXA camera driver header file
-
- Copyright (C) 2003, Intel Corporation
- Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-*/
-#ifndef __ASM_ARCH_CAMERA_RK30_H_
-#define __ASM_ARCH_CAMERA_RK30_H_
-
-#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
-#define RK29_CAM_DRV_NAME "rk3066b-camera"
-#define RK_SUPPORT_CIF0 1
-#define RK_SUPPORT_CIF1 0
-#elif defined(CONFIG_ARCH_RK30)
-#define RK29_CAM_DRV_NAME "rk30-camera"
-#define RK_SUPPORT_CIF0 1
-#define RK_SUPPORT_CIF1 1
-#endif
-
-#include <plat/rk_camera.h>
-
-#define CONFIG_CAMERA_INPUT_FMT_SUPPORT (RK_CAM_INPUT_FMT_YUV422)
-#ifdef CONFIG_SOC_RK3028
-#define CONFIG_CAMERA_SCALE_CROP_MACHINE RK_CAM_SCALE_CROP_ARM
-#else
-#define CONFIG_CAMERA_SCALE_CROP_MACHINE RK_CAM_SCALE_CROP_IPP
-#endif
-
-#if (CONFIG_CAMERA_SCALE_CROP_MACHINE==RK_CAM_SCALE_CROP_ARM)
- #define CAMERA_SCALE_CROP_MACHINE "arm"
-#elif (CONFIG_CAMERA_SCALE_CROP_MACHINE==RK_CAM_SCALE_CROP_IPP)
- #define CAMERA_SCALE_CROP_MACHINE "ipp"
-#elif (CONFIG_CAMERA_SCALE_CROP_MACHINE==RK_CAM_SCALE_CROP_RGA)
- #define CAMERA_SCALE_CROP_MACHINE "rga"
-#elif (CONFIG_CAMERA_SCALE_CROP_MACHINE==RK_CAM_SCALE_CROP_PP)
- #define CAMERA_SCALE_CROP_MACHINE "pp"
-#endif
-
-
-#define CAMERA_VIDEOBUF_ARM_ACCESS 1
-
-#endif
-
+++ /dev/null
-#ifndef __MACH_SRAM_H
-#define __MACH_SRAM_H
-
-#include <plat/sram.h>
-
-#define SRAM_LOOPS_PER_USEC 24
-#define SRAM_LOOP(loops) do { unsigned int i = (loops); if (i < 7) i = 7; barrier(); asm volatile(".align 4; 1: subs %0, %0, #1; bne 1b;" : "+r" (i)); } while (0)
-/* delay on slow mode */
-#define sram_udelay(usecs) SRAM_LOOP((usecs)*SRAM_LOOPS_PER_USEC)
-/* delay on deep slow mode */
-#define sram_32k_udelay(usecs) SRAM_LOOP(((usecs)*SRAM_LOOPS_PER_USEC)/(24000000/8192))
-
-#endif
+++ /dev/null
-#include <plat/system.h>
+++ /dev/null
-#include <plat/timex.h>
+++ /dev/null
-#include <plat/uncompress.h>
+++ /dev/null
-#ifndef __MACH_VMALLOC_H
-#define __MACH_VMALLOC_H
-
-#define VMALLOC_END 0xFE800000
-
-#endif
+++ /dev/null
-/* arch/arm/mach-rk30/io.c
- *
- * Copyright (C) 2011 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-
-#include <asm/page.h>
-#include <asm/mach/map.h>
-
-#define RK30_DEVICE(name) { \
- .virtual = (unsigned long) RK30_##name##_BASE, \
- .pfn = __phys_to_pfn(RK30_##name##_PHYS), \
- .length = RK30_##name##_SIZE, \
- .type = MT_DEVICE, \
- }
-
-static struct map_desc rk30_io_desc[] __initdata = {
- RK30_DEVICE(ROM),
- RK30_DEVICE(CORE),
- RK30_DEVICE(CPU_AXI_BUS),
-#if CONFIG_RK_DEBUG_UART == 0
- RK30_DEVICE(UART0),
-#elif CONFIG_RK_DEBUG_UART == 1
- RK30_DEVICE(UART1),
-#elif CONFIG_RK_DEBUG_UART == 2
- RK30_DEVICE(UART2),
-#elif CONFIG_RK_DEBUG_UART == 3
- RK30_DEVICE(UART3),
-#endif
- RK30_DEVICE(GRF),
- RK30_DEVICE(CRU),
- RK30_DEVICE(PMU),
- RK30_DEVICE(GPIO0),
- RK30_DEVICE(GPIO1),
- RK30_DEVICE(GPIO2),
- RK30_DEVICE(GPIO3),
-#if !defined(CONFIG_ARCH_RK3066B)
- RK30_DEVICE(GPIO4),
- RK30_DEVICE(GPIO6),
-#endif
- RK30_DEVICE(TIMER0),
- RK30_DEVICE(TIMER1),
- RK30_DEVICE(TIMER2),
- RK30_DEVICE(EFUSE),
- RK30_DEVICE(PWM01),
- RK30_DEVICE(PWM23),
- RK30_DEVICE(DDR_PCTL),
- RK30_DEVICE(DDR_PUBL),
- RK30_DEVICE(I2C1),
-};
-
-void __init rk30_map_common_io(void)
-{
- iotable_init(rk30_io_desc, ARRAY_SIZE(rk30_io_desc));
-}
+++ /dev/null
-static struct mux_config rk30_muxs[] = {
-/*
- * description mux mode mux mux
- * reg offset inter mode
- */
-
-//GPIO0C
-MUX_CFG(GPIO0C7_FLASHDATA15_NAME, GPIO0C, 14, 1, 0, DEFAULT)
-MUX_CFG(GPIO0C6_FLASHDATA14_NAME, GPIO0C, 12, 1, 0, DEFAULT)
-MUX_CFG(GPIO0C5_FLASHDATA13_NAME, GPIO0C, 10, 1, 0, DEFAULT)
-MUX_CFG(GPIO0C4_FLASHDATA12_NAME, GPIO0C, 8, 1, 0, DEFAULT)
-MUX_CFG(GPIO0C3_FLASHDATA11_NAME, GPIO0C, 6, 1, 0, DEFAULT)
-MUX_CFG(GPIO0C2_FLASHDATA10_NAME, GPIO0C, 4, 1, 0, DEFAULT)
-MUX_CFG(GPIO0C1_FLASHDATA9_NAME, GPIO0C, 2, 1, 0, DEFAULT)
-MUX_CFG(GPIO0C0_FLASHDATA8_NAME, GPIO0C, 0, 1, 0, DEFAULT)
-
-//GPIO0D
-MUX_CFG(GPIO0D7_SPI1CSN0_NAME, GPIO0D, 14, 1, 0, DEFAULT)
-MUX_CFG(GPIO0D6_SPI1CLK_NAME, GPIO0D, 12, 1, 0, DEFAULT)
-MUX_CFG(GPIO0D5_SPI1TXD_NAME, GPIO0D, 10, 1, 0, DEFAULT)
-MUX_CFG(GPIO0D4_SPI1RXD_NAME, GPIO0D, 8, 1, 0, DEFAULT)
-MUX_CFG(GPIO0D3_FLASHCSN3_EMMCRSTNOUT_NAME, GPIO0D, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO0D2_FLASHCSN2_EMMCCMD_NAME, GPIO0D, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO0D1_FLASHCSN1_NAME, GPIO0D, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO0D0_FLASHDQS_EMMCCLKOUT_NAME, GPIO0D, 0, 2, 0, DEFAULT)
-
-//GPIO1A
-MUX_CFG(GPIO1A7_UART1RTSN_SPI0CSN0_NAME, GPIO1A, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO1A6_UART1CTSN_SPI0CLK_NAME, GPIO1A, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO1A5_UART1SOUT_SPI0TXD_NAME, GPIO1A, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO1A4_UART1SIN_SPI0RXD_NAME, GPIO1A, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO1A3_UART0RTSN_NAME, GPIO1A, 6, 1, 0, DEFAULT)
-MUX_CFG(GPIO1A2_UART0CTSN_NAME, GPIO1A, 4, 1, 0, DEFAULT)
-MUX_CFG(GPIO1A1_UART0SOUT_NAME, GPIO1A, 2, 1, 0, DEFAULT)
-MUX_CFG(GPIO1A0_UART0SIN_NAME, GPIO1A, 0, 1, 0, DEFAULT)
-
-//GPIO1B
-MUX_CFG(GPIO1B7_SPI0CSN1_NAME, GPIO1B, 14, 1, 0, DEFAULT)
-MUX_CFG(GPIO1B6_SPDIFTX_SPI1CSN1_NAME, GPIO1B, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO1B5_UART3RTSN_NAME, GPIO1B, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO1B4_UART3CTSN_GPSRFCLK_NAME, GPIO1B, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO1B3_UART3SOUT_GPSSIG_NAME, GPIO1B, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO1B2_UART3SIN_GPSMAG_NAME, GPIO1B, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO1B1_UART2SOUT_JTAGTDO_NAME, GPIO1B, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO1B0_UART2SIN_JTAGTDI_NAME, GPIO1B, 0, 2, 0, DEFAULT)
-
-//GPIO1C
-MUX_CFG(GPIO1C5_I2SSDO_NAME, GPIO1C, 10, 1, 0, DEFAULT)
-MUX_CFG(GPIO1C4_I2SSDI_NAME, GPIO1C, 8, 1, 0, DEFAULT)
-MUX_CFG(GPIO1C3_I2SLRCLKTX_NAME, GPIO1C, 6, 1, 0, DEFAULT)
-MUX_CFG(GPIO1C2_I2SLRCLKRX_NAME, GPIO1C, 4, 1, 0, DEFAULT)
-MUX_CFG(GPIO1C1_I2SSCLK_NAME, GPIO1C, 2, 1, 0, DEFAULT)
-MUX_CFG(GPIO1C0_I2SCLK_NAME, GPIO1C, 0, 1, 0, DEFAULT)
-
-//GPIO1D
-MUX_CFG(GPIO1D7_I2C4SCL_NAME, GPIO1D, 14, 1, 0, DEFAULT)
-MUX_CFG(GPIO1D6_I2C4SDA_NAME, GPIO1D, 12, 1, 0, DEFAULT)
-MUX_CFG(GPIO1D5_I2C2SCL_NAME, GPIO1D, 10, 1, 0, DEFAULT)
-MUX_CFG(GPIO1D4_I2C2SDA_NAME, GPIO1D, 8, 1, 0, DEFAULT)
-MUX_CFG(GPIO1D3_I2C1SCL_NAME, GPIO1D, 6, 1, 0, DEFAULT)
-MUX_CFG(GPIO1D2_I2C1SDA_NAME, GPIO1D, 4, 1, 0, DEFAULT)
-MUX_CFG(GPIO1D1_I2C0SCL_NAME, GPIO1D, 2, 1, 0, DEFAULT)
-MUX_CFG(GPIO1D0_I2C0SDA_NAME, GPIO1D, 0, 1, 0, DEFAULT)
-
-//GPIO2A
-MUX_CFG(GPIO2A7_LCDC1DATA7_SMCDATA7_TRACEDATA7_NAME, GPIO2A, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO2A6_LCDC1DATA6_SMCDATA6_TRACEDATA6_NAME, GPIO2A, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO2A5_LCDC1DATA5_SMCDATA5_TRACEDATA5_NAME, GPIO2A, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO2A4_LCDC1DATA4_SMCDATA4_TRACEDATA4_NAME, GPIO2A, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO2A3_LCDC1DATA3_SMCDATA3_TRACEDATA3_NAME, GPIO2A, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO2A2_LCDC1DATA2_SMCDATA2_TRACEDATA2_NAME, GPIO2A, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO2A1_LCDC1DATA1_SMCDATA1_TRACEDATA1_NAME, GPIO2A, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO2A0_LCDC1DATA0_SMCDATA0_TRACEDATA0_NAME, GPIO2A, 0, 2, 0, DEFAULT)
-
-//GPIO2B
-MUX_CFG(GPIO2B7_LCDC1DATA15_SMCDATA15_TRACEDATA15_NAME, GPIO2B, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO2B6_LCDC1DATA14_SMCDATA14_TRACEDATA14_NAME, GPIO2B, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO2B5_LCDC1DATA13_SMCDATA13_TRACEDATA13_NAME, GPIO2B, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO2B4_LCDC1DATA12_SMCDATA12_TRACEDATA12_NAME, GPIO2B, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO2B3_LCDC1DATA11_SMCDATA11_TRACEDATA11_NAME, GPIO2B, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO2B2_LCDC1DATA10_SMCDATA10_TRACEDATA10_NAME, GPIO2B, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO2B1_LCDC1DATA9_SMCDATA9_TRACEDATA9_NAME, GPIO2B, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO2B0_LCDC1DATA8_SMCDATA8_TRACEDATA8_NAME, GPIO2B, 0, 2, 0, DEFAULT)
-
-//GPIO2C
-MUX_CFG(GPIO2C7_LCDC1DATA23_SMCADDR7_NAME, GPIO2C, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO2C6_LCDC1DATA22_SMCADDR6_NAME, GPIO2C, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO2C5_LCDC1DATA21_SMCADDR5_NAME, GPIO2C, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO2C4_LCDC1DATA20_SMCADDR4_NAME, GPIO2C, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO2C3_LCDC1DATA19_SMCADDR3_NAME, GPIO2C, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO2C2_LCDC1DATA18_SMCADDR2_NAME, GPIO2C, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO2C1_LCDC1DATA17_SMCADDR1_TRACECTL_NAME, GPIO2C, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO2C0_LCDC1DATA16_SMCADDR0_TRACECLK_NAME, GPIO2C, 0, 2, 0, DEFAULT)
-
-//GPIO2D
-MUX_CFG(GPIO2D7_TESTCLOCKOUT_NAME, GPIO2D, 14, 1, 0, DEFAULT)
-MUX_CFG(GPIO2D6_SMCCSN1_NAME, GPIO2D, 12, 1, 0, DEFAULT)
-MUX_CFG(GPIO2D5_SMCBLSN1_NAME, GPIO2D, 10, 1, 0, DEFAULT)
-MUX_CFG(GPIO2D4_SMCBLSN0_NAME, GPIO2D, 8, 1, 0, DEFAULT)
-MUX_CFG(GPIO2D3_LCDC1VSYNC_SMCADVN_NAME, GPIO2D, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO2D2_LCDC1HSYNC_SMCOEN_NAME, GPIO2D, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO2D1_LCDC1DEN_SMCWEN_NAME, GPIO2D, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO2D0_LCDC1DCLK_SMCCSN0_NAME, GPIO2D, 0, 2, 0, DEFAULT)
-
-//GPIO3A
-MUX_CFG(GPIO3A7_SDMMC0DATA3_NAME, GPIO3A, 14, 1, 0, DEFAULT)
-MUX_CFG(GPIO3A6_SDMMC0DATA2_NAME, GPIO3A, 12, 1, 0, DEFAULT)
-MUX_CFG(GPIO3A5_SDMMC0DATA1_NAME, GPIO3A, 10, 1, 0, DEFAULT)
-MUX_CFG(GPIO3A4_SDMMC0DATA0_NAME, GPIO3A, 8, 1, 0, DEFAULT)
-MUX_CFG(GPIO3A3_SDMMC0CMD_NAME, GPIO3A, 6, 1, 0, DEFAULT)
-MUX_CFG(GPIO3A2_SDMMC0CLKOUT_NAME, GPIO3A, 4, 1, 0, DEFAULT)
-MUX_CFG(GPIO3A1_SDMMC0PWREN_NAME, GPIO3A, 2, 1, 0, DEFAULT)
-MUX_CFG(GPIO3A0_SDMMC0RSTNOUT_NAME, GPIO3A, 0, 1, 0, DEFAULT)
-
-//GPIO3B
-MUX_CFG(GPIO3B7_CIFDATA11_I2C3SCL_NAME, GPIO3B, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO3B6_CIFDATA10_I2C3SDA_NAME, GPIO3B, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO3B5_CIFDATA1_HSADCDATA9_NAME, GPIO3B, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO3B4_CIFDATA0_HSADCDATA8_NAME, GPIO3B, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO3B3_CIFCLKOUT_NAME, GPIO3B, 6, 1, 0, DEFAULT)
-MUX_CFG(GPIO3B1_SDMMC0WRITEPRT_NAME, GPIO3B, 2, 1, 0, DEFAULT)
-MUX_CFG(GPIO3B0_SDMMC0DETECTN_NAME, GPIO3B, 0, 1, 0, DEFAULT)
-
-//GPIO3C
-MUX_CFG(GPIO3C7_SDMMC1WRITEPRT_RMIICRS_NAME, GPIO3C, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO3C6_SDMMC1DETECTN_RMIIRXERR_NAME, GPIO3C, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO3C5_SDMMC1CLKOUT_RMIICLKOUT_RMIICLKIN_NAME, GPIO3C, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO3C4_SDMMC1DATA3_RMIIRXD1_NAME, GPIO3C, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO3C3_SDMMC1DATA2_RMIIRXD0_NAME, GPIO3C, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO3C2_SDMMC1DATA1_RMIITXD0_NAME, GPIO3C, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO3C1_SDMMC1DATA0_RMIITXD1_NAME, GPIO3C, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO3C0_SDMMC1CMD_RMIITXEN_NAME, GPIO3C, 0, 2, 0, DEFAULT)
-
-//GPIO3D
-MUX_CFG(GPIO3D6_PWM3_JTAGTMS_HOSTDRVVBUS_NAME, GPIO3D, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO3D5_PWM2_JTAGTCK_OTGDRVVBUS_NAME, GPIO3D, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO3D4_PWM1_JTAGTRSTN_NAME, GPIO3D, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO3D3_PWM0_NAME, GPIO3D, 6, 1, 0, DEFAULT)
-MUX_CFG(GPIO3D2_SDMMC1INTN_NAME, GPIO3D, 4, 1, 0, DEFAULT)
-MUX_CFG(GPIO3D1_SDMMC1BACKENDPWR_MIIMDCLK_NAME, GPIO3D, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO3D0_SDMMC1PWREN_MIIMD_NAME, GPIO3D, 0, 2, 0, DEFAULT)
-};
-
-static int __init rk3066b_iomux_init(void)
-{
-
-#if defined(CONFIG_UART0_RK29) || (CONFIG_RK_DEBUG_UART == 0)
- rk30_mux_api_set(GPIO1A1_UART0SOUT_NAME, GPIO1A_UART0SOUT);
- rk30_mux_api_set(GPIO1A0_UART0SIN_NAME, GPIO1A_UART0SIN);
-#ifdef CONFIG_UART0_CTS_RTS_RK29
- rk30_mux_api_set(GPIO1A3_UART0RTSN_NAME, GPIO1A_UART0RTSN);
- rk30_mux_api_set(GPIO1A2_UART0CTSN_NAME, GPIO1A_UART0CTSN);
-#endif
-#endif
-#if defined(CONFIG_UART1_RK29) || (CONFIG_RK_DEBUG_UART == 1)
- //UART1 OR SPIM0
- rk30_mux_api_set(GPIO1A5_UART1SOUT_SPI0TXD_NAME, GPIO1A_UART1SOUT);
- rk30_mux_api_set(GPIO1A4_UART1SIN_SPI0RXD_NAME, GPIO1A_UART1SIN);
-#ifdef CONFIG_UART1_CTS_RTS_RK29
- rk30_mux_api_set(GPIO1A7_UART1RTSN_SPI0CSN0_NAME, GPIO1A_UART1RTSN);
- rk30_mux_api_set(GPIO1A6_UART1CTSN_SPI0CLK_NAME, GPIO1A_UART1CTSN);
-#endif
-#endif
-
-#if defined(CONFIG_UART2_RK29) || (CONFIG_RK_DEBUG_UART == 2)
- rk30_mux_api_set(GPIO1B1_UART2SOUT_JTAGTDO_NAME, GPIO1B_UART2SOUT);
- rk30_mux_api_set(GPIO1B0_UART2SIN_JTAGTDI_NAME, GPIO1B_UART2SIN);
-#endif
-#if defined(CONFIG_UART3_RK29) || (CONFIG_RK_DEBUG_UART == 3)
- rk30_mux_api_set(GPIO1B3_UART3SOUT_GPSSIG_NAME, GPIO1B_UART3SOUT);
- rk30_mux_api_set(GPIO1B2_UART3SIN_GPSMAG_NAME, GPIO1B_UART3SIN);
-#ifdef CONFIG_UART3_CTS_RTS_RK29
- rk30_mux_api_set(GPIO1B5_UART3RTSN_NAME, GPIO1B_UART3RTSN);
- rk30_mux_api_set(GPIO1B4_UART3CTSN_GPSRFCLK_NAME, GPIO1B_UART3CTSN);
-#endif
-#endif
-#ifdef CONFIG_SPIM0_RK29
- //UART1 OR SPIM0
- rk30_mux_api_set(GPIO1A6_UART1CTSN_SPI0CLK_NAME, GPIO1A_SPI0CLK);
- rk30_mux_api_set(GPIO1A7_UART1RTSN_SPI0CSN0_NAME, GPIO1A_SPI0CSN0);
- rk30_mux_api_set(GPIO1A5_UART1SOUT_SPI0TXD_NAME, GPIO1A_SPI0TXD);
- rk30_mux_api_set(GPIO1A4_UART1SIN_SPI0RXD_NAME, GPIO1A_SPI0RXD);
-#endif
-#ifdef CONFIG_SPIM1_RK29
- //rk30_mux_api_set(GPIO1B6_SPDIFTX_SPI1CSN1_NAME, GPIO1B_SPI1CSN1);
- rk30_mux_api_set(GPIO0D4_SPI1RXD_NAME, GPIO0D_SPI1RXD);
- rk30_mux_api_set(GPIO0D5_SPI1TXD_NAME, GPIO0D_SPI1TXD);
- rk30_mux_api_set(GPIO0D7_SPI1CSN0_NAME, GPIO0D_SPI1CSN0);
- rk30_mux_api_set(GPIO0D6_SPI1CLK_NAME, GPIO0D_SPI1CLK);
-#endif
-
-#ifdef CONFIG_I2C0_RK30
- rk30_mux_api_set(GPIO1D1_I2C0SCL_NAME, GPIO1D_I2C0SCL);
- rk30_mux_api_set(GPIO1D0_I2C0SDA_NAME, GPIO1D_I2C0SDA);
-#endif
-
-#ifdef CONFIG_I2C1_RK30
- rk30_mux_api_set(GPIO1D3_I2C1SCL_NAME, GPIO1D_I2C1SCL);
- rk30_mux_api_set(GPIO1D2_I2C1SDA_NAME, GPIO1D_I2C1SDA);
-#endif
-
-#ifdef CONFIG_I2C2_RK30
- rk30_mux_api_set(GPIO1D5_I2C2SCL_NAME, GPIO1D_I2C2SCL);
- rk30_mux_api_set(GPIO1D4_I2C2SDA_NAME, GPIO1D_I2C2SDA);
-#endif
-
-#ifdef CONFIG_I2C3_RK30
- rk30_mux_api_set(GPIO3B7_CIFDATA11_I2C3SCL_NAME, GPIO3B_I2C3SCL);
- rk30_mux_api_set(GPIO3B6_CIFDATA10_I2C3SDA_NAME, GPIO3B_I2C3SDA);
-#endif
-
-#ifdef CONFIG_I2C4_RK30
- rk30_mux_api_set(GPIO1D7_I2C4SCL_NAME, GPIO1D_I2C4SCL);
- rk30_mux_api_set(GPIO1D6_I2C4SDA_NAME, GPIO1D_I2C4SDA);
-#endif
-
-#ifdef CONFIG_RK30_VMAC
- rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_RMIICLKOUT_RMIICLKIN_NAME, GPIO3C_RMIICLKOUT);
- rk30_mux_api_set(GPIO3C0_SDMMC1CMD_RMIITXEN_NAME, GPIO3C_RMIITXEN);
- rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_RMIITXD1_NAME, GPIO3C_RMIITXD1);
- rk30_mux_api_set(GPIO3C2_SDMMC1DATA1_RMIITXD0_NAME, GPIO3C_RMIITXD0);
- rk30_mux_api_set(GPIO3C6_SDMMC1DETECTN_RMIIRXERR_NAME, GPIO3C_RMIIRXERR);
- rk30_mux_api_set(GPIO3C7_SDMMC1WRITEPRT_RMIICRS_NAME, GPIO3C_RMIICRS);
- rk30_mux_api_set(GPIO3C4_SDMMC1DATA3_RMIIRXD1_NAME, GPIO3C_RMIIRXD1);
- rk30_mux_api_set(GPIO3C3_SDMMC1DATA2_RMIIRXD0_NAME, GPIO3C_RMIIRXD0);
-
- rk30_mux_api_set(GPIO3D1_SDMMC1BACKENDPWR_MIIMDCLK_NAME, GPIO3D_MIIMDCLK);
- rk30_mux_api_set(GPIO3D0_SDMMC1PWREN_MIIMD_NAME, GPIO3D_MIIMD);
-#endif
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <asm/system.h>
-#include <asm/io.h>
-#include <linux/spinlock.h>
-
-#include <mach/io.h>
-#include <mach/iomux.h>
-
-//#define IOMUX_DBG
-
-static struct mux_config rk30_muxs[] = {
-/*
- * description mux mode mux mux
- * reg offset inter mode
- */
-//GPIO0A
-MUX_CFG(GPIO0A7_I2S8CHSDI_NAME, GPIO0A, 14, 1, 0, DEFAULT)
-MUX_CFG(GPIO0A6_HOSTDRVVBUS_NAME, GPIO0A, 12, 1, 0, DEFAULT)
-MUX_CFG(GPIO0A5_OTGDRVVBUS_NAME, GPIO0A, 10, 1, 0, DEFAULT)
-MUX_CFG(GPIO0A4_PWM1_NAME, GPIO0A, 8, 1, 0, DEFAULT)
-MUX_CFG(GPIO0A3_PWM0_NAME, GPIO0A, 6, 1, 0, DEFAULT)
-MUX_CFG(GPIO0A2_HDMII2CSDA_NAME, GPIO0A, 4, 1, 0, DEFAULT)
-MUX_CFG(GPIO0A1_HDMII2CSCL_NAME, GPIO0A, 2, 1, 0, DEFAULT)
-MUX_CFG(GPIO0A0_HDMIHOTPLUGIN_NAME, GPIO0A, 0, 1, 0, DEFAULT)
-
-//GPIO0B
-MUX_CFG(GPIO0B7_I2S8CHSDO3_NAME, GPIO0B, 14, 1, 0, DEFAULT)
-MUX_CFG(GPIO0B6_I2S8CHSDO2_NAME, GPIO0B, 12, 1, 0, DEFAULT)
-MUX_CFG(GPIO0B5_I2S8CHSDO1_NAME, GPIO0B, 10, 1, 0, DEFAULT)
-MUX_CFG(GPIO0B4_I2S8CHSDO0_NAME, GPIO0B, 8, 1, 0, DEFAULT)
-MUX_CFG(GPIO0B3_I2S8CHLRCKTX_NAME, GPIO0B, 6, 1, 0, DEFAULT)
-MUX_CFG(GPIO0B2_I2S8CHLRCKRX_NAME, GPIO0B, 4, 1, 0, DEFAULT)
-MUX_CFG(GPIO0B1_I2S8CHSCLK_NAME, GPIO0B, 2, 1, 0, DEFAULT)
-MUX_CFG(GPIO0B0_I2S8CHCLK_NAME, GPIO0B, 0, 1, 0, DEFAULT)
-
-//GPIO0C
-MUX_CFG(GPIO0C7_TRACECTL_SMCADDR3_NAME, GPIO0C, 14, 1, 0, DEFAULT)
-MUX_CFG(GPIO0C6_TRACECLK_SMCADDR2_NAME, GPIO0C, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO0C5_I2S12CHSDO_NAME, GPIO0C, 10, 1, 0, DEFAULT)
-MUX_CFG(GPIO0C4_I2S12CHSDI_NAME, GPIO0C, 8, 1, 0, DEFAULT)
-MUX_CFG(GPIO0C3_I2S12CHLRCKTX_NAME, GPIO0C, 6, 1, 0, DEFAULT)
-MUX_CFG(GPIO0C2_I2S12CHLRCKRX_NAME, GPIO0C, 4, 1, 0, DEFAULT)
-MUX_CFG(GPIO0C1_I2S12CHSCLK_NAME, GPIO0C, 2, 1, 0, DEFAULT)
-MUX_CFG(GPIO0C0_I2S12CHCLK_NAME, GPIO0C, 0, 1, 0, DEFAULT)
-
-//GPIO0D
-MUX_CFG(GPIO0D7_PWM3_NAME, GPIO0D, 14, 1, 0, DEFAULT)
-MUX_CFG(GPIO0D6_PWM2_NAME, GPIO0D, 12, 1, 0, DEFAULT)
-MUX_CFG(GPIO0D5_I2S22CHSDO_SMCADDR1_NAME, GPIO0D, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO0D4_I2S22CHSDI_SMCADDR0_NAME, GPIO0D, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO0D3_I2S22CHLRCKTX_SMCADVN_NAME, GPIO0D, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO0D2_I2S22CHLRCKRX_SMCOEN_NAME, GPIO0D, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO0D1_I2S22CHSCLK_SMCWEN_NAME, GPIO0D, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO0D0_I2S22CHCLK_SMCCSN0_NAME, GPIO0D, 0, 2, 0, DEFAULT)
-
-//GPIO1A
-MUX_CFG(GPIO1A7_UART1RTSN_SPI0TXD_NAME, GPIO1A, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO1A6_UART1CTSN_SPI0RXD_NAME, GPIO1A, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO1A5_UART1SOUT_SPI0CLK_NAME, GPIO1A, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO1A4_UART1SIN_SPI0CSN0_NAME, GPIO1A, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO1A3_UART0RTSN_NAME, GPIO1A, 6, 1, 0, DEFAULT)
-MUX_CFG(GPIO1A2_UART0CTSN_NAME, GPIO1A, 4, 1, 0, DEFAULT)
-MUX_CFG(GPIO1A1_UART0SOUT_NAME, GPIO1A, 2, 1, 0, DEFAULT)
-MUX_CFG(GPIO1A0_UART0SIN_NAME, GPIO1A, 0, 1, 0, DEFAULT)
-
-//GPIO1B
-MUX_CFG(GPIO1B7_CIFDATA11_NAME, GPIO1B, 14, 1, 0, DEFAULT)
-MUX_CFG(GPIO1B6_CIFDATA10_NAME, GPIO1B, 12, 1, 0, DEFAULT)
-MUX_CFG(GPIO1B5_CIF0DATA1_NAME, GPIO1B, 10, 1, 0, DEFAULT)
-MUX_CFG(GPIO1B4_CIF0DATA0_NAME, GPIO1B, 8, 1, 0, DEFAULT)
-MUX_CFG(GPIO1B3_CIF0CLKOUT_NAME, GPIO1B, 6, 1, 0, DEFAULT)
-MUX_CFG(GPIO1B2_SPDIFTX_NAME, GPIO1B, 4, 1, 0, DEFAULT)
-MUX_CFG(GPIO1B1_UART2SOUT_NAME, GPIO1B, 2, 1, 0, DEFAULT)
-MUX_CFG(GPIO1B0_UART2SIN_NAME, GPIO1B, 0, 1, 0, DEFAULT)
-
-//GPIO1C
-MUX_CFG(GPIO1C7_CIFDATA9_RMIIRXD0_NAME, GPIO1C, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO1C6_CIFDATA8_RMIIRXD1_NAME, GPIO1C, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO1C5_CIFDATA7_RMIICRSDVALID_NAME, GPIO1C, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO1C4_CIFDATA6_RMIIRXERR_NAME, GPIO1C, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO1C3_CIFDATA5_RMIITXD0_NAME, GPIO1C, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO1C2_CIF1DATA4_RMIITXD1_NAME, GPIO1C, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO1C1_CIFDATA3_RMIITXEN_NAME, GPIO1C, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO1C0_CIF1DATA2_RMIICLKOUT_RMIICLKIN_NAME, GPIO1C, 0, 2, 0, DEFAULT)
-
-//GPIO1D
-MUX_CFG(GPIO1D7_CIF1CLKOUT_NAME, GPIO1D, 14, 1, 0, DEFAULT)
-MUX_CFG(GPIO1D6_CIF1DATA11_NAME, GPIO1D, 12, 1, 0, DEFAULT)
-MUX_CFG(GPIO1D5_CIF1DATA10_NAME, GPIO1D, 10, 1, 0, DEFAULT)
-MUX_CFG(GPIO1D4_CIF1DATA1_NAME, GPIO1D, 8, 1, 0, DEFAULT)
-MUX_CFG(GPIO1D3_CIF1DATA0_NAME, GPIO1D, 6, 1, 0, DEFAULT)
-MUX_CFG(GPIO1D2_CIF1CLKIN_NAME, GPIO1D, 4, 1, 0, DEFAULT)
-MUX_CFG(GPIO1D1_CIF1HREF_MIIMDCLK_NAME, GPIO1D, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO1D0_CIF1VSYNC_MIIMD_NAME, GPIO1D, 0, 2, 0, DEFAULT)
-
-//GPIO2A
-MUX_CFG(GPIO2A7_LCDC1DATA7_SMCADDR11_NAME, GPIO2A, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO2A6_LCDC1DATA6_SMCADDR10_NAME, GPIO2A, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO2A5_LCDC1DATA5_SMCADDR9_NAME, GPIO2A, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO2A4_LCDC1DATA4_SMCADDR8_NAME, GPIO2A, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO2A3_LCDCDATA3_SMCADDR7_NAME, GPIO2A, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO2A2_LCDCDATA2_SMCADDR6_NAME, GPIO2A, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO2A1_LCDC1DATA1_SMCADDR5_NAME, GPIO2A, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO2A0_LCDC1DATA0_SMCADDR4_NAME, GPIO2A, 0, 2, 0, DEFAULT)
-
-//GPIO2B
-MUX_CFG(GPIO2B7_LCDC1DATA15_SMCADDR19_HSADCDATA7_NAME, GPIO2B, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO2B6_LCDC1DATA14_SMCADDR18_TSSYNC_NAME, GPIO2B, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO2B5_LCDC1DATA13_SMCADDR17_HSADCDATA8_NAME, GPIO2B, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO2B4_LCDC1DATA12_SMCADDR16_HSADCDATA9_NAME, GPIO2B, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO2B3_LCDC1DATA11_SMCADDR15_NAME, GPIO2B, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO2B2_LCDC1DATA10_SMCADDR14_NAME, GPIO2B, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO2B1_LCDC1DATA9_SMCADDR13_NAME, GPIO2B, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO2B0_LCDC1DATA8_SMCADDR12_NAME, GPIO2B, 0, 2, 0, DEFAULT)
-
-//GPIO2C
-MUX_CFG(GPIO2C7_LCDC1DATA23_SPI1CSN1_HSADCDATA4_NAME, GPIO2C, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO2C6_LCDC1DATA22_SPI1RXD_HSADCDATA3_NAME, GPIO2C, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO2C5_LCDC1DATA21_SPI1TXD_HSADCDATA2_NAME, GPIO2C, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO2C4_LCDC1DATA20_SPI1CSN0_HSADCDATA1_NAME, GPIO2C, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO2C3_LCDC1DATA19_SPI1CLK_HSADCDATA0_NAME, GPIO2C, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO2C2_LCDC1DATA18_SMCBLSN1_HSADCDATA5_NAME, GPIO2C, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO2C1_LCDC1DATA17_SMCBLSN0_HSADCDATA6_NAME, GPIO2C, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME, GPIO2C, 0, 2, 0, DEFAULT)
-
-//GPIO2D
-MUX_CFG(GPIO2D7_I2C1SCL_NAME, GPIO2D, 14, 1, 0, DEFAULT)
-MUX_CFG(GPIO2D6_I2C1SDA_NAME, GPIO2D, 12, 1, 0, DEFAULT)
-MUX_CFG(GPIO2D5_I2C0SCL_NAME, GPIO2D, 10, 1, 0, DEFAULT)
-MUX_CFG(GPIO2D4_I2C0SDA_NAME, GPIO2D, 8, 1, 0, DEFAULT)
-MUX_CFG(GPIO2D3_LCDC1VSYNC_NAME, GPIO2D, 6, 1, 0, DEFAULT)
-MUX_CFG(GPIO2D2_LCDC1HSYNC_NAME, GPIO2D, 4, 1, 0, DEFAULT)
-MUX_CFG(GPIO2D1_LCDC1DEN_SMCCSN1_NAME, GPIO2D, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO2D0_LCDC1DCLK_NAME, GPIO2D, 0, 1, 0, DEFAULT)
-
-//GPIO3A
-MUX_CFG(GPIO3A7_SDMMC0PWREN_NAME, GPIO3A, 14, 1, 0, DEFAULT) //Modifyed by xbw,at 2012-03-05
-MUX_CFG(GPIO3A6_SDMMC0RSTNOUT_NAME, GPIO3A, 12, 1, 0, DEFAULT)
-MUX_CFG(GPIO3A5_I2C4SCL_NAME, GPIO3A, 10, 1, 0, DEFAULT)
-MUX_CFG(GPIO3A4_I2C4SDA_NAME, GPIO3A, 8, 1, 0, DEFAULT)
-MUX_CFG(GPIO3A3_I2C3SCL_NAME, GPIO3A, 6, 1, 0, DEFAULT)
-MUX_CFG(GPIO3A2_I2C3SDA_NAME, GPIO3A, 4, 1, 0, DEFAULT)
-MUX_CFG(GPIO3A1_I2C2SCL_NAME, GPIO3A, 2, 1, 0, DEFAULT)
-MUX_CFG(GPIO3A0_I2C2SDA_NAME, GPIO3A, 0, 1, 0, DEFAULT)
-
-//GPIO3B
-MUX_CFG(GPIO3B7_SDMMC0WRITEPRT_NAME, GPIO3B, 14, 1, 0, DEFAULT)
-MUX_CFG(GPIO3B6_SDMMC0DETECTN_NAME, GPIO3B, 12, 1, 0, DEFAULT)
-MUX_CFG(GPIO3B5_SDMMC0DATA3_NAME, GPIO3B, 10, 1, 0, DEFAULT)
-MUX_CFG(GPIO3B4_SDMMC0DATA2_NAME, GPIO3B, 8, 1, 0, DEFAULT)
-MUX_CFG(GPIO3B3_SDMMC0DATA1_NAME, GPIO3B, 6, 1, 0, DEFAULT)
-MUX_CFG(GPIO3B2_SDMMC0DATA0_NAME, GPIO3B, 4, 1, 0, DEFAULT)
-MUX_CFG(GPIO3B1_SDMMC0CMD_NAME, GPIO3B, 2, 1, 0, DEFAULT)
-MUX_CFG(GPIO3B0_SDMMC0CLKOUT_NAME, GPIO3B, 0, 1, 0, DEFAULT)
-
-//GPIO3C
-MUX_CFG(GPIO3C7_SDMMC1WRITEPRT_NAME, GPIO3C, 14, 1, 0, DEFAULT)
-MUX_CFG(GPIO3C6_SDMMC1DETECTN_NAME, GPIO3C, 12, 1, 0, DEFAULT)
-MUX_CFG(GPIO3C5_SDMMC1CLKOUT_NAME, GPIO3C, 10, 1, 0, DEFAULT)
-MUX_CFG(GPIO3C4_SDMMC1DATA3_NAME, GPIO3C, 8, 1, 0, DEFAULT)
-MUX_CFG(GPIO3C3_SDMMC1DATA2_NAME, GPIO3C, 6, 1, 0, DEFAULT)
-MUX_CFG(GPIO3C2_SDMMC1DATA1_NAME, GPIO3C, 4, 1, 0, DEFAULT)
-MUX_CFG(GPIO3C1_SDMMC1DATA0_NAME, GPIO3C, 2, 1, 0, DEFAULT)
-MUX_CFG(GPIO3C0_SMMC1CMD_NAME, GPIO3C, 0, 1, 0, DEFAULT)
-
-//GPIO3D
-MUX_CFG(GPIO3D7_FLASHDQS_EMMCCLKOUT_NAME, GPIO3D, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO3D6_UART3RTSN_NAME, GPIO3D, 12, 1, 0, DEFAULT)
-MUX_CFG(GPIO3D5_UART3CTSN_NAME, GPIO3D, 10, 1, 0, DEFAULT)
-MUX_CFG(GPIO3D4_UART3SOUT_NAME, GPIO3D, 8, 1, 0, DEFAULT)
-MUX_CFG(GPIO3D3_UART3SIN_NAME, GPIO3D, 6, 1, 0, DEFAULT)
-MUX_CFG(GPIO3D2_SDMMC1INTN_NAME, GPIO3D, 4, 1, 0, DEFAULT)
-MUX_CFG(GPIO3D1_SDMMC1BACKENDPWR_NAME, GPIO3D, 2, 1, 0, DEFAULT)
-MUX_CFG(GPIO3D0_SDMMC1PWREN_NAME, GPIO3D, 0, 1, 0, DEFAULT)
-
-//GPIO4A
-MUX_CFG(GPIO4A7_FLASHDATA15_NAME, GPIO4A, 14, 1, 0, DEFAULT)
-MUX_CFG(GPIO4A6_FLASHDATA14_NAME, GPIO4A, 12, 1, 0, DEFAULT)
-MUX_CFG(GPIO4A5_FLASHDATA13_NAME, GPIO4A, 10, 1, 0, DEFAULT)
-MUX_CFG(GPIO4A4_FLASHDATA12_NAME, GPIO4A, 8, 1, 0, DEFAULT)
-MUX_CFG(GPIO4A3_FLASHDATA11_NAME, GPIO4A, 6, 1, 0, DEFAULT)
-MUX_CFG(GPIO4A2_FLASHDATA10_NAME, GPIO4A, 4, 1, 0, DEFAULT)
-MUX_CFG(GPIO4A1_FLASHDATA9_NAME, GPIO4A, 2, 1, 0, DEFAULT)
-MUX_CFG(GPIO4A0_FLASHDATA8_NAME, GPIO4A, 0, 1, 0, DEFAULT)
-
-//GPIO4B
-MUX_CFG(GPIO4B7_SPI0CSN1_NAME, GPIO4B, 14, 1, 0, DEFAULT)
-MUX_CFG(GPIO4B6_FLASHCSN7_NAME, GPIO4B, 12, 1, 0, DEFAULT)
-MUX_CFG(GPIO4B5_FLASHCSN6_NAME, GPIO4B, 10, 1, 0, DEFAULT)
-MUX_CFG(GPIO4B4_FLASHCSN5_NAME, GPIO4B, 8, 1, 0, DEFAULT)
-MUX_CFG(GPIO4B3_FLASHCSN4_NAME, GPIO4B, 6, 1, 0, DEFAULT)
-MUX_CFG(GPIO4B2_FLASHCSN3_EMMCRSTNOUT_NAME, GPIO4B, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO4B1_FLASHCSN2_EMMCCMD_NAME, GPIO4B, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO4B0_FLASHCSN1_NAME, GPIO4B, 0, 1, 0, DEFAULT)
-
-//GPIO4C
-MUX_CFG(GPIO4C7_SMCDATA7_TRACEDATA7_NAME, GPIO4C, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO4C6_SMCDATA6_TRACEDATA6_NAME, GPIO4C, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO4C5_SMCDATA5_TRACEDATA5_NAME, GPIO4C, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO4C4_SMCDATA4_TRACEDATA4_NAME, GPIO4C, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO4C3_SMCDATA3_TRACEDATA3_NAME, GPIO4C, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO4C2_SMCDATA2_TRACEDATA2_NAME, GPIO4C, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO4C1_SMCDATA1_TRACEDATA1_NAME, GPIO4C, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO4C0_SMCDATA0_TRACEDATA0_NAME, GPIO4C, 0, 2, 0, DEFAULT)
-
-//GPIO4D
-MUX_CFG(GPIO4D7_SMCDATA15_TRACEDATA15_NAME, GPIO4D, 14, 2, 0, DEFAULT)
-MUX_CFG(GPIO4D6_SMCDATA14_TRACEDATA14_NAME, GPIO4D, 12, 2, 0, DEFAULT)
-MUX_CFG(GPIO4D5_SMCDATA13_TRACEDATA13_NAME, GPIO4D, 10, 2, 0, DEFAULT)
-MUX_CFG(GPIO4D4_SMCDATA12_TRACEDATA12_NAME, GPIO4D, 8, 2, 0, DEFAULT)
-MUX_CFG(GPIO4D3_SMCDATA11_TRACEDATA11_NAME, GPIO4D, 6, 2, 0, DEFAULT)
-MUX_CFG(GPIO4D2_SMCDATA10_TRACEDATA10_NAME, GPIO4D, 4, 2, 0, DEFAULT)
-MUX_CFG(GPIO4D1_SMCDATA9_TRACEDATA9_NAME, GPIO4D, 2, 2, 0, DEFAULT)
-MUX_CFG(GPIO4D0_SMCDATA8_TRACEDATA8_NAME, GPIO4D, 0, 2, 0, DEFAULT)
-
-//GPIO6B
-MUX_CFG(GPIO6B7_TESTCLOCKOUT_NAME, GPIO6B, 14, 1, 0, DEFAULT)
-
-};
-
-
-void rk30_mux_set(struct mux_config *cfg)
-{
- int regValue = 0;
- int mask;
-
- mask = (((1<<(cfg->interleave))-1)<<cfg->offset) << 16;
- regValue |= mask;
- regValue |=(cfg->mode<<cfg->offset);
-#ifdef IOMUX_DBG
- printk("%s::reg=0x%p,Value=0x%x,mask=0x%x\n",__FUNCTION__,cfg->mux_reg,regValue,mask);
-#endif
- writel_relaxed(regValue,cfg->mux_reg);
- dsb();
-
- return;
-}
-
-
-int __init rk30_iomux_init(void)
-{
- int i;
- printk("%s\n",__func__);
-
- iomux_init();
-
- for(i=0;i<ARRAY_SIZE(rk30_muxs);i++)
- {
- if(rk30_muxs[i].flags != DEFAULT)
- rk30_mux_set(&rk30_muxs[i]);
- }
-
-#if defined(CONFIG_ARCH_RK3066B)
- return rk3066b_iomux_init();
-#elif defined(CONFIG_ARCH_RK30)
-
-#if defined(CONFIG_UART0_RK29) || (CONFIG_RK_DEBUG_UART == 0)
- rk30_mux_api_set(GPIO1A1_UART0SOUT_NAME, GPIO1A_UART0_SOUT);
- rk30_mux_api_set(GPIO1A0_UART0SIN_NAME, GPIO1A_UART0_SIN);
-#ifdef CONFIG_UART0_CTS_RTS_RK29
- rk30_mux_api_set(GPIO1A3_UART0RTSN_NAME, GPIO1A_UART0_RTS_N);
- rk30_mux_api_set(GPIO1A2_UART0CTSN_NAME, GPIO1A_UART0_CTS_N);
-#endif
-#endif
-#if defined(CONFIG_UART1_RK29) || (CONFIG_RK_DEBUG_UART == 1)
- //UART1 OR SPIM0
- rk30_mux_api_set(GPIO1A5_UART1SOUT_SPI0CLK_NAME, GPIO1A_UART1_SOUT);
- rk30_mux_api_set(GPIO1A4_UART1SIN_SPI0CSN0_NAME, GPIO1A_UART1_SIN);
-#ifdef CONFIG_UART1_CTS_RTS_RK29
- rk30_mux_api_set(GPIO1A7_UART1RTSN_SPI0TXD_NAME, GPIO1A_UART1_RTS_N);
- rk30_mux_api_set(GPIO1A6_UART1CTSN_SPI0RXD_NAME, GPIO1A_UART1_CTS_N);
-#endif
-#endif
-
-#if defined(CONFIG_UART2_RK29) || (CONFIG_RK_DEBUG_UART == 2)
- rk30_mux_api_set(GPIO1B1_UART2SOUT_NAME, GPIO1B_UART2_SOUT);
- rk30_mux_api_set(GPIO1B0_UART2SIN_NAME, GPIO1B_UART2_SIN);
-#endif
-#if defined(CONFIG_UART3_RK29) || (CONFIG_RK_DEBUG_UART == 3)
- rk30_mux_api_set(GPIO3D4_UART3SOUT_NAME, GPIO3D_UART3_SOUT);
- rk30_mux_api_set(GPIO3D3_UART3SIN_NAME, GPIO3D_UART3_SIN);
-#ifdef CONFIG_UART3_CTS_RTS_RK29
- rk30_mux_api_set(GPIO3D6_UART3RTSN_NAME, GPIO3D_UART3_RTS_N);
- rk30_mux_api_set(GPIO3D5_UART3CTSN_NAME, GPIO3D_UART3_CTS_N);
-#endif
-#endif
-#ifdef CONFIG_SPIM0_RK29
- //UART1 OR SPIM0
- rk30_mux_api_set(GPIO1A5_UART1SOUT_SPI0CLK_NAME, GPIO1A_SPI0_CLK);
- rk30_mux_api_set(GPIO1A4_UART1SIN_SPI0CSN0_NAME, GPIO1A_SPI0_CSN0);
- rk30_mux_api_set(GPIO1A7_UART1RTSN_SPI0TXD_NAME, GPIO1A_SPI0_TXD);
- rk30_mux_api_set(GPIO1A6_UART1CTSN_SPI0RXD_NAME, GPIO1A_SPI0_RXD);
-#endif
-#ifdef CONFIG_SPIM1_RK29
- //rk30_mux_api_set(GPIO2C7_LCDC1DATA23_SPI1CSN1_HSADCDATA4_NAME, GPIO2C_SPI1_CSN1);
- rk30_mux_api_set(GPIO2C6_LCDC1DATA22_SPI1RXD_HSADCDATA3_NAME, GPIO2C_SPI1_RXD);
- rk30_mux_api_set(GPIO2C5_LCDC1DATA21_SPI1TXD_HSADCDATA2_NAME, GPIO2C_SPI1_TXD);
- rk30_mux_api_set(GPIO2C4_LCDC1DATA20_SPI1CSN0_HSADCDATA1_NAME, GPIO2C_SPI1_CSN0);
- rk30_mux_api_set(GPIO2C3_LCDC1DATA19_SPI1CLK_HSADCDATA0_NAME, GPIO2C_SPI1_CLK);
-#endif
-
-#ifdef CONFIG_I2C0_RK30
- rk30_mux_api_set(GPIO2D5_I2C0SCL_NAME, GPIO2D_I2C0_SCL);
- rk30_mux_api_set(GPIO2D4_I2C0SDA_NAME, GPIO2D_I2C0_SDA);
-#endif
-
-#ifdef CONFIG_I2C1_RK30
- rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME, GPIO2D_I2C1_SCL);
- rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME, GPIO2D_I2C1_SDA);
-#endif
-
-#ifdef CONFIG_I2C2_RK30
- rk30_mux_api_set(GPIO3A1_I2C2SCL_NAME, GPIO3A_I2C2_SCL);
- rk30_mux_api_set(GPIO3A0_I2C2SDA_NAME, GPIO3A_I2C2_SDA);
-#endif
-
-#ifdef CONFIG_I2C3_RK30
- rk30_mux_api_set(GPIO3A3_I2C3SCL_NAME, GPIO3A_I2C3_SCL);
- rk30_mux_api_set(GPIO3A2_I2C3SDA_NAME, GPIO3A_I2C3_SDA);
-#endif
-
-#ifdef CONFIG_I2C4_RK30
- rk30_mux_api_set(GPIO3A5_I2C4SCL_NAME, GPIO3A_I2C4_SCL);
- rk30_mux_api_set(GPIO3A4_I2C4SDA_NAME, GPIO3A_I2C4_SDA);
-#endif
-
-#ifdef CONFIG_RK30_VMAC
- rk30_mux_api_set(GPIO1C0_CIF1DATA2_RMIICLKOUT_RMIICLKIN_NAME, GPIO1C_RMII_CLKOUT);
- rk30_mux_api_set(GPIO1C1_CIFDATA3_RMIITXEN_NAME, GPIO1C_RMII_TX_EN);
- rk30_mux_api_set(GPIO1C2_CIF1DATA4_RMIITXD1_NAME, GPIO1C_RMII_TXD1);
- rk30_mux_api_set(GPIO1C3_CIFDATA5_RMIITXD0_NAME, GPIO1C_RMII_TXD0);
- rk30_mux_api_set(GPIO1C4_CIFDATA6_RMIIRXERR_NAME, GPIO1C_RMII_RX_ERR);
- rk30_mux_api_set(GPIO1C5_CIFDATA7_RMIICRSDVALID_NAME, GPIO1C_RMII_CRS_DVALID);
- rk30_mux_api_set(GPIO1C6_CIFDATA8_RMIIRXD1_NAME, GPIO1C_RMII_RXD1);
- rk30_mux_api_set(GPIO1C7_CIFDATA9_RMIIRXD0_NAME, GPIO1C_RMII_RXD0);
-
- rk30_mux_api_set(GPIO1D1_CIF1HREF_MIIMDCLK_NAME, GPIO1D_MII_MDCLK);
- rk30_mux_api_set(GPIO1D0_CIF1VSYNC_MIIMD_NAME, GPIO1D_MII_MD);
-#endif
-
-#endif
-
- return 0;
-}
-
-/*
- *config iomux : input iomux name and iomux flags
- */
-void rk30_mux_api_set(char *name, unsigned int mode)
-{
- int i;
- if (!name) {
- return;
- }
- for(i=0;i<ARRAY_SIZE(rk30_muxs);i++)
- {
- if (!strcmp(rk30_muxs[i].name, name))
- {
- rk30_muxs[i].premode = rk30_muxs[i].mode;
- rk30_muxs[i].mode = mode;
- rk30_mux_set(&rk30_muxs[i]);
- break;
- }
- }
-}
-EXPORT_SYMBOL(rk30_mux_api_set);
-
-
-int rk30_mux_api_get(char *name)
-{
- int i,ret=0;
- if (!name) {
- return -1;
- }
- for(i=0;i<ARRAY_SIZE(rk30_muxs);i++)
- {
- if (!strcmp(rk30_muxs[i].name, name))
- {
- ret = readl(rk30_muxs[i].mux_reg);
- ret = (ret >> rk30_muxs[i].offset) &((1<<(rk30_muxs[i].interleave))-1);
- return ret;
- }
- }
-
- return -1;
-}
-EXPORT_SYMBOL(rk30_mux_api_get);
-
+++ /dev/null
-/*
- * arch/arm/mach-rk30/localtimer.c
- *
- * Copyright (C) 2002 ARM Ltd.
- * All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/clockchips.h>
-#include <asm/irq.h>
-#include <asm/smp_twd.h>
-#include <asm/localtimer.h>
-
-/*
- * Setup the local clock events for a CPU.
- */
-int __cpuinit local_timer_setup(struct clock_event_device *evt)
-{
- evt->irq = IRQ_LOCALTIMER;
- twd_timer_setup(evt);
- return 0;
-}
+++ /dev/null
-/*
- * RK30 SMP source file. It contains platform specific fucntions
- * needed for the linux smp kernel.
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- * All Rights Reserved
- */
-
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/io.h>
-#include <linux/version.h>
-
-#include <asm/cacheflush.h>
-#include <asm/fiq_glue.h>
-#include <asm/hardware/gic.h>
-#include <asm/smp_scu.h>
-
-#include <mach/pmu.h>
-
-#define SCU_CTRL 0x00
-#define SCU_STANDBY_EN (1 << 5)
-
-#ifdef CONFIG_FIQ
-static void gic_raise_softirq_non_secure(const struct cpumask *mask, unsigned int irq)
-{
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 2, 0))
- unsigned long map = *cpus_addr(*mask);
-#else
- int cpu;
- unsigned long map = 0;
-
- /* Convert our logical CPU mask into a physical one. */
- for_each_cpu(cpu, mask)
- map |= 1 << cpu_logical_map(cpu);
-#endif
-
- /*
- * Ensure that stores to Normal memory are visible to the
- * other CPUs before issuing the IPI.
- */
- dsb();
-
- /* this always happens on GIC0 */
- writel_relaxed(map << 16 | irq | 0x8000, GIC_DIST_BASE + GIC_DIST_SOFTINT);
-}
-
-static void gic_secondary_init_non_secure(void)
-{
-#define GIC_DIST_SECURITY 0x080
- writel_relaxed(0xffffffff, GIC_DIST_BASE + GIC_DIST_SECURITY);
- writel_relaxed(0xf, GIC_CPU_BASE + GIC_CPU_CTRL);
- dsb();
-}
-#endif
-
-void __cpuinit platform_secondary_init(unsigned int cpu)
-{
- /*
- * if any interrupts are already enabled for the primary
- * core (e.g. timer irq), then they will not have been enabled
- * for us: do so
- */
- gic_secondary_init(0);
-
-#ifdef CONFIG_FIQ
- gic_secondary_init_non_secure();
- fiq_glue_resume();
-#endif
-}
-
-extern void rk30_sram_secondary_startup(void);
-
-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
-{
- static bool first = true;
-
- if (first) {
- unsigned long sz = 0x10;
- unsigned int i, ncores = scu_get_core_count(RK30_SCU_BASE);
-
- for (i = 1; i < ncores; i++)
- pmu_set_power_domain(PD_A9_0 + i, false);
-
- memcpy(RK30_IMEM_NONCACHED, rk30_sram_secondary_startup, sz);
- isb();
- dsb();
-
- first = false;
- }
-
- pmu_set_power_domain(PD_A9_0 + cpu, true);
-
- return 0;
-}
-
-/*
- * Initialise the CPU possible map early - this describes the CPUs
- * which may be present or become present in the system.
- */
-void __init smp_init_cpus(void)
-{
- unsigned int i, ncores = scu_get_core_count(RK30_SCU_BASE);
-
- if (ncores > nr_cpu_ids) {
- pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
- ncores, nr_cpu_ids);
- ncores = nr_cpu_ids;
- }
-
- for (i = 0; i < ncores; i++)
- set_cpu_possible(i, true);
-
-#ifdef CONFIG_FIQ
- set_smp_cross_call(gic_raise_softirq_non_secure);
-#else
- set_smp_cross_call(gic_raise_softirq);
-#endif
-}
-
-void __init platform_smp_prepare_cpus(unsigned int max_cpus)
-{
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 1, 0))
- int i;
-
- /*
- * Initialise the present map, which describes the set of CPUs
- * actually populated at the present time.
- */
- for (i = 0; i < max_cpus; i++)
- set_cpu_present(i, true);
-#endif
-
- writel_relaxed(readl_relaxed(RK30_SCU_BASE + SCU_CTRL) | SCU_STANDBY_EN, RK30_SCU_BASE + SCU_CTRL);
-
- scu_enable(RK30_SCU_BASE);
-}
+++ /dev/null
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/pm.h>
-#include <linux/suspend.h>
-#include <linux/random.h>
-#include <linux/crc32.h>
-#include <linux/io.h>
-#include <linux/wakelock.h>
-#include <asm/cacheflush.h>
-#include <asm/tlbflush.h>
-#include <asm/hardware/cache-l2x0.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/pmu.h>
-#include <mach/board.h>
-#include <mach/system.h>
-#include <mach/sram.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <mach/cru.h>
-#include <mach/ddr.h>
-#include <mach/debug_uart.h>
-#include <plat/efuse.h>
-#include <plat/cpu.h>
-#include <linux/regulator/machine.h>
-
-
-
-#define cru_readl(offset) readl_relaxed(RK30_CRU_BASE + offset)
-#define cru_writel(v, offset) do { writel_relaxed(v, RK30_CRU_BASE + offset); dsb(); } while (0)
-
-#define pmu_readl(offset) readl_relaxed(RK30_PMU_BASE + offset)
-#define pmu_writel(v,offset) do { writel_relaxed(v, RK30_PMU_BASE + offset); dsb(); } while (0)
-
-#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
-
-#define gate_save_soc_clk(val,_save,cons,w_msk) \
- (_save)=cru_readl(cons);\
- cru_writel((((~(val)|(_save))&(w_msk))|((w_msk)<<16)),cons)
-
-
-__weak void board_gpio_suspend(void) {}
-__weak void board_gpio_resume(void) {}
-__weak void __sramfunc board_pmu_suspend(void) {}
-__weak void __sramfunc board_pmu_resume(void) {}
-__weak void __sramfunc rk30_suspend_voltage_set(unsigned int vol){}
-__weak void __sramfunc rk30_suspend_voltage_resume(unsigned int vol){}
-
-__weak void rk30_pwm_suspend_voltage_set(void){}
-__weak void rk30_pwm_resume_voltage_set(void){}
-__weak void board_act8846_set_suspend_vol(void){}
-__weak void board_act8846_set_resume_vol(void){}
-
-__weak void __sramfunc rk30_pwm_logic_suspend_voltage(void){}
-__weak void __sramfunc rk30_pwm_logic_resume_voltage(void){}
-__weak int __sramfunc rk30_phonecall_lowerpower(void)
-{
- return 0;
-}
-
-static int rk3188plus_soc = 0;
-
-/********************************sram_printch**************************************************/
-static bool __sramdata pm_log;
-extern void pm_emit_log_char(char c);
-
-void __sramfunc sram_printch(char byte)
-{
-#ifdef DEBUG_UART_BASE
- u32 clk_gate2, clk_gate4, clk_gate8;
-
- gate_save_soc_clk(0
- | (1 << CLK_GATE_ACLK_PERIPH % 16)
- | (1 << CLK_GATE_HCLK_PERIPH % 16)
- | (1 << CLK_GATE_PCLK_PERIPH % 16)
- , clk_gate2, CRU_CLKGATES_CON(2), 0
- | (1 << ((CLK_GATE_ACLK_PERIPH % 16) + 16))
- | (1 << ((CLK_GATE_HCLK_PERIPH % 16) + 16))
- | (1 << ((CLK_GATE_PCLK_PERIPH % 16) + 16)));
- gate_save_soc_clk((1 << CLK_GATE_ACLK_CPU_PERI % 16)
- , clk_gate4, CRU_CLKGATES_CON(4),
- (1 << ((CLK_GATE_ACLK_CPU_PERI % 16) + 16)));
- gate_save_soc_clk((1 << ((CLK_GATE_PCLK_UART0 + CONFIG_RK_DEBUG_UART) % 16)),
- clk_gate8, CRU_CLKGATES_CON(8),
- (1 << (((CLK_GATE_PCLK_UART0 + CONFIG_RK_DEBUG_UART) % 16) + 16)));
- sram_udelay(1);
-
- writel_relaxed(byte, DEBUG_UART_BASE);
- dsb();
-
- /* loop check LSR[6], Transmitter Empty bit */
- while (!(readl_relaxed(DEBUG_UART_BASE + 0x14) & 0x40))
- barrier();
-
- cru_writel(0xffff0000 | clk_gate2, CRU_CLKGATES_CON(2));
- cru_writel(0xffff0000 | clk_gate4, CRU_CLKGATES_CON(4));
- cru_writel(0xffff0000 | clk_gate8, CRU_CLKGATES_CON(8));
-#endif
-
- sram_log_char(byte);
- if (pm_log)
- pm_emit_log_char(byte);
-
- if (byte == '\n')
- sram_printch('\r');
-}
-/********************************ddr test**************************************************/
-
-#ifdef CONFIG_DDR_TEST
-static int ddr_debug=0;
-module_param(ddr_debug, int, 0644);
-
-static int inline calc_crc32(u32 addr, size_t len)
-{
- return crc32_le(~0, (const unsigned char *)addr, len);
-}
-
-extern __sramdata uint32_t mem_type;
-static void ddr_testmode(void)
-{
- int32_t g_crc1, g_crc2;
- uint32_t nMHz;
- uint32_t n = 0;
- uint32_t min,max;
- extern char _stext[], _etext[];
- if (ddr_debug == 0)
- return;
-
- if (ddr_debug == 1) {
- switch(mem_type)
- {
- case 0: //LPDDR
- case 1: //DDR
- max = 210;
- min = 100;
- break;
- case 2: //DDR2
- case 4: //LPDDR2
- max=410;
- min=100;
- break;
- case 3: //DDR3
- default:
- max=500;
- min=100;
- break;
- }
- for (;;) {
- sram_printascii("\n change freq:");
- g_crc1 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
- do
- {
- nMHz = min + random32();
- nMHz %= max;
- }while(nMHz < min);
- sram_printhex(nMHz);
- sram_printch(' ');
- nMHz = ddr_change_freq(nMHz);
- sram_printhex(n++);
- sram_printch(' ');
- g_crc2 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
- if (g_crc1!=g_crc2) {
- sram_printascii("fail\n");
- }
- //ddr_print("check image crc32 success--crc value = 0x%x!, count:%d\n",g_crc1, n++);
- // sram_printascii("change freq success\n");
- }
- } else if(ddr_debug == 2) {
- for (;;) {
- sram_printch(' ');
- sram_printch('9');
- sram_printch('9');
- sram_printch('9');
- sram_printch(' ');
- g_crc1 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
- nMHz = (random32()>>13);// 16.7s max
- ddr_suspend();
- sram_udelay(nMHz);
- ddr_resume();
- sram_printhex(nMHz);
- sram_printch(' ');
- sram_printhex(n++);
- g_crc2 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
- if (g_crc1 != g_crc2) {
- sram_printch(' ');
- sram_printch('f');
- sram_printch('a');
- sram_printch('i');
- sram_printch('l');
- }
- // ddr_print("check image crc32 fail!, count:%d\n", n++);
- // sram_printascii("self refresh fail\n");
- //else
- //ddr_print("check image crc32 success--crc value = 0x%x!, count:%d\n",g_crc1, n++);
- // sram_printascii("self refresh success\n");
- }
- } else if (ddr_debug == 3) {
- extern int memtester(void);
- memtester();
- }
- else
- {
- ddr_change_freq(ddr_debug);
- ddr_debug=0;
- }
-}
-#else
-static void ddr_testmode(void) {}
-#endif
-
-
-#define DUMP_GPIO_INT_STATUS(ID) \
-do { \
- if (irq_gpio & (1 << ID)) \
- printk("wakeup gpio" #ID ": %08x\n", readl_relaxed(RK30_GPIO##ID##_BASE + GPIO_INT_STATUS)); \
-} while (0)
-
-static noinline void rk30_pm_dump_irq(void)
-{
- u32 irq_gpio = (readl_relaxed(RK30_GICD_BASE + GIC_DIST_PENDING_SET + 8) >> 22) & 0x7F;
- printk("wakeup irq: %08x %08x %08x %08x\n",
- readl_relaxed(RK30_GICD_BASE + GIC_DIST_PENDING_SET + 4),
- readl_relaxed(RK30_GICD_BASE + GIC_DIST_PENDING_SET + 8),
- readl_relaxed(RK30_GICD_BASE + GIC_DIST_PENDING_SET + 12),
- readl_relaxed(RK30_GICD_BASE + GIC_DIST_PENDING_SET + 16));
- DUMP_GPIO_INT_STATUS(0);
- DUMP_GPIO_INT_STATUS(1);
- DUMP_GPIO_INT_STATUS(2);
- DUMP_GPIO_INT_STATUS(3);
-#if GPIO_BANKS > 4
- DUMP_GPIO_INT_STATUS(4);
-#endif
-#if GPIO_BANKS > 5
- DUMP_GPIO_INT_STATUS(6);
-#endif
-}
-
-#define DUMP_GPIO_INTEN(ID) \
-do { \
- u32 en = readl_relaxed(RK30_GPIO##ID##_BASE + GPIO_INTEN); \
- if (en) { \
- sram_printascii("GPIO" #ID "_INTEN: "); \
- sram_printhex(en); \
- sram_printch('\n'); \
- printk(KERN_DEBUG "GPIO%d_INTEN: %08x\n", ID, en); \
- } \
-} while (0)
-
-static noinline void rk30_pm_dump_inten(void)
-{
- DUMP_GPIO_INTEN(0);
- DUMP_GPIO_INTEN(1);
- DUMP_GPIO_INTEN(2);
- DUMP_GPIO_INTEN(3);
-#if !(defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188))
- DUMP_GPIO_INTEN(4);
- DUMP_GPIO_INTEN(6);
-#endif
-}
-
-static void pm_pll_wait_lock(int pll_idx)
-{
- u32 pll_state[4] = { 1, 0, 2, 3 };
-#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
-
- u32 bit = 0x20u << pll_state[pll_idx];
-#else
- u32 bit = 0x10u << pll_state[pll_idx];
-#endif
- u32 delay = pll_idx == APLL_ID ? 600000U : 30000000U;
- dsb();
- dsb();
- dsb();
- dsb();
- dsb();
- dsb();
- while (delay > 0) {
- if (grf_readl(GRF_SOC_STATUS0) & bit)
- break;
- delay--;
- }
- if (delay == 0) {
- //CRU_PRINTK_ERR("wait pll bit 0x%x time out!\n", bit);
- sram_printch('p');
- sram_printch('l');
- sram_printch('l');
- sram_printhex(pll_idx);
- sram_printch('\n');
- }
-}
-
-static void power_on_pll(enum rk_plls_id pll_id)
-{
-#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
- if (!rk3188plus_soc) {
- cru_writel(PLL_PWR_DN_W_MSK | PLL_PWR_ON, PLL_CONS((pll_id), 3));
- pm_pll_wait_lock((pll_id));
- } else {
- u32 pllcon0, pllcon1, pllcon2;
- cru_writel(PLL_PWR_DN_W_MSK | PLL_PWR_ON, PLL_CONS((pll_id),3));
- pllcon0 = cru_readl(PLL_CONS((pll_id),0));
- pllcon1 = cru_readl(PLL_CONS((pll_id),1));
- pllcon2 = cru_readl(PLL_CONS((pll_id),2));
-
- //enter slowmode
- cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
-
- //enter rest
- cru_writel(PLL_RESET_W_MSK | PLL_RESET, PLL_CONS(pll_id,3));
- cru_writel(pllcon0, PLL_CONS(pll_id,0));
- cru_writel(pllcon1, PLL_CONS(pll_id,1));
- cru_writel(pllcon2, PLL_CONS(pll_id,2));
- if (pll_id == APLL_ID)
- sram_udelay(5);
- else
- udelay(5);
-
- //return form rest
- cru_writel(PLL_RESET_W_MSK | PLL_RESET_RESUME, PLL_CONS(pll_id,3));
-
- //wating lock state
- if (pll_id == APLL_ID)
- sram_udelay(168);
- else
- udelay(168);
- pm_pll_wait_lock(pll_id);
-
- //return form slow
- cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
- }
-#else
- u32 pllcon0, pllcon1, pllcon2;
-
- cru_writel(PLL_PWR_DN_W_MSK | PLL_PWR_ON, PLL_CONS((pll_id),3));
- pllcon0 = cru_readl(PLL_CONS((pll_id),0));
- pllcon1 = cru_readl(PLL_CONS((pll_id),1));
- pllcon2 = cru_readl(PLL_CONS((pll_id),2));
-
- //enter slowmode
- cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
-
- //enter rest
- cru_writel(PLL_REST_W_MSK | PLL_REST, PLL_CONS(pll_id,3));
- cru_writel(pllcon0, PLL_CONS(pll_id,0));
- cru_writel(pllcon1, PLL_CONS(pll_id,1));
- cru_writel(pllcon2, PLL_CONS(pll_id,2));
- if (pll_id == APLL_ID)
- sram_udelay(5);
- else
- udelay(5);
-
- //return form rest
- cru_writel(PLL_REST_W_MSK | PLL_REST_RESM, PLL_CONS(pll_id,3));
-
- //wating lock state
- if (pll_id == APLL_ID)
- sram_udelay(168);
- else
- udelay(168);
- pm_pll_wait_lock(pll_id);
-
- //return form slow
- cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
-#endif
-}
-
-#define power_off_pll(id) \
- cru_writel(PLL_PWR_DN_W_MSK | PLL_PWR_DN, PLL_CONS((id), 3))
-
-
-#define DDR_SAVE_SP(save_sp) do { save_sp = ddr_save_sp(((unsigned long)SRAM_DATA_END & (~7))); } while (0)
-#define DDR_RESTORE_SP(save_sp) do { ddr_save_sp(save_sp); } while (0)
-static unsigned long save_sp;
-static noinline void interface_ctr_reg_pread(void)
-{
- u32 addr;
-
- flush_cache_all();
- outer_flush_all();
- local_flush_tlb_all();
-
- for (addr = (u32)SRAM_CODE_OFFSET; addr < (u32)SRAM_CODE_END; addr += PAGE_SIZE)
- readl_relaxed(addr);
- for (addr = (u32)SRAM_DATA_OFFSET; addr < (u32)SRAM_DATA_END; addr += PAGE_SIZE)
- readl_relaxed(addr);
- readl_relaxed(RK30_PMU_BASE);
- readl_relaxed(RK30_GRF_BASE);
- readl_relaxed(RK30_DDR_PCTL_BASE);
- readl_relaxed(RK30_DDR_PUBL_BASE);
- readl_relaxed(RK30_I2C1_BASE+SZ_4K);
- readl_relaxed(RK30_GPIO0_BASE);
- readl_relaxed(RK30_GPIO3_BASE);
-#if defined(RK30_GPIO6_BASE)
- readl_relaxed(RK30_GPIO6_BASE);
-#endif
-}
-
-
-static inline bool pm_pmu_power_domain_is_on(enum pmu_power_domain pd, u32 pmu_pwrdn_st)
-{
- return !(pmu_pwrdn_st & (1 << pd));
-}
-static void rk30_pm_set_power_domain(u32 pmu_pwrdn_st, bool state)
-{
-#if !(defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188))
- if (pm_pmu_power_domain_is_on(PD_DBG, pmu_pwrdn_st))
- pmu_set_power_domain(PD_DBG, state);
-#endif
-
- if (pm_pmu_power_domain_is_on(PD_GPU, pmu_pwrdn_st)) {
-#if defined(CONFIG_ARCH_RK3066B)
- u32 gate[3];
- gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU_MST));
- gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU_SLV));
- gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_CLK_GPU));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_CLK_GPU), CLK_GATE_CLKID_CONS(CLK_GATE_CLK_GPU));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU_MST), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU_MST));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU_SLV), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU_SLV));
- pmu_set_power_domain(PD_GPU, state);
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU_MST) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU_MST));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU_SLV) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU_SLV));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_CLK_GPU) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_CLK_GPU));
-#elif defined(CONFIG_ARCH_RK3188)
- u32 gate[2];
- gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU_SRC));
- gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU_SRC));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
- pmu_set_power_domain(PD_GPU, state);
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU_SRC) | gate[0],
- CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU_SRC));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
-#else
- u32 gate[2];
- gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_GPU_SRC));
- gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_GPU_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_GPU_SRC));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
- pmu_set_power_domain(PD_GPU, state);
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_GPU_SRC) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_GPU_SRC));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
-#endif
- }
-
- if (pm_pmu_power_domain_is_on(PD_VIDEO, pmu_pwrdn_st)) {
- u32 gate[3];
- gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
- gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
-#if !defined(CONFIG_ARCH_RK3188)
- gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
-#endif
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
-#if !defined(CONFIG_ARCH_RK3188)
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
-#endif
- pmu_set_power_domain(PD_VIDEO, state);
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
-#if !defined(CONFIG_ARCH_RK3188)
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
-#endif
- }
-
- if (pm_pmu_power_domain_is_on(PD_VIO, pmu_pwrdn_st)) {
- u32 gate[10];
- gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
- gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
- gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
- gate[3] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
- gate[4] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
- gate[5] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
- gate[6] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
- gate[7] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
- gate[8] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
- gate[9] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
- pmu_set_power_domain(PD_VIO, state);
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1) | gate[3], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0) | gate[4], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1) | gate[5], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0) | gate[6], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1) | gate[7], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP) | gate[8], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA) | gate[9], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
- }
-}
-static void __sramfunc rk_pm_soc_sram_volt_suspend(void)
-{
- rk30_suspend_voltage_set(1000000);
- rk30_pwm_logic_suspend_voltage();
-#ifdef CONFIG_ACT8846_SUPPORT_RESET
- board_act8846_set_suspend_vol();
-#endif
-}
-
-static void __sramfunc rk_pm_soc_sram_volt_resume(void)
-{
-
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- board_act8846_set_resume_vol();
- #endif
-
- rk30_pwm_logic_resume_voltage();
- rk30_suspend_voltage_resume(1100000);
-
-}
-
-#define CLK_GATE_W_MSK0 (0xffff)
-#define CLK_GATE_W_MSK1 (0xff9f) //defult:(0xffff); ignore usb:(0xff9f) G1_[6:5]
-#define CLK_GATE_W_MSK2 (0xffff)
-#define CLK_GATE_W_MSK3 (0xff9f) //defult:(0xff9f); ignore use:(0xff9f) G3_[6]
-#define CLK_GATE_W_MSK4 (0xffff)
-#define CLK_GATE_W_MSK5 (0xdfff) //defult:(0xffff); ignore usb:(0xdfff) G5_[13]
-#define CLK_GATE_W_MSK6 (0xffff)
-#define CLK_GATE_W_MSK7 (0xffe7) //defult:(0xffff); ignore usb:(0xffe7) G7_[4:3]
-#define CLK_GATE_W_MSK8 (0x01ff)
-#define CLK_GATE_W_MSK9 (0x07ff)
-static u32 __sramdata clkgt_regs_sram[CRU_CLKGATES_CON_CNT];
-static u32 __sramdata sram_grf_uoc0_con0_status;
-
-static void __sramfunc rk_pm_soc_sram_clk_gating(void)
-{
- int i;
-
- #if defined(CONFIG_ARCH_RK3188) && (CONFIG_RK_DEBUG_UART == 2)
- #ifdef CONFIG_RK_USB_UART
- sram_grf_uoc0_con0_status = grf_readl(GRF_UOC0_CON0);
- grf_writel(0x03000000, GRF_UOC0_CON0);
- #endif
- #endif
-
-
- for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
- clkgt_regs_sram[i] = cru_readl(CRU_CLKGATES_CON(i));
- }
-#ifndef CONFIG_PHONE_INCALL_IS_SUSPEND
- gate_save_soc_clk(0
- | (1 << CLK_GATE_CORE_PERIPH)
- | (1 << CLK_GATE_ACLK_CPU)
- | (1 << CLK_GATE_HCLK_CPU)
- | (1 << CLK_GATE_PCLK_CPU)
- | (1 << CLK_GATE_ACLK_CORE)
- , clkgt_regs_sram[0], CRU_CLKGATES_CON(0), CLK_GATE_W_MSK0);
-
-#else
- if(rk30_phonecall_lowerpower() == 0){
- gate_save_soc_clk(0
- | (1 << CLK_GATE_CORE_PERIPH)
- | (1 << CLK_GATE_ACLK_CPU)
- | (1 << CLK_GATE_HCLK_CPU)
- | (1 << CLK_GATE_PCLK_CPU)
- | (1 << CLK_GATE_ACLK_CORE)
- , clkgt_regs_sram[0], CRU_CLKGATES_CON(0), CLK_GATE_W_MSK0);
- }else{
- gate_save_soc_clk(0
- | (1 << CLK_GATE_CORE_PERIPH)
- | (1 << CLK_GATE_ACLK_CPU)
- | (1 << CLK_GATE_HCLK_CPU)
- | (1 << CLK_GATE_PCLK_CPU)
- | (1 << CLK_GATE_ACLK_CORE)
-
-#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
- | (1 << CLK_GATE_I2S0_SRC)
- | (1 << CLK_GATE_I2S0_FRAC)
-#else
- |(1<<CLK_GATE_I2S0_FRAC)
- |(1<<CLK_GATE_I2S1)
- |(1<<CLK_GATE_I2S1_FRAC)
- |(1<<CLK_GATE_I2S2)
- |(1<<CLK_GATE_I2S2_FRAC)
-#endif
- , clkgt_regs_sram[0], CRU_CLKGATES_CON(0), CLK_GATE_W_MSK0);
-
- }
-#endif
- gate_save_soc_clk(0, clkgt_regs_sram[1], CRU_CLKGATES_CON(1), CLK_GATE_W_MSK1);
-
-#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
- if(((clkgt_regs_sram[8] >> CLK_GATE_PCLK_GPIO3% 16) & 0x01) == 0x01){
-#else
- if(((clkgt_regs_sram[8] >> CLK_GATE_PCLK_GPIO3% 16) & 0x03) == 0x03){
-#endif
- gate_save_soc_clk(0
- , clkgt_regs_sram[2], CRU_CLKGATES_CON(2), CLK_GATE_W_MSK2);
-
- }else{
- gate_save_soc_clk(0
- | (1 << CLK_GATE_PERIPH_SRC % 16)
- | (1 << CLK_GATE_PCLK_PERIPH % 16)
- , clkgt_regs_sram[2], CRU_CLKGATES_CON(2), CLK_GATE_W_MSK2);
- }
- gate_save_soc_clk(0
- #if 1 //for uart befor wfi
- | (1 << CLK_GATE_PCLK_PERI_AXI_MATRIX % 16)
- | (1 << CLK_GATE_ACLK_PERI_AXI_MATRIX % 16)
- | (1 << CLK_GATE_ACLK_PEI_NIU % 16)
- #endif
-
- | (1 << CLK_GATE_ACLK_STRC_SYS % 16)
- | (1 << CLK_GATE_ACLK_INTMEM % 16)
- #if !defined(CONFIG_ARCH_RK3188)
- | (1 << CLK_GATE_HCLK_L2MEM % 16)
- #else
- | (1 << CLK_GATE_HCLK_IMEM1 % 16)
- | (1 << CLK_GATE_HCLK_IMEM0 % 16)
- #endif
- , clkgt_regs_sram[4], CRU_CLKGATES_CON(4), CLK_GATE_W_MSK4);
-
- gate_save_soc_clk(0
- | (1 << CLK_GATE_PCLK_GRF % 16)
- | (1 << CLK_GATE_PCLK_PMU % 16)
- , clkgt_regs_sram[5], CRU_CLKGATES_CON(5), CLK_GATE_W_MSK5);
-#ifndef CONFIG_PHONE_INCALL_IS_SUSPEND
- gate_save_soc_clk(0, clkgt_regs_sram[7], CRU_CLKGATES_CON(7), CLK_GATE_W_MSK7);
-#else
- if(rk30_phonecall_lowerpower() == 0){
- gate_save_soc_clk(0, clkgt_regs_sram[7], CRU_CLKGATES_CON(7), CLK_GATE_W_MSK7);
- }else{
- gate_save_soc_clk(0
-#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
- | (1 << CLK_GATE_HCLK_I2S0_2CH % 16)
-#else
- | (1 <<CLK_GATE_HCLK_I2S0_2CH)
- | (1 <<CLK_GATE_HCLK_I2S1_2CH)
- | (1 <<CLK_GATE_HCLK_I2S_8CH)
-#endif
- , clkgt_regs_sram[7], CRU_CLKGATES_CON(7),CLK_GATE_W_MSK7);
- }
-#endif
- gate_save_soc_clk(0
- | (1 << CLK_GATE_CLK_L2C % 16)
- | (1 << CLK_GATE_ACLK_INTMEM0 % 16)
- | (1 << CLK_GATE_ACLK_INTMEM1 % 16)
- | (1 << CLK_GATE_ACLK_INTMEM2 % 16)
- | (1 << CLK_GATE_ACLK_INTMEM3 % 16)
- , clkgt_regs_sram[9], CRU_CLKGATES_CON(9), CLK_GATE_W_MSK9);
-
-}
-
-static void __sramfunc rk_pm_soc_sram_clk_ungating(void)
-{
- int i;
- for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
- cru_writel(clkgt_regs_sram[i] | 0xffff0000, CRU_CLKGATES_CON(i));
- }
-
- #if defined(CONFIG_ARCH_RK3188) && (CONFIG_RK_DEBUG_UART == 2)
- #ifdef CONFIG_RK_USB_UART
- grf_writel(0x03000000 | sram_grf_uoc0_con0_status, GRF_UOC0_CON0);
- #endif
- #endif
-}
-
-static u32 __sramdata sram_cru_clksel0_con, sram_cru_clksel10_con,sram_cru_mode_con;
-static void __sramfunc rk_pm_soc_sram_sys_clk_suspend(void)
-{
- sram_cru_clksel0_con = cru_readl(CRU_CLKSELS_CON(0));
-#ifdef CONFIG_CLK_SWITCH_TO_32K
- sram_cru_mode_con = cru_readl(CRU_MODE_CON);
- sram_cru_clksel10_con = cru_readl(CRU_CLKSELS_CON(10));
- cru_writel(PERI_ACLK_DIV_W_MSK | PERI_ACLK_DIV(4), CRU_CLKSELS_CON(10));
- cru_writel(CORE_CLK_DIV_W_MSK | CORE_CLK_DIV(4) | CPU_CLK_DIV_W_MSK | CPU_CLK_DIV(4), CRU_CLKSELS_CON(0));
- cru_writel(0
- | PLL_MODE_DEEP(APLL_ID)
- | PLL_MODE_DEEP(DPLL_ID)
- | PLL_MODE_DEEP(CPLL_ID)
- | PLL_MODE_DEEP(GPLL_ID)
- , CRU_MODE_CON);
- //board_pmu_suspend();
-#else
- cru_writel(CORE_CLK_DIV_W_MSK | CORE_CLK_DIV_MSK | CPU_CLK_DIV_W_MSK | CPU_CLK_DIV_MSK, CRU_CLKSELS_CON(0));
-#endif
-
-}
-
-static void __sramfunc rk_pm_soc_sram_sys_clk_resume(void)
-{
-
-#ifdef CONFIG_CLK_SWITCH_TO_32K
- cru_writel((0xffff<<16) | sram_cru_mode_con, CRU_MODE_CON);
- cru_writel(CORE_CLK_DIV_W_MSK | CPU_CLK_DIV_W_MSK | sram_cru_clksel0_con, CRU_CLKSELS_CON(0));
- cru_writel(PERI_ACLK_DIV_W_MSK | sram_cru_clksel10_con, CRU_CLKSELS_CON(10));
-#else
- cru_writel(CORE_CLK_DIV_W_MSK | CPU_CLK_DIV_W_MSK | sram_cru_clksel0_con, CRU_CLKSELS_CON(0));
-#endif
-
-}
-/*********************************code is in ddr ******************************************/
-
-static inline void rk_pm_soc_prepare(void)
-{
- // dump GPIO INTEN for debug
- rk30_pm_dump_inten();
-#if !(defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188))
- //gpio6_b7
- grf_writel(0xc0004000, 0x10c);
- cru_writel(0x07000000, CRU_MISC_CON);
-#endif
-
-#ifdef CONFIG_DDR_TEST
- // memory tester
- ddr_testmode();
-#endif
-}
-
-static inline void rk_pm_soc_finsh(void)
-{
- rk30_pm_dump_irq();
-}
-
-
-static u32 pmu_pwrdn_st;
-
-static inline void rk_pm_soc_pd_suspend(void)
-{
- pmu_pwrdn_st = pmu_readl(PMU_PWRDN_ST);
- rk30_pm_set_power_domain(pmu_pwrdn_st, false);
-}
-
-static inline void rk_pm_soc_pd_resume(void)
-{
- rk30_pm_set_power_domain(pmu_pwrdn_st, true);
-}
-
-
-static u32 clkgt_regs_first[CRU_CLKGATES_CON_CNT];
-static void rk_pm_soc_clk_gating_first(void)
-{
- int i;
-
- for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
- clkgt_regs_first[i] = cru_readl(CRU_CLKGATES_CON(i));
- }
-#ifndef CONFIG_PHONE_INCALL_IS_SUSPEND
- gate_save_soc_clk(0
- | (1 << CLK_GATE_CORE_PERIPH)
-#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
- | (1 << CLK_GATE_CPU_GPLL_PATH)
- | (1 << CLK_GATE_ACLK_CORE)
-#endif
- | (1 << CLK_GATE_DDRPHY)
- | (1 << CLK_GATE_ACLK_CPU)
- | (1 << CLK_GATE_HCLK_CPU)
- | (1 << CLK_GATE_PCLK_CPU)
- , clkgt_regs_first[0], CRU_CLKGATES_CON(0), CLK_GATE_W_MSK0);
-
-#else
- if(rk30_phonecall_lowerpower() == 0){
- gate_save_soc_clk(0
- | (1 << CLK_GATE_CORE_PERIPH)
-#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
- | (1 << CLK_GATE_CPU_GPLL_PATH)
- | (1 << CLK_GATE_ACLK_CORE)
-#endif
- | (1 << CLK_GATE_DDRPHY)
- | (1 << CLK_GATE_ACLK_CPU)
- | (1 << CLK_GATE_HCLK_CPU)
- | (1 << CLK_GATE_PCLK_CPU)
- , clkgt_regs_first[0], CRU_CLKGATES_CON(0), CLK_GATE_W_MSK0);
- }else{
- gate_save_soc_clk(0
- | (1 << CLK_GATE_CORE_PERIPH)
-#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
- | (1 << CLK_GATE_CPU_GPLL_PATH)
- | (1 << CLK_GATE_ACLK_CORE)
-#endif
- | (1 << CLK_GATE_DDRPHY)
- | (1 << CLK_GATE_ACLK_CPU)
- | (1 << CLK_GATE_HCLK_CPU)
- | (1 << CLK_GATE_PCLK_CPU)
-
-#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
- | (1 << CLK_GATE_I2S0_SRC)
- | (1 << CLK_GATE_I2S0_FRAC)
-#else
- |(1<<CLK_GATE_I2S0_FRAC)
- |(1<<CLK_GATE_I2S1)
- |(1<<CLK_GATE_I2S1_FRAC)
- |(1<<CLK_GATE_I2S2)
- |(1<<CLK_GATE_I2S2_FRAC)
-#endif
- , clkgt_regs_first[0], CRU_CLKGATES_CON(0), CLK_GATE_W_MSK0);
-
- }
-#endif
- gate_save_soc_clk(0
- | (1 << CLK_GATE_DDR_GPLL % 16)
- , clkgt_regs_first[1], CRU_CLKGATES_CON(1), CLK_GATE_W_MSK1);
- gate_save_soc_clk(0
- | (1 << CLK_GATE_PERIPH_SRC % 16)
- | (1 << CLK_GATE_PCLK_PERIPH % 16)
- | (1 << CLK_GATE_ACLK_PERIPH % 16)
- , clkgt_regs_first[2], CRU_CLKGATES_CON(2),CLK_GATE_W_MSK2 );
- gate_save_soc_clk(0, clkgt_regs_first[3], CRU_CLKGATES_CON(3),CLK_GATE_W_MSK3);
- gate_save_soc_clk(0
- | (1 << CLK_GATE_HCLK_PERI_AXI_MATRIX % 16)
- | (1 << CLK_GATE_PCLK_PERI_AXI_MATRIX % 16)
- | (1 << CLK_GATE_ACLK_CPU_PERI % 16)
- | (1 << CLK_GATE_ACLK_PERI_AXI_MATRIX % 16)
- | (1 << CLK_GATE_ACLK_PEI_NIU % 16)
- | (1 << CLK_GATE_HCLK_PERI_AHB_ARBI % 16)
- | (1 << CLK_GATE_HCLK_CPUBUS % 16)
- | (1 << CLK_GATE_ACLK_STRC_SYS % 16)
- | (1 << CLK_GATE_ACLK_INTMEM % 16)
-#if !defined(CONFIG_ARCH_RK3188)
- | (1 << CLK_GATE_HCLK_L2MEM % 16)
-#else
- | (1 << CLK_GATE_HCLK_IMEM1 % 16)
- | (1 << CLK_GATE_HCLK_IMEM0 % 16)
-#endif
- , clkgt_regs_first[4], CRU_CLKGATES_CON(4), CLK_GATE_W_MSK4);
- gate_save_soc_clk(0
- | (1 << CLK_GATE_PCLK_GRF % 16)
- | (1 << CLK_GATE_PCLK_PMU % 16)
- | (1 << CLK_GATE_PCLK_DDRUPCTL % 16)
- , clkgt_regs_first[5], CRU_CLKGATES_CON(5), CLK_GATE_W_MSK5);
- gate_save_soc_clk(0, clkgt_regs_first[6], CRU_CLKGATES_CON(6), CLK_GATE_W_MSK6);
-#ifndef CONFIG_PHONE_INCALL_IS_SUSPEND
- gate_save_soc_clk(0
- | (1 << CLK_GATE_PCLK_PWM01 % 16)
- | (1 << CLK_GATE_PCLK_PWM23 % 16)
- , clkgt_regs_first[7], CRU_CLKGATES_CON(7),CLK_GATE_W_MSK7);
-#else
- if(rk30_phonecall_lowerpower() == 0){
- gate_save_soc_clk(0
- | (1 << CLK_GATE_PCLK_PWM01 % 16)
- | (1 << CLK_GATE_PCLK_PWM23 % 16)
- , clkgt_regs_first[7], CRU_CLKGATES_CON(7),CLK_GATE_W_MSK7);
- }else{
- gate_save_soc_clk(0
- | (1 << CLK_GATE_PCLK_PWM01 % 16)
- | (1 << CLK_GATE_PCLK_PWM23 % 16)
-#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
- | (1 << CLK_GATE_HCLK_I2S0_2CH % 16)
-#else
- | (1 <<CLK_GATE_HCLK_I2S0_2CH% 16)
- | (1 <<CLK_GATE_HCLK_I2S1_2CH% 16)
- | (1 <<CLK_GATE_HCLK_I2S_8CH% 16)
-#endif
- , clkgt_regs_first[7], CRU_CLKGATES_CON(7),CLK_GATE_W_MSK7);
- }
-#endif
- gate_save_soc_clk(0 , clkgt_regs_first[8], CRU_CLKGATES_CON(8), CLK_GATE_W_MSK8);
- gate_save_soc_clk(0
- | (1 << CLK_GATE_CLK_L2C % 16)
- | (1 << CLK_GATE_PCLK_PUBL % 16)
- | (1 << CLK_GATE_ACLK_INTMEM0 % 16)
- | (1 << CLK_GATE_ACLK_INTMEM1 % 16)
- | (1 << CLK_GATE_ACLK_INTMEM2 % 16)
- | (1 << CLK_GATE_ACLK_INTMEM3 % 16)
- , clkgt_regs_first[9], CRU_CLKGATES_CON(9), CLK_GATE_W_MSK9);
-}
-
-static void rk_pm_soc_clk_ungating_first(void)
-{
- int i;
-
- for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
- cru_writel(clkgt_regs_first[i] | 0xffff0000, CRU_CLKGATES_CON(i));
- }
-}
-
-static u32 clk_sel0, clk_sel1, clk_sel10;
-static u32 cpll_con3;
-static u32 cru_mode_con;
-static void rk_pm_soc_pll_suspend(void)
-{
- cru_mode_con = cru_readl(CRU_MODE_CON);
-
- //cpll
- if(rk_pll_flag()==0)
- {
- cru_writel(PLL_MODE_SLOW(CPLL_ID), CRU_MODE_CON);
- cpll_con3 = cru_readl(PLL_CONS(CPLL_ID, 3));
- power_off_pll(CPLL_ID);
- }
-
- //apll
- clk_sel0 = cru_readl(CRU_CLKSELS_CON(0));
- clk_sel1 = cru_readl(CRU_CLKSELS_CON(1));
-
- cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
- /* To make sure aclk_cpu select apll before div effect */
- cru_writel(CPU_SEL_PLL_W_MSK | CPU_SEL_APLL
- | CORE_SEL_PLL_W_MSK | CORE_SEL_APLL
- , CRU_CLKSELS_CON(0));
- cru_writel(CORE_PERIPH_W_MSK | CORE_PERIPH_2
- | CORE_CLK_DIV_W_MSK | CORE_CLK_DIV(1)
- | CPU_CLK_DIV_W_MSK | CPU_CLK_DIV(1)
- , CRU_CLKSELS_CON(0));
- cru_writel(CORE_ACLK_W_MSK | CORE_ACLK_11
-#if !defined(CONFIG_ARCH_RK3188)
- | CPU_ACLK_W_MSK | CPU_ACLK_11
-#endif
- | ACLK_HCLK_W_MSK | ACLK_HCLK_11
- | ACLK_PCLK_W_MSK | ACLK_PCLK_11
- | AHB2APB_W_MSK | AHB2APB_11
- , CRU_CLKSELS_CON(1));
- power_off_pll(APLL_ID);
-
- //gpll
- if(rk_pll_flag()==0)
- {
- cru_writel(PLL_MODE_SLOW(GPLL_ID), CRU_MODE_CON);
- clk_sel10 = cru_readl(CRU_CLKSELS_CON(10));
- cru_writel(CRU_W_MSK_SETBITS(0, PERI_ACLK_DIV_OFF, PERI_ACLK_DIV_MASK)
- | CRU_W_MSK_SETBITS(0, PERI_HCLK_DIV_OFF, PERI_HCLK_DIV_MASK)
- | CRU_W_MSK_SETBITS(0, PERI_PCLK_DIV_OFF, PERI_PCLK_DIV_MASK)
- , CRU_CLKSELS_CON(10));
- power_off_pll(GPLL_ID);
- }
-
-}
-
-static void rk_pm_soc_pll_resume(void)
-{
-
- //gpll
- if(rk_pll_flag()==0)
- {
- cru_writel(0xffff0000 | clk_sel10, CRU_CLKSELS_CON(10));
- power_on_pll(GPLL_ID);
- cru_writel((PLL_MODE_MSK(GPLL_ID) << 16) | (PLL_MODE_MSK(GPLL_ID) & cru_mode_con), CRU_MODE_CON);
- }
- //apll
- cru_writel(0xffff0000 | clk_sel1, CRU_CLKSELS_CON(1));
- /* To make sure aclk_cpu select gpll after div effect */
- cru_writel((0xffff0000 & ~CPU_SEL_PLL_W_MSK & ~CORE_SEL_PLL_W_MSK) | clk_sel0, CRU_CLKSELS_CON(0));
- cru_writel(CPU_SEL_PLL_W_MSK | CORE_SEL_PLL_W_MSK | clk_sel0, CRU_CLKSELS_CON(0));
- power_on_pll(APLL_ID);
- cru_writel((PLL_MODE_MSK(APLL_ID) << 16) | (PLL_MODE_MSK(APLL_ID) & cru_mode_con), CRU_MODE_CON);
-
- //cpll
- if(rk_pll_flag()==0)
- {
- if (((cpll_con3 & PLL_PWR_DN_MSK) == PLL_PWR_ON) &&
- ((PLL_MODE_NORM(CPLL_ID) & PLL_MODE_MSK(CPLL_ID)) == (cru_mode_con & PLL_MODE_MSK(CPLL_ID)))) {
- power_on_pll(CPLL_ID);
- }
- cru_writel((PLL_MODE_MSK(CPLL_ID) << 16) | (PLL_MODE_MSK(CPLL_ID) & cru_mode_con), CRU_MODE_CON);
- }
-
-
-}
-
-/*********************************pm control******************************************/
-
-enum rk_soc_pm_ctr_flags_offset {
-
- RK_PM_CTR_NO_PD=0,
- RK_PM_CTR_NO_CLK_GATING,
- RK_PM_CTR_NO_PLL,
- RK_PM_CTR_NO_VOLT,
- RK_PM_CTR_NO_GPIO,
- RK_PM_CTR_NO_SRAM,
- RK_PM_CTR_NO_DDR,
- RK_PM_CTR_NO_SYS_CLK,
- RK_PM_CTR_NO_PMIC,
-
- RK_PM_CTR_RET_DIRT=24,
- RK_PM_CTR_SRAM_NO_WFI,
- RK_PM_CTR_WAKE_UP_KEY,
- RK_PM_CTR_ALL=31,
-};
-
-struct rk_soc_pm_info_st {
- int offset;
- char *name;
-};
-
-#define RK_SOC_PM_HELP_(id,NAME)\
- {\
- .offset= RK_PM_CTR_##id,\
- .name= NAME,\
- }
-
-struct rk_soc_pm_info_st rk_soc_pm_helps[]={
- RK_SOC_PM_HELP_(NO_PD,"pd is not power dn"),
- RK_SOC_PM_HELP_(NO_CLK_GATING,"clk is not gating"),
- RK_SOC_PM_HELP_(NO_PLL,"pll is not power dn"),
- RK_SOC_PM_HELP_(NO_VOLT,"volt is not set suspend"),
- RK_SOC_PM_HELP_(NO_GPIO,"gpio is not control "),
- //RK_SOC_PM_HELP_(NO_SRAM,"not enter sram code"),
- RK_SOC_PM_HELP_(NO_DDR,"ddr is not reflash"),
- RK_SOC_PM_HELP_(NO_PMIC,"pmic is not suspend"),
- RK_SOC_PM_HELP_(RET_DIRT,"sys return from pm_enter directly"),
- RK_SOC_PM_HELP_(SRAM_NO_WFI,"sys is not runing wfi in sram"),
- RK_SOC_PM_HELP_(WAKE_UP_KEY,"send a power key to wake up lcd"),
-};
-
-ssize_t rk_soc_pm_helps_sprintf(char *buf)
-{
- char *s = buf;
- int i;
-
- for(i=0;i<ARRAY_SIZE(rk_soc_pm_helps);i++)
- {
- s += sprintf(s, "bit(%d): %s\n", rk_soc_pm_helps[i].offset,rk_soc_pm_helps[i].name);
- }
-
- return (s-buf);
-}
-
-void rk_soc_pm_helps_printk(void)
-{
- int i;
- printk("**************rk_suspend_ctr_bits bits help***********:\n");
- for(i=0;i<ARRAY_SIZE(rk_soc_pm_helps);i++)
- {
- printk("bit(%d): %s\n", rk_soc_pm_helps[i].offset,rk_soc_pm_helps[i].name);
- }
-}
-
-
-// pm enter return directly
-#define RK_SUSPEND_RET_DIRT_BITS ((1<<RK_PM_CTR_RET_DIRT))
-// not enter rk30_suspend
-#define RK_NO_SUSPEND_CTR_BITS ((1<<RK_PM_CTR_NO_PLL))
-//not running wfi in sram code
-#define RK_SUSPEND_NO_SRAM_WFI_BITS ((1<<RK_PM_CTR_SRAM_NO_WFI))
-
-
-static u32 __sramdata rk_soc_pm_ctr_flags_sram=0;
-static u32 rk_soc_pm_ctr_flags=0;
-
-static int arm_suspend_volt = 0;
-static int logic_suspend_volt = 0;
-
-static int __init early_param_rk_soc_pm_ctr(char *str)
-{
- get_option(&str, &rk_soc_pm_ctr_flags);
-
- printk("********rk_suspend_ctr_bits information is following:*********\n");
- printk("rk_suspend_ctr_bits=%x\n",rk_soc_pm_ctr_flags);
- if(rk_soc_pm_ctr_flags)
- {
- rk_soc_pm_helps_printk();
- }
- printk("********rk_suspend_ctr_bits information end*********\n");
- return 0;
-}
-
-early_param("rk_suspend_ctr_bits", early_param_rk_soc_pm_ctr);
-
-
-void rk_soc_pm_ctr_bits_set(u32 flags)
-{
- rk_soc_pm_ctr_flags = flags;
-
-}
-u32 rk_soc_pm_ctr_bits_get(void)
-{
- return rk_soc_pm_ctr_flags;
-}
-
-void rk_soc_pm_ctr_bit_set(int offset)
-{
- rk_soc_pm_ctr_flags|=(1<<offset);
-}
-void inline rk_soc_pm_ctr_bit_clear(int offset)
-{
- rk_soc_pm_ctr_flags&=~(1<<offset);
-}
-
-u32 inline rk_soc_pm_ctr_bits_check(int bits)
-{
- return (rk_soc_pm_ctr_flags_sram&(bits));
-}
-
-#define RK_SOC_PM_CTR_FUN(ctr,fun) \
- if(!(rk_soc_pm_ctr_bits_check((1<<RK_PM_CTR_##ctr))))\
- (fun)()
-
-void rk_soc_pm_ctr_bits_prepare(void)
-{
-
- rk_soc_pm_ctr_flags_sram=rk_soc_pm_ctr_flags;
- if(rk_soc_pm_ctr_flags_sram&(1<<RK_PM_CTR_NO_PLL))
- {
- rk_soc_pm_ctr_flags_sram|=(1<<RK_PM_CTR_NO_VOLT);
- }
-
-}
-
-
-static int __init set_arm_suspend_volt(char *str)
-{
- get_option(&str, &arm_suspend_volt);
- printk("rk_suspend_arm_volt=%dmV\n", arm_suspend_volt);
- return 0;
-}
-early_param("rk_suspend_arm_volt", set_arm_suspend_volt);
-
-static int __init set_logic_suspend_volt(char *str)
-{
- get_option(&str, &logic_suspend_volt);
- printk("rk_suspend_logic_volt=%dmV\n", logic_suspend_volt);
- return 0;
-}
-early_param("rk_suspend_logic_volt", set_logic_suspend_volt);
-
-
-
-static int __init pm_suspend_volt_seting(void)
-{
- struct regulator *regulator;
-
- printk("pmic set pm_suspend_volt:\n");
- if (arm_suspend_volt){
- regulator = regulator_get(NULL, "vdd_cpu");
- if (IS_ERR(regulator)){
- printk("%s:get vdd_cpu regulator err\n", __func__);
- return 0;
- }
- regulator_set_suspend_voltage(regulator, arm_suspend_volt);
- regulator_put(regulator);
- }
-
- if (logic_suspend_volt){
- regulator = regulator_get(NULL, "vdd_core");
- if (IS_ERR(regulator)){
- printk("%s:get vdd_core regulator err\n", __func__);
- return 0;
- }
- regulator_set_suspend_voltage(regulator, logic_suspend_volt);
- regulator_put(regulator);
- }
- return 0;
-}
-
-device_initcall_sync(pm_suspend_volt_seting);
-
-
-/*********************************pm main function******************************************/
-
-static void __sramfunc rk30_sram_suspend(void)
-{
-
- sram_printch('5');
-
- RK_SOC_PM_CTR_FUN(NO_DDR,ddr_suspend);
- sram_printch('6');
- RK_SOC_PM_CTR_FUN(NO_VOLT,rk_pm_soc_sram_volt_suspend);
- sram_printch('7');
- RK_SOC_PM_CTR_FUN(NO_CLK_GATING,rk_pm_soc_sram_clk_gating);
- RK_SOC_PM_CTR_FUN(NO_SYS_CLK,rk_pm_soc_sram_sys_clk_suspend);
- RK_SOC_PM_CTR_FUN(NO_PMIC,board_pmu_suspend);
- if(!rk_soc_pm_ctr_bits_check(RK_SUSPEND_NO_SRAM_WFI_BITS))
- {
- dsb();
- wfi();
- }
-
- RK_SOC_PM_CTR_FUN(NO_PMIC,board_pmu_resume);
- RK_SOC_PM_CTR_FUN(NO_SYS_CLK,rk_pm_soc_sram_sys_clk_resume);
- RK_SOC_PM_CTR_FUN(NO_CLK_GATING,rk_pm_soc_sram_clk_ungating);
- sram_printch('7');
- RK_SOC_PM_CTR_FUN(NO_VOLT,rk_pm_soc_sram_volt_resume);
- sram_printch('6');
- RK_SOC_PM_CTR_FUN(NO_DDR,ddr_resume);
- sram_printch('5');
-
-}
-
-static void noinline rk30_suspend(void)
-{
- DDR_SAVE_SP(save_sp);
- rk30_sram_suspend();
- DDR_RESTORE_SP(save_sp);
-}
-
-static int rk30_pm_enter(suspend_state_t state)
-{
- rk_soc_pm_ctr_bits_prepare();
-
- if(rk_soc_pm_ctr_bits_check(RK_SUSPEND_RET_DIRT_BITS))
- {
- printk("%s return directly\n",__FUNCTION__);
- return 0;
- }
-
- rk_pm_soc_prepare();
-
- printk(KERN_DEBUG "pm: ");
- pm_log = true;
- sram_log_reset();
- sram_printch('0');
-
- RK_SOC_PM_CTR_FUN(NO_PD,rk_pm_soc_pd_suspend);
-
- sram_printch('1');
- local_fiq_disable();
-
- RK_SOC_PM_CTR_FUN(NO_CLK_GATING,rk_pm_soc_clk_gating_first);
-
- sram_printch('2');
- RK_SOC_PM_CTR_FUN(NO_PLL,rk_pm_soc_pll_suspend);
-
- sram_printch('3');
-
- RK_SOC_PM_CTR_FUN(NO_VOLT,rk30_pwm_suspend_voltage_set);
- RK_SOC_PM_CTR_FUN(NO_GPIO,board_gpio_suspend);
-
-
- interface_ctr_reg_pread();
-
- sram_printch('4');
- pm_log = false;
-
- if(!rk_soc_pm_ctr_bits_check(RK_NO_SUSPEND_CTR_BITS))
- rk30_suspend();
-
-
- pm_log = true;
- sram_printch('4');
-
- RK_SOC_PM_CTR_FUN(NO_GPIO,board_gpio_resume);
- RK_SOC_PM_CTR_FUN(NO_VOLT,rk30_pwm_resume_voltage_set);
-
- sram_printch('3');
-
- RK_SOC_PM_CTR_FUN(NO_PLL,rk_pm_soc_pll_resume);
-
- sram_printch('2');
-
- RK_SOC_PM_CTR_FUN(NO_CLK_GATING,rk_pm_soc_clk_ungating_first);
-
- local_fiq_enable();
- sram_printch('1');
-
- RK_SOC_PM_CTR_FUN(NO_PD,rk_pm_soc_pd_resume);
-
- sram_printch('0');
- pm_log = false;
- printk(KERN_CONT "\n");
- sram_printch('\n');
- rk_pm_soc_finsh();
- return 0;
-}
-
-static int rk30_pm_prepare(void)
-{
- /* disable entering idle by disable_hlt() */
- disable_hlt();
- return 0;
-}
-
-static void rk30_pm_finish(void)
-{
- enable_hlt();
-#ifdef CONFIG_KEYS_RK29
- if(rk_soc_pm_ctr_bits_check(1<<RK_PM_CTR_WAKE_UP_KEY))
- {
- rk28_send_wakeup_key();
- printk("rk30_pm_finish rk28_send_wakeup_key\n");
- }
-#endif
-}
-
-static struct platform_suspend_ops rk30_pm_ops = {
- .enter = rk30_pm_enter,
- .valid = suspend_valid_only_mem,
- .prepare = rk30_pm_prepare,
- .finish = rk30_pm_finish,
-};
-
-static int __init rk30_pm_init(void)
-{
- suspend_set_ops(&rk30_pm_ops);
-#ifdef CONFIG_EARLYSUSPEND
- pm_set_vt_switch(0); /* disable vt switch while suspend */
-#endif
- rk3188plus_soc = soc_is_rk3188plus();
- return 0;
-}
-__initcall(rk30_pm_init);
-
+++ /dev/null
-#include <linux/module.h>
-#include <linux/spinlock.h>
-#include <mach/pmu.h>
-#include <mach/sram.h>
-#include <mach/cpu_axi.h>
-
-static void __sramfunc pmu_set_power_domain_sram(enum pmu_power_domain pd, bool on)
-{
- u32 mask = 1 << pd;
- u32 val = readl_relaxed(RK30_PMU_BASE + PMU_PWRDN_CON);
-
- if (on)
- val &= ~mask;
- else
- val |= mask;
- writel_relaxed(val, RK30_PMU_BASE + PMU_PWRDN_CON);
- dsb();
-
- while (pmu_power_domain_is_on(pd) != on)
- ;
-}
-
-static noinline void do_pmu_set_power_domain(enum pmu_power_domain pd, bool on)
-{
- static unsigned long save_sp;
-
- DDR_SAVE_SP(save_sp);
- pmu_set_power_domain_sram(pd, on);
- DDR_RESTORE_SP(save_sp);
-}
-
-/*
- * software should power down or power up power domain one by one. Power down or
- * power up multiple power domains simultaneously will result in chip electric current
- * change dramatically which will affect the chip function.
- */
-static DEFINE_SPINLOCK(pmu_pd_lock);
-static u32 lcdc0_qos[CPU_AXI_QOS_NUM_REGS];
-static u32 lcdc1_qos[CPU_AXI_QOS_NUM_REGS];
-static u32 cif0_qos[CPU_AXI_QOS_NUM_REGS];
-static u32 cif1_qos[CPU_AXI_QOS_NUM_REGS];
-static u32 ipp_qos[CPU_AXI_QOS_NUM_REGS];
-static u32 rga_qos[CPU_AXI_QOS_NUM_REGS];
-static u32 gpu_qos[CPU_AXI_QOS_NUM_REGS];
-static u32 vpu_qos[CPU_AXI_QOS_NUM_REGS];
-
-void pmu_set_power_domain(enum pmu_power_domain pd, bool on)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&pmu_pd_lock, flags);
- if (pmu_power_domain_is_on(pd) == on) {
- spin_unlock_irqrestore(&pmu_pd_lock, flags);
- return;
- }
- if (!on) {
- /* if power down, idle request to NIU first */
- if (pd == PD_VIO) {
- CPU_AXI_SAVE_QOS(lcdc0_qos, LCDC0);
- CPU_AXI_SAVE_QOS(lcdc1_qos, LCDC1);
- CPU_AXI_SAVE_QOS(cif0_qos, CIF0);
- CPU_AXI_SAVE_QOS(cif1_qos, CIF1);
- CPU_AXI_SAVE_QOS(ipp_qos, IPP);
- CPU_AXI_SAVE_QOS(rga_qos, RGA);
- pmu_set_idle_request(IDLE_REQ_VIO, true);
- } else if (pd == PD_VIDEO) {
- CPU_AXI_SAVE_QOS(vpu_qos, VPU);
- pmu_set_idle_request(IDLE_REQ_VIDEO, true);
- } else if (pd == PD_GPU) {
- CPU_AXI_SAVE_QOS(gpu_qos, GPU);
- pmu_set_idle_request(IDLE_REQ_GPU, true);
- }
- }
- do_pmu_set_power_domain(pd, on);
- if (on) {
- /* if power up, idle request release to NIU */
- if (pd == PD_VIO) {
- pmu_set_idle_request(IDLE_REQ_VIO, false);
- CPU_AXI_RESTORE_QOS(lcdc0_qos, LCDC0);
- CPU_AXI_RESTORE_QOS(lcdc1_qos, LCDC1);
- CPU_AXI_RESTORE_QOS(cif0_qos, CIF0);
- CPU_AXI_RESTORE_QOS(cif1_qos, CIF1);
- CPU_AXI_RESTORE_QOS(ipp_qos, IPP);
- CPU_AXI_RESTORE_QOS(rga_qos, RGA);
- } else if (pd == PD_VIDEO) {
- pmu_set_idle_request(IDLE_REQ_VIDEO, false);
- CPU_AXI_RESTORE_QOS(vpu_qos, VPU);
- } else if (pd == PD_GPU) {
- pmu_set_idle_request(IDLE_REQ_GPU, false);
- CPU_AXI_RESTORE_QOS(gpu_qos, GPU);
- }
- }
- spin_unlock_irqrestore(&pmu_pd_lock, flags);
-}
-EXPORT_SYMBOL(pmu_set_power_domain);
-
-static DEFINE_SPINLOCK(pmu_misc_con1_lock);
-
-void pmu_set_idle_request(enum pmu_idle_req req, bool idle)
-{
- u32 idle_mask = 1 << (26 - req);
- u32 idle_target = idle << (26 - req);
- u32 ack_mask = 1 << (31 - req);
- u32 ack_target = idle << (31 - req);
- u32 mask = 1 << (req + 1);
- u32 val;
- unsigned long flags;
-
-#if defined(CONFIG_ARCH_RK3188)
- if (req == IDLE_REQ_CORE) {
- idle_mask = 1 << 15;
- idle_target = idle << 15;
- ack_mask = 1 << 18;
- ack_target = idle << 18;
- } else if (req == IDLE_REQ_DMA) {
- idle_mask = 1 << 14;
- idle_target = idle << 14;
- ack_mask = 1 << 17;
- ack_target = idle << 17;
- }
-#endif
-
- spin_lock_irqsave(&pmu_misc_con1_lock, flags);
- val = readl_relaxed(RK30_PMU_BASE + PMU_MISC_CON1);
- if (idle)
- val |= mask;
- else
- val &= ~mask;
- writel_relaxed(val, RK30_PMU_BASE + PMU_MISC_CON1);
- dsb();
-
- while ((readl_relaxed(RK30_PMU_BASE + PMU_PWRDN_ST) & ack_mask) != ack_target)
- ;
- while ((readl_relaxed(RK30_PMU_BASE + PMU_PWRDN_ST) & idle_mask) != idle_target)
- ;
- spin_unlock_irqrestore(&pmu_misc_con1_lock, flags);
-}
-EXPORT_SYMBOL(pmu_set_idle_request);
+++ /dev/null
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <mach/system.h>
-#include <linux/string.h>
-#include <mach/cru.h>
-#include <mach/iomux.h>
-#include <mach/loader.h>
-#include <mach/board.h>
-#include <mach/pmu.h>
-
-static bool is_panic = false;
-
-static int panic_event(struct notifier_block *this, unsigned long event, void *ptr)
-{
- is_panic = true;
- return NOTIFY_DONE;
-}
-
-static struct notifier_block panic_block = {
- .notifier_call = panic_event,
-};
-
-static int __init arch_reset_init(void)
-{
- atomic_notifier_chain_register(&panic_notifier_list, &panic_block);
- return 0;
-}
-core_initcall(arch_reset_init);
-
-static void rk30_arch_reset(char mode, const char *cmd)
-{
- u32 boot_flag = 0;
- u32 boot_mode = BOOT_MODE_REBOOT;
-
- if (cmd) {
- if (!strcmp(cmd, "loader") || !strcmp(cmd, "bootloader"))
- boot_flag = SYS_LOADER_REBOOT_FLAG + BOOT_LOADER;
- else if(!strcmp(cmd, "recovery"))
- boot_flag = SYS_LOADER_REBOOT_FLAG + BOOT_RECOVER;
- else if (!strcmp(cmd, "charge"))
- boot_mode = BOOT_MODE_CHARGE;
- } else {
- if (is_panic)
- boot_mode = BOOT_MODE_PANIC;
- }
-#ifndef RK30_PMU_BASE
- writel_relaxed(boot_flag, RK30_GRF_BASE + GRF_OS_REG4); // for loader
- writel_relaxed(boot_mode, RK30_GRF_BASE + GRF_OS_REG5); // for linux
-#else
- writel_relaxed(boot_flag, RK30_PMU_BASE + PMU_SYS_REG0); // for loader
- writel_relaxed(boot_mode, RK30_PMU_BASE + PMU_SYS_REG1); // for linux
-#endif
- dsb();
-
- /* restore clk_cpu:aclk_cpu to default value for RK3168 */
-#if defined(CONFIG_ARCH_RK3066B)
- writel_relaxed(0x00070001 , RK30_CRU_BASE + CRU_CLKSELS_CON(1));
-#endif
-
- /* disable remap */
- writel_relaxed(1 << (12 + 16), RK30_GRF_BASE + GRF_SOC_CON0);
- /* pll enter slow mode */
- writel_relaxed(PLL_MODE_SLOW(APLL_ID) | PLL_MODE_SLOW(CPLL_ID) | PLL_MODE_SLOW(GPLL_ID), RK30_CRU_BASE + CRU_MODE_CON);
- dsb();
- writel_relaxed(0xeca8, RK30_CRU_BASE + CRU_GLB_SRST_SND);
- dsb();
-}
-
-void (*arch_reset)(char, const char *) = rk30_arch_reset;
+++ /dev/null
-/* linux/arch/arm/mach-rk30/timer.c
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/init.h>
-#include <linux/time.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/clk.h>
-#include <linux/clockchips.h>
-#include <linux/io.h>
-
-#include <asm/localtimer.h>
-#include <asm/sched_clock.h>
-#include <asm/mach/time.h>
-
-#define TIMER_LOAD_COUNT 0x0000
-#define TIMER_CUR_VALUE 0x0004
-#define TIMER_CONTROL_REG 0x0008
-#define TIMER_EOI 0x000C
-#define TIMER_INT_STATUS 0x0010
-
-#define TIMER_DISABLE 6
-#define TIMER_ENABLE 3
-#define TIMER_ENABLE_FREE_RUNNING 5
-
-static inline void timer_write(u32 n, u32 v, u32 offset)
-{
- void __iomem* base = (n == 0) ? RK30_TIMER0_BASE : (n == 1) ? RK30_TIMER1_BASE : RK30_TIMER2_BASE;
- void __iomem* addr = base + offset;
- __raw_writel(v, addr);
- dsb();
-}
-
-static inline u32 timer_read(u32 n, u32 offset)
-{
- void __iomem* base = (n == 0) ? RK30_TIMER0_BASE : (n == 1) ? RK30_TIMER1_BASE : RK30_TIMER2_BASE;
- void __iomem* addr = base + offset;
- return __raw_readl(addr);
-}
-
-#define RK_TIMER_ENABLE(n) timer_write(n, TIMER_ENABLE, TIMER_CONTROL_REG)
-#define RK_TIMER_ENABLE_FREE_RUNNING(n) timer_write(n, TIMER_ENABLE_FREE_RUNNING, TIMER_CONTROL_REG)
-#define RK_TIMER_DISABLE(n) timer_write(n, TIMER_DISABLE, TIMER_CONTROL_REG)
-
-#define RK_TIMER_SETCOUNT(n, count) timer_write(n, count, TIMER_LOAD_COUNT)
-#define RK_TIMER_GETCOUNT(n) timer_read(n, TIMER_LOAD_COUNT)
-
-#define RK_TIMER_READVALUE(n) timer_read(n, TIMER_CUR_VALUE)
-#define RK_TIMER_INT_CLEAR(n) timer_read(n, TIMER_EOI)
-
-#define RK_TIMER_INT_STATUS(n) timer_read(n, TIMER_INT_STATUS)
-
-#define TIMER_CLKEVT 0 /* timer0 */
-#define IRQ_NR_TIMER_CLKEVT IRQ_TIMER0
-#define TIMER_CLKEVT_NAME "timer0"
-
-#define TIMER_CLKSRC 1 /* timer1 */
-#define IRQ_NR_TIMER_CLKSRC IRQ_TIMER1
-#define TIMER_CLKSRC_NAME "timer1"
-
-static inline u32 rk30_timer_read_current_value(u32 n)
-{
- unsigned long flags;
- u32 v[3];
- int loop = 100;
-
- do {
- local_irq_save(flags);
- v[0] = RK_TIMER_READVALUE(n);
- v[1] = RK_TIMER_READVALUE(n);
- v[2] = RK_TIMER_READVALUE(n);
- local_irq_restore(flags);
- if ((v[0] >= v[1]) && ((v[0] - v[1]) < 24)
- && (v[1] >= v[2]) && ((v[1] - v[2]) < 24))
- break;
- } while (loop--);
-
- return v[1];
-}
-
-static int rk30_timer_set_next_event(unsigned long cycles, struct clock_event_device *evt)
-{
- do {
- RK_TIMER_DISABLE(TIMER_CLKEVT);
- RK_TIMER_SETCOUNT(TIMER_CLKEVT, cycles);
- RK_TIMER_ENABLE(TIMER_CLKEVT);
- } while (rk30_timer_read_current_value(TIMER_CLKEVT) > cycles);
- return 0;
-}
-
-static void rk30_timer_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
-{
- switch (mode) {
- case CLOCK_EVT_MODE_PERIODIC:
- rk30_timer_set_next_event(24000000 / HZ - 1, evt);
- break;
- case CLOCK_EVT_MODE_RESUME:
- case CLOCK_EVT_MODE_ONESHOT:
- break;
- case CLOCK_EVT_MODE_UNUSED:
- case CLOCK_EVT_MODE_SHUTDOWN:
- RK_TIMER_DISABLE(TIMER_CLKEVT);
- break;
- }
-}
-
-static struct clock_event_device rk30_timer_clockevent = {
- .name = TIMER_CLKEVT_NAME,
- .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
- .rating = 200,
- .set_next_event = rk30_timer_set_next_event,
- .set_mode = rk30_timer_set_mode,
-};
-
-static irqreturn_t rk30_timer_clockevent_interrupt(int irq, void *dev_id)
-{
- struct clock_event_device *evt = dev_id;
-
- RK_TIMER_INT_CLEAR(TIMER_CLKEVT);
- if (evt->mode == CLOCK_EVT_MODE_ONESHOT)
- RK_TIMER_DISABLE(TIMER_CLKEVT);
-
- evt->event_handler(evt);
-
- return IRQ_HANDLED;
-}
-
-static struct irqaction rk30_timer_clockevent_irq = {
- .name = TIMER_CLKEVT_NAME,
- .flags = IRQF_DISABLED | IRQF_TIMER,
- .handler = rk30_timer_clockevent_interrupt,
- .irq = IRQ_NR_TIMER_CLKEVT,
- .dev_id = &rk30_timer_clockevent,
-};
-
-static __init int rk30_timer_init_clockevent(void)
-{
- struct clock_event_device *ce = &rk30_timer_clockevent;
- struct clk *clk = clk_get(NULL, TIMER_CLKEVT_NAME);
- struct clk *pclk = clk_get(NULL, "pclk_" TIMER_CLKEVT_NAME);
-
- clk_enable(pclk);
- clk_enable(clk);
-
- RK_TIMER_DISABLE(TIMER_CLKEVT);
-
- setup_irq(rk30_timer_clockevent_irq.irq, &rk30_timer_clockevent_irq);
-
- ce->irq = rk30_timer_clockevent_irq.irq;
- ce->cpumask = cpu_all_mask;
- clockevents_config_and_register(ce, 24000000, 0xF, 0xFFFFFFFF);
-
- return 0;
-}
-
-static cycle_t rk30_timer_read(struct clocksource *cs)
-{
- return ~rk30_timer_read_current_value(TIMER_CLKSRC);
-}
-
-/*
- * Constants generated by clocksource_hz2mult(24000000, 26).
- * This gives a resolution of about 41ns and a wrap period of about 178s.
- */
-#define MULT 2796202667u
-#define SHIFT 26
-#define MASK (u32)~0
-
-static struct clocksource rk30_timer_clocksource = {
- .name = TIMER_CLKSRC_NAME,
- .rating = 200,
- .read = rk30_timer_read,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-static void __init rk30_timer_init_clocksource(void)
-{
- static char err[] __initdata = KERN_ERR "%s: can't register clocksource!\n";
- struct clocksource *cs = &rk30_timer_clocksource;
- struct clk *clk = clk_get(NULL, TIMER_CLKSRC_NAME);
- struct clk *pclk = clk_get(NULL, "pclk_" TIMER_CLKSRC_NAME);
-
- clk_enable(pclk);
- clk_enable(clk);
-
- RK_TIMER_DISABLE(TIMER_CLKSRC);
- clk_disable(clk);
- RK_TIMER_SETCOUNT(TIMER_CLKSRC, 0xFFFFFFFF);
- RK_TIMER_ENABLE_FREE_RUNNING(TIMER_CLKSRC);
- clk_enable(clk);
-
- if (clocksource_register_hz(cs, 24000000))
- printk(err, cs->name);
-}
-
-#ifdef CONFIG_HAVE_SCHED_CLOCK
-static DEFINE_CLOCK_DATA(cd);
-
-unsigned long long notrace sched_clock(void)
-{
- u32 cyc = ~rk30_timer_read_current_value(TIMER_CLKSRC);
- return cyc_to_fixed_sched_clock(&cd, cyc, MASK, MULT, SHIFT);
-}
-
-static void notrace rk30_update_sched_clock(void)
-{
- u32 cyc = ~rk30_timer_read_current_value(TIMER_CLKSRC);
- update_sched_clock(&cd, cyc, MASK);
-}
-
-static void __init rk30_sched_clock_init(void)
-{
- init_fixed_sched_clock(&cd, rk30_update_sched_clock, 32, 24000000, MULT, SHIFT);
-}
-#endif
-
-static void __init rk30_timer_init(void)
-{
-#ifdef CONFIG_HAVE_ARM_TWD
- twd_base = RK30_PTIMER_BASE;
-#endif
- rk30_timer_init_clocksource();
- rk30_timer_init_clockevent();
-#ifdef CONFIG_HAVE_SCHED_CLOCK
- rk30_sched_clock_init();
-#endif
-}
-
-struct sys_timer rk30_timer = {
- .init = rk30_timer_init
-};
-
+++ /dev/null
-/*
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License.
-*/
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/slab.h>
-
-#define TSADC_DATA 0x00
-#define TSADC_DATA_MASK 0xfff
-
-#define TSADC_STAS 0x04
-#define TSADC_STAS_BUSY (1 << 0)
-#define TSADC_STAS_BUSY_MASK (1 << 0)
-
-#define TSADC_CTRL 0x08
-#define TSADC_CTRL_CH(ch) ((ch) << 0)
-#define TSADC_CTRL_POWER_UP (1 << 3)
-#define TSADC_CTRL_START (1 << 4)
-#define TSADC_CTRL_IRQ_ENABLE (1 << 5)
-#define TSADC_CTRL_IRQ_STATUS (1 << 6)
-
-#define TSADC_DLY_PU_SOC 0x0C
-
-#define TSADC_CLK_RATE 50000 /* 50KHz */
-
-struct tsadc_table
-{
- int code;
- int temp;
-};
-
-static const struct tsadc_table table[] =
-{
- {TSADC_DATA_MASK, -40},
-
- {3800, -40},
- {3792, -35},
- {3783, -30},
- {3774, -25},
- {3765, -20},
- {3756, -15},
- {3747, -10},
- {3737, -5},
- {3728, 0},
- {3718, 5},
-
- {3708, 10},
- {3698, 15},
- {3688, 20},
- {3678, 25},
- {3667, 30},
- {3656, 35},
- {3645, 40},
- {3634, 45},
- {3623, 50},
- {3611, 55},
-
- {3600, 60},
- {3588, 65},
- {3575, 70},
- {3563, 75},
- {3550, 80},
- {3537, 85},
- {3524, 90},
- {3510, 95},
- {3496, 100},
- {3482, 105},
-
- {3467, 110},
- {3452, 115},
- {3437, 120},
- {3421, 125},
-
- {0, 125},
-};
-
-struct rk30_tsadc_device {
- void __iomem *regs;
- struct clk *clk;
- struct clk *pclk;
- struct resource *ioarea;
-};
-
-static struct rk30_tsadc_device *g_dev;
-
-static u32 tsadc_readl(u32 offset)
-{
- return readl_relaxed(g_dev->regs + offset);
-}
-
-static void tsadc_writel(u32 val, u32 offset)
-{
- writel_relaxed(val, g_dev->regs + offset);
-}
-
-static DEFINE_MUTEX(tsadc_mutex);
-static void rk30_tsadc_get(unsigned int chn, int *temp, int *code)
-{
- *temp = 0;
- *code = 0;
-
- if (!g_dev || chn > 1)
- return;
-
- mutex_lock(&tsadc_mutex);
-
- clk_enable(g_dev->pclk);
- clk_enable(g_dev->clk);
-
- msleep(10);
- tsadc_writel(0, TSADC_CTRL);
- tsadc_writel(TSADC_CTRL_POWER_UP | TSADC_CTRL_CH(chn), TSADC_CTRL);
- msleep(10);
- if ((tsadc_readl(TSADC_STAS) & TSADC_STAS_BUSY_MASK) != TSADC_STAS_BUSY) {
- int i;
- *code = tsadc_readl(TSADC_DATA) & TSADC_DATA_MASK;
- for (i = 0; i < ARRAY_SIZE(table) - 1; i++) {
- if ((*code) <= table[i].code && (*code) > table[i + 1].code) {
- *temp = table[i].temp + (table[i + 1].temp - table[i].temp) * (table[i].code - (*code)) / (table[i].code - table[i + 1].code);
- }
- }
- }
- tsadc_writel(0, TSADC_CTRL);
-
- clk_disable(g_dev->clk);
- clk_disable(g_dev->pclk);
-
- mutex_unlock(&tsadc_mutex);
-}
-
-int rk30_tsadc_get_temp(unsigned int chn)
-{
- int temp, code;
-
- rk30_tsadc_get(chn, &temp, &code);
- return temp;
-}
-EXPORT_SYMBOL(rk30_tsadc_get_temp);
-
-static int rk30_tsadc_get_temp0(char *buffer, struct kernel_param *kp)
-{
- int temp, code;
- rk30_tsadc_get(0, &temp, &code);
- return sprintf(buffer, "temp: %d code: %d", temp, code);
-}
-module_param_call(temp0, NULL, rk30_tsadc_get_temp0, NULL, S_IRUGO);
-
-static int rk30_tsadc_get_temp1(char *buffer, struct kernel_param *kp)
-{
- int temp, code;
- rk30_tsadc_get(1, &temp, &code);
- return sprintf(buffer, "temp: %d code: %d", temp, code);
-}
-module_param_call(temp1, NULL, rk30_tsadc_get_temp1, NULL, S_IRUGO);
-
-static int __init rk30_tsadc_probe(struct platform_device *pdev)
-{
- struct rk30_tsadc_device *dev = kzalloc(sizeof(*dev), GFP_KERNEL);
- struct resource *res;
- int ret;
-
- if (!dev) {
- dev_err(&pdev->dev, "failed to alloc mem\n");
- return -ENOMEM;
- }
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res) {
- dev_err(&pdev->dev, "cannot find IO resource\n");
- ret = -ENOENT;
- goto err1;
- }
-
- dev->ioarea = request_mem_region(res->start, (res->end - res->start) + 1, pdev->name);
- if (!dev->ioarea) {
- dev_err(&pdev->dev, "cannot request IO\n");
- ret = -ENXIO;
- goto err1;
- }
-
- dev->regs = ioremap(res->start, (res->end - res->start) + 1);
- if (!dev->regs) {
- dev_err(&pdev->dev, "cannot map IO\n");
- ret = -ENXIO;
- goto err2;
- }
-
- dev->clk = clk_get(NULL, "tsadc");
- if (IS_ERR(dev->clk)) {
- dev_err(&pdev->dev, "failed to get clk\n");
- ret = PTR_ERR(dev->clk);
- goto err3;
- }
-
- ret = clk_set_rate(dev->clk, TSADC_CLK_RATE);
- if (ret < 0) {
- dev_err(&pdev->dev, "failed to set clk\n");
- goto err4;
- }
-
- dev->pclk = clk_get(NULL, "pclk_tsadc");
- if (IS_ERR(dev->pclk)) {
- dev_err(&pdev->dev, "failed to get pclk\n");
- ret = PTR_ERR(dev->clk);
- goto err4;
- }
-
- platform_set_drvdata(pdev, dev);
- g_dev = dev;
-
- dev_info(&pdev->dev, "initialized\n");
-
- return 0;
-
-err4:
- clk_put(dev->clk);
-err3:
- iounmap(dev->regs);
-err2:
- release_resource(dev->ioarea);
-err1:
- kfree(dev);
- return ret;
-}
-
-static struct platform_driver rk30_tsadc_driver = {
- .driver = {
- .name = "rk30-tsadc",
- .owner = THIS_MODULE,
- },
-};
-
-static int __init rk30_tsadc_init(void)
-{
- return platform_driver_probe(&rk30_tsadc_driver, rk30_tsadc_probe);
-}
-rootfs_initcall(rk30_tsadc_init);
-
-MODULE_DESCRIPTION("Driver for TSADC");
-MODULE_AUTHOR("lw, lw@rock-chips.com");
-MODULE_LICENSE("GPL");
+++ /dev/null
-choice
- prompt "RK3026/RK3028A Board Type"
- depends on ARCH_RK3026
-
-config MACH_RK3026_FPGA
- bool "RK3026 FPGA Board"
-
-config MACH_RK3026_TB
- bool "RK3026 Top Board"
-
-config MACH_RK3026_86V
- bool "RK3026 86V Board"
-
-config MACH_RK3028A_TB
- bool "RK3028A Top Board"
-
-config MACH_RK3028A_86V
- bool "RK3028A 86V Board"
-
-config MACH_RK3028A_FAC
- bool "RK3028A Board for factory"
- select MACH_RK_FAC
-
-config MACH_RK3026_86V_FAC
- bool "RK3026 86V Board for factory"
- select MACH_RK_FAC
-
-config MACH_RK3026_FT
- bool "RK3026 FT Board"
-
-endchoice
+++ /dev/null
-ifneq ($(CONFIG_RK_FPGA),y)
-obj-y += ../plat-rk/clock.o
-obj-y += clock_data.o
-obj-y += ../mach-rk2928/ddr.o
-obj-y += reset.o
-obj-$(CONFIG_PM) += ../mach-rk2928/pm.o
-endif
-obj-y += common.o
-CFLAGS_common.o += -DTEXT_OFFSET=$(TEXT_OFFSET)
-obj-y += ../mach-rk2928/devices.o
-obj-y += ../mach-rk2928/io.o
-obj-y += rk_timer.o
-obj-$(CONFIG_SMP) += ../mach-rk30/platsmp.o ../mach-rk30/headsmp.o
-obj-$(CONFIG_HOTPLUG_CPU) += ../mach-rk30/hotplug.o
-obj-$(CONFIG_CPU_IDLE) += ../mach-rk30/cpuidle.o
-obj-$(CONFIG_CPU_FREQ) += ../mach-rk3188/cpufreq.o
-obj-$(CONFIG_DVFS) += dvfs.o
-obj-$(CONFIG_RK30_I2C_INSRAM) += ../mach-rk2928/i2c_sram.o
-
-obj-y += board.o
-
-board-$(CONFIG_MACH_RK3026_FPGA) += board-rk3026-fpga.o
-board-$(CONFIG_MACH_RK3026_TB) += board-rk3026-tb.o
-board-$(CONFIG_MACH_RK3026_86V) += board-rk3026-86v.o
-board-$(CONFIG_MACH_RK3028A_TB) += board-rk3028a-tb.o
-board-$(CONFIG_MACH_RK3028A_86V) += board-rk3028a-86v.o
-board-$(CONFIG_MACH_RK3028A_FAC) += board-rk3028a-86v-fac.o
-board-$(CONFIG_MACH_RK3026_86V_FAC) += board-rk3026-86v-fac.o
-board-$(CONFIG_MACH_RK3026_FT) += board-rk3026-ft.o
+++ /dev/null
-include $(srctree)/arch/arm/mach-rk30/Makefile.boot
+++ /dev/null
-#ifdef CONFIG_VIDEO_RK29
-#include <plat/rk_camera.h>
-/* Notes:
-
-Simple camera device registration:
-
- new_camera_device(sensor_name,\ // sensor name, it is equal to CONFIG_SENSOR_X
- face,\ // sensor face information, it can be back or front
- pwdn_io,\ // power down gpio configuration, it is equal to CONFIG_SENSOR_POWERDN_PIN_XX
- flash_attach,\ // sensor is attach flash or not
- mir,\ // sensor image mirror and flip control information
- i2c_chl,\ // i2c channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_IIC_ADAPTER_ID_X
- cif_chl) \ // cif channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_CIF_INDEX_X
-
-Comprehensive camera device registration:
-
- new_camera_device_ex(sensor_name,\
- face,\
- ori,\ // sensor orientation, it is equal to CONFIG_SENSOR_ORIENTATION_X
- pwr_io,\ // sensor power gpio configuration, it is equal to CONFIG_SENSOR_POWER_PIN_XX
- pwr_active,\ // sensor power active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- rst_io,\ // sensor reset gpio configuration, it is equal to CONFIG_SENSOR_RESET_PIN_XX
- rst_active,\ // sensor reset active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- pwdn_io,\
- pwdn_active,\ // sensor power down active level, is equal to CONFIG_SENSOR_POWERDNACTIVE_LEVEL_X
- flash_attach,\
- res,\ // sensor resolution, this is real resolution or resoltuion after interpolate
- mir,\
- i2c_chl,\
- i2c_spd,\ // i2c speed , 100000 = 100KHz
- i2c_addr,\ // the i2c slave device address for sensor
- cif_chl,\
- mclk)\ // sensor input clock rate, 24 or 48
-
-*/
-static struct rkcamera_platform_data new_camera[] = {
-
- /* new_camera_device(RK29_CAM_SENSOR_OV2659,
- front,
- RK30_PIN3_PB3,
- 0,
- 0,
- 1,
- 0),*/
- new_camera_device(RK29_CAM_SENSOR_GC0308,
- front,
- RK30_PIN3_PB3,
- 0,
- 0,
- 1,
- 0),
- /*
- new_camera_device(RK29_CAM_SENSOR_GC0308,
- back,
- RK30_PIN3_PD7,
- 0,
- 0,
- 1,
- 0),
- */
- new_camera_device_end
-};
-/*---------------- Camera Sensor Macro Define Begin ------------------------*/
-/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
-#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_GC2035 /* back camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_0 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 1
-#define CONFIG_SENSOR_CIF_INDEX_0 0
-#define CONFIG_SENSOR_ORIENTATION_0 90
-#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 RK30_PIN3_PB3
-#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_H
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000
-
-#define CONFIG_SENSOR_01 RK29_CAM_SENSOR_OV5642 /* back camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_01 0x00
-#define CONFIG_SENSOR_CIF_INDEX_01 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 4
-#define CONFIG_SENSOR_ORIENTATION_01 90
-#define CONFIG_SENSOR_POWER_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_01 RK2928_PIN3_PB3
-#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_01 30000
-
-#define CONFIG_SENSOR_02 RK29_CAM_SENSOR_OV5640 /* back camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_02 0x00
-#define CONFIG_SENSOR_CIF_INDEX_02 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 4
-#define CONFIG_SENSOR_ORIENTATION_02 90
-#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_02 RK2928_PIN3_PB3
-#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000
-
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_GC0308 /* front camera sensor 0 */
-#define CONFIG_SENSOR_IIC_ADDR_1 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 1
-#define CONFIG_SENSOR_CIF_INDEX_1 0
-#define CONFIG_SENSOR_ORIENTATION_1 270
-#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_1 RK30_PIN3_PD7
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000
-
-#define CONFIG_SENSOR_11 RK29_CAM_SENSOR_OV2659 /* front camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_11 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 3
-#define CONFIG_SENSOR_CIF_INDEX_11 0
-#define CONFIG_SENSOR_ORIENTATION_11 270
-#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_11 30000
-
-#define CONFIG_SENSOR_12 RK29_CAM_SENSOR_OV2659//RK29_CAM_SENSOR_OV2655 /* front camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_12 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 3
-#define CONFIG_SENSOR_CIF_INDEX_12 0
-#define CONFIG_SENSOR_ORIENTATION_12 270
-#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_12 30000
-
-
-#endif //#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk2928_camera.c"
-/*---------------- Camera Sensor Macro Define End ---------*/
-
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#if 0
-#define CONFIG_SENSOR_POWER_IOCTL_USR 0 //define this refer to your board layout
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
-#else
-#define CAMERA_NAME "gc0308_back_4"
-#define CONFIG_SENSOR_POWER_IOCTL_USR 1 //define this refer to your board layout
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 1
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_PMU 1
-
-
-#endif
-static void rk_cif_power(int on)
-{
- struct regulator *ldo_18,*ldo_28;
- #if 0
- ldo_28 = regulator_get(NULL, "ldo7"); // vcc28_cif
- ldo_18 = regulator_get(NULL, "ldo1"); // vcc18_cif
- #else
- ldo_28 = regulator_get(NULL, "vaux1"); // vcc28_cif
- ldo_18 = regulator_get(NULL, "vdig1"); // vcc18_cif
- #endif
- if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){
- printk("get cif ldo failed!\n");
- return;
- }
- if(on == 0){
- regulator_disable(ldo_28);
- regulator_put(ldo_28);
- regulator_disable(ldo_18);
- regulator_put(ldo_18);
- mdelay(500);
- }
- else{
- regulator_set_voltage(ldo_28, 2800000, 2800000);
- regulator_enable(ldo_28);
- // printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
- regulator_put(ldo_28);
-
- regulator_set_voltage(ldo_18, 1800000, 1800000);
- // regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(ldo_18);
- // printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
- regulator_put(ldo_18);
- }
-}
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- //#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
- struct regulator *ldo_18,*ldo_28;
-
-#if 0
- ldo_28 = regulator_get(NULL, "ldo7"); // vcc28_cif
- ldo_18 = regulator_get(NULL, "ldo1"); // vcc18_cif
-#else
- ldo_28 = regulator_get(NULL, "vaux1"); // vcc28_cif
- ldo_18 = regulator_get(NULL, "vdig1"); // vcc18_cif
-#endif
-
- if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){
- printk("get cif ldo failed!\n");
- return -1;
- }
- if(on == 0){
- while(regulator_is_enabled(ldo_28)>0)
- regulator_disable(ldo_28);
- regulator_put(ldo_28);
- while(regulator_is_enabled(ldo_18)>0)
- regulator_disable(ldo_18);
- regulator_put(ldo_18);
- mdelay(10);
- } else {
- regulator_set_voltage(ldo_28, 2800000, 2800000);
- regulator_enable(ldo_28);
- //printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
- regulator_put(ldo_28);
-
- regulator_set_voltage(ldo_18, 1800000, 1800000);
- //regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(ldo_18);
- //printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
- regulator_put(ldo_18);
- }
-
- return 0;
-}
-#endif
-
-#if CONFIG_SENSOR_RESET_IOCTL_USR
-static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
-static void rk_cif_powerdowen(int on)
-{
- struct regulator *ldo_28;
- ldo_28 = regulator_get(NULL, "vpll"); // vcc28_cif
- if (ldo_28 == NULL || IS_ERR(ldo_28) ){
- printk("get cif vpll ldo failed!\n");
- return;
- }
-
- // if((res->gpio_flag & RK29_CAM_POWERDNACTIVE_MASK) == RK29_CAM_POWERDNACTIVE_H) {
- if( CONFIG_SENSOR_POWERDNACTIVE_LEVEL_PMU ) {
- printk("hjc:%s[%d],on=%d\n",__func__,__LINE__,on);
- if(on == 0){//enable camera
- regulator_set_voltage(ldo_28, 2500000, 2500000);
- regulator_enable(ldo_28);
- printk(" %s set vpll vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
- regulator_put(ldo_28);
-
- }else{//disable camera
- if(regulator_is_enabled(ldo_28)>0){
- printk("%s[%d]\n",__func__,__LINE__);
- int a = regulator_disable(ldo_28);
-
- }
- // return;
- regulator_put(ldo_28);
-
- mdelay(500);
- }
- }else{
- printk("hjc:%s[%d],on=%d\n",__func__,__LINE__,on);
-
- if(on == 1){//enable camera
- regulator_set_voltage(ldo_28, 2500000, 2500000);
- regulator_enable(ldo_28);
- printk(" %s set vpll vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
- regulator_put(ldo_28);
- }else{//disable camera
- if(regulator_is_enabled(ldo_28)>0){
- regulator_disable(ldo_28);
- }
- regulator_put(ldo_28);
- mdelay(500);
- }
- }
-}
-static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
-int camera_powerdown = res->gpio_powerdown;
-
- #if 1 //defined(CONFIG_MACH_RK2926_V86)
- int ret = 0;
- printk("hjc:%s,%s,on=%d\n\n\n",__func__,res->dev_name,on);
- if(strcmp(res->dev_name,CAMERA_NAME)==0)//"gc0308_front_3") == 0)
- {
- //Èç¹ûΪpmu¿ØÖƵÄÒý½Å£¬"ov5642_front_1" ¸ù¾Ý sensorÃû×Ö £¬Ç°ºóÖà £¬ sensorÐòºÅÈ·¶¨
- //¾ßÌåpmu¿ØÖƲÙ×÷£¬¿É²Î¿¼ÎļþĩβµÄ²Î¿¼´úÂë
- //printk("\n\n%s.............pwm power,on=%d\n",__FUNCTION__,on);
- rk_cif_powerdowen(on);
- }else{ //gpio¿ØÖƵIJÙ×÷
- // int camera_powerdown = res->gpio_powerdown;
- int camera_ioflag = res->gpio_flag;
- int camera_io_init = res->gpio_init; // int ret = 0;
- if (camera_powerdown != INVALID_GPIO) {
- if (camera_io_init & RK29_CAM_POWERDNACTIVE_MASK) {
- if (on) {
- gpio_set_value(camera_powerdown, ((camera_ioflag&RK29_CAM_POWERDNACTIVE_MASK)>>RK29_CAM_POWERDNACTIVE_BITPOS));
- printk("%s..%s..PowerDownPin=%d ..PinLevel = %x \n",__FUNCTION__,res->dev_name,camera_powerdown, ((camera_ioflag&RK29_CAM_POWERDNACTIVE_MASK)>>RK29_CAM_POWERDNACTIVE_BITPOS));
- } else {
- gpio_set_value(camera_powerdown,(((~camera_ioflag)&RK29_CAM_POWERDNACTIVE_MASK)>>RK29_CAM_POWERDNACTIVE_BITPOS));
- printk("%s..%s..PowerDownPin= %d..PinLevel = %x \n",__FUNCTION__,res->dev_name, camera_powerdown, (((~camera_ioflag)&RK29_CAM_POWERDNACTIVE_MASK)>>RK29_CAM_POWERDNACTIVE_BITPOS));
- }
- } else { ret = RK29_CAM_EIO_REQUESTFAIL;
- printk("%s..%s..PowerDownPin=%d request failed!\n",__FUNCTION__,res->dev_name,camera_powerdown); }
- } else {
- ret = RK29_CAM_EIO_INVALID;
- }
- }
- return ret;
- #else
- #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
- #endif
-}
-#endif
-
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-
-#if CONFIG_SENSOR_IIC_ADDR_0
-static struct reginfo_t rk_init_data_sensor_reg_0[] =
-{
- {0x0000, 0x00,0,0}
- };
-static struct reginfo_t rk_init_data_sensor_winseqreg_0[] ={
- {0x0000, 0x00,0,0}
- };
-#endif
-
-#if CONFIG_SENSOR_IIC_ADDR_1
-static struct reginfo_t rk_init_data_sensor_reg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_01
-static struct reginfo_t rk_init_data_sensor_reg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_02
-static struct reginfo_t rk_init_data_sensor_reg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_11
-static struct reginfo_t rk_init_data_sensor_reg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_12
-static struct reginfo_t rk_init_data_sensor_reg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] =
-{
- #if CONFIG_SENSOR_IIC_ADDR_0
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_0,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_1
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_1,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_01
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_01,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_02
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_02,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_11
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_11,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_12
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_12,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
-
- };
-#include "../../../drivers/media/video/rk2928_camera.c"
-
-#endif /* CONFIG_VIDEO_RK29 */
+++ /dev/null
-/*
- * Copyright (C) 2013 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <linux/rk_fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/mfd/tps65910.h>
-#include <linux/regulator/act8846.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/dvfs.h>
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-
-#ifdef CONFIG_SND_SOC_RK3026
-#include "../../../sound/soc/codecs/rk3026_codec.h"
-#endif
-
-#if defined(CONFIG_RK_HDMI)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#if defined(CONFIG_GPS_RK)
-#include "../../../drivers/misc/gps/rk_gps/rk_gps.h"
-#endif
-#include "board-rk3026-86v-camera.c"
-#include <plat/config.h>
-#include <plat/board.h>
-#include "../plat-rk/rk-fac-config.c"
-#if 1
-#define INIT_ERR(name) do { printk("%s: %s init Failed: \n", __func__, (name)); } while(0)
-#else
-#define INIT_ERR(name)
-#endif
-
-/***********************************************************
-* board config
-************************************************************/
-
-//pwm regulator
-#define REG_PWM 1 // (0 ~ 2)
-//pmic
-#define PMU_INT_PIN RK30_PIN1_PB1
-#define PMU_SLEEP_PIN RK30_PIN1_PA1
-//ion reserve memory
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-
-static int pwm_mode[] = {PWM0, PWM1, PWM2};
-static inline int rk_gpio_request(int gpio, int direction, int value, const char *label)
-{
- int ret = 0;
- unsigned long flags = 0;
-
- if(!gpio_is_valid(gpio))
- return 0;
-
- if(direction == GPIOF_DIR_IN)
- flags = GPIOF_IN;
- else if(value == GPIO_LOW)
- flags = GPIOF_OUT_INIT_LOW;
- else
- flags = GPIOF_OUT_INIT_HIGH;
-
- ret = gpio_request_one(gpio, flags, label);
- if(ret < 0)
- pr_err("Failed to request '%s'\n", label);
-
- return ret;
-}
-////////////////////////////////////////////////////////////////////////////////////////
-//key
-////////////////////////////////////////////////////////////////////////////////////////
-#include <plat/key.h>
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "play",
- .code = KEY_POWER,
- .wakeup = 1,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- },
- {
- .desc = "menu",
- .code = EV_MENU,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- },
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .chn = -1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-////////////////////////////////////////////////////////////////////////////////////////
-//Backlight
-////////////////////////////////////////////////////////////////////////////////////////
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
- printk("rk29_backlight_io_init %d\n",bl_pwm_mode);
- iomux_set(bl_pwm_mode);
- msleep(50);
- if(bl_en== -1)
- return 0;
- ret = port_output_init(bl_en, 1, "bl_en");
- if(ret < 0){
- printk("%s: port output init faild\n", __func__);
- return ret;
- }
- port_output_on(bl_en);
-
- return ret;
-
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0, pwm_gpio;
-
- if(bl_en != -1)
- port_deinit(bl_en);
-
- pwm_gpio = iomux_mode_to_gpio(bl_pwm_mode);
- gpio_request(pwm_gpio, NULL);
- gpio_direction_output(pwm_gpio, GPIO_LOW);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret = 0, pwm_gpio;
-
- pwm_gpio = iomux_mode_to_gpio(bl_pwm_mode);
- if (gpio_request(pwm_gpio, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- gpio_direction_output(pwm_gpio, GPIO_LOW);
- port_output_off(bl_en);
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- int pwm_gpio = iomux_mode_to_gpio(bl_pwm_mode);
-
- gpio_free(pwm_gpio);
- iomux_set(bl_pwm_mode);
- msleep(30);
- port_output_on(bl_en);
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-#endif
-////////////////////////////////////////////////////////////////////////////////////////
-//LCD
-////////////////////////////////////////////////////////////////////////////////////////
-#ifdef CONFIG_FB_ROCKCHIP
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
- //printk("rk_fb_io_init %x,%x,%x\n",lcd_cs,lcd_en,lcd_std);
- if(lcd_cs != -1){
- ret = port_output_init(lcd_cs, 1, "lcd_cs");
- if(ret < 0)
- printk("%s: port output init faild\n", __func__);
- port_output_on(lcd_cs);
- }
-
- if(lcd_en != -1){
- ret = port_output_init(lcd_en, 1, "lcd_en");
- if(ret < 0)
- printk("%s: port output init faild\n", __func__);
- port_output_on(lcd_en);
- }
-
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
- if(lcd_cs != -1)
- port_output_off(lcd_cs);
- if(lcd_en != -1)
- port_output_on(lcd_en);
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- if(lcd_en != -1)
- port_output_on(lcd_en);
- if(lcd_cs != -1)
- port_output_on(lcd_cs);
- return 0;
-}
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
-struct rk29fb_info lcdc0_screen_info = {
-#if defined(CONFIG_RK_HDMI) && defined(CONFIG_HDMI_SOURCE_LCDC0) && defined(CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL)
- .prop = EXTEND, //extend display device
- .io_init = NULL,
- .io_disable = NULL,
- .io_enable = NULL,
- .set_screen_info = hdmi_init_lcdc,
-#else
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-#endif
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
-struct rk29fb_info lcdc1_screen_info = {
-#if defined(CONFIG_RK_HDMI) && defined(CONFIG_HDMI_SOURCE_LCDC1) && defined(CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL)
- .prop = EXTEND, //extend display device
- .io_init = NULL,
- .io_disable = NULL,
- .io_enable = NULL,
- .set_screen_info = hdmi_init_lcdc,
-#else
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-#endif
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
-static struct resource resource_lcdc0[] = {
- [0] = {
- .name = "lcdc0 reg",
- .start = RK3026_LCDC0_PHYS,
- .end = RK3026_LCDC0_PHYS + RK3026_LCDC0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc0 irq",
- .start = IRQ_LCDC,
- .end = IRQ_LCDC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc0 = {
- .name = "rk30-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc0),
- .resource = resource_lcdc0,
- .dev = {
- .platform_data = &lcdc0_screen_info,
- },
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
-static struct resource resource_lcdc1[] = {
- [0] = {
- .name = "lcdc1 reg",
- .start = RK3026_LCDC1_PHYS,
- .end = RK3026_LCDC1_PHYS + RK3026_LCDC1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc1 irq",
- .start = IRQ_LCDC1,
- .end = IRQ_LCDC1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc1 = {
- .name = "rk30-lcdc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resource_lcdc1),
- .resource = resource_lcdc1,
- .dev = {
- .platform_data = &lcdc1_screen_info,
- },
-};
-#endif
-
-static int rk_platform_add_display_devices(void)
-{
- struct platform_device *fb = NULL; //fb
- struct platform_device *lcdc0 = NULL; //lcdc0
- struct platform_device *lcdc1 = NULL; //lcdc1
- struct platform_device *bl = NULL; //backlight
-#ifdef CONFIG_FB_ROCKCHIP
- fb = &device_fb;
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
- lcdc0 = &device_lcdc0,
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
- lcdc1 = &device_lcdc1,
-#endif
-
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- bl = &rk29_device_backlight,
-#endif
- __rk_platform_add_display_devices(fb,lcdc0,lcdc1,bl);
-
- return 0;
-}
-
-////////////////////////////////////////////////////////////////////////////////////////
-//TP
-////////////////////////////////////////////////////////////////////////////////////////
-#if (defined(CONFIG_TOUCHSCREEN_GSLX680_RK3168)||defined (CONFIG_TOUCHSCREEN_GSLX680_RK3028))
-static int gslx680_init_platform_hw()
- {
- return 0;
- }
-
-static struct tp_platform_data gslx680_data = {
-
- .init_platform_hw = gslx680_init_platform_hw,
-};
-struct i2c_board_info __initdata gslx680_info = {
- .type = "gslX680",
- .flags = 0,
- .platform_data = &gslx680_data,
-};
-#endif
-
-
-#if defined (CONFIG_TOUCHSCREEN_86V_GT811_IIC)
-int gt811_init_platform_hw(int irq,int reset)
-{
- int ret;
- if(tp_rst!=-1){
- ret = port_output_init(tp_rst, 1, "tp_rst");
- if(ret<0)
- printk("%s: port output init faild\n", __func__);
- }
-
- port_output_off(tp_rst);
- msleep(500);
- port_output_off(tp_rst);
- msleep(500);
- port_output_on(tp_rst);
- mdelay(100);
- return 0;
-}
-
-
-static struct tp_platform_data gt811_data = {
- .model= 811,
- .init_platform_hw= gt811_init_platform_hw,
-};
-
-struct i2c_board_info __initdata gt811_info = {
- .type = "gt811_ts",
- .flags = 0,
- .platform_data = >811_data,
-};
-#endif
-#if defined(CONFIG_TOUCHSCREEN_GT8XX)
-#define TOUCH_PWR_PIN RK30_PIN0_PC5 // need to fly line by hardware engineer
-static int goodix_init_platform_hw(void)
-{
- int ret;
-
- if (TOUCH_PWR_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_PWR_PIN, "goodix power pin");
- if (ret != 0) {
- gpio_free(TOUCH_PWR_PIN);
- printk("goodix power error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_PWR_PIN, 0);
- gpio_set_value(TOUCH_PWR_PIN, GPIO_LOW);
- msleep(100);
- }
-
- if(tp_rst!=-1){
- ret = port_output_init(tp_rst, 1, "tp_rst");
- if(ret<0)
- printk("%s: port output init faild\n", __func__);
- }
- port_output_on(tp_rst);
- msleep(100);
- return 0;
-}
-
-struct tp_platform_data goodix_data = {
- .model = 8105,
- .init_platform_hw = goodix_init_platform_hw,
-};
-
-struct i2c_board_info __initdata goodix_info = {
- .type = "Goodix-TS",
- .flags = 0,
- .platform_data = &goodix_data,
-};
-#endif
-
-////////////////////////////////////////////////////////////////////////////////////////
-//Gsensor
-////////////////////////////////////////////////////////////////////////////////////////
-#if defined (CONFIG_GS_LSM303D)
-static int lms303d_init_platform_hw(void)
-{
- return 0;
-}
-static struct sensor_platform_data lms303d_data = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lms303d_init_platform_hw,
-};
-struct i2c_board_info __initdata lms303d_info = {
- .type = "gs_lsm303d",
- .flags = 0,
- .platform_data =&lms303d_data,
-};
-#endif
-
-#if defined (CONFIG_GS_MMA8452)
-static int mma8452_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data mma8452_data = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma8452_init_platform_hw,
-};
-struct i2c_board_info __initdata mma8452_info = {
- .type = "gs_mma8452",
- .flags = 0,
- .platform_data =&mma8452_data,
-};
-#endif
-
-/*MMA7660 gsensor*/
-#if defined (CONFIG_GS_MMA7660)
-static int mma7660_init_platform_hw(void)
-{
- //rk30_mux_api_set(GPIO1B2_SPI_RXD_UART1_SIN_NAME, GPIO1B_GPIO1B2);
-
- return 0;
-}
-
-static struct sensor_platform_data mma7660_data = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma7660_init_platform_hw,
-};
-struct i2c_board_info __initdata mma7660_info = {
- .type = "gs_mma7660",
- .flags = 0,
- .platform_data =&mma7660_data,
-};
-#endif
-
-#if defined (CONFIG_GS_MXC6225)
-static int mxc6225_init_platform_hw(void)
-{
-// rk30_mux_api_set(GPIO1B1_SPI_TXD_UART1_SOUT_NAME, GPIO1B_GPIO1B1);
- return 0;
-}
-
-static struct sensor_platform_data mxc6225_data = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 0,
- .poll_delay_ms = 30,
- .init_platform_hw = mxc6225_init_platform_hw,
-};
-struct i2c_board_info __initdata mxc6225_info = {
- .type = "gs_mxc6225",
- .flags = 0,
- .platform_data =&mxc6225_data,
-};
-#endif
-
-#if defined (CONFIG_GS_DMT10)
-static int dmt10_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data dmt10_data = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 0,
- .poll_delay_ms = 30,
- .init_platform_hw = dmt10_init_platform_hw,
-};
-struct i2c_board_info __initdata dmt10_info = {
- .type = "gs_dmard10",
- .flags = 0,
- .platform_data =&dmt10_data,
-};
-#endif
-
-
-#if defined (CONFIG_GS_LIS3DH)
-static int lis3dh_init_platform_hw(void)
-{
- return 0;
-}
-static struct sensor_platform_data lis3dh_data = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lis3dh_init_platform_hw,
-};
-struct i2c_board_info __initdata lis3dh_info = {
- .type = "gs_lis3dh",
- .flags = 0,
- .platform_data =&lis3dh_data,
-};
-#endif
-
-////////////////////////////////////////////////////////////////////////////////////////
-//battery
-////////////////////////////////////////////////////////////////////////////////////////
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
-
-};
-
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-
-////////////////////////////////////////////////////////////////////////////////////////
-//codec
-////////////////////////////////////////////////////////////////////////////////////////
-#ifdef CONFIG_SND_SOC_RK3026
-struct rk3026_codec_pdata rk3026_codec_pdata_info={
- .spk_ctl_gpio = INVALID_GPIO,
- .hp_ctl_gpio = RK2928_PIN1_PA0,
-};
-
-static struct resource resources_acodec[] = {
- {
- .start = RK2928_ACODEC_PHYS,
- .end = RK2928_ACODEC_PHYS + RK2928_ACODEC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device rk3026_codec = {
- .name = "rk3026-codec",
- .id = -1,
- .resource = resources_acodec,
- .dev = {
- .platform_data = &rk3026_codec_pdata_info,
- }
-};
-#endif
-
-#if defined (CONFIG_SND_RK29_SOC_RT5631)
-static struct codec_platform_data rt5631_data = {
-};
-struct i2c_board_info __initdata rt5631_info = {
- .type = "rt5631",
- .flags = 0,
- .platform_data =&rt5631_data,
-};
-#endif
-
-#if defined (CONFIG_SND_RK29_SOC_ES8323)
-static struct codec_platform_data es8323_data = {
-};
-struct i2c_board_info __initdata es8323_info = {
- .type = "es8323",
- .flags = 0,
- .platform_data =&es8323_data,
-};
-#endif
-
-#if defined(CONFIG_MFD_RK616)
-#define RK616_SCL_RATE (100*1000) //i2c scl rate
-static int rk616_power_on_init(void)
-{
- int ret;
-
- if(codec_power!=-1)
- {
- ret = port_output_init(codec_power, 1, "codec_power");
- if(ret < 0)
- printk("%s: port output init faild\n", __func__);
- port_output_on(codec_power);
- }
-
- if(codec_rst!=-1)
- {
- ret = port_output_init(codec_rst, 1, "codec_rst");
- if(ret < 0)
- printk("%s: port output init faild\n", __func__);
- port_output_on(codec_rst);
- msleep(100);
- port_output_off(codec_rst);
- msleep(100);
- port_output_on(codec_rst);
- }
- return 0;
-
-}
-
-
-static int rk616_power_deinit(void)
-{
- if(codec_power!=-1)
- {
- port_output_off(codec_power);
- port_deinit(codec_power);
- }
- if(codec_rst!=-1)
- {
- port_output_off(codec_rst);
- port_deinit(codec_rst);
- }
- return 0;
-}
-
-static struct rk616_platform_data rk616_pdata = {
- .power_init = rk616_power_on_init,
- .power_deinit = rk616_power_deinit,
- .scl_rate = RK616_SCL_RATE,
- .lcd0_func = INPUT, //port lcd0 as input
- .lcd1_func = INPUT, //port lcd1 as input
- .lvds_ch_nr = 1, //the number of used lvds channel
- //.hdmi_irq = RK30_PIN2_PD6,
- //.spk_ctl_gpio = RK30_PIN2_PD7,
- .hp_ctl_gpio = RK30_PIN2_PD7,
-};
-
-struct i2c_board_info __initdata rk616_info = {
- .type = "rk616",
- .flags = 0,
- .platform_data = &rk616_pdata,
-};
-#endif
-
-
-////////////////////////////////////////////////////////////////////////////////////////
-//spi
-////////////////////////////////////////////////////////////////////////////////////////
-static struct spi_board_info board_spi_devices[] = {
-};
-
-
-////////////////////////////////////////////////////////////////////////////////////////
-//compass
-////////////////////////////////////////////////////////////////////////////////////////
-#if defined (CONFIG_COMPASS_AK8975)
-static struct sensor_platform_data akm8975_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-#if defined (CONFIG_COMPASS_AK8963)
-static struct sensor_platform_data akm8963_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {0, 1, 0},
- {1, 0, 0},
- {0, 0, -1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {0, -1, 0},
- {-1, 0, 0},
- {0, 0, -1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-
-#if defined(CONFIG_GYRO_L3G4200D)
-
-#include <linux/l3g4200d.h>
-#define L3G4200D_INT_PIN RK30_PIN0_PB4
-
-static int l3g4200d_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data l3g4200d_info = {
- .type = SENSOR_TYPE_GYROSCOPE,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
- .init_platform_hw = l3g4200d_init_platform_hw,
- .x_min = 40,//x_min,y_min,z_min = (0-100) according to hardware
- .y_min = 40,
- .z_min = 20,
-};
-
-#endif
-
-#ifdef CONFIG_LS_CM3217
-static struct sensor_platform_data cm3217_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 0,
- .poll_delay_ms = 500,
-};
-
-#endif
-
-/***********************************************************
-* usb wifi
-************************************************************/
-#if defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU)
-
-static void rkusb_wifi_power(int on) {
- int ret=0;
- struct regulator *ldo = NULL;
- printk("hjc:%s[%d],on=%d\n",__func__,__LINE__,on);
-#if defined(CONFIG_MFD_TPS65910)
- if (pmic_is_tps65910())
- ldo = regulator_get(NULL, "vmmc"); //vccio_wl
-#endif
-#if defined(CONFIG_REGULATOR_ACT8931)
- if(pmic_is_act8931())
- ldo = regulator_get(NULL, "act_ldo4"); //vccio_wl
-#endif
-
- if(!on) {
-
- regulator_set_voltage(ldo, 3000000, 3000000);
- ret = regulator_enable(ldo);
- if(ret != 0){
- printk("faild to enable vmmc\n");
- }
- printk("%s: vccio_wl enable\n", __func__);
- } else {
- printk("%s: vccio_wl disable\n", __func__);
- regulator_disable(ldo);
- if(ret != 0){
- printk("faild to disable vmmc\n");
- }
- }
- regulator_put(ldo);
- udelay(100);
-}
-
-#endif
-
-
-/***********************************************************
-* sdmmc
-************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "board-rk3026-86v-sdmmc-config.c"
-#include "../plat-rk/rk-sdmmc-ops.c"
-#include "../plat-rk/rk-sdmmc-wifi.c"
-#endif //endif ---#ifdef CONFIG_SDMMC_RK29
-
-#ifdef CONFIG_SDMMC0_RK29
-#define CONFIG_SDMMC0_USE_DMA
-static int rk29_sdmmc0_cfg_gpio(void)
-{
- rk29_sdmmc_set_iomux(0, 0xFFFF);
- #if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- iomux_set_gpio_mode(iomux_gpio_to_mode(RK29SDK_SD_CARD_DETECT_N));
- #else
- iomux_set(MMC0_DETN);
- #endif
-
- #if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
- #endif
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
- .set_iomux = rk29_sdmmc_set_iomux,
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) && defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- .status = rk29sdk_wifi_mmc0_status,
- .register_status_notify = rk29sdk_wifi_mmc0_status_register,
-#endif
-
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .power_en = RK29SDK_SD_CARD_PWR_EN,
- .power_en_level = RK29SDK_SD_CARD_PWR_EN_LEVEL,
-#else
- .power_en = INVALID_GPIO,
- .power_en_level = GPIO_LOW,
-#endif
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC0_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- .det_pin_info = {
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N, //INVALID_GPIO,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
- #endif
- },
-
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
- .set_iomux = rk29_sdmmc_set_iomux,
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC) || defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC1_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- #if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
- .sdio_INT_gpio = RK29SDK_WIFI_SDIO_CARD_INT,
- #endif
-
- .det_pin_info = {
- #if defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- #else
- .io = INVALID_GPIO,
- #endif
-
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
- #endif
- },
- .enable_sd_wakeup = 0,
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-/***********************************************************
-* rfkill
-************************************************************/
-#ifdef CONFIG_RFKILL_RK
-// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
-static struct rfkill_rk_platform_data rfkill_rk_platdata = {
- .type = RFKILL_TYPE_BLUETOOTH,
-
- .poweron_gpio = { // BT_REG_ON
- .io = INVALID_GPIO, //RK30_PIN3_PC7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_poweron",
- //.fgpio = GPIO3_C7,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN1_PB3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_reset",
- .fgpio = GPIO1_B3,
- },
- },
-
- .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
- .io = RK30_PIN1_PB2, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_wake",
- .fgpio = GPIO1_B2,
- },
- },
-
- .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .gpio = {
- .io = RK30_PIN0_PA4, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
- .iomux = {
- .name = "bt_wake_host",
- //.fgpio = GPIO0_A4,
- },
- },
- },
-
- .rts_gpio = { // UART_RTS, enable or disable BT's data coming
- .io = RK30_PIN1_PA3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_rts",
- .fgpio = GPIO1_A3,
- .fmux = UART0_RTSN,
- },
- }
-};
-
-static struct platform_device device_rfkill_rk = {
- .name = "rfkill_rk",
- .id = -1,
- .dev = {
- .platform_data = &rfkill_rk_platdata,
- },
-};
-#endif
-
-/***********************************************************
-* ion
-************************************************************/
-#ifdef CONFIG_ION
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-/***********************************************************
-* pwm regulator
-************************************************************/
-#ifdef CONFIG_RK30_PWM_REGULATOR
-static int pwm_voltage_map[] = {
- 800000, 825000, 850000, 875000, 900000, 925000 ,
- 950000, 975000, 1000000, 1025000, 1050000, 1075000,
- 1100000, 1125000, 1150000, 1175000, 1200000, 1225000,
- 1250000, 1275000, 1300000, 1325000, 1350000, 1375000
-};
-
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_core",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] = {
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
- .pwm_id = REG_PWM,
- .pwm_voltage = 1200000,
- .suspend_voltage = 1050000,
- .min_uV = 950000,
- .max_uV = 1400000,
- .coefficient = 504, //50.4%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-
-static void pwm_regulator_init(void)
-{
- pwm_regulator_info[0].pwm_gpio = iomux_mode_to_gpio(pwm_mode[REG_PWM]);
- pwm_regulator_info[0].pwm_iomux_pwm = pwm_mode[REG_PWM];
- pwm_regulator_info[0].pwm_iomux_gpio = iomux_switch_gpio_mode(pwm_mode[REG_PWM]);
-}
-#endif
-
-int __sramdata pwm_iomux, pwm_do, pwm_dir, pwm_en;
-#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
-
-#define GPIO0_D2_OFFSET 10
-void __sramfunc rk30_pwm_logic_suspend_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- #if 0
- /* pwm0: GPIO0_D2, pwm1: GPIO0_D3, pwm2: GPIO0_D4 */
- int off = GPIO0_D2_OFFSET + REG_PWM;
-
- sram_udelay(10000);
- pwm_iomux = grf_readl(GRF_GPIO0D_IOMUX);
- pwm_dir = grf_readl(GRF_GPIO0H_DIR);
- pwm_do = grf_readl(GRF_GPIO0H_DO);
- pwm__en = grf_readl(GRF_GPIO0H_EN);
-
- grf_writel((1<<(2 * off), GRF_GPIO0D_IOMUX);
- grf_writel((1<<(16 + off))|(1<<off), GRF_GPIO0H_DIR);
- grf_writel((1<<(16 + off))|(1<<off), GRF_GPIO0H_DO);
- #endif
-#endif
-}
-
-void __sramfunc rk30_pwm_logic_resume_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- #if 0
- /* pwm0: GPIO0_D2, pwm1: GPIO0_D3, pwm2: GPIO0_D4 */
- int off = GPIO0_D2_OFFSET + REG_PWM;
-
- grf_writel((1<<(2 * off))|pwm_iomux, GRF_GPIO0D_IOMUX);
- grf_writel(((1<<(16 + off))|pwm_dir), GRF_GPIO0L_DIR);
- grf_writel(((1<<(16 + off))|pwm_do), GRF_GPIO0L_DO);
- grf_writel(((1<<(16 + off))|pwm_en), GRF_GPIO0L_EN);
- sram_udelay(10000);
- #endif
-#endif
-}
-extern void pwm_suspend_voltage(void);
-extern void pwm_resume_voltage(void);
-
-void rk30_pwm_suspend_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_suspend_voltage();
-#endif
-}
-
-void rk30_pwm_resume_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_resume_voltage();
-#endif
-}
-
-/***********************************************************
-* pmic
-************************************************************/
-int __sramdata g_pmic_type = 0;
-
-#ifdef CONFIG_MFD_TPS65910
-#define TPS65910_HOST_IRQ PMU_INT_PIN
-#define PMU_POWER_SLEEP PMU_SLEEP_PIN
-static struct pmu_info tps65910_dcdc_info[] = {
- {
- .name = "vdd_cpu",
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vdd_core",
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vio",
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
-
-};
-static struct pmu_info tps65910_ldo_info[] = {
-
- {
- .name = "vpll", //vcc25
- .min_uv = 2500000,
- .max_uv = 2500000,
- },
-
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
-
- {
- .name = "vdig2", //vdd11
- .min_uv = 1100000,
- .max_uv = 1100000,
- },
- {
- .name = "vaux1", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "vaux2", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vaux33", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
-/* {
- .name = "vmmc", //vcca30
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
-*/
- {
- .name = "vdac", //
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
-};
-#include "../mach-rk30/board-pmu-tps65910.c"
-#endif
-
-void __sramfunc board_pmu_suspend(void)
-{
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_suspend();
- #endif
-}
-
-void __sramfunc board_pmu_resume(void)
-{
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_resume();
- #endif
-}
-
-static int gpio_118,
- gpio_11c,
- gpio_120,
- gpio_124,
- gpio_128,
- gpio_12c,
- gpio_130,
- gpio_134,
- lcd_gpio;
-
-void board_gpio_suspend(void)
-{
-
-
- gpio_118 = grf_readl(0x0118);
- gpio_11c = grf_readl(0x011c);
- gpio_120 = grf_readl(0x0120);
- gpio_124 = grf_readl(0x0124);
- gpio_128 = grf_readl(0x0128);
- gpio_12c = grf_readl(0x012c);
- gpio_130 = grf_readl(0x0130);
- gpio_134 = grf_readl(0x0134);
-// lcd_gpio = grf_readl(0x0cc);
- grf_writel(0xffffffff, 0x0118);
- grf_writel(0xffffffff, 0x011c);
- grf_writel(0xffffffff, 0x0120);
- grf_writel(0xffffffff, 0x0124);
- grf_writel(0xff7fff7f, 0x0128);
- grf_writel(0xffffffff, 0x012c);
- grf_writel(0xfefffeff, 0x0130);
- grf_writel(0xffffffff, 0x0134);
-
-
-
-
- sram_printch('9');
-
-}
- void board_gpio_resume(void)
- {
- grf_writel(0xffff0000|gpio_118, 0x0118);
- grf_writel(0xffff0000|gpio_11c, 0x011c);
- grf_writel(0xffff0000|gpio_120, 0x0120);
- grf_writel(0xffff0000|gpio_124, 0x0124);
- grf_writel(0xffff0000|gpio_128, 0x0128);
- grf_writel(0xffff0000|gpio_12c, 0x012c);
- grf_writel(0xffff0000|gpio_130, 0x0130);
- grf_writel(0xffff0000|gpio_134, 0x0134);
- }
-
-#if defined(CONFIG_GPS_RK)
-#define GPS_OSCEN_PIN RK2928_PIN1_PB0
-#define GPS_RXEN_PIN RK2928_PIN1_PB0
-
-static int rk_gps_io_init(void)
-{
- printk("%s \n", __FUNCTION__);
-
- gpio_request(GPS_OSCEN_PIN, NULL);
- gpio_direction_output(GPS_OSCEN_PIN, GPIO_LOW);
-
- iomux_set(GPS_CLK);//GPS_CLK
- iomux_set(GPS_MAG);//GPS_MAG
- iomux_set(GPS_SIGN);//GPS_SIGN
-#if 0
- gpio_request(RK30_PIN1_PA6, NULL);
- gpio_direction_output(RK30_PIN1_PA6, GPIO_LOW);
-
- gpio_request(RK30_PIN1_PA5, NULL);
- gpio_direction_output(RK30_PIN1_PA5, GPIO_LOW);
-
- gpio_request(RK30_PIN1_PA7, NULL);
- gpio_direction_output(RK30_PIN1_PA7, GPIO_LOW);
-#endif
- return 0;
-}
-static int rk_gps_power_up(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-static int rk_gps_power_down(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-static int rk_gps_reset_set(int level)
-{
- return 0;
-}
-static int rk_enable_hclk_gps(void)
-{
- struct clk *gps_aclk = NULL;
- gps_aclk = clk_get(NULL, "aclk_gps");
- if(gps_aclk) {
- clk_enable(gps_aclk);
- clk_put(gps_aclk);
- printk("%s \n", __FUNCTION__);
- }
- else
- printk("get gps aclk fail\n");
- return 0;
-}
-static int rk_disable_hclk_gps(void)
-{
- struct clk *gps_aclk = NULL;
- gps_aclk = clk_get(NULL, "aclk_gps");
- if(gps_aclk) {
- //TO wait long enough until GPS ISR is finished.
- msleep(5);
- clk_disable(gps_aclk);
- clk_put(gps_aclk);
- printk("%s \n", __FUNCTION__);
- }
- else
- printk("get gps aclk fail\n");
- return 0;
-}
-static struct rk_gps_data rk_gps_info = {
- .io_init = rk_gps_io_init,
- .power_up = rk_gps_power_up,
- .power_down = rk_gps_power_down,
- .reset = rk_gps_reset_set,
- .enable_hclk_gps = rk_enable_hclk_gps,
- .disable_hclk_gps = rk_disable_hclk_gps,
- .GpsSign = RK2928_PIN1_PA5,
- .GpsMag = RK2928_PIN1_PA4, //GPIO index
- .GpsClk = RK2928_PIN1_PA2, //GPIO index
- .GpsVCCEn = GPS_OSCEN_PIN, //GPIO index
-#if 0
- .GpsSpi_CSO = RK30_PIN1_PA4, //GPIO index
- .GpsSpiClk = RK30_PIN1_PA5, //GPIO index
- .GpsSpiMOSI = RK30_PIN1_PA7, //GPIO index
-#endif
- .GpsIrq = IRQ_GPS,
- .GpsSpiEn = 0,
- .GpsAdcCh = 2,
- .u32GpsPhyAddr = RK2928_GPS_PHYS,
- .u32GpsPhySize = RK2928_GPS_SIZE,
-};
-
-static struct platform_device rk_device_gps = {
- .name = "gps_hv5820b",
- .id = -1,
- .dev = {
- .platform_data = &rk_gps_info,
- }
- };
-#endif
-
-
-/***********************************************************
-* i2c
-************************************************************/
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C1_RK30
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8975_info,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8975_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8963)
- {
- .type = "ak8963",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8963_info,
- },
-#endif
-#if defined (CONFIG_GYRO_L3G4200D)
- {
- .type = "l3g4200d_gryo",
- .addr = 0x69,
- .flags = 0,
- .irq = L3G4200D_INT_PIN,
- .platform_data = &l3g4200d_info,
- },
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO// RK30_PIN2_PD6 //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO//RK30_PIN2_PD7 //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- return 0;
-}
-
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-
-};
-#endif
-
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(4, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-
-/***********************************************************
-* board init
-************************************************************/
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- &rk29sdk_wifi_device,
-#endif
-#ifdef CONFIG_RFKILL_RK
- &device_rfkill_rk,
-#endif
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
- &rk30_device_adc_battery,
-#endif
-#ifdef CONFIG_SND_SOC_RK3026
- &rk3026_codec,
-#endif
-#ifdef CONFIG_GPS_RK
- &rk_device_gps,
-#endif
-};
-
-static void rk30_pm_power_off(void)
-{
-#if defined(CONFIG_MFD_TPS65910)
- tps65910_device_shutdown();//tps65910 shutdown
-#endif
- port_output_off(pwr_on);
- while(1);
-}
-static int __init tp_board_init(void)
-{
- int i;
- struct port_config irq_port;
- struct port_config rst_port;
- int ret = check_tp_param();
-
- if(ret < 0)
- return ret;
-
- irq_port = get_port_config(tp_irq);
- rst_port = get_port_config(tp_rst);
-#if (defined (CONFIG_TOUCHSCREEN_GSLX680_RK3168)||defined (CONFIG_TOUCHSCREEN_GSLX680_RK3028))
- if(tp_type == TP_TYPE_GSLX680){
- gslx680_data.irq_pin = irq_port.gpio;
- gslx680_info.addr = tp_addr;
- //gslx680_data.reset_pin= rst_port.gpio;
- gslx680_data.x_max=tp_xmax;
- gslx680_data.y_max=tp_ymax;
- gslx680_data.firmVer=tp_firmVer;
- i2c_register_board_info(tp_i2c, &gslx680_info, 1);
- }
-#endif
-
-#if defined (CONFIG_TOUCHSCREEN_86V_GT811_IIC)
- if(tp_type == TP_TYPE_GT811_86V){
- gt811_data.irq_pin = irq_port.gpio;
- gt811_info.addr = tp_addr;
- gt811_data.reset_pin= rst_port.gpio;
- gt811_data.x_max=tp_xmax;
- gt811_data.y_max=tp_ymax;
- i2c_register_board_info(tp_i2c, >811_info, 1);
- }
-#endif
-
-#if defined(CONFIG_TOUCHSCREEN_GT8XX)
- if(tp_type == TP_TYPE_GT8XX){
- goodix_data.irq_pin = irq_port.gpio;
- goodix_info.addr = tp_addr;
- goodix_data.reset_pin= rst_port.gpio;
- goodix_data.x_max=tp_xmax;
- goodix_data.y_max=tp_ymax;
- i2c_register_board_info(tp_i2c, &goodix_info, 1);
- }
-#endif
- return 0;
-}
-
-
-static int __init codec_board_init(void)
-{
- struct port_config spk_port;
- struct port_config hp_port;
- struct port_config hdmi_irq_port;
- int ret = check_codec_param();
-
- if(ret < 0)
- return ret;
-
- spk_port = get_port_config(spk_ctl);
- hp_port = get_port_config(hp_det);
-
-#if defined (CONFIG_SND_RK29_SOC_RT5631)
- if(codec_type == CODEC_TYPE_RT5631){
- rt5631_data.spk_pin = spk_port.gpio;
- rt5631_info.addr = codec_addr;
- rt5631_data.hp_pin= hp_port.gpio;
- i2c_register_board_info(codec_i2c, &rt5631_info, 1);
- }
-#endif
-
-#if defined (CONFIG_SND_RK29_SOC_ES8323)
- if(codec_type == CODEC_TYPE_ES8323){
- es8323_data.spk_pin = spk_port.gpio;
- es8323_info.addr = codec_addr;
- es8323_data.hp_pin= hp_port.gpio;
- i2c_register_board_info(codec_i2c, &es8323_info, 1);
- }
-#endif
-
-#if defined (CONFIG_MFD_RK616)
-if(codec_type == CODEC_TYPE_RK616){
- rk616_pdata.spk_ctl_gpio = spk_port.gpio;
- rk616_info.addr = codec_addr;
- rk616_pdata.hdmi_irq= get_port_config(codec_hdmi_irq).gpio;
- i2c_register_board_info(codec_i2c, &rk616_info, 1);
- }
-#endif
- return 0;
-}
-
-static int __init chg_board_init(void)
-{
- int i;
- int ret = check_chg_param();
- if(ret < 0)
- return ret;
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
- //rk30_adc_battery_platdata.adc_channel = chg_adc;
- if(dc_det != -1){
- rk30_adc_battery_platdata.dc_det_pin = get_port_config(dc_det).gpio;
- printk("rk30_adc_battery_platdata.dc_det_pin %d %d",rk30_adc_battery_platdata.dc_det_pin,RK30_PIN0_PB2);
- rk30_adc_battery_platdata.dc_det_level = !get_port_config(dc_det).io.active_low;
- }
- else{
- rk30_adc_battery_platdata.dc_det_pin=INVALID_GPIO;
- }
- if(bat_low != -1){
- rk30_adc_battery_platdata.batt_low_pin = get_port_config(bat_low).gpio;
- rk30_adc_battery_platdata.batt_low_level = !get_port_config(bat_low).io.active_low;
- }
- else{
- rk30_adc_battery_platdata.batt_low_pin=INVALID_GPIO;
- }
- if(chg_ok != -1){
- rk30_adc_battery_platdata.charge_ok_pin = get_port_config(chg_ok).gpio;
- rk30_adc_battery_platdata.charge_ok_level = !get_port_config(chg_ok).io.active_low;
- }
- else{
- rk30_adc_battery_platdata.charge_ok_pin=INVALID_GPIO;
- }
- if(chg_set != -1){
- rk30_adc_battery_platdata.charge_set_pin = get_port_config(chg_set).gpio;
- rk30_adc_battery_platdata.charge_set_level = !get_port_config(chg_set).io.active_low;
- }
- else{
- rk30_adc_battery_platdata.charge_set_pin=INVALID_GPIO;
- }
- if(usb_det!= -1){
- rk30_adc_battery_platdata.usb_det_pin = get_port_config(chg_set).gpio;
- rk30_adc_battery_platdata.usb_det_level = !get_port_config(chg_set).io.active_low;
- }
- else{
- rk30_adc_battery_platdata.usb_det_pin=INVALID_GPIO;
- }
-
- if(ref_vol!= -1){
- rk30_adc_battery_platdata.reference_voltage=ref_vol;
- }
-
- if(up_res!= -1){
- rk30_adc_battery_platdata.pull_up_res=up_res;
- }
- if(down_res!= -1){
- rk30_adc_battery_platdata.pull_down_res=down_res;
- }
- if(root_chg!= -1){
- rk30_adc_battery_platdata.is_reboot_charging=root_chg;
- }
- if(save_cap!= -1){
- rk30_adc_battery_platdata.save_capacity=save_cap;
- }
- if(low_vol!= -1){
- rk30_adc_battery_platdata.low_voltage_protection=low_vol;
- }
-
- for(i=0;i<11;i++)
- {
- rk30_adc_battery_platdata.chargeArray[i]=bat_charge[i];
- rk30_adc_battery_platdata.dischargeArray[i]=bat_discharge[i];
- }
-#endif
- return 0;
-}
-
-static int __init gs_board_init(void)
-{
- int i;
- struct port_config port;
- int ret = check_gs_param();
- if(ret < 0)
- return ret;
- port = get_port_config(gs_irq);
-//mma7660
-#if defined (CONFIG_GS_MMA7660)
- if(gs_type == GS_TYPE_MMA7660){
-
- mma7660_info.irq = port.gpio;
- mma7660_info.addr = gs_addr;
- for(i = 0; i < 9; i++)
- mma7660_data.orientation[i] = gs_orig[i];
- i2c_register_board_info(gs_i2c, &mma7660_info, 1);
- }
-#endif
-
-#if defined (CONFIG_GS_LIS3DH)
- if(gs_type == GS_TYPE_LIS3DH){
- lis3dh_info.irq = port.gpio;
- lis3dh_info.addr = gs_addr;
- for(i = 0; i < 9; i++)
- lis3dh_data.orientation[i] = gs_orig[i];
- i2c_register_board_info(gs_i2c, &lis3dh_info, 1);
- }
-#endif
-
-#if defined (CONFIG_GS_MXC6225)
- if(gs_type == GS_TYPE_MXC6225){
- mxc6225_info.irq = port.gpio;
- mxc6225_info.addr = gs_addr;
- for(i = 0; i < 9; i++)
- mxc6225_data.orientation[i] = gs_orig[i];
- i2c_register_board_info(gs_i2c, &mxc6225_info, 1);
- }
-#endif
-
-#if defined (CONFIG_GS_DMT10)
- if(gs_type == GS_TYPE_DMARAD10){
- dmt10_info.irq = port.gpio;
- dmt10_info.addr = gs_addr;
- for(i = 0; i < 9; i++)
- dmt10_data.orientation[i] = gs_orig[i];
- i2c_register_board_info(gs_i2c, &dmt10_info, 1);
- }
-#endif
-
-#if defined (CONFIG_GS_MMA8452)
- if(gs_type == GS_TYPE_MMA8452){
- mma8452_info.irq = port.gpio;
- mma8452_info.addr = gs_addr;
- for(i = 0; i < 9; i++)
- mma8452_data.orientation[i] = gs_orig[i];
- i2c_register_board_info(gs_i2c, &mma8452_info, 1);
- }
-#endif
-
-#if defined (CONFIG_GS_LSM303D)
- if(gs_type == GS_TYPE_LSM303D){
- lms303d_info.irq = port.gpio;
- lms303d_info.addr = gs_addr;
- for(i = 0; i < 9; i++)
- lms303d_data.orientation[i] = gs_orig[i];
- i2c_register_board_info(gs_i2c, &lms303d_info, 1);
- }
-#endif
- return 0;
-}
-
-static int __init bl_board_init(void){
- int ret = check_bl_param();
- if(ret < 0)
- return ret;
-
- switch(bl_pwmid)
- {
- case 0:
- bl_pwm_mode = PWM0;
- break;
- case 1:
- bl_pwm_mode = PWM1;
- break;
- case 2:
- bl_pwm_mode = PWM2;
- break;
- }
-
- rk29_bl_info.pwm_id = bl_pwmid;
- rk29_bl_info.brightness_mode=bl_mode;
- rk29_bl_info.pre_div=bl_div;
- rk29_bl_info.bl_ref = bl_ref;
- rk29_bl_info.min_brightness=bl_min;
- rk29_bl_info.max_brightness=bl_max;
-
-
- return 0;
-}
-
-static int __init lcd_board_init(void)
-{
- return check_lcd_param();
-}
-
-static int __init key_board_init(void){
- int i;
- struct port_config port;
- for(i = 0; i < key_val_size; i++){
- if(key_val[i] & (1<<31)){
- key_button[i].adc_value = key_val[i] & 0xffff;
- key_button[i].gpio = INVALID_GPIO;
- }else{
- port = get_port_config(key_val[i]);
- key_button[i].gpio = port.gpio;
- key_button[i].active_low = port.io.active_low;
- }
- }
- rk29_keys_pdata.nbuttons = key_val_size;
- rk29_keys_pdata.chn = key_adc;
- return 0;
-}
-
-static int __init wifi_board_init(void)
-{
- return check_wifi_param();
-}
-
-
-static int __init rk_config_init(void)
-{
- int ret = 0;
- ret = lcd_board_init();
- if(ret < 0)
- INIT_ERR("lcd");
-
- ret = bl_board_init();
- if(ret < 0)
- INIT_ERR("backlight");
-
- ret = tp_board_init();
- if(ret < 0)
- INIT_ERR("tp");
-
- ret = gs_board_init();
- if(ret < 0)
- INIT_ERR("gsensor");
-
- ret = codec_board_init();
- if(ret < 0)
- INIT_ERR("codec");
-
- ret = key_board_init();
- if(ret < 0)
- INIT_ERR("key");
-
- ret = chg_board_init();
- if(ret < 0)
- INIT_ERR("charge");
-
- ret = wifi_board_init();
- if(ret < 0)
- INIT_ERR("wifi");
-
- return 0;
-}
-
-static void __init machine_rk30_board_init(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_regulator_init();
-#endif
- avs_init();
- pm_power_off = rk30_pm_power_off;
- rk_power_on();
- rk_config_init();
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- rk_platform_add_display_devices();
-#if defined(CONFIG_WIFI_CONTROL_FUNC)
- rk29sdk_wifi_bt_gpio_control_init();
-#elif defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- rk29sdk_wifi_combo_module_gpio_init();
-#endif
-}
-
-static void __init rk30_reserve(void)
-{
- //fb reserve
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0 buf", get_fb_size());
- resource_fb[0].end = resource_fb[0].start + get_fb_size()- 1;
- #if 0
- resource_fb[1].start = board_mem_reserve_add("ipp buf", RK30_FB0_MEM_SIZE);
- resource_fb[1].end = resource_fb[1].start + RK30_FB0_MEM_SIZE - 1;
- #endif
-
- #if defined(CONFIG_FB_ROTATE) || !defined(CONFIG_THREE_FB_BUFFER)
- resource_fb[2].start = board_mem_reserve_add("fb2 buf",get_fb_size());
- resource_fb[2].end = resource_fb[2].start + get_fb_size() - 1;
- #endif
-#endif
- //ion reserve
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
-#ifdef CONFIG_GPS_RK
- //it must be more than 8MB
- rk_gps_info.u32MemoryPhyAddr = board_mem_reserve_add("gps", SZ_8M);
-#endif
- board_mem_reserved();
-}
-
-/***********************************************************
-* clock
-************************************************************/
-static struct cpufreq_frequency_table dvfs_arm_table[] = {
- {.frequency = 312 * 1000, .index = 1200 * 1000},
- {.frequency = 504 * 1000, .index = 1200 * 1000},
- {.frequency = 816 * 1000, .index = 1250 * 1000},
- {.frequency = 1008 * 1000, .index = 1350 * 1000},
- //{.frequency = 1200 * 1000, .index = 1200 * 1000},
- //{.frequency = 1416 * 1000, .index = 1200 * 1000},
- //{.frequency = 1608 * 1000, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- {.frequency = 100 * 1000, .index = 1200 * 1000},
- {.frequency = 200 * 1000, .index = 1200 * 1000},
- {.frequency = 266 * 1000, .index = 1200 * 1000},
- {.frequency = 300 * 1000, .index = 1200 * 1000},
- {.frequency = 400 * 1000, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 1200 * 1000},
- {.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = 1200 * 1000},
- {.frequency = 400 * 1000 + DDR_FREQ_NORMAL, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-void __init board_clock_init(void)
-{
- rk2928_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
- //dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "cpu"), dvfs_arm_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
-}
-
-/************************ end *****************************/
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk2928_fixup,
- .reserve = &rk30_reserve,
- .map_io = rk2928_map_io,
- .init_irq = rk2928_init_irq,
- .timer = &rk2928_timer,
- .init_machine = machine_rk30_board_init,
-MACHINE_END
+++ /dev/null
-/*****************************************************************************************
- * arch/arm/mach-rkxx/baord-xxx-sdmmc-config.c
- *
- * Copyright (C) 2013 ROCKCHIP, Inc.
- *
- * Description:
- * define the gpio for SD-MMC-SDIO-Wifi functions according to your own projects.
- *
- * Author: Michael Xie
- * 15 Jan,2013
- * E-mail: xbw@rock-chips.com
- *
- ******************************************************************************************/
-
-/*
-** If you select the macro of CONFIG_SDMMC0_RK29_WRITE_PROTECT, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define SDMMC0_WRITE_PROTECT_PIN RK30_PIN3_PB2 //According to your own project to set the value of write-protect-pin.
-//#define SDMMC0_WRITE_PROTECT_ENABLE_VALUE GPIO_HIGH
-
-/*
-** If you select the macro of CONFIG_SDMMC1_RK29_WRITE_PROTECT, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define SDMMC1_WRITE_PROTECT_PIN RK30_PIN3_PB3 //According to your own project to set the value of write-protect-pin.
-//#define SDMMC1_WRITE_PROTECT_ENABLE_VALUE GPIO_HIGH
-
-/*
-** If you select the macro of CONFIG_RK29_SDIO_IRQ_FROM_GPIO, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define RK29SDK_WIFI_SDIO_CARD_INT RK30_PIN3_PD2
-
-
-/*
-* define sdcard PowerEn-pin
-*/
-#define RK29SDK_SD_CARD_PWR_EN INVALID_GPIO
-#define RK29SDK_SD_CARD_PWR_EN_LEVEL GPIO_LOW
-int rk31sdk_get_sdmmc0_pin_io_voltage(void)
-{
- int voltage;
-#define RK31SDK_SET_SDMMC0_PIN_VOLTAGE
-
- /**************************************************************************************
- ** Please tell me how much voltage of your SDMMC0-pin in your project.
- **
- ** ÀýÈç: ÓеÄÏîÄ¿£¬ËüµÄSDMMC0ËùÔÚµÄRKÖ÷¿ØµÄIO×飬ÏëÓÃ1.8V, ¶ø¿¨±¾ÉíÓÃ3.3V,
- ** ¶øÖмäͨ¹ý¸öµçƽת»».ÄÇô£¬Äú´Ëʱ£¬Ó¦¸ÃÉèÖÃÏÂÃæµÄvoltageֵΪ 1.8V(¼´1800mv)
- ***************************************************************************************/
- voltage = 3300; //default the voltage 3300mv.
-
- return voltage;
-}
-
-/*
-* define the card-detect-pin.
-*/
-#define RK29SDK_SD_CARD_DETECT_N RK30_PIN2_PA7 //According to your own project to set the value of card-detect-pin.
-#define RK29SDK_SD_CARD_INSERT_LEVEL GPIO_LOW // set the voltage of insert-card. Please pay attention to the default setting.
-
-/*
-* Define wifi module's power and reset gpio, and gpio sensitive level.
-* Please set the value according to your own project.
-*
-* Well, you just own engineering module to set the value in the corresponding module branch.
-* Otherwise, you do not define this macro, eliminate it.
-*
-*/
-#if defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU) || defined(CONFIG_RTL8723AU) || defined(CONFIG_MT7601)
- //#define CONFIG_USB_WIFI_POWER_CONTROLED_BY_GPIO
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN0_PD3
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_LOW//GPIO_HIGH
-
-#elif defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319) || defined(CONFIG_RKWIFI) || defined(CONFIG_RTL8189ES)
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD3
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN0_PC2 // RK30_PIN2_PA7
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
-
-#elif defined(CONFIG_MT5931_MT6622) || defined(CONFIG_MT5931)
-
- #ifdef CONFIG_MACH_RK3168_LR097
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- //#define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- //#define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
-
- #else
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN0_PA5
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #endif
-
-#elif defined(CONFIG_MT6620)
- #define COMBO_MODULE_MT6620_CDT 0 // to control antsel2,antsel3 and gps_lan foot when using AcSip or Cdtech chip.
- //- 1--use Cdtech chip; 0--unuse CDT chip
-
- //power, PMU_EN//hjc test
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN0_PB5
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- //reset, DAIRST,SYSRST_B
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- //VDDIO
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL RK30_PIN0_PD2 //You do not get control of the foot, and you do not need to define the macro
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_ENABLE_VALUE GPIO_HIGH
- //WIFI_INT_B
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
- //BGF_INT_B
- #define RK30SDK_WIFI_GPIO_BGF_INT_B RK30_PIN0_PA5
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_ENABLE_VALUE GPIO_HIGH
- //GPS_SYNC
- #define RK30SDK_WIFI_GPIO_GPS_SYNC RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_ENABLE_VALUE GPIO_HIGH
-
- #if COMBO_MODULE_MT6620_CDT
- //ANTSEL2
- #define RK30SDK_WIFI_GPIO_ANTSEL2 RK30_PIN4_PD4
- #define RK30SDK_WIFI_GPIO_ANTSEL2_ENABLE_VALUE GPIO_LOW //use 6620 in CDT chip, LOW--work; High--no work.
- //ANTSEL3
- #define RK30SDK_WIFI_GPIO_ANTSEL3 RK30_PIN4_PD3
- #define RK30SDK_WIFI_GPIO_ANTSEL3_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- //GPS_LAN
- #define RK30SDK_WIFI_GPIO_GPS_LAN RK30_PIN4_PD6
- #define RK30SDK_WIFI_GPIO_GPS_LAN_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- #endif // #if COMBO_MODULE_MT6620_CDT--#endif
-#endif
-
-#ifndef RK30SDK_WIFI_GPIO_WIFI_INT_B
-#define RK30SDK_WIFI_GPIO_WIFI_INT_B INVALID_GPIO
-#define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
-#endif
-
-int rk31sdk_get_sdio_wifi_voltage(void)
-{
- int voltage;
-
- /******************************************************************************
- ** Please tell me how much wifi-module uses voltage in your project.
- ******************************************************************************/
-#if defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319) || defined(CONFIG_RKWIFI)
- voltage = 1800 ; //power 1800mV
-
-#elif defined(CONFIG_MT5931_MT6622)||defined(CONFIG_MT5931)
- voltage = 1800 ; //power 1800V
-#elif defined(CONFIG_MT6620)
- voltage = 1800 ; //power 2800V
-#elif defined(CONFIG_RDA5990)||defined(CONFIG_RTL8723AS)
- voltage = 3300 ; //power 3300V
-#else
- //default, sdio use 3.0V
- voltage = 3000 ; //power 3000V
-#endif
-
- return voltage;
-}
-
-
-
+++ /dev/null
-/*
- * Copyright (C) 2013 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <linux/rk_fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/mfd/tps65910.h>
-#include <linux/regulator/act8846.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/dvfs.h>
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-
-#include <plat/efuse.h>
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-
-#ifdef CONFIG_SND_SOC_RK3026
-#include "../../../sound/soc/codecs/rk3026_codec.h"
-#endif
-
-#if defined(CONFIG_RK_HDMI)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#if defined(CONFIG_GPS_RK)
-#include "../../../drivers/misc/gps/rk_gps/rk_gps.h"
-#endif
-#include "board-rk3026-86v-camera.c"
-
-/***********************************************************
-* board config
-************************************************************/
-//system power on
-#define POWER_ON_PIN RK30_PIN1_PA2 //PWR_HOLD
-
-//touchscreen
-//#define TOUCH_RST_PIN RK2928_PIN0_PD3
-//#define TOUCH_RST_VALUE GPIO_HIGH
-//#define TOUCH_PWR_PIN RK2928_PIN2_PB3
-//#define TOUCH_PWR_VALUE GPIO_LOW
-#define TOUCH_INT_PIN RK2928_PIN1_PB0
-
-//backlight
-#define LCD_DISP_ON_PIN
-#define BL_PWM 0 // (0 ~ 2)
-#define PWM_EFFECT_VALUE 0
-//#define PWM_MUX_NAME GPIO0D2_PWM_0_NAME
-//#define PWM_MUX_MODE GPIO0D_PWM_0
-//#define PWM_MUX_MODE_GPIO GPIO0D_GPIO0D2
-//#define PWM_GPIO RK2928_PIN0_PD2
-
-
-#define BL_EN_PIN RK2928_PIN3_PC1
-#define BL_EN_VALUE GPIO_HIGH
-#define BL_EN_MUX_NAME GPIO3C1_OTG_DRVVBUS_NAME
-#define BL_EN_MUX_MODE GPIO3C_GPIO3C1
-
-
-//fb
-#define LCD_EN_PIN RK2928_PIN1_PB3
-#define LCD_EN_VALUE GPIO_LOW
-#define LCD_CS_PIN INVALID_GPIO
-#define LCD_CS_VALUE GPIO_HIGH
-
-//gsensor
-#define GS_INT_PIN RK2928_PIN1_PB2
-
-//sdmmc
-//Reference to board-rk3026-tb-sdmmc-config.c
-
-//keyboard
-//#define RK31XX_MAINBOARD_V1 //if mainboard is RK31XX_MAINBOARD_V1.0
-#define PLAY_ON_PIN RK30_PIN1_PA4 //wakeup key
-
-//pwm regulator
-#define REG_PWM 1 // (0 ~ 2)
-
-//pmic
-#define PMU_INT_PIN RK30_PIN1_PB1
-#define PMU_SLEEP_PIN RK30_PIN1_PA1
-
-//ion reserve memory
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-
-static int pwm_mode[] = {PWM0, PWM1, PWM2};
-static inline int rk_gpio_request(int gpio, int direction, int value, const char *label)
-{
- int ret = 0;
- unsigned long flags = 0;
-
- if(!gpio_is_valid(gpio))
- return 0;
-
- if(direction == GPIOF_DIR_IN)
- flags = GPIOF_IN;
- else if(value == GPIO_LOW)
- flags = GPIOF_OUT_INIT_LOW;
- else
- flags = GPIOF_OUT_INIT_HIGH;
-
- ret = gpio_request_one(gpio, flags, label);
- if(ret < 0)
- pr_err("Failed to request '%s'\n", label);
-
- return ret;
-}
-
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* touchscreen
-************************************************************/
-#if defined(CONFIG_TOUCHSCREEN_GSLX680_RK3028)
-//#define TOUCH_RESET_PIN RK30_PIN0_PC1
-//#define TOUCH_EN_PIN NULL
-//#define TOUCH_INT_PIN RK30_PIN0_PB4
-
- int gslx680_init_platform_hw(void)
- {
- #if 0
- if(gpio_request(TOUCH_RST_PIN,NULL) != 0){
- gpio_free(TOUCH_RST_PIN);
- printk("gslx680_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- #endif
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("gslx680_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- #if 0
- gpio_direction_output(TOUCH_RST_PIN, TOUCH_RST_VALUE);
- mdelay(10);
- gpio_set_value(TOUCH_RST_PIN,!TOUCH_RST_VALUE);
- mdelay(10);
- gpio_set_value(TOUCH_RST_PIN,TOUCH_RST_VALUE);
- msleep(300);
- #endif
- return 0;
-
- }
-
- struct ts_hw_data gslx680_info = {
- //.reset_gpio = TOUCH_RST_PIN,
- .touch_en_gpio = TOUCH_INT_PIN,
- .init_platform_hw = gslx680_init_platform_hw,
- };
-#endif
-
-
-#if defined(CONFIG_TOUCHSCREEN_GT8XX)
-static int goodix_init_platform_hw(void)
-{
- int ret = 0;
-
- ret = rk_gpio_request(TOUCH_PWR_PIN, GPIOF_DIR_OUT, TOUCH_PWR_VALUE, "touch_pwr");
- if(ret < 0)
- return ret;
- msleep(100);
-
- ret = rk_gpio_request(TOUCH_RST_PIN, GPIOF_DIR_OUT, TOUCH_RST_VALUE, "touch_rst");
- if(ret < 0)
- return ret;
- msleep(100);
-
- return 0;
-}
-
-struct goodix_platform_data goodix_info = {
- .model = 8105,
- .irq_pin = TOUCH_INT_PIN,
- .rest_pin = TOUCH_RST_PIN,
- .init_platform_hw = goodix_init_platform_hw,
-};
-#endif
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
-
- iomux_set(pwm_mode[BL_PWM]);
- //ret = rk_gpio_request(RK30_PIN0_PD2, GPIOF_DIR_OUT, GPIO_LOW, "PWM");
- msleep(50);
-#ifdef LCD_DISP_ON_PIN
- ret = rk_gpio_request(BL_EN_PIN, GPIOF_DIR_OUT, BL_EN_VALUE, "bl_en");
- if(ret < 0)
- return ret;
-#endif
- return 0;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int pwm_gpio;
-#ifdef LCD_DISP_ON_PIN
- gpio_free(BL_EN_PIN);
-#endif
- pwm_gpio = iomux_mode_to_gpio(pwm_mode[BL_PWM]);
- return rk_gpio_request(BL_EN_PIN, GPIOF_DIR_OUT, GPIO_LOW, "BL_PWM");
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret, pwm_gpio = iomux_mode_to_gpio(pwm_mode[BL_PWM]);
-
- ret = rk_gpio_request(pwm_gpio, GPIOF_DIR_OUT, GPIO_LOW, "BL_PWM");
- if(ret < 0)
- return ret;
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, !BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- int pwm_gpio = iomux_mode_to_gpio(pwm_mode[BL_PWM]);
-
- gpio_free(pwm_gpio);
- iomux_set(pwm_mode[BL_PWM]);
-#ifdef LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .pwm_id = BL_PWM,
- .min_brightness=100,
- .max_brightness=255,
- .brightness_mode = BRIGHTNESS_MODE_CONIC,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
- .pre_div = 10000,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-#endif
-
-/***********************************************************
-* fb
-************************************************************/
-#ifdef CONFIG_FB_ROCKCHIP
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
-
- ret = rk_gpio_request(LCD_CS_PIN, GPIOF_DIR_OUT, LCD_CS_VALUE, "lcd_cs");
- if(ret < 0)
- return ret;
-
- return rk_gpio_request(LCD_EN_PIN, GPIOF_DIR_OUT, LCD_EN_VALUE, "lcd_en");
-}
-
-static int rk_fb_io_disable(void)
-{
- gpio_set_value(LCD_CS_PIN, !LCD_CS_VALUE);
- gpio_set_value(LCD_EN_PIN, !LCD_EN_VALUE);
-
- return 0;
-}
-
-static int rk_fb_io_enable(void)
-{
- gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE);
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
-
- return 0;
-}
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
-struct rk29fb_info lcdc0_screen_info = {
-#if defined(CONFIG_RK_HDMI) && defined(CONFIG_HDMI_SOURCE_LCDC0) && defined(CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL)
- .prop = EXTEND, //extend display device
- .io_init = NULL,
- .io_disable = NULL,
- .io_enable = NULL,
- .set_screen_info = hdmi_init_lcdc,
-#else
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-#endif
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
-struct rk29fb_info lcdc1_screen_info = {
-#if defined(CONFIG_RK_HDMI) && defined(CONFIG_HDMI_SOURCE_LCDC1) && defined(CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL)
- .prop = EXTEND, //extend display device
- .io_init = NULL,
- .io_disable = NULL,
- .io_enable = NULL,
- .set_screen_info = hdmi_init_lcdc,
-#else
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-#endif
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
-static struct resource resource_lcdc0[] = {
- [0] = {
- .name = "lcdc0 reg",
- .start = RK3026_LCDC0_PHYS,
- .end = RK3026_LCDC0_PHYS + RK3026_LCDC0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc0 irq",
- .start = IRQ_LCDC,
- .end = IRQ_LCDC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc0 = {
- .name = "rk30-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc0),
- .resource = resource_lcdc0,
- .dev = {
- .platform_data = &lcdc0_screen_info,
- },
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
-static struct resource resource_lcdc1[] = {
- [0] = {
- .name = "lcdc1 reg",
- .start = RK3026_LCDC1_PHYS,
- .end = RK3026_LCDC1_PHYS + RK3026_LCDC1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc1 irq",
- .start = IRQ_LCDC1,
- .end = IRQ_LCDC1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc1 = {
- .name = "rk30-lcdc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resource_lcdc1),
- .resource = resource_lcdc1,
- .dev = {
- .platform_data = &lcdc1_screen_info,
- },
-};
-#endif
-
-static int rk_platform_add_display_devices(void)
-{
- struct platform_device *fb = NULL; //fb
- struct platform_device *lcdc0 = NULL; //lcdc0
- struct platform_device *lcdc1 = NULL; //lcdc1
- struct platform_device *bl = NULL; //backlight
-#ifdef CONFIG_FB_ROCKCHIP
- fb = &device_fb;
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
- lcdc0 = &device_lcdc0,
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
- lcdc1 = &device_lcdc1,
-#endif
-
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- bl = &rk29_device_backlight,
-#endif
- __rk_platform_add_display_devices(fb,lcdc0,lcdc1,bl);
-
- return 0;
-}
-
-
-/***********************************************************
-* gsensor
-************************************************************/
-// mma 8452 gsensor
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN GS_INT_PIN
-static int mma8452_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data mma8452_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma8452_init_platform_hw,
- .orientation = {-1, 0, 0, 0, -1, 0, 0, 0, 1},
-};
-#endif
-
-// lsm303d gsensor
-#if defined (CONFIG_GS_LSM303D)
-#define LSM303D_INT_PIN GS_INT_PIN
-static int lms303d_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data lms303d_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lms303d_init_platform_hw,
- .orientation = {-1, 0, 0, 0, -1, 0, 0, 0, 1},
-};
-#endif
-
-
-/*MMA7660 gsensor*/
-#if defined (CONFIG_GS_MMA7660)
-#define MMA7660_INT_PIN GS_INT_PIN
-
-static int mma7660_init_platform_hw(void)
-{
- //rk30_mux_api_set(GPIO1B2_SPI_RXD_UART1_SIN_NAME, GPIO1B_GPIO1B2);
-
- return 0;
-}
-
-static struct sensor_platform_data mma7660_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma7660_init_platform_hw,
- .orientation = {0, 1, 0, 1, 0, 0, 0, 0, -1},
-};
-#endif
-
-
-#if defined (CONFIG_GS_MXC6225)
-#define MXC6225_INT_PIN GS_INT_PIN
-
-static int mxc6225_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data mxc6225_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 0,
- .poll_delay_ms = 30,
- .init_platform_hw = mxc6225_init_platform_hw,
- .orientation = { 1, 0, 0, 0, 1, 0, 0, 0, 0},
-};
-#endif
-#if defined (CONFIG_GS_LIS3DH)
-#define LIS3DH_INT_PIN GS_INT_PIN
-
- static int lis3dh_init_platform_hw(void)
- {
-
- return 0;
- }
-
- static struct sensor_platform_data lis3dh_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lis3dh_init_platform_hw,
- .orientation = {1, 0, 0, 0, 1, 0, 0, 0, 1},
- };
-#endif
-
-#if defined (CONFIG_COMPASS_AK8975)
-static struct sensor_platform_data akm8975_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-#if defined (CONFIG_COMPASS_AK8963)
-static struct sensor_platform_data akm8963_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {0, 1, 0},
- {1, 0, 0},
- {0, 0, -1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {0, -1, 0},
- {-1, 0, 0},
- {0, 0, -1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-
-#if defined(CONFIG_GYRO_L3G4200D)
-
-#include <linux/l3g4200d.h>
-#define L3G4200D_INT_PIN RK30_PIN0_PB4
-
-static int l3g4200d_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data l3g4200d_info = {
- .type = SENSOR_TYPE_GYROSCOPE,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
- .init_platform_hw = l3g4200d_init_platform_hw,
- .x_min = 40,//x_min,y_min,z_min = (0-100) according to hardware
- .y_min = 40,
- .z_min = 20,
-};
-
-#endif
-
-#ifdef CONFIG_LS_CM3217
-static struct sensor_platform_data cm3217_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 0,
- .poll_delay_ms = 500,
-};
-
-#endif
-
-/***********************************************************
-* keyboard
-************************************************************/
-#include <plat/key.h>
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = PLAY_ON_PIN,
- .active_low = PRESS_LEV_LOW,
- .wakeup = 1,
- },
-/* disable adc keyboard,
- * because rk280a adc reference voltage is 3.3V, but
- * rk30xx mainbord key's supply voltage is 2.5V and
- * rk31xx mainbord key's supply voltage is 1.8V.
- */
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .gpio = INVALID_GPIO,
- .adc_value = 1,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .gpio = INVALID_GPIO,
- .adc_value = 512,
- .active_low = PRESS_LEV_LOW,
- },
- /*{
- .desc = "menu",
- .code = EV_MENU,
- .adc_value = 133,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .code = KEY_HOME,
- .adc_value = 550,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .adc_value = 333,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "camera",
- .code = KEY_CAMERA,
- .adc_value = 742,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },*/
-
-};
-
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = 3, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-/***********************************************************
-* usb wifi
-************************************************************/
-#if defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU)
-
-static void rkusb_wifi_power(int on) {
- int ret=0;
- struct regulator *ldo = NULL;
- printk("hjc:%s[%d],on=%d\n",__func__,__LINE__,on);
-#if defined(CONFIG_MFD_TPS65910)
- if (pmic_is_tps65910())
- ldo = regulator_get(NULL, "vmmc"); //vccio_wl
-#endif
-#if defined(CONFIG_REGULATOR_ACT8931)
- if(pmic_is_act8931())
- ldo = regulator_get(NULL, "act_ldo4"); //vccio_wl
-#endif
-
- if(!on) {
-
- regulator_set_voltage(ldo, 3000000, 3000000);
- ret = regulator_enable(ldo);
- if(ret != 0){
- printk("faild to enable vmmc\n");
- }
- printk("%s: vccio_wl enable\n", __func__);
- } else {
- printk("%s: vccio_wl disable\n", __func__);
- regulator_disable(ldo);
- if(ret != 0){
- printk("faild to disable vmmc\n");
- }
- }
- regulator_put(ldo);
- udelay(100);
-}
-
-#endif
-
-
-
-/***********************************************************
-* sdmmc
-************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "board-rk3026-86v-sdmmc-config.c"
-#include "../plat-rk/rk-sdmmc-ops.c"
-#include "../plat-rk/rk-sdmmc-wifi.c"
-#endif //endif ---#ifdef CONFIG_SDMMC_RK29
-
-#ifdef CONFIG_SDMMC0_RK29
-#define CONFIG_SDMMC0_USE_DMA
-static int rk29_sdmmc0_cfg_gpio(void)
-{
- rk29_sdmmc_set_iomux(0, 0xFFFF);
- #if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- iomux_set_gpio_mode(iomux_gpio_to_mode(RK29SDK_SD_CARD_DETECT_N));
- #else
- iomux_set(MMC0_DETN);
- #endif
-
- #if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
- #endif
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
- .set_iomux = rk29_sdmmc_set_iomux,
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) && defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- .status = rk29sdk_wifi_mmc0_status,
- .register_status_notify = rk29sdk_wifi_mmc0_status_register,
-#endif
-
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .power_en = RK29SDK_SD_CARD_PWR_EN,
- .power_en_level = RK29SDK_SD_CARD_PWR_EN_LEVEL,
-#else
- .power_en = INVALID_GPIO,
- .power_en_level = GPIO_LOW,
-#endif
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC0_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- .det_pin_info = {
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N, //INVALID_GPIO,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
- #endif
- },
-
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
- .set_iomux = rk29_sdmmc_set_iomux,
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC) || defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC1_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- #if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
- .sdio_INT_gpio = RK29SDK_WIFI_SDIO_CARD_INT,
- #endif
-
- .det_pin_info = {
- #if defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- #else
- .io = INVALID_GPIO,
- #endif
-
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
- #endif
- },
- .enable_sd_wakeup = 0,
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
-
-#define DC_DET_PIN RK30_PIN1_PA5
-#define CHARGE_OK_PIN INVALID_GPIO//RK30_PIN0_PC6
-
-static int rk30_adc_battery_io_init(void){
- //dc charge detect pin
- int ret=0;
- if (DC_DET_PIN != INVALID_GPIO){
- ret = gpio_request(RK30_PIN1_PA5, NULL);
- if (ret) {
- printk("failed to request dc_det gpio\n");
- }
-
- gpio_pull_updown(DC_DET_PIN, PullDisable);//important
- ret = gpio_direction_input(DC_DET_PIN);
- if (ret) {
- printk("failed to set gpio dc_det input\n");
- }
- }
-
- //charge ok detect
- if (CHARGE_OK_PIN != INVALID_GPIO){
- ret = gpio_request(RK30_PIN0_PC6, NULL);
- if (ret) {
- printk("failed to request charge_ok gpio\n");
- }
-
- gpio_pull_updown(CHARGE_OK_PIN, GPIOPullUp);//important
- ret = gpio_direction_input(CHARGE_OK_PIN);
- if (ret) {
- printk("failed to set gpio charge_ok input\n");
- }
- }
- ret = gpio_request(RK30_PIN3_PD6, NULL);
- if (ret) {
- printk("failed to request charge_ok gpio\n");
- }
-
- gpio_pull_updown(RK30_PIN3_PD6, GPIOPullUp);//important
- // ret = gpio_direction_input(RK30_PIN3_PD6);
- // if (ret) {
- // printk("failed to set gpio charge_ok input\n");
- // }
-
-
-}
-
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = RK30_PIN1_PA5,
- .batt_low_pin = INVALID_GPIO,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = INVALID_GPIO,//RK30_PIN1_PA0,
- .usb_det_pin = INVALID_GPIO,
- .dc_det_level = GPIO_LOW,
- .charge_ok_level = GPIO_HIGH,
-
- .reference_voltage = 3300, // the rK2928 is 3300;RK3066 and rk29 are 2500;rk3066B is 1800;
- .pull_up_res = 200, //divider resistance , pull-up resistor
- .pull_down_res = 200, //divider resistance , pull-down resistor
-
- .io_init = rk30_adc_battery_io_init,
- .is_reboot_charging = 1,
- .save_capacity = 1 ,
- .low_voltage_protection = 3600,
-};
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-
-
-/***********************************************************
-* rfkill
-************************************************************/
-#ifdef CONFIG_RFKILL_RK
-// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
-static struct rfkill_rk_platform_data rfkill_rk_platdata = {
- .type = RFKILL_TYPE_BLUETOOTH,
-
- .poweron_gpio = { // BT_REG_ON
- .io = INVALID_GPIO, //RK30_PIN3_PC7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_poweron",
- //.fgpio = GPIO3_C7,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN1_PB3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_reset",
- .fgpio = GPIO1_B3,
- },
- },
-
- .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
- .io = RK30_PIN1_PB2, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_wake",
- .fgpio = GPIO1_B2,
- },
- },
-
- .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .gpio = {
- .io = RK30_PIN0_PA4, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
- .iomux = {
- .name = "bt_wake_host",
- //.fgpio = GPIO0_A4,
- },
- },
- },
-
- .rts_gpio = { // UART_RTS, enable or disable BT's data coming
- .io = RK30_PIN1_PA3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_rts",
- .fgpio = GPIO1_A3,
- .fmux = UART0_RTSN,
- },
- }
-};
-
-static struct platform_device device_rfkill_rk = {
- .name = "rfkill_rk",
- .id = -1,
- .dev = {
- .platform_data = &rfkill_rk_platdata,
- },
-};
-#endif
-
-/***********************************************************
-* ion
-************************************************************/
-#ifdef CONFIG_ION
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-/***********************************************************
-* pwm regulator
-************************************************************/
-#ifdef CONFIG_RK30_PWM_REGULATOR
-static int pwm_voltage_map[] = {
- 800000, 825000, 850000, 875000, 900000, 925000 ,
- 950000, 975000, 1000000, 1025000, 1050000, 1075000,
- 1100000, 1125000, 1150000, 1175000, 1200000, 1225000,
- 1250000, 1275000, 1300000, 1325000, 1350000, 1375000
-};
-
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_core",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] = {
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
- .pwm_id = REG_PWM,
- .pwm_voltage = 1200000,
- .suspend_voltage = 1050000,
- .min_uV = 950000,
- .max_uV = 1400000,
- .coefficient = 504, //50.4%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-
-static void pwm_regulator_init(void)
-{
- pwm_regulator_info[0].pwm_gpio = iomux_mode_to_gpio(pwm_mode[REG_PWM]);
- pwm_regulator_info[0].pwm_iomux_pwm = pwm_mode[REG_PWM];
- pwm_regulator_info[0].pwm_iomux_gpio = iomux_switch_gpio_mode(pwm_mode[REG_PWM]);
-}
-#endif
-
-int __sramdata pwm_iomux, pwm_do, pwm_dir, pwm_en;
-#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
-
-#define GPIO0_D2_OFFSET 10
-void __sramfunc rk30_pwm_logic_suspend_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- #if 0
- /* pwm0: GPIO0_D2, pwm1: GPIO0_D3, pwm2: GPIO0_D4 */
- int off = GPIO0_D2_OFFSET + REG_PWM;
-
- sram_udelay(10000);
- pwm_iomux = grf_readl(GRF_GPIO0D_IOMUX);
- pwm_dir = grf_readl(GRF_GPIO0H_DIR);
- pwm_do = grf_readl(GRF_GPIO0H_DO);
- pwm__en = grf_readl(GRF_GPIO0H_EN);
-
- grf_writel((1<<(2 * off), GRF_GPIO0D_IOMUX);
- grf_writel((1<<(16 + off))|(1<<off), GRF_GPIO0H_DIR);
- grf_writel((1<<(16 + off))|(1<<off), GRF_GPIO0H_DO);
- #endif
-#endif
-}
-
-void __sramfunc rk30_pwm_logic_resume_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- #if 0
- /* pwm0: GPIO0_D2, pwm1: GPIO0_D3, pwm2: GPIO0_D4 */
- int off = GPIO0_D2_OFFSET + REG_PWM;
-
- grf_writel((1<<(2 * off))|pwm_iomux, GRF_GPIO0D_IOMUX);
- grf_writel(((1<<(16 + off))|pwm_dir), GRF_GPIO0L_DIR);
- grf_writel(((1<<(16 + off))|pwm_do), GRF_GPIO0L_DO);
- grf_writel(((1<<(16 + off))|pwm_en), GRF_GPIO0L_EN);
- sram_udelay(10000);
- #endif
-#endif
-}
-extern void pwm_suspend_voltage(void);
-extern void pwm_resume_voltage(void);
-
-void rk30_pwm_suspend_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_suspend_voltage();
-#endif
-}
-
-void rk30_pwm_resume_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_resume_voltage();
-#endif
-}
-
-/***********************************************************
-* pmic
-************************************************************/
-int __sramdata g_pmic_type = 0;
-
-#ifdef CONFIG_MFD_TPS65910
-#define TPS65910_HOST_IRQ PMU_INT_PIN
-#define PMU_POWER_SLEEP PMU_SLEEP_PIN
-static struct pmu_info tps65910_dcdc_info[] = {
- {
- .name = "vdd_cpu",
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vdd_core",
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vio",
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
-};
-
-static struct pmu_info tps65910_ldo_info[] = {
-
- {
- .name = "vpll", //vcc25
- .min_uv = 2500000,
- .max_uv = 2500000,
- },
-
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
-
- {
- .name = "vdig2", //vdd11
- .min_uv = 1100000,
- .max_uv = 1100000,
- },
- {
- .name = "vaux1", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "vaux2", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vaux33", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
-/* {
- .name = "vmmc", //vcca30
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
-*/
- {
- .name = "vdac", //
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
-};
-#include "../mach-rk30/board-pmu-tps65910.c"
-#endif
-
-void __sramfunc board_pmu_suspend(void)
-{
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_suspend();
- #endif
-}
-
-void __sramfunc board_pmu_resume(void)
-{
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_resume();
- #endif
-}
-
-static int gpio_118,
- gpio_11c,
- gpio_120,
- gpio_124,
- gpio_128,
- gpio_12c,
- gpio_130,
- gpio_134,
- lcd_gpio;
-
-void board_gpio_suspend(void)
-{
-
-
- gpio_118 = grf_readl(0x0118);
- gpio_11c = grf_readl(0x011c);
- gpio_120 = grf_readl(0x0120);
- gpio_124 = grf_readl(0x0124);
- gpio_128 = grf_readl(0x0128);
- gpio_12c = grf_readl(0x012c);
- gpio_130 = grf_readl(0x0130);
- gpio_134 = grf_readl(0x0134);
-// lcd_gpio = grf_readl(0x0cc);
- grf_writel(0xffffffff, 0x0118);
- grf_writel(0xffffffff, 0x011c);
- grf_writel(0xffffffff, 0x0120);
- grf_writel(0xffffffff, 0x0124);
- grf_writel(0xff7fff7f, 0x0128);
- grf_writel(0xffffffff, 0x012c);
- grf_writel(0xfefffeff, 0x0130);
- grf_writel(0xffffffff, 0x0134);
-
-
-
-
- sram_printch('9');
-
-}
- void board_gpio_resume(void)
- {
- grf_writel(0xffff0000|gpio_118, 0x0118);
- grf_writel(0xffff0000|gpio_11c, 0x011c);
- grf_writel(0xffff0000|gpio_120, 0x0120);
- grf_writel(0xffff0000|gpio_124, 0x0124);
- grf_writel(0xffff0000|gpio_128, 0x0128);
- grf_writel(0xffff0000|gpio_12c, 0x012c);
- grf_writel(0xffff0000|gpio_130, 0x0130);
- grf_writel(0xffff0000|gpio_134, 0x0134);
- }
-
-#ifdef CONFIG_SND_SOC_RK3026
-struct rk3026_codec_pdata rk3026_codec_pdata_info={
- .spk_ctl_gpio = INVALID_GPIO,
- .hp_ctl_gpio = RK2928_PIN1_PA0,
-};
-
-static struct resource resources_acodec[] = {
- {
- .start = RK2928_ACODEC_PHYS,
- .end = RK2928_ACODEC_PHYS + RK2928_ACODEC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device rk3026_codec = {
- .name = "rk3026-codec",
- .id = -1,
- .resource = resources_acodec,
- .dev = {
- .platform_data = &rk3026_codec_pdata_info,
- }
-};
-#endif
-#if defined(CONFIG_GPS_RK)
-#define GPS_OSCEN_PIN RK2928_PIN1_PB0
-#define GPS_RXEN_PIN RK2928_PIN1_PB0
-
-static int rk_gps_io_init(void)
-{
- printk("%s \n", __FUNCTION__);
-
- gpio_request(GPS_OSCEN_PIN, NULL);
- gpio_direction_output(GPS_OSCEN_PIN, GPIO_LOW);
-
- iomux_set(GPS_CLK);//GPS_CLK
- iomux_set(GPS_MAG);//GPS_MAG
- iomux_set(GPS_SIGN);//GPS_SIGN
-#if 0
- gpio_request(RK30_PIN1_PA6, NULL);
- gpio_direction_output(RK30_PIN1_PA6, GPIO_LOW);
-
- gpio_request(RK30_PIN1_PA5, NULL);
- gpio_direction_output(RK30_PIN1_PA5, GPIO_LOW);
-
- gpio_request(RK30_PIN1_PA7, NULL);
- gpio_direction_output(RK30_PIN1_PA7, GPIO_LOW);
-#endif
- return 0;
-}
-static int rk_gps_power_up(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-static int rk_gps_power_down(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-static int rk_gps_reset_set(int level)
-{
- return 0;
-}
-static int rk_enable_hclk_gps(void)
-{
- struct clk *gps_aclk = NULL;
- gps_aclk = clk_get(NULL, "aclk_gps");
- if(gps_aclk) {
- clk_enable(gps_aclk);
- clk_put(gps_aclk);
- printk("%s \n", __FUNCTION__);
- }
- else
- printk("get gps aclk fail\n");
- return 0;
-}
-static int rk_disable_hclk_gps(void)
-{
- struct clk *gps_aclk = NULL;
- gps_aclk = clk_get(NULL, "aclk_gps");
- if(gps_aclk) {
- //TO wait long enough until GPS ISR is finished.
- msleep(5);
- clk_disable(gps_aclk);
- clk_put(gps_aclk);
- printk("%s \n", __FUNCTION__);
- }
- else
- printk("get gps aclk fail\n");
- return 0;
-}
-static struct rk_gps_data rk_gps_info = {
- .io_init = rk_gps_io_init,
- .power_up = rk_gps_power_up,
- .power_down = rk_gps_power_down,
- .reset = rk_gps_reset_set,
- .enable_hclk_gps = rk_enable_hclk_gps,
- .disable_hclk_gps = rk_disable_hclk_gps,
- .GpsSign = RK2928_PIN1_PA5,
- .GpsMag = RK2928_PIN1_PA4, //GPIO index
- .GpsClk = RK2928_PIN1_PA2, //GPIO index
- .GpsVCCEn = GPS_OSCEN_PIN, //GPIO index
-#if 0
- .GpsSpi_CSO = RK30_PIN1_PA4, //GPIO index
- .GpsSpiClk = RK30_PIN1_PA5, //GPIO index
- .GpsSpiMOSI = RK30_PIN1_PA7, //GPIO index
-#endif
- .GpsIrq = IRQ_GPS,
- .GpsSpiEn = 0,
- .GpsAdcCh = 2,
- .u32GpsPhyAddr = RK2928_GPS_PHYS,
- .u32GpsPhySize = RK2928_GPS_SIZE,
-};
-
-static struct platform_device rk_device_gps = {
- .name = "gps_hv5820b",
- .id = -1,
- .dev = {
- .platform_data = &rk_gps_info,
- }
- };
-#endif
-/***********************************************************
-* i2c
-************************************************************/
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C1_RK30
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_GS_MXC6225)
- {
- .type = "gs_mxc6225",
- .addr = 0x15,
- .flags = 0,
- .irq = MXC6225_INT_PIN,
- .platform_data = &mxc6225_info,
- },
-#endif
-#if defined (CONFIG_GS_MMA7660)
- {
- .type = "gs_mma7660",//gs_mma7660
- .addr = 0x4c,
- .flags = 0,
- .irq = MMA7660_INT_PIN,
- .platform_data = &mma7660_info,
- },
-#endif
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1d,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_GS_LIS3DH)
- {
- .type = "gs_lis3dh",
- .addr = 0x19, //0x19(SA0-->VCC), 0x18(SA0-->GND)
- .flags = 0,
- .irq = LIS3DH_INT_PIN,
- .platform_data = &lis3dh_info,
- },
-#endif
-#if defined (CONFIG_GS_LSM303D)
- {
- .type = "gs_lsm303d",
- .addr = 0x1d, //0x19(SA0-->VCC), 0x18(SA0-->GND)
- .flags = 0,
- .irq = LSM303D_INT_PIN,
- .platform_data = &lms303d_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8975_info,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8975_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8963)
- {
- .type = "ak8963",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8963_info,
- },
-#endif
-#if defined (CONFIG_GYRO_L3G4200D)
- {
- .type = "l3g4200d_gryo",
- .addr = 0x69,
- .flags = 0,
- .irq = L3G4200D_INT_PIN,
- .platform_data = &l3g4200d_info,
- },
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-#if defined (CONFIG_TOUCHSCREEN_GT8XX)
- {
- .type = "Goodix-TS",
- .addr = 0x55,
- .flags = 0,
- .irq = TOUCH_INT_PIN,
- .platform_data = &goodix_info,
- },
-#endif
-#if defined (CONFIG_TOUCHSCREEN_GSLX680_RK3028)
- {
- .type = "gslX680",
- .addr = 0x40,
- .flags = 0,
- .platform_data =&gslx680_info,
- },
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO// RK2928_PIN2_PD6 //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO//RK2928_PIN2_PD7 //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- return 0;
-}
-
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(4, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-
-/***********************************************************
-* board init
-************************************************************/
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- &rk29sdk_wifi_device,
-#endif
-#ifdef CONFIG_RFKILL_RK
- &device_rfkill_rk,
-#endif
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
- &rk30_device_adc_battery,
-#endif
-#ifdef CONFIG_SND_SOC_RK3026
- &rk3026_codec,
-#endif
-#ifdef CONFIG_GPS_RK
- &rk_device_gps,
-#endif
-};
-
-static void rk30_pm_power_off(void)
-{
-#if defined(CONFIG_MFD_TPS65910)
- tps65910_device_shutdown();//tps65910 shutdown
-#endif
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
- while(1);
-}
-
-static void __init machine_rk30_board_init(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_regulator_init();
-#endif
- avs_init();
- pm_power_off = rk30_pm_power_off;
- rk_gpio_request(POWER_ON_PIN, GPIOF_DIR_OUT, GPIO_HIGH, "system power on");
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- rk_platform_add_display_devices();
-#if defined(CONFIG_WIFI_CONTROL_FUNC)
- rk29sdk_wifi_bt_gpio_control_init();
-#elif defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- rk29sdk_wifi_combo_module_gpio_init();
-#endif
-}
-
-static void __init rk30_reserve(void)
-{
- //fb reserve
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0 buf", get_fb_size());
- resource_fb[0].end = resource_fb[0].start + get_fb_size()- 1;
- #if 0
- resource_fb[1].start = board_mem_reserve_add("ipp buf", RK30_FB0_MEM_SIZE);
- resource_fb[1].end = resource_fb[1].start + RK30_FB0_MEM_SIZE - 1;
- #endif
-
- #if defined(CONFIG_FB_ROTATE) || !defined(CONFIG_THREE_FB_BUFFER)
- resource_fb[2].start = board_mem_reserve_add("fb2 buf",get_fb_size());
- resource_fb[2].end = resource_fb[2].start + get_fb_size() - 1;
- #endif
-#endif
- //ion reserve
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
-#ifdef CONFIG_GPS_RK
- //it must be more than 8MB
- rk_gps_info.u32MemoryPhyAddr = board_mem_reserve_add("gps", SZ_8M);
-#endif
- board_mem_reserved();
-}
-
-/***********************************************************
-* clock
-************************************************************/
-static struct cpufreq_frequency_table dvfs_arm_table_v0[] = {
- {.frequency = 312 * 1000, .index = 1200 * 1000},
- {.frequency = 504 * 1000, .index = 1200 * 1000},
- {.frequency = 816 * 1000, .index = 1250 * 1000},
- {.frequency = 912 * 1000, .index = 1350 * 1000},
- {.frequency = 1008 * 1000, .index = 1350 * 1000},
- //{.frequency = 1200 * 1000, .index = 1200 * 1000},
- //{.frequency = 1416 * 1000, .index = 1200 * 1000},
- //{.frequency = 1608 * 1000, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_arm_table_v1[] = {
- {.frequency = 312 * 1000, .index = 1200 * 1000},
- {.frequency = 504 * 1000, .index = 1200 * 1000},
- {.frequency = 816 * 1000, .index = 1275 * 1000},
- {.frequency = 912 * 1000, .index = 1350 * 1000},
- {.frequency = 1008 * 1000, .index = 1400 * 1000},
- //{.frequency = 1200 * 1000, .index = 1200 * 1000},
- //{.frequency = 1416 * 1000, .index = 1200 * 1000},
- //{.frequency = 1608 * 1000, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- {.frequency = 100 * 1000, .index = 1250 * 1000},
- {.frequency = 200 * 1000, .index = 1250 * 1000},
- {.frequency = 266 * 1000, .index = 1250 * 1000},
- {.frequency = 300 * 1000, .index = 1250 * 1000},
- {.frequency = 400 * 1000, .index = 1250 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 1200 * 1000},
- {.frequency = 300 * 1000, .index = 1200 * 1000},
- {.frequency = 400 * 1000 + DDR_FREQ_NORMAL, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-#define RK3026_SOC_V0 0x00
-#define RK3026_SOC_V1 0x01
-
-void __init board_clock_init(void)
-{
- rk2928_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
- //dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
-
- printk(KERN_INFO "rk3026 soc version:%d\n", rk3026_version_val());
- if (rk3026_version_val() == RK3026_SOC_V1)
- dvfs_set_freq_volt_table(clk_get(NULL, "cpu"), dvfs_arm_table_v1);
- else
- dvfs_set_freq_volt_table(clk_get(NULL, "cpu"), dvfs_arm_table_v0);
-
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
-}
-
-/************************ end *****************************/
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk2928_fixup,
- .reserve = &rk30_reserve,
- .map_io = rk2928_map_io,
- .init_irq = rk2928_init_irq,
- .timer = &rk2928_timer,
- .init_machine = machine_rk30_board_init,
-MACHINE_END
+++ /dev/null
-/*\r
- *\r
- * Copyright (C) 2013 ROCKCHIP, Inc.\r
- *\r
- * This software is licensed under the terms of the GNU General Public\r
- * License version 2, as published by the Free Software Foundation, and\r
- * may be copied, distributed, and modified under those terms.\r
- *\r
- * This program is distributed in the hope that it will be useful,\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- * GNU General Public License for more details.\r
- *\r
- */\r
-\r
-#include <linux/kernel.h>\r
-#include <linux/init.h>\r
-#include <linux/io.h>\r
-#include <linux/delay.h>\r
-#include <linux/clk.h>\r
-\r
-#include <asm/mach-types.h>\r
-#include <asm/mach/arch.h>\r
-\r
-#include <mach/board.h>\r
-#include <mach/gpio.h>\r
-\r
-#define FT\r
-\r
-#ifdef FT\r
-#define CONSOLE_LOGLEVEL 9\r
-#define ARM_PLL_MHZ (312)\r
-#else\r
-#define CONSOLE_LOGLEVEL 9\r
-#define ARM_PLL_MHZ (816)\r
-#endif\r
-\r
-static void __init machine_rk2928_board_init(void)\r
-{\r
- console_loglevel = CONSOLE_LOGLEVEL;\r
-}\r
-\r
-#define ft_printk(fmt, arg...) \\r
- printk(KERN_EMERG fmt, ##arg)\r
-\r
-void __init board_clock_init(void)\r
-{\r
- rk2928_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);\r
- clk_set_rate(clk_get(NULL, "cpu"), ARM_PLL_MHZ * 1000 * 1000);\r
- preset_lpj = loops_per_jiffy;\r
-}\r
-\r
-static void __init ft_fixup(struct machine_desc *desc, struct tag *tags,\r
- char **cmdline, struct meminfo *mi)\r
-{\r
- mi->nr_banks = 1;\r
- mi->bank[0].start = PLAT_PHYS_OFFSET;\r
- mi->bank[0].size = SZ_512M;\r
-}\r
-\r
-MACHINE_START(RK30, "RK30board")\r
- .boot_params = PLAT_PHYS_OFFSET + 0x800,\r
- .fixup = ft_fixup,\r
- .map_io = rk2928_map_io,\r
- .init_irq = rk2928_init_irq,\r
- .timer = &rk2928_timer,\r
- .init_machine = machine_rk2928_board_init,\r
-MACHINE_END\r
-\r
+++ /dev/null
-#ifdef CONFIG_VIDEO_RK29
-#include <plat/rk_camera.h>
-/* Notes:
-
-Simple camera device registration:
-
- new_camera_device(sensor_name,\ // sensor name, it is equal to CONFIG_SENSOR_X
- face,\ // sensor face information, it can be back or front
- pwdn_io,\ // power down gpio configuration, it is equal to CONFIG_SENSOR_POWERDN_PIN_XX
- flash_attach,\ // sensor is attach flash or not
- mir,\ // sensor image mirror and flip control information
- i2c_chl,\ // i2c channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_IIC_ADAPTER_ID_X
- cif_chl) \ // cif channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_CIF_INDEX_X
-
-Comprehensive camera device registration:
-
- new_camera_device_ex(sensor_name,\
- face,\
- ori,\ // sensor orientation, it is equal to CONFIG_SENSOR_ORIENTATION_X
- pwr_io,\ // sensor power gpio configuration, it is equal to CONFIG_SENSOR_POWER_PIN_XX
- pwr_active,\ // sensor power active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- rst_io,\ // sensor reset gpio configuration, it is equal to CONFIG_SENSOR_RESET_PIN_XX
- rst_active,\ // sensor reset active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- pwdn_io,\
- pwdn_active,\ // sensor power down active level, is equal to CONFIG_SENSOR_POWERDNACTIVE_LEVEL_X
- flash_attach,\
- res,\ // sensor resolution, this is real resolution or resoltuion after interpolate
- mir,\
- i2c_chl,\
- i2c_spd,\ // i2c speed , 100000 = 100KHz
- i2c_addr,\ // the i2c slave device address for sensor
- cif_chl,\
- mclk)\ // sensor input clock rate, 24 or 48
-
-*/
-static struct rkcamera_platform_data new_camera[] = {
- new_camera_device(RK29_CAM_SENSOR_OV5640,
- back,
- RK2928_PIN3_PB3,
- 0,
- 0,
- 0,
- 0),
- new_camera_device_end
-};
-/*---------------- Camera Sensor Macro Define Begin ------------------------*/
-/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
-#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_OV5642 /* back camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_0 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 0
-#define CONFIG_SENSOR_CIF_INDEX_0 0
-#define CONFIG_SENSOR_ORIENTATION_0 90
-#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 RK2928_PIN3_PB3
-#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000
-
-#define CONFIG_SENSOR_01 RK29_CAM_SENSOR_OV5642 /* back camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_01 0x00
-#define CONFIG_SENSOR_CIF_INDEX_01 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 4
-#define CONFIG_SENSOR_ORIENTATION_01 90
-#define CONFIG_SENSOR_POWER_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_01 RK2928_PIN3_PB3
-#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_01 30000
-
-#define CONFIG_SENSOR_02 RK29_CAM_SENSOR_OV5640 /* back camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_02 0x00
-#define CONFIG_SENSOR_CIF_INDEX_02 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 4
-#define CONFIG_SENSOR_ORIENTATION_02 90
-#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_02 RK2928_PIN3_PB3
-#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000
-
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_OV2659 /* front camera sensor 0 */
-#define CONFIG_SENSOR_IIC_ADDR_1 0// 0x60
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 3
-#define CONFIG_SENSOR_CIF_INDEX_1 0
-#define CONFIG_SENSOR_ORIENTATION_1 270
-#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_1 RK2928_PIN3_PB3
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000
-
-#define CONFIG_SENSOR_11 RK29_CAM_SENSOR_OV2659 /* front camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_11 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 3
-#define CONFIG_SENSOR_CIF_INDEX_11 0
-#define CONFIG_SENSOR_ORIENTATION_11 270
-#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_11 30000
-
-#define CONFIG_SENSOR_12 RK29_CAM_SENSOR_OV2659//RK29_CAM_SENSOR_OV2655 /* front camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_12 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 3
-#define CONFIG_SENSOR_CIF_INDEX_12 0
-#define CONFIG_SENSOR_ORIENTATION_12 270
-#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_12 30000
-
-
-#endif //#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk2928_camera.c"
-/*---------------- Camera Sensor Macro Define End ---------*/
-
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#define CONFIG_SENSOR_POWER_IOCTL_USR 0 //define this refer to your board layout
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
-
-static void rk_cif_power(int on)
-{
- struct regulator *ldo_18,*ldo_28;
- ldo_28 = regulator_get(NULL, "ldo7"); // vcc28_cif
- ldo_18 = regulator_get(NULL, "ldo1"); // vcc18_cif
- if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){
- printk("get cif ldo failed!\n");
- return;
- }
- if(on == 0){
- regulator_disable(ldo_28);
- regulator_put(ldo_28);
- regulator_disable(ldo_18);
- regulator_put(ldo_18);
- mdelay(500);
- }
- else{
- regulator_set_voltage(ldo_28, 2800000, 2800000);
- regulator_enable(ldo_28);
- // printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
- regulator_put(ldo_28);
-
- regulator_set_voltage(ldo_18, 1800000, 1800000);
- // regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(ldo_18);
- // printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
- regulator_put(ldo_18);
- }
-}
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- //#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
- rk_cif_power(on);
-}
-#endif
-
-#if CONFIG_SENSOR_RESET_IOCTL_USR
-static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
-static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-
-#if CONFIG_SENSOR_IIC_ADDR_0
-static struct reginfo_t rk_init_data_sensor_reg_0[] =
-{
- {0x0000, 0x00,0,0}
- };
-static struct reginfo_t rk_init_data_sensor_winseqreg_0[] ={
- {0x0000, 0x00,0,0}
- };
-#endif
-
-#if CONFIG_SENSOR_IIC_ADDR_1
-static struct reginfo_t rk_init_data_sensor_reg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_01
-static struct reginfo_t rk_init_data_sensor_reg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_02
-static struct reginfo_t rk_init_data_sensor_reg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_11
-static struct reginfo_t rk_init_data_sensor_reg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_12
-static struct reginfo_t rk_init_data_sensor_reg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] =
-{
- #if CONFIG_SENSOR_IIC_ADDR_0
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_0,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_1
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_1,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_01
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_01,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_02
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_02,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_11
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_11,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_12
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_12,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
-
- };
-#include "../../../drivers/media/video/rk2928_camera.c"
-
-#endif /* CONFIG_VIDEO_RK29 */
+++ /dev/null
-/*****************************************************************************************
- * arch/arm/mach-rkxx/baord-xxx-sdmmc-config.c
- *
- * Copyright (C) 2013 ROCKCHIP, Inc.
- *
- * Description:
- * define the gpio for SD-MMC-SDIO-Wifi functions according to your own projects.
- *
- * Author: Michael Xie
- * 15 Jan,2013
- * E-mail: xbw@rock-chips.com
- *
- ******************************************************************************************/
-
-/*
-** If you select the macro of CONFIG_SDMMC0_RK29_WRITE_PROTECT, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define SDMMC0_WRITE_PROTECT_PIN RK30_PIN3_PB2 //According to your own project to set the value of write-protect-pin.
-//#define SDMMC0_WRITE_PROTECT_ENABLE_VALUE GPIO_HIGH
-
-/*
-** If you select the macro of CONFIG_SDMMC1_RK29_WRITE_PROTECT, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define SDMMC1_WRITE_PROTECT_PIN RK30_PIN3_PB3 //According to your own project to set the value of write-protect-pin.
-//#define SDMMC1_WRITE_PROTECT_ENABLE_VALUE GPIO_HIGH
-
-/*
-** If you select the macro of CONFIG_RK29_SDIO_IRQ_FROM_GPIO, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define RK29SDK_WIFI_SDIO_CARD_INT RK30_PIN3_PD2
-
-
-/*
-* define sdcard PowerEn-pin
-*/
-#define RK29SDK_SD_CARD_PWR_EN INVALID_GPIO
-#define RK29SDK_SD_CARD_PWR_EN_LEVEL GPIO_LOW
-int rk31sdk_get_sdmmc0_pin_io_voltage(void)
-{
- int voltage;
-#define RK31SDK_SET_SDMMC0_PIN_VOLTAGE
-
- /**************************************************************************************
- ** Please tell me how much voltage of your SDMMC0-pin in your project.
- **
- ** ÀýÈç: ÓеÄÏîÄ¿£¬ËüµÄSDMMC0ËùÔÚµÄRKÖ÷¿ØµÄIO×飬ÏëÓÃ1.8V, ¶ø¿¨±¾ÉíÓÃ3.3V,
- ** ¶øÖмäͨ¹ý¸öµçƽת»».ÄÇô£¬Äú´Ëʱ£¬Ó¦¸ÃÉèÖÃÏÂÃæµÄvoltageֵΪ 1.8V(¼´1800mv)
- ***************************************************************************************/
- voltage = 3300; //default the voltage 3300mv.
-
- return voltage;
-}
-
-/*
-* define the card-detect-pin.
-*/
-#define RK29SDK_SD_CARD_DETECT_N RK30_PIN2_PA7 //According to your own project to set the value of card-detect-pin.
-#define RK29SDK_SD_CARD_INSERT_LEVEL GPIO_LOW // set the voltage of insert-card. Please pay attention to the default setting.
-
-/*
-* Define wifi module's power and reset gpio, and gpio sensitive level.
-* Please set the value according to your own project.
-*
-* Well, you just own engineering module to set the value in the corresponding module branch.
-* Otherwise, you do not define this macro, eliminate it.
-*
-*/
-#if defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU)
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_LOW//GPIO_HIGH
-
-#elif defined(CONFIG_BCM4330) || defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319) || defined(CONFIG_RK903) || defined(CONFIG_RK901)
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN2_PA7
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
-
-#elif defined(CONFIG_MT5931_MT6622) || defined(CONFIG_MT5931)
-
- #ifdef CONFIG_MACH_RK3168_LR097
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- //#define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- //#define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
-
- #else
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN0_PA5
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #endif
-
-#elif defined(CONFIG_MT6620)
- #define COMBO_MODULE_MT6620_CDT 1 // to control antsel2,antsel3 and gps_lan foot when using AcSip or Cdtech chip.
- //- 1--use Cdtech chip; 0--unuse CDT chip
-
- //power, PMU_EN
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PC7
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- //reset, DAIRST,SYSRST_B
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- //VDDIO
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL RK30_PIN0_PD2 //You do not get control of the foot, and you do not need to define the macro
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_ENABLE_VALUE GPIO_HIGH
- //WIFI_INT_B
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
- //BGF_INT_B
- #define RK30SDK_WIFI_GPIO_BGF_INT_B RK30_PIN6_PA7
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_ENABLE_VALUE GPIO_HIGH
- //GPS_SYNC
- #define RK30SDK_WIFI_GPIO_GPS_SYNC RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_ENABLE_VALUE GPIO_HIGH
-
- #if COMBO_MODULE_MT6620_CDT
- //ANTSEL2
- #define RK30SDK_WIFI_GPIO_ANTSEL2 RK30_PIN4_PD4
- #define RK30SDK_WIFI_GPIO_ANTSEL2_ENABLE_VALUE GPIO_LOW //use 6620 in CDT chip, LOW--work; High--no work.
- //ANTSEL3
- #define RK30SDK_WIFI_GPIO_ANTSEL3 RK30_PIN4_PD3
- #define RK30SDK_WIFI_GPIO_ANTSEL3_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- //GPS_LAN
- #define RK30SDK_WIFI_GPIO_GPS_LAN RK30_PIN4_PD6
- #define RK30SDK_WIFI_GPIO_GPS_LAN_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- #endif // #if COMBO_MODULE_MT6620_CDT--#endif
-#endif
-
-#ifndef RK30SDK_WIFI_GPIO_WIFI_INT_B
-#define RK30SDK_WIFI_GPIO_WIFI_INT_B INVALID_GPIO
-#define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
-#endif
-
-int rk31sdk_get_sdio_wifi_voltage(void)
-{
- int voltage;
-
- /******************************************************************************
- ** Please tell me how much wifi-module uses voltage in your project.
- ******************************************************************************/
-#if defined(CONFIG_BCM4330) || defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319) || defined(CONFIG_RK903) || defined(CONFIG_RK901)
- voltage = 1800 ; //power 1800mV
-
-#elif defined(CONFIG_MT5931_MT6622)||defined(CONFIG_MT5931)
- voltage = 1800 ; //power 1800V
-#elif defined(CONFIG_MT6620)
- voltage = 2800 ; //power 2800V
-#elif defined(CONFIG_RDA5990)||defined(CONFIG_RTL8723AS)
- voltage = 3300 ; //power 3300V
-#else
- //default, sdio use 3.0V
- voltage = 3000 ; //power 3000V
-#endif
-
- return voltage;
-}
-
-
-
+++ /dev/null
-/*
- * Copyright (C) 2013 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <linux/rk_fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/mfd/tps65910.h>
-#include <linux/regulator/act8846.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/dvfs.h>
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-
-#ifdef CONFIG_SND_SOC_RK3026
-#include "../../../sound/soc/codecs/rk3026_codec.h"
-#endif
-
-#if defined(CONFIG_RK_HDMI)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#include "board-rk3026-tb-camera.c"
-
-/***********************************************************
-* board config
-************************************************************/
-//system power on
-#define POWER_ON_PIN RK30_PIN1_PA2 //PWR_HOLD
-
-//touchscreen
-#define TOUCH_RST_PIN RK2928_PIN2_PB0
-#define TOUCH_RST_VALUE GPIO_HIGH
-#define TOUCH_PWR_PIN RK2928_PIN2_PB3
-#define TOUCH_PWR_VALUE GPIO_LOW
-#define TOUCH_INT_PIN RK2928_PIN1_PB0
-
-//backlight
-#define LCD_DISP_ON_PIN
-#define BL_PWM 0 // (0 ~ 2)
-#define PWM_EFFECT_VALUE 1
-#define BL_EN_PIN RK2928_PIN2_PC1
-#define BL_EN_VALUE GPIO_HIGH
-
-//fb
-#define LCD_EN_PIN RK2928_PIN1_PB3
-#define LCD_EN_VALUE GPIO_HIGH
-#define LCD_CS_PIN INVALID_GPIO
-#define LCD_CS_VALUE GPIO_HIGH
-
-//gsensor
-#define GS_INT_PIN RK2928_PIN1_PB2
-
-//sdmmc
-//Reference to board-rk3026-tb-sdmmc-config.c
-
-//keyboard
-//#define RK31XX_MAINBOARD_V1 //if mainboard is RK31XX_MAINBOARD_V1.0
-#define PLAY_ON_PIN RK30_PIN1_PA4 //wakeup key
-
-//pwm regulator
-#define REG_PWM 1 // (0 ~ 2)
-
-//pmic
-#define PMU_INT_PIN RK30_PIN1_PB1
-#define PMU_SLEEP_PIN RK30_PIN1_PA1
-
-//ion reserve memory
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-
-static int pwm_mode[] = {PWM0, PWM1, PWM2};
-static inline int rk_gpio_request(int gpio, int direction, int value, const char *label)
-{
- int ret = 0;
- unsigned long flags = 0;
-
- if(!gpio_is_valid(gpio))
- return 0;
-
- if(direction == GPIOF_DIR_IN)
- flags = GPIOF_IN;
- else if(value == GPIO_LOW)
- flags = GPIOF_OUT_INIT_LOW;
- else
- flags = GPIOF_OUT_INIT_HIGH;
-
- ret = gpio_request_one(gpio, flags, label);
- if(ret < 0)
- pr_err("Failed to request '%s'\n", label);
-
- return ret;
-}
-
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* touchscreen
-************************************************************/
-#if defined(CONFIG_TOUCHSCREEN_GT8XX)
-static int goodix_init_platform_hw(void)
-{
- int ret = 0;
-
- ret = rk_gpio_request(TOUCH_PWR_PIN, GPIOF_DIR_OUT, TOUCH_PWR_VALUE, "touch_pwr");
- if(ret < 0)
- return ret;
- msleep(100);
-
- ret = rk_gpio_request(TOUCH_RST_PIN, GPIOF_DIR_OUT, TOUCH_RST_VALUE, "touch_rst");
- if(ret < 0)
- return ret;
- msleep(100);
-
- return 0;
-}
-
-struct goodix_platform_data goodix_info = {
- .model = 8105,
- .irq_pin = TOUCH_INT_PIN,
- .rest_pin = TOUCH_RST_PIN,
- .init_platform_hw = goodix_init_platform_hw,
-};
-#endif
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
-
- iomux_set(pwm_mode[BL_PWM]);
-#ifdef LCD_DISP_ON_PIN
- ret = rk_gpio_request(BL_EN_PIN, GPIOF_DIR_OUT, BL_EN_VALUE, "bl_en");
- if(ret < 0)
- return ret;
-#endif
- return 0;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int pwm_gpio;
-#ifdef LCD_DISP_ON_PIN
- gpio_free(BL_EN_PIN);
-#endif
- pwm_gpio = iomux_mode_to_gpio(pwm_mode[BL_PWM]);
- return rk_gpio_request(BL_EN_PIN, GPIOF_DIR_OUT, GPIO_LOW, "BL_PWM");
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret, pwm_gpio = iomux_mode_to_gpio(pwm_mode[BL_PWM]);
-
- ret = rk_gpio_request(pwm_gpio, GPIOF_DIR_OUT, GPIO_LOW, "BL_PWM");
- if(ret < 0)
- return ret;
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, !BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- int pwm_gpio = iomux_mode_to_gpio(pwm_mode[BL_PWM]);
-
- gpio_free(pwm_gpio);
- iomux_set(pwm_mode[BL_PWM]);
-#ifdef LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .pwm_id = BL_PWM,
- .min_brightness=20,
- .max_brightness=255,
- .brightness_mode = BRIGHTNESS_MODE_CONIC,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-#endif
-
-/***********************************************************
-* fb
-************************************************************/
-#ifdef CONFIG_FB_ROCKCHIP
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
-
- ret = rk_gpio_request(LCD_CS_PIN, GPIOF_DIR_OUT, LCD_CS_VALUE, "lcd_cs");
- if(ret < 0)
- return ret;
-
- return rk_gpio_request(LCD_EN_PIN, GPIOF_DIR_OUT, LCD_EN_VALUE, "lcd_en");
-}
-
-static int rk_fb_io_disable(void)
-{
- gpio_set_value(LCD_CS_PIN, !LCD_CS_VALUE);
- gpio_set_value(LCD_EN_PIN, !LCD_EN_VALUE);
-
- return 0;
-}
-
-static int rk_fb_io_enable(void)
-{
- gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE);
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
-
- return 0;
-}
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
-struct rk29fb_info lcdc0_screen_info = {
-#if defined(CONFIG_RK_HDMI) && defined(CONFIG_HDMI_SOURCE_LCDC0) && defined(CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL)
- .prop = EXTEND, //extend display device
- .io_init = NULL,
- .io_disable = NULL,
- .io_enable = NULL,
- .set_screen_info = hdmi_init_lcdc,
-#else
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-#endif
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
-struct rk29fb_info lcdc1_screen_info = {
-#if defined(CONFIG_RK_HDMI) && defined(CONFIG_HDMI_SOURCE_LCDC1) && defined(CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL)
- .prop = EXTEND, //extend display device
- .io_init = NULL,
- .io_disable = NULL,
- .io_enable = NULL,
- .set_screen_info = hdmi_init_lcdc,
-#else
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-#endif
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
-static struct resource resource_lcdc0[] = {
- [0] = {
- .name = "lcdc0 reg",
- .start = RK3026_LCDC0_PHYS,
- .end = RK3026_LCDC0_PHYS + RK3026_LCDC0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc0 irq",
- .start = IRQ_LCDC,
- .end = IRQ_LCDC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc0 = {
- .name = "rk30-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc0),
- .resource = resource_lcdc0,
- .dev = {
- .platform_data = &lcdc0_screen_info,
- },
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
-static struct resource resource_lcdc1[] = {
- [0] = {
- .name = "lcdc1 reg",
- .start = RK3026_LCDC1_PHYS,
- .end = RK3026_LCDC1_PHYS + RK3026_LCDC1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc1 irq",
- .start = IRQ_LCDC1,
- .end = IRQ_LCDC1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc1 = {
- .name = "rk30-lcdc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resource_lcdc1),
- .resource = resource_lcdc1,
- .dev = {
- .platform_data = &lcdc1_screen_info,
- },
-};
-#endif
-
-static int rk_platform_add_display_devices(void)
-{
- struct platform_device *fb = NULL; //fb
- struct platform_device *lcdc0 = NULL; //lcdc0
- struct platform_device *lcdc1 = NULL; //lcdc1
- struct platform_device *bl = NULL; //backlight
-#ifdef CONFIG_FB_ROCKCHIP
- fb = &device_fb;
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
- lcdc0 = &device_lcdc0,
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
- lcdc1 = &device_lcdc1,
-#endif
-
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- bl = &rk29_device_backlight,
-#endif
- __rk_platform_add_display_devices(fb,lcdc0,lcdc1,bl);
-
- return 0;
-}
-
-
-/***********************************************************
-* gsensor
-************************************************************/
-#if defined (CONFIG_GS_MMA8452)
-static int mma8452_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data mma8452_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma8452_init_platform_hw,
- .orientation = {-1, 0, 0, 0, -1, 0, 0, 0, 1},
-};
-#endif
-
-/***********************************************************
-* keyboard
-************************************************************/
-#include <plat/key.h>
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = PLAY_ON_PIN,
- .active_low = PRESS_LEV_LOW,
- .wakeup = 1,
- },
-/* disable adc keyboard,
- * because rk280a adc reference voltage is 3.3V, but
- * rk30xx mainbord key's supply voltage is 2.5V and
- * rk31xx mainbord key's supply voltage is 1.8V.
- */
-#if 0
-#ifdef RK31XX_MAINBOARD_V1
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .adc_value = 744,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = PLAY_ON_PIN,
- .active_low = PRESS_LEV_LOW,
- .wakeup = 1,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .adc_value = 558,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "menu",
- .code = EV_MENU,
- .adc_value = 1,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .adc_value = 354,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .adc_value = 169,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-#else
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .adc_value = 900,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = PLAY_ON_PIN,
- .active_low = PRESS_LEV_LOW,
- .wakeup = 1,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .adc_value = 1,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "menu",
- .code = EV_MENU,
- .adc_value = 133,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .adc_value = 550,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .adc_value = 333,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "camera",
- .code = KEY_CAMERA,
- .adc_value = 742,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-#endif
-#endif
-};
-
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = 1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
-/***********************************************************
-* sdmmc
-************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "board-rk3026-tb-sdmmc-config.c"
-#include "../plat-rk/rk-sdmmc-ops.c"
-#include "../plat-rk/rk-sdmmc-wifi.c"
-#endif //endif ---#ifdef CONFIG_SDMMC_RK29
-
-#ifdef CONFIG_SDMMC0_RK29
-#define CONFIG_SDMMC0_USE_DMA
-static int rk29_sdmmc0_cfg_gpio(void)
-{
- rk29_sdmmc_set_iomux(0, 0xFFFF);
- #if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- iomux_set_gpio_mode(iomux_gpio_to_mode(RK29SDK_SD_CARD_DETECT_N));
- #else
- iomux_set(MMC0_DETN);
- #endif
-
- #if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
- #endif
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
- .set_iomux = rk29_sdmmc_set_iomux,
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) && defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- .status = rk29sdk_wifi_mmc0_status,
- .register_status_notify = rk29sdk_wifi_mmc0_status_register,
-#endif
-
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .power_en = RK29SDK_SD_CARD_PWR_EN,
- .power_en_level = RK29SDK_SD_CARD_PWR_EN_LEVEL,
-#else
- .power_en = INVALID_GPIO,
- .power_en_level = GPIO_LOW,
-#endif
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC0_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- .det_pin_info = {
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N, //INVALID_GPIO,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
- #endif
- },
-
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
- .set_iomux = rk29_sdmmc_set_iomux,
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC) || defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC1_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- #if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
- .sdio_INT_gpio = RK29SDK_WIFI_SDIO_CARD_INT,
- #endif
-
- .det_pin_info = {
- #if defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- #else
- .io = INVALID_GPIO,
- #endif
-
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
- #endif
- },
- .enable_sd_wakeup = 0,
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-
-
-/***********************************************************
-* ion
-************************************************************/
-#ifdef CONFIG_ION
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-/***********************************************************
-* pwm regulator
-************************************************************/
-#ifdef CONFIG_RK30_PWM_REGULATOR
-static int pwm_voltage_map[] = {
- 800000, 825000, 850000, 875000, 900000, 925000 ,
- 950000, 975000, 1000000, 1025000, 1050000, 1075000,
- 1100000, 1125000, 1150000, 1175000, 1200000, 1225000,
- 1250000, 1275000, 1300000, 1325000, 1350000, 1375000
-};
-
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_core",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] = {
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
- .pwm_id = REG_PWM,
- .pwm_voltage = 1200000,
- .suspend_voltage = 1050000,
- .min_uV = 950000,
- .max_uV = 1400000,
- .coefficient = 504, //50.4%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-
-static void pwm_regulator_init(void)
-{
- pwm_regulator_info[0].pwm_gpio = iomux_mode_to_gpio(pwm_mode[REG_PWM]);
- pwm_regulator_info[0].pwm_iomux_pwm = pwm_mode[REG_PWM];
- pwm_regulator_info[0].pwm_iomux_gpio = iomux_switch_gpio_mode(pwm_mode[REG_PWM]);
-}
-#endif
-
-int __sramdata pwm_iomux, pwm_do, pwm_dir, pwm_en;
-#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
-
-#define GPIO0_D2_OFFSET 10
-void __sramfunc rk30_pwm_logic_suspend_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- #if 0
- /* pwm0: GPIO0_D2, pwm1: GPIO0_D3, pwm2: GPIO0_D4 */
- int off = GPIO0_D2_OFFSET + REG_PWM;
-
- sram_udelay(10000);
- pwm_iomux = grf_readl(GRF_GPIO0D_IOMUX);
- pwm_dir = grf_readl(GRF_GPIO0H_DIR);
- pwm_do = grf_readl(GRF_GPIO0H_DO);
- pwm__en = grf_readl(GRF_GPIO0H_EN);
-
- grf_writel((1<<(2 * off), GRF_GPIO0D_IOMUX);
- grf_writel((1<<(16 + off))|(1<<off), GRF_GPIO0H_DIR);
- grf_writel((1<<(16 + off))|(1<<off), GRF_GPIO0H_DO);
- #endif
-#endif
-}
-
-void __sramfunc rk30_pwm_logic_resume_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- #if 0
- /* pwm0: GPIO0_D2, pwm1: GPIO0_D3, pwm2: GPIO0_D4 */
- int off = GPIO0_D2_OFFSET + REG_PWM;
-
- grf_writel((1<<(2 * off))|pwm_iomux, GRF_GPIO0D_IOMUX);
- grf_writel(((1<<(16 + off))|pwm_dir), GRF_GPIO0L_DIR);
- grf_writel(((1<<(16 + off))|pwm_do), GRF_GPIO0L_DO);
- grf_writel(((1<<(16 + off))|pwm_en), GRF_GPIO0L_EN);
- sram_udelay(10000);
- #endif
-#endif
-}
-extern void pwm_suspend_voltage(void);
-extern void pwm_resume_voltage(void);
-
-void rk30_pwm_suspend_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_suspend_voltage();
-#endif
-}
-
-void rk30_pwm_resume_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_resume_voltage();
-#endif
-}
-
-/***********************************************************
-* pmic
-************************************************************/
-int __sramdata g_pmic_type = 0;
-
-#ifdef CONFIG_MFD_TPS65910
-#define TPS65910_HOST_IRQ PMU_INT_PIN
-#define PMU_POWER_SLEEP PMU_SLEEP_PIN
-static struct pmu_info tps65910_dcdc_info[] = {
- {
- .name = "vdd_cpu",
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vdd2",
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vio",
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
-};
-
-static struct pmu_info tps65910_ldo_info[] = {
- {
- .name = "vpll", //vcc25
- .min_uv = 2500000,
- .max_uv = 2500000,
- },
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
-
- {
- .name = "vdig2", //vdd11
- .min_uv = 1100000,
- .max_uv = 1100000,
- },
- {
- .name = "vaux1", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "vaux2", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vaux33", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vmmc", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "vdac", //
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
-};
-#include "../mach-rk30/board-pmu-tps65910.c"
-#endif
-
-void __sramfunc board_pmu_suspend(void)
-{
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_suspend();
- #endif
-}
-
-void __sramfunc board_pmu_resume(void)
-{
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_resume();
- #endif
-}
-
-#ifdef CONFIG_SND_SOC_RK3026
-struct rk3026_codec_pdata rk3026_codec_pdata_info={
- .spk_ctl_gpio = INVALID_GPIO,
- .hp_ctl_gpio = RK2928_PIN1_PA0,
- .delay_time = 10,
-};
-
-static struct resource resources_acodec[] = {
- {
- .start = RK2928_ACODEC_PHYS,
- .end = RK2928_ACODEC_PHYS + RK2928_ACODEC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device rk3026_codec = {
- .name = "rk3026-codec",
- .id = -1,
- .resource = resources_acodec,
- .dev = {
- .platform_data = &rk3026_codec_pdata_info,
- }
-};
-#endif
-/***********************************************************
-* i2c
-************************************************************/
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1d,
- .flags = 0,
- .irq = GS_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C1_RK30
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-#if defined (CONFIG_TOUCHSCREEN_GT8XX)
- {
- .type = "Goodix-TS",
- .addr = 0x55,
- .flags = 0,
- .irq = TOUCH_INT_PIN,
- .platform_data = &goodix_info,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO// RK2928_PIN2_PD6 //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO//RK2928_PIN2_PD7 //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- return 0;
-}
-
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(4, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-
-/***********************************************************
-* board init
-************************************************************/
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- &rk29sdk_wifi_device,
-#endif
-#ifdef CONFIG_SND_SOC_RK3026
- &rk3026_codec,
-#endif
-};
-
-static void rk30_pm_power_off(void)
-{
-#if defined(CONFIG_MFD_TPS65910)
- tps65910_device_shutdown();//tps65910 shutdown
-#endif
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
- while(1);
-}
-
-static void __init machine_rk30_board_init(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_regulator_init();
-#endif
- avs_init();
- pm_power_off = rk30_pm_power_off;
- rk_gpio_request(POWER_ON_PIN, GPIOF_DIR_OUT, GPIO_HIGH, "system power on");
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- rk_platform_add_display_devices();
-#if defined(CONFIG_WIFI_CONTROL_FUNC)
- rk29sdk_wifi_bt_gpio_control_init();
-#elif defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- rk29sdk_wifi_combo_module_gpio_init();
-#endif
-}
-
-static void __init rk30_reserve(void)
-{
- //fb reserve
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0 buf", get_fb_size());
- resource_fb[0].end = resource_fb[0].start + get_fb_size()- 1;
- #if 0
- resource_fb[1].start = board_mem_reserve_add("ipp buf", RK30_FB0_MEM_SIZE);
- resource_fb[1].end = resource_fb[1].start + RK30_FB0_MEM_SIZE - 1;
- #endif
-
- #if defined(CONFIG_FB_ROTATE) || !defined(CONFIG_THREE_FB_BUFFER)
- resource_fb[2].start = board_mem_reserve_add("fb2 buf",get_fb_size());
- resource_fb[2].end = resource_fb[2].start + get_fb_size() - 1;
- #endif
-#endif
- //ion reserve
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
- board_mem_reserved();
-}
-
-/***********************************************************
-* clock
-************************************************************/
-static struct cpufreq_frequency_table dvfs_arm_table[] = {
- {.frequency = 312 * 1000, .index = 1200 * 1000},
- {.frequency = 504 * 1000, .index = 1200 * 1000},
- {.frequency = 816 * 1000, .index = 1200 * 1000},
- //{.frequency = 1008 * 1000, .index = 1200 * 1000},
- //{.frequency = 1200 * 1000, .index = 1200 * 1000},
- //{.frequency = 1416 * 1000, .index = 1200 * 1000},
- //{.frequency = 1608 * 1000, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- {.frequency = 100 * 1000, .index = 1200 * 1000},
- {.frequency = 200 * 1000, .index = 1200 * 1000},
- {.frequency = 266 * 1000, .index = 1200 * 1000},
- {.frequency = 300 * 1000, .index = 1200 * 1000},
- {.frequency = 400 * 1000, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 1200 * 1000},
- {.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = 1200 * 1000},
- {.frequency = 400 * 1000 + DDR_FREQ_NORMAL, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-void __init board_clock_init(void)
-{
- rk2928_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
- //dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "cpu"), dvfs_arm_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
-}
-
-/************************ end *****************************/
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk2928_fixup,
- .reserve = &rk30_reserve,
- .map_io = rk2928_map_io,
- .init_irq = rk2928_init_irq,
- .timer = &rk2928_timer,
- .init_machine = machine_rk30_board_init,
-MACHINE_END
+++ /dev/null
-#ifdef CONFIG_VIDEO_RK29
-#include <plat/rk_camera.h>
-/* Notes:
-
-Simple camera device registration:
-
- new_camera_device(sensor_name,\ // sensor name, it is equal to CONFIG_SENSOR_X
- face,\ // sensor face information, it can be back or front
- pwdn_io,\ // power down gpio configuration, it is equal to CONFIG_SENSOR_POWERDN_PIN_XX
- flash_attach,\ // sensor is attach flash or not
- mir,\ // sensor image mirror and flip control information
- i2c_chl,\ // i2c channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_IIC_ADAPTER_ID_X
- cif_chl) \ // cif channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_CIF_INDEX_X
-
-Comprehensive camera device registration:
-
- new_camera_device_ex(sensor_name,\
- face,\
- ori,\ // sensor orientation, it is equal to CONFIG_SENSOR_ORIENTATION_X
- pwr_io,\ // sensor power gpio configuration, it is equal to CONFIG_SENSOR_POWER_PIN_XX
- pwr_active,\ // sensor power active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- rst_io,\ // sensor reset gpio configuration, it is equal to CONFIG_SENSOR_RESET_PIN_XX
- rst_active,\ // sensor reset active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- pwdn_io,\
- pwdn_active,\ // sensor power down active level, is equal to CONFIG_SENSOR_POWERDNACTIVE_LEVEL_X
- flash_attach,\
- res,\ // sensor resolution, this is real resolution or resoltuion after interpolate
- mir,\
- i2c_chl,\
- i2c_spd,\ // i2c speed , 100000 = 100KHz
- i2c_addr,\ // the i2c slave device address for sensor
- cif_chl,\
- mclk)\ // sensor input clock rate, 24 or 48
-
-*/
-static struct rkcamera_platform_data new_camera[] = {
- new_camera_device(RK29_CAM_SENSOR_GC2035,
- back,
- RK30_PIN3_PB3,
- 0,
- 0,
- 1,
- 0),
- new_camera_device(RK29_CAM_SENSOR_GC0308,
- front,
- RK30_PIN3_PD7,
- 0,
- 0,
- 1,
- 0),
- new_camera_device_end
-};
-/*---------------- Camera Sensor Macro Define Begin ------------------------*/
-/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
-#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_GC2035 /* back camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_0 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 1
-#define CONFIG_SENSOR_CIF_INDEX_0 0
-#define CONFIG_SENSOR_ORIENTATION_0 90
-#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 RK30_PIN3_PB3
-#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_H
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000
-
-#define CONFIG_SENSOR_01 RK29_CAM_SENSOR_OV5642 /* back camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_01 0x00
-#define CONFIG_SENSOR_CIF_INDEX_01 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 4
-#define CONFIG_SENSOR_ORIENTATION_01 90
-#define CONFIG_SENSOR_POWER_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_01 RK2928_PIN3_PB3
-#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_01 30000
-
-#define CONFIG_SENSOR_02 RK29_CAM_SENSOR_OV5640 /* back camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_02 0x00
-#define CONFIG_SENSOR_CIF_INDEX_02 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 4
-#define CONFIG_SENSOR_ORIENTATION_02 90
-#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_02 RK2928_PIN3_PB3
-#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000
-
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_GC0308 /* front camera sensor 0 */
-#define CONFIG_SENSOR_IIC_ADDR_1 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 1
-#define CONFIG_SENSOR_CIF_INDEX_1 0
-#define CONFIG_SENSOR_ORIENTATION_1 270
-#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_1 RK30_PIN3_PD7
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000
-
-#define CONFIG_SENSOR_11 RK29_CAM_SENSOR_OV2659 /* front camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_11 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 3
-#define CONFIG_SENSOR_CIF_INDEX_11 0
-#define CONFIG_SENSOR_ORIENTATION_11 270
-#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_11 30000
-
-#define CONFIG_SENSOR_12 RK29_CAM_SENSOR_OV2659//RK29_CAM_SENSOR_OV2655 /* front camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_12 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 3
-#define CONFIG_SENSOR_CIF_INDEX_12 0
-#define CONFIG_SENSOR_ORIENTATION_12 270
-#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_12 30000
-
-
-#endif //#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk2928_camera.c"
-/*---------------- Camera Sensor Macro Define End ---------*/
-
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#define CONFIG_SENSOR_POWER_IOCTL_USR 0 //define this refer to your board layout
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
-
-static void rk_cif_power(int on)
-{
- struct regulator *ldo_18,*ldo_28;
- #if defined(CONFIG_MACH_RK3028A_86V)||defined(CONFIG_MACH_RK3028A_FAC)
- ldo_28 = regulator_get(NULL, "ldo7"); // vcc28_cif
- ldo_18 = regulator_get(NULL, "ldo1"); // vcc18_cif
- #else
- ldo_28 = regulator_get(NULL, "vaux1"); // vcc28_cif
- ldo_18 = regulator_get(NULL, "vdig1"); // vcc18_cif
- #endif
- if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){
- printk("get cif ldo failed!\n");
- return;
- }
- if(on == 0){
- regulator_disable(ldo_28);
- regulator_put(ldo_28);
- regulator_disable(ldo_18);
- regulator_put(ldo_18);
- mdelay(500);
- }
- else{
- regulator_set_voltage(ldo_28, 2800000, 2800000);
- regulator_enable(ldo_28);
- // printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
- regulator_put(ldo_28);
-
- regulator_set_voltage(ldo_18, 1800000, 1800000);
- // regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(ldo_18);
- // printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
- regulator_put(ldo_18);
- }
-}
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- //#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
- struct regulator *ldo_18,*ldo_28;
- ldo_28 = regulator_get(NULL, "ldo7"); // vcc28_cif
- ldo_18 = regulator_get(NULL, "ldo1"); // vcc18_cif
- if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){
- printk("get cif ldo failed!\n");
- return -1;
- }
- if(on == 0){
- while(regulator_is_enabled(ldo_28)>0)
- regulator_disable(ldo_28);
- regulator_put(ldo_28);
- while(regulator_is_enabled(ldo_18)>0)
- regulator_disable(ldo_18);
- regulator_put(ldo_18);
- mdelay(10);
- } else {
- regulator_set_voltage(ldo_28, 2800000, 2800000);
- regulator_enable(ldo_28);
- //printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
- regulator_put(ldo_28);
-
- regulator_set_voltage(ldo_18, 1800000, 1800000);
- //regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(ldo_18);
- //printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
- regulator_put(ldo_18);
- }
-
- return 0;
-}
-#endif
-
-#if CONFIG_SENSOR_RESET_IOCTL_USR
-static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
-static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-
-#if CONFIG_SENSOR_IIC_ADDR_0
-static struct reginfo_t rk_init_data_sensor_reg_0[] =
-{
- {0x0000, 0x00,0,0}
- };
-static struct reginfo_t rk_init_data_sensor_winseqreg_0[] ={
- {0x0000, 0x00,0,0}
- };
-#endif
-
-#if CONFIG_SENSOR_IIC_ADDR_1
-static struct reginfo_t rk_init_data_sensor_reg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_01
-static struct reginfo_t rk_init_data_sensor_reg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_02
-static struct reginfo_t rk_init_data_sensor_reg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_11
-static struct reginfo_t rk_init_data_sensor_reg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_12
-static struct reginfo_t rk_init_data_sensor_reg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] =
-{
- #if CONFIG_SENSOR_IIC_ADDR_0
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_0,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_1
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_1,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_01
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_01,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_02
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_02,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_11
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_11,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_12
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_12,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
-
- };
-#include "../../../drivers/media/video/rk2928_camera.c"
-
-#endif /* CONFIG_VIDEO_RK29 */
+++ /dev/null
-/*
- * Copyright (C) 2013 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <linux/rk_fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/mfd/tps65910.h>
-#include <linux/regulator/act8846.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/dvfs.h>
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-
-#ifdef CONFIG_SND_SOC_RK3026
-#include "../../../sound/soc/codecs/rk3026_codec.h"
-#endif
-
-#if defined(CONFIG_RK_HDMI)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#if defined(CONFIG_GPS_RK)
-#include "../../../drivers/misc/gps/rk_gps/rk_gps.h"
-#endif
-#include "board-rk3028a-86v-camera.c"
-#include <plat/config.h>
-#include <plat/board.h>
-#include "../plat-rk/rk-fac-config.c"
-#if 1
-#define INIT_ERR(name) do { printk("%s: %s init Failed: \n", __func__, (name)); } while(0)
-#else
-#define INIT_ERR(name)
-#endif
-
-/***********************************************************
-* board config
-************************************************************/
-
-//pwm regulator
-#define REG_PWM 1 // (0 ~ 2)
-//pmic
-#define PMU_INT_PIN RK30_PIN3_PC6
-#define PMU_SLEEP_PIN RK30_PIN3_PC4
-//ion reserve memory
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-
-static int pwm_mode[] = {PWM0, PWM1, PWM2};
-static inline int rk_gpio_request(int gpio, int direction, int value, const char *label)
-{
- int ret = 0;
- unsigned long flags = 0;
-
- if(!gpio_is_valid(gpio))
- return 0;
-
- if(direction == GPIOF_DIR_IN)
- flags = GPIOF_IN;
- else if(value == GPIO_LOW)
- flags = GPIOF_OUT_INIT_LOW;
- else
- flags = GPIOF_OUT_INIT_HIGH;
-
- ret = gpio_request_one(gpio, flags, label);
- if(ret < 0)
- pr_err("Failed to request '%s'\n", label);
-
- return ret;
-}
-////////////////////////////////////////////////////////////////////////////////////////
-//key
-////////////////////////////////////////////////////////////////////////////////////////
-#include <plat/key.h>
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "play",
- .code = KEY_POWER,
- .wakeup = 1,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- },
- {
- .desc = "menu",
- .code = EV_MENU,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- },
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .chn = -1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-////////////////////////////////////////////////////////////////////////////////////////
-//Backlight
-////////////////////////////////////////////////////////////////////////////////////////
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
- printk("rk29_backlight_io_init %d\n",bl_pwm_mode);
- iomux_set(bl_pwm_mode);
- msleep(50);
- if(bl_en== -1)
- return 0;
- ret = port_output_init(bl_en, 1, "bl_en");
- if(ret < 0){
- printk("%s: port output init faild\n", __func__);
- return ret;
- }
- port_output_on(bl_en);
-
- return ret;
-
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0, pwm_gpio;
-
- if(bl_en != -1)
- port_deinit(bl_en);
-
- pwm_gpio = iomux_mode_to_gpio(bl_pwm_mode);
- gpio_request(pwm_gpio, NULL);
- gpio_direction_output(pwm_gpio, GPIO_LOW);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret = 0, pwm_gpio;
-
- pwm_gpio = iomux_mode_to_gpio(bl_pwm_mode);
- if (gpio_request(pwm_gpio, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- gpio_direction_output(pwm_gpio, GPIO_LOW);
- port_output_off(bl_en);
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- int pwm_gpio = iomux_mode_to_gpio(bl_pwm_mode);
-
- gpio_free(pwm_gpio);
- iomux_set(bl_pwm_mode);
- msleep(30);
- port_output_on(bl_en);
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-#endif
-////////////////////////////////////////////////////////////////////////////////////////
-//LCD
-////////////////////////////////////////////////////////////////////////////////////////
-#ifdef CONFIG_FB_ROCKCHIP
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
- //printk("rk_fb_io_init %x,%x,%x\n",lcd_cs,lcd_en,lcd_std);
- if(lcd_cs != -1){
- ret = port_output_init(lcd_cs, 1, "lcd_cs");
- if(ret < 0)
- printk("%s: port output init faild\n", __func__);
- port_output_on(lcd_cs);
- }
-
- if(lcd_en != -1){
- ret = port_output_init(lcd_en, 1, "lcd_en");
- if(ret < 0)
- printk("%s: port output init faild\n", __func__);
- port_output_on(lcd_en);
- }
-
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
- if(lcd_cs != -1)
- port_output_off(lcd_cs);
- if(lcd_en != -1)
- port_output_on(lcd_en);
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- if(lcd_en != -1)
- port_output_on(lcd_en);
- if(lcd_cs != -1)
- port_output_on(lcd_cs);
- return 0;
-}
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
-struct rk29fb_info lcdc0_screen_info = {
-#if defined(CONFIG_RK_HDMI) && defined(CONFIG_HDMI_SOURCE_LCDC0) && defined(CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL)
- .prop = EXTEND, //extend display device
- .io_init = NULL,
- .io_disable = NULL,
- .io_enable = NULL,
- .set_screen_info = hdmi_init_lcdc,
-#else
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-#endif
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
-struct rk29fb_info lcdc1_screen_info = {
-#if defined(CONFIG_RK_HDMI) && defined(CONFIG_HDMI_SOURCE_LCDC1) && defined(CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL)
- .prop = EXTEND, //extend display device
- .io_init = NULL,
- .io_disable = NULL,
- .io_enable = NULL,
- .set_screen_info = hdmi_init_lcdc,
-#else
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-#endif
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
-static struct resource resource_lcdc0[] = {
- [0] = {
- .name = "lcdc0 reg",
- .start = RK3026_LCDC0_PHYS,
- .end = RK3026_LCDC0_PHYS + RK3026_LCDC0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc0 irq",
- .start = IRQ_LCDC,
- .end = IRQ_LCDC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc0 = {
- .name = "rk30-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc0),
- .resource = resource_lcdc0,
- .dev = {
- .platform_data = &lcdc0_screen_info,
- },
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
-static struct resource resource_lcdc1[] = {
- [0] = {
- .name = "lcdc1 reg",
- .start = RK3026_LCDC1_PHYS,
- .end = RK3026_LCDC1_PHYS + RK3026_LCDC1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc1 irq",
- .start = IRQ_LCDC1,
- .end = IRQ_LCDC1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc1 = {
- .name = "rk30-lcdc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resource_lcdc1),
- .resource = resource_lcdc1,
- .dev = {
- .platform_data = &lcdc1_screen_info,
- },
-};
-#endif
-
-static int rk_platform_add_display_devices(void)
-{
- struct platform_device *fb = NULL; //fb
- struct platform_device *lcdc0 = NULL; //lcdc0
- struct platform_device *lcdc1 = NULL; //lcdc1
- struct platform_device *bl = NULL; //backlight
-#ifdef CONFIG_FB_ROCKCHIP
- fb = &device_fb;
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
- lcdc0 = &device_lcdc0,
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
- lcdc1 = &device_lcdc1,
-#endif
-
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- bl = &rk29_device_backlight,
-#endif
- __rk_platform_add_display_devices(fb,lcdc0,lcdc1,bl);
-
- return 0;
-}
-
-////////////////////////////////////////////////////////////////////////////////////////
-//TP
-////////////////////////////////////////////////////////////////////////////////////////
-#if (defined(CONFIG_TOUCHSCREEN_GSLX680_RK3168)||defined (CONFIG_TOUCHSCREEN_GSLX680_RK3028))
-static int gslx680_init_platform_hw()
- {
- int ret;
- if(tp_rst!=-1){
- ret = port_output_init(tp_rst, 1, "tp_rst");
- if(ret<0)
- printk("%s: port output init faild\n", __func__);
- }
-
- port_output_on(tp_rst);
- mdelay(10);
- port_output_off(tp_rst);
- mdelay(10);
- port_output_on(tp_rst);
- msleep(300);
- return 0;
- }
-
-static struct tp_platform_data gslx680_data = {
-
- .init_platform_hw = gslx680_init_platform_hw,
-};
-struct i2c_board_info __initdata gslx680_info = {
- .type = "gslX680",
- .flags = 0,
- .platform_data = &gslx680_data,
-};
-#endif
-
-
-#if defined (CONFIG_TOUCHSCREEN_86V_GT811_IIC)
-int gt811_init_platform_hw(int irq,int reset)
-{
- int ret;
- if(tp_rst!=-1){
- ret = port_output_init(tp_rst, 1, "tp_rst");
- if(ret<0)
- printk("%s: port output init faild\n", __func__);
- }
-
- port_output_off(tp_rst);
- msleep(500);
- port_output_off(tp_rst);
- msleep(500);
- port_output_on(tp_rst);
- mdelay(100);
- return 0;
-}
-
-
-static struct tp_platform_data gt811_data = {
- .model= 811,
- .init_platform_hw= gt811_init_platform_hw,
-};
-
-struct i2c_board_info __initdata gt811_info = {
- .type = "gt811_ts",
- .flags = 0,
- .platform_data = >811_data,
-};
-#endif
-#if defined(CONFIG_TOUCHSCREEN_GT8XX)
-#define TOUCH_PWR_PIN RK30_PIN0_PC5 // need to fly line by hardware engineer
-static int goodix_init_platform_hw(void)
-{
- int ret;
-
- if (TOUCH_PWR_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_PWR_PIN, "goodix power pin");
- if (ret != 0) {
- gpio_free(TOUCH_PWR_PIN);
- printk("goodix power error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_PWR_PIN, 0);
- gpio_set_value(TOUCH_PWR_PIN, GPIO_LOW);
- msleep(100);
- }
-
- if(tp_rst!=-1){
- ret = port_output_init(tp_rst, 1, "tp_rst");
- if(ret<0)
- printk("%s: port output init faild\n", __func__);
- }
- port_output_on(tp_rst);
- msleep(100);
- return 0;
-}
-
-struct tp_platform_data goodix_data = {
- .model = 8105,
- .init_platform_hw = goodix_init_platform_hw,
-};
-
-struct i2c_board_info __initdata goodix_info = {
- .type = "Goodix-TS",
- .flags = 0,
- .platform_data = &goodix_data,
-};
-#endif
-
-////////////////////////////////////////////////////////////////////////////////////////
-//Gsensor
-////////////////////////////////////////////////////////////////////////////////////////
-#if defined (CONFIG_GS_LSM303D)
-static int lms303d_init_platform_hw(void)
-{
- return 0;
-}
-static struct sensor_platform_data lms303d_data = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lms303d_init_platform_hw,
-};
-struct i2c_board_info __initdata lms303d_info = {
- .type = "gs_lsm303d",
- .flags = 0,
- .platform_data =&lms303d_data,
-};
-#endif
-
-#if defined (CONFIG_GS_MMA8452)
-static int mma8452_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data mma8452_data = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma8452_init_platform_hw,
-};
-struct i2c_board_info __initdata mma8452_info = {
- .type = "gs_mma8452",
- .flags = 0,
- .platform_data =&mma8452_data,
-};
-#endif
-
-/*MMA7660 gsensor*/
-#if defined (CONFIG_GS_MMA7660)
-static int mma7660_init_platform_hw(void)
-{
- //rk30_mux_api_set(GPIO1B2_SPI_RXD_UART1_SIN_NAME, GPIO1B_GPIO1B2);
-
- return 0;
-}
-
-static struct sensor_platform_data mma7660_data = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma7660_init_platform_hw,
-};
-struct i2c_board_info __initdata mma7660_info = {
- .type = "gs_mma7660",
- .flags = 0,
- .platform_data =&mma7660_data,
-};
-#endif
-
-#if defined (CONFIG_GS_MXC6225)
-static int mxc6225_init_platform_hw(void)
-{
-// rk30_mux_api_set(GPIO1B1_SPI_TXD_UART1_SOUT_NAME, GPIO1B_GPIO1B1);
- return 0;
-}
-
-static struct sensor_platform_data mxc6225_data = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 0,
- .poll_delay_ms = 30,
- .init_platform_hw = mxc6225_init_platform_hw,
-};
-struct i2c_board_info __initdata mxc6225_info = {
- .type = "gs_mxc6225",
- .flags = 0,
- .platform_data =&mxc6225_data,
-};
-#endif
-
-#if defined (CONFIG_GS_DMT10)
-static int dmt10_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data dmt10_data = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 0,
- .poll_delay_ms = 30,
- .init_platform_hw = dmt10_init_platform_hw,
-};
-struct i2c_board_info __initdata dmt10_info = {
- .type = "gs_dmard10",
- .flags = 0,
- .platform_data =&dmt10_data,
-};
-#endif
-
-
-#if defined (CONFIG_GS_LIS3DH)
-static int lis3dh_init_platform_hw(void)
-{
- return 0;
-}
-static struct sensor_platform_data lis3dh_data = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lis3dh_init_platform_hw,
-};
-struct i2c_board_info __initdata lis3dh_info = {
- .type = "gs_lis3dh",
- .flags = 0,
- .platform_data =&lis3dh_data,
-};
-#endif
-
-////////////////////////////////////////////////////////////////////////////////////////
-//battery
-////////////////////////////////////////////////////////////////////////////////////////
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
-
-};
-
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-
-////////////////////////////////////////////////////////////////////////////////////////
-//codec
-////////////////////////////////////////////////////////////////////////////////////////
-#ifdef CONFIG_SND_SOC_RK3026
-struct rk3026_codec_pdata rk3026_codec_pdata_info={
- .spk_ctl_gpio = RK2928_PIN3_PD4,
- .hp_ctl_gpio = RK2928_PIN3_PD4,
-};
-
-static struct resource resources_acodec[] = {
- {
- .start = RK2928_ACODEC_PHYS,
- .end = RK2928_ACODEC_PHYS + RK2928_ACODEC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device rk3026_codec = {
- .name = "rk3026-codec",
- .id = -1,
- .resource = resources_acodec,
- .dev = {
- .platform_data = &rk3026_codec_pdata_info,
- }
-};
-#endif
-
-#if defined (CONFIG_SND_RK29_SOC_RT5631)
-static struct codec_platform_data rt5631_data = {
-};
-struct i2c_board_info __initdata rt5631_info = {
- .type = "rt5631",
- .flags = 0,
- .platform_data =&rt5631_data,
-};
-#endif
-
-#if defined (CONFIG_SND_RK29_SOC_ES8323)
-static struct codec_platform_data es8323_data = {
-};
-struct i2c_board_info __initdata es8323_info = {
- .type = "es8323",
- .flags = 0,
- .platform_data =&es8323_data,
-};
-#endif
-
-#if defined(CONFIG_MFD_RK616)
-#define RK616_SCL_RATE (100*1000) //i2c scl rate
-static int rk616_power_on_init(void)
-{
- int ret;
-
- if(codec_power!=-1)
- {
- ret = port_output_init(codec_power, 1, "codec_power");
- if(ret < 0)
- printk("%s: port output init faild\n", __func__);
- port_output_on(codec_power);
- }
-
- if(codec_rst!=-1)
- {
- ret = port_output_init(codec_rst, 1, "codec_rst");
- if(ret < 0)
- printk("%s: port output init faild\n", __func__);
- port_output_on(codec_rst);
- msleep(100);
- port_output_off(codec_rst);
- msleep(100);
- port_output_on(codec_rst);
- }
- return 0;
-
-}
-
-
-static int rk616_power_deinit(void)
-{
- if(codec_power!=-1)
- {
- port_output_off(codec_power);
- port_deinit(codec_power);
- }
- if(codec_rst!=-1)
- {
- port_output_off(codec_rst);
- port_deinit(codec_rst);
- }
- return 0;
-}
-
-static struct rk616_platform_data rk616_pdata = {
- .power_init = rk616_power_on_init,
- .power_deinit = rk616_power_deinit,
- .scl_rate = RK616_SCL_RATE,
- .lcd0_func = INPUT, //port lcd0 as input
- .lcd1_func = INPUT, //port lcd1 as input
- .lvds_ch_nr = 1, //the number of used lvds channel
- //.hdmi_irq = RK30_PIN2_PD6,
- //.spk_ctl_gpio = RK30_PIN2_PD7,
- .hp_ctl_gpio = RK30_PIN2_PD7,
-};
-
-struct i2c_board_info __initdata rk616_info = {
- .type = "rk616",
- .flags = 0,
- .platform_data = &rk616_pdata,
-};
-#endif
-
-
-////////////////////////////////////////////////////////////////////////////////////////
-//spi
-////////////////////////////////////////////////////////////////////////////////////////
-static struct spi_board_info board_spi_devices[] = {
-};
-
-
-////////////////////////////////////////////////////////////////////////////////////////
-//compass
-////////////////////////////////////////////////////////////////////////////////////////
-#if defined (CONFIG_COMPASS_AK8975)
-static struct sensor_platform_data akm8975_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-#if defined (CONFIG_COMPASS_AK8963)
-static struct sensor_platform_data akm8963_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {0, 1, 0},
- {1, 0, 0},
- {0, 0, -1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {0, -1, 0},
- {-1, 0, 0},
- {0, 0, -1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-
-#if defined(CONFIG_GYRO_L3G4200D)
-
-#include <linux/l3g4200d.h>
-#define L3G4200D_INT_PIN RK30_PIN0_PB4
-
-static int l3g4200d_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data l3g4200d_info = {
- .type = SENSOR_TYPE_GYROSCOPE,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
- .init_platform_hw = l3g4200d_init_platform_hw,
- .x_min = 40,//x_min,y_min,z_min = (0-100) according to hardware
- .y_min = 40,
- .z_min = 20,
-};
-
-#endif
-
-#ifdef CONFIG_LS_CM3217
-static struct sensor_platform_data cm3217_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 0,
- .poll_delay_ms = 500,
-};
-
-#endif
-
-
-/***********************************************************
-* sdmmc
-************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "board-rk3028a-86v-sdmmc-config.c"
-#include "../plat-rk/rk-sdmmc-ops.c"
-#include "../plat-rk/rk-sdmmc-wifi.c"
-#endif //endif ---#ifdef CONFIG_SDMMC_RK29
-
-#ifdef CONFIG_SDMMC0_RK29
-#define CONFIG_SDMMC0_USE_DMA
-static int rk29_sdmmc0_cfg_gpio(void)
-{
- rk29_sdmmc_set_iomux(0, 0xFFFF);
- #if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- iomux_set_gpio_mode(iomux_gpio_to_mode(RK29SDK_SD_CARD_DETECT_N));
- #else
- iomux_set(MMC0_DETN);
- #endif
-
- #if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
- #endif
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
- .set_iomux = rk29_sdmmc_set_iomux,
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) && defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- .status = rk29sdk_wifi_mmc0_status,
- .register_status_notify = rk29sdk_wifi_mmc0_status_register,
-#endif
-
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .power_en = RK29SDK_SD_CARD_PWR_EN,
- .power_en_level = RK29SDK_SD_CARD_PWR_EN_LEVEL,
-#else
- .power_en = INVALID_GPIO,
- .power_en_level = GPIO_LOW,
-#endif
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC0_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- .det_pin_info = {
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N, //INVALID_GPIO,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
- #endif
- },
-
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
- .set_iomux = rk29_sdmmc_set_iomux,
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC) || defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC1_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- #if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
- .sdio_INT_gpio = RK29SDK_WIFI_SDIO_CARD_INT,
- #endif
-
- .det_pin_info = {
- #if defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- #else
- .io = INVALID_GPIO,
- #endif
-
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
- #endif
- },
- .enable_sd_wakeup = 0,
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-/***********************************************************
-* rfkill
-************************************************************/
-#ifdef CONFIG_RFKILL_RK
-// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
-static struct rfkill_rk_platform_data rfkill_rk_platdata = {
- .type = RFKILL_TYPE_BLUETOOTH,
-
- .poweron_gpio = { // BT_REG_ON
- .io = INVALID_GPIO, //RK30_PIN3_PC7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_poweron",
- //.fgpio = GPIO3_C7,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN1_PB3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_reset",
- .fgpio = GPIO1_B3,
- },
- },
-
- .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
- .io = RK30_PIN1_PB2, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_wake",
- .fgpio = GPIO1_B2,
- },
- },
-
- .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .gpio = {
- .io = RK30_PIN0_PA4, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
- .iomux = {
- .name = "bt_wake_host",
- //.fgpio = GPIO0_A4,
- },
- },
- },
-
- .rts_gpio = { // UART_RTS, enable or disable BT's data coming
- .io = RK30_PIN1_PA3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_rts",
- .fgpio = GPIO1_A3,
- .fmux = UART0_RTSN,
- },
- }
-};
-
-static struct platform_device device_rfkill_rk = {
- .name = "rfkill_rk",
- .id = -1,
- .dev = {
- .platform_data = &rfkill_rk_platdata,
- },
-};
-#endif
-
-/***********************************************************
-* ion
-************************************************************/
-#ifdef CONFIG_ION
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-/***********************************************************
-* pwm regulator
-************************************************************/
-#ifdef CONFIG_RK30_PWM_REGULATOR
-static int pwm_voltage_map[] = {
- 800000, 825000, 850000, 875000, 900000, 925000 ,
- 950000, 975000, 1000000, 1025000, 1050000, 1075000,
- 1100000, 1125000, 1150000, 1175000, 1200000, 1225000,
- 1250000, 1275000, 1300000, 1325000, 1350000, 1375000
-};
-
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_core",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] = {
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
- .pwm_id = REG_PWM,
- .pwm_voltage = 1200000,
- .suspend_voltage = 1050000,
- .min_uV = 950000,
- .max_uV = 1400000,
- .coefficient = 504, //50.4%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-
-static void pwm_regulator_init(void)
-{
- pwm_regulator_info[0].pwm_gpio = iomux_mode_to_gpio(pwm_mode[REG_PWM]);
- pwm_regulator_info[0].pwm_iomux_pwm = pwm_mode[REG_PWM];
- pwm_regulator_info[0].pwm_iomux_gpio = iomux_switch_gpio_mode(pwm_mode[REG_PWM]);
-}
-#endif
-
-int __sramdata pwm_iomux, pwm_do, pwm_dir, pwm_en;
-#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
-
-#define GPIO0_D2_OFFSET 10
-void __sramfunc rk30_pwm_logic_suspend_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- #if 0
- /* pwm0: GPIO0_D2, pwm1: GPIO0_D3, pwm2: GPIO0_D4 */
- int off = GPIO0_D2_OFFSET + REG_PWM;
-
- sram_udelay(10000);
- pwm_iomux = grf_readl(GRF_GPIO0D_IOMUX);
- pwm_dir = grf_readl(GRF_GPIO0H_DIR);
- pwm_do = grf_readl(GRF_GPIO0H_DO);
- pwm__en = grf_readl(GRF_GPIO0H_EN);
-
- grf_writel((1<<(2 * off), GRF_GPIO0D_IOMUX);
- grf_writel((1<<(16 + off))|(1<<off), GRF_GPIO0H_DIR);
- grf_writel((1<<(16 + off))|(1<<off), GRF_GPIO0H_DO);
- #endif
-#endif
-}
-
-void __sramfunc rk30_pwm_logic_resume_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- #if 0
- /* pwm0: GPIO0_D2, pwm1: GPIO0_D3, pwm2: GPIO0_D4 */
- int off = GPIO0_D2_OFFSET + REG_PWM;
-
- grf_writel((1<<(2 * off))|pwm_iomux, GRF_GPIO0D_IOMUX);
- grf_writel(((1<<(16 + off))|pwm_dir), GRF_GPIO0L_DIR);
- grf_writel(((1<<(16 + off))|pwm_do), GRF_GPIO0L_DO);
- grf_writel(((1<<(16 + off))|pwm_en), GRF_GPIO0L_EN);
- sram_udelay(10000);
- #endif
-#endif
-}
-extern void pwm_suspend_voltage(void);
-extern void pwm_resume_voltage(void);
-
-void rk30_pwm_suspend_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_suspend_voltage();
-#endif
-}
-
-void rk30_pwm_resume_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_resume_voltage();
-#endif
-}
-
-/***********************************************************
-* pmic
-************************************************************/
-int __sramdata g_pmic_type = 0;
-
-#ifdef CONFIG_MFD_TPS65910
-#define TPS65910_HOST_IRQ PMU_INT_PIN
-#define PMU_POWER_SLEEP PMU_SLEEP_PIN
-static struct pmu_info tps65910_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1100000,
- .max_uv = 1100000,
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1100000,
- .max_uv = 1100000,
- },
- {
- .name = "vio", //vcc_io
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
-
-};
-static struct pmu_info tps65910_ldo_info[] = {
- /*{
- .name = "vpll", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- },*/
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 2800000,//1800000,
- .max_uv = 2800000,//1800000,
- },
- {
- .name = "vdig2", //vdd11
- .min_uv = 1100000,
- .max_uv = 1100000,
- },
- {
- .name = "vaux1", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "vaux2", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vaux33", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vmmc", //vcca30
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
- {
- .name = "vdac", //
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
-};
-#include "../mach-rk30/board-pmu-tps65910.c"
-#endif
-
-void __sramfunc board_pmu_suspend(void)
-{
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_suspend();
- #endif
-}
-
-void __sramfunc board_pmu_resume(void)
-{
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_resume();
- #endif
-}
-
-#if defined(CONFIG_GPS_RK)
-#define GPS_OSCEN_PIN RK2928_PIN1_PB0
-#define GPS_RXEN_PIN RK2928_PIN1_PB0
-
-static int rk_gps_io_init(void)
-{
- printk("%s \n", __FUNCTION__);
-
- gpio_request(GPS_OSCEN_PIN, NULL);
- gpio_direction_output(GPS_OSCEN_PIN, GPIO_LOW);
-
- iomux_set(GPS_CLK);//GPS_CLK
- iomux_set(GPS_MAG);//GPS_MAG
- iomux_set(GPS_SIGN);//GPS_SIGN
-#if 0
- gpio_request(RK30_PIN1_PA6, NULL);
- gpio_direction_output(RK30_PIN1_PA6, GPIO_LOW);
-
- gpio_request(RK30_PIN1_PA5, NULL);
- gpio_direction_output(RK30_PIN1_PA5, GPIO_LOW);
-
- gpio_request(RK30_PIN1_PA7, NULL);
- gpio_direction_output(RK30_PIN1_PA7, GPIO_LOW);
-#endif
- return 0;
-}
-static int rk_gps_power_up(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-static int rk_gps_power_down(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-static int rk_gps_reset_set(int level)
-{
- return 0;
-}
-static int rk_enable_hclk_gps(void)
-{
- struct clk *gps_aclk = NULL;
- gps_aclk = clk_get(NULL, "aclk_gps");
- if(gps_aclk) {
- clk_enable(gps_aclk);
- clk_put(gps_aclk);
- printk("%s \n", __FUNCTION__);
- }
- else
- printk("get gps aclk fail\n");
- return 0;
-}
-static int rk_disable_hclk_gps(void)
-{
- struct clk *gps_aclk = NULL;
- gps_aclk = clk_get(NULL, "aclk_gps");
- if(gps_aclk) {
- //TO wait long enough until GPS ISR is finished.
- msleep(5);
- clk_disable(gps_aclk);
- clk_put(gps_aclk);
- printk("%s \n", __FUNCTION__);
- }
- else
- printk("get gps aclk fail\n");
- return 0;
-}
-static struct rk_gps_data rk_gps_info = {
- .io_init = rk_gps_io_init,
- .power_up = rk_gps_power_up,
- .power_down = rk_gps_power_down,
- .reset = rk_gps_reset_set,
- .enable_hclk_gps = rk_enable_hclk_gps,
- .disable_hclk_gps = rk_disable_hclk_gps,
- .GpsSign = RK2928_PIN1_PA5,
- .GpsMag = RK2928_PIN1_PA4, //GPIO index
- .GpsClk = RK2928_PIN1_PA2, //GPIO index
- .GpsVCCEn = GPS_OSCEN_PIN, //GPIO index
-#if 0
- .GpsSpi_CSO = RK30_PIN1_PA4, //GPIO index
- .GpsSpiClk = RK30_PIN1_PA5, //GPIO index
- .GpsSpiMOSI = RK30_PIN1_PA7, //GPIO index
-#endif
- .GpsIrq = IRQ_GPS,
- .GpsSpiEn = 0,
- .GpsAdcCh = 2,
- .u32GpsPhyAddr = RK2928_GPS_PHYS,
- .u32GpsPhySize = RK2928_GPS_SIZE,
-};
-
-static struct platform_device rk_device_gps = {
- .name = "gps_hv5820b",
- .id = -1,
- .dev = {
- .platform_data = &rk_gps_info,
- }
- };
-#endif
-
-
-/***********************************************************
-* i2c
-************************************************************/
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C1_RK30
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8975_info,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8975_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8963)
- {
- .type = "ak8963",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8963_info,
- },
-#endif
-#if defined (CONFIG_GYRO_L3G4200D)
- {
- .type = "l3g4200d_gryo",
- .addr = 0x69,
- .flags = 0,
- .irq = L3G4200D_INT_PIN,
- .platform_data = &l3g4200d_info,
- },
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO// RK30_PIN2_PD6 //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO//RK30_PIN2_PD7 //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- return 0;
-}
-
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-
-};
-#endif
-
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(4, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-
-/***********************************************************
-* board init
-************************************************************/
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- &rk29sdk_wifi_device,
-#endif
-#ifdef CONFIG_RFKILL_RK
- &device_rfkill_rk,
-#endif
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
- &rk30_device_adc_battery,
-#endif
-#ifdef CONFIG_SND_SOC_RK3026
- &rk3026_codec,
-#endif
-#ifdef CONFIG_GPS_RK
- &rk_device_gps,
-#endif
-};
-
-static void rk30_pm_power_off(void)
-{
-#if defined(CONFIG_MFD_TPS65910)
- tps65910_device_shutdown();//tps65910 shutdown
-#endif
- port_output_off(pwr_on);
- while(1);
-}
-static int __init tp_board_init(void)
-{
- int i;
- struct port_config irq_port;
- struct port_config rst_port;
- int ret = check_tp_param();
-
- if(ret < 0)
- return ret;
-
- irq_port = get_port_config(tp_irq);
- rst_port = get_port_config(tp_rst);
-#if (defined (CONFIG_TOUCHSCREEN_GSLX680_RK3168)||defined (CONFIG_TOUCHSCREEN_GSLX680_RK3028))
- if(tp_type == TP_TYPE_GSLX680){
- gslx680_data.irq_pin = irq_port.gpio;
- gslx680_info.addr = tp_addr;
- gslx680_data.reset_pin= rst_port.gpio;
- gslx680_data.x_max=tp_xmax;
- gslx680_data.y_max=tp_ymax;
- gslx680_data.firmVer=tp_firmVer;
- i2c_register_board_info(tp_i2c, &gslx680_info, 1);
- }
-#endif
-
-#if defined (CONFIG_TOUCHSCREEN_86V_GT811_IIC)
- if(tp_type == TP_TYPE_GT811_86V){
- gt811_data.irq_pin = irq_port.gpio;
- gt811_info.addr = tp_addr;
- gt811_data.reset_pin= rst_port.gpio;
- gt811_data.x_max=tp_xmax;
- gt811_data.y_max=tp_ymax;
- i2c_register_board_info(tp_i2c, >811_info, 1);
- }
-#endif
-
-#if defined(CONFIG_TOUCHSCREEN_GT8XX)
- if(tp_type == TP_TYPE_GT8XX){
- goodix_data.irq_pin = irq_port.gpio;
- goodix_info.addr = tp_addr;
- goodix_data.reset_pin= rst_port.gpio;
- goodix_data.x_max=tp_xmax;
- goodix_data.y_max=tp_ymax;
- i2c_register_board_info(tp_i2c, &goodix_info, 1);
- }
-#endif
- return 0;
-}
-
-
-static int __init codec_board_init(void)
-{
- struct port_config spk_port;
- struct port_config hp_port;
- struct port_config hdmi_irq_port;
- int ret = check_codec_param();
-
- if(ret < 0)
- return ret;
-
- spk_port = get_port_config(spk_ctl);
- hp_port = get_port_config(hp_det);
-
-#if defined (CONFIG_SND_RK29_SOC_RT5631)
- if(codec_type == CODEC_TYPE_RT5631){
- rt5631_data.spk_pin = spk_port.gpio;
- rt5631_info.addr = codec_addr;
- rt5631_data.hp_pin= hp_port.gpio;
- i2c_register_board_info(codec_i2c, &rt5631_info, 1);
- }
-#endif
-
-#if defined (CONFIG_SND_RK29_SOC_ES8323)
- if(codec_type == CODEC_TYPE_ES8323){
- es8323_data.spk_pin = spk_port.gpio;
- es8323_info.addr = codec_addr;
- es8323_data.hp_pin= hp_port.gpio;
- i2c_register_board_info(codec_i2c, &es8323_info, 1);
- }
-#endif
-
-#if defined (CONFIG_MFD_RK616)
-if(codec_type == CODEC_TYPE_RK616){
- rk616_pdata.spk_ctl_gpio = spk_port.gpio;
- rk616_info.addr = codec_addr;
- rk616_pdata.hdmi_irq= get_port_config(codec_hdmi_irq).gpio;
- i2c_register_board_info(codec_i2c, &rk616_info, 1);
- }
-#endif
- return 0;
-}
-
-static int __init chg_board_init(void)
-{
- int i;
- int ret = check_chg_param();
- if(ret < 0)
- return ret;
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
- //rk30_adc_battery_platdata.adc_channel = chg_adc;
- if(dc_det != -1){
- rk30_adc_battery_platdata.dc_det_pin = get_port_config(dc_det).gpio;
- printk("rk30_adc_battery_platdata.dc_det_pin %d %d",rk30_adc_battery_platdata.dc_det_pin,RK30_PIN0_PB2);
- rk30_adc_battery_platdata.dc_det_level = !get_port_config(dc_det).io.active_low;
- }
- else{
- rk30_adc_battery_platdata.dc_det_pin=INVALID_GPIO;
- }
- if(bat_low != -1){
- rk30_adc_battery_platdata.batt_low_pin = get_port_config(bat_low).gpio;
- rk30_adc_battery_platdata.batt_low_level = !get_port_config(bat_low).io.active_low;
- }
- else{
- rk30_adc_battery_platdata.batt_low_pin=INVALID_GPIO;
- }
- if(chg_ok != -1){
- rk30_adc_battery_platdata.charge_ok_pin = get_port_config(chg_ok).gpio;
- rk30_adc_battery_platdata.charge_ok_level = !get_port_config(chg_ok).io.active_low;
- }
- else{
- rk30_adc_battery_platdata.charge_ok_pin=INVALID_GPIO;
- }
- if(chg_set != -1){
- rk30_adc_battery_platdata.charge_set_pin = get_port_config(chg_set).gpio;
- rk30_adc_battery_platdata.charge_set_level = !get_port_config(chg_set).io.active_low;
- }
- else{
- rk30_adc_battery_platdata.charge_set_pin=INVALID_GPIO;
- }
- if(usb_det!= -1){
- rk30_adc_battery_platdata.usb_det_pin = get_port_config(chg_set).gpio;
- rk30_adc_battery_platdata.usb_det_level = !get_port_config(chg_set).io.active_low;
- }
- else{
- rk30_adc_battery_platdata.usb_det_pin=INVALID_GPIO;
- }
-
- if(ref_vol!= -1){
- rk30_adc_battery_platdata.reference_voltage=ref_vol;
- }
-
- if(up_res!= -1){
- rk30_adc_battery_platdata.pull_up_res=up_res;
- }
- if(down_res!= -1){
- rk30_adc_battery_platdata.pull_down_res=down_res;
- }
- if(root_chg!= -1){
- rk30_adc_battery_platdata.is_reboot_charging=root_chg;
- }
- if(save_cap!= -1){
- rk30_adc_battery_platdata.save_capacity=save_cap;
- }
- if(low_vol!= -1){
- rk30_adc_battery_platdata.low_voltage_protection=low_vol;
- }
-
- for(i=0;i<11;i++)
- {
- rk30_adc_battery_platdata.chargeArray[i]=bat_charge[i];
- rk30_adc_battery_platdata.dischargeArray[i]=bat_discharge[i];
- }
-#endif
- return 0;
-}
-
-static int __init gs_board_init(void)
-{
- int i;
- struct port_config port;
- int ret = check_gs_param();
- if(ret < 0)
- return ret;
- port = get_port_config(gs_irq);
-//mma7660
-#if defined (CONFIG_GS_MMA7660)
- if(gs_type == GS_TYPE_MMA7660){
-
- mma7660_info.irq = port.gpio;
- mma7660_info.addr = gs_addr;
- for(i = 0; i < 9; i++)
- mma7660_data.orientation[i] = gs_orig[i];
- i2c_register_board_info(gs_i2c, &mma7660_info, 1);
- }
-#endif
-
-#if defined (CONFIG_GS_LIS3DH)
- if(gs_type == GS_TYPE_LIS3DH){
- lis3dh_info.irq = port.gpio;
- lis3dh_info.addr = gs_addr;
- for(i = 0; i < 9; i++)
- lis3dh_data.orientation[i] = gs_orig[i];
- i2c_register_board_info(gs_i2c, &lis3dh_info, 1);
- }
-#endif
-
-#if defined (CONFIG_GS_MXC6225)
- if(gs_type == GS_TYPE_MXC6225){
- mxc6225_info.irq = port.gpio;
- mxc6225_info.addr = gs_addr;
- for(i = 0; i < 9; i++)
- mxc6225_data.orientation[i] = gs_orig[i];
- i2c_register_board_info(gs_i2c, &mxc6225_info, 1);
- }
-#endif
-
-#if defined (CONFIG_GS_DMT10)
- if(gs_type == GS_TYPE_DMARAD10){
- dmt10_info.irq = port.gpio;
- dmt10_info.addr = gs_addr;
- for(i = 0; i < 9; i++)
- dmt10_data.orientation[i] = gs_orig[i];
- i2c_register_board_info(gs_i2c, &dmt10_info, 1);
- }
-#endif
-
-#if defined (CONFIG_GS_MMA8452)
- if(gs_type == GS_TYPE_MMA8452){
- mma8452_info.irq = port.gpio;
- mma8452_info.addr = gs_addr;
- for(i = 0; i < 9; i++)
- mma8452_data.orientation[i] = gs_orig[i];
- i2c_register_board_info(gs_i2c, &mma8452_info, 1);
- }
-#endif
-
-#if defined (CONFIG_GS_LSM303D)
- if(gs_type == GS_TYPE_LSM303D){
- lms303d_info.irq = port.gpio;
- lms303d_info.addr = gs_addr;
- for(i = 0; i < 9; i++)
- lms303d_data.orientation[i] = gs_orig[i];
- i2c_register_board_info(gs_i2c, &lms303d_info, 1);
- }
-#endif
- return 0;
-}
-
-static int __init bl_board_init(void){
- int ret = check_bl_param();
- if(ret < 0)
- return ret;
-
- switch(bl_pwmid)
- {
- case 0:
- bl_pwm_mode = PWM0;
- break;
- case 1:
- bl_pwm_mode = PWM1;
- break;
- case 2:
- bl_pwm_mode = PWM2;
- break;
- }
-
- rk29_bl_info.pwm_id = bl_pwmid;
- rk29_bl_info.brightness_mode=bl_mode;
- rk29_bl_info.pre_div=bl_div;
- rk29_bl_info.bl_ref = bl_ref;
- rk29_bl_info.min_brightness=bl_min;
- rk29_bl_info.max_brightness=bl_max;
-
-
- return 0;
-}
-
-static int __init lcd_board_init(void)
-{
- return check_lcd_param();
-}
-
-static int __init key_board_init(void){
- int i;
- struct port_config port;
- for(i = 0; i < key_val_size; i++){
- if(key_val[i] & (1<<31)){
- key_button[i].adc_value = key_val[i] & 0xffff;
- key_button[i].gpio = INVALID_GPIO;
- }else{
- port = get_port_config(key_val[i]);
- key_button[i].gpio = port.gpio;
- key_button[i].active_low = port.io.active_low;
- }
- }
- rk29_keys_pdata.nbuttons = key_val_size;
- rk29_keys_pdata.chn = key_adc;
- return 0;
-}
-
-static int __init wifi_board_init(void)
-{
- return check_wifi_param();
-}
-
-
-static int __init rk_config_init(void)
-{
- int ret = 0;
- ret = lcd_board_init();
- if(ret < 0)
- INIT_ERR("lcd");
-
- ret = bl_board_init();
- if(ret < 0)
- INIT_ERR("backlight");
-
- ret = tp_board_init();
- if(ret < 0)
- INIT_ERR("tp");
-
- ret = gs_board_init();
- if(ret < 0)
- INIT_ERR("gsensor");
-
- ret = codec_board_init();
- if(ret < 0)
- INIT_ERR("codec");
-
- ret = key_board_init();
- if(ret < 0)
- INIT_ERR("key");
-
- ret = chg_board_init();
- if(ret < 0)
- INIT_ERR("charge");
-
- ret = wifi_board_init();
- if(ret < 0)
- INIT_ERR("wifi");
-
- return 0;
-}
-
-static void __init machine_rk30_board_init(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_regulator_init();
-#endif
- avs_init();
- pm_power_off = rk30_pm_power_off;
- rk_power_on();
- rk_config_init();
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- rk_platform_add_display_devices();
-#if defined(CONFIG_WIFI_CONTROL_FUNC)
- rk29sdk_wifi_bt_gpio_control_init();
-#elif defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- rk29sdk_wifi_combo_module_gpio_init();
-#endif
-}
-
-static void __init rk30_reserve(void)
-{
- //fb reserve
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0 buf", get_fb_size());
- resource_fb[0].end = resource_fb[0].start + get_fb_size()- 1;
- #if 0
- resource_fb[1].start = board_mem_reserve_add("ipp buf", RK30_FB0_MEM_SIZE);
- resource_fb[1].end = resource_fb[1].start + RK30_FB0_MEM_SIZE - 1;
- #endif
-
- #if defined(CONFIG_FB_ROTATE) || !defined(CONFIG_THREE_FB_BUFFER)
- resource_fb[2].start = board_mem_reserve_add("fb2 buf",get_fb_size());
- resource_fb[2].end = resource_fb[2].start + get_fb_size() - 1;
- #endif
-#endif
- //ion reserve
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
-#ifdef CONFIG_GPS_RK
- //it must be more than 8MB
- rk_gps_info.u32MemoryPhyAddr = board_mem_reserve_add("gps", SZ_8M);
-#endif
- board_mem_reserved();
-}
-
-/***********************************************************
-* clock
-************************************************************/
-static struct cpufreq_frequency_table dvfs_arm_table[] = {
- {.frequency = 312 * 1000, .index = 1100 * 1000},
- {.frequency = 504 * 1000, .index = 1100 * 1000},
- {.frequency = 816 * 1000, .index = 1150 * 1000},
- {.frequency = 1008 * 1000, .index = 1200 * 1000},
- //{.frequency = 1200 * 1000, .index = 1300 * 1000},
- //{.frequency = 1416 * 1000, .index = 1200 * 1000},
- //{.frequency = 1608 * 1000, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- //{.frequency = 100 * 1000, .index = 1200 * 1000},
- {.frequency = 200 * 1000, .index = 1200 * 1000},
- //{.frequency = 266 * 1000, .index = 1200 * 1000},
- //{.frequency = 300 * 1000, .index = 1200 * 1000},
- //{.frequency = 400 * 1000, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- //{.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 1200 * 1000},
- //{.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = 1200 * 1000},
- {.frequency = 360 * 1000 + DDR_FREQ_NORMAL, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-void __init board_clock_init(void)
-{
- rk2928_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
- //dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "cpu"), dvfs_arm_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
-}
-
-/************************ end *****************************/
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk2928_fixup,
- .reserve = &rk30_reserve,
- .map_io = rk2928_map_io,
- .init_irq = rk2928_init_irq,
- .timer = &rk2928_timer,
- .init_machine = machine_rk30_board_init,
-MACHINE_END
+++ /dev/null
-/*****************************************************************************************
- * arch/arm/mach-rkxx/baord-xxx-sdmmc-config.c
- *
- * Copyright (C) 2013 ROCKCHIP, Inc.
- *
- * Description:
- * define the gpio for SD-MMC-SDIO-Wifi functions according to your own projects.
- *
- * Author: Michael Xie
- * 15 Jan,2013
- * E-mail: xbw@rock-chips.com
- *
- ******************************************************************************************/
-
-/*
-** If you select the macro of CONFIG_SDMMC0_RK29_WRITE_PROTECT, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define SDMMC0_WRITE_PROTECT_PIN RK30_PIN3_PB2 //According to your own project to set the value of write-protect-pin.
-//#define SDMMC0_WRITE_PROTECT_ENABLE_VALUE GPIO_HIGH
-
-/*
-** If you select the macro of CONFIG_SDMMC1_RK29_WRITE_PROTECT, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define SDMMC1_WRITE_PROTECT_PIN RK30_PIN3_PB3 //According to your own project to set the value of write-protect-pin.
-//#define SDMMC1_WRITE_PROTECT_ENABLE_VALUE GPIO_HIGH
-
-/*
-** If you select the macro of CONFIG_RK29_SDIO_IRQ_FROM_GPIO, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define RK29SDK_WIFI_SDIO_CARD_INT RK30_PIN3_PD2
-
-
-/*
-* define sdcard PowerEn-pin
-*/
-#define RK29SDK_SD_CARD_PWR_EN RK30_PIN3_PA1
-#define RK29SDK_SD_CARD_PWR_EN_LEVEL GPIO_LOW
-int rk31sdk_get_sdmmc0_pin_io_voltage(void)
-{
- int voltage;
-#define RK31SDK_SET_SDMMC0_PIN_VOLTAGE
-
- /**************************************************************************************
- ** Please tell me how much voltage of your SDMMC0-pin in your project.
- **
- ** ÀýÈç: ÓеÄÏîÄ¿£¬ËüµÄSDMMC0ËùÔÚµÄRKÖ÷¿ØµÄIO×飬ÏëÓÃ1.8V, ¶ø¿¨±¾ÉíÓÃ3.3V,
- ** ¶øÖмäͨ¹ý¸öµçƽת»».ÄÇô£¬Äú´Ëʱ£¬Ó¦¸ÃÉèÖÃÏÂÃæµÄvoltageֵΪ 1.8V(¼´1800mv)
- ***************************************************************************************/
- voltage = 3300; //default the voltage 3300mv.
-
- return voltage;
-}
-
-/*
-* define the card-detect-pin.
-*/
-#define RK29SDK_SD_CARD_DETECT_N RK30_PIN3_PB0 //According to your own project to set the value of card-detect-pin.
-#define RK29SDK_SD_CARD_INSERT_LEVEL GPIO_LOW // set the voltage of insert-card. Please pay attention to the default setting.
-
-/*
-* Define wifi module's power and reset gpio, and gpio sensitive level.
-* Please set the value according to your own project.
-*
-* Well, you just own engineering module to set the value in the corresponding module branch.
-* Otherwise, you do not define this macro, eliminate it.
-*
-*/
-#if defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU) || defined(CONFIG_RTL8723AU) || defined(CONFIG_MT7601)
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD3
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_LOW//GPIO_HIGH
-
-#elif defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319) || defined(CONFIG_RKWIFI) || defined(CONFIG_RTL8189ES)
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD3
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN0_PC2 // RK30_PIN2_PA7
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
-
-#elif defined(CONFIG_MT5931_MT6622) || defined(CONFIG_MT5931)
-
- #ifdef CONFIG_MACH_RK3168_LR097
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- //#define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- //#define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
-
- #else
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN0_PA5
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #endif
-
-#elif defined(CONFIG_MT6620)
- #define COMBO_MODULE_MT6620_CDT 0 // to control antsel2,antsel3 and gps_lan foot when using AcSip or Cdtech chip.
- //- 1--use Cdtech chip; 0--unuse CDT chip
-
- //power, PMU_EN//hjc test
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN0_PB5
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- //reset, DAIRST,SYSRST_B
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- //VDDIO
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL RK30_PIN0_PD2 //You do not get control of the foot, and you do not need to define the macro
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_ENABLE_VALUE GPIO_HIGH
- //WIFI_INT_B
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
- //BGF_INT_B
- #define RK30SDK_WIFI_GPIO_BGF_INT_B RK30_PIN0_PA5
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_ENABLE_VALUE GPIO_HIGH
- //GPS_SYNC
- #define RK30SDK_WIFI_GPIO_GPS_SYNC RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_ENABLE_VALUE GPIO_HIGH
-
- #if COMBO_MODULE_MT6620_CDT
- //ANTSEL2
- #define RK30SDK_WIFI_GPIO_ANTSEL2 RK30_PIN4_PD4
- #define RK30SDK_WIFI_GPIO_ANTSEL2_ENABLE_VALUE GPIO_LOW //use 6620 in CDT chip, LOW--work; High--no work.
- //ANTSEL3
- #define RK30SDK_WIFI_GPIO_ANTSEL3 RK30_PIN4_PD3
- #define RK30SDK_WIFI_GPIO_ANTSEL3_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- //GPS_LAN
- #define RK30SDK_WIFI_GPIO_GPS_LAN RK30_PIN4_PD6
- #define RK30SDK_WIFI_GPIO_GPS_LAN_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- #endif // #if COMBO_MODULE_MT6620_CDT--#endif
-#endif
-
-#ifndef RK30SDK_WIFI_GPIO_WIFI_INT_B
-#define RK30SDK_WIFI_GPIO_WIFI_INT_B INVALID_GPIO
-#define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
-#endif
-
-int rk31sdk_get_sdio_wifi_voltage(void)
-{
- int voltage;
-
- /******************************************************************************
- ** Please tell me how much wifi-module uses voltage in your project.
- ******************************************************************************/
-#if defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319) || defined(CONFIG_RKWIFI)
- voltage = 1800 ; //power 1800mV
-
-#elif defined(CONFIG_MT5931_MT6622)||defined(CONFIG_MT5931)
- voltage = 1800 ; //power 1800V
-#elif defined(CONFIG_MT6620)
- voltage = 1800 ; //power 2800V
-#elif defined(CONFIG_RDA5990)||defined(CONFIG_RTL8723AS)
- voltage = 3300 ; //power 3300V
-#else
- //default, sdio use 3.0V
- voltage = 3000 ; //power 3000V
-#endif
-
- return voltage;
-}
-
-
-
+++ /dev/null
-/*
- * Copyright (C) 2013 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <linux/rk_fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/mfd/tps65910.h>
-#include <linux/regulator/act8846.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/dvfs.h>
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-
-#ifdef CONFIG_SND_SOC_RK3026
-#include "../../../sound/soc/codecs/rk3026_codec.h"
-#endif
-
-#if defined(CONFIG_RK_HDMI)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#if defined(CONFIG_GPS_RK)
-#include "../../../drivers/misc/gps/rk_gps/rk_gps.h"
-#endif
-#include "board-rk3028a-86v-camera.c"
-
-/***********************************************************
-* board config
-************************************************************/
-//system power on
-#define POWER_ON_PIN RK30_PIN1_PA1 //PWR_HOLD
-
-//touchscreen
-#define TOUCH_RST_PIN RK30_PIN3_PC3
-#define TOUCH_RST_VALUE GPIO_HIGH
-#define TOUCH_PWR_PIN RK30_PIN2_PD0
-#define TOUCH_PWR_VALUE GPIO_LOW
-#define TOUCH_INT_PIN RK30_PIN3_PC7
-
-//backlight
-#define LCD_DISP_ON_PIN
-#define BL_PWM 0 // (0 ~ 2)
-#define PWM_EFFECT_VALUE 0
-#define BL_EN_PIN RK30_PIN3_PC5
-#define BL_EN_VALUE GPIO_HIGH
-
-//fb
-#define LCD_EN_PIN RK30_PIN3_PD2
-#define LCD_EN_VALUE GPIO_LOW
-#define LCD_CS_PIN INVALID_GPIO
-#define LCD_CS_VALUE GPIO_LOW
-
-//gsensor
-#define GS_INT_PIN RK30_PIN3_PD1
-
-//sdmmc
-//Reference to board-rk3028a-tb-sdmmc-config.c
-
-//keyboard
-//#define RK31XX_MAINBOARD_V1 //if mainboard is RK31XX_MAINBOARD_V1.0
-#define PLAY_ON_PIN RK30_PIN0_PD1 //wakeup key
-
-//pwm regulator
-#define REG_PWM 1 // (0 ~ 2)
-
-//pmic
-#define PMU_INT_PIN RK30_PIN3_PC6
-#define PMU_SLEEP_PIN RK30_PIN3_PC4
-
-//ion reserve memory
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-
-static int pwm_mode[] = {PWM0, PWM1, PWM2};
-static inline int rk_gpio_request(int gpio, int direction, int value, const char *label)
-{
- int ret = 0;
- unsigned long flags = 0;
-
- if(!gpio_is_valid(gpio))
- return 0;
-
- if(direction == GPIOF_DIR_IN)
- flags = GPIOF_IN;
- else if(value == GPIO_LOW)
- flags = GPIOF_OUT_INIT_LOW;
- else
- flags = GPIOF_OUT_INIT_HIGH;
-
- ret = gpio_request_one(gpio, flags, label);
- if(ret < 0)
- pr_err("Failed to request '%s'\n", label);
-
- return ret;
-}
-
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* touchscreen
-************************************************************/
-#if defined(CONFIG_TOUCHSCREEN_GSLX680_RK3028)
-//#define TOUCH_RESET_PIN RK30_PIN0_PC1
-//#define TOUCH_EN_PIN NULL
-//#define TOUCH_INT_PIN RK30_PIN0_PB4
-
- int gslx680_init_platform_hw(void)
- {
-
- if(gpio_request(TOUCH_RST_PIN,NULL) != 0){
- gpio_free(TOUCH_RST_PIN);
- printk("gslx680_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("gslx680_init_platform_hw gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RST_PIN, TOUCH_RST_VALUE);
- mdelay(10);
- gpio_set_value(TOUCH_RST_PIN,!TOUCH_RST_VALUE);
- mdelay(10);
- gpio_set_value(TOUCH_RST_PIN,TOUCH_RST_VALUE);
- msleep(300);
- return 0;
-
- }
-
- struct ts_hw_data gslx680_info = {
- .reset_gpio = TOUCH_RST_PIN,
- .touch_en_gpio = TOUCH_INT_PIN,
- .init_platform_hw = gslx680_init_platform_hw,
- };
-#endif
-
-
-#if defined(CONFIG_TOUCHSCREEN_GT8XX)
-static int goodix_init_platform_hw(void)
-{
- int ret = 0;
-
- ret = rk_gpio_request(TOUCH_PWR_PIN, GPIOF_DIR_OUT, TOUCH_PWR_VALUE, "touch_pwr");
- if(ret < 0)
- return ret;
- msleep(100);
-
- ret = rk_gpio_request(TOUCH_RST_PIN, GPIOF_DIR_OUT, TOUCH_RST_VALUE, "touch_rst");
- if(ret < 0)
- return ret;
- msleep(100);
-
- return 0;
-}
-
-struct goodix_platform_data goodix_info = {
- .model = 8105,
- .irq_pin = TOUCH_INT_PIN,
- .rest_pin = TOUCH_RST_PIN,
- .init_platform_hw = goodix_init_platform_hw,
-};
-#endif
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
-
- iomux_set(pwm_mode[BL_PWM]);
- msleep(50);
-#ifdef LCD_DISP_ON_PIN
- ret = rk_gpio_request(BL_EN_PIN, GPIOF_DIR_OUT, BL_EN_VALUE, "bl_en");
- if(ret < 0)
- return ret;
-#endif
- return 0;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int pwm_gpio;
-#ifdef LCD_DISP_ON_PIN
- gpio_free(BL_EN_PIN);
-#endif
- pwm_gpio = iomux_mode_to_gpio(pwm_mode[BL_PWM]);
- return rk_gpio_request(BL_EN_PIN, GPIOF_DIR_OUT, GPIO_LOW, "BL_PWM");
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret, pwm_gpio = iomux_mode_to_gpio(pwm_mode[BL_PWM]);
-
- ret = rk_gpio_request(pwm_gpio, GPIOF_DIR_OUT, GPIO_LOW, "BL_PWM");
- if(ret < 0)
- return ret;
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, !BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- int pwm_gpio = iomux_mode_to_gpio(pwm_mode[BL_PWM]);
-
- gpio_free(pwm_gpio);
- iomux_set(pwm_mode[BL_PWM]);
-#ifdef LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .pwm_id = BL_PWM,
- .min_brightness=60,
- .max_brightness=255,
- .brightness_mode = BRIGHTNESS_MODE_CONIC,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-#endif
-
-/***********************************************************
-* fb
-************************************************************/
-#ifdef CONFIG_FB_ROCKCHIP
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
-
- ret = rk_gpio_request(LCD_CS_PIN, GPIOF_DIR_OUT, LCD_CS_VALUE, "lcd_cs");
- if(ret < 0)
- return ret;
-
- return rk_gpio_request(LCD_EN_PIN, GPIOF_DIR_OUT, LCD_EN_VALUE, "lcd_en");
-}
-
-static int rk_fb_io_disable(void)
-{
- gpio_set_value(LCD_CS_PIN, !LCD_CS_VALUE);
- gpio_set_value(LCD_EN_PIN, !LCD_EN_VALUE);
-
- return 0;
-}
-
-static int rk_fb_io_enable(void)
-{
- gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE);
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
-
- return 0;
-}
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
-struct rk29fb_info lcdc0_screen_info = {
-#if defined(CONFIG_RK_HDMI) && defined(CONFIG_HDMI_SOURCE_LCDC0) && defined(CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL)
- .prop = EXTEND, //extend display device
- .io_init = NULL,
- .io_disable = NULL,
- .io_enable = NULL,
- .set_screen_info = hdmi_init_lcdc,
-#else
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-#endif
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
-struct rk29fb_info lcdc1_screen_info = {
-#if defined(CONFIG_RK_HDMI) && defined(CONFIG_HDMI_SOURCE_LCDC1) && defined(CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL)
- .prop = EXTEND, //extend display device
- .io_init = NULL,
- .io_disable = NULL,
- .io_enable = NULL,
- .set_screen_info = hdmi_init_lcdc,
-#else
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-#endif
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
-static struct resource resource_lcdc0[] = {
- [0] = {
- .name = "lcdc0 reg",
- .start = RK3026_LCDC0_PHYS,
- .end = RK3026_LCDC0_PHYS + RK3026_LCDC0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc0 irq",
- .start = IRQ_LCDC,
- .end = IRQ_LCDC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc0 = {
- .name = "rk30-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc0),
- .resource = resource_lcdc0,
- .dev = {
- .platform_data = &lcdc0_screen_info,
- },
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
-static struct resource resource_lcdc1[] = {
- [0] = {
- .name = "lcdc1 reg",
- .start = RK3026_LCDC1_PHYS,
- .end = RK3026_LCDC1_PHYS + RK3026_LCDC1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc1 irq",
- .start = IRQ_LCDC1,
- .end = IRQ_LCDC1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc1 = {
- .name = "rk30-lcdc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resource_lcdc1),
- .resource = resource_lcdc1,
- .dev = {
- .platform_data = &lcdc1_screen_info,
- },
-};
-#endif
-
-static int rk_platform_add_display_devices(void)
-{
- struct platform_device *fb = NULL; //fb
- struct platform_device *lcdc0 = NULL; //lcdc0
- struct platform_device *lcdc1 = NULL; //lcdc1
- struct platform_device *bl = NULL; //backlight
-#ifdef CONFIG_FB_ROCKCHIP
- fb = &device_fb;
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
- lcdc0 = &device_lcdc0,
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
- lcdc1 = &device_lcdc1,
-#endif
-
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- bl = &rk29_device_backlight,
-#endif
- __rk_platform_add_display_devices(fb,lcdc0,lcdc1,bl);
-
- return 0;
-}
-
-
-/***********************************************************
-* gsensor
-************************************************************/
-// mma 8452 gsensor
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN GS_INT_PIN
-static int mma8452_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data mma8452_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma8452_init_platform_hw,
- .orientation = {-1, 0, 0, 0, -1, 0, 0, 0, 1},
-};
-#endif
-
-// lsm303d gsensor
-#if defined (CONFIG_GS_LSM303D)
-#define LSM303D_INT_PIN GS_INT_PIN
-static int lms303d_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data lms303d_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lms303d_init_platform_hw,
- .orientation = {-1, 0, 0, 0, -1, 0, 0, 0, 1},
-};
-#endif
-
-
-/*MMA7660 gsensor*/
-#if defined (CONFIG_GS_MMA7660)
-#define MMA7660_INT_PIN GS_INT_PIN
-
-static int mma7660_init_platform_hw(void)
-{
- //rk30_mux_api_set(GPIO1B2_SPI_RXD_UART1_SIN_NAME, GPIO1B_GPIO1B2);
-
- return 0;
-}
-
-static struct sensor_platform_data mma7660_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma7660_init_platform_hw,
-#ifndef CONFIG_MFD_RK616
- #ifdef CONFIG_TOUCHSCREEN_GSLX680_RK3168
- .orientation = {-1, 0, 0, 0, -1, 0, 0, 0, 1},
- #else
- .orientation = {0, -1, 0, -1, 0, 0, 0, 0, -1},
- #endif
-#else
- .orientation = {1, 0, 0, 0, -1, 0, 0, 0, -1},
-#endif
-};
-#endif
-
-
-#if defined (CONFIG_GS_MXC6225)
-#define MXC6225_INT_PIN GS_INT_PIN
-
-static int mxc6225_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data mxc6225_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 0,
- .poll_delay_ms = 30,
- .init_platform_hw = mxc6225_init_platform_hw,
- .orientation = { 0, -1, 0, 1, 0, 0, 0, 0, 0},
-};
-#endif
-#if defined (CONFIG_GS_LIS3DH)
-#define LIS3DH_INT_PIN GS_INT_PIN
-
- static int lis3dh_init_platform_hw(void)
- {
-
- return 0;
- }
-
- static struct sensor_platform_data lis3dh_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lis3dh_init_platform_hw,
- .orientation = {1, 0, 0, 0, 1, 0, 0, 0, 1},
- };
-#endif
-
-#if defined (CONFIG_COMPASS_AK8975)
-static struct sensor_platform_data akm8975_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-#if defined (CONFIG_COMPASS_AK8963)
-static struct sensor_platform_data akm8963_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {0, 1, 0},
- {1, 0, 0},
- {0, 0, -1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {0, -1, 0},
- {-1, 0, 0},
- {0, 0, -1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-
-#if defined(CONFIG_GYRO_L3G4200D)
-
-#include <linux/l3g4200d.h>
-#define L3G4200D_INT_PIN RK30_PIN0_PB4
-
-static int l3g4200d_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data l3g4200d_info = {
- .type = SENSOR_TYPE_GYROSCOPE,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
- .init_platform_hw = l3g4200d_init_platform_hw,
- .x_min = 40,//x_min,y_min,z_min = (0-100) according to hardware
- .y_min = 40,
- .z_min = 20,
-};
-
-#endif
-
-#ifdef CONFIG_LS_CM3217
-static struct sensor_platform_data cm3217_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 0,
- .poll_delay_ms = 500,
-};
-
-#endif
-
-/***********************************************************
-* keyboard
-************************************************************/
-#include <plat/key.h>
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = PLAY_ON_PIN,
- .active_low = PRESS_LEV_LOW,
- .wakeup = 1,
- },
-/* disable adc keyboard,
- * because rk280a adc reference voltage is 3.3V, but
- * rk30xx mainbord key's supply voltage is 2.5V and
- * rk31xx mainbord key's supply voltage is 1.8V.
- */
- /*
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .gpio = INVALID_GPIO,
- .adc_value = 1,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .gpio = INVALID_GPIO,
- .adc_value = 512,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "menu",
- .code = EV_MENU,
- .adc_value = 133,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .code = KEY_HOME,
- .adc_value = 550,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .adc_value = 333,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "camera",
- .code = KEY_CAMERA,
- .adc_value = 742,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },*/
-
-};
-
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = 3, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
-/***********************************************************
-* sdmmc
-************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "board-rk3028a-86v-sdmmc-config.c"
-#include "../plat-rk/rk-sdmmc-ops.c"
-#include "../plat-rk/rk-sdmmc-wifi.c"
-#endif //endif ---#ifdef CONFIG_SDMMC_RK29
-
-#ifdef CONFIG_SDMMC0_RK29
-#define CONFIG_SDMMC0_USE_DMA
-static int rk29_sdmmc0_cfg_gpio(void)
-{
- rk29_sdmmc_set_iomux(0, 0xFFFF);
- #if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- iomux_set_gpio_mode(iomux_gpio_to_mode(RK29SDK_SD_CARD_DETECT_N));
- #else
- iomux_set(MMC0_DETN);
- #endif
-
- #if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
- #endif
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
- .set_iomux = rk29_sdmmc_set_iomux,
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) && defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- .status = rk29sdk_wifi_mmc0_status,
- .register_status_notify = rk29sdk_wifi_mmc0_status_register,
-#endif
-
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .power_en = RK29SDK_SD_CARD_PWR_EN,
- .power_en_level = RK29SDK_SD_CARD_PWR_EN_LEVEL,
-#else
- .power_en = INVALID_GPIO,
- .power_en_level = GPIO_LOW,
-#endif
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC0_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- .det_pin_info = {
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N, //INVALID_GPIO,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
- #endif
- },
-
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
- .set_iomux = rk29_sdmmc_set_iomux,
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC) || defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC1_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- #if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
- .sdio_INT_gpio = RK29SDK_WIFI_SDIO_CARD_INT,
- #endif
-
- .det_pin_info = {
- #if defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- #else
- .io = INVALID_GPIO,
- #endif
-
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
- #endif
- },
- .enable_sd_wakeup = 0,
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = RK30_PIN1_PB4,
- .batt_low_pin = INVALID_GPIO,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = RK30_PIN1_PA0,
- .usb_det_pin = INVALID_GPIO,
- .dc_det_level = GPIO_LOW,
- .charge_ok_level = GPIO_HIGH,
-
- .reference_voltage = 3300, // the rK2928 is 3300;RK3066 and rk29 are 2500;rk3066B is 1800;
- .pull_up_res = 200, //divider resistance , pull-up resistor
- .pull_down_res = 120, //divider resistance , pull-down resistor
-
- .is_reboot_charging = 1,
- .save_capacity = 1 ,
- .low_voltage_protection = 3600,
-};
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-
-
-/***********************************************************
-* rfkill
-************************************************************/
-#ifdef CONFIG_RFKILL_RK
-// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
-static struct rfkill_rk_platform_data rfkill_rk_platdata = {
- .type = RFKILL_TYPE_BLUETOOTH,
-
- .poweron_gpio = { // BT_REG_ON
- .io = INVALID_GPIO, //RK30_PIN3_PC7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_poweron",
- //.fgpio = GPIO3_C7,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN1_PB3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_reset",
- .fgpio = GPIO1_B3,
- },
- },
-
- .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
- .io = RK30_PIN1_PB2, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_wake",
- .fgpio = GPIO1_B2,
- },
- },
-
- .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .gpio = {
- .io = RK30_PIN0_PA4, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
- .iomux = {
- .name = "bt_wake_host",
- //.fgpio = GPIO0_A4,
- },
- },
- },
-
- .rts_gpio = { // UART_RTS, enable or disable BT's data coming
- .io = RK30_PIN1_PA3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_rts",
- .fgpio = GPIO1_A3,
- .fmux = UART0_RTSN,
- },
- }
-};
-
-static struct platform_device device_rfkill_rk = {
- .name = "rfkill_rk",
- .id = -1,
- .dev = {
- .platform_data = &rfkill_rk_platdata,
- },
-};
-#endif
-
-/***********************************************************
-* ion
-************************************************************/
-#ifdef CONFIG_ION
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-/***********************************************************
-* pwm regulator
-************************************************************/
-#ifdef CONFIG_RK30_PWM_REGULATOR
-static int pwm_voltage_map[] = {
- 800000, 825000, 850000, 875000, 900000, 925000 ,
- 950000, 975000, 1000000, 1025000, 1050000, 1075000,
- 1100000, 1125000, 1150000, 1175000, 1200000, 1225000,
- 1250000, 1275000, 1300000, 1325000, 1350000, 1375000
-};
-
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_core",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] = {
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
- .pwm_id = REG_PWM,
- .pwm_voltage = 1200000,
- .suspend_voltage = 1050000,
- .min_uV = 950000,
- .max_uV = 1400000,
- .coefficient = 504, //50.4%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-
-static void pwm_regulator_init(void)
-{
- pwm_regulator_info[0].pwm_gpio = iomux_mode_to_gpio(pwm_mode[REG_PWM]);
- pwm_regulator_info[0].pwm_iomux_pwm = pwm_mode[REG_PWM];
- pwm_regulator_info[0].pwm_iomux_gpio = iomux_switch_gpio_mode(pwm_mode[REG_PWM]);
-}
-#endif
-
-int __sramdata pwm_iomux, pwm_do, pwm_dir, pwm_en;
-#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
-
-#define GPIO0_D2_OFFSET 10
-void __sramfunc rk30_pwm_logic_suspend_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- #if 0
- /* pwm0: GPIO0_D2, pwm1: GPIO0_D3, pwm2: GPIO0_D4 */
- int off = GPIO0_D2_OFFSET + REG_PWM;
-
- sram_udelay(10000);
- pwm_iomux = grf_readl(GRF_GPIO0D_IOMUX);
- pwm_dir = grf_readl(GRF_GPIO0H_DIR);
- pwm_do = grf_readl(GRF_GPIO0H_DO);
- pwm__en = grf_readl(GRF_GPIO0H_EN);
-
- grf_writel((1<<(2 * off), GRF_GPIO0D_IOMUX);
- grf_writel((1<<(16 + off))|(1<<off), GRF_GPIO0H_DIR);
- grf_writel((1<<(16 + off))|(1<<off), GRF_GPIO0H_DO);
- #endif
-#endif
-}
-
-void __sramfunc rk30_pwm_logic_resume_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- #if 0
- /* pwm0: GPIO0_D2, pwm1: GPIO0_D3, pwm2: GPIO0_D4 */
- int off = GPIO0_D2_OFFSET + REG_PWM;
-
- grf_writel((1<<(2 * off))|pwm_iomux, GRF_GPIO0D_IOMUX);
- grf_writel(((1<<(16 + off))|pwm_dir), GRF_GPIO0L_DIR);
- grf_writel(((1<<(16 + off))|pwm_do), GRF_GPIO0L_DO);
- grf_writel(((1<<(16 + off))|pwm_en), GRF_GPIO0L_EN);
- sram_udelay(10000);
- #endif
-#endif
-}
-extern void pwm_suspend_voltage(void);
-extern void pwm_resume_voltage(void);
-
-void rk30_pwm_suspend_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_suspend_voltage();
-#endif
-}
-
-void rk30_pwm_resume_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_resume_voltage();
-#endif
-}
-
-/***********************************************************
-* pmic
-************************************************************/
-int __sramdata g_pmic_type = 0;
-
-#ifdef CONFIG_MFD_TPS65910
-#define TPS65910_HOST_IRQ PMU_INT_PIN
-#define PMU_POWER_SLEEP PMU_SLEEP_PIN
-static struct pmu_info tps65910_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1100000,
- .max_uv = 1100000,
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1100000,
- .max_uv = 1100000,
- },
- {
- .name = "vio", //vcc_io
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
-
-};
-static struct pmu_info tps65910_ldo_info[] = {
- /*{
- .name = "vpll", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- },*/
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 2800000,//1800000,
- .max_uv = 2800000,//1800000,
- },
- {
- .name = "vdig2", //vdd11
- .min_uv = 1100000,
- .max_uv = 1100000,
- },
- {
- .name = "vaux1", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "vaux2", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vaux33", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vmmc", //vcca30
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
- {
- .name = "vdac", //
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
-};
-#include "../mach-rk30/board-pmu-tps65910.c"
-#endif
-
-void __sramfunc board_pmu_suspend(void)
-{
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_suspend();
- #endif
-}
-
-void __sramfunc board_pmu_resume(void)
-{
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_resume();
- #endif
-}
-
-#ifdef CONFIG_SND_SOC_RK3026
-struct rk3026_codec_pdata rk3026_codec_pdata_info={
- .spk_ctl_gpio = RK2928_PIN3_PD4,
- .hp_ctl_gpio = RK2928_PIN3_PD4,
-};
-
-static struct resource resources_acodec[] = {
- {
- .start = RK2928_ACODEC_PHYS,
- .end = RK2928_ACODEC_PHYS + RK2928_ACODEC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device rk3026_codec = {
- .name = "rk3026-codec",
- .id = -1,
- .resource = resources_acodec,
- .dev = {
- .platform_data = &rk3026_codec_pdata_info,
- }
-};
-#endif
-#if defined(CONFIG_GPS_RK)
-#define GPS_OSCEN_PIN RK2928_PIN1_PB0
-#define GPS_RXEN_PIN RK2928_PIN1_PB0
-
-static int rk_gps_io_init(void)
-{
- printk("%s \n", __FUNCTION__);
-
- gpio_request(GPS_OSCEN_PIN, NULL);
- gpio_direction_output(GPS_OSCEN_PIN, GPIO_LOW);
-
- iomux_set(GPS_CLK);//GPS_CLK
- iomux_set(GPS_MAG);//GPS_MAG
- iomux_set(GPS_SIGN);//GPS_SIGN
-#if 0
- gpio_request(RK30_PIN1_PA6, NULL);
- gpio_direction_output(RK30_PIN1_PA6, GPIO_LOW);
-
- gpio_request(RK30_PIN1_PA5, NULL);
- gpio_direction_output(RK30_PIN1_PA5, GPIO_LOW);
-
- gpio_request(RK30_PIN1_PA7, NULL);
- gpio_direction_output(RK30_PIN1_PA7, GPIO_LOW);
-#endif
- return 0;
-}
-static int rk_gps_power_up(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-static int rk_gps_power_down(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-static int rk_gps_reset_set(int level)
-{
- return 0;
-}
-static int rk_enable_hclk_gps(void)
-{
- struct clk *gps_aclk = NULL;
- gps_aclk = clk_get(NULL, "aclk_gps");
- if(gps_aclk) {
- clk_enable(gps_aclk);
- clk_put(gps_aclk);
- printk("%s \n", __FUNCTION__);
- }
- else
- printk("get gps aclk fail\n");
- return 0;
-}
-static int rk_disable_hclk_gps(void)
-{
- struct clk *gps_aclk = NULL;
- gps_aclk = clk_get(NULL, "aclk_gps");
- if(gps_aclk) {
- //TO wait long enough until GPS ISR is finished.
- msleep(5);
- clk_disable(gps_aclk);
- clk_put(gps_aclk);
- printk("%s \n", __FUNCTION__);
- }
- else
- printk("get gps aclk fail\n");
- return 0;
-}
-static struct rk_gps_data rk_gps_info = {
- .io_init = rk_gps_io_init,
- .power_up = rk_gps_power_up,
- .power_down = rk_gps_power_down,
- .reset = rk_gps_reset_set,
- .enable_hclk_gps = rk_enable_hclk_gps,
- .disable_hclk_gps = rk_disable_hclk_gps,
- .GpsSign = RK2928_PIN1_PA5,
- .GpsMag = RK2928_PIN1_PA4, //GPIO index
- .GpsClk = RK2928_PIN1_PA2, //GPIO index
- .GpsVCCEn = GPS_OSCEN_PIN, //GPIO index
-#if 0
- .GpsSpi_CSO = RK30_PIN1_PA4, //GPIO index
- .GpsSpiClk = RK30_PIN1_PA5, //GPIO index
- .GpsSpiMOSI = RK30_PIN1_PA7, //GPIO index
-#endif
- .GpsIrq = IRQ_GPS,
- .GpsSpiEn = 0,
- .GpsAdcCh = 2,
- .u32GpsPhyAddr = RK2928_GPS_PHYS,
- .u32GpsPhySize = RK2928_GPS_SIZE,
-};
-
-static struct platform_device rk_device_gps = {
- .name = "gps_hv5820b",
- .id = -1,
- .dev = {
- .platform_data = &rk_gps_info,
- }
- };
-#endif
-
-
-/***********************************************************
-* i2c
-************************************************************/
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C1_RK30
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_GS_MXC6225)
- {
- .type = "gs_mxc6225",
- .addr = 0x15,
- .flags = 0,
- .irq = MXC6225_INT_PIN,
- .platform_data = &mxc6225_info,
- },
-#endif
-#if defined (CONFIG_GS_MMA7660)
- {
- .type = "gs_mma7660",//gs_mma7660
- .addr = 0x4c,
- .flags = 0,
- .irq = MMA7660_INT_PIN,
- .platform_data = &mma7660_info,
- },
-#endif
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1d,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_GS_LIS3DH)
- {
- .type = "gs_lis3dh",
- .addr = 0x19, //0x19(SA0-->VCC), 0x18(SA0-->GND)
- .flags = 0,
- .irq = LIS3DH_INT_PIN,
- .platform_data = &lis3dh_info,
- },
-#endif
-#if defined (CONFIG_GS_LSM303D)
- {
- .type = "gs_lsm303d",
- .addr = 0x1d, //0x19(SA0-->VCC), 0x18(SA0-->GND)
- .flags = 0,
- .irq = LSM303D_INT_PIN,
- .platform_data = &lms303d_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8975_info,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8975_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8963)
- {
- .type = "ak8963",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8963_info,
- },
-#endif
-#if defined (CONFIG_GYRO_L3G4200D)
- {
- .type = "l3g4200d_gryo",
- .addr = 0x69,
- .flags = 0,
- .irq = L3G4200D_INT_PIN,
- .platform_data = &l3g4200d_info,
- },
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-#if defined (CONFIG_TOUCHSCREEN_GT8XX)
- {
- .type = "Goodix-TS",
- .addr = 0x55,
- .flags = 0,
- .irq = TOUCH_INT_PIN,
- .platform_data = &goodix_info,
- },
-#endif
-#if defined (CONFIG_TOUCHSCREEN_GSLX680_RK3028)
- {
- .type = "gslX680",
- .addr = 0x40,
- .flags = 0,
- .platform_data =&gslx680_info,
- },
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO// RK30_PIN2_PD6 //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO//RK30_PIN2_PD7 //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- return 0;
-}
-
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(4, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-
-/***********************************************************
-* board init
-************************************************************/
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- &rk29sdk_wifi_device,
-#endif
-#ifdef CONFIG_RFKILL_RK
- &device_rfkill_rk,
-#endif
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
- &rk30_device_adc_battery,
-#endif
-#ifdef CONFIG_SND_SOC_RK3026
- &rk3026_codec,
-#endif
-#ifdef CONFIG_GPS_RK
- &rk_device_gps,
-#endif
-};
-
-static void rk30_pm_power_off(void)
-{
-#if defined(CONFIG_MFD_TPS65910)
- tps65910_device_shutdown();//tps65910 shutdown
-#endif
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
- while(1);
-}
-
-static void __init machine_rk30_board_init(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_regulator_init();
-#endif
- avs_init();
- pm_power_off = rk30_pm_power_off;
- rk_gpio_request(POWER_ON_PIN, GPIOF_DIR_OUT, GPIO_HIGH, "system power on");
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- rk_platform_add_display_devices();
-#if defined(CONFIG_WIFI_CONTROL_FUNC)
- rk29sdk_wifi_bt_gpio_control_init();
-#elif defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- rk29sdk_wifi_combo_module_gpio_init();
-#endif
-}
-
-static void __init rk30_reserve(void)
-{
- //fb reserve
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0 buf", get_fb_size());
- resource_fb[0].end = resource_fb[0].start + get_fb_size()- 1;
- #if 0
- resource_fb[1].start = board_mem_reserve_add("ipp buf", RK30_FB0_MEM_SIZE);
- resource_fb[1].end = resource_fb[1].start + RK30_FB0_MEM_SIZE - 1;
- #endif
-
- #if defined(CONFIG_FB_ROTATE) || !defined(CONFIG_THREE_FB_BUFFER)
- resource_fb[2].start = board_mem_reserve_add("fb2 buf",get_fb_size());
- resource_fb[2].end = resource_fb[2].start + get_fb_size() - 1;
- #endif
-#endif
- //ion reserve
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
-#ifdef CONFIG_GPS_RK
- //it must be more than 8MB
- rk_gps_info.u32MemoryPhyAddr = board_mem_reserve_add("gps", SZ_8M);
-#endif
- board_mem_reserved();
-}
-
-/***********************************************************
-* clock
-************************************************************/
-static struct cpufreq_frequency_table dvfs_arm_table[] = {
- {.frequency = 312 * 1000, .index = 1100 * 1000},
- {.frequency = 504 * 1000, .index = 1100 * 1000},
- {.frequency = 816 * 1000, .index = 1150 * 1000},
- {.frequency = 1008 * 1000, .index = 1200 * 1000},
- //{.frequency = 1200 * 1000, .index = 1300 * 1000},
- //{.frequency = 1416 * 1000, .index = 1200 * 1000},
- //{.frequency = 1608 * 1000, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- //{.frequency = 100 * 1000, .index = 1200 * 1000},
- {.frequency = 200 * 1000, .index = 1200 * 1000},
- //{.frequency = 266 * 1000, .index = 1200 * 1000},
- //{.frequency = 300 * 1000, .index = 1200 * 1000},
- //{.frequency = 400 * 1000, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- //{.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 1200 * 1000},
- //{.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = 1200 * 1000},
- {.frequency = 360 * 1000 + DDR_FREQ_NORMAL, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-void __init board_clock_init(void)
-{
- rk2928_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
- //dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "cpu"), dvfs_arm_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
-}
-
-/************************ end *****************************/
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk2928_fixup,
- .reserve = &rk30_reserve,
- .map_io = rk2928_map_io,
- .init_irq = rk2928_init_irq,
- .timer = &rk2928_timer,
- .init_machine = machine_rk30_board_init,
-MACHINE_END
+++ /dev/null
-/*****************************************************************************************
- * arch/arm/mach-rkxx/baord-xxx-sdmmc-config.c
- *
- * Copyright (C) 2013 ROCKCHIP, Inc.
- *
- * Description:
- * define the gpio for SD-MMC-SDIO-Wifi functions according to your own projects.
- *
- * Author: Michael Xie
- * 15 Jan,2013
- * E-mail: xbw@rock-chips.com
- *
- ******************************************************************************************/
-
-/*
-** If you select the macro of CONFIG_SDMMC0_RK29_WRITE_PROTECT, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define SDMMC0_WRITE_PROTECT_PIN RK30_PIN3_PB2 //According to your own project to set the value of write-protect-pin.
-//#define SDMMC0_WRITE_PROTECT_ENABLE_VALUE GPIO_HIGH
-
-/*
-** If you select the macro of CONFIG_SDMMC1_RK29_WRITE_PROTECT, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define SDMMC1_WRITE_PROTECT_PIN RK30_PIN3_PB3 //According to your own project to set the value of write-protect-pin.
-//#define SDMMC1_WRITE_PROTECT_ENABLE_VALUE GPIO_HIGH
-
-/*
-** If you select the macro of CONFIG_RK29_SDIO_IRQ_FROM_GPIO, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define RK29SDK_WIFI_SDIO_CARD_INT RK30_PIN3_PD2
-
-
-/*
-* define sdcard PowerEn-pin
-*/
-#define RK29SDK_SD_CARD_PWR_EN RK30_PIN1_PB6
-#define RK29SDK_SD_CARD_PWR_EN_LEVEL GPIO_LOW
-int rk31sdk_get_sdmmc0_pin_io_voltage(void)
-{
- int voltage;
-#define RK31SDK_SET_SDMMC0_PIN_VOLTAGE
-
- /**************************************************************************************
- ** Please tell me how much voltage of your SDMMC0-pin in your project.
- **
- ** ÀýÈç: ÓеÄÏîÄ¿£¬ËüµÄSDMMC0ËùÔÚµÄRKÖ÷¿ØµÄIO×飬ÏëÓÃ1.8V, ¶ø¿¨±¾ÉíÓÃ3.3V,
- ** ¶øÖмäͨ¹ý¸öµçƽת»».ÄÇô£¬Äú´Ëʱ£¬Ó¦¸ÃÉèÖÃÏÂÃæµÄvoltageֵΪ 1.8V(¼´1800mv)
- ***************************************************************************************/
- voltage = 3300; //default the voltage 3300mv.
-
- return voltage;
-}
-
-/*
-* define the card-detect-pin.
-*/
-#define RK29SDK_SD_CARD_DETECT_N RK30_PIN1_PC1 //According to your own project to set the value of card-detect-pin.
-#define RK29SDK_SD_CARD_INSERT_LEVEL GPIO_LOW // set the voltage of insert-card. Please pay attention to the default setting.
-
-/*
-* Define wifi module's power and reset gpio, and gpio sensitive level.
-* Please set the value according to your own project.
-*
-* Well, you just own engineering module to set the value in the corresponding module branch.
-* Otherwise, you do not define this macro, eliminate it.
-*
-*/
-#if defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU)
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_LOW//GPIO_HIGH
-
-#elif defined(CONFIG_BCM4330) || defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319) || defined(CONFIG_RK903) || defined(CONFIG_RK901)
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN0_PD6
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PC2
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
-
-#elif defined(CONFIG_MT5931_MT6622) || defined(CONFIG_MT5931)
-
- #ifdef CONFIG_MACH_RK3168_LR097
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- //#define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- //#define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
-
- #else
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN0_PA5
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #endif
-
-#elif defined(CONFIG_MT6620)
- #define COMBO_MODULE_MT6620_CDT 1 // to control antsel2,antsel3 and gps_lan foot when using AcSip or Cdtech chip.
- //- 1--use Cdtech chip; 0--unuse CDT chip
-
- //power, PMU_EN
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PC7
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- //reset, DAIRST,SYSRST_B
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- //VDDIO
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL RK30_PIN0_PD2 //You do not get control of the foot, and you do not need to define the macro
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_ENABLE_VALUE GPIO_HIGH
- //WIFI_INT_B
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
- //BGF_INT_B
- #define RK30SDK_WIFI_GPIO_BGF_INT_B RK30_PIN6_PA7
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_ENABLE_VALUE GPIO_HIGH
- //GPS_SYNC
- #define RK30SDK_WIFI_GPIO_GPS_SYNC RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_ENABLE_VALUE GPIO_HIGH
-
- #if COMBO_MODULE_MT6620_CDT
- //ANTSEL2
- #define RK30SDK_WIFI_GPIO_ANTSEL2 RK30_PIN4_PD4
- #define RK30SDK_WIFI_GPIO_ANTSEL2_ENABLE_VALUE GPIO_LOW //use 6620 in CDT chip, LOW--work; High--no work.
- //ANTSEL3
- #define RK30SDK_WIFI_GPIO_ANTSEL3 RK30_PIN4_PD3
- #define RK30SDK_WIFI_GPIO_ANTSEL3_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- //GPS_LAN
- #define RK30SDK_WIFI_GPIO_GPS_LAN RK30_PIN4_PD6
- #define RK30SDK_WIFI_GPIO_GPS_LAN_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- #endif // #if COMBO_MODULE_MT6620_CDT--#endif
-#endif
-
-#ifndef RK30SDK_WIFI_GPIO_WIFI_INT_B
-#define RK30SDK_WIFI_GPIO_WIFI_INT_B INVALID_GPIO
-#define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
-#endif
-
-int rk31sdk_get_sdio_wifi_voltage(void)
-{
- int voltage;
-
- /******************************************************************************
- ** Please tell me how much wifi-module uses voltage in your project.
- ******************************************************************************/
-#if defined(CONFIG_BCM4330) || defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319) || defined(CONFIG_RK903) || defined(CONFIG_RK901)
- voltage = 1800 ; //power 1800mV
-
-#elif defined(CONFIG_MT5931_MT6622)||defined(CONFIG_MT5931)
- voltage = 1800 ; //power 1800V
-#elif defined(CONFIG_MT6620)
- voltage = 2800 ; //power 2800V
-#elif defined(CONFIG_RDA5990)||defined(CONFIG_RTL8723AS)
- voltage = 3300 ; //power 3300V
-#else
- //default, sdio use 3.0V
- voltage = 3000 ; //power 3000V
-#endif
-
- return voltage;
-}
-
-
-
+++ /dev/null
-/*
- * Copyright (C) 2013 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <linux/rk_fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/mfd/tps65910.h>
-#include <linux/regulator/act8846.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/dvfs.h>
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-
-#ifdef CONFIG_SND_SOC_RK3026
-#include "../../../sound/soc/codecs/rk3026_codec.h"
-#endif
-
-#if defined(CONFIG_RK_HDMI)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#if defined(CONFIG_GPS_RK)
-#include "../../../drivers/misc/gps/rk_gps/rk_gps.h"
-#endif
-
-#include "board-rk3026-tb-camera.c"
-
-/***********************************************************
-* board config
-************************************************************/
-//system power on
-#define POWER_ON_PIN RK30_PIN1_PA1 //PWR_HOLD
-
-//touchscreen
-#define TOUCH_RST_PIN RK30_PIN3_PC3
-#define TOUCH_RST_VALUE GPIO_HIGH
-#define TOUCH_PWR_PIN RK30_PIN2_PD0
-#define TOUCH_PWR_VALUE GPIO_LOW
-#define TOUCH_INT_PIN RK30_PIN3_PC7
-
-//backlight
-#define LCD_DISP_ON_PIN
-#define BL_PWM 0 // (0 ~ 2)
-#define PWM_EFFECT_VALUE 1
-#define BL_EN_PIN RK30_PIN3_PC5
-#define BL_EN_VALUE GPIO_HIGH
-
-//fb
-#define LCD_EN_PIN RK30_PIN3_PD2
-#define LCD_EN_VALUE GPIO_HIGH
-#define LCD_CS_PIN INVALID_GPIO
-#define LCD_CS_VALUE GPIO_HIGH
-
-//gsensor
-#define GS_INT_PIN RK30_PIN3_PD1
-
-//sdmmc
-//Reference to board-rk3028a-tb-sdmmc-config.c
-
-//keyboard
-//#define RK31XX_MAINBOARD_V1 //if mainboard is RK31XX_MAINBOARD_V1.0
-#define PLAY_ON_PIN RK30_PIN0_PD1 //wakeup key
-
-//pwm regulator
-#define REG_PWM 2 // (0 ~ 2)
-
-//pmic
-#define PMU_INT_PIN RK30_PIN3_PC6
-#define PMU_SLEEP_PIN RK30_PIN0_PD0
-
-//ion reserve memory
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-
-static int pwm_mode[] = {PWM0, PWM1, PWM2};
-static inline int rk_gpio_request(int gpio, int direction, int value, const char *label)
-{
- int ret = 0;
- unsigned long flags = 0;
-
- if(!gpio_is_valid(gpio))
- return 0;
-
- if(direction == GPIOF_DIR_IN)
- flags = GPIOF_IN;
- else if(value == GPIO_LOW)
- flags = GPIOF_OUT_INIT_LOW;
- else
- flags = GPIOF_OUT_INIT_HIGH;
-
- ret = gpio_request_one(gpio, flags, label);
- if(ret < 0)
- pr_err("Failed to request '%s'\n", label);
-
- return ret;
-}
-
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* touchscreen
-************************************************************/
-#if defined(CONFIG_TOUCHSCREEN_GT8XX)
-static int goodix_init_platform_hw(void)
-{
- int ret = 0;
-
- ret = rk_gpio_request(TOUCH_PWR_PIN, GPIOF_DIR_OUT, TOUCH_PWR_VALUE, "touch_pwr");
- if(ret < 0)
- return ret;
- msleep(100);
-
- ret = rk_gpio_request(TOUCH_RST_PIN, GPIOF_DIR_OUT, TOUCH_RST_VALUE, "touch_rst");
- if(ret < 0)
- return ret;
- msleep(100);
-
- return 0;
-}
-
-struct goodix_platform_data goodix_info = {
- .model = 8105,
- .irq_pin = TOUCH_INT_PIN,
- .rest_pin = TOUCH_RST_PIN,
- .init_platform_hw = goodix_init_platform_hw,
-};
-#endif
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
-
- iomux_set(pwm_mode[BL_PWM]);
-#ifdef LCD_DISP_ON_PIN
- ret = rk_gpio_request(BL_EN_PIN, GPIOF_DIR_OUT, BL_EN_VALUE, "bl_en");
- if(ret < 0)
- return ret;
-#endif
- return 0;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int pwm_gpio;
-#ifdef LCD_DISP_ON_PIN
- gpio_free(BL_EN_PIN);
-#endif
- pwm_gpio = iomux_mode_to_gpio(pwm_mode[BL_PWM]);
- return rk_gpio_request(BL_EN_PIN, GPIOF_DIR_OUT, GPIO_LOW, "BL_PWM");
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret, pwm_gpio = iomux_mode_to_gpio(pwm_mode[BL_PWM]);
-
- ret = rk_gpio_request(pwm_gpio, GPIOF_DIR_OUT, GPIO_LOW, "BL_PWM");
- if(ret < 0)
- return ret;
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, !BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- int pwm_gpio = iomux_mode_to_gpio(pwm_mode[BL_PWM]);
-
- gpio_free(pwm_gpio);
- iomux_set(pwm_mode[BL_PWM]);
-#ifdef LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .pwm_id = BL_PWM,
- .min_brightness=20,
- .max_brightness=255,
- .brightness_mode = BRIGHTNESS_MODE_CONIC,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-#endif
-
-/***********************************************************
-* fb
-************************************************************/
-#ifdef CONFIG_FB_ROCKCHIP
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
-
- ret = rk_gpio_request(LCD_CS_PIN, GPIOF_DIR_OUT, LCD_CS_VALUE, "lcd_cs");
- if(ret < 0)
- return ret;
-
- return rk_gpio_request(LCD_EN_PIN, GPIOF_DIR_OUT, LCD_EN_VALUE, "lcd_en");
-}
-
-static int rk_fb_io_disable(void)
-{
- gpio_set_value(LCD_CS_PIN, !LCD_CS_VALUE);
- gpio_set_value(LCD_EN_PIN, !LCD_EN_VALUE);
-
- return 0;
-}
-
-static int rk_fb_io_enable(void)
-{
- gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE);
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
-
- return 0;
-}
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
-struct rk29fb_info lcdc0_screen_info = {
-#if defined(CONFIG_RK_HDMI) && defined(CONFIG_HDMI_SOURCE_LCDC0) && defined(CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL)
- .prop = EXTEND, //extend display device
- .io_init = NULL,
- .io_disable = NULL,
- .io_enable = NULL,
- .set_screen_info = hdmi_init_lcdc,
-#else
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-#endif
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
-struct rk29fb_info lcdc1_screen_info = {
-#if defined(CONFIG_RK_HDMI) && defined(CONFIG_HDMI_SOURCE_LCDC1) && defined(CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL)
- .prop = EXTEND, //extend display device
- .io_init = NULL,
- .io_disable = NULL,
- .io_enable = NULL,
- .set_screen_info = hdmi_init_lcdc,
-#else
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-#endif
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
-static struct resource resource_lcdc0[] = {
- [0] = {
- .name = "lcdc0 reg",
- .start = RK3026_LCDC0_PHYS,
- .end = RK3026_LCDC0_PHYS + RK3026_LCDC0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc0 irq",
- .start = IRQ_LCDC,
- .end = IRQ_LCDC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc0 = {
- .name = "rk30-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc0),
- .resource = resource_lcdc0,
- .dev = {
- .platform_data = &lcdc0_screen_info,
- },
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
-static struct resource resource_lcdc1[] = {
- [0] = {
- .name = "lcdc1 reg",
- .start = RK3026_LCDC1_PHYS,
- .end = RK3026_LCDC1_PHYS + RK3026_LCDC1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc1 irq",
- .start = IRQ_LCDC1,
- .end = IRQ_LCDC1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc1 = {
- .name = "rk30-lcdc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resource_lcdc1),
- .resource = resource_lcdc1,
- .dev = {
- .platform_data = &lcdc1_screen_info,
- },
-};
-#endif
-
-static int rk_platform_add_display_devices(void)
-{
- struct platform_device *fb = NULL; //fb
- struct platform_device *lcdc0 = NULL; //lcdc0
- struct platform_device *lcdc1 = NULL; //lcdc1
- struct platform_device *bl = NULL; //backlight
-#ifdef CONFIG_FB_ROCKCHIP
- fb = &device_fb;
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
- lcdc0 = &device_lcdc0,
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
- lcdc1 = &device_lcdc1,
-#endif
-
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- bl = &rk29_device_backlight,
-#endif
- __rk_platform_add_display_devices(fb,lcdc0,lcdc1,bl);
-
- return 0;
-}
-
-
-/***********************************************************
-* gsensor
-************************************************************/
-#if defined (CONFIG_GS_MMA8452)
-static int mma8452_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data mma8452_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma8452_init_platform_hw,
- .orientation = {-1, 0, 0, 0, -1, 0, 0, 0, 1},
-};
-#endif
-#if defined (CONFIG_GS_LIS3DH)
-static int lis3dh_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data lis3dh_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lis3dh_init_platform_hw,
- .orientation = {-1, 0, 0, 0, -1, 0, 0, 0, 1},
-};
-#endif
-
-/***********************************************************
-* keyboard
-************************************************************/
-#include <plat/key.h>
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = PLAY_ON_PIN,
- .active_low = PRESS_LEV_LOW,
- .wakeup = 1,
- },
-/* disable adc keyboard,
- * because rk280a adc reference voltage is 3.3V, but
- * rk30xx mainbord key's supply voltage is 2.5V and
- * rk31xx mainbord key's supply voltage is 1.8V.
- */
-#if 0
-#ifdef RK31XX_MAINBOARD_V1
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .adc_value = 744,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = PLAY_ON_PIN,
- .active_low = PRESS_LEV_LOW,
- .wakeup = 1,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .adc_value = 558,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "menu",
- .code = EV_MENU,
- .adc_value = 1,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .adc_value = 354,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .adc_value = 169,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-#else
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .adc_value = 900,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = PLAY_ON_PIN,
- .active_low = PRESS_LEV_LOW,
- .wakeup = 1,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .adc_value = 1,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "menu",
- .code = EV_MENU,
- .adc_value = 133,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .adc_value = 550,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .adc_value = 333,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "camera",
- .code = KEY_CAMERA,
- .adc_value = 742,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-#endif
-#endif
-};
-
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = 1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
-/***********************************************************
-* sdmmc
-************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "board-rk3028a-tb-sdmmc-config.c"
-#include "../plat-rk/rk-sdmmc-ops.c"
-#include "../plat-rk/rk-sdmmc-wifi.c"
-#endif //endif ---#ifdef CONFIG_SDMMC_RK29
-
-#ifdef CONFIG_SDMMC0_RK29
-#define CONFIG_SDMMC0_USE_DMA
-static int rk29_sdmmc0_cfg_gpio(void)
-{
- rk29_sdmmc_set_iomux(0, 0xFFFF);
- #if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- iomux_set_gpio_mode(iomux_gpio_to_mode(RK29SDK_SD_CARD_DETECT_N));
- #else
- iomux_set(MMC0_DETN);
- #endif
-
- #if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
- #endif
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
- .set_iomux = rk29_sdmmc_set_iomux,
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) && defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- .status = rk29sdk_wifi_mmc0_status,
- .register_status_notify = rk29sdk_wifi_mmc0_status_register,
-#endif
-
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .power_en = RK29SDK_SD_CARD_PWR_EN,
- .power_en_level = RK29SDK_SD_CARD_PWR_EN_LEVEL,
-#else
- .power_en = INVALID_GPIO,
- .power_en_level = GPIO_LOW,
-#endif
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC0_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- .det_pin_info = {
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N, //INVALID_GPIO,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
- #endif
- },
-
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
- .set_iomux = rk29_sdmmc_set_iomux,
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC) || defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC1_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- #if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
- .sdio_INT_gpio = RK29SDK_WIFI_SDIO_CARD_INT,
- #endif
-
- .det_pin_info = {
- #if defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- #else
- .io = INVALID_GPIO,
- #endif
-
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
- #endif
- },
- .enable_sd_wakeup = 0,
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-/***********************************************************
-* rfkill
-************************************************************/
-#ifdef CONFIG_RFKILL_RK
-// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
-static struct rfkill_rk_platform_data rfkill_rk_platdata = {
- .type = RFKILL_TYPE_BLUETOOTH,
-
- .poweron_gpio = { // BT_REG_ON
- .io = INVALID_GPIO, //RK30_PIN3_PC7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_poweron",
- //.fgpio = GPIO3_C7,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN3_PD5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_reset",
- //.fgpio = GPIO3_D5,
- },
- },
-
- .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
- .io = RK30_PIN0_PC6, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_wake",
- //.fgpio = GPIO0_C6,
- },
- },
-
- .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .gpio = {
- .io = RK30_PIN0_PC5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
- .iomux = {
- .name = "bt_wake_host",
- //.fgpio = GPIO0_C5,
- },
- },
- },
-
- .rts_gpio = { // UART_RTS, enable or disable BT's data coming
- .io = RK30_PIN0_PC3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_rts",
- .fgpio = GPIO0_C3,
- .fmux = UART0_RTSN,
- },
- }
-};
-
-static struct platform_device device_rfkill_rk = {
- .name = "rfkill_rk",
- .id = -1,
- .dev = {
- .platform_data = &rfkill_rk_platdata,
- },
-};
-#endif
-
-/***********************************************************
-* ion
-************************************************************/
-#ifdef CONFIG_ION
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_SND_SOC_RK3026
-struct rk3026_codec_pdata rk3026_codec_pdata_info={
- .spk_ctl_gpio = INVALID_GPIO,
- .hp_ctl_gpio = RK2928_PIN3_PD4,
- .delay_time = 10,
- };
-
-static struct resource resources_acodec[] = {
- {
- .start = RK2928_ACODEC_PHYS,
- .end = RK2928_ACODEC_PHYS + RK2928_ACODEC_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device rk3026_codec = {
- .name = "rk3026-codec",
- .id = -1,
- .resource = resources_acodec,
- .dev = {
- .platform_data = &rk3026_codec_pdata_info,
- }
- };
-#endif
-
-/***********************************************************
-* pwm regulator
-************************************************************/
-#ifdef CONFIG_RK30_PWM_REGULATOR
-static int pwm_voltage_map[] = {
- 800000, 825000, 850000, 875000, 900000, 925000 ,
- 950000, 975000, 1000000, 1025000, 1050000, 1075000,
- 1100000, 1125000, 1150000, 1175000, 1200000, 1225000,
- 1250000, 1275000, 1300000, 1325000, 1350000, 1375000
-};
-
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_core",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] = {
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
- .pwm_id = REG_PWM,
- .pwm_voltage = 1200000,
- .suspend_voltage = 1050000,
- .min_uV = 950000,
- .max_uV = 1400000,
- .coefficient = 504, //50.4%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-
-static void pwm_regulator_init(void)
-{
- pwm_regulator_info[0].pwm_gpio = iomux_mode_to_gpio(pwm_mode[REG_PWM]);
- pwm_regulator_info[0].pwm_iomux_pwm = pwm_mode[REG_PWM];
- pwm_regulator_info[0].pwm_iomux_gpio = iomux_switch_gpio_mode(pwm_mode[REG_PWM]);
-}
-#endif
-
-int __sramdata pwm_iomux, pwm_do, pwm_dir, pwm_en;
-#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
-
-#define GPIO0_D2_OFFSET 10
-void __sramfunc rk30_pwm_logic_suspend_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- #if 0
- /* pwm0: GPIO0_D2, pwm1: GPIO0_D3, pwm2: GPIO0_D4 */
- int off = GPIO0_D2_OFFSET + REG_PWM;
-
- sram_udelay(10000);
- pwm_iomux = grf_readl(GRF_GPIO0D_IOMUX);
- pwm_dir = grf_readl(GRF_GPIO0H_DIR);
- pwm_do = grf_readl(GRF_GPIO0H_DO);
- pwm__en = grf_readl(GRF_GPIO0H_EN);
-
- grf_writel((1<<(2 * off), GRF_GPIO0D_IOMUX);
- grf_writel((1<<(16 + off))|(1<<off), GRF_GPIO0H_DIR);
- grf_writel((1<<(16 + off))|(1<<off), GRF_GPIO0H_DO);
- #endif
-#endif
-}
-
-void __sramfunc rk30_pwm_logic_resume_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- #if 0
- /* pwm0: GPIO0_D2, pwm1: GPIO0_D3, pwm2: GPIO0_D4 */
- int off = GPIO0_D2_OFFSET + REG_PWM;
-
- grf_writel((1<<(2 * off))|pwm_iomux, GRF_GPIO0D_IOMUX);
- grf_writel(((1<<(16 + off))|pwm_dir), GRF_GPIO0L_DIR);
- grf_writel(((1<<(16 + off))|pwm_do), GRF_GPIO0L_DO);
- grf_writel(((1<<(16 + off))|pwm_en), GRF_GPIO0L_EN);
- sram_udelay(10000);
- #endif
-#endif
-}
-extern void pwm_suspend_voltage(void);
-extern void pwm_resume_voltage(void);
-
-void rk30_pwm_suspend_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_suspend_voltage();
-#endif
-}
-
-void rk30_pwm_resume_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_resume_voltage();
-#endif
-}
-
-/***********************************************************
-* pmic
-************************************************************/
-int __sramdata g_pmic_type = 0;
-
-#ifdef CONFIG_MFD_TPS65910
-#define TPS65910_HOST_IRQ PMU_INT_PIN
-#define PMU_POWER_SLEEP PMU_SLEEP_PIN
-static struct pmu_info tps65910_dcdc_info[] = {
- {
- .name = "vdd_cpu",
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vdd2",
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vio",
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
-};
-
-static struct pmu_info tps65910_ldo_info[] = {
- {
- .name = "vpll", //vcc25
- .min_uv = 2500000,
- .max_uv = 2500000,
- },
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 2800000,//1800000,
- .max_uv = 2800000,//1800000,
- },
-
- {
- .name = "vdig2", //vdd11
- .min_uv = 1100000,
- .max_uv = 1100000,
- },
- {
- .name = "vaux1", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "vaux2", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vaux33", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vmmc", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "vdac", //
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
-};
-#include "../mach-rk30/board-pmu-tps65910.c"
-#endif
-
-void __sramfunc board_pmu_suspend(void)
-{
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_suspend();
- #endif
-}
-
-void __sramfunc board_pmu_resume(void)
-{
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_resume();
- #endif
-}
-
-#if defined(CONFIG_GPS_RK)
-#define GPS_OSCEN_PIN RK2928_PIN1_PB0
-#define GPS_RXEN_PIN RK2928_PIN1_PB0
-
-static int rk_gps_io_init(void)
-{
- printk("%s \n", __FUNCTION__);
-
- gpio_request(GPS_OSCEN_PIN, NULL);
- gpio_direction_output(GPS_OSCEN_PIN, GPIO_LOW);
-
- iomux_set(GPS_CLK);//GPS_CLK
- iomux_set(GPS_MAG);//GPS_MAG
- iomux_set(GPS_SIGN);//GPS_SIGN
-#if 0
- gpio_request(RK30_PIN1_PA6, NULL);
- gpio_direction_output(RK30_PIN1_PA6, GPIO_LOW);
-
- gpio_request(RK30_PIN1_PA5, NULL);
- gpio_direction_output(RK30_PIN1_PA5, GPIO_LOW);
-
- gpio_request(RK30_PIN1_PA7, NULL);
- gpio_direction_output(RK30_PIN1_PA7, GPIO_LOW);
-#endif
- return 0;
-}
-static int rk_gps_power_up(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-static int rk_gps_power_down(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-static int rk_gps_reset_set(int level)
-{
- return 0;
-}
-static int rk_enable_hclk_gps(void)
-{
- struct clk *gps_aclk = NULL;
- gps_aclk = clk_get(NULL, "aclk_gps");
- if(gps_aclk) {
- clk_enable(gps_aclk);
- clk_put(gps_aclk);
- printk("%s \n", __FUNCTION__);
- }
- else
- printk("get gps aclk fail\n");
- return 0;
-}
-static int rk_disable_hclk_gps(void)
-{
- struct clk *gps_aclk = NULL;
- gps_aclk = clk_get(NULL, "aclk_gps");
- if(gps_aclk) {
- //TO wait long enough until GPS ISR is finished.
- msleep(5);
- clk_disable(gps_aclk);
- clk_put(gps_aclk);
- printk("%s \n", __FUNCTION__);
- }
- else
- printk("get gps aclk fail\n");
- return 0;
-}
-static struct rk_gps_data rk_gps_info = {
- .io_init = rk_gps_io_init,
- .power_up = rk_gps_power_up,
- .power_down = rk_gps_power_down,
- .reset = rk_gps_reset_set,
- .enable_hclk_gps = rk_enable_hclk_gps,
- .disable_hclk_gps = rk_disable_hclk_gps,
- .GpsSign = RK2928_PIN1_PA5,
- .GpsMag = RK2928_PIN1_PA4, //GPIO index
- .GpsClk = RK2928_PIN1_PA2, //GPIO index
- .GpsVCCEn = GPS_OSCEN_PIN, //GPIO index
-#if 0
- .GpsSpi_CSO = RK30_PIN1_PA4, //GPIO index
- .GpsSpiClk = RK30_PIN1_PA5, //GPIO index
- .GpsSpiMOSI = RK30_PIN1_PA7, //GPIO index
-#endif
- .GpsIrq = IRQ_GPS,
- .GpsSpiEn = 0,
- .GpsAdcCh = 2,
- .u32GpsPhyAddr = RK2928_GPS_PHYS,
- .u32GpsPhySize = RK2928_GPS_SIZE,
-};
-
-static struct platform_device rk_device_gps = {
- .name = "gps_hv5820b",
- .id = -1,
- .dev = {
- .platform_data = &rk_gps_info,
- }
- };
-#endif
-
-
-/***********************************************************
-* i2c
-************************************************************/
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1d,
- .flags = 0,
- .irq = GS_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_GS_LIS3DH)
- {
- .type = "gs_lis3dh",
- .addr = 0x19, //0x19(SA0-->VCC), 0x18(SA0-->GND)
- .flags = 0,
- .irq = GS_INT_PIN,
- .platform_data = &lis3dh_info,
- },
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C1_RK30
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-#if defined (CONFIG_TOUCHSCREEN_GT8XX)
- {
- .type = "Goodix-TS",
- .addr = 0x55,
- .flags = 0,
- .irq = TOUCH_INT_PIN,
- .platform_data = &goodix_info,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO// RK30_PIN2_PD6 //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO//RK30_PIN2_PD7 //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- return 0;
-}
-
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(4, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-
-/***********************************************************
-* board init
-************************************************************/
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- &rk29sdk_wifi_device,
-#endif
-#ifdef CONFIG_RFKILL_RK
- &device_rfkill_rk,
-#endif
-#ifdef CONFIG_SND_SOC_RK3026
- &rk3026_codec,
-#endif
-#ifdef CONFIG_GPS_RK
- &rk_device_gps,
-#endif
-};
-
-static void rk30_pm_power_off(void)
-{
-#if defined(CONFIG_MFD_TPS65910)
- tps65910_device_shutdown();//tps65910 shutdown
-#endif
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
- while(1);
-}
-
-static void __init machine_rk30_board_init(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_regulator_init();
-#endif
- avs_init();
- pm_power_off = rk30_pm_power_off;
- rk_gpio_request(POWER_ON_PIN, GPIOF_DIR_OUT, GPIO_HIGH, "system power on");
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- rk_platform_add_display_devices();
-#if defined(CONFIG_WIFI_CONTROL_FUNC)
- rk29sdk_wifi_bt_gpio_control_init();
-#elif defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- rk29sdk_wifi_combo_module_gpio_init();
-#endif
-}
-
-static void __init rk30_reserve(void)
-{
- //fb reserve
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0 buf", get_fb_size());
- resource_fb[0].end = resource_fb[0].start + get_fb_size()- 1;
- #if 0
- resource_fb[1].start = board_mem_reserve_add("ipp buf", RK30_FB0_MEM_SIZE);
- resource_fb[1].end = resource_fb[1].start + RK30_FB0_MEM_SIZE - 1;
- #endif
-
- #if defined(CONFIG_FB_ROTATE) || !defined(CONFIG_THREE_FB_BUFFER)
- resource_fb[2].start = board_mem_reserve_add("fb2 buf",get_fb_size());
- resource_fb[2].end = resource_fb[2].start + get_fb_size() - 1;
- #endif
-#endif
- //ion reserve
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
-#ifdef CONFIG_GPS_RK
- //it must be more than 8MB
- rk_gps_info.u32MemoryPhyAddr = board_mem_reserve_add("gps", SZ_8M);
-#endif
- board_mem_reserved();
-}
-
-/***********************************************************
-* clock
-************************************************************/
-static struct cpufreq_frequency_table dvfs_arm_table[] = {
- {.frequency = 312 * 1000, .index = 1200 * 1000},
- {.frequency = 504 * 1000, .index = 1200 * 1000},
- {.frequency = 816 * 1000, .index = 1200 * 1000},
- //{.frequency = 1008 * 1000, .index = 1200 * 1000},
- //{.frequency = 1200 * 1000, .index = 1200 * 1000},
- //{.frequency = 1416 * 1000, .index = 1200 * 1000},
- //{.frequency = 1608 * 1000, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- {.frequency = 100 * 1000, .index = 1200 * 1000},
- {.frequency = 200 * 1000, .index = 1200 * 1000},
- {.frequency = 266 * 1000, .index = 1200 * 1000},
- {.frequency = 300 * 1000, .index = 1200 * 1000},
- {.frequency = 400 * 1000, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 1200 * 1000},
- {.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = 1200 * 1000},
- {.frequency = 400 * 1000 + DDR_FREQ_NORMAL, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-void __init board_clock_init(void)
-{
- rk2928_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
- //dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "cpu"), dvfs_arm_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
-}
-
-/************************ end *****************************/
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk2928_fixup,
- .reserve = &rk30_reserve,
- .map_io = rk2928_map_io,
- .init_irq = rk2928_init_irq,
- .timer = &rk2928_timer,
- .init_machine = machine_rk30_board_init,
-MACHINE_END
+++ /dev/null
-/* arch/arm/mach-rk2928/clock_data.c
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/hardirq.h>
-#include <mach/cru.h>
-#include <mach/iomux.h>
-#include <mach/clock.h>
-#include <mach/dvfs.h>
-//#include <mach/pmu.h>
-#include <mach/ddr.h>
-
-#define MHZ (1000 * 1000)
-#define KHZ (1000)
-#define CLK_LOOPS_JIFFY_REF 11996091ULL
-#define CLK_LOOPS_RATE_REF (1200) //Mhz
-#define CLK_LOOPS_RECALC(new_rate) div_u64(CLK_LOOPS_JIFFY_REF*(new_rate),CLK_LOOPS_RATE_REF*MHZ)
-#define LPJ_24M (CLK_LOOPS_JIFFY_REF * 24) / CLK_LOOPS_RATE_REF
-
-static int flag_uboot_display = 0;
-
-struct apll_clk_set {
- unsigned long rate;
- u32 pllcon0;
- u32 pllcon1;
- u32 pllcon2; //nb=bwadj+1;0:11;nb=nf/2
- u32 clksel0;
- u32 clksel1;
- u32 rst_dly;//us
- unsigned long lpj; //loop per jeffise
-};
-
-struct pll_clk_set {
- unsigned long rate;
- u32 pllcon0;
- u32 pllcon1;
- u32 pllcon2; //nb=bwadj+1;0:11;nb=nf/2
- u32 rst_dly;//us
-};
-#if 0
-#define CLKDATA_DBG(fmt, args...) printk("CLKDATA_DBG:\t"fmt, ##args)
-#define CLKDATA_LOG(fmt, args...) printk("CLKDATA_LOG:\t"fmt, ##args)
-#else
-#define CLKDATA_DBG(fmt, args...) do {} while(0)
-#define CLKDATA_LOG(fmt, args...) do {} while(0)
-#endif
-#define CLKDATA_ERR(fmt, args...) printk(KERN_ERR "CLKDATA_ERR:\t"fmt, ##args)
-#define CLKDATA_WARNNING(fmt, args...) printk("CLKDATA_WANNING:\t"fmt, ##args)
-
-#define cru_readl(offset) readl_relaxed(RK2928_CRU_BASE + offset)
-#define cru_writel(v, offset) do { writel_relaxed(v, RK2928_CRU_BASE + offset); dsb(); } while (0)
-
-#define rk_clock_udelay(a) udelay(a);
-
-#define PLLS_IN_NORM(pll_id) \
- (((cru_readl(CRU_MODE_CON) & PLL_MODE_MSK(pll_id)) == (PLL_MODE_NORM(pll_id) & PLL_MODE_MSK(pll_id)))\
- && !(cru_readl(PLL_CONS(pll_id, 0)) & PLL_BYPASS))
-
-#define get_cru_bits(con, mask, shift)\
- ((cru_readl((con)) >> (shift)) & (mask))
-
-#define CRU_DIV_SET(mask, shift, max) \
- .div_mask = (mask),\
-.div_shift = (shift),\
-.div_max = (max)
-
-#define CRU_SRC_SET(mask, shift ) \
- .src_mask = (mask),\
-.src_shift = (shift)
-
-#define CRU_PARENTS_SET(parents_array) \
- .parents = (parents_array),\
-.parents_num = ARRAY_SIZE((parents_array))
-
-#define get_cru_bits(con,mask,shift)\
- ((cru_readl((con)) >> (shift)) & (mask))
-
-#define set_cru_bits_w_msk(val,mask,shift,con)\
- cru_writel(((mask)<<(shift+16))|((val)<<(shift)),(con))
-#define regfile_readl(offset) readl_relaxed(RK2928_GRF_BASE + offset)
-#define regfile_writel(v, offset) do { writel_relaxed(v, RK2928_GRF_BASE + offset); dsb(); } while (0)
-#define cru_writel_frac(v,offset) cru_writel((v),(offset))
-/*******************PLL CON0 BITS***************************/
-#define SET_PLL_DATA(_pll_id,_table) \
-{\
- .id=(_pll_id),\
- .table=(_table),\
-}
-
-#define GATE_CLK(NAME,PARENT,ID) \
- static struct clk clk_##NAME = { \
- .name = #NAME, \
- .parent = &PARENT, \
- .mode = gate_mode, \
- .gate_idx = CLK_GATE_##ID, \
- }
-
-//FIXME
-//lpj
-#define _APLL_SET_CLKS(_mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac, \
- _periph_div, _aclk_core_div, _axi_div, _apb_div, _ahb_div) \
-{ \
- .rate = (_mhz) * MHZ, \
- .pllcon0 = PLL_SET_POSTDIV1(_postdiv1) | PLL_SET_FBDIV(_fbdiv), \
- .pllcon1 = PLL_SET_DSMPD(_dsmpd) | PLL_SET_POSTDIV2(_postdiv2) | PLL_SET_REFDIV(_refdiv), \
- .pllcon2 = PLL_SET_FRAC(_frac), \
- .clksel1 = ACLK_CORE_DIV(RATIO_##_aclk_core_div) | CLK_CORE_PERI_DIV(RATIO_##_periph_div), \
- .lpj = (CLK_LOOPS_JIFFY_REF * _mhz) / CLK_LOOPS_RATE_REF, \
- .rst_dly = 0,\
-}
-
-static const struct apll_clk_set apll_clks[] = {
- _APLL_SET_CLKS(1608, 1, 67, 1, 1, 1, 0, 81, 21, 41, 21, 21),
- _APLL_SET_CLKS(1584, 1, 66, 1, 1, 1, 0, 81, 21, 41, 21, 21),
- _APLL_SET_CLKS(1560, 1, 65, 1, 1, 1, 0, 81, 21, 41, 21, 21),
- _APLL_SET_CLKS(1536, 1, 64, 1, 1, 1, 0, 81, 21, 41, 21, 21),
- _APLL_SET_CLKS(1512, 1, 63, 1, 1, 1, 0, 81, 21, 41, 21, 21),
- _APLL_SET_CLKS(1488, 1, 62, 1, 1, 1, 0, 81, 21, 41, 21, 21),
- _APLL_SET_CLKS(1464, 1, 61, 1, 1, 1, 0, 81, 21, 41, 21, 21),
- _APLL_SET_CLKS(1440, 1, 60, 1, 1, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS(1416, 1, 59, 1, 1, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS(1392, 1, 58, 1, 1, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS(1368, 1, 57, 1, 1, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS(1344, 1, 56, 1, 1, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS(1320, 1, 55, 1, 1, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS(1296, 1, 54, 1, 1, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS(1272, 1, 53, 1, 1, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS(1248, 1, 52, 1, 1, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS(1200, 1, 50, 1, 1, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS(1104, 1, 46, 1, 1, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS(1008, 1, 42, 1, 1, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS( 984, 1, 41, 1, 1, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS( 960, 1, 40, 1, 1, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS( 936, 1, 39, 1, 1, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS( 912, 1, 38, 1, 1, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS( 888, 1, 37, 1, 1, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS( 864, 1, 36, 1, 1, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS( 840, 1, 35, 1, 1, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS( 816, 1, 34, 1, 1, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS( 696, 1, 29, 1, 1, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS( 600, 1, 25, 1, 1, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS( 504, 1, 21, 1, 1, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS( 408, 1, 17, 1, 1, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS( 312, 1, 52, 2, 2, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS( 216, 1, 36, 2, 2, 1, 0, 41, 21, 41, 21, 21),
- _APLL_SET_CLKS( 96, 1, 32, 4, 2, 1, 0, 21, 21, 41, 21, 21),
- _APLL_SET_CLKS( 0, 1, 0, 1, 1, 1, 0, 41, 21, 41, 21, 21),
-};
-
-#define _PLL_SET_CLKS(_mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac) \
-{ \
- .rate = (_mhz) * KHZ, \
- .pllcon0 = PLL_SET_POSTDIV1(_postdiv1) | PLL_SET_FBDIV(_fbdiv), \
- .pllcon1 = PLL_SET_DSMPD(_dsmpd) | PLL_SET_POSTDIV2(_postdiv2) | PLL_SET_REFDIV(_refdiv), \
- .pllcon2 = PLL_SET_FRAC(_frac), \
-}
-static const struct pll_clk_set cpll_clks[] = {
- _PLL_SET_CLKS(798000, 4, 133, 1, 1, 1, 0),
- _PLL_SET_CLKS(594000, 2, 99, 2, 1, 1, 0),
- _PLL_SET_CLKS(1064000, 3, 133, 1, 1, 1, 0),
-};
-
-static const struct pll_clk_set gpll_clks[] = {
- _PLL_SET_CLKS(297000, 2, 99, 4, 1, 1, 0),
- _PLL_SET_CLKS(768000, 1, 32, 1, 1, 1, 0),
-};
-
-static u32 clk_gcd(u32 numerator, u32 denominator)
-{
- u32 a, b;
-
- if (!numerator || !denominator)
- return 0;
-
- if (numerator > denominator) {
- a = numerator;
- b = denominator;
- } else {
- a = denominator;
- b = numerator;
- }
-
- while (b != 0) {
- int r = b;
- b = a % b;
- a = r;
- }
-
- return a;
-}
-
-static int frac_div_get_seting(unsigned long rate_out, unsigned long rate,
- u32 *numerator, u32 *denominator)
-{
- u32 gcd_vl;
- gcd_vl = clk_gcd(rate, rate_out);
- CLKDATA_DBG("frac_get_seting rate=%lu,parent=%lu,gcd=%d\n", rate_out, rate, gcd_vl);
-
- if (!gcd_vl) {
- CLKDATA_ERR("gcd=0, i2s frac div is not be supported\n");
- return -ENOENT;
- }
-
- *numerator = rate_out / gcd_vl;
- *denominator = rate / gcd_vl;
-
- CLKDATA_DBG("frac_get_seting numerator=%d,denominator=%d,times=%d\n",
- *numerator, *denominator, *denominator / *numerator);
-
- if (*numerator > 0xffff || *denominator > 0xffff ||
- (*denominator / (*numerator)) < 20) {
- CLKDATA_ERR("can't get a available nume and deno\n");
- return -ENOENT;
- }
-
- return 0;
-
-}
-/************************option functions*****************/
-/************************clk recalc div rate**************/
-
-//for free div
-static unsigned long clksel_recalc_div(struct clk *clk)
-{
- u32 div = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
- unsigned long rate = clk->parent->rate / div;
-
- CLKDATA_DBG("ENTER %s clk=%s\n", __func__, clk->name);
- CLKDATA_DBG("%s new clock rate is %lu (div %u)\n", clk->name, rate, div);
- return rate;
-}
-
-//for div 2^n
-static unsigned long clksel_recalc_shift(struct clk *clk)
-{
- u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift);
- unsigned long rate = clk->parent->rate >> shift;
- CLKDATA_DBG("ENTER %s clk=%s\n", __func__, clk->name);
- CLKDATA_DBG("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
- return rate;
-}
-
-//for rate equal to parent
-static unsigned long clksel_recalc_equal_parent(struct clk *clk)
-{
- unsigned long rate = clk->parent->rate;
- CLKDATA_DBG("ENTER %s clk=%s\n", __func__, clk->name);
- CLKDATA_DBG("%s new clock rate is %lu (equal to parent)\n", clk->name, rate);
-
- return rate;
-}
-
-//for Fixed divide ratio
-static unsigned long clksel_recalc_fixed_div2(struct clk *clk)
-{
- unsigned long rate = clk->parent->rate >> 1;
- CLKDATA_DBG("ENTER %s clk=%s\n", __func__, clk->name);
- CLKDATA_DBG("%s new clock rate is %lu (div %u)\n", clk->name, rate, 2);
-
- return rate;
-}
-
-static unsigned long clksel_recalc_fixed_div4(struct clk *clk)
-{
- unsigned long rate = clk->parent->rate >> 2;
- CLKDATA_DBG("ENTER %s clk=%s\n", __func__, clk->name);
- CLKDATA_DBG("%s new clock rate is %lu (div %u)\n", clk->name, rate, 4);
-
- return rate;
-}
-
-static unsigned long clksel_recalc_frac(struct clk *clk)
-{
- unsigned long rate;
- u64 rate64;
- u32 r = cru_readl(clk->clksel_con), numerator, denominator;
- CLKDATA_DBG("ENTER %s clk=%s\n", __func__, clk->name);
- if (r == 0) // FPGA ?
- return clk->parent->rate;
- numerator = r >> 16;
- denominator = r & 0xFFFF;
- rate64 = (u64)clk->parent->rate * numerator;
- do_div(rate64, denominator);
- rate = rate64;
- CLKDATA_DBG("%s new clock rate is %lu (frac %u/%u)\n", clk->name, rate, numerator, denominator);
- return rate;
-}
-
-#define FRAC_MODE 0
-static unsigned long pll_clk_recalc(u8 pll_id, unsigned long parent_rate)
-{
- unsigned long rate;
- unsigned int dsmp = 0;
- u64 rate64 = 0, frac_rate64 = 0;
- dsmp = PLL_GET_DSMPD(cru_readl(PLL_CONS(pll_id, 1)));
-
- if (PLLS_IN_NORM(pll_id)) {
- u32 pll_con0 = cru_readl(PLL_CONS(pll_id, 0));
- u32 pll_con1 = cru_readl(PLL_CONS(pll_id, 1));
- u32 pll_con2 = cru_readl(PLL_CONS(pll_id, 2));
- //integer mode
- rate64 = (u64)parent_rate * PLL_GET_FBDIV(pll_con0);
- do_div(rate64, PLL_GET_REFDIV(pll_con1));
-
- if (FRAC_MODE == dsmp) {
- //fractional mode
- frac_rate64 = (u64)parent_rate * PLL_GET_FRAC(pll_con2);
- do_div(frac_rate64, PLL_GET_REFDIV(pll_con1));
- rate64 += frac_rate64 >> 24;
- CLKDATA_DBG("%s id=%d frac_rate=%llu(%08x/2^24) by pass mode\n",
- __func__, pll_id, frac_rate64 >> 24, PLL_GET_FRAC(pll_con2));
- }
- do_div(rate64, PLL_GET_POSTDIV1(pll_con0));
- do_div(rate64, PLL_GET_POSTDIV2(pll_con1));
-
- rate = rate64;
- } else {
- rate = parent_rate;
- CLKDATA_DBG("pll_clk_recalc id=%d rate=%lu by pass mode\n", pll_id, rate);
- }
- return rate;
-}
-
-static unsigned long plls_clk_recalc(struct clk *clk)
-{
- return pll_clk_recalc(clk->pll->id, clk->parent->rate);
-}
-
-/************************clk set rate*********************************/
-static int clksel_set_rate_freediv(struct clk *clk, unsigned long rate)
-{
- u32 div = 0;
-
- for (div = 0; div <= clk->div_max; div++) {
- u32 new_rate = clk->parent->rate / (div + 1);
- if (new_rate <= rate) {
- set_cru_bits_w_msk(div, clk->div_mask, clk->div_shift, clk->clksel_con);
- //clk->rate = new_rate;
- CLKDATA_DBG("clksel_set_rate_freediv for clock %s to rate %ld (div %d)\n",
- clk->name, rate, div + 1);
- return 0;
- }
- if (div == clk->div_max - 1) {
- CLKDATA_WARNNING("%s clk=%s, div=%u, rate=%lu, new_rate=%u\n",
- __func__, clk->name, div, rate, new_rate);
- set_cru_bits_w_msk(div, clk->div_mask, clk->div_shift, clk->clksel_con);
- return 0;
- }
- }
- return -ENOENT;
-}
-
-//for div 1 2 4 2^n
-static int clksel_set_rate_shift(struct clk *clk, unsigned long rate)
-{
- u32 shift;
- for (shift = 0; (1 << shift) <= clk->div_max; shift++) {
- u32 new_rate = clk->parent->rate >> shift;
- if (new_rate <= rate) {
- set_cru_bits_w_msk(shift, clk->div_mask, clk->div_shift, clk->clksel_con);
- clk->rate = new_rate;
- CLKDATA_DBG("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n",
- clk->name, rate, shift);
- return 0;
- }
- }
- return -ENOENT;
-}
-#if 0
-//for div 2 4 2^n
-static int clksel_set_rate_shift_2(struct clk *clk, unsigned long rate)
-{
- u32 shift;
-
- for (shift = 1; (1 << shift) < clk->div_max; shift++) {
- u32 new_rate = clk->parent->rate >> shift;
- if (new_rate <= rate) {
- set_cru_bits_w_msk(shift - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
- clk->rate = new_rate;
- CLKDATA_DBG("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n",
- clk->name, rate, shift);
- return 0;
- }
- }
- return -ENOENT;
-}
-#endif
-//for div 1 2 4 2*n
-static int clksel_set_rate_even(struct clk *clk, unsigned long rate)
-{
- u32 div = 0, new_rate = 0;
- for (div = 1; div <= clk->div_max; div++) {
- if (div >= 3 && div % 2 != 0)
- continue;
- new_rate = clk->parent->rate / div;
- if (new_rate <= rate) {
- set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
- clk->rate = new_rate;
- pr_debug("%s for clock %s to rate %ld (even div = %d)\n",
- __func__, clk->name, rate, div);
- return 0;
- }
- }
- return -ENOENT;
-}
-
-static u32 clk_get_freediv(unsigned long rate_out, unsigned long rate , u32 div_max)
-{
- u32 div;
- unsigned long new_rate;
- for (div = 0; div < div_max; div++) {
- new_rate = rate / (div + 1);
- if (new_rate <= rate_out) {
- return div + 1;
- }
- }
- return div_max ? div_max : 1;
-}
-struct clk *get_freediv_parents_div(struct clk *clk, unsigned long rate, u32 *div_out) {
- u32 div[2] = {0, 0};
- unsigned long new_rate[2] = {0, 0};
- u32 i;
-
- if (clk->rate == rate)
- return clk->parent;
- for (i = 0; i < 2; i++) {
- div[i] = clk_get_freediv(rate, clk->parents[i]->rate, clk->div_max);
- new_rate[i] = clk->parents[i]->rate / div[i];
- if (new_rate[i] == rate) {
- *div_out = div[i];
- return clk->parents[i];
- }
- }
- if (new_rate[0] < new_rate[1])
- i = 1;
- else
- i = 0;
- *div_out = div[i];
- return clk->parents[i];
-}
-
-static int clkset_rate_freediv_autosel_parents(struct clk *clk, unsigned long rate)
-{
- struct clk *p_clk;
- u32 div, old_div;
- int ret = 0;
- if (clk->rate == rate)
- return 0;
- p_clk = get_freediv_parents_div(clk, rate, &div);
-
- if (!p_clk)
- return -ENOENT;
-
- CLKDATA_DBG("%s %lu,form %s\n", clk->name, rate, p_clk->name);
- if (clk->parent != p_clk) {
- old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con), clk->div_shift, clk->div_mask) + 1;
-
- if (div > old_div) {
- set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
- }
- ret = clk_set_parent_nolock(clk, p_clk);
- if (ret) {
- CLKDATA_ERR("%s can't set %lu,reparent err\n", clk->name, rate);
- return -ENOENT;
- }
- }
- //set div
- set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
- return 0;
-}
-#if 0
-//rate==div rate //hdmi
-static int clk_freediv_autosel_parents_set_fixed_rate(struct clk *clk, unsigned long rate)
-{
- struct clk *p_clk;
- u32 div, old_div;
- int ret;
- p_clk = get_freediv_parents_div(clk, rate, &div);
-
- if (!p_clk)
- return -ENOENT;
-
- if ((p_clk->rate / div) != rate || (p_clk->rate % div))
- return -ENOENT;
-
- if (clk->parent != p_clk) {
- old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con),
- clk->div_shift, clk->div_mask) + 1;
- if(div > old_div) {
- set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
- }
- ret = clk_set_parent_nolock(clk, p_clk);
- if (ret) {
- CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
- return ret;
- }
- }
- //set div
- set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
- return 0;
-}
-#endif
-/************************round functions*****************/
-static long clksel_freediv_round_rate(struct clk *clk, unsigned long rate)
-{
- return clk->parent->rate / clk_get_freediv(rate, clk->parent->rate, clk->div_max);
-}
-
-static long clk_freediv_round_autosel_parents_rate(struct clk *clk, unsigned long rate)
-{
- u32 div;
- struct clk *p_clk;
- if (clk->rate == rate)
- return clk->rate;
- p_clk = get_freediv_parents_div(clk, rate, &div);
- if (!p_clk)
- return 0;
- return p_clk->rate / div;
-}
-
-static const struct apll_clk_set *apll_clk_get_best_pll_set(unsigned long rate,
- struct apll_clk_set *tables) {
- const struct apll_clk_set *ps, *pt;
-
- /* find the arm_pll we want. */
- ps = pt = tables;
- while (pt->rate) {
- if (pt->rate == rate) {
- ps = pt;
- break;
- }
- // we are sorted, and ps->rate > pt->rate.
- if ((pt->rate > rate || (rate - pt->rate < ps->rate - rate)))
- ps = pt;
- if (pt->rate < rate)
- break;
- pt++;
- }
- //CLKDATA_DBG("arm pll best rate=%lu\n",ps->rate);
- return ps;
-}
-static long apll_clk_round_rate(struct clk *clk, unsigned long rate)
-{
- return apll_clk_get_best_pll_set(rate, clk->pll->table)->rate;
-}
-
-/************************others functions*****************/
-static void pll_wait_lock(int pll_idx)
-{
- u32 pll_state[4] = {1, 0, 2, 3};
- u32 bit = 0x10u << pll_state[pll_idx];
- int delay = 24000000;
- while (delay > 0) {
- if ((cru_readl(PLL_CONS(pll_idx, 1)) & (0x1 << PLL_LOCK_SHIFT))) {
- //CLKDATA_DBG("%s %08x\n", __func__, cru_readl(PLL_CONS(pll_idx, 1)) & (0x1 << PLL_LOCK_SHIFT));
- //CLKDATA_DBG("%s ! %08x\n", __func__, !(cru_readl(PLL_CONS(pll_idx, 1)) & (0x1 << PLL_LOCK_SHIFT)));
- break;
- }
- delay--;
- }
- if (delay == 0) {
- CLKDATA_ERR("wait pll bit 0x%x time out!\n", bit);
- while(1);
- }
-}
-
-static int pll_clk_mode(struct clk *clk, int on)
-{
- u8 pll_id = clk->pll->id;
- // FIXME here 500 must be changed
- u32 dly = 1500;
-
- CLKDATA_DBG("pll_mode %s(%d)\n", clk->name, on);
- //FIXME
- if (on) {
- cru_writel(CRU_W_MSK_SETBIT(PLL_PWR_ON, PLL_BYPASS_SHIFT), PLL_CONS(pll_id, 0));
- rk_clock_udelay(dly);
- pll_wait_lock(pll_id);
- cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
- } else {
- cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
- cru_writel(CRU_W_MSK_SETBIT(PLL_PWR_DN, PLL_BYPASS_SHIFT), PLL_CONS(pll_id, 0));
- }
- return 0;
-}
-static struct clk *clksel_get_parent(struct clk *clk) {
- return clk->parents[(cru_readl(clk->clksel_con) >> clk->src_shift) & clk->src_mask];
-}
-static int clksel_set_parent(struct clk *clk, struct clk *parent)
-{
- u32 i;
- if (unlikely(!clk->parents))
- return -EINVAL;
- for (i = 0; (i < clk->parents_num); i++) {
- if (clk->parents[i] != parent)
- continue;
- set_cru_bits_w_msk(i, clk->src_mask, clk->src_shift, clk->clksel_con);
- return 0;
- }
- return -EINVAL;
-}
-
-static int gate_mode(struct clk *clk, int on)
-{
- int idx = clk->gate_idx;
- CLKDATA_DBG("ENTER %s clk=%s, on=%d\n", __func__, clk->name, on);
- if (idx >= CLK_GATE_MAX)
- return -EINVAL;
- if (on) {
- cru_writel(CLK_GATE_W_MSK(idx) | CLK_UN_GATE(idx), CLK_GATE_CLKID_CONS(idx));
- } else {
- cru_writel(CLK_GATE_W_MSK(idx) | CLK_GATE(idx), CLK_GATE_CLKID_CONS(idx));
- }
- return 0;
-}
-#define PLL_INT_MODE 1
-#define PLL_FRAC_MODE 0
-
-#define rk2928_clock_udelay(a) udelay(a);
-static int pll_clk_set_rate(struct pll_clk_set *clk_set, u8 pll_id)
-{
- //enter slowmode
- cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
-
- cru_writel(clk_set->pllcon0, PLL_CONS(pll_id, 0));
- cru_writel(clk_set->pllcon1, PLL_CONS(pll_id, 1));
- cru_writel(clk_set->pllcon2, PLL_CONS(pll_id, 2));
-
- CLKDATA_DBG("id=%d,pllcon0%08x\n", pll_id, cru_readl(PLL_CONS(pll_id, 0)));
- CLKDATA_DBG("id=%d,pllcon1%08x\n", pll_id, cru_readl(PLL_CONS(pll_id, 1)));
- CLKDATA_DBG("id=%d,pllcon2%08x\n", pll_id, cru_readl(PLL_CONS(pll_id, 2)));
- //rk2928_clock_udelay(5);
-
- //wating lock state
- rk2928_clock_udelay(clk_set->rst_dly);
- pll_wait_lock(pll_id);
-
- //return form slow
- cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
-
- return 0;
-}
-#define PLL_FREF_MIN (183 * KHZ)
-#define PLL_FREF_MAX (1500 * MHZ)
-
-#define PLL_FVCO_MIN (300 * MHZ)
-#define PLL_FVCO_MAX (1500 * MHZ)
-
-#define PLL_FOUT_MIN (18750 * KHZ)
-#define PLL_FOUT_MAX (1500 * MHZ)
-
-#define PLL_NF_MAX (4096)
-#define PLL_NR_MAX (64)
-#define PLL_NO_MAX (16)
-
-static int pll_clk_check_legality(unsigned long fin_hz, unsigned long fout_hz,
- u32 refdiv, u32 fbdiv, u32 postdiv1, u32 postdiv2)
-{
- fin_hz /= MHZ;
- if (fin_hz < 1 || fin_hz > 800) {
- CLKDATA_ERR("%s fbdiv out of [1, 800]MHz\n", __func__);
- return -1;
- }
-
- if (fbdiv < 16 || fbdiv > 1600) {
- CLKDATA_ERR("%s fbdiv out of [16, 1600]MHz\n", __func__);
- return -1;
- }
-
- if (fin_hz / refdiv < 1 || fin_hz / refdiv > 40) {
- CLKDATA_ERR("%s fin / refdiv out of [1, 40]MHz\n", __func__);
- return -1;
- }
-
- if (fin_hz * fbdiv / refdiv < 400 || fin_hz * fbdiv / refdiv > 1600) {
- CLKDATA_ERR("%s fin_hz * fbdiv / refdiv out of [400, 1600]MHz\n", __func__);
- return -1;
- }
-
- if (fin_hz * fbdiv / refdiv / postdiv1 / postdiv2 < 8
- || fin_hz * fbdiv / refdiv / postdiv1 / postdiv2 > 1600) {
- CLKDATA_ERR("%s fin_hz * fbdiv / refdiv / postdiv1 / postdiv2 out of [8, 1600]MHz\n", __func__);
- return -1;
- }
-
-}
-
-static int pll_clk_check_legality_frac(unsigned long fin_hz, unsigned long fout_hz,
- u32 refdiv, u32 fbdiv, u32 postdiv1, u32 postdiv2, u32 frac)
-{
- fin_hz /= MHZ;
- if (fin_hz < 10 || fin_hz > 800) {
- CLKDATA_ERR("%s fin_hz out of [10, 800]MHz\n", __func__);
- return -1;
- }
- if (fbdiv < 19 || fbdiv > 160) {
- CLKDATA_ERR("%s fbdiv out of [19, 160]MHz\n", __func__);
- return -1;
- }
-
- if (fin_hz / refdiv < 1 || fin_hz / refdiv > 40) {
- CLKDATA_ERR("%s fin / refdiv out of [1, 40]MHz\n", __func__);
- return -1;
- }
-
- if (fin_hz * fbdiv / refdiv < 400 || fin_hz * fbdiv / refdiv > 1600) {
- CLKDATA_ERR("%s fin_hz * fbdiv / refdiv out of [400, 1600]MHz\n", __func__);
- return -1;
- }
-
- if (fin_hz * fbdiv / refdiv / postdiv1 / postdiv2 < 8
- || fin_hz * fbdiv / refdiv / postdiv1 / postdiv2 > 1600) {
- CLKDATA_ERR("%s fin_hz * fbdiv / refdiv / postdiv1 / postdiv2 out of [8, 1600]MHz\n", __func__);
- return -1;
- }
-
-}
-#define MIN_FOUTVCO_FREQ (400 * 1000 * 1000)
-#define MAX_FOUTVCO_FREQ (1600 * 1000 * 1000)
-static int pll_clk_set_postdiv(unsigned long fout_hz, u32 *postdiv1, u32 *postdiv2, u32 *foutvco)
-{
- if (fout_hz < MIN_FOUTVCO_FREQ) {
- for (*postdiv1 = 1; *postdiv1 <= 7; (*postdiv1)++)
- for (*postdiv2 = 1; *postdiv2 <= 7; (*postdiv2)++) {
- if (fout_hz * (*postdiv1) * (*postdiv2) >= MIN_FOUTVCO_FREQ
- && fout_hz * (*postdiv1) * (*postdiv2) <= MAX_FOUTVCO_FREQ) {
- *foutvco = fout_hz * (*postdiv1) * (*postdiv2);
- return 0;
- }
- }
- CLKDATA_ERR("CANNOT FINE postdiv1/2 to make fout in range from 400M to 1600M, fout = %lu\n",
- fout_hz);
- } else {
- *postdiv1 = 1;
- *postdiv2 = 1;
- }
- return 0;
-}
-static int pll_clk_get_set(unsigned long fin_hz, unsigned long fout_hz,
- u32 *refdiv, u32 *fbdiv, u32 *postdiv1, u32 *postdiv2, u32 *frac)
-{
- // FIXME set postdiv1/2 always 1
- u32 gcd, foutvco = fout_hz;
- u64 fin_64, frac_64;
- u32 f_frac;
- if (!fin_hz || !fout_hz || fout_hz == fin_hz)
- return -1;
-
- pll_clk_set_postdiv(fout_hz, postdiv1, postdiv2, &foutvco);
- if (fin_hz / MHZ *MHZ == fin_hz && fout_hz / MHZ *MHZ == fout_hz) {
- fin_hz /= MHZ;
- foutvco /= MHZ;
- gcd = clk_gcd(fin_hz, foutvco);
- *refdiv = fin_hz / gcd;
- *fbdiv = foutvco / gcd;
-
- *frac = 0;
-
- CLKDATA_DBG("fin=%lu,fout=%lu,gcd=%u,refdiv=%u,fbdiv=%u,postdiv1=%u,postdiv2=%u,frac=%u\n",
- fin_hz, fout_hz, gcd, *refdiv, *fbdiv, *postdiv1, *postdiv2, *frac);
- } else {
- CLKDATA_DBG("******frac div running, fin_hz=%lu, fout_hz=%lu, fin_INT_mhz=%lu, fout_INT_mhz=%lu\n",
- fin_hz, fout_hz, fin_hz / MHZ * MHZ, fout_hz / MHZ * MHZ);
- CLKDATA_DBG("******frac get postdiv1=%u, postdiv2=%u, foutvco=%u\n", *postdiv1, *postdiv2, foutvco);
- gcd = clk_gcd(fin_hz / MHZ, foutvco / MHZ);
- *refdiv = fin_hz / MHZ / gcd;
- *fbdiv = foutvco / MHZ / gcd;
- CLKDATA_DBG("******frac get refdiv=%u, fbdiv=%u\n", *refdiv, *fbdiv);
-
- *frac = 0;
-
- f_frac = (foutvco % MHZ);
- fin_64 = fin_hz;
- do_div(fin_64, (u64)*refdiv);
- frac_64 = (u64)f_frac << 24;
- do_div(frac_64, fin_64);
- *frac = (u32) frac_64;
- CLKDATA_DBG("frac=%x\n", *frac);
- }
- return 0;
-}
-static int pll_set_con(u8 id, u32 refdiv, u32 fbdiv, u32 postdiv1, u32 postdiv2, u32 frac)
-{
- struct pll_clk_set temp_clk_set;
- temp_clk_set.pllcon0 = PLL_SET_FBDIV(fbdiv) | PLL_SET_POSTDIV1(postdiv1);
- temp_clk_set.pllcon1 = PLL_SET_REFDIV(refdiv) | PLL_SET_POSTDIV2(postdiv2);
- if (frac != 0) {
- temp_clk_set.pllcon1 |= PLL_SET_DSMPD(0);
- } else {
- temp_clk_set.pllcon1 |= PLL_SET_DSMPD(1);
- }
- temp_clk_set.pllcon2 = PLL_SET_FRAC(frac);
- temp_clk_set.rst_dly = 0;
- CLKDATA_DBG("setting....\n");
- return pll_clk_set_rate(&temp_clk_set, id);
-}
-static int apll_clk_set_rate(struct clk *clk, unsigned long rate)
-{
- unsigned long flags;
- struct _pll_data *pll_data = clk->pll;
- struct apll_clk_set *clk_set = (struct apll_clk_set *)pll_data->table;
-
- u32 fin_hz, fout_hz;
- u32 refdiv, fbdiv, postdiv1, postdiv2, frac;
- u8 pll_id = pll_data->id;
-
- fin_hz = clk->parent->rate;
- fout_hz = rate;
-
- while (clk_set->rate) {
- if (clk_set->rate == rate) {
- break;
- }
- clk_set++;
- }
-
- CLKDATA_DBG("%s %s %lu\n", __func__, clk->name, rate);
- CLKDATA_DBG("pllcon0 %08x\n", cru_readl(PLL_CONS(0, 0)));
- CLKDATA_DBG("pllcon1 %08x\n", cru_readl(PLL_CONS(0, 1)));
- CLKDATA_DBG("pllcon2 %08x\n", cru_readl(PLL_CONS(0, 2)));
- //CLKDATA_DBG("pllcon3 %08x\n", cru_readl(PLL_CONS(0,3)));
- CLKDATA_DBG("clksel0 %08x\n", cru_readl(CRU_CLKSELS_CON(0)));
- CLKDATA_DBG("clksel1 %08x\n", cru_readl(CRU_CLKSELS_CON(1)));
- if (clk_set->rate == rate) {
- CLKDATA_DBG("apll get a rate\n");
-
- //enter slowmode
- local_irq_save(flags);
- cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
- loops_per_jiffy = LPJ_24M;
-
- cru_writel(clk_set->pllcon0, PLL_CONS(pll_id, 0));
- cru_writel(clk_set->pllcon1, PLL_CONS(pll_id, 1));
- cru_writel(clk_set->pllcon2, PLL_CONS(pll_id, 2));
- cru_writel(clk_set->clksel0, CRU_CLKSELS_CON(0));
- cru_writel(clk_set->clksel1, CRU_CLKSELS_CON(1));
- //local_irq_restore(flags);
-
- CLKDATA_DBG("pllcon0 %08x\n", cru_readl(PLL_CONS(0, 0)));
- CLKDATA_DBG("pllcon1 %08x\n", cru_readl(PLL_CONS(0, 1)));
- CLKDATA_DBG("pllcon2 %08x\n", cru_readl(PLL_CONS(0, 2)));
- CLKDATA_DBG("pllcon3 %08x\n", cru_readl(PLL_CONS(0, 3)));
- CLKDATA_DBG("clksel0 %08x\n", cru_readl(CRU_CLKSELS_CON(0)));
- CLKDATA_DBG("clksel1 %08x\n", cru_readl(CRU_CLKSELS_CON(1)));
- //rk2928_clock_udelay(5);
-
- //wating lock state
- rk2928_clock_udelay(clk_set->rst_dly);
- pll_wait_lock(pll_id);
-
- //return form slow
- //local_irq_save(flags);
- cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
- loops_per_jiffy = clk_set->lpj;
- local_irq_restore(flags);
- } else {
- // FIXME
- pll_clk_get_set(clk->parent->rate, rate, &refdiv, &fbdiv, &postdiv1, &postdiv2, &frac);
- pll_set_con(clk->pll->id, refdiv, fbdiv, postdiv1, postdiv2, frac);
- }
-
- CLKDATA_DBG("setting OK\n");
- return 0;
-}
-
-static int dpll_clk_set_rate(struct clk *clk, unsigned long rate)
-{
- // FIXME do nothing here
- CLKDATA_DBG("setting OK\n");
- return 0;
-}
-
-static int cpll_clk_set_rate(struct clk *clk, unsigned long rate)
-{
- // FIXME
- struct _pll_data *pll_data = clk->pll;
- struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
-
- unsigned long fin_hz, fout_hz;
- u32 refdiv, fbdiv, postdiv1, postdiv2, frac;
- fin_hz = clk->parent->rate;
- fout_hz = rate;
-
- while (clk_set->rate) {
- if (clk_set->rate == rate) {
- break;
- }
- clk_set++;
- }
-
- if (clk_set->rate == rate) {
- CLKDATA_DBG("cpll get a rate\n");
- pll_clk_set_rate(clk_set, pll_data->id);
-
- } else {
- CLKDATA_DBG("cpll get auto calc a rate\n");
- if (pll_clk_get_set(clk->parent->rate, rate, &refdiv, &fbdiv, &postdiv1, &postdiv2, &frac) != 0) {
- pr_err("cpll auto set rate error\n");
- return -ENOENT;
- }
- CLKDATA_DBG("%s get fin=%lu, fout=%lu, rate=%lu, refdiv=%u, fbdiv=%u, postdiv1=%u, postdiv2=%u",
- __func__, fin_hz, fout_hz, rate, refdiv, fbdiv, postdiv1, postdiv2);
- pll_set_con(pll_data->id, refdiv, fbdiv, postdiv1, postdiv2, frac);
-
- }
-
- CLKDATA_DBG("setting OK\n");
- return 0;
-}
-
-static int gpll_clk_set_rate(struct clk *clk, unsigned long rate)
-{
- // FIXME
- struct _pll_data *pll_data = clk->pll;
- struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
-
- CLKDATA_DBG("******%s\n", __func__);
- while (clk_set->rate) {
- CLKDATA_DBG("******%s clk_set->rate=%lu\n", __func__, clk_set->rate);
- if (clk_set->rate == rate) {
- break;
- }
- clk_set++;
- }
- if (clk_set->rate == rate) {
- pll_clk_set_rate(clk_set, pll_data->id);
- //lpj_gpll = CLK_LOOPS_RECALC(rate);
- } else {
- CLKDATA_ERR("gpll is no corresponding rate=%lu\n", rate);
- return -1;
- }
- CLKDATA_DBG("******%s end\n", __func__);
-
- return 0;
-}
-
-/**********************pll datas*************************/
-static u32 rk2928_clock_flags = 0;
-static struct _pll_data apll_data = SET_PLL_DATA(APLL_ID, (void *)apll_clks);
-static struct _pll_data dpll_data = SET_PLL_DATA(DPLL_ID, NULL);
-static struct _pll_data cpll_data = SET_PLL_DATA(CPLL_ID, (void *)cpll_clks);
-static struct _pll_data gpll_data = SET_PLL_DATA(GPLL_ID, (void *)gpll_clks);
-/*********************************************************/
-/************************clocks***************************/
-/*********************************************************/
-
-static struct clk xin24m = {
- .name = "xin24m",
- .rate = 24 * MHZ,
- .flags = RATE_FIXED,
-};
-
-static struct clk clk_12m = {
- .name = "clk_12m",
- .parent = &xin24m,
- .rate = 12 * MHZ,
- .flags = RATE_FIXED,
-};
-/************************plls***********************/
-static struct clk arm_pll_clk = {
- .name = "arm_pll",
- .parent = &xin24m,
- .mode = pll_clk_mode,
- .recalc = plls_clk_recalc,
- .set_rate = apll_clk_set_rate,
- .round_rate = apll_clk_round_rate,
- .pll = &apll_data,
-};
-
-static struct clk ddr_pll_clk = {
- .name = "ddr_pll",
- .parent = &xin24m,
- .mode = pll_clk_mode,
- .recalc = plls_clk_recalc,
- .set_rate = dpll_clk_set_rate,
- .pll = &dpll_data,
-};
-
-static struct clk codec_pll_clk = {
- .name = "codec_pll",
- .parent = &xin24m,
- .mode = pll_clk_mode,
- .recalc = plls_clk_recalc,
- .set_rate = cpll_clk_set_rate,
- .pll = &cpll_data,
-};
-
-static struct clk general_pll_clk = {
- .name = "general_pll",
- .parent = &xin24m,
- .mode = pll_clk_mode,
- .gate_idx = CLK_GATE_CPU_GPLL,
- .recalc = plls_clk_recalc,
- .set_rate = gpll_clk_set_rate,
- .pll = &gpll_data,
-};
-#define SELECT_FROM_2PLLS_GC {&general_pll_clk, &codec_pll_clk}
-#define SELECT_FROM_2PLLS_CG {&codec_pll_clk, &general_pll_clk}
-
-GATE_CLK(ddrphy_src, ddr_pll_clk, DDRPHY_SRC);
-GATE_CLK(ddrphy_gpll_src, general_pll_clk, DDRPHY_GPLL_SRC);
-GATE_CLK(core_gpll, general_pll_clk, CORE_GPLL);
-GATE_CLK(cpu_gpll, general_pll_clk, CPU_GPLL);
-/*********ddr******/
-static int ddr_clk_set_rate(struct clk *c, unsigned long rate)
-{
- // need to do nothing
- return 0;
-}
-
-static long ddr_clk_round_rate(struct clk *clk, unsigned long rate)
-{
- return ddr_set_pll(rate / MHZ, 0) * MHZ;
-}
-static void ddr_update_rate(struct clk *clk, struct clk *clk_ignore)
-{
- struct clk *clkp;
- if (!clk->pll) {
- ddr_update_rate(clk->parent, NULL);
- } else {
- clk->rate = clk->recalc(clk);
- }
-
- list_for_each_entry(clkp, &clk->children, sibling) {
- if (clkp == clk_ignore)
- continue;
-
- if (clkp->recalc)
- clkp->rate = clkp->recalc(clk);
- else if (clkp->parent)
- clkp->rate = clkp->parent->rate;
- }
-}
-static unsigned long ddr_clk_recalc_rate(struct clk *clk)
-{
- ddr_update_rate(clk->parent, clk);
- clk->rate = clk->parent->rate >> 1;
- return clk->rate;
-}
-
-static struct clk *clk_ddr_pllsel_parents[] = {&clk_ddrphy_src, &clk_ddrphy_gpll_src};
-static struct clk clk_ddr_pllsel = {
- .name = "ddr_pllsel",
- .parent = &ddr_pll_clk,
- .clksel_con = CRU_CLKSELS_CON(26),
- CRU_SRC_SET(0x1, 8),
- CRU_PARENTS_SET(clk_ddr_pllsel_parents),
-};
-
-static struct clk clk_ddr_dll = {
- .name = "ddr_dll",
- .parent = &clk_ddr_pllsel,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_DLL_DDR,
- .set_rate = clksel_set_rate_freediv,
- .recalc = clksel_recalc_div,
- .clksel_con = CRU_CLKSELS_CON(5),
- CRU_DIV_SET(0x3f, 0, 64),
-};
-
-static struct clk clk_ddrphy2x = {
- .name = "ddrphy2x",
- .parent = &clk_ddr_pllsel,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_DDRPHY_SRC,
- .recalc = clksel_recalc_shift,
- .clksel_con = CRU_CLKSELS_CON(26),
- CRU_DIV_SET(0x3, 0, 4),
-};
-
-static struct clk clk_ddrc = {
- .name = "ddrc",
- .parent = &clk_ddrphy2x,
- .set_rate = ddr_clk_set_rate,
- .recalc = ddr_clk_recalc_rate,
- .round_rate = ddr_clk_round_rate,
-};
-
-static struct clk clk_ddrphy = {
- .name = "ddrphy",
- .parent = &clk_ddrphy2x,
- .recalc = clksel_recalc_fixed_div2,
-};
-
-/****************core*******************/
-#if 0
-static unsigned long core_clk_get_rate(struct clk *c)
-{
- u32 div = (get_cru_bits(c->clksel_con, c->div_mask, c->div_shift) + 1);
- //c->parent->rate=c->parent->recalc(c->parent);
- return c->parent->rate / div;
-}
-#endif
-static long core_clk_round_rate(struct clk *clk, unsigned long rate)
-{
- u32 div = (get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1);
- return clk_round_rate_nolock(clk->parent, rate) / div;
-}
-
-static int core_clksel_set_parent(struct clk *clk, struct clk *new_prt)
-{
- // FIXME
- u32 temp_div;
- struct clk *old_prt;
-
- if (clk->parent == new_prt)
- return 0;
- if (unlikely(!clk->parents))
- return -EINVAL;
- CLKDATA_DBG("%s,reparent %s\n", clk->name, new_prt->name);
- //arm
- old_prt = clk->parent;
-
- if (clk->parents[0] == new_prt) {
- new_prt->set_rate(new_prt, 300 * MHZ);
- set_cru_bits_w_msk(0, clk->div_mask, clk->div_shift, clk->clksel_con);
- } else if (clk->parents[1] == new_prt) {
-
- if (new_prt->rate > old_prt->rate) {
- temp_div = clk_get_freediv(old_prt->rate, new_prt->rate, clk->div_max);
- set_cru_bits_w_msk(temp_div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
- }
- set_cru_bits_w_msk(1, clk->src_mask, clk->src_shift, clk->clksel_con);
- new_prt->set_rate(new_prt, 300 * MHZ);
- } else
- return -1;
-
- return 0;
-}
-
-// this clk is cpu?
-static int arm_core_clk_set_rate(struct clk *c, unsigned long rate)
-{
- int ret;
- //set arm pll div 1
- //set_cru_bits_w_msk(0,c->div_mask,c->div_shift,c->clksel_con);
-
- CLKDATA_DBG("change clk pll %s to %lu\n", c->name, rate);
- ret = clk_set_rate_nolock(c->parent, rate);
- if (ret) {
- CLKDATA_ERR("Failed to change clk pll %s to %lu\n", c->name, rate);
- return ret;
- }
- CLKDATA_DBG("change clk pll %s to %lu OK\n", c->name, rate);
- return 0;
-}
-
-static struct clk *clk_core_pre_parents[2] = {&arm_pll_clk, &clk_core_gpll};
-static struct clk clk_dll_core = {
- .name = "dll_core",
- .parent = &arm_pll_clk,
- .gate_idx = CLK_GATE_DLL_CORE,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(4),
- CRU_DIV_SET(0x3f, 0, 64),
-};
-
-static struct clk clk_core_pre = {
- .name = "core_pre",
- .parent = &arm_pll_clk,
- .recalc = clksel_recalc_div,
- .set_rate = arm_core_clk_set_rate,
- .round_rate = core_clk_round_rate,
- .set_parent = core_clksel_set_parent,
- .clksel_con = CRU_CLKSELS_CON(0),
- CRU_DIV_SET(A9_CORE_DIV_MASK, A9_CORE_DIV_SHIFT, 32),
- CRU_SRC_SET(0x1, CORE_CLK_PLL_SEL_SHIFT),
- CRU_PARENTS_SET(clk_core_pre_parents),
-};
-
-static struct clk clk_core_periph = {
- .name = "core_periph",
- .parent = &clk_core_pre,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_CORE_PERIPH,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(1),
- CRU_DIV_SET(CORE_PERIPH_DIV_MASK, CORE_PERIPH_DIV_SHIFT, 16),
-};
-
-static struct clk clk_l2c = {
- .name = "l2c",
- .parent = &clk_core_pre,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_CLK_L2C,
-};
-
-static struct clk aclk_core_pre = {
- .name = "aclk_core_pre",
- .parent = &clk_core_pre,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_ACLK_CORE,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(1),
- CRU_DIV_SET(ACLK_CORE_DIV_MASK, ACLK_CORE_DIV_SHIFT, 8),
-};
-
-/****************cpu*******************/
-
-static struct clk *clk_cpu_div_parents[] = {&arm_pll_clk, &clk_cpu_gpll};
-/*seperate because of gating*/
-static struct clk clk_cpu_div = {
- .name = "cpu_div",
- .parent = &arm_pll_clk,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(0),
- CRU_DIV_SET(ACLK_CPU_DIV_MASK, ACLK_CPU_DIV_SHIFT, 32),
- CRU_SRC_SET(0x1, CPU_CLK_PLL_SEL_SHIFT),
- CRU_PARENTS_SET(clk_cpu_div_parents),
-};
-static struct clk aclk_cpu_pre = {
- .name = "aclk_cpu_pre",
- .parent = &clk_cpu_div,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_ACLK_CPU,
- .recalc = clksel_recalc_equal_parent,
-};
-static struct clk hclk_cpu_pre = {
- .name = "hclk_cpu_pre",
- .parent = &aclk_cpu_pre,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_HCLK_CPU,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(1),
- CRU_DIV_SET(HCLK_CPU_DIV_MASK, HCLK_CPU_DIV_SHIFT, 4),
-};
-static struct clk pclk_cpu_pre = {
- .name = "pclk_cpu_pre",
- .parent = &aclk_cpu_pre,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_PCLK_CPU,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(1),
- CRU_DIV_SET(PCLK_CPU_DIV_MASK, PCLK_CPU_DIV_SHIFT, 8),
-};
-/****************vcodec*******************/
-// FIXME
-static struct clk *clk_aclk_vepu_parents[] = SELECT_FROM_2PLLS_CG;
-static struct clk *clk_aclk_vdpu_parents[] = SELECT_FROM_2PLLS_CG;
-static struct clk aclk_vepu = {
- .name = "aclk_vepu",
- .parent = &codec_pll_clk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_ACLK_VEPU_SRC,
- .recalc = clksel_recalc_div,
- .clksel_con = CRU_CLKSELS_CON(32),
- .set_rate = clkset_rate_freediv_autosel_parents,
- .round_rate = clk_freediv_round_autosel_parents_rate,
- CRU_DIV_SET(0x1f, 0, 32),
- CRU_SRC_SET(0x1, 7),
- CRU_PARENTS_SET(clk_aclk_vepu_parents),
-};
-static struct clk aclk_vdpu = {
- .name = "aclk_vdpu",
- .parent = &clk_cpu_div,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_ACLK_VDPU_SRC,
- .recalc = clksel_recalc_div,
- .set_rate = clkset_rate_freediv_autosel_parents,
- .round_rate = clk_freediv_round_autosel_parents_rate,
- .clksel_con = CRU_CLKSELS_CON(32),
- CRU_DIV_SET(0x1f, 8, 32),
- CRU_SRC_SET(0x1, 15),
- CRU_PARENTS_SET(clk_aclk_vdpu_parents),
-};
-static struct clk hclk_vepu = {
- .name = "hclk_vepu",
- .parent = &aclk_vepu,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_HCLK_VDPU, // hclk_vdpu and hclk_vepu use the same gating
- .recalc = clksel_recalc_fixed_div4,
-};
-static struct clk hclk_vdpu = {
- .name = "hclk_vdpu",
- .parent = &aclk_vepu, // do not use aclk_vdpu as hclk_vepu/hclk_vdpu src
- .mode = gate_mode,
- .gate_idx = CLK_GATE_HCLK_VDPU,
- .recalc = clksel_recalc_fixed_div4,
-};
-
-/****************vio*******************/
-// name: lcdc0_aclk
-static struct clk *clk_aclk_lcdc_parents[] = SELECT_FROM_2PLLS_CG;
-static struct clk aclk_lcdc0_pre = {
- .name = "aclk_lcdc0_pre",
- .parent = &general_pll_clk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_ACLK_LCDC0_SRC,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(31),
- CRU_DIV_SET(0x1f, 0, 32),
- CRU_SRC_SET(0x1, 7),
- CRU_PARENTS_SET(clk_aclk_lcdc_parents),
-};
-static struct clk aclk_lcdc1_pre = {
- .name = "aclk_lcdc1_pre",
- .parent = &general_pll_clk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_ACLK_LCDC1_SRC,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(31),
- CRU_DIV_SET(0x1f, 8, 32),
- CRU_SRC_SET(0x1, 15),
- CRU_PARENTS_SET(clk_aclk_lcdc_parents),
-};
-static struct clk hclk_disp_pre = {
- .name = "hclk_disp_pre",
- .parent = &general_pll_clk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_HCLK_DISP,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(30),
- CRU_DIV_SET(0x1f, 8, 32),
- CRU_SRC_SET(0x1, 15),
- CRU_PARENTS_SET(clk_aclk_lcdc_parents),
-};
-
-/****************periph*******************/
-static struct clk *peri_aclk_parents[] = SELECT_FROM_2PLLS_GC;
-static struct clk aclk_periph_pre = {
- .name = "aclk_periph",
- .parent = &general_pll_clk,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_ACLK_PERIPH,
- .clksel_con = CRU_CLKSELS_CON(10),
- CRU_DIV_SET(PERI_ACLK_DIV_MASK, PERI_ACLK_DIV_SHIFT, 32),
- CRU_SRC_SET(0x1, PERI_PLL_SEL_SHIFT),
- CRU_PARENTS_SET(peri_aclk_parents),
-};
-
-static struct clk hclk_periph_pre = {
- .name = "hclk_periph",
- .parent = &aclk_periph_pre,
- .recalc = clksel_recalc_shift,
- .set_rate = clksel_set_rate_shift,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_HCLK_PERIPH,
- .clksel_con = CRU_CLKSELS_CON(10),
- CRU_DIV_SET(PERI_HCLK_DIV_MASK, PERI_HCLK_DIV_SHIFT, 8),
-};
-
-static struct clk pclk_periph_pre = {
- .name = "pclk_periph",
- .parent = &aclk_periph_pre,
- .recalc = clksel_recalc_shift,
- .set_rate = clksel_set_rate_shift,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_PCLK_PERIPH,
- .clksel_con = CRU_CLKSELS_CON(10),
- CRU_DIV_SET(PERI_PCLK_DIV_MASK, PERI_PCLK_DIV_SHIFT, 4),
-};
-
-static struct clk clk_crypto = {
- .name = "clk_crypto",
- .parent = &aclk_periph_pre,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(24),
- CRU_DIV_SET(0x3, 0, 4),
-};
-
-/****************timer*******************/
-static struct clk *clk_timer0_parents[] = {&xin24m, &pclk_periph_pre};
-static struct clk *clk_timer1_parents[] = {&xin24m, &pclk_periph_pre};
-static struct clk clk_timer0 = {
- .name = "timer0",
- .parent = &xin24m,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_TIMER0,
- .recalc = clksel_recalc_equal_parent,
- .clksel_con = CRU_CLKSELS_CON(2),
- CRU_SRC_SET(0x1, 4),
- CRU_PARENTS_SET(clk_timer0_parents),
-};
-static struct clk clk_timer1 = {
- .name = "timer1",
- .parent = &xin24m,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_TIMER1,
- .recalc = clksel_recalc_equal_parent,
- .clksel_con = CRU_CLKSELS_CON(2),
- CRU_SRC_SET(0x1, 5),
- CRU_PARENTS_SET(clk_timer1_parents),
-};
-/****************sdmmc*******************/
-static struct clk *clk_sdmmc0_parents[] = SELECT_FROM_2PLLS_CG;
-static struct clk clk_sdmmc0 = {
- .name = "sdmmc0",
- .parent = &general_pll_clk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_MMC0_SRC,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_even,
- .clksel_con = CRU_CLKSELS_CON(11),
- CRU_SRC_SET(0x1, 6),
- CRU_DIV_SET(0x3f, 0, 64),
- CRU_PARENTS_SET(clk_sdmmc0_parents),
-};
-#if 0
-static struct clk clk_sdmmc0_sample = {
- .name = "sdmmc0_sample",
- .parent = &general_pll_clk,
- .recalc = ,
- //.set_rate = ,
- .clksel_con = ,
- CRU_DIV_SET(, ,),
-};
-static struct clk clk_sdmmc0_drv = {
- .name = "sdmmc0_drv",
- .parent = &clk_sdmmc0,
- .recalc = ,
- //.set_rate = ,
- .clksel_con = ,
- CRU_DIV_SET(, ,),
-};
-#endif
-/****************sdio*******************/
-static struct clk *clk_sdio_parents[] = SELECT_FROM_2PLLS_CG;
-static struct clk clk_sdio = {
- .name = "sdio",
- .parent = &general_pll_clk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_SDIO_SRC,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_even,
- .clksel_con = CRU_CLKSELS_CON(12),
- CRU_SRC_SET(0x1, 6),
- CRU_DIV_SET(0x3f, 0, 64),
- CRU_PARENTS_SET(clk_sdio_parents),
-};
-#if 0
-static struct clk clk_sdio_sample = {
- .name = "sdio_sample",
- .parent = &general_pll_clk,
- .recalc = ,
- //.set_rate = ,
- .clksel_con = ,
- CRU_DIV_SET(, ,),
-};
-static struct clk clk_sdio_drv = {
- .name = "sdio_drv",
- .parent = &clk_sdio,
- .recalc = ,
- //.set_rate = ,
- .clksel_con = ,
- CRU_DIV_SET(, ,),
-};
-#endif
-/****************emmc*******************/
-static struct clk *clk_emmc_parents[] = SELECT_FROM_2PLLS_CG;
-static struct clk clk_emmc = {
- .name = "emmc",
- .parent = &general_pll_clk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_EMMC_SRC,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(12),
- CRU_SRC_SET(0x1, 7),
- CRU_DIV_SET(0x3f, 8, 64),
- CRU_PARENTS_SET(clk_emmc_parents),
-};
-#if 0
-static struct clk clk_emmc_sample = {
- .name = "emmc_sample",
- .parent = &general_pll_clk,
- .recalc = ,
- //.set_rate = ,
- .clksel_con = ,
- CRU_DIV_SET(, ,),
-};
-static struct clk clk_emmc_drv = {
- .name = "emmc_drv",
- .parent = &clk_emmc,
- .recalc = ,
- //.set_rate = ,
- .clksel_con = ,
- CRU_DIV_SET(, ,),
-};
-#endif
-/****************lcdc*******************/
-// DO NOT USE ARM_PLL
-#if 0
-static int sclk_lcdc_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret = 0;
- struct clk *parent;
-
- CLKDATA_DBG("enter %s clk=%s, rate=%lu\n", __func__, clk->name, rate);
- parent = clk->parent;
- ret = clk_set_rate_nolock(parent, rate);
- set_cru_bits_w_msk(0, clk->div_mask, clk->div_shift, clk->clksel_con);
- return ret;
-}
-#endif
-static struct clk *dclk_lcdc_parents[] = SELECT_FROM_2PLLS_CG;
-static struct clk dclk_lcdc0 = {
- .name = "dclk_lcdc0",
- .parent = &general_pll_clk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_DCLK_LCDC0_SRC,
- .recalc = clksel_recalc_div,
- .set_rate = clkset_rate_freediv_autosel_parents,
- //.set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(27),
- CRU_DIV_SET(0xff, 8, 256),
- CRU_SRC_SET(0x1, 0),
- CRU_PARENTS_SET(dclk_lcdc_parents),
-};
-static struct clk dclk_lcdc1 = {
- .name = "dclk_lcdc1",
- .parent = &general_pll_clk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_DCLK_LCDC1_SRC,
- .recalc = clksel_recalc_div,
- .set_rate = clkset_rate_freediv_autosel_parents,
- //.set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(28),
- CRU_DIV_SET(0xff, 8, 256),
- CRU_SRC_SET(0x1, 0),
- CRU_PARENTS_SET(dclk_lcdc_parents),
-};
-static struct clk *dclk_ebc_parents[] = SELECT_FROM_2PLLS_CG;
-static struct clk dclk_ebc = {
- .name = "dclk_ebc",
- .parent = &general_pll_clk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_DCLK_EBC_SRC,
- .recalc = clksel_recalc_div,
- //.set_rate = clkset_rate_freediv_autosel_parents,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(23),
- CRU_DIV_SET(0xff, 8, 256),
- CRU_SRC_SET(0x1, 0),
- CRU_PARENTS_SET(dclk_ebc_parents),
-};
-/****************gps*******************/
-#if 0
-static struct clk hclk_gps_parents = SELECT_FROM_2PLLS_CG;
-static struct clk hclk_gps = {
- .name = "hclk_gps",
- .parent = &general_pll_clk,
- .recalc = ,
- //.set_rate = ,
- .clksel_con = ,
- CRU_DIV_SET(, ,),
-};
-#endif
-/****************camera*******************/
-static int cif_out_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret = 0;
- struct clk *parent;
-
- if (rate == 24 * MHZ) {
- parent = clk->parents[1];
- } else {
- parent = clk->parents[0];
- ret = clk_set_rate_nolock(parent, rate);
- if (ret)
- return ret;
- }
- if (clk->parent != parent)
- ret = clk_set_parent_nolock(clk, parent);
-
- return ret;
-}
-static struct clk *clk_cif_out_div_parents[] = SELECT_FROM_2PLLS_CG;
-static struct clk clk_cif_out_div = {
- .name = "cif_out_div",
- .parent = &general_pll_clk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_CIF_OUT_SRC,
- .recalc = clksel_recalc_div,
- //.set_rate = clkset_rate_freediv_autosel_parents,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(29),
- CRU_SRC_SET(0x1, 0),
- CRU_DIV_SET(0x1f, 1, 32),
- CRU_PARENTS_SET(clk_cif_out_div_parents),
-};
-static struct clk *clk_cif_out_parents[] = {&clk_cif_out_div, &xin24m};
-static struct clk clk_cif_out = {
- .name = "cif0_out",
- .parent = &clk_cif_out_div,
- .set_rate = cif_out_set_rate,
- .clksel_con = CRU_CLKSELS_CON(29),
- CRU_SRC_SET(0x1, 7),
- CRU_PARENTS_SET(clk_cif_out_parents),
-};
-/*External clock*/
-static struct clk pclkin_cif0 = {
- .name = "pclkin_cif0",
- .mode = gate_mode,
- .gate_idx = CLK_GATE_PCLKIN_CIF,
-};
-
-static struct clk inv_cif0 = {
- .name = "inv_cif0",
- .parent = &pclkin_cif0,
-};
-
-static struct clk *cif0_in_parents[] = {&pclkin_cif0, &inv_cif0};
-static struct clk cif0_in = {
- .name = "cif0_in",
- .parent = &pclkin_cif0,
- .clksel_con = CRU_CLKSELS_CON(30),
- CRU_SRC_SET(0x1, 7),
- CRU_PARENTS_SET(cif0_in_parents),
-};
-/****************i2s*******************/
-#define I2S_SRC_DIV (0x0)
-#define I2S_SRC_FRAC (0x1)
-#define I2S_SRC_12M (0x2)
-
-static int i2s_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret = -EINVAL;
- struct clk *parent;
-
- if (rate == clk->parents[I2S_SRC_12M]->rate) {
- parent = clk->parents[I2S_SRC_12M];
- } else if ((long)clk_round_rate_nolock(clk->parents[I2S_SRC_DIV], rate) == rate) {
- parent = clk->parents[I2S_SRC_DIV];
- } else {
- parent = clk->parents[I2S_SRC_FRAC];
- }
-
- CLKDATA_DBG("%s %s set rate=%lu parent %s(old %s)\n",
- __func__, clk->name, rate, parent->name, clk->parent->name);
-
- if (parent != clk->parents[I2S_SRC_12M]) {
- ret = clk_set_rate_nolock(parent, rate); //div 1:1
- if (ret) {
- CLKDATA_DBG("%s set rate%lu err\n", clk->name, rate);
- return ret;
- }
- }
-
- if (clk->parent != parent) {
- ret = clk_set_parent_nolock(clk, parent);
- if (ret) {
- CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
- return ret;
- }
- }
-
- return ret;
-};
-static struct clk *clk_i2s_div_parents[] = SELECT_FROM_2PLLS_GC;
-static struct clk clk_i2s_pll = {
- .name = "i2s_pll",
- .parent = &general_pll_clk,
- .clksel_con = CRU_CLKSELS_CON(2),
- CRU_SRC_SET(0x1, 15),
- CRU_PARENTS_SET(clk_i2s_div_parents),
-};
-static int i2s_fracdiv_set_rate(struct clk *clk, unsigned long rate)
-{
- u32 numerator, denominator;
- int i = 10;
- //clk_i2s_div->clk_i2s_pll->gpll/cpll
- //clk->parent->parent
- if (frac_div_get_seting(rate, clk->parent->parent->rate,
- &numerator, &denominator) == 0) {
- clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
- while (i--) {
- cru_writel_frac((numerator - 1) << 16 | denominator, clk->clksel_con);
- mdelay(1);
- cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
- mdelay(1);
- }
- CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
- } else {
- CLKDATA_DBG("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
- return -ENOENT;
- }
- return 0;
-}
-
-
-static struct clk clk_i2s_div = {
- .name = "i2s_div",
- .parent = &clk_i2s_pll,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_I2S_SRC,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- //.round_rate = clksel_freediv_round_rate,
- .clksel_con = CRU_CLKSELS_CON(3),
- CRU_DIV_SET(0x7f, 0, 128),
-};
-static struct clk clk_i2s_frac_div = {
- .name = "i2s_frac_div",
- .parent = &clk_i2s_div,
- .recalc = clksel_recalc_frac,
- .set_rate = i2s_fracdiv_set_rate,
- //.round_rate = clksel_freediv_round_rate,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_I2S_FRAC_SRC,
- .clksel_con = CRU_CLKSELS_CON(7),
-};
-
-static struct clk *clk_i2s_parents[] = {&clk_i2s_div, &clk_i2s_frac_div, &clk_12m};
-static struct clk clk_i2s = {
- .name = "i2s",
- .parent = &clk_i2s_div,
- .set_rate = i2s_set_rate,
- .clksel_con = CRU_CLKSELS_CON(3),
- CRU_SRC_SET(0x3, 8),
- CRU_PARENTS_SET(clk_i2s_parents),
-};
-
-/****************otgphy*******************/
-#if 0
-static struct clk clk_otgphy0 = {
- .name = "otgphy0",
- .parent = &clk_12m,
- .recalc = ,
- //.set_rate = ,
- .clksel_con = ,
- CRU_DIV_SET(, ,),
-};
-static struct clk clk_otgphy1 = {
- .name = "otgphy1",
- .parent = &clk_12m,
- .recalc = ,
- //.set_rate = ,
- .clksel_con = ,
- CRU_DIV_SET(, ,),
-};
-#endif
-GATE_CLK(otgphy0, clk_12m, OTGPHY0);
-GATE_CLK(otgphy1, clk_12m, OTGPHY1);
-/****************saradc*******************/
-static struct clk clk_saradc = {
- .name = "saradc",
- .parent = &xin24m,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_SARADC_SRC,
- .clksel_con = CRU_CLKSELS_CON(24),
- CRU_DIV_SET(0xff, 8, 256),
-};
-/****************gpu_pre*******************/
-// name: gpu_aclk
-static struct clk *clk_gpu_pre_parents[] = SELECT_FROM_2PLLS_CG;
-static struct clk clk_gpu_pre = {
- .name = "gpu_pre",
- .parent = &general_pll_clk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_GPU_PRE,
- .recalc = clksel_recalc_div,
- //.set_rate = clkset_rate_freediv_autosel_parents,
- .set_rate = clksel_set_rate_freediv,
- .round_rate = clksel_freediv_round_rate,
- .clksel_con = CRU_CLKSELS_CON(34),
- CRU_SRC_SET(0x1, 8),
- CRU_DIV_SET(0x1f, 0, 32),
- CRU_PARENTS_SET(clk_gpu_pre_parents),
-};
-
-static struct clk clk_dll_gpu = {
- .name = "dll_gpu",
- .parent = &general_pll_clk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_GPU_PRE,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .round_rate = clksel_freediv_round_rate,
- .clksel_con = CRU_CLKSELS_CON(6),
- CRU_DIV_SET(0x3f, 0, 64),
- CRU_PARENTS_SET(clk_gpu_pre_parents),
-};
-/****************spi*******************/
-static struct clk *clk_spi_parents[] = SELECT_FROM_2PLLS_CG;
-static struct clk clk_spi = {
- .name = "spi",
- .parent = &general_pll_clk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_SPI0_SRC,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(25),
- CRU_SRC_SET(0x1, 8),
- CRU_DIV_SET(0x7f, 0, 128),
- CRU_PARENTS_SET(clk_spi_parents),
-};
-
-/****************uart*******************/
-static int clk_uart_fracdiv_set_rate(struct clk *clk, unsigned long rate)
-{
- u32 numerator, denominator;
- //clk_uart0_div->clk_uart_pll->gpll/cpll
- //clk->parent->parent
- if(frac_div_get_seting(rate, clk->parent->parent->rate,
- &numerator, &denominator) == 0) {
- clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
-
- cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
-
- CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
- } else {
- CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
- return -ENOENT;
- }
- return 0;
-}
-#define UART_SRC_DIV 0
-#define UART_SRC_FRAC 1
-#define UART_SRC_24M 2
-static int clk_uart_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret = 0;
- struct clk *parent;
-
- if (rate == clk->parents[UART_SRC_24M]->rate) { //24m
- parent = clk->parents[UART_SRC_24M];
- } else if ((long)clk_round_rate_nolock(clk->parents[UART_SRC_DIV], rate) == rate) {
- parent = clk->parents[UART_SRC_DIV];
- } else {
- parent = clk->parents[UART_SRC_FRAC];
- }
-
-
-
- CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
- clk->name, rate, parent->name, clk->parent->name);
-
-
- if (parent != clk->parents[UART_SRC_24M]) {
- ret = clk_set_rate_nolock(parent, rate);
- if (ret) {
- CLKDATA_DBG("%s set rate%lu err\n", clk->name, rate);
- return ret;
- }
- }
-
- if (clk->parent != parent) {
- ret = clk_set_parent_nolock(clk, parent);
- if (ret) {
- CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
- return ret;
- }
- }
-
-
- return ret;
-}
-
-
-static struct clk *clk_uart_pll_src_parents[] = SELECT_FROM_2PLLS_GC;
-static struct clk clk_uart_pll = {
- .name = "uart_pll",
- .parent = &general_pll_clk,
- .clksel_con = CRU_CLKSELS_CON(12),
- CRU_SRC_SET(0x1, 15),
- CRU_PARENTS_SET(clk_uart_pll_src_parents),
-};
-static struct clk clk_uart0_div = {
- .name = "uart0_div",
- .parent = &clk_uart_pll,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_UART0_SRC,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .round_rate = clksel_freediv_round_rate,
- .clksel_con = CRU_CLKSELS_CON(13),
- CRU_DIV_SET(0x7f, 0, 64),
-};
-static struct clk clk_uart1_div = {
- .name = "uart1_div",
- .parent = &clk_uart_pll,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_UART1_SRC,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .round_rate = clksel_freediv_round_rate,
- .clksel_con = CRU_CLKSELS_CON(14),
- CRU_DIV_SET(0x7f, 0, 64),
-};
-static struct clk clk_uart2_div = {
- .name = "uart2_div",
- .parent = &clk_uart_pll,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_UART2_SRC,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .round_rate = clksel_freediv_round_rate,
- .clksel_con = CRU_CLKSELS_CON(15),
- CRU_DIV_SET(0x7f, 0, 64),
-};
-static struct clk clk_uart0_frac_div = {
- .name = "uart0_frac_div",
- .parent = &clk_uart0_div,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_UART0_FRAC_SRC,
- .recalc = clksel_recalc_frac,
- .set_rate = clk_uart_fracdiv_set_rate,
- .clksel_con = CRU_CLKSELS_CON(17),
-};
-static struct clk clk_uart1_frac_div = {
- .name = "uart1_frac_div",
- .parent = &clk_uart1_div,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_UART1_FRAC_SRC,
- .recalc = clksel_recalc_frac,
- .set_rate = clk_uart_fracdiv_set_rate,
- .clksel_con = CRU_CLKSELS_CON(18),
-};
-static struct clk clk_uart2_frac_div = {
- .name = "uart2_frac_div",
- .parent = &clk_uart2_div,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_UART2_FRAC_SRC,
- .recalc = clksel_recalc_frac,
- .set_rate = clk_uart_fracdiv_set_rate,
- .clksel_con = CRU_CLKSELS_CON(19),
-};
-
-static struct clk *clk_uart0_parents[] = {&clk_uart0_div, &clk_uart0_frac_div, &xin24m};
-static struct clk *clk_uart1_parents[] = {&clk_uart1_div, &clk_uart1_frac_div, &xin24m};
-static struct clk *clk_uart2_parents[] = {&clk_uart2_div, &clk_uart2_frac_div, &xin24m};
-static struct clk clk_uart0 = {
- .name = "uart0",
- .parent = &xin24m,
- .set_rate = clk_uart_set_rate,
- .clksel_con = CRU_CLKSELS_CON(13),
- CRU_SRC_SET(0x3, 8),
- CRU_PARENTS_SET(clk_uart0_parents),
-};
-static struct clk clk_uart1 = {
- .name = "uart1",
- .parent = &xin24m,
- .set_rate = clk_uart_set_rate,
- .clksel_con = CRU_CLKSELS_CON(14),
- CRU_SRC_SET(0x3, 8),
- CRU_PARENTS_SET(clk_uart1_parents),
-};
-static struct clk clk_uart2 = {
- .name = "uart2",
- .parent = &xin24m,
- .set_rate = clk_uart_set_rate,
- .clksel_con = CRU_CLKSELS_CON(15),
- CRU_SRC_SET(0x3, 8),
- CRU_PARENTS_SET(clk_uart2_parents),
-};
-/****************sub clock---pre*******************/
-/*************************aclk_cpu***********************/
-GATE_CLK(aclk_intmem, aclk_cpu_pre, ACLK_INTMEM);
-GATE_CLK(aclk_strc_sys, aclk_cpu_pre, ACLK_STRC_SYS);
-
-/*************************hclk_cpu***********************/
-//FIXME
-//GATE_CLK(hclk_cpubus, hclk_cpu_pre, HCLK_CPUBUS);
-GATE_CLK(hclk_rom, hclk_cpu_pre, HCLK_ROM);
-
-/*************************pclk_cpu***********************/
-//FIXME
-GATE_CLK(pclk_hdmi, pclk_cpu_pre, PCLK_HDMI);
-GATE_CLK(pclk_acodec, pclk_cpu_pre, PCLK_ACODEC);
-GATE_CLK(pclk_ddrupctl, pclk_cpu_pre, PCLK_DDRUPCTL);
-GATE_CLK(pclk_grf, pclk_cpu_pre, PCLK_GRF);
-
-/*************************aclk_periph********************/
-GATE_CLK(aclk_peri_axi_matrix, aclk_periph_pre, ACLK_PERI_AXI_MATRIX);
-GATE_CLK(aclk_dma2, aclk_periph_pre, ACLK_DMAC2);
-GATE_CLK(aclk_peri_niu, aclk_periph_pre, ACLK_PERI_NIU);
-GATE_CLK(aclk_cpu_peri, aclk_periph_pre, ACLK_CPU_PERI);
-GATE_CLK(aclk_gps, aclk_periph_pre, ACLK_GPS);
-
-/*************************hclk_periph***********************/
-GATE_CLK(hclk_peri_axi_matrix, hclk_periph_pre, HCLK_PERI_AXI_MATRIX);
-GATE_CLK(hclk_usb_peri, hclk_periph_pre, HCLK_USB_PERI);
-GATE_CLK(hclk_otg0, clk_hclk_usb_peri, HCLK_OTG0); // is not parent in clk tree, but when hclk_otg0/1 open,
-GATE_CLK(hclk_otg1, clk_hclk_usb_peri, HCLK_OTG1); // called hclk_otg20; must open hclk_usb_peri
-GATE_CLK(hclk_i2s, hclk_periph_pre, HCLK_I2S);
-GATE_CLK(hclk_peri_ahb_arbi, hclk_periph_pre, HCLK_PERI_ARBI);
-GATE_CLK(nandc, hclk_periph_pre, HCLK_NANDC);
-GATE_CLK(hclk_crypto, hclk_periph_pre, HCLK_CRYPTO);
-GATE_CLK(hclk_sdmmc0, hclk_periph_pre, HCLK_SDMMC0);
-GATE_CLK(hclk_sdio, hclk_periph_pre, HCLK_SDIO);
-GATE_CLK(hclk_emmc, hclk_periph_pre, HCLK_EMMC);
-GATE_CLK(hclk_emem_peri, hclk_periph_pre, HCLK_EMEM_PERI);
-
-/*************************pclk_periph***********************/
-GATE_CLK(pclk_peri_axi_matrix, pclk_periph_pre, PCLK_PERI_AXI_MATRIX);
-GATE_CLK(pclk_spi0, pclk_periph_pre, PCLK_SPI0);
-GATE_CLK(pclk_uart0, pclk_periph_pre, PCLK_UART0);
-GATE_CLK(pclk_uart1, pclk_periph_pre, PCLK_UART1);
-GATE_CLK(pclk_uart2, pclk_periph_pre, PCLK_UART2);
-GATE_CLK(pclk_pwm01, pclk_periph_pre, PCLK_PWM01);
-GATE_CLK(pclk_wdt, pclk_periph_pre, PCLK_WDT);
-GATE_CLK(pclk_i2c0, pclk_periph_pre, PCLK_I2C0);
-GATE_CLK(pclk_i2c1, pclk_periph_pre, PCLK_I2C1);
-GATE_CLK(pclk_i2c2, pclk_periph_pre, PCLK_I2C2);
-GATE_CLK(pclk_i2c3, pclk_periph_pre, PCLK_I2C3);
-GATE_CLK(pclk_saradc, pclk_periph_pre, PCLK_SARADC);
-GATE_CLK(pclk_efuse, pclk_periph_pre, PCLK_EFUSE);
-GATE_CLK(pclk_timer0, pclk_periph_pre, PCLK_TIMER0);
-GATE_CLK(pclk_timer1, pclk_periph_pre, PCLK_TIMER1);
-GATE_CLK(gpio0, pclk_periph_pre, PCLK_GPIO0);
-GATE_CLK(gpio1, pclk_periph_pre, PCLK_GPIO1);
-GATE_CLK(gpio2, pclk_periph_pre, PCLK_GPIO2);
-GATE_CLK(gpio3, pclk_periph_pre, PCLK_GPIO3);
-
-/*************************aclk_lcdc0***********************/
-GATE_CLK(aclk_vio0_niu, aclk_lcdc0_pre, ACLK_VIO0);
-GATE_CLK(aclk_lcdc0, clk_aclk_vio0_niu, ACLK_LCDC0);
-GATE_CLK(aclk_cif0, clk_aclk_vio0_niu, ACLK_CIF);
-GATE_CLK(aclk_rga, clk_aclk_vio0_niu, ACLK_RGA);
-
-/*************************aclk_lcdc1***********************/
-GATE_CLK(aclk_vio1_niu, aclk_lcdc1_pre, ACLK_VIO1);
-GATE_CLK(aclk_lcdc1, clk_aclk_vio1_niu, ACLK_LCDC1);
-GATE_CLK(aclk_iep, clk_aclk_vio1_niu, ACLK_IEP);
-
-/*************************hclk_disp***********************/
-GATE_CLK(hclk_rga, hclk_disp_pre, HCLK_RGA);
-GATE_CLK(hclk_lcdc0, hclk_disp_pre, HCLK_LCDC0);
-GATE_CLK(hclk_lcdc1, hclk_disp_pre, HCLK_LCDC1);
-GATE_CLK(hclk_iep, hclk_disp_pre, HCLK_IEP);
-GATE_CLK(hclk_vio_bus, hclk_disp_pre, HCLK_VIO_BUS);
-GATE_CLK(hclk_cif0, hclk_disp_pre, HCLK_CIF);
-GATE_CLK(hclk_ebc, hclk_disp_pre, HCLK_EBC);
-
-/* Power domain, not exist in fact*/
-enum pmu_power_domain {
- PD_A9_0 = 0,
- PD_A9_1,
- PD_ALIVE,
- PD_RTC,
- PD_SCU,
- PD_CPU,
- PD_PERI = 6,
- PD_VIO,
- PD_VIDEO,
- PD_VCODEC = PD_VIDEO,
- PD_GPU,
- PD_DBG,
-};
-
-static int pm_off_mode(struct clk *clk, int on)
-{
- return 0;
-}
-static struct clk pd_peri = {
- .name = "pd_peri",
- .flags = IS_PD,
- .mode = pm_off_mode,
- .gate_idx = PD_PERI,
-};
-
-static int pd_display_mode(struct clk *clk, int on)
-{
- return 0;
-}
-
-static struct clk pd_display = {
- .name = "pd_display",
- .flags = IS_PD,
- .mode = pd_display_mode,
- .gate_idx = PD_VIO,
-};
-
-static struct clk pd_lcdc0 = {
- .parent = &pd_display,
- .name = "pd_lcdc0",
-};
-static struct clk pd_lcdc1 = {
- .parent = &pd_display,
- .name = "pd_lcdc1",
-};
-static struct clk pd_cif0 = {
- .parent = &pd_display,
- .name = "pd_cif0",
-};
-static struct clk pd_cif1 = {
- .parent = &pd_display,
- .name = "pd_cif1",
-};
-static struct clk pd_rga = {
- .parent = &pd_display,
- .name = "pd_rga",
-};
-static struct clk pd_ipp = {
- .parent = &pd_display,
- .name = "pd_ipp",
-};
-static int pd_video_mode(struct clk *clk, int on)
-{
- return 0;
-}
-
-static struct clk pd_video = {
- .name = "pd_video",
- .flags = IS_PD,
- .mode = pd_video_mode,
- .gate_idx = PD_VIDEO,
-};
-
-static int pd_gpu_mode(struct clk *clk, int on)
-{
- return 0;
-}
-
-static struct clk pd_gpu = {
- .name = "pd_gpu",
- .flags = IS_PD,
- .mode = pd_gpu_mode,
- .gate_idx = PD_GPU,
-};
-static struct clk pd_dbg = {
- .name = "pd_dbg",
- .flags = IS_PD,
- .mode = pm_off_mode,
- .gate_idx = PD_DBG,
-};
-
-#define PD_CLK(name) \
-{\
- .dev_id = NULL,\
- .con_id = #name,\
- .clk = &name,\
-}
-/* Power domain END, not exist in fact*/
-
-#define CLK(dev, con, ck) \
-{\
- .dev_id = dev,\
- .con_id = con,\
- .clk = ck,\
-}
-
-#define CLK_GATE_NODEV(name) \
-{\
- .dev_id = NULL,\
- .con_id = #name,\
- .clk = &clk_##name,\
-}
-
-static struct clk_lookup clks[] = {
- CLK(NULL, "xin24m", &xin24m),
- CLK(NULL, "xin12m", &clk_12m),
-
- CLK(NULL, "arm_pll", &arm_pll_clk),
- CLK(NULL, "ddr_pll", &ddr_pll_clk),
- CLK(NULL, "codec_pll", &codec_pll_clk),
- CLK(NULL, "general_pll", &general_pll_clk),
-
- CLK_GATE_NODEV(ddrphy_src),
- CLK_GATE_NODEV(ddrphy_gpll_src),
- CLK_GATE_NODEV(core_gpll),
- CLK_GATE_NODEV(cpu_gpll),
- CLK(NULL, "ddr_pllsel", &clk_ddr_pllsel),
- CLK(NULL, "ddrdll", &clk_ddr_dll),
- CLK(NULL, "ddrphy2x", &clk_ddrphy2x),
- CLK(NULL, "ddr", &clk_ddrc),
- CLK(NULL, "ddrphy", &clk_ddrphy),
-
- CLK(NULL, "cpu", &clk_core_pre),
- CLK("smp_twd", NULL, &clk_core_periph),
- CLK(NULL, "l2c", &clk_l2c),
- CLK(NULL, "aclk_core_pre", &aclk_core_pre),
- CLK(NULL, "coredll", &clk_dll_core),
-
- CLK(NULL, "cpu_div", &clk_cpu_div),
- CLK(NULL, "aclk_cpu_pre", &aclk_cpu_pre),
- CLK(NULL, "pclk_cpu_pre", &pclk_cpu_pre),
- CLK(NULL, "hclk_cpu_pre", &hclk_cpu_pre),
-
- CLK(NULL, "aclk_vepu", &aclk_vepu),
- CLK(NULL, "aclk_vdpu", &aclk_vdpu),
- CLK(NULL, "hclk_vepu", &hclk_vepu),
- CLK(NULL, "hclk_vdpu", &hclk_vdpu),
-
- CLK(NULL, "aclk_lcdc0_pre", &aclk_lcdc0_pre),
- CLK(NULL, "aclk_lcdc1_pre", &aclk_lcdc1_pre),
- CLK(NULL, "hclk_lcdc1_pre", &hclk_disp_pre),
-
- CLK(NULL, "aclk_periph_pre", &aclk_periph_pre),
- CLK(NULL, "pclk_periph_pre", &pclk_periph_pre),
- CLK(NULL, "hclk_periph_pre", &hclk_periph_pre),
-
- CLK(NULL, "crypto", &clk_crypto),
-
- CLK(NULL, "timer0", &clk_timer0),
- CLK(NULL, "timer1", &clk_timer1),
-
- CLK("rk29_sdmmc.0", "mmc", &clk_sdmmc0),
- //CLK("rk29_sdmmc.0", "mmc_sample", &clk_sdmmc0_sample),
- //CLK("rk29_sdmmc.0", "mmc_drv", &clk_sdmmc0_drv),
-
- CLK("rk29_sdmmc.1", "mmc", &clk_sdio),
- //CLK("rk29_sdmmc.1", "mmc_sample", &clk_sdio_sample),
- //CLK("rk29_sdmmc.1", "mmc_drv", &clk_sdio_drv),
-
- CLK(NULL, "emmc", &clk_emmc),
- //CLK(NULL, "emmc_sample", &clk_emmc_sample),
- //CLK(NULL, "emmc_drv", &clk_emmc_drv),
-
- CLK(NULL, "dclk_lcdc0", &dclk_lcdc0),
- CLK(NULL, "dclk_lcdc1", &dclk_lcdc1),
- CLK(NULL, "dclk_ebc", &dclk_ebc),
-
- CLK(NULL, "cif_out_div", &clk_cif_out_div),
- CLK(NULL, "cif0_out", &clk_cif_out),
- CLK(NULL, "pclkin_cif0", &pclkin_cif0),
- CLK(NULL, "inv_cif0", &inv_cif0),
- CLK(NULL, "cif0_in", &cif0_in),
-
- CLK(NULL, "i2s_pll", &clk_i2s_pll),
- CLK("rk29_i2s.0", "i2s_div", &clk_i2s_div),
- CLK("rk29_i2s.0", "i2s_frac_div", &clk_i2s_frac_div),
- CLK("rk29_i2s.0", "i2s", &clk_i2s),
-
- CLK(NULL, "otgphy0", &clk_otgphy0),
- CLK(NULL, "otgphy1", &clk_otgphy1),
- CLK(NULL, "saradc", &clk_saradc),
- CLK(NULL, "gpudll", &clk_dll_gpu),
- CLK(NULL, "gpu", &clk_gpu_pre),
-
- CLK("rk29xx_spim.0", "spi", &clk_spi),
-
- CLK(NULL, "uart_pll", &clk_uart_pll),
- CLK("rk_serial.0", "uart_div", &clk_uart0_div),
- CLK("rk_serial.1", "uart_div", &clk_uart1_div),
- CLK("rk_serial.2", "uart_div", &clk_uart2_div),
- CLK("rk_serial.0", "uart_frac_div", &clk_uart0_frac_div),
- CLK("rk_serial.1", "uart_frac_div", &clk_uart1_frac_div),
- CLK("rk_serial.2", "uart_frac_div", &clk_uart2_frac_div),
- CLK("rk_serial.0", "uart", &clk_uart0),
- CLK("rk_serial.1", "uart", &clk_uart1),
- CLK("rk_serial.2", "uart", &clk_uart2),
-
- /*********fixed clock ******/
- CLK_GATE_NODEV(aclk_intmem),
- CLK_GATE_NODEV(aclk_strc_sys),
-
- CLK_GATE_NODEV(hclk_rom),
-
- CLK_GATE_NODEV(pclk_hdmi),
- CLK_GATE_NODEV(pclk_acodec),
- CLK_GATE_NODEV(pclk_ddrupctl),
- CLK_GATE_NODEV(pclk_grf),
-
- CLK_GATE_NODEV(aclk_peri_axi_matrix),
- CLK_GATE_NODEV(aclk_dma2),
- CLK_GATE_NODEV(aclk_peri_niu),
- CLK_GATE_NODEV(aclk_cpu_peri),
- CLK_GATE_NODEV(aclk_gps),
-
- CLK_GATE_NODEV(hclk_peri_axi_matrix),
- CLK_GATE_NODEV(hclk_usb_peri),
- CLK_GATE_NODEV(hclk_otg0),
- CLK_GATE_NODEV(hclk_otg1),
- CLK_GATE_NODEV(hclk_i2s),
- CLK_GATE_NODEV(hclk_peri_ahb_arbi),
- CLK_GATE_NODEV(nandc),
- CLK_GATE_NODEV(hclk_crypto),
- CLK("rk29_sdmmc.0", "hclk_mmc", &clk_hclk_sdmmc0),
- CLK("rk29_sdmmc.1", "hclk_mmc", &clk_hclk_sdio),
- CLK(NULL, "hclk_emmc", &clk_hclk_emmc),
- CLK_GATE_NODEV(hclk_emem_peri),
-
- CLK_GATE_NODEV(pclk_peri_axi_matrix),
- CLK("rk29xx_spim.0", "pclk_spi", &clk_pclk_spi0),
- CLK("rk_serial.0", "pclk_uart", &clk_pclk_uart0),
- CLK("rk_serial.1", "pclk_uart", &clk_pclk_uart1),
- CLK("rk_serial.2", "pclk_uart", &clk_pclk_uart2),
- CLK(NULL, "pwm01", &clk_pclk_pwm01),
- CLK_GATE_NODEV(pclk_wdt),
- CLK("rk30_i2c.0", "i2c", &clk_pclk_i2c0),
- CLK("rk30_i2c.1", "i2c", &clk_pclk_i2c1),
- CLK("rk30_i2c.2", "i2c", &clk_pclk_i2c2),
- CLK("rk30_i2c.3", "i2c", &clk_pclk_i2c3),
- CLK_GATE_NODEV(pclk_saradc),
- CLK_GATE_NODEV(pclk_efuse),
- CLK_GATE_NODEV(pclk_timer0),
- CLK_GATE_NODEV(pclk_timer1),
- CLK_GATE_NODEV(gpio0),
- CLK_GATE_NODEV(gpio1),
- CLK_GATE_NODEV(gpio2),
- CLK_GATE_NODEV(gpio3),
-
- CLK_GATE_NODEV(aclk_vio0_niu),
- CLK_GATE_NODEV(aclk_lcdc0),
- CLK_GATE_NODEV(aclk_cif0),
- CLK_GATE_NODEV(aclk_rga),
-
- CLK_GATE_NODEV(aclk_vio1_niu),
- CLK_GATE_NODEV(aclk_lcdc1),
- CLK_GATE_NODEV(aclk_iep),
-
- CLK_GATE_NODEV(hclk_rga),
- CLK_GATE_NODEV(hclk_lcdc0),
- CLK_GATE_NODEV(hclk_lcdc1),
- CLK_GATE_NODEV(hclk_iep),
- CLK_GATE_NODEV(hclk_vio_bus),
- CLK_GATE_NODEV(hclk_cif0),
- CLK_GATE_NODEV(hclk_ebc),
-
- /* Power domain, not exist in fact*/
- PD_CLK(pd_peri),
- PD_CLK(pd_display),
- PD_CLK(pd_video),
- PD_CLK(pd_lcdc0),
- PD_CLK(pd_lcdc1),
- PD_CLK(pd_cif0),
- PD_CLK(pd_cif1),
- PD_CLK(pd_rga),
- PD_CLK(pd_ipp),
- PD_CLK(pd_video),
- PD_CLK(pd_gpu),
- PD_CLK(pd_dbg),
-
-};
-
-static void __init rk30_init_enable_clocks(void)
-{
- CLKDATA_DBG("ENTER %s\n", __func__);
- // core
- clk_enable_nolock(&clk_core_pre);
- clk_enable_nolock(&clk_core_periph);
- clk_enable_nolock(&clk_l2c);
- clk_enable_nolock(&aclk_core_pre);
-
- // logic
- clk_enable_nolock(&aclk_cpu_pre);
- clk_enable_nolock(&hclk_cpu_pre);
- clk_enable_nolock(&pclk_cpu_pre);
-
- // ddr
- clk_enable_nolock(&clk_ddrc);
- clk_enable_nolock(&clk_ddrphy);
- clk_enable_nolock(&clk_ddrphy2x);
-
- clk_enable_nolock(&aclk_periph_pre);
- clk_enable_nolock(&pclk_periph_pre);
- clk_enable_nolock(&hclk_periph_pre);
-
- // others
- //clk_enable_nolock(&clk_aclk_vio0_niu);
- clk_enable_nolock(&clk_pclk_pwm01);
- clk_enable_nolock(&clk_hclk_otg0);
- clk_enable_nolock(&clk_hclk_otg1);
-
-#if CONFIG_RK_DEBUG_UART == 0
- clk_enable_nolock(&clk_uart0);
- clk_enable_nolock(&clk_pclk_uart0);
-
-#elif CONFIG_RK_DEBUG_UART == 1
- clk_enable_nolock(&clk_uart1);
- clk_enable_nolock(&clk_pclk_uart1);
-
-#elif CONFIG_RK_DEBUG_UART == 2
- clk_enable_nolock(&clk_uart2);
- clk_enable_nolock(&clk_pclk_uart2);
-#endif
-
- if (flag_uboot_display) {
- clk_enable_nolock(&dclk_lcdc0);
- clk_enable_nolock(&dclk_lcdc1);
- clk_enable_nolock(&clk_hclk_lcdc0);
- clk_enable_nolock(&clk_hclk_lcdc1);
- clk_enable_nolock(&clk_aclk_lcdc0);
- clk_enable_nolock(&clk_aclk_lcdc1);
- clk_enable_nolock(&aclk_lcdc0_pre);
- clk_enable_nolock(&aclk_lcdc1_pre);
- clk_enable_nolock(&pd_lcdc0);
- clk_enable_nolock(&pd_lcdc1);
- }
- /*************************aclk_cpu***********************/
- clk_enable_nolock(&clk_aclk_intmem);
- clk_enable_nolock(&clk_aclk_strc_sys);
-
- /*************************hclk_cpu***********************/
- clk_enable_nolock(&clk_hclk_rom);
-
- /*************************pclk_cpu***********************/
- clk_enable_nolock(&clk_pclk_ddrupctl);
- clk_enable_nolock(&clk_pclk_grf);
-
- /*************************aclk_periph***********************/
- clk_enable_nolock(&clk_aclk_dma2);
- clk_enable_nolock(&clk_aclk_peri_niu);
- clk_enable_nolock(&clk_aclk_cpu_peri);
- clk_enable_nolock(&clk_aclk_peri_axi_matrix);
-
- /*************************hclk_periph***********************/
- clk_enable_nolock(&clk_hclk_peri_axi_matrix);
- clk_enable_nolock(&clk_hclk_peri_ahb_arbi);
- clk_enable_nolock(&clk_nandc);
-
- /*************************pclk_periph***********************/
- clk_enable_nolock(&clk_pclk_peri_axi_matrix);
- /*************************hclk_vio***********************/
- clk_enable_nolock(&clk_hclk_vio_bus);
-}
-
-
-static void rk_dump_clock(struct clk *clk, int deep, const struct list_head *root_clocks)
-{
- struct clk *ck;
- int i;
- unsigned long rate = clk->rate;
- for (i = 0; i < deep; i++)
- printk(" ");
-
- printk("%-11s ", clk->name);
- if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
- int idx = clk->gate_idx;
- u32 v;
- v = cru_readl(CLK_GATE_CLKID_CONS(idx)) & ((0x1) << (idx % 16));
- printk("%s ", v ? "off" : "on ");
- }
-
- if (clk->pll) {
- u32 pll_mode;
- u32 pll_id = clk->pll->id;
- pll_mode = cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id);
- if (pll_mode == (PLL_MODE_SLOW(pll_id) & PLL_MODE_MSK(pll_id)))
- printk("slow ");
- else if (pll_mode == (PLL_MODE_NORM(pll_id) & PLL_MODE_MSK(pll_id)))
- printk("normal ");
- //else if (pll_mode == (PLL_MODE_DEEP(pll_id) & PLL_MODE_MSK(pll_id)))
- // printk("deep ");
-
- if (cru_readl(PLL_CONS(pll_id, 3)) & PLL_BYPASS)
- printk("bypass ");
- } else if (clk == &clk_ddrc) {
- rate = clk->recalc(clk);
- }
-
- if (rate >= MHZ) {
- if (rate % MHZ)
- printk("%ld.%06ld MHz", rate / MHZ, rate % MHZ);
- else
- printk("%ld MHz", rate / MHZ);
- } else if (rate >= KHZ) {
- if (rate % KHZ)
- printk("%ld.%03ld KHz", rate / KHZ, rate % KHZ);
- else
- printk("%ld KHz", rate / KHZ);
- } else {
- printk("%ld Hz", rate);
- }
-
- printk(" usecount = %d", clk->usecount);
-
- if (clk->parent)
- printk(" parent = %s", clk->parent->name);
-
- if (clk->last_set_rate != 0)
- printk(" [set %lu Hz]", clk->last_set_rate);
-
- printk("\n");
-
- list_for_each_entry(ck, root_clocks, node) {
- if (ck->parent == clk)
- rk_dump_clock(ck, deep + 1, root_clocks);
- }
-}
-
-#if 1
-extern struct list_head *get_rk_clocks_head(void);
-
-void rk_dump_clock_info(void)
-{
- struct clk *clk;
- list_for_each_entry(clk, get_rk_clocks_head(), node) {
- if (!clk->parent)
- rk_dump_clock(clk, 0, get_rk_clocks_head());
- }
-}
-#endif
-static struct clk def_ops_clk = {
- .get_parent = clksel_get_parent,
- .set_parent = clksel_set_parent,
-};
-
-#ifdef CONFIG_PROC_FS
-static void dump_clock(struct seq_file *s, struct clk *clk, int deep, const struct list_head *root_clocks)
-{
- struct clk *ck;
- int i;
- unsigned long rate = clk->rate;
- //CLKDATA_DBG("dump_clock %s\n",clk->name);
- for (i = 0; i < deep; i++)
- seq_printf(s, " ");
-
- seq_printf(s, "%-11s ", clk->name);
-
- if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
- int idx = clk->gate_idx;
- u32 v;
- v = cru_readl(CLK_GATE_CLKID_CONS(idx)) & ((0x1) << (idx % 16));
- seq_printf(s, "%s ", v ? "off" : "on ");
- }
-
- if (clk->pll) {
- u32 pll_mode;
- u32 pll_id = clk->pll->id;
- pll_mode = cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id);
- if (pll_mode == (PLL_MODE_SLOW(pll_id) & PLL_MODE_MSK(pll_id)))
- seq_printf(s, "slow ");
- else if (pll_mode == (PLL_MODE_NORM(pll_id) & PLL_MODE_MSK(pll_id)))
- seq_printf(s, "normal ");
- if (cru_readl(PLL_CONS(pll_id, 3)) & PLL_BYPASS)
- seq_printf(s, "bypass ");
- } else if (clk == &ddr_pll_clk) {
- rate = clk->recalc(clk);
- }
-
- if (rate >= MHZ) {
- if (rate % MHZ)
- seq_printf(s, "%ld.%06ld MHz", rate / MHZ, rate % MHZ);
- else
- seq_printf(s, "%ld MHz", rate / MHZ);
- } else if (rate >= KHZ) {
- if (rate % KHZ)
- seq_printf(s, "%ld.%03ld KHz", rate / KHZ, rate % KHZ);
- else
- seq_printf(s, "%ld KHz", rate / KHZ);
- } else {
- seq_printf(s, "%ld Hz", rate);
- }
-
- seq_printf(s, " usecount = %d", clk->usecount);
-
- if (clk->parent)
- seq_printf(s, " parent = %s", clk->parent->name);
-
- if (clk->last_set_rate != 0)
- seq_printf(s, " [set %lu Hz]", clk->last_set_rate);
-
- seq_printf(s, "\n");
-
- list_for_each_entry(ck, root_clocks, node) {
- if (ck->parent == clk)
- dump_clock(s, ck, deep + 1, root_clocks);
- }
-}
-
-static void dump_regs(struct seq_file *s)
-{
- int i = 0;
- seq_printf(s, "\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
- seq_printf(s, "\nPLLRegisters:\n");
- for (i = 0; i < END_PLL_ID; i++) {
- seq_printf(s, "pll%d :cons:%x,%x,%x,%x\n", i,
- cru_readl(PLL_CONS(i, 0)),
- cru_readl(PLL_CONS(i, 1)),
- cru_readl(PLL_CONS(i, 2)),
- cru_readl(PLL_CONS(i, 3))
- );
- }
- seq_printf(s, "MODE :%x\n", cru_readl(CRU_MODE_CON));
-
- for (i = 0; i < CRU_CLKSELS_CON_CNT; i++) {
- seq_printf(s, "CLKSEL%d :%x\n", i, cru_readl(CRU_CLKSELS_CON(i)));
- }
- for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
- seq_printf(s, "CLKGATE%d :%x\n", i, cru_readl(CRU_CLKGATES_CON(i)));
- }
- seq_printf(s, "GLB_SRST_FST:%x\n", cru_readl(CRU_GLB_SRST_FST));
- seq_printf(s, "GLB_SRST_SND:%x\n", cru_readl(CRU_GLB_SRST_SND));
-
- for (i = 0; i < CRU_SOFTRSTS_CON_CNT; i++) {
- seq_printf(s, "CLKGATE%d :%x\n", i, cru_readl(CRU_SOFTRSTS_CON(i)));
- }
- seq_printf(s, "CRU MISC :%x\n", cru_readl(CRU_MISC_CON));
- seq_printf(s, "GLB_CNT_TH :%x\n", cru_readl(CRU_GLB_CNT_TH));
-
-}
-
-void rk30_clk_dump_regs(void)
-{
- int i = 0;
- CLKDATA_DBG("\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
- CLKDATA_DBG("\nPLLRegisters:\n");
- for (i = 0; i < END_PLL_ID; i++) {
- CLKDATA_DBG("pll%d :cons:%x,%x,%x,%x\n", i,
- cru_readl(PLL_CONS(i, 0)),
- cru_readl(PLL_CONS(i, 1)),
- cru_readl(PLL_CONS(i, 2)),
- cru_readl(PLL_CONS(i, 3))
- );
- }
- CLKDATA_DBG("MODE :%x\n", cru_readl(CRU_MODE_CON));
-
- for (i = 0; i < CRU_CLKSELS_CON_CNT; i++) {
- CLKDATA_DBG("CLKSEL%d :%x\n", i, cru_readl(CRU_CLKSELS_CON(i)));
- }
- for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
- CLKDATA_DBG("CLKGATE%d :%x\n", i, cru_readl(CRU_CLKGATES_CON(i)));
- }
- CLKDATA_DBG("GLB_SRST_FST:%x\n", cru_readl(CRU_GLB_SRST_FST));
- CLKDATA_DBG("GLB_SRST_SND:%x\n", cru_readl(CRU_GLB_SRST_SND));
-
- for (i = 0; i < CRU_SOFTRSTS_CON_CNT; i++) {
- CLKDATA_DBG("SOFTRST%d :%x\n", i, cru_readl(CRU_SOFTRSTS_CON(i)));
- }
- CLKDATA_DBG("CRU MISC :%x\n", cru_readl(CRU_MISC_CON));
- CLKDATA_DBG("GLB_CNT_TH :%x\n", cru_readl(CRU_GLB_CNT_TH));
-
-}
-
-#ifdef CONFIG_PROC_FS
-static void dump_clock(struct seq_file *s, struct clk *clk, int deep, const struct list_head *root_clocks);
-struct clk_dump_ops dump_ops = {
- .dump_clk = dump_clock,
- .dump_regs = dump_regs,
-};
-#endif
-#endif
-
-static void periph_clk_set_init(void)
-{
- unsigned long aclk_p, hclk_p, pclk_p;
- unsigned long gpll_rate = general_pll_clk.rate;
- //aclk 148.5
-
- /* general pll */
- switch (gpll_rate) {
- case 148500* KHZ:
- aclk_p = 148500 * KHZ;
- hclk_p = aclk_p >> 1;
- pclk_p = aclk_p >> 2;
- break;
- case 1188*MHZ:
- aclk_p = gpll_rate >> 3; // 0
- hclk_p = aclk_p >> 1;
- pclk_p = aclk_p >> 2;
- break;
-
- case 768 * MHZ:
- aclk_p = gpll_rate >> 2;
- hclk_p = aclk_p >> 1;
- pclk_p = aclk_p >> 2;
- break;
-
- case 297 * MHZ:
- aclk_p = gpll_rate >> 0;
- hclk_p = aclk_p >> 1;
- pclk_p = aclk_p >> 1;
- break;
-
- case 300 * MHZ:
- aclk_p = gpll_rate >> 1;
- hclk_p = aclk_p >> 0;
- pclk_p = aclk_p >> 1;
- break;
- default:
- aclk_p = 150 * MHZ;
- hclk_p = 150 * MHZ;
- pclk_p = 75 * MHZ;
- break;
- }
- clk_set_parent_nolock(&aclk_periph_pre, &general_pll_clk);
- clk_set_rate_nolock(&aclk_periph_pre, aclk_p);
- clk_set_rate_nolock(&hclk_periph_pre, hclk_p);
- clk_set_rate_nolock(&pclk_periph_pre, pclk_p);
-}
-
-static void cpu_axi_init(void)
-{
- unsigned long aclk_cpu_rate, hclk_cpu_rate, pclk_cpu_rate;
- unsigned long gpll_rate = general_pll_clk.rate;
- switch (gpll_rate) {
- case 297 * MHZ:
- aclk_cpu_rate = gpll_rate >> 0;
- hclk_cpu_rate = aclk_cpu_rate >> 1;
- pclk_cpu_rate = aclk_cpu_rate >> 2;
- break;
-
- case 768 * MHZ:
- aclk_cpu_rate = gpll_rate >> 2;
- hclk_cpu_rate = aclk_cpu_rate >> 1;
- pclk_cpu_rate = aclk_cpu_rate >> 2;
- break;
-
- default:
- aclk_cpu_rate = 150 * MHZ;
- hclk_cpu_rate = 150 * MHZ;
- pclk_cpu_rate = 75 * MHZ;
- break;
- }
-
- clk_set_parent_nolock(&clk_cpu_div, &clk_cpu_gpll);
- clk_set_rate_nolock(&clk_cpu_div, aclk_cpu_rate);
- //clk_set_rate_nolock(&aclk_cpu_pre, aclk_cpu_rate);
- clk_set_rate_nolock(&hclk_cpu_pre, hclk_cpu_rate);
- clk_set_rate_nolock(&pclk_cpu_pre, pclk_cpu_rate);
-}
-
-#define CLK_FLG_MAX_I2S_12288KHZ (1<<1)
-#define CLK_FLG_MAX_I2S_22579_2KHZ (1<<2)
-#define CLK_FLG_MAX_I2S_24576KHZ (1<<3)
-#define CLK_FLG_MAX_I2S_49152KHZ (1<<4)
-
-void rk2928_clock_common_i2s_init(void)
-{
- unsigned long i2s_rate;
- //struct clk *max_clk,*min_clk;
- //20 times
- if (rk2928_clock_flags & CLK_FLG_MAX_I2S_49152KHZ) {
- i2s_rate = 49152000;
-
- } else if (rk2928_clock_flags & CLK_FLG_MAX_I2S_24576KHZ) {
- i2s_rate = 24576000;
-
- } else if (rk2928_clock_flags & CLK_FLG_MAX_I2S_22579_2KHZ) {
- i2s_rate = 22579000;
-
- } else if (rk2928_clock_flags & CLK_FLG_MAX_I2S_12288KHZ) {
- i2s_rate = 12288000;
-
- } else {
- i2s_rate = 49152000;
- }
-
- if (((i2s_rate * 20) <= codec_pll_clk.rate)
- || !(codec_pll_clk.rate % i2s_rate)) {
- clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
-
- } else if (((i2s_rate * 20) <= general_pll_clk.rate)
- || !(general_pll_clk.rate % i2s_rate)) {
- clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
-
- } else {
- if (general_pll_clk.rate > codec_pll_clk.rate)
- clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
- else
- clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
- }
-
-}
-static void inline clock_set_max_div(struct clk *clk)
-{
- set_cru_bits_w_msk(clk->div_max - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
-}
-static void div_clk_for_pll_init(void)
-{
- clock_set_max_div(&clk_cpu_div);
- clock_set_max_div(&aclk_vdpu);
- clock_set_max_div(&aclk_vepu);
- clock_set_max_div(&clk_gpu_pre);
- if (!flag_uboot_display) {
- clock_set_max_div(&aclk_lcdc0_pre);
- clock_set_max_div(&aclk_lcdc1_pre);
- clock_set_max_div(&dclk_lcdc0);
- clock_set_max_div(&dclk_lcdc1);
- }
- clock_set_max_div(&aclk_periph_pre);
- clock_set_max_div(&clk_cif_out_div);
- clock_set_max_div(&clk_i2s_div);
- //clock_set_max_div(&clk_spdif_div);
- clock_set_max_div(&clk_uart0_div);
- clock_set_max_div(&clk_uart1_div);
- clock_set_max_div(&clk_uart2_div);
- //clock_set_max_div(&clk_uart3_div);
- //clock_set_max_div(&clk_hsicphy_12m);
- //clock_set_max_div(&clk_hsadc_pll_div);
- clock_set_max_div(&clk_saradc);
-}
-static void __init rk2928_clock_common_init(unsigned long gpll_rate, unsigned long cpll_rate)
-{
-
- //general
- if (!flag_uboot_display)
- clk_set_rate_nolock(&general_pll_clk, gpll_rate);
- //code pll
- if (!flag_uboot_display)
- clk_set_rate_nolock(&codec_pll_clk, cpll_rate);
-
- cpu_axi_init();
-
- clk_set_rate_nolock(&clk_core_pre, 600 * MHZ);
-
- //periph clk
- periph_clk_set_init();
-
- //i2s
- rk2928_clock_common_i2s_init();
-
- // spi
- clk_set_rate_nolock(&clk_spi, clk_spi.parent->rate);
-
- // uart
-#if 0
- clk_set_parent_nolock(&clk_uart_pll, &codec_pll_clk);
-#else
- clk_set_parent_nolock(&clk_uart_pll, &general_pll_clk);
-#endif
- //mac
- // FIXME
-#if 0
- if(!(gpll_rate % (50 * MHZ)))
- clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
- else if(!(ddr_pll_clk.rate % (50 * MHZ)))
- clk_set_parent_nolock(&clk_mac_pll_div, &ddr_pll_clk);
- else
- CRU_PRINTK_ERR("mac can't get 50mhz\n");
- //hsadc
- //auto pll sel
- //clk_set_parent_nolock(&clk_hsadc_pll_div, &general_pll_clk);
-
- //lcdc1 hdmi
- //clk_set_parent_nolock(&dclk_lcdc1_div, &general_pll_clk);
-
- //lcdc0 lcd auto sel pll
- //clk_set_parent_nolock(&dclk_lcdc0_div, &general_pll_clk);
-#endif
-
- //cif
- clk_set_parent_nolock(&clk_cif_out_div, &general_pll_clk);
-
- // FIXME yxj this plase cause display unusual
- //clk_set_parent_nolock(&aclk_vio_pre, &general_pll_clk);
-
- //axi lcdc auto sel
- //clk_set_parent_nolock(&aclk_lcdc0, &general_pll_clk);
- //clk_set_parent_nolock(&aclk_lcdc1, &general_pll_clk);
- // FIXME
-
- if (!flag_uboot_display) {
- //lcdc0 lcd auto sel pll
- clk_set_parent_nolock(&dclk_lcdc0, &general_pll_clk);
- clk_set_parent_nolock(&dclk_lcdc1, &general_pll_clk);
-
- //axi lcdc auto sel
- clk_set_parent_nolock(&aclk_lcdc0_pre, &general_pll_clk);
- clk_set_parent_nolock(&aclk_lcdc1_pre, &general_pll_clk);
- clk_set_rate_nolock(&aclk_lcdc0_pre, 300 * MHZ);
- clk_set_rate_nolock(&aclk_lcdc1_pre, 300 * MHZ);
- clk_set_rate_nolock(&hclk_disp_pre, 300 * MHZ);
- }
- //axi vepu auto sel
- clk_set_parent_nolock(&aclk_vepu, &codec_pll_clk);
- clk_set_parent_nolock(&aclk_vdpu, &codec_pll_clk);
-
- clk_set_rate_nolock(&aclk_vepu, 400 * MHZ);
- clk_set_rate_nolock(&aclk_vdpu, 400 * MHZ);
- //gpu auto sel
- clk_set_parent_nolock(&clk_gpu_pre, &general_pll_clk);
- clk_set_rate_nolock(&clk_gpu_pre, 133 * MHZ);
-
- clk_set_parent_nolock(&clk_sdmmc0, &general_pll_clk);
- clk_set_parent_nolock(&clk_sdio, &general_pll_clk);
- clk_set_parent_nolock(&clk_emmc, &general_pll_clk);
-
- clk_set_rate_nolock(&clk_sdmmc0, 24750000);
- clk_set_rate_nolock(&clk_sdio, 24750000);
-
- //rk_dump_clock_info();
-}
-#include <plat/efuse.h>
-void __init _rk2928_clock_data_init(unsigned long gpll, unsigned long cpll, int flags)
-{
- struct clk_lookup *clk;
- clk_register_dump_ops(&dump_ops);
- clk_register_default_ops_clk(&def_ops_clk);
-
- rk2928_clock_flags = flags;
-
- CLKDATA_DBG("%s total %d clks\n", __func__, ARRAY_SIZE(clks));
- for (clk = clks; clk < clks + ARRAY_SIZE(clks); clk++) {
- CLKDATA_DBG("%s add dev_id=%s, con_id=%s\n",
- __func__, clk->dev_id ? clk->dev_id : "NULL", clk->con_id ? clk->con_id : "NULL");
- clkdev_add(clk);
- clk_register(clk->clk);
- }
-
- rk_efuse_init();
-
- CLKDATA_DBG("clk_recalculate_root_clocks_nolock\n");
- div_clk_for_pll_init();
- clk_recalculate_root_clocks_nolock();
- // print loader config
- //rk_dump_clock_info();
- loops_per_jiffy = CLK_LOOPS_RECALC(arm_pll_clk.rate);
-
- /*
- * Only enable those clocks we will need, let the drivers
- * enable other clocks as necessary
- */
- rk30_init_enable_clocks();
- /*
- * Disable any unused clocks left on by the bootloader
- */
- clk_disable_unused();
-
- CLKDATA_DBG("rk2928_clock_common_init, gpll=%lu, cpll=%lu\n", gpll, cpll);
- rk2928_clock_common_init(gpll, cpll);
- preset_lpj = loops_per_jiffy;
-
- CLKDATA_DBG("%s clks init finish\n", __func__);
-}
-
-int rk292x_dvfs_init(void);
-void __init rk2928_clock_data_init(unsigned long gpll, unsigned long cpll, u32 flags)
-{
- printk("%s version: 2013-7-17\n", __func__);
- _rk2928_clock_data_init(gpll, cpll, flags);
- rk292x_dvfs_init();
-}
-
-#define STR_UBOOT_DISPLAY "fastboot"
-static int __init bootloader_setup(char *str)
-{
- if (0 == strncmp(str, STR_UBOOT_DISPLAY, strlen(STR_UBOOT_DISPLAY))) {
- printk("CLKDATA_MSG: get uboot display\n");
- flag_uboot_display = 1;
- }
- return 0;
-}
-early_param("androidboot.bootloader", bootloader_setup);
-
-int support_uboot_display(void)
-{
- return flag_uboot_display;
-}
+++ /dev/null
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-
-#include <asm/pgtable-hwdef.h>
-#include <asm/hardware/gic.h>
-#include <asm/mach/arch.h>
-#include <asm/hardware/cache-l2x0.h>
-
-#include <plat/sram.h>
-#include <mach/board.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <mach/fiq.h>
-#include <mach/loader.h>
-#include <mach/ddr.h>
-#include <mach/cpu.h>
-#include <mach/cpu_axi.h>
-#include <mach/debug_uart.h>
-
-static void __init cpu_axi_init(void)
-{
- CPU_AXI_SET_QOS_PRIORITY(0, 0, CPU0);
- CPU_AXI_SET_QOS_PRIORITY(0, 0, CPU1R);
- CPU_AXI_SET_QOS_PRIORITY(0, 0, CPU1W);
- CPU_AXI_SET_QOS_PRIORITY(0, 0, PERI);
- CPU_AXI_SET_QOS_PRIORITY(3, 3, LCDC0);
- CPU_AXI_SET_QOS_PRIORITY(3, 3, LCDC1);
- CPU_AXI_SET_QOS_PRIORITY(2, 1, GPU);
-
- writel_relaxed(0x3f, RK30_CPU_AXI_BUS_BASE + 0x0014); // memory scheduler read latency
- dsb();
-}
-
-#define L2_LY_SP_OFF (0)
-#define L2_LY_SP_MSK (0x7)
-
-#define L2_LY_RD_OFF (4)
-#define L2_LY_RD_MSK (0x7)
-
-#define L2_LY_WR_OFF (8)
-#define L2_LY_WR_MSK (0x7)
-#define L2_LY_SET(ly,off) (((ly)-1)<<(off))
-
-#define L2_LATENCY(setup_cycles, read_cycles, write_cycles) \
- L2_LY_SET(setup_cycles, L2_LY_SP_OFF) | \
- L2_LY_SET(read_cycles, L2_LY_RD_OFF) | \
- L2_LY_SET(write_cycles, L2_LY_WR_OFF)
-
-static void __init l2_cache_init(void)
-{
-#ifdef CONFIG_CACHE_L2X0
- u32 aux_ctrl, aux_ctrl_mask;
-
- writel_relaxed(L2_LATENCY(1, 1, 1), RK30_L2C_BASE + L2X0_TAG_LATENCY_CTRL);
- writel_relaxed(L2_LATENCY(2, 3, 1), RK30_L2C_BASE + L2X0_DATA_LATENCY_CTRL);
-
- /* L2X0 Prefetch Control */
- writel_relaxed(0x70000003, RK30_L2C_BASE + L2X0_PREFETCH_CTRL);
-
- /* L2X0 Power Control */
- writel_relaxed(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, RK30_L2C_BASE + L2X0_POWER_CTRL);
-
- /* force 16-way, 16KB way-size on RK3026 */
- aux_ctrl = (
- (1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) | // 16-way
- (0x1 << 25) | // Round-robin cache replacement policy
- (0x1 << 0) | // Full Line of Zero Enable
- (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
- (0x1 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | // 16KB way-size
- (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
- (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
- (0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT) );
-
- aux_ctrl_mask = ~(
- (1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) |
- (0x1 << 25) | // Cache replacement policy
- (0x1 << 0) | // Full Line of Zero Enable
- (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
- (0x7 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
- (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
- (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
- (0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT) );
-
- l2x0_init(RK30_L2C_BASE, aux_ctrl, aux_ctrl_mask);
-#endif
-}
-
-static int boot_mode;
-
-static void __init boot_mode_init(void)
-{
- u32 boot_flag = readl_relaxed(RK30_GRF_BASE + GRF_OS_REG4);
- boot_mode = readl_relaxed(RK30_GRF_BASE + GRF_OS_REG5);
-
- if (boot_flag == (SYS_KERNRL_REBOOT_FLAG | BOOT_RECOVER)) {
- boot_mode = BOOT_MODE_RECOVERY;
- }
- if (boot_mode || ((boot_flag & 0xff) && ((boot_flag & 0xffffff00) == SYS_KERNRL_REBOOT_FLAG)))
- printk("Boot mode: %s (%d) flag: %s (0x%08x)\n", boot_mode_name(boot_mode), boot_mode, boot_flag_name(boot_flag), boot_flag);
-#ifdef CONFIG_RK29_WATCHDOG
- writel_relaxed(BOOT_MODE_WATCHDOG, RK30_GRF_BASE + GRF_OS_REG5);
-#endif
-}
-
-int board_boot_mode(void)
-{
- return boot_mode;
-}
-EXPORT_SYMBOL(board_boot_mode);
-
-void __init rk2928_init_irq(void)
-{
- gic_init(0, IRQ_LOCALTIMER, GIC_DIST_BASE, GIC_CPU_BASE);
-#ifdef CONFIG_FIQ
- rk_fiq_init();
-#endif
- rk30_gpio_init();
- soc_gpio_init();
-}
-
-static unsigned int __initdata ddr_freq = DDR_FREQ;
-static int __init ddr_freq_setup(char *str)
-{
- get_option(&str, &ddr_freq);
- return 0;
-}
-early_param("ddr_freq", ddr_freq_setup);
-
-static void usb_uart_init(void)
-{
-#ifdef DEBUG_UART_BASE
- writel_relaxed(0x34000000, RK2928_GRF_BASE + GRF_UOC1_CON0);
-#ifdef CONFIG_RK_USB_UART
- writel_relaxed(0x34000000, RK30_GRF_BASE + GRF_UOC1_CON0);
-
- if((readl_relaxed(RK30_GRF_BASE + GRF_SOC_STATUS0) & (1<<10)))//detect id
- {
- if(!(readl_relaxed(RK30_GRF_BASE + GRF_SOC_STATUS0) & (1<<7)))//detect vbus
- {
- writel_relaxed(0x007f0055, RK30_GRF_BASE + GRF_UOC0_CON0);
- writel_relaxed(0x34003000, RK30_GRF_BASE + GRF_UOC1_CON0);
- }
- else
- {
- writel_relaxed(0x34000000, RK30_GRF_BASE + GRF_UOC1_CON0);
- }
- }
-
-#endif // end of CONFIG_RK_USB_UART
- writel_relaxed(0x07, DEBUG_UART_BASE + 0x88);
- writel_relaxed(0x07, DEBUG_UART_BASE + 0x88);
- writel_relaxed(0x00, DEBUG_UART_BASE + 0x04);
- writel_relaxed(0x83, DEBUG_UART_BASE + 0x0c);
- writel_relaxed(0x0d, DEBUG_UART_BASE + 0x00);
- writel_relaxed(0x00, DEBUG_UART_BASE + 0x04);
- writel_relaxed(0x03, DEBUG_UART_BASE + 0x0c);
-#endif //end of DEBUG_UART_BASE
-}
-
-void __init rk2928_map_io(void)
-{
- rk2928_map_common_io();
- usb_uart_init();
- rk29_setup_early_printk();
- cpu_axi_init();
- rk29_sram_init();
- board_clock_init();
- l2_cache_init();
- ddr_init(DDR_TYPE, ddr_freq);
- iomux_init();
- boot_mode_init();
-}
-
-static __init u32 get_ddr_size(void)
-{
- u32 size;
- u32 v[1], a[1];
- u32 pgtbl = PAGE_OFFSET + TEXT_OFFSET - 0x4000;
- u32 flag = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ;
-
- a[0] = pgtbl + (((u32)RK30_GRF_BASE >> 20) << 2);
- v[0] = readl_relaxed(a[0]);
- writel_relaxed(flag | ((RK30_GRF_PHYS >> 20) << 20), a[0]);
-
- size = ddr_get_cap();
-
- writel_relaxed(v[0], a[0]);
-
- return size;
-}
-
-void __init rk2928_fixup(struct machine_desc *desc, struct tag *tags,
- char **cmdline, struct meminfo *mi)
-{
- mi->nr_banks = 1;
- mi->bank[0].start = PLAT_PHYS_OFFSET;
- mi->bank[0].size = get_ddr_size();
-}
-
+++ /dev/null
-/* arch/arm/mach-rk3026/dvfs.c\r
- *\r
- * Copyright (C) 2012 ROCKCHIP, Inc.\r
- *\r
- * This software is licensed under the terms of the GNU General Public\r
- * License version 2, as published by the Free Software Foundation, and\r
- * may be copied, distributed, and modified under those terms.\r
- *\r
- * This program is distributed in the hope that it will be useful,\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- * GNU General Public License for more details.\r
- *\r
- */\r
-\r
-#include <linux/kernel.h>\r
-#include <linux/err.h>\r
-#include <linux/spinlock.h>\r
-#include <linux/list.h>\r
-#include <linux/slab.h>\r
-#include <linux/clk.h>\r
-#include <linux/cpufreq.h>\r
-#include <mach/dvfs.h>\r
-#include <mach/clock.h>\r
-#include <linux/regulator/consumer.h>\r
-#include <linux/delay.h>\r
-#include <linux/io.h>\r
-#include <linux/hrtimer.h>\r
-#include <plat/efuse.h>\r
-\r
-static int rk_dvfs_clk_notifier_event(struct notifier_block *this,\r
- unsigned long event, void *ptr)\r
-{\r
- struct clk_notifier_data *noti_info;\r
- struct clk *clk;\r
- struct clk_node *dvfs_clk;\r
- noti_info = (struct clk_notifier_data *)ptr;\r
- clk = noti_info->clk;\r
- dvfs_clk = clk->dvfs_info;\r
-\r
- switch (event) {\r
- case CLK_PRE_RATE_CHANGE:\r
- DVFS_DBG("%s CLK_PRE_RATE_CHANGE\n", __func__);\r
- break;\r
- case CLK_POST_RATE_CHANGE:\r
- DVFS_DBG("%s CLK_POST_RATE_CHANGE\n", __func__);\r
- break;\r
- case CLK_ABORT_RATE_CHANGE:\r
- DVFS_DBG("%s CLK_ABORT_RATE_CHANGE\n", __func__);\r
- break;\r
- case CLK_PRE_ENABLE:\r
- DVFS_DBG("%s CLK_PRE_ENABLE\n", __func__);\r
- break;\r
- case CLK_POST_ENABLE:\r
- DVFS_DBG("%s CLK_POST_ENABLE\n", __func__);\r
- break;\r
- case CLK_ABORT_ENABLE:\r
- DVFS_DBG("%s CLK_ABORT_ENABLE\n", __func__);\r
- break;\r
- case CLK_PRE_DISABLE:\r
- DVFS_DBG("%s CLK_PRE_DISABLE\n", __func__);\r
- break;\r
- case CLK_POST_DISABLE:\r
- DVFS_DBG("%s CLK_POST_DISABLE\n", __func__);\r
- dvfs_clk->set_freq = 0;\r
- break;\r
- case CLK_ABORT_DISABLE:\r
- DVFS_DBG("%s CLK_ABORT_DISABLE\n", __func__);\r
-\r
- break;\r
- default:\r
- break;\r
- }\r
- return 0;\r
-}\r
-\r
-static struct notifier_block rk_dvfs_clk_notifier = {\r
- .notifier_call = rk_dvfs_clk_notifier_event,\r
-};\r
-struct lkg_maxvolt {\r
- int leakage_level;\r
- unsigned int maxvolt;\r
-};\r
-#if 0\r
-#if 0\r
-/* avdd_com & vdd_arm separate circuit */\r
-static struct lkg_maxvolt lkg_volt_table[] = {\r
- {.leakage_level = 1, .maxvolt = 1350 * 1000},\r
- {.leakage_level = 3, .maxvolt = 1275 * 1000},\r
- {.leakage_level = 15, .maxvolt = 1200 * 1000},\r
-};\r
-#else\r
-/* avdd_com & vdd_arm short circuit */\r
-static struct lkg_maxvolt lkg_volt_table[] = {\r
- {.leakage_level = 3, .maxvolt = 1350 * 1000},\r
- {.leakage_level = 15, .maxvolt = 1250 * 1000},\r
-};\r
-#endif\r
-static int leakage_level = 0;\r
-#define MHZ (1000 * 1000)\r
-#define KHZ (1000)\r
-// Delayline bound for nandc = 148.5MHz, Varm = Vlog = 1.00V\r
-#define HIGH_DELAYLINE 125\r
-#define LOW_DELAYLINE 125\r
-static u8 rk30_get_avs_val(void);\r
-void dvfs_adjust_table_lmtvolt(struct clk *clk, struct cpufreq_frequency_table *table)\r
-{\r
- int i = 0;\r
- unsigned int maxvolt = 0;\r
- if (IS_ERR_OR_NULL(clk) || IS_ERR_OR_NULL(table)) {\r
- DVFS_ERR("%s: clk error OR table error\n", __func__);\r
- return ;\r
- }\r
-\r
- leakage_level = rk_leakage_val();\r
- printk("DVFS MSG: %s: %s get leakage_level = %d\n", clk->name, __func__, leakage_level);\r
- if (leakage_level == 0) {\r
-\r
- /*\r
- * This is for delayline auto scale voltage, \r
- * FIXME: HIGH_DELAYLINE / LOW_DELAYLINE value maybe redefined under\r
- * Varm = Vlog = 1.00V.\r
- * Warning: this value is frequency/voltage sensitive, care\r
- * about Freq nandc/Volt log.\r
- *\r
- */\r
-\r
- unsigned long delayline_val = 0;\r
- unsigned long high_delayline = 0, low_delayline = 0;\r
- unsigned long rate_nandc = 0;\r
- rate_nandc = clk_get_rate(clk_get(NULL, "nandc")) / KHZ;\r
- printk("Get nandc rate = %lu KHz\n", rate_nandc);\r
- high_delayline = HIGH_DELAYLINE * 148500 / rate_nandc;\r
- low_delayline = LOW_DELAYLINE * 148500 / rate_nandc;\r
- delayline_val = rk30_get_avs_val();\r
- printk("This chip no leakage msg, use delayline instead, val = %lu.(HDL=%lu, LDL=%lu)\n",\r
- delayline_val, high_delayline, low_delayline);\r
-\r
- if (delayline_val >= high_delayline) {\r
- leakage_level = 4; //same as leakage_level > 4\r
-\r
- } else if (delayline_val <= low_delayline) {\r
- leakage_level = 1;\r
- printk("Delayline TOO LOW, high voltage request\n");\r
-\r
- } else\r
- leakage_level = 2; //same as leakage_level = 3\r
- }\r
-\r
- for (i = 0; i < ARRAY_SIZE(lkg_volt_table); i++) {\r
- if (leakage_level <= lkg_volt_table[i].leakage_level) {\r
- maxvolt = lkg_volt_table[i].maxvolt;\r
- break;\r
- }\r
- }\r
-\r
- for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) {\r
- if (table[i].index > maxvolt) {\r
- printk("\t\tadjust table freq=%d KHz, index=%d mV", table[i].frequency, table[i].index);\r
- table[i].index = maxvolt;\r
- printk(" to index=%d mV\n", table[i].index);\r
- }\r
- }\r
-}\r
-#endif\r
-\r
-//static struct clk_node *dvfs_clk_cpu;\r
-static struct vd_node vd_core;\r
-int dvfs_target(struct clk *clk, unsigned long rate_hz)\r
-{\r
- struct clk_node *dvfs_clk;\r
- int volt_new = 0, clk_volt_store = 0;\r
- struct cpufreq_frequency_table clk_fv;\r
- int ret = 0;\r
- unsigned long rate_new, rate_old;\r
-\r
- if (!clk) {\r
- DVFS_ERR("%s is not a clk\n", __func__);\r
- return -1;\r
- }\r
- dvfs_clk = clk_get_dvfs_info(clk);\r
- DVFS_DBG("enter %s: clk(%s) rate = %lu Hz\n", __func__, dvfs_clk->name, rate_hz);\r
-\r
- if (!dvfs_clk || dvfs_clk->vd == NULL || IS_ERR_OR_NULL(dvfs_clk->vd->regulator)) {\r
- DVFS_ERR("dvfs(%s) is not register regulator\n", dvfs_clk->name);\r
- return -1;\r
- }\r
-\r
- if (dvfs_clk->vd->volt_set_flag == DVFS_SET_VOLT_FAILURE) {\r
- /* It means the last time set voltage error */\r
- ret = dvfs_reset_volt(dvfs_clk->vd);\r
- if (ret < 0) {\r
- return -1;\r
- }\r
- }\r
-\r
- /* Check limit rate */\r
- if (rate_hz < dvfs_clk->min_rate) {\r
- rate_hz = dvfs_clk->min_rate;\r
- } else if (rate_hz > dvfs_clk->max_rate) {\r
- rate_hz = dvfs_clk->max_rate;\r
- }\r
-\r
- /* need round rate */\r
- rate_old = clk_get_rate(clk);\r
- rate_new = clk_round_rate_nolock(clk, rate_hz);\r
- if(rate_new == rate_old)\r
- return 0;\r
-\r
- DVFS_DBG("dvfs(%s) round rate (%lu)(rount %lu) old (%lu)\n",\r
- dvfs_clk->name, rate_hz, rate_new, rate_old);\r
-\r
- /* find the clk corresponding voltage */\r
- if (0 != dvfs_clk_get_ref_volt(dvfs_clk, rate_new / 1000, &clk_fv)) {\r
- DVFS_ERR("dvfs(%s) rate %luhz is larger,not support\n", dvfs_clk->name, rate_hz);\r
- return -1;\r
- }\r
- clk_volt_store = dvfs_clk->set_volt;\r
- dvfs_clk->set_volt = clk_fv.index;\r
- volt_new = dvfs_vd_get_newvolt_byclk(dvfs_clk);\r
- DVFS_DBG("%s,%s,new rate=%lu(was=%lu),new volt=%lu,(was=%d)\n",__FUNCTION__,dvfs_clk->name,rate_new,\r
- rate_old,volt_new,dvfs_clk->vd->cur_volt);\r
-\r
- /* if up the rate */\r
- if (rate_new > rate_old) {\r
- ret = dvfs_scale_volt_direct(dvfs_clk->vd, volt_new);\r
- if (ret < 0)\r
- goto fail_roll_back;\r
- }\r
-\r
- /* scale rate */\r
- if (dvfs_clk->clk_dvfs_target) {\r
- ret = dvfs_clk->clk_dvfs_target(clk, rate_new, clk_set_rate_locked);\r
- } else {\r
- ret = clk_set_rate_locked(clk, rate_new);\r
- }\r
-\r
- if (ret < 0) {\r
- DVFS_ERR("%s set rate err\n", __func__);\r
- goto fail_roll_back;\r
- }\r
- dvfs_clk->set_freq = rate_new / 1000;\r
-\r
- DVFS_DBG("dvfs %s set rate %lu ok\n", dvfs_clk->name, clk_get_rate(clk));\r
-\r
- /* if down the rate */\r
- if (rate_new < rate_old) {\r
- ret = dvfs_scale_volt_direct(dvfs_clk->vd, volt_new);\r
- if (ret < 0)\r
- goto out;\r
- }\r
-\r
- return ret;\r
-fail_roll_back:\r
- dvfs_clk->set_volt = clk_volt_store;\r
-out:\r
- return -1;\r
-}\r
-\r
-\r
-/*****************************init**************************/\r
-/**\r
- * rate must be raising sequence\r
- */\r
-static struct cpufreq_frequency_table cpu_dvfs_table[] = {\r
- // {.frequency = 48 * DVFS_KHZ, .index = 920*DVFS_MV},\r
- // {.frequency = 126 * DVFS_KHZ, .index = 970 * DVFS_MV},\r
- // {.frequency = 252 * DVFS_KHZ, .index = 1040 * DVFS_MV},\r
- // {.frequency = 504 * DVFS_KHZ, .index = 1050 * DVFS_MV},\r
- {.frequency = 816 * DVFS_KHZ, .index = 1050 * DVFS_MV},\r
- // {.frequency = 1008 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
- {.frequency = CPUFREQ_TABLE_END},\r
-};\r
-\r
-static struct cpufreq_frequency_table ddr_dvfs_table[] = {\r
- // {.frequency = 100 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
- {.frequency = 200 * DVFS_KHZ, .index = 1000 * DVFS_MV},\r
- {.frequency = 300 * DVFS_KHZ, .index = 1050 * DVFS_MV},\r
- {.frequency = 400 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
- {.frequency = 500 * DVFS_KHZ, .index = 1150 * DVFS_MV},\r
- {.frequency = 600 * DVFS_KHZ, .index = 1200 * DVFS_MV},\r
- {.frequency = CPUFREQ_TABLE_END},\r
-};\r
-\r
-static struct cpufreq_frequency_table gpu_dvfs_table[] = {\r
- {.frequency = 90 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
- {.frequency = 180 * DVFS_KHZ, .index = 1150 * DVFS_MV},\r
- {.frequency = 300 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
- {.frequency = 400 * DVFS_KHZ, .index = 1150 * DVFS_MV},\r
- {.frequency = 500 * DVFS_KHZ, .index = 1200 * DVFS_MV},\r
- {.frequency = CPUFREQ_TABLE_END},\r
-};\r
-#if 0\r
-static struct cpufreq_frequency_table peri_aclk_dvfs_table[] = {\r
- {.frequency = 100 * DVFS_KHZ, .index = 1000 * DVFS_MV},\r
- {.frequency = 200 * DVFS_KHZ, .index = 1050 * DVFS_MV},\r
- {.frequency = 300 * DVFS_KHZ, .index = 1070 * DVFS_MV},\r
- {.frequency = 500 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
- {.frequency = CPUFREQ_TABLE_END},\r
-};\r
-#endif\r
-static struct cpufreq_frequency_table vpu_dvfs_table[] = {\r
- {.frequency = 266 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
- {.frequency = 300 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
- {.frequency = 400 * DVFS_KHZ, .index = 1200 * DVFS_MV},\r
- {.frequency = CPUFREQ_TABLE_END},\r
-};\r
-\r
-static struct cpufreq_frequency_table dep_cpu2core_table[] = {\r
- // {.frequency = 252 * DVFS_KHZ, .index = 1025 * DVFS_MV},\r
- // {.frequency = 504 * DVFS_KHZ, .index = 1025 * DVFS_MV},\r
- {.frequency = 816 * DVFS_KHZ, .index = 1050 * DVFS_MV},//logic 1.050V\r
- // {.frequency = 1008 * DVFS_KHZ,.index = 1050 * DVFS_MV},\r
- // {.frequency = 1200 * DVFS_KHZ,.index = 1050 * DVFS_MV},\r
- // {.frequency = 1272 * DVFS_KHZ,.index = 1050 * DVFS_MV},//logic 1.050V\r
- // {.frequency = 1416 * DVFS_KHZ,.index = 1100 * DVFS_MV},//logic 1.100V\r
- // {.frequency = 1512 * DVFS_KHZ,.index = 1125 * DVFS_MV},//logic 1.125V\r
- // {.frequency = 1608 * DVFS_KHZ,.index = 1175 * DVFS_MV},//logic 1.175V\r
- {.frequency = CPUFREQ_TABLE_END},\r
-};\r
-\r
-static struct vd_node vd_cpu = {\r
- .name = "vd_cpu",\r
- .regulator_name = "vdd_cpu",\r
- .volt_set_flag = DVFS_SET_VOLT_FAILURE,\r
- .vd_dvfs_target = dvfs_target,\r
-};\r
-\r
-static struct vd_node vd_core = {\r
- .name = "vd_core",\r
- .regulator_name = "vdd_core",\r
- .volt_set_flag = DVFS_SET_VOLT_FAILURE,\r
- .vd_dvfs_target = dvfs_target,\r
-};\r
-\r
-static struct vd_node vd_rtc = {\r
- .name = "vd_rtc",\r
- .regulator_name = "vdd_rtc",\r
- .volt_set_flag = DVFS_SET_VOLT_FAILURE,\r
- .vd_dvfs_target = NULL,\r
-};\r
-\r
-static struct vd_node *rk30_vds[] = {&vd_cpu, &vd_core, &vd_rtc};\r
-\r
-static struct pd_node pd_a9_0 = {\r
- .name = "pd_a9_0",\r
- .vd = &vd_cpu,\r
-};\r
-static struct pd_node pd_a9_1 = {\r
- .name = "pd_a9_1",\r
- .vd = &vd_cpu,\r
-};\r
-static struct pd_node pd_debug = {\r
- .name = "pd_debug",\r
- .vd = &vd_cpu,\r
-};\r
-static struct pd_node pd_scu = {\r
- .name = "pd_scu",\r
- .vd = &vd_cpu,\r
-};\r
-static struct pd_node pd_video = {\r
- .name = "pd_video",\r
- .vd = &vd_core,\r
-};\r
-static struct pd_node pd_vio = {\r
- .name = "pd_vio",\r
- .vd = &vd_core,\r
-};\r
-static struct pd_node pd_gpu = {\r
- .name = "pd_gpu",\r
- .vd = &vd_core,\r
-};\r
-static struct pd_node pd_peri = {\r
- .name = "pd_peri",\r
- .vd = &vd_core,\r
-};\r
-static struct pd_node pd_cpu = {\r
- .name = "pd_cpu",\r
- .vd = &vd_core,\r
-};\r
-static struct pd_node pd_alive = {\r
- .name = "pd_alive",\r
- .vd = &vd_core,\r
-};\r
-static struct pd_node pd_rtc = {\r
- .name = "pd_rtc",\r
- .vd = &vd_rtc,\r
-};\r
-#define LOOKUP_PD(_ppd) \\r
-{ \\r
- .pd = _ppd, \\r
-}\r
-static struct pd_node_lookup rk30_pds[] = {\r
- LOOKUP_PD(&pd_a9_0),\r
- LOOKUP_PD(&pd_a9_1),\r
- LOOKUP_PD(&pd_debug),\r
- LOOKUP_PD(&pd_scu),\r
- LOOKUP_PD(&pd_video),\r
- LOOKUP_PD(&pd_vio),\r
- LOOKUP_PD(&pd_gpu),\r
- LOOKUP_PD(&pd_peri),\r
- LOOKUP_PD(&pd_cpu),\r
- LOOKUP_PD(&pd_alive),\r
- LOOKUP_PD(&pd_rtc),\r
-};\r
-\r
-#define CLK_PDS(_ppd) \\r
-{ \\r
- .pd = _ppd, \\r
-}\r
-\r
-static struct pds_list cpu_pds[] = {\r
- CLK_PDS(&pd_a9_0),\r
- CLK_PDS(&pd_a9_1),\r
- CLK_PDS(NULL),\r
-};\r
-\r
-static struct pds_list ddr_pds[] = {\r
- CLK_PDS(&pd_cpu),\r
- CLK_PDS(NULL),\r
-};\r
-\r
-static struct pds_list gpu_pds[] = {\r
- CLK_PDS(&pd_gpu),\r
- CLK_PDS(NULL),\r
-};\r
-#if 0\r
-static struct pds_list aclk_periph_pds[] = {\r
- CLK_PDS(&pd_peri),\r
- CLK_PDS(NULL),\r
-};\r
-#endif\r
-static struct pds_list aclk_vepu_pds[] = {\r
- CLK_PDS(&pd_video),\r
- CLK_PDS(NULL),\r
-};\r
-\r
-#define RK_CLKS(_clk_name, _ppds, _dvfs_table, _dvfs_nb) \\r
-{ \\r
- .name = _clk_name, \\r
- .pds = _ppds,\\r
- .dvfs_table = _dvfs_table, \\r
- .dvfs_nb = _dvfs_nb, \\r
-}\r
-\r
-static struct clk_node rk30_clks[] = {\r
- RK_CLKS("cpu", cpu_pds, cpu_dvfs_table, &rk_dvfs_clk_notifier),\r
- RK_CLKS("ddr", ddr_pds, ddr_dvfs_table, &rk_dvfs_clk_notifier),\r
- RK_CLKS("gpu", gpu_pds, gpu_dvfs_table, &rk_dvfs_clk_notifier),\r
- RK_CLKS("aclk_vepu", aclk_vepu_pds, vpu_dvfs_table, &rk_dvfs_clk_notifier),\r
- //RK_CLKS("aclk_periph", aclk_periph_pds, peri_aclk_dvfs_table, &rk_dvfs_clk_notifier),\r
-};\r
-\r
-#define RK_DEPPENDS(_clk_name, _pvd, _dep_table) \\r
-{ \\r
- .clk_name = _clk_name, \\r
- .dep_vd = _pvd,\\r
- .dep_table = _dep_table, \\r
-}\r
-\r
-static struct depend_lookup rk30_depends[] = {\r
- RK_DEPPENDS("cpu", &vd_core, dep_cpu2core_table),\r
- //RK_DEPPENDS("gpu", &vd_cpu, NULL),\r
- //RK_DEPPENDS("gpu", &vd_cpu, NULL),\r
-};\r
-\r
-\r
-static struct avs_ctr_st rk292x_avs_ctr;\r
-\r
-int rk292x_dvfs_init(void)\r
-{\r
- int i = 0;\r
- for (i = 0; i < ARRAY_SIZE(rk30_vds); i++) {\r
- rk_regist_vd(rk30_vds[i]);\r
- }\r
- for (i = 0; i < ARRAY_SIZE(rk30_pds); i++) {\r
- rk_regist_pd(&rk30_pds[i]);\r
- }\r
- for (i = 0; i < ARRAY_SIZE(rk30_clks); i++) {\r
- rk_regist_clk(&rk30_clks[i]);\r
- }\r
- for (i = 0; i < ARRAY_SIZE(rk30_depends); i++) {\r
- rk_regist_depends(&rk30_depends[i]);\r
- }\r
- //dvfs_clk_cpu = dvfs_get_dvfs_clk_byname("cpu");\r
- avs_board_init(&rk292x_avs_ctr);\r
- return 0;\r
-}\r
-\r
-/******************************rk292x avs**************************************************/\r
-\r
-static void __iomem *rk292x_nandc_base;\r
-#define nandc_readl(offset) readl_relaxed(rk292x_nandc_base + offset)\r
-#define nandc_writel(v, offset) do { writel_relaxed(v, rk292x_nandc_base + offset); dsb(); } while (0)\r
-static u8 rk292x_get_avs_val(void)\r
-{\r
- u32 nanc_save_reg[4];\r
- unsigned long flags;\r
- u32 paramet = 0;\r
- u32 count = 100;\r
- if(rk292x_nandc_base == NULL) \r
- return 0;\r
- preempt_disable();\r
- local_irq_save(flags);\r
-\r
- nanc_save_reg[0] = nandc_readl(0);\r
- nanc_save_reg[1] = nandc_readl(0x130);\r
- nanc_save_reg[2] = nandc_readl(0x134);\r
- nanc_save_reg[3] = nandc_readl(0x158);\r
-\r
- nandc_writel(nanc_save_reg[0] | 0x1 << 14, 0);\r
- nandc_writel(0x5, 0x130);\r
-\r
- /* Just break lock status */\r
- nandc_writel(0x1, 0x158);\r
- nandc_writel(0x7, 0x158);\r
- nandc_writel(0x21, 0x134);\r
-\r
- while(count--) {\r
- paramet = nandc_readl(0x138);\r
- if((paramet & 0x1))\r
- break;\r
- udelay(1);\r
- };\r
- paramet = (paramet >> 1) & 0xff;\r
- nandc_writel(nanc_save_reg[0], 0);\r
- nandc_writel(nanc_save_reg[1], 0x130);\r
- nandc_writel(nanc_save_reg[2], 0x134);\r
- nandc_writel(nanc_save_reg[3], 0x158);\r
-\r
- local_irq_restore(flags);\r
- preempt_enable();\r
- return (u8)paramet;\r
-\r
-}\r
-\r
-void rk292x_avs_init(void)\r
-{\r
- rk292x_nandc_base = ioremap(RK2928_NANDC_PHYS, RK2928_NANDC_SIZE);\r
- //avs_init_val_get(0,1150000,"board_init");\r
-}\r
-\r
-static struct avs_ctr_st rk292x_avs_ctr = {\r
- .avs_init =rk292x_avs_init,\r
- .avs_get_val = rk292x_get_avs_val,\r
-};\r
+++ /dev/null
-#include <../../mach-rk2928/include/mach/board.h>
+++ /dev/null
-#include <plat/clkdev.h>
+++ /dev/null
-#include <plat/clock.h>
+++ /dev/null
-#include <../../mach-rk2928/include/mach/config.h>
+++ /dev/null
-#include <../../mach-rk2928/include/mach/cpu.h>
+++ /dev/null
-#ifndef __MACH_CPU_AXI_H
-#define __MACH_CPU_AXI_H
-
-#include <plat/cpu_axi.h>
-
-#define CPU_AXI_BUS_BASE RK2928_CPU_AXI_BUS_BASE
-
-#define CPU_AXI_CPU0_QOS_BASE (CPU_AXI_BUS_BASE + 0x2000)
-#define CPU_AXI_CPU1W_QOS_BASE (CPU_AXI_BUS_BASE + 0x2080)
-#define CPU_AXI_CPU1R_QOS_BASE (CPU_AXI_BUS_BASE + 0x2100)
-#define CPU_AXI_PERI_QOS_BASE (CPU_AXI_BUS_BASE + 0x4000)
-#define CPU_AXI_GPU_QOS_BASE (CPU_AXI_BUS_BASE + 0x5000)
-#define CPU_AXI_VPU_QOS_BASE (CPU_AXI_BUS_BASE + 0x6000)
-#define CPU_AXI_LCDC1_QOS_BASE (CPU_AXI_BUS_BASE + 0x7000)
-#define CPU_AXI_EBC_QOS_BASE (CPU_AXI_BUS_BASE + 0x7080)
-#define CPU_AXI_IEP_QOS_BASE (CPU_AXI_BUS_BASE + 0x7100)
-#define CPU_AXI_LCDC0_QOS_BASE (CPU_AXI_BUS_BASE + 0x7180)
-#define CPU_AXI_CIF0_QOS_BASE (CPU_AXI_BUS_BASE + 0x7200)
-#define CPU_AXI_RGA_QOS_BASE (CPU_AXI_BUS_BASE + 0x7280)
-
-#endif
+++ /dev/null
-#ifndef __MACH_CRU_H
-#define __MACH_CRU_H
-
-enum rk_plls_id {
- APLL_ID = 0,
- DPLL_ID,
- CPLL_ID,
- GPLL_ID,
- END_PLL_ID,
-};
-
-/*****cru reg offset*****/
-
-#define CRU_MODE_CON 0x40
-#define CRU_CLKSEL_CON 0x44
-#define CRU_CLKGATE_CON 0xd0
-#define CRU_GLB_SRST_FST 0x100
-#define CRU_GLB_SRST_SND 0x104
-#define CRU_SOFTRST_CON 0x110
-
-#define PLL_CONS(id, i) ((id) * 0x10 + ((i) * 4))
-
-#define CRU_CLKSELS_CON_CNT (35)
-#define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON + ((i) * 4))
-
-#define CRU_CLKGATES_CON_CNT (10)
-#define CRU_CLKGATES_CON(i) (CRU_CLKGATE_CON + ((i) * 4))
-
-#define CRU_SOFTRSTS_CON_CNT (9)
-#define CRU_SOFTRSTS_CON(i) (CRU_SOFTRST_CON + ((i) * 4))
-
-#define CRU_MISC_CON (0x134)
-#define CRU_GLB_CNT_TH (0x140)
-
-/*PLL_CON 0,1,2*/
-#define PLL_PWR_ON (0)
-#define PLL_PWR_DN (1)
-#define PLL_BYPASS (1 << 15)
-#define PLL_NO_BYPASS (0 << 15)
-//con0
-#define PLL_BYPASS_SHIFT (15)
-
-#define PLL_POSTDIV1_MASK (0x7)
-#define PLL_POSTDIV1_SHIFT (12)
-#define PLL_FBDIV_MASK (0xfff)
-#define PLL_FBDIV_SHIFT (0)
-
-//con1
-#define PLL_RSTMODE_SHIFT (15)
-#define PLL_RST_SHIFT (14)
-#define PLL_PWR_DN_SHIFT (13)
-#define PLL_DSMPD_SHIFT (12)
-#define PLL_LOCK_SHIFT (10)
-
-#define PLL_POSTDIV2_MASK (0x7)
-#define PLL_POSTDIV2_SHIFT (6)
-#define PLL_REFDIV_MASK (0x3f)
-#define PLL_REFDIV_SHIFT (0)
-
-//con2
-#define PLL_FOUT4PHASE_PWR_DN_SHIFT (27)
-#define PLL_FOUTVCO_PWR_DN_SHIFT (26)
-#define PLL_FOUTPOSTDIV_PWR_DN_SHIFT (25)
-#define PLL_DAC_PWR_DN_SHIFT (24)
-
-#define PLL_FRAC_MASK (0xffffff)
-#define PLL_FRAC_SHIFT (0)
-
-/********************************************************************/
-#define CRU_GET_REG_BIT_VAL(reg, bits_shift) (((reg) >> (bits_shift)) & (0x1))
-#define CRU_GET_REG_BITS_VAL(reg, bits_shift, msk) (((reg) >> (bits_shift)) & (msk))
-#define CRU_SET_BIT(val, bits_shift) (((val) & (0x1)) << (bits_shift))
-#define CRU_SET_BITS(val, bits_shift, msk) (((val) & (msk)) << (bits_shift))
-#define CRU_W_MSK(bits_shift, msk) ((msk) << ((bits_shift) + 16))
-
-#define CRU_W_MSK_SETBITS(val, bits_shift, msk) (CRU_W_MSK(bits_shift, msk) \
- | CRU_SET_BITS(val, bits_shift, msk))
-#define CRU_W_MSK_SETBIT(val, bits_shift) (CRU_W_MSK(bits_shift, 0x1) \
- | CRU_SET_BIT(val, bits_shift))
-
-#define PLL_SET_REFDIV(val) CRU_W_MSK_SETBITS(val, PLL_REFDIV_SHIFT, PLL_REFDIV_MASK)
-#define PLL_SET_FBDIV(val) CRU_W_MSK_SETBITS(val, PLL_FBDIV_SHIFT, PLL_FBDIV_MASK)
-#define PLL_SET_POSTDIV1(val) CRU_W_MSK_SETBITS(val, PLL_POSTDIV1_SHIFT, PLL_POSTDIV1_MASK)
-#define PLL_SET_POSTDIV2(val) CRU_W_MSK_SETBITS(val, PLL_POSTDIV2_SHIFT, PLL_POSTDIV2_MASK)
-#define PLL_SET_FRAC(val) CRU_SET_BITS(val, PLL_FRAC_SHIFT, PLL_FRAC_MASK)
-
-#define PLL_GET_REFDIV(reg) CRU_GET_REG_BITS_VAL(reg, PLL_REFDIV_SHIFT, PLL_REFDIV_MASK)
-#define PLL_GET_FBDIV(reg) CRU_GET_REG_BITS_VAL(reg, PLL_FBDIV_SHIFT, PLL_FBDIV_MASK)
-#define PLL_GET_POSTDIV1(reg) CRU_GET_REG_BITS_VAL(reg, PLL_POSTDIV1_SHIFT, PLL_POSTDIV1_MASK)
-#define PLL_GET_POSTDIV2(reg) CRU_GET_REG_BITS_VAL(reg, PLL_POSTDIV2_SHIFT, PLL_POSTDIV2_MASK)
-#define PLL_GET_FRAC(reg) CRU_GET_REG_BITS_VAL(reg, PLL_FRAC_SHIFT, PLL_FRAC_MASK)
-
-//#define APLL_SET_BYPASS(val) CRU_SET_BIT(val, PLL_BYPASS_SHIFT)
-#define PLL_SET_DSMPD(val) CRU_W_MSK_SETBIT(val, PLL_DSMPD_SHIFT)
-#define PLL_GET_DSMPD(reg) CRU_GET_REG_BIT_VAL(reg, PLL_DSMPD_SHIFT)
-/*******************MODE BITS***************************/
-#define PLL_MODE_MSK(id) (0x1 << ((id) * 4))
-#define PLL_MODE_SHIFT(id) ((id) * 4)
-#define PLL_MODE_SLOW(id) (CRU_W_MSK_SETBIT(0x0, PLL_MODE_SHIFT(id)))
-#define PLL_MODE_NORM(id) (CRU_W_MSK_SETBIT(0x1, PLL_MODE_SHIFT(id)))
-/*******************CLKSEL0 BITS***************************/
-#define CLK_SET_DIV_CON_SUB1(val, bits_shift, msk) CRU_W_MSK_SETBITS((val - 1), bits_shift, msk)
-
-#define CPU_CLK_PLL_SEL_SHIFT (13)
-#define CORE_CLK_PLL_SEL_SHIFT (7)
-#define SEL_APLL (0)
-#define SEL_GPLL (1)
-#define CPU_SEL_PLL(plls) CRU_W_MSK_SETBIT(plls, CPU_CLK_PLL_SEL_SHIFT)
-#define CORE_SEL_PLL(plls) CRU_W_MSK_SETBIT(plls, CORE_CLK_PLL_SEL_SHIFT)
-
-#define ACLK_CPU_DIV_MASK (0x1f)
-#define ACLK_CPU_DIV_SHIFT (8)
-#define A9_CORE_DIV_MASK (0x1f)
-#define A9_CORE_DIV_SHIFT (0)
-
-#define RATIO_11 (1)
-#define RATIO_21 (2)
-#define RATIO_41 (4)
-#define RATIO_81 (8)
-
-#define ACLK_CPU_DIV(val) CLK_SET_DIV_CON_SUB1(val, ACLK_CPU_DIV_SHIFT, ACLK_CPU_DIV_MASK)
-#define CLK_CORE_DIV(val) CLK_SET_DIV_CON_SUB1(val, A9_CORE_DIV_SHIFT, A9_CORE_DIV_MASK)
-/*******************CLKSEL1 BITS***************************/
-#define PCLK_CPU_DIV_MASK (0x7)
-#define PCLK_CPU_DIV_SHIFT (12)
-#define HCLK_CPU_DIV_MASK (0x3)
-#define HCLK_CPU_DIV_SHIFT (8)
-#define ACLK_CORE_DIV_MASK (0x7)
-#define ACLK_CORE_DIV_SHIFT (4)
-#define CORE_PERIPH_DIV_MASK (0xf)
-#define CORE_PERIPH_DIV_SHIFT (0)
-
-#define PCLK_CPU_DIV(val) CLK_SET_DIV_CON_SUB1(val, PCLK_CPU_DIV_SHIFT, PCLK_CPU_DIV_MASK)
-#define HCLK_CPU_DIV(val) CLK_SET_DIV_CON_SUB1(val, HCLK_CPU_DIV_SHIFT, HCLK_CPU_DIV_MASK)
-#define ACLK_CORE_DIV(val) CLK_SET_DIV_CON_SUB1(val, ACLK_CORE_DIV_SHIFT, ACLK_CORE_DIV_MASK)
-#define CLK_CORE_PERI_DIV(val) CLK_SET_DIV_CON_SUB1(val, CORE_PERIPH_DIV_SHIFT, CORE_PERIPH_DIV_MASK)
-
-/*******************clksel10***************************/
-#define PERI_PLL_SEL_SHIFT 15
-#define PERI_PCLK_DIV_MASK (0x3)
-#define PERI_PCLK_DIV_SHIFT (12)
-#define PERI_HCLK_DIV_MASK (0x3)
-#define PERI_HCLK_DIV_SHIFT (8)
-#define PERI_ACLK_DIV_MASK (0x1f)
-#define PERI_ACLK_DIV_SHIFT (0)
-
-#define SEL_2PLL_GPLL (0)
-#define SEL_2PLL_CPLL (1)
-
-#define PERI_CLK_SEL_PLL(plls) CRU_W_MSK_SETBIT(plls, PERI_PLL_SEL_SHIFT)
-#define PERI_SET_ACLK_DIV(val) CLK_SET_DIV_CON_SUB1(val, PERI_ACLK_DIV_SHIFT, PERI_ACLK_DIV_MASK)
-/*******************gate BITS***************************/
-#define CLK_GATE_CLKID_CONS(i) CRU_CLKGATES_CON((i) / 16)
-
-#define CLK_GATE(i) (1 << ((i)%16))
-#define CLK_UN_GATE(i) (0)
-
-#define CLK_GATE_W_MSK(i) (1 << (((i) % 16) + 16))
-#define CLK_GATE_CLKID(i) (16 * (i))
-
-enum cru_clk_gate {
- /* SCU CLK GATE 0 CON */
- CLK_GATE_CORE_PERIPH = CLK_GATE_CLKID(0),
- CLK_GATE_CPU_GPLL,
- CLK_GATE_DDRPHY_SRC,
- CLK_GATE_ACLK_CPU,
-
- CLK_GATE_HCLK_CPU,
- CLK_GATE_PCLK_CPU,
- CLK_GATE_CORE_GPLL,
- CLK_GATE_ACLK_CORE,
-
- CLK_GATE_DDRPHY_GPLL_SRC,
- CLK_GATE_I2S_SRC,
- CLK_GATE_I2S_FRAC_SRC,
- CLK_GATE_HCLK_DISP,
-
- CLK_GATE_CRYPTO,
- CLK_GATE_0RES13,
- CLK_GATE_0RES14,
- CLK_GATE_TESTCLK,
-
- CLK_GATE_TIMER0 = CLK_GATE_CLKID(1),
- CLK_GATE_TIMER1,
- CLK_GATE_1RES2,
- CLK_GATE_JTAG,
-
- CLK_GATE_ACLK_LCDC1_SRC,
- CLK_GATE_OTGPHY0,
- CLK_GATE_OTGPHY1,
- CLK_GATE_DLL_DDR,
-
- CLK_GATE_UART0_SRC,
- CLK_GATE_UART0_FRAC_SRC,
- CLK_GATE_UART1_SRC,
- CLK_GATE_UART1_FRAC_SRC,
-
- CLK_GATE_UART2_SRC,
- CLK_GATE_UART2_FRAC_SRC,
- CLK_GATE_DLL_GPU,
- CLK_GATE_DLL_CORE,
-
- CLK_GATE_PERIPH_SRC = CLK_GATE_CLKID(2),
- CLK_GATE_ACLK_PERIPH,
- CLK_GATE_HCLK_PERIPH,
- CLK_GATE_PCLK_PERIPH,
-
- CLK_GATE_2RES4,
- CLK_GATE_2RES5,
- CLK_GATE_2RES6,
- CLK_GATE_2RES7,
-
- CLK_GATE_SARADC_SRC,
- CLK_GATE_SPI0_SRC,
- CLK_GATE_2RES10,
- CLK_GATE_MMC0_SRC,
-
- CLK_GATE_2RES12,
- CLK_GATE_SDIO_SRC,
- CLK_GATE_EMMC_SRC,
- CLK_GATE_2RES15,
-
- CLK_GATE_ACLK_LCDC0_SRC = CLK_GATE_CLKID(3),
- CLK_GATE_DCLK_LCDC0_SRC,
- CLK_GATE_DCLK_LCDC1_SRC,
- CLK_GATE_PCLKIN_CIF,
-
- CLK_GATE_DCLK_EBC_SRC,
- CLK_GATE_HCLK_CRYPTO,
- CLK_GATE_HCLK_EMEM_PERI,
- CLK_GATE_CIF_OUT_SRC,
-
- CLK_GATE_PCLK_HDMI,
- CLK_GATE_ACLK_VEPU_SRC,
- CLK_GATE_3RES10,
- CLK_GATE_ACLK_VDPU_SRC,
-
- CLK_GATE_HCLK_VDPU,
- CLK_GATE_GPU_PRE,
- CLK_GATE_ACLK_GPS,
- CLK_GATE_3RES15,
-
- CLK_GATE_HCLK_PERI_AXI_MATRIX = CLK_GATE_CLKID(4),
- CLK_GATE_PCLK_PERI_AXI_MATRIX,
- CLK_GATE_ACLK_CPU_PERI,
- CLK_GATE_ACLK_PERI_AXI_MATRIX,
-
- CLK_GATE_4RES4,
- CLK_GATE_4RES5,
- CLK_GATE_4RES6,
- CLK_GATE_4RES7,
-
- CLK_GATE_4RES8,
- CLK_GATE_4RES9,
- CLK_GATE_ACLK_STRC_SYS,
- CLK_GATE_4RES11,
-
- CLK_GATE_ACLK_INTMEM,
- CLK_GATE_4RES13,
- CLK_GATE_4RES14,
- CLK_GATE_4RES15,
-
- CLK_GATE_5RES0 = CLK_GATE_CLKID(5),
- CLK_GATE_ACLK_DMAC2,
- CLK_GATE_PCLK_EFUSE,
- CLK_GATE_5RES3,
-
- CLK_GATE_PCLK_GRF,
- CLK_GATE_5RES5,
- CLK_GATE_HCLK_ROM,
- CLK_GATE_PCLK_DDRUPCTL,
-
- CLK_GATE_5RES8,
- CLK_GATE_HCLK_NANDC,
- CLK_GATE_HCLK_SDMMC0,
- CLK_GATE_HCLK_SDIO,
-
- CLK_GATE_5RES12,
- CLK_GATE_HCLK_OTG0,
- CLK_GATE_PCLK_ACODEC,
- CLK_GATE_5RES15,
-
- CLK_GATE_ACLK_LCDC0 = CLK_GATE_CLKID(6),
- CLK_GATE_HCLK_LCDC0,
- CLK_GATE_6RES2,
- CLK_GATE_6RES3,
-
- CLK_GATE_HCLK_CIF,
- CLK_GATE_ACLK_CIF,
- CLK_GATE_6RES6,
- CLK_GATE_6RES7,
-
- CLK_GATE_6RES8,
- CLK_GATE_6RES9,
- CLK_GATE_HCLK_RGA,
- CLK_GATE_ACLK_RGA,
-
- CLK_GATE_HCLK_VIO_BUS,
- CLK_GATE_ACLK_VIO0,
- CLK_GATE_6RES14,
- CLK_GATE_6RES15,
-
- CLK_GATE_HCLK_EMMC = CLK_GATE_CLKID(7),
- CLK_GATE_7RES1,
- CLK_GATE_HCLK_I2S,
- CLK_GATE_HCLK_OTG1,
-
- CLK_GATE_7RES4,
- CLK_GATE_7RES5,
- CLK_GATE_7RES6,
- CLK_GATE_PCLK_TIMER0,
-
- CLK_GATE_PCLK_TIMER1,
- CLK_GATE_7RES9,
- CLK_GATE_PCLK_PWM01,
- CLK_GATE_7RES11,
-
- CLK_GATE_PCLK_SPI0,
- CLK_GATE_7RES13,
- CLK_GATE_PCLK_SARADC,
- CLK_GATE_PCLK_WDT,
-
- CLK_GATE_PCLK_UART0 = CLK_GATE_CLKID(8),
- CLK_GATE_PCLK_UART1,
- CLK_GATE_PCLK_UART2,
- CLK_GATE_8RES3,
-
- CLK_GATE_PCLK_I2C0,
- CLK_GATE_PCLK_I2C1,
- CLK_GATE_PCLK_I2C2,
- CLK_GATE_PCLK_I2C3,
-
- CLK_GATE_8RES8,
- CLK_GATE_PCLK_GPIO0,
- CLK_GATE_PCLK_GPIO1,
- CLK_GATE_PCLK_GPIO2,
-
- CLK_GATE_PCLK_GPIO3,
- CLK_GATE_8RES13,
- CLK_GATE_8RES14,
- CLK_GATE_8RES15,
-
- CLK_GATE_CLK_CORE_DBG = CLK_GATE_CLKID(9),
- CLK_GATE_PCLK_DBG,
- CLK_GATE_9RES2,
- CLK_GATE_9RES3,
-
- CLK_GATE_CLK_L2C,
- CLK_GATE_HCLK_LCDC1,
- CLK_GATE_ACLK_LCDC1,
- CLK_GATE_HCLK_IEP,
-
- CLK_GATE_ACLK_IEP,
- CLK_GATE_HCLK_EBC,
- CLK_GATE_ACLK_VIO1,
- CLK_GATE_9RES11,
-
- CLK_GATE_9RES12,
- CLK_GATE_HCLK_USB_PERI,
- CLK_GATE_HCLK_PERI_ARBI,
- CLK_GATE_ACLK_PERI_NIU,
-
- CLK_GATE_MAX,
-};
-
-#define SOFT_RST_ID(i) (16 * (i))
-
-enum cru_soft_reset {
- SOFT_RST_CORE_SRST_WDT_SEL = SOFT_RST_ID(0),
- SOFT_RST_0RES1,
- SOFT_RST_MCORE,
- SOFT_RST_CORE0,
-
- SOFT_RST_CORE1,
- SOFT_RST_0RES5,
- SOFT_RST_0RES6,
- SOFT_RST_MCORE_DBG,
-
- SOFT_RST_CORE0_DBG,
- SOFT_RST_CORE1_DBG,
- SOFT_RST_CORE0_WDT,
- SOFT_RST_CORE1_WDT,
-
- SOFT_RST_0RES12,
- SOFT_RST_ACLK_CORE,
- SOFT_RST_STRC_SYS_AXI,
- SOFT_RST_L2C,
-
- SOFT_RST_1RES0 = SOFT_RST_ID(1),
- SOFT_RST_CPUSYS_AHB,
- SOFT_RST_L2MEM_CON_AXI,
- SOFT_RST_AHB2APB,
-
- SOFT_RST_1RES4,
- SOFT_RST_INTMEM,
- SOFT_RST_ROM,
- SOFT_RST_PERI_NIU,
-
- SOFT_RST_I2S,
- SOFT_RST_DDR_DLL,
- SOFT_RST_GPU_DLL,
- SOFT_RST_TIMER0,
-
- SOFT_RST_TIMER1,
- SOFT_RST_CORE_DLL,
- SOFT_RST_EFUSE_APB,
- SOFT_RST_ACODEC,
-
- SOFT_RST_GPIO0 = SOFT_RST_ID(2),
- SOFT_RST_GPIO1,
- SOFT_RST_GPIO2,
- SOFT_RST_GPIO3,
-
- SOFT_RST_2RES4,
- SOFT_RST_2RES5,
- SOFT_RST_2RES6,
- SOFT_RST_UART0,
-
- SOFT_RST_UART1,
- SOFT_RST_UART2,
- SOFT_RST_2RES10,
- SOFT_RST_I2C0,
-
- SOFT_RST_I2C1,
- SOFT_RST_I2C2,
- SOFT_RST_I2C3,
- SOFT_RST_2RES15,
-
- SOFT_RST_PWM0 = SOFT_RST_ID(3),
- SOFT_RST_PWM1,
- SOFT_RST_DAP_PO,
- SOFT_RST_DAP,
-
- SOFT_RST_DAP_SYS,
- SOFT_RST_CRYPTO,
- SOFT_RST_3RES6,
- SOFT_RST_GRF,
-
- SOFT_RST_3RES8,
- SOFT_RST_PERIPHSYS_AXI,
- SOFT_RST_PERIPHSYS_AHB,
- SOFT_RST_PERIPHSYS_APB,
-
- SOFT_RST_PWM2,
- SOFT_RST_CPU_PERI,
- SOFT_RST_EMEM_PERI,
- SOFT_RST_USB_PERI,
-
- SOFT_RST_DMA2 = SOFT_RST_ID(4),
- SOFT_RST_4RES1,
- SOFT_RST_4RES2,
- SOFT_RST_GPS,
-
- SOFT_RST_NANDC,
- SOFT_RST_USBOTG0,
- SOFT_RST_4RES6,
- SOFT_RST_OTGC0,
-
- SOFT_RST_USBOTG1,
- SOFT_RST_4RES9,
- SOFT_RST_OTGC1,
- SOFT_RST_4RES11,
-
- SOFT_RST_4RES12,
- SOFT_RST_4RES13,
- SOFT_RST_4RES14,
- SOFT_RST_DDRMSCH,
-
- SOFT_RST_5RES0 = SOFT_RST_ID(5),
- SOFT_RST_MMC0,
- SOFT_RST_SDIO,
- SOFT_RST_EMMC,
-
- SOFT_RST_SPI0,
- SOFT_RST_5RES5,
- SOFT_RST_WDT,
- SOFT_RST_SARADC,
-
- SOFT_RST_DDRPHY,
- SOFT_RST_DDRPHY_APB,
- SOFT_RST_DDRCTRL,
- SOFT_RST_DDRCTRL_APB,
-
- SOFT_RST_5RES12,
- SOFT_RST_5RES13,
- SOFT_RST_5RES14,
- SOFT_RST_5RES15,
-
- SOFT_RST_HDMI_PCLK = SOFT_RST_ID(6),
- SOFT_RST_VIO_ARBI_AHB,
- SOFT_RST_VIO0_AXI,
- SOFT_RST_VIO_BUS_AHB,
-
- SOFT_RST_LCDC0_AXI,
- SOFT_RST_LCDC0_AHB,
- SOFT_RST_LCDC0_DCLK,
- SOFT_RST_UTMI0,
-
- SOFT_RST_UTMI1,
- SOFT_RST_USBPOR,
- SOFT_RST_IEP_AXI,
- SOFT_RST_IEP_AHB,
-
- SOFT_RST_RGA_AXI,
- SOFT_RST_RGA_AHB,
- SOFT_RST_CIF0,
- SOFT_RST_6RES15,
-
- SOFT_RST_VCODEC_AXI = SOFT_RST_ID(7),
- SOFT_RST_VCODEC_AHB,
- SOFT_RST_VIO1_AXI,
- SOFT_RST_CPU_VCODEC, //Actually not exist, Compatible with rk2928
-
- SOFT_RST_VCODEC_NIU_AXI,
- SOFT_RST_LCDC1_AXI,
- SOFT_RST_LCDC1_AHB,
- SOFT_RST_LCDC1_DCLK,
-
- SOFT_RST_GPU,
- SOFT_RST_7RES9,
- SOFT_RST_GPU_NIU_AXI,
- SOFT_RST_EBC_AXI,
-
- SOFT_RST_EBC_AHB,
- SOFT_RST_7RES13,
- SOFT_RST_7RES14,
- SOFT_RST_7RES15,
-
- SOFT_RST_8RES0 = SOFT_RST_ID(8),
- SOFT_RST_8RES1,
- SOFT_RST_CORE_DBG,
- SOFT_RST_DBG_APB,
-
- SOFT_RST_8RES4,
- SOFT_RST_8RES5,
- SOFT_RST_8RES6,
- SOFT_RST_8RES7,
-
- SOFT_RST_8RES8,
- SOFT_RST_8RES9,
- SOFT_RST_8RES10,
- SOFT_RST_8RES11,
-
- SOFT_RST_8RES12,
- SOFT_RST_8RES13,
- SOFT_RST_8RES14,
- SOFT_RST_8RES15,
-
- SOFT_RST_MAX,
-};
-
-/*****cru reg end*****/
-static inline void cru_set_soft_reset(enum cru_soft_reset idx, bool on)
-{
- const void __iomem *reg = RK2928_CRU_BASE + CRU_SOFTRSTS_CON(idx >> 4);
- u32 val = on ? 0x10001U << (idx & 0xf) : 0x10000U << (idx & 0xf);
- writel_relaxed(val, reg);
- dsb();
-}
-
-#endif
+++ /dev/null
-#include <plat/ddr.h>
+++ /dev/null
-#include <plat/debug-macro.S>
+++ /dev/null
-#include <../../mach-rk2928/include/mach/debug_uart.h>
+++ /dev/null
-#include <plat/dma-pl330.h>
+++ /dev/null
-#ifndef RK_MACH_DVFS_H
-#define RK_MACH_DVFS_H
-
-#include <plat/dvfs.h>
-
-#ifdef CONFIG_DVFS
-int rk292x_dvfs_init(void);
-#else
-static inline int rk292x_dvfs_init(void){ return 0; }
-#endif
-#endif
+++ /dev/null
-#include <plat/entry-macro.S>
+++ /dev/null
-#include <plat/fiq.h>
+++ /dev/null
-#include <../../mach-rk2928/include/mach/gpio.h>
+++ /dev/null
-#ifndef __MACH_GRF_H
-#define __MACH_GRF_H
-
-#define GRF_GPIO0A_IOMUX 0x00a8
-#define GRF_GPIO0B_IOMUX 0x00ac
-#define GRF_GPIO0C_IOMUX 0x00b0
-#define GRF_GPIO0D_IOMUX 0x00b4
-#define GRF_GPIO1A_IOMUX 0x00b8
-#define GRF_GPIO1B_IOMUX 0x00bc
-#define GRF_GPIO1C_IOMUX 0x00c0
-#define GRF_GPIO1D_IOMUX 0x00c4
-#define GRF_GPIO2A_IOMUX 0x00c8
-#define GRF_GPIO2B_IOMUX 0x00cc
-#define GRF_GPIO2C_IOMUX 0x00d0
-#define GRF_GPIO2D_IOMUX 0x00d4
-#define GRF_GPIO3C_IOMUX 0x00e0
-#define GRF_GPIO3D_IOMUX 0x00e4
-#define GRF_GPIO_DS 0x0100
-#define GRF_GPIO0L_PULL 0x0118
-#define GRF_GPIO0H_PULL 0x011c
-#define GRF_GPIO1L_PULL 0x0120
-#define GRF_GPIO1H_PULL 0x0124
-#define GRF_GPIO2L_PULL 0x0128
-#define GRF_GPIO2H_PULL 0x012c
-#define GRF_GPIO3L_PULL 0x0130
-#define GRF_GPIO3H_PULL 0x0134
-#define GRF_SOC_CON0 0x0140
-#define GRF_SOC_CON1 0x0144
-#define GRF_SOC_CON2 0x0148
-#define GRF_SOC_STATUS0 0x014c
-#define GRF_LVDS_CON0 0x0150
-#define GRF_DMAC_CON0 0x015c
-#define GRF_DMAC_CON1 0x0160
-#define GRF_DMAC_CON2 0x0164
-#define GRF_UOC0_CON0 0x017c
-#define GRF_UOC1_CON0 0x0190
-#define GRF_UOC1_CON1 0x0194
-#define GRF_DDRC_STAT 0x019c
-#define GRF_UOC_CON 0x01a0
-#define GRF_CPU_CON0 0x01a8
-#define GRF_CPU_CON1 0x01ac
-#define GRF_CPU_CON2 0x01b0
-#define GRF_CPU_CON3 0x01b4
-#define GRF_CPU_CON4 0x01b8
-#define GRF_CPU_CON5 0x01bc
-#define GRF_CPU_STATUS0 0x01c0
-#define GRF_CPU_STATUS1 0x01c4
-#define GRF_OS_REG0 0x01c8
-#define GRF_OS_REG1 0x01cc
-#define GRF_OS_REG2 0x01d0
-#define GRF_OS_REG3 0x01d4
-#define GRF_OS_REG4 0x01d8
-#define GRF_OS_REG5 0x01dc
-#define GRF_OS_REG6 0x01e0
-#define GRF_OS_REG7 0x01e4
-#define GRF_DLL_CON0 0x0200
-#define GRF_DLL_CON1 0x0204
-#define GRF_DLL_CON2 0x0208
-#define GRF_DLL_CON3 0x020c
-#define GRF_DLL_STATUS 0x0210
-#define GRF_DFI_WRNUM 0x0220
-#define GRF_DFI_RDNUM 0x0224
-#define GRF_DFI_ACTNUM 0x0228
-#define GRF_DFI_TIMERVAL 0x022c
-#define GRF_NIF_FIFO0 0x0230
-#define GRF_NIF_FIFO1 0x0234
-#define GRF_NIF_FIFO2 0x0238
-#define GRF_NIF_FIFO3 0x023c
-#define GRF_USBPHY0_CON0 0x0280
-#define GRF_USBPHY0_CON1 0x0284
-#define GRF_USBPHY0_CON2 0x0288
-#define GRF_USBPHY0_CON3 0x028c
-#define GRF_USBPHY0_CON4 0x0290
-#define GRF_USBPHY0_CON5 0x0294
-#define GRF_USBPHY0_CON6 0x0298
-#define GRF_USBPHY0_CON7 0x029c
-#define GRF_USBPHY1_CON0 0x02a0
-#define GRF_USBPHY1_CON1 0x02a4
-#define GRF_USBPHY1_CON2 0x02a8
-#define GRF_USBPHY1_CON3 0x02ac
-#define GRF_USBPHY1_CON4 0x02b0
-#define GRF_USBPHY1_CON5 0x02b4
-#define GRF_USBPHY1_CON6 0x02b8
-#define GRF_USBPHY1_CON7 0x02bc
-#define GRF_CHIP_TAG 0x0300
-
-#endif
+++ /dev/null
-#ifndef __MACH_HARDWARE_H
-#define __MACH_HARDWARE_H
-
-#endif
+++ /dev/null
-#include <../../mach-rk2928/include/mach/io.h>
+++ /dev/null
-#ifndef __MACH_IOMUX_H
-#define __MACH_IOMUX_H
-
-#include <mach/grf.h>
-#include <plat/iomux.h>
-
-#define GRF_IOMUX_BASE (RK2928_GRF_BASE + GRF_GPIO0A_IOMUX)
-
-enum {
- /* GPIO0_A */
- GPIO0_A0 = 0x0a00, I2C0_SCL,
- GPIO0_A1 = 0x0a10, I2C0_SDA,
- GPIO0_A2 = 0x0a20, I2C1_SCL,
- GPIO0_A3 = 0x0a30, I2C1_SDA,
- GPIO0_A6 = 0x0a60, I2C3_SCL, HDMI_DDCSCL,
- GPIO0_A7 = 0x0a70, I2C3_SDA, HDMI_DDCSDA,
-
- /* GPIO0_B */
- GPIO0_B0 = 0x0b00, MMC1_CMD,
- GPIO0_B1 = 0x0b10, MMC1_CLKOUT,
- GPIO0_B2 = 0x0b20, MMC1_DETN,
- GPIO0_B3 = 0x0b30, MMC1_D0,
- GPIO0_B4 = 0x0b40, MMC1_D1,
- GPIO0_B5 = 0x0b50, MMC1_D2,
- GPIO0_B6 = 0x0b60, MMC1_D3,
- GPIO0_B7 = 0x0b70, HDMI_HOTPLUGIN,
-
- /* GPIO0_C */
- GPIO0_C0 = 0x0c00, UART0_SOUT,
- GPIO0_C1 = 0x0c10, UART0_SIN,
- GPIO0_C2 = 0x0c20, UART0_RTSN,
- GPIO0_C3 = 0x0c30, UART0_CTSN,
- GPIO0_C4 = 0x0c40, HDMI_CECSDA,
- GPIO0_C7 = 0x0c70, NAND_CS1,
-
- /* GPIO0_D */
- GPIO0_D0 = 0x0d00, UART2_RTSN,
- GPIO0_D1 = 0x0d10, UART2_CTSN,
- GPIO0_D2 = 0x0d20, PWM0,
- GPIO0_D3 = 0x0d30, PWM1,
- GPIO0_D4 = 0x0d40, PWM2,
- GPIO0_D5 = 0x0d50, MMC1_WRPRT,
- GPIO0_D6 = 0x0d60, MMC1_PWREN,
- GPIO0_D7 = 0x0d70, MMC1_BKEPWR,
-
- /* GPIO1_A */
- GPIO1_A0 = 0x1a00, I2S0_MCLK,
- GPIO1_A1 = 0x1a10, I2S0_SCLK,
- GPIO1_A2 = 0x1a20, I2S0_LRCKRX, GPS_CLK,
- GPIO1_A3 = 0x1a30, I2S0_LRCKTX,
- GPIO1_A4 = 0x1a40, I2S0_SDO, GPS_MAG,
- GPIO1_A5 = 0x1a50, I2S0_SDI, GPS_SIGN, JTAG_TCK,
- GPIO1_A6 = 0x1a60, MMC1_INTN,
- GPIO1_A7 = 0x1a70, MMC0_WRPRT,
-
- /* GPIO1_B */
- GPIO1_B0 = 0x1b00, SPI0_CLK, UART1_CTSN,
- GPIO1_B1 = 0x1b10, SPI0_TXD, UART1_SOUT,
- GPIO1_B2 = 0x1b20, SPI0_RXD, UART1_SIN, JTAG_TMS,
- GPIO1_B3 = 0x1b30, SPI0_CS0, UART1_RTSN,
- GPIO1_B4 = 0x1b40, SPI0_CS1,
- GPIO1_B5 = 0x1b50, MMC0_RSTNOUT,
- GPIO1_B6 = 0x1b60, MMC0_PWREN,
- GPIO1_B7 = 0x1b70, MMC0_CMD,
-
- /* GPIO1_C */
- GPIO1_C0 = 0x1c00, MMC0_CLKOUT,
- GPIO1_C1 = 0x1c10, MMC0_DETN,
- GPIO1_C2 = 0x1c20, MMC0_D0,
- GPIO1_C3 = 0x1c30, MMC0_D1,
- GPIO1_C4 = 0x1c40, MMC0_D2, /* JTAG_TCK when sdmmc0_detectn is invalid */
- GPIO1_C5 = 0x1c50, MMC0_D3, /* JTAG_TMS when sdmmc0_detectn is invalid */
- GPIO1_C6 = 0x1c60, NAND_CS2, EMMC_CMD,
- GPIO1_C7 = 0x1c70, NAND_CS3, EMMC_RSTNOUT,
-
- /* GPIO1_D */
- GPIO1_D0 = 0x1d00, NAND_D0, EMMC_D0,
- GPIO1_D1 = 0x1d10, NAND_D1, EMMC_D1,
- GPIO1_D2 = 0x1d20, NAND_D2, EMMC_D2,
- GPIO1_D3 = 0x1d30, NAND_D3, EMMC_D3,
- GPIO1_D4 = 0x1d40, NAND_D4, EMMC_D4,
- GPIO1_D5 = 0x1d50, NAND_D5, EMMC_D5,
- GPIO1_D6 = 0x1d60, NAND_D6, EMMC_D6,
- GPIO1_D7 = 0x1d70, NAND_D7, EMMC_D7,
-
- /* GPIO2_A */
- GPIO2_A0 = 0x2a00, NAND_ALE,
- GPIO2_A1 = 0x2a10, NAND_CLE,
- GPIO2_A2 = 0x2a20, NAND_WRN,
- GPIO2_A3 = 0x2a30, NAND_RDN,
- GPIO2_A4 = 0x2a40, NAND_RDY,
- GPIO2_A5 = 0x2a50, NAND_WP, EMMC_PWREN,
- GPIO2_A6 = 0x2a60, NAND_CS0,
- GPIO2_A7 = 0x2a70, NAND_DQS, EMMC_CLKOUT,
-
- /* GPIO2_B */
- GPIO2_B0 = 0x2b00, LCDC0_DCLK, EBC_SDCLK,
- GPIO2_B1 = 0x2b10, LCDC0_HSYNC, EBC_SDLE,
- GPIO2_B2 = 0x2b20, LCDC0_VSYNC, EBC_SDOE,
- GPIO2_B3 = 0x2b30, LCDC0_DEN, EBC_GDCLK,
- GPIO2_B4 = 0x2b40, LCDC0_D10, EBC_SDCE2,
- GPIO2_B5 = 0x2b50, LCDC0_D11, EBC_SDCE3,
- GPIO2_B6 = 0x2b60, LCDC0_D12, EBC_SDCE4,
- GPIO2_B7 = 0x2b70, LCDC0_D13, EBC_SDCE5,
-
- /* GPIO2_C */
- GPIO2_C0 = 0x2c00, LCDC0_D14, EBC_VCOM,
- GPIO2_C1 = 0x2c10, LCDC0_D15, EBC_GDOE,
- GPIO2_C2 = 0x2c20, LCDC0_D16, EBC_GDSP,
- GPIO2_C3 = 0x2c30, LCDC0_D17, EBC_GDPWR0,
- GPIO2_C4 = 0x2c40, LCDC0_D18, EBC_GDRL, I2C2_SDA,
- GPIO2_C5 = 0x2c50, LCDC0_D19, EBC_SDSHR, I2C2_SCL,
- GPIO2_C6 = 0x2c60, LCDC0_D20, EBC_BORDER0, UART2_SIN,
- GPIO2_C7 = 0x2c70, LCDC0_D21, EBC_BORDER1, UART2_SOUT,
-
- /* GPIO2_D */
- GPIO2_D0 = 0x2d00, LCDC0_D22, EBC_GDPWR1,
- GPIO2_D1 = 0x2d10, LCDC0_D23, EBC_GDPWR2,
-
- /* GPIO3_A */
- /* GPIO3_B */
- /* GPIO3_C */
- GPIO3_C1 = 0x3c10, OTG_DRV_VBUS,
-
- /* GPIO3_D */
- GPIO3_D7 = 0x3d70, TEST_CLK_OUT,
-};
-
-#define rk29_mux_api_set(name, mode) iomux_set(mode)
-#define rk30_mux_api_set(name, mode) iomux_set(mode)
-
-#endif
+++ /dev/null
-#include <../../mach-rk2928/include/mach/irqs.h>
+++ /dev/null
-#include <plat/loader.h>
+++ /dev/null
-#ifndef __MACH_MEMORY_H
-#define __MACH_MEMORY_H
-
-#include <plat/memory.h>
-#include <mach/io.h>
-
-/*
- * SRAM memory whereabouts
- */
-#define SRAM_CODE_OFFSET (RK2928_IMEM_BASE + 0x0010)
-#define SRAM_CODE_END (RK2928_IMEM_BASE + 0x0FFF)
-#define SRAM_DATA_OFFSET (RK2928_IMEM_BASE + 0x1000)
-#define SRAM_DATA_END (RK2928_IMEM_BASE + 0x1FFF)
-
-#endif
+++ /dev/null
-#ifndef __MACH_PMU_H
-#define __MACH_PMU_H
-
-#include <linux/io.h>
-#include <mach/cru.h>
-
-enum pmu_power_domain {
- PD_A9_0 = 0,
- PD_A9_1,
- PD_ALIVE,
- PD_RTC,
- PD_SCU,
- PD_CPU,
- PD_PERI = 6,
- PD_VIO,
- PD_VIDEO,
- PD_VCODEC = PD_VIDEO,
- PD_GPU,
- PD_DBG,
-};
-
-static inline bool pmu_power_domain_is_on(enum pmu_power_domain pd)
-{
- return true;
-}
-
-static inline void pmu_set_power_domain(enum pmu_power_domain pd, bool on)
-{
- if (on && pd == PD_A9_1) {
- cru_set_soft_reset(SOFT_RST_CORE1, true);
- cru_set_soft_reset(SOFT_RST_CORE1, false);
- }
-}
-
-enum pmu_idle_req {
- IDLE_REQ_CPU = 0,
- IDLE_REQ_PERI,
- IDLE_REQ_GPU,
- IDLE_REQ_VIDEO,
- IDLE_REQ_VIO,
-};
-
-static inline void pmu_set_idle_request(enum pmu_idle_req req, bool idle)
-{
-}
-
-#endif
+++ /dev/null
-#include <../../mach-rk2928/include/mach/rk2928_camera.h>
+++ /dev/null
-#include <../../mach-rk30/include/mach/sram.h>
+++ /dev/null
-#include <plat/system.h>
+++ /dev/null
-#include <plat/timex.h>
+++ /dev/null
-#include <plat/uncompress.h>
+++ /dev/null
-#include <../../mach-rk30/include/mach/vmalloc.h>
+++ /dev/null
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <mach/system.h>
-#include <linux/string.h>
-#include <mach/cru.h>
-#include <mach/grf.h>
-#include <mach/loader.h>
-#include <mach/board.h>
-
-//#define DEBUG // for jtag debug
-
-#define cru_readl(offset) readl_relaxed(RK30_CRU_BASE + offset)
-#define cru_writel(v, offset) do { writel_relaxed(v, RK30_CRU_BASE + offset); } while (0)
-#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
-
-static bool is_panic = false;
-
-static int panic_event(struct notifier_block *this, unsigned long event, void *ptr)
-{
- is_panic = true;
- return NOTIFY_DONE;
-}
-
-static struct notifier_block panic_block = {
- .notifier_call = panic_event,
-};
-
-static int __init arch_reset_init(void)
-{
- atomic_notifier_chain_register(&panic_notifier_list, &panic_block);
- return 0;
-}
-core_initcall(arch_reset_init);
-
-#ifdef DEBUG
-__sramdata volatile int reset_loop = 1;
-#endif
-
-static void __sramfunc __noreturn soft_reset(void)
-{
- /* pll enter slow mode */
- cru_writel(0xffff0000, CRU_MODE_CON);
- dsb();
-
- /* restore clock select and divide */
- cru_writel(0xffff0200, CRU_CLKSELS_CON(0));
- cru_writel(0xffff3113, CRU_CLKSELS_CON(1));
- cru_writel(0xfff00000, CRU_CLKSELS_CON(2)); // 3:0 reserved
- cru_writel(0xffff0200, CRU_CLKSELS_CON(3));
- cru_writel(0x003f0000, CRU_CLKSELS_CON(4)); // 15:6 reserved
- cru_writel(0x003f0000, CRU_CLKSELS_CON(5)); // 15:6 reserved
- cru_writel(0x0bb8ea60, CRU_CLKSELS_CON(6));
- cru_writel(0x0bb8ea60, CRU_CLKSELS_CON(7));
- cru_writel(0xffff2100, CRU_CLKSELS_CON(10));
- cru_writel(0x007f0017, CRU_CLKSELS_CON(11)); // 15:7 reserved
- cru_writel(0xffff1717, CRU_CLKSELS_CON(12));
- cru_writel(0xffff0200, CRU_CLKSELS_CON(13));
- cru_writel(0xffff0200, CRU_CLKSELS_CON(14));
- cru_writel(0xffff0200, CRU_CLKSELS_CON(15));
- cru_writel(0x0bb8ea60, CRU_CLKSELS_CON(17));
- cru_writel(0x0bb8ea60, CRU_CLKSELS_CON(18));
- cru_writel(0x0bb8ea60, CRU_CLKSELS_CON(19));
- cru_writel(0x0bb8ea60, CRU_CLKSELS_CON(23));
- cru_writel(0xffff1700, CRU_CLKSELS_CON(24));
- cru_writel(0x017f0107, CRU_CLKSELS_CON(25)); // 15:9 7 reserved
- cru_writel(0xffff0000, CRU_CLKSELS_CON(26));
- cru_writel(0xffff0700, CRU_CLKSELS_CON(27));
- cru_writel(0xffff0700, CRU_CLKSELS_CON(28));
- cru_writel(0xffff0012, CRU_CLKSELS_CON(29));
- cru_writel(0xffff0300, CRU_CLKSELS_CON(30));
- cru_writel(0xffff0001, CRU_CLKSELS_CON(31));
- cru_writel(0xffff0303, CRU_CLKSELS_CON(32));
- cru_writel(0xffff0003, CRU_CLKSELS_CON(34));
- dsb();
-
- /* idle request PERI/VIO/VPU/GPU */
- grf_writel(0x1e00ffff, GRF_SOC_CON2);
- while ((grf_readl(GRF_SOC_STATUS0) & (0x1e << 16)) != (0x1e << 16))
- ;
- while ((grf_readl(GRF_SOC_STATUS0) & (0x1e << 22)) != (0x1e << 22))
- ;
-
- /* software reset modules */
-#ifdef DEBUG
- cru_writel(0xfff3ffff, CRU_SOFTRSTS_CON(8)); // CORE_DBG/DBG_APB
-#else
- cru_writel(0xffffffff, CRU_SOFTRSTS_CON(8));
-#endif
- cru_writel(0xffffffff, CRU_SOFTRSTS_CON(7));
- cru_writel(0xffffffff, CRU_SOFTRSTS_CON(6));
- cru_writel(0xffffffff, CRU_SOFTRSTS_CON(5));
- cru_writel(0x7fffffff, CRU_SOFTRSTS_CON(4)); // DDRMSCH
-#ifdef DEBUG
- cru_writel(0xff63ffff, CRU_SOFTRSTS_CON(3)); // DAP_PO/DAP/DAP_SYS
-#else
- cru_writel(0xff7fffff, CRU_SOFTRSTS_CON(3)); // GRF
-#endif
- cru_writel(0xfff0ffff, CRU_SOFTRSTS_CON(2)); // GPIO0/1/2/3
- cru_writel(0xffdfffff, CRU_SOFTRSTS_CON(1)); // INTMEM
-#ifdef DEBUG
- cru_writel(0x1e60ffff, CRU_SOFTRSTS_CON(0)); // MCORE_DBG/CORE0_DBG
-#else
- cru_writel(0x1fe0ffff, CRU_SOFTRSTS_CON(0)); // CORE_SRST_WDT_SEL/MCORE/CORE0/CORE1/ACLK_CORE/STRC_SYS_AXI/L2C
-#endif
- dsb();
-
- sram_udelay(1000);
-
- cru_writel(0xffff0000, CRU_SOFTRSTS_CON(0));
- cru_writel(0xffff0000, CRU_SOFTRSTS_CON(1));
- cru_writel(0xffff0000, CRU_SOFTRSTS_CON(2));
- cru_writel(0xffff0000, CRU_SOFTRSTS_CON(3));
- cru_writel(0xffff0000, CRU_SOFTRSTS_CON(4));
- cru_writel(0xffff0000, CRU_SOFTRSTS_CON(5));
- cru_writel(0xffff0000, CRU_SOFTRSTS_CON(6));
- cru_writel(0xffff0000, CRU_SOFTRSTS_CON(7));
- cru_writel(0xffff0000, CRU_SOFTRSTS_CON(8));
- dsb();
-
- /* disable idle request */
- grf_writel(0x3f000000, GRF_SOC_CON2);
- while (grf_readl(GRF_SOC_STATUS0) & (0x3f << 16))
- ;
- while (grf_readl(GRF_SOC_STATUS0) & (0x3f << 22))
- ;
-
-#ifdef DEBUG
-// while (reset_loop);
-#endif
-
- cru_writel(0x801cffff, CRU_SOFTRSTS_CON(0)); // MCORE/CORE0/CORE1/L2C
- dsb();
-
- while (1);
-}
-
-static void rk30_arch_reset(char mode, const char *cmd)
-{
- unsigned i;
- u32 boot_flag = 0;
- u32 boot_mode = BOOT_MODE_REBOOT;
-
- if (cmd) {
- if (!strcmp(cmd, "loader") || !strcmp(cmd, "bootloader"))
- boot_flag = SYS_LOADER_REBOOT_FLAG + BOOT_LOADER;
- else if(!strcmp(cmd, "recovery"))
- boot_flag = SYS_LOADER_REBOOT_FLAG + BOOT_RECOVER;
- else if (!strcmp(cmd, "charge"))
- boot_mode = BOOT_MODE_CHARGE;
- } else {
- if (is_panic)
- boot_mode = BOOT_MODE_PANIC;
- }
- grf_writel(boot_flag, GRF_OS_REG4); // for loader
- grf_writel(boot_mode, GRF_OS_REG5); // for linux
-
- /* enable all clock */
- for (i = 0; i < CRU_CLKGATES_CON_CNT; i++)
- cru_writel(0xffff0000, CRU_CLKGATES_CON(i));
-
- /* disable remap */
- grf_writel(1 << (12 + 16), GRF_SOC_CON0);
-
- ((void(*)(void))((u32)soft_reset - (u32)RK30_IMEM_BASE + (u32)RK30_IMEM_NONCACHED))();
-}
-
-void (*arch_reset)(char, const char *) = rk30_arch_reset;
+++ /dev/null
-#include <linux/clockchips.h>
-#include <linux/platform_device.h>
-#include <asm/mach/time.h>
-#include <asm/localtimer.h>
-#include <asm/smp_twd.h>
-#include <mach/io.h>
-#include <mach/irqs.h>
-
-#define TIMER_NAME "rk_timer"
-#define BASE RK2928_TIMER0_BASE
-#define OFFSET 0x20
-
-static struct resource rk_timer_resources[] __initdata = {
- {
- .name = "cs_base",
- .start = (unsigned long) BASE + 1 * OFFSET,
- .flags = IORESOURCE_MEM,
- }, {
- .name = "cs_clk",
- .start = (unsigned long) "timer1",
- }, {
- .name = "cs_pclk",
- .start = (unsigned long) "pclk_timer0",
- },
-
- {
- .name = "ce_base0",
- .start = (unsigned long) BASE + 0 * OFFSET,
- .flags = IORESOURCE_MEM,
- }, {
- .name = "ce_irq0",
- .start = (unsigned long) IRQ_TIMER0,
- .flags = IORESOURCE_IRQ,
- }, {
- .name = "ce_clk0",
- .start = (unsigned long) "timer0",
- }, {
- .name = "ce_pclk0",
- .start = (unsigned long) "pclk_timer0",
- },
-};
-
-static struct platform_device rk_timer_device __initdata = {
- .name = TIMER_NAME,
- .id = 0,
- .resource = rk_timer_resources,
- .num_resources = ARRAY_SIZE(rk_timer_resources),
-};
-
-static struct platform_device *rk_timer_devices[] __initdata = {
- &rk_timer_device,
-};
-
-static void __init rk_timer_init(void)
-{
-#ifdef CONFIG_HAVE_ARM_TWD
- twd_base = RK30_PTIMER_BASE;
-#endif
- early_platform_add_devices(rk_timer_devices, ARRAY_SIZE(rk_timer_devices));
- early_platform_driver_register_all(TIMER_NAME);
- early_platform_driver_probe(TIMER_NAME, 1, 0);
-}
-
-struct sys_timer rk30_timer = {
- .init = rk_timer_init
-};
-
-struct sys_timer rk2928_timer = {
- .init = rk_timer_init
-};
-
-#ifdef CONFIG_LOCAL_TIMERS
-/*
- * Setup the local clock events for a CPU.
- */
-int __cpuinit local_timer_setup(struct clock_event_device *evt)
-{
- evt->irq = IRQ_LOCALTIMER;
- twd_timer_setup(evt);
- evt->features &= ~CLOCK_EVT_FEAT_C3STOP;
- return 0;
-}
-#endif
+++ /dev/null
-choice
- prompt "Rockchip SoC Type"
- depends on ARCH_RK3188
-
-config SOC_RK3188
- bool "RK3188"
- select USB_ARCH_HAS_EHCI if USB_SUPPORT
-
-config SOC_RK3188M
- bool "RK3188M"
- select USB_ARCH_HAS_EHCI if USB_SUPPORT
-
-endchoice
-
-choice
- prompt "RK3188 Board Type"
- depends on SOC_RK3188
-
-config MACH_RK3188_TB
- bool "RK3188 Top Board"
-
-config MACH_RK3188_SDK
- bool "RK3188 sdk Board"
-
-config MACH_RK3188_FPGA
- bool "RK3188 FPGA board"
- select RK_FPGA
-
-config MACH_RK3188_LR097
- bool "RK3188 LR097 JC21CA board"
-
-config MACH_RK3188_DS1006H
- bool "RK3188 ds1006h board"
-
-config MACH_RK3188_U30GT2
- bool "RK3188 u30gt2 board"
-
-
-config MACH_RK3188_FAC
- bool "RK3188 Board for factory"
- select MACH_RK_FAC
-
-config MACH_RK3188_JETTAB
- bool "RK3188 jettaB top board"
-
-config MACH_RK3188_RK618
- bool "RK3188 RK618 sdk"
-
-config MACH_RK3188_FT
- bool "RK3188 FT Board"
-config MACH_RK3188_AC
- bool "RK3188 android computer board"
-
-endchoice
-
-choice
- prompt "RK3188M Board Type"
- depends on SOC_RK3188M
-
-config MACH_RK3188M_TB
- bool "RK3188m Top Board"
-
-config MACH_RK3188M_F304
- bool "RK3188m F304 Board"
-
-endchoice
+++ /dev/null
-EXTRA_CFLAGS += -Os
-ifneq ($(CONFIG_RK_FPGA),y)
-obj-y += ../plat-rk/clock.o
-obj-y += clock_data.o
-obj-y += ../mach-rk30/ddr.o
-obj-y += ../mach-rk30/pmu.o
-obj-y += ../mach-rk30/reset.o
-obj-$(CONFIG_PM) += ../mach-rk30/pm.o
-endif
-obj-y += ../mach-rk30/common.o
-CFLAGS_common.o += -DTEXT_OFFSET=$(TEXT_OFFSET)
-obj-y += ../mach-rk30/devices.o
-obj-y += io.o
-obj-y += rk_timer.o
-obj-$(CONFIG_SMP) += ../mach-rk30/platsmp.o ../mach-rk30/headsmp.o
-obj-$(CONFIG_HOTPLUG_CPU) += ../mach-rk30/hotplug.o
-obj-$(CONFIG_CPU_IDLE) += ../mach-rk30/cpuidle.o
-obj-$(CONFIG_CPU_FREQ) += cpufreq.o
-obj-$(CONFIG_DVFS) += dvfs.o
-obj-y += board.o
-obj-y += delayline.o
-
-board-$(CONFIG_MACH_RK3188_FPGA) += board-rk3188-fpga.o
-board-$(CONFIG_MACH_RK3188_TB) += ../mach-rk30/board-rk3168-tb.o
-board-$(CONFIG_MACH_RK3188_FT) += board-rk3188-ft.o
-board-$(CONFIG_MACH_RK3188_SDK) += board-rk3188-sdk.o
-board-$(CONFIG_MACH_RK3188_LR097) += ../mach-rk30/board-rk3168-LR097.o
-board-$(CONFIG_MACH_RK3188_DS1006H) += board-rk3188-ds1006h.o
-board-$(CONFIG_MACH_RK3188_U30GT2) += board-rk3188-u30gt2.o
-board-$(CONFIG_MACH_RK3188_JETTAB) += board-rk3188-jettaplus.o
-board-$(CONFIG_MACH_RK3188_RK618) += board-rk3188-jettaplus.o
-board-$(CONFIG_MACH_RK3188M_TB) += board-rk3188m-tb.o
-board-$(CONFIG_MACH_RK3188M_F304) += board-rk3188m-f304.o
-obj-$(CONFIG_SOC_RK3188) += board.o
-board-$(CONFIG_MACH_RK3188_FAC) += board-rk3188-fac.o
-board-$(CONFIG_MACH_RK3188_AC) += board-rk3188-ac.o
+++ /dev/null
-include $(srctree)/arch/arm/mach-rk30/Makefile.boot
+++ /dev/null
-/*****************************************************************************************
- * arch/arm/mach-rkxx/baord-xxx-sdmmc-config.c
- *
- * Copyright (C) 2013 ROCKCHIP, Inc.
- *
- * Description:
- * define the gpio for SD-MMC-SDIO-Wifi functions according to your own projects.
- *
- * Author: Michael Xie
- * 15 Jan,2013
- * E-mail: xbw@rock-chips.com
- *
- ******************************************************************************************/
-
-#define DS1006H_V1_2_SUPPORT 1
-
-/*
-** If you select the macro of CONFIG_SDMMC0_RK29_WRITE_PROTECT, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define SDMMC0_WRITE_PROTECT_PIN RK30_PIN3_PB2 //According to your own project to set the value of write-protect-pin.
-//#define SDMMC0_WRITE_PROTECT_ENABLE_VALUE GPIO_HIGH
-
-/*
-** If you select the macro of CONFIG_SDMMC1_RK29_WRITE_PROTECT, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define SDMMC1_WRITE_PROTECT_PIN RK30_PIN3_PB3 //According to your own project to set the value of write-protect-pin.
-//#define SDMMC1_WRITE_PROTECT_ENABLE_VALUE GPIO_HIGH
-
-/*
-** If you select the macro of CONFIG_RK29_SDIO_IRQ_FROM_GPIO, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define RK29SDK_WIFI_SDIO_CARD_INT RK30_PIN3_PD2
-
-
-/*
-* define sdcard PowerEn-pin
-*/
-#define RK29SDK_SD_CARD_PWR_EN RK30_PIN3_PA1
-#define RK29SDK_SD_CARD_PWR_EN_LEVEL GPIO_LOW
-int rk31sdk_get_sdmmc0_pin_io_voltage(void)
-{
- int voltage;
-#define RK31SDK_SET_SDMMC0_PIN_VOLTAGE
-
- /**************************************************************************************
- ** Please tell me how much voltage of your SDMMC0-pin in your project.
- **
- ** ÀýÈç: ÓеÄÏîÄ¿£¬ËüµÄSDMMC0ËùÔÚµÄRKÖ÷¿ØµÄIO×飬ÏëÓÃ1.8V, ¶ø¿¨±¾ÉíÓÃ3.3V,
- ** ¶øÖмäͨ¹ý¸öµçƽת»».ÄÇô£¬Äú´Ëʱ£¬Ó¦¸ÃÉèÖÃÏÂÃæµÄvoltageֵΪ 1.8V(¼´1800mv)
- ***************************************************************************************/
- voltage = 3300; //default the voltage 3300mv.
-
- return voltage;
-}
-
-/*
-* define the card-detect-pin.
-*/
-#define RK29SDK_SD_CARD_DETECT_N RK30_PIN3_PB0 //According to your own project to set the value of card-detect-pin.
-#define RK29SDK_SD_CARD_INSERT_LEVEL GPIO_LOW // set the voltage of insert-card. Please pay attention to the default setting.
-
-#define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
-#define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
-
-/*
-* Define wifi module's power and reset gpio, and gpio sensitive level.
-* Please set the value according to your own project.
-*
-* Well, you just own engineering module to set the value in the corresponding module branch.
-* Otherwise, you do not define this macro, eliminate it.
-*
-*/
-#if defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU) || defined(CONFIG_RTL8723AU)
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_LOW//GPIO_HIGH
-
-#elif defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319) || defined(CONFIG_RKWIFI) \
- || defined(CONFIG_RTL8189ES)
-
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PA1
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- //#define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN2_PA7
- //#define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
-
-#elif defined(CONFIG_MT5931_MT6622) || defined(CONFIG_MT5931)
-
- #ifdef CONFIG_MACH_RK3168_LR097
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- //#define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- //#define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
-
- #else
- #if DS1006H_V1_2_SUPPORT
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- #else
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN0_PA5
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #endif
- #endif
-
-#elif defined(CONFIG_MT6620)
- #define COMBO_MODULE_MT6620_CDT 1 // to control antsel2,antsel3 and gps_lan foot when using AcSip or Cdtech chip.
- //- 1--use Cdtech chip; 0--unuse CDT chip
-
- //power, PMU_EN
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PC7
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- //reset, DAIRST,SYSRST_B
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- //VDDIO
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL RK30_PIN0_PD2 //You do not get control of the foot, and you do not need to define the macro
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_ENABLE_VALUE GPIO_HIGH
- //WIFI_INT_B
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
- //BGF_INT_B
- #define RK30SDK_WIFI_GPIO_BGF_INT_B RK30_PIN6_PA7
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_ENABLE_VALUE GPIO_HIGH
- //GPS_SYNC
- #define RK30SDK_WIFI_GPIO_GPS_SYNC RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_ENABLE_VALUE GPIO_HIGH
-
- #if COMBO_MODULE_MT6620_CDT
- //ANTSEL2
- #define RK30SDK_WIFI_GPIO_ANTSEL2 RK30_PIN4_PD4
- #define RK30SDK_WIFI_GPIO_ANTSEL2_ENABLE_VALUE GPIO_LOW //use 6620 in CDT chip, LOW--work; High--no work.
- //ANTSEL3
- #define RK30SDK_WIFI_GPIO_ANTSEL3 RK30_PIN4_PD3
- #define RK30SDK_WIFI_GPIO_ANTSEL3_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- //GPS_LAN
- #define RK30SDK_WIFI_GPIO_GPS_LAN RK30_PIN4_PD6
- #define RK30SDK_WIFI_GPIO_GPS_LAN_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- #endif // #if COMBO_MODULE_MT6620_CDT--#endif
-#endif
-
-int rk31sdk_get_sdio_wifi_voltage(void)
-{
- int voltage;
-
- /******************************************************************************
- ** Please tell me how much wifi-module uses voltage in your project.
- ******************************************************************************/
-#if defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319) || defined(CONFIG_RKWIFI)
- voltage = 1800 ; //power 1800mV
-
-#elif defined(CONFIG_MT5931_MT6622)||defined(CONFIG_MT5931)
- voltage = 2800 ; //power 1800V
-#elif defined(CONFIG_MT6620)
- voltage = 2800 ; //power 2800V
-#elif defined(CONFIG_RDA5990)||defined(CONFIG_RTL8723AS) || defined(CONFIG_RTL8189ES)
- voltage = 3300 ; //power 3300V
-#else
- //default, sdio use 3.0V
- voltage = 3000 ; //power 3000V
-#endif
-
- return voltage;
-}
-
-
-
+++ /dev/null
-/*
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <mach/dvfs.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <linux/rk_fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/mfd/tps65910.h>
-#include <linux/regulator/act8846.h>
-#include <plat/efuse.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-#if defined(CONFIG_CT36X_TS)
-#include <linux/ct36x.h>
-#endif
-#if defined(CONFIG_MFD_RK610)
-#include <linux/mfd/rk610_core.h>
-#endif
-
-#if defined(CONFIG_RK_HDMI)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-#if defined(CONFIG_MT6229)
-#include <linux/mt6229.h>
-#endif
-#if defined(CONFIG_GPS_RK)
-#include "../../../drivers/misc/gps/rk_gps/rk_gps.h"
-#endif
-
-#if defined(CONFIG_MT6620)
-#include <linux/gps.h>
-#endif
-#ifdef CONFIG_RK_REMOTECTL
-#include <mach/remotectl.h>
-#endif
-
-#include "../mach-rk30/board-rk3168-ds1006h-camera.c"
-#include <plat/key.h>
-#include <linux/scaler-core.h>
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK30_PIN0_PA4,
- .active_low = PRESS_LEV_LOW,
- .wakeup = 1,
- },
-/*
- {
- .desc = "esc",
- .code = KEY_BACK,
- .adc_value = 1,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- */
- {
- .desc = "mode_switch",
- .code = 248,
- //.desc = "vol+",
- //.code = KEY_VOLUMEUP,
-
- .adc_value = 1,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- .wakeup = 1
- },
-
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = 1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
-/*
- v1.0 : ignore
- v1.1 : rk610 lvds + rk610 codec + MT5931_MT6622 + light photoresistor + adc/cw2015
- v1.2 : lvds + rt5631 + M500 + us5151 + adc
-*/
-#define DS1006H_V1_2_SUPPORT 1
-int get_harware_version()
-{
- #if DS1006H_V1_2_SUPPORT
- return 2;
- #else
- return 1;
- #endif
-}
-EXPORT_SYMBOL_GPL(get_harware_version);
-
-#if defined(CONFIG_CT36X_TS)
-
-#define TOUCH_MODEL 363
-#define TOUCH_MAX_X 1280
-#define TOUCH_MAX_y 800
-#define TOUCH_RESET_PIN RK30_PIN0_PB6
-#define TOUCH_INT_PIN RK30_PIN1_PB7
-
-static struct ct36x_platform_data ct36x_info = {
- .model = TOUCH_MODEL,
- .x_max = TOUCH_MAX_X,
- .y_max = TOUCH_MAX_y,
-
- .rst_io = {
- .gpio = TOUCH_RESET_PIN,
- .active_low = 1,
- },
- .irq_io = {
- .gpio = TOUCH_INT_PIN,
- .active_low = 1,
- },
- .orientation = {1, 0, 0, 1},
-};
-#endif
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-#define PWM_ID 3
-#define PWM_MODE PWM3
-#define PWM_EFFECT_VALUE 1
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-#define BL_EN_PIN RK30_PIN0_PA2
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
-
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
- ret = gpio_request(BL_EN_PIN, NULL);
- if (ret != 0) {
- gpio_free(BL_EN_PIN);
- }
-
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
-
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0, pwm_gpio;
-
-#ifdef LCD_DISP_ON_PIN
- gpio_free(BL_EN_PIN);
-#endif
-
- pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
- gpio_request(pwm_gpio, NULL);
- gpio_direction_output(pwm_gpio, GPIO_LOW);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret = 0, pwm_gpio;
-
- pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
- if (gpio_request(pwm_gpio, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- gpio_direction_output(pwm_gpio, GPIO_LOW);
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, !BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- int pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
-
- gpio_free(pwm_gpio);
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, 1);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .min_brightness = 65,
- .max_brightness = 150,
- .brightness_mode =BRIGHTNESS_MODE_CONIC,
- .pre_div = 30 * 1000, // pwm output clk: 30k;
- .pwm_id = PWM_ID,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-#endif
-#ifdef CONFIG_RK_REMOTECTL
-
-void rk30_remotectl_iomux(void)
-{
- ;
-}
-
-struct RKxx_remotectl_platform_data rk30_remotectl_pdata = {
- .gpio = RK30_PIN0_PA3,
- .wakeup = 1,
- .rep = 0,
- .set_iomux = rk30_remotectl_iomux,
-};
-
-static struct platform_device rk30_device_remotectl = {
- .name = "rkxx-remotectl",
- .id = -1,
- .dev = {
- .platform_data = &rk30_remotectl_pdata,
- },
-};
-#endif
-
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN RK30_PIN0_PB7
-
-static int mma8452_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data mma8452_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma8452_init_platform_hw,
- .orientation = {-1, 0, 0, 0, 0, -1, 0, 1, 0},
-};
-#endif
-#if defined (CONFIG_GS_LIS3DH)
-#define LIS3DH_INT_PIN RK30_PIN0_PB7
-
-static int lis3dh_init_platform_hw(void)
-{
-
- return 0;
-}
-
-static struct sensor_platform_data lis3dh_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lis3dh_init_platform_hw,
- .orientation = {-1, 0, 0, 0, 1, 0, 0, 0, -1},
-};
-#endif
-
-#if defined (CONFIG_COMPASS_AK8963)
-static struct sensor_platform_data akm8963_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {0, 1, 0},
- {1, 0, 0},
- {0, 0, -1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {0, -1, 0},
- {-1, 0, 0},
- {0, 0, -1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-#if defined(CONFIG_LS_PHOTORESISTOR)
-static struct sensor_platform_data light_photoresistor_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 0,
- .address = 2 ,
- .poll_delay_ms = 200,
-};
-#endif
-
-#if defined (CONFIG_COMPASS_AK8975)
-static struct sensor_platform_data akm8975_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-#if defined(CONFIG_MT6229)
-static int mt6229_io_init(void)
-{
- #if 0
- rk30_mux_api_set(GPIO2B6_LCDC1DATA14_SMCADDR18_TSSYNC_NAME, GPIO2B_GPIO2B6);
- k30_mux_api_set(GPIO4D2_SMCDATA10_TRACEDATA10_NAME, GPIO4D_GPIO4D2);
- rk30_mux_api_set(GPIO2B7_LCDC1DATA15_SMCADDR19_HSADCDATA7_NAME, GPIO2B_GPIO2B7);
- rk30_mux_api_set(GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME, GPIO2C_GPIO2C0);
- rk30_mux_api_set(GPIO2C1_LCDC1DATA17_SMCBLSN0_HSADCDATA6_NAME, GPIO2C_GPIO2C1);
- rk30_mux_api_set(GPIO2C1_LCDC1DATA17_SMCBLSN0_HSADCDATA6_NAME, GPIO2C_GPIO2C1);
- #endif
- return 0;
-}
-
-static int mt6229_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mt6229_data rk29_mt6229_info = {
- .io_init = mt6229_io_init,
- .io_deinit = mt6229_io_deinit,
- .modem_power_en = RK30_PIN0_PC6,
- .bp_power = RK30_PIN2_PD5,
- .modem_usb_en = RK30_PIN0_PC7,
- .modem_uart_en = RK30_PIN2_PD4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
- .ap_ready = RK30_PIN0_PC4,
-
-};
-struct platform_device rk29_device_mt6229 = {
- .name = "mt6229",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mt6229_info,
- }
- };
-#endif
-
-#if defined(CONFIG_GYRO_L3G4200D)
-
-#include <linux/l3g4200d.h>
-#define L3G4200D_INT_PIN RK30_PIN0_PB4
-
-static int l3g4200d_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data l3g4200d_info = {
- .type = SENSOR_TYPE_GYROSCOPE,
- .irq_enable = 1,
- .poll_delay_ms = 0,
- .orientation = {1, 0, 0 , 0 , -1, 0, 0, 0, -1},
- .init_platform_hw = l3g4200d_init_platform_hw,
- .x_min = 40,//x_min,y_min,z_min = (0-100) according to hardware
- .y_min = 40,
- .z_min = 20,
-};
-
-#endif
-
-#ifdef CONFIG_LS_CM3217
-static struct sensor_platform_data cm3217_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 0,
- .poll_delay_ms = 500,
-};
-
-#endif
-
-#ifdef CONFIG_FB_ROCKCHIP
-
-#if DS1006H_V1_2_SUPPORT
-#define LCD_CS_PIN RK30_PIN0_PB0
-#else
-#define LCD_CS_PIN INVALID_GPIO
-#endif
-#define LCD_CS_VALUE GPIO_HIGH
-
-#if DS1006H_V1_2_SUPPORT
-#define LCD_EN_PIN RK30_PIN0_PB1
-#else
-#define LCD_EN_PIN RK30_PIN0_PB0
-#endif
-#define LCD_EN_VALUE GPIO_LOW
-
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
-
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_CS_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_CS_PIN);
- printk(KERN_ERR "request lcd cs pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_CS_PIN, LCD_CS_VALUE);
- }
- }
-
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_EN_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_EN_PIN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_EN_PIN, LCD_EN_VALUE);
- }
- }
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, !LCD_CS_VALUE);
- }
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, !LCD_EN_VALUE);
- }
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE);
- }
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
- }
- return 0;
-}
-
-#if defined(CONFIG_LCDC1_RK3188)
-struct rk29fb_info lcdc1_screen_info = {
- .prop = EXTEND, //extend display device
- .lcd_info = NULL,
- .set_screen_info = hdmi_init_lcdc,
-
-};
-#endif
-extern void set_vga_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info);
-
-#if defined(CONFIG_LCDC0_RK3188)
-struct rk29fb_info lcdc0_screen_info = {
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- //.set_screen_info = set_lcd_info,
- .set_screen_info = set_vga_lcd_info,
-
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-
-#if defined(CONFIG_ARCH_RK3188)
-static struct resource resource_mali[] = {
- [0] = {
- .name = "ump buf",
- .start = 0,
- .end = 0,
- .flags = IORESOURCE_MEM,
- },
-
-};
-
-static struct platform_device device_mali= {
- .name = "mali400_ump",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_mali),
- .resource = resource_mali,
-};
-#endif
-
-#if defined(CONFIG_LCDC0_RK3188)
-static struct resource resource_lcdc0[] = {
- [0] = {
- .name = "lcdc0 reg",
- .start = RK30_LCDC0_PHYS,
- .end = RK30_LCDC0_PHYS + RK30_LCDC0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc0 irq",
- .start = IRQ_LCDC0,
- .end = IRQ_LCDC0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc0 = {
- .name = "rk30-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc0),
- .resource = resource_lcdc0,
- .dev = {
- .platform_data = &lcdc0_screen_info,
- },
-};
-#endif
-#if defined(CONFIG_LCDC1_RK3188)
-static struct resource resource_lcdc1[] = {
- [0] = {
- .name = "lcdc1 reg",
- .start = RK30_LCDC1_PHYS,
- .end = RK30_LCDC1_PHYS + RK30_LCDC1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc1 irq",
- .start = IRQ_LCDC1,
- .end = IRQ_LCDC1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc1 = {
- .name = "rk30-lcdc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resource_lcdc1),
- .resource = resource_lcdc1,
- .dev = {
- .platform_data = &lcdc1_screen_info,
- },
-};
-#endif
-
-#if defined(CONFIG_MFD_RK610)
-#define RK610_RST_PIN RK30_PIN3_PB2
-static int rk610_power_on_init(void)
-{
- int ret;
- if(RK610_RST_PIN != INVALID_GPIO)
- {
- ret = gpio_request(RK610_RST_PIN, "rk610 reset");
- if (ret)
- {
- printk(KERN_ERR "rk610_control_probe request gpio fail\n");
- }
- else
- {
- gpio_direction_output(RK610_RST_PIN, GPIO_HIGH);
- msleep(100);
- gpio_direction_output(RK610_RST_PIN, GPIO_LOW);
- msleep(100);
- gpio_set_value(RK610_RST_PIN, GPIO_HIGH);
- }
- }
-
- return 0;
-
-}
-
-
-static struct rk610_ctl_platform_data rk610_ctl_pdata = {
- .rk610_power_on_init = rk610_power_on_init,
-};
-#endif
-
-#ifdef CONFIG_SND_SOC_RK610
-static int rk610_codec_io_init(void)
-{
-//if need iomux.
-//Must not gpio_request
- return 0;
-}
-
-static struct rk610_codec_platform_data rk610_codec_pdata = {
- .spk_ctl_io = RK30_PIN2_PD7,
- .io_init = rk610_codec_io_init,
- .boot_depop = 1,
-};
-#endif
-
-#ifdef CONFIG_RK_HDMI
-#define RK_HDMI_RST_PIN RK30_PIN3_PB2
-static int rk_hdmi_power_init(void)
-{
- int ret;
-
- if(RK_HDMI_RST_PIN != INVALID_GPIO)
- {
- if (gpio_request(RK_HDMI_RST_PIN, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- gpio_direction_output(RK_HDMI_RST_PIN, GPIO_LOW);
- gpio_set_value(RK_HDMI_RST_PIN, GPIO_LOW);
- msleep(100);
- gpio_set_value(RK_HDMI_RST_PIN, GPIO_HIGH);
- msleep(50);
- }
- return 0;
-}
-static struct rk_hdmi_platform_data rk_hdmi_pdata = {
- //.io_init = rk_hdmi_power_init,
-};
-#endif
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and sdio.noted by xbw at 2012-03-05
-**************************************************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "board-rk3188-ac-sdmmc-config.c"
-#include "../plat-rk/rk-sdmmc-ops.c"
-#include "../plat-rk/rk-sdmmc-wifi.c"
-#endif //endif ---#ifdef CONFIG_SDMMC_RK29
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- iomux_set(MMC0_CMD);
- iomux_set(MMC0_CLKOUT);
- iomux_set(MMC0_D0);
- iomux_set(MMC0_D1);
- iomux_set(MMC0_D2);
- iomux_set(MMC0_D3);
-
- iomux_set_gpio_mode(iomux_mode_to_gpio(MMC0_DETN));
-
- gpio_request(RK30_PIN3_PA7, "sdmmc-power");
- gpio_direction_output(RK30_PIN3_PA7, GPIO_LOW);
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- #if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set_gpio_mode(iomux_gpio_to_mode(RK29SDK_SD_CARD_DETECT_N));
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO);
- #endif
- #else
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(MMC0_DETN);
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FMUX);
- #endif
- #endif
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- .status = rk29sdk_wifi_mmc0_status,
- .register_status_notify = rk29sdk_wifi_mmc0_status_register,
-#endif
-
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .power_en = RK29SDK_SD_CARD_PWR_EN,
- .power_en_level = RK29SDK_SD_CARD_PWR_EN_LEVEL,
-#else
- .power_en = INVALID_GPIO,
- .power_en_level = GPIO_LOW,
-#endif
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC0_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- .det_pin_info = {
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N, //INVALID_GPIO,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
- #endif
- },
-
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- iomux_set(MMC1_CMD);
- iomux_set(MMC1_CLKOUT);
- iomux_set(MMC1_D0);
- iomux_set(MMC1_D1);
- iomux_set(MMC1_D2);
- iomux_set(MMC1_D3);
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC) || defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC1_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- #if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
- .sdio_INT_gpio = RK29SDK_WIFI_SDIO_CARD_INT,
- #endif
-
- .det_pin_info = {
-#if defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- #else
- .io = INVALID_GPIO,
- #endif
-
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-
- .enable_sd_wakeup = 0,
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-/**************************************************************************************************
- * the end of setting for SDMMC devices
-**************************************************************************************************/
-
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
-static int ac_current = -1;
-#define CHARING_CURRENT_500MA 0
-#define CHARING_CURRENT_1000MA 1
-
-#define DC_CUR_SET_PIN RK30_PIN0_PB0
-#define CHARGE_OK_PIN RK30_PIN0_PA6
-#define DC_DET_PIN RK30_PIN0_PB2
-static int rk30_battery_adc_io_init(void)
-{
- int ret = 0;
- printk("charging: set charging current 500ma \n");
- ac_current = CHARING_CURRENT_500MA;
- //dc charge detect pin
- ret = gpio_request(DC_DET_PIN, NULL);
- if (ret) {
- printk("failed to request dc_det gpio\n");
- return ret ;
- }
-
- gpio_pull_updown(DC_DET_PIN, 1);//important
- ret = gpio_direction_input(DC_DET_PIN);
- if (ret) {
- printk("failed to set gpio dc_det input\n");
- return ret ;
- }
-
- //charge ok pin
- ret = gpio_request(CHARGE_OK_PIN, NULL);
- if (ret) {
- printk("failed to request charge_ok gpio\n");
- return ret ;
- }
-
- gpio_pull_updown(CHARGE_OK_PIN, 1);//important
- ret = gpio_direction_input(CHARGE_OK_PIN);
- if (ret) {
- printk("failed to set gpio charge_ok input\n");
- return ret ;
- }
- //charge current set pin
- ret = gpio_request(DC_CUR_SET_PIN, NULL);
- if (ret) {
- printk("failed to request DC_CUR_SET_PIN gpio\n");
- return ret ;
- }
-
- ret = gpio_direction_output(DC_CUR_SET_PIN, GPIO_LOW);//500ma
- if (ret) {
- printk("failed to set gpio DC_CUR_SET_PIN output\n");
- return ret ;
- }
-
- return 0;
-
-}
-
-static int set_usb_charging_current(int mode)
-{
-#if 0
- if ( (ac_current==CHARING_CURRENT_1000MA) && (mode == PC_MODE) ) {
- gpio_set_value(DC_CUR_SET_PIN, GPIO_LOW);
- ac_current = CHARING_CURRENT_500MA;
- }
- else if ((mode == ADAPT_MODE) && (ac_current==CHARING_CURRENT_500MA))
- {
- gpio_set_value(DC_CUR_SET_PIN, GPIO_HIGH);
- ac_current = CHARING_CURRENT_1000MA;
-
- }
-#endif
- gpio_set_value(DC_CUR_SET_PIN, GPIO_LOW);
- ac_current = CHARING_CURRENT_500MA;
-}
-
-
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = RK30_PIN0_PB2,
- .batt_low_pin = INVALID_GPIO,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = RK30_PIN0_PA6,
- .usb_det_pin = INVALID_GPIO,
- .dc_det_level = GPIO_LOW,
- .charge_ok_level = GPIO_HIGH,
-
- .reference_voltage = 1800, // the rK2928 is 3300;RK3066 and rk29 are 2500;rk3066B is 1800;
- .pull_up_res = 200, //divider resistance , pull-up resistor
- .pull_down_res = 120, //divider resistance , pull-down resistor
-
- .is_reboot_charging = 1,
- .save_capacity = 1 ,
- .low_voltage_protection = 3600,
- .io_init = rk30_battery_adc_io_init,
- .control_usb_charging= set_usb_charging_current,
-};
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-#ifdef CONFIG_RK30_PWM_REGULATOR
-static int pwm_voltage_map[] = {
- 800000,825000,850000, 875000,900000, 925000 ,950000, 975000,1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000,1375000
-};
-
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_cpu",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] =
-{
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
- .pwm_id = 1,
- .pwm_gpio = RK30_PIN3_PD4,
- .pwm_iomux_pwm = PWM1,
- .pwm_iomux_gpio = GPIO3_D4,
- .pwm_voltage = 1100000,
- .suspend_voltage = 1000000,
- .min_uV = 800000,
- .max_uV = 1375000,
- .coefficient = 575, //57.5%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-#endif
-
-#ifdef CONFIG_RK29_VMAC
-#define PHY_PWR_EN_GPIO INVALID_GPIO
-#define PHY_PWR_EN_IOMUX GPIO3_D2
-#define PHY_PWR_EN_VALUE GPIO_HIGH
-#define RMII_EXT_CLK
-#include "../mach-rk30/board-rk31-sdk-vmac.c"
-#endif
-
-#ifdef CONFIG_RFKILL_RK
-// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
-static struct rfkill_rk_platform_data rfkill_rk_platdata = {
- .type = RFKILL_TYPE_BLUETOOTH,
-
- .poweron_gpio = { // BT_REG_ON
- .io = INVALID_GPIO, //RK30_PIN3_PC7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_poweron",
- .fgpio = GPIO3_C7,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN3_PA0, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_reset",
- .fgpio = GPIO3_A0,
- },
- },
-
- .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
- .io = RK30_PIN3_PB0, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_wake",
- .fgpio = GPIO3_B0,
- },
- },
-
- .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .gpio = {
- .io = RK30_PIN3_PB1, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
- .iomux = {
- .name = NULL,
- },
- },
- },
-
- .rts_gpio = { // UART_RTS, enable or disable BT's data coming
- .io = RK30_PIN1_PA3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_rts",
- .fgpio = GPIO1_A3,
- .fmux = UART0_RTSN,
- },
- },
-};
-
-static struct platform_device device_rfkill_rk = {
- .name = "rfkill_rk",
- .id = -1,
- .dev = {
- .platform_data = &rfkill_rk_platdata,
- },
-};
-#endif
-
-#if defined(CONFIG_GPS_RK)
-int rk_gps_io_init(void)
-{
- printk("%s \n", __FUNCTION__);
-
- rk30_mux_api_set(GPIO1B5_UART3RTSN_NAME, GPIO1B_GPIO1B5);//VCC_EN
- gpio_request(RK30_PIN1_PB5, NULL);
- gpio_direction_output(RK30_PIN1_PB5, GPIO_LOW);
-
- rk30_mux_api_set(GPIO1B4_UART3CTSN_GPSRFCLK_NAME, GPIO1B_GPSRFCLK);//GPS_CLK
- rk30_mux_api_set(GPIO1B2_UART3SIN_GPSMAG_NAME, GPIO1B_GPSMAG);//GPS_MAG
- rk30_mux_api_set(GPIO1B3_UART3SOUT_GPSSIG_NAME, GPIO1B_GPSSIG);//GPS_SIGN
-
- rk30_mux_api_set(GPIO1A6_UART1CTSN_SPI0CLK_NAME, GPIO1A_GPIO1A6);//SPI_CLK
- gpio_request(RK30_PIN1_PA6, NULL);
- gpio_direction_output(RK30_PIN1_PA6, GPIO_LOW);
-
- rk30_mux_api_set(GPIO1A5_UART1SOUT_SPI0TXD_NAME, GPIO1A_GPIO1A5);//SPI_MOSI
- gpio_request(RK30_PIN1_PA5, NULL);
- gpio_direction_output(RK30_PIN1_PA5, GPIO_LOW);
-
- rk30_mux_api_set(GPIO1A7_UART1RTSN_SPI0CSN0_NAME, GPIO1A_GPIO1A7);//SPI_CS
- gpio_request(RK30_PIN1_PA7, NULL);
- gpio_direction_output(RK30_PIN1_PA7, GPIO_LOW);
- return 0;
-}
-int rk_gps_power_up(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_power_down(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_reset_set(int level)
-{
- return 0;
-}
-int rk_enable_hclk_gps(void)
-{
- printk("%s \n", __FUNCTION__);
- clk_enable(clk_get(NULL, "hclk_gps"));
- return 0;
-}
-int rk_disable_hclk_gps(void)
-{
- printk("%s \n", __FUNCTION__);
- clk_disable(clk_get(NULL, "hclk_gps"));
- return 0;
-}
-struct rk_gps_data rk_gps_info = {
- .io_init = rk_gps_io_init,
- .power_up = rk_gps_power_up,
- .power_down = rk_gps_power_down,
- .reset = rk_gps_reset_set,
- .enable_hclk_gps = rk_enable_hclk_gps,
- .disable_hclk_gps = rk_disable_hclk_gps,
- .GpsSign = RK30_PIN1_PB3,
- .GpsMag = RK30_PIN1_PB2, //GPIO index
- .GpsClk = RK30_PIN1_PB4, //GPIO index
- .GpsVCCEn = RK30_PIN1_PB5, //GPIO index
- .GpsSpi_CSO = RK30_PIN1_PA4, //GPIO index
- .GpsSpiClk = RK30_PIN1_PA5, //GPIO index
- .GpsSpiMOSI = RK30_PIN1_PA7, //GPIO index
- .GpsIrq = IRQ_GPS,
- .GpsSpiEn = 0,
- .GpsAdcCh = 2,
- .u32GpsPhyAddr = RK30_GPS_PHYS,
- .u32GpsPhySize = RK30_GPS_SIZE,
-};
-
-struct platform_device rk_device_gps = {
- .name = "gps_hv5820b",
- .id = -1,
- .dev = {
- .platform_data = &rk_gps_info,
- }
- };
-#endif
-
-#if defined(CONFIG_MT5931_MT6622)
-static struct mt6622_platform_data mt6622_platdata = {
- .power_gpio = { // BT_REG_ON
- #if DS1006H_V1_2_SUPPORT
- .io = RK30_PIN3_PC7, // set io to INVALID_GPIO for disable it
- #else
- .io = RK30_PIN3_PD5, // set io to INVALID_GPIO for disable it
- #endif
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .reset_gpio = { // BT_RST
- #if DS1006H_V1_2_SUPPORT
- .io = RK30_PIN3_PD1,
- #else
- .io = RK30_PIN0_PD7,
- #endif
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .irq_gpio = {
- #if DS1006H_V1_2_SUPPORT
- .io = RK30_PIN0_PA5,
- #else
- .io = RK30_PIN3_PD2,
- #endif
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- }
-};
-
-static struct platform_device device_mt6622 = {
- .name = "mt6622",
- .id = -1,
- .dev = {
- .platform_data = &mt6622_platdata,
- },
-};
-#endif
-
-#if defined CONFIG_TCC_BT_DEV
-static struct tcc_bt_platform_data tcc_bt_platdata = {
-
- .power_gpio = { // ldoon
- .io = RK2928_PIN3_PC0,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .wake_host_gpio = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .io = RK2928_PIN0_PC5, // set io to INVALID_GPIO for disable it
- .enable = IRQF_TRIGGER_RISING,// set IRQF_TRIGGER_FALLING for falling, set IRQF_TRIGGER_RISING for rising
- .iomux = {
- .name = NULL,
- },
- },
-};
-
-static struct platform_device device_tcc_bt = {
- .name = "tcc_bt_dev",
- .id = -1,
- .dev = {
- .platform_data = &tcc_bt_platdata,
- },
-};
-#endif
-
-#if defined(CONFIG_AC_USB_SWITCH)
-static struct ac_usb_switch_platform_data ac_usb_switch_platdata= {
- .usb_switch_pin = RK30_PIN3_PB2,
- .pc_state_pin = INVALID_GPIO,
-};
-static struct platform_device device_ac_usb_switch = {
- .name = "ac_usb_switch",
- .id = -1,
- .dev = {
- .platform_data = &ac_usb_switch_platdata,
- },
-};
-#endif
-
-static struct platform_device *devices[] __initdata = {
-
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- &rk29sdk_wifi_device,
-#endif
-
-#if defined(CONFIG_MT6620)
- &mt3326_device_gps,
-#endif
-
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
- &rk30_device_adc_battery,
-#endif
-#ifdef CONFIG_RFKILL_RK
- &device_rfkill_rk,
-#endif
-#ifdef CONFIG_GPS_RK
- &rk_device_gps,
-#endif
-#ifdef CONFIG_MT5931_MT6622
- &device_mt6622,
-#endif
-#if defined(CONFIG_MT6229)
- &rk29_device_mt6229,
-#endif
-#if defined(CONFIG_ARCH_RK3188)
- &device_mali,
-#endif
-
-#ifdef CONFIG_TCC_BT_DEV
- &device_tcc_bt,
-#endif
-#if defined(CONFIG_AC_USB_SWITCH)
- &device_ac_usb_switch,
-#endif
-#ifdef CONFIG_RK_REMOTECTL
- &rk30_device_remotectl,
-#endif
-
-};
-
-
-static int rk_platform_add_display_devices(void)
-{
- struct platform_device *fb = NULL; //fb
- struct platform_device *lcdc0 = NULL; //lcdc0
- struct platform_device *lcdc1 = NULL; //lcdc1
- struct platform_device *bl = NULL; //backlight
-#ifdef CONFIG_FB_ROCKCHIP
- fb = &device_fb;
-#endif
-
-#if defined(CONFIG_LCDC0_RK3188)
- lcdc0 = &device_lcdc0,
-#endif
-
-#if defined(CONFIG_LCDC1_RK3188)
- lcdc1 = &device_lcdc1,
-#endif
-
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- bl = &rk29_device_backlight,
-#endif
- __rk_platform_add_display_devices(fb,lcdc0,lcdc1,bl);
-
- return 0;
-
-}
-
-// i2c
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1d,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-
-#if defined (CONFIG_GS_LIS3DH)
- {
- .type = "gs_lis3dh",
- .addr = 0x19, //0x19(SA0-->VCC), 0x18(SA0-->GND)
- .flags = 0,
- .irq = LIS3DH_INT_PIN,
- .platform_data = &lis3dh_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8963)
- {
- .type = "ak8963",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8963_info,
- },
-#endif
-
-#if defined (CONFIG_LS_PHOTORESISTOR)
- {
- .type = "ls_photoresistor",
- .addr = 0x5e,
- .flags = 0,
- .irq = INVALID_GPIO,
- .platform_data = &light_photoresistor_info,
- },
-#endif
-
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8975_info,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8975_info,
- },
-#endif
-#if defined (CONFIG_GYRO_L3G4200D)
- {
- .type = "l3g4200d_gryo",
- .addr = 0x69,
- .flags = 0,
- .irq = L3G4200D_INT_PIN,
- .platform_data = &l3g4200d_info,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_CX2070X)
- {
- .type = "cx2070x",
- .addr = 0x14,
- .flags = 0,
- },
-#endif
-};
-#endif
-
-int __sramdata g_pmic_type = 0;
-#ifdef CONFIG_I2C1_RK30
-#ifdef CONFIG_REGULATOR_ACT8846
-#define PMU_POWER_SLEEP RK30_PIN0_PD1
-#define PMU_VSEL RK30_PIN3_PD3
-#define ACT8846_HOST_IRQ RK30_PIN0_PB3
-
-static struct pmu_info act8846_dcdc_info[] = {
- {
- .name = "act_dcdc1", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- .suspend_vol = 1200000,
- },
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 1200000,
- #else
- .suspend_vol = 900000,
- #endif
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 1200000,
- #else
- .suspend_vol = 900000,
- #endif
- },
- {
- .name = "act_dcdc4", //vccio
- .min_uv = 3000000,
- .max_uv = 3000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 3000000,
- #else
- .suspend_vol = 2800000,
- #endif
- },
-
-};
-static struct pmu_info act8846_ldo_info[] = {
- {
- .name = "act_ldo1", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "act_ldo2", //vdd12
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "act_ldo3", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo4", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo5", //vcctp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo6", //vcc_jetta
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo7", //vcc18
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo8", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- };
-
-#include "../mach-rk30/board-pmu-act8846.c"
-#endif
-
-#ifdef CONFIG_MFD_WM831X_I2C
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info wm8326_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "dcdc3", //ddr
- .min_uv = 1150000,
- .max_uv = 1150000,
- .suspend_vol = 1150000,
- },
- #ifdef CONFIG_MACH_RK3066_SDK
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3000000,
- },
- #else
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3000000,
- .max_uv = 3000000,
- .suspend_vol = 2800000,
- },
- #endif
-};
-
-static struct pmu_info wm8326_ldo_info[] = {
- {
- .name = "ldo1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo2", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo3", //
- .min_uv = 1100000,
- .max_uv = 1100000,
- .suspend_vol = 1100000,
- },
- {
- .name = "ldo4", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 1000000,
- },
- {
- .name = "ldo5", //vcc25
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo6", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo7", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- .suspend_vol = 2800000,
- },
- {
- .name = "ldo8", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo9", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo10", //flash_io
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
-};
-
-#include "../mach-rk30/board-pmu-wm8326.c"
-#endif
-
-#ifdef CONFIG_MFD_TPS65910
-#ifdef CONFIG_ARCH_RK3188
-#define TPS65910_HOST_IRQ RK30_PIN0_PB3
-#else
-#define TPS65910_HOST_IRQ RK30_PIN6_PA4
-#endif
-
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info tps65910_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1100000,
- .max_uv = 1100000,
- },
- {
- .name = "vdd2", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vio", //vcc_io
- .min_uv = 2500000,
- .max_uv = 2500000,
- },
-
-};
-static struct pmu_info tps65910_ldo_info[] = {
- {
- .name = "vpll", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "vdig2", //vdd_jetta
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vaux1", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "vaux2", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vaux33", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vmmc", //vcc30
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
- {
- .name = "vdac", //vcc18
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- };
-
-#include "../mach-rk30/board-pmu-tps65910.c"
-#endif
-
-#if defined(CONFIG_SCALER_TV5735)
-struct scaler_output_port tv_oports[] ={
- {
- .led_gpio = INVALID_GPIO,
- .type = SCALER_OUT_VGA,
- },
-};
-
-struct scaler_input_port tv_iports[] = {
- {//rk
- .led_gpio = RK30_PIN0_PD4,
- .type = SCALER_IN_RGB,
- },
- {//pc
- .led_gpio = RK30_PIN0_PD5,
- .type = SCALER_IN_VGA,
- }
-};
-
-struct scaler_platform_data tv5735_data = {
- .func_type = SCALER_FUNC_FULL,
-
- .iports = tv_iports,
- .iport_size = ARRAY_SIZE(tv_iports),
-
- .oports = tv_oports,
- .oport_size = ARRAY_SIZE(tv_oports),
-
- .power_gpio = RK30_PIN2_PD7,
- .power_level = GPIO_HIGH,
- .vga5v_gpio = RK30_PIN3_PD7,
- .vga5v_level = GPIO_HIGH,
- .ddc_sel_gpio = RK30_PIN0_PB4,
- .ddc_sel_level = GPIO_HIGH, //set default input port
- .vga_hsync_gpio= RK30_PIN0_PA1,
- .vga_vsync_gpio= RK30_PIN0_PA5,
-};
-#endif
-
-#if defined(CONFIG_SCALER_TEST)
-//the fisrt port is default
-struct scaler_output_port tst_oports[] ={
- {
- .led_gpio = INVALID_GPIO,
- .type = SCALER_OUT_VGA,
- },
-};
-
-//the fisrt port is default
-struct scaler_input_port tst_iports[] = {
- {
- //RK
- .led_gpio = RK30_PIN0_PD4,
- .type = SCALER_IN_VGA,
- },
- {
- //pc
- .led_gpio = RK30_PIN0_PD5,
- .type = SCALER_IN_VGA,
- },
-};
-
-static void test_init_hw(void)
-{
- //xn223
- if (!gpio_request(RK30_PIN1_PD6, NULL))
- gpio_direction_output(RK30_PIN1_PD6, GPIO_HIGH);
- else
- printk("%s: request XNN223_PWN gpio failed\n", __func__);
-}
-
-struct scaler_platform_data test_data = {
- .func_type = SCALER_FUNC_SWITCH,
-
- .iports = tst_iports,
- .iport_size = ARRAY_SIZE(tst_iports),
- .oports = tst_oports,
- .oport_size = ARRAY_SIZE(tst_oports),
-
- .power_gpio = RK30_PIN2_PD7,
- .power_level = GPIO_HIGH,
- .vga5v_gpio = RK30_PIN3_PD7,
- .vga5v_level = GPIO_HIGH,
- .ddc_sel_gpio = RK30_PIN0_PB4,
- .ddc_sel_level = GPIO_HIGH,
- //func
- .init_hw = test_init_hw,
-};
-#endif
-
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined(CONFIG_SCALER_TEST)
- {
- .type = "aswitch",
- .addr = 0x57,
- .flags = 0,
- .platform_data = &test_data,
- },
-#endif
-#if defined (CONFIG_REGULATOR_ACT8846)
- {
- .type = "act8846",
- .addr = 0x5a,
- .flags = 0,
- .irq = ACT8846_HOST_IRQ,
- .platform_data=&act8846_data,
- },
-#endif
-#if defined (CONFIG_RTC_HYM8563)
- {
- .type = "rtc_hym8563",
- .addr = 0x51,
- .flags = 0,
- .irq = RK30_PIN0_PB5,
- },
-#endif
-#if defined (CONFIG_MFD_WM831X_I2C)
- {
- .type = "wm8326",
- .addr = 0x34,
- .flags = 0,
- .irq = RK30_PIN0_PB3,
- .platform_data = &wm831x_platdata,
- },
-#endif
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-};
-#endif
-
-void __sramfunc board_pmu_suspend(void)
-{
- #if defined (CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- board_pmu_act8846_suspend();
- #endif
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_suspend();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_suspend();
- #endif
-}
-
-void __sramfunc board_pmu_resume(void)
-{
- #if defined (CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- board_pmu_act8846_resume();
- #endif
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_resume();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_resume();
- #endif
-}
-
- int __sramdata gpio3d6_iomux,gpio3d6_do,gpio3d6_dir,gpio3d6_en;
-
-#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
-
-void __sramfunc rk30_pwm_logic_suspend_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
-
-// int gpio0d7_iomux,gpio0d7_do,gpio0d7_dir,gpio0d7_en;
- sram_udelay(10000);
- gpio3d6_iomux = grf_readl(GRF_GPIO3D_IOMUX);
- gpio3d6_do = grf_readl(GRF_GPIO3H_DO);
- gpio3d6_dir = grf_readl(GRF_GPIO3H_DIR);
- gpio3d6_en = grf_readl(GRF_GPIO3H_EN);
-
- grf_writel((1<<28), GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DIR);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DO);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_EN);
-#endif
-}
-void __sramfunc rk30_pwm_logic_resume_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- grf_writel((1<<28)|gpio3d6_iomux, GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|gpio3d6_en, GRF_GPIO3H_EN);
- grf_writel((1<<30)|gpio3d6_dir, GRF_GPIO3H_DIR);
- grf_writel((1<<30)|gpio3d6_do, GRF_GPIO3H_DO);
- sram_udelay(10000);
-
-#endif
-
-}
-extern void pwm_suspend_voltage(void);
-extern void pwm_resume_voltage(void);
-void rk30_pwm_suspend_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_suspend_voltage();
-#endif
-}
-void rk30_pwm_resume_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_resume_voltage();
-#endif
-}
-
-
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-#if defined(CONFIG_SCALER_TV5735)
- {
- .type = "tv5735",
- .addr = 0x57,
- .flags = 0,
- .platform_data = &tv5735_data,
- },
-#endif
-#if defined(CONFIG_SCALER_DEVICE_DDC)
- {
- .type = "scaler_ddc",
- .addr = 0x50,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_CT36X_TS)
- {
- .type = CT36X_NAME,
- .addr = 0x01,
- .flags = 0,
- .platform_data = &ct36x_info,
- },
-#endif
-#if defined (CONFIG_LS_CM3217)
- {
- .type = "lightsensor",
- .addr = 0x10,
- .flags = 0,
- .platform_data = &cm3217_info,
- },
-#endif
-#if defined (CONFIG_LS_US5151)
- {
- .type = "us5151",
- .addr = 0x10,
- .flags = 0,
- },
-#endif
-
-#if defined(CONFIG_HDMI_CAT66121)
- {
- .type = "cat66121_hdmi",
- .addr = 0x4c,
- .flags = 0,
- .irq = RK30_PIN2_PD6,
- .platform_data = &rk_hdmi_pdata,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C4_RK30
-static struct i2c_board_info __initdata i2c4_info[] = {
-#ifdef CONFIG_MFD_RK610
- {
- .type = "rk610_ctl",
- .addr = 0x40,
- .flags = 0,
- .platform_data = &rk610_ctl_pdata,
- },
-#ifdef CONFIG_RK610_TVOUT
- {
- .type = "rk610_tvout",
- .addr = 0x42,
- .flags = 0,
- },
-#endif
-#ifdef CONFIG_HDMI_RK610
- {
- .type = "rk610_hdmi",
- .addr = 0x46,
- .flags = 0,
- .irq = INVALID_GPIO,
- },
-#endif
-#ifdef CONFIG_SND_SOC_RK610
- {//RK610_CODEC addr from 0x60 to 0x80 (0x60~0x80)
- .type = "rk610_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- .platform_data = &rk610_codec_pdata,
- },
-#endif
-#endif
-
-#if defined (CONFIG_SND_SOC_RT5631)
- {
- .type = "rt5631",
- .addr = 0x1a,
- .flags = 0,
- },
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO// RK30_PIN2_PD6 //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO//RK30_PIN2_PD7 //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- //set iomux (gpio) here
- //rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME, GPIO2D_GPIO2D7);
- //rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME, GPIO2D_GPIO2D6);
-
- return 0;
-}
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C4_RK30
- i2c_register_board_info(4, i2c4_info, ARRAY_SIZE(i2c4_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(5, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-
-#define POWER_ON_PIN RK30_PIN0_PA0 //power_hold
-static void rk30_pm_power_off(void)
-{
- printk(KERN_ERR "rk30_pm_power_off start...\n");
-#if defined(CONFIG_MFD_WM831X)
- wm831x_set_bits(Wm831x,WM831X_GPIO_LEVEL,0x0001,0x0000); //set sys_pwr 0
- wm831x_device_shutdown(Wm831x);//wm8326 shutdown
-#endif
-#if defined(CONFIG_REGULATOR_ACT8846)
- if (pmic_is_act8846()) {
- printk("enter dcdet===========\n");
- if(gpio_get_value (RK30_PIN0_PB2) == GPIO_LOW)
- {
- printk("enter restart===========\n");
- arm_pm_restart(0, "charge");
- }
- /** code here may cause tablet cannot boot when shutdown without charger pluged in
- * and then plug in charger. -- Cody Xie
- else
- {
- act8846_device_shutdown();
- }
- */
- }
-#endif
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
- while (1);
-}
-
-static void __init machine_rk30_board_init(void)
-{
- //avs_init();
- gpio_request(POWER_ON_PIN, "poweronpin");
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
- pm_power_off = rk30_pm_power_off;
-
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
-
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- rk_platform_add_display_devices();
- //board_usb_detect_init(RK30_PIN0_PA7);
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- rk29sdk_wifi_bt_gpio_control_init();
-#endif
-
-#if defined(CONFIG_MT6620)
- clk_set_rate(clk_get_sys("rk_serial.1", "uart"), 48*1000000);
-#endif
-
-#if defined(CONFIG_MT5931_MT6622)
- clk_set_rate(clk_get_sys("rk_serial.0", "uart"), 24*1000000);
-#endif
-}
-
-#define HD_SCREEN_SIZE 1920UL*1200UL*4*3
-static void __init rk30_reserve(void)
-{
-#if defined(CONFIG_ARCH_RK3188)
- /*if lcd resolution great than or equal to 1920*1200,reserve the ump memory */
- if(!(get_fb_size() < ALIGN(HD_SCREEN_SIZE,SZ_1M)))
- {
- int ump_mem_phy_size=512UL*1024UL*1024UL;
- resource_mali[0].start = board_mem_reserve_add("ump buf", ump_mem_phy_size);
- resource_mali[0].end = resource_mali[0].start + ump_mem_phy_size -1;
- }
-#endif
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0 buf", get_fb_size());
- resource_fb[0].end = resource_fb[0].start + get_fb_size()- 1;
-#if 0
- resource_fb[1].start = board_mem_reserve_add("ipp buf", RK30_FB0_MEM_SIZE);
- resource_fb[1].end = resource_fb[1].start + RK30_FB0_MEM_SIZE - 1;
-#endif
-
-#if defined(CONFIG_FB_ROTATE) || !defined(CONFIG_THREE_FB_BUFFER)
- resource_fb[2].start = board_mem_reserve_add("fb2 buf",get_fb_size());
- resource_fb[2].end = resource_fb[2].start + get_fb_size() - 1;
-#endif
-#endif
-
-
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
-
-#ifdef CONFIG_GPS_RK
- //it must be more than 8MB
- rk_gps_info.u32MemoryPhyAddr = board_mem_reserve_add("gps", SZ_8M);
-#endif
- board_mem_reserved();
-}
-/******************************** arm dvfs frequency volt table **********************************/
-/**
- * dvfs_cpu_logic_table: table for arm and logic dvfs
- * @frequency : arm frequency
- * @cpu_volt : arm voltage depend on frequency
- */
-
-//sdk
-static struct cpufreq_frequency_table dvfs_arm_table_volt_level0[] = {
- {.frequency = 312 * 1000, .index = 850 * 1000},
- {.frequency = 504 * 1000, .index = 900 * 1000},
- {.frequency = 816 * 1000, .index = 950 * 1000},
- {.frequency = 1008 * 1000, .index = 1025 * 1000},
- {.frequency = 1200 * 1000, .index = 1100 * 1000},
- {.frequency = 1416 * 1000, .index = 1200 * 1000},
- {.frequency = 1608 * 1000, .index = 1300 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-//default
-static struct cpufreq_frequency_table dvfs_arm_table_volt_level1[] = {
- {.frequency = 312 * 1000, .index = 875 * 1000},
- {.frequency = 504 * 1000, .index = 925 * 1000},
- {.frequency = 816 * 1000, .index = 975 * 1000},
- {.frequency = 1008 * 1000, .index = 1075 * 1000},
- {.frequency = 1200 * 1000, .index = 1150 * 1000},
- {.frequency = 1416 * 1000, .index = 1250 * 1000},
- {.frequency = 1608 * 1000, .index = 1350 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-// ds1006h 10'
-static struct cpufreq_frequency_table dvfs_arm_table_volt_level2[] = {
- {.frequency = 312 * 1000, .index = 900 * 1000},
- {.frequency = 504 * 1000, .index = 925 * 1000},
- {.frequency = 816 * 1000, .index = 1000 * 1000},
- {.frequency = 1008 * 1000, .index = 1075 * 1000},
- {.frequency = 1200 * 1000, .index = 1200 * 1000},
- {.frequency = 1416 * 1000, .index = 1250 * 1000},
- {.frequency = 1608 * 1000, .index = 1350 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-//if you board is good for volt quality,select dvfs_arm_table_volt_level0
-#define dvfs_arm_table dvfs_arm_table_volt_level2
-
-/******************************** gpu dvfs frequency volt table **********************************/
-//sdk
-static struct cpufreq_frequency_table dvfs_gpu_table_volt_level0[] = {
- {.frequency = 133 * 1000, .index = 975 * 1000},//the mininum rate is limited 133M for rk3188
- {.frequency = 200 * 1000, .index = 975 * 1000},
- {.frequency = 266 * 1000, .index = 1000 * 1000},
- {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1100 * 1000},
- {.frequency = 600 * 1000, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-//ds1006h 10'
-static struct cpufreq_frequency_table dvfs_gpu_table_volt_level1[] = {
- {.frequency = 133 * 1000, .index = 975 * 1000},
- {.frequency = 200 * 1000, .index = 1000 * 1000},
- {.frequency = 266 * 1000, .index = 1025 * 1000},
- {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1100 * 1000},
- {.frequency = 600 * 1000, .index = 1250 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-#define dvfs_gpu_table dvfs_gpu_table_volt_level1
-
-/******************************** ddr dvfs frequency volt table **********************************/
-static struct cpufreq_frequency_table dvfs_ddr_table_volt_level0[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 950 * 1000},
- {.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = 1000 * 1000},
- //{.frequency = 396 * 1000 + DDR_FREQ_NORMAL, .index = 1100 * 1000},
- {.frequency = 666 * 1000 + DDR_FREQ_NORMAL, .index = 1250 * 1000},
- {.frequency = 666 * 1000 + DDR_FREQ_DUALVIEW, .index = 1250 * 1000},
- //{.frequency = 528 * 1000 + DDR_FREQ_NORMAL, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table_t[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 950 * 1000},
- //{.frequency = 460 * 1000 + DDR_FREQ_NORMAL, .index = 1150 * 1000},
- {.frequency = 666 * 1000 + DDR_FREQ_NORMAL, .index = 1250 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-#define dvfs_ddr_table dvfs_ddr_table_volt_level0
-
-/******************************** arm dvfs frequency volt table end **********************************/
-
-
-
-//#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
-//static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
-//static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
-int get_max_freq(struct cpufreq_frequency_table *table)
-{
- int i,temp=0;
-
- for(i=0;table[i].frequency!= CPUFREQ_TABLE_END;i++)
- {
- if(temp<table[i].frequency)
- temp=table[i].frequency;
- }
- printk("get_max_freq=%d\n",temp);
- return temp;
-}
-
-void __init board_clock_init(void)
-{
- u32 flags=RK30_CLOCKS_DEFAULT_FLAGS;
-#if !defined(CONFIG_ARCH_RK3188)
- if(get_max_freq(dvfs_gpu_table)<=(400*1000))
- {
- flags=RK30_CLOCKS_DEFAULT_FLAGS|CLK_GPU_GPLL;
- }
- else
- flags=RK30_CLOCKS_DEFAULT_FLAGS|CLK_GPU_CPLL;
-#endif
- rk30_clock_data_init(periph_pll_default, codec_pll_default, flags);
- //dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "cpu"), dvfs_arm_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
-#if defined(CONFIG_ARCH_RK3188)
- if (rk_pll_flag() == 0)
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
- else
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table_t);
-#else
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
-#endif
-}
-
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk30_fixup,
- .reserve = &rk30_reserve,
- .map_io = rk30_map_io,
- .init_irq = rk30_init_irq,
- .timer = &rk30_timer,
- .init_machine = machine_rk30_board_init,
-MACHINE_END
+++ /dev/null
-/*****************************************************************************************
- * arch/arm/mach-rkxx/baord-xxx-sdmmc-config.c
- *
- * Copyright (C) 2013 ROCKCHIP, Inc.
- *
- * Description:
- * define the gpio for SD-MMC-SDIO-Wifi functions according to your own projects.
- *
- * Author: Michael Xie
- * 15 Jan,2013
- * E-mail: xbw@rock-chips.com
- *
- ******************************************************************************************/
-
-#define DS1006H_V1_2_SUPPORT 1
-
-/*
-** If you select the macro of CONFIG_SDMMC0_RK29_WRITE_PROTECT, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define SDMMC0_WRITE_PROTECT_PIN RK30_PIN3_PB2 //According to your own project to set the value of write-protect-pin.
-//#define SDMMC0_WRITE_PROTECT_ENABLE_VALUE GPIO_HIGH
-
-/*
-** If you select the macro of CONFIG_SDMMC1_RK29_WRITE_PROTECT, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define SDMMC1_WRITE_PROTECT_PIN RK30_PIN3_PB3 //According to your own project to set the value of write-protect-pin.
-//#define SDMMC1_WRITE_PROTECT_ENABLE_VALUE GPIO_HIGH
-
-/*
-** If you select the macro of CONFIG_RK29_SDIO_IRQ_FROM_GPIO, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define RK29SDK_WIFI_SDIO_CARD_INT RK30_PIN3_PD2
-
-
-/*
-* define sdcard PowerEn-pin
-*/
-#define RK29SDK_SD_CARD_PWR_EN RK30_PIN3_PA1
-#define RK29SDK_SD_CARD_PWR_EN_LEVEL GPIO_LOW
-int rk31sdk_get_sdmmc0_pin_io_voltage(void)
-{
- int voltage;
-#define RK31SDK_SET_SDMMC0_PIN_VOLTAGE
-
- /**************************************************************************************
- ** Please tell me how much voltage of your SDMMC0-pin in your project.
- **
- ** ÀýÈç: ÓеÄÏîÄ¿£¬ËüµÄSDMMC0ËùÔÚµÄRKÖ÷¿ØµÄIO×飬ÏëÓÃ1.8V, ¶ø¿¨±¾ÉíÓÃ3.3V,
- ** ¶øÖмäͨ¹ý¸öµçƽת»».ÄÇô£¬Äú´Ëʱ£¬Ó¦¸ÃÉèÖÃÏÂÃæµÄvoltageֵΪ 1.8V(¼´1800mv)
- ***************************************************************************************/
- voltage = 3300; //default the voltage 3300mv.
-
- return voltage;
-}
-
-/*
-* define the card-detect-pin.
-*/
-#define RK29SDK_SD_CARD_DETECT_N RK30_PIN3_PB0 //According to your own project to set the value of card-detect-pin.
-#define RK29SDK_SD_CARD_INSERT_LEVEL GPIO_LOW // set the voltage of insert-card. Please pay attention to the default setting.
-
-#define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
-#define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
-
-/*
-* Define wifi module's power and reset gpio, and gpio sensitive level.
-* Please set the value according to your own project.
-*
-* Well, you just own engineering module to set the value in the corresponding module branch.
-* Otherwise, you do not define this macro, eliminate it.
-*
-*/
-#if defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU) || defined(CONFIG_RTL8723AU)
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_LOW//GPIO_HIGH
-
-#elif defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319) || defined(CONFIG_RKWIFI) \
- || defined(CONFIG_RTL8189ES)
-
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN2_PA7
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
-
-#elif defined(CONFIG_MT5931_MT6622) || defined(CONFIG_MT5931)
-
- #ifdef CONFIG_MACH_RK3168_LR097
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- //#define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- //#define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
-
- #else
- #if DS1006H_V1_2_SUPPORT
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- #else
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN0_PA5
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #endif
- #endif
-
-#elif defined(CONFIG_MT6620)
- #define COMBO_MODULE_MT6620_CDT 1 // to control antsel2,antsel3 and gps_lan foot when using AcSip or Cdtech chip.
- //- 1--use Cdtech chip; 0--unuse CDT chip
-
- //power, PMU_EN
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PC7
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- //reset, DAIRST,SYSRST_B
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- //VDDIO
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL RK30_PIN0_PD2 //You do not get control of the foot, and you do not need to define the macro
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_ENABLE_VALUE GPIO_HIGH
- //WIFI_INT_B
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
- //BGF_INT_B
- #define RK30SDK_WIFI_GPIO_BGF_INT_B RK30_PIN6_PA7
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_ENABLE_VALUE GPIO_HIGH
- //GPS_SYNC
- #define RK30SDK_WIFI_GPIO_GPS_SYNC RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_ENABLE_VALUE GPIO_HIGH
-
- #if COMBO_MODULE_MT6620_CDT
- //ANTSEL2
- #define RK30SDK_WIFI_GPIO_ANTSEL2 RK30_PIN4_PD4
- #define RK30SDK_WIFI_GPIO_ANTSEL2_ENABLE_VALUE GPIO_LOW //use 6620 in CDT chip, LOW--work; High--no work.
- //ANTSEL3
- #define RK30SDK_WIFI_GPIO_ANTSEL3 RK30_PIN4_PD3
- #define RK30SDK_WIFI_GPIO_ANTSEL3_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- //GPS_LAN
- #define RK30SDK_WIFI_GPIO_GPS_LAN RK30_PIN4_PD6
- #define RK30SDK_WIFI_GPIO_GPS_LAN_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- #endif // #if COMBO_MODULE_MT6620_CDT--#endif
-#endif
-
-int rk31sdk_get_sdio_wifi_voltage(void)
-{
- int voltage;
-
- /******************************************************************************
- ** Please tell me how much wifi-module uses voltage in your project.
- ******************************************************************************/
-#if defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319) || defined(CONFIG_RKWIFI)
- voltage = 1800 ; //power 1800mV
-
-#elif defined(CONFIG_MT5931_MT6622)||defined(CONFIG_MT5931)
- voltage = 2800 ; //power 1800V
-#elif defined(CONFIG_MT6620)
- voltage = 2800 ; //power 2800V
-#elif defined(CONFIG_RDA5990)||defined(CONFIG_RTL8723AS) || defined(CONFIG_RTL8189ES)
- voltage = 3300 ; //power 3300V
-#else
- //default, sdio use 3.0V
- voltage = 3000 ; //power 3000V
-#endif
-
- return voltage;
-}
-
-
-
+++ /dev/null
-/*
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <mach/dvfs.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <linux/rk_fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/mfd/tps65910.h>
-#include <linux/regulator/act8846.h>
-#include <plat/efuse.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-#if defined(CONFIG_CT36X_TS)
-#include <linux/ct36x.h>
-#endif
-#if defined(CONFIG_MFD_RK610)
-#include <linux/mfd/rk610_core.h>
-#endif
-
-#if defined(CONFIG_RK_HDMI)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-#if defined(CONFIG_MT6229)
-#include <linux/mt6229.h>
-#endif
-#if defined(CONFIG_GPS_RK)
-#include "../../../drivers/misc/gps/rk_gps/rk_gps.h"
-#endif
-
-#if defined(CONFIG_MT6620)
-#include <linux/gps.h>
-#endif
-
-#ifdef CONFIG_CW2015_BATTERY
-#include <linux/power/cw2015_battery.h>
-#endif
-
-#include "../mach-rk30/board-rk3168-ds1006h-camera.c"
-#include <plat/key.h>
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK30_PIN0_PA4,
- .active_low = PRESS_LEV_LOW,
- .wakeup = 1,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .adc_value = 1,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = 1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
-/*
- v1.0 : ignore
- v1.1 : rk610 lvds + rk610 codec + MT5931_MT6622 + light photoresistor + adc/cw2015
- v1.2 : lvds + rt5631 + M500 + us5151 + adc
-*/
-#define DS1006H_V1_2_SUPPORT 1
-int get_harware_version()
-{
- #if DS1006H_V1_2_SUPPORT
- return 2;
- #else
- return 1;
- #endif
-}
-EXPORT_SYMBOL_GPL(get_harware_version);
-
-#if defined(CONFIG_CT36X_TS)
-
-#define TOUCH_MODEL 363
-#define TOUCH_MAX_X 1280
-#define TOUCH_MAX_y 800
-#define TOUCH_RESET_PIN RK30_PIN0_PB6
-#define TOUCH_INT_PIN RK30_PIN1_PB7
-
-static struct ct36x_platform_data ct36x_info = {
- .model = TOUCH_MODEL,
- .x_max = TOUCH_MAX_X,
- .y_max = TOUCH_MAX_y,
-
- .rst_io = {
- .gpio = TOUCH_RESET_PIN,
- .active_low = 1,
- },
- .irq_io = {
- .gpio = TOUCH_INT_PIN,
- .active_low = 1,
- },
- .orientation = {1, 0, 0, 1},
-};
-#endif
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-#define PWM_ID 3
-#define PWM_MODE PWM3
-#define PWM_EFFECT_VALUE 1
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-#define BL_EN_PIN RK30_PIN0_PA2
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
-
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
- ret = gpio_request(BL_EN_PIN, NULL);
- if (ret != 0) {
- gpio_free(BL_EN_PIN);
- }
-
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
-
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0, pwm_gpio;
-
-#ifdef LCD_DISP_ON_PIN
- gpio_free(BL_EN_PIN);
-#endif
-
- pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
- gpio_request(pwm_gpio, NULL);
- gpio_direction_output(pwm_gpio, GPIO_LOW);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret = 0, pwm_gpio;
-
- pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
- if (gpio_request(pwm_gpio, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- gpio_direction_output(pwm_gpio, GPIO_LOW);
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, 0);
- gpio_set_value(BL_EN_PIN, !BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- int pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
-
- gpio_free(pwm_gpio);
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, 1);
- gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .min_brightness = 65,
- .max_brightness = 150,
- .brightness_mode =BRIGHTNESS_MODE_CONIC,
- .pre_div = 30 * 1000, // pwm output clk: 30k;
- .pwm_id = PWM_ID,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-#endif
-
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN RK30_PIN0_PB7
-
-static int mma8452_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data mma8452_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma8452_init_platform_hw,
- .orientation = {-1, 0, 0, 0, 0, -1, 0, 1, 0},
-};
-#endif
-#if defined (CONFIG_GS_LIS3DH)
-#define LIS3DH_INT_PIN RK30_PIN0_PB7
-
-static int lis3dh_init_platform_hw(void)
-{
-
- return 0;
-}
-
-static struct sensor_platform_data lis3dh_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lis3dh_init_platform_hw,
- .orientation = {-1, 0, 0, 0, 1, 0, 0, 0, -1},
-};
-#endif
-
-#if defined (CONFIG_COMPASS_AK8963)
-static struct sensor_platform_data akm8963_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {0, 1, 0},
- {1, 0, 0},
- {0, 0, -1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {0, -1, 0},
- {-1, 0, 0},
- {0, 0, -1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-#if defined(CONFIG_LS_PHOTORESISTOR)
-static struct sensor_platform_data light_photoresistor_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 0,
- .address = 2 ,
- .poll_delay_ms = 200,
-};
-#endif
-
-#if defined (CONFIG_COMPASS_AK8975)
-static struct sensor_platform_data akm8975_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-#if defined(CONFIG_MT6229)
-static int mt6229_io_init(void)
-{
- #if 0
- rk30_mux_api_set(GPIO2B6_LCDC1DATA14_SMCADDR18_TSSYNC_NAME, GPIO2B_GPIO2B6);
- k30_mux_api_set(GPIO4D2_SMCDATA10_TRACEDATA10_NAME, GPIO4D_GPIO4D2);
- rk30_mux_api_set(GPIO2B7_LCDC1DATA15_SMCADDR19_HSADCDATA7_NAME, GPIO2B_GPIO2B7);
- rk30_mux_api_set(GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME, GPIO2C_GPIO2C0);
- rk30_mux_api_set(GPIO2C1_LCDC1DATA17_SMCBLSN0_HSADCDATA6_NAME, GPIO2C_GPIO2C1);
- rk30_mux_api_set(GPIO2C1_LCDC1DATA17_SMCBLSN0_HSADCDATA6_NAME, GPIO2C_GPIO2C1);
- #endif
- return 0;
-}
-
-static int mt6229_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mt6229_data rk29_mt6229_info = {
- .io_init = mt6229_io_init,
- .io_deinit = mt6229_io_deinit,
- .modem_power_en = RK30_PIN0_PC6,
- .bp_power = RK30_PIN2_PD5,
- .modem_usb_en = RK30_PIN0_PC7,
- .modem_uart_en = RK30_PIN2_PD4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
- .ap_ready = RK30_PIN0_PC4,
-
-};
-struct platform_device rk29_device_mt6229 = {
- .name = "mt6229",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mt6229_info,
- }
- };
-#endif
-
-#if defined(CONFIG_GYRO_L3G4200D)
-
-#include <linux/l3g4200d.h>
-#define L3G4200D_INT_PIN RK30_PIN0_PB4
-
-static int l3g4200d_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data l3g4200d_info = {
- .type = SENSOR_TYPE_GYROSCOPE,
- .irq_enable = 1,
- .poll_delay_ms = 0,
- .orientation = {1, 0, 0 , 0 , -1, 0, 0, 0, -1},
- .init_platform_hw = l3g4200d_init_platform_hw,
- .x_min = 40,//x_min,y_min,z_min = (0-100) according to hardware
- .y_min = 40,
- .z_min = 20,
-};
-
-#endif
-
-#ifdef CONFIG_LS_CM3217
-static struct sensor_platform_data cm3217_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 0,
- .poll_delay_ms = 500,
-};
-
-#endif
-
-#ifdef CONFIG_FB_ROCKCHIP
-
-#if DS1006H_V1_2_SUPPORT
-#define LCD_CS_PIN RK30_PIN0_PB0
-#else
-#define LCD_CS_PIN INVALID_GPIO
-#endif
-#define LCD_CS_VALUE GPIO_HIGH
-
-#if DS1006H_V1_2_SUPPORT
-#define LCD_EN_PIN RK30_PIN0_PB1
-#else
-#define LCD_EN_PIN RK30_PIN0_PB0
-#endif
-#define LCD_EN_VALUE GPIO_LOW
-
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
-
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_CS_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_CS_PIN);
- printk(KERN_ERR "request lcd cs pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_CS_PIN, LCD_CS_VALUE);
- }
- }
-
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_EN_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_EN_PIN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_EN_PIN, LCD_EN_VALUE);
- }
- }
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, !LCD_CS_VALUE);
- }
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, !LCD_EN_VALUE);
- }
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE);
- }
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
- }
- return 0;
-}
-
-#if defined(CONFIG_LCDC0_RK3188)
-struct rk29fb_info lcdc0_screen_info = {
- .prop = EXTEND, //extend display device
- .lcd_info = NULL,
- .set_screen_info = hdmi_init_lcdc,
-
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK3188)
-struct rk29fb_info lcdc1_screen_info = {
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-
-#if defined(CONFIG_ARCH_RK3188)
-static struct resource resource_mali[] = {
- [0] = {
- .name = "ump buf",
- .start = 0,
- .end = 0,
- .flags = IORESOURCE_MEM,
- },
-
-};
-
-static struct platform_device device_mali= {
- .name = "mali400_ump",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_mali),
- .resource = resource_mali,
-};
-#endif
-
-#if defined(CONFIG_LCDC0_RK3188)
-static struct resource resource_lcdc0[] = {
- [0] = {
- .name = "lcdc0 reg",
- .start = RK30_LCDC0_PHYS,
- .end = RK30_LCDC0_PHYS + RK30_LCDC0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc0 irq",
- .start = IRQ_LCDC0,
- .end = IRQ_LCDC0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc0 = {
- .name = "rk30-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc0),
- .resource = resource_lcdc0,
- .dev = {
- .platform_data = &lcdc0_screen_info,
- },
-};
-#endif
-#if defined(CONFIG_LCDC1_RK3188)
-static struct resource resource_lcdc1[] = {
- [0] = {
- .name = "lcdc1 reg",
- .start = RK30_LCDC1_PHYS,
- .end = RK30_LCDC1_PHYS + RK30_LCDC1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc1 irq",
- .start = IRQ_LCDC1,
- .end = IRQ_LCDC1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc1 = {
- .name = "rk30-lcdc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resource_lcdc1),
- .resource = resource_lcdc1,
- .dev = {
- .platform_data = &lcdc1_screen_info,
- },
-};
-#endif
-
-#if defined(CONFIG_MFD_RK610)
-#define RK610_RST_PIN RK30_PIN3_PB2
-static int rk610_power_on_init(void)
-{
- int ret;
- if(RK610_RST_PIN != INVALID_GPIO)
- {
- ret = gpio_request(RK610_RST_PIN, "rk610 reset");
- if (ret)
- {
- printk(KERN_ERR "rk610_control_probe request gpio fail\n");
- }
- else
- {
- gpio_direction_output(RK610_RST_PIN, GPIO_HIGH);
- msleep(100);
- gpio_direction_output(RK610_RST_PIN, GPIO_LOW);
- msleep(100);
- gpio_set_value(RK610_RST_PIN, GPIO_HIGH);
- }
- }
-
- return 0;
-
-}
-
-
-static struct rk610_ctl_platform_data rk610_ctl_pdata = {
- .rk610_power_on_init = rk610_power_on_init,
-};
-#endif
-
-#ifdef CONFIG_SND_SOC_RK610
-static int rk610_codec_io_init(void)
-{
-//if need iomux.
-//Must not gpio_request
- return 0;
-}
-
-static struct rk610_codec_platform_data rk610_codec_pdata = {
- .spk_ctl_io = RK30_PIN2_PD7,
- .io_init = rk610_codec_io_init,
- .boot_depop = 1,
-};
-#endif
-
-#ifdef CONFIG_RK_HDMI
-#define RK_HDMI_RST_PIN RK30_PIN3_PB2
-static int rk_hdmi_power_init(void)
-{
- int ret;
-
- if(RK_HDMI_RST_PIN != INVALID_GPIO)
- {
- if (gpio_request(RK_HDMI_RST_PIN, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- gpio_direction_output(RK_HDMI_RST_PIN, GPIO_LOW);
- gpio_set_value(RK_HDMI_RST_PIN, GPIO_LOW);
- msleep(100);
- gpio_set_value(RK_HDMI_RST_PIN, GPIO_HIGH);
- msleep(50);
- }
- return 0;
-}
-static struct rk_hdmi_platform_data rk_hdmi_pdata = {
- //.io_init = rk_hdmi_power_init,
-};
-#endif
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and sdio.noted by xbw at 2012-03-05
-**************************************************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "board-rk3188-ds1006h-sdmmc-config.c"
-#include "../plat-rk/rk-sdmmc-ops.c"
-#include "../plat-rk/rk-sdmmc-wifi.c"
-#endif //endif ---#ifdef CONFIG_SDMMC_RK29
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- iomux_set(MMC0_CMD);
- iomux_set(MMC0_CLKOUT);
- iomux_set(MMC0_D0);
- iomux_set(MMC0_D1);
- iomux_set(MMC0_D2);
- iomux_set(MMC0_D3);
-
- iomux_set_gpio_mode(iomux_mode_to_gpio(MMC0_DETN));
-
- gpio_request(RK30_PIN3_PA7, "sdmmc-power");
- gpio_direction_output(RK30_PIN3_PA7, GPIO_LOW);
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- #if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set_gpio_mode(iomux_gpio_to_mode(RK29SDK_SD_CARD_DETECT_N));
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO);
- #endif
- #else
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(MMC0_DETN);
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FMUX);
- #endif
- #endif
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) && defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- .status = rk29sdk_wifi_mmc0_status,
- .register_status_notify = rk29sdk_wifi_mmc0_status_register,
-#endif
-
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .power_en = RK29SDK_SD_CARD_PWR_EN,
- .power_en_level = RK29SDK_SD_CARD_PWR_EN_LEVEL,
-#else
- .power_en = INVALID_GPIO,
- .power_en_level = GPIO_LOW,
-#endif
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC0_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- .det_pin_info = {
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N, //INVALID_GPIO,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
- #endif
- },
-
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- iomux_set(MMC1_CMD);
- iomux_set(MMC1_CLKOUT);
- iomux_set(MMC1_D0);
- iomux_set(MMC1_D1);
- iomux_set(MMC1_D2);
- iomux_set(MMC1_D3);
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC) || defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC1_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- #if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
- .sdio_INT_gpio = RK29SDK_WIFI_SDIO_CARD_INT,
- #endif
-
- .det_pin_info = {
-#if defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- #else
- .io = INVALID_GPIO,
- #endif
-
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-
- .enable_sd_wakeup = 0,
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-/**************************************************************************************************
- * the end of setting for SDMMC devices
-**************************************************************************************************/
-
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = RK30_PIN0_PB2,
- .batt_low_pin = INVALID_GPIO,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = RK30_PIN0_PA6,
- .usb_det_pin = INVALID_GPIO,
- .dc_det_level = GPIO_LOW,
- .charge_ok_level = GPIO_HIGH,
-
- .reference_voltage = 1800, // the rK2928 is 3300;RK3066 and rk29 are 2500;rk3066B is 1800;
- .pull_up_res = 200, //divider resistance , pull-up resistor
- .pull_down_res = 120, //divider resistance , pull-down resistor
-
- .is_reboot_charging = 1,
- .save_capacity = 1 ,
- .low_voltage_protection = 3600,
-};
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-
-#ifdef CONFIG_CW2015_BATTERY
-static u8 config_info[SIZE_BATINFO] = {
-#if 0
- 0x14, 0xB0, 0x58, 0x57, 0x53,
- 0x4F, 0x4C, 0x49, 0x47, 0x45,
- 0x42, 0x3F, 0x3B, 0x33, 0x2C,
- 0x24, 0x20, 0x1B, 0x18, 0x13,
- 0x1E, 0x47, 0x4D, 0x4A, 0x30,
- 0x63, 0x0B, 0x85, 0x11, 0x22,
- 0x3B, 0x58, 0x6E, 0x67, 0x6C,
- 0x70, 0x42, 0x1C, 0x5A, 0x2A,
- 0x17, 0x4F, 0x52, 0x87, 0x8F,
- 0x91, 0x94, 0x52, 0x82, 0x8C,
- 0x92, 0x96, 0xB6, 0x84, 0xA4,
- 0xCB, 0x2F, 0x7D, 0x72, 0xA5,
- 0xB5, 0xC1, 0x46, 0xAE
-#else
- 0x15,0x20,0x5C,0x5A,0x58,
- 0x54,0x50,0x4C,0x49,0x49,
- 0x47,0x45,0x41,0x38,0x2E,
- 0x26,0x1D,0x1A,0x13,0x11,
- 0x1D,0x3E,0x4E,0x4C,0x36,
- 0x41,0x0B,0x85,0x1E,0x3C,
- 0x43,0x8B,0x95,0x70,0x61,
- 0x69,0x42,0x1B,0x52,0x41,
- 0x08,0x22,0x5F,0x86,0x8F,
- 0x91,0x91,0x18,0x58,0x82,
- 0x94,0xA5,0x42,0xB2,0xDE,
- 0xCB,0x2F,0x7D,0x72,0xA5,
- 0xB5,0xC1,0x46,0xAE
-#endif
-};
-
-static struct cw_bat_platform_data cw_bat_platdata = {
- .dc_det_pin = RK30_PIN0_PB2,
- .bat_low_pin = RK30_PIN0_PB1,
- .chg_ok_pin = RK30_PIN0_PA6,
- .dc_det_level = GPIO_LOW,
- .bat_low_level = GPIO_LOW,
- .chg_ok_level = GPIO_HIGH,
-
- .cw_bat_config_info = config_info,
-
-};
-
-#endif
-
-#ifdef CONFIG_RK30_PWM_REGULATOR
-static int pwm_voltage_map[] = {
- 800000,825000,850000, 875000,900000, 925000 ,950000, 975000,1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000,1375000
-};
-
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_cpu",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] =
-{
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
- .pwm_id = 1,
- .pwm_gpio = RK30_PIN3_PD4,
- .pwm_iomux_pwm = PWM1,
- .pwm_iomux_gpio = GPIO3_D4,
- .pwm_voltage = 1100000,
- .suspend_voltage = 1000000,
- .min_uV = 800000,
- .max_uV = 1375000,
- .coefficient = 575, //57.5%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-#endif
-
-#ifdef CONFIG_RFKILL_RK
-// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
-static struct rfkill_rk_platform_data rfkill_rk_platdata = {
- .type = RFKILL_TYPE_BLUETOOTH,
-
- .poweron_gpio = { // BT_REG_ON
- .io = INVALID_GPIO, //RK30_PIN3_PC7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_poweron",
- .fgpio = GPIO3_C7,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN3_PD1, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_reset",
- .fgpio = GPIO3_D1,
- },
- },
-
- .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
- .io = RK30_PIN3_PC6, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_wake",
- .fgpio = GPIO3_C6,
- },
- },
-
- .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .gpio = {
- .io = RK30_PIN0_PA5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
- .iomux = {
- .name = NULL,
- },
- },
- },
-
- .rts_gpio = { // UART_RTS, enable or disable BT's data coming
- .io = RK30_PIN1_PA3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_rts",
- .fgpio = GPIO1_A3,
- .fmux = UART0_RTSN,
- },
- },
-};
-
-static struct platform_device device_rfkill_rk = {
- .name = "rfkill_rk",
- .id = -1,
- .dev = {
- .platform_data = &rfkill_rk_platdata,
- },
-};
-#endif
-
-#if defined(CONFIG_GPS_RK)
-int rk_gps_io_init(void)
-{
- printk("%s \n", __FUNCTION__);
-
- rk30_mux_api_set(GPIO1B5_UART3RTSN_NAME, GPIO1B_GPIO1B5);//VCC_EN
- gpio_request(RK30_PIN1_PB5, NULL);
- gpio_direction_output(RK30_PIN1_PB5, GPIO_LOW);
-
- rk30_mux_api_set(GPIO1B4_UART3CTSN_GPSRFCLK_NAME, GPIO1B_GPSRFCLK);//GPS_CLK
- rk30_mux_api_set(GPIO1B2_UART3SIN_GPSMAG_NAME, GPIO1B_GPSMAG);//GPS_MAG
- rk30_mux_api_set(GPIO1B3_UART3SOUT_GPSSIG_NAME, GPIO1B_GPSSIG);//GPS_SIGN
-
- rk30_mux_api_set(GPIO1A6_UART1CTSN_SPI0CLK_NAME, GPIO1A_GPIO1A6);//SPI_CLK
- gpio_request(RK30_PIN1_PA6, NULL);
- gpio_direction_output(RK30_PIN1_PA6, GPIO_LOW);
-
- rk30_mux_api_set(GPIO1A5_UART1SOUT_SPI0TXD_NAME, GPIO1A_GPIO1A5);//SPI_MOSI
- gpio_request(RK30_PIN1_PA5, NULL);
- gpio_direction_output(RK30_PIN1_PA5, GPIO_LOW);
-
- rk30_mux_api_set(GPIO1A7_UART1RTSN_SPI0CSN0_NAME, GPIO1A_GPIO1A7);//SPI_CS
- gpio_request(RK30_PIN1_PA7, NULL);
- gpio_direction_output(RK30_PIN1_PA7, GPIO_LOW);
- return 0;
-}
-int rk_gps_power_up(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_power_down(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_reset_set(int level)
-{
- return 0;
-}
-int rk_enable_hclk_gps(void)
-{
- printk("%s \n", __FUNCTION__);
- clk_enable(clk_get(NULL, "hclk_gps"));
- return 0;
-}
-int rk_disable_hclk_gps(void)
-{
- printk("%s \n", __FUNCTION__);
- clk_disable(clk_get(NULL, "hclk_gps"));
- return 0;
-}
-struct rk_gps_data rk_gps_info = {
- .io_init = rk_gps_io_init,
- .power_up = rk_gps_power_up,
- .power_down = rk_gps_power_down,
- .reset = rk_gps_reset_set,
- .enable_hclk_gps = rk_enable_hclk_gps,
- .disable_hclk_gps = rk_disable_hclk_gps,
- .GpsSign = RK30_PIN1_PB3,
- .GpsMag = RK30_PIN1_PB2, //GPIO index
- .GpsClk = RK30_PIN1_PB4, //GPIO index
- .GpsVCCEn = RK30_PIN1_PB5, //GPIO index
- .GpsSpi_CSO = RK30_PIN1_PA4, //GPIO index
- .GpsSpiClk = RK30_PIN1_PA5, //GPIO index
- .GpsSpiMOSI = RK30_PIN1_PA7, //GPIO index
- .GpsIrq = IRQ_GPS,
- .GpsSpiEn = 0,
- .GpsAdcCh = 2,
- .u32GpsPhyAddr = RK30_GPS_PHYS,
- .u32GpsPhySize = RK30_GPS_SIZE,
-};
-
-struct platform_device rk_device_gps = {
- .name = "gps_hv5820b",
- .id = -1,
- .dev = {
- .platform_data = &rk_gps_info,
- }
- };
-#endif
-
-#if defined(CONFIG_MT5931_MT6622)
-static struct mt6622_platform_data mt6622_platdata = {
- .power_gpio = { // BT_REG_ON
- #if DS1006H_V1_2_SUPPORT
- .io = RK30_PIN3_PC7, // set io to INVALID_GPIO for disable it
- #else
- .io = RK30_PIN3_PD5, // set io to INVALID_GPIO for disable it
- #endif
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .reset_gpio = { // BT_RST
- #if DS1006H_V1_2_SUPPORT
- .io = RK30_PIN3_PD1,
- #else
- .io = RK30_PIN0_PD7,
- #endif
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .irq_gpio = {
- #if DS1006H_V1_2_SUPPORT
- .io = RK30_PIN0_PA5,
- #else
- .io = RK30_PIN3_PD2,
- #endif
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- }
-};
-
-static struct platform_device device_mt6622 = {
- .name = "mt6622",
- .id = -1,
- .dev = {
- .platform_data = &mt6622_platdata,
- },
-};
-#endif
-
-#if defined CONFIG_TCC_BT_DEV
-static struct tcc_bt_platform_data tcc_bt_platdata = {
-
- .power_gpio = { // ldoon
- .io = RK2928_PIN3_PC0,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .wake_host_gpio = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .io = RK2928_PIN0_PC5, // set io to INVALID_GPIO for disable it
- .enable = IRQF_TRIGGER_RISING,// set IRQF_TRIGGER_FALLING for falling, set IRQF_TRIGGER_RISING for rising
- .iomux = {
- .name = NULL,
- },
- },
-};
-
-static struct platform_device device_tcc_bt = {
- .name = "tcc_bt_dev",
- .id = -1,
- .dev = {
- .platform_data = &tcc_bt_platdata,
- },
-};
-#endif
-
-
-static struct platform_device *devices[] __initdata = {
-
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- &rk29sdk_wifi_device,
-#endif
-
-#if defined(CONFIG_MT6620)
- &mt3326_device_gps,
-#endif
-
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
- &rk30_device_adc_battery,
-#endif
-#ifdef CONFIG_RFKILL_RK
- &device_rfkill_rk,
-#endif
-#ifdef CONFIG_GPS_RK
- &rk_device_gps,
-#endif
-#ifdef CONFIG_MT5931_MT6622
- &device_mt6622,
-#endif
-#if defined(CONFIG_MT6229)
- &rk29_device_mt6229,
-#endif
-#if defined(CONFIG_ARCH_RK3188)
- &device_mali,
-#endif
-
-#ifdef CONFIG_TCC_BT_DEV
- &device_tcc_bt,
-#endif
-};
-
-
-static int rk_platform_add_display_devices(void)
-{
- struct platform_device *fb = NULL; //fb
- struct platform_device *lcdc0 = NULL; //lcdc0
- struct platform_device *lcdc1 = NULL; //lcdc1
- struct platform_device *bl = NULL; //backlight
-#ifdef CONFIG_FB_ROCKCHIP
- fb = &device_fb;
-#endif
-
-#if defined(CONFIG_LCDC0_RK3188)
- lcdc0 = &device_lcdc0,
-#endif
-
-#if defined(CONFIG_LCDC1_RK3188)
- lcdc1 = &device_lcdc1,
-#endif
-
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- bl = &rk29_device_backlight,
-#endif
- __rk_platform_add_display_devices(fb,lcdc0,lcdc1,bl);
-
- return 0;
-
-}
-
-// i2c
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1d,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-
-#if defined (CONFIG_GS_LIS3DH)
- {
- .type = "gs_lis3dh",
- .addr = 0x19, //0x19(SA0-->VCC), 0x18(SA0-->GND)
- .flags = 0,
- .irq = LIS3DH_INT_PIN,
- .platform_data = &lis3dh_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8963)
- {
- .type = "ak8963",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8963_info,
- },
-#endif
-
-#if defined (CONFIG_LS_PHOTORESISTOR)
- {
- .type = "ls_photoresistor",
- .addr = 0x5e,
- .flags = 0,
- .irq = INVALID_GPIO,
- .platform_data = &light_photoresistor_info,
- },
-#endif
-
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8975_info,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8975_info,
- },
-#endif
-#if defined (CONFIG_GYRO_L3G4200D)
- {
- .type = "l3g4200d_gryo",
- .addr = 0x69,
- .flags = 0,
- .irq = L3G4200D_INT_PIN,
- .platform_data = &l3g4200d_info,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-};
-#endif
-
-int __sramdata g_pmic_type = 0;
-#ifdef CONFIG_I2C1_RK30
-#ifdef CONFIG_REGULATOR_ACT8846
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-#define PMU_VSEL RK30_PIN3_PD3
-#define ACT8846_HOST_IRQ RK30_PIN0_PB3
-
-static struct pmu_info act8846_dcdc_info[] = {
- {
- .name = "act_dcdc1", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- .suspend_vol = 1200000,
- },
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 1200000,
- #else
- .suspend_vol = 900000,
- #endif
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 1200000,
- #else
- .suspend_vol = 900000,
- #endif
- },
- {
- .name = "act_dcdc4", //vccio
- .min_uv = 3000000,
- .max_uv = 3000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 3000000,
- #else
- .suspend_vol = 2800000,
- #endif
- },
-
-};
-static struct pmu_info act8846_ldo_info[] = {
- {
- .name = "act_ldo1", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "act_ldo2", //vdd12
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "act_ldo3", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo4", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo5", //vcctp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo6", //vcc_jetta
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo7", //vcc18
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo8", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- };
-
-#include "../mach-rk30/board-pmu-act8846.c"
-#endif
-
-#ifdef CONFIG_MFD_WM831X_I2C
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info wm8326_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "dcdc3", //ddr
- .min_uv = 1150000,
- .max_uv = 1150000,
- .suspend_vol = 1150000,
- },
- #ifdef CONFIG_MACH_RK3066_SDK
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3000000,
- },
- #else
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3000000,
- .max_uv = 3000000,
- .suspend_vol = 2800000,
- },
- #endif
-};
-
-static struct pmu_info wm8326_ldo_info[] = {
- {
- .name = "ldo1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo2", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo3", //
- .min_uv = 1100000,
- .max_uv = 1100000,
- .suspend_vol = 1100000,
- },
- {
- .name = "ldo4", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 1000000,
- },
- {
- .name = "ldo5", //vcc25
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo6", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo7", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- .suspend_vol = 2800000,
- },
- {
- .name = "ldo8", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo9", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo10", //flash_io
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
-};
-
-#include "../mach-rk30/board-pmu-wm8326.c"
-#endif
-
-#ifdef CONFIG_MFD_TPS65910
-#ifdef CONFIG_ARCH_RK3188
-#define TPS65910_HOST_IRQ RK30_PIN0_PB3
-#else
-#define TPS65910_HOST_IRQ RK30_PIN6_PA4
-#endif
-
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info tps65910_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1100000,
- .max_uv = 1100000,
- },
- {
- .name = "vdd2", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vio", //vcc_io
- .min_uv = 2500000,
- .max_uv = 2500000,
- },
-
-};
-static struct pmu_info tps65910_ldo_info[] = {
- {
- .name = "vpll", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "vdig2", //vdd_jetta
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vaux1", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "vaux2", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vaux33", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vmmc", //vcc30
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
- {
- .name = "vdac", //vcc18
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- };
-
-#include "../mach-rk30/board-pmu-tps65910.c"
-#endif
-
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_REGULATOR_ACT8846)
- {
- .type = "act8846",
- .addr = 0x5a,
- .flags = 0,
- .irq = ACT8846_HOST_IRQ,
- .platform_data=&act8846_data,
- },
-#endif
-#if defined (CONFIG_RTC_HYM8563)
- {
- .type = "rtc_hym8563",
- .addr = 0x51,
- .flags = 0,
- .irq = RK30_PIN0_PB5,
- },
-#endif
-#if defined (CONFIG_MFD_WM831X_I2C)
- {
- .type = "wm8326",
- .addr = 0x34,
- .flags = 0,
- .irq = RK30_PIN0_PB3,
- .platform_data = &wm831x_platdata,
- },
-#endif
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-#if defined (CONFIG_CW2015_BATTERY)
- {
- .type = "cw201x",
- .addr = 0x62,
- .flags = 0,
- .platform_data = &cw_bat_platdata,
- },
-#endif
-
-};
-#endif
-
-void __sramfunc board_pmu_suspend(void)
-{
- #if defined (CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- board_pmu_act8846_suspend();
- #endif
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_suspend();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_suspend();
- #endif
-}
-
-void __sramfunc board_pmu_resume(void)
-{
- #if defined (CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- board_pmu_act8846_resume();
- #endif
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_resume();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_resume();
- #endif
-}
-
- int __sramdata gpio3d6_iomux,gpio3d6_do,gpio3d6_dir,gpio3d6_en;
-
-#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
-
-void __sramfunc rk30_pwm_logic_suspend_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
-
-// int gpio0d7_iomux,gpio0d7_do,gpio0d7_dir,gpio0d7_en;
- sram_udelay(10000);
- gpio3d6_iomux = grf_readl(GRF_GPIO3D_IOMUX);
- gpio3d6_do = grf_readl(GRF_GPIO3H_DO);
- gpio3d6_dir = grf_readl(GRF_GPIO3H_DIR);
- gpio3d6_en = grf_readl(GRF_GPIO3H_EN);
-
- grf_writel((1<<28), GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DIR);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DO);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_EN);
-#endif
-}
-void __sramfunc rk30_pwm_logic_resume_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- grf_writel((1<<28)|gpio3d6_iomux, GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|gpio3d6_en, GRF_GPIO3H_EN);
- grf_writel((1<<30)|gpio3d6_dir, GRF_GPIO3H_DIR);
- grf_writel((1<<30)|gpio3d6_do, GRF_GPIO3H_DO);
- sram_udelay(10000);
-
-#endif
-
-}
-extern void pwm_suspend_voltage(void);
-extern void pwm_resume_voltage(void);
-void rk30_pwm_suspend_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_suspend_voltage();
-#endif
-}
-void rk30_pwm_resume_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_resume_voltage();
-#endif
-}
-
-
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-#if defined (CONFIG_CT36X_TS)
- {
- .type = CT36X_NAME,
- .addr = 0x01,
- .flags = 0,
- .platform_data = &ct36x_info,
- },
-#endif
-#if defined (CONFIG_LS_CM3217)
- {
- .type = "lightsensor",
- .addr = 0x10,
- .flags = 0,
- .platform_data = &cm3217_info,
- },
-#endif
-#if defined (CONFIG_LS_US5151)
- {
- .type = "us5151",
- .addr = 0x10,
- .flags = 0,
- },
-#endif
-
-#if defined(CONFIG_HDMI_CAT66121)
- {
- .type = "cat66121_hdmi",
- .addr = 0x4c,
- .flags = 0,
- .irq = RK30_PIN2_PD6,
- .platform_data = &rk_hdmi_pdata,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C4_RK30
-static struct i2c_board_info __initdata i2c4_info[] = {
-#ifdef CONFIG_MFD_RK610
- {
- .type = "rk610_ctl",
- .addr = 0x40,
- .flags = 0,
- .platform_data = &rk610_ctl_pdata,
- },
-#ifdef CONFIG_RK610_TVOUT
- {
- .type = "rk610_tvout",
- .addr = 0x42,
- .flags = 0,
- },
-#endif
-#ifdef CONFIG_HDMI_RK610
- {
- .type = "rk610_hdmi",
- .addr = 0x46,
- .flags = 0,
- .irq = INVALID_GPIO,
- },
-#endif
-#ifdef CONFIG_SND_SOC_RK610
- {//RK610_CODEC addr from 0x60 to 0x80 (0x60~0x80)
- .type = "rk610_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- .platform_data = &rk610_codec_pdata,
- },
-#endif
-#endif
-
-#if defined (CONFIG_SND_SOC_RT5631)
- {
- .type = "rt5631",
- .addr = 0x1a,
- .flags = 0,
- },
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO// RK30_PIN2_PD6 //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO//RK30_PIN2_PD7 //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- //set iomux (gpio) here
- //rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME, GPIO2D_GPIO2D7);
- //rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME, GPIO2D_GPIO2D6);
-
- return 0;
-}
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C4_RK30
- i2c_register_board_info(4, i2c4_info, ARRAY_SIZE(i2c4_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(5, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-
-#define POWER_ON_PIN RK30_PIN0_PA0 //power_hold
-static void rk30_pm_power_off(void)
-{
- printk(KERN_ERR "rk30_pm_power_off start...\n");
-#if defined(CONFIG_MFD_WM831X)
- wm831x_set_bits(Wm831x,WM831X_GPIO_LEVEL,0x0001,0x0000); //set sys_pwr 0
- wm831x_device_shutdown(Wm831x);//wm8326 shutdown
-#endif
-#if defined(CONFIG_REGULATOR_ACT8846)
- if (pmic_is_act8846()) {
- printk("enter dcdet===========\n");
- if(gpio_get_value (RK30_PIN0_PB2) == GPIO_LOW)
- {
- printk("enter restart===========\n");
- arm_pm_restart(0, "charge");
- }
- /** code here may cause tablet cannot boot when shutdown without charger pluged in
- * and then plug in charger. -- Cody Xie
- else
- {
- act8846_device_shutdown();
- }
- */
- }
-#endif
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
- while (1);
-}
-
-static void __init machine_rk30_board_init(void)
-{
- //avs_init();
- gpio_request(POWER_ON_PIN, "poweronpin");
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
- pm_power_off = rk30_pm_power_off;
-
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
-
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- rk_platform_add_display_devices();
- //board_usb_detect_init(RK30_PIN0_PA7);
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
- rk29sdk_wifi_bt_gpio_control_init();
-#endif
-
-#if defined(CONFIG_MT6620)
- clk_set_rate(clk_get_sys("rk_serial.1", "uart"), 48*1000000);
-#endif
-
-#if defined(CONFIG_MT5931_MT6622)
- clk_set_rate(clk_get_sys("rk_serial.0", "uart"), 24*1000000);
-#endif
-}
-
-#define HD_SCREEN_SIZE 1920UL*1200UL*4*3
-static void __init rk30_reserve(void)
-{
-#if defined(CONFIG_ARCH_RK3188)
- /*if lcd resolution great than or equal to 1920*1200,reserve the ump memory */
- if(!(get_fb_size() < ALIGN(HD_SCREEN_SIZE,SZ_1M)))
- {
- int ump_mem_phy_size=512UL*1024UL*1024UL;
- resource_mali[0].start = board_mem_reserve_add("ump buf", ump_mem_phy_size);
- resource_mali[0].end = resource_mali[0].start + ump_mem_phy_size -1;
- }
-#endif
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0 buf", get_fb_size());
- resource_fb[0].end = resource_fb[0].start + get_fb_size()- 1;
-#if 0
- resource_fb[1].start = board_mem_reserve_add("ipp buf", RK30_FB0_MEM_SIZE);
- resource_fb[1].end = resource_fb[1].start + RK30_FB0_MEM_SIZE - 1;
-#endif
-
-#if defined(CONFIG_FB_ROTATE) || !defined(CONFIG_THREE_FB_BUFFER)
- resource_fb[2].start = board_mem_reserve_add("fb2 buf",get_fb_size());
- resource_fb[2].end = resource_fb[2].start + get_fb_size() - 1;
-#endif
-#endif
-
-
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
-
-#ifdef CONFIG_GPS_RK
- //it must be more than 8MB
- rk_gps_info.u32MemoryPhyAddr = board_mem_reserve_add("gps", SZ_8M);
-#endif
- board_mem_reserved();
-}
-/******************************** arm dvfs frequency volt table **********************************/
-/**
- * dvfs_cpu_logic_table: table for arm and logic dvfs
- * @frequency : arm frequency
- * @cpu_volt : arm voltage depend on frequency
- */
-
-//sdk
-static struct cpufreq_frequency_table dvfs_arm_table_volt_level0[] = {
- {.frequency = 312 * 1000, .index = 850 * 1000},
- {.frequency = 504 * 1000, .index = 900 * 1000},
- {.frequency = 816 * 1000, .index = 950 * 1000},
- {.frequency = 1008 * 1000, .index = 1025 * 1000},
- {.frequency = 1200 * 1000, .index = 1100 * 1000},
- {.frequency = 1416 * 1000, .index = 1200 * 1000},
- {.frequency = 1608 * 1000, .index = 1300 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-//default
-static struct cpufreq_frequency_table dvfs_arm_table_volt_level1[] = {
- {.frequency = 312 * 1000, .index = 875 * 1000},
- {.frequency = 504 * 1000, .index = 925 * 1000},
- {.frequency = 816 * 1000, .index = 975 * 1000},
- {.frequency = 1008 * 1000, .index = 1075 * 1000},
- {.frequency = 1200 * 1000, .index = 1150 * 1000},
- {.frequency = 1416 * 1000, .index = 1250 * 1000},
- {.frequency = 1608 * 1000, .index = 1350 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-// ds1006h 10'
-static struct cpufreq_frequency_table dvfs_arm_table_volt_level2[] = {
- {.frequency = 312 * 1000, .index = 900 * 1000},
- {.frequency = 504 * 1000, .index = 925 * 1000},
- {.frequency = 816 * 1000, .index = 1000 * 1000},
- {.frequency = 1008 * 1000, .index = 1075 * 1000},
- {.frequency = 1200 * 1000, .index = 1200 * 1000},
- {.frequency = 1416 * 1000, .index = 1250 * 1000},
- {.frequency = 1608 * 1000, .index = 1350 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-//if you board is good for volt quality,select dvfs_arm_table_volt_level0
-#define dvfs_arm_table dvfs_arm_table_volt_level2
-
-/******************************** gpu dvfs frequency volt table **********************************/
-//sdk
-static struct cpufreq_frequency_table dvfs_gpu_table_volt_level0[] = {
- {.frequency = 133 * 1000, .index = 975 * 1000},//the mininum rate is limited 133M for rk3188
- {.frequency = 200 * 1000, .index = 975 * 1000},
- {.frequency = 266 * 1000, .index = 1000 * 1000},
- {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1100 * 1000},
- {.frequency = 600 * 1000, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-//ds1006h 10'
-static struct cpufreq_frequency_table dvfs_gpu_table_volt_level1[] = {
- {.frequency = 133 * 1000, .index = 975 * 1000},
- {.frequency = 200 * 1000, .index = 1000 * 1000},
- {.frequency = 266 * 1000, .index = 1025 * 1000},
- {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1100 * 1000},
- {.frequency = 600 * 1000, .index = 1250 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-#define dvfs_gpu_table dvfs_gpu_table_volt_level1
-
-/******************************** ddr dvfs frequency volt table **********************************/
-static struct cpufreq_frequency_table dvfs_ddr_table_volt_level0[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 950 * 1000},
- {.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = 1000 * 1000},
- {.frequency = 396 * 1000 + DDR_FREQ_NORMAL, .index = 1100 * 1000},
- {.frequency = 460 * 1000 + DDR_FREQ_DUALVIEW, .index = 1150 * 1000},
- //{.frequency = 528 * 1000 + DDR_FREQ_NORMAL, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table_t[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 950 * 1000},
- {.frequency = 460 * 1000 + DDR_FREQ_NORMAL, .index = 1150 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-#define dvfs_ddr_table dvfs_ddr_table_volt_level0
-
-/******************************** arm dvfs frequency volt table end **********************************/
-
-
-
-//#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
-//static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
-//static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
-int get_max_freq(struct cpufreq_frequency_table *table)
-{
- int i,temp=0;
-
- for(i=0;table[i].frequency!= CPUFREQ_TABLE_END;i++)
- {
- if(temp<table[i].frequency)
- temp=table[i].frequency;
- }
- printk("get_max_freq=%d\n",temp);
- return temp;
-}
-
-void __init board_clock_init(void)
-{
- u32 flags=RK30_CLOCKS_DEFAULT_FLAGS;
-#if !defined(CONFIG_ARCH_RK3188)
- if(get_max_freq(dvfs_gpu_table)<=(400*1000))
- {
- flags=RK30_CLOCKS_DEFAULT_FLAGS|CLK_GPU_GPLL;
- }
- else
- flags=RK30_CLOCKS_DEFAULT_FLAGS|CLK_GPU_CPLL;
-#endif
- rk30_clock_data_init(periph_pll_default, codec_pll_default, flags);
- //dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "cpu"), dvfs_arm_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
-#if defined(CONFIG_ARCH_RK3188)
- if (rk_pll_flag() == 0)
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
- else
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table_t);
-#else
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
-#endif
-}
-
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk30_fixup,
- .reserve = &rk30_reserve,
- .map_io = rk30_map_io,
- .init_irq = rk30_init_irq,
- .timer = &rk30_timer,
- .init_machine = machine_rk30_board_init,
-MACHINE_END
+++ /dev/null
-/*
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <mach/dvfs.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <linux/rk_fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/mfd/tps65910.h>
-#include <linux/regulator/act8846.h>
-#include <linux/mfd/rk808.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-
-#if defined(CONFIG_MFD_RK610)
-#include <linux/mfd/rk610_core.h>
-#endif
-
-#if defined(CONFIG_MFD_RK616)
-#include <linux/mfd/rk616.h>
-#endif
-
-
-#if defined(CONFIG_RK_HDMI)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-#if defined(CONFIG_GPS_RK)
-#include "../../../drivers/misc/gps/rk_gps/rk_gps.h"
-#endif
-#if defined(CONFIG_MU509)
-#include <linux/mu509.h>
-#endif
-#if defined(CONFIG_MW100)
-#include <linux/mw100.h>
-#endif
-#if defined(CONFIG_MT6229)
-#include <linux/mt6229.h>
-#endif
-#if defined(CONFIG_ANDROID_TIMED_GPIO)
-#include "../../../drivers/staging/android/timed_gpio.h"
-#endif
-
-#if defined(CONFIG_MT6620)
-#include <linux/gps.h>
-#endif
-#include "../mach-rk30/board-rk3168-tb-camera.c"
-
-#include <plat/config.h>
-#include <plat/board.h>
-#include "../plat-rk/rk-fac-config.c"
-#if 1
-#define INIT_ERR(name) do { printk("%s: %s init Failed: \n", __func__, (name)); } while(0)
-#else
-#define INIT_ERR(name)
-#endif
-
-////////////////////////////////////////////////////////////////////////////////////////
-#include <plat/key.h>
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "play",
- .code = KEY_POWER,
- .wakeup = 1,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- },
- {
- .desc = "menu",
- .code = EV_MENU,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- },
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .chn = -1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-////////////////////////////////////////////////////////////////////////////////////////
-//Backlight
-////////////////////////////////////////////////////////////////////////////////////////
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
- printk("rk29_backlight_io_init %d\n",bl_pwm_mode);
- iomux_set(bl_pwm_mode);
- msleep(100);
-
- if(bl_en== -1)
- return 0;
- ret = port_output_init(bl_en, 1, "bl_en");
- if(ret < 0){
- printk("%s: port output init faild\n", __func__);
- return ret;
- }
- port_output_on(bl_en);
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0, pwm_gpio;
-
- if(bl_en != -1)
- port_deinit(bl_en);
-
- pwm_gpio = iomux_mode_to_gpio(bl_pwm_mode);
- gpio_request(pwm_gpio, NULL);
- gpio_direction_output(pwm_gpio, GPIO_LOW);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret = 0, pwm_gpio;
-
- pwm_gpio = iomux_mode_to_gpio(bl_pwm_mode);
- if (gpio_request(pwm_gpio, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- gpio_direction_output(pwm_gpio, GPIO_LOW);
- port_output_off(bl_en);
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- int pwm_gpio = iomux_mode_to_gpio(bl_pwm_mode);
- gpio_free(pwm_gpio);
- iomux_set(bl_pwm_mode);
- msleep(150);
- port_output_on(bl_en);
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-#endif
-////////////////////////////////////////////////////////////////////////////////////////
-//LCD
-////////////////////////////////////////////////////////////////////////////////////////
-#ifdef CONFIG_FB_ROCKCHIP
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
- //printk("rk_fb_io_init %x,%x,%x\n",lcd_cs,lcd_en,lcd_std);
- if(lcd_cs != -1){
- ret = port_output_init(lcd_cs, 1, "lcd_cs");
- if(ret < 0)
- printk("%s: port output init faild\n", __func__);
- port_output_on(lcd_cs);
- }
-
- if(lcd_en != -1){
- ret = port_output_init(lcd_en, 1, "lcd_en");
- if(ret < 0)
- printk("%s: port output init faild\n", __func__);
- port_output_on(lcd_en);
- }
-
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
- if(lcd_cs != -1)
- port_output_off(lcd_cs);
- if(lcd_en != -1)
- port_output_on(lcd_en);
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- if(lcd_en != -1)
- port_output_on(lcd_en);
- if(lcd_cs != -1)
- port_output_on(lcd_cs);
- return 0;
-}
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
-struct rk29fb_info lcdc0_screen_info = {
-#if defined(CONFIG_RK_HDMI) && defined(CONFIG_HDMI_SOURCE_LCDC0) && defined(CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL)
- .prop = EXTEND, //extend display device
- .io_init = NULL,
- .io_disable = NULL,
- .io_enable = NULL,
- .set_screen_info = hdmi_init_lcdc,
-#else
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-#endif
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
-struct rk29fb_info lcdc1_screen_info = {
-#if defined(CONFIG_RK_HDMI) && defined(CONFIG_HDMI_SOURCE_LCDC1) && defined(CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL)
- .prop = EXTEND, //extend display device
- .io_init = NULL,
- .io_disable = NULL,
- .io_enable = NULL,
- .set_screen_info = hdmi_init_lcdc,
-#else
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-#endif
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
-static struct resource resource_lcdc0[] = {
- [0] = {
- .name = "lcdc0 reg",
- .start = RK30_LCDC0_PHYS,
- .end = RK30_LCDC0_PHYS + RK30_LCDC0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc0 irq",
- .start = IRQ_LCDC0,
- .end = IRQ_LCDC0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc0 = {
- .name = "rk30-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc0),
- .resource = resource_lcdc0,
- .dev = {
- .platform_data = &lcdc0_screen_info,
- },
-};
-#endif
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
-static struct resource resource_lcdc1[] = {
- [0] = {
- .name = "lcdc1 reg",
- .start = RK30_LCDC1_PHYS,
- .end = RK30_LCDC1_PHYS + RK30_LCDC1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc1 irq",
- .start = IRQ_LCDC1,
- .end = IRQ_LCDC1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc1 = {
- .name = "rk30-lcdc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resource_lcdc1),
- .resource = resource_lcdc1,
- .dev = {
- .platform_data = &lcdc1_screen_info,
- },
-};
-#endif
-////////////////////////////////////////////////////////////////////////////////////////
-//TP
-////////////////////////////////////////////////////////////////////////////////////////
-#if defined (CONFIG_TOUCHSCREEN_GSLX680_RK3168)
-static int gslx680_init_platform_hw()
-{
- int ret;
- if(tp_rst!=-1){
- ret = port_output_init(tp_rst, 1, "tp_rst");
- if(ret<0)
- printk("%s: port output init faild\n", __func__);
- }
-
- port_output_on(tp_rst);
- mdelay(10);
- port_output_off(tp_rst);
- mdelay(10);
- port_output_on(tp_rst);
- msleep(300);
- return 0;
-}
-
-static struct tp_platform_data gslx680_data = {
-
- .init_platform_hw = gslx680_init_platform_hw,
-};
-struct i2c_board_info __initdata gslx680_info = {
- .type = "gslX680",
- .flags = 0,
- .platform_data = &gslx680_data,
-};
-#endif
-
-
-#if defined (CONFIG_TOUCHSCREEN_86V_GT811_IIC)
-int gt811_init_platform_hw(int irq,int reset)
-{
- int ret;
- if(tp_rst!=-1){
- ret = port_output_init(tp_rst, 1, "tp_rst");
- if(ret<0)
- printk("%s: port output init faild\n", __func__);
- }
-
- port_output_off(tp_rst);
- msleep(500);
- port_output_off(tp_rst);
- msleep(500);
- port_output_on(tp_rst);
- mdelay(100);
- return 0;
-}
-
-
-static struct tp_platform_data gt811_data = {
- .model= 811,
- .init_platform_hw= gt811_init_platform_hw,
-};
-
-struct i2c_board_info __initdata gt811_info = {
- .type = "gt811_ts",
- .flags = 0,
- .platform_data = >811_data,
-};
-#endif
-
-
-#if defined(CONFIG_TOUCHSCREEN_GT8XX)
-#define TOUCH_PWR_PIN RK30_PIN0_PC5 // need to fly line by hardware engineer
-static int goodix_init_platform_hw(void)
-{
- int ret;
-
- if (TOUCH_PWR_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_PWR_PIN, "goodix power pin");
- if (ret != 0) {
- gpio_free(TOUCH_PWR_PIN);
- printk("goodix power error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_PWR_PIN, 0);
- gpio_set_value(TOUCH_PWR_PIN, GPIO_LOW);
- msleep(100);
- }
-
- if(tp_rst!=-1){
- ret = port_output_init(tp_rst, 1, "tp_rst");
- if(ret<0)
- printk("%s: port output init faild\n", __func__);
- }
- port_output_on(tp_rst);
- msleep(100);
- return 0;
-}
-
-struct tp_platform_data goodix_data = {
- .model = 8105,
- .init_platform_hw = goodix_init_platform_hw,
-};
-
-struct i2c_board_info __initdata goodix_info = {
- .type = "Goodix-TS",
- .flags = 0,
- .platform_data = &goodix_data,
-};
-#endif
-
-////////////////////////////////////////////////////////////////////////////////////////
-//Gsensor
-////////////////////////////////////////////////////////////////////////////////////////
-/*MMA7660 gsensor*/
-#if defined (CONFIG_GS_MMA7660)
-static int mma7660_init_platform_hw(void)
-{
- //rk30_mux_api_set(GPIO1B2_SPI_RXD_UART1_SIN_NAME, GPIO1B_GPIO1B2);
-
- return 0;
-}
-
-static struct sensor_platform_data mma7660_data = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma7660_init_platform_hw,
-};
-struct i2c_board_info __initdata mma7660_info = {
- .type = "gs_mma7660",
- .flags = 0,
- .platform_data =&mma7660_data,
-};
-#endif
-
-#if defined (CONFIG_GS_MXC6225)
-static int mxc6225_init_platform_hw(void)
-{
-// rk30_mux_api_set(GPIO1B1_SPI_TXD_UART1_SOUT_NAME, GPIO1B_GPIO1B1);
- return 0;
-}
-
-static struct sensor_platform_data mxc6225_data = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 0,
- .poll_delay_ms = 30,
- .init_platform_hw = mxc6225_init_platform_hw,
-};
-struct i2c_board_info __initdata mxc6225_info = {
- .type = "gs_mxc6225",
- .flags = 0,
- .platform_data =&mxc6225_data,
-};
-#endif
-
-#if defined (CONFIG_GS_DMT10)
-static int dmt10_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data dmt10_data = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 0,
- .poll_delay_ms = 30,
- .init_platform_hw = dmt10_init_platform_hw,
-};
-struct i2c_board_info __initdata dmt10_info = {
- .type = "gs_dmard10",
- .flags = 0,
- .platform_data =&dmt10_data,
-};
-#endif
-
-
-#if defined (CONFIG_GS_LIS3DH)
-static int lis3dh_init_platform_hw(void)
-{
- return 0;
-}
-static struct sensor_platform_data lis3dh_data = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lis3dh_init_platform_hw,
-};
-struct i2c_board_info __initdata lis3dh_info = {
- .type = "gs_lis3dh",
- .flags = 0,
- .platform_data =&lis3dh_data,
-};
-#endif
-
-#if defined (CONFIG_GS_LSM303D)
-static int lms303d_init_platform_hw(void)
-{
- return 0;
-}
-static struct sensor_platform_data lms303d_data = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lms303d_init_platform_hw,
-};
-struct i2c_board_info __initdata lms303d_info = {
- .type = "gs_lsm303d",
- .flags = 0,
- .platform_data =&lms303d_data,
-};
-#endif
-
-#if defined (CONFIG_GS_MMA8452)
-static int mma8452_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data mma8452_data = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma8452_init_platform_hw,
-};
-struct i2c_board_info __initdata mma8452_info = {
- .type = "gs_mma8452",
- .flags = 0,
- .platform_data =&mma8452_data,
-};
-#endif
-
-////////////////////////////////////////////////////////////////////////////////////////
-//battery
-////////////////////////////////////////////////////////////////////////////////////////
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
-
-};
-
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-
-////////////////////////////////////////////////////////////////////////////////////////
-//codec
-////////////////////////////////////////////////////////////////////////////////////////
-#if defined (CONFIG_SND_RK29_SOC_RT5631)
-static struct codec_platform_data rt5631_data = {
-};
-struct i2c_board_info __initdata rt5631_info = {
- .type = "rt5631",
- .flags = 0,
- .platform_data =&rt5631_data,
-};
-#endif
-
-#if defined (CONFIG_SND_RK29_SOC_ES8323)
-static struct codec_platform_data es8323_data = {
-};
-struct i2c_board_info __initdata es8323_info = {
- .type = "es8323",
- .flags = 0,
- .platform_data =&es8323_data,
-};
-#endif
-
-#if defined(CONFIG_MFD_RK616)
-#define RK616_SCL_RATE (100*1000) //i2c scl rate
-static int rk616_power_on_init(void)
-{
- int ret;
-
- if(codec_power!=-1)
- {
- ret = port_output_init(codec_power, 1, "codec_power");
- if(ret < 0)
- printk("%s: port output init faild\n", __func__);
- port_output_on(codec_power);
- }
-
- if(codec_rst!=-1)
- {
- ret = port_output_init(codec_rst, 1, "codec_rst");
- if(ret < 0)
- printk("%s: port output init faild\n", __func__);
- port_output_on(codec_rst);
- msleep(100);
- port_output_off(codec_rst);
- msleep(100);
- port_output_on(codec_rst);
- }
- return 0;
-
-}
-
-
-static int rk616_power_deinit(void)
-{
- if(codec_power!=-1)
- {
- port_output_off(codec_power);
- port_deinit(codec_power);
- }
- if(codec_rst!=-1)
- {
- port_output_off(codec_rst);
- port_deinit(codec_rst);
- }
- return 0;
-}
-
-static struct rk616_platform_data rk616_pdata = {
- .power_init = rk616_power_on_init,
- .power_deinit = rk616_power_deinit,
- .scl_rate = RK616_SCL_RATE,
- .lcd0_func = INPUT, //port lcd0 as input
- .lcd1_func = INPUT, //port lcd1 as input
- .lvds_ch_nr = 1, //the number of used lvds channel
- //.hdmi_irq = RK30_PIN2_PD6,
- //.spk_ctl_gpio = RK30_PIN2_PD7,
- .hp_ctl_gpio = RK30_PIN2_PD7,
-};
-
-struct i2c_board_info __initdata rk616_info = {
- .type = "rk616",
- .flags = 0,
- .platform_data = &rk616_pdata,
-};
-#endif
-
-
-////////////////////////////////////////////////////////////////////////////////////////
-//spi
-////////////////////////////////////////////////////////////////////////////////////////
-static struct spi_board_info board_spi_devices[] = {
-};
-
-////////////////////////////////////////////////////////////////////////////////////////
-//modem
-////////////////////////////////////////////////////////////////////////////////////////
-#ifdef CONFIG_RK29_SUPPORT_MODEM
-
-#define RK30_MODEM_POWER RK30_PIN0_PC6
-#define RK30_MODEM_POWER_IOMUX iomux_set(GPIO0_C6)
-
-static int rk30_modem_io_init(void)
-{
- printk("%s\n", __FUNCTION__);
- RK30_MODEM_POWER_IOMUX;
-
- return 0;
-}
-
-static struct rk29_io_t rk30_modem_io = {
- .io_addr = RK30_MODEM_POWER,
- .enable = GPIO_HIGH,
- .disable = GPIO_LOW,
- .io_init = rk30_modem_io_init,
-};
-
-static struct platform_device rk30_device_modem = {
- .name = "rk30_modem",
- .id = -1,
- .dev = {
- .platform_data = &rk30_modem_io,
- }
-};
-#endif
-#if defined(CONFIG_MU509)
-static int mu509_io_init(void)
-{
-
- iomux_set(GPIO2_D5);
- iomux_set(GPIO0_C6);
- iomux_set(GPIO2_D4);
- iomux_set(GPIO0_C4);
- iomux_set(GPIO0_C5);
- return 0;
-}
-
-static int mu509_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mu509_data rk29_mu509_info = {
- .io_init = mu509_io_init,
- .io_deinit = mu509_io_deinit,
- .modem_power_en = RK30_PIN2_PD5,
- .bp_power = RK30_PIN0_PC6,
- .bp_reset = RK30_PIN2_PD4,
- .ap_wakeup_bp = RK30_PIN0_PC4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
-};
-struct platform_device rk29_device_mu509 = {
- .name = "mu509",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mu509_info,
- }
- };
-#endif
-#if defined(CONFIG_MW100)
-static int mw100_io_init(void)
-{
- iomux_set(GPIO2_D5);
- iomux_set(GPIO0_C6);
- iomux_set(GPIO2_D4);
- iomux_set(GPIO0_C4);
- iomux_set(GPIO0_C5);
- return 0;
-}
-
-static int mw100_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mw100_data rk29_mw100_info = {
- .io_init = mw100_io_init,
- .io_deinit = mw100_io_deinit,
- .modem_power_en = RK30_PIN2_PD5,
- .bp_power = RK30_PIN0_PC6,
- .bp_reset = RK30_PIN2_PD4,
- .ap_wakeup_bp = RK30_PIN0_PC4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
-};
-struct platform_device rk29_device_mw100 = {
- .name = "mw100",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mw100_info,
- }
- };
-#endif
-#if defined(CONFIG_MT6229)
-static int mt6229_io_init(void)
-{
- iomux_set(GPIO2_D5);
- iomux_set(GPIO0_C6);
- iomux_set(GPIO2_D4);
- iomux_set(GPIO0_C4);
- iomux_set(GPIO0_C5);
- return 0;
-}
-
-static int mt6229_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mt6229_data rk29_mt6229_info = {
- .io_init = mt6229_io_init,
- .io_deinit = mt6229_io_deinit,
- .modem_power_en = RK30_PIN2_PD5,
- .bp_power = RK30_PIN0_PC6,
- .bp_reset = RK30_PIN2_PD4,
- .ap_wakeup_bp = RK30_PIN0_PC4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
-};
-struct platform_device rk29_device_mt6229 = {
- .name = "mt6229",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mt6229_info,
- }
- };
-#endif
-
-
-////////////////////////////////////////////////////////////////////////////////////////
-//compass
-////////////////////////////////////////////////////////////////////////////////////////
-#if defined (CONFIG_COMPASS_AK8975)
-static struct sensor_platform_data akm8975_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-#if defined(CONFIG_GYRO_L3G4200D)
-
-#include <linux/l3g4200d.h>
-#define L3G4200D_INT_PIN RK30_PIN0_PB4
-
-static int l3g4200d_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data l3g4200d_info = {
- .type = SENSOR_TYPE_GYROSCOPE,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
- .init_platform_hw = l3g4200d_init_platform_hw,
- .x_min = 40,//x_min,y_min,z_min = (0-100) according to hardware
- .y_min = 40,
- .z_min = 20,
-};
-
-#endif
-
-#ifdef CONFIG_LS_CM3217
-static struct sensor_platform_data cm3217_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 0,
- .poll_delay_ms = 500,
-};
-
-#endif
-
-
-
-////////////////////////////////////////////////////////////////////////////////////////
-//GPU
-////////////////////////////////////////////////////////////////////////////////////////
-#if defined(CONFIG_ARCH_RK3188)
-static struct resource resource_mali[] = {
- [0] = {
- .name = "ump buf",
- .start = 0,
- .end = 0,
- .flags = IORESOURCE_MEM,
- },
-
-};
-
-static struct platform_device device_mali= {
- .name = "mali400_ump",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_mali),
- .resource = resource_mali,
-};
-#endif
-
-////////////////////////////////////////////////////////////////////////////////////////
-//TimeGpio
-////////////////////////////////////////////////////////////////////////////////////////
-#ifdef CONFIG_ANDROID_TIMED_GPIO
-static struct timed_gpio timed_gpios[] = {
- {
- .name = "vibrator",
- .gpio = INVALID_GPIO,
- .max_timeout = 1000,
- .active_low = 0,
- .adjust_time =20, //adjust for diff product
- },
-};
-
-static struct timed_gpio_platform_data rk29_vibrator_info = {
- .num_gpios = 1,
- .gpios = timed_gpios,
-};
-
-static struct platform_device rk29_device_vibrator = {
- .name = "timed-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_vibrator_info,
- },
-
-};
-#endif
-
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
-static struct gpio_led rk29_leds[] = {
- {
- .name = "button-backlight",
- .gpio = INVALID_GPIO,
- .default_trigger = "timer",
- .active_low = 0,
- .retain_state_suspended = 0,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- },
-};
-
-static struct gpio_led_platform_data rk29_leds_pdata = {
- .leds = rk29_leds,
- .num_leds = ARRAY_SIZE(rk29_leds),
-};
-
-static struct platform_device rk29_device_gpio_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_leds_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_RK_IRDA
-#define IRDA_IRQ_PIN INVALID_GPIO //RK30_PIN0_PA3
-
-static int irda_iomux_init(void)
-{
- int ret = 0;
-
- //irda irq pin
- ret = gpio_request(IRDA_IRQ_PIN, NULL);
- if (ret != 0) {
- gpio_free(IRDA_IRQ_PIN);
- printk(">>>>>> IRDA_IRQ_PIN gpio_request err \n ");
- }
- gpio_pull_updown(IRDA_IRQ_PIN, PullDisable);
- gpio_direction_input(IRDA_IRQ_PIN);
-
- return 0;
-}
-
-static int irda_iomux_deinit(void)
-{
- gpio_free(IRDA_IRQ_PIN);
- return 0;
-}
-
-static struct irda_info rk29_irda_info = {
- .intr_pin = IRDA_IRQ_PIN,
- .iomux_init = irda_iomux_init,
- .iomux_deinit = irda_iomux_deinit,
- //.irda_pwr_ctl = bu92747guw_power_ctl,
-};
-
-static struct platform_device irda_device = {
-#ifdef CONFIG_RK_IRDA_NET
- .name = "rk_irda",
-#else
- .name = "bu92747_irda",
-#endif
- .id = -1,
- .dev = {
- .platform_data = &rk29_irda_info,
- }
-};
-#endif
-
-
-////////////////////////////////////////////////////////////////////////////////////////
-//ION
-////////////////////////////////////////////////////////////////////////////////////////
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and sdio.noted by xbw at 2012-03-05
-**************************************************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "../mach-rk30/board-rk3168-tb-sdmmc-conifg.c"
-#include "../plat-rk/rk-sdmmc-ops.c"
-#include "../plat-rk/rk-sdmmc-wifi.c"
-#endif //endif ---#ifdef CONFIG_SDMMC_RK29
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- iomux_set(MMC0_CMD);
- iomux_set(MMC0_CLKOUT);
- iomux_set(MMC0_D0);
- iomux_set(MMC0_D1);
- iomux_set(MMC0_D2);
- iomux_set(MMC0_D3);
-
- iomux_set_gpio_mode(iomux_mode_to_gpio(MMC0_DETN));
-
- gpio_request(RK30_PIN3_PA7, "sdmmc-power");
- gpio_direction_output(RK30_PIN3_PA7, GPIO_LOW);
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- #if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set_gpio_mode(iomux_gpio_to_mode(RK29SDK_SD_CARD_DETECT_N));
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO);
- #endif
- #else
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(MMC0_DETN);
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FMUX);
- #endif
- #endif
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) && defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- .status = rk29sdk_wifi_mmc0_status,
- .register_status_notify = rk29sdk_wifi_mmc0_status_register,
-#endif
-
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .power_en = RK29SDK_SD_CARD_PWR_EN,
- .power_en_level = RK29SDK_SD_CARD_PWR_EN_LEVEL,
-#else
- .power_en = INVALID_GPIO,
- .power_en_level = GPIO_LOW,
-#endif
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC0_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- .det_pin_info = {
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N, //INVALID_GPIO,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
- #endif
- },
-
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- iomux_set(MMC1_CMD);
- iomux_set(MMC1_CLKOUT);
- iomux_set(MMC1_D0);
- iomux_set(MMC1_D1);
- iomux_set(MMC1_D2);
- iomux_set(MMC1_D3);
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC) || defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC1_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- #if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
- .sdio_INT_gpio = RK29SDK_WIFI_SDIO_CARD_INT,
- #endif
-
- .det_pin_info = {
-#if defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- #else
- .io = INVALID_GPIO,
- #endif
-
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-
- .enable_sd_wakeup = 0,
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-////////////////////////////////////////////////////////////////////////////////////////
-//PMU
-////////////////////////////////////////////////////////////////////////////////////////
-#ifdef CONFIG_RK30_PWM_REGULATOR
-static int pwm_voltage_map[] = {
- 800000,825000,850000, 875000,900000, 925000 ,950000, 975000,1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000,1375000
-};
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_cpu",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] =
-{
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
- .pwm_id = 1,
- .pwm_gpio = RK30_PIN3_PD4,
- .pwm_iomux_pwm = PWM1,
- .pwm_iomux_gpio = GPIO3_D4,
- .pwm_voltage = 1100000,
- .suspend_voltage = 1000000,
- .min_uV = 800000,
- .max_uV = 1375000,
- .coefficient = 575, //57.5%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-#endif
-
-#ifdef CONFIG_RK29_VMAC
-#define PHY_PWR_EN_GPIO RK30_PIN1_PD6
-#include "board-rk30-sdk-vmac.c"
-#endif
-
-#ifdef CONFIG_RFKILL_RK
-// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
-static struct rfkill_rk_platform_data rfkill_rk_platdata = {
- .type = RFKILL_TYPE_BLUETOOTH,
-
- .poweron_gpio = { // BT_REG_ON
- .io = INVALID_GPIO, //RK30_PIN3_PC7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_poweron",
- .fgpio = GPIO3_C7,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN3_PC7, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_reset",
- .fgpio = GPIO3_C7,
- },
- },
-
- .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
- .io = RK30_PIN3_PC6, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_wake",
- .fgpio = GPIO3_C6,
- },
- },
-
- .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .gpio = {
- .io = RK30_PIN0_PA5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
- .iomux = {
- .name = NULL,
- },
- },
- },
-
- .rts_gpio = { // UART_RTS, enable or disable BT's data coming
- .io = RK30_PIN1_PA3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_rts",
- .fgpio = GPIO1_A3,
- .fmux = UART0_RTSN,
- },
- },
-};
-
-static struct platform_device device_rfkill_rk = {
- .name = "rfkill_rk",
- .id = -1,
- .dev = {
- .platform_data = &rfkill_rk_platdata,
- },
-};
-#endif
-
-#if defined(CONFIG_GPS_RK)
-int rk_gps_io_init(void)
-{
- printk("%s \n", __FUNCTION__);
-
- gpio_request(RK30_PIN1_PB5, NULL);
- gpio_direction_output(RK30_PIN1_PB5, GPIO_LOW);
-
- iomux_set(GPS_RFCLK);//GPS_CLK
- iomux_set(GPS_MAG);//GPS_MAG
- iomux_set(GPS_SIG);//GPS_SIGN
-
- gpio_request(RK30_PIN1_PA6, NULL);
- gpio_direction_output(RK30_PIN1_PA6, GPIO_LOW);
-
- gpio_request(RK30_PIN1_PA5, NULL);
- gpio_direction_output(RK30_PIN1_PA5, GPIO_LOW);
-
- gpio_request(RK30_PIN1_PA7, NULL);
- gpio_direction_output(RK30_PIN1_PA7, GPIO_LOW);
- return 0;
-}
-int rk_gps_power_up(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_power_down(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_reset_set(int level)
-{
- return 0;
-}
-int rk_enable_hclk_gps(void)
-{
- struct clk *gps_aclk = NULL;
- gps_aclk = clk_get(NULL, "aclk_gps");
- if(gps_aclk) {
- clk_enable(gps_aclk);
- clk_put(gps_aclk);
- printk("%s \n", __FUNCTION__);
- }
- else
- printk("get gps aclk fail\n");
- return 0;
-}
-int rk_disable_hclk_gps(void)
-{
- struct clk *gps_aclk = NULL;
- gps_aclk = clk_get(NULL, "aclk_gps");
- if(gps_aclk) {
- //TO wait long enough until GPS ISR is finished.
- msleep(5);
- clk_disable(gps_aclk);
- clk_put(gps_aclk);
- printk("%s \n", __FUNCTION__);
- }
- else
- printk("get gps aclk fail\n");
- return 0;
-}
-struct rk_gps_data rk_gps_info = {
- .io_init = rk_gps_io_init,
- .power_up = rk_gps_power_up,
- .power_down = rk_gps_power_down,
- .reset = rk_gps_reset_set,
- .enable_hclk_gps = rk_enable_hclk_gps,
- .disable_hclk_gps = rk_disable_hclk_gps,
- .GpsSign = RK30_PIN1_PB3,
- .GpsMag = RK30_PIN1_PB2, //GPIO index
- .GpsClk = RK30_PIN1_PB4, //GPIO index
- .GpsVCCEn = RK30_PIN1_PB5, //GPIO index
- .GpsSpi_CSO = RK30_PIN1_PA4, //GPIO index
- .GpsSpiClk = RK30_PIN1_PA5, //GPIO index
- .GpsSpiMOSI = RK30_PIN1_PA7, //GPIO index
- .GpsIrq = IRQ_GPS,
- .GpsSpiEn = 0,
- .GpsAdcCh = 2,
- .u32GpsPhyAddr = RK30_GPS_PHYS,
- .u32GpsPhySize = RK30_GPS_SIZE,
-};
-
-struct platform_device rk_device_gps = {
- .name = "gps_hv5820b",
- .id = -1,
- .dev = {
- .platform_data = &rk_gps_info,
- }
- };
-#endif
-
-#if defined(CONFIG_MT5931_MT6622)
-static struct mt6622_platform_data mt6622_platdata = {
- .power_gpio = { // BT_REG_ON
- .io = RK30_PIN3_PD5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN0_PD7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .irq_gpio = {
- .io = RK30_PIN3_PD2,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- }
-};
-
-static struct platform_device device_mt6622 = {
- .name = "mt6622",
- .id = -1,
- .dev = {
- .platform_data = &mt6622_platdata,
- },
-};
-#endif
-
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_ANDROID_TIMED_GPIO
- &rk29_device_vibrator,
-#endif
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
- &rk29_device_gpio_leds,
-#endif
-#ifdef CONFIG_RK_IRDA
- &irda_device,
-#endif
-#if defined(CONFIG_WIFI_CONTROL_FUNC)||defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- &rk29sdk_wifi_device,
-#endif
-
-#if defined(CONFIG_MT6620)
- &mt3326_device_gps,
-#endif
-
-#ifdef CONFIG_RK29_SUPPORT_MODEM
- &rk30_device_modem,
-#endif
-#if defined(CONFIG_MU509)
- &rk29_device_mu509,
-#endif
-#if defined(CONFIG_MW100)
- &rk29_device_mw100,
-#endif
-#if defined(CONFIG_MT6229)
- &rk29_device_mt6229,
-#endif
-#if defined(CONFIG_BATTERY_RK30_ADC)||defined(CONFIG_BATTERY_RK30_ADC_FAC)
- &rk30_device_adc_battery,
-#endif
-#ifdef CONFIG_RFKILL_RK
- &device_rfkill_rk,
-#endif
-#ifdef CONFIG_GPS_RK
- &rk_device_gps,
-#endif
-#if defined(CONFIG_ARCH_RK3188)
- &device_mali,
-#endif
-#ifdef CONFIG_MT5931_MT6622
- &device_mt6622,
-#endif
-};
-
-static int rk_platform_add_display_devices(void)
-{
- struct platform_device *fb = NULL; //fb
- struct platform_device *lcdc0 = NULL; //lcdc0
- struct platform_device *lcdc1 = NULL; //lcdc1
- struct platform_device *bl = NULL; //backlight
-#ifdef CONFIG_FB_ROCKCHIP
- fb = &device_fb;
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
- lcdc0 = &device_lcdc0,
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
- lcdc1 = &device_lcdc1,
-#endif
-
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- bl = &rk29_device_backlight,
-#endif
- __rk_platform_add_display_devices(fb,lcdc0,lcdc1,bl);
-
- return 0;
-
-}
-
-// i2c
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8975_info,
- },
-#endif
-#if defined (CONFIG_GYRO_L3G4200D)
- {
- .type = "l3g4200d_gryo",
- .addr = 0x69,
- .flags = 0,
- .irq = L3G4200D_INT_PIN,
- .platform_data = &l3g4200d_info,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RT5640)
- {
- .type = "rt5640",
- .addr = 0x1c,
- .flags = 0,
- },
-#endif
-
-#ifdef CONFIG_MFD_RK610
- {
- .type = "rk610_ctl",
- .addr = 0x40,
- .flags = 0,
- .platform_data = &rk610_ctl_pdata,
- },
-#ifdef CONFIG_RK610_TVOUT
- {
- .type = "rk610_tvout",
- .addr = 0x42,
- .flags = 0,
- },
-#endif
-#ifdef CONFIG_HDMI_RK610
- {
- .type = "rk610_hdmi",
- .addr = 0x46,
- .flags = 0,
- .irq = INVALID_GPIO,
- },
-#endif
-#ifdef CONFIG_SND_SOC_RK610
- {//RK610_CODEC addr from 0x60 to 0x80 (0x60~0x80)
- .type = "rk610_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- .platform_data = &rk610_codec_pdata,
- },
-#endif
-#endif
-
-};
-#endif
-
-int __sramdata g_pmic_type = 0;
-#ifdef CONFIG_I2C1_RK30
-#ifdef CONFIG_MFD_WM831X_I2C
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info wm8326_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "dcdc3", //ddr
- .min_uv = 1150000,
- .max_uv = 1150000,
- .suspend_vol = 1150000,
- },
- #ifdef CONFIG_MACH_RK3066_SDK
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3000000,
- },
- #else
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3000000,
- .max_uv = 3000000,
- .suspend_vol = 2800000,
- },
- #endif
-};
-
-static struct pmu_info wm8326_ldo_info[] = {
- {
- .name = "ldo1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo2", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo3", //
- .min_uv = 1100000,
- .max_uv = 1100000,
- .suspend_vol = 1100000,
- },
- {
- .name = "ldo4", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 1000000,
- },
- {
- .name = "ldo5", //vcc25
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo6", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo7", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- .suspend_vol = 2800000,
- },
- {
- .name = "ldo8", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo9", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo10", //flash_io
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
-};
-
-#include "../mach-rk30/board-pmu-wm8326.c"
-#endif
-
-#ifdef CONFIG_MFD_TPS65910
-#define TPS65910_HOST_IRQ RK30_PIN0_PB3
-
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info tps65910_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1100000,
- .max_uv = 1100000,
- },
- {
- .name = "vdd2", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vio", //vcc_io
- .min_uv = 2500000,
- .max_uv = 2500000,
- },
-
-};
-static struct pmu_info tps65910_ldo_info[] = {
- {
- .name = "vpll", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "vdig2", //vdd_jetta
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vaux1", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "vaux2", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vaux33", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vmmc", //vcc30
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
- {
- .name = "vdac", //vcc18
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- };
-
-#include "../mach-rk30/board-pmu-tps65910.c"
-#endif
-
-#ifdef CONFIG_REGULATOR_ACT8846
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-#define PMU_VSEL RK30_PIN3_PD3
-static struct pmu_info act8846_dcdc_info[] = {
- {
- .name = "act_dcdc1", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- .suspend_vol = 1200000,
- },
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 1200000,
- #else
- .suspend_vol = 900000,
- #endif
-
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 1200000,
- #else
- .suspend_vol = 900000,
- #endif
-
- },
- {
- .name = "act_dcdc4", //vccio
- .min_uv = 3000000,
- .max_uv = 3000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 3000000,
- #else
- .suspend_vol = 2800000,
- #endif
-
- },
-
-};
-static struct pmu_info act8846_ldo_info[] = {
- {
- .name = "act_ldo1", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "act_ldo2", //vdd12
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "act_ldo3", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo4", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo5", //vcctp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo6", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo7", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo8", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- };
-
-#include "../mach-rk30/board-pmu-act8846.c"
-#endif
-
-#ifdef CONFIG_MFD_RK808
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-#define RK808_HOST_IRQ RK30_PIN0_PB3
-
-static struct pmu_info rk808_dcdc_info[] = {
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 900000,
- },
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 900000,
- },
- {
- .name = "rk_dcdc3", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- .suspend_vol = 1200000,
- },
- {
- .name = "rk_dcdc4", //vccio
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3000000,
- },
-
-};
-static struct pmu_info rk808_ldo_info[] = {
- {
- .name = "rk_ldo1", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "rk_ldo2", //vcctp
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
-
- },
- {
- .name = "rk_ldo3", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 1000000,
- },
- {
- .name = "rk_ldo4", //vcc18
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "rk_ldo5", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- .suspend_vol = 2800000,
- },
- {
- .name = "rk_ldo6", //vdd12
- .min_uv = 1200000,
- .max_uv = 1200000,
- .suspend_vol = 1200000,
- },
- {
- .name = "rk_ldo7", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "rk_ldo8", //vcca_33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- };
-
-#include "board-pmu-rk808.c"
-#endif
-
-
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_MFD_WM831X_I2C)
- {
- .type = "wm8326",
- .addr = 0x34,
- .flags = 0,
- .irq = RK30_PIN0_PB3,
- .platform_data = &wm831x_platdata,
- },
-#endif
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-
-#if defined (CONFIG_REGULATOR_ACT8846)
- {
- .type = "act8846",
- .addr = 0x5a,
- .flags = 0,
- // .irq = ACT8846_HOST_IRQ,
- .platform_data=&act8846_data,
- },
-#endif
-#if defined (CONFIG_MFD_RK808)
- {
- .type = "rk808",
- .addr = 0x1b,
- .flags = 0,
- // .irq = ACT8846_HOST_IRQ,
- .platform_data=&rk808_data,
- },
-#endif
-
-#if defined (CONFIG_RTC_HYM8563)
- {
- .type = "rtc_hym8563",
- .addr = 0x51,
- .flags = 0,
- .irq = RK30_PIN1_PA4,
- },
-#endif
-
-};
-#endif
-
-void __sramfunc board_pmu_suspend(void)
-{
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_suspend();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_suspend();
- #endif
- #if defined (CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- board_pmu_act8846_suspend();
- #endif
- #if defined (CONFIG_MFD_RK808)
- if(pmic_is_rk808())
- board_pmu_rk808_suspend();
- #endif
-
-}
-
-void __sramfunc board_pmu_resume(void)
-{
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_resume();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_resume();
- #endif
- #if defined (CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- board_pmu_act8846_resume();
- #endif
- #if defined (CONFIG_MFD_RK808)
- if(pmic_is_rk808())
- board_pmu_rk808_resume();
- #endif
-
-}
-
- int __sramdata gpio3d6_iomux,gpio3d6_do,gpio3d6_dir,gpio3d6_en;
-
-#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
-
-void __sramfunc rk30_pwm_logic_suspend_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
-
-// int gpio0d7_iomux,gpio0d7_do,gpio0d7_dir,gpio0d7_en;
- sram_udelay(10000);
- gpio3d6_iomux = grf_readl(GRF_GPIO3D_IOMUX);
- gpio3d6_do = grf_readl(GRF_GPIO3H_DO);
- gpio3d6_dir = grf_readl(GRF_GPIO3H_DIR);
- gpio3d6_en = grf_readl(GRF_GPIO3H_EN);
-
- grf_writel((1<<28), GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DIR);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DO);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_EN);
-#endif
-}
-void __sramfunc rk30_pwm_logic_resume_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- grf_writel((1<<28)|gpio3d6_iomux, GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|gpio3d6_en, GRF_GPIO3H_EN);
- grf_writel((1<<30)|gpio3d6_dir, GRF_GPIO3H_DIR);
- grf_writel((1<<30)|gpio3d6_do, GRF_GPIO3H_DO);
- sram_udelay(10000);
-
-#endif
-
-}
-extern void pwm_suspend_voltage(void);
-extern void pwm_resume_voltage(void);
-void rk30_pwm_suspend_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_suspend_voltage();
-#endif
-}
-void rk30_pwm_resume_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_resume_voltage();
-#endif
-}
-
-
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-#if defined (CONFIG_LS_CM3217)
- {
- .type = "lightsensor",
- .addr = 0x10,
- .flags = 0,
- .platform_data = &cm3217_info,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C4_RK30
-static struct i2c_board_info __initdata i2c4_info[] = {
-
-};
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO// RK30_PIN2_PD6 //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO//RK30_PIN2_PD7 //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- //set iomux (gpio) here
- //rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME, GPIO2D_GPIO2D7);
- //rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME, GPIO2D_GPIO2D6);
-
- return 0;
-}
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C4_RK30
- i2c_register_board_info(4, i2c4_info, ARRAY_SIZE(i2c4_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(5, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-
-//#define POWER_ON_PIN RK30_PIN0_PA0 //power_hold
-static void rk30_pm_power_off(void)
-{
- printk(KERN_ERR "rk30_pm_power_off start...\n");
- #if defined(CONFIG_MFD_WM831X)
- if(pmic_is_wm8326()){
- wm831x_set_bits(Wm831x,WM831X_GPIO_LEVEL,0x0001,0x0000); //set sys_pwr 0
- wm831x_device_shutdown(Wm831x);//wm8326 shutdown
- }
- #endif
-
- #if defined(CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- {
- act8846_device_shutdown();
- }
- #endif
-
- #if defined(CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- {
- tps65910_device_shutdown();//tps65910 shutdown
- }
- #endif
-
- #if defined(CONFIG_MFD_RK808)
- if(pmic_is_rk808())
- {
- rk808_device_shutdown();//rk808 shutdown
- }
- #endif
-
- //gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
- port_output_off(pwr_on);
- while (1);
-}
-
-
-static int __init tp_board_init(void)
-{
- struct port_config irq_port;
- struct port_config rst_port;
- int ret = check_tp_param();
-
- if(ret < 0)
- return ret;
-
- irq_port = get_port_config(tp_irq);
- rst_port = get_port_config(tp_rst);
-#if defined (CONFIG_TOUCHSCREEN_GSLX680_RK3168)
- if(tp_type == TP_TYPE_GSLX680){
- gslx680_data.irq_pin = irq_port.gpio;
- gslx680_info.addr = tp_addr;
- gslx680_data.reset_pin= rst_port.gpio;
- gslx680_data.x_max=tp_xmax;
- gslx680_data.y_max=tp_ymax;
- gslx680_data.firmVer=tp_firmVer;
- i2c_register_board_info(tp_i2c, &gslx680_info, 1);
- }
-#endif
-
-#if defined (CONFIG_TOUCHSCREEN_86V_GT811_IIC)
- if(tp_type == TP_TYPE_GT811_86V){
- gt811_data.irq_pin = irq_port.gpio;
- gt811_info.addr = tp_addr;
- gt811_data.reset_pin= rst_port.gpio;
- gt811_data.x_max=tp_xmax;
- gt811_data.y_max=tp_ymax;
- i2c_register_board_info(tp_i2c, >811_info, 1);
- }
-#endif
-
-#if defined(CONFIG_TOUCHSCREEN_GT8XX)
- if(tp_type == TP_TYPE_GT8XX){
- goodix_data.irq_pin = irq_port.gpio;
- goodix_info.addr = tp_addr;
- goodix_data.reset_pin= rst_port.gpio;
- goodix_data.x_max=tp_xmax;
- goodix_data.y_max=tp_ymax;
- i2c_register_board_info(tp_i2c, &goodix_info, 1);
- }
-#endif
- return 0;
-}
-
-
-static int __init codec_board_init(void)
-{
- struct port_config spk_port;
- struct port_config hp_port;
- int ret = check_codec_param();
-
- if(ret < 0)
- return ret;
-
- spk_port = get_port_config(spk_ctl);
- hp_port = get_port_config(hp_det);
-
-#if defined (CONFIG_SND_RK29_SOC_RT5631)
- if(codec_type == CODEC_TYPE_RT5631){
- rt5631_data.spk_pin = spk_port.gpio;
- rt5631_info.addr = codec_addr;
- rt5631_data.hp_pin= hp_port.gpio;
- i2c_register_board_info(codec_i2c, &rt5631_info, 1);
- }
-#endif
-
-#if defined (CONFIG_SND_RK29_SOC_ES8323)
- if(codec_type == CODEC_TYPE_ES8323){
- es8323_data.spk_pin = spk_port.gpio;
- es8323_info.addr = codec_addr;
- es8323_data.hp_pin= hp_port.gpio;
- i2c_register_board_info(codec_i2c, &es8323_info, 1);
- }
-#endif
-
-#if defined (CONFIG_MFD_RK616)
-if(codec_type == CODEC_TYPE_RK616){
- rk616_pdata.spk_ctl_gpio = spk_port.gpio;
- rk616_info.addr = codec_addr;
- rk616_pdata.hdmi_irq= get_port_config(codec_hdmi_irq).gpio;
- i2c_register_board_info(codec_i2c, &rk616_info, 1);
- }
-#endif
- return 0;
-}
-
-static int __init chg_board_init(void)
-{
- int ret = check_chg_param();
- if(ret < 0)
- return ret;
-#ifdef CONFIG_BATTERY_RK30_ADC_FAC
- //rk30_adc_battery_platdata.adc_channel = chg_adc;
- if(dc_det != -1){
- rk30_adc_battery_platdata.dc_det_pin = get_port_config(dc_det).gpio;
- printk("rk30_adc_battery_platdata.dc_det_pin %d %d",rk30_adc_battery_platdata.dc_det_pin,RK30_PIN0_PB2);
- rk30_adc_battery_platdata.dc_det_level = !get_port_config(dc_det).io.active_low;
- }
- else{
- rk30_adc_battery_platdata.dc_det_pin=INVALID_GPIO;
- }
- if(bat_low != -1){
- rk30_adc_battery_platdata.batt_low_pin = get_port_config(bat_low).gpio;
- rk30_adc_battery_platdata.batt_low_level = !get_port_config(bat_low).io.active_low;
- }
- else{
- rk30_adc_battery_platdata.batt_low_pin=INVALID_GPIO;
- }
- if(chg_ok != -1){
- rk30_adc_battery_platdata.charge_ok_pin = get_port_config(chg_ok).gpio;
- rk30_adc_battery_platdata.charge_ok_level = !get_port_config(chg_ok).io.active_low;
- }
- else{
- rk30_adc_battery_platdata.charge_ok_pin=INVALID_GPIO;
- }
- if(chg_set != -1){
- rk30_adc_battery_platdata.charge_set_pin = get_port_config(chg_set).gpio;
- rk30_adc_battery_platdata.charge_set_level = !get_port_config(chg_set).io.active_low;
- }
- else{
- rk30_adc_battery_platdata.charge_set_pin=INVALID_GPIO;
- }
- if(usb_det!= -1){
- rk30_adc_battery_platdata.usb_det_pin = get_port_config(chg_set).gpio;
- rk30_adc_battery_platdata.usb_det_level = !get_port_config(chg_set).io.active_low;
- }
- else{
- rk30_adc_battery_platdata.usb_det_pin=INVALID_GPIO;
- }
-
- if(ref_vol!= -1){
- rk30_adc_battery_platdata.reference_voltage=ref_vol;
- }
-
- if(up_res!= -1){
- rk30_adc_battery_platdata.pull_up_res=up_res;
- }
- if(down_res!= -1){
- rk30_adc_battery_platdata.pull_down_res=down_res;
- }
- if(root_chg!= -1){
- rk30_adc_battery_platdata.is_reboot_charging=root_chg;
- }
- if(save_cap!= -1){
- rk30_adc_battery_platdata.save_capacity=save_cap;
- }
- if(low_vol!= -1){
- rk30_adc_battery_platdata.low_voltage_protection=low_vol;
- }
-
- for(i=0;i<11;i++)
- {
- rk30_adc_battery_platdata.chargeArray[i]=bat_charge[i];
- rk30_adc_battery_platdata.dischargeArray[i]=bat_discharge[i];
- }
-#endif
- return 0;
-}
-
-static int __init gs_board_init(void)
-{
- int i;
- struct port_config port;
- int ret = check_gs_param();
- if(ret < 0)
- return ret;
- port = get_port_config(gs_irq);
-//mma7660
-#if defined (CONFIG_GS_MMA7660)
- if(gs_type == GS_TYPE_MMA7660){
-
- mma7660_info.irq = port.gpio;
- mma7660_info.addr = gs_addr;
- for(i = 0; i < 9; i++)
- mma7660_data.orientation[i] = gs_orig[i];
- i2c_register_board_info(gs_i2c, &mma7660_info, 1);
- }
-#endif
-
-#if defined (CONFIG_GS_LIS3DH)
- if(gs_type == GS_TYPE_LIS3DH){
- lis3dh_info.irq = port.gpio;
- lis3dh_info.addr = gs_addr;
- for(i = 0; i < 9; i++)
- lis3dh_data.orientation[i] = gs_orig[i];
- i2c_register_board_info(gs_i2c, &lis3dh_info, 1);
- }
-#endif
-
-#if defined (CONFIG_GS_MXC6225)
- if(gs_type == GS_TYPE_MXC6225){
- mxc6225_info.irq = port.gpio;
- mxc6225_info.addr = gs_addr;
- for(i = 0; i < 9; i++)
- mxc6225_data.orientation[i] = gs_orig[i];
- i2c_register_board_info(gs_i2c, &mxc6225_info, 1);
- }
-#endif
-
-#if defined (CONFIG_GS_DMT10)
- if(gs_type == GS_TYPE_DMARAD10){
- dmt10_info.irq = port.gpio;
- dmt10_info.addr = gs_addr;
- for(i = 0; i < 9; i++)
- dmt10_data.orientation[i] = gs_orig[i];
- i2c_register_board_info(gs_i2c, &dmt10_info, 1);
- }
-#endif
-
-#if defined (CONFIG_GS_MMA8452)
- if(gs_type == GS_TYPE_MMA8452){
- mma8452_info.irq = port.gpio;
- mma8452_info.addr = gs_addr;
- for(i = 0; i < 9; i++)
- mma8452_data.orientation[i] = gs_orig[i];
- i2c_register_board_info(gs_i2c, &mma8452_info, 1);
- }
-#endif
-
-#if defined (CONFIG_GS_LSM303D)
- if(gs_type == GS_TYPE_LSM303D){
- lms303d_info.irq = port.gpio;
- lms303d_info.addr = gs_addr;
- for(i = 0; i < 9; i++)
- lms303d_data.orientation[i] = gs_orig[i];
- i2c_register_board_info(gs_i2c, &lms303d_info, 1);
- }
-#endif
-
-
- return 0;
-}
-
-static int __init bl_board_init(void){
- int ret = check_bl_param();
- if(ret < 0)
- return ret;
-
- switch(bl_pwmid)
- {
- case 0:
- bl_pwm_mode = PWM0;
- break;
- case 1:
- bl_pwm_mode = PWM1;
- break;
- case 2:
- bl_pwm_mode = PWM2;
- break;
- case 3:
- bl_pwm_mode = PWM3;
- break;
- }
-
- rk29_bl_info.pwm_id = bl_pwmid;
- rk29_bl_info.brightness_mode=bl_mode;
- rk29_bl_info.pre_div=bl_div;
- rk29_bl_info.bl_ref = bl_ref;
- rk29_bl_info.min_brightness=bl_min;
- rk29_bl_info.max_brightness=bl_max;
-
-
- return 0;
-}
-
-static int __init lcd_board_init(void)
-{
- return check_lcd_param();
-}
-
-static int __init key_board_init(void){
- int i;
- struct port_config port;
- for(i = 0; i < key_val_size; i++){
- if(key_val[i] & (1<<31)){
- key_button[i].adc_value = key_val[i] & 0xffff;
- key_button[i].gpio = INVALID_GPIO;
- }else{
- port = get_port_config(key_val[i]);
- key_button[i].gpio = port.gpio;
- key_button[i].active_low = port.io.active_low;
- }
- }
- rk29_keys_pdata.nbuttons = key_val_size;
- rk29_keys_pdata.chn = key_adc;
- return 0;
-}
-
-static int __init wifi_board_init(void)
-{
- return check_wifi_param();
-}
-
-
-static int __init rk_config_init(void)
-{
- int ret = 0;
- ret = lcd_board_init();
- if(ret < 0)
- INIT_ERR("lcd");
-
- ret = bl_board_init();
- if(ret < 0)
- INIT_ERR("backlight");
-
- ret = tp_board_init();
- if(ret < 0)
- INIT_ERR("tp");
-
- ret = gs_board_init();
- if(ret < 0)
- INIT_ERR("gsensor");
-
- ret = codec_board_init();
- if(ret < 0)
- INIT_ERR("codec");
-
- ret = key_board_init();
- if(ret < 0)
- INIT_ERR("key");
-
- ret = chg_board_init();
- if(ret < 0)
- INIT_ERR("charge");
-
- ret = wifi_board_init();
- if(ret < 0)
- INIT_ERR("wifi");
-
- return 0;
-}
-
-static void __init machine_rk30_board_init(void)
-{
- //avs_init();
- rk_power_on();
- rk_config_init();
- pm_power_off = rk30_pm_power_off;
-
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- rk_platform_add_display_devices();
- board_usb_detect_init(RK30_PIN0_PA7);
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC)
- rk29sdk_wifi_bt_gpio_control_init();
-#elif defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- rk29sdk_wifi_combo_module_gpio_init();
-#endif
-
-#if defined(CONFIG_MT6620)
- clk_set_rate(clk_get_sys("rk_serial.0", "uart"), 48*1000000);
-#endif
-
-#if defined(CONFIG_MT5931_MT6622)
- clk_set_rate(clk_get_sys("rk_serial.0", "uart"), 24*1000000);
-#endif
-}
-#define HD_SCREEN_SIZE 1920UL*1200UL*4*3
-static void __init rk30_reserve(void)
-{
- size_t fbsize=get_fb_size();
-#if defined(CONFIG_ARCH_RK3188)
- /*if lcd resolution great than or equal to 1920*1200,reserve the ump memory */
- if(!(fbsize < ALIGN(HD_SCREEN_SIZE,SZ_1M)))
- {
- int ump_mem_phy_size=512UL*1024UL*1024UL;
- resource_mali[0].start = board_mem_reserve_add("ump buf", ump_mem_phy_size);
- resource_mali[0].end = resource_mali[0].start + ump_mem_phy_size -1;
- }
-#endif
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0 buf", fbsize);
- resource_fb[0].end = resource_fb[0].start + fbsize- 1;
-#if 0
- resource_fb[1].start = board_mem_reserve_add("ipp buf", RK30_FB0_MEM_SIZE);
- resource_fb[1].end = resource_fb[1].start + RK30_FB0_MEM_SIZE - 1;
-#endif
-
-#if defined(CONFIG_FB_ROTATE) || !defined(CONFIG_THREE_FB_BUFFER)
- resource_fb[2].start = board_mem_reserve_add("fb2 buf",fbsize);
- resource_fb[2].end = resource_fb[2].start + fbsize - 1;
-#endif
-#endif
-
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
-
-#ifdef CONFIG_GPS_RK
- //it must be more than 8MB
- rk_gps_info.u32MemoryPhyAddr = board_mem_reserve_add("gps", SZ_8M);
-#endif
- board_mem_reserved();
-}
-/******************************** arm dvfs frequency volt table **********************************/
-/**
- * dvfs_cpu_logic_table: table for arm and logic dvfs
- * @frequency : arm frequency
- * @cpu_volt : arm voltage depend on frequency
- */
-
-#if defined(CONFIG_ARCH_RK3188)
-//sdk
-static struct cpufreq_frequency_table dvfs_arm_table_volt_level0[] = {
- {.frequency = 312 * 1000, .index = 850 * 1000},
- {.frequency = 504 * 1000, .index = 900 * 1000},
- {.frequency = 816 * 1000, .index = 950 * 1000},
- {.frequency = 1008 * 1000, .index = 1025 * 1000},
- {.frequency = 1200 * 1000, .index = 1100 * 1000},
- {.frequency = 1416 * 1000, .index = 1200 * 1000},
- {.frequency = 1608 * 1000, .index = 1300 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-//default
-static struct cpufreq_frequency_table dvfs_arm_table_volt_level1[] = {
- {.frequency = 312 * 1000, .index = 875 * 1000},
- {.frequency = 504 * 1000, .index = 925 * 1000},
- {.frequency = 816 * 1000, .index = 975 * 1000},
- {.frequency = 1008 * 1000, .index = 1075 * 1000},
- {.frequency = 1200 * 1000, .index = 1150 * 1000},
- {.frequency = 1416 * 1000, .index = 1250 * 1000},
- {.frequency = 1608 * 1000, .index = 1350 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-// cube 10'
-static struct cpufreq_frequency_table dvfs_arm_table_volt_level2[] = {
- {.frequency = 312 * 1000, .index = 900 * 1000},
- {.frequency = 504 * 1000, .index = 925 * 1000},
- {.frequency = 816 * 1000, .index = 1000 * 1000},
- {.frequency = 1008 * 1000, .index = 1075 * 1000},
- {.frequency = 1200 * 1000, .index = 1200 * 1000},
- {.frequency = 1416 * 1000, .index = 1250 * 1000},
- {.frequency = 1608 * 1000, .index = 1350 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-/******************************** gpu dvfs frequency volt table **********************************/
-//sdk
-static struct cpufreq_frequency_table dvfs_gpu_table_volt_level0[] = {
- {.frequency = 133 * 1000, .index = 975 * 1000},//the mininum rate is limited 133M for rk3188
- {.frequency = 200 * 1000, .index = 975 * 1000},
- {.frequency = 266 * 1000, .index = 1000 * 1000},
- {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1100 * 1000},
- {.frequency = 600 * 1000, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-//cube 10'
-static struct cpufreq_frequency_table dvfs_gpu_table_volt_level1[] = {
- {.frequency = 133 * 1000, .index = 975 * 1000},//the mininum rate is limited 133M for rk3188
- {.frequency = 200 * 1000, .index = 1000 * 1000},
- {.frequency = 266 * 1000, .index = 1025 * 1000},
- {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1100 * 1000},
- {.frequency = 600 * 1000, .index = 1250 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-/******************************** ddr dvfs frequency volt table **********************************/
-static struct cpufreq_frequency_table dvfs_ddr_table_volt_level0[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 950 * 1000},
- {.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = 1000 * 1000},
- {.frequency = 396 * 1000 + DDR_FREQ_NORMAL, .index = 1100 * 1000},
- {.frequency = 460 * 1000 + DDR_FREQ_DUALVIEW, .index = 1150 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-//if you board is good for volt quality,select dvfs_arm_table_volt_level0
-#define dvfs_arm_table dvfs_arm_table_volt_level1
-#define dvfs_gpu_table dvfs_gpu_table_volt_level1
-#define dvfs_ddr_table dvfs_ddr_table_volt_level0
-
-#else
-//for RK3168 && RK3066B
-static struct cpufreq_frequency_table dvfs_arm_table[] = {
- {.frequency = 312 * 1000, .index = 950 * 1000},
- {.frequency = 504 * 1000, .index = 1000 * 1000},
- {.frequency = 816 * 1000, .index = 1050 * 1000},
- {.frequency = 1008 * 1000, .index = 1125 * 1000},
- {.frequency = 1200 * 1000, .index = 1200 * 1000},
- //{.frequency = 1416 * 1000, .index = 1250 * 1000},
- //{.frequency = 1608 * 1000, .index = 1300 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- {.frequency = 100 * 1000, .index = 1000 * 1000},
- {.frequency = 200 * 1000, .index = 1000 * 1000},
- {.frequency = 266 * 1000, .index = 1050 * 1000},
- //{.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1125 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 1000 * 1000},
- {.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = 1050 * 1000},
- {.frequency = 400 * 1000 + DDR_FREQ_NORMAL, .index = 1100 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-#endif
-/******************************** arm dvfs frequency volt table end **********************************/
-//#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
-//static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
-//static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
-
-void __init board_clock_init(void)
-{
- rk30_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
- //dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "cpu"), dvfs_arm_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
-}
-
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk30_fixup,
- .reserve = &rk30_reserve,
- .map_io = rk30_map_io,
- .init_irq = rk30_init_irq,
- .timer = &rk30_timer,
- .init_machine = machine_rk30_board_init,
-MACHINE_END
+++ /dev/null
-/*
- * Copyright (C) 2013 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <linux/fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-
-#include <asm/cacheflush.h>
-#include <asm/fiq_glue.h>
-#include <asm/smp_scu.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <mach/ddr.h>
-#include <mach/fiq.h>
-
-
-#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Macro Define Begin ------------------------*/
-/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
-#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_OV5642 /* back camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_0 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 4
-#define CONFIG_SENSOR_ORIENTATION_0 90
-#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000
-
-#define CONFIG_SENSOR_01 RK29_CAM_SENSOR_OV5642 /* back camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_01 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 4
-#define CONFIG_SENSOR_ORIENTATION_01 90
-#define CONFIG_SENSOR_POWER_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_01 30000
-
-#define CONFIG_SENSOR_02 RK29_CAM_SENSOR_OV5640 /* back camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_02 0x00
-#define CONFIG_SENSOR_CIF_INDEX_02 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 4
-#define CONFIG_SENSOR_ORIENTATION_02 90
-#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000
-
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_OV2659 /* front camera sensor 0 */
-#define CONFIG_SENSOR_IIC_ADDR_1 0x60
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 1
-#define CONFIG_SENSOR_ORIENTATION_1 270
-#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000
-
-#define CONFIG_SENSOR_11 RK29_CAM_SENSOR_OV2659 /* front camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_11 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 3
-#define CONFIG_SENSOR_ORIENTATION_11 270
-#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_11 30000
-
-#define CONFIG_SENSOR_12 RK29_CAM_SENSOR_OV2659//RK29_CAM_SENSOR_OV2655 /* front camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_12 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 3
-#define CONFIG_SENSOR_ORIENTATION_12 270
-#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_12 30000
-
-
-#endif //#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk30_camera.c"
-/*---------------- Camera Sensor Macro Define End ---------*/
-
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#define CONFIG_SENSOR_POWER_IOCTL_USR 0 //define this refer to your board layout
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
-
-static void rk_cif_power(int on)
-{
- struct regulator *ldo_18,*ldo_28;
-
- ldo_28 = regulator_get(NULL, "ldo7"); // vcc28_cif
- ldo_18 = regulator_get(NULL, "ldo1"); // vcc18_cif
- if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)) {
- printk("get cif ldo failed!\n");
- return;
- }
- if(on == 0) {
- regulator_disable(ldo_28);
- regulator_put(ldo_28);
- regulator_disable(ldo_18);
- regulator_put(ldo_18);
- mdelay(500);
- } else {
- regulator_set_voltage(ldo_28, 2800000, 2800000);
- regulator_enable(ldo_28);
- // printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
- regulator_put(ldo_28);
-
- regulator_set_voltage(ldo_18, 1800000, 1800000);
- // regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(ldo_18);
- // printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
- regulator_put(ldo_18);
- }
-}
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- //#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
- rk_cif_power(on);
-}
-#endif
-
-#if CONFIG_SENSOR_RESET_IOCTL_USR
-static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
-static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-
-#if CONFIG_SENSOR_IIC_ADDR_0
-static struct reginfo_t rk_init_data_sensor_reg_0[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_0[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-
-#if CONFIG_SENSOR_IIC_ADDR_1
-static struct reginfo_t rk_init_data_sensor_reg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_01
-static struct reginfo_t rk_init_data_sensor_reg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_02
-static struct reginfo_t rk_init_data_sensor_reg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_11
-static struct reginfo_t rk_init_data_sensor_reg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_12
-static struct reginfo_t rk_init_data_sensor_reg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] =
-{
- #if CONFIG_SENSOR_IIC_ADDR_0
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_0,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_1
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_1,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_01
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_01,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_02
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_02,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_11
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_11,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_12
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_12,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
-
- };
-#include "../../../drivers/media/video/rk30_camera.c"
-
-#endif /* CONFIG_VIDEO_RK29 */
-
-#ifdef CONFIG_FB_ROCKCHIP
-
-#define RK_FB_MEM_SIZE 3*SZ_1M
-
-#define LCD_CS_PIN INVALID_GPIO
-#define LCD_CS_VALUE GPIO_HIGH
-
-#define LCD_EN_PIN INVALID_GPIO
-#define LCD_EN_VALUE GPIO_LOW
-
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
-
- if(LCD_CS_PIN != INVALID_GPIO)
- {
- ret = gpio_request(LCD_CS_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_CS_PIN);
- printk(KERN_ERR "request lcd cs pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_CS_PIN, LCD_CS_VALUE);
- }
- }
-
- if(LCD_EN_PIN != INVALID_GPIO)
- {
- ret = gpio_request(LCD_EN_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_EN_PIN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_EN_PIN, LCD_EN_VALUE);
- }
- }
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
- if(LCD_CS_PIN != INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, !LCD_CS_VALUE);
- }
-
- if(LCD_EN_PIN != INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, !LCD_EN_VALUE);
- }
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- if(LCD_CS_PIN != INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE);
- }
-
- if(LCD_EN_PIN != INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
- }
- return 0;
-}
-
-struct rk29fb_info lcdc0_screen_info = {
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-};
-
-struct rk29fb_info lcdc1_screen_info = {
- .prop = EXTEND, //extend display device
- .lcd_info = NULL,
- .set_screen_info = NULL,
-};
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-
-#if defined(CONFIG_LCDC0_RK3188)
-static struct resource resource_lcdc0[] = {
- [0] = {
- .name = "lcdc0 reg",
- .start = RK30_LCDC0_PHYS,
- .end = RK30_LCDC0_PHYS + RK30_LCDC0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc0 irq",
- .start = IRQ_LCDC0,
- .end = IRQ_LCDC0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc0 = {
- .name = "rk3188-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc0),
- .resource = resource_lcdc0,
- .dev = {
- .platform_data = &lcdc0_screen_info,
- },
-};
-#endif
-#if defined(CONFIG_LCDC1_RK3188)
-extern struct rk29fb_info lcdc1_screen_info;
-static struct resource resource_lcdc1[] = {
- [0] = {
- .name = "lcdc1 reg",
- .start = RK30_LCDC1_PHYS,
- .end = RK30_LCDC1_PHYS + RK30_LCDC1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc1 irq",
- .start = IRQ_LCDC1,
- .end = IRQ_LCDC1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc1 = {
- .name = "rk3188-lcdc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resource_lcdc1),
- .resource = resource_lcdc1,
- .dev = {
- .platform_data = &lcdc1_screen_info,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-};
-
-static struct i2c_board_info __initdata i2c1_info[] = {
-};
-
-static struct i2c_board_info __initdata i2c2_info[] = {
-};
-
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-
-static void __init rk30_i2c_register_board_info(void)
-{
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-}
-//end of i2c
-
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#define PWM_ID 1
-#define PWM_MUX_NAME GPIO0A3_PWM0_NAME
-#define PWM_MUX_MODE GPIO0A_PWM0
-#define PWM_MUX_MODE_GPIO GPIO0A_GPIO0A3
-#define PWM_GPIO RK30_PIN0_PA3
-#define PWM_EFFECT_VALUE 1
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-
-#define BL_EN_PIN RK30_PIN6_PB3
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0;
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret = 0;
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-/***********************************************************
-* rk30 ion device
-************************************************************/
-#define ION_RESERVE_SIZE (8 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_FB_ROCKCHIP
- &device_fb,
-#endif
-#if defined(CONFIG_LCDC0_RK3188)
- &device_lcdc0,
-#endif
-#if defined(CONFIG_LCDC1_RK3188)
- &device_lcdc1,
-#endif
-
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- &rk29_device_backlight,
-#endif
- &device_ion,
-};
-
-static void __init fpga_board_init(void)
-{
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
-}
-
-static void __init fpga_reserve(void)
-{
-#if defined(CONFIG_FB_ROCKCHIP)
- resource_fb[0].start = board_mem_reserve_add("fb0", RK_FB_MEM_SIZE);
- resource_fb[0].end = resource_fb[0].start + RK_FB_MEM_SIZE - 1;
-#endif
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
- board_mem_reserved();
-}
-
-#include <plat/key.h>
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "menu",
- .code = EV_MENU,
- .gpio = RK30_PIN3_PB2,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .gpio = RK30_PIN3_PB1,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .gpio = RK30_PIN3_PB0,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .gpio = RK30_PIN3_PB3,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .gpio = RK30_PIN3_PB4,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "key6",
- .code = KEY_CAMERA,
- .gpio = RK30_PIN3_PB5,
- .active_low = PRESS_LEV_LOW,
- },
-};
-
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = -1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
-static void __init fpga_fixup(struct machine_desc *desc, struct tag *tags,
- char **cmdline, struct meminfo *mi)
-{
- mi->nr_banks = 1;
- mi->bank[0].start = PLAT_PHYS_OFFSET;
- mi->bank[0].size = ddr_get_cap();
-}
-
-static void __init fpga_map_io(void)
-{
- rk30_map_common_io();
- rk29_setup_early_printk();
- rk29_sram_init();
- board_clock_init();
-}
-
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = fpga_fixup,
- .reserve = &fpga_reserve,
- .map_io = fpga_map_io,
- .init_irq = rk30_init_irq,
- .timer = &rk30_timer,
- .init_machine = fpga_board_init,
-MACHINE_END
-
-#include <mach/system.h>
-static void fpga_reset(char mode, const char *cmd)
-{
- sram_printascii("\nfpga reset\n");
- while (1);
-}
-void (*arch_reset)(char, const char *) = fpga_reset;
-
-int ddr_init(uint32_t dram_type, uint32_t freq)
-{
- return 0;
-}
-
-uint32_t ddr_get_cap(void)
-{
- return SZ_128M;
-}
-
-struct cpufreq_frequency_table *dvfs_get_freq_volt_table(struct clk *clk)
-{
- return NULL;
-}
-
-#include <linux/clkdev.h>
-
-struct clk {
- const char *name;
- unsigned long rate;
-};
-
-static struct clk xin24m = {
- .name = "xin24m",
- .rate = 24000000,
-};
-
-static struct clk xin12m = {
- .name = "xin12m",
- .rate = 12000000,
-};
-
-#define CLK(dev, con, ck) \
- { \
- .dev_id = dev, \
- .con_id = con, \
- .clk = ck, \
- }
-
-static struct clk_lookup clks[] = {
- CLK("rk30_i2c.0", "i2c", &xin24m),
- CLK("rk30_i2c.1", "i2c", &xin24m),
- CLK("rk30_i2c.2", "i2c", &xin24m),
- CLK("rk30_i2c.3", "i2c", &xin24m),
- CLK("rk30_i2c.4", "i2c", &xin24m),
- CLK("rk29xx_spim.0", "spi", &xin24m),
- CLK("rk29xx_spim.1", "spi", &xin24m),
-
- CLK("rk_serial.0", "uart_div", &xin24m),
- CLK("rk_serial.0", "uart_frac_div", &xin24m),
- CLK("rk_serial.0", "uart", &xin24m),
- CLK("rk_serial.0", "pclk_uart", &xin24m),
- CLK("rk_serial.1", "uart_div", &xin24m),
- CLK("rk_serial.1", "uart_frac_div", &xin24m),
- CLK("rk_serial.1", "uart", &xin24m),
- CLK("rk_serial.1", "pclk_uart", &xin24m),
- CLK("rk_serial.2", "uart_div", &xin24m),
- CLK("rk_serial.2", "uart_frac_div", &xin24m),
- CLK("rk_serial.2", "uart", &xin24m),
- CLK("rk_serial.2", "pclk_uart", &xin24m),
-
- CLK("rk29_i2s.1", "i2s_div", &xin24m),
- CLK("rk29_i2s.1", "i2s_frac_div", &xin24m),
- CLK("rk29_i2s.1", "i2s", &xin12m),
- CLK("rk29_i2s.1", "hclk_i2s", &xin24m),
-
- CLK("rk29_sdmmc.0","mmc",&xin24m),
- CLK("rk29_sdmmc.0","hclk_mmc",&xin24m),
- CLK("rk29_sdmmc.1","mmc",&xin24m),
- CLK("rk29_sdmmc.1","hclk_mmc",&xin24m),
-
- CLK(NULL,"pd_lcdc0",&xin24m),
- CLK(NULL,"hclk_lcdc0",&xin24m),
- CLK(NULL,"aclk_lcdc0",&xin24m),
- CLK(NULL,"dclk_lcdc0",&xin24m),
- CLK(NULL,"pd_lcdc1",&xin24m),
- CLK(NULL,"hclk_lcdc1",&xin24m),
- CLK(NULL,"aclk_lcdc1",&xin24m),
- CLK(NULL,"dclk_lcdc1",&xin24m),
-
- CLK(NULL,"pd_cif0",&xin24m),
- CLK(NULL,"aclk_cif0",&xin24m),
- CLK(NULL,"hclk_cif0",&xin24m),
- CLK(NULL,"cif0_in",&xin24m),
- CLK(NULL,"cif0_out",&xin24m),
-
- CLK(NULL,"pwm01",&xin24m),
-};
-
-static void __init fpga_clock_init(void)
-{
- struct clk_lookup *lk;
-
- for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) {
- clkdev_add(lk);
- }
-}
-
-void __init board_clock_init(void)
-{
- fpga_clock_init();
-}
-
-int __init clk_disable_unused(void)
-{
- return 0;
-}
-
-int clk_enable(struct clk *clk)
-{
- return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
- if (clk)
- return clk->rate;
- else
- return 24000000;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
- return 0;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
- return 0;
-}
-EXPORT_SYMBOL(clk_set_parent);
-
+++ /dev/null
-/*\r
- *\r
- * Copyright (C) 2013 ROCKCHIP, Inc.\r
- *\r
- * This software is licensed under the terms of the GNU General Public\r
- * License version 2, as published by the Free Software Foundation, and\r
- * may be copied, distributed, and modified under those terms.\r
- *\r
- * This program is distributed in the hope that it will be useful,\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- * GNU General Public License for more details.\r
- *\r
- */\r
-\r
-#include <linux/kernel.h>\r
-#include <linux/init.h>\r
-#include <linux/io.h>\r
-#include <linux/delay.h>\r
-#include <linux/clk.h>\r
-\r
-#include <asm/mach-types.h>\r
-#include <asm/mach/arch.h>\r
-\r
-#include <mach/board.h>\r
-#include <mach/gpio.h>\r
-\r
-#define FT\r
-\r
-#ifdef FT\r
-#define CONSOLE_LOGLEVEL 2\r
-#define ARM_PLL_MHZ (552)\r
-#else\r
-#define CONSOLE_LOGLEVEL 9\r
-#define ARM_PLL_MHZ (816)\r
-#endif\r
-\r
-static void __init machine_rk30_board_init(void)\r
-{\r
- console_loglevel = CONSOLE_LOGLEVEL;\r
-}\r
-\r
-#define ft_printk(fmt, arg...) \\r
- printk(KERN_EMERG fmt, ##arg)\r
-unsigned long __init ft_test_init_arm_rate(void);\r
-\r
-void __init board_clock_init(void)\r
-{\r
- rk30_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);\r
- clk_set_rate(clk_get(NULL, "cpu"), ft_test_init_arm_rate());\r
- preset_lpj = loops_per_jiffy;\r
-}\r
-\r
-static void __init ft_fixup(struct machine_desc *desc, struct tag *tags,\r
- char **cmdline, struct meminfo *mi)\r
-{\r
- mi->nr_banks = 1;\r
- mi->bank[0].start = PLAT_PHYS_OFFSET;\r
- mi->bank[0].size = SZ_1G;\r
-}\r
-\r
-MACHINE_START(RK30, "RK30board")\r
- .boot_params = PLAT_PHYS_OFFSET + 0x800,\r
- .fixup = ft_fixup,\r
- .map_io = rk30_map_io,\r
- .init_irq = rk30_init_irq,\r
- .timer = &rk30_timer,\r
- .init_machine = machine_rk30_board_init,\r
-MACHINE_END\r
-\r
+++ /dev/null
-#ifdef CONFIG_VIDEO_RK29
-#include <plat/rk_camera.h>
-#include "../../../drivers/spi/rk29_spim.h"
-#include <linux/spi/spi.h>
-#include <linux/dma-mapping.h>
-#include <linux/interrupt.h>
-#include <linux/highmem.h>
-#include <linux/delay.h>
-#include <linux/slab.h>
-#include <linux/platform_device.h>
-#include <linux/clk.h>
-#include <linux/cpufreq.h>
-#include <mach/gpio.h>
-#include <mach/irqs.h>
-#include <linux/miscdevice.h>
-#include <asm/dma.h>
-#include <linux/preempt.h>
-#include <mach/board.h>
-#include <linux/miscdevice.h>
-
-struct spi_device* g_icatch_spi_dev = NULL;
-
-
-static struct rk29xx_spi_chip spi_icatch = {
- //.poll_mode = 1,
- .enable_dma = 0,
-};
-//user must define this struct according to hardware config
-static struct spi_board_info board_spi_icatch_devices[] = {
- {
- .modalias = "spi_icatch",
- .bus_num = 0, //0 or 1
- .max_speed_hz = 24*1000*1000,
- .chip_select = 0,
- .mode = SPI_MODE_0,
- .controller_data = &spi_icatch,
- },
-
-};
-
-
-static int __devinit spi_icatch_probe(struct spi_device *spi)
-{
- struct spi_test_data *spi_test_data;
- int ret = 0;
-
- spi->bits_per_word = 8;
- spi->mode = SPI_MODE_0;
- ret = spi_setup(spi);
- if (ret < 0){
- dev_err(spi, "ERR: fail to setup spi\n");
- return -1;
- }
-
- g_icatch_spi_dev = spi;
-
- printk("%s:bus_num=%d,ok\n",__func__,spi->master->bus_num);
-
- return ret;
-
-}
-
-
-static struct spi_driver spi_icatch_driver = {
- .driver = {
- .name = "spi_icatch",
- .bus = &spi_bus_type,
- .owner = THIS_MODULE,
- },
-
- .probe = spi_icatch_probe,
-};
-
-static struct miscdevice spi_test_icatch = {
- .minor = MISC_DYNAMIC_MINOR,
- .name = "spi_misc_icatch",
-};
-
-static int __init spi_icatch_init(void)
-{
- spi_register_board_info(board_spi_icatch_devices, ARRAY_SIZE(board_spi_icatch_devices));
-
- misc_register(&spi_test_icatch);
- return spi_register_driver(&spi_icatch_driver);
-}
-
-static void __exit spi_icatch_exit(void)
-{
-
- misc_deregister(&spi_test_icatch);
- return spi_unregister_driver(&spi_icatch_driver);
-}
-
-module_init(spi_icatch_init);
-module_exit(spi_icatch_exit);
-
-/* Notes:
-
-Simple camera device registration:
-
- new_camera_device(sensor_name,\ // sensor name, it is equal to CONFIG_SENSOR_X
- face,\ // sensor face information, it can be back or front
- pwdn_io,\ // power down gpio configuration, it is equal to CONFIG_SENSOR_POWERDN_PIN_XX
- flash_attach,\ // sensor is attach flash or not
- mir,\ // sensor image mirror and flip control information
- i2c_chl,\ // i2c channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_IIC_ADAPTER_ID_X
- cif_chl) \ // cif channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_CIF_INDEX_X
-
-Comprehensive camera device registration:
-
- new_camera_device_ex(sensor_name,\
- face,\
- ori,\ // sensor orientation, it is equal to CONFIG_SENSOR_ORIENTATION_X
- pwr_io,\ // sensor power gpio configuration, it is equal to CONFIG_SENSOR_POWER_PIN_XX
- pwr_active,\ // sensor power active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- rst_io,\ // sensor reset gpio configuration, it is equal to CONFIG_SENSOR_RESET_PIN_XX
- rst_active,\ // sensor reset active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- pwdn_io,\
- pwdn_active,\ // sensor power down active level, is equal to CONFIG_SENSOR_POWERDNACTIVE_LEVEL_X
- flash_attach,\
- res,\ // sensor resolution, this is real resolution or resoltuion after interpolate
- mir,\
- i2c_chl,\
- i2c_spd,\ // i2c speed , 100000 = 100KHz
- i2c_addr,\ // the i2c slave device address for sensor
- cif_chl,\
- mclk)\ // sensor input clock rate, 24 or 48
-
-*/
-static struct rkcamera_platform_data new_camera[] = {
- new_camera_device_ex(RK29_CAM_ISP_ICATCH7002_OV5693,
- back,
- 180, // sensor orientation, it is equal to CONFIG_SENSOR_ORIENTATION_X
- INVALID_VALUE, // sensor power gpio configuration, it is equal to CONFIG_SENSOR_POWER_PIN_XX
- INVALID_VALUE, // sensor power active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- RK30_PIN0_PC1, // sensor reset gpio configuration, it is equal to CONFIG_SENSOR_RESET_PIN_XX
- 0x0, // sensor reset active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- RK30_PIN0_PC0,
- 0x1, // sensor power down active level, is equal to CONFIG_SENSOR_POWERDNACTIVE_LEVEL_X
- INVALID_VALUE,
- CONS(RK29_CAM_ISP_ICATCH7002_OV5693,_FULL_RESOLUTION), // sensor resolution, this is real resolution or resoltuion after interpolate
- 0,
- 3,
- 300000, // i2c speed , 100000 = 100KHz
- CONS(RK29_CAM_ISP_ICATCH7002_OV5693,_I2C_ADDR), // the i2c slave device address for sensor
- 0,
- 24), // sensor input clock rate, 24 or 48
- new_camera_device_ex(RK29_CAM_ISP_ICATCH7002_MI1040, //RK29_CAM_ISP_ICATCH7002_MI1040,
- front,
- 360, // sensor orientation, it is equal to CONFIG_SENSOR_ORIENTATION_X
- INVALID_VALUE, // sensor power gpio configuration, it is equal to CONFIG_SENSOR_POWER_PIN_XX
- INVALID_VALUE, // sensor power active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- RK30_PIN0_PC1, // sensor reset gpio configuration, it is equal to CONFIG_SENSOR_RESET_PIN_XX
- 0x0, // sensor reset active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- RK30_PIN0_PC0,
- 0x1, // sensor power down active level, is equal to CONFIG_SENSOR_POWERDNACTIVE_LEVEL_X
- INVALID_VALUE,
- CONS(RK29_CAM_ISP_ICATCH7002_MI1040,_FULL_RESOLUTION), // sensor resolution, this is real resolution or resoltuion after interpolate
- 0,
- 3,
- 300000, // i2c speed , 100000 = 100KHz
- CONS(RK29_CAM_ISP_ICATCH7002_MI1040,_I2C_ADDR), // the i2c slave device address for sensor
- 0,
- 24), // sensor input clock rate, 24 or 48
- new_camera_device_end
-};
-#endif //#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk30_camera.c"
-/*---------------- Camera Sensor Macro Define End ---------*/
-
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#define CONFIG_SENSOR_POWER_IOCTL_USR 1 //define this refer to your board layout
-#define CONFIG_SENSOR_RESET_IOCTL_USR 1
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
-
-static void rk_cif_power(struct rk29camera_gpio_res *res,int on)
-{
- struct regulator *ldo_18,*ldo_28;
- int camera_reset = res->gpio_reset;
- int camera_pwrdn = res->gpio_powerdown;
-
-
- ldo_28 = regulator_get(NULL, "ricoh_ldo8"); // vcc28_cif
- ldo_18 = regulator_get(NULL, "ricoh_ldo5"); // vcc18_cif
- if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){
- printk("get cif ldo failed!\n");
- return;
- }
- if(on == 0){
- while(regulator_is_enabled(ldo_28)>0)
- regulator_disable(ldo_28);
- regulator_put(ldo_28);
-
- while(regulator_is_enabled(ldo_18)>0)
- regulator_disable(ldo_18);
-
- iomux_set(GPIO1_A4);
- iomux_set(GPIO1_A5) ;
- iomux_set(GPIO1_A6);
- iomux_set(GPIO1_A7);
- iomux_set(GPIO3_B6);
- iomux_set(GPIO3_B7);
- iomux_set(GPIO0_C0);
- gpio_set_value(RK30_PIN1_PA4,0);
- gpio_set_value(RK30_PIN1_PA5,0);
- gpio_set_value(RK30_PIN1_PA6,0); // for clk 24M
- gpio_set_value(RK30_PIN1_PA7,0);
- gpio_set_value(RK30_PIN3_PB6,0);
- gpio_set_value(RK30_PIN3_PB7,0);
- gpio_set_value(RK30_PIN0_PC0,0);
-
- printk("%s off ldo5 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
- regulator_put(ldo_18);
-
- }
- else{
- // reset must be low
- if (camera_reset != INVALID_GPIO)
- gpio_set_value(camera_reset, 0);
- printk("%s ResetPin=%d ..PinLevel = %x\n",res->dev_name,camera_reset,0);
- //pwdn musb be low
- if (camera_pwrdn != INVALID_GPIO)
- gpio_set_value(camera_pwrdn, 0);
- printk("%s PwrdnPin=%d ..PinLevel = %x\n",res->dev_name,camera_pwrdn,0);
-
- gpio_set_value(RK30_PIN1_PA6,1); //Vincent_Liu@asus.com for clk 24M
-
-
- regulator_set_voltage(ldo_18, 1800000, 1800000);
- regulator_enable(ldo_18);
- printk("%s set ldo5 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
- regulator_put(ldo_18);
-
- regulator_set_voltage(ldo_28, 2800000, 2800000);
- regulator_enable(ldo_28);
- //printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
- regulator_put(ldo_28);
-
- }
-}
-
-#if CONFIG_SENSOR_RESET_IOCTL_USR
-static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- //#error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
-
- int camera_reset = res->gpio_reset;
- int camera_ioflag = res->gpio_flag;
- int camera_io_init = res->gpio_init;
- int ret = 0;
-
- if (camera_reset != INVALID_GPIO) {
- if (camera_io_init & RK29_CAM_RESETACTIVE_MASK) {
- if (on) {
- gpio_set_value(camera_reset, ((camera_ioflag&RK29_CAM_RESETACTIVE_MASK)>>RK29_CAM_RESETACTIVE_BITPOS));
- printk("%s ResetPin=%d ..PinLevel = %x\n",res->dev_name,camera_reset, ((camera_ioflag&RK29_CAM_RESETACTIVE_MASK)>>RK29_CAM_RESETACTIVE_BITPOS));
- mdelay(6);
- } else {
- gpio_set_value(camera_reset,(((~camera_ioflag)&RK29_CAM_RESETACTIVE_MASK)>>RK29_CAM_RESETACTIVE_BITPOS));
- printk("%s ResetPin= %d..PinLevel = %x\n",res->dev_name, camera_reset, (((~camera_ioflag)&RK29_CAM_RESETACTIVE_MASK)>>RK29_CAM_RESETACTIVE_BITPOS));
- mdelay(6);
- iomux_set(SPI0_CLK);
- iomux_set(SPI0_RXD);
- iomux_set(SPI0_TXD);
- iomux_set(SPI0_CS0);
- iomux_set(I2C3_SDA);
- iomux_set(I2C3_SCL);
- mdelay(6);
- }
- } else {
- ret = RK29_CAM_EIO_REQUESTFAIL;
- printk("%s ResetPin=%d request failed!", res->dev_name,camera_reset);
- }
- } else {
- ret = RK29_CAM_EIO_INVALID;
- }
- return ret;
-
-}
-#endif
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- //#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
- rk_cif_power(res,on);
- return 0;
-}
-#endif
-
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] ;
-#include "../../../drivers/media/video/rk30_camera.c"
-
-#endif /* CONFIG_VIDEO_RK29 */
+++ /dev/null
-/*
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <mach/dvfs.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <linux/rk_fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/mfd/tps65910.h>
-#include <linux/regulator/act8846.h>
-#include <linux/mfd/rk808.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-
-#ifdef CONFIG_CW2015_BATTERY
-#include <linux/power/cw2015_battery.h>
-#endif
-#if defined(CONFIG_MFD_RK610)
-#include <linux/mfd/rk610_core.h>
-#endif
-
-#if defined(CONFIG_MFD_RK616)
-#include <linux/mfd/rk616.h>
-#endif
-
-
-#if defined(CONFIG_RK_HDMI)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-#if defined(CONFIG_GPS_RK)
-#include "../../../drivers/misc/gps/rk_gps/rk_gps.h"
-#endif
-#if defined(CONFIG_MU509)
-#include <linux/mu509.h>
-#endif
-#if defined(CONFIG_MW100)
-#include <linux/mw100.h>
-#endif
-#if defined(CONFIG_MT6229)
-#include <linux/mt6229.h>
-#endif
-#if defined(CONFIG_ANDROID_TIMED_GPIO)
-#include "../../../drivers/staging/android/timed_gpio.h"
-#endif
-
-#if defined(CONFIG_MT6620)
-#include <linux/gps.h>
-#endif
-#include "../mach-rk30/board-rk3168-tb-camera.c"
-
-#if defined(CONFIG_TOUCHSCREEN_GT8XX)
-#define TOUCH_RESET_PIN RK30_PIN0_PB6
-#define TOUCH_PWR_PIN RK30_PIN0_PC5 // need to fly line by hardware engineer
-
-/* Android Parameter */
-static int ap_mdm = 0;
-module_param(ap_mdm, int, 0644);
-static int ap_has_alsa = 0;
-module_param(ap_has_alsa, int, 0644);
-static int ap_data_only = 2;
-module_param(ap_data_only, int, 0644);
-static int ap_has_earphone = 0;
-module_param(ap_has_earphone, int, 0644);
-
-
-static int goodix_init_platform_hw(void)
-{
- int ret;
-
- if (TOUCH_PWR_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_PWR_PIN, "goodix power pin");
- if (ret != 0) {
- gpio_free(TOUCH_PWR_PIN);
- printk("goodix power error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_PWR_PIN, 0);
- gpio_set_value(TOUCH_PWR_PIN, GPIO_LOW);
- msleep(100);
- }
-
- if (TOUCH_RESET_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_RESET_PIN, "goodix reset pin");
- if (ret != 0) {
- gpio_free(TOUCH_RESET_PIN);
- printk("goodix gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, 1);
- msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_LOW);
- //msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_HIGH);
- //msleep(500);
- }
- return 0;
-}
-
-struct goodix_platform_data goodix_info = {
- .model = 8105,
- .irq_pin = RK30_PIN1_PB7,
- .rest_pin = TOUCH_RESET_PIN,
- .init_platform_hw = goodix_init_platform_hw,
-};
-#endif
-
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-#define PWM_ID 3
-#define PWM_MODE PWM3
-#define PWM_EFFECT_VALUE 1
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-#define BL_EN_PIN RK30_PIN0_PA2
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
-
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
- ret = gpio_request(BL_EN_PIN, "bl_en");
- if (ret == 0) {
- gpio_direction_output(BL_EN_PIN, BL_EN_VALUE);
- }
-#endif
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0, pwm_gpio;
-#ifdef LCD_DISP_ON_PIN
- gpio_free(BL_EN_PIN);
-#endif
- pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
- gpio_request(pwm_gpio, "bl_pwm");
- gpio_direction_output(pwm_gpio, GPIO_LOW);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret, pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
-
- ret = gpio_request(pwm_gpio, "bl_pwm");
- if (ret) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return ret;
- }
- gpio_direction_output(pwm_gpio, GPIO_LOW);
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, !BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- int pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
-
- gpio_free(pwm_gpio);
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .min_brightness=20,
- .max_brightness=255,
- .brightness_mode =BRIGHTNESS_MODE_CONIC,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-#endif
-
-#ifdef CONFIG_RK29_SUPPORT_MODEM
-
-#define RK30_MODEM_POWER RK30_PIN0_PC6
-#define RK30_MODEM_POWER_IOMUX iomux_set(GPIO0_C6)
-
-static int rk30_modem_io_init(void)
-{
- printk("%s\n", __FUNCTION__);
- RK30_MODEM_POWER_IOMUX;
-
- return 0;
-}
-
-static struct rk29_io_t rk30_modem_io = {
- .io_addr = RK30_MODEM_POWER,
- .enable = GPIO_HIGH,
- .disable = GPIO_LOW,
- .io_init = rk30_modem_io_init,
-};
-
-static struct platform_device rk30_device_modem = {
- .name = "rk30_modem",
- .id = -1,
- .dev = {
- .platform_data = &rk30_modem_io,
- }
-};
-#endif
-#if defined(CONFIG_MU509)
-static int mu509_io_init(void)
-{
-
- iomux_set(GPIO2_D5);
- iomux_set(GPIO0_C6);
- iomux_set(GPIO2_D4);
- iomux_set(GPIO0_C4);
- iomux_set(GPIO0_C5);
- return 0;
-}
-
-static int mu509_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mu509_data rk29_mu509_info = {
- .io_init = mu509_io_init,
- .io_deinit = mu509_io_deinit,
- .modem_power_en = RK30_PIN2_PD5,
- .bp_power = RK30_PIN0_PC6,
- .bp_reset = RK30_PIN2_PD4,
- .ap_wakeup_bp = RK30_PIN0_PC4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
-};
-struct platform_device rk29_device_mu509 = {
- .name = "mu509",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mu509_info,
- }
- };
-#endif
-#if defined(CONFIG_MW100)
-static int mw100_io_init(void)
-{
- iomux_set(GPIO2_D5);
- iomux_set(GPIO0_C6);
- iomux_set(GPIO2_D4);
- iomux_set(GPIO0_C4);
- iomux_set(GPIO0_C5);
- return 0;
-}
-
-static int mw100_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mw100_data rk29_mw100_info = {
- .io_init = mw100_io_init,
- .io_deinit = mw100_io_deinit,
- .modem_power_en = RK30_PIN2_PD5,
- .bp_power = RK30_PIN0_PC6,
- .bp_reset = RK30_PIN2_PD4,
- .ap_wakeup_bp = RK30_PIN0_PC4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
-};
-struct platform_device rk29_device_mw100 = {
- .name = "mw100",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mw100_info,
- }
- };
-#endif
-#if defined(CONFIG_MT6229)
-static int mt6229_io_init(void)
-{
- iomux_set(GPIO2_D5);
- iomux_set(GPIO0_C6);
- iomux_set(GPIO2_D4);
- iomux_set(GPIO0_C4);
- iomux_set(GPIO0_C5);
- return 0;
-}
-
-static int mt6229_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mt6229_data rk29_mt6229_info = {
- .io_init = mt6229_io_init,
- .io_deinit = mt6229_io_deinit,
- .modem_power_en = RK30_PIN2_PD5,
- .bp_power = RK30_PIN0_PC6,
- .bp_reset = RK30_PIN2_PD4,
- .ap_wakeup_bp = RK30_PIN0_PC4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
-};
-struct platform_device rk29_device_mt6229 = {
- .name = "mt6229",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mt6229_info,
- }
- };
-#endif
-
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN RK30_PIN0_PB7
-
-static int mma8452_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data mma8452_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma8452_init_platform_hw,
- .orientation = {-1, 0, 0, 0, -1, 0, 0, 0, 1},
-};
-#endif
-#if defined (CONFIG_GS_LIS3DH)
-#define LIS3DH_INT_PIN RK30_PIN0_PB7
-
-static int lis3dh_init_platform_hw(void)
-{
-
- return 0;
-}
-
-static struct sensor_platform_data lis3dh_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lis3dh_init_platform_hw,
- .orientation = {-1, 0, 0, 0, -1, 0, 0, 0, 1},
-};
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
-static struct sensor_platform_data akm8975_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-#if defined(CONFIG_GYRO_L3G4200D)
-
-#include <linux/l3g4200d.h>
-#define L3G4200D_INT_PIN RK30_PIN0_PB4
-
-static int l3g4200d_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data l3g4200d_info = {
- .type = SENSOR_TYPE_GYROSCOPE,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
- .init_platform_hw = l3g4200d_init_platform_hw,
- .x_min = 40,//x_min,y_min,z_min = (0-100) according to hardware
- .y_min = 40,
- .z_min = 20,
-};
-
-#endif
-
-#ifdef CONFIG_LS_CM3217
-static struct sensor_platform_data cm3217_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 0,
- .poll_delay_ms = 500,
-};
-
-#endif
-
-#ifdef CONFIG_FB_ROCKCHIP
-
-#define LCD_CS_PIN INVALID_GPIO
-#define LCD_CS_VALUE GPIO_HIGH
-
-#define LCD_EN_PIN RK30_PIN0_PB0
-#if defined(CONFIG_MACH_RK3188_RK618)
-#define MIPI_LCD_RST_PIN RK30_PIN0_PC3 //mipi lcd's reset pin, if no reset pin, set's INVALID_GPIO
-#define LCD_EN_VALUE GPIO_LOW
-#else
-#define LCD_EN_VALUE GPIO_HIGH
-#endif
-
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
-
-
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_CS_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_CS_PIN);
- printk(KERN_ERR "request lcd cs pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_CS_PIN, LCD_CS_VALUE);
- }
- }
-
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_EN_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_EN_PIN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_EN_PIN, LCD_EN_VALUE);
- }
- }
-
- if(MIPI_LCD_RST_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(MIPI_LCD_RST_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(MIPI_LCD_RST_PIN);
- printk(KERN_ERR "request mipi lcd rst pin fail!\n");
- return -1;
- }
-
- else
- {
- gpio_set_value(MIPI_LCD_RST_PIN, !GPIO_LOW);
- msleep(20);
- }
- }
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, !LCD_CS_VALUE);
- }
-
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, !LCD_EN_VALUE);
- }
-
- if(MIPI_LCD_RST_PIN !=INVALID_GPIO)
- {
- gpio_set_value(MIPI_LCD_RST_PIN, GPIO_LOW);
- msleep(10);
- }
-
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE);
- }
-
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
- }
-
- if(MIPI_LCD_RST_PIN !=INVALID_GPIO)
- {
- gpio_set_value(MIPI_LCD_RST_PIN, !GPIO_LOW);
- msleep(10);
- }
- return 0;
-}
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
-struct rk29fb_info lcdc0_screen_info = {
-#if defined(CONFIG_RK_HDMI) && defined(CONFIG_HDMI_SOURCE_LCDC0) && defined(CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL)
- .prop = EXTEND, //extend display device
- .io_init = NULL,
- .io_disable = NULL,
- .io_enable = NULL,
- .set_screen_info = hdmi_init_lcdc,
-#else
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-#endif
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
-struct rk29fb_info lcdc1_screen_info = {
-#if defined(CONFIG_RK_HDMI) && defined(CONFIG_HDMI_SOURCE_LCDC1) && defined(CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL)
- .prop = EXTEND, //extend display device
- .io_init = NULL,
- .io_disable = NULL,
- .io_enable = NULL,
- .set_screen_info = hdmi_init_lcdc,
-#else
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-#endif
-};
-#endif
-
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-#if defined(CONFIG_ARCH_RK3188)
-static struct resource resource_mali[] = {
- [0] = {
- .name = "ump buf",
- .start = 0,
- .end = 0,
- .flags = IORESOURCE_MEM,
- },
-
-};
-
-static struct platform_device device_mali= {
- .name = "mali400_ump",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_mali),
- .resource = resource_mali,
-};
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
-static struct resource resource_lcdc0[] = {
- [0] = {
- .name = "lcdc0 reg",
- .start = RK30_LCDC0_PHYS,
- .end = RK30_LCDC0_PHYS + RK30_LCDC0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc0 irq",
- .start = IRQ_LCDC0,
- .end = IRQ_LCDC0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc0 = {
- .name = "rk30-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc0),
- .resource = resource_lcdc0,
- .dev = {
- .platform_data = &lcdc0_screen_info,
- },
-};
-#endif
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
-static struct resource resource_lcdc1[] = {
- [0] = {
- .name = "lcdc1 reg",
- .start = RK30_LCDC1_PHYS,
- .end = RK30_LCDC1_PHYS + RK30_LCDC1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc1 irq",
- .start = IRQ_LCDC1,
- .end = IRQ_LCDC1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc1 = {
- .name = "rk30-lcdc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resource_lcdc1),
- .resource = resource_lcdc1,
- .dev = {
- .platform_data = &lcdc1_screen_info,
- },
-};
-#endif
-
-#if defined(CONFIG_MFD_RK610)
-#define RK610_RST_PIN RK30_PIN2_PC5
-static int rk610_power_on_init(void)
-{
- int ret;
- if(RK610_RST_PIN != INVALID_GPIO)
- {
- ret = gpio_request(RK610_RST_PIN, "rk610 reset");
- if (ret)
- {
- printk(KERN_ERR "rk610_control_probe request gpio fail\n");
- }
- else
- {
- gpio_direction_output(RK610_RST_PIN, GPIO_HIGH);
- msleep(100);
- gpio_direction_output(RK610_RST_PIN, GPIO_LOW);
- msleep(100);
- gpio_set_value(RK610_RST_PIN, GPIO_HIGH);
- }
- }
-
- return 0;
-
-}
-
-
-static struct rk610_ctl_platform_data rk610_ctl_pdata = {
- .rk610_power_on_init = rk610_power_on_init,
-};
-#endif
-
-#if defined(CONFIG_MFD_RK616)
-#define RK616_RST_PIN RK30_PIN3_PB2
-
-#if defined(CONFIG_MACH_RK3188_RK618)
-#define RK616_PWREN_PIN INVALID_GPIO
-#else
-#define RK616_PWREN_PIN RK30_PIN0_PA3
-#endif
-#define RK616_SCL_RATE (100*1000) //i2c scl rate
-static int rk616_power_on_init(void)
-{
- int ret;
-
- if(RK616_PWREN_PIN != INVALID_GPIO)
- {
- ret = gpio_request(RK616_PWREN_PIN, "rk616 pwren");
- if (ret)
- {
- printk(KERN_ERR "rk616 pwren gpio request fail\n");
- }
- else
- {
- gpio_direction_output(RK616_PWREN_PIN,GPIO_HIGH);
- }
- }
-
- if(RK616_RST_PIN != INVALID_GPIO)
- {
- ret = gpio_request(RK616_RST_PIN, "rk616 reset");
- if (ret)
- {
- printk(KERN_ERR "rk616 reset gpio request fail\n");
- }
- else
- {
- gpio_direction_output(RK616_RST_PIN, GPIO_HIGH);
- msleep(2);
- gpio_direction_output(RK616_RST_PIN, GPIO_LOW);
- msleep(10);
- gpio_set_value(RK616_RST_PIN, GPIO_HIGH);
- }
- }
-
- return 0;
-
-}
-
-
-static int rk616_power_deinit(void)
-{
- gpio_set_value(RK616_PWREN_PIN,GPIO_LOW);
- gpio_set_value(RK616_RST_PIN,GPIO_LOW);
- gpio_free(RK616_PWREN_PIN);
- gpio_free(RK616_RST_PIN);
-
- return 0;
-}
-
-static struct rk616_platform_data rk616_pdata = {
- .power_init = rk616_power_on_init,
- .power_deinit = rk616_power_deinit,
- .scl_rate = RK616_SCL_RATE,
- .lcd0_func = INPUT, //port lcd0 as input
- .lcd1_func = INPUT, //port lcd1 as input
- .lvds_ch_nr = 1, //the number of used lvds channel
- .hdmi_irq = RK30_PIN2_PD6,
- .spk_ctl_gpio = RK30_PIN2_PD7,
- .hp_ctl_gpio = RK30_PIN2_PD7,
-};
-#endif
-
-#ifdef CONFIG_SND_SOC_RK610
-static int rk610_codec_io_init(void)
-{
-//if need iomux.
-//Must not gpio_request
- return 0;
-}
-
-static struct rk610_codec_platform_data rk610_codec_pdata = {
- .spk_ctl_io = RK30_PIN2_PD7,
- .io_init = rk610_codec_io_init,
-};
-#endif
-
-#ifdef CONFIG_ANDROID_TIMED_GPIO
-static struct timed_gpio timed_gpios[] = {
- {
- .name = "vibrator",
- .gpio = INVALID_GPIO,
- .max_timeout = 1000,
- .active_low = 0,
- .adjust_time =20, //adjust for diff product
- },
-};
-
-static struct timed_gpio_platform_data rk29_vibrator_info = {
- .num_gpios = 1,
- .gpios = timed_gpios,
-};
-
-static struct platform_device rk29_device_vibrator = {
- .name = "timed-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_vibrator_info,
- },
-
-};
-#endif
-
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
-static struct gpio_led rk29_leds[] = {
- {
- .name = "button-backlight",
- .gpio = INVALID_GPIO,
- .default_trigger = "timer",
- .active_low = 0,
- .retain_state_suspended = 0,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- },
-};
-
-static struct gpio_led_platform_data rk29_leds_pdata = {
- .leds = rk29_leds,
- .num_leds = ARRAY_SIZE(rk29_leds),
-};
-
-static struct platform_device rk29_device_gpio_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_leds_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_RK_IRDA
-#define IRDA_IRQ_PIN INVALID_GPIO //RK30_PIN0_PA3
-
-static int irda_iomux_init(void)
-{
- int ret = 0;
-
- //irda irq pin
- ret = gpio_request(IRDA_IRQ_PIN, NULL);
- if (ret != 0) {
- gpio_free(IRDA_IRQ_PIN);
- printk(">>>>>> IRDA_IRQ_PIN gpio_request err \n ");
- }
- gpio_pull_updown(IRDA_IRQ_PIN, PullDisable);
- gpio_direction_input(IRDA_IRQ_PIN);
-
- return 0;
-}
-
-static int irda_iomux_deinit(void)
-{
- gpio_free(IRDA_IRQ_PIN);
- return 0;
-}
-
-static struct irda_info rk29_irda_info = {
- .intr_pin = IRDA_IRQ_PIN,
- .iomux_init = irda_iomux_init,
- .iomux_deinit = irda_iomux_deinit,
- //.irda_pwr_ctl = bu92747guw_power_ctl,
-};
-
-static struct platform_device irda_device = {
-#ifdef CONFIG_RK_IRDA_NET
- .name = "rk_irda",
-#else
- .name = "bu92747_irda",
-#endif
- .id = -1,
- .dev = {
- .platform_data = &rk29_irda_info,
- }
-};
-#endif
-
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and sdio.noted by xbw at 2012-03-05
-**************************************************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "../mach-rk30/board-rk3168-tb-sdmmc-conifg.c"
-#include "../plat-rk/rk-sdmmc-ops.c"
-#include "../plat-rk/rk-sdmmc-wifi.c"
-#endif //endif ---#ifdef CONFIG_SDMMC_RK29
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- iomux_set(MMC0_CMD);
- iomux_set(MMC0_CLKOUT);
- iomux_set(MMC0_D0);
- iomux_set(MMC0_D1);
- iomux_set(MMC0_D2);
- iomux_set(MMC0_D3);
-
- iomux_set_gpio_mode(iomux_mode_to_gpio(MMC0_DETN));
-
- gpio_request(RK30_PIN3_PA7, "sdmmc-power");
- gpio_direction_output(RK30_PIN3_PA7, GPIO_LOW);
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- #if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set_gpio_mode(iomux_gpio_to_mode(RK29SDK_SD_CARD_DETECT_N));
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO);
- #endif
- #else
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(MMC0_DETN);
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FMUX);
- #endif
- #endif
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) && defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- .status = rk29sdk_wifi_mmc0_status,
- .register_status_notify = rk29sdk_wifi_mmc0_status_register,
-#endif
-
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .power_en = RK29SDK_SD_CARD_PWR_EN,
- .power_en_level = RK29SDK_SD_CARD_PWR_EN_LEVEL,
-#else
- .power_en = INVALID_GPIO,
- .power_en_level = GPIO_LOW,
-#endif
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC0_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- .det_pin_info = {
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N, //INVALID_GPIO,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
- #endif
- },
-
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- iomux_set(MMC1_CMD);
- iomux_set(MMC1_CLKOUT);
- iomux_set(MMC1_D0);
- iomux_set(MMC1_D1);
- iomux_set(MMC1_D2);
- iomux_set(MMC1_D3);
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC) || defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC1_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- #if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
- .sdio_INT_gpio = RK29SDK_WIFI_SDIO_CARD_INT,
- #endif
-
- .det_pin_info = {
-#if defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- #else
- .io = INVALID_GPIO,
- #endif
-
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-
- .enable_sd_wakeup = 0,
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-/**************************************************************************************************
- * the end of setting for SDMMC devices
-**************************************************************************************************/
-
-#ifdef CONFIG_BATTERY_RK30_ADC
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = RK30_PIN0_PB2,
- .batt_low_pin = RK30_PIN0_PB1,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = RK30_PIN0_PA6,
- .dc_det_level = GPIO_LOW,
- .charge_ok_level = GPIO_HIGH,
-};
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-#ifdef CONFIG_CW2015_BATTERY
-/*
- note the follow array must set depend on the battery that you use
- you must send the battery to cellwise-semi the contact information:
- name: chen gan; tel:13416876079; E-mail: ben.chen@cellwise-semi.com
- */
-static u8 config_info[SIZE_BATINFO] = {
- 0x15, 0x42, 0x60, 0x59, 0x52,
- 0x58, 0x4D, 0x48, 0x48, 0x44,
- 0x44, 0x46, 0x49, 0x48, 0x32,
- 0x24, 0x20, 0x17, 0x13, 0x0F,
- 0x19, 0x3E, 0x51, 0x45, 0x08,
- 0x76, 0x0B, 0x85, 0x0E, 0x1C,
- 0x2E, 0x3E, 0x4D, 0x52, 0x52,
- 0x57, 0x3D, 0x1B, 0x6A, 0x2D,
- 0x25, 0x43, 0x52, 0x87, 0x8F,
- 0x91, 0x94, 0x52, 0x82, 0x8C,
- 0x92, 0x96, 0xFF, 0x7B, 0xBB,
- 0xCB, 0x2F, 0x7D, 0x72, 0xA5,
- 0xB5, 0xC1, 0x46, 0xAE
-};
-
-static struct cw_bat_platform_data cw_bat_platdata = {
- .dc_det_pin = RK30_PIN0_PB2,
- .bat_low_pin = RK30_PIN0_PB1,
- .chg_ok_pin = RK30_PIN0_PA6,
- .dc_det_level = GPIO_LOW,
- .bat_low_level = GPIO_LOW,
- .chg_ok_level = GPIO_HIGH,
-
- .cw_bat_config_info = config_info,
-
-};
-
-#endif
-#ifdef CONFIG_RK30_PWM_REGULATOR
-static int pwm_voltage_map[] = {
- 800000,825000,850000, 875000,900000, 925000 ,950000, 975000,1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000,1375000
-};
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_cpu",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] =
-{
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
- .pwm_id = 1,
- .pwm_gpio = RK30_PIN3_PD4,
- .pwm_iomux_pwm = PWM1,
- .pwm_iomux_gpio = GPIO3_D4,
- .pwm_voltage = 1100000,
- .suspend_voltage = 1000000,
- .min_uV = 800000,
- .max_uV = 1375000,
- .coefficient = 575, //57.5%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-#endif
-
-#ifdef CONFIG_RK29_VMAC
-#define PHY_PWR_EN_GPIO RK30_PIN1_PD6
-#include "board-rk30-sdk-vmac.c"
-#endif
-
-#ifdef CONFIG_RFKILL_RK
-// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
-static struct rfkill_rk_platform_data rfkill_rk_platdata = {
- .type = RFKILL_TYPE_BLUETOOTH,
-
- .poweron_gpio = { // BT_REG_ON
- .io = INVALID_GPIO, //RK30_PIN3_PC7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_poweron",
- .fgpio = GPIO3_C7,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN3_PC7, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_reset",
- .fgpio = GPIO3_C7,
- },
- },
-
- .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
- .io = RK30_PIN3_PC6, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_wake",
- .fgpio = GPIO3_C6,
- },
- },
-
- .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .gpio = {
- .io = RK30_PIN0_PA5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
- .iomux = {
- .name = NULL,
- },
- },
- },
-
- .rts_gpio = { // UART_RTS, enable or disable BT's data coming
- .io = RK30_PIN1_PA3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_rts",
- .fgpio = GPIO1_A3,
- .fmux = UART0_RTSN,
- },
- },
-};
-
-static struct platform_device device_rfkill_rk = {
- .name = "rfkill_rk",
- .id = -1,
- .dev = {
- .platform_data = &rfkill_rk_platdata,
- },
-};
-#endif
-
-#if defined(CONFIG_GPS_RK)
-int rk_gps_io_init(void)
-{
- printk("%s \n", __FUNCTION__);
-
- gpio_request(RK30_PIN1_PB5, NULL);
- gpio_direction_output(RK30_PIN1_PB5, GPIO_LOW);
-
- iomux_set(GPS_RFCLK);//GPS_CLK
- iomux_set(GPS_MAG);//GPS_MAG
- iomux_set(GPS_SIG);//GPS_SIGN
-
- gpio_request(RK30_PIN1_PA6, NULL);
- gpio_direction_output(RK30_PIN1_PA6, GPIO_LOW);
-
- gpio_request(RK30_PIN1_PA5, NULL);
- gpio_direction_output(RK30_PIN1_PA5, GPIO_LOW);
-
- gpio_request(RK30_PIN1_PA7, NULL);
- gpio_direction_output(RK30_PIN1_PA7, GPIO_LOW);
- return 0;
-}
-int rk_gps_power_up(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_power_down(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_reset_set(int level)
-{
- return 0;
-}
-int rk_enable_hclk_gps(void)
-{
- struct clk *gps_aclk = NULL;
- gps_aclk = clk_get(NULL, "aclk_gps");
- if(gps_aclk) {
- clk_enable(gps_aclk);
- clk_put(gps_aclk);
- printk("%s \n", __FUNCTION__);
- }
- else
- printk("get gps aclk fail\n");
- return 0;
-}
-int rk_disable_hclk_gps(void)
-{
- struct clk *gps_aclk = NULL;
- gps_aclk = clk_get(NULL, "aclk_gps");
- if(gps_aclk) {
- //TO wait long enough until GPS ISR is finished.
- msleep(5);
- clk_disable(gps_aclk);
- clk_put(gps_aclk);
- printk("%s \n", __FUNCTION__);
- }
- else
- printk("get gps aclk fail\n");
- return 0;
-}
-struct rk_gps_data rk_gps_info = {
- .io_init = rk_gps_io_init,
- .power_up = rk_gps_power_up,
- .power_down = rk_gps_power_down,
- .reset = rk_gps_reset_set,
- .enable_hclk_gps = rk_enable_hclk_gps,
- .disable_hclk_gps = rk_disable_hclk_gps,
- .GpsSign = RK30_PIN1_PB3,
- .GpsMag = RK30_PIN1_PB2, //GPIO index
- .GpsClk = RK30_PIN1_PB4, //GPIO index
- .GpsVCCEn = RK30_PIN1_PB5, //GPIO index
- .GpsSpi_CSO = RK30_PIN1_PA4, //GPIO index
- .GpsSpiClk = RK30_PIN1_PA5, //GPIO index
- .GpsSpiMOSI = RK30_PIN1_PA7, //GPIO index
- .GpsIrq = IRQ_GPS,
- .GpsSpiEn = 0,
- .GpsAdcCh = 2,
- .u32GpsPhyAddr = RK30_GPS_PHYS,
- .u32GpsPhySize = RK30_GPS_SIZE,
-};
-
-struct platform_device rk_device_gps = {
- .name = "gps_hv5820b",
- .id = -1,
- .dev = {
- .platform_data = &rk_gps_info,
- }
- };
-#endif
-
-#if defined(CONFIG_MT5931_MT6622)
-static struct mt6622_platform_data mt6622_platdata = {
- .power_gpio = { // BT_REG_ON
- .io = RK30_PIN3_PD5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN0_PD7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .irq_gpio = {
- .io = RK30_PIN3_PD2,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- }
-};
-
-static struct platform_device device_mt6622 = {
- .name = "mt6622",
- .id = -1,
- .dev = {
- .platform_data = &mt6622_platdata,
- },
-};
-#endif
-
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_ANDROID_TIMED_GPIO
- &rk29_device_vibrator,
-#endif
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
- &rk29_device_gpio_leds,
-#endif
-#ifdef CONFIG_RK_IRDA
- &irda_device,
-#endif
-#if defined(CONFIG_WIFI_CONTROL_FUNC)||defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- &rk29sdk_wifi_device,
-#endif
-
-#if defined(CONFIG_MT6620)
- &mt3326_device_gps,
-#endif
-
-#ifdef CONFIG_RK29_SUPPORT_MODEM
- &rk30_device_modem,
-#endif
-#if defined(CONFIG_MU509)
- &rk29_device_mu509,
-#endif
-#if defined(CONFIG_MW100)
- &rk29_device_mw100,
-#endif
-#if defined(CONFIG_MT6229)
- &rk29_device_mt6229,
-#endif
-#ifdef CONFIG_BATTERY_RK30_ADC
- &rk30_device_adc_battery,
-#endif
-#ifdef CONFIG_RFKILL_RK
- &device_rfkill_rk,
-#endif
-#ifdef CONFIG_GPS_RK
- &rk_device_gps,
-#endif
-#if defined(CONFIG_ARCH_RK3188)
- &device_mali,
-#endif
-#ifdef CONFIG_MT5931_MT6622
- &device_mt6622,
-#endif
-};
-
-static int rk_platform_add_display_devices(void)
-{
- struct platform_device *fb = NULL; //fb
- struct platform_device *lcdc0 = NULL; //lcdc0
- struct platform_device *lcdc1 = NULL; //lcdc1
- struct platform_device *bl = NULL; //backlight
-#ifdef CONFIG_FB_ROCKCHIP
- fb = &device_fb;
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
- lcdc0 = &device_lcdc0,
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
- lcdc1 = &device_lcdc1,
-#endif
-
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- bl = &rk29_device_backlight,
-#endif
- __rk_platform_add_display_devices(fb,lcdc0,lcdc1,bl);
-
- return 0;
-
-}
-
-// i2c
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1d,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_GS_LIS3DH)
- {
- .type = "gs_lis3dh",
- .addr = 0x19, //0x19(SA0-->VCC), 0x18(SA0-->GND)
- .flags = 0,
- .irq = LIS3DH_INT_PIN,
- .platform_data = &lis3dh_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8975_info,
- },
-#endif
-#if defined (CONFIG_GYRO_L3G4200D)
- {
- .type = "l3g4200d_gryo",
- .addr = 0x69,
- .flags = 0,
- .irq = L3G4200D_INT_PIN,
- .platform_data = &l3g4200d_info,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RT5631)
- {
- .type = "rt5631",
- .addr = 0x1a,
- .flags = 0,
- },
-#endif
-
-#if defined (CONFIG_SND_SOC_RT5640)
- {
- .type = "rt5640",
- .addr = 0x1c,
- .flags = 0,
- },
-#endif
-
-#ifdef CONFIG_MFD_RK610
- {
- .type = "rk610_ctl",
- .addr = 0x40,
- .flags = 0,
- .platform_data = &rk610_ctl_pdata,
- },
-#ifdef CONFIG_RK610_TVOUT
- {
- .type = "rk610_tvout",
- .addr = 0x42,
- .flags = 0,
- },
-#endif
-#ifdef CONFIG_HDMI_RK610
- {
- .type = "rk610_hdmi",
- .addr = 0x46,
- .flags = 0,
- .irq = INVALID_GPIO,
- },
-#endif
-#ifdef CONFIG_SND_SOC_RK610
- {//RK610_CODEC addr from 0x60 to 0x80 (0x60~0x80)
- .type = "rk610_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- .platform_data = &rk610_codec_pdata,
- },
-#endif
-#endif
-
-};
-#endif
-
-int __sramdata g_pmic_type = 0;
-#ifdef CONFIG_I2C1_RK30
-#ifdef CONFIG_MFD_WM831X_I2C
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info wm8326_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "dcdc3", //ddr
- .min_uv = 1150000,
- .max_uv = 1150000,
- .suspend_vol = 1150000,
- },
- #ifdef CONFIG_MACH_RK3066_SDK
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3000000,
- },
- #else
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3000000,
- .max_uv = 3000000,
- .suspend_vol = 2800000,
- },
- #endif
-};
-
-static struct pmu_info wm8326_ldo_info[] = {
- {
- .name = "ldo1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo2", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo3", //
- .min_uv = 1100000,
- .max_uv = 1100000,
- .suspend_vol = 1100000,
- },
- {
- .name = "ldo4", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 1000000,
- },
- {
- .name = "ldo5", //vcc25
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo6", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo7", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- .suspend_vol = 2800000,
- },
- {
- .name = "ldo8", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo9", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo10", //flash_io
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
-};
-
-#include "../mach-rk30/board-pmu-wm8326.c"
-#endif
-
-#ifdef CONFIG_MFD_TPS65910
-#define TPS65910_HOST_IRQ RK30_PIN0_PB3
-
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info tps65910_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1100000,
- .max_uv = 1100000,
- },
- {
- .name = "vdd2", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vio", //vcc_io
- .min_uv = 2500000,
- .max_uv = 2500000,
- },
-
-};
-static struct pmu_info tps65910_ldo_info[] = {
- {
- .name = "vpll", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "vdig2", //vdd_jetta
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vaux1", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "vaux2", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vaux33", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vmmc", //vcc30
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
- {
- .name = "vdac", //vcc18
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- };
-
-#include "../mach-rk30/board-pmu-tps65910.c"
-#endif
-
-#ifdef CONFIG_REGULATOR_ACT8846
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-#define PMU_VSEL RK30_PIN3_PD3
-static struct pmu_info act8846_dcdc_info[] = {
- {
- .name = "act_dcdc1", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- .suspend_vol = 1200000,
- },
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 1200000,
- #else
- .suspend_vol = 900000,
- #endif
-
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 1200000,
- #else
- .suspend_vol = 900000,
- #endif
-
- },
- {
- .name = "act_dcdc4", //vccio
- .min_uv = 3000000,
- .max_uv = 3000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 3000000,
- #else
- .suspend_vol = 2800000,
- #endif
-
- },
-
-};
-static struct pmu_info act8846_ldo_info[] = {
- {
- .name = "act_ldo1", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "act_ldo2", //vdd12
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "act_ldo3", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo4", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo5", //vcctp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo6", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo7", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo8", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- };
-
-#include "../mach-rk30/board-pmu-act8846.c"
-#endif
-
-#ifdef CONFIG_MFD_RK808
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-#define RK808_HOST_IRQ RK30_PIN0_PB3
-
-static struct pmu_info rk808_dcdc_info[] = {
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 900000,
- },
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 900000,
- },
- {
- .name = "rk_dcdc3", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- .suspend_vol = 1200000,
- },
- {
- .name = "rk_dcdc4", //vccio
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3000000,
- },
-
-};
-static struct pmu_info rk808_ldo_info[] = {
- {
- .name = "rk_ldo1", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "rk_ldo2", //vcctp
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
-
- },
- {
- .name = "rk_ldo3", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 1000000,
- },
- {
- .name = "rk_ldo4", //vcc18
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "rk_ldo5", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- .suspend_vol = 2800000,
- },
- {
- .name = "rk_ldo6", //vdd12
- .min_uv = 1200000,
- .max_uv = 1200000,
- .suspend_vol = 1200000,
- },
- {
- .name = "rk_ldo7", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "rk_ldo8", //vcca_33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- };
-
-#include "board-pmu-rk808.c"
-#endif
-
-
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_MFD_WM831X_I2C)
- {
- .type = "wm8326",
- .addr = 0x34,
- .flags = 0,
- .irq = RK30_PIN0_PB3,
- .platform_data = &wm831x_platdata,
- },
-#endif
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-
-#if defined (CONFIG_REGULATOR_ACT8846)
- {
- .type = "act8846",
- .addr = 0x5a,
- .flags = 0,
- // .irq = ACT8846_HOST_IRQ,
- .platform_data=&act8846_data,
- },
-#endif
-#if defined (CONFIG_MFD_RK808)
- {
- .type = "rk808",
- .addr = 0x1b,
- .flags = 0,
- // .irq = ACT8846_HOST_IRQ,
- .platform_data=&rk808_data,
- },
-#endif
-
-#if defined (CONFIG_RTC_HYM8563)
- {
- .type = "rtc_hym8563",
- .addr = 0x51,
- .flags = 0,
- .irq = RK30_PIN1_PA4,
- },
-#if defined (CONFIG_CW2015_BATTERY)
- {
- .type = "cw201x",
- .addr = 0x62,
- .flags = 0,
- .platform_data = &cw_bat_platdata,
- },
-#endif
-#endif
-
-};
-#endif
-
-void __sramfunc board_pmu_suspend(void)
-{
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_suspend();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_suspend();
- #endif
- #if defined (CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- board_pmu_act8846_suspend();
- #endif
- #if defined (CONFIG_MFD_RK808)
- if(pmic_is_rk808())
- board_pmu_rk808_suspend();
- #endif
-
-}
-
-void __sramfunc board_pmu_resume(void)
-{
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_resume();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_resume();
- #endif
- #if defined (CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- board_pmu_act8846_resume();
- #endif
- #if defined (CONFIG_MFD_RK808)
- if(pmic_is_rk808())
- board_pmu_rk808_resume();
- #endif
-
-}
-
- int __sramdata gpio3d6_iomux,gpio3d6_do,gpio3d6_dir,gpio3d6_en;
-
-#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
-
-void __sramfunc rk30_pwm_logic_suspend_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
-
-// int gpio0d7_iomux,gpio0d7_do,gpio0d7_dir,gpio0d7_en;
- sram_udelay(10000);
- gpio3d6_iomux = grf_readl(GRF_GPIO3D_IOMUX);
- gpio3d6_do = grf_readl(GRF_GPIO3H_DO);
- gpio3d6_dir = grf_readl(GRF_GPIO3H_DIR);
- gpio3d6_en = grf_readl(GRF_GPIO3H_EN);
-
- grf_writel((1<<28), GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DIR);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DO);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_EN);
-#endif
-}
-void __sramfunc rk30_pwm_logic_resume_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- grf_writel((1<<28)|gpio3d6_iomux, GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|gpio3d6_en, GRF_GPIO3H_EN);
- grf_writel((1<<30)|gpio3d6_dir, GRF_GPIO3H_DIR);
- grf_writel((1<<30)|gpio3d6_do, GRF_GPIO3H_DO);
- sram_udelay(10000);
-
-#endif
-
-}
-extern void pwm_suspend_voltage(void);
-extern void pwm_resume_voltage(void);
-void rk30_pwm_suspend_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_suspend_voltage();
-#endif
-}
-void rk30_pwm_resume_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_resume_voltage();
-#endif
-}
-
-
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-#if defined (CONFIG_TOUCHSCREEN_GT8XX)
- {
- .type = "Goodix-TS",
- .addr = 0x55,
- .flags = 0,
- .irq = RK30_PIN1_PB7,
- .platform_data = &goodix_info,
- },
-#endif
-#if defined (CONFIG_LS_CM3217)
- {
- .type = "lightsensor",
- .addr = 0x10,
- .flags = 0,
- .platform_data = &cm3217_info,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C4_RK30
-static struct i2c_board_info __initdata i2c4_info[] = {
-#if defined (CONFIG_MFD_RK616)
- {
- .type = "rk616",
- .addr = 0x50,
- .flags = 0,
- .platform_data = &rk616_pdata,
- },
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO// RK30_PIN2_PD6 //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO//RK30_PIN2_PD7 //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- //set iomux (gpio) here
- //rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME, GPIO2D_GPIO2D7);
- //rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME, GPIO2D_GPIO2D6);
-
- return 0;
-}
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C4_RK30
- i2c_register_board_info(4, i2c4_info, ARRAY_SIZE(i2c4_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(5, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-
-// ========== Begin of rk3168 top board keypad defination ============
-
-#include <plat/key.h>
-
-
-#if defined(CONFIG_MACH_RK3188_RK618)
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK30_PIN0_PA4,
- .active_low = PRESS_LEV_LOW,
- .wakeup = 1,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .adc_value = 1,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .adc_value = 133,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .adc_value = 550,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "menu",
- .code = EV_MENU,
- .adc_value = 354,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .adc_value = 742,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-};
-
-#else
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .adc_value = 900,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK30_PIN0_PA4,
- .active_low = PRESS_LEV_LOW,
- .wakeup = 1,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .adc_value = 1,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "menu",
- .code = EV_MENU,
- .adc_value = 133,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .adc_value = 550,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .adc_value = 333,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "camera",
- .code = KEY_CAMERA,
- .adc_value = 742,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-};
-#endif
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = 1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
-// =========== End of rk3168 top board keypad defination =============
-
-
-#define POWER_ON_PIN RK30_PIN0_PA0 //power_hold
-static void rk30_pm_power_off(void)
-{
- printk(KERN_ERR "rk30_pm_power_off start...\n");
- #if defined(CONFIG_MFD_WM831X)
- if(pmic_is_wm8326()){
- wm831x_set_bits(Wm831x,WM831X_GPIO_LEVEL,0x0001,0x0000); //set sys_pwr 0
- wm831x_device_shutdown(Wm831x);//wm8326 shutdown
- }
- #endif
-
- #if defined(CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- {
- act8846_device_shutdown();
- }
- #endif
-
- #if defined(CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- {
- tps65910_device_shutdown();//tps65910 shutdown
- }
- #endif
-
- #if defined(CONFIG_MFD_RK808)
- if(pmic_is_rk808())
- {
- rk808_device_shutdown();//rk808 shutdown
- }
- #endif
-
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
- while (1);
-}
-
-static void __init machine_rk30_board_init(void)
-{
- //avs_init();
- gpio_request(POWER_ON_PIN, "poweronpin");
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
- pm_power_off = rk30_pm_power_off;
-
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
-
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- rk_platform_add_display_devices();
- board_usb_detect_init(RK30_PIN0_PA7);
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC)
- rk29sdk_wifi_bt_gpio_control_init();
-#elif defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- rk29sdk_wifi_combo_module_gpio_init();
-#endif
-
-#if defined(CONFIG_MT6620)
- clk_set_rate(clk_get_sys("rk_serial.0", "uart"), 48*1000000);
-#endif
-
-#if defined(CONFIG_MT5931_MT6622)
- clk_set_rate(clk_get_sys("rk_serial.0", "uart"), 24*1000000);
-#endif
-}
-#define HD_SCREEN_SIZE 1920UL*1200UL*4*3
-static void __init rk30_reserve(void)
-{
-#if defined(CONFIG_ARCH_RK3188)
- /*if lcd resolution great than or equal to 1920*1200,reserve the ump memory */
- if(!(get_fb_size() < ALIGN(HD_SCREEN_SIZE,SZ_1M)))
- {
- int ump_mem_phy_size=512UL*1024UL*1024UL;
- resource_mali[0].start = board_mem_reserve_add("ump buf", ump_mem_phy_size);
- resource_mali[0].end = resource_mali[0].start + ump_mem_phy_size -1;
- }
-#endif
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0 buf", get_fb_size());
- resource_fb[0].end = resource_fb[0].start + get_fb_size()- 1;
-#if 0
- resource_fb[1].start = board_mem_reserve_add("ipp buf", RK30_FB0_MEM_SIZE);
- resource_fb[1].end = resource_fb[1].start + RK30_FB0_MEM_SIZE - 1;
-#endif
-
-#if defined(CONFIG_FB_ROTATE) || !defined(CONFIG_THREE_FB_BUFFER)
- resource_fb[2].start = board_mem_reserve_add("fb2 buf",get_fb_size());
- resource_fb[2].end = resource_fb[2].start + get_fb_size() - 1;
-#endif
-#endif
-
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
-
-#ifdef CONFIG_GPS_RK
- //it must be more than 8MB
- rk_gps_info.u32MemoryPhyAddr = board_mem_reserve_add("gps", SZ_8M);
-#endif
- board_mem_reserved();
-}
-/******************************** arm dvfs frequency volt table **********************************/
-/**
- * dvfs_cpu_logic_table: table for arm and logic dvfs
- * @frequency : arm frequency
- * @cpu_volt : arm voltage depend on frequency
- */
-
-#if defined(CONFIG_ARCH_RK3188)
-//sdk
-static struct cpufreq_frequency_table dvfs_arm_table_volt_level0[] = {
- {.frequency = 312 * 1000, .index = 850 * 1000},
- {.frequency = 504 * 1000, .index = 900 * 1000},
- {.frequency = 816 * 1000, .index = 950 * 1000},
- {.frequency = 1008 * 1000, .index = 1025 * 1000},
- {.frequency = 1200 * 1000, .index = 1100 * 1000},
- {.frequency = 1416 * 1000, .index = 1200 * 1000},
- {.frequency = 1608 * 1000, .index = 1300 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-//default
-static struct cpufreq_frequency_table dvfs_arm_table_volt_level1[] = {
- {.frequency = 312 * 1000, .index = 875 * 1000},
- {.frequency = 504 * 1000, .index = 925 * 1000},
- {.frequency = 816 * 1000, .index = 975 * 1000},
- {.frequency = 1008 * 1000, .index = 1075 * 1000},
- {.frequency = 1200 * 1000, .index = 1150 * 1000},
- {.frequency = 1416 * 1000, .index = 1250 * 1000},
- {.frequency = 1608 * 1000, .index = 1350 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-// cube 10'
-static struct cpufreq_frequency_table dvfs_arm_table_volt_level2[] = {
- {.frequency = 312 * 1000, .index = 900 * 1000},
- {.frequency = 504 * 1000, .index = 925 * 1000},
- {.frequency = 816 * 1000, .index = 1000 * 1000},
- {.frequency = 1008 * 1000, .index = 1075 * 1000},
- {.frequency = 1200 * 1000, .index = 1200 * 1000},
- {.frequency = 1416 * 1000, .index = 1250 * 1000},
- {.frequency = 1608 * 1000, .index = 1350 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-/******************************** gpu dvfs frequency volt table **********************************/
-//sdk
-static struct cpufreq_frequency_table dvfs_gpu_table_volt_level0[] = {
- {.frequency = 133 * 1000, .index = 975 * 1000},//the mininum rate is limited 133M for rk3188
- {.frequency = 200 * 1000, .index = 975 * 1000},
- {.frequency = 266 * 1000, .index = 1000 * 1000},
- {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1100 * 1000},
- {.frequency = 600 * 1000, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-//cube 10'
-static struct cpufreq_frequency_table dvfs_gpu_table_volt_level1[] = {
- {.frequency = 133 * 1000, .index = 975 * 1000},//the mininum rate is limited 133M for rk3188
- {.frequency = 200 * 1000, .index = 1000 * 1000},
- {.frequency = 266 * 1000, .index = 1025 * 1000},
- {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1100 * 1000},
- {.frequency = 600 * 1000, .index = 1250 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-/******************************** ddr dvfs frequency volt table **********************************/
-static struct cpufreq_frequency_table dvfs_ddr_table_volt_level0[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 950 * 1000},
- {.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = 1000 * 1000},
- {.frequency = 396 * 1000 + DDR_FREQ_NORMAL, .index = 1100 * 1000},
- {.frequency = 460 * 1000 + DDR_FREQ_DUALVIEW, .index = 1150 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-//if you board is good for volt quality,select dvfs_arm_table_volt_level0
-#define dvfs_arm_table dvfs_arm_table_volt_level1
-#define dvfs_gpu_table dvfs_gpu_table_volt_level1
-#define dvfs_ddr_table dvfs_ddr_table_volt_level0
-
-#else
-//for RK3168 && RK3066B
-static struct cpufreq_frequency_table dvfs_arm_table[] = {
- {.frequency = 312 * 1000, .index = 950 * 1000},
- {.frequency = 504 * 1000, .index = 1000 * 1000},
- {.frequency = 816 * 1000, .index = 1050 * 1000},
- {.frequency = 1008 * 1000, .index = 1125 * 1000},
- {.frequency = 1200 * 1000, .index = 1200 * 1000},
- //{.frequency = 1416 * 1000, .index = 1250 * 1000},
- //{.frequency = 1608 * 1000, .index = 1300 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- {.frequency = 100 * 1000, .index = 1000 * 1000},
- {.frequency = 200 * 1000, .index = 1000 * 1000},
- {.frequency = 266 * 1000, .index = 1050 * 1000},
- //{.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1125 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 1000 * 1000},
- {.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = 1050 * 1000},
- {.frequency = 400 * 1000 + DDR_FREQ_NORMAL, .index = 1100 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-#endif
-/******************************** arm dvfs frequency volt table end **********************************/
-//#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
-//static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
-//static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
-
-void __init board_clock_init(void)
-{
- rk30_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
- //dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "cpu"), dvfs_arm_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
-}
-
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk30_fixup,
- .reserve = &rk30_reserve,
- .map_io = rk30_map_io,
- .init_irq = rk30_init_irq,
- .timer = &rk30_timer,
- .init_machine = machine_rk30_board_init,
-MACHINE_END
+++ /dev/null
-/*
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <mach/dvfs.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <linux/rk_fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/mfd/tps65910.h>
-#include <linux/regulator/act8846.h>
-#include <linux/mfd/rk808.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-
-#ifdef CONFIG_CW2015_BATTERY
-#include <linux/power/cw2015_battery.h>
-#endif
-#if defined(CONFIG_MFD_RK610)
-#include <linux/mfd/rk610_core.h>
-#endif
-
-#if defined(CONFIG_RK_HDMI)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-#if defined(CONFIG_GPS_RK)
-#include "../../../drivers/misc/gps/rk_gps/rk_gps.h"
-#endif
-#if defined(CONFIG_MU509)
-#include <linux/mu509.h>
-#endif
-#if defined(CONFIG_MW100)
-#include <linux/mw100.h>
-#endif
-#if defined(CONFIG_MT6229)
-#include <linux/mt6229.h>
-#endif
-#if defined(CONFIG_ANDROID_TIMED_GPIO)
-#include "../../../drivers/staging/android/timed_gpio.h"
-#endif
-
-#if defined(CONFIG_BOARD_ID)
-#include <linux/board-id.h>
-#endif
-
-#if defined(CONFIG_MT6620)
-#include <linux/gps.h>
-#endif
-#include "../mach-rk30/board-rk3168-tb-camera.c"
-
-#if defined(CONFIG_TOUCHSCREEN_GT8XX)
-#define TOUCH_RESET_PIN RK30_PIN0_PB6
-#define TOUCH_PWR_PIN RK30_PIN0_PC5 // need to fly line by hardware engineer
-
-/* Android Parameter */
-static int ap_mdm = 0;
-module_param(ap_mdm, int, 0644);
-static int ap_has_alsa = 0;
-module_param(ap_has_alsa, int, 0644);
-static int ap_data_only = 2;
-module_param(ap_data_only, int, 0644);
-static int ap_has_earphone = 0;
-module_param(ap_has_earphone, int, 0644);
-
-
-static int goodix_init_platform_hw(void)
-{
- int ret;
-
- if (TOUCH_PWR_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_PWR_PIN, "goodix power pin");
- if (ret != 0) {
- gpio_free(TOUCH_PWR_PIN);
- printk("goodix power error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_PWR_PIN, 0);
- gpio_set_value(TOUCH_PWR_PIN, GPIO_LOW);
- msleep(100);
- }
-
- if (TOUCH_RESET_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_RESET_PIN, "goodix reset pin");
- if (ret != 0) {
- gpio_free(TOUCH_RESET_PIN);
- printk("goodix gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, 1);
- msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_LOW);
- //msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_HIGH);
- //msleep(500);
- }
- return 0;
-}
-
-struct goodix_platform_data goodix_info = {
- .model = 8105,
- .irq_pin = RK30_PIN1_PB7,
- .rest_pin = TOUCH_RESET_PIN,
- .init_platform_hw = goodix_init_platform_hw,
-};
-#endif
-
-#ifdef CONFIG_SND_RK29_SOC_AK4396
-static struct rk29xx_spi_chip spi_ak4399_chip = {
- .enable_dma = 1,
-};
-#endif
-
-static struct spi_board_info board_spi_devices[] = {
-#ifdef CONFIG_SND_RK29_SOC_AK4396
- {
- .modalias = "AK4396",
- .mode = SPI_MODE_0,
- .max_speed_hz = 3*1000*1000,
- .bus_num = 1,
- .chip_select = 0,
- //.controller_data = &spi_ak4399_chip,
- },
-#endif
-};
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-#define PWM_ID 3
-#define PWM_MODE PWM3
-#define PWM_EFFECT_VALUE 1
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-#define BL_EN_PIN RK30_PIN0_PA2
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
-
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
- ret = gpio_request(BL_EN_PIN, "bl_en");
- if (ret == 0) {
- gpio_direction_output(BL_EN_PIN, BL_EN_VALUE);
- }
-#endif
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0, pwm_gpio;
-#ifdef LCD_DISP_ON_PIN
- gpio_free(BL_EN_PIN);
-#endif
- pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
- gpio_request(pwm_gpio, "bl_pwm");
- gpio_direction_output(pwm_gpio, GPIO_LOW);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret, pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
-
- ret = gpio_request(pwm_gpio, "bl_pwm");
- if (ret) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return ret;
- }
- gpio_direction_output(pwm_gpio, GPIO_LOW);
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, !BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- int pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
-
- gpio_free(pwm_gpio);
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .min_brightness=20,
- .max_brightness=255,
- .brightness_mode =BRIGHTNESS_MODE_CONIC,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-#endif
-
-#ifdef CONFIG_RK29_SUPPORT_MODEM
-
-#define RK30_MODEM_POWER RK30_PIN0_PC6
-#define RK30_MODEM_POWER_IOMUX iomux_set(GPIO0_C6)
-
-static int rk30_modem_io_init(void)
-{
- printk("%s\n", __FUNCTION__);
- RK30_MODEM_POWER_IOMUX;
-
- return 0;
-}
-
-static struct rk29_io_t rk30_modem_io = {
- .io_addr = RK30_MODEM_POWER,
- .enable = GPIO_HIGH,
- .disable = GPIO_LOW,
- .io_init = rk30_modem_io_init,
-};
-
-static struct platform_device rk30_device_modem = {
- .name = "rk30_modem",
- .id = -1,
- .dev = {
- .platform_data = &rk30_modem_io,
- }
-};
-#endif
-#if defined(CONFIG_MU509)
-static int mu509_io_init(void)
-{
-
- iomux_set(GPIO2_D5);
- iomux_set(GPIO0_C6);
- iomux_set(GPIO2_D4);
- iomux_set(GPIO0_C4);
- iomux_set(GPIO0_C5);
- return 0;
-}
-
-static int mu509_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mu509_data rk29_mu509_info = {
- .io_init = mu509_io_init,
- .io_deinit = mu509_io_deinit,
- .modem_power_en = RK30_PIN2_PD5,
- .bp_power = RK30_PIN0_PC6,
- .bp_reset = RK30_PIN2_PD4,
- .ap_wakeup_bp = RK30_PIN0_PC4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
-};
-struct platform_device rk29_device_mu509 = {
- .name = "mu509",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mu509_info,
- }
- };
-#endif
-#if defined(CONFIG_MW100)
-static int mw100_io_init(void)
-{
- iomux_set(GPIO2_D5);
- iomux_set(GPIO0_C6);
- iomux_set(GPIO2_D4);
- iomux_set(GPIO0_C4);
- iomux_set(GPIO0_C5);
- return 0;
-}
-
-static int mw100_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mw100_data rk29_mw100_info = {
- .io_init = mw100_io_init,
- .io_deinit = mw100_io_deinit,
- .modem_power_en = RK30_PIN2_PD5,
- .bp_power = RK30_PIN0_PC6,
- .bp_reset = RK30_PIN2_PD4,
- .ap_wakeup_bp = RK30_PIN0_PC4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
-};
-struct platform_device rk29_device_mw100 = {
- .name = "mw100",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mw100_info,
- }
- };
-#endif
-#if defined(CONFIG_MT6229)
-static int mt6229_io_init(void)
-{
- iomux_set(GPIO2_D5);
- iomux_set(GPIO0_C6);
- iomux_set(GPIO2_D4);
- iomux_set(GPIO0_C4);
- iomux_set(GPIO0_C5);
- return 0;
-}
-
-static int mt6229_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mt6229_data rk29_mt6229_info = {
- .io_init = mt6229_io_init,
- .io_deinit = mt6229_io_deinit,
- .modem_power_en = RK30_PIN2_PD5,
- .bp_power = RK30_PIN0_PC6,
- .bp_reset = RK30_PIN2_PD4,
- .ap_wakeup_bp = RK30_PIN0_PC4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
-};
-struct platform_device rk29_device_mt6229 = {
- .name = "mt6229",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mt6229_info,
- }
- };
-#endif
-
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN RK30_PIN0_PB7
-
-static int mma8452_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data mma8452_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma8452_init_platform_hw,
- .orientation = {-1, 0, 0, 0, -1, 0, 0, 0, 1},
-};
-#endif
-#if defined (CONFIG_GS_LIS3DH)
-#define LIS3DH_INT_PIN RK30_PIN0_PB7
-
-static int lis3dh_init_platform_hw(void)
-{
-
- return 0;
-}
-
-static struct sensor_platform_data lis3dh_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lis3dh_init_platform_hw,
- .orientation = {-1, 0, 0, 0, -1, 0, 0, 0, 1},
-};
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
-static struct sensor_platform_data akm8975_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-#if defined (CONFIG_COMPASS_AK8963)
-static struct sensor_platform_data akm8963_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .layout = 8,
- .m_layout =
- {
- //compass
- {
- {0, 1, 0},
- {-1, 0, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- //gsensor
- {
- {0, -1, 0},
- {1, 0, 0},
- {0, 0, -1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
-
- }
-};
-
-#endif
-
-
-#if defined(CONFIG_GYRO_L3G4200D)
-
-#include <linux/l3g4200d.h>
-#define L3G4200D_INT_PIN RK30_PIN0_PB4
-
-static int l3g4200d_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data l3g4200d_info = {
- .type = SENSOR_TYPE_GYROSCOPE,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
- .init_platform_hw = l3g4200d_init_platform_hw,
- .x_min = 40,//x_min,y_min,z_min = (0-100) according to hardware
- .y_min = 40,
- .z_min = 20,
-};
-
-#endif
-
-#ifdef CONFIG_LS_CM3217
-static struct sensor_platform_data cm3217_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 0,
- .poll_delay_ms = 500,
-};
-
-#endif
-
-#ifdef CONFIG_RK_HDMI
-#define RK_HDMI_RST_PIN RK30_PIN3_PB2
-static int rk_hdmi_power_init(void)
-{
- int ret;
-
- if(RK_HDMI_RST_PIN != INVALID_GPIO)
- {
- if (gpio_request(RK_HDMI_RST_PIN, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- gpio_direction_output(RK_HDMI_RST_PIN, GPIO_LOW);
- gpio_set_value(RK_HDMI_RST_PIN, GPIO_LOW);
- msleep(100);
- gpio_set_value(RK_HDMI_RST_PIN, GPIO_HIGH);
- msleep(50);
- }
- return 0;
-}
-static struct rk_hdmi_platform_data rk_hdmi_pdata = {
- .io_init = rk_hdmi_power_init,
-};
-#endif
-
-
-#ifdef CONFIG_FB_ROCKCHIP
-
-#define LCD_CS_PIN INVALID_GPIO
-#define LCD_CS_VALUE GPIO_HIGH
-
-#define LCD_EN_PIN RK30_PIN0_PB0
-#define LCD_EN_VALUE GPIO_HIGH
-
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
-
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_CS_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_CS_PIN);
- printk(KERN_ERR "request lcd cs pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_CS_PIN, LCD_CS_VALUE);
- }
- }
-
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_EN_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_EN_PIN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_EN_PIN, LCD_EN_VALUE);
- }
- }
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, !LCD_CS_VALUE);
- }
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, !LCD_EN_VALUE);
- }
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE);
- }
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
- }
- return 0;
-}
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
-struct rk29fb_info lcdc0_screen_info = {
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
-struct rk29fb_info lcdc1_screen_info = {
- #if defined(CONFIG_RK_HDMI)
- .prop = EXTEND, //extend display device
- .lcd_info = NULL,
- .set_screen_info = hdmi_init_lcdc,
- #endif
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-#if defined(CONFIG_ARCH_RK3188)
-static struct resource resource_mali[] = {
- [0] = {
- .name = "ump buf",
- .start = 0,
- .end = 0,
- .flags = IORESOURCE_MEM,
- },
-
-};
-
-static struct platform_device device_mali= {
- .name = "mali400_ump",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_mali),
- .resource = resource_mali,
-};
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
-static struct resource resource_lcdc0[] = {
- [0] = {
- .name = "lcdc0 reg",
- .start = RK30_LCDC0_PHYS,
- .end = RK30_LCDC0_PHYS + RK30_LCDC0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc0 irq",
- .start = IRQ_LCDC0,
- .end = IRQ_LCDC0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc0 = {
- .name = "rk30-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc0),
- .resource = resource_lcdc0,
- .dev = {
- .platform_data = &lcdc0_screen_info,
- },
-};
-#endif
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
-static struct resource resource_lcdc1[] = {
- [0] = {
- .name = "lcdc1 reg",
- .start = RK30_LCDC1_PHYS,
- .end = RK30_LCDC1_PHYS + RK30_LCDC1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc1 irq",
- .start = IRQ_LCDC1,
- .end = IRQ_LCDC1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc1 = {
- .name = "rk30-lcdc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resource_lcdc1),
- .resource = resource_lcdc1,
- .dev = {
- .platform_data = &lcdc1_screen_info,
- },
-};
-#endif
-
-#if defined(CONFIG_MFD_RK610)
-#define RK610_RST_PIN RK30_PIN2_PC5
-static int rk610_power_on_init(void)
-{
- int ret;
- if(RK610_RST_PIN != INVALID_GPIO)
- {
- ret = gpio_request(RK610_RST_PIN, "rk610 reset");
- if (ret)
- {
- printk(KERN_ERR "rk610_control_probe request gpio fail\n");
- }
- else
- {
- gpio_direction_output(RK610_RST_PIN, GPIO_HIGH);
- msleep(100);
- gpio_direction_output(RK610_RST_PIN, GPIO_LOW);
- msleep(100);
- gpio_set_value(RK610_RST_PIN, GPIO_HIGH);
- }
- }
-
- return 0;
-
-}
-
-
-static struct rk610_ctl_platform_data rk610_ctl_pdata = {
- .rk610_power_on_init = rk610_power_on_init,
-};
-#endif
-
-#ifdef CONFIG_SND_SOC_RK610
-static int rk610_codec_io_init(void)
-{
-//if need iomux.
-//Must not gpio_request
- return 0;
-}
-
-static struct rk610_codec_platform_data rk610_codec_pdata = {
- .spk_ctl_io = RK30_PIN4_PC6,
- .io_init = rk610_codec_io_init,
-};
-#endif
-
-#ifdef CONFIG_ANDROID_TIMED_GPIO
-static struct timed_gpio timed_gpios[] = {
- {
- .name = "vibrator",
- .gpio = INVALID_GPIO,
- .max_timeout = 1000,
- .active_low = 0,
- .adjust_time =20, //adjust for diff product
- },
-};
-
-static struct timed_gpio_platform_data rk29_vibrator_info = {
- .num_gpios = 1,
- .gpios = timed_gpios,
-};
-
-static struct platform_device rk29_device_vibrator = {
- .name = "timed-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_vibrator_info,
- },
-
-};
-#endif
-
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
-static struct gpio_led rk29_leds[] = {
- {
- .name = "button-backlight",
- .gpio = INVALID_GPIO,
- .default_trigger = "timer",
- .active_low = 0,
- .retain_state_suspended = 0,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- },
-};
-
-static struct gpio_led_platform_data rk29_leds_pdata = {
- .leds = rk29_leds,
- .num_leds = ARRAY_SIZE(rk29_leds),
-};
-
-static struct platform_device rk29_device_gpio_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_leds_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_RK_IRDA
-#define IRDA_IRQ_PIN INVALID_GPIO //RK30_PIN0_PA3
-
-static int irda_iomux_init(void)
-{
- int ret = 0;
-
- //irda irq pin
- ret = gpio_request(IRDA_IRQ_PIN, NULL);
- if (ret != 0) {
- gpio_free(IRDA_IRQ_PIN);
- printk(">>>>>> IRDA_IRQ_PIN gpio_request err \n ");
- }
- gpio_pull_updown(IRDA_IRQ_PIN, PullDisable);
- gpio_direction_input(IRDA_IRQ_PIN);
-
- return 0;
-}
-
-static int irda_iomux_deinit(void)
-{
- gpio_free(IRDA_IRQ_PIN);
- return 0;
-}
-
-static struct irda_info rk29_irda_info = {
- .intr_pin = IRDA_IRQ_PIN,
- .iomux_init = irda_iomux_init,
- .iomux_deinit = irda_iomux_deinit,
- //.irda_pwr_ctl = bu92747guw_power_ctl,
-};
-
-static struct platform_device irda_device = {
-#ifdef CONFIG_RK_IRDA_NET
- .name = "rk_irda",
-#else
- .name = "bu92747_irda",
-#endif
- .id = -1,
- .dev = {
- .platform_data = &rk29_irda_info,
- }
-};
-#endif
-
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and sdio.noted by xbw at 2012-03-05
-**************************************************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "../mach-rk30/board-rk3168-tb-sdmmc-conifg.c"
-#include "../plat-rk/rk-sdmmc-ops.c"
-#include "../plat-rk/rk-sdmmc-wifi.c"
-#endif //endif ---#ifdef CONFIG_SDMMC_RK29
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- iomux_set(MMC0_CMD);
- iomux_set(MMC0_CLKOUT);
- iomux_set(MMC0_D0);
- iomux_set(MMC0_D1);
- iomux_set(MMC0_D2);
- iomux_set(MMC0_D3);
-
- iomux_set_gpio_mode(iomux_mode_to_gpio(MMC0_DETN));
-
- gpio_request(RK30_PIN3_PA7, "sdmmc-power");
- gpio_direction_output(RK30_PIN3_PA7, GPIO_LOW);
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- #if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set_gpio_mode(iomux_gpio_to_mode(RK29SDK_SD_CARD_DETECT_N));
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO);
- #endif
- #else
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(MMC0_DETN);
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FMUX);
- #endif
- #endif
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) && defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- .status = rk29sdk_wifi_mmc0_status,
- .register_status_notify = rk29sdk_wifi_mmc0_status_register,
-#endif
-
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .power_en = RK29SDK_SD_CARD_PWR_EN,
- .power_en_level = RK29SDK_SD_CARD_PWR_EN_LEVEL,
-#else
- .power_en = INVALID_GPIO,
- .power_en_level = GPIO_LOW,
-#endif
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC0_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- .det_pin_info = {
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N, //INVALID_GPIO,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
- #endif
- },
-
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- iomux_set(MMC1_CMD);
- iomux_set(MMC1_CLKOUT);
- iomux_set(MMC1_D0);
- iomux_set(MMC1_D1);
- iomux_set(MMC1_D2);
- iomux_set(MMC1_D3);
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC) || defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC1_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- #if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
- .sdio_INT_gpio = RK29SDK_WIFI_SDIO_CARD_INT,
- #endif
-
- .det_pin_info = {
-#if defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- #else
- .io = INVALID_GPIO,
- #endif
-
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-
- .enable_sd_wakeup = 0,
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-/**************************************************************************************************
- * the end of setting for SDMMC devices
-**************************************************************************************************/
-
-#ifdef CONFIG_BATTERY_RK30_ADC
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = RK30_PIN0_PB2,
- .batt_low_pin = RK30_PIN0_PB1,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = RK30_PIN0_PA6,
- .dc_det_level = GPIO_LOW,
- .charge_ok_level = GPIO_HIGH,
-};
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-#ifdef CONFIG_CW2015_BATTERY
-/*
- note the follow array must set depend on the battery that you use
- you must send the battery to cellwise-semi the contact information:
- name: chen gan; tel:13416876079; E-mail: ben.chen@cellwise-semi.com
- */
-static u8 config_info[SIZE_BATINFO] = {
- 0x15, 0x42, 0x60, 0x59, 0x52,
- 0x58, 0x4D, 0x48, 0x48, 0x44,
- 0x44, 0x46, 0x49, 0x48, 0x32,
- 0x24, 0x20, 0x17, 0x13, 0x0F,
- 0x19, 0x3E, 0x51, 0x45, 0x08,
- 0x76, 0x0B, 0x85, 0x0E, 0x1C,
- 0x2E, 0x3E, 0x4D, 0x52, 0x52,
- 0x57, 0x3D, 0x1B, 0x6A, 0x2D,
- 0x25, 0x43, 0x52, 0x87, 0x8F,
- 0x91, 0x94, 0x52, 0x82, 0x8C,
- 0x92, 0x96, 0xFF, 0x7B, 0xBB,
- 0xCB, 0x2F, 0x7D, 0x72, 0xA5,
- 0xB5, 0xC1, 0x46, 0xAE
-};
-
-static struct cw_bat_platform_data cw_bat_platdata = {
- .dc_det_pin = RK30_PIN0_PB2,
- .bat_low_pin = INVALID_GPIO,//RK30_PIN0_PB1,
- .chg_ok_pin = RK30_PIN0_PA6,
- .dc_det_level = GPIO_LOW,
- .bat_low_level = GPIO_LOW,
- .chg_ok_level = GPIO_HIGH,
-
- .cw_bat_config_info = config_info,
-
-};
-
-#endif
-#ifdef CONFIG_RK30_PWM_REGULATOR
-static int pwm_voltage_map[] = {
- 800000,825000,850000, 875000,900000, 925000 ,950000, 975000,1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000,1375000
-};
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_cpu",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] =
-{
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
- .pwm_id = 1,
- .pwm_gpio = RK30_PIN3_PD4,
- .pwm_iomux_pwm = PWM1,
- .pwm_iomux_gpio = GPIO3_D4,
- .pwm_voltage = 1100000,
- .suspend_voltage = 1000000,
- .min_uV = 800000,
- .max_uV = 1375000,
- .coefficient = 575, //57.5%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-#endif
-
-#ifdef CONFIG_RK29_VMAC
-#define PHY_PWR_EN_GPIO RK30_PIN0_PC0
-#define PHY_PWR_EN_IOMUX GPIO0_C0
-#define PHY_PWR_EN_VALUE GPIO_HIGH
-#include "../mach-rk30/board-rk31-sdk-vmac.c"
-
-#endif
-
-#ifdef CONFIG_RFKILL_RK
-// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
-static struct rfkill_rk_platform_data rfkill_rk_platdata = {
- .type = RFKILL_TYPE_BLUETOOTH,
-
- .poweron_gpio = { // BT_REG_ON
- .io = RK30_PIN3_PC7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_poweron",
- .fgpio = GPIO3_C7,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN3_PD1, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_reset",
- .fgpio = GPIO3_D1,
- },
- },
-
- .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
- .io = RK30_PIN3_PC6, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_wake",
- .fgpio = GPIO3_C6,
- },
- },
-
- .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .gpio = {
- .io = RK30_PIN0_PA5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
- .iomux = {
- .name = NULL,
- },
- },
- },
-
- .rts_gpio = { // UART_RTS, enable or disable BT's data coming
- .io = RK30_PIN1_PA3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_rts",
- .fgpio = GPIO1_A3,
- .fmux = UART0_RTSN,
- },
- },
-};
-
-static struct platform_device device_rfkill_rk = {
- .name = "rfkill_rk",
- .id = -1,
- .dev = {
- .platform_data = &rfkill_rk_platdata,
- },
-};
-#endif
-
-#if defined(CONFIG_GPS_RK)
-int rk_gps_io_init(void)
-{
- printk("%s \n", __FUNCTION__);
-
- gpio_request(RK30_PIN1_PB5, NULL);
- gpio_direction_output(RK30_PIN1_PB5, GPIO_LOW);
-
- iomux_set(GPS_RFCLK);//GPS_CLK
- iomux_set(GPS_MAG);//GPS_MAG
- iomux_set(GPS_SIG);//GPS_SIGN
-
- gpio_request(RK30_PIN1_PA6, NULL);
- gpio_direction_output(RK30_PIN1_PA6, GPIO_LOW);
-
- gpio_request(RK30_PIN1_PA5, NULL);
- gpio_direction_output(RK30_PIN1_PA5, GPIO_LOW);
-
- gpio_request(RK30_PIN1_PA7, NULL);
- gpio_direction_output(RK30_PIN1_PA7, GPIO_LOW);
- return 0;
-}
-int rk_gps_power_up(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_power_down(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_reset_set(int level)
-{
- return 0;
-}
-int rk_enable_hclk_gps(void)
-{
- struct clk *gps_aclk = NULL;
- gps_aclk = clk_get(NULL, "aclk_gps");
- if(gps_aclk) {
- clk_enable(gps_aclk);
- clk_put(gps_aclk);
- printk("%s \n", __FUNCTION__);
- }
- else
- printk("get gps aclk fail\n");
- return 0;
-}
-int rk_disable_hclk_gps(void)
-{
- struct clk *gps_aclk = NULL;
- gps_aclk = clk_get(NULL, "aclk_gps");
- if(gps_aclk) {
- //TO wait long enough until GPS ISR is finished.
- msleep(5);
- clk_disable(gps_aclk);
- clk_put(gps_aclk);
- printk("%s \n", __FUNCTION__);
- }
- else
- printk("get gps aclk fail\n");
- return 0;
-}
-struct rk_gps_data rk_gps_info = {
- .io_init = rk_gps_io_init,
- .power_up = rk_gps_power_up,
- .power_down = rk_gps_power_down,
- .reset = rk_gps_reset_set,
- .enable_hclk_gps = rk_enable_hclk_gps,
- .disable_hclk_gps = rk_disable_hclk_gps,
- .GpsSign = RK30_PIN1_PB3,
- .GpsMag = RK30_PIN1_PB2, //GPIO index
- .GpsClk = RK30_PIN1_PB4, //GPIO index
- .GpsVCCEn = RK30_PIN1_PB5, //GPIO index
- .GpsSpi_CSO = RK30_PIN1_PA4, //GPIO index
- .GpsSpiClk = RK30_PIN1_PA5, //GPIO index
- .GpsSpiMOSI = RK30_PIN1_PA7, //GPIO index
- .GpsIrq = IRQ_GPS,
- .GpsSpiEn = 0,
- .GpsAdcCh = 2,
- .u32GpsPhyAddr = RK30_GPS_PHYS,
- .u32GpsPhySize = RK30_GPS_SIZE,
-};
-
-struct platform_device rk_device_gps = {
- .name = "gps_hv5820b",
- .id = -1,
- .dev = {
- .platform_data = &rk_gps_info,
- }
- };
-#endif
-
-#if defined(CONFIG_MT5931_MT6622)
-static struct mt6622_platform_data mt6622_platdata = {
- .power_gpio = { // BT_REG_ON
- .io = RK30_PIN3_PD5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN0_PD7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .irq_gpio = {
- .io = RK30_PIN3_PD2,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- }
-};
-
-static struct platform_device device_mt6622 = {
- .name = "mt6622",
- .id = -1,
- .dev = {
- .platform_data = &mt6622_platdata,
- },
-};
-#endif
-
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_ANDROID_TIMED_GPIO
- &rk29_device_vibrator,
-#endif
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
- &rk29_device_gpio_leds,
-#endif
-#ifdef CONFIG_RK_IRDA
- &irda_device,
-#endif
-#if defined(CONFIG_WIFI_CONTROL_FUNC)||defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- &rk29sdk_wifi_device,
-#endif
-
-#if defined(CONFIG_MT6620)
- &mt3326_device_gps,
-#endif
-
-#ifdef CONFIG_RK29_SUPPORT_MODEM
- &rk30_device_modem,
-#endif
-#if defined(CONFIG_MU509)
- &rk29_device_mu509,
-#endif
-#if defined(CONFIG_MW100)
- &rk29_device_mw100,
-#endif
-#if defined(CONFIG_MT6229)
- &rk29_device_mt6229,
-#endif
-#ifdef CONFIG_BATTERY_RK30_ADC
- &rk30_device_adc_battery,
-#endif
-#ifdef CONFIG_RFKILL_RK
- &device_rfkill_rk,
-#endif
-#ifdef CONFIG_GPS_RK
- &rk_device_gps,
-#endif
-#if defined(CONFIG_ARCH_RK3188)
- &device_mali,
-#endif
-#ifdef CONFIG_MT5931_MT6622
- &device_mt6622,
-#endif
-};
-
-static int rk_platform_add_display_devices(void)
-{
- struct platform_device *fb = NULL; //fb
- struct platform_device *lcdc0 = NULL; //lcdc0
- struct platform_device *lcdc1 = NULL; //lcdc1
- struct platform_device *bl = NULL; //backlight
-#ifdef CONFIG_FB_ROCKCHIP
- fb = &device_fb;
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
- lcdc0 = &device_lcdc0,
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
- lcdc1 = &device_lcdc1,
-#endif
-
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- bl = &rk29_device_backlight,
-#endif
- __rk_platform_add_display_devices(fb,lcdc0,lcdc1,bl);
-
- return 0;
-
-}
-
-// i2c
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1d,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_GS_LIS3DH)
- {
- .type = "gs_lis3dh",
- .addr = 0x19, //0x19(SA0-->VCC), 0x18(SA0-->GND)
- .flags = 0,
- .irq = LIS3DH_INT_PIN,
- .platform_data = &lis3dh_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8975_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8963)
- {
- .type = "ak8963",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8963_info,
- },
-#endif
-
-#if defined (CONFIG_GYRO_L3G4200D)
- {
- .type = "l3g4200d_gryo",
- .addr = 0x69,
- .flags = 0,
- .irq = L3G4200D_INT_PIN,
- .platform_data = &l3g4200d_info,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RT5631)
- {
- .type = "rt5631",
- .addr = 0x1a,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RT5640)
- {
- .type = "rt5640",
- .addr = 0x1c,
- .flags = 0,
- },
-#endif
-#ifdef CONFIG_MFD_RK610
- {
- .type = "rk610_ctl",
- .addr = 0x40,
- .flags = 0,
- .platform_data = &rk610_ctl_pdata,
- },
-#ifdef CONFIG_RK610_TVOUT
- {
- .type = "rk610_tvout",
- .addr = 0x42,
- .flags = 0,
- },
-#endif
-#ifdef CONFIG_HDMI_RK610
- {
- .type = "rk610_hdmi",
- .addr = 0x46,
- .flags = 0,
- .irq = INVALID_GPIO,
- },
-#endif
-#ifdef CONFIG_SND_SOC_RK610
- {//RK610_CODEC addr from 0x60 to 0x80 (0x60~0x80)
- .type = "rk610_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- .platform_data = &rk610_codec_pdata,
- },
-#endif
-#endif
-
-#if defined (CONFIG_CW2015_BATTERY)
- {
- .type = "cw201x",
- .addr = 0x62,
- .flags = 0,
- .platform_data = &cw_bat_platdata,
- },
-#endif
-
-};
-#endif
-
-int __sramdata g_pmic_type = 0;
-#ifdef CONFIG_I2C1_RK30
-#ifdef CONFIG_MFD_WM831X_I2C
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info wm8326_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "dcdc3", //ddr
- .min_uv = 1150000,
- .max_uv = 1150000,
- .suspend_vol = 1150000,
- },
- #ifdef CONFIG_MACH_RK3066_SDK
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3000000,
- },
- #else
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3000000,
- .max_uv = 3000000,
- .suspend_vol = 2800000,
- },
- #endif
-};
-
-static struct pmu_info wm8326_ldo_info[] = {
- {
- .name = "ldo1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo2", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo3", //
- .min_uv = 1100000,
- .max_uv = 1100000,
- .suspend_vol = 1100000,
- },
- {
- .name = "ldo4", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 1000000,
- },
- {
- .name = "ldo5", //vcc25
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo6", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo7", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- .suspend_vol = 2800000,
- },
- {
- .name = "ldo8", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo9", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo10", //flash_io
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
-};
-
-#include "../mach-rk30/board-pmu-wm8326.c"
-#endif
-
-#ifdef CONFIG_MFD_TPS65910
-#define TPS65910_HOST_IRQ RK30_PIN0_PB3
-
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info tps65910_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1100000,
- .max_uv = 1100000,
- },
- {
- .name = "vdd2", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vio", //vcc_io
- .min_uv = 2500000,
- .max_uv = 2500000,
- },
-
-};
-static struct pmu_info tps65910_ldo_info[] = {
- {
- .name = "vpll", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "vdig2", //vdd_jetta
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vaux1", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "vaux2", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vaux33", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vmmc", //vcc30
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
- {
- .name = "vdac", //vcc18
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- };
-
-#include "../mach-rk30/board-pmu-tps65910.c"
-#endif
-
-#ifdef CONFIG_REGULATOR_ACT8846
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-#define PMU_VSEL RK30_PIN3_PD3
-static struct pmu_info act8846_dcdc_info[] = {
- {
- .name = "act_dcdc1", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- .suspend_vol = 1200000,
- },
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 1200000,
- #else
- .suspend_vol = 900000,
- #endif
-
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 1200000,
- #else
- .suspend_vol = 900000,
- #endif
-
- },
- {
- .name = "act_dcdc4", //vccio
- .min_uv = 3000000,
- .max_uv = 3000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 3000000,
- #else
- .suspend_vol = 2800000,
- #endif
-
- },
-
-};
-static struct pmu_info act8846_ldo_info[] = {
- {
- .name = "act_ldo1", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "act_ldo2", //vdd12
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "act_ldo3", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo4", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo5", //vcctp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo6", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo7", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo8", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- };
-
-#include "../mach-rk30/board-pmu-act8846.c"
-#endif
-
-#ifdef CONFIG_MFD_RK808
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-#define RK808_HOST_IRQ RK30_PIN0_PB3
-
-static struct pmu_info rk808_dcdc_info[] = {
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1100000,
- .max_uv = 1100000,
- .suspend_vol = 900000,
- },
- {
- .name = "vdd_core", //logic
- .min_uv = 1100000,
- .max_uv = 1100000,
- .suspend_vol = 900000,
- },
- {
- .name = "rk_dcdc3", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- .suspend_vol = 1200000,
- },
- {
- .name = "rk_dcdc4", //vccio
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3000000,
- },
-
-};
-static struct pmu_info rk808_ldo_info[] = {
- {
- .name = "rk_ldo1", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "rk_ldo2", //vcctp
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
-
- },
- {
- .name = "rk_ldo3", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 1000000,
- },
- {
- .name = "rk_ldo4", //vcc18
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "rk_ldo5", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- .suspend_vol = 2800000,
- },
- {
- .name = "rk_ldo6", //vdd12
- .min_uv = 1200000,
- .max_uv = 1200000,
- .suspend_vol = 1200000,
- },
- {
- .name = "rk_ldo7", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "rk_ldo8", //vcca_33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- };
-
-#include "../mach-rk30/board-pmu-rk808.c"
-#endif
-
-
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_MFD_WM831X_I2C)
- {
- .type = "wm8326",
- .addr = 0x34,
- .flags = 0,
- .irq = RK30_PIN0_PB3,
- .platform_data = &wm831x_platdata,
- },
-#endif
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-
-#if defined (CONFIG_REGULATOR_ACT8846)
- {
- .type = "act8846",
- .addr = 0x5a,
- .flags = 0,
- // .irq = ACT8846_HOST_IRQ,
- .platform_data=&act8846_data,
- },
-#endif
-#if defined (CONFIG_MFD_RK808)
- {
- .type = "rk808",
- .addr = 0x1b,
- .flags = 0,
- // .irq = ACT8846_HOST_IRQ,
- .platform_data=&rk808_data,
- },
-#endif
-
-#if defined (CONFIG_RTC_HYM8563)
- {
- .type = "rtc_hym8563",
- .addr = 0x51,
- .flags = 0,
- .irq = RK30_PIN1_PA4,
- },
-#endif
-
-};
-#endif
-
-void __sramfunc board_pmu_suspend(void)
-{
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_suspend();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_suspend();
- #endif
- #if defined (CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- board_pmu_act8846_suspend();
- #endif
- #if defined (CONFIG_MFD_RK808)
- if(pmic_is_rk808())
- board_pmu_rk808_suspend();
- #endif
-
-}
-
-void __sramfunc board_pmu_resume(void)
-{
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_resume();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_resume();
- #endif
- #if defined (CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- board_pmu_act8846_resume();
- #endif
- #if defined (CONFIG_MFD_RK808)
- if(pmic_is_rk808())
- board_pmu_rk808_resume();
- #endif
-
-}
-
- int __sramdata gpio3d6_iomux,gpio3d6_do,gpio3d6_dir,gpio3d6_en;
-
-#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
-
-void __sramfunc rk30_pwm_logic_suspend_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
-
-// int gpio0d7_iomux,gpio0d7_do,gpio0d7_dir,gpio0d7_en;
- sram_udelay(10000);
- gpio3d6_iomux = grf_readl(GRF_GPIO3D_IOMUX);
- gpio3d6_do = grf_readl(GRF_GPIO3H_DO);
- gpio3d6_dir = grf_readl(GRF_GPIO3H_DIR);
- gpio3d6_en = grf_readl(GRF_GPIO3H_EN);
-
- grf_writel((1<<28), GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DIR);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DO);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_EN);
-#endif
-}
-void __sramfunc rk30_pwm_logic_resume_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- grf_writel((1<<28)|gpio3d6_iomux, GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|gpio3d6_en, GRF_GPIO3H_EN);
- grf_writel((1<<30)|gpio3d6_dir, GRF_GPIO3H_DIR);
- grf_writel((1<<30)|gpio3d6_do, GRF_GPIO3H_DO);
- sram_udelay(10000);
-
-#endif
-
-}
-extern void pwm_suspend_voltage(void);
-extern void pwm_resume_voltage(void);
-void rk30_pwm_suspend_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_suspend_voltage();
-#endif
-}
-void rk30_pwm_resume_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_resume_voltage();
-#endif
-}
-
-
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-#if defined (CONFIG_TOUCHSCREEN_GT8XX)
- {
- .type = "Goodix-TS",
- .addr = 0x55,
- .flags = 0,
- .irq = RK30_PIN1_PB7,
- .platform_data = &goodix_info,
- },
-#endif
-#if defined (CONFIG_LS_CM3217)
- {
- .type = "lightsensor",
- .addr = 0x10,
- .flags = 0,
- .platform_data = &cm3217_info,
- },
-#endif
-#if defined(CONFIG_HDMI_CAT66121)
- {
- .type = "cat66121_hdmi",
- .addr = 0x4c,
- .flags = 0,
- .irq = RK30_PIN2_PD6,
- .platform_data = &rk_hdmi_pdata,
- },
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C4_RK30
-static struct i2c_board_info __initdata i2c4_info[] = {
- #if defined (CONFIG_SND_SOC_RT5616)
- {
- .type = "rt5616",
- .addr = 0x1b,
- .flags = 0,
-
- },
- #endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO// RK30_PIN2_PD6 //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO//RK30_PIN2_PD7 //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- //set iomux (gpio) here
- //rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME, GPIO2D_GPIO2D7);
- //rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME, GPIO2D_GPIO2D6);
-
- return 0;
-}
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C4_RK30
- i2c_register_board_info(4, i2c4_info, ARRAY_SIZE(i2c4_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(5, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-
-// ========== Begin of rk3168 top board keypad defination ============
-
-#include <plat/key.h>
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .adc_value = 174,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK30_PIN0_PA4,
- .active_low = PRESS_LEV_LOW,
- .wakeup = 1,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .adc_value = 1,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "menu",
- .code = EV_MENU,
- .adc_value = 360,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .adc_value = 750,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .adc_value = 564,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "camera",
- .code = KEY_CAMERA,
- .adc_value = 742,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = 1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
-// =========== End of rk3168 top board keypad defination =============
-
-
-#define POWER_ON_PIN RK30_PIN0_PA0 //power_hold
-static void rk30_pm_power_off(void)
-{
- printk(KERN_ERR "rk30_pm_power_off start...\n");
- #if defined(CONFIG_MFD_WM831X)
- if(pmic_is_wm8326()){
- wm831x_set_bits(Wm831x,WM831X_GPIO_LEVEL,0x0001,0x0000); //set sys_pwr 0
- wm831x_device_shutdown(Wm831x);//wm8326 shutdown
- }
- #endif
-
- #if defined(CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- {
- act8846_device_shutdown();
- }
- #endif
-
- #if defined(CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- {
- tps65910_device_shutdown();//tps65910 shutdown
- }
- #endif
-
- #if defined(CONFIG_MFD_RK808)
- if(pmic_is_rk808())
- {
- rk808_device_shutdown();//rk808 shutdown
- }
- #endif
-
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
- while (1);
-}
-
-
-#if defined(CONFIG_BOARD_ID)
-static int board_id_init(void)
-{
-
- return 0;
-}
-
-static int board_id_deinit(void)
-{
-
- return 0;
-}
-
-#if defined(CONFIG_BOARD_ID_FLASH)
-static struct valid_invalid_name __initdata valid_device_name[] = {
- {"rk-fb"},
- {"mali400_ump"},
- {"rk30-lcdc"},
- {"ion-rockchip"},
-
- {"a10_tp_syn"},
-
- //pmic
- {"act8846"},
- {"wm8326"},
- {"tps65910"},
-
- /*angle*/
- {"angle_kxtik"},
- {"angle_lis3dh"},
- {"angle_mma7660"},
- /*gsensor*/
- {"gsensor"},
- {"gs_mma8452"},
- {"gs_kxtik"},
- {"gs_kxtj9"},
- {"gs_lis3dh"},
- {"gs_mma7660"},
- {"gs_mxc6225"},
- /*compass*/
- {"compass"},
- {"ak8975"},
- {"ak8963"},
- {"ak09911"},
- {"mmc314x"},
- /*gyroscope*/
- {"gyro"},
- {"l3g4200d_gryo"},
- {"l3g20d_gryo"},
- {"k3g"},
- /*light sensor*/
- {"lightsensor"},
- {"light_cm3217"},
- {"light_cm3232"},
- {"light_al3006"},
- {"ls_stk3171"},
- {"ls_isl29023"},
- {"ls_ap321xx"},
- {"ls_photoresistor"},
- {"ls_us5152"},
- /*proximity sensor*/
- {"psensor"},
- {"proximity_al3006"},
- {"ps_stk3171"},
- {"ps_ap321xx"},
-
- /*temperature*/
- {"temperature"},
- {"tmp_ms5607"},
-
- /*pressure*/
- {"pressure"},
- {"pr_ms5607"},
-
- {"rk610_ctl"},
-
- {"rk-lid"},
- {"rt3261"},
-};
-
-
-static struct valid_invalid_name __initdata invalid_device_name[5] = {
- {"st480"},
- {"rk1000_i2c_codec"},
- {"rk1000_control"},
-
- {"leds-lm3642"},
- {"leds-lm2759"},
-};
-
-
-
-static struct board_device_table __initdata device_table[] = {
- //don't move
- {.addr = (int *)valid_device_name, .size = ARRAY_SIZE(valid_device_name), .type = BOARD_DEVICE_TYPE_VALID},
- {.addr = (int *)invalid_device_name, .size = ARRAY_SIZE(invalid_device_name), .type = BOARD_DEVICE_TYPE_INVALID},
-
-
-#if defined(CONFIG_I2C0_RK30)
- {.addr = (int *)i2c0_info, .size = ARRAY_SIZE(i2c0_info), .type = BOARD_DEVICE_TYPE_I2C, .bus = BUS_NUM_I2C_0},
-#endif
-#if defined(CONFIG_I2C1_RK30)
- {.addr = (int *)i2c1_info, .size = ARRAY_SIZE(i2c1_info), .type = BOARD_DEVICE_TYPE_I2C, .bus = BUS_NUM_I2C_1},
-#endif
-#if defined(CONFIG_I2C2_RK30)
- {.addr = (int *)i2c2_info, .size = ARRAY_SIZE(i2c2_info), .type = BOARD_DEVICE_TYPE_I2C, .bus = BUS_NUM_I2C_2},
-#endif
-#if defined(CONFIG_I2C3_RK30)
- {.addr = (int *)i2c3_info, .size = ARRAY_SIZE(i2c3_info), .type = BOARD_DEVICE_TYPE_I2C, .bus = BUS_NUM_I2C_3},
-#endif
-#if defined(CONFIG_I2C4_RK30)
- {.addr = (int *)i2c4_info, .size = ARRAY_SIZE(i2c4_info), .type = BOARD_DEVICE_TYPE_I2C, .bus = BUS_NUM_I2C_4},
-#endif
-#if defined(CONFIG_I2C_GPIO_RK30)
- {.addr = (int *)i2c_gpio_info, .size = ARRAY_SIZE(i2c_gpio_info), .type = BOARD_DEVICE_TYPE_I2C, .bus = BUS_NUM_I2C_GPIO},
-#endif
- {.addr = (int *)board_spi_devices, .size = ARRAY_SIZE(board_spi_devices), .type = BOARD_DEVICE_TYPE_SPI},
- {.addr = (int *)devices, .size = ARRAY_SIZE(devices), .type = BOARD_DEVICE_TYPE_PLATFORM},
-
-};
-#endif
-
-
-#if defined(CONFIG_BOARD_ID_HW)
-static int board_id_hw_init_paramter(int id)
-{
- if(id < 0)
- return -1;
-
- switch(id)
- {
- case BOARD_ID_DS763:
- //to do
- break;
- case BOARD_ID_AIO_BAT:
- //to do
- break;
- default:
- break;
-
- }
-
- return 0;
-}
-#endif
-
-
-static struct board_id_platform_data board_id_info = {
- .init_platform_hw = board_id_init,
- .exit_platform_hw = board_id_deinit,
-
-#if defined(CONFIG_BOARD_ID_FLASH)
- //board_id_flash
- .device_table_size = ARRAY_SIZE(device_table),
-#endif
-
-#if defined(CONFIG_BOARD_ID_HW)
- //or board_id_hw
- .gpio_pin = {RK30_PIN0_PC4,RK30_PIN0_PC5,RK30_PIN0_PC6,RK30_PIN0_PC7},
- .num_gpio = 4,
- .init_parameter = board_id_hw_init_paramter,
-#endif
-};
-
-
-static struct platform_device device_board_id = {
-#if defined(CONFIG_BOARD_ID_FLASH)
- .name = "board_id",
-#elif defined(CONFIG_BOARD_ID_HW)
- .name = "board_id_hw",
-#endif
- .id = -1,
- .dev = {
- .platform_data = &board_id_info,
- },
-
-};
-
-
-static struct platform_device *devices_id[] __initdata = {
- &device_board_id,
-};
-
-#endif
-
-
-static void __init machine_rk30_board_init(void)
-{
- //avs_init();
- gpio_request(POWER_ON_PIN, "poweronpin");
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
- pm_power_off = rk30_pm_power_off;
-
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
-#if defined(CONFIG_BOARD_ID)
- #if defined(CONFIG_BOARD_ID_FLASH)
- board_id_info.device_table = device_table;
- platform_add_devices(devices_id, ARRAY_SIZE(devices_id));
- rk_platform_add_display_devices();
-
- #elif defined(CONFIG_BOARD_ID_HW)
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- rk_platform_add_display_devices();
- platform_add_devices(devices_id, ARRAY_SIZE(devices_id));
- #endif
-#else
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- rk_platform_add_display_devices();
-#endif
- board_usb_detect_init(RK30_PIN0_PA7);
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC)
- rk29sdk_wifi_bt_gpio_control_init();
-#elif defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- rk29sdk_wifi_combo_module_gpio_init();
-#endif
-
-#if defined(CONFIG_MT6620)
- clk_set_rate(clk_get_sys("rk_serial.0", "uart"), 48*1000000);
-#endif
-
-#if defined(CONFIG_MT5931_MT6622)
- clk_set_rate(clk_get_sys("rk_serial.0", "uart"), 24*1000000);
-#endif
-}
-#define HD_SCREEN_SIZE 1920UL*1200UL*4*3
-static void __init rk30_reserve(void)
-{
-#if defined(CONFIG_ARCH_RK3188)
- /*if lcd resolution great than or equal to 1920*1200,reserve the ump memory */
- if(!(get_fb_size() < ALIGN(HD_SCREEN_SIZE,SZ_1M)))
- {
- int ump_mem_phy_size=512UL*1024UL*1024UL;
- resource_mali[0].start = board_mem_reserve_add("ump buf", ump_mem_phy_size);
- resource_mali[0].end = resource_mali[0].start + ump_mem_phy_size -1;
- }
-#endif
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0 buf", get_fb_size());
- resource_fb[0].end = resource_fb[0].start + get_fb_size()- 1;
-#if 0
- resource_fb[1].start = board_mem_reserve_add("ipp buf", RK30_FB0_MEM_SIZE);
- resource_fb[1].end = resource_fb[1].start + RK30_FB0_MEM_SIZE - 1;
-#endif
-
-#if defined(CONFIG_FB_ROTATE) || !defined(CONFIG_THREE_FB_BUFFER)
- resource_fb[2].start = board_mem_reserve_add("fb2 buf",get_fb_size());
- resource_fb[2].end = resource_fb[2].start + get_fb_size() - 1;
-#endif
-#endif
-
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
-
-#ifdef CONFIG_GPS_RK
- //it must be more than 8MB
- rk_gps_info.u32MemoryPhyAddr = board_mem_reserve_add("gps", SZ_8M);
-#endif
- board_mem_reserved();
-}
-/******************************** arm dvfs frequency volt table **********************************/
-/**
- * dvfs_cpu_logic_table: table for arm and logic dvfs
- * @frequency : arm frequency
- * @cpu_volt : arm voltage depend on frequency
- */
-
-#if defined(CONFIG_ARCH_RK3188)
-//sdk
-static struct cpufreq_frequency_table dvfs_arm_table_volt_level0[] = {
- {.frequency = 312 * 1000, .index = 850 * 1000},
- {.frequency = 504 * 1000, .index = 900 * 1000},
- {.frequency = 816 * 1000, .index = 950 * 1000},
- {.frequency = 1008 * 1000, .index = 1025 * 1000},
- {.frequency = 1200 * 1000, .index = 1100 * 1000},
- {.frequency = 1416 * 1000, .index = 1200 * 1000},
- {.frequency = 1608 * 1000, .index = 1300 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-//default
-static struct cpufreq_frequency_table dvfs_arm_table_volt_level1[] = {
- {.frequency = 312 * 1000, .index = 875 * 1000},
- {.frequency = 504 * 1000, .index = 925 * 1000},
- {.frequency = 816 * 1000, .index = 975 * 1000},
- {.frequency = 1008 * 1000, .index = 1075 * 1000},
- {.frequency = 1200 * 1000, .index = 1150 * 1000},
- {.frequency = 1416 * 1000, .index = 1250 * 1000},
- {.frequency = 1608 * 1000, .index = 1350 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-// cube 10'
-static struct cpufreq_frequency_table dvfs_arm_table_volt_level2[] = {
- {.frequency = 312 * 1000, .index = 900 * 1000},
- {.frequency = 504 * 1000, .index = 925 * 1000},
- {.frequency = 816 * 1000, .index = 1000 * 1000},
- {.frequency = 1008 * 1000, .index = 1075 * 1000},
- {.frequency = 1200 * 1000, .index = 1200 * 1000},
- {.frequency = 1416 * 1000, .index = 1250 * 1000},
- {.frequency = 1608 * 1000, .index = 1350 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-/******************************** gpu dvfs frequency volt table **********************************/
-//sdk
-static struct cpufreq_frequency_table dvfs_gpu_table_volt_level0[] = {
- {.frequency = 133 * 1000, .index = 975 * 1000},//the mininum rate is limited 133M for rk3188
- {.frequency = 200 * 1000, .index = 975 * 1000},
- {.frequency = 266 * 1000, .index = 1000 * 1000},
- {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1100 * 1000},
- {.frequency = 600 * 1000, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-//cube 10'
-static struct cpufreq_frequency_table dvfs_gpu_table_volt_level1[] = {
- {.frequency = 133 * 1000, .index = 975 * 1000},//the mininum rate is limited 133M for rk3188
- {.frequency = 200 * 1000, .index = 1000 * 1000},
- {.frequency = 266 * 1000, .index = 1025 * 1000},
- {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1100 * 1000},
- {.frequency = 600 * 1000, .index = 1250 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-/******************************** ddr dvfs frequency volt table **********************************/
-static struct cpufreq_frequency_table dvfs_ddr_table_volt_level0[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 950 * 1000},
- {.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = 1000 * 1000},
- {.frequency = 396 * 1000 + DDR_FREQ_NORMAL, .index = 1100 * 1000},
- //{.frequency = 528 * 1000 + DDR_FREQ_NORMAL, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-//if you board is good for volt quality,select dvfs_arm_table_volt_level0
-#define dvfs_arm_table dvfs_arm_table_volt_level1
-#define dvfs_gpu_table dvfs_gpu_table_volt_level1
-#define dvfs_ddr_table dvfs_ddr_table_volt_level0
-
-#else
-//for RK3168 && RK3066B
-static struct cpufreq_frequency_table dvfs_arm_table[] = {
- {.frequency = 312 * 1000, .index = 950 * 1000},
- {.frequency = 504 * 1000, .index = 1000 * 1000},
- {.frequency = 816 * 1000, .index = 1050 * 1000},
- {.frequency = 1008 * 1000, .index = 1125 * 1000},
- {.frequency = 1200 * 1000, .index = 1200 * 1000},
- //{.frequency = 1416 * 1000, .index = 1250 * 1000},
- //{.frequency = 1608 * 1000, .index = 1300 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- {.frequency = 100 * 1000, .index = 1000 * 1000},
- {.frequency = 200 * 1000, .index = 1000 * 1000},
- {.frequency = 266 * 1000, .index = 1050 * 1000},
- //{.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1125 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 1000 * 1000},
- {.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = 1050 * 1000},
- {.frequency = 400 * 1000 + DDR_FREQ_NORMAL, .index = 1100 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-#endif
-/******************************** arm dvfs frequency volt table end **********************************/
-//#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
-//static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
-//static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
-
-void __init board_clock_init(void)
-{
- rk30_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
- //dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "cpu"), dvfs_arm_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
-}
-
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk30_fixup,
- .reserve = &rk30_reserve,
- .map_io = rk30_map_io,
- .init_irq = rk30_init_irq,
- .timer = &rk30_timer,
- .init_machine = machine_rk30_board_init,
-MACHINE_END
+++ /dev/null
-#ifdef CONFIG_VIDEO_RK29
-#include <plat/rk_camera.h>
-/* Notes:
-
-Simple camera device registration:
-
- new_camera_device(sensor_name,\ // sensor name, it is equal to CONFIG_SENSOR_X
- face,\ // sensor face information, it can be back or front
- pwdn_io,\ // power down gpio configuration, it is equal to CONFIG_SENSOR_POWERDN_PIN_XX
- flash_attach,\ // sensor is attach flash or not
- mir,\ // sensor image mirror and flip control information
- i2c_chl,\ // i2c channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_IIC_ADAPTER_ID_X
- cif_chl) \ // cif channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_CIF_INDEX_X
-
-Comprehensive camera device registration:
-
- new_camera_device_ex(sensor_name,\
- face,\
- ori,\ // sensor orientation, it is equal to CONFIG_SENSOR_ORIENTATION_X
- pwr_io,\ // sensor power gpio configuration, it is equal to CONFIG_SENSOR_POWER_PIN_XX
- pwr_active,\ // sensor power active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- rst_io,\ // sensor reset gpio configuration, it is equal to CONFIG_SENSOR_RESET_PIN_XX
- rst_active,\ // sensor reset active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- pwdn_io,\
- pwdn_active,\ // sensor power down active level, is equal to CONFIG_SENSOR_POWERDNACTIVE_LEVEL_X
- flash_attach,\
- res,\ // sensor resolution, this is real resolution or resoltuion after interpolate
- mir,\
- i2c_chl,\
- i2c_spd,\ // i2c speed , 100000 = 100KHz
- i2c_addr,\ // the i2c slave device address for sensor
- cif_chl,\
- mclk)\ // sensor input clock rate, 24 or 48
-
-*/
-static struct rkcamera_platform_data new_camera[] = {
- new_camera_device_ex(RK29_CAM_SENSOR_OV5640,
- back,
- INVALID_VALUE,
- INVALID_VALUE,
- INVALID_VALUE,
- INVALID_VALUE,
- INVALID_VALUE,
- RK30_PIN3_PB4,
- CONS(RK29_CAM_SENSOR_OV5640,_PWRDN_ACTIVE),
- 1,
- CONS(RK29_CAM_SENSOR_OV5640,_FULL_RESOLUTION),
- 0x00,
- 3,
- 100000,
- CONS(RK29_CAM_SENSOR_OV5640,_I2C_ADDR),
- 0,
- 24),
- new_camera_device(RK29_CAM_SENSOR_OV2659,
- front,
- RK30_PIN3_PB5,
- 0,
- 0,
- 3,
- 0),
- new_camera_device(RK29_CAM_SENSOR_GC0308,
- front,
- RK30_PIN3_PB5,
- 0,
- 0,
- 3,
- 0),
- new_camera_device_end
-};
-/*---------------- Camera Sensor Macro Define Begin ------------------------*/
-/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
-#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_OV5640 /* back camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_0 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 3
-#define CONFIG_SENSOR_ORIENTATION_0 90
-#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 RK30_PIN3_PB4//RK30_PIN3_PB5
-#define CONFIG_SENSOR_FALSH_PIN_0 RK30_PIN0_PD7
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_H
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000
-
-#define CONFIG_SENSOR_01 RK29_CAM_SENSOR_OV5642 /* back camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_01 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 4
-#define CONFIG_SENSOR_ORIENTATION_01 90
-#define CONFIG_SENSOR_POWER_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_01 RK30_PIN1_PD6
-#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_01 30000
-
-#define CONFIG_SENSOR_02 RK29_CAM_SENSOR_OV5640 /* back camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_02 0x00
-#define CONFIG_SENSOR_CIF_INDEX_02 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 4
-#define CONFIG_SENSOR_ORIENTATION_02 90
-#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000
-
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_GC0308 /* front camera sensor 0 */
-#define CONFIG_SENSOR_IIC_ADDR_1 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 3
-#define CONFIG_SENSOR_ORIENTATION_1 270
-#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_1 RK30_PIN3_PB5//RK30_PIN3_PB4
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000
-
-#define CONFIG_SENSOR_11 RK29_CAM_SENSOR_OV2659 /* front camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_11 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 3
-#define CONFIG_SENSOR_ORIENTATION_11 270
-#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_11 RK30_PIN3_PB5//RK30_PIN1_PB7
-#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_11 30000
-
-#define CONFIG_SENSOR_12 RK29_CAM_SENSOR_OV2659//RK29_CAM_SENSOR_OV2655 /* front camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_12 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 3
-#define CONFIG_SENSOR_ORIENTATION_12 270
-#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_12 INVALID_GPIO//RK30_PIN1_PB7
-#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_12 30000
-
-
-#endif //#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk30_camera.c"
-/*---------------- Camera Sensor Macro Define End ---------*/
-
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#define CONFIG_SENSOR_POWER_IOCTL_USR 1 //define this refer to your board layout
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
-
-static void rk_cif_power(struct rk29camera_gpio_res *res,int on)
-{
- struct regulator *ldo_18,*ldo_28;
- int camera_power = res->gpio_power;
- int camera_ioflag = res->gpio_flag;
- int camera_io_init = res->gpio_init;
-
- ldo_28 = regulator_get(NULL, "act_ldo8"); // vcc28_cif
- ldo_18 = regulator_get(NULL, "act_ldo3"); // vcc18_cif
- if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){
- printk("get cif ldo failed!\n");
- return;
- }
- if(on == 0){
- while(regulator_is_enabled(ldo_28)>0)
- regulator_disable(ldo_28);
- regulator_put(ldo_28);
- while(regulator_is_enabled(ldo_18)>0)
- regulator_disable(ldo_18);
- regulator_put(ldo_18);
- mdelay(10);
- if (camera_power != INVALID_GPIO) {
- if (camera_io_init & RK29_CAM_POWERACTIVE_MASK) {
- gpio_set_value(camera_power, (((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
- // dprintk("%s..%s..PowerPin=%d ..PinLevel = %x \n",__FUNCTION__,res->dev_name, camera_power, (((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
- }
- }
- }
- else{
- regulator_set_voltage(ldo_28, 2800000, 2800000);
- regulator_enable(ldo_28);
- // printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
- regulator_put(ldo_28);
-
- regulator_set_voltage(ldo_18, 1500000, 1500000);
- // regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(ldo_18);
- // printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
- regulator_put(ldo_18);
- if (camera_power != INVALID_GPIO) {
- if (camera_io_init & RK29_CAM_POWERACTIVE_MASK) {
- gpio_set_value(camera_power, ((camera_ioflag&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
- //dprintk("%s..%s..PowerPin=%d ..PinLevel = %x \n",__FUNCTION__,res->dev_name, camera_power, ((camera_ioflag&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
- mdelay(10);
- }
- }
-
- }
-}
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- //#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
- rk_cif_power(res,on);
- return 0;
-}
-#endif
-
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-
-#if CONFIG_SENSOR_IIC_ADDR_0
-static struct reginfo_t rk_init_data_sensor_reg_0[] =
-{
- {0x0000, 0x00,0,0}
- };
-static struct reginfo_t rk_init_data_sensor_winseqreg_0[] ={
- {0x0000, 0x00,0,0}
- };
-#endif
-
-#if CONFIG_SENSOR_IIC_ADDR_1
-static struct reginfo_t rk_init_data_sensor_reg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_01
-static struct reginfo_t rk_init_data_sensor_reg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_02
-static struct reginfo_t rk_init_data_sensor_reg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_11
-static struct reginfo_t rk_init_data_sensor_reg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_12
-static struct reginfo_t rk_init_data_sensor_reg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] =
-{
- #if CONFIG_SENSOR_IIC_ADDR_0
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_0,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_1
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_1,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_01
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_01,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_02
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_02,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_11
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_11,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_12
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_12,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
-
- };
-#include "../../../drivers/media/video/rk30_camera.c"
-
-#endif /* CONFIG_VIDEO_RK29 */
+++ /dev/null
-/*****************************************************************************************
- * arch/arm/mach-rkxx/baord-xxx-sdmmc-config.c
- *
- * Copyright (C) 2013 ROCKCHIP, Inc.
- *
- * Description:
- * define the gpio for SD-MMC-SDIO-Wifi functions according to your own projects.
- *
- * Author: Michael Xie
- * 15 Jan,2013
- * E-mail: xbw@rock-chips.com
- *
- ******************************************************************************************/
-
-/*
-** If you select the macro of CONFIG_SDMMC0_RK29_WRITE_PROTECT, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define SDMMC0_WRITE_PROTECT_PIN RK30_PIN3_PB2 //According to your own project to set the value of write-protect-pin.
-//#define SDMMC0_WRITE_PROTECT_ENABLE_VALUE GPIO_HIGH
-
-/*
-** If you select the macro of CONFIG_SDMMC1_RK29_WRITE_PROTECT, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define SDMMC1_WRITE_PROTECT_PIN RK30_PIN3_PB3 //According to your own project to set the value of write-protect-pin.
-//#define SDMMC1_WRITE_PROTECT_ENABLE_VALUE GPIO_HIGH
-
-/*
-** If you select the macro of CONFIG_RK29_SDIO_IRQ_FROM_GPIO, You must define the following values.
-** Otherwise, there is no need to define the following values¡£
-*/
-//#define RK29SDK_WIFI_SDIO_CARD_INT RK30_PIN3_PD2
-
-
-/*
-* define sdcard PowerEn-pin
-*/
-#define RK29SDK_SD_CARD_PWR_EN RK30_PIN3_PA1
-#define RK29SDK_SD_CARD_PWR_EN_LEVEL GPIO_LOW
-int rk31sdk_get_sdmmc0_pin_io_voltage(void)
-{
- int voltage;
-#define RK31SDK_SET_SDMMC0_PIN_VOLTAGE
-
- /**************************************************************************************
- ** Please tell me how much voltage of your SDMMC0-pin in your project.
- **
- ** ÀýÈç: ÓеÄÏîÄ¿£¬ËüµÄSDMMC0ËùÔÚµÄRKÖ÷¿ØµÄIO×飬ÏëÓÃ1.8V, ¶ø¿¨±¾ÉíÓÃ3.3V,
- ** ¶øÖмäͨ¹ý¸öµçƽת»».ÄÇô£¬Äú´Ëʱ£¬Ó¦¸ÃÉèÖÃÏÂÃæµÄvoltageֵΪ 1.8V(¼´1800mv)
- ***************************************************************************************/
- voltage = 3300; //default the voltage 3300mv.
-
- return voltage;
-}
-
-/*
-* define the card-detect-pin.
-*/
-#define RK29SDK_SD_CARD_DETECT_N RK30_PIN3_PB0 //According to your own project to set the value of card-detect-pin.
-#define RK29SDK_SD_CARD_INSERT_LEVEL GPIO_LOW // set the voltage of insert-card. Please pay attention to the default setting.
-
-/*
-* Define wifi module's power and reset gpio, and gpio sensitive level.
-* Please set the value according to your own project.
-*
-* Well, you just own engineering module to set the value in the corresponding module branch.
-* Otherwise, you do not define this macro, eliminate it.
-*
-*/
-#if defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU)
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_LOW//GPIO_HIGH
-
-#elif defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319) || defined(CONFIG_RK903) || defined(CONFIG_RK901)
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN2_PA7
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
-
-#elif defined(CONFIG_MT5931_MT6622) || defined(CONFIG_MT5931)
-
- #ifdef CONFIG_MACH_RK3168_LR097
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- //#define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- //#define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
-
- #else
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN0_PA5
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
-
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #endif
-
-#elif defined(CONFIG_MT6620)
- #define COMBO_MODULE_MT6620_CDT 1 // to control antsel2,antsel3 and gps_lan foot when using AcSip or Cdtech chip.
- //- 1--use Cdtech chip; 0--unuse CDT chip
-
- //power, PMU_EN
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PC7
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- //reset, DAIRST,SYSRST_B
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- //VDDIO
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL RK30_PIN0_PD2 //You do not get control of the foot, and you do not need to define the macro
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_ENABLE_VALUE GPIO_HIGH
- //WIFI_INT_B
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
- //BGF_INT_B
- #define RK30SDK_WIFI_GPIO_BGF_INT_B RK30_PIN6_PA7
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_ENABLE_VALUE GPIO_HIGH
- //GPS_SYNC
- #define RK30SDK_WIFI_GPIO_GPS_SYNC RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_ENABLE_VALUE GPIO_HIGH
-
- #if COMBO_MODULE_MT6620_CDT
- //ANTSEL2
- #define RK30SDK_WIFI_GPIO_ANTSEL2 RK30_PIN4_PD4
- #define RK30SDK_WIFI_GPIO_ANTSEL2_ENABLE_VALUE GPIO_LOW //use 6620 in CDT chip, LOW--work; High--no work.
- //ANTSEL3
- #define RK30SDK_WIFI_GPIO_ANTSEL3 RK30_PIN4_PD3
- #define RK30SDK_WIFI_GPIO_ANTSEL3_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- //GPS_LAN
- #define RK30SDK_WIFI_GPIO_GPS_LAN RK30_PIN4_PD6
- #define RK30SDK_WIFI_GPIO_GPS_LAN_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- #endif // #if COMBO_MODULE_MT6620_CDT--#endif
-#endif
-
-int rk31sdk_get_sdio_wifi_voltage(void)
-{
- int voltage;
-
- /******************************************************************************
- ** Please tell me how much wifi-module uses voltage in your project.
- ******************************************************************************/
-#if defined(CONFIG_BCM4329) || defined(CONFIG_BCM4319) || defined(CONFIG_RK903) || defined(CONFIG_RK901)
- voltage = 1800 ; //power 1800mV
-
-#elif defined(CONFIG_MT5931_MT6622)||defined(CONFIG_MT5931)
- voltage = 1800 ; //power 1800V
-#elif defined(CONFIG_MT6620)
- voltage = 2800 ; //power 2800V
-#elif defined(CONFIG_RDA5990)||defined(CONFIG_RTL8723AS)
- voltage = 3300 ; //power 3300V
-#else
- //default, sdio use 3.0V
- voltage = 3000 ; //power 3000V
-#endif
-
- return voltage;
-}
-
-
-
+++ /dev/null
-/*
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <mach/dvfs.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <linux/rk_fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/mfd/tps65910.h>
-#include <linux/regulator/act8846.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-
-#ifdef CONFIG_CW2015_BATTERY
-#include <linux/power/cw2015_battery.h>
-#endif
-
-#if defined(CONFIG_MFD_RK610)
-#include <linux/mfd/rk610_core.h>
-#endif
-
-#if defined(CONFIG_RK_HDMI)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-#if defined(CONFIG_GPS_RK)
-#include "../../../drivers/misc/gps/rk_gps/rk_gps.h"
-#endif
-#if defined(CONFIG_MU509)
-#include <linux/mu509.h>
-#endif
-#if defined(CONFIG_MW100)
-#include <linux/mw100.h>
-#endif
-#if defined(CONFIG_MT6229)
-#include <linux/mt6229.h>
-#endif
-#if defined(CONFIG_ANDROID_TIMED_GPIO)
-#include "../../../drivers/staging/android/timed_gpio.h"
-#endif
-
-#if defined(CONFIG_MT6620)
-#include <linux/gps.h>
-#endif
-#include "board-rk3188-u30gt2-camera.c"
-
-#if defined(CONFIG_TOUCHSCREEN_GT8XX)
-#define TOUCH_RESET_PIN RK30_PIN0_PB6
-#define TOUCH_PWR_PIN RK30_PIN0_PC5 // need to fly line by hardware engineer
-
-/* Android Parameter */
-static int ap_mdm = 0;
-module_param(ap_mdm, int, 0644);
-static int ap_has_alsa = 0;
-module_param(ap_has_alsa, int, 0644);
-static int ap_data_only = 2;
-module_param(ap_data_only, int, 0644);
-static int ap_has_earphone = 0;
-module_param(ap_has_earphone, int, 0644);
-
-
-static int goodix_init_platform_hw(void)
-{
- int ret;
-
- if (TOUCH_PWR_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_PWR_PIN, "goodix power pin");
- if (ret != 0) {
- gpio_free(TOUCH_PWR_PIN);
- printk("goodix power error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_PWR_PIN, 0);
- gpio_set_value(TOUCH_PWR_PIN, GPIO_LOW);
- msleep(100);
- }
-
- if (TOUCH_RESET_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_RESET_PIN, "goodix reset pin");
- if (ret != 0) {
- gpio_free(TOUCH_RESET_PIN);
- printk("goodix gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, 1);
- msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_LOW);
- //msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_HIGH);
- //msleep(500);
- }
- return 0;
-}
-
-struct goodix_platform_data goodix_info = {
- .model = 8105,
- .irq_pin = RK30_PIN1_PB7,
- .rest_pin = TOUCH_RESET_PIN,
- .init_platform_hw = goodix_init_platform_hw,
-};
-#endif
-
-/*ft5x0x touchpad*/
-#if defined (CONFIG_TOUCHSCREEN_FT5X0X)
-
-#define TOUCH_RESET_PIN RK30_PIN0_PB6
-#define TOUCH_EN_PIN NULL
-#define TOUCH_INT_PIN RK30_PIN1_PB7
-
-static struct ts_hw_data ts_hw_info = {
- .reset_gpio = TOUCH_RESET_PIN,
- //.touch_en_gpio = TOUCH_POWER_PIN,
-};
-
-#endif
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-#define PWM_ID 3
-#define PWM_MODE PWM3
-#define PWM_EFFECT_VALUE 0
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-#define BL_EN_PIN RK30_PIN0_PA2
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-
-struct delayed_work backlight_enable_work;
-void backlight_enable(struct work_struct *work)
-{
- printk("xhc function: %s\n", __func__);
- gpio_direction_output(BL_EN_PIN, BL_EN_VALUE);
-}
-
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
-
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
- ret = gpio_request(BL_EN_PIN, "bl_en");
- if (ret == 0) {
- msleep(20);
- gpio_direction_output(BL_EN_PIN, !BL_EN_VALUE);
- }
-#endif
- printk("xhc call %s()\n", __func__);
-
- INIT_DELAYED_WORK(&backlight_enable_work, backlight_enable);
- schedule_delayed_work(&backlight_enable_work, msecs_to_jiffies(300));
-
- return ret;
-}
-
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0, pwm_gpio;
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, !BL_EN_VALUE);
- gpio_free(BL_EN_PIN);
-#endif
- pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
- gpio_request(pwm_gpio, "bl_pwm");
- gpio_direction_output(pwm_gpio, GPIO_LOW);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret, pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
-
- ret = gpio_request(pwm_gpio, "bl_pwm");
- if (ret) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return ret;
- }
- gpio_direction_output(pwm_gpio, GPIO_LOW);
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, !BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- int pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
-
- gpio_free(pwm_gpio);
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
-#if 1
- msleep(250);
- gpio_direction_output(BL_EN_PIN, BL_EN_VALUE);
-#endif
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .min_brightness=20,
- .max_brightness=180,
- .brightness_mode =BRIGHTNESS_MODE_CONIC,
- .pre_div = 10 * 1000, // pwm output clk: 40k;
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
- .min_brightness = 50,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-#endif
-
-#ifdef CONFIG_RK29_SUPPORT_MODEM
-
-#define RK30_MODEM_POWER RK30_PIN0_PC6
-#define RK30_MODEM_POWER_IOMUX iomux_set(GPIO0_C6)
-
-static int rk30_modem_io_init(void)
-{
- printk("%s\n", __FUNCTION__);
- RK30_MODEM_POWER_IOMUX;
-
- return 0;
-}
-
-static struct rk29_io_t rk30_modem_io = {
- .io_addr = RK30_MODEM_POWER,
- .enable = GPIO_HIGH,
- .disable = GPIO_LOW,
- .io_init = rk30_modem_io_init,
-};
-
-static struct platform_device rk30_device_modem = {
- .name = "rk30_modem",
- .id = -1,
- .dev = {
- .platform_data = &rk30_modem_io,
- }
-};
-#endif
-#if defined(CONFIG_MU509)
-static int mu509_io_init(void)
-{
-
- iomux_set(GPIO2_D5);
- iomux_set(GPIO0_C6);
- iomux_set(GPIO2_D4);
- iomux_set(GPIO0_C4);
- iomux_set(GPIO0_C5);
- return 0;
-}
-
-static int mu509_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mu509_data rk29_mu509_info = {
- .io_init = mu509_io_init,
- .io_deinit = mu509_io_deinit,
- .modem_power_en = RK30_PIN2_PD5,
- .bp_power = RK30_PIN0_PC6,
- .bp_reset = RK30_PIN2_PD4,
- .ap_wakeup_bp = RK30_PIN0_PC4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
-};
-struct platform_device rk29_device_mu509 = {
- .name = "mu509",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mu509_info,
- }
- };
-#endif
-#if defined(CONFIG_MW100)
-static int mw100_io_init(void)
-{
- iomux_set(GPIO2_D5);
- iomux_set(GPIO0_C6);
- iomux_set(GPIO2_D4);
- iomux_set(GPIO0_C4);
- iomux_set(GPIO0_C5);
- return 0;
-}
-
-static int mw100_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mw100_data rk29_mw100_info = {
- .io_init = mw100_io_init,
- .io_deinit = mw100_io_deinit,
- .modem_power_en = RK30_PIN2_PD5,
- .bp_power = RK30_PIN0_PC6,
- .bp_reset = RK30_PIN2_PD4,
- .ap_wakeup_bp = RK30_PIN0_PC4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
-};
-struct platform_device rk29_device_mw100 = {
- .name = "mw100",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mw100_info,
- }
- };
-#endif
-#if defined(CONFIG_MT6229)
-static int mt6229_io_init(void)
-{
- iomux_set(GPIO2_D5);
- iomux_set(GPIO0_C6);
- iomux_set(GPIO2_D4);
- iomux_set(GPIO0_C4);
- iomux_set(GPIO0_C5);
- return 0;
-}
-
-static int mt6229_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mt6229_data rk29_mt6229_info = {
- .io_init = mt6229_io_init,
- .io_deinit = mt6229_io_deinit,
- .modem_power_en = RK30_PIN2_PD5,
- .bp_power = RK30_PIN0_PC6,
- .bp_reset = RK30_PIN2_PD4,
- .ap_wakeup_bp = RK30_PIN0_PC4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
-};
-struct platform_device rk29_device_mt6229 = {
- .name = "mt6229",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mt6229_info,
- }
- };
-#endif
-
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN RK30_PIN0_PB7
-
-static int mma8452_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data mma8452_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma8452_init_platform_hw,
- //.orientation = {-1, 0, 0, 0, 0, 1, 0, -1, 0},
- .orientation = {-1, 0, 0, 0, -1, 0, 0, 0, 1},
-};
-#endif
-#if defined (CONFIG_GS_LIS3DH)
-#define LIS3DH_INT_PIN RK30_PIN0_PB7
-
-static int lis3dh_init_platform_hw(void)
-{
-
- return 0;
-}
-
-static struct sensor_platform_data lis3dh_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lis3dh_init_platform_hw,
- // .orientation = {0, -1, 0, 0, 0, -1, -1, 0, 0},
- .orientation = {0, -1, 0, -1, 0, 0, 0, 0, -1},
-};
-#endif
-
-#if defined(CONFIG_CHARGER_CW2015)
-struct cw2015_platform_data cw2015_info = {
- .dc_det_pin = RK30_PIN0_PB2,
- .batt_low_pin = RK30_PIN0_PB1,
- .dc_det_level = GPIO_LOW,
- .batt_low_level = GPIO_LOW,
-};
-#endif
-
-#if defined (CONFIG_COMPASS_AK8975)
-static struct sensor_platform_data akm8975_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-#if defined(CONFIG_GYRO_L3G20D)
-
-#include <linux/l3g4200d.h>
-#define L3G20D_INT_PIN RK30_PIN0_PB4
-
-static int l3g20d_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data l3g20d_info = {
- .type = SENSOR_TYPE_GYROSCOPE,
- .irq_enable = 1,
- .poll_delay_ms = 0, //30,
- .orientation = {1, 0, 0, 0, -1, 0, 0, 0, -1},
- .init_platform_hw = l3g20d_init_platform_hw,
- .x_min = 40,//x_min,y_min,z_min = (0-100) according to hardware
- .y_min = 40,
- .z_min = 20,
-};
-
-#endif
-
-#ifdef CONFIG_LS_CM3217
-static struct sensor_platform_data cm3217_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 0,
- .poll_delay_ms = 500,
-};
-
-#endif
-
-#ifdef CONFIG_FB_ROCKCHIP
-
-#define LCD_CS_PIN RK30_PIN1_PB6
-#define LCD_CS_VALUE GPIO_HIGH
-
-#define LCD_EN_PIN RK30_PIN0_PB0
-#define LCD_EN_VALUE GPIO_LOW
-
-#define LCD_PWR_PIN RK30_PIN1_PB5
-#define LCD_PWR_VALUE GPIO_HIGH
-
-
-#define LCD_CS_PIN_1 RK30_PIN3_PD4
-#define LCD_CS_VALUE_1 GPIO_HIGH
-
-#define LCD_PWR_PIN_1 RK30_PIN0_PA7
-#define LCD_PWR_VALUE_1 GPIO_HIGH
-
-
-
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
-
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_CS_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_CS_PIN);
- printk(KERN_ERR "request lcd cs pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_CS_PIN, LCD_CS_VALUE);
- }
- }
- if(LCD_CS_PIN_1 !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_CS_PIN_1, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_CS_PIN_1);
- printk(KERN_ERR "request lcd cs pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_CS_PIN_1, LCD_CS_VALUE_1);
- }
- }
-
-
-
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_EN_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_EN_PIN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_EN_PIN, LCD_EN_VALUE);
- }
- }
- if(LCD_PWR_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_PWR_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_PWR_PIN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_PWR_PIN, LCD_PWR_VALUE);
- }
- }
- if(LCD_PWR_PIN_1 !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_PWR_PIN_1, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_PWR_PIN_1);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_PWR_PIN_1, LCD_PWR_VALUE_1);
- }
- }
-
-
-
-
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, !LCD_CS_VALUE);
- }
- if(LCD_CS_PIN_1 !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN_1, !LCD_CS_VALUE_1);
- }
-
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, !LCD_EN_VALUE);
- }
- if(LCD_PWR_PIN !=INVALID_GPIO)
- {
- gpio_direction_output(LCD_PWR_PIN, !LCD_PWR_VALUE);
- }
- if(LCD_PWR_PIN_1 !=INVALID_GPIO)
- {
- gpio_direction_output(LCD_PWR_PIN_1, !LCD_PWR_VALUE_1);
- }
-
-
-
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE);
- }
- if(LCD_CS_PIN_1 !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN_1, LCD_CS_VALUE_1);
- }
-
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
- }
- if(LCD_PWR_PIN !=INVALID_GPIO)
- {
- gpio_direction_output(LCD_PWR_PIN, LCD_PWR_VALUE);
- }
- if(LCD_PWR_PIN_1 !=INVALID_GPIO)
- {
- gpio_direction_output(LCD_PWR_PIN_1, LCD_PWR_VALUE_1);
- }
-
-
-
- return 0;
-}
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
-struct rk29fb_info lcdc0_screen_info = {
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
-struct rk29fb_info lcdc1_screen_info = {
- #if defined(CONFIG_RK_HDMI)
- .prop = EXTEND, //extend display device
- .lcd_info = NULL,
- .set_screen_info = hdmi_init_lcdc,
- #endif
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-#if defined(CONFIG_ARCH_RK3188)
-static struct resource resource_mali[] = {
- [0] = {
- .name = "ump buf",
- .start = 0,
- .end = 0,
- .flags = IORESOURCE_MEM,
- },
-
-};
-
-static struct platform_device device_mali= {
- .name = "mali400_ump",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_mali),
- .resource = resource_mali,
-};
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
-static struct resource resource_lcdc0[] = {
- [0] = {
- .name = "lcdc0 reg",
- .start = RK30_LCDC0_PHYS,
- .end = RK30_LCDC0_PHYS + RK30_LCDC0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc0 irq",
- .start = IRQ_LCDC0,
- .end = IRQ_LCDC0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc0 = {
- .name = "rk30-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc0),
- .resource = resource_lcdc0,
- .dev = {
- .platform_data = &lcdc0_screen_info,
- },
-};
-#endif
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
-static struct resource resource_lcdc1[] = {
- [0] = {
- .name = "lcdc1 reg",
- .start = RK30_LCDC1_PHYS,
- .end = RK30_LCDC1_PHYS + RK30_LCDC1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc1 irq",
- .start = IRQ_LCDC1,
- .end = IRQ_LCDC1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc1 = {
- .name = "rk30-lcdc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resource_lcdc1),
- .resource = resource_lcdc1,
- .dev = {
- .platform_data = &lcdc1_screen_info,
- },
-};
-#endif
-
-#if defined(CONFIG_MFD_RK610)
-#define RK610_RST_PIN RK30_PIN2_PC5
-static int rk610_power_on_init(void)
-{
- int ret;
- if(RK610_RST_PIN != INVALID_GPIO)
- {
- ret = gpio_request(RK610_RST_PIN, "rk610 reset");
- if (ret)
- {
- printk(KERN_ERR "rk610_control_probe request gpio fail\n");
- }
- else
- {
- gpio_direction_output(RK610_RST_PIN, GPIO_HIGH);
- msleep(100);
- gpio_direction_output(RK610_RST_PIN, GPIO_LOW);
- msleep(100);
- gpio_set_value(RK610_RST_PIN, GPIO_HIGH);
- }
- }
-
- return 0;
-
-}
-
-
-static struct rk610_ctl_platform_data rk610_ctl_pdata = {
- .rk610_power_on_init = rk610_power_on_init,
-};
-#endif
-
-#ifdef CONFIG_SND_SOC_RK610
-static int rk610_codec_io_init(void)
-{
-//if need iomux.
-//Must not gpio_request
- return 0;
-}
-
-static struct rk610_codec_platform_data rk610_codec_pdata = {
- .spk_ctl_io = RK30_PIN4_PC6,
- .io_init = rk610_codec_io_init,
-};
-#endif
-
-#ifdef CONFIG_ANDROID_TIMED_GPIO
-static struct timed_gpio timed_gpios[] = {
- {
- .name = "vibrator",
- .gpio = INVALID_GPIO,
- .max_timeout = 1000,
- .active_low = 0,
- .adjust_time =20, //adjust for diff product
- },
-};
-
-static struct timed_gpio_platform_data rk29_vibrator_info = {
- .num_gpios = 1,
- .gpios = timed_gpios,
-};
-
-static struct platform_device rk29_device_vibrator = {
- .name = "timed-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_vibrator_info,
- },
-
-};
-#endif
-
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
-static struct gpio_led rk29_leds[] = {
- {
- .name = "button-backlight",
- .gpio = INVALID_GPIO,
- .default_trigger = "timer",
- .active_low = 0,
- .retain_state_suspended = 0,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- },
-};
-
-static struct gpio_led_platform_data rk29_leds_pdata = {
- .leds = rk29_leds,
- .num_leds = ARRAY_SIZE(rk29_leds),
-};
-
-static struct platform_device rk29_device_gpio_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_leds_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_RK_IRDA
-#define IRDA_IRQ_PIN INVALID_GPIO //RK30_PIN0_PA3
-
-static int irda_iomux_init(void)
-{
- int ret = 0;
-
- //irda irq pin
- ret = gpio_request(IRDA_IRQ_PIN, NULL);
- if (ret != 0) {
- gpio_free(IRDA_IRQ_PIN);
- printk(">>>>>> IRDA_IRQ_PIN gpio_request err \n ");
- }
- gpio_pull_updown(IRDA_IRQ_PIN, PullDisable);
- gpio_direction_input(IRDA_IRQ_PIN);
-
- return 0;
-}
-
-static int irda_iomux_deinit(void)
-{
- gpio_free(IRDA_IRQ_PIN);
- return 0;
-}
-
-static struct irda_info rk29_irda_info = {
- .intr_pin = IRDA_IRQ_PIN,
- .iomux_init = irda_iomux_init,
- .iomux_deinit = irda_iomux_deinit,
- //.irda_pwr_ctl = bu92747guw_power_ctl,
-};
-
-static struct platform_device irda_device = {
-#ifdef CONFIG_RK_IRDA_NET
- .name = "rk_irda",
-#else
- .name = "bu92747_irda",
-#endif
- .id = -1,
- .dev = {
- .platform_data = &rk29_irda_info,
- }
-};
-#endif
-
-#ifdef CONFIG_RK_HDMI
-#define RK_HDMI_RST_PIN RK30_PIN3_PB2
-static int rk_hdmi_power_init(void)
-{
- if(RK_HDMI_RST_PIN != INVALID_GPIO)
- {
- if (gpio_request(RK_HDMI_RST_PIN, NULL)) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return -1;
- }
- gpio_direction_output(RK_HDMI_RST_PIN, GPIO_LOW);
- gpio_set_value(RK_HDMI_RST_PIN, GPIO_LOW);
- msleep(100);
- gpio_set_value(RK_HDMI_RST_PIN, GPIO_HIGH);
- msleep(50);
- }
- return 0;
-}
-static struct rk_hdmi_platform_data rk_hdmi_pdata = {
- .io_init = rk_hdmi_power_init,
-};
-#endif
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (120 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and sdio.noted by xbw at 2012-03-05
-**************************************************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "board-rk3188-u30gt2-sdmmc-config.c"
-#include "../plat-rk/rk-sdmmc-ops.c"
-#include "../plat-rk/rk-sdmmc-wifi.c"
-#endif //endif ---#ifdef CONFIG_SDMMC_RK29
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- iomux_set(MMC0_CMD);
- iomux_set(MMC0_CLKOUT);
- iomux_set(MMC0_D0);
- iomux_set(MMC0_D1);
- iomux_set(MMC0_D2);
- iomux_set(MMC0_D3);
-
- iomux_set_gpio_mode(iomux_mode_to_gpio(MMC0_DETN));
-
- gpio_request(RK30_PIN3_PA7, "sdmmc-power");
- gpio_direction_output(RK30_PIN3_PA7, GPIO_LOW);
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- #if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set_gpio_mode(iomux_gpio_to_mode(RK29SDK_SD_CARD_DETECT_N));
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO);
- #endif
- #else
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(MMC0_DETN);
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FMUX);
- #endif
- #endif
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) && defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- .status = rk29sdk_wifi_mmc0_status,
- .register_status_notify = rk29sdk_wifi_mmc0_status_register,
-#endif
-
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .power_en = RK29SDK_SD_CARD_PWR_EN,
- .power_en_level = RK29SDK_SD_CARD_PWR_EN_LEVEL,
-#else
- .power_en = INVALID_GPIO,
- .power_en_level = GPIO_LOW,
-#endif
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC0_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- .det_pin_info = {
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N, //INVALID_GPIO,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
- #endif
- },
-
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- iomux_set(MMC1_CMD);
- iomux_set(MMC1_CLKOUT);
- iomux_set(MMC1_D0);
- iomux_set(MMC1_D1);
- iomux_set(MMC1_D2);
- iomux_set(MMC1_D3);
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC) || defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC1_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- #if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
- .sdio_INT_gpio = RK29SDK_WIFI_SDIO_CARD_INT,
- #endif
-
- .det_pin_info = {
-#if defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- #else
- .io = INVALID_GPIO,
- #endif
-
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-
- .enable_sd_wakeup = 0,
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-/**************************************************************************************************
- * the end of setting for SDMMC devices
-**************************************************************************************************/
-
-#ifdef CONFIG_BATTERY_RK30_ADC
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = RK30_PIN0_PB2,
- .batt_low_pin = RK30_PIN0_PB1,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = RK30_PIN0_PA6,
- .dc_det_level = GPIO_LOW,
- .charge_ok_level = GPIO_HIGH,
-};
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-
-#ifdef CONFIG_CW2015_BATTERY
-
-static u8 config_info[SIZE_BATINFO] = {
- 0x15, 0x42, 0x60, 0x59, 0x52,\r
- 0x58, 0x4D, 0x48, 0x48, 0x44,\r
- 0x44, 0x46, 0x49, 0x48, 0x32,\r
- 0x24, 0x20, 0x17, 0x13, 0x0F,\r
- 0x19, 0x3E, 0x51, 0x45, 0x08,\r
- 0x76, 0x0B, 0x85, 0x0E, 0x1C,\r
- 0x2E, 0x3E, 0x4D, 0x52, 0x52,\r
- 0x57, 0x3D, 0x1B, 0x6A, 0x2D,\r
- 0x25, 0x43, 0x52, 0x87, 0x8F,\r
- 0x91, 0x94, 0x52, 0x82, 0x8C,\r
- 0x92, 0x96, 0xFF, 0x7B, 0xBB,\r
- 0xCB, 0x2F, 0x7D, 0x72, 0xA5,\r
- 0xB5, 0xC1, 0x46, 0xAE
-};
-
-static struct cw_bat_platform_data cw_bat_platdata = {
- .dc_det_pin = RK30_PIN0_PB2,
- .bat_low_pin = RK30_PIN0_PB1,
- .chg_ok_pin = RK30_PIN0_PA6,
- .dc_det_level = GPIO_LOW,
- .bat_low_level = GPIO_LOW,
- .chg_ok_level = GPIO_HIGH,
-
- .cw_bat_config_info = config_info,
-
-};
-
-#endif
-
-
-#ifdef CONFIG_RK30_PWM_REGULATOR
-static int pwm_voltage_map[] = {
- 800000,825000,850000, 875000,900000, 925000 ,950000, 975000,1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000,1375000
-};
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_cpu",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] =
-{
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
- .pwm_id = 1,
- .pwm_gpio = RK30_PIN3_PD4,
- .pwm_iomux_pwm = PWM1,
- .pwm_iomux_gpio = GPIO3_D4,
- .pwm_voltage = 1100000,
- .suspend_voltage = 1000000,
- .min_uV = 800000,
- .max_uV = 1375000,
- .coefficient = 575, //57.5%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-#endif
-
-#ifdef CONFIG_RK29_VMAC
-#define PHY_PWR_EN_GPIO RK30_PIN1_PD6
-#include "board-rk30-sdk-vmac.c"
-#endif
-
-#ifdef CONFIG_RFKILL_RK
-// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
-static struct rfkill_rk_platform_data rfkill_rk_platdata = {
- .type = RFKILL_TYPE_BLUETOOTH,
-
- .poweron_gpio = { // BT_REG_ON
- .io = RK30_PIN3_PC7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_poweron",
- .fgpio = GPIO3_C7,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN3_PD1,//RK30_PIN3_PC7, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_reset",
- .fgpio = GPIO3_D1,
- },
- },
-
- .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
- .io = RK30_PIN3_PC6, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_wake",
- .fgpio = GPIO3_C6,
- },
- },
-
- .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .gpio = {
- .io = RK30_PIN0_PA5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
- .iomux = {
- .name = NULL,
- },
- },
- },
-
- .rts_gpio = { // UART_RTS, enable or disable BT's data coming
- .io = RK30_PIN1_PA3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_rts",
- .fgpio = GPIO1_A3,
- .fmux = UART0_RTSN,
- },
- },
-};
-
-static struct platform_device device_rfkill_rk = {
- .name = "rfkill_rk",
- .id = -1,
- .dev = {
- .platform_data = &rfkill_rk_platdata,
- },
-};
-#endif
-
-#if defined(CONFIG_GPS_RK)
-int rk_gps_io_init(void)
-{
- printk("%s \n", __FUNCTION__);
-
- gpio_request(RK30_PIN1_PB5, NULL);
- gpio_direction_output(RK30_PIN1_PB5, GPIO_LOW);
-
- iomux_set(GPS_RFCLK);//GPS_CLK
- iomux_set(GPS_MAG);//GPS_MAG
- iomux_set(GPS_SIG);//GPS_SIGN
-
- gpio_request(RK30_PIN1_PA6, NULL);
- gpio_direction_output(RK30_PIN1_PA6, GPIO_LOW);
-
- gpio_request(RK30_PIN1_PA5, NULL);
- gpio_direction_output(RK30_PIN1_PA5, GPIO_LOW);
-
- gpio_request(RK30_PIN1_PA7, NULL);
- gpio_direction_output(RK30_PIN1_PA7, GPIO_LOW);
- return 0;
-}
-int rk_gps_power_up(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_power_down(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_reset_set(int level)
-{
- return 0;
-}
-int rk_enable_hclk_gps(void)
-{
- struct clk *gps_aclk = NULL;
- gps_aclk = clk_get(NULL, "aclk_gps");
- if(gps_aclk) {
- clk_enable(gps_aclk);
- clk_put(gps_aclk);
- printk("%s \n", __FUNCTION__);
- }
- else
- printk("get gps aclk fail\n");
- return 0;
-}
-int rk_disable_hclk_gps(void)
-{
- struct clk *gps_aclk = NULL;
- gps_aclk = clk_get(NULL, "aclk_gps");
- if(gps_aclk) {
- //TO wait long enough until GPS ISR is finished.
- msleep(5);
- clk_disable(gps_aclk);
- clk_put(gps_aclk);
- printk("%s \n", __FUNCTION__);
- }
- else
- printk("get gps aclk fail\n");
- return 0;
-}
-struct rk_gps_data rk_gps_info = {
- .io_init = rk_gps_io_init,
- .power_up = rk_gps_power_up,
- .power_down = rk_gps_power_down,
- .reset = rk_gps_reset_set,
- .enable_hclk_gps = rk_enable_hclk_gps,
- .disable_hclk_gps = rk_disable_hclk_gps,
- .GpsSign = RK30_PIN1_PB3,
- .GpsMag = RK30_PIN1_PB2, //GPIO index
- .GpsClk = RK30_PIN1_PB4, //GPIO index
- .GpsVCCEn = RK30_PIN1_PB5, //GPIO index
- .GpsSpi_CSO = RK30_PIN1_PA4, //GPIO index
- .GpsSpiClk = RK30_PIN1_PA5, //GPIO index
- .GpsSpiMOSI = RK30_PIN1_PA7, //GPIO index
- .GpsIrq = IRQ_GPS,
- .GpsSpiEn = 0,
- .GpsAdcCh = 2,
- .u32GpsPhyAddr = RK30_GPS_PHYS,
- .u32GpsPhySize = RK30_GPS_SIZE,
-};
-
-struct platform_device rk_device_gps = {
- .name = "gps_hv5820b",
- .id = -1,
- .dev = {
- .platform_data = &rk_gps_info,
- }
- };
-#endif
-
-
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_ANDROID_TIMED_GPIO
- &rk29_device_vibrator,
-#endif
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
- &rk29_device_gpio_leds,
-#endif
-#ifdef CONFIG_RK_IRDA
- &irda_device,
-#endif
-#if defined(CONFIG_WIFI_CONTROL_FUNC)||defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- &rk29sdk_wifi_device,
-#endif
-
-#if defined(CONFIG_MT6620)
- &mt3326_device_gps,
-#endif
-
-#ifdef CONFIG_RK29_SUPPORT_MODEM
- &rk30_device_modem,
-#endif
-#if defined(CONFIG_MU509)
- &rk29_device_mu509,
-#endif
-#if defined(CONFIG_MW100)
- &rk29_device_mw100,
-#endif
-#if defined(CONFIG_MT6229)
- &rk29_device_mt6229,
-#endif
-#ifdef CONFIG_BATTERY_RK30_ADC
- &rk30_device_adc_battery,
-#endif
-#ifdef CONFIG_RFKILL_RK
- &device_rfkill_rk,
-#endif
-#ifdef CONFIG_GPS_RK
- &rk_device_gps,
-#endif
-#if defined(CONFIG_ARCH_RK3188)
- &device_mali,
-#endif
-};
-
-static int rk_platform_add_display_devices(void)
-{
- struct platform_device *fb = NULL; //fb
- struct platform_device *lcdc0 = NULL; //lcdc0
- struct platform_device *lcdc1 = NULL; //lcdc1
- struct platform_device *bl = NULL; //backlight
-#ifdef CONFIG_FB_ROCKCHIP
- fb = &device_fb;
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
- lcdc0 = &device_lcdc0,
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
- lcdc1 = &device_lcdc1,
-#endif
-
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- bl = &rk29_device_backlight,
-#endif
- __rk_platform_add_display_devices(fb,lcdc0,lcdc1,bl);
-
- return 0;
-
-}
-
-// i2c
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_GS_LSM303D)
- {
- .type = "lsm303d",
- .addr = 0x1d, //0x19(SA0-->VCC), 0x18(SA0-->GND)
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1d,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_GS_LIS3DH)
- {
- .type = "gs_lis3dh",
- .addr = 0x19, //0x19(SA0-->VCC), 0x18(SA0-->GND)
- .flags = 0,
- .irq = LIS3DH_INT_PIN,
- .platform_data = &lis3dh_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8975_info,
- },
-#endif
-#if defined (CONFIG_GYRO_L3G20D)
- {
- .type = "l3g20d_gryo",
- .addr = 0x6b,
- .flags = 0,
- .irq = L3G20D_INT_PIN,
- .platform_data = &l3g20d_info,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RT5631)
- {
- .type = "rt5631",
- .addr = 0x1a,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_RK29_SOC_ES8323)
- {
- .type = "es8323",//"es8323",
- .addr = 0x10,
- .flags = 0,
- },
-#endif
-
-#ifdef CONFIG_MFD_RK610
- {
- .type = "rk610_ctl",
- .addr = 0x40,
- .flags = 0,
- .platform_data = &rk610_ctl_pdata,
- },
-#ifdef CONFIG_RK610_TVOUT
- {
- .type = "rk610_tvout",
- .addr = 0x42,
- .flags = 0,
- },
-#endif
-#ifdef CONFIG_HDMI_RK610
- {
- .type = "rk610_hdmi",
- .addr = 0x46,
- .flags = 0,
- .irq = INVALID_GPIO,
- },
-#endif
-#ifdef CONFIG_SND_SOC_RK610
- {//RK610_CODEC addr from 0x60 to 0x80 (0x60~0x80)
- .type = "rk610_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- .platform_data = &rk610_codec_pdata,
- },
-#endif
-#endif
-
-};
-#endif
-
-int __sramdata g_pmic_type = 0;
-#ifdef CONFIG_I2C1_RK30
-#ifdef CONFIG_MFD_WM831X_I2C
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info wm8326_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "dcdc3", //ddr
- .min_uv = 1150000,
- .max_uv = 1150000,
- .suspend_vol = 1150000,
- },
- #ifdef CONFIG_MACH_RK3066_SDK
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3000000,
- },
- #else
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3000000,
- .max_uv = 3000000,
- .suspend_vol = 2800000,
- },
- #endif
-};
-
-static struct pmu_info wm8326_ldo_info[] = {
- {
- .name = "ldo1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo2", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo3", //
- .min_uv = 1100000,
- .max_uv = 1100000,
- .suspend_vol = 1100000,
- },
- {
- .name = "ldo4", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 1000000,
- },
- {
- .name = "ldo5", //vcc25
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo6", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo7", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- .suspend_vol = 2800000,
- },
- {
- .name = "ldo8", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo9", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo10", //flash_io
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
-};
-
-#include "board-pmu-wm8326.c"
-#endif
-
-#ifdef CONFIG_MFD_TPS65910
-#define TPS65910_HOST_IRQ RK30_PIN0_PB3
-
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info tps65910_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1100000,
- .max_uv = 1100000,
- },
- {
- .name = "vdd2", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vio", //vcc_io
- .min_uv = 2500000,
- .max_uv = 2500000,
- },
-
-};
-static struct pmu_info tps65910_ldo_info[] = {
- {
- .name = "vpll", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "vdig2", //vdd_jetta
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vaux1", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "vaux2", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vaux33", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vmmc", //vcc30
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
- {
- .name = "vdac", //vcc18
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- };
-
-#include "board-pmu-tps65910.c"
-#endif
-
-#ifdef CONFIG_REGULATOR_ACT8846
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-#define PMU_VSEL RK30_PIN3_PD3
-static struct pmu_info act8846_dcdc_info[] = {
- {
- .name = "act_dcdc1", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- .suspend_vol = 1200000,
- },
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 1200000,
- #else
- .suspend_vol = 900000,
- #endif
-
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 1200000,
- #else
- .suspend_vol = 900000,
- #endif
-
- },
- {
- .name = "act_dcdc4", //vccio
- .min_uv = 3000000,
- .max_uv = 3000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 3000000,
- #else
- .suspend_vol = 2800000,
- #endif
-
- },
-
-};
-static struct pmu_info act8846_ldo_info[] = {
- {
- .name = "act_ldo1", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "act_ldo2", //vdd12
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "act_ldo3", //vcc18_cif
- .min_uv = 1500000,
- .max_uv = 1500000,
- },
- {
- .name = "act_ldo4", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo5", //vcctp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo6", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo7", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo8", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- };
-
-#include "../mach-rk30/board-pmu-act8846.c"
-#endif
-
-
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_MFD_WM831X_I2C)
- {
- .type = "wm8326",
- .addr = 0x34,
- .flags = 0,
- .irq = RK30_PIN0_PB3,
- .platform_data = &wm831x_platdata,
- },
-#endif
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-
-#if defined (CONFIG_REGULATOR_ACT8846)
- {
- .type = "act8846",
- .addr = 0x5a,
- .flags = 0,
- // .irq = ACT8846_HOST_IRQ,
- .platform_data=&act8846_data,
- },
-#endif
-#if defined (CONFIG_RTC_HYM8563)
- {
- .type = "rtc_hym8563",
- .addr = 0x51,
- .flags = 0,
- .irq = RK30_PIN1_PA4,
- },
-#endif
-#if defined (CONFIG_CHARGER_CW2015)
- {
- .type = "cw2015",
- .addr = 0x62,
- .flags = 0,
- .platform_data = &cw2015_info,
- },
-#endif
-
-#if defined (CONFIG_CW2015_BATTERY)
- {
- .type = "cw201x",
- .addr = 0x62,
- .flags = 0,
- .platform_data = &cw_bat_platdata,
- },
-#endif
-
-};
-#endif
-
-void __sramfunc board_pmu_suspend(void)
-{
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_suspend();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_suspend();
- #endif
- #if defined (CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- board_pmu_act8846_suspend();
- #endif
-
-}
-
-void __sramfunc board_pmu_resume(void)
-{
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_resume();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_resume();
- #endif
- #if defined (CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- board_pmu_act8846_resume();
- #endif
-}
-
- int __sramdata gpio3d6_iomux,gpio3d6_do,gpio3d6_dir,gpio3d6_en;
-
-#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
-
-void __sramfunc rk30_pwm_logic_suspend_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
-
-// int gpio0d7_iomux,gpio0d7_do,gpio0d7_dir,gpio0d7_en;
- sram_udelay(10000);
- gpio3d6_iomux = grf_readl(GRF_GPIO3D_IOMUX);
- gpio3d6_do = grf_readl(GRF_GPIO3H_DO);
- gpio3d6_dir = grf_readl(GRF_GPIO3H_DIR);
- gpio3d6_en = grf_readl(GRF_GPIO3H_EN);
-
- grf_writel((1<<28), GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DIR);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DO);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_EN);
-#endif
-}
-void __sramfunc rk30_pwm_logic_resume_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- grf_writel((1<<28)|gpio3d6_iomux, GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|gpio3d6_en, GRF_GPIO3H_EN);
- grf_writel((1<<30)|gpio3d6_dir, GRF_GPIO3H_DIR);
- grf_writel((1<<30)|gpio3d6_do, GRF_GPIO3H_DO);
- sram_udelay(10000);
-
-#endif
-
-}
-extern void pwm_suspend_voltage(void);
-extern void pwm_resume_voltage(void);
-void rk30_pwm_suspend_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_suspend_voltage();
-#endif
-}
-void rk30_pwm_resume_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_resume_voltage();
-#endif
-}
-
-#if defined (CONFIG_TOUCHSCREEN_FT5406)
-#define TOUCH_RESET_PIN RK30_PIN0_PB6
-#define TOUCH_INT_PIN RK30_PIN1_PB7
-int ft5406_init_platform_hw(void)
-{
- printk("ft5406_init_platform_hw\n");
- if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
- gpio_free(TOUCH_RESET_PIN);
- printk("ft5406_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
- gpio_free(TOUCH_INT_PIN);
- printk("ift5406_init_platform_hw gpio_request error\n");
- return -EIO;
- }
-
- gpio_direction_output(TOUCH_RESET_PIN, 0);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- mdelay(10);
- gpio_direction_input(TOUCH_INT_PIN);
- mdelay(10);
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- msleep(300);
- return 0;
-}
-
-void ft5406_exit_platform_hw(void)
-{
- printk("ft5406_exit_platform_hw\n");
- gpio_free(TOUCH_RESET_PIN);
- gpio_free(TOUCH_INT_PIN);
-}
-
-int ft5406_platform_sleep(void)
-{
- printk("ft5406_platform_sleep\n");
- gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
- return 0;
-}
-
-int ft5406_platform_wakeup(void)
-{
- printk("ft5406_platform_wakeup\n");
- gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
- msleep(300);
- return 0;
-}
-
-struct ft5406_platform_data ft5406_info = {
-
- .init_platform_hw= ft5406_init_platform_hw,
- .exit_platform_hw= ft5406_exit_platform_hw,
- .platform_sleep = ft5406_platform_sleep,
- .platform_wakeup = ft5406_platform_wakeup,
-
-};
-#endif
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-#if defined (CONFIG_TOUCHSCREEN_FT5406)
- {
- .type ="ft5x0x_ts",
- .addr = 0x38, //0x70,
- .flags =0,
- .irq =RK30_PIN1_PB7, // support goodix tp detect, 20110706
- .platform_data = &ft5406_info,
- },
-#endif
-#if defined (CONFIG_TOUCHSCREEN_GT8XX)
- {
- .type = "Goodix-TS",
- .addr = 0x55,
- .flags = 0,
- .irq = RK30_PIN1_PB7,
- .platform_data = &goodix_info,
- },
-#endif
-
-#if defined (CONFIG_TOUCHSCREEN_FT5X0X)
- {
- .type = "ft5x0x_ts",
- .addr = 0x38,
- .flags = 0,
- .irq = RK30_PIN1_PB7,
- //.platform_data = &ft5x0x_info,
- .platform_data = &ts_hw_info,
- },
-#endif
-
-#if defined (CONFIG_LS_CM3217)
- {
- .type = "lightsensor",
- .addr = 0x10,
- .flags = 0,
- .platform_data = &cm3217_info,
- },
-#endif
-#if defined (CONFIG_LS_US5151)
- {
- .type = "us5151",
- .addr = 0x10,
- .flags = 0,
- },
-#endif
-//#ifdef CONFIG_U30GT_V3
-#if defined(CONFIG_HDMI_CAT66121)
- {
- .type = "cat66121_hdmi",
- .addr = 0x4c,
- .flags = 0,
- .irq = RK30_PIN2_PD6,
- .platform_data = &rk_hdmi_pdata,
- },
-#endif
-//#endif
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C4_RK30
-static struct i2c_board_info __initdata i2c4_info[] = {
-#if defined(CONFIG_HDMI_CAT6611)
- {
- .type = "cat6611_hdmi",
- .addr = 0x4c,
- .flags = 0,
- .irq = RK30_PIN1_PB7,
- },
-#endif
-//#ifdef CONFIG_U30GT_V3
-#if defined (CONFIG_SND_RK29_SOC_ES8323)
- {
- .type = "es8323",//"es8323",
- .addr = 0x10,
- .flags = 0,
- },
-#endif
-//#endif
-};
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO// RK30_PIN2_PD6 //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO//RK30_PIN2_PD7 //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- //set iomux (gpio) here
- //rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME, GPIO2D_GPIO2D7);
- //rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME, GPIO2D_GPIO2D6);
-
- return 0;
-}
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C4_RK30
- i2c_register_board_info(4, i2c4_info, ARRAY_SIZE(i2c4_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(5, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-
-// ========== Begin of rk3168 top board keypad defination ============
-
-#include <plat/key.h>
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .adc_value = 169,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK30_PIN0_PA4,
- .active_low = PRESS_LEV_LOW,
- .wakeup = 1,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .adc_value = 1,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-#if 0
- {
- .desc = "menu",
- .code = EV_MENU,
- .adc_value = 133,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .adc_value = 550,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .adc_value = 333,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "camera",
- .code = KEY_CAMERA,
- .adc_value = 742,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-#endif
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = 1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
-// =========== End of rk3168 top board keypad defination =============
-
-
-#define POWER_ON_PIN RK30_PIN0_PA0 //power_hold
-static void rk30_pm_power_off(void)
-{
- printk(KERN_ERR "rk30_pm_power_off start...\n");
- #if defined(CONFIG_MFD_WM831X)
- if(pmic_is_wm8326()){
- wm831x_set_bits(Wm831x,WM831X_GPIO_LEVEL,0x0001,0x0000); //set sys_pwr 0
- wm831x_device_shutdown(Wm831x);//wm8326 shutdown
- }
- #endif
-
- #if defined(CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- {
- act8846_device_shutdown();
- }
- #endif
-
- #if defined(CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- {
- tps65910_device_shutdown();//tps65910 shutdown
- }
- #endif
-
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
- while (1);
-}
-
-static void __init machine_rk30_board_init(void)
-{
- //avs_init();
- writel_relaxed(0x03000300, RK30_GRF_BASE + 0xf8);
- gpio_request(POWER_ON_PIN, "poweronpin");
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
- // gpio_direction_output(RK30_PIN1_PB4, GPIO_LOW);
- //gpio_direction_output(RK30_PIN3_PD5, GPIO_HIGH);
-
- pm_power_off = rk30_pm_power_off;
-
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
-
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- rk_platform_add_display_devices();
- // board_usb_detect_init(RK30_PIN0_PA7);
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC)
- rk29sdk_wifi_bt_gpio_control_init();
-#elif defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- rk29sdk_wifi_combo_module_gpio_init();
-#endif
-
-#if defined(CONFIG_MT6620)
- clk_set_rate(clk_get_sys("rk_serial.0", "uart"), 48*1000000);
-#endif
-}
-#define HD_SCREEN_SIZE 1920UL*1200UL*4*3
-static void __init rk30_reserve(void)
-{
-#if defined(CONFIG_ARCH_RK3188)
- /*if lcd resolution great than or equal to 1920*1200,reserve the ump memory */
- if(!(get_fb_size() < ALIGN(HD_SCREEN_SIZE,SZ_1M)))
- {
- int ump_mem_phy_size=512UL*1024UL*1024UL;
- resource_mali[0].start = board_mem_reserve_add("ump buf", ump_mem_phy_size);
- resource_mali[0].end = resource_mali[0].start + ump_mem_phy_size -1;
- }
-#endif
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0 buf", get_fb_size());
- resource_fb[0].end = resource_fb[0].start + get_fb_size()- 1;
-#if 0
- resource_fb[1].start = board_mem_reserve_add("ipp buf", RK30_FB0_MEM_SIZE);
- resource_fb[1].end = resource_fb[1].start + RK30_FB0_MEM_SIZE - 1;
-#endif
-
-#if defined(CONFIG_FB_ROTATE) || !defined(CONFIG_THREE_FB_BUFFER)
- resource_fb[2].start = board_mem_reserve_add("fb2 buf",get_fb_size());
- resource_fb[2].end = resource_fb[2].start + get_fb_size() - 1;
-#endif
-#endif
-
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
-
-#ifdef CONFIG_GPS_RK
- //it must be more than 8MB
- rk_gps_info.u32MemoryPhyAddr = board_mem_reserve_add("gps", SZ_8M);
-#endif
- board_mem_reserved();
-}
-/******************************** arm dvfs frequency volt table **********************************/
-/**
- * dvfs_cpu_logic_table: table for arm and logic dvfs
- * @frequency : arm frequency
- * @cpu_volt : arm voltage depend on frequency
- */
-
-#if 0
-//sdk
-static struct cpufreq_frequency_table dvfs_arm_table_volt_level0[] = {
- {.frequency = 312 * 1000, .index = 850 * 1000},
- {.frequency = 504 * 1000, .index = 900 * 1000},
- {.frequency = 816 * 1000, .index = 950 * 1000},
- {.frequency = 1008 * 1000, .index = 1025 * 1000},
- {.frequency = 1200 * 1000, .index = 1100 * 1000},
- {.frequency = 1416 * 1000, .index = 1200 * 1000},
- {.frequency = 1608 * 1000, .index = 1300 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-//default
-static struct cpufreq_frequency_table dvfs_arm_table_volt_level1[] = {
- {.frequency = 312 * 1000, .index = 875 * 1000},
- {.frequency = 504 * 1000, .index = 925 * 1000},
- {.frequency = 816 * 1000, .index = 975 * 1000},
- {.frequency = 1008 * 1000, .index = 1075 * 1000},
- {.frequency = 1200 * 1000, .index = 1150 * 1000},
- {.frequency = 1416 * 1000, .index = 1250 * 1000},
- {.frequency = 1608 * 1000, .index = 1350 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-#endif
-// cube 10'
-static struct cpufreq_frequency_table dvfs_arm_table_volt_level2[] = {
- {.frequency = 312 * 1000, .index = 900 * 1000},
- {.frequency = 504 * 1000, .index = 925 * 1000},
- {.frequency = 816 * 1000, .index = 1000 * 1000},
- {.frequency = 1008 * 1000, .index = 1075 * 1000},
- {.frequency = 1200 * 1000, .index = 1200 * 1000},
- {.frequency = 1416 * 1000, .index = 1250 * 1000},
- {.frequency = 1608 * 1000, .index = 1350 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-//if you board is good for volt quality,select dvfs_arm_table_volt_level0
-#define dvfs_arm_table dvfs_arm_table_volt_level2
-
-/******************************** gpu dvfs frequency volt table **********************************/
-//sdk
-static struct cpufreq_frequency_table dvfs_gpu_table_volt_level0[] = {
-#if defined(CONFIG_ARCH_RK3188)
- {.frequency = 133 * 1000, .index = 975 * 1000},//the mininum rate is limited 133M for rk3188
-#elif defined(CONFIG_ARCH_RK3066B)
- {.frequency = 100 * 1000, .index = 950 * 1000},//the minimum rate is no limit for rk3168 rk3066B
-#endif
-
- {.frequency = 200 * 1000, .index = 1025 * 1000},
- {.frequency = 266 * 1000, .index = 1025 * 1000},
- {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1100 * 1000},
- {.frequency = 600 * 1000, .index = 1250 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-#if 0
-//cube 10'
-static struct cpufreq_frequency_table dvfs_gpu_table_volt_level1[] = {
-#if defined(CONFIG_ARCH_RK3188)
- {.frequency = 133 * 1000, .index = 975 * 1000},//the mininum rate is limited 133M for rk3188
-#elif defined(CONFIG_ARCH_RK3066B)
- {.frequency = 100 * 1000, .index = 950 * 1000},//the minimum rate is no limit for rk3168 rk3066B
-#endif
-
- {.frequency = 200 * 1000, .index = 1000 * 1000},
- {.frequency = 266 * 1000, .index = 1025 * 1000},
- {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1100 * 1000},
- {.frequency = 600 * 1000, .index = 1250 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-#endif
-
-#define dvfs_gpu_table dvfs_gpu_table_volt_level0
-
-/******************************** ddr dvfs frequency volt table **********************************/
-static struct cpufreq_frequency_table dvfs_ddr_table_volt_level0[] = {
-#if defined(CONFIG_ARCH_RK3188)
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 950 * 1000},
-// {.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = 1000 * 1000},
-#endif
- {.frequency = 528* 1000 + DDR_FREQ_NORMAL, .index = 1250 * 1000},
-// {.frequency = 400 * 1000 + DDR_FREQ_NORMAL, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-#define dvfs_ddr_table dvfs_ddr_table_volt_level0
-
-/******************************** arm dvfs frequency volt table end **********************************/
-
-
-
-//#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
-//static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
-//static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
-
-void __init board_clock_init(void)
-{
- rk30_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
- //dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "cpu"), dvfs_arm_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
-}
-
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk30_fixup,
- .reserve = &rk30_reserve,
- .map_io = rk30_map_io,
- .init_irq = rk30_init_irq,
- .timer = &rk30_timer,
- .init_machine = machine_rk30_board_init,
-MACHINE_END
+++ /dev/null
-#ifdef CONFIG_VIDEO_RK29
-#include <plat/rk_camera.h>
-/* Notes:
-
-Simple camera device registration:
-
- new_camera_device(sensor_name,\ // sensor name, it is equal to CONFIG_SENSOR_X
- face,\ // sensor face information, it can be back or front
- pwdn_io,\ // power down gpio configuration, it is equal to CONFIG_SENSOR_POWERDN_PIN_XX
- flash_attach,\ // sensor is attach flash or not
- mir,\ // sensor image mirror and flip control information
- i2c_chl,\ // i2c channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_IIC_ADAPTER_ID_X
- cif_chl) \ // cif channel which the sensor attached in hardware, it is equal to CONFIG_SENSOR_CIF_INDEX_X
-
-Comprehensive camera device registration:
-
- new_camera_device_ex(sensor_name,\
- face,\
- ori,\ // sensor orientation, it is equal to CONFIG_SENSOR_ORIENTATION_X
- pwr_io,\ // sensor power gpio configuration, it is equal to CONFIG_SENSOR_POWER_PIN_XX
- pwr_active,\ // sensor power active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- rst_io,\ // sensor reset gpio configuration, it is equal to CONFIG_SENSOR_RESET_PIN_XX
- rst_active,\ // sensor reset active level, is equal to CONFIG_SENSOR_RESETACTIVE_LEVEL_X
- pwdn_io,\
- pwdn_active,\ // sensor power down active level, is equal to CONFIG_SENSOR_POWERDNACTIVE_LEVEL_X
- flash_attach,\
- res,\ // sensor resolution, this is real resolution or resoltuion after interpolate
- mir,\
- i2c_chl,\
- i2c_spd,\ // i2c speed , 100000 = 100KHz
- i2c_addr,\ // the i2c slave device address for sensor
- cif_chl,\
- mclk)\ // sensor input clock rate, 24 or 48
-
-*/
-static struct rkcamera_platform_data new_camera[] = {
-
- new_camera_device(RK29_CAM_SENSOR_NT99340,
- back,
- RK30_PIN3_PB5,
- 0,
- 0,
- 3,
- 0),
- new_camera_device(RK29_CAM_SENSOR_NT99252,
- front,
- RK30_PIN3_PB4,
- 0,
- 0,
- 3,
- 0),
- new_camera_device_end
-};
-
-#endif //#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk30_camera.c"
-/*---------------- Camera Sensor Macro Define End ---------*/
-
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#ifdef CONFIG_VIDEO_RK29
-#define CONFIG_SENSOR_POWER_IOCTL_USR 1 //define this refer to your board layout
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
-
-static void rk_cif_power(struct rk29camera_gpio_res *res,int on)
-{
- struct regulator *ldo_18,*ldo_28;
- int camera_power = res->gpio_power;
- int camera_ioflag = res->gpio_flag;
- int camera_io_init = res->gpio_init;
-
- ldo_28 = regulator_get(NULL, "ricoh_ldo4"); // vcc28_cif
- ldo_18 = regulator_get(NULL, "ricoh_ldo5"); // vcc18_cif
- if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){
- printk("get cif ldo failed!\n");
- return;
- }
- if(on == 0){
- while(regulator_is_enabled(ldo_28)>0)
- regulator_disable(ldo_28);
- regulator_put(ldo_28);
- while(regulator_is_enabled(ldo_18)>0)
- regulator_disable(ldo_18);
- regulator_put(ldo_18);
- mdelay(10);
- if (camera_power != INVALID_GPIO) {
- if (camera_io_init & RK29_CAM_POWERACTIVE_MASK) {
- gpio_set_value(camera_power, (((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
- // dprintk("%s..%s..PowerPin=%d ..PinLevel = %x \n",__FUNCTION__,res->dev_name, camera_power, (((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
- }
- }
- }
- else{
- regulator_set_voltage(ldo_28, 2800000, 2800000);
- regulator_enable(ldo_28);
- printk("%s set vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
- regulator_put(ldo_28);
-
- regulator_set_voltage(ldo_18, 1800000, 1800000);
- // regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(ldo_18);
- printk("%s set vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
- regulator_put(ldo_18);
- if (camera_power != INVALID_GPIO) {
- if (camera_io_init & RK29_CAM_POWERACTIVE_MASK) {
- gpio_set_value(camera_power, ((camera_ioflag&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
- //dprintk("%s..%s..PowerPin=%d ..PinLevel = %x \n",__FUNCTION__,res->dev_name, camera_power, ((camera_ioflag&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
- mdelay(10);
- }
- }
-
- }
-}
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- //#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
- rk_cif_power(res,on);
- return 0;
-}
-#endif
-
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-
-
-static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] =
-{
- #if CONFIG_SENSOR_IIC_ADDR_0
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_0,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_1
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_1,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_01
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_01,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_02
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_02,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_11
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_11,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_12
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_12,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
-
- };
-#include "../../../drivers/media/video/rk30_camera.c"
-
-#endif /* CONFIG_VIDEO_RK29 */
+++ /dev/null
-/*
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <mach/dvfs.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <linux/rk_fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/mfd/tps65910.h>
-#include <linux/regulator/act8846.h>
-#include <linux/mfd/rk808.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-
-
-#ifdef CONFIG_CW2015_BATTERY
-#include <linux/power/cw2015_battery.h>
-#endif
-#if defined(CONFIG_MFD_RK610)
-#include <linux/mfd/rk610_core.h>
-#endif
-
-#if defined(CONFIG_MFD_RK616)
-#include <linux/mfd/rk616.h>
-#endif
-
-#if defined (CONFIG_RK_HEADSET_DET) || defined (CONFIG_RK_HEADSET_IRQ_HOOK_ADC_DET)
-#include "../../../drivers/headset_observe/rk_headset.h"
-#endif
-
-#if defined(CONFIG_RK_HDMI)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-#if defined(CONFIG_GPS_RK)
-#include "../../../drivers/misc/gps/rk_gps/rk_gps.h"
-#endif
-#if defined(CONFIG_MU509)
-#include <linux/mu509.h>
-#endif
-#if defined(CONFIG_MW100)
-#include <linux/mw100.h>
-#endif
-#if defined(CONFIG_MT6229)
-#include <linux/mt6229.h>
-#endif
-#if defined(CONFIG_ANDROID_TIMED_GPIO)
-#include "../../../drivers/staging/android/timed_gpio.h"
-#endif
-
-#if defined(CONFIG_MT6620)
-#include <linux/gps.h>
-#endif
-#include "board-rk3188m-f304-camera.c"
-
-#if defined(CONFIG_TOUCHSCREEN_GT8XX)
-#define TOUCH_RESET_PIN RK30_PIN0_PB6
-#define TOUCH_PWR_PIN RK30_PIN0_PC5 // need to fly line by hardware engineer
-
-/* Android Parameter */
-static int ap_mdm = 0;
-module_param(ap_mdm, int, 0644);
-static int ap_has_alsa = 0;
-module_param(ap_has_alsa, int, 0644);
-static int ap_data_only = 2;
-module_param(ap_data_only, int, 0644);
-static int ap_has_earphone = 0;
-module_param(ap_has_earphone, int, 0644);
-
-
-static int goodix_init_platform_hw(void)
-{
- int ret;
-
- if (TOUCH_PWR_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_PWR_PIN, "goodix power pin");
- if (ret != 0) {
- gpio_free(TOUCH_PWR_PIN);
- printk("goodix power error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_PWR_PIN, 0);
- gpio_set_value(TOUCH_PWR_PIN, GPIO_LOW);
- msleep(100);
- }
-
- if (TOUCH_RESET_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_RESET_PIN, "goodix reset pin");
- if (ret != 0) {
- gpio_free(TOUCH_RESET_PIN);
- printk("goodix gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, 1);
- msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_LOW);
- //msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_HIGH);
- //msleep(500);
- }
- return 0;
-}
-
-struct goodix_platform_data goodix_info = {
- .model = 8105,
- .irq_pin = RK30_PIN1_PB7,
- .rest_pin = TOUCH_RESET_PIN,
- .init_platform_hw = goodix_init_platform_hw,
-};
-#endif
-
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-#define PWM_ID 3
-#define PWM_MODE PWM3
-#define PWM_EFFECT_VALUE 0
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-#define BL_EN_PIN RK30_PIN0_PA2
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
-
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
- ret = gpio_request(BL_EN_PIN, "bl_en");
- if (ret == 0) {
- gpio_direction_output(BL_EN_PIN, BL_EN_VALUE);
- }
-#endif
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0, pwm_gpio;
-#ifdef LCD_DISP_ON_PIN
- gpio_free(BL_EN_PIN);
-#endif
- pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
- gpio_request(pwm_gpio, "bl_pwm");
- gpio_direction_output(pwm_gpio, GPIO_LOW);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret, pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
-
- ret = gpio_request(pwm_gpio, "bl_pwm");
- if (ret) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return ret;
- }
- gpio_direction_output(pwm_gpio, GPIO_LOW);
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, !BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- int pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
-
- gpio_free(pwm_gpio);
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .min_brightness=100,
- .max_brightness=255,
- .pre_div = 400 * 1000,
- .brightness_mode = BRIGHTNESS_MODE_CONIC,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-#endif
-
-#ifdef CONFIG_RK29_SUPPORT_MODEM
-
-#define RK30_MODEM_POWER RK30_PIN0_PC6
-#define RK30_MODEM_POWER_IOMUX iomux_set(GPIO0_C6)
-
-static int rk30_modem_io_init(void)
-{
- printk("%s\n", __FUNCTION__);
- RK30_MODEM_POWER_IOMUX;
-
- return 0;
-}
-
-static struct rk29_io_t rk30_modem_io = {
- .io_addr = RK30_MODEM_POWER,
- .enable = GPIO_HIGH,
- .disable = GPIO_LOW,
- .io_init = rk30_modem_io_init,
-};
-
-static struct platform_device rk30_device_modem = {
- .name = "rk30_modem",
- .id = -1,
- .dev = {
- .platform_data = &rk30_modem_io,
- }
-};
-#endif
-#if defined(CONFIG_MU509)
-static int mu509_io_init(void)
-{
-
- iomux_set(GPIO2_D5);
- iomux_set(GPIO0_C6);
- iomux_set(GPIO2_D4);
- iomux_set(GPIO0_C4);
- iomux_set(GPIO0_C5);
- return 0;
-}
-
-static int mu509_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mu509_data rk29_mu509_info = {
- .io_init = mu509_io_init,
- .io_deinit = mu509_io_deinit,
- .modem_power_en = RK30_PIN2_PD5,
- .bp_power = RK30_PIN0_PC6,
- .bp_reset = RK30_PIN2_PD4,
- .ap_wakeup_bp = RK30_PIN0_PC4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
-};
-struct platform_device rk29_device_mu509 = {
- .name = "mu509",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mu509_info,
- }
- };
-#endif
-#if defined(CONFIG_MW100)
-static int mw100_io_init(void)
-{
- iomux_set(GPIO2_D5);
- iomux_set(GPIO0_C6);
- iomux_set(GPIO2_D4);
- iomux_set(GPIO0_C4);
- iomux_set(GPIO0_C5);
- return 0;
-}
-
-static int mw100_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mw100_data rk29_mw100_info = {
- .io_init = mw100_io_init,
- .io_deinit = mw100_io_deinit,
- .modem_power_en = RK30_PIN2_PD5,
- .bp_power = RK30_PIN0_PC6,
- .bp_reset = RK30_PIN2_PD4,
- .ap_wakeup_bp = RK30_PIN0_PC4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
-};
-struct platform_device rk29_device_mw100 = {
- .name = "mw100",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mw100_info,
- }
- };
-#endif
-#if defined(CONFIG_MT6229)
-static int mt6229_io_init(void)
-{
- iomux_set(GPIO2_D5);
- iomux_set(GPIO0_C6);
- iomux_set(GPIO2_D4);
- iomux_set(GPIO0_C4);
- iomux_set(GPIO0_C5);
- return 0;
-}
-
-static int mt6229_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mt6229_data rk29_mt6229_info = {
- .io_init = mt6229_io_init,
- .io_deinit = mt6229_io_deinit,
- .modem_power_en = RK30_PIN2_PD5,
- .bp_power = RK30_PIN0_PC6,
- .bp_reset = RK30_PIN2_PD4,
- .ap_wakeup_bp = RK30_PIN0_PC4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
-};
-struct platform_device rk29_device_mt6229 = {
- .name = "mt6229",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mt6229_info,
- }
- };
-#endif
-
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN RK30_PIN0_PB7
-
-static int mma8452_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data mma8452_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma8452_init_platform_hw,
- // .orientation = {-1, 0, 0, 0, -1, 0, 0, 0, 1},
- .orientation = {1, 0, 0, 0, -1, 0, 0, 0, -1},
-};
-#endif
-#if defined (CONFIG_GS_LIS3DH)
-#define LIS3DH_INT_PIN RK30_PIN0_PB7
-
-static int lis3dh_init_platform_hw(void)
-{
-
- return 0;
-}
-
-static struct sensor_platform_data lis3dh_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lis3dh_init_platform_hw,
- .orientation = {-1, 0, 0, 0, -1, 0, 0, 0, 1},
-};
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
-static struct sensor_platform_data akm8975_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-#if defined(CONFIG_GYRO_L3G4200D)
-
-#include <linux/l3g4200d.h>
-#define L3G4200D_INT_PIN RK30_PIN0_PB4
-
-static int l3g4200d_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data l3g4200d_info = {
- .type = SENSOR_TYPE_GYROSCOPE,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
- .init_platform_hw = l3g4200d_init_platform_hw,
- .x_min = 40,//x_min,y_min,z_min = (0-100) according to hardware
- .y_min = 40,
- .z_min = 20,
-};
-
-#endif
-
-#ifdef CONFIG_LS_CM3217
-static struct sensor_platform_data cm3217_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 0,
- .poll_delay_ms = 500,
-};
-
-#endif
-
-#ifdef CONFIG_FB_ROCKCHIP
-
-#define LCD_CS_PIN INVALID_GPIO
-#define LCD_CS_VALUE GPIO_HIGH
-
-#define LCD_EN_PIN RK30_PIN0_PB0
-#define LCD_EN_VALUE GPIO_LOW
-
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
-
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_CS_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_CS_PIN);
- printk(KERN_ERR "request lcd cs pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_CS_PIN, LCD_CS_VALUE);
- }
- }
-
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_EN_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_EN_PIN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_EN_PIN, LCD_EN_VALUE);
- }
- }
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, !LCD_CS_VALUE);
- }
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, !LCD_EN_VALUE);
- }
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE);
- }
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
- }
- return 0;
-}
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
-struct rk29fb_info lcdc0_screen_info = {
- #if defined(CONFIG_RK_HDMI)
- .prop = EXTEND, //extend display device
- .lcd_info = NULL,
- .set_screen_info = hdmi_init_lcdc,
- #endif
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
-struct rk29fb_info lcdc1_screen_info = {
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-#if defined(CONFIG_ARCH_RK3188)
-static struct resource resource_mali[] = {
- [0] = {
- .name = "ump buf",
- .start = 0,
- .end = 0,
- .flags = IORESOURCE_MEM,
- },
-
-};
-
-static struct platform_device device_mali= {
- .name = "mali400_ump",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_mali),
- .resource = resource_mali,
-};
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
-static struct resource resource_lcdc0[] = {
- [0] = {
- .name = "lcdc0 reg",
- .start = RK30_LCDC0_PHYS,
- .end = RK30_LCDC0_PHYS + RK30_LCDC0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc0 irq",
- .start = IRQ_LCDC0,
- .end = IRQ_LCDC0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc0 = {
- .name = "rk30-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc0),
- .resource = resource_lcdc0,
- .dev = {
- .platform_data = &lcdc0_screen_info,
- },
-};
-#endif
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
-static struct resource resource_lcdc1[] = {
- [0] = {
- .name = "lcdc1 reg",
- .start = RK30_LCDC1_PHYS,
- .end = RK30_LCDC1_PHYS + RK30_LCDC1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc1 irq",
- .start = IRQ_LCDC1,
- .end = IRQ_LCDC1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc1 = {
- .name = "rk30-lcdc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resource_lcdc1),
- .resource = resource_lcdc1,
- .dev = {
- .platform_data = &lcdc1_screen_info,
- },
-};
-#endif
-
-#if defined(CONFIG_MFD_RK610)
-#define RK610_RST_PIN RK30_PIN2_PC5
-static int rk610_power_on_init(void)
-{
- int ret;
- if(RK610_RST_PIN != INVALID_GPIO)
- {
- ret = gpio_request(RK610_RST_PIN, "rk610 reset");
- if (ret)
- {
- printk(KERN_ERR "rk610_control_probe request gpio fail\n");
- }
- else
- {
- gpio_direction_output(RK610_RST_PIN, GPIO_HIGH);
- msleep(100);
- gpio_direction_output(RK610_RST_PIN, GPIO_LOW);
- msleep(100);
- gpio_set_value(RK610_RST_PIN, GPIO_HIGH);
- }
- }
-
- return 0;
-
-}
-
-
-static struct rk610_ctl_platform_data rk610_ctl_pdata = {
- .rk610_power_on_init = rk610_power_on_init,
-};
-#endif
-
-#if defined(CONFIG_MFD_RK616)
-#define RK616_RST_PIN RK30_PIN2_PD5
-#define RK616_PWREN_PIN RK30_PIN0_PB0
-#define RK616_SPK_CTL2 RK30_PIN2_PD7
-#define RK616_SCL_RATE (80*1000) //i2c scl rate
-static int rk616_power_on_init(void)
-{
- int ret;
-#if 0
- if(RK616_SPK_CTL2 != INVALID_GPIO)
- {
- ret = gpio_request(RK616_SPK_CTL2, "rk616 spk ctl2");
- if (ret)
- {
- printk(KERN_ERR "rk616 spk_ctl2 gpio request fail\n");
- }
- else
- {
- gpio_direction_output(RK616_SPK_CTL2,GPIO_HIGH);
- }
- }
-#endif
- if(RK616_PWREN_PIN != INVALID_GPIO)
- {
- ret = gpio_request(RK616_PWREN_PIN, "rk616 pwren");
- if (ret)
- {
- printk(KERN_ERR "rk616 pwren gpio request fail\n");
- }
- else
- {
- gpio_direction_output(RK616_PWREN_PIN,GPIO_LOW);
- mdelay(200);
- }
- }
-
- if(RK616_RST_PIN != INVALID_GPIO)
- {
- ret = gpio_request(RK616_RST_PIN, "rk616 reset");
- if (ret)
- {
- printk(KERN_ERR "rk616 reset gpio request fail\n");
- }
- else
- {
- gpio_direction_output(RK616_RST_PIN, GPIO_HIGH);
- mdelay(200);;
- gpio_direction_output(RK616_RST_PIN, GPIO_LOW);
- mdelay(200);
- gpio_set_value(RK616_RST_PIN, GPIO_HIGH);
- }
- }
-
- return 0;
-
-}
-
-
-static struct rk616_platform_data rk616_pdata = {
- .power_init = rk616_power_on_init,
- .scl_rate = RK616_SCL_RATE,
- .lcd0_func = INPUT, //port lcd0 as input
- .lcd1_func = INPUT, //port lcd1 as input
- .lvds_ch_nr = 0, //the number of used lvds channel
- .hdmi_irq = RK30_PIN2_PD4,
- .spk_ctl_gpio = RK30_PIN2_PD7,
-// .hp_ctl_gpio = RK30_PIN2_PD7,
-};
-#endif
-
-#if defined (CONFIG_RK_HEADSET_DET) || defined (CONFIG_RK_HEADSET_IRQ_HOOK_ADC_DET)
-
-static int rk_headset_io_init(int gpio)
-{
- int ret;
- ret = gpio_request(gpio, "headset_input");
- if(ret)
- return ret;
-
- //rk30_mux_api_set(iomux_name, iomux_mode);
- gpio_pull_updown(gpio, PullDisable);
- gpio_direction_input(gpio);
- return 0;
-};
-
-struct rk_headset_pdata rk_headset_info = {
- .Headset_gpio = RK30_PIN0_PD3,
- .headset_in_type = HEADSET_IN_LOW,
- .Hook_adc_chn = 2,
- .hook_key_code = KEY_MEDIA,
- .headset_io_init = rk_headset_io_init,
-};
-
-struct platform_device rk_device_headset = {
- .name = "rk_headsetdet",
- .id = 0,
- .dev = {
- .platform_data = &rk_headset_info,
- }
-};
-#endif
-
-
-#ifdef CONFIG_SND_SOC_RK610
-static int rk610_codec_io_init(void)
-{
-//if need iomux.
-//Must not gpio_request
- return 0;
-}
-
-static struct rk610_codec_platform_data rk610_codec_pdata = {
- .spk_ctl_io = RK30_PIN2_PD7,
- .io_init = rk610_codec_io_init,
-};
-#endif
-
-#ifdef CONFIG_ANDROID_TIMED_GPIO
-static struct timed_gpio timed_gpios[] = {
- {
- .name = "vibrator",
- .gpio = INVALID_GPIO,
- .max_timeout = 1000,
- .active_low = 0,
- .adjust_time =20, //adjust for diff product
- },
-};
-
-static struct timed_gpio_platform_data rk29_vibrator_info = {
- .num_gpios = 1,
- .gpios = timed_gpios,
-};
-
-static struct platform_device rk29_device_vibrator = {
- .name = "timed-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_vibrator_info,
- },
-
-};
-#endif
-
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
-static struct gpio_led rk29_leds[] = {
- {
- .name = "button-backlight",
- .gpio = INVALID_GPIO,
- .default_trigger = "timer",
- .active_low = 0,
- .retain_state_suspended = 0,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- },
-};
-
-static struct gpio_led_platform_data rk29_leds_pdata = {
- .leds = rk29_leds,
- .num_leds = ARRAY_SIZE(rk29_leds),
-};
-
-static struct platform_device rk29_device_gpio_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_leds_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_RK_IRDA
-#define IRDA_IRQ_PIN INVALID_GPIO //RK30_PIN0_PA3
-
-static int irda_iomux_init(void)
-{
- int ret = 0;
-
- //irda irq pin
- ret = gpio_request(IRDA_IRQ_PIN, NULL);
- if (ret != 0) {
- gpio_free(IRDA_IRQ_PIN);
- printk(">>>>>> IRDA_IRQ_PIN gpio_request err \n ");
- }
- gpio_pull_updown(IRDA_IRQ_PIN, PullDisable);
- gpio_direction_input(IRDA_IRQ_PIN);
-
- return 0;
-}
-
-static int irda_iomux_deinit(void)
-{
- gpio_free(IRDA_IRQ_PIN);
- return 0;
-}
-
-static struct irda_info rk29_irda_info = {
- .intr_pin = IRDA_IRQ_PIN,
- .iomux_init = irda_iomux_init,
- .iomux_deinit = irda_iomux_deinit,
- //.irda_pwr_ctl = bu92747guw_power_ctl,
-};
-
-static struct platform_device irda_device = {
-#ifdef CONFIG_RK_IRDA_NET
- .name = "rk_irda",
-#else
- .name = "bu92747_irda",
-#endif
- .id = -1,
- .dev = {
- .platform_data = &rk29_irda_info,
- }
-};
-#endif
-
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and sdio.noted by xbw at 2012-03-05
-**************************************************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "../mach-rk30/board-rk3168-tb-sdmmc-conifg.c"
-#include "../plat-rk/rk-sdmmc-ops.c"
-#include "../plat-rk/rk-sdmmc-wifi.c"
-#endif //endif ---#ifdef CONFIG_SDMMC_RK29
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- iomux_set(MMC0_CMD);
- iomux_set(MMC0_CLKOUT);
- iomux_set(MMC0_D0);
- iomux_set(MMC0_D1);
- iomux_set(MMC0_D2);
- iomux_set(MMC0_D3);
-
- iomux_set_gpio_mode(iomux_mode_to_gpio(MMC0_DETN));
-
- gpio_request(RK30_PIN3_PA7, "sdmmc-power");
- gpio_direction_output(RK30_PIN3_PA7, GPIO_LOW);
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- #if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set_gpio_mode(iomux_gpio_to_mode(RK29SDK_SD_CARD_DETECT_N));
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO);
- #endif
- #else
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(MMC0_DETN);
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FMUX);
- #endif
- #endif
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) && defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- .status = rk29sdk_wifi_mmc0_status,
- .register_status_notify = rk29sdk_wifi_mmc0_status_register,
-#endif
-
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .power_en = RK29SDK_SD_CARD_PWR_EN,
- .power_en_level = RK29SDK_SD_CARD_PWR_EN_LEVEL,
-#else
- .power_en = INVALID_GPIO,
- .power_en_level = GPIO_LOW,
-#endif
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC0_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- .det_pin_info = {
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N, //INVALID_GPIO,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
- #endif
- },
-
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- iomux_set(MMC1_CMD);
- iomux_set(MMC1_CLKOUT);
- iomux_set(MMC1_D0);
- iomux_set(MMC1_D1);
- iomux_set(MMC1_D2);
- iomux_set(MMC1_D3);
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC) || defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC1_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- #if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
- .sdio_INT_gpio = RK29SDK_WIFI_SDIO_CARD_INT,
- #endif
-
- .det_pin_info = {
-#if defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- #else
- .io = INVALID_GPIO,
- #endif
-
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-
- .enable_sd_wakeup = 0,
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-/**************************************************************************************************
- * the end of setting for SDMMC devices
-**************************************************************************************************/
-
-#ifdef CONFIG_BATTERY_RK30_ADC
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = RK30_PIN0_PB2,
- .batt_low_pin = RK30_PIN0_PB1,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = RK30_PIN0_PA6,
- .dc_det_level = GPIO_LOW,
- .charge_ok_level = GPIO_HIGH,
-};
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-#ifdef CONFIG_CW2015_BATTERY
-/*
- note the follow array must set depend on the battery that you use
- you must send the battery to cellwise-semi the contact information:
- name: chen gan; tel:13416876079; E-mail: ben.chen@cellwise-semi.com
- */
-static u8 config_info[SIZE_BATINFO] = {
- 0x15, 0x42, 0x60, 0x59, 0x52,
- 0x58, 0x4D, 0x48, 0x48, 0x44,
- 0x44, 0x46, 0x49, 0x48, 0x32,
- 0x24, 0x20, 0x17, 0x13, 0x0F,
- 0x19, 0x3E, 0x51, 0x45, 0x08,
- 0x76, 0x0B, 0x85, 0x0E, 0x1C,
- 0x2E, 0x3E, 0x4D, 0x52, 0x52,
- 0x57, 0x3D, 0x1B, 0x6A, 0x2D,
- 0x25, 0x43, 0x52, 0x87, 0x8F,
- 0x91, 0x94, 0x52, 0x82, 0x8C,
- 0x92, 0x96, 0xFF, 0x7B, 0xBB,
- 0xCB, 0x2F, 0x7D, 0x72, 0xA5,
- 0xB5, 0xC1, 0x46, 0xAE
-};
-
-static struct cw_bat_platform_data cw_bat_platdata = {
- .dc_det_pin = RK30_PIN0_PB2,
- .bat_low_pin = RK30_PIN0_PB1,
- .chg_ok_pin = RK30_PIN0_PA6,
- .dc_det_level = GPIO_LOW,
- .bat_low_level = GPIO_LOW,
- .chg_ok_level = GPIO_HIGH,
-
- .cw_bat_config_info = config_info,
-
-};
-
-#endif
-#ifdef CONFIG_RK30_PWM_REGULATOR
-static int pwm_voltage_map[] = {
- 800000,825000,850000, 875000,900000, 925000 ,950000, 975000,1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000,1375000
-};
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_cpu",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] =
-{
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
- .pwm_id = 1,
- .pwm_gpio = RK30_PIN3_PD4,
- .pwm_iomux_pwm = PWM1,
- .pwm_iomux_gpio = GPIO3_D4,
- .pwm_voltage = 1100000,
- .suspend_voltage = 1000000,
- .min_uV = 800000,
- .max_uV = 1375000,
- .coefficient = 575, //57.5%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-#endif
-
-#ifdef CONFIG_RK29_VMAC
-#define PHY_PWR_EN_GPIO RK30_PIN1_PD6
-#include "board-rk30-sdk-vmac.c"
-#endif
-
-#ifdef CONFIG_RFKILL_RK
-// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
-static struct rfkill_rk_platform_data rfkill_rk_platdata = {
- .type = RFKILL_TYPE_BLUETOOTH,
-
- .poweron_gpio = { // BT_REG_ON
- .io = RK30_PIN3_PC7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_poweron",
- .fgpio = GPIO3_C7,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN3_PD1, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_reset",
- .fgpio = GPIO3_D1,
- },
- },
-
- .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
- .io = RK30_PIN3_PC6, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_wake",
- .fgpio = GPIO3_C6,
- },
- },
-
- .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .gpio = {
- .io = RK30_PIN0_PA5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
- .iomux = {
- .name = NULL,
- },
- },
- },
-
- .rts_gpio = { // UART_RTS, enable or disable BT's data coming
- .io = INVALID_GPIO, //RK30_PIN1_PA3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_rts",
- .fgpio = GPIO1_A3,
- .fmux = UART0_RTSN,
- },
- },
-};
-
-static struct platform_device device_rfkill_rk = {
- .name = "rfkill_rk",
- .id = -1,
- .dev = {
- .platform_data = &rfkill_rk_platdata,
- },
-};
-#endif
-
-#if defined(CONFIG_GPS_RK)
-int rk_gps_io_init(void)
-{
- printk("%s \n", __FUNCTION__);
-
- gpio_request(RK30_PIN1_PB5, NULL);
- gpio_direction_output(RK30_PIN1_PB5, GPIO_LOW);
-
- iomux_set(GPS_RFCLK);//GPS_CLK
- iomux_set(GPS_MAG);//GPS_MAG
- iomux_set(GPS_SIG);//GPS_SIGN
-
- gpio_request(RK30_PIN1_PA6, NULL);
- gpio_direction_output(RK30_PIN1_PA6, GPIO_LOW);
-
- gpio_request(RK30_PIN1_PA5, NULL);
- gpio_direction_output(RK30_PIN1_PA5, GPIO_LOW);
-
- gpio_request(RK30_PIN1_PA7, NULL);
- gpio_direction_output(RK30_PIN1_PA7, GPIO_LOW);
- return 0;
-}
-int rk_gps_power_up(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_power_down(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_reset_set(int level)
-{
- return 0;
-}
-int rk_enable_hclk_gps(void)
-{
- struct clk *gps_aclk = NULL;
- gps_aclk = clk_get(NULL, "aclk_gps");
- if(gps_aclk) {
- clk_enable(gps_aclk);
- clk_put(gps_aclk);
- printk("%s \n", __FUNCTION__);
- }
- else
- printk("get gps aclk fail\n");
- return 0;
-}
-int rk_disable_hclk_gps(void)
-{
- struct clk *gps_aclk = NULL;
- gps_aclk = clk_get(NULL, "aclk_gps");
- if(gps_aclk) {
- //TO wait long enough until GPS ISR is finished.
- msleep(5);
- clk_disable(gps_aclk);
- clk_put(gps_aclk);
- printk("%s \n", __FUNCTION__);
- }
- else
- printk("get gps aclk fail\n");
- return 0;
-}
-struct rk_gps_data rk_gps_info = {
- .io_init = rk_gps_io_init,
- .power_up = rk_gps_power_up,
- .power_down = rk_gps_power_down,
- .reset = rk_gps_reset_set,
- .enable_hclk_gps = rk_enable_hclk_gps,
- .disable_hclk_gps = rk_disable_hclk_gps,
- .GpsSign = RK30_PIN1_PB3,
- .GpsMag = RK30_PIN1_PB2, //GPIO index
- .GpsClk = RK30_PIN1_PB4, //GPIO index
- .GpsVCCEn = RK30_PIN1_PB5, //GPIO index
- .GpsSpi_CSO = RK30_PIN1_PA4, //GPIO index
- .GpsSpiClk = RK30_PIN1_PA5, //GPIO index
- .GpsSpiMOSI = RK30_PIN1_PA7, //GPIO index
- .GpsIrq = IRQ_GPS,
- .GpsSpiEn = 0,
- .GpsAdcCh = 2,
- .u32GpsPhyAddr = RK30_GPS_PHYS,
- .u32GpsPhySize = RK30_GPS_SIZE,
-};
-
-struct platform_device rk_device_gps = {
- .name = "gps_hv5820b",
- .id = -1,
- .dev = {
- .platform_data = &rk_gps_info,
- }
- };
-#endif
-
-#if defined(CONFIG_MT5931_MT6622)
-static struct mt6622_platform_data mt6622_platdata = {
- .power_gpio = { // BT_REG_ON
- .io = RK30_PIN3_PD5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN0_PD7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .irq_gpio = {
- .io = RK30_PIN3_PD2,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- }
-};
-
-static struct platform_device device_mt6622 = {
- .name = "mt6622",
- .id = -1,
- .dev = {
- .platform_data = &mt6622_platdata,
- },
-};
-#endif
-
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_ANDROID_TIMED_GPIO
- &rk29_device_vibrator,
-#endif
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
- &rk29_device_gpio_leds,
-#endif
-#ifdef CONFIG_RK_IRDA
- &irda_device,
-#endif
-#if defined(CONFIG_WIFI_CONTROL_FUNC)||defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- &rk29sdk_wifi_device,
-#endif
-
-#if defined(CONFIG_MT6620)
- &mt3326_device_gps,
-#endif
-
-#ifdef CONFIG_RK29_SUPPORT_MODEM
- &rk30_device_modem,
-#endif
-#if defined(CONFIG_MU509)
- &rk29_device_mu509,
-#endif
-#if defined(CONFIG_MW100)
- &rk29_device_mw100,
-#endif
-#if defined(CONFIG_MT6229)
- &rk29_device_mt6229,
-#endif
-#ifdef CONFIG_BATTERY_RK30_ADC
- &rk30_device_adc_battery,
-#endif
-#ifdef CONFIG_RFKILL_RK
- &device_rfkill_rk,
-#endif
-#ifdef CONFIG_GPS_RK
- &rk_device_gps,
-#endif
-#if defined(CONFIG_ARCH_RK3188)
- &device_mali,
-#endif
-#ifdef CONFIG_MT5931_MT6622
- &device_mt6622,
-#endif
-#if defined (CONFIG_RK_HEADSET_DET) || defined (CONFIG_RK_HEADSET_IRQ_HOOK_ADC_DET)
- &rk_device_headset,
-#endif
-};
-
-static int rk_platform_add_display_devices(void)
-{
- struct platform_device *fb = NULL; //fb
- struct platform_device *lcdc0 = NULL; //lcdc0
- struct platform_device *lcdc1 = NULL; //lcdc1
- struct platform_device *bl = NULL; //backlight
-#ifdef CONFIG_FB_ROCKCHIP
- fb = &device_fb;
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
- lcdc0 = &device_lcdc0,
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
- lcdc1 = &device_lcdc1,
-#endif
-
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- bl = &rk29_device_backlight,
-#endif
- __rk_platform_add_display_devices(fb,lcdc0,lcdc1,bl);
-
- return 0;
-
-}
-
-// i2c
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1d,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_GS_LIS3DH)
- {
- .type = "gs_lis3dh",
- .addr = 0x19, //0x19(SA0-->VCC), 0x18(SA0-->GND)
- .flags = 0,
- .irq = LIS3DH_INT_PIN,
- .platform_data = &lis3dh_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8975_info,
- },
-#endif
-#if defined (CONFIG_GYRO_L3G4200D)
- {
- .type = "l3g4200d_gryo",
- .addr = 0x69,
- .flags = 0,
- .irq = L3G4200D_INT_PIN,
- .platform_data = &l3g4200d_info,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RT5631)
- {
- .type = "rt5631",
- .addr = 0x1a,
- .flags = 0,
- },
-#endif
-
-#if defined (CONFIG_SND_SOC_RT5640)
- {
- .type = "rt5640",
- .addr = 0x1c,
- .flags = 0,
- },
-#endif
-
-#ifdef CONFIG_MFD_RK610
- {
- .type = "rk610_ctl",
- .addr = 0x40,
- .flags = 0,
- .platform_data = &rk610_ctl_pdata,
- },
-#ifdef CONFIG_RK610_TVOUT
- {
- .type = "rk610_tvout",
- .addr = 0x42,
- .flags = 0,
- },
-#endif
-#ifdef CONFIG_HDMI_RK610
- {
- .type = "rk610_hdmi",
- .addr = 0x46,
- .flags = 0,
- .irq = INVALID_GPIO,
- },
-#endif
-#ifdef CONFIG_SND_SOC_RK610
- {//RK610_CODEC addr from 0x60 to 0x80 (0x60~0x80)
- .type = "rk610_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- .platform_data = &rk610_codec_pdata,
- },
-#endif
-#endif
-
-};
-#endif
-
-int __sramdata g_pmic_type = 0;
-#ifdef CONFIG_I2C1_RK30
-#ifdef CONFIG_MFD_WM831X_I2C
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info wm8326_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "dcdc3", //ddr
- .min_uv = 1150000,
- .max_uv = 1150000,
- .suspend_vol = 1150000,
- },
- #ifdef CONFIG_MACH_RK3066_SDK
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3000000,
- },
- #else
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3000000,
- .max_uv = 3000000,
- .suspend_vol = 2800000,
- },
- #endif
-};
-
-static struct pmu_info wm8326_ldo_info[] = {
- {
- .name = "ldo1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo2", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo3", //
- .min_uv = 1100000,
- .max_uv = 1100000,
- .suspend_vol = 1100000,
- },
- {
- .name = "ldo4", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 1000000,
- },
- {
- .name = "ldo5", //vcc25
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo6", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo7", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- .suspend_vol = 2800000,
- },
- {
- .name = "ldo8", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo9", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo10", //flash_io
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
-};
-
-#include "../mach-rk30/board-pmu-wm8326.c"
-#endif
-
-#ifdef CONFIG_MFD_TPS65910
-#define TPS65910_HOST_IRQ RK30_PIN0_PB3
-
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info tps65910_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1100000,
- .max_uv = 1100000,
- },
- {
- .name = "vdd2", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vio", //vcc_io
- .min_uv = 2500000,
- .max_uv = 2500000,
- },
-
-};
-static struct pmu_info tps65910_ldo_info[] = {
- {
- .name = "vpll", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "vdig2", //vdd_jetta
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vaux1", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "vaux2", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vaux33", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vmmc", //vcc30
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
- {
- .name = "vdac", //vcc18
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- };
-
-#include "../mach-rk30/board-pmu-tps65910.c"
-#endif
-
-#ifdef CONFIG_REGULATOR_ACT8846
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-#define PMU_VSEL RK30_PIN3_PD3
-static struct pmu_info act8846_dcdc_info[] = {
- {
- .name = "act_dcdc1", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- .suspend_vol = 1200000,
- },
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 1200000,
- #else
- .suspend_vol = 900000,
- #endif
-
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 1200000,
- #else
- .suspend_vol = 900000,
- #endif
-
- },
- {
- .name = "act_dcdc4", //vccio
- .min_uv = 3000000,
- .max_uv = 3000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 3000000,
- #else
- .suspend_vol = 2800000,
- #endif
-
- },
-
-};
-static struct pmu_info act8846_ldo_info[] = {
- {
- .name = "act_ldo1", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "act_ldo2", //vdd12
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "act_ldo3", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo4", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo5", //vcctp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo6", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo7", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo8", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- };
-
-#include "../mach-rk30/board-pmu-act8846.c"
-#endif
-
-#ifdef CONFIG_MFD_RK808
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-#define RK808_HOST_IRQ RK30_PIN0_PB3
-
-static struct pmu_info rk808_dcdc_info[] = {
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 900000,
- },
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 900000,
- },
- {
- .name = "rk_dcdc3", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- .suspend_vol = 1200000,
- },
- {
- .name = "rk_dcdc4", //vccio
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3000000,
- },
-
-};
-static struct pmu_info rk808_ldo_info[] = {
- {
- .name = "rk_ldo1", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "rk_ldo2", //vcctp
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
-
- },
- {
- .name = "rk_ldo3", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 1000000,
- },
- {
- .name = "rk_ldo4", //vcc18
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "rk_ldo5", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- .suspend_vol = 2800000,
- },
- {
- .name = "rk_ldo6", //vdd12
- .min_uv = 1200000,
- .max_uv = 1200000,
- .suspend_vol = 1200000,
- },
- {
- .name = "rk_ldo7", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "rk_ldo8", //vcca_33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- };
-
-#include "board-pmu-rk808.c"
-#endif
-
-#ifdef CONFIG_MFD_RICOH619
-#include <linux/mfd/ricoh619.h>
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-#define RICOH619_HOST_IRQ RK30_PIN0_PB3
-
-static struct pmu_info ricoh619_dcdc_info[] = {
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 900000,
- },
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 900000,
- },
-
- {
- .name = "ricoh_dc3", //vcc18
- .min_uv = 2000000,
- .max_uv = 2000000,
- .suspend_vol = 2000000,
- },
-
- {
- .name = "ricoh_dc4", //vccio
- .min_uv = 3100000,
- .max_uv = 3100000,
- .suspend_vol = 3000000,
- },
-
- {
- .name = "ricoh_dc5", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- .suspend_vol = 1200000,
- },
-
-};
-static struct pmu_info ricoh619_ldo_info[] = {
- {
- .name = "ricoh_ldo1", //vcc30
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
- {
- .name = "ricoh_ldo2", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "ricoh_ldo3", //vcctp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "ricoh_ldo4", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "ricoh_ldo5", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "ricoh_ldo6", //vdd12
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "ricoh_ldo7", //vccio_18
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "ricoh_ldo8", //vcca_25
- .min_uv = 2500000,
- .max_uv = 2500000,
- },
- {
- .name = "ricoh_ldo9", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "ricoh_ldo10", //vcca18
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
-
- };
-
-#include "../mach-rk30/board-pmu-ricoh619.c"
-#endif
-
-
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_MFD_WM831X_I2C)
- {
- .type = "wm8326",
- .addr = 0x34,
- .flags = 0,
- .irq = RK30_PIN0_PB3,
- .platform_data = &wm831x_platdata,
- },
-#endif
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-
-#if defined (CONFIG_REGULATOR_ACT8846)
- {
- .type = "act8846",
- .addr = 0x5a,
- .flags = 0,
- // .irq = ACT8846_HOST_IRQ,
- .platform_data=&act8846_data,
- },
-#endif
-#if defined (CONFIG_MFD_RK808)
- {
- .type = "rk808",
- .addr = 0x1b,
- .flags = 0,
- // .irq = ACT8846_HOST_IRQ,
- .platform_data=&rk808_data,
- },
-#endif
-
-#if defined (CONFIG_RTC_HYM8563)
- {
- .type = "rtc_hym8563",
- .addr = 0x51,
- .flags = 0,
- .irq = RK30_PIN1_PA4,
- },
-#if defined (CONFIG_CW2015_BATTERY)
- {
- .type = "cw201x",
- .addr = 0x62,
- .flags = 0,
- .platform_data = &cw_bat_platdata,
- },
-#endif
-#endif
-#if defined (CONFIG_MFD_RICOH619)
- {
- .type = "ricoh619",
- .addr = 0x32,
- .flags = 0,
- .irq = RICOH619_HOST_IRQ,
- .platform_data=&ricoh619_data,
- },
-#endif
-
-};
-#endif
-
-void __sramfunc board_pmu_suspend(void)
-{
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_suspend();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_suspend();
- #endif
- #if defined (CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- board_pmu_act8846_suspend();
- #endif
- #if defined (CONFIG_MFD_RK808)
- if(pmic_is_rk808())
- board_pmu_rk808_suspend();
- #endif
- #if defined (CONFIG_MFD_RICOH619)
- if(pmic_is_ricoh619())
- board_pmu_ricoh619_suspend();
- #endif
-}
-
-void __sramfunc board_pmu_resume(void)
-{
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_resume();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_resume();
- #endif
- #if defined (CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- board_pmu_act8846_resume();
- #endif
- #if defined (CONFIG_MFD_RK808)
- if(pmic_is_rk808())
- board_pmu_rk808_resume();
- #endif
- #if defined (CONFIG_MFD_RICOH619)
- if(pmic_is_ricoh619())
- board_pmu_ricoh619_resume();
- #endif
-}
-
- int __sramdata gpio3d6_iomux,gpio3d6_do,gpio3d6_dir,gpio3d6_en;
-
-#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
-
-void __sramfunc rk30_pwm_logic_suspend_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
-
-// int gpio0d7_iomux,gpio0d7_do,gpio0d7_dir,gpio0d7_en;
- sram_udelay(10000);
- gpio3d6_iomux = grf_readl(GRF_GPIO3D_IOMUX);
- gpio3d6_do = grf_readl(GRF_GPIO3H_DO);
- gpio3d6_dir = grf_readl(GRF_GPIO3H_DIR);
- gpio3d6_en = grf_readl(GRF_GPIO3H_EN);
-
- grf_writel((1<<28), GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DIR);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DO);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_EN);
-#endif
-}
-void __sramfunc rk30_pwm_logic_resume_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- grf_writel((1<<28)|gpio3d6_iomux, GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|gpio3d6_en, GRF_GPIO3H_EN);
- grf_writel((1<<30)|gpio3d6_dir, GRF_GPIO3H_DIR);
- grf_writel((1<<30)|gpio3d6_do, GRF_GPIO3H_DO);
- sram_udelay(10000);
-
-#endif
-
-}
-extern void pwm_suspend_voltage(void);
-extern void pwm_resume_voltage(void);
-void rk30_pwm_suspend_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_suspend_voltage();
-#endif
-}
-void rk30_pwm_resume_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_resume_voltage();
-#endif
-}
-
-
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-#if defined (CONFIG_TOUCHSCREEN_GT8XX)
- {
- .type = "Goodix-TS",
- .addr = 0x55,
- .flags = 0,
- .irq = RK30_PIN1_PB7,
- .platform_data = &goodix_info,
- },
-#endif
-#if defined (CONFIG_LS_CM3217)
- {
- .type = "lightsensor",
- .addr = 0x10,
- .flags = 0,
- .platform_data = &cm3217_info,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C4_RK30
-static struct i2c_board_info __initdata i2c4_info[] = {
-#if defined (CONFIG_MFD_RK616)
- {
- .type = "rk616",
- .addr = 0x50,
- .flags = 0,
- .platform_data = &rk616_pdata,
- },
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO// RK30_PIN2_PD6 //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO//RK30_PIN2_PD7 //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- //set iomux (gpio) here
- //rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME, GPIO2D_GPIO2D7);
- //rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME, GPIO2D_GPIO2D6);
-
- return 0;
-}
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C4_RK30
- i2c_register_board_info(4, i2c4_info, ARRAY_SIZE(i2c4_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(5, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-
-// ========== Begin of rk3168 top board keypad defination ============
-
-#include <plat/key.h>
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .adc_value = 1,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-#if 0
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK30_PIN0_PA4,
- .active_low = PRESS_LEV_LOW,
- .wakeup = 1,
- },
-#endif
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .adc_value = 200,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-#if 0
- {
- .desc = "menu",
- .code = EV_MENU,
- .adc_value = 133,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .adc_value = 550,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .adc_value = 333,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "camera",
- .code = KEY_CAMERA,
- .adc_value = 742,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-#endif
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = 1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
-// =========== End of rk3168 top board keypad defination =============
-
-
-#define POWER_ON_PIN RK30_PIN0_PA0 //power_hold
-static void rk30_pm_power_off(void)
-{
- printk(KERN_ERR "rk30_pm_power_off start...\n");
- #if defined(CONFIG_MFD_WM831X)
- if(pmic_is_wm8326()){
- wm831x_set_bits(Wm831x,WM831X_GPIO_LEVEL,0x0001,0x0000); //set sys_pwr 0
- wm831x_device_shutdown(Wm831x);//wm8326 shutdown
- }
- #endif
-
- #if defined(CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- {
- act8846_device_shutdown();
- }
- #endif
-
- #if defined(CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- {
- tps65910_device_shutdown();//tps65910 shutdown
- }
- #endif
-
- #if defined(CONFIG_MFD_RK808)
- if(pmic_is_rk808())
- {
- rk808_device_shutdown();//rk808 shutdown
- }
- #endif
- #if defined(CONFIG_MFD_RICOH619)
- if(pmic_is_ricoh619()){
- ricoh619_power_off(); //ricoh619 shutdown
- }
- #endif
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
- while (1);
-}
-
-static void __init machine_rk30_board_init(void)
-{
- //avs_init();
- gpio_request(POWER_ON_PIN, "poweronpin");
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
- pm_power_off = rk30_pm_power_off;
-
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
-
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- rk_platform_add_display_devices();
- board_usb_detect_init(RK30_PIN0_PA7);
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC)
- rk29sdk_wifi_bt_gpio_control_init();
-#elif defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- rk29sdk_wifi_combo_module_gpio_init();
-#endif
-
-#if defined(CONFIG_MT6620)
- clk_set_rate(clk_get_sys("rk_serial.0", "uart"), 48*1000000);
-#endif
-
-#if defined(CONFIG_MT5931_MT6622)
- clk_set_rate(clk_get_sys("rk_serial.0", "uart"), 24*1000000);
-#endif
-}
-#define HD_SCREEN_SIZE 1920UL*1200UL*4*3
-static void __init rk30_reserve(void)
-{
-#if defined(CONFIG_ARCH_RK3188)
- /*if lcd resolution great than or equal to 1920*1200,reserve the ump memory */
- if(!(get_fb_size() < ALIGN(HD_SCREEN_SIZE,SZ_1M)))
- {
- int ump_mem_phy_size=512UL*1024UL*1024UL;
- resource_mali[0].start = board_mem_reserve_add("ump buf", ump_mem_phy_size);
- resource_mali[0].end = resource_mali[0].start + ump_mem_phy_size -1;
- }
-#endif
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0 buf", get_fb_size());
- resource_fb[0].end = resource_fb[0].start + get_fb_size()- 1;
-#if 0
- resource_fb[1].start = board_mem_reserve_add("ipp buf", RK30_FB0_MEM_SIZE);
- resource_fb[1].end = resource_fb[1].start + RK30_FB0_MEM_SIZE - 1;
-#endif
-
-#if defined(CONFIG_FB_ROTATE) || !defined(CONFIG_THREE_FB_BUFFER)
- resource_fb[2].start = board_mem_reserve_add("fb2 buf",get_fb_size());
- resource_fb[2].end = resource_fb[2].start + get_fb_size() - 1;
-#endif
-#endif
-
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
-
-#ifdef CONFIG_GPS_RK
- //it must be more than 8MB
- rk_gps_info.u32MemoryPhyAddr = board_mem_reserve_add("gps", SZ_8M);
-#endif
- board_mem_reserved();
-}
-/******************************** arm dvfs frequency volt table **********************************/
-/**
- * dvfs_cpu_logic_table: table for arm and logic dvfs
- * @frequency : arm frequency
- * @cpu_volt : arm voltage depend on frequency
- */
-
-#if defined(CONFIG_ARCH_RK3188)
-//sdk
-static struct cpufreq_frequency_table dvfs_arm_table_volt_level0[] = {
- {.frequency = 312 * 1000, .index = 900 * 1000},
- {.frequency = 504 * 1000, .index = 900 * 1000},
- {.frequency = 816 * 1000, .index = 975 * 1000},
- {.frequency = 1008 * 1000,.index = 1025 * 1000},
- {.frequency = 1200 * 1000,.index = 1125 * 1000},
- {.frequency = 1296 * 1000,.index = 1175 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-//default
-static struct cpufreq_frequency_table dvfs_arm_table_volt_level1[] = {
- {.frequency = 312 * 1000, .index = 875 * 1000},
- {.frequency = 504 * 1000, .index = 925 * 1000},
- {.frequency = 816 * 1000, .index = 975 * 1000},
- {.frequency = 1008 * 1000, .index = 1075 * 1000},
- {.frequency = 1200 * 1000, .index = 1150 * 1000},
- {.frequency = 1416 * 1000, .index = 1250 * 1000},
- {.frequency = 1608 * 1000, .index = 1350 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-// cube 10'
-static struct cpufreq_frequency_table dvfs_arm_table_volt_level2[] = {
- {.frequency = 312 * 1000, .index = 900 * 1000},
- {.frequency = 504 * 1000, .index = 925 * 1000},
- {.frequency = 816 * 1000, .index = 1000 * 1000},
- {.frequency = 1008 * 1000, .index = 1075 * 1000},
- {.frequency = 1200 * 1000, .index = 1200 * 1000},
- {.frequency = 1416 * 1000, .index = 1250 * 1000},
- {.frequency = 1608 * 1000, .index = 1350 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-/******************************** gpu dvfs frequency volt table **********************************/
-//sdk
-static struct cpufreq_frequency_table dvfs_gpu_table_volt_level0[] = {
- {.frequency = 133 * 1000, .index = 975 * 1000},//the mininum rate is limited 133M for rk3188
- {.frequency = 200 * 1000, .index = 975 * 1000},
- {.frequency = 266 * 1000, .index = 1000 * 1000},
- {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1100 * 1000},
- {.frequency = 600 * 1000, .index = 1125 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-//cube 10'
-static struct cpufreq_frequency_table dvfs_gpu_table_volt_level1[] = {
- {.frequency = 133 * 1000, .index = 975 * 1000},//the mininum rate is limited 133M for rk3188
- {.frequency = 200 * 1000, .index = 1000 * 1000},
- {.frequency = 266 * 1000, .index = 1025 * 1000},
- {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1100 * 1000},
- {.frequency = 600 * 1000, .index = 1250 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-/******************************** ddr dvfs frequency volt table **********************************/
-static struct cpufreq_frequency_table dvfs_ddr_table_volt_level0[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 950 * 1000},
- {.frequency = 528 * 1000 + DDR_FREQ_VIDEO, .index = 1200 * 1000},
- {.frequency = 528 * 1000 + DDR_FREQ_DUALVIEW, .index = 1200 * 1000},
- {.frequency = 528 * 1000 + DDR_FREQ_NORMAL, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-//if you board is good for volt quality,select dvfs_arm_table_volt_level0
-#define dvfs_arm_table dvfs_arm_table_volt_level0
-#define dvfs_gpu_table dvfs_gpu_table_volt_level1
-#define dvfs_ddr_table dvfs_ddr_table_volt_level0
-
-#else
-//for RK3168 && RK3066B
-static struct cpufreq_frequency_table dvfs_arm_table[] = {
- {.frequency = 312 * 1000, .index = 950 * 1000},
- {.frequency = 504 * 1000, .index = 1000 * 1000},
- {.frequency = 816 * 1000, .index = 1050 * 1000},
- {.frequency = 1008 * 1000, .index = 1125 * 1000},
- {.frequency = 1200 * 1000, .index = 1200 * 1000},
- //{.frequency = 1416 * 1000, .index = 1250 * 1000},
- //{.frequency = 1608 * 1000, .index = 1300 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- {.frequency = 100 * 1000, .index = 1000 * 1000},
- {.frequency = 200 * 1000, .index = 1000 * 1000},
- {.frequency = 266 * 1000, .index = 1050 * 1000},
- //{.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1125 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 1000 * 1000},
- {.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = 1050 * 1000},
- {.frequency = 400 * 1000 + DDR_FREQ_NORMAL, .index = 1100 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-#endif
-/******************************** arm dvfs frequency volt table end **********************************/
-//#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
-//static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
-//static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
-
-void __init board_clock_init(void)
-{
- rk30_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
- //dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "cpu"), dvfs_arm_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
-}
-
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk30_fixup,
- .reserve = &rk30_reserve,
- .map_io = rk30_map_io,
- .init_irq = rk30_init_irq,
- .timer = &rk30_timer,
- .init_machine = machine_rk30_board_init,
-MACHINE_END
+++ /dev/null
-/*
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <mach/dvfs.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <linux/rk_fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-#include <linux/mfd/tps65910.h>
-#include <linux/regulator/act8846.h>
-#include <linux/mfd/rk808.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-
-#ifdef CONFIG_CW2015_BATTERY
-#include <linux/power/cw2015_battery.h>
-#endif
-#if defined(CONFIG_MFD_RK610)
-#include <linux/mfd/rk610_core.h>
-#endif
-
-#if defined(CONFIG_MFD_RK616)
-#include <linux/mfd/rk616.h>
-#endif
-
-
-#if defined(CONFIG_RK_HDMI)
- #include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
-#endif
-
-#if defined(CONFIG_SPIM_RK29)
-#include "../../../drivers/spi/rk29_spim.h"
-#endif
-#if defined(CONFIG_GPS_RK)
-#include "../../../drivers/misc/gps/rk_gps/rk_gps.h"
-#endif
-#if defined(CONFIG_MU509)
-#include <linux/mu509.h>
-#endif
-#if defined(CONFIG_MW100)
-#include <linux/mw100.h>
-#endif
-#if defined(CONFIG_MT6229)
-#include <linux/mt6229.h>
-#endif
-#if defined(CONFIG_ANDROID_TIMED_GPIO)
-#include "../../../drivers/staging/android/timed_gpio.h"
-#endif
-
-#if defined(CONFIG_MT6620)
-#include <linux/gps.h>
-#endif
-#include "../mach-rk30/board-rk3168-tb-camera.c"
-
-//#define RK31XX_MAINBOARD_V1
-
-
-#if defined(CONFIG_TOUCHSCREEN_GT8XX)
-#define TOUCH_RESET_PIN RK30_PIN0_PB6
-#define TOUCH_PWR_PIN RK30_PIN0_PC5 // need to fly line by hardware engineer
-
-/* Android Parameter */
-static int ap_mdm = 0;
-module_param(ap_mdm, int, 0644);
-static int ap_has_alsa = 0;
-module_param(ap_has_alsa, int, 0644);
-static int ap_data_only = 2;
-module_param(ap_data_only, int, 0644);
-static int ap_has_earphone = 0;
-module_param(ap_has_earphone, int, 0644);
-
-
-static int goodix_init_platform_hw(void)
-{
- int ret;
-
- if (TOUCH_PWR_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_PWR_PIN, "goodix power pin");
- if (ret != 0) {
- gpio_free(TOUCH_PWR_PIN);
- printk("goodix power error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_PWR_PIN, 0);
- gpio_set_value(TOUCH_PWR_PIN, GPIO_LOW);
- msleep(100);
- }
-
- if (TOUCH_RESET_PIN != INVALID_GPIO) {
- ret = gpio_request(TOUCH_RESET_PIN, "goodix reset pin");
- if (ret != 0) {
- gpio_free(TOUCH_RESET_PIN);
- printk("goodix gpio_request error\n");
- return -EIO;
- }
- gpio_direction_output(TOUCH_RESET_PIN, 1);
- msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_LOW);
- //msleep(100);
- //gpio_set_value(TOUCH_RESET_PIN, GPIO_HIGH);
- //msleep(500);
- }
- return 0;
-}
-
-struct goodix_platform_data goodix_info = {
- .model = 8105,
- .irq_pin = RK30_PIN1_PB7,
- .rest_pin = TOUCH_RESET_PIN,
- .init_platform_hw = goodix_init_platform_hw,
-};
-#endif
-
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#ifdef CONFIG_BACKLIGHT_RK29_BL
-#define PWM_ID 3
-#define PWM_MODE PWM3
-#define PWM_EFFECT_VALUE 1
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-#define BL_EN_PIN RK30_PIN0_PA2
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
-
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
- ret = gpio_request(BL_EN_PIN, "bl_en");
- if (ret == 0) {
- gpio_direction_output(BL_EN_PIN, BL_EN_VALUE);
- }
-#endif
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0, pwm_gpio;
-#ifdef LCD_DISP_ON_PIN
- gpio_free(BL_EN_PIN);
-#endif
- pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
- gpio_request(pwm_gpio, "bl_pwm");
- gpio_direction_output(pwm_gpio, GPIO_LOW);
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret, pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
-
- ret = gpio_request(pwm_gpio, "bl_pwm");
- if (ret) {
- printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
- return ret;
- }
- gpio_direction_output(pwm_gpio, GPIO_LOW);
-#ifdef LCD_DISP_ON_PIN
- gpio_direction_output(BL_EN_PIN, !BL_EN_VALUE);
-#endif
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- int pwm_gpio = iomux_mode_to_gpio(PWM_MODE);
-
- gpio_free(pwm_gpio);
- iomux_set(PWM_MODE);
-#ifdef LCD_DISP_ON_PIN
- msleep(30);
- gpio_direction_output(BL_EN_PIN, BL_EN_VALUE);
-#endif
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .min_brightness=20,
- .max_brightness=255,
- .brightness_mode = BRIGHTNESS_MODE_CONIC,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-#endif
-
-#ifdef CONFIG_RK29_SUPPORT_MODEM
-
-#define RK30_MODEM_POWER RK30_PIN0_PC6
-#define RK30_MODEM_POWER_IOMUX iomux_set(GPIO0_C6)
-
-static int rk30_modem_io_init(void)
-{
- printk("%s\n", __FUNCTION__);
- RK30_MODEM_POWER_IOMUX;
-
- return 0;
-}
-
-static struct rk29_io_t rk30_modem_io = {
- .io_addr = RK30_MODEM_POWER,
- .enable = GPIO_HIGH,
- .disable = GPIO_LOW,
- .io_init = rk30_modem_io_init,
-};
-
-static struct platform_device rk30_device_modem = {
- .name = "rk30_modem",
- .id = -1,
- .dev = {
- .platform_data = &rk30_modem_io,
- }
-};
-#endif
-#if defined(CONFIG_MU509)
-static int mu509_io_init(void)
-{
-
- iomux_set(GPIO2_D5);
- iomux_set(GPIO0_C6);
- iomux_set(GPIO2_D4);
- iomux_set(GPIO0_C4);
- iomux_set(GPIO0_C5);
- return 0;
-}
-
-static int mu509_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mu509_data rk29_mu509_info = {
- .io_init = mu509_io_init,
- .io_deinit = mu509_io_deinit,
- .modem_power_en = RK30_PIN2_PD5,
- .bp_power = RK30_PIN0_PC6,
- .bp_reset = RK30_PIN2_PD4,
- .ap_wakeup_bp = RK30_PIN0_PC4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
-};
-struct platform_device rk29_device_mu509 = {
- .name = "mu509",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mu509_info,
- }
- };
-#endif
-#if defined(CONFIG_MW100)
-static int mw100_io_init(void)
-{
- iomux_set(GPIO2_D5);
- iomux_set(GPIO0_C6);
- iomux_set(GPIO2_D4);
- iomux_set(GPIO0_C4);
- iomux_set(GPIO0_C5);
- return 0;
-}
-
-static int mw100_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mw100_data rk29_mw100_info = {
- .io_init = mw100_io_init,
- .io_deinit = mw100_io_deinit,
- .modem_power_en = RK30_PIN2_PD5,
- .bp_power = RK30_PIN0_PC6,
- .bp_reset = RK30_PIN2_PD4,
- .ap_wakeup_bp = RK30_PIN0_PC4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
-};
-struct platform_device rk29_device_mw100 = {
- .name = "mw100",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mw100_info,
- }
- };
-#endif
-#if defined(CONFIG_MT6229)
-static int mt6229_io_init(void)
-{
- iomux_set(GPIO2_D5);
- iomux_set(GPIO0_C6);
- iomux_set(GPIO2_D4);
- iomux_set(GPIO0_C4);
- iomux_set(GPIO0_C5);
- return 0;
-}
-
-static int mt6229_io_deinit(void)
-{
-
- return 0;
-}
-
-struct rk29_mt6229_data rk29_mt6229_info = {
- .io_init = mt6229_io_init,
- .io_deinit = mt6229_io_deinit,
- .modem_power_en = RK30_PIN2_PD5,
- .bp_power = RK30_PIN0_PC6,
- .bp_reset = RK30_PIN2_PD4,
- .ap_wakeup_bp = RK30_PIN0_PC4,
- .bp_wakeup_ap = RK30_PIN0_PC5,
-};
-struct platform_device rk29_device_mt6229 = {
- .name = "mt6229",
- .id = -1,
- .dev = {
- .platform_data = &rk29_mt6229_info,
- }
- };
-#endif
-
-/*MMA8452 gsensor*/
-#if defined (CONFIG_GS_MMA8452)
-#define MMA8452_INT_PIN RK30_PIN0_PB7
-
-static int mma8452_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data mma8452_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = mma8452_init_platform_hw,
- .orientation = {-1, 0, 0, 0, -1, 0, 0, 0, 1},
-};
-#endif
-#if defined (CONFIG_GS_LIS3DH)
-#define LIS3DH_INT_PIN RK30_PIN0_PB7
-
-static int lis3dh_init_platform_hw(void)
-{
-
- return 0;
-}
-
-static struct sensor_platform_data lis3dh_info = {
- .type = SENSOR_TYPE_ACCEL,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .init_platform_hw = lis3dh_init_platform_hw,
- .orientation = {-1, 0, 0, 0, -1, 0, 0, 0, 1},
-};
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
-static struct sensor_platform_data akm8975_info =
-{
- .type = SENSOR_TYPE_COMPASS,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .m_layout =
- {
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
-
- {
- {1, 0, 0},
- {0, 1, 0},
- {0, 0, 1},
- },
- }
-};
-
-#endif
-
-#if defined(CONFIG_GYRO_L3G4200D)
-
-#include <linux/l3g4200d.h>
-#define L3G4200D_INT_PIN RK30_PIN0_PB4
-
-static int l3g4200d_init_platform_hw(void)
-{
- return 0;
-}
-
-static struct sensor_platform_data l3g4200d_info = {
- .type = SENSOR_TYPE_GYROSCOPE,
- .irq_enable = 1,
- .poll_delay_ms = 30,
- .orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
- .init_platform_hw = l3g4200d_init_platform_hw,
- .x_min = 40,//x_min,y_min,z_min = (0-100) according to hardware
- .y_min = 40,
- .z_min = 20,
-};
-
-#endif
-
-#ifdef CONFIG_LS_CM3217
-static struct sensor_platform_data cm3217_info = {
- .type = SENSOR_TYPE_LIGHT,
- .irq_enable = 0,
- .poll_delay_ms = 500,
-};
-
-#endif
-
-#ifdef CONFIG_FB_ROCKCHIP
-
-#define LCD_CS_PIN INVALID_GPIO
-#define LCD_CS_VALUE GPIO_HIGH
-
-#define LCD_EN_PIN RK30_PIN0_PB0
-#define LCD_EN_VALUE GPIO_HIGH
-
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
-
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_CS_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_CS_PIN);
- printk(KERN_ERR "request lcd cs pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_CS_PIN, LCD_CS_VALUE);
- }
- }
-
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- ret = gpio_request(LCD_EN_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_EN_PIN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_EN_PIN, LCD_EN_VALUE);
- }
- }
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, !LCD_CS_VALUE);
- }
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, !LCD_EN_VALUE);
- }
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- if(LCD_CS_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE);
- }
- if(LCD_EN_PIN !=INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
- }
- return 0;
-}
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
-struct rk29fb_info lcdc0_screen_info = {
- #if defined(CONFIG_RK_HDMI)
- .prop = EXTEND, //extend display device
- .lcd_info = NULL,
- .set_screen_info = hdmi_init_lcdc,
- #endif
-};
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
-struct rk29fb_info lcdc1_screen_info = {
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-
-};
-#endif
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-#if defined(CONFIG_ARCH_RK3188)
-static struct resource resource_mali[] = {
- [0] = {
- .name = "ump buf",
- .start = 0,
- .end = 0,
- .flags = IORESOURCE_MEM,
- },
-
-};
-
-static struct platform_device device_mali= {
- .name = "mali400_ump",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_mali),
- .resource = resource_mali,
-};
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
-static struct resource resource_lcdc0[] = {
- [0] = {
- .name = "lcdc0 reg",
- .start = RK30_LCDC0_PHYS,
- .end = RK30_LCDC0_PHYS + RK30_LCDC0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc0 irq",
- .start = IRQ_LCDC0,
- .end = IRQ_LCDC0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc0 = {
- .name = "rk30-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc0),
- .resource = resource_lcdc0,
- .dev = {
- .platform_data = &lcdc0_screen_info,
- },
-};
-#endif
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
-static struct resource resource_lcdc1[] = {
- [0] = {
- .name = "lcdc1 reg",
- .start = RK30_LCDC1_PHYS,
- .end = RK30_LCDC1_PHYS + RK30_LCDC1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc1 irq",
- .start = IRQ_LCDC1,
- .end = IRQ_LCDC1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc1 = {
- .name = "rk30-lcdc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resource_lcdc1),
- .resource = resource_lcdc1,
- .dev = {
- .platform_data = &lcdc1_screen_info,
- },
-};
-#endif
-
-#if defined(CONFIG_MFD_RK610)
-#define RK610_RST_PIN RK30_PIN2_PC5
-static int rk610_power_on_init(void)
-{
- int ret;
- if(RK610_RST_PIN != INVALID_GPIO)
- {
- ret = gpio_request(RK610_RST_PIN, "rk610 reset");
- if (ret)
- {
- printk(KERN_ERR "rk610_control_probe request gpio fail\n");
- }
- else
- {
- gpio_direction_output(RK610_RST_PIN, GPIO_HIGH);
- msleep(100);
- gpio_direction_output(RK610_RST_PIN, GPIO_LOW);
- msleep(100);
- gpio_set_value(RK610_RST_PIN, GPIO_HIGH);
- }
- }
-
- return 0;
-
-}
-
-
-static struct rk610_ctl_platform_data rk610_ctl_pdata = {
- .rk610_power_on_init = rk610_power_on_init,
-};
-#endif
-
-#if defined(CONFIG_MFD_RK616)
-#define RK616_RST_PIN RK30_PIN3_PB2
-#define RK616_PWREN_PIN RK30_PIN0_PC5
-#define RK616_SCL_RATE (80*1000) //i2c scl rate
-static int rk616_power_on_init(void)
-{
- int ret;
-
- if(RK616_PWREN_PIN != INVALID_GPIO)
- {
- ret = gpio_request(RK616_PWREN_PIN, "rk616 pwren");
- if (ret)
- {
- printk(KERN_ERR "rk616 pwren gpio request fail\n");
- }
- else
- {
- gpio_direction_output(RK616_PWREN_PIN,GPIO_HIGH);
- }
- }
-
- if(RK616_RST_PIN != INVALID_GPIO)
- {
- ret = gpio_request(RK616_RST_PIN, "rk616 reset");
- if (ret)
- {
- printk(KERN_ERR "rk616 reset gpio request fail\n");
- }
- else
- {
- gpio_direction_output(RK616_RST_PIN, GPIO_HIGH);
- msleep(100);
- gpio_direction_output(RK616_RST_PIN, GPIO_LOW);
- msleep(100);
- gpio_set_value(RK616_RST_PIN, GPIO_HIGH);
- }
- }
-
- return 0;
-
-}
-
-
-static struct rk616_platform_data rk616_pdata = {
- .power_init = rk616_power_on_init,
- .scl_rate = RK616_SCL_RATE,
- .lcd0_func = INPUT, //port lcd0 as input
- .lcd1_func = INPUT, //port lcd1 as input
- .lvds_ch_nr = 0, //the number of used lvds channel
- .hdmi_irq = RK30_PIN2_PD4,
- .spk_ctl_gpio = RK30_PIN0_PD5,
- .hp_ctl_gpio = RK30_PIN0_PD5,
-};
-#endif
-
-#ifdef CONFIG_SND_SOC_RK610
-static int rk610_codec_io_init(void)
-{
-//if need iomux.
-//Must not gpio_request
- return 0;
-}
-
-static struct rk610_codec_platform_data rk610_codec_pdata = {
- .spk_ctl_io = RK30_PIN2_PD7,
- .io_init = rk610_codec_io_init,
-};
-#endif
-
-#ifdef CONFIG_ANDROID_TIMED_GPIO
-static struct timed_gpio timed_gpios[] = {
- {
- .name = "vibrator",
- .gpio = INVALID_GPIO,
- .max_timeout = 1000,
- .active_low = 0,
- .adjust_time =20, //adjust for diff product
- },
-};
-
-static struct timed_gpio_platform_data rk29_vibrator_info = {
- .num_gpios = 1,
- .gpios = timed_gpios,
-};
-
-static struct platform_device rk29_device_vibrator = {
- .name = "timed-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_vibrator_info,
- },
-
-};
-#endif
-
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
-static struct gpio_led rk29_leds[] = {
- {
- .name = "button-backlight",
- .gpio = INVALID_GPIO,
- .default_trigger = "timer",
- .active_low = 0,
- .retain_state_suspended = 0,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- },
-};
-
-static struct gpio_led_platform_data rk29_leds_pdata = {
- .leds = rk29_leds,
- .num_leds = ARRAY_SIZE(rk29_leds),
-};
-
-static struct platform_device rk29_device_gpio_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rk29_leds_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_RK_IRDA
-#define IRDA_IRQ_PIN INVALID_GPIO //RK30_PIN0_PA3
-
-static int irda_iomux_init(void)
-{
- int ret = 0;
-
- //irda irq pin
- ret = gpio_request(IRDA_IRQ_PIN, NULL);
- if (ret != 0) {
- gpio_free(IRDA_IRQ_PIN);
- printk(">>>>>> IRDA_IRQ_PIN gpio_request err \n ");
- }
- gpio_pull_updown(IRDA_IRQ_PIN, PullDisable);
- gpio_direction_input(IRDA_IRQ_PIN);
-
- return 0;
-}
-
-static int irda_iomux_deinit(void)
-{
- gpio_free(IRDA_IRQ_PIN);
- return 0;
-}
-
-static struct irda_info rk29_irda_info = {
- .intr_pin = IRDA_IRQ_PIN,
- .iomux_init = irda_iomux_init,
- .iomux_deinit = irda_iomux_deinit,
- //.irda_pwr_ctl = bu92747guw_power_ctl,
-};
-
-static struct platform_device irda_device = {
-#ifdef CONFIG_RK_IRDA_NET
- .name = "rk_irda",
-#else
- .name = "bu92747_irda",
-#endif
- .id = -1,
- .dev = {
- .platform_data = &rk29_irda_info,
- }
-};
-#endif
-
-#ifdef CONFIG_ION
-#define ION_RESERVE_SIZE (80 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-#endif
-
-/**************************************************************************************************
- * SDMMC devices, include the module of SD,MMC,and sdio.noted by xbw at 2012-03-05
-**************************************************************************************************/
-#ifdef CONFIG_SDMMC_RK29
-#include "../mach-rk30/board-rk3168-tb-sdmmc-conifg.c"
-#include "../plat-rk/rk-sdmmc-ops.c"
-#include "../plat-rk/rk-sdmmc-wifi.c"
-#endif //endif ---#ifdef CONFIG_SDMMC_RK29
-
-#ifdef CONFIG_SDMMC0_RK29
-static int rk29_sdmmc0_cfg_gpio(void)
-{
-#ifdef CONFIG_SDMMC_RK29_OLD
- iomux_set(MMC0_CMD);
- iomux_set(MMC0_CLKOUT);
- iomux_set(MMC0_D0);
- iomux_set(MMC0_D1);
- iomux_set(MMC0_D2);
- iomux_set(MMC0_D3);
-
- iomux_set_gpio_mode(iomux_mode_to_gpio(MMC0_DETN));
-
- gpio_request(RK30_PIN3_PA7, "sdmmc-power");
- gpio_direction_output(RK30_PIN3_PA7, GPIO_LOW);
-
-#else
- rk29_sdmmc_set_iomux(0, 0xFFFF);
-
- #if defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set_gpio_mode(iomux_gpio_to_mode(RK29SDK_SD_CARD_DETECT_N));
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO);
- #endif
- #else
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(MMC0_DETN);
- #else
- rk30_mux_api_set(RK29SDK_SD_CARD_DETECT_PIN_NAME, RK29SDK_SD_CARD_DETECT_IOMUX_FMUX);
- #endif
- #endif
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
- gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-#define CONFIG_SDMMC0_USE_DMA
-struct rk29_sdmmc_platform_data default_sdmmc0_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .io_init = rk29_sdmmc0_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sd_mmc",
-#ifdef CONFIG_SDMMC0_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) && defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- .status = rk29sdk_wifi_mmc0_status,
- .register_status_notify = rk29sdk_wifi_mmc0_status_register,
-#endif
-
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .power_en = RK29SDK_SD_CARD_PWR_EN,
- .power_en_level = RK29SDK_SD_CARD_PWR_EN_LEVEL,
-#else
- .power_en = INVALID_GPIO,
- .power_en_level = GPIO_LOW,
-#endif
- .enable_sd_wakeup = 0,
-
-#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
- .write_prt = SDMMC0_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC0_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- .det_pin_info = {
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N, //INVALID_GPIO,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
- #endif
- },
-
-};
-#endif // CONFIG_SDMMC0_RK29
-
-#ifdef CONFIG_SDMMC1_RK29
-#define CONFIG_SDMMC1_USE_DMA
-static int rk29_sdmmc1_cfg_gpio(void)
-{
-#if defined(CONFIG_SDMMC_RK29_OLD)
- iomux_set(MMC1_CMD);
- iomux_set(MMC1_CLKOUT);
- iomux_set(MMC1_D0);
- iomux_set(MMC1_D1);
- iomux_set(MMC1_D2);
- iomux_set(MMC1_D3);
-#else
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
- gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
-#endif
-
-#endif
-
- return 0;
-}
-
-struct rk29_sdmmc_platform_data default_sdmmc1_data = {
- .host_ocr_avail =
- (MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
- MMC_VDD_33_34),
-
-#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#else
- .host_caps =
- (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-#endif
-
- .io_init = rk29_sdmmc1_cfg_gpio,
-
-#if !defined(CONFIG_SDMMC_RK29_OLD)
- .set_iomux = rk29_sdmmc_set_iomux,
-#endif
-
- .dma_name = "sdio",
-#ifdef CONFIG_SDMMC1_USE_DMA
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC) || defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- .status = rk29sdk_wifi_status,
- .register_status_notify = rk29sdk_wifi_status_register,
-#endif
-
-#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
- .write_prt = SDMMC1_WRITE_PROTECT_PIN,
- .write_prt_enalbe_level = SDMMC1_WRITE_PROTECT_ENABLE_VALUE;
-#else
- .write_prt = INVALID_GPIO,
-#endif
-
- #if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
- .sdio_INT_gpio = RK29SDK_WIFI_SDIO_CARD_INT,
- #endif
-
- .det_pin_info = {
-#if defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
- #if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- #else
- .io = INVALID_GPIO,
- #endif
-
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
- #else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-
- .enable_sd_wakeup = 0,
-};
-#endif //endif--#ifdef CONFIG_SDMMC1_RK29
-
-/**************************************************************************************************
- * the end of setting for SDMMC devices
-**************************************************************************************************/
-
-#ifdef CONFIG_BATTERY_RK30_ADC
-static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
- .dc_det_pin = RK30_PIN0_PB2,
- .batt_low_pin = RK30_PIN0_PB1,
- .charge_set_pin = INVALID_GPIO,
- .charge_ok_pin = RK30_PIN0_PA6,
- .dc_det_level = GPIO_LOW,
- .charge_ok_level = GPIO_HIGH,
-};
-
-static struct platform_device rk30_device_adc_battery = {
- .name = "rk30-battery",
- .id = -1,
- .dev = {
- .platform_data = &rk30_adc_battery_platdata,
- },
-};
-#endif
-#ifdef CONFIG_CW2015_BATTERY
-/*
- note the follow array must set depend on the battery that you use
- you must send the battery to cellwise-semi the contact information:
- name: chen gan; tel:13416876079; E-mail: ben.chen@cellwise-semi.com
- */
-static u8 config_info[SIZE_BATINFO] = {
- 0x15, 0x42, 0x60, 0x59, 0x52,
- 0x58, 0x4D, 0x48, 0x48, 0x44,
- 0x44, 0x46, 0x49, 0x48, 0x32,
- 0x24, 0x20, 0x17, 0x13, 0x0F,
- 0x19, 0x3E, 0x51, 0x45, 0x08,
- 0x76, 0x0B, 0x85, 0x0E, 0x1C,
- 0x2E, 0x3E, 0x4D, 0x52, 0x52,
- 0x57, 0x3D, 0x1B, 0x6A, 0x2D,
- 0x25, 0x43, 0x52, 0x87, 0x8F,
- 0x91, 0x94, 0x52, 0x82, 0x8C,
- 0x92, 0x96, 0xFF, 0x7B, 0xBB,
- 0xCB, 0x2F, 0x7D, 0x72, 0xA5,
- 0xB5, 0xC1, 0x46, 0xAE
-};
-
-static struct cw_bat_platform_data cw_bat_platdata = {
- .dc_det_pin = RK30_PIN0_PB2,
- .bat_low_pin = RK30_PIN0_PB1,
- .chg_ok_pin = RK30_PIN0_PA6,
- .dc_det_level = GPIO_LOW,
- .bat_low_level = GPIO_LOW,
- .chg_ok_level = GPIO_HIGH,
-
- .cw_bat_config_info = config_info,
-
-};
-
-#endif
-#ifdef CONFIG_RK30_PWM_REGULATOR
-static int pwm_voltage_map[] = {
- 800000,825000,850000, 875000,900000, 925000 ,950000, 975000,1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000,1375000
-};
-static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
- {
- .supply = "vdd_cpu",
- }
-};
-
-struct regulator_init_data pwm_regulator_init_dcdc[1] =
-{
- {
- .constraints = {
- .name = "PWM_DCDC1",
- .min_uV = 600000,
- .max_uV = 1800000, //0.6-1.8V
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
- .consumer_supplies = pwm_dcdc1_consumers,
- },
-};
-
-static struct pwm_platform_data pwm_regulator_info[1] = {
- {
- .pwm_id = 1,
- .pwm_gpio = RK30_PIN3_PD4,
- .pwm_iomux_pwm = PWM1,
- .pwm_iomux_gpio = GPIO3_D4,
- .pwm_voltage = 1100000,
- .suspend_voltage = 1000000,
- .min_uV = 800000,
- .max_uV = 1375000,
- .coefficient = 575, //57.5%
- .pwm_voltage_map = pwm_voltage_map,
- .init_data = &pwm_regulator_init_dcdc[0],
- },
-};
-
-struct platform_device pwm_regulator_device[1] = {
- {
- .name = "pwm-voltage-regulator",
- .id = 0,
- .dev = {
- .platform_data = &pwm_regulator_info[0],
- }
- },
-};
-#endif
-
-#ifdef CONFIG_RK29_VMAC
-#define PHY_PWR_EN_GPIO RK30_PIN1_PD6
-#include "board-rk30-sdk-vmac.c"
-#endif
-
-#ifdef CONFIG_RFKILL_RK
-// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
-static struct rfkill_rk_platform_data rfkill_rk_platdata = {
- .type = RFKILL_TYPE_BLUETOOTH,
-
- .poweron_gpio = { // BT_REG_ON
- .io = INVALID_GPIO, //RK30_PIN3_PC7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_poweron",
- .fgpio = GPIO3_C7,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN3_PC7, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_reset",
- .fgpio = GPIO3_C7,
- },
- },
-
- .wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
- .io = RK30_PIN3_PC6, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "bt_wake",
- .fgpio = GPIO3_C6,
- },
- },
-
- .wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
- .gpio = {
- .io = RK30_PIN0_PA5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
- .iomux = {
- .name = NULL,
- },
- },
- },
-
- .rts_gpio = { // UART_RTS, enable or disable BT's data coming
- .io = RK30_PIN1_PA3, // set io to INVALID_GPIO for disable it
- .enable = GPIO_LOW,
- .iomux = {
- .name = "bt_rts",
- .fgpio = GPIO1_A3,
- .fmux = UART0_RTSN,
- },
- },
-};
-
-static struct platform_device device_rfkill_rk = {
- .name = "rfkill_rk",
- .id = -1,
- .dev = {
- .platform_data = &rfkill_rk_platdata,
- },
-};
-#endif
-
-#if defined(CONFIG_GPS_RK)
-int rk_gps_io_init(void)
-{
- printk("%s \n", __FUNCTION__);
-
- gpio_request(RK30_PIN1_PB5, NULL);
- gpio_direction_output(RK30_PIN1_PB5, GPIO_LOW);
-
- iomux_set(GPS_RFCLK);//GPS_CLK
- iomux_set(GPS_MAG);//GPS_MAG
- iomux_set(GPS_SIG);//GPS_SIGN
-
- gpio_request(RK30_PIN1_PA6, NULL);
- gpio_direction_output(RK30_PIN1_PA6, GPIO_LOW);
-
- gpio_request(RK30_PIN1_PA5, NULL);
- gpio_direction_output(RK30_PIN1_PA5, GPIO_LOW);
-
- gpio_request(RK30_PIN1_PA7, NULL);
- gpio_direction_output(RK30_PIN1_PA7, GPIO_LOW);
- return 0;
-}
-int rk_gps_power_up(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_power_down(void)
-{
- printk("%s \n", __FUNCTION__);
-
- return 0;
-}
-
-int rk_gps_reset_set(int level)
-{
- return 0;
-}
-int rk_enable_hclk_gps(void)
-{
- struct clk *gps_aclk = NULL;
- gps_aclk = clk_get(NULL, "aclk_gps");
- if(gps_aclk) {
- clk_enable(gps_aclk);
- clk_put(gps_aclk);
- printk("%s \n", __FUNCTION__);
- }
- else
- printk("get gps aclk fail\n");
- return 0;
-}
-int rk_disable_hclk_gps(void)
-{
- struct clk *gps_aclk = NULL;
- gps_aclk = clk_get(NULL, "aclk_gps");
- if(gps_aclk) {
- //TO wait long enough until GPS ISR is finished.
- msleep(5);
- clk_disable(gps_aclk);
- clk_put(gps_aclk);
- printk("%s \n", __FUNCTION__);
- }
- else
- printk("get gps aclk fail\n");
- return 0;
-}
-struct rk_gps_data rk_gps_info = {
- .io_init = rk_gps_io_init,
- .power_up = rk_gps_power_up,
- .power_down = rk_gps_power_down,
- .reset = rk_gps_reset_set,
- .enable_hclk_gps = rk_enable_hclk_gps,
- .disable_hclk_gps = rk_disable_hclk_gps,
- .GpsSign = RK30_PIN1_PB3,
- .GpsMag = RK30_PIN1_PB2, //GPIO index
- .GpsClk = RK30_PIN1_PB4, //GPIO index
- .GpsVCCEn = RK30_PIN1_PB5, //GPIO index
- .GpsSpi_CSO = RK30_PIN1_PA4, //GPIO index
- .GpsSpiClk = RK30_PIN1_PA5, //GPIO index
- .GpsSpiMOSI = RK30_PIN1_PA7, //GPIO index
- .GpsIrq = IRQ_GPS,
- .GpsSpiEn = 0,
- .GpsAdcCh = 2,
- .u32GpsPhyAddr = RK30_GPS_PHYS,
- .u32GpsPhySize = RK30_GPS_SIZE,
-};
-
-struct platform_device rk_device_gps = {
- .name = "gps_hv5820b",
- .id = -1,
- .dev = {
- .platform_data = &rk_gps_info,
- }
- };
-#endif
-
-#if defined(CONFIG_MT5931_MT6622)
-static struct mt6622_platform_data mt6622_platdata = {
- .power_gpio = { // BT_REG_ON
- .io = RK30_PIN3_PD5, // set io to INVALID_GPIO for disable it
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .reset_gpio = { // BT_RST
- .io = RK30_PIN0_PD7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- },
-
- .irq_gpio = {
- .io = RK30_PIN3_PD2,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = NULL,
- },
- }
-};
-
-static struct platform_device device_mt6622 = {
- .name = "mt6622",
- .id = -1,
- .dev = {
- .platform_data = &mt6622_platdata,
- },
-};
-#endif
-
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_ION
- &device_ion,
-#endif
-#ifdef CONFIG_ANDROID_TIMED_GPIO
- &rk29_device_vibrator,
-#endif
-#ifdef CONFIG_LEDS_GPIO_PLATFORM
- &rk29_device_gpio_leds,
-#endif
-#ifdef CONFIG_RK_IRDA
- &irda_device,
-#endif
-#if defined(CONFIG_WIFI_CONTROL_FUNC)||defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- &rk29sdk_wifi_device,
-#endif
-
-#if defined(CONFIG_MT6620)
- &mt3326_device_gps,
-#endif
-
-#ifdef CONFIG_RK29_SUPPORT_MODEM
- &rk30_device_modem,
-#endif
-#if defined(CONFIG_MU509)
- &rk29_device_mu509,
-#endif
-#if defined(CONFIG_MW100)
- &rk29_device_mw100,
-#endif
-#if defined(CONFIG_MT6229)
- &rk29_device_mt6229,
-#endif
-#ifdef CONFIG_BATTERY_RK30_ADC
- &rk30_device_adc_battery,
-#endif
-#ifdef CONFIG_RFKILL_RK
- &device_rfkill_rk,
-#endif
-#ifdef CONFIG_GPS_RK
- &rk_device_gps,
-#endif
-#if defined(CONFIG_ARCH_RK3188)
- &device_mali,
-#endif
-#ifdef CONFIG_MT5931_MT6622
- &device_mt6622,
-#endif
-};
-
-static int rk_platform_add_display_devices(void)
-{
- struct platform_device *fb = NULL; //fb
- struct platform_device *lcdc0 = NULL; //lcdc0
- struct platform_device *lcdc1 = NULL; //lcdc1
- struct platform_device *bl = NULL; //backlight
-#ifdef CONFIG_FB_ROCKCHIP
- fb = &device_fb;
-#endif
-
-#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
- lcdc0 = &device_lcdc0,
-#endif
-
-#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
- lcdc1 = &device_lcdc1,
-#endif
-
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- bl = &rk29_device_backlight,
-#endif
- __rk_platform_add_display_devices(fb,lcdc0,lcdc1,bl);
-
- return 0;
-
-}
-
-// i2c
-#ifdef CONFIG_I2C0_RK30
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_GS_MMA8452)
- {
- .type = "gs_mma8452",
- .addr = 0x1d,
- .flags = 0,
- .irq = MMA8452_INT_PIN,
- .platform_data = &mma8452_info,
- },
-#endif
-#if defined (CONFIG_GS_LIS3DH)
- {
- .type = "gs_lis3dh",
- .addr = 0x19, //0x19(SA0-->VCC), 0x18(SA0-->GND)
- .flags = 0,
- .irq = LIS3DH_INT_PIN,
- .platform_data = &lis3dh_info,
- },
-#endif
-#if defined (CONFIG_COMPASS_AK8975)
- {
- .type = "ak8975",
- .addr = 0x0d,
- .flags = 0,
- .irq = RK30_PIN3_PD7,
- .platform_data = &akm8975_info,
- },
-#endif
-#if defined (CONFIG_GYRO_L3G4200D)
- {
- .type = "l3g4200d_gryo",
- .addr = 0x69,
- .flags = 0,
- .irq = L3G4200D_INT_PIN,
- .platform_data = &l3g4200d_info,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-#if defined (CONFIG_SND_SOC_RT5631)
- {
- .type = "rt5631",
- .addr = 0x1a,
- .flags = 0,
- },
-#endif
-
-#if defined (CONFIG_SND_SOC_RT5640)
- {
- .type = "rt5640",
- .addr = 0x1c,
- .flags = 0,
- },
-#endif
-
-#ifdef CONFIG_MFD_RK610
- {
- .type = "rk610_ctl",
- .addr = 0x40,
- .flags = 0,
- .platform_data = &rk610_ctl_pdata,
- },
-#ifdef CONFIG_RK610_TVOUT
- {
- .type = "rk610_tvout",
- .addr = 0x42,
- .flags = 0,
- },
-#endif
-#ifdef CONFIG_HDMI_RK610
- {
- .type = "rk610_hdmi",
- .addr = 0x46,
- .flags = 0,
- .irq = INVALID_GPIO,
- },
-#endif
-#ifdef CONFIG_SND_SOC_RK610
- {//RK610_CODEC addr from 0x60 to 0x80 (0x60~0x80)
- .type = "rk610_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- .platform_data = &rk610_codec_pdata,
- },
-#endif
-#endif
-
-};
-#endif
-
-int __sramdata g_pmic_type = 0;
-#ifdef CONFIG_I2C1_RK30
-#ifdef CONFIG_MFD_WM831X_I2C
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info wm8326_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 950000,
- },
- {
- .name = "dcdc3", //ddr
- .min_uv = 1150000,
- .max_uv = 1150000,
- .suspend_vol = 1150000,
- },
- #ifdef CONFIG_MACH_RK3066_SDK
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3000000,
- },
- #else
- {
- .name = "dcdc4", //vcc_io
- .min_uv = 3000000,
- .max_uv = 3000000,
- .suspend_vol = 2800000,
- },
- #endif
-};
-
-static struct pmu_info wm8326_ldo_info[] = {
- {
- .name = "ldo1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo2", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo3", //
- .min_uv = 1100000,
- .max_uv = 1100000,
- .suspend_vol = 1100000,
- },
- {
- .name = "ldo4", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 1000000,
- },
- {
- .name = "ldo5", //vcc25
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "ldo6", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo7", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- .suspend_vol = 2800000,
- },
- {
- .name = "ldo8", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo9", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "ldo10", //flash_io
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
-};
-
-#include "../mach-rk30/board-pmu-wm8326.c"
-#endif
-
-#ifdef CONFIG_MFD_TPS65910
-#define TPS65910_HOST_IRQ RK30_PIN0_PB3
-
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-
-static struct pmu_info tps65910_dcdc_info[] = {
- {
- .name = "vdd_core", //logic
- .min_uv = 1100000,
- .max_uv = 1100000,
- },
- {
- .name = "vdd2", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vio", //vcc_io
- .min_uv = 2500000,
- .max_uv = 2500000,
- },
-
-};
-static struct pmu_info tps65910_ldo_info[] = {
- {
- .name = "vpll", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "vdig1", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "vdig2", //vdd_jetta
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "vaux1", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- {
- .name = "vaux2", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vaux33", //vcc_tp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "vmmc", //vcc30
- .min_uv = 3000000,
- .max_uv = 3000000,
- },
- {
- .name = "vdac", //vcc18
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- };
-
-#include "../mach-rk30/board-pmu-tps65910.c"
-#endif
-
-#ifdef CONFIG_REGULATOR_ACT8846
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-#define PMU_VSEL RK30_PIN3_PD3
-static struct pmu_info act8846_dcdc_info[] = {
- {
- .name = "act_dcdc1", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- .suspend_vol = 1200000,
- },
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 1200000,
- #else
- .suspend_vol = 900000,
- #endif
-
- },
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 1200000,
- #else
- .suspend_vol = 900000,
- #endif
-
- },
- {
- .name = "act_dcdc4", //vccio
- .min_uv = 3000000,
- .max_uv = 3000000,
- #ifdef CONFIG_ACT8846_SUPPORT_RESET
- .suspend_vol = 3000000,
- #else
- .suspend_vol = 2800000,
- #endif
-
- },
-
-};
-static struct pmu_info act8846_ldo_info[] = {
- {
- .name = "act_ldo1", //vdd11
- .min_uv = 1000000,
- .max_uv = 1000000,
- },
- {
- .name = "act_ldo2", //vdd12
- .min_uv = 1200000,
- .max_uv = 1200000,
- },
- {
- .name = "act_ldo3", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo4", //vcca33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo5", //vcctp
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo6", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- },
- {
- .name = "act_ldo7", //vccio_wl
- .min_uv = 1800000,
- .max_uv = 1800000,
- },
- {
- .name = "act_ldo8", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- },
- };
-
-#include "../mach-rk30/board-pmu-act8846.c"
-#endif
-
-#ifdef CONFIG_MFD_RK808
-#define PMU_POWER_SLEEP RK30_PIN0_PA1
-#define RK808_HOST_IRQ RK30_PIN0_PB3
-
-static struct pmu_info rk808_dcdc_info[] = {
- {
- .name = "vdd_cpu", //arm
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 900000,
- },
- {
- .name = "vdd_core", //logic
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 900000,
- },
- {
- .name = "rk_dcdc3", //ddr
- .min_uv = 1200000,
- .max_uv = 1200000,
- .suspend_vol = 1200000,
- },
- {
- .name = "rk_dcdc4", //vccio
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3000000,
- },
-
-};
-static struct pmu_info rk808_ldo_info[] = {
- {
- .name = "rk_ldo1", //vcc33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- {
- .name = "rk_ldo2", //vcctp
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
-
- },
- {
- .name = "rk_ldo3", //vdd10
- .min_uv = 1000000,
- .max_uv = 1000000,
- .suspend_vol = 1000000,
- },
- {
- .name = "rk_ldo4", //vcc18
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "rk_ldo5", //vcc28_cif
- .min_uv = 2800000,
- .max_uv = 2800000,
- .suspend_vol = 2800000,
- },
- {
- .name = "rk_ldo6", //vdd12
- .min_uv = 1200000,
- .max_uv = 1200000,
- .suspend_vol = 1200000,
- },
- {
- .name = "rk_ldo7", //vcc18_cif
- .min_uv = 1800000,
- .max_uv = 1800000,
- .suspend_vol = 1800000,
- },
- {
- .name = "rk_ldo8", //vcca_33
- .min_uv = 3300000,
- .max_uv = 3300000,
- .suspend_vol = 3300000,
- },
- };
-
-#include "board-pmu-rk808.c"
-#endif
-
-
-static struct i2c_board_info __initdata i2c1_info[] = {
-#if defined (CONFIG_MFD_WM831X_I2C)
- {
- .type = "wm8326",
- .addr = 0x34,
- .flags = 0,
- .irq = RK30_PIN0_PB3,
- .platform_data = &wm831x_platdata,
- },
-#endif
-#if defined (CONFIG_MFD_TPS65910)
- {
- .type = "tps65910",
- .addr = TPS65910_I2C_ID0,
- .flags = 0,
- .irq = TPS65910_HOST_IRQ,
- .platform_data = &tps65910_data,
- },
-#endif
-
-#if defined (CONFIG_REGULATOR_ACT8846)
- {
- .type = "act8846",
- .addr = 0x5a,
- .flags = 0,
- // .irq = ACT8846_HOST_IRQ,
- .platform_data=&act8846_data,
- },
-#endif
-#if defined (CONFIG_MFD_RK808)
- {
- .type = "rk808",
- .addr = 0x1b,
- .flags = 0,
- // .irq = ACT8846_HOST_IRQ,
- .platform_data=&rk808_data,
- },
-#endif
-
-#if defined (CONFIG_RTC_HYM8563)
- {
- .type = "rtc_hym8563",
- .addr = 0x51,
- .flags = 0,
- .irq = RK30_PIN1_PA4,
- },
-#if defined (CONFIG_CW2015_BATTERY)
- {
- .type = "cw201x",
- .addr = 0x62,
- .flags = 0,
- .platform_data = &cw_bat_platdata,
- },
-#endif
-#endif
-
-};
-#endif
-
-void __sramfunc board_pmu_suspend(void)
-{
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_suspend();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_suspend();
- #endif
- #if defined (CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- board_pmu_act8846_suspend();
- #endif
- #if defined (CONFIG_MFD_RK808)
- if(pmic_is_rk808())
- board_pmu_rk808_suspend();
- #endif
-
-}
-
-void __sramfunc board_pmu_resume(void)
-{
- #if defined (CONFIG_MFD_WM831X_I2C)
- if(pmic_is_wm8326())
- board_pmu_wm8326_resume();
- #endif
- #if defined (CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- board_pmu_tps65910_resume();
- #endif
- #if defined (CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- board_pmu_act8846_resume();
- #endif
- #if defined (CONFIG_MFD_RK808)
- if(pmic_is_rk808())
- board_pmu_rk808_resume();
- #endif
-
-}
-
- int __sramdata gpio3d6_iomux,gpio3d6_do,gpio3d6_dir,gpio3d6_en;
-
-#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
-
-void __sramfunc rk30_pwm_logic_suspend_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
-
-// int gpio0d7_iomux,gpio0d7_do,gpio0d7_dir,gpio0d7_en;
- sram_udelay(10000);
- gpio3d6_iomux = grf_readl(GRF_GPIO3D_IOMUX);
- gpio3d6_do = grf_readl(GRF_GPIO3H_DO);
- gpio3d6_dir = grf_readl(GRF_GPIO3H_DIR);
- gpio3d6_en = grf_readl(GRF_GPIO3H_EN);
-
- grf_writel((1<<28), GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DIR);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_DO);
- grf_writel((1<<30)|(1<<14), GRF_GPIO3H_EN);
-#endif
-}
-void __sramfunc rk30_pwm_logic_resume_voltage(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- grf_writel((1<<28)|gpio3d6_iomux, GRF_GPIO3D_IOMUX);
- grf_writel((1<<30)|gpio3d6_en, GRF_GPIO3H_EN);
- grf_writel((1<<30)|gpio3d6_dir, GRF_GPIO3H_DIR);
- grf_writel((1<<30)|gpio3d6_do, GRF_GPIO3H_DO);
- sram_udelay(10000);
-
-#endif
-
-}
-extern void pwm_suspend_voltage(void);
-extern void pwm_resume_voltage(void);
-void rk30_pwm_suspend_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_suspend_voltage();
-#endif
-}
-void rk30_pwm_resume_voltage_set(void)
-{
-#ifdef CONFIG_RK30_PWM_REGULATOR
- pwm_resume_voltage();
-#endif
-}
-
-
-#ifdef CONFIG_I2C2_RK30
-static struct i2c_board_info __initdata i2c2_info[] = {
-#if defined (CONFIG_TOUCHSCREEN_GT8XX)
- {
- .type = "Goodix-TS",
- .addr = 0x55,
- .flags = 0,
- .irq = RK30_PIN1_PB7,
- .platform_data = &goodix_info,
- },
-#endif
-#if defined (CONFIG_LS_CM3217)
- {
- .type = "lightsensor",
- .addr = 0x10,
- .flags = 0,
- .platform_data = &cm3217_info,
- },
-#endif
-};
-#endif
-
-#ifdef CONFIG_I2C3_RK30
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-#endif
-
-#ifdef CONFIG_I2C4_RK30
-static struct i2c_board_info __initdata i2c4_info[] = {
-#if defined (CONFIG_MFD_RK616)
- {
- .type = "rk616",
- .addr = 0x50,
- .flags = 0,
- .platform_data = &rk616_pdata,
- },
-#endif
-
-};
-#endif
-
-#ifdef CONFIG_I2C_GPIO_RK30
-#define I2C_SDA_PIN INVALID_GPIO// RK30_PIN2_PD6 //set sda_pin here
-#define I2C_SCL_PIN INVALID_GPIO//RK30_PIN2_PD7 //set scl_pin here
-static int rk30_i2c_io_init(void)
-{
- //set iomux (gpio) here
- //rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME, GPIO2D_GPIO2D7);
- //rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME, GPIO2D_GPIO2D6);
-
- return 0;
-}
-struct i2c_gpio_platform_data default_i2c_gpio_data = {
- .sda_pin = I2C_SDA_PIN,
- .scl_pin = I2C_SCL_PIN,
- .udelay = 5, // clk = 500/udelay = 100Khz
- .timeout = 100,//msecs_to_jiffies(100),
- .bus_num = 5,
- .io_init = rk30_i2c_io_init,
-};
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-#endif
-
-static void __init rk30_i2c_register_board_info(void)
-{
-#ifdef CONFIG_I2C0_RK30
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
-#endif
-#ifdef CONFIG_I2C1_RK30
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
-#endif
-#ifdef CONFIG_I2C2_RK30
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
-#endif
-#ifdef CONFIG_I2C3_RK30
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-#endif
-#ifdef CONFIG_I2C4_RK30
- i2c_register_board_info(4, i2c4_info, ARRAY_SIZE(i2c4_info));
-#endif
-#ifdef CONFIG_I2C_GPIO_RK30
- i2c_register_board_info(5, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
-#endif
-}
-//end of i2c
-
-// ========== Begin of rk3168 top board keypad defination ============
-
-#include <plat/key.h>
-
-static struct rk29_keys_button key_button[] = {
-#ifdef RK31XX_MAINBOARD_V1
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .adc_value = 744,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK30_PIN0_PA4,
- .active_low = PRESS_LEV_LOW,
- .wakeup = 1,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .adc_value = 558,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "menu",
- .code = EV_MENU,
- .adc_value = 1,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .adc_value = 354,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .adc_value = 169,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-#else
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .adc_value = 900,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "play",
- .code = KEY_POWER,
- .gpio = RK30_PIN0_PA4,
- .active_low = PRESS_LEV_LOW,
- .wakeup = 1,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .adc_value = 1,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "menu",
- .code = EV_MENU,
- .adc_value = 133,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .adc_value = 550,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .adc_value = 333,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "camera",
- .code = KEY_CAMERA,
- .adc_value = 742,
- .gpio = INVALID_GPIO,
- .active_low = PRESS_LEV_LOW,
- },
-#endif
-};
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = 1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
-// =========== End of rk3168 top board keypad defination =============
-
-
-#define POWER_ON_PIN RK30_PIN0_PA0 //power_hold
-static void rk30_pm_power_off(void)
-{
- printk(KERN_ERR "rk30_pm_power_off start...\n");
- #if defined(CONFIG_MFD_WM831X)
- if(pmic_is_wm8326()){
- wm831x_set_bits(Wm831x,WM831X_GPIO_LEVEL,0x0001,0x0000); //set sys_pwr 0
- wm831x_device_shutdown(Wm831x);//wm8326 shutdown
- }
- #endif
-
- #if defined(CONFIG_REGULATOR_ACT8846)
- if(pmic_is_act8846())
- {
- act8846_device_shutdown();
- }
- #endif
-
- #if defined(CONFIG_MFD_TPS65910)
- if(pmic_is_tps65910())
- {
- tps65910_device_shutdown();//tps65910 shutdown
- }
- #endif
-
- #if defined(CONFIG_MFD_RK808)
- if(pmic_is_rk808())
- {
- rk808_device_shutdown();//rk808 shutdown
- }
- #endif
-
- gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
- while (1);
-}
-
-static void __init machine_rk30_board_init(void)
-{
- //avs_init();
- gpio_request(POWER_ON_PIN, "poweronpin");
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
- pm_power_off = rk30_pm_power_off;
-
- gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
-
-
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
- rk_platform_add_display_devices();
- board_usb_detect_init(RK30_PIN0_PA7);
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC)
- rk29sdk_wifi_bt_gpio_control_init();
-#elif defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
- rk29sdk_wifi_combo_module_gpio_init();
-#endif
-
-#if defined(CONFIG_MT6620)
- clk_set_rate(clk_get_sys("rk_serial.0", "uart"), 48*1000000);
-#endif
-
-#if defined(CONFIG_MT5931_MT6622)
- clk_set_rate(clk_get_sys("rk_serial.0", "uart"), 24*1000000);
-#endif
-}
-#define HD_SCREEN_SIZE 1920UL*1200UL*4*3
-static void __init rk30_reserve(void)
-{
-#if defined(CONFIG_ARCH_RK3188)
- /*if lcd resolution great than or equal to 1920*1200,reserve the ump memory */
- if(!(get_fb_size() < ALIGN(HD_SCREEN_SIZE,SZ_1M)))
- {
- int ump_mem_phy_size=512UL*1024UL*1024UL;
- resource_mali[0].start = board_mem_reserve_add("ump buf", ump_mem_phy_size);
- resource_mali[0].end = resource_mali[0].start + ump_mem_phy_size -1;
- }
-#endif
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-#ifdef CONFIG_FB_ROCKCHIP
- resource_fb[0].start = board_mem_reserve_add("fb0 buf", get_fb_size());
- resource_fb[0].end = resource_fb[0].start + get_fb_size()- 1;
-#if 0
- resource_fb[1].start = board_mem_reserve_add("ipp buf", RK30_FB0_MEM_SIZE);
- resource_fb[1].end = resource_fb[1].start + RK30_FB0_MEM_SIZE - 1;
-#endif
-
-#if defined(CONFIG_FB_ROTATE) || !defined(CONFIG_THREE_FB_BUFFER)
- resource_fb[2].start = board_mem_reserve_add("fb2 buf",get_fb_size());
- resource_fb[2].end = resource_fb[2].start + get_fb_size() - 1;
-#endif
-#endif
-
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
-
-#ifdef CONFIG_GPS_RK
- //it must be more than 8MB
- rk_gps_info.u32MemoryPhyAddr = board_mem_reserve_add("gps", SZ_8M);
-#endif
- board_mem_reserved();
-}
-/******************************** arm dvfs frequency volt table **********************************/
-/**
- * dvfs_cpu_logic_table: table for arm and logic dvfs
- * @frequency : arm frequency
- * @cpu_volt : arm voltage depend on frequency
- */
-
-#if defined(CONFIG_ARCH_RK3188)
-//sdk
-static struct cpufreq_frequency_table dvfs_arm_table_volt_level0[] = {
- {.frequency = 312 * 1000, .index = 850 * 1000},
- {.frequency = 504 * 1000, .index = 900 * 1000},
- {.frequency = 816 * 1000, .index = 950 * 1000},
- {.frequency = 1008 * 1000, .index = 1025 * 1000},
- {.frequency = 1200 * 1000, .index = 1100 * 1000},
- {.frequency = 1296 * 1000, .index = 1125 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-//default
-static struct cpufreq_frequency_table dvfs_arm_table_volt_level1[] = {
- {.frequency = 312 * 1000, .index = 875 * 1000},
- {.frequency = 504 * 1000, .index = 925 * 1000},
- {.frequency = 816 * 1000, .index = 975 * 1000},
- {.frequency = 1008 * 1000, .index = 1075 * 1000},
- {.frequency = 1200 * 1000, .index = 1150 * 1000},
- {.frequency = 1416 * 1000, .index = 1250 * 1000},
- {.frequency = 1608 * 1000, .index = 1350 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-// cube 10'
-static struct cpufreq_frequency_table dvfs_arm_table_volt_level2[] = {
- {.frequency = 312 * 1000, .index = 900 * 1000},
- {.frequency = 504 * 1000, .index = 925 * 1000},
- {.frequency = 816 * 1000, .index = 1000 * 1000},
- {.frequency = 1008 * 1000, .index = 1075 * 1000},
- {.frequency = 1200 * 1000, .index = 1200 * 1000},
- {.frequency = 1416 * 1000, .index = 1250 * 1000},
- {.frequency = 1608 * 1000, .index = 1350 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-/******************************** gpu dvfs frequency volt table **********************************/
-//sdk
-static struct cpufreq_frequency_table dvfs_gpu_table_volt_level0[] = {
- {.frequency = 133 * 1000, .index = 975 * 1000},//the mininum rate is limited 133M for rk3188
- {.frequency = 200 * 1000, .index = 975 * 1000},
- {.frequency = 266 * 1000, .index = 1000 * 1000},
- {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1100 * 1000},
- {.frequency = 600 * 1000, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-//cube 10'
-static struct cpufreq_frequency_table dvfs_gpu_table_volt_level1[] = {
- {.frequency = 133 * 1000, .index = 975 * 1000},//the mininum rate is limited 133M for rk3188
- {.frequency = 200 * 1000, .index = 1000 * 1000},
- {.frequency = 266 * 1000, .index = 1025 * 1000},
- {.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1100 * 1000},
- {.frequency = 600 * 1000, .index = 1250 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-/******************************** ddr dvfs frequency volt table **********************************/
-static struct cpufreq_frequency_table dvfs_ddr_table_volt_level0[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 950 * 1000},
- {.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = 1000 * 1000},
- {.frequency = 396 * 1000 + DDR_FREQ_NORMAL, .index = 1100 * 1000},
- //{.frequency = 528 * 1000 + DDR_FREQ_NORMAL, .index = 1200 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-//if you board is good for volt quality,select dvfs_arm_table_volt_level0
-#define dvfs_arm_table dvfs_arm_table_volt_level0
-#define dvfs_gpu_table dvfs_gpu_table_volt_level1
-#define dvfs_ddr_table dvfs_ddr_table_volt_level0
-
-#else
-//for RK3168 && RK3066B
-static struct cpufreq_frequency_table dvfs_arm_table[] = {
- {.frequency = 312 * 1000, .index = 950 * 1000},
- {.frequency = 504 * 1000, .index = 1000 * 1000},
- {.frequency = 816 * 1000, .index = 1050 * 1000},
- {.frequency = 1008 * 1000, .index = 1125 * 1000},
- {.frequency = 1200 * 1000, .index = 1200 * 1000},
- //{.frequency = 1416 * 1000, .index = 1250 * 1000},
- //{.frequency = 1608 * 1000, .index = 1300 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_gpu_table[] = {
- {.frequency = 100 * 1000, .index = 1000 * 1000},
- {.frequency = 200 * 1000, .index = 1000 * 1000},
- {.frequency = 266 * 1000, .index = 1050 * 1000},
- //{.frequency = 300 * 1000, .index = 1050 * 1000},
- {.frequency = 400 * 1000, .index = 1125 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 1000 * 1000},
- {.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = 1050 * 1000},
- {.frequency = 400 * 1000 + DDR_FREQ_NORMAL, .index = 1100 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-#endif
-/******************************** arm dvfs frequency volt table end **********************************/
-//#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
-//static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
-//static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
-
-void __init board_clock_init(void)
-{
- rk30_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
- //dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "cpu"), dvfs_arm_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
- dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
-}
-
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = rk30_fixup,
- .reserve = &rk30_reserve,
- .map_io = rk30_map_io,
- .init_irq = rk30_init_irq,
- .timer = &rk30_timer,
- .init_machine = machine_rk30_board_init,
-MACHINE_END
+++ /dev/null
-/* linux/arch/arm/mach-rk30/clock_data.c
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/hardirq.h>
-#include <plat/efuse.h>
-#include <mach/cru.h>
-#include <mach/iomux.h>
-#include <mach/clock.h>
-#include <mach/pmu.h>
-#include <mach/dvfs.h>
-#include <mach/ddr.h>
-#include <mach/cpu.h>
-
-#define MHZ (1000UL * 1000UL)
-#define KHZ (1000UL)
-#define CLK_LOOPS_JIFFY_REF 11996091ULL
-#define CLK_LOOPS_RATE_REF (1200UL) //Mhz
-#define CLK_LOOPS_RECALC(new_rate) div_u64(CLK_LOOPS_JIFFY_REF*(new_rate),CLK_LOOPS_RATE_REF*MHZ)
-void rk30_clk_dump_regs(void);
-static int flag_uboot_display = 0;
-//flags bit
-//has extern 27mhz
-#define CLK_FLG_EXT_27MHZ (1<<0)
-//max i2s rate
-#define CLK_FLG_MAX_I2S_12288KHZ (1<<1)
-#define CLK_FLG_MAX_I2S_22579_2KHZ (1<<2)
-#define CLK_FLG_MAX_I2S_24576KHZ (1<<3)
-#define CLK_FLG_MAX_I2S_49152KHZ (1<<4)
-//uart 1m\3m
-#define CLK_FLG_UART_1_3M (1<<5)
-
-#define ARCH_RK31
-
-struct apll_clk_set {
- unsigned long rate;
- u32 pllcon0;
- u32 pllcon1;
- u32 pllcon2; //nb=bwadj+1;0:11;nb=nf/2
- u32 rst_dly;//us
- u32 clksel0;
- u32 clksel1;
- unsigned long lpj;
-};
-struct pll_clk_set {
- unsigned long rate;
- u32 pllcon0;
- u32 pllcon1;
- u32 pllcon2; //nb=bwadj+1;0:11;nb=nf/2
- unsigned long rst_dly;//us
-};
-
-#define SET_PLL_DATA(_pll_id,_table) \
-{\
- .id=(_pll_id),\
- .table=(_table),\
-}
-
-
-#define _PLL_SET_CLKS(_mhz, nr, nf, no) \
-{ \
- .rate = (_mhz) * KHZ, \
- .pllcon0 = PLL_CLKR_SET(nr)|PLL_CLKOD_SET(no), \
- .pllcon1 = PLL_CLKF_SET(nf),\
- .pllcon2 = PLL_CLK_BWADJ_SET(nf >> 1),\
- .rst_dly=((nr*500)/24+1),\
-}
-
-
-#define _APLL_SET_LPJ(_mhz) \
- .lpj= (CLK_LOOPS_JIFFY_REF * _mhz)/CLK_LOOPS_RATE_REF
-
-
-#define _APLL_SET_CLKS(_mhz, nr, nf, no, _periph_div, _axi_core_div,\
- _axi_div,_ahb_div, _apb_div,_ahb2apb) \
-{ \
- .rate = _mhz * MHZ, \
- .pllcon0 = PLL_CLKR_SET(nr) | PLL_CLKOD_SET(no), \
- .pllcon1 = PLL_CLKF_SET(nf),\
- .pllcon2 = PLL_CLK_BWADJ_SET(nf >> 1),\
- .clksel0 = CORE_PERIPH_W_MSK | CORE_PERIPH_##_periph_div,\
- .clksel1 = CORE_ACLK_W_MSK | CORE_ACLK_##_axi_core_div,\
- _APLL_SET_LPJ(_mhz),\
- .rst_dly=((nr*500)/24+1),\
-}
-
-#define CRU_DIV_SET(mask,shift,max) \
- .div_mask=(mask),\
-.div_shift=(shift),\
-.div_max=(max)
-
-
-#define CRU_SRC_SET(mask,shift ) \
- .src_mask=(mask),\
-.src_shift=(shift)
-
-#define CRU_PARENTS_SET(parents_array) \
- .parents=(parents_array),\
-.parents_num=ARRAY_SIZE((parents_array))
-
-#define CRU_GATE_MODE_SET(_func,_IDX) \
- .mode=_func,\
-.gate_idx=(_IDX)
-
-struct clk_src_sel {
- struct clk *parent;
- u8 value;//crt bit
- u8 flag;
- //selgate
-};
-
-#define GATE_CLK(NAME,PARENT,ID) \
- static struct clk clk_##NAME = { \
- .name = #NAME, \
- .parent = &PARENT, \
- .mode = gate_mode, \
- .gate_idx = CLK_GATE_##ID, \
- }
-#ifdef RK30_CLK_OFFBOARD_TEST
-u32 TEST_GRF_REG[0x240];
-u32 TEST_CRU_REG[0x240];
-#define cru_readl(offset) (TEST_CRU_REG[offset/4])
-
-u32 cru_writel_is_pr(u32 offset)
-{
- return (offset == 0x4000);
-}
-void cru_writel(u32 v, u32 offset)
-{
-
- u32 mask_v = v >> 16;
- TEST_CRU_REG[offset/4] &= (~mask_v);
-
- v &= (mask_v);
-
- TEST_CRU_REG[offset/4] |= v;
- TEST_CRU_REG[offset/4] &= 0x0000ffff;
-
- if(cru_writel_is_pr(offset)) {
- CLKDATA_DBG("cru w offset=%d,set=%x,reg=%x\n", offset, v, TEST_CRU_REG[offset/4]);
-
- }
-
-}
-void cru_writel_i2s(u32 v, u32 offset)
-{
- TEST_CRU_REG[offset/4] = v;
-}
-#define cru_writel_frac(v,offset) cru_writel_i2s((v),(offset))
-
-#define regfile_readl(offset) (0xffffffff)
-//#define pmu_readl(offset) readl(RK30_GRF_BASE + offset)
-void rk30_clkdev_add(struct clk_lookup *cl);
-#else
-#define regfile_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
-#define regfile_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
-#define cru_readl(offset) readl_relaxed(RK30_CRU_BASE + offset)
-#define cru_writel(v, offset) do { writel_relaxed(v, RK30_CRU_BASE + offset); dsb(); } while (0)
-
-#define cru_writel_frac(v,offset) cru_writel((v),(offset))
-#endif
-
-//#define DEBUG
-#ifdef DEBUG
-#define CLKDATA_DBG(fmt, args...) printk(KERN_DEBUG "CLKDATA_DBG:\t"fmt, ##args)
-#define CLKDATA_LOG(fmt, args...) printk(KERN_INFO "CLKDATA_LOG:\t"fmt, ##args)
-//#define CLKDATA_DBG(fmt, args...) printk("CLKDATA_DBG:\t"fmt, ##args)
-//#define CLKDATA_LOG(fmt, args...) printk("CLKDATA_LOG:\t"fmt, ##args)
-#else
-#define CLKDATA_DBG(fmt, args...) do {} while(0)
-#define CLKDATA_LOG(fmt, args...) do {} while(0)
-#endif
-#define CLKDATA_ERR(fmt, args...) printk(KERN_ERR "CLKDATA_ERR:\t"fmt, ##args)
-#define CLKDATA_WARNING(fmt, args...) printk("CLKDATA_WANING:\t"fmt, ##args)
-
-
-#define get_cru_bits(con,mask,shift)\
- ((cru_readl((con)) >> (shift)) & (mask))
-
-#define set_cru_bits_w_msk(val,mask,shift,con)\
- cru_writel(((mask)<<(shift+16))|((val)<<(shift)),(con))
-
-
-#define PLLS_IN_NORM(pll_id) (((cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id))==(PLL_MODE_NORM(pll_id)&PLL_MODE_MSK(pll_id)))\
- &&!(cru_readl(PLL_CONS(pll_id,3))&PLL_BYPASS))
-
-
-static u32 rk30_clock_flags = 0;
-static struct clk codec_pll_clk;
-static struct clk general_pll_clk;
-static struct clk arm_pll_clk;
-static unsigned long lpj_gpll;
-static unsigned int __initdata armclk = 504 * MHZ;
-
-
-/************************clk recalc div rate*********************************/
-
-//for free div
-static unsigned long clksel_recalc_div(struct clk *clk)
-{
- u32 div = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
-
- unsigned long rate = clk->parent->rate / div;
- pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, div);
- return rate;
-}
-
-//for div 1 2 4 2^n
-static unsigned long clksel_recalc_shift(struct clk *clk)
-{
- u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift);
- unsigned long rate = clk->parent->rate >> shift;
- pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
- return rate;
-}
-
-
-static unsigned long clksel_recalc_shift_2(struct clk *clk)
-{
- u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
- unsigned long rate = clk->parent->rate >> shift;
- pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
- return rate;
-}
-
-static unsigned long clksel_recalc_parent_rate(struct clk *clk)
-{
- unsigned long rate = clk->parent->rate;
- pr_debug("%s new clock rate is %lu\n", clk->name, rate);
- return rate;
-}
-/********************************set div rate***********************************/
-
-//for free div
-static int clksel_set_rate_freediv(struct clk *clk, unsigned long rate)
-{
- u32 div;
- for (div = 0; div < clk->div_max; div++) {
- u32 new_rate = clk->parent->rate / (div + 1);
- if (new_rate <= rate) {
- set_cru_bits_w_msk(div, clk->div_mask, clk->div_shift, clk->clksel_con);
- //clk->rate = new_rate;
- pr_debug("clksel_set_rate_freediv for clock %s to rate %ld (div %d)\n",
- clk->name, rate, div + 1);
- return 0;
- }
- }
- return -ENOENT;
-}
-
-//for div 1 2 4 2^n
-static int clksel_set_rate_shift(struct clk *clk, unsigned long rate)
-{
- u32 shift;
- for (shift = 0; (1 << shift) < clk->div_max; shift++) {
- u32 new_rate = clk->parent->rate >> shift;
- if (new_rate <= rate) {
- set_cru_bits_w_msk(shift, clk->div_mask, clk->div_shift, clk->clksel_con);
- clk->rate = new_rate;
- pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n",
- clk->name, rate, shift);
- return 0;
- }
- }
- return -ENOENT;
-}
-
-//for div 2 4 2^n
-static int clksel_set_rate_shift_2(struct clk *clk, unsigned long rate)
-{
- u32 shift;
-
- for (shift = 1; (1 << shift) < clk->div_max; shift++) {
- u32 new_rate = clk->parent->rate >> shift;
- if (new_rate <= rate) {
- set_cru_bits_w_msk(shift - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
- clk->rate = new_rate;
- pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n",
- clk->name, rate, shift);
- return 0;
- }
- }
- return -ENOENT;
-}
-
-//for div 1 2 4 2*n
-static int clksel_set_rate_even(struct clk *clk, unsigned long rate)
-{
- u32 div = 0, new_rate = 0;
- for (div = 1; div < clk->div_max; div++) {
- if (div >= 3 && div % 2 != 0)
- continue;
- new_rate = clk->parent->rate / div;
- if (new_rate <= rate) {
- set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
- clk->rate = new_rate;
- pr_debug("%s for clock %s to rate %ld (even div = %d)\n",
- __func__, clk->name, rate, div);
- return 0;
- }
- }
- return -ENOENT;
-}
-static u32 clk_get_freediv(unsigned long rate_out, unsigned long rate , u32 div_max)
-{
- u32 div;
- unsigned long new_rate;
- for (div = 0; div < div_max; div++) {
- new_rate = rate / (div + 1);
- if (new_rate <= rate_out) {
- return div + 1;
- }
- }
- return div_max ? div_max : 1;
-}
-static u32 clk_get_evendiv(unsigned long rate_out, unsigned long rate , u32 div_max)
-{
- u32 div;
- unsigned long new_rate;
- for (div = 1; div < div_max; div += 2) {
- new_rate = rate / (div + 1);
- if (new_rate <= rate_out) {
- return div + 1;
- }
- }
- return div_max ? div_max : 1;
-}
-struct clk *get_freediv_parents_div(struct clk *clk, unsigned long rate, u32 *div_out) {
- u32 div[2] = {0, 0};
- unsigned long new_rate[2] = {0, 0};
- u32 i;
-
- if(clk->rate == rate)
- return clk->parent;
- for(i = 0; i < 2; i++) {
- div[i] = clk_get_freediv(rate, clk->parents[i]->rate, clk->div_max);
- new_rate[i] = clk->parents[i]->rate / div[i];
- if(new_rate[i] == rate) {
- *div_out = div[i];
- return clk->parents[i];
- }
- }
- if(new_rate[0] < new_rate[1])
- i = 1;
- else
- i = 0;
- *div_out = div[i];
- return clk->parents[i];
-}
-struct clk *get_evendiv_parents_div(struct clk *clk, unsigned long rate, u32 *div_out) {
- u32 div[2] = {0, 0};
- unsigned long new_rate[2] = {0, 0};
- u32 i;
-
- if(clk->rate == rate)
- return clk->parent;
- for(i = 0; i < 2; i++) {
- div[i] = clk_get_evendiv(rate, clk->parents[i]->rate, clk->div_max);
- new_rate[i] = clk->parents[i]->rate / div[i];
- if(new_rate[i] == rate) {
- *div_out = div[i];
- return clk->parents[i];
- }
- }
- if(new_rate[0] < new_rate[1])
- i = 1;
- else
- i = 0;
- *div_out = div[i];
- return clk->parents[i];
-}
-
-static int clkset_rate_freediv_autosel_parents(struct clk *clk, unsigned long rate)
-{
- struct clk *p_clk;
- u32 div, old_div;
- int ret = 0;
- if(clk->rate == rate)
- return 0;
- p_clk = get_freediv_parents_div(clk, rate, &div);
-
- if(!p_clk)
- return -ENOENT;
-
- CLKDATA_DBG("%s %lu,form %s\n", clk->name, rate, p_clk->name);
- if (clk->parent != p_clk) {
- old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con), clk->div_shift, clk->div_mask) + 1;
-
- if(div > old_div) {
- set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
- }
- ret = clk_set_parent_nolock(clk, p_clk);
- if(ret) {
- CLKDATA_ERR("%s can't set %lu,reparent err\n", clk->name, rate);
- return -ENOENT;
- }
- }
- //set div
- set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
- return 0;
-}
-static int clkset_rate_evendiv_autosel_parents(struct clk *clk, unsigned long rate)
-{
- struct clk *p_clk;
- u32 div, old_div;
- int ret = 0;
- if(clk->rate == rate)
- return 0;
- p_clk = get_evendiv_parents_div(clk, rate, &div);
-
- if(!p_clk)
- return -ENOENT;
-
- CLKDATA_DBG("%s %lu,form %s\n", clk->name, rate, p_clk->name);
- if (clk->parent != p_clk) {
- old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con), clk->div_shift, clk->div_mask) + 1;
-
- if(div > old_div) {
- set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
- }
- ret = clk_set_parent_nolock(clk, p_clk);
- if(ret) {
- CLKDATA_ERR("%s can't set %lu,reparent err\n", clk->name, rate);
- return -ENOENT;
- }
- }
- //set div
- set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
- return 0;
-}
-
-//rate==div rate //hdmi
-static int clk_freediv_autosel_parents_set_fixed_rate(struct clk *clk, unsigned long rate)
-{
- struct clk *p_clk;
- u32 div, old_div;
- int ret;
- p_clk = get_freediv_parents_div(clk, rate, &div);
-
- if(!p_clk)
- return -ENOENT;
-
- if((p_clk->rate / div) != rate || (p_clk->rate % div))
- return -ENOENT;
-
- if (clk->parent != p_clk) {
- old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con),
- clk->div_shift, clk->div_mask) + 1;
- if(div > old_div) {
- set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
- }
- ret = clk_set_parent_nolock(clk, p_clk);
- if (ret) {
- CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
- return ret;
- }
- }
- //set div
- set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
- return 0;
-}
-
-/***************************round********************************/
-
-static long clksel_freediv_round_rate(struct clk *clk, unsigned long rate)
-{
- return clk->parent->rate / clk_get_freediv(rate, clk->parent->rate, clk->div_max);
-}
-
-static long clk_freediv_round_autosel_parents_rate(struct clk *clk, unsigned long rate)
-{
- u32 div;
- struct clk *p_clk;
- if(clk->rate == rate)
- return clk->rate;
- p_clk = get_freediv_parents_div(clk, rate, &div);
- if(!p_clk)
- return 0;
- return p_clk->rate / div;
-}
-
-/**************************************others seting************************************/
-
-static struct clk *clksel_get_parent(struct clk *clk) {
- return clk->parents[(cru_readl(clk->clksel_con) >> clk->src_shift) & clk->src_mask];
-}
-static int clksel_set_parent(struct clk *clk, struct clk *parent)
-{
- u32 i;
- if (unlikely(!clk->parents))
- return -EINVAL;
- for (i = 0; (i < clk->parents_num); i++) {
- if (clk->parents[i] != parent)
- continue;
- set_cru_bits_w_msk(i, clk->src_mask, clk->src_shift, clk->clksel_con);
- return 0;
- }
- return -EINVAL;
-}
-
-static int gate_mode(struct clk *clk, int on)
-{
- int idx = clk->gate_idx;
- if (idx >= CLK_GATE_MAX)
- return -EINVAL;
- if(on) {
- cru_writel(CLK_GATE_W_MSK(idx) | CLK_UN_GATE(idx), CLK_GATE_CLKID_CONS(idx));
- //CLKDATA_DBG("un gate id=%d %s(%x),con %x\n",idx,clk->name,
- // CLK_GATE_W_MSK(idx)|CLK_UN_GATE(idx),CLK_GATE_CLKID_CONS(idx));
- } else {
- cru_writel(CLK_GATE_W_MSK(idx) | CLK_GATE(idx), CLK_GATE_CLKID_CONS(idx));
- // CLKDATA_DBG("gate id=%d %s(%x),con%x\n",idx,clk->name,
- // CLK_GATE_W_MSK(idx)|CLK_GATE(idx),CLK_GATE_CLKID_CONS(idx));
- }
- return 0;
-}
-/*****************************frac set******************************************/
-
-static unsigned long clksel_recalc_frac(struct clk *clk)
-{
- unsigned long rate;
- u64 rate64;
- u32 r = cru_readl(clk->clksel_con), numerator, denominator;
- if (r == 0) // FPGA ?
- return clk->parent->rate;
- numerator = r >> 16;
- denominator = r & 0xFFFF;
- rate64 = (u64)clk->parent->rate * numerator;
- do_div(rate64, denominator);
- rate = rate64;
- pr_debug("%s new clock rate is %lu (frac %u/%u)\n", clk->name, rate, numerator, denominator);
- return rate;
-}
-
-static u32 clk_gcd(u32 numerator, u32 denominator)
-{
- u32 a, b;
-
- if (!numerator || !denominator)
- return 0;
- if (numerator > denominator) {
- a = numerator;
- b = denominator;
- } else {
- a = denominator;
- b = numerator;
- }
- while (b != 0) {
- int r = b;
- b = a % b;
- a = r;
- }
-
- return a;
-}
-
-static int frac_div_get_seting(unsigned long rate_out, unsigned long rate,
- u32 *numerator, u32 *denominator)
-{
- u32 gcd_vl;
- gcd_vl = clk_gcd(rate, rate_out);
- CLKDATA_DBG("frac_get_seting rate=%lu,parent=%lu,gcd=%d\n", rate_out, rate, gcd_vl);
-
- if (!gcd_vl) {
- CLKDATA_ERR("gcd=0, i2s frac div is not be supported\n");
- return -ENOENT;
- }
-
- *numerator = rate_out / gcd_vl;
- *denominator = rate / gcd_vl;
-
- CLKDATA_DBG("frac_get_seting numerator=%d,denominator=%d,times=%d\n",
- *numerator, *denominator, *denominator / *numerator);
-
- if (*numerator > 0xffff || *denominator > 0xffff ||
- (*denominator / (*numerator)) < 20) {
- CLKDATA_ERR("can't get a available nume and deno\n");
- return -ENOENT;
- }
-
- return 0;
-
-}
-/* *********************pll **************************/
-
-#define rk30_clock_udelay(a) udelay(a);
-
-/*********************pll lock status**********************************/
-//#define GRF_SOC_CON0 0x15c
-static void pll_wait_lock(int pll_idx)
-{
- u32 pll_state[4] = {1, 0, 2, 3};
- u32 bit = 0x20u << pll_state[pll_idx];
- int delay = 24000000;
- while (delay > 0) {
- if (regfile_readl(GRF_SOC_STATUS0) & bit)
- break;
- delay--;
- }
- if (delay == 0) {
- CLKDATA_ERR("PLL_ID=%d\npll_con0=%08x\npll_con1=%08x\npll_con2=%08x\npll_con3=%08x\n", pll_idx,
- cru_readl(PLL_CONS(pll_idx, 0)),
- cru_readl(PLL_CONS(pll_idx, 1)),
- cru_readl(PLL_CONS(pll_idx, 2)),
- cru_readl(PLL_CONS(pll_idx, 3)));
-
- CLKDATA_ERR("wait pll bit 0x%x time out!\n", bit);
- while(1);
- }
-}
-
-
-
-/***************************pll function**********************************/
-static unsigned long pll_clk_recalc(u32 pll_id, unsigned long parent_rate)
-{
- unsigned long rate;
-
- if (PLLS_IN_NORM(pll_id)) {
- u32 pll_con0 = cru_readl(PLL_CONS(pll_id, 0));
- u32 pll_con1 = cru_readl(PLL_CONS(pll_id, 1));
-
-
- u64 rate64 = (u64)parent_rate * PLL_NF(pll_con1);
-
- /*
- CLKDATA_DBG("selcon con0(%x) %x,con1(%x)%x, rate64 %llu\n",PLL_CONS(pll_id,0),pll_con0
- ,PLL_CONS(pll_id,1),pll_con1, rate64);
- */
-
-
- //CLKDATA_DBG("pll id=%d con0=%x,con1=%x,parent=%lu\n",pll_id,pll_con0,pll_con1,parent_rate);
- //CLKDATA_DBG("first pll id=%d rate is %lu (NF %d NR %d NO %d)\n",
- //pll_id, rate, PLL_NF(pll_con1), PLL_NR(pll_con0), 1 << PLL_NO(pll_con0));
-
- do_div(rate64, PLL_NR(pll_con0));
- do_div(rate64, PLL_NO(pll_con0));
-
- rate = rate64;
- /*
- CLKDATA_DBG("pll_clk_recalc id=%d rate=%lu (NF %d NR %d NO %d) rate64=%llu\n",
- pll_id, rate, PLL_NF(pll_con1), PLL_NR(pll_con0),PLL_NO(pll_con0), rate64);
- */
- } else {
- rate = parent_rate;
- CLKDATA_DBG("pll_clk_recalc id=%d rate=%lu by pass mode\n", pll_id, rate);
- }
- return rate;
-}
-static unsigned long plls_clk_recalc(struct clk *clk)
-{
- return pll_clk_recalc(clk->pll->id, clk->parent->rate);
-}
-static unsigned long plus_pll_clk_recalc(u32 pll_id, unsigned long parent_rate)
-{
- unsigned long rate;
-
- if (PLLS_IN_NORM(pll_id)) {
- u32 pll_con0 = cru_readl(PLL_CONS(pll_id, 0));
- u32 pll_con1 = cru_readl(PLL_CONS(pll_id, 1));
-
- u64 rate64 = (u64)parent_rate * PLUS_PLL_NF(pll_con1);
-
- do_div(rate64, PLUS_PLL_NR(pll_con0));
- do_div(rate64, PLUS_PLL_NO(pll_con0));
-
- rate = rate64;
- } else {
- rate = parent_rate;
- CLKDATA_DBG("pll_clk_recalc id=%d rate=%lu by pass mode\n", pll_id, rate);
- }
- return rate;
-}
-static unsigned long plus_plls_clk_recalc(struct clk *clk)
-{
- DVFS_DBG("%s: for rk3188 plus\n", __func__);
- return plus_pll_clk_recalc(clk->pll->id, clk->parent->rate);
-}
-
-static int pll_clk_set_rate(struct pll_clk_set *clk_set, u8 pll_id)
-{
- //enter slowmode
- cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
- cru_writel((0x1<<(16+1))|(0x1<<1), PLL_CONS(pll_id, 3));
- dsb();
- dsb();
- dsb();
- dsb();
- dsb();
- dsb();
- cru_writel(clk_set->pllcon0, PLL_CONS(pll_id, 0));
- cru_writel(clk_set->pllcon1, PLL_CONS(pll_id, 1));
-
- rk30_clock_udelay(1);
- cru_writel((0x1<<(16+1)), PLL_CONS(pll_id, 3));
-
- pll_wait_lock(pll_id);
-
- //return form slow
- cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
-
- /*
- CLKDATA_ERR("pll reg id=%d,con0=%x,con1=%x,mode=%x\n",pll_id,
- cru_readl(PLL_CONS(pll_id,0)),(PLL_CONS(pll_id,1)),cru_readl(CRU_MODE_CON));
- */
-
- return 0;
-}
-
-static int plus_pll_clk_set_rate(struct pll_clk_set *clk_set, u8 pll_id)
-{
- //enter slowmode
- cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
-
- //enter rest
- cru_writel(PLL_RESET_W_MSK | PLL_RESET, PLL_CONS(pll_id, 3));
- cru_writel(clk_set->pllcon0, PLL_CONS(pll_id, 0));
- cru_writel(clk_set->pllcon1, PLL_CONS(pll_id, 1));
- cru_writel(clk_set->pllcon2, PLL_CONS(pll_id, 2));
- rk30_clock_udelay(5);
-
- //return form rest
- cru_writel(PLL_RESET_W_MSK | PLL_RESET_RESUME, PLL_CONS(pll_id, 3));
-
- //wating lock state
- rk30_clock_udelay(clk_set->rst_dly);
- pll_wait_lock(pll_id);
-
- //return form slow
- cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
-
- return 0;
-}
-
-static int gpll_clk_set_rate(struct clk *c, unsigned long rate)
-{
- struct _pll_data *pll_data = c->pll;
- struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
-
- while(clk_set->rate) {
- if (clk_set->rate == rate) {
- break;
- }
- clk_set++;
- }
- if(clk_set->rate == rate) {
- pll_clk_set_rate(clk_set, pll_data->id);
- lpj_gpll = CLK_LOOPS_RECALC(rate);
- } else {
- CLKDATA_ERR("gpll is no corresponding rate=%lu\n", rate);
- return -1;
- }
- return 0;
-}
-
-static int plus_gpll_clk_set_rate(struct clk *c, unsigned long rate)
-{
- struct _pll_data *pll_data = c->pll;
- struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
- DVFS_DBG("%s: for rk3188 plus\n", __func__);
-
- while(clk_set->rate) {
- if (clk_set->rate == rate) {
- break;
- }
- clk_set++;
- }
- if(clk_set->rate == rate) {
- plus_pll_clk_set_rate(clk_set, pll_data->id);
- lpj_gpll = CLK_LOOPS_RECALC(rate);
- } else {
- CLKDATA_ERR("gpll is no corresponding rate=%lu\n", rate);
- return -1;
- }
- return 0;
-}
-#define PLL_FREF_MIN (183*KHZ)
-#define PLL_FREF_MAX (1500*MHZ)
-
-#define PLL_FVCO_MIN (300*MHZ)
-#define PLL_FVCO_MAX (1500*MHZ)
-
-#define PLL_FOUT_MIN (18750*KHZ)
-#define PLL_FOUT_MAX (1500*MHZ)
-
-#define PLL_NF_MAX (65536)
-#define PLL_NR_MAX (64)
-#define PLL_NO_MAX (64)
-
-static int pll_clk_get_set(unsigned long fin_hz, unsigned long fout_hz, u32 *clk_nr, u32 *clk_nf, u32 *clk_no)
-{
- u32 nr, nf, no, nonr;
- u32 n;
- u32 YFfenzi;
- u32 YFfenmu;
- unsigned long fref, fvco, fout;
- u32 gcd_val = 0;
-
- CLKDATA_DBG("pll_clk_get_set fin=%lu,fout=%lu\n", fin_hz, fout_hz);
- if(!fin_hz || !fout_hz || fout_hz == fin_hz)
- return 0;
- gcd_val = clk_gcd(fin_hz, fout_hz);
- YFfenzi = fout_hz / gcd_val;
- YFfenmu = fin_hz / gcd_val;
-
- for(n = 1;; n++) {
- nf = YFfenzi * n;
- nonr = YFfenmu * n;
- if(nf > PLL_NF_MAX || nonr > (PLL_NO_MAX * PLL_NR_MAX))
- break;
- for(no = 1; no <= PLL_NO_MAX; no++) {
- if(!(no == 1 || !(no % 2)))
- continue;
-
- if(nonr % no)
- continue;
- nr = nonr / no;
-
- if(nr > PLL_NR_MAX) //PLL_NR_MAX
- continue;
-
- fref = fin_hz / nr;
- if(fref < PLL_FREF_MIN || fref > PLL_FREF_MAX)
- continue;
-
- fvco = (fin_hz / nr) * nf;
- if(fvco < PLL_FVCO_MIN || fvco > PLL_FVCO_MAX)
- continue;
- fout = fvco / no;
- if(fout < PLL_FOUT_MIN || fout > PLL_FOUT_MAX)
- continue;
- *clk_nr = nr;
- *clk_no = no;
- *clk_nf = nf;
- return 1;
-
- }
-
- }
- return 0;
-}
-
-static int pll_clk_mode(struct clk *clk, int on)
-{
- u8 pll_id = clk->pll->id;
- u32 nr = PLL_NR(cru_readl(PLL_CONS(pll_id, 0)));
- u32 dly = (nr * 500) / 24 + 1;
- CLKDATA_DBG("pll_mode %s(%d)\n", clk->name, on);
- if (on) {
- cru_writel(PLL_PWR_ON | PLL_PWR_DN_W_MSK, PLL_CONS(pll_id, 3));
- rk30_clock_udelay(dly);
- pll_wait_lock(pll_id);
- cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
- } else {
- cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
- cru_writel(PLL_PWR_DN | PLL_PWR_DN_W_MSK, PLL_CONS(pll_id, 3));
- }
- return 0;
-}
-
-static int cpll_clk_set_rate(struct clk *c, unsigned long rate)
-{
- struct _pll_data *pll_data = c->pll;
- struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
- struct pll_clk_set temp_clk_set;
- u32 clk_nr, clk_nf, clk_no;
-
- if(rate == 24 * MHZ) {
- cru_writel(PLL_MODE_SLOW(pll_data->id), CRU_MODE_CON);
- cru_writel((0x1 << (16+1)) | (0x1<<1), PLL_CONS(pll_data->id, 3));
- return 0;
- }
- while(clk_set->rate) {
- if (clk_set->rate == rate) {
- break;
- }
- clk_set++;
- }
- if(clk_set->rate == rate) {
- CLKDATA_DBG("cpll get a rate\n");
- pll_clk_set_rate(clk_set, pll_data->id);
-
- } else {
- CLKDATA_DBG("cpll get auto calc a rate\n");
- if(pll_clk_get_set(c->parent->rate, rate, &clk_nr, &clk_nf, &clk_no) == 0) {
- pr_err("cpll auto set rate error\n");
- return -ENOENT;
- }
- CLKDATA_DBG("cpll auto ger rate set nr=%d,nf=%d,no=%d\n", clk_nr, clk_nf, clk_no);
- temp_clk_set.pllcon0 = PLL_CLKR_SET(clk_nr) | PLL_CLKOD_SET(clk_no);
- temp_clk_set.pllcon1 = PLL_CLKF_SET(clk_nf);
- temp_clk_set.rst_dly = (clk_nr * 500) / 24 + 1;
- pll_clk_set_rate(&temp_clk_set, pll_data->id);
-
- }
- return 0;
-}
-static int plus_cpll_clk_set_rate(struct clk *c, unsigned long rate)
-{
- struct _pll_data *pll_data = c->pll;
- struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
- struct pll_clk_set temp_clk_set;
- u32 clk_nr, clk_nf, clk_no;
- DVFS_DBG("%s: for rk3188 plus\n", __func__);
-
- while(clk_set->rate) {
- if (clk_set->rate == rate) {
- break;
- }
- clk_set++;
- }
- if(clk_set->rate == rate) {
- CLKDATA_DBG("cpll get a rate\n");
- plus_pll_clk_set_rate(clk_set, pll_data->id);
-
- } else {
- CLKDATA_DBG("cpll get auto calc a rate\n");
- if(pll_clk_get_set(c->parent->rate, rate, &clk_nr, &clk_nf, &clk_no) == 0) {
- pr_err("cpll auto set rate error\n");
- return -ENOENT;
- }
- CLKDATA_DBG("cpll auto ger rate set nr=%d,nf=%d,no=%d\n", clk_nr, clk_nf, clk_no);
- temp_clk_set.pllcon0 = PLL_CLKR_SET(clk_nr) | PLL_CLKOD_SET(clk_no);
- temp_clk_set.pllcon1 = PLL_CLKF_SET(clk_nf);
- temp_clk_set.rst_dly = (clk_nr * 500) / 24 + 1;
- plus_pll_clk_set_rate(&temp_clk_set, pll_data->id);
-
- }
- return 0;
-}
-
-
-/* ******************fixed input clk ***********************************************/
-static struct clk xin24m = {
- .name = "xin24m",
- .rate = 24 * MHZ,
- .flags = RATE_FIXED,
-};
-
-static struct clk clk_12m = {
- .name = "clk_12m",
- .parent = &xin24m,
- .rate = 12 * MHZ,
- .flags = RATE_FIXED,
-};
-
-/************************************pll func***************************/
-static const struct apll_clk_set *arm_pll_clk_get_best_pll_set(unsigned long rate,
- struct apll_clk_set *tables) {
- const struct apll_clk_set *ps, *pt;
-
- /* find the arm_pll we want. */
- ps = pt = tables;
- while (pt->rate) {
- if (pt->rate == rate) {
- ps = pt;
- break;
- }
- // we are sorted, and ps->rate > pt->rate.
- if ((pt->rate > rate || (rate - pt->rate < ps->rate - rate)))
- ps = pt;
- if (pt->rate < rate)
- break;
- pt++;
- }
- //CLKDATA_DBG("arm pll best rate=%lu\n",ps->rate);
- return ps;
-}
-static long arm_pll_clk_round_rate(struct clk *clk, unsigned long rate)
-{
- return arm_pll_clk_get_best_pll_set(rate, clk->pll->table)->rate;
-}
-#if 1
-struct arm_clks_div_set {
- u32 rate;
- u32 clksel0;
- u32 clksel1;
-};
-
-#define _arm_clks_div_set(_mhz,_periph_div,_axi_div,_ahb_div, _apb_div,_ahb2apb) \
-{ \
- .rate =_mhz,\
- .clksel0 = CORE_PERIPH_W_MSK|CORE_PERIPH_##_periph_div,\
- .clksel1 = CORE_ACLK_W_MSK|CORE_ACLK_##_axi_div\
- |ACLK_HCLK_W_MSK|ACLK_HCLK_##_ahb_div\
- |ACLK_PCLK_W_MSK|ACLK_PCLK_##_apb_div\
- |AHB2APB_W_MSK |AHB2APB_##_ahb2apb,\
-}
-struct arm_clks_div_set arm_clk_div_tlb[] = {
- _arm_clks_div_set(50 , 2, 11, 11, 11, 11),//25,50,50,50,50
- _arm_clks_div_set(100 , 4, 11, 21, 21, 11),//25,100,50,50,50
- _arm_clks_div_set(150 , 4, 11, 21, 21, 11),//37,150,75,75,75
- _arm_clks_div_set(200 , 8, 21, 21, 21, 11),//25,100,50,50,50
- _arm_clks_div_set(300 , 8, 21, 21, 21, 11),//37,150,75,75,75
- _arm_clks_div_set(400 , 8, 21, 21, 41, 21),//50,200,100,50,50
- _arm_clks_div_set(0 , 2, 11, 11, 11, 11),//25,50,50,50,50
-};
-struct arm_clks_div_set *arm_clks_get_div(u32 rate) {
- int i = 0;
- for(i = 0; arm_clk_div_tlb[i].rate != 0; i++) {
- if(arm_clk_div_tlb[i].rate >= rate)
- return &arm_clk_div_tlb[i];
- }
- return NULL;
-}
-
-#endif
-
-static int arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
-{
- unsigned long flags;
- const struct apll_clk_set *ps;
- u32 pll_id = clk->pll->id;
- u32 temp_div;
- u32 old_aclk_div = 0, new_aclk_div;
-
- ps = arm_pll_clk_get_best_pll_set(rate, (struct apll_clk_set *)clk->pll->table);
-
- old_aclk_div = GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
- new_aclk_div = GET_CORE_ACLK_VAL(ps->clksel1 & CORE_ACLK_MSK);
-
- CLKDATA_LOG("apll will set rate(%lu) tlb con(%x,%x,%x),sel(%x,%x)\n",
- ps->rate, ps->pllcon0, ps->pllcon1, ps->pllcon2, ps->clksel0, ps->clksel1);
-
- if(general_pll_clk.rate > clk->rate) {
- temp_div = clk_get_freediv(clk->rate, general_pll_clk.rate, 10);
- } else {
- temp_div = 1;
- }
-
- // ungating cpu gpll path
- //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_UN_GATE(CLK_GATE_CPU_GPLL_PATH),
- // CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
-
- local_irq_save(flags);
- //div arm clk for gpll
-
- cru_writel(CORE_CLK_DIV_W_MSK|CORE_CLK_DIV(temp_div), CRU_CLKSELS_CON(0));
- cru_writel(CORE_SEL_PLL_W_MSK|CORE_SEL_GPLL, CRU_CLKSELS_CON(0));
-
- loops_per_jiffy = lpj_gpll / temp_div;
- smp_wmb();
-
- /*if core src don't select gpll ,apll neet to enter slow mode */
- //cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
-
-
- cru_writel((0x1<<(16+1))|(0x1<<1), PLL_CONS(pll_id, 3));
- dsb();
- dsb();
- dsb();
- dsb();
- dsb();
- dsb();
- cru_writel(ps->pllcon0, PLL_CONS(pll_id, 0));
- cru_writel(ps->pllcon1, PLL_CONS(pll_id, 1));
-
- rk30_clock_udelay(1);
- cru_writel((0x1<<(16+1)), PLL_CONS(pll_id, 3));
-
- pll_wait_lock(pll_id);
-
- //return form slow
- //cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
- //reparent to apll
-
- if(new_aclk_div>=old_aclk_div) {
- cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
- cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
- }
-
- cru_writel(CORE_SEL_PLL_W_MSK | CORE_SEL_APLL, CRU_CLKSELS_CON(0));
- if(old_aclk_div>new_aclk_div) {
- cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
- cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
- }
-
- cru_writel(CORE_CLK_DIV_W_MSK|CORE_CLK_DIV(1), CRU_CLKSELS_CON(0));
-
- loops_per_jiffy = ps->lpj;
- smp_wmb();
-
- //CLKDATA_DBG("apll set loops_per_jiffy =%lu,rate(%lu)\n",loops_per_jiffy,ps->rate);
-
- local_irq_restore(flags);
-
- //gate gpll path
- // FIXME
- //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_GATE(CLK_GATE_CPU_GPLL_PATH)
- // , CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
-
- CLKDATA_LOG("apll set over con(%x,%x,%x,%x),sel(%x,%x)\n", cru_readl(PLL_CONS(pll_id, 0)),
- cru_readl(PLL_CONS(pll_id, 1)), cru_readl(PLL_CONS(pll_id, 2)),
- cru_readl(PLL_CONS(pll_id, 3)), cru_readl(CRU_CLKSELS_CON(0)),
- cru_readl(CRU_CLKSELS_CON(1)));
- return 0;
-}
-
-static int plus_arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
-{
- unsigned long flags;
- const struct apll_clk_set *ps;
- u32 pll_id = clk->pll->id;
- u32 temp_div;
- u32 old_aclk_div = 0, new_aclk_div;
- DVFS_DBG("%s: for rk3188 plus\n", __func__);
-
- ps = arm_pll_clk_get_best_pll_set(rate, (struct apll_clk_set *)clk->pll->table);
-
- old_aclk_div = GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
- new_aclk_div = GET_CORE_ACLK_VAL(ps->clksel1 & CORE_ACLK_MSK);
-
- CLKDATA_LOG("apll will set rate(%lu) tlb con(%x,%x,%x),sel(%x,%x)\n",
- ps->rate, ps->pllcon0, ps->pllcon1, ps->pllcon2, ps->clksel0, ps->clksel1);
-
- if(general_pll_clk.rate > clk->rate) {
- temp_div = clk_get_freediv(clk->rate, general_pll_clk.rate, 10);
- } else {
- temp_div = 1;
- }
-
- // ungating cpu gpll path
- //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_UN_GATE(CLK_GATE_CPU_GPLL_PATH),
- // CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
-
- local_irq_save(flags);
- //div arm clk for gpll
-
- cru_writel(CORE_CLK_DIV_W_MSK | CORE_CLK_DIV(temp_div), CRU_CLKSELS_CON(0));
- cru_writel(CORE_SEL_PLL_W_MSK | CORE_SEL_GPLL, CRU_CLKSELS_CON(0));
-
- loops_per_jiffy = lpj_gpll / temp_div;
- smp_wmb();
-
- /*if core src don't select gpll ,apll neet to enter slow mode */
- //cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
-
- //enter rest
- cru_writel(PLL_RESET_W_MSK | PLL_RESET, PLL_CONS(pll_id, 3));
- cru_writel(ps->pllcon0, PLL_CONS(pll_id, 0));
- cru_writel(ps->pllcon1, PLL_CONS(pll_id, 1));
- cru_writel(ps->pllcon2, PLL_CONS(pll_id, 2));
- rk30_clock_udelay(5);
-
- //return form rest
- cru_writel(PLL_RESET_W_MSK | PLL_RESET_RESUME, PLL_CONS(pll_id, 3));
-
- //wating lock state
- rk30_clock_udelay(ps->rst_dly);
- pll_wait_lock(pll_id);
-
- if(new_aclk_div>=old_aclk_div) {
- cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
- cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
- }
-
- cru_writel(CORE_SEL_PLL_W_MSK | CORE_SEL_APLL, CRU_CLKSELS_CON(0));
- if(old_aclk_div>new_aclk_div) {
- cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
- cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
- }
-
- cru_writel(CORE_CLK_DIV_W_MSK|CORE_CLK_DIV(1), CRU_CLKSELS_CON(0));
-
- loops_per_jiffy = ps->lpj;
- smp_wmb();
-
- //CLKDATA_DBG("apll set loops_per_jiffy =%lu,rate(%lu)\n",loops_per_jiffy,ps->rate);
-
- local_irq_restore(flags);
-
- //gate gpll path
- // FIXME
- //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_GATE(CLK_GATE_CPU_GPLL_PATH)
- // , CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
-
- CLKDATA_LOG("apll set over con(%x,%x,%x,%x),sel(%x,%x)\n", cru_readl(PLL_CONS(pll_id, 0)),
- cru_readl(PLL_CONS(pll_id, 1)), cru_readl(PLL_CONS(pll_id, 2)),
- cru_readl(PLL_CONS(pll_id, 3)), cru_readl(CRU_CLKSELS_CON(0)),
- cru_readl(CRU_CLKSELS_CON(1)));
- return 0;
-}
-
-/************************************pll clocks***************************/
-
-static const struct apll_clk_set apll_clks[] = {
- //_APLL_SET_CLKS(_mhz, nr, nf, no, _periph_div,
- // _axi_core_div, _axi_div, _ahb_div, _apb_div, _ahb2apb)
- _APLL_SET_CLKS(2208, 1, 92, 1, 8, 81, 81, 21, 41, 21),
- _APLL_SET_CLKS(2184, 1, 91, 1, 8, 81, 81, 21, 41, 21),
- _APLL_SET_CLKS(2160, 1, 90, 1, 8, 81, 81, 21, 41, 21),
- _APLL_SET_CLKS(2136, 1, 89, 1, 8, 81, 81, 21, 41, 21),
- _APLL_SET_CLKS(2112, 1, 88, 1, 8, 81, 81, 21, 41, 21),
- _APLL_SET_CLKS(2088, 1, 87, 1, 8, 81, 81, 21, 41, 21),
- _APLL_SET_CLKS(2064, 1, 86, 1, 8, 81, 81, 21, 41, 21),
- _APLL_SET_CLKS(2040, 1, 85, 1, 8, 81, 81, 21, 41, 21),
- _APLL_SET_CLKS(2016, 1, 84, 1, 8, 81, 81, 21, 41, 21),
- _APLL_SET_CLKS(1992, 1, 83, 1, 8, 81, 81, 21, 41, 21),
- _APLL_SET_CLKS(1968, 1, 82, 1, 8, 81, 81, 21, 41, 21),
- _APLL_SET_CLKS(1944, 1, 81, 1, 8, 81, 81, 21, 41, 21),
- _APLL_SET_CLKS(1920, 1, 80, 1, 8, 81, 81, 21, 41, 21),
- _APLL_SET_CLKS(1896, 1, 79, 1, 8, 81, 81, 21, 41, 21),
- _APLL_SET_CLKS(1872, 1, 78, 1, 8, 81, 81, 21, 41, 21),
- _APLL_SET_CLKS(1848, 1, 77, 1, 8, 81, 81, 21, 41, 21),
- _APLL_SET_CLKS(1824, 1, 76, 1, 8, 81, 81, 21, 41, 21),
- _APLL_SET_CLKS(1800, 1, 75, 1, 8, 81, 81, 21, 41, 21),
- _APLL_SET_CLKS(1776, 1, 74, 1, 8, 81, 81, 21, 41, 21),
- _APLL_SET_CLKS(1752, 1, 73, 1, 8, 81, 81, 21, 41, 21),
- _APLL_SET_CLKS(1728, 1, 72, 1, 8, 81, 81, 21, 41, 21),
- _APLL_SET_CLKS(1704, 1, 71, 1, 8, 81, 81, 21, 41, 21),
- _APLL_SET_CLKS(1680, 1, 70, 1, 8, 41, 41, 21, 41, 21),
- _APLL_SET_CLKS(1656, 1, 69, 1, 8, 41, 41, 21, 41, 21),
- _APLL_SET_CLKS(1632, 1, 68, 1, 8, 41, 41, 21, 41, 21),
- _APLL_SET_CLKS(1608, 1, 67, 1, 8, 41, 41, 21, 41, 21),
- _APLL_SET_CLKS(1560, 1, 65, 1, 8, 41, 41, 21, 41, 21),
- _APLL_SET_CLKS(1512, 1, 63, 1, 8, 41, 41, 21, 41, 21),
- _APLL_SET_CLKS(1488, 1, 62, 1, 8, 41, 41, 21, 41, 21),
- _APLL_SET_CLKS(1464, 1, 61, 1, 8, 41, 41, 21, 41, 21),
- _APLL_SET_CLKS(1440, 1, 60, 1, 8, 41, 41, 21, 41, 21),
- _APLL_SET_CLKS(1416, 1, 59, 1, 8, 41, 41, 21, 41, 21),
- _APLL_SET_CLKS(1392, 1, 58, 1, 8, 41, 41, 21, 41, 21),
- _APLL_SET_CLKS(1368, 1, 57, 1, 8, 41, 41, 21, 41, 21),
- _APLL_SET_CLKS(1344, 1, 56, 1, 8, 41, 41, 21, 41, 21),
- _APLL_SET_CLKS(1320, 1, 55, 1, 8, 41, 41, 21, 41, 21),
- _APLL_SET_CLKS(1296, 1, 54, 1, 8, 41, 41, 21, 41, 21),
- _APLL_SET_CLKS(1272, 1, 53, 1, 8, 41, 41, 21, 41, 21),
- _APLL_SET_CLKS(1248, 1, 52, 1, 8, 41, 41, 21, 41, 21),
- _APLL_SET_CLKS(1224, 1, 51, 1, 8, 41, 41, 21, 41, 21),
- _APLL_SET_CLKS(1200, 1, 50, 1, 8, 41, 41, 21, 41, 21),
- _APLL_SET_CLKS(1176, 1, 49, 1, 8, 41, 41, 21, 41, 21),
- _APLL_SET_CLKS(1128, 1, 47, 1, 8, 41, 41, 21, 41, 21),
- _APLL_SET_CLKS(1104, 1, 46, 1, 8, 41, 41, 21, 41, 21),
- _APLL_SET_CLKS(1008, 1, 84, 2, 8, 41, 31, 21, 41, 21),
- _APLL_SET_CLKS(912, 1, 76, 2, 8, 41, 31, 21, 41, 21),
- _APLL_SET_CLKS(888, 1, 74, 2, 8, 41, 31, 21, 41, 21),
- _APLL_SET_CLKS(816 , 1, 68, 2, 8, 41, 31, 21, 41, 21),
- _APLL_SET_CLKS(792 , 1, 66, 2, 8, 41, 31, 21, 41, 21),
- _APLL_SET_CLKS(696 , 1, 58, 2, 8, 41, 31, 21, 41, 21),
- _APLL_SET_CLKS(600 , 1, 50, 2, 4, 41, 31, 21, 41, 21),
- _APLL_SET_CLKS(552 , 1, 92, 4, 4, 41, 21, 21, 41, 21),
- _APLL_SET_CLKS(504 , 1, 84, 4, 4, 41, 21, 21, 41, 21),
- _APLL_SET_CLKS(408 , 1, 68, 4, 4, 21, 21, 21, 41, 21),
- _APLL_SET_CLKS(312 , 1, 52, 4, 2, 21, 21, 21, 21, 11),
- _APLL_SET_CLKS(252 , 1, 84, 8, 2, 21, 21, 21, 21, 11),
- _APLL_SET_CLKS(216 , 1, 72, 8, 2, 21, 21, 21, 21, 11),
- _APLL_SET_CLKS(126 , 1, 84, 16, 2, 11, 21, 11, 11, 11),
- _APLL_SET_CLKS(48 , 1, 64, 32, 2, 11, 11, 11, 11, 11),
- _APLL_SET_CLKS(0 , 1, 21, 4, 2, 11, 11, 11, 11, 11),
-
-};
-static struct _pll_data apll_data = SET_PLL_DATA(APLL_ID, (void *)apll_clks);
-static struct clk arm_pll_clk = {
- .name = "arm_pll",
- .parent = &xin24m,
- .mode = pll_clk_mode,
- .recalc = plls_clk_recalc,
- .set_rate = arm_pll_clk_set_rate,
- .round_rate = arm_pll_clk_round_rate,
- .pll = &apll_data,
-};
-
-static int ddr_pll_clk_set_rate(struct clk *clk, unsigned long rate)
-{
- /* do nothing here */
- return 0;
-}
-static struct _pll_data dpll_data = SET_PLL_DATA(DPLL_ID, NULL);
-static struct clk ddr_pll_clk = {
- .name = "ddr_pll",
- .parent = &xin24m,
- .recalc = plls_clk_recalc,
- .set_rate = ddr_pll_clk_set_rate,
- .pll = &dpll_data,
-};
-
-static const struct pll_clk_set cpll_clks[] = {
- _PLL_SET_CLKS(360000, 1, 60, 4),
- _PLL_SET_CLKS(408000, 1, 68, 4),
- _PLL_SET_CLKS(456000, 1, 76, 4),
- _PLL_SET_CLKS(504000, 1, 84, 4),
- _PLL_SET_CLKS(552000, 1, 46, 2),
- _PLL_SET_CLKS(594000, 2, 198, 4),
- _PLL_SET_CLKS(600000, 1, 50, 2),
- _PLL_SET_CLKS(742500, 8, 495, 2),
- _PLL_SET_CLKS(768000, 1, 64, 2),
- _PLL_SET_CLKS(798000, 2, 133, 2),
- _PLL_SET_CLKS(1188000, 2, 99, 1),
- _PLL_SET_CLKS( 0, 4, 133, 1),
-};
-static struct _pll_data cpll_data = SET_PLL_DATA(CPLL_ID, (void *)cpll_clks);
-static struct clk codec_pll_clk = {
- .name = "codec_pll",
- .parent = &xin24m,
- .mode = pll_clk_mode,
- .recalc = plls_clk_recalc,
- .set_rate = cpll_clk_set_rate,
- .pll = &cpll_data,
-};
-
-static const struct pll_clk_set gpll_clks[] = {
- _PLL_SET_CLKS(148500, 2, 99, 8),
- _PLL_SET_CLKS(297000, 2, 198, 8),
- _PLL_SET_CLKS(300000, 1, 50, 4),
- _PLL_SET_CLKS(384000, 2, 128, 4),
- _PLL_SET_CLKS(594000, 2, 198, 4),
- _PLL_SET_CLKS(768000, 1, 64, 2),
- _PLL_SET_CLKS(891000, 8, 594, 2),
- _PLL_SET_CLKS(1188000, 2, 99, 1),
- _PLL_SET_CLKS(1200000, 1, 50, 1),
- _PLL_SET_CLKS(0, 0, 0, 0),
-};
-static struct _pll_data gpll_data = SET_PLL_DATA(GPLL_ID, (void *)gpll_clks);
-static struct clk general_pll_clk = {
- .name = "general_pll",
- .parent = &xin24m,
- .recalc = plls_clk_recalc,
- .set_rate = gpll_clk_set_rate,
- .pll = &gpll_data
-};
-/********************************clocks***********************************/
-//GATE_CLK(ddr_gpll_path, general_pll_clk, DDR_GPLL);
-static struct clk clk_ddr_gpll_path = {
- .name = "ddr_gpll_path",
- .parent = &general_pll_clk,
- .recalc = clksel_recalc_parent_rate,
- .gate_idx = CLK_GATE_DDR_GPLL,
- .mode = gate_mode,
-};
-
-/* core and cpu setting */
-static int ddr_clk_set_rate(struct clk *c, unsigned long rate)
-{
- CLKDATA_DBG("%s do nothing for ddr set rate\n", __func__);
- return 0;
-}
-
-static long ddr_clk_round_rate(struct clk *clk, unsigned long rate)
-{
- CLKDATA_DBG("%s do nothing for ddr round rate\n", __func__);
- return ddr_set_pll_rk3066b(rate / MHZ, 0) * MHZ;
-}
-static unsigned long ddr_clk_recalc_rate(struct clk *clk)
-{
- u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift);
- unsigned long rate = 0;
- clk->parent = clk->get_parent(clk);
- clk->parent->rate = clk->parent->recalc(clk->parent);
- rate = clk->parent->rate >> shift;
-
- CLKDATA_DBG("%s new clock rate is %lu (shift %u), parent=%s, rate=%lu\n",
- clk->name, rate, shift, clk->parent->name, clk->parent->rate);
- return rate;
-}
-static struct clk *clk_ddr_parents[2] = {&ddr_pll_clk, &clk_ddr_gpll_path};
-static struct clk clk_ddr = {
- .name = "ddr",
- .parent = &ddr_pll_clk,
- .get_parent = clksel_get_parent,
- .set_parent = clksel_set_parent,
- .recalc = ddr_clk_recalc_rate,
- .set_rate = ddr_clk_set_rate,
- .round_rate = ddr_clk_round_rate,
- .gate_idx = CLK_GATE_DDRPHY,
- .clksel_con = CRU_CLKSELS_CON(26),
- CRU_DIV_SET(0x3, 0, 4),
- CRU_SRC_SET(1, 8),
- CRU_PARENTS_SET(clk_ddr_parents),
-};
-static int clk_core_set_rate(struct clk *c, unsigned long rate)
-{
- int ret;
-
- ret = clk_set_rate_nolock(c->parent, rate);
- if (ret) {
- CLKDATA_ERR("Failed to change clk pll %s to %lu\n", c->name, rate);
- return ret;
- }
- //set arm pll div 1
- set_cru_bits_w_msk(0, c->div_mask, c->div_shift, c->clksel_con);
- return 0;
-}
-static unsigned long clk_core_get_rate(struct clk *c)
-{
- u32 div = (get_cru_bits(c->clksel_con, c->div_mask, c->div_shift) + 1);
- //c->parent->rate=c->parent->recalc(c->parent);
- return c->parent->rate / div;
-}
-static long core_clk_round_rate(struct clk *clk, unsigned long rate)
-{
- u32 div = (get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1);
- return clk_round_rate_nolock(clk->parent, rate) / div;
-}
-
-static int core_clksel_set_parent(struct clk *clk, struct clk *new_prt)
-{
-
- u32 temp_div;
- struct clk *old_prt;
-
- if(clk->parent == new_prt)
- return 0;
- if (unlikely(!clk->parents))
- return -EINVAL;
- CLKDATA_DBG("%s,reparent %s\n", clk->name, new_prt->name);
- //arm
- old_prt = clk->parent;
-
- if(clk->parents[0] == new_prt) {
- new_prt->set_rate(new_prt, 300 * MHZ);
- set_cru_bits_w_msk(0, clk->div_mask, clk->div_shift, clk->clksel_con);
- } else if(clk->parents[1] == new_prt) {
-
- if(new_prt->rate > old_prt->rate) {
- temp_div = clk_get_freediv(old_prt->rate, new_prt->rate, clk->div_max);
- set_cru_bits_w_msk(temp_div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
- }
- set_cru_bits_w_msk(1, clk->src_mask, clk->src_shift, clk->clksel_con);
- new_prt->set_rate(new_prt, 300 * MHZ);
- } else
- return -1;
-
-
- return 0;
-
-}
-
-static int core_gpll_clk_set_rate(struct clk *c, unsigned long rate)
-{
- u32 temp_div;
- u32 old_aclk_div = 0, new_aclk_div;
- struct arm_clks_div_set *temp_clk_div;
- unsigned long arm_gpll_rate, arm_gpll_lpj;
- temp_div = clk_get_freediv(rate, c->parent->rate, c->div_max);
- arm_gpll_rate = c->parent->rate / temp_div;
-
- temp_clk_div = arm_clks_get_div(arm_gpll_rate / MHZ);
- if(!temp_clk_div)
- temp_clk_div = &arm_clk_div_tlb[4];
-
- old_aclk_div = GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
- new_aclk_div = GET_CORE_ACLK_VAL(temp_clk_div->clksel1 & CORE_ACLK_MSK);
- if(c->rate >= rate) {
- arm_gpll_lpj = lpj_gpll / temp_div;
- set_cru_bits_w_msk(temp_div - 1, c->div_mask, c->div_shift, c->clksel_con);
- }
-
- cru_writel((temp_clk_div->clksel1), CRU_CLKSELS_CON(1));
- cru_writel((temp_clk_div->clksel0) | CORE_CLK_DIV(temp_div) | CORE_CLK_DIV_W_MSK,
- CRU_CLKSELS_CON(0));
- if((c->rate < rate)) {
- arm_gpll_lpj = lpj_gpll / temp_div;
- set_cru_bits_w_msk(temp_div - 1, c->div_mask, c->div_shift, c->clksel_con);
- }
- return 0;
-}
-static unsigned long arm_core_gpll_clk_get_rate(struct clk *c)
-{
- return c->parent->rate;
-}
-static struct clk clk_core_gpll_path = {
- .name = "cpu_gpll_path",
- .parent = &general_pll_clk,
- .recalc = arm_core_gpll_clk_get_rate,
- .set_rate = core_gpll_clk_set_rate,
- CRU_GATE_MODE_SET(gate_mode, CLK_GATE_CPU_GPLL_PATH),
-};
-
-
-static struct clk *clk_core_parents[2] = {&arm_pll_clk, &clk_core_gpll_path};
-
-static struct clk clk_core = {
- .name = "core",
- .parent = &arm_pll_clk,
- .set_rate = clk_core_set_rate,
- .recalc = clk_core_get_rate,
- .round_rate = core_clk_round_rate,
- .set_parent = core_clksel_set_parent,
- .clksel_con = CRU_CLKSELS_CON(0),
- CRU_DIV_SET(0x1f, 9, 32),
- CRU_SRC_SET(1, 8),
- CRU_PARENTS_SET(clk_core_parents),
-};
-GATE_CLK(l2c, clk_core, CLK_L2C);
-GATE_CLK(core_dbg, clk_core, CLK_CORE_DBG);
-static unsigned long aclk_recalc(struct clk *clk)
-{
- unsigned long rate;
- u32 div = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
-
- BUG_ON(div > 5);
- if (div >= 5)
- div = 8;
- rate = clk->parent->rate / div;
- pr_debug("%s new clock rate is %ld (div %d)\n", clk->name, rate, div);
-
- return rate;
-};
-static struct clk core_periph = {
- .name = "core_periph",
- .parent = &clk_core,
- .gate_idx = CLK_GATE_CORE_PERIPH,
- .recalc = clksel_recalc_shift_2,
- .clksel_con = CRU_CLKSELS_CON(0),
- CRU_DIV_SET(0x3, 6, 16),
-};
-static struct clk aclk_core = {
- .name = "aclk_core",
- .parent = &clk_core,
- .gate_idx = CLK_GATE_ACLK_CORE,
- .recalc = aclk_recalc,
- .clksel_con = CRU_CLKSELS_CON(1),
- CRU_DIV_SET(0x7, 3, 8),
-};
-
-static struct clk *clk_cpu_div_parents[2] = {&arm_pll_clk, &general_pll_clk};
-static struct clk clk_cpu_div = {
- .name = "cpu_div",
- .parent = &arm_pll_clk,
- .set_rate = clksel_set_rate_freediv,
- .recalc = clksel_recalc_div,
- .clksel_con = CRU_CLKSELS_CON(0),
- CRU_DIV_SET(0x1f, 0, 32),
- CRU_SRC_SET(1, 5),
- CRU_PARENTS_SET(clk_cpu_div_parents),
-};
-
-static struct clk aclk_cpu = {
- .name = "aclk_cpu",
- .parent = &clk_cpu_div,
- .gate_idx = CLK_GATE_ACLK_CPU,
-};
-
-static struct clk hclk_cpu = {
- .name = "hclk_cpu",
- .parent = &aclk_cpu,
- .gate_idx = CLK_GATE_HCLK_CPU,
- .recalc = clksel_recalc_shift,
- .set_rate = clksel_set_rate_shift,
- .clksel_con = CRU_CLKSELS_CON(1),
- CRU_DIV_SET(0x3, 8, 4),
-
-};
-
-static struct clk pclk_cpu = {
- .name = "pclk_cpu",
- .parent = &aclk_cpu,
- .gate_idx = CLK_GATE_PCLK_CPU,
- .recalc = clksel_recalc_shift,
- .set_rate = clksel_set_rate_shift,
- .clksel_con = CRU_CLKSELS_CON(1),
- CRU_DIV_SET(0x3, 12, 8),
-};
-
-static struct clk ahb2apb_cpu = {
- .name = "ahb2apb",
- .parent = &hclk_cpu,
- .recalc = clksel_recalc_shift,
- .set_rate = clksel_set_rate_shift,
- .clksel_con = CRU_CLKSELS_CON(1),
- CRU_DIV_SET(0x3, 14, 4),
-};
-
-
-static struct clk atclk_cpu = {
- .name = "atclk_cpu",
- .parent = &pclk_cpu,
- .gate_idx = CLK_GATE_ATCLK_CPU,
-};
-
-/* GPU setting */
-static int clk_gpu_set_rate(struct clk *clk, unsigned long rate)
-{
- unsigned long max_rate = rate / 100 * 105; /* +5% */
- return clkset_rate_freediv_autosel_parents(clk, max_rate);
-};
-
-static struct clk *aclk_gpu_parents[2] = {&codec_pll_clk, &general_pll_clk};
-
-static struct clk aclk_gpu = {
- .name = "aclk_gpu",
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .round_rate = clk_freediv_round_autosel_parents_rate,
- .set_rate = clkset_rate_freediv_autosel_parents,
- .clksel_con = CRU_CLKSELS_CON(34),
- .gate_idx = CLK_GATE_ACLK_GPU,
- CRU_DIV_SET(0x1f, 0, 32),
- CRU_SRC_SET(0x1, 7),
- CRU_PARENTS_SET(aclk_gpu_parents),
-};
-
-/* vcodec setting */
-static unsigned long clksel_recalc_vpu_hclk(struct clk *clk)
-{
- unsigned long rate = clk->parent->rate / 4;
- pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, 4);
- return rate;
-}
-
-static struct clk *aclk_vepu_parents[2] = {&codec_pll_clk, &general_pll_clk};
-
-static struct clk aclk_vepu = {
- .name = "aclk_vepu",
- .parent = &codec_pll_clk,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clkset_rate_freediv_autosel_parents,
- .clksel_con = CRU_CLKSELS_CON(32),
- .gate_idx = CLK_GATE_ACLK_VEPU,
- CRU_DIV_SET(0x1f, 0, 32),
- CRU_SRC_SET(0x1, 7),
- CRU_PARENTS_SET(aclk_vepu_parents),
-};
-
-static struct clk *aclk_vdpu_parents[2] = {&codec_pll_clk, &general_pll_clk};
-
-static struct clk aclk_vdpu = {
- .name = "aclk_vdpu",
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clkset_rate_freediv_autosel_parents,
- .clksel_con = CRU_CLKSELS_CON(32),
- .gate_idx = CLK_GATE_ACLK_VDPU,
- CRU_DIV_SET(0x1f, 8, 32),
- CRU_SRC_SET(0x1, 15),
- CRU_PARENTS_SET(aclk_vdpu_parents),
-};
-static struct clk hclk_vepu = {
- .name = "hclk_vepu",
- .parent = &aclk_vepu,
- .mode = gate_mode,
- .recalc = clksel_recalc_vpu_hclk,
- .gate_idx = CLK_GATE_HCLK_VEPU,
-};
-
-static struct clk hclk_vdpu = {
- .name = "hclk_vdpu",
- .parent = &aclk_vdpu,
- .mode = gate_mode,
- .recalc = clksel_recalc_vpu_hclk,
- .gate_idx = CLK_GATE_HCLK_VDPU,
-};
-
-/* aclk lcdc setting */
-static struct clk *aclk_lcdc0_parents[] = {&codec_pll_clk, &general_pll_clk};
-
-static struct clk aclk_lcdc0_pre = {
- .name = "aclk_lcdc0_pre",
- .parent = &codec_pll_clk,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clkset_rate_freediv_autosel_parents,
- .gate_idx = CLK_GATE_ACLK_LCDC0_SRC,
- .clksel_con = CRU_CLKSELS_CON(31),
- CRU_DIV_SET(0x1f, 0, 32),
- CRU_SRC_SET(0x1, 7),
- CRU_PARENTS_SET(aclk_lcdc0_parents),
-};
-
-static struct clk *aclk_lcdc1_parents[] = {&codec_pll_clk, &general_pll_clk};
-
-static struct clk aclk_lcdc1_pre = {
- .name = "aclk_lcdc1_pre",
- .parent = &codec_pll_clk,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clkset_rate_freediv_autosel_parents,
- .gate_idx = CLK_GATE_ACLK_LCDC1_SRC,
- .clksel_con = CRU_CLKSELS_CON(31),
- CRU_DIV_SET(0x1f, 8, 32),
- CRU_SRC_SET(0x1, 15),
- CRU_PARENTS_SET(aclk_lcdc1_parents),
-};
-
-/* aclk/hclk/pclk periph setting */
-static struct clk *aclk_periph_parents[2] = {&codec_pll_clk, &general_pll_clk};
-
-static struct clk aclk_periph = {
- .name = "aclk_periph",
- .parent = &general_pll_clk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_ACLK_PERIPH,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(10),
- CRU_DIV_SET(0x1f, 0, 32),
- CRU_SRC_SET(1, 15),
- CRU_PARENTS_SET(aclk_periph_parents),
-};
-GATE_CLK(periph_src, aclk_periph, PERIPH_SRC);
-
-static struct clk pclk_periph = {
- .name = "pclk_periph",
- .parent = &aclk_periph,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_PCLK_PERIPH,
- .recalc = clksel_recalc_shift,
- .set_rate = clksel_set_rate_shift,
- .clksel_con = CRU_CLKSELS_CON(10),
- CRU_DIV_SET(0x3, 12, 8),
-};
-
-static struct clk hclk_periph = {
- .name = "hclk_periph",
- .parent = &aclk_periph,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_HCLK_PERIPH,
- .recalc = clksel_recalc_shift,
- .set_rate = clksel_set_rate_shift,
- .clksel_con = CRU_CLKSELS_CON(10),
- CRU_DIV_SET(0x3, 8, 4),
-};
-/* dclk lcdc setting */
-// FIXME
-static int clksel_set_rate_hdmi(struct clk *clk, unsigned long rate)
-{
- u32 div, old_div;
- int i;
- unsigned long new_rate;
- int ret = 0;
-
- if(clk->rate == rate)
- return 0;
- for(i = 0; i < 2; i++) {
- div = clk_get_freediv(rate, clk->parents[i]->rate, clk->div_max);
- new_rate = clk->parents[i]->rate / div;
- if((rate == new_rate) && !(clk->parents[i]->rate % div)) {
- break;
- }
- }
- if(i >= 2) {
- CLKDATA_ERR("%s can't set fixed rate%lu\n", clk->name, rate);
- return -1;
- }
-
- //CLKDATA_DBG("%s set rate %lu(from %s)\n",clk->name,rate,clk->parents[i]->name);
-
- old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con),
- clk->div_shift, clk->div_mask) + 1;
- if(div > old_div)
- set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
-
- if(clk->parents[i] != clk->parent) {
- ret = clk_set_parent_nolock(clk, clk->parents[i]);
- }
-
- if (ret) {
- CLKDATA_ERR("lcdc1 %s can't get rate%lu,reparent%s(now %s) err\n",
- clk->name, rate, clk->parents[i]->name, clk->parent->name);
- return ret;
- }
- set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
- return 0;
-}
-
-static int dclk_lcdc_set_rate(struct clk *clk, unsigned long rate)
-{
- if (rate == 27 * MHZ)
- return clkset_rate_freediv_autosel_parents(clk, rate);
- else
- return clkset_rate_evendiv_autosel_parents(clk, rate);
-
-#if 0
- int ret = 0;
- struct clk *parent;
- if (rate == 27 * MHZ && (rk30_clock_flags & CLK_FLG_EXT_27MHZ)) {
- parent = clk->parents[1];
- //CLKDATA_DBG(" %s from=%s\n",clk->name,parent->name);
- } else {
- parent = clk->parents[0];
- }
- //CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
- //clk->name,rate,parent->name,clk->parent->name);
-
- if(parent != clk->parents[1]) {
- ret = clk_set_rate_nolock(parent, rate); //div 1:1
- if (ret) {
- CLKDATA_DBG("%s set rate=%lu err\n", clk->name, rate);
- return ret;
- }
- }
- if (clk->parent != parent) {
- ret = clk_set_parent_nolock(clk, parent);
- if (ret) {
- CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
- return ret;
- }
- }
- return ret;
-#endif
-}
-
-static struct clk *dclk_lcdc0_parents[2] = {&codec_pll_clk, &general_pll_clk};
-static struct clk dclk_lcdc0 = {
- .name = "dclk_lcdc0",
- .mode = gate_mode,
- .set_rate = dclk_lcdc_set_rate,
- .recalc = clksel_recalc_div,
- .gate_idx = CLK_GATE_DCLK_LCDC0_SRC,
- .clksel_con = CRU_CLKSELS_CON(27),
- CRU_SRC_SET(0x1, 0),
- CRU_DIV_SET(0xff, 8, 256),
- CRU_PARENTS_SET(dclk_lcdc0_parents),
-};
-
-static struct clk *dclk_lcdc1_parents[2] = {&codec_pll_clk, &general_pll_clk};
-static struct clk dclk_lcdc1 = {
- .name = "dclk_lcdc1",
- .mode = gate_mode,
- .set_rate = dclk_lcdc_set_rate,
- .recalc = clksel_recalc_div,
- .gate_idx = CLK_GATE_DCLK_LCDC1_SRC,
- .clksel_con = CRU_CLKSELS_CON(28),
- CRU_SRC_SET(0x1, 0),
- CRU_DIV_SET(0xff, 8, 256),
- CRU_PARENTS_SET(dclk_lcdc1_parents),
-};
-
-/* cif setting */
-// FIXME
-static struct clk *cifout_sel_pll_parents[2] = {&codec_pll_clk, &general_pll_clk};
-static struct clk cif_out_pll = {
- .name = "cif_out_pll",
- .parent = &general_pll_clk,
- .clksel_con = CRU_CLKSELS_CON(29),
- CRU_SRC_SET(0x1, 0),
- CRU_PARENTS_SET(cifout_sel_pll_parents),
-};
-
-static struct clk cif0_out_div = {
- .name = "cif0_out_div",
- .parent = &cif_out_pll,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .gate_idx = CLK_GATE_CIF0_OUT,
- .clksel_con = CRU_CLKSELS_CON(29),
- CRU_DIV_SET(0x1f, 1, 32),
-};
-
-static int cif_out_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret = 0;
- struct clk *parent;
-
- if (rate == 24 * MHZ) {
- parent = clk->parents[1];
- } else {
- parent = clk->parents[0];
- ret = clk_set_rate_nolock(parent, rate);
- if (ret)
- return ret;
- }
- if (clk->parent != parent)
- ret = clk_set_parent_nolock(clk, parent);
-
- return ret;
-}
-
-static struct clk *cif0_out_parents[2] = {&cif0_out_div, &xin24m};
-static struct clk cif0_out = {
- .name = "cif0_out",
- .parent = &cif0_out_div,
- .set_rate = cif_out_set_rate,
- .clksel_con = CRU_CLKSELS_CON(29),
- CRU_SRC_SET(0x1, 7),
- CRU_PARENTS_SET(cif0_out_parents),
-};
-
-static struct clk pclkin_cif0 = {
- .name = "pclkin_cif0",
- .mode = gate_mode,
- .gate_idx = CLK_GATE_PCLKIN_CIF0,
-};
-
-static struct clk inv_cif0 = {
- .name = "inv_cif0",
- .parent = &pclkin_cif0,
-};
-
-static struct clk *cif0_in_parents[2] = {&pclkin_cif0, &inv_cif0};
-static struct clk cif0_in = {
- .name = "cif0_in",
- .parent = &pclkin_cif0,
- .clksel_con = CRU_CLKSELS_CON(30),
- CRU_SRC_SET(0x1, 8),
- CRU_PARENTS_SET(cif0_in_parents),
-};
-
-/* i2s/spdif setting */
-static struct clk *clk_i2s_div_parents[] = {&general_pll_clk, &codec_pll_clk};
-static struct clk clk_i2s_pll = {
- .name = "i2s_pll",
- .parent = &general_pll_clk,
- .clksel_con = CRU_CLKSELS_CON(2),
- CRU_SRC_SET(0x1, 15),
- CRU_PARENTS_SET(clk_i2s_div_parents),
-};
-
-static struct clk clk_i2s0_div = {
- .name = "i2s0_div",
- .parent = &clk_i2s_pll,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .round_rate = clksel_freediv_round_rate,
- .gate_idx = CLK_GATE_I2S0_SRC,
- .clksel_con = CRU_CLKSELS_CON(3),
- CRU_DIV_SET(0x7f, 0, 64),
-};
-
-static struct clk clk_spdif_div = {
- .name = "spdif_div",
- .parent = &clk_i2s_pll,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .round_rate = clksel_freediv_round_rate,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_SPDIF_SRC,
- .clksel_con = CRU_CLKSELS_CON(5),
- CRU_DIV_SET(0x7f, 0, 64),
-};
-static int clk_i2s_fracdiv_set_rate(struct clk *clk, unsigned long rate)
-{
- u32 numerator, denominator;
- int i = 10;
- //clk_i2s_div->clk_i2s_pll->gpll/cpll
- //clk->parent->parent
- if(frac_div_get_seting(rate, clk->parent->parent->rate,
- &numerator, &denominator) == 0) {
- clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
-
- while (i--) {
- cru_writel_frac((numerator - 1) << 16 | denominator, clk->clksel_con);
- mdelay(1);
- cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
- mdelay(1);
- }
- CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
- } else {
- CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
- return -ENOENT;
- }
- return 0;
-}
-
-static struct clk clk_i2s0_frac_div = {
- .name = "i2s0_frac_div",
- .parent = &clk_i2s0_div,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_I2S0_FRAC,
- .recalc = clksel_recalc_frac,
- .set_rate = clk_i2s_fracdiv_set_rate,
- .clksel_con = CRU_CLKSELS_CON(7),
-};
-
-static struct clk clk_spdif_frac_div = {
- .name = "spdif_frac_div",
- .parent = &clk_spdif_div,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_SPDIF_FRAC,
- .recalc = clksel_recalc_frac,
- .set_rate = clk_i2s_fracdiv_set_rate,
- .clksel_con = CRU_CLKSELS_CON(9),
-};
-
-#define I2S_SRC_DIV (0x0)
-#define I2S_SRC_FRAC (0x1)
-#define I2S_SRC_12M (0x2)
-
-static int i2s_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret = -EINVAL;
- struct clk *parent;
-
- if (rate == clk->parents[I2S_SRC_12M]->rate) {
- parent = clk->parents[I2S_SRC_12M];
- } else if((long)clk_round_rate_nolock(clk->parents[I2S_SRC_DIV], rate) == rate) {
- parent = clk->parents[I2S_SRC_DIV];
- } else {
- parent = clk->parents[I2S_SRC_FRAC];
- }
-
- CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
- clk->name, rate, parent->name, clk->parent->name);
-
- if(parent != clk->parents[I2S_SRC_12M]) {
- ret = clk_set_rate_nolock(parent, rate); //div 1:1
- if (ret) {
- CLKDATA_DBG("%s set rate%lu err\n", clk->name, rate);
- return ret;
- }
- }
-
- if (clk->parent != parent) {
- ret = clk_set_parent_nolock(clk, parent);
- if (ret) {
- CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
- return ret;
- }
- }
-
- return ret;
-};
-
-static struct clk *clk_i2s0_parents[3] = {&clk_i2s0_div, &clk_i2s0_frac_div, &clk_12m};
-
-static struct clk clk_i2s0 = {
- .name = "i2s0",
- .set_rate = i2s_set_rate,
- .clksel_con = CRU_CLKSELS_CON(3),
- CRU_SRC_SET(0x3, 8),
- CRU_PARENTS_SET(clk_i2s0_parents),
-};
-
-static struct clk *clk_spdif_parents[3] = {&clk_spdif_div, &clk_spdif_frac_div, &clk_12m};
-
-static struct clk clk_spdif = {
- .name = "spdif",
- .parent = &clk_spdif_frac_div,
- .set_rate = i2s_set_rate,
- .clksel_con = CRU_CLKSELS_CON(5),
- CRU_SRC_SET(0x3, 8),
- CRU_PARENTS_SET(clk_spdif_parents),
-};
-
-/* otgphy setting */
-GATE_CLK(otgphy0, xin24m, OTGPHY0);
-GATE_CLK(otgphy1, xin24m, OTGPHY1);
-
-static struct clk clk_otgphy0_480m = {
- .name = "otgphy0_480m",
- .parent = &clk_otgphy0,
-};
-static struct clk clk_otgphy1_480m = {
- .name = "otgphy1_480m",
- .parent = &clk_otgphy1,
-};
-
-/* hsicphy setting */
-#ifdef ARCH_RK31
-static struct clk *clk_hsicphy_parents[4] = {&clk_otgphy0_480m, &clk_otgphy1_480m, &general_pll_clk, &codec_pll_clk};
-static struct clk clk_hsicphy_480m = {
- .name = "hsicphy_480m",
- .parent = &clk_otgphy0_480m,
- .clksel_con = CRU_CLKSELS_CON(30),
- CRU_SRC_SET(0x3, 0),
- CRU_PARENTS_SET(clk_hsicphy_parents),
-};
-static struct clk clk_hsicphy_12m = {
- .name = "hsicphy_12m",
- .parent = &clk_hsicphy_480m,
- .clksel_con = CRU_CLKSELS_CON(11),
- CRU_DIV_SET(0x3f, 8, 64),
-};
-#endif
-
-/* mac and rmii setting */
-// FIXME
-static struct clk rmii_clkin = {
- .name = "rmii_clkin",
-};
-static struct clk *clk_mac_ref_div_parents[2] = {&general_pll_clk, &ddr_pll_clk};
-static struct clk clk_mac_pll_div = {
- .name = "mac_pll_div",
- .parent = &general_pll_clk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_MAC_SRC,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(21),
- CRU_DIV_SET(0x1f, 8, 32),
- CRU_SRC_SET(0x1, 0),
- CRU_PARENTS_SET(clk_mac_ref_div_parents),
-};
-
-static int clksel_mac_ref_set_rate(struct clk *clk, unsigned long rate)
-{
- if(clk->parent == clk->parents[1]) {
- CLKDATA_DBG("mac_ref clk is form mii clkin,can't set it\n" );
- return -ENOENT;
- } else if(clk->parent == clk->parents[0]) {
- return clk_set_rate_nolock(clk->parents[0], rate);
- }
- return -ENOENT;
-}
-
-static struct clk *clk_mac_ref_parents[2] = {&clk_mac_pll_div, &rmii_clkin};
-
-static struct clk clk_mac_ref = {
- .name = "mac_ref",
- .parent = &clk_mac_pll_div,
- .set_rate = clksel_mac_ref_set_rate,
- .clksel_con = CRU_CLKSELS_CON(21),
- CRU_SRC_SET(0x1, 4),
- CRU_PARENTS_SET(clk_mac_ref_parents),
-};
-
-static int clk_set_mii_tx_parent(struct clk *clk, struct clk *parent)
-{
- return clk_set_parent_nolock(clk->parent, parent);
-}
-
-static struct clk clk_mii_tx = {
- .name = "mii_tx",
- .parent = &clk_mac_ref,
- //.set_parent = clk_set_mii_tx_parent,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_MAC_LBTEST,
-};
-
-/* hsadc and saradc */
-static struct clk *clk_hsadc_pll_parents[2] = {&general_pll_clk, &codec_pll_clk};
-static struct clk clk_hsadc_pll_div = {
- .name = "hsadc_pll_div",
- .parent = &general_pll_clk,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_HSADC_SRC,
- .recalc = clksel_recalc_div,
- .round_rate = clk_freediv_round_autosel_parents_rate,
- .set_rate = clkset_rate_freediv_autosel_parents,
- //.round_rate = clksel_freediv_round_rate,
- //.set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(22),
- CRU_DIV_SET(0xff, 8, 256),
- CRU_SRC_SET(0x1, 0),
- CRU_PARENTS_SET(clk_hsadc_pll_parents),
-};
-static int clk_hsadc_fracdiv_set_rate_fixed_parent(struct clk *clk, unsigned long rate)
-{
- u32 numerator, denominator;
- // clk_hsadc_pll_div->gpll/cpll
- //clk->parent->parent
- if(frac_div_get_seting(rate, clk->parent->parent->rate,
- &numerator, &denominator) == 0) {
- clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
-
- cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
-
- CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
- } else {
- CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
- return -ENOENT;
- }
- return 0;
-}
-static int clk_hsadc_fracdiv_set_rate_auto_parents(struct clk *clk, unsigned long rate)
-{
- u32 numerator, denominator;
- u32 i, ret = 0;
- // clk_hsadc_pll_div->gpll/cpll
- //clk->parent->parent
- for(i = 0; i < 2; i++) {
- if(frac_div_get_seting(rate, clk->parent->parents[i]->rate,
- &numerator, &denominator) == 0)
- break;
- }
- if(i >= 2)
- return -ENOENT;
-
- if(clk->parent->parent != clk->parent->parents[i])
- ret = clk_set_parent_nolock(clk->parent, clk->parent->parents[i]);
- if(ret == 0) {
- clk_set_rate_nolock(clk->parent, clk->parent->parents[i]->rate); //PLL:DIV 1:
-
- cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
-
- CLKDATA_DBG("clk_frac_div %s, rate=%lu\n", clk->name, rate);
- } else {
- CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
- return -ENOENT;
- }
- return 0;
-}
-
-static long clk_hsadc_fracdiv_round_rate(struct clk *clk, unsigned long rate)
-{
- u32 numerator, denominator;
-
- CLKDATA_ERR("clk_hsadc_fracdiv_round_rate\n");
- if(frac_div_get_seting(rate, clk->parent->parent->rate,
- &numerator, &denominator) == 0)
- return rate;
-
- return 0;
-}
-static struct clk clk_hsadc_frac_div = {
- .name = "hsadc_frac_div",
- .parent = &clk_hsadc_pll_div,
- .mode = gate_mode,
- .recalc = clksel_recalc_frac,
- .set_rate = clk_hsadc_fracdiv_set_rate_auto_parents,
- .round_rate = clk_hsadc_fracdiv_round_rate,
- .gate_idx = CLK_GATE_HSADC_FRAC_SRC,
- .clksel_con = CRU_CLKSELS_CON(23),
-};
-
-#define HSADC_SRC_DIV 0x0
-#define HSADC_SRC_FRAC 0x1
-#define HSADC_SRC_EXT 0x2
-static int clk_hsadc_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret = -EINVAL;
- struct clk *parent;
-
- if(clk->parent == clk->parents[HSADC_SRC_EXT]) {
- CLKDATA_DBG("hsadc clk is form ext\n");
- return 0;
- } else if((long)clk_round_rate_nolock(clk->parents[HSADC_SRC_DIV], rate) == rate) {
- parent = clk->parents[HSADC_SRC_DIV];
- } else if((long)clk_round_rate_nolock(clk->parents[HSADC_SRC_FRAC], rate) == rate) {
- parent = clk->parents[HSADC_SRC_FRAC];
- } else
- parent = clk->parents[HSADC_SRC_DIV];
-
- CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
- clk->name, rate, parent->name, clk->parent->name);
-
- ret = clk_set_rate_nolock(parent, rate);
- if (ret) {
- CLKDATA_ERR("%s set rate%lu err\n", clk->name, rate);
- return ret;
- }
- if (clk->parent != parent) {
- ret = clk_set_parent_nolock(clk, parent);
- if (ret) {
- CLKDATA_ERR("%s can't get rate%lu,reparent err\n", clk->name, rate);
- return ret;
- }
- }
- return ret;
-}
-
-static struct clk clk_hsadc_ext = {
- .name = "hsadc_ext",
-};
-
-static struct clk *clk_hsadc_out_parents[3] = {&clk_hsadc_pll_div, &clk_hsadc_frac_div, &clk_hsadc_ext};
-static struct clk clk_hsadc_out = {
- .name = "hsadc_out",
- .parent = &clk_hsadc_pll_div,
- .set_rate = clk_hsadc_set_rate,
- .clksel_con = CRU_CLKSELS_CON(22),
- CRU_SRC_SET(0x3, 4),
- CRU_PARENTS_SET(clk_hsadc_out_parents),
-};
-static struct clk clk_hsadc_out_inv = {
- .name = "hsadc_out_inv",
- .parent = &clk_hsadc_out,
-};
-
-static struct clk *clk_hsadc_parents[3] = {&clk_hsadc_out, &clk_hsadc_out_inv};
-static struct clk clk_hsadc = {
- .name = "hsadc",
- .parent = &clk_hsadc_out,
- .clksel_con = CRU_CLKSELS_CON(22),
- CRU_SRC_SET(0x1, 7),
- CRU_PARENTS_SET(clk_hsadc_parents),
-};
-
-static struct clk clk_saradc = {
- .name = "saradc",
- .parent = &xin24m,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .gate_idx = CLK_GATE_SARADC_SRC,
- .clksel_con = CRU_CLKSELS_CON(24),
- CRU_DIV_SET(0xff, 8, 256),
-};
-
-/* smc setting */
-GATE_CLK(smc, hclk_periph, SMC_SRC);//smc
-static struct clk clkn_smc = {
- .name = "smc_inv",
- .parent = &clk_smc,
-};
-
-/* spi setting */
-static struct clk clk_spi0 = {
- .name = "spi0",
- .parent = &pclk_periph,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .gate_idx = CLK_GATE_SPI0_SRC,
- .clksel_con = CRU_CLKSELS_CON(25),
- CRU_DIV_SET(0x7f, 0, 128),
-};
-
-static struct clk clk_spi1 = {
- .name = "spi1",
- .parent = &pclk_periph,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .gate_idx = CLK_GATE_SPI1_SRC,
- .clksel_con = CRU_CLKSELS_CON(25),
- CRU_DIV_SET(0x7f, 8, 128),
-};
-
-/* sdmmc/sdio/emmc setting */
-static struct clk clk_sdmmc = {
- .name = "sdmmc",
- .parent = &hclk_periph,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_even,
- .gate_idx = CLK_GATE_MMC0_SRC,
- .clksel_con = CRU_CLKSELS_CON(11),
- CRU_DIV_SET(0x3f, 0, 64),
-};
-
-static struct clk clk_sdio = {
- .name = "sdio",
- .parent = &hclk_periph,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_even,
- .gate_idx = CLK_GATE_SDIO_SRC,
- .clksel_con = CRU_CLKSELS_CON(12),
- CRU_DIV_SET(0x3f, 0, 64),
-
-};
-
-static struct clk clk_emmc = {
- .name = "emmc",
- .parent = &hclk_periph,
- .mode = gate_mode,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_even,
- .gate_idx = CLK_GATE_EMMC_SRC,
- .clksel_con = CRU_CLKSELS_CON(12),
- CRU_DIV_SET(0x3f, 8, 64),
-};
-
-/* uart setting */
-static struct clk *clk_uart_src_parents[2] = {&general_pll_clk, &codec_pll_clk};
-static struct clk clk_uart_pll = {
- .name = "uart_pll",
- .parent = &general_pll_clk,
- .clksel_con = CRU_CLKSELS_CON(12),
- CRU_SRC_SET(0x1, 15),
- CRU_PARENTS_SET(clk_uart_src_parents),
-};
-static struct clk clk_uart0_div = {
- .name = "uart0_div",
- .parent = &clk_uart_pll,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_UART0_SRC,
- .recalc = clksel_recalc_div,
- .set_rate = clksel_set_rate_freediv,
- .round_rate = clksel_freediv_round_rate,
- .clksel_con = CRU_CLKSELS_CON(13),
- CRU_DIV_SET(0x7f, 0, 64),
-};
-static struct clk clk_uart1_div = {
- .name = "uart1_div",
- .parent = &clk_uart_pll,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_UART1_SRC,
- .recalc = clksel_recalc_div,
- .round_rate = clksel_freediv_round_rate,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(14),
- CRU_DIV_SET(0x7f, 0, 64),
-};
-
-static struct clk clk_uart2_div = {
- .name = "uart2_div",
- .parent = &clk_uart_pll,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_UART2_SRC,
- .recalc = clksel_recalc_div,
- .round_rate = clksel_freediv_round_rate,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(15),
- CRU_DIV_SET(0x7f, 0, 64),
-};
-
-static struct clk clk_uart3_div = {
- .name = "uart3_div",
- .parent = &clk_uart_pll,
- .mode = gate_mode,
- .gate_idx = CLK_GATE_UART3_SRC,
- .recalc = clksel_recalc_div,
- .round_rate = clksel_freediv_round_rate,
- .set_rate = clksel_set_rate_freediv,
- .clksel_con = CRU_CLKSELS_CON(16),
- CRU_DIV_SET(0x7f, 0, 64),
-};
-static int clk_uart_fracdiv_set_rate(struct clk *clk, unsigned long rate)
-{
- u32 numerator, denominator;
- //clk_uart0_div->clk_uart_pll->gpll/cpll
- //clk->parent->parent
- if(frac_div_get_seting(rate, clk->parent->parent->rate,
- &numerator, &denominator) == 0) {
- clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
-
- cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
-
- CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
- } else {
- CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
- return -ENOENT;
- }
- return 0;
-}
-
-static struct clk clk_uart0_frac_div = {
- .name = "uart0_frac_div",
- .parent = &clk_uart0_div,
- .mode = gate_mode,
- .recalc = clksel_recalc_frac,
- .set_rate = clk_uart_fracdiv_set_rate,
- .gate_idx = CLK_GATE_UART0_FRAC_SRC,
- .clksel_con = CRU_CLKSELS_CON(17),
-};
-static struct clk clk_uart1_frac_div = {
- .name = "uart1_frac_div",
- .parent = &clk_uart1_div,
- .mode = gate_mode,
- .recalc = clksel_recalc_frac,
- .set_rate = clk_uart_fracdiv_set_rate,
- .gate_idx = CLK_GATE_UART1_FRAC_SRC,
- .clksel_con = CRU_CLKSELS_CON(18),
-};
-static struct clk clk_uart2_frac_div = {
- .name = "uart2_frac_div",
- .mode = gate_mode,
- .parent = &clk_uart2_div,
- .recalc = clksel_recalc_frac,
- .set_rate = clk_uart_fracdiv_set_rate,
- .gate_idx = CLK_GATE_UART2_FRAC_SRC,
- .clksel_con = CRU_CLKSELS_CON(19),
-};
-static struct clk clk_uart3_frac_div = {
- .name = "uart3_frac_div",
- .parent = &clk_uart3_div,
- .mode = gate_mode,
- .recalc = clksel_recalc_frac,
- .set_rate = clk_uart_fracdiv_set_rate,
- .gate_idx = CLK_GATE_UART3_FRAC_SRC,
- .clksel_con = CRU_CLKSELS_CON(20),
-};
-
-#define UART_SRC_DIV 0
-#define UART_SRC_FRAC 1
-#define UART_SRC_24M 2
-
-static int clk_uart_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret = 0;
- struct clk *parent;
-
- if(rate == clk->parents[UART_SRC_24M]->rate) { //24m
- parent = clk->parents[UART_SRC_24M];
- } else if((long)clk_round_rate_nolock(clk->parents[UART_SRC_DIV], rate) == rate) {
- parent = clk->parents[UART_SRC_DIV];
- } else {
- parent = clk->parents[UART_SRC_FRAC];
- }
-
- CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
- clk->name, rate, parent->name, clk->parent->name);
-
- if(parent != clk->parents[UART_SRC_24M]) {
- ret = clk_set_rate_nolock(parent, rate);
- if (ret) {
- CLKDATA_DBG("%s set rate%lu err\n", clk->name, rate);
- return ret;
- }
- }
-
- if (clk->parent != parent) {
- ret = clk_set_parent_nolock(clk, parent);
- if (ret) {
- CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
- return ret;
- }
- }
-
- return ret;
-}
-
-static struct clk *clk_uart0_parents[3] = {&clk_uart0_div, &clk_uart0_frac_div, &xin24m};
-static struct clk clk_uart0 = {
- .name = "uart0",
- .set_rate = clk_uart_set_rate,
- .clksel_con = CRU_CLKSELS_CON(13),
- CRU_SRC_SET(0x3, 8),
- CRU_PARENTS_SET(clk_uart0_parents),
-};
-
-static struct clk *clk_uart1_parents[3] = {&clk_uart1_div, &clk_uart1_frac_div, &xin24m};
-static struct clk clk_uart1 = {
- .name = "uart1",
- .set_rate = clk_uart_set_rate,
- .clksel_con = CRU_CLKSELS_CON(14),
- CRU_SRC_SET(0x3, 8),
- CRU_PARENTS_SET(clk_uart1_parents),
-};
-
-static struct clk *clk_uart2_parents[3] = {&clk_uart2_div, &clk_uart2_frac_div, &xin24m};
-static struct clk clk_uart2 = {
- .name = "uart2",
- .set_rate = clk_uart_set_rate,
- .clksel_con = CRU_CLKSELS_CON(15),
- CRU_SRC_SET(0x3, 8),
- CRU_PARENTS_SET(clk_uart2_parents),
-};
-static struct clk *clk_uart3_parents[3] = {&clk_uart3_div, &clk_uart3_frac_div, &xin24m};
-static struct clk clk_uart3 = {
- .name = "uart3",
- .set_rate = clk_uart_set_rate,
- .clksel_con = CRU_CLKSELS_CON(16),
- CRU_SRC_SET(0x3, 8),
- CRU_PARENTS_SET(clk_uart3_parents),
-};
-
-/* timer setting */
-GATE_CLK(timer0, xin24m, TIMER0);
-GATE_CLK(timer1, xin24m, TIMER1);
-GATE_CLK(timer2, xin24m, TIMER2);
-GATE_CLK(timer3, xin24m, TIMER3);
-GATE_CLK(timer4, xin24m, TIMER4);
-GATE_CLK(timer5, xin24m, TIMER5);
-GATE_CLK(timer6, xin24m, TIMER6);
-
-/*********************power domain*******************************/
-#if 1
-#ifdef RK30_CLK_OFFBOARD_TEST
-void pmu_set_power_domain_test(enum pmu_power_domain pd, bool on) {};
-#define _pmu_set_power_domain pmu_set_power_domain_test//rk30_pmu_set_power_domain
-#else
-void pmu_set_power_domain(enum pmu_power_domain pd, bool on);
-#define _pmu_set_power_domain pmu_set_power_domain
-#endif
-
-static int pd_video_mode(struct clk *clk, int on)
-{
- u32 gate[3];
- gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
- gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
- //gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
- //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
- pmu_set_power_domain(PD_VIDEO, on);
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
- //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
- return 0;
-}
-
-static struct clk pd_video = {
- .name = "pd_video",
- .flags = IS_PD,
- .mode = pd_video_mode,
- .gate_idx = PD_VIDEO,
-};
-static int pd_display_mode(struct clk *clk, int on)
-{
- u32 gate[10];
- gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
- gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
- gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
- gate[3] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
- gate[4] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
- //gate[5] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
- gate[6] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
- gate[7] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
- gate[8] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
- gate[9] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
- //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
- pmu_set_power_domain(PD_VIO, on);
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1) | gate[3], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0) | gate[4], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
- //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1) | gate[5], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0) | gate[6], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1) | gate[7], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP) | gate[8], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA) | gate[9], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
- return 0;
-}
-
-static struct clk pd_display = {
- .name = "pd_vio",
- .flags = IS_PD,
- .mode = pd_display_mode,
- .gate_idx = PD_VIO,
-};
-static struct clk pd_lcdc0 = {
- .parent = &pd_display,
- .name = "pd_lcdc0",
-};
-static struct clk pd_lcdc1 = {
- .parent = &pd_display,
- .name = "pd_lcdc1",
-};
-static struct clk pd_cif0 = {
- .parent = &pd_display,
- .name = "pd_cif0",
-};
-static struct clk pd_rga = {
- .parent = &pd_display,
- .name = "pd_rga",
-};
-static struct clk pd_ipp = {
- .parent = &pd_display,
- .name = "pd_ipp",
-};
-static struct clk pd_hdmi = {
- .parent = &pd_display,
- .name = "pd_hdmi",
-};
-
-
-static int pd_gpu_mode(struct clk *clk, int on)
-{
- u32 gate[3];
- gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
- pmu_set_power_domain(PD_GPU, on);
- cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
- return 0;
-}
-
-static struct clk pd_gpu = {
- .name = "pd_gpu",
- .flags = IS_PD,
- .mode = pd_gpu_mode,
- .gate_idx = PD_GPU,
-};
-
-static int pm_off_mode(struct clk *clk, int on)
-{
- _pmu_set_power_domain(clk->gate_idx, on); //on 1
- return 0;
-}
-static struct clk pd_peri = {
- .name = "pd_peri",
- .flags = IS_PD,
- .mode = pm_off_mode,
- .gate_idx = PD_PERI,
-};
-
-
-#define PD_CLK(name) \
-{\
- .dev_id = NULL,\
- .con_id = #name,\
- .clk = &name,\
-}
-
-#endif
-/************************rk30 fixed div clock****************************************/
-
-/*************************aclk_cpu***********************/
-
-GATE_CLK(dma1, aclk_cpu, ACLK_DMAC1);
-GATE_CLK(intmem, aclk_cpu, ACLK_INTMEM);
-GATE_CLK(aclk_strc_sys, aclk_cpu, ACLK_STRC_SYS);
-
-/*************************hclk_cpu***********************/
-
-GATE_CLK(rom, hclk_cpu, HCLK_ROM);
-GATE_CLK(hclk_i2s0_2ch, hclk_cpu, HCLK_I2S0_2CH);
-GATE_CLK(hclk_spdif, hclk_cpu, HCLK_SPDIF);
-GATE_CLK(hclk_cpubus, hclk_cpu, HCLK_CPUBUS);
-GATE_CLK(hclk_ahb2apb, hclk_cpu, HCLK_AHB2APB);
-GATE_CLK(hclk_vio_bus, hclk_cpu, HCLK_VIO_BUS);
-GATE_CLK(hclk_lcdc0, hclk_cpu, HCLK_LCDC0);
-GATE_CLK(hclk_lcdc1, hclk_cpu, HCLK_LCDC1);
-GATE_CLK(hclk_cif0, hclk_cpu, HCLK_CIF0);
-GATE_CLK(hclk_ipp, hclk_cpu, HCLK_IPP);
-GATE_CLK(hclk_rga, hclk_cpu, HCLK_RGA);
-GATE_CLK(hclk_imem0, hclk_cpu, HCLK_IMEM0);
-GATE_CLK(hclk_imem1, hclk_cpu, HCLK_IMEM1);
-
-/*************************ahb2apb_cpu(pclk_cpu_h2p)***********************/
-GATE_CLK(pclk_uart0, ahb2apb_cpu, PCLK_UART0);
-GATE_CLK(pclk_uart1, ahb2apb_cpu, PCLK_UART1);
-/*************************pclk_cpu***********************/
-GATE_CLK(pwm01, pclk_cpu, PCLK_PWM01);//pwm 0¡¢1
-GATE_CLK(pclk_timer0, pclk_cpu, PCLK_TIMER0);
-GATE_CLK(pclk_timer2, pclk_cpu, PCLK_TIMER2);
-GATE_CLK(i2c0, pclk_cpu, PCLK_I2C0);
-GATE_CLK(i2c1, pclk_cpu, PCLK_I2C1);
-GATE_CLK(gpio0, pclk_cpu, PCLK_GPIO0);
-GATE_CLK(gpio1, pclk_cpu, PCLK_GPIO1);
-GATE_CLK(gpio2, pclk_cpu, PCLK_GPIO2);
-GATE_CLK(efuse, pclk_cpu, PCLK_EFUSE);
-GATE_CLK(tzpc, pclk_cpu, PCLK_TZPC);
-GATE_CLK(pclk_ddrupctl, pclk_cpu, PCLK_DDRUPCTL);
-GATE_CLK(pclk_ddrpubl, pclk_cpu, PCLK_PUBL);
-GATE_CLK(dbg, pclk_cpu, PCLK_DBG);
-GATE_CLK(grf, pclk_cpu, PCLK_GRF);
-GATE_CLK(pmu, pclk_cpu, PCLK_PMU);
-
-/*************************aclk_periph***********************/
-
-GATE_CLK(dma2, aclk_periph, ACLK_DMAC2);
-GATE_CLK(aclk_smc, aclk_periph, ACLK_SMC);
-GATE_CLK(aclk_gps, aclk_periph, ACLK_GPS);
-GATE_CLK(aclk_peri_niu, aclk_periph, ACLK_PEI_NIU);
-GATE_CLK(aclk_cpu_peri, aclk_periph, ACLK_CPU_PERI);
-GATE_CLK(aclk_peri_axi_matrix, aclk_periph, ACLK_PERI_AXI_MATRIX);
-
-/*************************hclk_periph***********************/
-GATE_CLK(hclk_peri_axi_matrix, hclk_periph, HCLK_PERI_AXI_MATRIX);
-GATE_CLK(hclk_peri_ahb_arbi, hclk_periph, HCLK_PERI_AHB_ARBI);
-GATE_CLK(hclk_emem_peri, hclk_periph, HCLK_EMEM_PERI);
-GATE_CLK(hclk_mac, hclk_periph, HCLK_EMAC);
-GATE_CLK(nandc, hclk_periph, HCLK_NANDC);
-GATE_CLK(hclk_usb_peri, hclk_periph, HCLK_USB_PERI);
-GATE_CLK(hclk_otg0, clk_hclk_usb_peri, HCLK_OTG0);
-GATE_CLK(hclk_otg1, clk_hclk_usb_peri, HCLK_OTG1);
-GATE_CLK(hclk_hsic, hclk_periph, HCLK_HSIC);
-GATE_CLK(hclk_hsadc, hclk_periph, HCLK_HSADC);
-GATE_CLK(hclk_pidfilter, hclk_periph, HCLK_PIDF);
-GATE_CLK(hclk_sdmmc, hclk_periph, HCLK_SDMMC0);
-GATE_CLK(hclk_sdio, hclk_periph, HCLK_SDIO);
-GATE_CLK(hclk_emmc, hclk_periph, HCLK_EMMC);
-/*************************pclk_periph***********************/
-GATE_CLK(pclk_peri_axi_matrix, pclk_periph, PCLK_PERI_AXI_MATRIX);
-GATE_CLK(pwm23, pclk_periph, PCLK_PWM23);
-GATE_CLK(wdt, pclk_periph, PCLK_WDT);
-GATE_CLK(pclk_spi0, pclk_periph, PCLK_SPI0);
-GATE_CLK(pclk_spi1, pclk_periph, PCLK_SPI1);
-GATE_CLK(pclk_uart2, pclk_periph, PCLK_UART2);
-GATE_CLK(pclk_uart3, pclk_periph, PCLK_UART3);
-GATE_CLK(i2c2, pclk_periph, PCLK_I2C2);
-GATE_CLK(i2c3, pclk_periph, PCLK_I2C3);
-GATE_CLK(i2c4, pclk_periph, PCLK_I2C4);
-GATE_CLK(gpio3, pclk_periph, PCLK_GPIO3);
-GATE_CLK(pclk_saradc, pclk_periph, PCLK_SARADC);
-/*************************aclk_lcdc0***********************/
-
-GATE_CLK(aclk_vio0, aclk_lcdc0_pre, ACLK_VIO0);
-GATE_CLK(aclk_lcdc0, clk_aclk_vio0, ACLK_LCDC0);
-GATE_CLK(aclk_cif0, clk_aclk_vio0, ACLK_CIF0);
-GATE_CLK(aclk_ipp, clk_aclk_vio0, ACLK_IPP);
-
-/*************************aclk_lcdc0***********************/
-
-GATE_CLK(aclk_vio1, aclk_lcdc1_pre, ACLK_VIO1);
-GATE_CLK(aclk_lcdc1, clk_aclk_vio1, ACLK_LCDC1);
-GATE_CLK(aclk_rga, clk_aclk_vio1, ACLK_RGA);
-
-
-#if 1
-#define CLK(dev, con, ck) \
-{\
- .dev_id = dev,\
- .con_id = con,\
- .clk = ck,\
-}
-
-
-#define CLK1(name) \
-{\
- .dev_id = NULL,\
- .con_id = #name,\
- .clk = &clk_##name,\
-}
-
-#endif
-
-static struct clk_lookup clks[] = {
- CLK(NULL, "xin24m", &xin24m),
- //CLK(NULL, "xin27m", &xin27m),
- CLK(NULL, "xin12m", &clk_12m),
- CLK(NULL, "arm_pll", &arm_pll_clk),
- CLK(NULL, "ddr_pll", &ddr_pll_clk),
- CLK(NULL, "codec_pll", &codec_pll_clk),
- CLK(NULL, "general_pll", &general_pll_clk),
-
- CLK(NULL, "arm_gpll", &clk_core_gpll_path),
- CLK(NULL, "ddr_gpll", &clk_ddr_gpll_path),
-
- CLK(NULL, "ddr", &clk_ddr),
- CLK(NULL, "cpu", &clk_core),
- CLK1(l2c),
- CLK1(core_dbg),
- CLK("smp_twd", NULL, &core_periph),
- CLK(NULL, "aclk_core", &aclk_core),
-
- CLK(NULL, "logic", &clk_cpu_div),
- CLK(NULL, "aclk_cpu", &aclk_cpu),
- CLK(NULL, "pclk_cpu", &pclk_cpu),
- CLK(NULL, "atclk_cpu", &atclk_cpu),
- CLK(NULL, "hclk_cpu", &hclk_cpu),
- CLK(NULL, "ahb2apb_cpu", &ahb2apb_cpu),
-
- CLK(NULL, "gpu", &aclk_gpu),
-
- CLK(NULL, "aclk_vepu", &aclk_vepu),
- CLK(NULL, "hclk_vepu", &hclk_vepu),
- CLK(NULL, "aclk_vdpu", &aclk_vdpu),
- CLK(NULL, "hclk_vdpu", &hclk_vdpu),
-
- CLK(NULL, "aclk_lcdc0_pre", &aclk_lcdc0_pre),
- CLK(NULL, "aclk_lcdc1_pre", &aclk_lcdc1_pre),
-
- CLK(NULL, "aclk_periph", &aclk_periph),
- CLK(NULL, "pclk_periph", &pclk_periph),
- CLK(NULL, "hclk_periph", &hclk_periph),
-
- CLK(NULL, "dclk_lcdc0", &dclk_lcdc0),
- CLK(NULL, "dclk_lcdc1", &dclk_lcdc1),
-
- CLK(NULL, "cif_out_pll", &cif_out_pll),
- CLK(NULL, "cif0_out_div", &cif0_out_div),
- CLK(NULL, "cif0_out", &cif0_out),
-
- CLK(NULL, "pclkin_cif0", &pclkin_cif0),
- CLK(NULL, "inv_cif0", &inv_cif0),
- CLK(NULL, "cif0_in", &cif0_in),
-
- CLK1(i2s_pll),
- CLK("rk29_i2s.0", "i2s_div", &clk_i2s0_div),
- CLK("rk29_i2s.0", "i2s_frac_div", &clk_i2s0_frac_div),
- CLK("rk29_i2s.0", "i2s", &clk_i2s0),
-
- // actually no i2s1
- CLK("rk29_i2s.1", "i2s_div", &clk_i2s0_div),
- CLK("rk29_i2s.1", "i2s_frac_div", &clk_i2s0_frac_div),
- CLK("rk29_i2s.1", "i2s", &clk_i2s0),
-
-
- CLK1(spdif_div),
- CLK1(spdif_frac_div),
- CLK1(spdif),
-
- CLK1(otgphy0),
- CLK1(otgphy1),
- CLK1(otgphy0_480m),
- CLK1(otgphy1_480m),
- CLK1(hsicphy_480m),
- CLK1(hsicphy_12m),
-
- CLK(NULL, "rmii_clkin", &rmii_clkin),
- CLK(NULL, "mac_ref_div", &clk_mac_pll_div), // compatible with rk29
- CLK1(mac_ref),
- CLK1(mii_tx),
-
- CLK1(hsadc_pll_div),
- CLK1(hsadc_frac_div),
- CLK1(hsadc_ext),
- CLK1(hsadc_out),
- CLK1(hsadc_out_inv),
- CLK1(hsadc),
-
- CLK1(saradc),
-
- CLK1(smc),
- CLK(NULL, "smc_inv", &clkn_smc),
-
- CLK("rk29xx_spim.0", "spi", &clk_spi0),
- CLK("rk29xx_spim.1", "spi", &clk_spi1),
-
- CLK("rk29_sdmmc.0", "mmc", &clk_sdmmc),
- CLK("rk29_sdmmc.1", "mmc", &clk_sdio),
- CLK1(emmc),
-
- CLK1(uart_pll),
- CLK("rk_serial.0", "uart_div", &clk_uart0_div),
- CLK("rk_serial.0", "uart_frac_div", &clk_uart0_frac_div),
- CLK("rk_serial.0", "uart", &clk_uart0),
- CLK("rk_serial.1", "uart_div", &clk_uart1_div),
- CLK("rk_serial.1", "uart_frac_div", &clk_uart1_frac_div),
- CLK("rk_serial.1", "uart", &clk_uart1),
- CLK("rk_serial.2", "uart_div", &clk_uart2_div),
- CLK("rk_serial.2", "uart_frac_div", &clk_uart2_frac_div),
- CLK("rk_serial.2", "uart", &clk_uart2),
- CLK("rk_serial.3", "uart_div", &clk_uart3_div),
- CLK("rk_serial.3", "uart_frac_div", &clk_uart3_frac_div),
- CLK("rk_serial.3", "uart", &clk_uart3),
-
- CLK1(timer0),
- CLK1(timer1),
- CLK1(timer2),
- CLK1(timer3),
- CLK1(timer4),
- CLK1(timer5),
- CLK1(timer6),
-
- /*************************aclk_cpu***********************/
- CLK1(dma1),
- CLK1(intmem),
- CLK1(aclk_strc_sys),
-
- /*************************hclk_cpu***********************/
- CLK1(rom),
- CLK("rk29_i2s.0", "hclk_i2s", &clk_hclk_i2s0_2ch),
- // actually no i2s1
- CLK("rk29_i2s.1", "hclk_i2s", &clk_hclk_i2s0_2ch),
- CLK1(hclk_spdif),
- CLK1(hclk_cpubus),
- CLK1(hclk_ahb2apb),
- CLK1(hclk_vio_bus),
- CLK1(hclk_lcdc0),
- CLK1(hclk_lcdc1),
- CLK1(hclk_cif0),
- CLK1(hclk_ipp),
- CLK1(hclk_rga),
- CLK1(hclk_imem0),
- CLK1(hclk_imem1),
-
- /*************************pclk_cpu***********************/
- CLK1(pwm01),
- CLK1(pclk_timer0),
- CLK1(pclk_timer2),
- CLK("rk30_i2c.0", "i2c", &clk_i2c0),
- CLK("rk30_i2c.1", "i2c", &clk_i2c1),
- CLK1(gpio0),
- CLK1(gpio1),
- CLK1(gpio2),
- CLK1(efuse),
- CLK1(tzpc),
- CLK("rk_serial.0", "pclk_uart", &clk_pclk_uart0),
- CLK("rk_serial.1", "pclk_uart", &clk_pclk_uart1),
- CLK1(pclk_ddrupctl),
- CLK1(pclk_ddrpubl),
- CLK1(dbg),
- CLK1(grf),
- CLK1(pmu),
-
- /*************************aclk_periph***********************/
- CLK1(dma2),
- CLK1(aclk_smc),
- CLK1(aclk_gps),
- CLK1(aclk_peri_niu),
- CLK1(aclk_cpu_peri),
- CLK1(aclk_peri_axi_matrix),
-
- /*************************hclk_periph***********************/
- CLK1(hclk_peri_axi_matrix),
- CLK1(hclk_peri_ahb_arbi),
- CLK1(hclk_emem_peri),
- CLK1(hclk_mac),
- CLK1(nandc),
- CLK1(hclk_usb_peri),
- CLK1(hclk_otg0),
- CLK1(hclk_otg1),
- CLK1(hclk_hsic),
- CLK1(hclk_hsadc),
- CLK1(hclk_pidfilter),
- CLK("rk29_sdmmc.0", "hclk_mmc", &clk_hclk_sdmmc),
- CLK("rk29_sdmmc.1", "hclk_mmc", &clk_hclk_sdio),
- CLK1(hclk_emmc),
-
- /*************************pclk_periph***********************/
- CLK1(pclk_peri_axi_matrix),
- CLK1(pwm23),
- CLK1(wdt),
- CLK("rk29xx_spim.0", "pclk_spi", &clk_pclk_spi0),
- CLK("rk29xx_spim.1", "pclk_spi", &clk_pclk_spi1),
- CLK("rk_serial.2", "pclk_uart", &clk_pclk_uart2),
- CLK("rk_serial.3", "pclk_uart", &clk_pclk_uart3),
- CLK("rk30_i2c.2", "i2c", &clk_i2c2),
- CLK("rk30_i2c.3", "i2c", &clk_i2c3),
- CLK("rk30_i2c.4", "i2c", &clk_i2c4),
- CLK1(gpio3),
- CLK1(pclk_saradc),
-
- /*************************aclk_lcdc0***********************/
- CLK1(aclk_vio0),
- CLK(NULL, "aclk_lcdc0", &clk_aclk_lcdc0),
- CLK1(aclk_cif0),
- CLK1(aclk_ipp),
-
- /*************************aclk_lcdc1***********************/
- CLK1(aclk_vio1),
- CLK(NULL, "aclk_lcdc1", &clk_aclk_lcdc1),
- CLK1(aclk_rga),
- /************************power domain**********************/
-
- PD_CLK(pd_peri),
- PD_CLK(pd_display),
- PD_CLK(pd_lcdc0),
- PD_CLK(pd_lcdc1),
- PD_CLK(pd_cif0),
- //PD_CLK(pd_cif1),
- PD_CLK(pd_rga),
- PD_CLK(pd_ipp),
- //PD_CLK(pd_video),
- PD_CLK(pd_gpu),
- //PD_CLK(pd_dbg),
-};
-static void __init rk30_init_enable_clocks(void)
-{
- #if 0
- //clk_enable_nolock(&xin24m);
- //clk_enable_nolock(&clk_12m);
- //clk_enable_nolock(&arm_pll_clk);
- //clk_enable_nolock(&ddr_pll_clk);
- //clk_enable_nolock(&codec_pll_clk);
- //clk_enable_nolock(&general_pll_clk);
- #endif
- clk_enable_nolock(&clk_ddr);
- //clk_enable_nolock(&clk_core);
- clk_enable_nolock(&clk_cpu_div);
- clk_enable_nolock(&clk_core_gpll_path);
- clk_enable_nolock(&clk_ddr_gpll_path);
- clk_enable_nolock(&clk_l2c);
- clk_enable_nolock(&clk_core_dbg);
- clk_enable_nolock(&core_periph);
- clk_enable_nolock(&aclk_core);
- //clk_enable_nolock(&aclk_cpu);
- //clk_enable_nolock(&pclk_cpu);
- clk_enable_nolock(&atclk_cpu);
- //clk_enable_nolock(&hclk_cpu);
- clk_enable_nolock(&ahb2apb_cpu);
- if (flag_uboot_display) {
- clk_enable_nolock(&dclk_lcdc0);
- clk_enable_nolock(&dclk_lcdc1);
- clk_enable_nolock(&clk_hclk_lcdc0);
- clk_enable_nolock(&clk_hclk_lcdc1);
- clk_enable_nolock(&clk_aclk_lcdc0);
- clk_enable_nolock(&clk_aclk_lcdc1);
- clk_enable_nolock(&aclk_lcdc0_pre);
- clk_enable_nolock(&aclk_lcdc1_pre);
- clk_enable_nolock(&pd_lcdc0);
- clk_enable_nolock(&pd_lcdc1);
- }
- #if 0
- clk_enable_nolock(&clk_gpu);
- clk_enable_nolock(&aclk_gpu);
- clk_enable_nolock(&aclk_gpu_slv);
- clk_enable_nolock(&aclk_gpu_mst);
-
- clk_enable_nolock(&aclk_vepu);
- clk_enable_nolock(&hclk_vepu);
- clk_enable_nolock(&aclk_vdpu);
- clk_enable_nolock(&hclk_vdpu);
-
-
- clk_enable_nolock(&aclk_periph);
- clk_enable_nolock(&pclk_periph);
- clk_enable_nolock(&hclk_periph);
- #endif
- #if 0
- clk_enable_nolock(&cif_out_pll);
- clk_enable_nolock(&cif0_out_div);
-
- clk_enable_nolock(&cif0_out);
- clk_enable_nolock(&pclkin_cif0);
- clk_enable_nolock(&inv_cif0);
- clk_enable_nolock(&cif0_in);
-
- clk_enable_nolock(&clk_i2s_pll);
- clk_enable_nolock(&clk_i2s0_div);
- clk_enable_nolock(&clk_i2s0_frac_div);
- clk_enable_nolock(&clk_i2s0);
-
- actually no i2s1
- clk_enable_nolock(&clk_i2s0_div);
- clk_enable_nolock(&clk_i2s0_frac_div);
- clk_enable_nolock(&clk_i2s0);
-
- clk_enable_nolock(&clk_spdif_div);
- clk_enable_nolock(&clk_spdif_frac_div);
- clk_enable_nolock(&clk_spdif);
- #endif
- #if 0
- clk_enable_nolock(&clk_otgphy0);
- clk_enable_nolock(&clk_otgphy1);
- clk_enable_nolock(&clk_otgphy0_480m);
- clk_enable_nolock(&clk_otgphy1_480m);
- clk_enable_nolock(&clk_hsicphy_480m);
- clk_enable_nolock(&clk_hsicphy_12m);
- #endif
-
- #if 0
- clk_enable_nolock(&rmii_clkin);
- clk_enable_nolock(&clk_mac_pll_div); // compatible with rk29
- clk_enable_nolock(&clk_mac_ref);
- clk_enable_nolock(&clk_mii_tx);
- #endif
-
- #if 0
- clk_enable_nolock(&clk_hsadc_pll_div);
- clk_enable_nolock(&clk_hsadc_frac_div);
- clk_enable_nolock(&clk_hsadc_ext);
- clk_enable_nolock(&clk_hsadc_out);
- clk_enable_nolock(&clk_hsadc_out_inv);
- clk_enable_nolock(&clk_hsadc);
-
- clk_enable_nolock(&clk_saradc);
- #endif
- /*
- clk_enable_nolock(&clk_smc);
- clk_enable_nolock(&clkn_smc);
- */
- /*
- clk_enable_nolock(&clk_spi0);
- clk_enable_nolock(&clk_spi1);
- */
- /*
- clk_enable_nolock(&clk_sdmmc);
- clk_enable_nolock(&clk_sdio);
- clk_enable_nolock(&clk_emmc);
- */
- #if 0
- clk_enable_nolock(&clk_uart_pll);
- clk_enable_nolock(&clk_uart0_div);
- clk_enable_nolock(&clk_uart0_frac_div);
- clk_enable_nolock(&clk_uart0);
- clk_enable_nolock(&clk_uart1_div);
- clk_enable_nolock(&clk_uart1_frac_div);
- clk_enable_nolock(&clk_uart1);
- clk_enable_nolock(&clk_uart2_div);
- clk_enable_nolock(&clk_uart2_frac_div);
- clk_enable_nolock(&clk_uart2);
- clk_enable_nolock(&clk_uart3_div);
- clk_enable_nolock(&clk_uart3_frac_div);
- clk_enable_nolock(&clk_uart3);
- #endif
- #if CONFIG_RK_DEBUG_UART == 0
- clk_enable_nolock(&clk_uart0);
- clk_enable_nolock(&clk_pclk_uart0);
- #elif CONFIG_RK_DEBUG_UART == 1
- clk_enable_nolock(&clk_uart1);
- clk_enable_nolock(&clk_pclk_uart1);
-
- #elif CONFIG_RK_DEBUG_UART == 2
- clk_enable_nolock(&clk_uart2);
- clk_enable_nolock(&clk_pclk_uart2);
-
- #elif CONFIG_RK_DEBUG_UART == 3
- clk_enable_nolock(&clk_uart3);
- clk_enable_nolock(&clk_pclk_uart3);
-
- #endif
- #if 0
- clk_enable_nolock(&clk_timer0);
- clk_enable_nolock(&clk_timer1);
- clk_enable_nolock(&clk_timer2);
- #endif
-
- /*************************aclk_cpu***********************/
- clk_enable_nolock(&clk_dma1);
- clk_enable_nolock(&clk_intmem);
- clk_enable_nolock(&clk_aclk_strc_sys);
-
- /*************************hclk_cpu***********************/
- clk_enable_nolock(&clk_rom);
- #if 0
- clk_enable_nolock(&clk_hclk_i2s0_2ch);
- // actually no i2s1
- clk_enable_nolock(&clk_hclk_i2s0_2ch);
- clk_enable_nolock(&clk_hclk_spdif);
- #endif
- clk_enable_nolock(&clk_hclk_cpubus);
- clk_enable_nolock(&clk_hclk_ahb2apb);
- clk_enable_nolock(&clk_hclk_vio_bus);
- #if 0
- clk_enable_nolock(&clk_hclk_cif0);
- clk_enable_nolock(&clk_hclk_ipp);
- clk_enable_nolock(&clk_hclk_rga);
- #endif
- clk_enable_nolock(&clk_hclk_imem0);
- clk_enable_nolock(&clk_hclk_imem1);
-
- /*************************pclk_cpu***********************/
- #if 0
- clk_enable_nolock(&clk_pwm01);
- clk_enable_nolock(&clk_pclk_timer0);
- clk_enable_nolock(&clk_pclk_timer1);
- clk_enable_nolock(&clk_pclk_timer2);
- clk_enable_nolock(&clk_i2c0);
- clk_enable_nolock(&clk_i2c1);
- clk_enable_nolock(&clk_gpio0);
- clk_enable_nolock(&clk_gpio1);
- clk_enable_nolock(&clk_gpio2);
- clk_enable_nolock(&clk_efuse);
- #endif
- clk_enable_nolock(&clk_tzpc);
- //clk_enable_nolock(&clk_pclk_uart0);
- //clk_enable_nolock(&clk_pclk_uart1);
- clk_enable_nolock(&clk_pclk_ddrupctl);
- clk_enable_nolock(&clk_pclk_ddrpubl);
- clk_enable_nolock(&clk_dbg);
- clk_enable_nolock(&clk_grf);
- clk_enable_nolock(&clk_pmu);
-
- /*************************aclk_periph***********************/
- clk_enable_nolock(&clk_dma2);
- clk_enable_nolock(&clk_aclk_smc);
- clk_enable_nolock(&clk_aclk_peri_niu);
- clk_enable_nolock(&clk_aclk_cpu_peri);
- clk_enable_nolock(&clk_aclk_peri_axi_matrix);
-
- /*************************hclk_periph***********************/
- clk_enable_nolock(&clk_hclk_peri_axi_matrix);
- clk_enable_nolock(&clk_hclk_peri_ahb_arbi);
- clk_enable_nolock(&clk_hclk_emem_peri);
- //clk_enable_nolock(&clk_hclk_mac);
- clk_enable_nolock(&clk_nandc);
- clk_enable_nolock(&clk_hclk_usb_peri);
- #if 0
- clk_enable_nolock(&clk_hclk_otg0);
- clk_enable_nolock(&clk_hclk_otg1);
- clk_enable_nolock(&clk_hclk_hsic);
- clk_enable_nolock(&clk_hclk_gps);
- clk_enable_nolock(&clk_hclk_hsadc);
- clk_enable_nolock(&clk_hclk_pidfilter);
- clk_enable_nolock(&clk_hclk_sdmmc);
- clk_enable_nolock(&clk_hclk_sdio);
- clk_enable_nolock(&clk_hclk_emmc);
- #endif
-
- /*************************pclk_periph***********************/
- clk_enable_nolock(&clk_pclk_peri_axi_matrix);
- #if 0
- clk_enable_nolock(&clk_pwm23);
- clk_enable_nolock(&clk_wdt);
- clk_enable_nolock(&clk_pclk_spi0);
- clk_enable_nolock(&clk_pclk_spi1);
- clk_enable_nolock(&clk_pclk_uart2);
- clk_enable_nolock(&clk_pclk_uart3);
- #endif
- #if 0
- clk_enable_nolock(&clk_i2c2);
- clk_enable_nolock(&clk_i2c3);
- clk_enable_nolock(&clk_i2c4);
- clk_enable_nolock(&clk_gpio3);
- clk_enable_nolock(&clk_pclk_saradc);
- #endif
- /*************************aclk_lcdc0***********************/
-#if 1
- //clk_enable_nolock(&clk_aclk_vio0);
- //clk_enable_nolock(&clk_aclk_cif0);
- //clk_enable_nolock(&clk_aclk_ipp);
-#endif
- /*************************aclk_lcdc1***********************/
-#if 1
- //clk_enable_nolock(&clk_aclk_vio1);
- //clk_enable_nolock(&clk_aclk_rga);
-#endif
- /************************power domain**********************/
-
-}
-static void periph_clk_set_init(void)
-{
- unsigned long aclk_p, hclk_p, pclk_p;
- unsigned long ppll_rate = general_pll_clk.rate;
- //aclk 148.5
-
- /* general pll */
- switch (ppll_rate) {
- case 148500 * KHZ:
- aclk_p = 148500 * KHZ;
- hclk_p = aclk_p >> 1;
- pclk_p = aclk_p >> 2;
- break;
- case 297 * MHZ:
- aclk_p = ppll_rate >> 1;
- hclk_p = aclk_p >> 0;
- pclk_p = aclk_p >> 1;
- break;
- case 300 * MHZ:
- aclk_p = ppll_rate >> 1;
- hclk_p = aclk_p >> 0;
- pclk_p = aclk_p >> 1;
- break;
- case 384 * MHZ:
- aclk_p = ppll_rate >> 1;
- hclk_p = aclk_p >> 1;
- pclk_p = aclk_p >> 2;
- break;
- case 594 * MHZ:
- aclk_p = ppll_rate >> 2;
- hclk_p = aclk_p >> 0;
- pclk_p = aclk_p >> 1;
- break;
- case 768 * MHZ:
- aclk_p = ppll_rate >> 2;
- hclk_p = aclk_p >> 1;
- pclk_p = aclk_p >> 2;
- break;
- case 891 * MHZ:
- aclk_p = ppll_rate / 6;
- hclk_p = aclk_p >> 0;
- pclk_p = aclk_p >> 1;
- break;
- case 1188 * MHZ:
- aclk_p = ppll_rate >> 3;
- hclk_p = aclk_p >> 0;
- pclk_p = aclk_p >> 1;
- break;
-
- default:
- aclk_p = 150 * MHZ;
- hclk_p = 150 * MHZ;
- pclk_p = 75 * MHZ;
- break;
- }
- clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
- clk_set_rate_nolock(&aclk_periph, aclk_p);
- clk_set_rate_nolock(&hclk_periph, hclk_p);
- clk_set_rate_nolock(&pclk_periph, pclk_p);
-}
-
-static void cpu_axi_init(void)
-{
- unsigned long cpu_div_rate = 0, aclk_cpu_rate = 0, hclk_cpu_rate = 0,
- pclk_cpu_rate = 0, ahb2apb_cpu_rate = 0;
- unsigned long gpll_rate = general_pll_clk.rate;
-
- switch (gpll_rate) {
- case 297 * MHZ:
- cpu_div_rate = gpll_rate;
- aclk_cpu_rate = cpu_div_rate >> 0;
- hclk_cpu_rate = aclk_cpu_rate >> 1;
- pclk_cpu_rate = aclk_cpu_rate >> 2;
- break;
-
- case 384 * MHZ:
- cpu_div_rate = gpll_rate >> 1;
- aclk_cpu_rate = cpu_div_rate >> 0;
- hclk_cpu_rate = aclk_cpu_rate >> 1;
- pclk_cpu_rate = aclk_cpu_rate >> 2;
- break;
-
- case 594 * MHZ:
- cpu_div_rate = gpll_rate >> 1;
- aclk_cpu_rate = cpu_div_rate >> 0;
- hclk_cpu_rate = aclk_cpu_rate >> 1;
- pclk_cpu_rate = aclk_cpu_rate >> 2;
- break;
-
- case 768 * MHZ:
- cpu_div_rate = gpll_rate >> 2;
- aclk_cpu_rate = cpu_div_rate >> 0;
- hclk_cpu_rate = aclk_cpu_rate >> 1;
- pclk_cpu_rate = aclk_cpu_rate >> 2;
- break;
-
- case 891 * MHZ:
- cpu_div_rate = gpll_rate / 3;
- aclk_cpu_rate = cpu_div_rate >> 0;
- hclk_cpu_rate = aclk_cpu_rate >> 1;
- pclk_cpu_rate = aclk_cpu_rate >> 2;
- break;
-
- case 1188 * MHZ:
- cpu_div_rate = gpll_rate >> 2;
- aclk_cpu_rate = cpu_div_rate >> 0;
- hclk_cpu_rate = aclk_cpu_rate >> 1;
- pclk_cpu_rate = aclk_cpu_rate >> 2;
- break;
-
- default:
- cpu_div_rate = 150 * MHZ;
- aclk_cpu_rate = 150 * MHZ;
- hclk_cpu_rate = 150 * MHZ;
- pclk_cpu_rate = 75 * MHZ;
- break;
- }
- ahb2apb_cpu_rate = pclk_cpu_rate;
-
- clk_set_parent_nolock(&clk_cpu_div, &general_pll_clk);
- clk_set_rate_nolock(&clk_cpu_div, cpu_div_rate);
- clk_set_rate_nolock(&aclk_cpu, aclk_cpu_rate);
- clk_set_rate_nolock(&hclk_cpu, hclk_cpu_rate);
- clk_set_rate_nolock(&pclk_cpu, pclk_cpu_rate);
- clk_set_rate_nolock(&ahb2apb_cpu, ahb2apb_cpu_rate);
-}
-
-void rk30_clock_common_i2s_init(void)
-{
- unsigned long i2s_rate;
- //20 times
- if(rk30_clock_flags & CLK_FLG_MAX_I2S_49152KHZ) {
- i2s_rate = 49152000;
- } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_24576KHZ) {
- i2s_rate = 24576000;
- } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_22579_2KHZ) {
- i2s_rate = 22579000;
- } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_12288KHZ) {
- i2s_rate = 12288000;
- } else {
- i2s_rate = 49152000;
- }
-
- /*
- * Priority setting i2s under cpll to fix i2s frac div do not effect, let
- * axi_cpu's pll different with i2s's
- * */
- if(((i2s_rate * 20) <= codec_pll_clk.rate) || !(codec_pll_clk.rate % i2s_rate)) {
- clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
- } else if(((i2s_rate * 20) <= general_pll_clk.rate) || !(general_pll_clk.rate % i2s_rate)) {
- clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
- } else {
- if(general_pll_clk.rate > codec_pll_clk.rate)
- clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
- else
- clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
- }
-}
-void rk30_clock_common_uart_init(struct clk *cpll_clk,struct clk *gpll_clk)
-{
- struct clk *p_clk;
- unsigned long rate;
- if(!(gpll_clk->rate%(48*MHZ)))
- {
- p_clk=gpll_clk;
- rate=48*MHZ;
- }
- else if(!(cpll_clk->rate%(48*MHZ)))
- {
- p_clk=cpll_clk;
- rate=48*MHZ;
- }
- else if(!(gpll_clk->rate%(49500*KHZ)))
- {
- p_clk=gpll_clk;
- rate=(49500*KHZ);
- }
- else if(!(cpll_clk->rate%(49500*KHZ)))
- {
- p_clk=cpll_clk;
- rate=(49500*KHZ);
- }
- else
- {
- if(cpll_clk->rate>gpll_clk->rate)
- {
- p_clk=cpll_clk;
- }
- else
- {
- p_clk=gpll_clk;
- }
- rate=50*MHZ;
- }
- clk_set_parent_nolock(&clk_uart_pll, p_clk);
- clk_set_rate_nolock(&clk_uart0_div,rate);
- clk_set_rate_nolock(&clk_uart1_div,rate);
- clk_set_rate_nolock(&clk_uart2_div,rate);
- clk_set_rate_nolock(&clk_uart3_div,rate);
-}
-
-static void inline clock_set_div(struct clk *clk,u32 div)
-{
- set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
-}
-
-static void inline clock_set_max_div(struct clk *clk)
-{
- set_cru_bits_w_msk(clk->div_max - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
-}
-
-static void div_clk_for_pll_init(void)
-{
- clock_set_max_div(&clk_cpu_div);
- clock_set_max_div(&aclk_vdpu);
- clock_set_max_div(&aclk_vepu);
- clock_set_max_div(&aclk_gpu);
- if (!flag_uboot_display) {
- clock_set_max_div(&aclk_lcdc0_pre);
- clock_set_max_div(&aclk_lcdc1_pre);
- clock_set_max_div(&dclk_lcdc0);
- clock_set_max_div(&dclk_lcdc1);
- }
- clock_set_max_div(&aclk_periph);
- clock_set_max_div(&cif0_out_div);
- clock_set_max_div(&clk_i2s0_div);
- clock_set_max_div(&clk_spdif_div);
- clock_set_max_div(&clk_uart0_div);
- clock_set_max_div(&clk_uart1_div);
- clock_set_max_div(&clk_uart2_div);
- clock_set_max_div(&clk_uart3_div);
- clock_set_max_div(&clk_hsicphy_12m);
- clock_set_max_div(&clk_hsadc_pll_div);
- clock_set_max_div(&clk_saradc);
-}
-
-static u8 pll_flag = 0;
-
-static void __init rk30_clock_common_init(unsigned long gpll_rate, unsigned long cpll_rate)
-{
- //general
- if (!flag_uboot_display)
- clk_set_rate_nolock(&general_pll_clk, gpll_rate);
- lpj_gpll = CLK_LOOPS_RECALC(general_pll_clk.rate);
-
- //code pll
- if (!flag_uboot_display)
- clk_set_rate_nolock(&codec_pll_clk, cpll_rate);
-
- cpu_axi_init();
- clk_set_rate_nolock(&clk_core, 792 * MHZ);
- //periph clk
- periph_clk_set_init();
-
- //i2s
- rk30_clock_common_i2s_init();
-
- // spi
- clk_set_rate_nolock(&clk_spi0, clk_spi0.parent->rate);
- clk_set_rate_nolock(&clk_spi1, clk_spi1.parent->rate);
-
- // uart
- rk30_clock_common_uart_init(&codec_pll_clk,&general_pll_clk);
-
- //mac
- if(!(gpll_rate % (50 * MHZ))) {
- clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
-
- } else if((!(ddr_pll_clk.rate % (50 * MHZ))) && (ddr_pll_clk.rate != 24 * MHZ) && ((pll_flag & 0x2) == 0)) {
- clk_set_parent_nolock(&clk_mac_pll_div, &ddr_pll_clk);
-
- } else {
- CLKDATA_DBG("mac can't get 50mhz, set to gpll\n");
- clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
- }
-
- //hsadc
- //auto pll sel
- //clk_set_parent_nolock(&clk_hsadc_pll_div, &general_pll_clk);
-
- if (!flag_uboot_display) {
- //lcdc0 lcd auto sel pll
- clk_set_parent_nolock(&dclk_lcdc0, &general_pll_clk);
- clk_set_parent_nolock(&dclk_lcdc1, &general_pll_clk);
-
- //axi lcdc auto sel
- clk_set_parent_nolock(&aclk_lcdc0_pre, &general_pll_clk);
- clk_set_parent_nolock(&aclk_lcdc1_pre, &general_pll_clk);
- clk_set_rate_nolock(&aclk_lcdc0_pre, 300 * MHZ);
- clk_set_rate_nolock(&aclk_lcdc1_pre, 300 * MHZ);
- }
- //cif
- clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
-
- //axi vepu auto sel
- //clk_set_parent_nolock(&aclk_vepu, &general_pll_clk);
- //clk_set_parent_nolock(&aclk_vdpu, &general_pll_clk);
-
- clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
- clk_set_rate_nolock(&aclk_vdpu, 300 * MHZ);
- //gpu auto sel
- clk_set_parent_nolock(&aclk_gpu, &general_pll_clk);
- clk_set_rate_nolock(&aclk_gpu, 200 * MHZ);
-
- if (0 == pll_flag) {
- clk_set_rate_nolock(&clk_uart0, 48000000);
- } else {
- clk_set_rate_nolock(&clk_uart0, 49500000);
- }
- clk_set_rate_nolock(&clk_sdmmc, 24750000);
- clk_set_rate_nolock(&clk_sdio, 24750000);
-}
-
-static struct clk def_ops_clk = {
- .get_parent = clksel_get_parent,
- .set_parent = clksel_set_parent,
-};
-
-#ifdef CONFIG_PROC_FS
-struct clk_dump_ops dump_ops;
-#endif
-void rk_dump_clock_info(void);
-void __init _rk30_clock_data_init(unsigned long gpll, unsigned long cpll, int flags)
-{
- struct clk_lookup *lk;
-
- if (soc_is_rk3188plus()) {
- arm_pll_clk.recalc = plus_plls_clk_recalc;
- ddr_pll_clk.recalc = plus_plls_clk_recalc;
- codec_pll_clk.recalc = plus_plls_clk_recalc;
- general_pll_clk.recalc = plus_plls_clk_recalc;
-
- arm_pll_clk.set_rate = plus_arm_pll_clk_set_rate;
- codec_pll_clk.set_rate = plus_cpll_clk_set_rate;
- general_pll_clk.set_rate = plus_gpll_clk_set_rate;
- }
-
- rk_efuse_init();
- pll_flag = rk_pll_flag();
- printk("CLKDATA_MSG: pll_flag = 0x%02x\n", pll_flag);
-
- if (0 != pll_flag) {
- CLKDATA_DBG("CPLL=%lu, GPLL=%lu;CPLL CAN NOT LOCK, SET CPLL BY PASS, USE GPLL REPLACE CPLL\n",
- cpll, gpll);
- codec_pll_clk.mode = NULL;
- cpll = 24 * MHZ;
- gpll = 891 * MHZ;
- }
-
- clk_register_dump_ops(&dump_ops);
- clk_register_default_ops_clk(&def_ops_clk);
- rk30_clock_flags = flags;
- for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) {
-#ifdef RK30_CLK_OFFBOARD_TEST
- rk30_clkdev_add(lk);
-#else
- clkdev_add(lk);
-#endif
- clk_register(lk->clk);
- }
-
- div_clk_for_pll_init();
- clk_recalculate_root_clocks_nolock();
-
- loops_per_jiffy = CLK_LOOPS_RECALC(arm_pll_clk.rate);
-
- /*
- * Only enable those clocks we will need, let the drivers
- * enable other clocks as necessary
- */
-
- rk30_init_enable_clocks();
-#if 0
- // print loader config
- CLKDATA_DBG("%s clks register dbg start\n", __func__);
- rk_dump_clock_info();
- rk30_clk_dump_regs();
-
- CLKDATA_DBG("%s clks register dbg end\n", __func__);
-#endif
- /*
- * Disable any unused clocks left on by the bootloader
- */
- //clk_disable_unused();
- rk30_clock_common_init(gpll, cpll);
- preset_lpj = loops_per_jiffy;
-
-
- //gpio6_b7
- //regfile_writel(0xc0004000,0x10c);
- //cru_writel(0x07000000,CRU_MISC_CON);
-
-}
-extern int rk3188_dvfs_init(void);
-
-void __init rk30_clock_data_init(unsigned long gpll, unsigned long cpll, u32 flags)
-{
- CLKDATA_DBG("clock: gpll %lu cpll %lu flags 0x%x con2 0x%x/0x%x\n",
- gpll, cpll, flags, cru_readl(PLL_CONS(DPLL_ID, 2)), cru_readl(PLL_CONS(CPLL_ID, 2)));
- _rk30_clock_data_init(gpll, cpll, flags);
- rk3188_dvfs_init();
-}
-#define STR_UBOOT_DISPLAY "fastboot"
-static int __init bootloader_setup(char *str)
-{
- if (0 == strncmp(str, STR_UBOOT_DISPLAY, strlen(STR_UBOOT_DISPLAY))) {
- printk("CLKDATA_MSG: get uboot display\n");
- flag_uboot_display = 1;
- }
- return 0;
-}
-early_param("androidboot.bootloader", bootloader_setup);
-
-int support_uboot_display(void)
-{
- return flag_uboot_display;
-}
-/*
- * You can override arm_clk rate with armclk= cmdline option.
- */
-static int __init armclk_setup(char *str)
-{
- get_option(&str, &armclk);
-
- if (!armclk)
- return 0;
- if (armclk < 10000)
- armclk *= MHZ;
- //clk_set_rate_nolock(&arm_pll_clk, armclk);
- return 0;
-}
-#ifndef RK30_CLK_OFFBOARD_TEST
-early_param("armclk", armclk_setup);
-#endif
-
-
-static void rk_dump_clock(struct clk *clk, int deep, const struct list_head *root_clocks)
-{
- struct clk *ck;
- int i;
- unsigned long rate = clk->rate;
- //CLKDATA_DBG("dump_clock %s\n",clk->name);
- for (i = 0; i < deep; i++)
- printk(" ");
-
- printk("%-11s ", clk->name);
-#ifndef RK30_CLK_OFFBOARD_TEST
- if (clk->flags & IS_PD) {
- printk("%s ", pmu_power_domain_is_on(clk->gate_idx) ? "on " : "off");
- }
-#endif
- if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
- int idx = clk->gate_idx;
- u32 v;
- v = cru_readl(CLK_GATE_CLKID_CONS(idx)) & ((0x1) << (idx % 16));
- printk("%s ", v ? "off" : "on ");
- }
-
- if (clk->pll) {
- u32 pll_mode;
- u32 pll_id = clk->pll->id;
- pll_mode = cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id);
- if (pll_mode == (PLL_MODE_SLOW(pll_id) & PLL_MODE_MSK(pll_id)))
- printk("slow ");
- else if (pll_mode == (PLL_MODE_NORM(pll_id) & PLL_MODE_MSK(pll_id)))
- printk("normal ");
- else if (pll_mode == (PLL_MODE_DEEP(pll_id) & PLL_MODE_MSK(pll_id)))
- printk("deep ");
-
- if(cru_readl(PLL_CONS(pll_id, 3)) & PLL_BYPASS)
- printk("bypass ");
- } else if(clk == &clk_ddr) {
- rate = clk->recalc(clk);
- }
-
- if (rate >= MHZ) {
- if (rate % MHZ)
- printk("%ld.%06ld MHz", rate / MHZ, rate % MHZ);
- else
- printk("%ld MHz", rate / MHZ);
- } else if (rate >= KHZ) {
- if (rate % KHZ)
- printk("%ld.%03ld KHz", rate / KHZ, rate % KHZ);
- else
- printk("%ld KHz", rate / KHZ);
- } else {
- printk("%ld Hz", rate);
- }
-
- printk(" usecount = %d", clk->usecount);
-
- if (clk->parent)
- printk(" parent = %s", clk->parent->name);
-
- printk("\n");
-
- list_for_each_entry(ck, root_clocks, node) {
- if (ck->parent == clk)
- rk_dump_clock(ck, deep + 1, root_clocks);
- }
-}
-
-#if 1
-struct list_head *get_rk_clocks_head(void);
-
-void rk_dump_clock_info(void)
-{
- struct clk* clk;
- list_for_each_entry(clk, get_rk_clocks_head(), node) {
- if (!clk->parent)
- rk_dump_clock(clk, 0,get_rk_clocks_head());
- }
-}
-#endif
-
-#ifdef CONFIG_PROC_FS
-
-static void dump_clock(struct seq_file *s, struct clk *clk, int deep, const struct list_head *root_clocks)
-{
- struct clk *ck;
- int i;
- unsigned long rate = clk->rate;
- //CLKDATA_DBG("dump_clock %s\n",clk->name);
- for (i = 0; i < deep; i++)
- seq_printf(s, " ");
-
- seq_printf(s, "%-11s ", clk->name);
-#ifndef RK30_CLK_OFFBOARD_TEST
- if (clk->flags & IS_PD) {
- seq_printf(s, "%s ", pmu_power_domain_is_on(clk->gate_idx) ? "on " : "off");
- }
-#endif
- if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
- int idx = clk->gate_idx;
- u32 v;
- v = cru_readl(CLK_GATE_CLKID_CONS(idx)) & ((0x1) << (idx % 16));
- seq_printf(s, "%s ", v ? "off" : "on ");
- }
-
- if (clk->pll) {
- u32 pll_mode;
- u32 pll_id = clk->pll->id;
- pll_mode = cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id);
- if (pll_mode == (PLL_MODE_SLOW(pll_id) & PLL_MODE_MSK(pll_id)))
- seq_printf(s, "slow ");
- else if (pll_mode == (PLL_MODE_NORM(pll_id) & PLL_MODE_MSK(pll_id)))
- seq_printf(s, "normal ");
- else if (pll_mode == (PLL_MODE_DEEP(pll_id) & PLL_MODE_MSK(pll_id)))
- seq_printf(s, "deep ");
-
- if(cru_readl(PLL_CONS(pll_id, 3)) & PLL_BYPASS)
- seq_printf(s, "bypass ");
- } else if(clk == &clk_ddr) {
- rate = clk->recalc(clk);
- }
-
- if (rate >= MHZ) {
- if (rate % MHZ)
- seq_printf(s, "%ld.%06ld MHz", rate / MHZ, rate % MHZ);
- else
- seq_printf(s, "%ld MHz", rate / MHZ);
- } else if (rate >= KHZ) {
- if (rate % KHZ)
- seq_printf(s, "%ld.%03ld KHz", rate / KHZ, rate % KHZ);
- else
- seq_printf(s, "%ld KHz", rate / KHZ);
- } else {
- seq_printf(s, "%ld Hz", rate);
- }
-
- seq_printf(s, " usecount = %d", clk->usecount);
-
- if (clk->parent)
- seq_printf(s, " parent = %s", clk->parent->name);
-
- if (clk->last_set_rate != 0)
- seq_printf(s, " [set %lu Hz]", clk->last_set_rate);
-
- seq_printf(s, "\n");
-
- list_for_each_entry(ck, root_clocks, node) {
- if (ck->parent == clk)
- dump_clock(s, ck, deep + 1, root_clocks);
- }
-}
-
-static void dump_regs(struct seq_file *s)
-{
- int i = 0;
- seq_printf(s, "\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
- seq_printf(s, "\nPLLRegisters:\n");
- for(i = 0; i < END_PLL_ID; i++) {
- seq_printf(s, "pll%d :cons:%x,%x,%x,%x\n", i,
- cru_readl(PLL_CONS(i, 0)),
- cru_readl(PLL_CONS(i, 1)),
- cru_readl(PLL_CONS(i, 2)),
- cru_readl(PLL_CONS(i, 3))
- );
- }
- seq_printf(s, "MODE :%x\n", cru_readl(CRU_MODE_CON));
-
- for(i = 0; i < CRU_CLKSELS_CON_CNT; i++) {
- seq_printf(s, "CLKSEL%d :%x\n", i, cru_readl(CRU_CLKSELS_CON(i)));
- }
- for(i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
- seq_printf(s, "CLKGATE%d :%x\n", i, cru_readl(CRU_CLKGATES_CON(i)));
- }
- seq_printf(s, "GLB_SRST_FST:%x\n", cru_readl(CRU_GLB_SRST_FST));
- seq_printf(s, "GLB_SRST_SND:%x\n", cru_readl(CRU_GLB_SRST_SND));
-
- for(i = 0; i < CRU_SOFTRSTS_CON_CNT; i++) {
- seq_printf(s, "CLKGATE%d :%x\n", i, cru_readl(CRU_SOFTRSTS_CON(i)));
- }
- seq_printf(s, "CRU MISC :%x\n", cru_readl(CRU_MISC_CON));
- seq_printf(s, "GLB_CNT_TH :%x\n", cru_readl(CRU_GLB_CNT_TH));
-
-}
-
-void rk30_clk_dump_regs(void)
-{
- int i = 0;
- printk("\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
- printk("\nPLLRegisters:\n");
- for(i = 0; i < END_PLL_ID; i++) {
- printk("pll%d :cons:%x,%x,%x,%x\n", i,
- cru_readl(PLL_CONS(i, 0)),
- cru_readl(PLL_CONS(i, 1)),
- cru_readl(PLL_CONS(i, 2)),
- cru_readl(PLL_CONS(i, 3))
- );
- }
- printk("MODE :%x\n", cru_readl(CRU_MODE_CON));
-
- for(i = 0; i < CRU_CLKSELS_CON_CNT; i++) {
- printk("CLKSEL%d :%x\n", i, cru_readl(CRU_CLKSELS_CON(i)));
- }
- for(i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
- printk("CLKGATE%d :%x\n", i, cru_readl(CRU_CLKGATES_CON(i)));
- }
- printk("GLB_SRST_FST:%x\n", cru_readl(CRU_GLB_SRST_FST));
- printk("GLB_SRST_SND:%x\n", cru_readl(CRU_GLB_SRST_SND));
-
- for(i = 0; i < CRU_SOFTRSTS_CON_CNT; i++) {
- printk("SOFTRST%d :%x\n", i, cru_readl(CRU_SOFTRSTS_CON(i)));
- }
- printk("CRU MISC :%x\n", cru_readl(CRU_MISC_CON));
- printk("GLB_CNT_TH :%x\n", cru_readl(CRU_GLB_CNT_TH));
-
-}
-
-
-#ifdef CONFIG_PROC_FS
-static void dump_clock(struct seq_file *s, struct clk *clk, int deep, const struct list_head *root_clocks);
-struct clk_dump_ops dump_ops = {
- .dump_clk = dump_clock,
- .dump_regs = dump_regs,
-};
-#endif
-
-
-#endif /* CONFIG_PROC_FS */
-
-
-
-
-#ifdef RK30_CLK_OFFBOARD_TEST
-struct clk *test_get_parent(struct clk *clk) {
- return clk->parent;
-}
-
-void i2s_test(void)
-{
- struct clk *i2s_clk = &clk_i2s0;
-
- clk_enable_nolock(i2s_clk);
-
- clk_set_rate_nolock(i2s_clk, 12288000);
- printk("int %s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
- clk_set_rate_nolock(i2s_clk, 297 * MHZ / 2);
- printk("int%s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
- clk_set_rate_nolock(i2s_clk, 12 * MHZ);
- printk("int%s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
-
-}
-
-void uart_test(void)
-{
- struct clk *uart_clk = &clk_uart0;
-
- clk_enable_nolock(uart_clk);
-
- clk_set_rate_nolock(uart_clk, 12288000);
- printk("int %s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
- clk_set_rate_nolock(uart_clk, 297 * MHZ / 2);
- printk("int%s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
- clk_set_rate_nolock(uart_clk, 12 * MHZ);
- printk("int%s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
-
-}
-void hsadc_test(void)
-{
- struct clk *hsadc_clk = &clk_hsadc;
-
- printk("******************hsadc_test**********************\n");
- clk_enable_nolock(hsadc_clk);
-
- clk_set_rate_nolock(hsadc_clk, 12288000);
- printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
-
-
- clk_set_rate_nolock(hsadc_clk, 297 * MHZ / 2);
- printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
-
- clk_set_rate_nolock(hsadc_clk, 300 * MHZ / 2);
-
- clk_set_rate_nolock(hsadc_clk, 296 * MHZ / 2);
-
- printk("******************hsadc out clock**********************\n");
-
- clk_set_parent_nolock(hsadc_clk, &clk_hsadc_ext);
- printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
- clk_set_rate_nolock(hsadc_clk, 297 * MHZ / 2);
- printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
-
-
-
-}
-
-static void __init rk30_clock_test_init(unsigned long ppll_rate)
-{
- //arm
- printk("*********arm_pll_clk***********\n");
- clk_set_rate_nolock(&arm_pll_clk, 816 * MHZ);
-
- printk("*********set clk_core parent***********\n");
- clk_set_parent_nolock(&clk_core, &arm_pll_clk);
- clk_set_rate_nolock(&clk_core, 504 * MHZ);
-
- //general
- printk("*********general_pll_clk***********\n");
- clk_set_rate_nolock(&general_pll_clk, ppll_rate);
-
- //code pll
- printk("*********codec_pll_clk***********\n");
- clk_set_rate_nolock(&codec_pll_clk, 600 * MHZ);
-
-
- printk("*********periph_clk_set_init***********\n");
- clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
- periph_clk_set_init();
-
-#if 0 //
- clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
-#else
- printk("*********clk i2s***********\n");
- clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
- printk("common %s parent is %s\n", clk_i2s_pll.name, test_get_parent(&clk_i2s_pll)->name);
- i2s_test();
-#endif
- // spi
- clk_enable_nolock(&clk_spi0);
- clk_set_rate_nolock(&clk_spi0, 30 * MHZ);
- printk("common %s parent is %s\n", clk_spi0.name, test_get_parent(&clk_spi0)->name);
- //saradc
- clk_enable_nolock(&clk_saradc);
- clk_set_rate_nolock(&clk_saradc, 6 * MHZ);
- printk("common %s parent is %s\n", clk_saradc.name, test_get_parent(&clk_saradc)->name);
- //sdio
- clk_enable_nolock(&clk_sdio);
- clk_set_rate_nolock(&clk_sdio, 50 * MHZ);
- printk("common %s parent is %s\n", clk_sdio.name, test_get_parent(&clk_sdio)->name);
- // uart
- clk_set_parent_nolock(&clk_uart_pll, &general_pll_clk);
- uart_test();
- //mac
- printk("*********mac***********\n");
-
- clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
- printk("common %s parent is %s\n", clk_mac_pll_div.name, test_get_parent(&clk_mac_pll_div)->name);
-
- //clk_set_parent_nolock(&clk_mac_ref, &clk_mac_pll_div);
- clk_set_rate_nolock(&clk_mac_ref, 50 * MHZ);
- printk("common %s parent is %s\n", clk_mac_ref.name, test_get_parent(&clk_mac_ref)->name);
-
- printk("*********mac mii set***********\n");
- clk_set_parent_nolock(&clk_mac_ref, &rmii_clkin);
- clk_set_rate_nolock(&clk_mac_ref, 20 * MHZ);
- printk("common %s parent is %s\n", clk_mac_ref.name, test_get_parent(&clk_mac_ref)->name);
- //hsadc
- printk("*********hsadc 1***********\n");
- //auto pll
- hsadc_test();
- //lcdc
- clk_enable_nolock(&dclk_lcdc0);
-
- clk_set_rate_nolock(&dclk_lcdc0, 60 * MHZ);
- clk_set_rate_nolock(&dclk_lcdc0, 27 * MHZ);
-
- //cif
- clk_enable_nolock(&cif0_out);
-
- clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
- printk("common %s parent is %s\n", cif_out_pll.name, test_get_parent(&cif_out_pll)->name);
-
- clk_set_rate_nolock(&cif0_out, 60 * MHZ);
- printk("common %s parent is %s\n", cif0_out.name, test_get_parent(&cif0_out)->name);
-
- clk_set_rate_nolock(&cif0_out, 24 * MHZ);
- printk("common %s parent is %s\n", cif0_out.name, test_get_parent(&cif0_out)->name);
- //cif_in
- clk_enable_nolock(&cif0_in);
- clk_set_rate_nolock(&cif0_in, 24 * MHZ);
- //axi lcdc
- clk_enable_nolock(&aclk_lcdc0);
- clk_set_rate_nolock(&aclk_lcdc0, 150 * MHZ);
- printk("common %s parent is %s\n", aclk_lcdc0.name, test_get_parent(&aclk_lcdc0)->name);
- //axi vepu
- clk_enable_nolock(&aclk_vepu);
- clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
- printk("common %s parent is %s\n", aclk_vepu.name, test_get_parent(&aclk_vepu)->name);
-
- clk_set_rate_nolock(&hclk_vepu, 300 * MHZ);
- printk("common %s parent is %s\n", hclk_vepu.name, test_get_parent(&hclk_vepu)->name);
-
- printk("test end\n");
-
- /* arm pll
- clk_set_rate_nolock(&arm_pll_clk, armclk);
- clk_set_rate_nolock(&clk_core, armclk);//pll:core =1:1
- */
- //
- //clk_set_rate_nolock(&codec_pll_clk, ppll_rate*2);
- //
- //clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
- //clk_set_rate_nolock(&clk_gpu, 300 * MHZ);
-
-}
-
-
-
-
-
-static LIST_HEAD(rk30_clocks);
-static DEFINE_MUTEX(rk30_clocks_mutex);
-
-static inline int __rk30clk_get(struct clk *clk)
-{
- return 1;
-}
-void rk30_clkdev_add(struct clk_lookup *cl)
-{
- mutex_lock(&rk30_clocks_mutex);
- list_add_tail(&cl->node, &rk30_clocks);
- mutex_unlock(&rk30_clocks_mutex);
-}
-static struct clk_lookup *rk30_clk_find(const char *dev_id, const char *con_id) {
- struct clk_lookup *p, *cl = NULL;
- int match, best = 0;
-
- list_for_each_entry(p, &rk30_clocks, node) {
- match = 0;
- if (p->dev_id) {
- if (!dev_id || strcmp(p->dev_id, dev_id))
- continue;
- match += 2;
- }
- if (p->con_id) {
- if (!con_id || strcmp(p->con_id, con_id))
- continue;
- match += 1;
- }
-
- if (match > best) {
- cl = p;
- if (match != 3)
- best = match;
- else
- break;
- }
- }
- return cl;
-}
-
-struct clk *rk30_clk_get_sys(const char *dev_id, const char *con_id) {
- struct clk_lookup *cl;
-
- mutex_lock(&rk30_clocks_mutex);
- cl = rk30_clk_find(dev_id, con_id);
- if (cl && !__rk30clk_get(cl->clk))
- cl = NULL;
- mutex_unlock(&rk30_clocks_mutex);
-
- return cl ? cl->clk : ERR_PTR(-ENOENT);
-}
-//EXPORT_SYMBOL(rk30_clk_get_sys);
-
-struct clk *rk30_clk_get(struct device *dev, const char *con_id) {
- const char *dev_id = dev ? dev_name(dev) : NULL;
- return rk30_clk_get_sys(dev_id, con_id);
-}
-//EXPORT_SYMBOL(rk30_clk_get);
-
-
-int rk30_clk_set_rate(struct clk *clk, unsigned long rate);
-
-void rk30_clocks_test(void)
-{
- struct clk *test_gpll;
- test_gpll = rk30_clk_get(NULL, "general_pll");
- if(test_gpll) {
- rk30_clk_set_rate(test_gpll, 297 * 2 * MHZ);
- printk("gpll rate=%lu\n", test_gpll->rate);
- }
- //while(1);
-}
-
-void __init rk30_clock_init_test(void)
-{
-
- rk30_clock_init(periph_pll_297mhz, codec_pll_360mhz, max_i2s_12288khz);
- //while(1);
-}
-
-
-#endif
-
-
+++ /dev/null
-/*
- * Copyright (C) 2013 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-//#define DEBUG 1
-#define pr_fmt(fmt) "cpufreq: " fmt
-#include <linux/clk.h>
-#include <linux/cpu.h>
-#include <linux/cpufreq.h>
-#include <linux/err.h>
-#include <linux/kernel_stat.h>
-#include <linux/init.h>
-#include <linux/reboot.h>
-#include <linux/suspend.h>
-#include <linux/tick.h>
-#include <linux/workqueue.h>
-#include <linux/delay.h>
-#include <linux/regulator/consumer.h>
-#include <linux/fs.h>
-#include <linux/miscdevice.h>
-#include <linux/string.h>
-#include <linux/earlysuspend.h>
-#include <asm/smp_plat.h>
-#include <asm/cpu.h>
-#include <asm/unistd.h>
-#include <asm/uaccess.h>
-#include <mach/cpu.h>
-#include <mach/ddr.h>
-#include <mach/dvfs.h>
-#include <plat/efuse.h>
-
-#define VERSION "2.2"
-
-#ifdef DEBUG
-#define FREQ_DBG(fmt, args...) pr_debug(fmt, ## args)
-#define FREQ_LOG(fmt, args...) pr_debug(fmt, ## args)
-#else
-#define FREQ_DBG(fmt, args...) do {} while(0)
-#define FREQ_LOG(fmt, args...) do {} while(0)
-#endif
-#define FREQ_ERR(fmt, args...) pr_err(fmt, ## args)
-
-/* Frequency table index must be sequential starting at 0 */
-static struct cpufreq_frequency_table default_freq_table[] = {
- {.frequency = 816 * 1000, .index = 1000 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-
-static struct cpufreq_frequency_table *freq_table = default_freq_table;
-
-/*********************************************************/
-
-/* additional symantics for "relation" in cpufreq with pm */
-#define DISABLE_FURTHER_CPUFREQ 0x10
-#define ENABLE_FURTHER_CPUFREQ 0x20
-#define MASK_FURTHER_CPUFREQ 0x30
-/* With 0x00(NOCHANGE), it depends on the previous "further" status */
-#define CPUFREQ_PRIVATE 0x100
-static int no_cpufreq_access;
-static unsigned int suspend_freq = 816 * 1000;
-#if defined(CONFIG_ARCH_RK3026)
-static unsigned int suspend_volt = 1100000; // 1.1V
-#else
-static unsigned int suspend_volt = 1000000; // 1V
-#endif
-static unsigned int low_battery_freq = 600 * 1000;
-static unsigned int low_battery_capacity = 5; // 5%
-static bool is_booting = true;
-
-static struct workqueue_struct *freq_wq;
-static struct clk *cpu_clk;
-
-static DEFINE_MUTEX(cpufreq_mutex);
-
-static struct clk *gpu_clk;
-static bool gpu_is_mali400;
-static struct clk *ddr_clk;
-
-static int cpufreq_scale_rate_for_dvfs(struct clk *clk, unsigned long rate, dvfs_set_rate_callback set_rate);
-
-/*******************************************************/
-static unsigned int rk3188_cpufreq_get(unsigned int cpu)
-{
- return clk_get_rate(cpu_clk) / 1000;
-}
-
-static bool cpufreq_is_ondemand(struct cpufreq_policy *policy)
-{
- char c = 0;
- if (policy && policy->governor)
- c = policy->governor->name[0];
- return (c == 'o' || c == 'i' || c == 'c' || c == 'h');
-}
-
-static unsigned int get_freq_from_table(unsigned int max_freq)
-{
- unsigned int i;
- unsigned int target_freq = 0;
- for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
- unsigned int freq = freq_table[i].frequency;
- if (freq <= max_freq && target_freq < freq) {
- target_freq = freq;
- }
- }
- if (!target_freq)
- target_freq = max_freq;
- return target_freq;
-}
-
-/**********************thermal limit**************************/
-#define CONFIG_RK30_CPU_FREQ_LIMIT_BY_TEMP
-
-#ifdef CONFIG_RK30_CPU_FREQ_LIMIT_BY_TEMP
-static unsigned int temp_limit_freq = -1;
-module_param(temp_limit_freq, uint, 0444);
-
-#if defined(CONFIG_SOC_RK3188M)
-static struct cpufreq_frequency_table temp_limits[4][4] = {
- { // 1 CPU busy
- {.frequency = -1, .index = 50},
- {.frequency = -1, .index = 55},
- {.frequency = 1416 * 1000, .index = 60},
- {.frequency = 1200 * 1000, .index = 75},
- }, { // 2 CPUs busy
- {.frequency = 1416 * 1000, .index = 50},
- {.frequency = 1200 * 1000, .index = 55},
- {.frequency = 1008 * 1000, .index = 60},
- {.frequency = 816 * 1000, .index = 75},
- }, { // 3 CPUs busy
- {.frequency = 1296 * 1000, .index = 50},
- {.frequency = 1104 * 1000, .index = 55},
- {.frequency = 912 * 1000, .index = 60},
- {.frequency = 696 * 1000, .index = 75},
- }, { // 4 CPUs busy
- {.frequency = 1200 * 1000, .index = 50},
- {.frequency = 1008 * 1000, .index = 55},
- {.frequency = 816 * 1000, .index = 60},
- {.frequency = 600 * 1000, .index = 75},
- }
-};
-
-static struct cpufreq_frequency_table temp_limits_cpu_perf[] = {
- {.frequency = 1200 * 1000, .index = 60},
- {.frequency = 1008 * 1000, .index = 100},
-};
-
-static struct cpufreq_frequency_table temp_limits_gpu_perf[] = {
- {.frequency = 1008 * 1000, .index = 0},
-};
-#elif defined(CONFIG_ARCH_RK3026)
-static struct cpufreq_frequency_table temp_limits[2][1] = {
- { // 1 CPU busy
- {.frequency = 912 * 1000, .index = 0},
- }, { // 2 CPUs busy
- {.frequency = 816 * 1000, .index = 0},
- }
-};
-
-static struct cpufreq_frequency_table temp_limits_cpu_perf[] = {
- {.frequency = 1008 * 1000, .index = 0},
-};
-
-static struct cpufreq_frequency_table temp_limits_gpu_perf[] = {
- {.frequency = 1008 * 1000, .index = 0},
-};
-
-static struct cpufreq_frequency_table temp_limits_3028a[2][1] = {
- { // 1 CPU busy
- {.frequency = -1, .index = 0},
- }, { // 2 CPUs busy
- {.frequency = 1008 * 1000, .index = 0},
- }
-};
-
-static struct cpufreq_frequency_table temp_limits_cpu_perf_3028a[] = {
- {.frequency = 1200 * 1000, .index = 0},
-};
-#else /* 3188/3168 etc */
-static struct cpufreq_frequency_table temp_limits[4][4] = {
- { // 1 CPU busy
- {.frequency = -1, .index = 50},
- {.frequency = -1, .index = 55},
- {.frequency = -1, .index = 60},
- {.frequency = 1608 * 1000, .index = 75},
- }, { // 2 CPUs busy
- {.frequency = 1800 * 1000, .index = 50},
- {.frequency = 1608 * 1000, .index = 55},
- {.frequency = 1416 * 1000, .index = 60},
- {.frequency = 1200 * 1000, .index = 75},
- }, { // 3 CPUs busy
- {.frequency = 1608 * 1000, .index = 50},
- {.frequency = 1416 * 1000, .index = 55},
- {.frequency = 1200 * 1000, .index = 60},
- {.frequency = 1008 * 1000, .index = 75},
- }, { // 4 CPUs busy
- {.frequency = 1416 * 1000, .index = 50},
- {.frequency = 1200 * 1000, .index = 55},
- {.frequency = 1008 * 1000, .index = 60},
- {.frequency = 816 * 1000, .index = 75},
- }
-};
-
-static struct cpufreq_frequency_table temp_limits_cpu_perf[] = {
- {.frequency = 1008 * 1000, .index = 100},
-};
-
-static struct cpufreq_frequency_table temp_limits_gpu_perf[] = {
- {.frequency = 1008 * 1000, .index = 0},
-};
-#endif
-
-static int rk3188_get_temp(void)
-{
- return 60;
-}
-
-static char sys_state;
-static ssize_t sys_state_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
-{
- char state;
-
- if (count < 1)
- return count;
- if (copy_from_user(&state, buffer, 1)) {
- return -EFAULT;
- }
-
- sys_state = state;
- return count;
-}
-
-static const struct file_operations sys_state_fops = {
- .owner = THIS_MODULE,
- .write = sys_state_write,
-};
-
-static struct miscdevice sys_state_dev = {
- .fops = &sys_state_fops,
- .name = "sys_state",
- .minor = MISC_DYNAMIC_MINOR,
-};
-
-static void rk3188_cpufreq_temp_limit_work_func(struct work_struct *work)
-{
- static bool in_perf = false;
- struct cpufreq_policy *policy;
- int temp, i;
- unsigned int new_freq = -1;
- unsigned long delay = HZ / 10; // 100ms
- unsigned int nr_cpus = num_online_cpus();
- const struct cpufreq_frequency_table *limits_table = temp_limits[nr_cpus - 1];
- size_t limits_size = ARRAY_SIZE(temp_limits[nr_cpus - 1]);
-
- temp = rk3188_get_temp();
-
- if (sys_state == '1') {
- in_perf = true;
- if (gpu_is_mali400) {
- unsigned int gpu_irqs[2];
- gpu_irqs[0] = kstat_irqs(IRQ_GPU_GP);
- msleep(40);
- gpu_irqs[1] = kstat_irqs(IRQ_GPU_GP);
- delay = 0;
- if ((gpu_irqs[1] - gpu_irqs[0]) < 8) {
- limits_table = temp_limits_cpu_perf;
- limits_size = ARRAY_SIZE(temp_limits_cpu_perf);
- } else {
- limits_table = temp_limits_gpu_perf;
- limits_size = ARRAY_SIZE(temp_limits_gpu_perf);
- }
- } else {
- delay = HZ; // 1s
- limits_table = temp_limits_cpu_perf;
- limits_size = ARRAY_SIZE(temp_limits_cpu_perf);
- }
- } else if (in_perf) {
- in_perf = false;
- } else {
- static u64 last_time_in_idle = 0;
- static u64 last_time_in_idle_timestamp = 0;
- u64 time_in_idle = 0, now;
- u32 delta_idle;
- u32 delta_time;
- unsigned cpu;
-
- for_each_online_cpu(cpu) {
- time_in_idle += get_cpu_idle_time_us(cpu, &now);
- }
- delta_time = now - last_time_in_idle_timestamp;
- delta_idle = time_in_idle - last_time_in_idle;
- last_time_in_idle = time_in_idle;
- last_time_in_idle_timestamp = now;
- delta_idle += delta_time >> 4; // +6.25%
- if (delta_idle > (nr_cpus - 1) * delta_time && delta_idle < (nr_cpus + 1) * delta_time)
- limits_table = temp_limits[0];
- else if (delta_idle > (nr_cpus - 2) * delta_time)
- limits_table = temp_limits[1];
- else if (delta_idle > (nr_cpus - 3) * delta_time)
- limits_table = temp_limits[2];
- FREQ_DBG("delta time %6u us idle %6u us %u cpus select table %d\n", delta_time, delta_idle, nr_cpus, (limits_table - temp_limits[0]) / ARRAY_SIZE(temp_limits[0]));
- }
-
- for (i = 0; i < limits_size; i++) {
- if (temp >= limits_table[i].index) {
- new_freq = limits_table[i].frequency;
- }
- }
-
- if (temp_limit_freq != new_freq) {
- unsigned int cur_freq;
- temp_limit_freq = new_freq;
- cur_freq = rk3188_cpufreq_get(0);
- FREQ_DBG("temp limit %7d KHz cur %7d KHz\n", temp_limit_freq, cur_freq);
- if (cur_freq > temp_limit_freq) {
- policy = cpufreq_cpu_get(0);
- cpufreq_driver_target(policy, policy->cur, CPUFREQ_RELATION_L | CPUFREQ_PRIVATE);
- cpufreq_cpu_put(policy);
- }
- }
-
- queue_delayed_work_on(0, freq_wq, to_delayed_work(work), delay);
-}
-
-static DECLARE_DELAYED_WORK(rk3188_cpufreq_temp_limit_work, rk3188_cpufreq_temp_limit_work_func);
-
-static int rk3188_cpufreq_notifier_policy(struct notifier_block *nb, unsigned long val, void *data)
-{
- struct cpufreq_policy *policy = data;
-
- if (val != CPUFREQ_NOTIFY)
- return 0;
-
- if (cpufreq_is_ondemand(policy)) {
- FREQ_DBG("queue work\n");
- queue_delayed_work_on(0, freq_wq, &rk3188_cpufreq_temp_limit_work, 0);
- } else {
- FREQ_DBG("cancel work\n");
- cancel_delayed_work_sync(&rk3188_cpufreq_temp_limit_work);
- }
-
- return 0;
-}
-
-static struct notifier_block notifier_policy_block = {
- .notifier_call = rk3188_cpufreq_notifier_policy
-};
-
-static void rk3188_cpufreq_temp_limit_init(struct cpufreq_policy *policy)
-{
- unsigned int i;
- struct cpufreq_frequency_table *table;
-
-#if defined(CONFIG_ARCH_RK3026)
- if (soc_is_rk3028a()) {
- memcpy(temp_limits, temp_limits_3028a, sizeof(temp_limits));
- memcpy(temp_limits_cpu_perf, temp_limits_cpu_perf_3028a, sizeof(temp_limits_cpu_perf));
- }
-#endif
-
- table = temp_limits[0];
- for (i = 0; i < sizeof(temp_limits) / sizeof(struct cpufreq_frequency_table); i++) {
- table[i].frequency = get_freq_from_table(table[i].frequency);
- }
- table = temp_limits_cpu_perf;
- for (i = 0; i < sizeof(temp_limits_cpu_perf) / sizeof(struct cpufreq_frequency_table); i++) {
- table[i].frequency = get_freq_from_table(table[i].frequency);
- }
- table = temp_limits_gpu_perf;
- for (i = 0; i < sizeof(temp_limits_gpu_perf) / sizeof(struct cpufreq_frequency_table); i++) {
- table[i].frequency = get_freq_from_table(table[i].frequency);
- }
- misc_register(&sys_state_dev);
- if (cpufreq_is_ondemand(policy)) {
- queue_delayed_work_on(0, freq_wq, &rk3188_cpufreq_temp_limit_work, 0*HZ);
- }
- cpufreq_register_notifier(¬ifier_policy_block, CPUFREQ_POLICY_NOTIFIER);
-}
-
-static void rk3188_cpufreq_temp_limit_exit(void)
-{
- cpufreq_unregister_notifier(¬ifier_policy_block, CPUFREQ_POLICY_NOTIFIER);
- if (freq_wq)
- cancel_delayed_work(&rk3188_cpufreq_temp_limit_work);
-}
-#else
-static inline void rk3188_cpufreq_temp_limit_init(struct cpufreq_policy *policy) {}
-static inline void rk3188_cpufreq_temp_limit_exit(void) {}
-#endif
-
-/************************************dvfs tst************************************/
-//#define CPU_FREQ_DVFS_TST
-#ifdef CPU_FREQ_DVFS_TST
-static unsigned int freq_dvfs_tst_rate;
-static int test_count;
-#define TEST_FRE_NUM 11
-static int test_tlb_rate[TEST_FRE_NUM] = { 504, 1008, 504, 1200, 252, 816, 1416, 252, 1512, 252, 816 };
-//static int test_tlb_rate[TEST_FRE_NUM]={504,1008,504,1200,252,816,1416,126,1512,126,816};
-
-#define TEST_GPU_NUM 3
-
-static int test_tlb_gpu[TEST_GPU_NUM] = { 360, 400, 180 };
-static int test_tlb_ddr[TEST_GPU_NUM] = { 401, 200, 500 };
-
-static int gpu_ddr = 0;
-
-static void rk3188_cpufreq_dvsf_tst_work_func(struct work_struct *work)
-{
- struct cpufreq_policy *policy = cpufreq_cpu_get(0);
-
- gpu_ddr++;
-
-#if 0
- FREQ_LOG("cpufreq_dvsf_tst,ddr%u,gpu%u\n",
- test_tlb_ddr[gpu_ddr % TEST_GPU_NUM],
- test_tlb_gpu[gpu_ddr % TEST_GPU_NUM]);
- clk_set_rate(ddr_clk, test_tlb_ddr[gpu_ddr % TEST_GPU_NUM] * 1000 * 1000);
- clk_set_rate(gpu_clk, test_tlb_gpu[gpu_ddr % TEST_GPU_NUM] * 1000 * 1000);
-#endif
-
- test_count++;
- freq_dvfs_tst_rate = test_tlb_rate[test_count % TEST_FRE_NUM] * 1000;
- FREQ_LOG("cpufreq_dvsf_tst,cpu set rate %d\n", freq_dvfs_tst_rate);
- cpufreq_driver_target(policy, policy->cur, CPUFREQ_RELATION_L);
- cpufreq_cpu_put(policy);
-
- queue_delayed_work_on(0, freq_wq, to_delayed_work(work), msecs_to_jiffies(1000));
-}
-
-static DECLARE_DELAYED_WORK(rk3188_cpufreq_dvsf_tst_work, rk3188_cpufreq_dvsf_tst_work_func);
-#endif /* CPU_FREQ_DVFS_TST */
-
-/***********************************************************************/
-static int rk3188_cpufreq_verify(struct cpufreq_policy *policy)
-{
- if (!freq_table)
- return -EINVAL;
- return cpufreq_frequency_table_verify(policy, freq_table);
-}
-
-static int rk3188_cpufreq_init_cpu0(struct cpufreq_policy *policy)
-{
- unsigned int i;
-
- gpu_is_mali400 = cpu_is_rk3188();
- gpu_clk = clk_get(NULL, "gpu");
- if (IS_ERR(gpu_clk))
- return PTR_ERR(gpu_clk);
-
- ddr_clk = clk_get(NULL, "ddr");
- if (IS_ERR(ddr_clk))
- return PTR_ERR(ddr_clk);
-
- cpu_clk = clk_get(NULL, "cpu");
- if (IS_ERR(cpu_clk))
- return PTR_ERR(cpu_clk);
-
-#if defined(CONFIG_ARCH_RK3188)
- if (soc_is_rk3188() || soc_is_rk3188plus()) {
- struct cpufreq_frequency_table *table_adjust;
- /* Adjust dvfs table avoid overheat */
- table_adjust = dvfs_get_freq_volt_table(cpu_clk);
- dvfs_adjust_table_lmtvolt(cpu_clk, table_adjust);
- table_adjust = dvfs_get_freq_volt_table(gpu_clk);
- dvfs_adjust_table_lmtvolt(gpu_clk, table_adjust);
- }
-#endif
- clk_enable_dvfs(gpu_clk);
- if (gpu_is_mali400)
- dvfs_clk_enable_limit(gpu_clk, 133000000, 600000000);
-
- clk_enable_dvfs(ddr_clk);
-
- dvfs_clk_register_set_rate_callback(cpu_clk, cpufreq_scale_rate_for_dvfs);
- freq_table = dvfs_get_freq_volt_table(cpu_clk);
- if (freq_table == NULL) {
- freq_table = default_freq_table;
- } else {
- int v = INT_MAX;
- for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
- if (freq_table[i].index >= suspend_volt && v > freq_table[i].index) {
- suspend_freq = freq_table[i].frequency;
- v = freq_table[i].index;
- }
- }
- }
- low_battery_freq = get_freq_from_table(low_battery_freq);
- clk_enable_dvfs(cpu_clk);
- if(rk_tflag()){
-#define RK3188_T_LIMIT_FREQ (1416 * 1000)
- dvfs_clk_enable_limit(cpu_clk, 0, RK3188_T_LIMIT_FREQ * 1000);
- for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
- if (freq_table[i].frequency > RK3188_T_LIMIT_FREQ) {
- printk("cpufreq: delete arm freq(%u)\n", freq_table[i].frequency);
- freq_table[i].frequency = CPUFREQ_TABLE_END;
- }
- }
- }
- freq_wq = alloc_workqueue("rk3188_cpufreqd", WQ_NON_REENTRANT | WQ_MEM_RECLAIM | WQ_HIGHPRI | WQ_FREEZABLE, 1);
- rk3188_cpufreq_temp_limit_init(policy);
-#ifdef CPU_FREQ_DVFS_TST
- queue_delayed_work(freq_wq, &rk3188_cpufreq_dvsf_tst_work, msecs_to_jiffies(20 * 1000));
-#endif
-
- printk("rk3188 cpufreq version " VERSION ", suspend freq %d MHz\n", suspend_freq / 1000);
- return 0;
-}
-
-static int rk3188_cpufreq_init(struct cpufreq_policy *policy)
-{
- if (policy->cpu == 0) {
- int err = rk3188_cpufreq_init_cpu0(policy);
- if (err)
- return err;
- }
-
- //set freq min max
- cpufreq_frequency_table_cpuinfo(policy, freq_table);
- //sys nod
- cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
-
- policy->cur = rk3188_cpufreq_get(0);
-
- policy->cpuinfo.transition_latency = 40 * NSEC_PER_USEC; // make ondemand default sampling_rate to 40000
-
- /*
- * On SMP configuartion, both processors share the voltage
- * and clock. So both CPUs needs to be scaled together and hence
- * needs software co-ordination. Use cpufreq affected_cpus
- * interface to handle this scenario. Additional is_smp() check
- * is to keep SMP_ON_UP build working.
- */
- if (is_smp())
- cpumask_setall(policy->cpus);
-
- return 0;
-}
-
-static int rk3188_cpufreq_exit(struct cpufreq_policy *policy)
-{
- if (policy->cpu != 0)
- return 0;
-
- cpufreq_frequency_table_cpuinfo(policy, freq_table);
- clk_put(cpu_clk);
- rk3188_cpufreq_temp_limit_exit();
- if (freq_wq) {
- flush_workqueue(freq_wq);
- destroy_workqueue(freq_wq);
- freq_wq = NULL;
- }
-
- return 0;
-}
-
-static struct freq_attr *rk3188_cpufreq_attr[] = {
- &cpufreq_freq_attr_scaling_available_freqs,
- NULL,
-};
-
-#ifdef CONFIG_POWER_SUPPLY
-extern int rk_get_system_battery_capacity(void);
-#else
-static int rk_get_system_battery_capacity(void) { return 100; }
-#endif
-
-static unsigned int cpufreq_scale_limit(unsigned int target_freq, struct cpufreq_policy *policy, bool is_private)
-{
- bool is_ondemand = cpufreq_is_ondemand(policy);
-
-#ifdef CPU_FREQ_DVFS_TST
- if (freq_dvfs_tst_rate) {
- target_freq = freq_dvfs_tst_rate;
- freq_dvfs_tst_rate = 0;
- return target_freq;
- }
-#endif
-
- if (!is_ondemand)
- return target_freq;
-
- if (is_booting) {
- s64 boottime_ms = ktime_to_ms(ktime_get_boottime());
- if (boottime_ms > 60 * MSEC_PER_SEC) {
- is_booting = false;
- } else if (target_freq > low_battery_freq &&
- rk_get_system_battery_capacity() <= low_battery_capacity) {
- target_freq = low_battery_freq;
- }
- }
-
-#ifdef CONFIG_RK30_CPU_FREQ_LIMIT_BY_TEMP
- {
- static unsigned int ondemand_target = 816 * 1000;
- if (is_private)
- target_freq = ondemand_target;
- else
- ondemand_target = target_freq;
- }
-
- /*
- * If the new frequency is more than the thermal max allowed
- * frequency, go ahead and scale the mpu device to proper frequency.
- */
- target_freq = min(target_freq, temp_limit_freq);
-#endif
-
- return target_freq;
-}
-
-static int cpufreq_scale_rate_for_dvfs(struct clk *clk, unsigned long rate, dvfs_set_rate_callback set_rate)
-{
- unsigned int i;
- int ret;
- struct cpufreq_freqs freqs;
-
- freqs.new = rate / 1000;
- freqs.old = clk_get_rate(clk) / 1000;
-
- for_each_online_cpu(freqs.cpu) {
- cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
- }
- FREQ_DBG("cpufreq_scale_rate_for_dvfs(%lu)\n", rate);
- ret = set_rate(clk, rate);
-
-#ifdef CONFIG_SMP
- /*
- * Note that loops_per_jiffy is not updated on SMP systems in
- * cpufreq driver. So, update the per-CPU loops_per_jiffy value
- * on frequency transition. We need to update all dependent CPUs.
- */
- for_each_possible_cpu(i) {
- per_cpu(cpu_data, i).loops_per_jiffy = loops_per_jiffy;
- }
-#endif
-
- freqs.new = clk_get_rate(clk) / 1000;
- /* notifiers */
- for_each_online_cpu(freqs.cpu) {
- cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
- }
-
- return ret;
-}
-
-static int rk3188_cpufreq_target(struct cpufreq_policy *policy, unsigned int target_freq, unsigned int relation)
-{
- unsigned int i, new_freq = target_freq, new_rate, cur_rate;
- int ret = 0;
- bool is_private;
-
- if (!freq_table) {
- FREQ_ERR("no freq table!\n");
- return -EINVAL;
- }
-
- mutex_lock(&cpufreq_mutex);
-
- is_private = relation & CPUFREQ_PRIVATE;
- relation &= ~CPUFREQ_PRIVATE;
-
- if (relation & ENABLE_FURTHER_CPUFREQ)
- no_cpufreq_access--;
- if (no_cpufreq_access) {
- FREQ_LOG("denied access to %s as it is disabled temporarily\n", __func__);
- ret = -EINVAL;
- goto out;
- }
- if (relation & DISABLE_FURTHER_CPUFREQ)
- no_cpufreq_access++;
- relation &= ~MASK_FURTHER_CPUFREQ;
-
- ret = cpufreq_frequency_table_target(policy, freq_table, target_freq, relation, &i);
- if (ret) {
- FREQ_ERR("no freq match for %d(ret=%d)\n", target_freq, ret);
- goto out;
- }
- new_freq = freq_table[i].frequency;
- if (!no_cpufreq_access)
- new_freq = cpufreq_scale_limit(new_freq, policy, is_private);
-
- new_rate = new_freq * 1000;
- cur_rate = clk_get_rate(cpu_clk);
- FREQ_LOG("req = %7u new = %7u (was = %7u)\n", target_freq, new_freq, cur_rate / 1000);
- if (new_rate == cur_rate)
- goto out;
- ret = clk_set_rate(cpu_clk, new_rate);
-
-out:
- FREQ_DBG("set freq (%7u) end, ret %d\n", new_freq, ret);
- mutex_unlock(&cpufreq_mutex);
- return ret;
-}
-
-static int rk3188_cpufreq_pm_notifier_event(struct notifier_block *this, unsigned long event, void *ptr)
-{
- int ret = NOTIFY_DONE;
- struct cpufreq_policy *policy = cpufreq_cpu_get(0);
-
- if (!policy)
- return ret;
-
- if (!cpufreq_is_ondemand(policy))
- goto out;
-
- switch (event) {
- case PM_SUSPEND_PREPARE:
- ret = cpufreq_driver_target(policy, suspend_freq, DISABLE_FURTHER_CPUFREQ | CPUFREQ_RELATION_H);
- if (ret < 0) {
- ret = NOTIFY_BAD;
- goto out;
- }
- ret = NOTIFY_OK;
- break;
- case PM_POST_RESTORE:
- case PM_POST_SUSPEND:
- cpufreq_driver_target(policy, suspend_freq, ENABLE_FURTHER_CPUFREQ | CPUFREQ_RELATION_H);
- ret = NOTIFY_OK;
- break;
- }
-out:
- cpufreq_cpu_put(policy);
- return ret;
-}
-
-static struct notifier_block rk3188_cpufreq_pm_notifier = {
- .notifier_call = rk3188_cpufreq_pm_notifier_event,
-};
-
-static int rk3188_cpufreq_reboot_notifier_event(struct notifier_block *this, unsigned long event, void *ptr)
-{
- struct cpufreq_policy *policy = cpufreq_cpu_get(0);
-
- if (policy) {
- is_booting = false;
- cpufreq_driver_target(policy, suspend_freq, DISABLE_FURTHER_CPUFREQ | CPUFREQ_RELATION_H);
- cpufreq_cpu_put(policy);
- }
-
- return NOTIFY_OK;
-}
-
-static struct notifier_block rk3188_cpufreq_reboot_notifier = {
- .notifier_call = rk3188_cpufreq_reboot_notifier_event,
-};
-
-static struct cpufreq_driver rk3188_cpufreq_driver = {
- .flags = CPUFREQ_CONST_LOOPS,
- .verify = rk3188_cpufreq_verify,
- .target = rk3188_cpufreq_target,
- .get = rk3188_cpufreq_get,
- .init = rk3188_cpufreq_init,
- .exit = rk3188_cpufreq_exit,
- .name = "rk3188",
- .attr = rk3188_cpufreq_attr,
-};
-
-static int __init rk3188_cpufreq_driver_init(void)
-{
- register_pm_notifier(&rk3188_cpufreq_pm_notifier);
- register_reboot_notifier(&rk3188_cpufreq_reboot_notifier);
- return cpufreq_register_driver(&rk3188_cpufreq_driver);
-}
-
-static void __exit rk3188_cpufreq_driver_exit(void)
-{
- cpufreq_unregister_driver(&rk3188_cpufreq_driver);
-}
-
-device_initcall(rk3188_cpufreq_driver_init);
-module_exit(rk3188_cpufreq_driver_exit);
+++ /dev/null
-/*
- * Copyright (C) 2013 ROCKCHIP, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License.
- */
-
-//#define DEBUG 1
-#define pr_fmt(fmt) "delayline: " fmt
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <mach/cpu.h>
-
-#define RK30_DELAYLINE_BASE (RK30_TIMER0_BASE + 0x1000)
-#define delayline_readl(offset) readl_relaxed(RK30_DELAYLINE_BASE + offset)
-#define delayline_writel(val, offset) writel_relaxed(val, RK30_DELAYLINE_BASE + offset)
-
-#define DELAYLINE_CON0 (0x0000)
-#define DELAYLINE_STOP (0 << 5)
-#define DELAYLINE_START (1 << 5)
-#define DELAYLINE_CLK_SEL_24M (0 << 4)
-#define DELAYLINE_CLK_SEL_ACLK_CPU (1 << 4)
-#define DELAYLINE_DIV_MAX (0xf)
-
-#define DELAYLINE_CON1 (0x0004)
-#define DELAYLINE_INCREMENT(n) ((n & 0xff) << 8)
-#define DELAYLINE_START_POINT(n) (n & 0xff)
-
-#define DELAYLINE_STATUS (0x0008)
-#define DELAYLINE_LOCKED (1 << 8)
-#define DELAYLINE_VALUE_MASK (0xff)
-
-static u32 delayline_div;
-static u32 start_point;
-
-int rk3188_get_delayline_value(void)
-{
- u32 status;
- u32 loop = 1000;
-
- if (!start_point)
- return 0;
-
- delayline_writel(DELAYLINE_INCREMENT(4) | start_point, DELAYLINE_CON1);
- delayline_writel(DELAYLINE_START | DELAYLINE_CLK_SEL_ACLK_CPU | delayline_div, DELAYLINE_CON0);
- dsb();
- delayline_writel(DELAYLINE_STOP | DELAYLINE_CLK_SEL_ACLK_CPU | delayline_div, DELAYLINE_CON0);
- dsb();
-
- do {
- status = delayline_readl(DELAYLINE_STATUS);
- if (status & DELAYLINE_LOCKED)
- break;
- udelay(1);
- loop--;
- } while (loop);
-
- if (!loop) {
- start_point >>= 1;
- return 0;
- }
-
- return status & DELAYLINE_VALUE_MASK;
-}
-
-static int __init delayline_set_rate(unsigned long parent_rate, unsigned long rate)
-{
- u32 div;
- for (div = 0; div <= DELAYLINE_DIV_MAX; div++) {
- u32 new_rate = parent_rate / (div + 1);
- if (new_rate <= rate) {
- delayline_div = div;
- return 0;
- }
- }
- return -ENOENT;
-}
-
-static int __init rk3188_delayline_init(void)
-{
- struct clk *clk_aclk_cpu;
- unsigned long aclk_rate;
-
- if (!soc_is_rk3188plus())
- return 0;
-
- clk_aclk_cpu = clk_get(NULL, "aclk_cpu");
- if (IS_ERR_OR_NULL(clk_aclk_cpu)) {
- pr_err("can not get parent clock 'aclk_cpu'\n");
- return 0;
- }
-
- aclk_rate = clk_get_rate(clk_aclk_cpu);
- clk_put(clk_aclk_cpu);
- delayline_set_rate(aclk_rate, 100 * 1000 * 1000);
- start_point = 0x10;
- start_point = rk3188_get_delayline_value() >> 1;
- printk(KERN_DEBUG "delayline: aclk_cpu %lu div %u clk %lu start point %u\n", aclk_rate, delayline_div, aclk_rate / (delayline_div + 1), start_point);
-
- return 0;
-}
-
-pure_initcall(rk3188_delayline_init);
+++ /dev/null
-/* arch/arm/mach-rk30/rk30_dvfs.c\r
- *\r
- * Copyright (C) 2012 ROCKCHIP, Inc.\r
- *\r
- * This software is licensed under the terms of the GNU General Public\r
- * License version 2, as published by the Free Software Foundation, and\r
- * may be copied, distributed, and modified under those terms.\r
- *\r
- * This program is distributed in the hope that it will be useful,\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- * GNU General Public License for more details.\r
- *\r
- */\r
-\r
-#include <linux/kernel.h>\r
-#include <linux/err.h>\r
-#include <linux/spinlock.h>\r
-#include <linux/list.h>\r
-#include <linux/slab.h>\r
-#include <linux/clk.h>\r
-#include <linux/cpufreq.h>\r
-#include <mach/dvfs.h>\r
-#include <mach/clock.h>\r
-#include <linux/regulator/consumer.h>\r
-#include <linux/delay.h>\r
-#include <linux/io.h>\r
-#include <linux/hrtimer.h>\r
-#include <plat/efuse.h>\r
-\r
-static int rk_dvfs_clk_notifier_event(struct notifier_block *this,\r
- unsigned long event, void *ptr)\r
-{\r
- struct clk_notifier_data *noti_info;\r
- struct clk *clk;\r
- struct clk_node *dvfs_clk;\r
- noti_info = (struct clk_notifier_data *)ptr;\r
- clk = noti_info->clk;\r
- dvfs_clk = clk->dvfs_info;\r
-\r
- switch (event) {\r
- case CLK_PRE_RATE_CHANGE:\r
- DVFS_DBG("%s CLK_PRE_RATE_CHANGE\n", __func__);\r
- break;\r
- case CLK_POST_RATE_CHANGE:\r
- DVFS_DBG("%s CLK_POST_RATE_CHANGE\n", __func__);\r
- break;\r
- case CLK_ABORT_RATE_CHANGE:\r
- DVFS_DBG("%s CLK_ABORT_RATE_CHANGE\n", __func__);\r
- break;\r
- case CLK_PRE_ENABLE:\r
- DVFS_DBG("%s CLK_PRE_ENABLE\n", __func__);\r
- break;\r
- case CLK_POST_ENABLE:\r
- DVFS_DBG("%s CLK_POST_ENABLE\n", __func__);\r
- break;\r
- case CLK_ABORT_ENABLE:\r
- DVFS_DBG("%s CLK_ABORT_ENABLE\n", __func__);\r
- break;\r
- case CLK_PRE_DISABLE:\r
- DVFS_DBG("%s CLK_PRE_DISABLE\n", __func__);\r
- break;\r
- case CLK_POST_DISABLE:\r
- DVFS_DBG("%s CLK_POST_DISABLE\n", __func__);\r
- dvfs_clk->set_freq = 0;\r
- break;\r
- case CLK_ABORT_DISABLE:\r
- DVFS_DBG("%s CLK_ABORT_DISABLE\n", __func__);\r
-\r
- break;\r
- default:\r
- break;\r
- }\r
- return 0;\r
-}\r
-\r
-static struct notifier_block rk_dvfs_clk_notifier = {\r
- .notifier_call = rk_dvfs_clk_notifier_event,\r
-};\r
-\r
-struct lkg_maxvolt {\r
- int leakage_level;\r
- unsigned int maxvolt;\r
-};\r
-#if 0\r
-/* avdd_com & vdd_arm separate circuit */\r
-static struct lkg_maxvolt lkg_volt_table[] = {\r
- {.leakage_level = 1, .maxvolt = 1350 * 1000},\r
- {.leakage_level = 3, .maxvolt = 1275 * 1000},\r
- {.leakage_level = 15, .maxvolt = 1200 * 1000},\r
-};\r
-#else\r
-/* avdd_com & vdd_arm short circuit */\r
-static struct lkg_maxvolt lkg_volt_table[] = {\r
- {.leakage_level = 3, .maxvolt = 1350 * 1000},\r
- {.leakage_level = 5, .maxvolt = 1300 * 1000},\r
- {.leakage_level = 15, .maxvolt = 1250 * 1000},\r
-};\r
-#endif\r
-#define LOW_LEAKAGE_BOUND 2\r
-#define VOLT_COMPENSATION (25000) // uV\r
-static int leakage_level = 0;\r
-#define MHZ (1000 * 1000)\r
-#define KHZ (1000)\r
-// Delayline bound for nandc = 148.5MHz, Varm = Vlog = 1.00V\r
-#define HIGH_DELAYLINE 125\r
-#define LOW_DELAYLINE 125\r
-static u8 rk30_get_avs_val(void);\r
-void dvfs_adjust_table_lmtvolt(struct clk *clk, struct cpufreq_frequency_table *table)\r
-{\r
- int i = 0;\r
- unsigned int maxvolt = 0;\r
- if (IS_ERR_OR_NULL(clk) || IS_ERR_OR_NULL(table)) {\r
- DVFS_ERR("%s: clk error OR table error\n", __func__);\r
- return ;\r
- }\r
-\r
- leakage_level = rk_leakage_val();\r
- printk("DVFS MSG: %s: %s get leakage_level = %d\n", clk->name, __func__, leakage_level);\r
- if (leakage_level == 0) {\r
- \r
- /*\r
- * This is for delayline auto scale voltage, \r
- * FIXME: HIGH_DELAYLINE / LOW_DELAYLINE value maybe redefined under\r
- * Varm = Vlog = 1.00V.\r
- * Warning: this value is frequency/voltage sensitive, care\r
- * about Freq nandc/Volt log.\r
- *\r
- */\r
-\r
- unsigned long delayline_val = 0;\r
- unsigned long high_delayline = 0, low_delayline = 0;\r
- unsigned long rate_nandc = 0;\r
- rate_nandc = clk_get_rate(clk_get(NULL, "nandc")) / KHZ;\r
- printk("Get nandc rate = %lu KHz\n", rate_nandc);\r
- high_delayline = HIGH_DELAYLINE * 148500 / rate_nandc;\r
- low_delayline = LOW_DELAYLINE * 148500 / rate_nandc;\r
- delayline_val = rk30_get_avs_val();\r
- printk("This chip no leakage msg, use delayline instead, val = %lu.(HDL=%lu, LDL=%lu)\n",\r
- delayline_val, high_delayline, low_delayline);\r
-\r
- if (delayline_val >= high_delayline) {\r
- leakage_level = 4; //same as leakage_level > 4\r
-\r
- } else if (delayline_val <= low_delayline) {\r
- leakage_level = 1;\r
- printk("Delayline TOO LOW, high voltage request\n");\r
-\r
- } else\r
- leakage_level = 2; //same as leakage_level = 3\r
- }\r
-\r
- for (i = 0; i < ARRAY_SIZE(lkg_volt_table); i++) {\r
- if (leakage_level <= lkg_volt_table[i].leakage_level) {\r
- maxvolt = lkg_volt_table[i].maxvolt;\r
- break;\r
- }\r
- }\r
-\r
- // limit high voltage\r
- for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) {\r
- if (table[i].index > maxvolt) {\r
- printk("\t\tadjust table freq=%d KHz, index=%d mV", table[i].frequency, table[i].index);\r
- table[i].index = maxvolt;\r
- printk(" to index=%d mV\n", table[i].index);\r
- }\r
- }\r
-#if 0\r
- /*\r
- * Low freq add some voltage for low leakage chip.\r
- * Open it when necessary.\r
- *\r
- */\r
-\r
- // limit low voltage\r
- if (strncmp(clk->dvfs_info->name, "cpu", strlen("cpu")) == 0\r
- && leakage_level <= LOW_LEAKAGE_BOUND) {\r
- for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) {\r
- if (table[i].index + VOLT_COMPENSATION < maxvolt) {\r
- printk("\t\tadjust table freq=%d KHz, index=%d mV",\r
- table[i].frequency, table[i].index);\r
- table[i].index += VOLT_COMPENSATION;\r
- printk(" to index=%d mV\n", table[i].index);\r
- }\r
- }\r
- }\r
-#endif\r
-}\r
-\r
-#define NO_VOLT_DIFF\r
-#ifdef NO_VOLT_DIFF\r
-\r
-int dvfs_target(struct clk *clk, unsigned long rate_hz)\r
-{\r
- struct clk_node *dvfs_clk;\r
- int volt_new = 0, clk_volt_store = 0;\r
- struct cpufreq_frequency_table clk_fv;\r
- int ret = 0;\r
- unsigned long rate_new, rate_old;\r
-\r
- if (!clk) {\r
- DVFS_ERR("%s is not a clk\n", __func__);\r
- return -1;\r
- }\r
- dvfs_clk = clk_get_dvfs_info(clk);\r
- DVFS_DBG("enter %s: clk(%s) rate = %lu Hz\n", __func__, dvfs_clk->name, rate_hz);\r
-\r
- if (!dvfs_clk || dvfs_clk->vd == NULL || IS_ERR_OR_NULL(dvfs_clk->vd->regulator)) {\r
- DVFS_ERR("dvfs(%s) is not register regulator\n", dvfs_clk->name);\r
- return -1;\r
- }\r
-\r
- if (dvfs_clk->vd->volt_set_flag == DVFS_SET_VOLT_FAILURE) {\r
- /* It means the last time set voltage error */\r
- ret = dvfs_reset_volt(dvfs_clk->vd);\r
- if (ret < 0) {\r
- return -1;\r
- }\r
- }\r
-\r
- /* Check limit rate */\r
- //if (dvfs_clk->freq_limit_en) {\r
- if (rate_hz < dvfs_clk->min_rate) {\r
- rate_hz = dvfs_clk->min_rate;\r
- } else if (rate_hz > dvfs_clk->max_rate) {\r
- rate_hz = dvfs_clk->max_rate;\r
- }\r
- //}\r
-\r
- /* need round rate */\r
- rate_old = clk_get_rate(clk);\r
- rate_new = clk_round_rate_nolock(clk, rate_hz);\r
- if(rate_new == rate_old)\r
- return 0;\r
-\r
- DVFS_DBG("dvfs(%s) round rate (%lu)(rount %lu) old (%lu)\n",\r
- dvfs_clk->name, rate_hz, rate_new, rate_old);\r
-\r
- /* find the clk corresponding voltage */\r
- if (0 != dvfs_clk_get_ref_volt(dvfs_clk, rate_new / 1000, &clk_fv)) {\r
- DVFS_ERR("dvfs(%s) rate %luhz is larger,not support\n", dvfs_clk->name, rate_hz);\r
- return -1;\r
- }\r
- clk_volt_store = dvfs_clk->set_volt;\r
- dvfs_clk->set_volt = clk_fv.index;\r
- volt_new = dvfs_vd_get_newvolt_byclk(dvfs_clk);\r
- DVFS_DBG("%s,%s,new rate=%lu(was=%lu),new volt=%lu,(was=%d)\n",__FUNCTION__,dvfs_clk->name,rate_new,\r
- rate_old,volt_new,dvfs_clk->vd->cur_volt);\r
-\r
- /* if up the rate */\r
- if (rate_new > rate_old) {\r
- ret = dvfs_scale_volt_direct(dvfs_clk->vd, volt_new);\r
- if (ret < 0)\r
- goto fail_roll_back;\r
- }\r
-\r
- /* scale rate */\r
- if (dvfs_clk->clk_dvfs_target) {\r
- ret = dvfs_clk->clk_dvfs_target(clk, rate_new, clk_set_rate_locked);\r
- } else {\r
- ret = clk_set_rate_locked(clk, rate_new);\r
- }\r
-\r
- if (ret < 0) {\r
- DVFS_ERR("%s set rate err\n", __func__);\r
- goto fail_roll_back;\r
- }\r
- dvfs_clk->set_freq = rate_new / 1000;\r
-\r
- DVFS_DBG("dvfs %s set rate %lu ok\n", dvfs_clk->name, clk_get_rate(clk));\r
-\r
- /* if down the rate */\r
- if (rate_new < rate_old) {\r
- ret = dvfs_scale_volt_direct(dvfs_clk->vd, volt_new);\r
- if (ret < 0)\r
- goto out;\r
- }\r
-\r
- return ret;\r
-fail_roll_back:\r
- dvfs_clk->set_volt = clk_volt_store;\r
-out:\r
- return -1;\r
-}\r
-\r
-\r
-#else\r
-\r
-#ifdef CONFIG_ARCH_RK3188\r
-static int g_arm_high_logic = 50 * 1000;\r
-static int g_logic_high_arm = 100 * 1000;\r
-#else\r
-static int g_arm_high_logic = 150 * 1000;\r
-static int g_logic_high_arm = 100 * 1000;\r
-#endif\r
-\r
-\r
-#ifdef CONFIG_ARCH_RK3188\r
-static struct cpufreq_frequency_table arm_high_logic_table[] = {\r
- {.frequency = 1416 * DVFS_KHZ, .index = 25 * DVFS_MV},\r
- {.frequency = 1608 * DVFS_KHZ, .index = 25 * DVFS_MV},\r
- {.frequency = CPUFREQ_TABLE_END},\r
-};\r
-\r
-static struct cpufreq_frequency_table logic_high_arm_table[] = {\r
- {.frequency = 1008 * DVFS_KHZ, .index = 150 * DVFS_MV},\r
- {.frequency = 1608 * DVFS_KHZ, .index = 75 * DVFS_MV},\r
- {.frequency = CPUFREQ_TABLE_END},\r
-};\r
-#else\r
-static struct cpufreq_frequency_table arm_high_logic_table[] = {\r
- {.frequency = 1416 * DVFS_KHZ, .index = 50 * DVFS_MV},\r
- {.frequency = 1608 * DVFS_KHZ, .index = 100 * DVFS_MV},\r
- {.frequency = CPUFREQ_TABLE_END},\r
-};\r
-static struct cpufreq_frequency_table logic_high_arm_table[] = {\r
- {.frequency = 816 * DVFS_KHZ, .index = 200 * DVFS_MV},\r
- {.frequency = 1416 * DVFS_KHZ, .index = 150 * DVFS_MV},\r
- {.frequency = 1608 * DVFS_KHZ, .index = 100 * DVFS_MV},\r
-};\r
-#endif\r
-\r
-\r
-int get_arm_logic_limit(unsigned long arm_rate, int *arm_high_logic, int *logic_high_arm)\r
-{\r
- int i;\r
-\r
- for (i = 0; arm_high_logic_table[i].frequency != CPUFREQ_TABLE_END; i++) {\r
- if (arm_rate <= arm_high_logic_table[i].frequency) {\r
- *arm_high_logic = arm_high_logic_table[i].index;\r
- break;\r
- }\r
- }\r
-\r
- if (arm_high_logic_table[i].frequency == CPUFREQ_TABLE_END) {\r
- *arm_high_logic = arm_high_logic_table[i-1].index;\r
- }\r
-\r
- for (i = 0; logic_high_arm_table[i].frequency != CPUFREQ_TABLE_END; i++) {\r
- if (arm_rate <= logic_high_arm_table[i].frequency) {\r
- *logic_high_arm = logic_high_arm_table[i].index;\r
- break;\r
- }\r
- }\r
- if (logic_high_arm_table[i].frequency == CPUFREQ_TABLE_END)\r
- *logic_high_arm = logic_high_arm_table[i-1].index;\r
-\r
- return 0;\r
-}\r
-\r
-static struct clk_node *dvfs_clk_cpu;\r
-static struct vd_node vd_core;\r
-int dvfs_target_cpu(struct clk *clk, unsigned long rate_hz)\r
-{\r
- struct clk_node *dvfs_clk;\r
- int volt_new = 0, volt_dep_new = 0, clk_volt_store = 0;\r
- struct cpufreq_frequency_table clk_fv;\r
- int ret = 0;\r
- unsigned long rate_new, rate_old;\r
- int cur_arm_high_logic, cur_logic_high_arm;\r
-\r
- if (!clk) {\r
- DVFS_ERR("%s is not a clk\n", __func__);\r
- return -1;\r
- }\r
- dvfs_clk = clk_get_dvfs_info(clk);\r
- DVFS_DBG("enter %s: clk(%s) rate = %lu Hz\n", __func__, dvfs_clk->name, rate_hz);\r
-\r
- if (!dvfs_clk || dvfs_clk->vd == NULL || IS_ERR_OR_NULL(dvfs_clk->vd->regulator)) {\r
- DVFS_ERR("dvfs(%s) is not register regulator\n", dvfs_clk->name);\r
- return -1;\r
- }\r
-\r
- if (dvfs_clk->vd->volt_set_flag == DVFS_SET_VOLT_FAILURE) {\r
- /* It means the last time set voltage error */\r
- ret = dvfs_reset_volt(dvfs_clk->vd);\r
- if (ret < 0) {\r
- return -1;\r
- }\r
- }\r
-\r
- /* Check limit rate */\r
- //if (dvfs_clk->freq_limit_en) {\r
- if (rate_hz < dvfs_clk->min_rate) {\r
- rate_hz = dvfs_clk->min_rate;\r
- } else if (rate_hz > dvfs_clk->max_rate) {\r
- rate_hz = dvfs_clk->max_rate;\r
- }\r
- //}\r
-\r
- /* need round rate */\r
- rate_old = clk_get_rate(clk);\r
- rate_new = clk_round_rate_nolock(clk, rate_hz);\r
- if(rate_new == rate_old)\r
- return 0;\r
-\r
- DVFS_DBG("dvfs(%s) round rate (%lu)(rount %lu) old (%lu)\n",\r
- dvfs_clk->name, rate_hz, rate_new, rate_old);\r
-\r
- /* find the clk corresponding voltage */\r
- if (0 != dvfs_clk_get_ref_volt(dvfs_clk, rate_new / 1000, &clk_fv)) {\r
- DVFS_ERR("dvfs(%s) rate %luhz is larger,not support\n", dvfs_clk->name, rate_hz);\r
- return -1;\r
- }\r
- clk_volt_store = dvfs_clk->set_volt;\r
- dvfs_clk->set_volt = clk_fv.index;\r
- volt_new = dvfs_vd_get_newvolt_byclk(dvfs_clk);\r
-\r
- /* if up the rate */\r
- if (rate_new > rate_old) {\r
- if (!list_empty(&dvfs_clk->depend_list)) {\r
- // update depend's req_volt\r
- ret = dvfs_get_depend_volt(dvfs_clk, &vd_core, rate_new);\r
- if (ret <= 0)\r
- goto fail_roll_back;\r
- }\r
- volt_dep_new = dvfs_vd_get_newvolt_bypd(&vd_core);\r
- if (volt_dep_new <= 0)\r
- goto fail_roll_back;\r
-\r
- cur_arm_high_logic = g_arm_high_logic;\r
- cur_logic_high_arm = g_logic_high_arm;\r
-\r
-#ifdef CONFIG_ARCH_RK3188\r
- get_arm_logic_limit(rate_new / 1000, &g_arm_high_logic, &g_logic_high_arm);\r
-#endif\r
-\r
- ret = dvfs_scale_volt_bystep(dvfs_clk->vd, &vd_core, volt_new, volt_dep_new,\r
- cur_arm_high_logic, cur_logic_high_arm, g_arm_high_logic, g_logic_high_arm);\r
- if (ret < 0)\r
- goto fail_roll_back;\r
-\r
- }\r
-\r
- /* scale rate */\r
- if (dvfs_clk->clk_dvfs_target) {\r
- ret = dvfs_clk->clk_dvfs_target(clk, rate_new, clk_set_rate_locked);\r
- } else {\r
- ret = clk_set_rate_locked(clk, rate_new);\r
- }\r
-\r
- if (ret < 0) {\r
- DVFS_ERR("%s set rate err\n", __func__);\r
- goto fail_roll_back;\r
- }\r
- dvfs_clk->set_freq = rate_new / 1000;\r
-\r
- DVFS_DBG("dvfs %s set rate %lu ok\n", dvfs_clk->name, clk_get_rate(clk));\r
-\r
- /* if down the rate */\r
- if (rate_new < rate_old) {\r
- if (!list_empty(&dvfs_clk->depend_list)) {\r
- // update depend's req_volt\r
- ret = dvfs_get_depend_volt(dvfs_clk, &vd_core, rate_new);\r
- if (ret <= 0)\r
- goto out;\r
- }\r
-\r
- volt_dep_new = dvfs_vd_get_newvolt_bypd(&vd_core);\r
- if (volt_dep_new <= 0)\r
- goto out;\r
-\r
-#ifdef CONFIG_ARCH_RK3188\r
- get_arm_logic_limit(rate_new / 1000, &g_arm_high_logic, &g_logic_high_arm);\r
-#endif\r
- cur_arm_high_logic = g_arm_high_logic;\r
- cur_logic_high_arm = g_logic_high_arm;\r
-\r
- ret = dvfs_scale_volt_bystep(dvfs_clk->vd, &vd_core, volt_new, volt_dep_new,\r
- cur_arm_high_logic, cur_logic_high_arm, g_arm_high_logic, g_logic_high_arm);\r
- if (ret < 0)\r
- goto out;\r
-\r
- }\r
-\r
- return ret;\r
-fail_roll_back:\r
- dvfs_clk->set_volt = clk_volt_store;\r
- ret = dvfs_get_depend_volt(dvfs_clk, &vd_core, rate_old);\r
- if (ret <= 0) {\r
- DVFS_ERR("%s dvfs_get_depend_volt error when roll back!\n", __func__);\r
- }\r
-out:\r
- return -1;\r
-}\r
-\r
-int dvfs_target_core(struct clk *clk, unsigned long rate_hz)\r
-{\r
- struct clk_node *dvfs_clk;\r
- int volt_new = 0, volt_dep_new = 0, clk_volt_store = 0;\r
- struct cpufreq_frequency_table clk_fv;\r
- int ret = 0;\r
- unsigned long rate_new, rate_old;\r
-\r
- if (!clk) {\r
- DVFS_ERR("%s is not a clk\n", __func__);\r
- return -1;\r
- }\r
- dvfs_clk = clk_get_dvfs_info(clk);\r
- DVFS_DBG("enter %s: clk(%s) rate = %lu Hz\n", __func__, dvfs_clk->name, rate_hz);\r
-\r
- if (!dvfs_clk || dvfs_clk->vd == NULL || IS_ERR_OR_NULL(dvfs_clk->vd->regulator)) {\r
- DVFS_ERR("dvfs(%s) is not register regulator\n", dvfs_clk->name);\r
- return -1;\r
- }\r
-\r
- if (dvfs_clk->vd->volt_set_flag == DVFS_SET_VOLT_FAILURE) {\r
- /* It means the last time set voltage error */\r
- ret = dvfs_reset_volt(dvfs_clk->vd);\r
- if (ret < 0) {\r
- return -1;\r
- }\r
- }\r
-\r
- /* Check limit rate */\r
- //if (dvfs_clk->freq_limit_en) {\r
- if (rate_hz < dvfs_clk->min_rate) {\r
- rate_hz = dvfs_clk->min_rate;\r
- } else if (rate_hz > dvfs_clk->max_rate) {\r
- rate_hz = dvfs_clk->max_rate;\r
- }\r
- //}\r
-\r
- /* need round rate */\r
- rate_old = clk_get_rate(clk);\r
- rate_new = clk_round_rate_nolock(clk, rate_hz);\r
- if(rate_new == rate_old)\r
- return 0;\r
- DVFS_DBG("dvfs(%s) round rate (%lu)(rount %lu) old (%lu)\n",\r
- dvfs_clk->name, rate_hz, rate_new, rate_old);\r
-\r
- /* find the clk corresponding voltage */\r
- if (0 != dvfs_clk_get_ref_volt(dvfs_clk, rate_new / 1000, &clk_fv)) {\r
- DVFS_ERR("dvfs(%s) rate %luhz is larger,not support\n", dvfs_clk->name, rate_hz);\r
- return -1;\r
- }\r
- clk_volt_store = dvfs_clk->set_volt;\r
- dvfs_clk->set_volt = clk_fv.index;\r
- volt_new = dvfs_vd_get_newvolt_byclk(dvfs_clk);\r
-\r
- /* if up the rate */\r
- if (rate_new > rate_old) {\r
- DVFS_DBG("-----------------------------rate_new > rate_old\n");\r
- volt_dep_new = dvfs_vd_get_newvolt_byclk(dvfs_clk_cpu);\r
-\r
- if (volt_dep_new < 0)\r
- goto fail_roll_back;\r
- ret = dvfs_scale_volt_bystep(dvfs_clk->vd, dvfs_clk_cpu->vd, volt_new, volt_dep_new,\r
- g_logic_high_arm, g_arm_high_logic, g_logic_high_arm, g_arm_high_logic);\r
- if (ret < 0)\r
- goto fail_roll_back;\r
- }\r
-\r
- /* scale rate */\r
- if (dvfs_clk->clk_dvfs_target) {\r
- ret = dvfs_clk->clk_dvfs_target(clk, rate_new, clk_set_rate_locked);\r
- } else {\r
- ret = clk_set_rate_locked(clk, rate_new);\r
- }\r
-\r
- if (ret < 0) {\r
- DVFS_ERR("%s set rate err\n", __func__);\r
- goto fail_roll_back;\r
- }\r
- dvfs_clk->set_freq = rate_new / 1000;\r
-\r
- DVFS_DBG("dvfs %s set rate %lu ok\n", dvfs_clk->name, clk_get_rate(clk));\r
-\r
- /* if down the rate */\r
- if (rate_new < rate_old) {\r
- DVFS_DBG("-----------------------------rate_new < rate_old\n");\r
- volt_dep_new = dvfs_vd_get_newvolt_byclk(dvfs_clk_cpu);\r
-\r
- if (volt_dep_new < 0)\r
- goto out;\r
- ret = dvfs_scale_volt_bystep(dvfs_clk->vd, dvfs_clk_cpu->vd, volt_new, volt_dep_new,\r
- g_logic_high_arm, g_arm_high_logic, g_logic_high_arm, g_arm_high_logic);\r
- if (ret < 0)\r
- goto out;\r
- }\r
-\r
- return ret;\r
-fail_roll_back:\r
- dvfs_clk->set_volt = clk_volt_store;\r
- ret = dvfs_get_depend_volt(dvfs_clk, &vd_core, rate_old);\r
- if (ret <= 0) {\r
- DVFS_ERR("%s dvfs_get_depend_volt error when roll back!\n", __func__);\r
- }\r
-\r
-out:\r
- return -1;\r
-}\r
-\r
-\r
-#endif\r
-/*****************************init**************************/\r
-/**\r
- * rate must be raising sequence\r
- */\r
-static struct cpufreq_frequency_table cpu_dvfs_table[] = {\r
- // {.frequency = 48 * DVFS_KHZ, .index = 920*DVFS_MV},\r
- // {.frequency = 126 * DVFS_KHZ, .index = 970 * DVFS_MV},\r
- // {.frequency = 252 * DVFS_KHZ, .index = 1040 * DVFS_MV},\r
- // {.frequency = 504 * DVFS_KHZ, .index = 1050 * DVFS_MV},\r
- {.frequency = 816 * DVFS_KHZ, .index = 1050 * DVFS_MV},\r
- // {.frequency = 1008 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
- {.frequency = CPUFREQ_TABLE_END},\r
-};\r
-\r
-static struct cpufreq_frequency_table ddr_dvfs_table[] = {\r
- // {.frequency = 100 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
- {.frequency = 200 * DVFS_KHZ, .index = 1000 * DVFS_MV},\r
- {.frequency = 300 * DVFS_KHZ, .index = 1050 * DVFS_MV},\r
- {.frequency = 400 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
- {.frequency = 500 * DVFS_KHZ, .index = 1150 * DVFS_MV},\r
- {.frequency = 600 * DVFS_KHZ, .index = 1200 * DVFS_MV},\r
- {.frequency = CPUFREQ_TABLE_END},\r
-};\r
-\r
-static struct cpufreq_frequency_table gpu_dvfs_table[] = {\r
- {.frequency = 90 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
- {.frequency = 180 * DVFS_KHZ, .index = 1150 * DVFS_MV},\r
- {.frequency = 300 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
- {.frequency = 400 * DVFS_KHZ, .index = 1150 * DVFS_MV},\r
- {.frequency = 500 * DVFS_KHZ, .index = 1200 * DVFS_MV},\r
- {.frequency = CPUFREQ_TABLE_END},\r
-};\r
-\r
-static struct cpufreq_frequency_table peri_aclk_dvfs_table[] = {\r
- {.frequency = 100 * DVFS_KHZ, .index = 1000 * DVFS_MV},\r
- {.frequency = 200 * DVFS_KHZ, .index = 1050 * DVFS_MV},\r
- {.frequency = 300 * DVFS_KHZ, .index = 1070 * DVFS_MV},\r
- {.frequency = 500 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
- {.frequency = CPUFREQ_TABLE_END},\r
-};\r
-\r
-static struct cpufreq_frequency_table dep_cpu2core_table[] = {\r
- // {.frequency = 252 * DVFS_KHZ, .index = 1025 * DVFS_MV},\r
- // {.frequency = 504 * DVFS_KHZ, .index = 1025 * DVFS_MV},\r
- {.frequency = 816 * DVFS_KHZ, .index = 1050 * DVFS_MV},//logic 1.050V\r
- // {.frequency = 1008 * DVFS_KHZ,.index = 1050 * DVFS_MV},\r
- // {.frequency = 1200 * DVFS_KHZ,.index = 1050 * DVFS_MV},\r
- // {.frequency = 1272 * DVFS_KHZ,.index = 1050 * DVFS_MV},//logic 1.050V\r
- // {.frequency = 1416 * DVFS_KHZ,.index = 1100 * DVFS_MV},//logic 1.100V\r
- // {.frequency = 1512 * DVFS_KHZ,.index = 1125 * DVFS_MV},//logic 1.125V\r
- // {.frequency = 1608 * DVFS_KHZ,.index = 1175 * DVFS_MV},//logic 1.175V\r
- {.frequency = CPUFREQ_TABLE_END},\r
-};\r
-\r
-static struct vd_node vd_cpu = {\r
- .name = "vd_cpu",\r
- .regulator_name = "vdd_cpu",\r
- .volt_set_flag = DVFS_SET_VOLT_FAILURE,\r
-#ifdef NO_VOLT_DIFF\r
- .vd_dvfs_target = dvfs_target,\r
-#else\r
- .vd_dvfs_target = dvfs_target_cpu,\r
-#endif\r
-};\r
-\r
-static struct vd_node vd_core = {\r
- .name = "vd_core",\r
- .regulator_name = "vdd_core",\r
- .volt_set_flag = DVFS_SET_VOLT_FAILURE,\r
-#ifdef NO_VOLT_DIFF\r
- .vd_dvfs_target = dvfs_target,\r
-#else\r
- .vd_dvfs_target = dvfs_target_core,\r
-#endif\r
-\r
-};\r
-\r
-static struct vd_node vd_rtc = {\r
- .name = "vd_rtc",\r
- .regulator_name = "vdd_rtc",\r
- .volt_set_flag = DVFS_SET_VOLT_FAILURE,\r
- .vd_dvfs_target = NULL,\r
-};\r
-\r
-static struct vd_node *rk30_vds[] = {&vd_cpu, &vd_core, &vd_rtc};\r
-\r
-static struct pd_node pd_a9_0 = {\r
- .name = "pd_a9_0",\r
- .vd = &vd_cpu,\r
-};\r
-static struct pd_node pd_a9_1 = {\r
- .name = "pd_a9_1",\r
- .vd = &vd_cpu,\r
-};\r
-static struct pd_node pd_a9_2 = {\r
- .name = "pd_a9_2",\r
- .vd = &vd_cpu,\r
-};\r
-static struct pd_node pd_a9_3 = {\r
- .name = "pd_a9_3",\r
- .vd = &vd_cpu,\r
-};\r
-\r
-static struct pd_node pd_debug = {\r
- .name = "pd_debug",\r
- .vd = &vd_cpu,\r
-};\r
-static struct pd_node pd_scu = {\r
- .name = "pd_scu",\r
- .vd = &vd_cpu,\r
-};\r
-static struct pd_node pd_video = {\r
- .name = "pd_video",\r
- .vd = &vd_core,\r
-};\r
-static struct pd_node pd_vio = {\r
- .name = "pd_vio",\r
- .vd = &vd_core,\r
-};\r
-static struct pd_node pd_gpu = {\r
- .name = "pd_gpu",\r
- .vd = &vd_core,\r
-};\r
-static struct pd_node pd_peri = {\r
- .name = "pd_peri",\r
- .vd = &vd_core,\r
-};\r
-static struct pd_node pd_cpu = {\r
- .name = "pd_cpu",\r
- .vd = &vd_core,\r
-};\r
-static struct pd_node pd_alive = {\r
- .name = "pd_alive",\r
- .vd = &vd_core,\r
-};\r
-static struct pd_node pd_rtc = {\r
- .name = "pd_rtc",\r
- .vd = &vd_rtc,\r
-};\r
-#define LOOKUP_PD(_ppd) \\r
-{ \\r
- .pd = _ppd, \\r
-}\r
-static struct pd_node_lookup rk30_pds[] = {\r
- LOOKUP_PD(&pd_a9_0),\r
- LOOKUP_PD(&pd_a9_1),\r
- LOOKUP_PD(&pd_a9_2),\r
- LOOKUP_PD(&pd_a9_3),\r
- LOOKUP_PD(&pd_debug),\r
- LOOKUP_PD(&pd_scu),\r
- LOOKUP_PD(&pd_video),\r
- LOOKUP_PD(&pd_vio),\r
- LOOKUP_PD(&pd_gpu),\r
- LOOKUP_PD(&pd_peri),\r
- LOOKUP_PD(&pd_cpu),\r
- LOOKUP_PD(&pd_alive),\r
- LOOKUP_PD(&pd_rtc),\r
-};\r
-\r
-#define CLK_PDS(_ppd) \\r
-{ \\r
- .pd = _ppd, \\r
-}\r
-\r
-static struct pds_list cpu_pds[] = {\r
- CLK_PDS(&pd_a9_0),\r
- CLK_PDS(&pd_a9_1),\r
- CLK_PDS(&pd_a9_2),\r
- CLK_PDS(&pd_a9_3),\r
- CLK_PDS(NULL),\r
-};\r
-\r
-static struct pds_list ddr_pds[] = {\r
- CLK_PDS(&pd_cpu),\r
- CLK_PDS(NULL),\r
-};\r
-\r
-static struct pds_list gpu_pds[] = {\r
- CLK_PDS(&pd_gpu),\r
- CLK_PDS(NULL),\r
-};\r
-\r
-static struct pds_list aclk_periph_pds[] = {\r
- CLK_PDS(&pd_peri),\r
- CLK_PDS(NULL),\r
-};\r
-\r
-#define RK_CLKS(_clk_name, _ppds, _dvfs_table, _dvfs_nb) \\r
-{ \\r
- .name = _clk_name, \\r
- .pds = _ppds,\\r
- .dvfs_table = _dvfs_table, \\r
- .dvfs_nb = _dvfs_nb, \\r
-}\r
-\r
-static struct clk_node rk30_clks[] = {\r
- RK_CLKS("cpu", cpu_pds, cpu_dvfs_table, &rk_dvfs_clk_notifier),\r
- RK_CLKS("ddr", ddr_pds, ddr_dvfs_table, &rk_dvfs_clk_notifier),\r
- RK_CLKS("gpu", gpu_pds, gpu_dvfs_table, &rk_dvfs_clk_notifier),\r
- RK_CLKS("aclk_periph", aclk_periph_pds, peri_aclk_dvfs_table, &rk_dvfs_clk_notifier),\r
-};\r
-\r
-#if 0\r
-#define RK_DEPPENDS(_clk_name, _pvd, _dep_table) \\r
-{ \\r
- .clk_name = _clk_name, \\r
- .dep_vd = _pvd,\\r
- .dep_table = _dep_table, \\r
-}\r
-\r
-static struct depend_lookup rk30_depends[] = {\r
-#ifndef CONFIG_ARCH_RK3188\r
- RK_DEPPENDS("cpu", &vd_core, dep_cpu2core_table),\r
-#endif\r
- //RK_DEPPENDS("gpu", &vd_cpu, NULL),\r
- //RK_DEPPENDS("gpu", &vd_cpu, NULL),\r
-};\r
-#endif\r
-static struct avs_ctr_st rk30_avs_ctr;\r
-\r
-int rk3188_dvfs_init(void)\r
-{\r
- int i = 0;\r
- for (i = 0; i < ARRAY_SIZE(rk30_vds); i++) {\r
- rk_regist_vd(rk30_vds[i]);\r
- }\r
- for (i = 0; i < ARRAY_SIZE(rk30_pds); i++) {\r
- rk_regist_pd(&rk30_pds[i]);\r
- }\r
- for (i = 0; i < ARRAY_SIZE(rk30_clks); i++) {\r
- rk_regist_clk(&rk30_clks[i]);\r
- }\r
- #if 0\r
- for (i = 0; i < ARRAY_SIZE(rk30_depends); i++) {\r
- rk_regist_depends(&rk30_depends[i]);\r
- }\r
- #endif\r
-#ifndef NO_VOLT_DIFF\r
- dvfs_clk_cpu = dvfs_get_dvfs_clk_byname("cpu");\r
-#endif\r
- avs_board_init(&rk30_avs_ctr);\r
- return 0;\r
-}\r
-\r
-\r
-\r
-/******************************rk30 avs**************************************************/\r
-static void __iomem *rk30_nandc_base=NULL;\r
-\r
-#define nandc_readl(offset) readl_relaxed(rk30_nandc_base + offset)\r
-#define nandc_writel(v, offset) do { writel_relaxed(v, rk30_nandc_base + offset); dsb(); } while (0)\r
-static u8 rk30_get_avs_val(void)\r
-{\r
- u32 nanc_save_reg[4];\r
- unsigned long flags;\r
- u32 paramet = 0;\r
- u32 count = 100;\r
- if(rk30_nandc_base==NULL) \r
- return 0;\r
- \r
- preempt_disable();\r
- local_irq_save(flags);\r
-\r
- nanc_save_reg[0] = nandc_readl(0);\r
- nanc_save_reg[1] = nandc_readl(0x130);\r
- nanc_save_reg[2] = nandc_readl(0x134);\r
- nanc_save_reg[3] = nandc_readl(0x158);\r
-\r
- nandc_writel(nanc_save_reg[0] | 0x1 << 14, 0);\r
- nandc_writel(0x5, 0x130);\r
-\r
- /* Just break lock status */\r
- nandc_writel(0x1, 0x158);\r
- nandc_writel(0x3, 0x158);\r
- nandc_writel(0x21, 0x134);\r
-\r
- while(count--) {\r
- paramet = nandc_readl(0x138);\r
- if((paramet & 0x1))\r
- break;\r
- udelay(1);\r
- };\r
- paramet = (paramet >> 1) & 0xff;\r
- nandc_writel(nanc_save_reg[0], 0);\r
- nandc_writel(nanc_save_reg[1], 0x130);\r
- nandc_writel(nanc_save_reg[2], 0x134);\r
- nandc_writel(nanc_save_reg[3], 0x158);\r
-\r
- local_irq_restore(flags);\r
- preempt_enable();\r
- return (u8)paramet;\r
-\r
-}\r
-\r
-void rk30_avs_init(void)\r
-{\r
- rk30_nandc_base = ioremap(RK30_NANDC_PHYS, RK30_NANDC_SIZE);\r
-}\r
-static struct avs_ctr_st rk30_avs_ctr= {\r
- .avs_init =rk30_avs_init,\r
- .avs_get_val = rk30_get_avs_val,\r
-};\r
-\r
-\r
+++ /dev/null
-#ifndef __MACH_BOARD_H
-#define __MACH_BOARD_H
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-#include <linux/types.h>
-#include <linux/timer.h>
-#include <linux/notifier.h>
-#include <asm/setup.h>
-#include <plat/board.h>
-#include <mach/sram.h>
-#include <linux/i2c-gpio.h>
-
-
-void __init rk30_map_common_io(void);
-void __init rk30_init_irq(void);
-void __init rk30_map_io(void);
-struct machine_desc;
-void __init rk30_fixup(struct machine_desc *desc, struct tag *tags, char **cmdline, struct meminfo *mi);
-void __init rk30_clock_data_init(unsigned long gpll,unsigned long cpll,u32 flags);
-
-#ifdef CONFIG_RK30_PWM_REGULATOR
-void rk30_pwm_suspend_voltage_set(void);
-void rk30_pwm_resume_voltage_set(void);
-void __sramfunc rk30_pwm_logic_suspend_voltage(void);
- void __sramfunc rk30_pwm_logic_resume_voltage(void);
-#endif
-
-extern struct sys_timer rk30_timer;
-
-enum _periph_pll {
- periph_pll_1485mhz = 148500000,
- periph_pll_297mhz = 297000000,
- periph_pll_300mhz = 300000000,
- periph_pll_384mhz = 384000000,
- periph_pll_768mhz = 768000000,
- periph_pll_594mhz = 594000000,
- periph_pll_1188mhz = 1188000000, /* for box*/
-};
-enum _codec_pll {
- codec_pll_360mhz = 360000000, /* for HDMI */
- codec_pll_408mhz = 408000000,
- codec_pll_456mhz = 456000000,
- codec_pll_504mhz = 504000000,
- codec_pll_552mhz = 552000000, /* for HDMI */
- codec_pll_594mhz = 594000000, /* for HDMI */
- codec_pll_600mhz = 600000000,
- codec_pll_742_5khz = 742500000,
- codec_pll_768mhz = 768000000,
- codec_pll_798mhz = 798000000,
- codec_pll_1188mhz = 1188000000,
- codec_pll_1200mhz = 1200000000,
-};
-
-//has extern 27mhz
-#define CLK_FLG_EXT_27MHZ (1<<0)
-//max i2s rate
-#define CLK_FLG_MAX_I2S_12288KHZ (1<<1)
-#define CLK_FLG_MAX_I2S_22579_2KHZ (1<<2)
-#define CLK_FLG_MAX_I2S_24576KHZ (1<<3)
-#define CLK_FLG_MAX_I2S_49152KHZ (1<<4)
-//uart 1m\3m
-#define CLK_FLG_UART_1_3M (1<<5)
-#define CLK_CPU_HPCLK_11 (1<<6)
-
-
-#ifdef CONFIG_RK29_VMAC
-
-#define RK30_CLOCKS_DEFAULT_FLAGS (CLK_FLG_MAX_I2S_12288KHZ/*|CLK_FLG_EXT_27MHZ*/)
-#define periph_pll_default periph_pll_300mhz
-#define codec_pll_default codec_pll_1188mhz
-
-#else
-
-
-#define RK30_CLOCKS_DEFAULT_FLAGS (CLK_FLG_MAX_I2S_12288KHZ/*|CLK_FLG_EXT_27MHZ*/)
-
-#define codec_pll_default codec_pll_594mhz
-#define periph_pll_default periph_pll_768mhz
-
-//#define codec_pll_default codec_pll_798mhz
-//#define periph_pll_default periph_pll_594mhz
-
-#endif
-
-
-
-
-
-
-#endif
+++ /dev/null
-#include <plat/clkdev.h>
+++ /dev/null
-#include <plat/clock.h>
+++ /dev/null
-#include <plat/cpu.h>
+++ /dev/null
-#ifndef __MACH_CPU_AXI_H
-#define __MACH_CPU_AXI_H
-
-#include <plat/cpu_axi.h>
-
-#define CPU_AXI_BUS_BASE RK30_CPU_AXI_BUS_BASE
-
-#define CPU_AXI_DMAC_QOS_BASE (CPU_AXI_BUS_BASE + 0x1000)
-#define CPU_AXI_CPU0_QOS_BASE (CPU_AXI_BUS_BASE + 0x2000)
-#define CPU_AXI_CPU1R_QOS_BASE (CPU_AXI_BUS_BASE + 0x2080)
-#define CPU_AXI_CPU1W_QOS_BASE (CPU_AXI_BUS_BASE + 0x2100)
-#define CPU_AXI_PERI_QOS_BASE (CPU_AXI_BUS_BASE + 0x4000)
-#define CPU_AXI_GPU_QOS_BASE (CPU_AXI_BUS_BASE + 0x5000)
-#define CPU_AXI_VPU_QOS_BASE (CPU_AXI_BUS_BASE + 0x6000)
-#define CPU_AXI_LCDC0_QOS_BASE (CPU_AXI_BUS_BASE + 0x7000)
-#define CPU_AXI_CIF0_QOS_BASE (CPU_AXI_BUS_BASE + 0x7080)
-#define CPU_AXI_IPP_QOS_BASE (CPU_AXI_BUS_BASE + 0x7100)
-#define CPU_AXI_LCDC1_QOS_BASE (CPU_AXI_BUS_BASE + 0x7180)
-#define CPU_AXI_CIF1_QOS_BASE (CPU_AXI_BUS_BASE + 0x7200)
-#define CPU_AXI_RGA_QOS_BASE (CPU_AXI_BUS_BASE + 0x7280)
-
-#endif
+++ /dev/null
-enum rk_plls_id {
- APLL_ID = 0,
- DPLL_ID,
- CPLL_ID,
- GPLL_ID,
- END_PLL_ID,
-};
-
-/*****cru reg offset*****/
-
-#define CRU_MODE_CON 0x40
-#define CRU_CLKSEL_CON 0x44
-#define CRU_CLKGATE_CON 0xd0
-#define CRU_GLB_SRST_FST 0x100
-#define CRU_GLB_SRST_SND 0x104
-#define CRU_SOFTRST_CON 0x110
-
-#define PLL_CONS(id, i) ((id) * 0x10 + ((i) * 4))
-
-#define CRU_CLKSELS_CON_CNT (35)
-#define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON + ((i) * 4))
-
-#define CRU_CLKGATES_CON_CNT (10)
-#define CRU_CLKGATES_CON(i) (CRU_CLKGATE_CON + ((i) * 4))
-
-#define CRU_SOFTRSTS_CON_CNT (9)
-#define CRU_SOFTRSTS_CON(i) (CRU_SOFTRST_CON + ((i) * 4))
-
-#define CRU_MISC_CON (0x134)
-#define CRU_GLB_CNT_TH (0x140)
-
-/********************************************************************/
-#define CRU_GET_REG_BITS_VAL(reg,bits_shift, msk) (((reg) >> (bits_shift))&(msk))
-#define CRU_W_MSK(bits_shift, msk) ((msk) << ((bits_shift) + 16))
-#define CRU_SET_BITS(val,bits_shift, msk) (((val)&(msk)) << (bits_shift))
-
-#define CRU_W_MSK_SETBITS(val,bits_shift,msk) (CRU_W_MSK(bits_shift, msk)|CRU_SET_BITS(val,bits_shift, msk))
-
-/*******************PLL CON0 BITS***************************/
-
-#define PLL_CLKFACTOR_SET(val, shift, msk) \
- ((((val) - 1) & (msk)) << (shift))
-
-#define PLL_CLKFACTOR_GET(reg, shift, msk) \
- ((((reg) >> (shift)) & (msk)) + 1)
-
-#define PLL_OD_MSK (0x3f)
-#define PLL_OD_SHIFT (0x0)
-
-#define PLL_CLKOD(val) PLL_CLKFACTOR_SET(val, PLL_OD_SHIFT, PLL_OD_MSK)
-#define PLL_NO(reg) PLL_CLKFACTOR_GET(reg, PLL_OD_SHIFT, PLL_OD_MSK)
-
-#define PLL_NO_SHIFT(reg) PLL_CLKFACTOR_GET(reg, PLL_OD_SHIFT, PLL_OD_MSK)
-
-#define PLL_CLKOD_SET(val) (PLL_CLKOD(val) | CRU_W_MSK(PLL_OD_SHIFT, PLL_OD_MSK))
-
-#define PLL_NR_MSK (0x3f)
-#define PLL_NR_SHIFT (8)
-#define PLL_CLKR(val) PLL_CLKFACTOR_SET(val, PLL_NR_SHIFT, PLL_NR_MSK)
-#define PLL_NR(reg) PLL_CLKFACTOR_GET(reg, PLL_NR_SHIFT, PLL_NR_MSK)
-
-#define PLL_CLKR_SET(val) (PLL_CLKR(val) | CRU_W_MSK(PLL_NR_SHIFT, PLL_NR_MSK))
-
-#define PLUS_PLL_OD_MSK (0xf)
-#define PLUS_PLL_NO(reg) (PLL_NO(reg) & PLUS_PLL_OD_MSK)
-
-#define PLUS_PLL_NR_MSK (0x3f)
-#define PLUS_PLL_NR(reg) (PLL_NR(reg) & PLUS_PLL_NR_MSK)
-
-#define PLUS_PLL_CLKR_SET(val) PLL_CLKR_SET(val & PLUS_PLL_NR_MSK)
-#define PLUS_PLL_CLKOD_SET(val) PLL_CLKOD_SET(val & PLUS_PLL_OD_MSK)
-/*******************PLL CON1 BITS***************************/
-
-#define PLL_NF_MSK (0xffff)
-#define PLL_NF_SHIFT (0)
-#define PLL_CLKF(val) PLL_CLKFACTOR_SET(val, PLL_NF_SHIFT, PLL_NF_MSK)
-#define PLL_NF(reg) PLL_CLKFACTOR_GET(reg, PLL_NF_SHIFT, PLL_NF_MSK)
-#define PLL_CLKF_SET(val) (PLL_CLKF(val) | CRU_W_MSK(PLL_NF_SHIFT, PLL_NF_MSK))
-
-#define PLUS_PLL_NF_MSK (0x1fff)
-#define PLUS_PLL_NF(reg) (PLL_NF(reg) & PLUS_PLL_NF_MSK)
-#define PLUS_PLL_CLKF_SET(val) PLL_CLKF_SET(val & PLUS_PLL_NF_MSK)
-/*******************PLL CON2 BITS***************************/
-
-#define PLL_BWADJ_MSK (0xfff)
-#define PLL_BWADJ_SHIFT (0)
-#define PLL_CLK_BWADJ_SET(val) ((val) | CRU_W_MSK(PLL_BWADJ_SHIFT, PLL_BWADJ_MSK))
-
-/*******************PLL CON3 BITS***************************/
-
-#define PLL_RESET_MSK (1 << 5)
-#define PLL_RESET_W_MSK (PLL_RESET_MSK << 16)
-#define PLL_RESET (1 << 5)
-#define PLL_RESET_RESUME (0 << 5)
-
-#define PLL_BYPASS_MSK (1 << 0)
-#define PLL_BYPASS (1 << 0)
-#define PLL_NO_BYPASS (0 << 0)
-
-#define PLL_PWR_DN_MSK (1 << 1)
-#define PLL_PWR_DN_W_MSK (PLL_PWR_DN_MSK << 16)
-#define PLL_PWR_DN (1 << 1)
-#define PLL_PWR_ON (0 << 1)
-
-#define PLL_STANDBY_MSK (1 << 2)
-#define PLL_STANDBY (1 << 2)
-#define PLL_NO_STANDBY (0 << 2)
-/*******************CLKSEL0 BITS***************************/
-//core preiph div
-#define CORE_PERIPH_W_MSK (3 << 22)
-#define CORE_PERIPH_MSK (3 << 6)
-#define CORE_PERIPH_2 (0 << 6)
-#define CORE_PERIPH_4 (1 << 6)
-#define CORE_PERIPH_8 (2 << 6)
-#define CORE_PERIPH_16 (3 << 6)
-//arm clk pll sel
-#define CORE_SEL_PLL_MSK (1 << 8)
-#define CORE_SEL_PLL_W_MSK (1 << 24)
-#define CORE_SEL_APLL (0 << 8)
-#define CORE_SEL_GPLL (1 << 8)
-
-#define CORE_CLK_DIV_W_MSK (0x1F << 25)
-#define CORE_CLK_DIV_MSK (0x1F << 9)
-#define CORE_CLK_DIV(i) ((((i) - 1) & 0x1F) << 9)
-
-#define CPU_SEL_PLL_MSK (1 << 5)
-#define CPU_SEL_PLL_W_MSK (1 << 21)
-#define CPU_SEL_APLL (0 << 5)
-#define CPU_SEL_GPLL (1 << 5)
-
-#define CPU_CLK_DIV_W_MSK (0x1F << 16)
-#define CPU_CLK_DIV_MSK (0x1F)
-#define CPU_CLK_DIV(i) (((i) - 1) & 0x1F)
-
-/*******************CLKSEL1 BITS***************************/
-//aclk div
-#define GET_CORE_ACLK_VAL(reg) ((reg)>=4 ?8:((reg)+1))
-
-#define CORE_ACLK_W_MSK (7 << 19)
-#define CORE_ACLK_MSK (7 << 3)
-#define CORE_ACLK_11 (0 << 3)
-#define CORE_ACLK_21 (1 << 3)
-#define CORE_ACLK_31 (2 << 3)
-#define CORE_ACLK_41 (3 << 3)
-#define CORE_ACLK_81 (4 << 3)
-//hclk div
-#define ACLK_HCLK_W_MSK (3 << 24)
-#define ACLK_HCLK_MSK (3 << 8)
-#define ACLK_HCLK_11 (0 << 8)
-#define ACLK_HCLK_21 (1 << 8)
-#define ACLK_HCLK_41 (2 << 8)
-// pclk div
-#define ACLK_PCLK_W_MSK (3 << 28)
-#define ACLK_PCLK_MSK (3 << 12)
-#define ACLK_PCLK_11 (0 << 12)
-#define ACLK_PCLK_21 (1 << 12)
-#define ACLK_PCLK_41 (2 << 12)
-#define ACLK_PCLK_81 (3 << 12)
-// ahb2apb div
-#define AHB2APB_W_MSK (3 << 30)
-#define AHB2APB_MSK (3 << 14)
-#define AHB2APB_11 (0 << 14)
-#define AHB2APB_21 (1 << 14)
-#define AHB2APB_41 (2 << 14)
-
-/*******************MODE BITS***************************/
-
-#define PLL_MODE_MSK(id) (0x3 << ((id) * 4))
-#define PLL_MODE_SLOW(id) ((0x0<<((id)*4))|(0x3<<(16+(id)*4)))
-#define PLL_MODE_NORM(id) ((0x1<<((id)*4))|(0x3<<(16+(id)*4)))
-#define PLL_MODE_DEEP(id) ((0x2<<((id)*4))|(0x3<<(16+(id)*4)))
-
-/*******************clksel10***************************/
-
-#define PERI_ACLK_DIV_MASK 0x1f
-#define PERI_ACLK_DIV_W_MSK (PERI_ACLK_DIV_MASK << 16)
-#define PERI_ACLK_DIV(i) (((i) - 1) & PERI_ACLK_DIV_MASK)
-#define PERI_ACLK_DIV_OFF 0
-
-#define PERI_HCLK_DIV_MASK 0x3
-#define PERI_HCLK_DIV_OFF 8
-
-#define PERI_PCLK_DIV_MASK 0x3
-#define PERI_PCLK_DIV_OFF 12
-
-/*******************gate BITS***************************/
-
-#define CLK_GATE_CLKID(i) (16 * (i))
-#define CLK_GATE_CLKID_CONS(i) CRU_CLKGATES_CON((i) / 16)
-
-#define CLK_GATE(i) (1 << ((i)%16))
-#define CLK_UN_GATE(i) (0)
-
-#define CLK_GATE_W_MSK(i) (1 << (((i) % 16) + 16))
-
-enum cru_clk_gate {
- /* SCU CLK GATE 0 CON */
- CLK_GATE_CORE_PERIPH = CLK_GATE_CLKID(0),
- CLK_GATE_CPU_GPLL_PATH,
- CLK_GATE_DDRPHY,
- CLK_GATE_ACLK_CPU,
-
- CLK_GATE_HCLK_CPU,
- CLK_GATE_PCLK_CPU,
- CLK_GATE_ATCLK_CPU,
- CLK_GATE_ACLK_CORE,
-
- CLK_GATE_0RES8,
- CLK_GATE_I2S0_SRC,
- CLK_GATE_I2S0_FRAC,
- CLK_GATE_0RES11,
-
- CLK_GATE_0RES12,
- CLK_GATE_SPDIF_SRC,
- CLK_GATE_SPDIF_FRAC,
- CLK_GATE_TESTCLK,
-
- CLK_GATE_TIMER0 = CLK_GATE_CLKID(1),
- CLK_GATE_TIMER1,
- CLK_GATE_TIMER3,
- CLK_GATE_JTAG,
-
- CLK_GATE_ACLK_LCDC1_SRC,
- CLK_GATE_OTGPHY0,
- CLK_GATE_OTGPHY1,
- CLK_GATE_DDR_GPLL,
-
- CLK_GATE_UART0_SRC,
- CLK_GATE_UART0_FRAC_SRC,
- CLK_GATE_UART1_SRC,
- CLK_GATE_UART1_FRAC_SRC,
-
- CLK_GATE_UART2_SRC,
- CLK_GATE_UART2_FRAC_SRC,
- CLK_GATE_UART3_SRC,
- CLK_GATE_UART3_FRAC_SRC,
-
- CLK_GATE_PERIPH_SRC = CLK_GATE_CLKID(2),
- CLK_GATE_ACLK_PERIPH,
- CLK_GATE_HCLK_PERIPH,
- CLK_GATE_PCLK_PERIPH,
-
- CLK_GATE_SMC_SRC,
- CLK_GATE_MAC_SRC,
- CLK_GATE_HSADC_SRC,
- CLK_GATE_HSADC_FRAC_SRC,
-
- CLK_GATE_SARADC_SRC,
- CLK_GATE_SPI0_SRC,
- CLK_GATE_SPI1_SRC,
- CLK_GATE_MMC0_SRC,
-
- CLK_GATE_MAC_LBTEST,
- CLK_GATE_SDIO_SRC,
- CLK_GATE_EMMC_SRC,
- CLK_GATE_2RES15,
-
- CLK_GATE_ACLK_LCDC0_SRC = CLK_GATE_CLKID(3),
- CLK_GATE_DCLK_LCDC0_SRC,
- CLK_GATE_DCLK_LCDC1_SRC,
- CLK_GATE_PCLKIN_CIF0,
-
- CLK_GATE_TIMER2,
- CLK_GATE_TIMER4,
- CLK_GATE_HSICPHY_SRC,
- CLK_GATE_CIF0_OUT,
-
- CLK_GATE_TIMER5,
- CLK_GATE_ACLK_VEPU,
- CLK_GATE_HCLK_VEPU,
- CLK_GATE_ACLK_VDPU,
-
- CLK_GATE_HCLK_VDPU,
- CLK_GATE_3RES13,
- CLK_GATE_TIMER6,
- CLK_GATE_ACLK_GPU_SRC,
-
- CLK_GATE_HCLK_PERI_AXI_MATRIX = CLK_GATE_CLKID(4),
- CLK_GATE_PCLK_PERI_AXI_MATRIX,
- CLK_GATE_ACLK_CPU_PERI,
- CLK_GATE_ACLK_PERI_AXI_MATRIX,
-
- CLK_GATE_ACLK_PEI_NIU,
- CLK_GATE_HCLK_USB_PERI,
- CLK_GATE_HCLK_PERI_AHB_ARBI,
- CLK_GATE_HCLK_EMEM_PERI,
-
- CLK_GATE_HCLK_CPUBUS,
- CLK_GATE_HCLK_AHB2APB,
- CLK_GATE_ACLK_STRC_SYS,
- CLK_GATE_4RES11,
-
- CLK_GATE_ACLK_INTMEM,
- CLK_GATE_4RES13,
- CLK_GATE_HCLK_IMEM1,
- CLK_GATE_HCLK_IMEM0,
-
- CLK_GATE_ACLK_DMAC1 = CLK_GATE_CLKID(5),
- CLK_GATE_ACLK_DMAC2,
- CLK_GATE_PCLK_EFUSE,
- CLK_GATE_PCLK_TZPC,
-
- CLK_GATE_PCLK_GRF,
- CLK_GATE_PCLK_PMU,
- CLK_GATE_HCLK_ROM,
- CLK_GATE_PCLK_DDRUPCTL,
-
- CLK_GATE_ACLK_SMC,
- CLK_GATE_HCLK_NANDC,
- CLK_GATE_HCLK_SDMMC0,
- CLK_GATE_HCLK_SDIO,
-
- CLK_GATE_HCLK_EMMC,
- CLK_GATE_HCLK_OTG0,
- CLK_GATE_5RES14,
- CLK_GATE_5RES15,
-
- CLK_GATE_ACLK_LCDC0 = CLK_GATE_CLKID(6),
- CLK_GATE_HCLK_LCDC0,
- CLK_GATE_HCLK_LCDC1,
- CLK_GATE_ACLK_LCDC1,
-
- CLK_GATE_HCLK_CIF0,
- CLK_GATE_ACLK_CIF0,
- CLK_GATE_6RES6,
- CLK_GATE_6RES7,
-
- CLK_GATE_ACLK_IPP,
- CLK_GATE_HCLK_IPP,
- CLK_GATE_HCLK_RGA,
- CLK_GATE_ACLK_RGA,
-
- CLK_GATE_HCLK_VIO_BUS,
- CLK_GATE_ACLK_VIO0,
- CLK_GATE_6RES14,
- CLK_GATE_6RES15,
-
- CLK_GATE_HCLK_EMAC = CLK_GATE_CLKID(7),
- CLK_GATE_HCLK_SPDIF,
- CLK_GATE_HCLK_I2S0_2CH,
- CLK_GATE_HCLK_OTG1,
-
- CLK_GATE_HCLK_HSIC,
- CLK_GATE_HCLK_HSADC,
- CLK_GATE_HCLK_PIDF,
- CLK_GATE_PCLK_TIMER0,
-
- CLK_GATE_7RES8,
- CLK_GATE_PCLK_TIMER2, //same as RK3066B, diff list's mistake
- CLK_GATE_PCLK_PWM01,
- CLK_GATE_PCLK_PWM23,
-
- CLK_GATE_PCLK_SPI0,
- CLK_GATE_PCLK_SPI1,
- CLK_GATE_PCLK_SARADC,
- CLK_GATE_PCLK_WDT,
-
- CLK_GATE_PCLK_UART0 = CLK_GATE_CLKID(8),
- CLK_GATE_PCLK_UART1,
- CLK_GATE_PCLK_UART2,
- CLK_GATE_PCLK_UART3,
-
- CLK_GATE_PCLK_I2C0,
- CLK_GATE_PCLK_I2C1,
- CLK_GATE_PCLK_I2C2,
- CLK_GATE_PCLK_I2C3,
-
- CLK_GATE_PCLK_I2C4,
- CLK_GATE_PCLK_GPIO0,
- CLK_GATE_PCLK_GPIO1,
- CLK_GATE_PCLK_GPIO2,
-
- CLK_GATE_PCLK_GPIO3,
- CLK_GATE_ACLK_GPS,
- CLK_GATE_8RES14,
- CLK_GATE_8RES15,
-
- CLK_GATE_CLK_CORE_DBG = CLK_GATE_CLKID(9),
- CLK_GATE_PCLK_DBG,
- CLK_GATE_CLK_TRACE,
- CLK_GATE_ATCLK,
-
- CLK_GATE_CLK_L2C,
- CLK_GATE_ACLK_VIO1,
- CLK_GATE_PCLK_PUBL,
- CLK_GATE_ACLK_GPU,
-
- CLK_GATE_9RES8,
- CLK_GATE_9RES9,
- CLK_GATE_9RES10,
- CLK_GATE_9RES11,
-
- CLK_GATE_9RES12,
- CLK_GATE_9RES13,
- CLK_GATE_9RES14,
- CLK_GATE_9RES15,
-
- CLK_GATE_MAX,
-};
-
-/* for compatible with rk30xx */
-#define CLK_GATE_ACLK_CIF1 CLK_GATE_ACLK_CIF0
-#define CLK_GATE_ACLK_INTMEM0 CLK_GATE_CLK_L2C
-#define CLK_GATE_ACLK_INTMEM1 CLK_GATE_ACLK_INTMEM0
-#define CLK_GATE_ACLK_INTMEM2 CLK_GATE_ACLK_INTMEM0
-#define CLK_GATE_ACLK_INTMEM3 CLK_GATE_ACLK_INTMEM0
-
-#define SOFT_RST_ID(i) (16 * (i))
-
-enum cru_soft_reset {
- SOFT_RST_PTM_CORE2 = SOFT_RST_ID(0),
- SOFT_RST_PTM_CORE3,
- SOFT_RST_MCORE,
- SOFT_RST_CORE0,
-
- SOFT_RST_CORE1,
- SOFT_RST_CORE2,
- SOFT_RST_CORE3,
- SOFT_RST_MCORE_DBG,
-
- SOFT_RST_CORE0_DBG,
- SOFT_RST_CORE1_DBG,
- SOFT_RST_CORE2_DBG,
- SOFT_RST_CORE3_DBG,
-
- SOFT_RST_CORE0_WDT,
- SOFT_RST_CORE1_WDT,
- SOFT_RST_STRC_SYS_AXI,
- SOFT_RST_L2C,
-
- SOFT_RST_TIMER2 = SOFT_RST_ID(1),
- SOFT_RST_CPUSYS_AHB,
- SOFT_RST_1RES2,
- SOFT_RST_AHB2APB,
-
- SOFT_RST_DMA1,
- SOFT_RST_INTMEM,
- SOFT_RST_ROM,
- SOFT_RST_TIMER4,
-
- SOFT_RST_I2S,
- SOFT_RST_TIMER5,
- SOFT_RST_SPDIF,
- SOFT_RST_TIMER0,
-
- SOFT_RST_TIMER1,
- SOFT_RST_TIMER3,
- SOFT_RST_EFUSE_APB,
- SOFT_RST_TIMER6,
-
- SOFT_RST_GPIO0 = SOFT_RST_ID(2),
- SOFT_RST_GPIO1,
- SOFT_RST_GPIO2,
- SOFT_RST_GPIO3,
-
- SOFT_RST_PTM3,
- SOFT_RST_PTM3_ATB,
- SOFT_RST_2RES6,
- SOFT_RST_UART0,
-
- SOFT_RST_UART1,
- SOFT_RST_UART2,
- SOFT_RST_UART3,
- SOFT_RST_I2C0,
-
- SOFT_RST_I2C1,
- SOFT_RST_I2C2,
- SOFT_RST_I2C3,
- SOFT_RST_I2C4,
-
- SOFT_RST_PWM0 = SOFT_RST_ID(3),
- SOFT_RST_PWM1,
- SOFT_RST_DAP_PO,
- SOFT_RST_DAP,
-
- SOFT_RST_DAP_SYS,
- SOFT_RST_TPIU_ATB,
- SOFT_RST_PMU_APB,
- SOFT_RST_GRF,
-
- SOFT_RST_PMU,
- SOFT_RST_PERIPHSYS_AXI,
- SOFT_RST_PERIPHSYS_AHB,
- SOFT_RST_PERIPHSYS_APB,
-
- SOFT_RST_PERIPH_NIU,
- SOFT_RST_CPU_PERI,
- SOFT_RST_EMEM_PERI,
- SOFT_RST_USB_PERI,
-
- SOFT_RST_DMA2 = SOFT_RST_ID(4),
- SOFT_RST_SMC,
- SOFT_RST_MAC,
- SOFT_RST_GPS,
-
- SOFT_RST_NANDC,
- SOFT_RST_USBOTG0,
- SOFT_RST_USBPHY0,
- SOFT_RST_OTGC0,
-
- SOFT_RST_USBOTG1,
- SOFT_RST_USBPHY1,
- SOFT_RST_OTGC1,
- SOFT_RST_HSICPHY,
-
- SOFT_RST_HSADC,
- SOFT_RST_PIDFILTER,
- SOFT_RST_TIMER_APB,
- SOFT_RST_DDRMSCH,
-
- SOFT_RST_TZPC = SOFT_RST_ID(5),
- SOFT_RST_MMC0,
- SOFT_RST_SDIO,
- SOFT_RST_EMMC,
-
- SOFT_RST_SPI0,
- SOFT_RST_SPI1,
- SOFT_RST_WDT,
- SOFT_RST_SARADC,
-
- SOFT_RST_DDRPHY,
- SOFT_RST_DDRPHY_APB,
- SOFT_RST_DDRCTRL,
- SOFT_RST_DDRCTRL_APB,
-
- SOFT_RST_PTM2,
- SOFT_RST_DDRPHY_CTL,
- SOFT_RST_CORE2_WDT,
- SOFT_RST_CORE3_WDT,
-
- SOFT_RST_6RES0 = SOFT_RST_ID(6),
- SOFT_RST_6RES1,
- SOFT_RST_VIO0_AXI,
- SOFT_RST_VIO_BUS_AHB,
-
- SOFT_RST_LCDC0_AXI,
- SOFT_RST_LCDC0_AHB,
- SOFT_RST_LCDC0_DCLK,
- SOFT_RST_LCDC1_AXI,
-
- SOFT_RST_LCDC1_AHB,
- SOFT_RST_LCDC1_DCLK,
- SOFT_RST_IPP_AXI,
- SOFT_RST_IPP_AHB,
-
- SOFT_RST_RGA_AXI,
- SOFT_RST_RGA_AHB,
- SOFT_RST_CIF0,
- SOFT_RST_PTM2_ATB,//SOFT_RST_6RES15, NO CIF1
-
- SOFT_RST_VCODEC_AXI = SOFT_RST_ID(7),
- SOFT_RST_VCODEC_AHB,
- SOFT_RST_VIO1_AXI,
- SOFT_RST_CPU_VCODEC,
-
- SOFT_RST_VCODEC_NIU_AXI,
- SOFT_RST_HSIC_AHB,
- SOFT_RST_CTI2,
- SOFT_RST_CTI2_APB,
-
- SOFT_RST_GPU_CORE,
- SOFT_RST_GPU_BRIDGE_AXI,
- SOFT_RST_GPU_NIU_AXI,
- SOFT_RST_CTI3,
-
- SOFT_RST_CTI3_APB,
- SOFT_RST_TFUN_ATB,
- SOFT_RST_TFUN_APB,
- SOFT_RST_CTI4_APB,
-
- SOFT_RST_TPIU_APB = SOFT_RST_ID(8),
- SOFT_RST_TRACE,
- SOFT_RST_CORE_DBG,
- SOFT_RST_DBG_APB,
-
- SOFT_RST_CTI0,
- SOFT_RST_CTI0_APB,
- SOFT_RST_CTI1,
- SOFT_RST_CTI1_APB,
-
- SOFT_RST_PTM_CORE0,
- SOFT_RST_PTM_CORE1,
- SOFT_RST_PTM0,
- SOFT_RST_PTM0_ATB,
-
- SOFT_RST_PTM1,
- SOFT_RST_PTM1_ATB,
- SOFT_RST_CTM,
- SOFT_RST_TS,
-
- SOFT_RST_MAX,
-};
-
-/*****cru reg end*****/
-
-static inline void cru_set_soft_reset(enum cru_soft_reset idx, bool on)
-{
- const void __iomem *reg = RK30_CRU_BASE + CRU_SOFTRSTS_CON(idx >> 4);
- u32 val = on ? 0x10001U << (idx & 0xf) : 0x10000U << (idx & 0xf);
- writel_relaxed(val, reg);
- dsb();
-}
+++ /dev/null
-#ifndef __MACH_CRU_H
-#define __MACH_CRU_H
-#include <mach/cru-rk3188.h>
-#endif
+++ /dev/null
-#include <plat/ddr.h>
+++ /dev/null
-#include <plat/debug-macro.S>
+++ /dev/null
-#include <../../mach-rk30/include/mach/debug_uart.h>
+++ /dev/null
-#include <plat/dma-pl330.h>
+++ /dev/null
-#ifndef RK_MACH_DVFS_H
-#define RK_MACH_DVFS_H
-
-#include <plat/dvfs.h>
-
-#ifdef CONFIG_DVFS
-int rk3188_dvfs_init(void);
-void dvfs_adjust_table_lmtvolt(struct clk *clk, struct cpufreq_frequency_table *table);
-#else
-static inline int rk3188_dvfs_init(void){ return 0; }
-static inline void dvfs_adjust_table_lmtvolt(struct clk *clk, struct cpufreq_frequency_table *table){}
-#endif
-
-#endif
+++ /dev/null
-#include <plat/entry-macro.S>
+++ /dev/null
-#include <plat/fiq.h>
+++ /dev/null
-#include <../../mach-rk30/include/mach/gpio.h>
+++ /dev/null
-#ifndef __MACH_GRF_H
-#define __MACH_GRF_H
-
-#include <asm/io.h>
-
-#define GRF_GPIO0L_DIR 0x0000
-#define GRF_GPIO0H_DIR 0x0004
-#define GRF_GPIO1L_DIR 0x0008
-#define GRF_GPIO1H_DIR 0x000c
-#define GRF_GPIO2L_DIR 0x0010
-#define GRF_GPIO2H_DIR 0x0014
-#define GRF_GPIO3L_DIR 0x0018
-#define GRF_GPIO3H_DIR 0x001c
-#define GRF_GPIO0L_DO 0x0020
-#define GRF_GPIO0H_DO 0x0024
-#define GRF_GPIO1L_DO 0x0028
-#define GRF_GPIO1H_DO 0x002c
-#define GRF_GPIO2L_DO 0x0030
-#define GRF_GPIO2H_DO 0x0034
-#define GRF_GPIO3L_DO 0x0038
-#define GRF_GPIO3H_DO 0x003c
-#define GRF_GPIO0L_EN 0x0040
-#define GRF_GPIO0H_EN 0x0044
-#define GRF_GPIO1L_EN 0x0048
-#define GRF_GPIO1H_EN 0x004c
-#define GRF_GPIO2L_EN 0x0050
-#define GRF_GPIO2H_EN 0x0054
-#define GRF_GPIO3L_EN 0x0058
-#define GRF_GPIO3H_EN 0x005c
-
-
-#define GRF_GPIO0C_IOMUX 0x0068
-#define GRF_GPIO0D_IOMUX 0x006c
-#define GRF_GPIO1A_IOMUX 0x0070
-#define GRF_GPIO1B_IOMUX 0x0074
-#define GRF_GPIO1C_IOMUX 0x0078
-#define GRF_GPIO1D_IOMUX 0x007c
-#define GRF_GPIO2A_IOMUX 0x0080
-#define GRF_GPIO2B_IOMUX 0x0084
-#define GRF_GPIO2C_IOMUX 0x0088
-#define GRF_GPIO2D_IOMUX 0x008c
-#define GRF_GPIO3A_IOMUX 0x0090
-#define GRF_GPIO3B_IOMUX 0x0094
-#define GRF_GPIO3C_IOMUX 0x0098
-#define GRF_GPIO3D_IOMUX 0x009c
-#define GRF_SOC_CON0 0x00a0
-#define GRF_SOC_CON1 0x00a4
-#define GRF_SOC_CON2 0x00a8
-#define GRF_SOC_STATUS0 0x00ac
-#define GRF_DMAC1_CON0 0x00b0
-#define GRF_DMAC1_CON1 0x00b4
-#define GRF_DMAC1_CON2 0x00b8
-#define GRF_DMAC2_CON0 0x00bc
-#define GRF_DMAC2_CON1 0x00c0
-#define GRF_DMAC2_CON2 0x00c4
-#define GRF_DMAC2_CON3 0x00c8
-#define GRF_CPU_CON0 0x00cc
-#define GRF_CPU_CON1 0x00d0
-#define GRF_CPU_CON2 0x00d4
-#define GRF_CPU_CON3 0x00d8
-#define GRF_CPU_CON4 0x00dc
-#define GRF_CPU_CON5 0x00e0
-
-
-#define GRF_DDRC_CON0 0x00ec
-#define GRF_DDRC_STAT 0x00f0
-#define GRF_IO_CON0 0x00f4
-#define GRF_IO_CON1 0x00f8
-#define GRF_IO_CON2 0x00fc
-#define GRF_IO_CON3 0x0100
-#define GRF_IO_CON4 0x0104
-#define GRF_SOC_STATUS1 0x0108
-#define GRF_UOC0_CON0 0x010c
-#define GRF_UOC0_CON1 0x0110
-#define GRF_UOC0_CON2 0x0114
-#define GRF_UOC0_CON3 0x0118
-#define GRF_UOC1_CON0 0x011c
-#define GRF_UOC1_CON1 0x0120
-#define GRF_UOC1_CON2 0x0124
-#define GRF_UOC1_CON3 0x0128
-#define GRF_UOC2_CON0 0x012c
-#define GRF_UOC2_CON1 0x0130
-
-#define GRF_UOC3_CON0 0x0138
-#define GRF_UOC3_CON1 0x013c
-#define GRF_HSIC_STAT 0x0140
-#define GRF_OS_REG0 0x0144
-#define GRF_OS_REG1 0x0148
-#define GRF_OS_REG2 0x014c
-#define GRF_OS_REG3 0x0150
-#define GRF_OS_REG4 0x0154
-#define GRF_OS_REG5 0x0158
-#define GRF_OS_REG6 0x015c
-#define GRF_OS_REG7 0x0160
-#define GRF_GPIO0B_PULL 0x0164
-#define GRF_GPIO0C_PULL 0x0168
-#define GRF_GPIO0D_PULL 0x016c
-#define GRF_GPIO1A_PULL 0x0170
-#define GRF_GPIO1B_PULL 0x0174
-#define GRF_GPIO1C_PULL 0x0178
-#define GRF_GPIO1D_PULL 0x017c
-#define GRF_GPIO2A_PULL 0x0180
-#define GRF_GPIO2B_PULL 0x0184
-#define GRF_GPIO2C_PULL 0x0188
-#define GRF_GPIO2D_PULL 0x018c
-#define GRF_GPIO3A_PULL 0x0190
-#define GRF_GPIO3B_PULL 0x0194
-#define GRF_GPIO3C_PULL 0x0198
-#define GRF_GPIO3D_PULL 0x019c
-#define GRF_FLASH_DATA_PULL 0x01a0
-#define GRF_FLASH_CMD_PULL 0x01a4
-
-enum grf_io_power_domain_voltage {
- IO_PD_VOLTAGE_3_3V = 0,
- IO_PD_VOLTAGE_1_8V = 1,
-};
-
-enum grf_io_power_domain {
- IO_PD_AP0 = 8,
- IO_PD_AP1,
- IO_PD_CIF,
- IO_PD_FLASH,
- IO_PD_VCCIO0,
- IO_PD_VCCIO1,
- IO_PD_LCDC0,
- IO_PD_LCDC1,
-};
-
-static inline void grf_set_io_power_domain_voltage(enum grf_io_power_domain pd, enum grf_io_power_domain_voltage volt)
-{
- writel_relaxed((0x10000 + volt) << pd, RK30_GRF_BASE + GRF_IO_CON4);
- dsb();
-}
-
-static inline enum grf_io_power_domain_voltage grf_get_io_power_domain_voltage(enum grf_io_power_domain pd)
-{
- return (readl_relaxed(RK30_GRF_BASE + GRF_IO_CON4) >> pd) & 1;
-}
-
-#endif
+++ /dev/null
-#ifndef __MACH_HARDWARE_H
-#define __MACH_HARDWARE_H
-
-#endif
+++ /dev/null
-#ifndef __MACH_IO_H
-#define __MACH_IO_H
-
-#include <plat/io.h>
-
-/*
- * RK3188 IO memory map:
- *
- * Virt Phys Size What
- * ---------------------------------------------------------------------------
- * FEA00000 10000000 1M
- * FEB00000 10100000 1M
- * FEC00000 10200000 176K
- * 10300000 1M Peri AXI BUS
- * FEC80000 10500000 16K NANDC
- * FECE0000 1FFE0000 128K CPU Debug
- * FED00000 20000000 640K
- * FEF00000 10080000/0 32K SRAM
- */
-
-#define RK30_IO_TO_VIRT0(pa) IOMEM(pa + (0xFEA00000 - 0x10000000))
-#define RK30_IO_TO_VIRT1(pa) IOMEM(pa + (0xFED00000 - 0x20000000))
-
-#define RK30_IMEM_PHYS 0x10080000
-#define RK30_IMEM_BASE IOMEM(0xFEF00000)
-#define RK30_IMEM_NONCACHED RK30_IO_TO_VIRT0(RK30_IMEM_PHYS)
-#define RK3188_IMEM_SIZE SZ_32K
-#define RK30_GPU_PHYS 0x10090000
-#define RK30_GPU_SIZE SZ_64K
-
-#define RK3188_ROM_PHYS 0x10120000
-#define RK30_ROM_BASE IOMEM(0xFEB00000)
-#define RK30_ROM_SIZE SZ_16K
-
-#define RK30_VCODEC_PHYS 0x10104000
-#define RK30_VCODEC_SIZE SZ_16K
-#define RK30_CIF0_PHYS 0x10108000
-#define RK30_CIF0_SIZE SZ_8K
-
-#define RK30_LCDC0_PHYS 0x1010c000
-#define RK30_LCDC0_SIZE SZ_8K
-#define RK30_LCDC1_PHYS 0x1010e000
-#define RK30_LCDC1_SIZE SZ_8K
-#define RK30_IPP_PHYS 0x10110000
-#define RK30_IPP_SIZE SZ_16K
-#define RK30_RGA_PHYS 0x10114000
-#define RK30_RGA_SIZE SZ_8K
-
-#define RK30_I2S1_2CH_PHYS 0x1011a000
-#define RK30_I2S1_2CH_SIZE SZ_8K
-#define RK30_SPDIF_PHYS 0x1011e000
-#define RK30_SPDIF_SIZE SZ_8K
-
-#define RK30_UART0_PHYS 0x10124000
-#define RK30_UART0_BASE RK30_IO_TO_VIRT0(RK30_UART0_PHYS)
-#define RK30_UART0_SIZE SZ_8K
-#define RK30_UART1_PHYS 0x10126000
-#define RK30_UART1_BASE RK30_IO_TO_VIRT0(RK30_UART1_PHYS)
-#define RK30_UART1_SIZE SZ_8K
-#define RK30_CPU_AXI_BUS_PHYS 0x10128000
-#define RK30_CPU_AXI_BUS_BASE RK30_IO_TO_VIRT0(RK30_CPU_AXI_BUS_PHYS)
-#define RK30_CPU_AXI_BUS_SIZE SZ_32K
-
-#define RK30_L2C_PHYS 0x10138000
-#define RK30_L2C_BASE RK30_IO_TO_VIRT0(RK30_L2C_PHYS)
-#define RK30_L2C_SIZE SZ_16K
-#define RK30_SCU_PHYS 0x1013c000
-#define RK30_SCU_BASE RK30_IO_TO_VIRT0(RK30_SCU_PHYS)
-#define RK30_SCU_SIZE SZ_256
-#define RK30_GICC_PHYS 0x1013c100
-#define RK30_GICC_BASE RK30_IO_TO_VIRT0(RK30_GICC_PHYS)
-#define RK30_GICC_SIZE SZ_256
-#define RK30_GTIMER_PHYS 0x1013c200
-#define RK30_GTIMER_BASE RK30_IO_TO_VIRT0(RK30_GTIMER_PHYS)
-#define RK30_GTIMER_SIZE SZ_1K
-#define RK30_PTIMER_PHYS 0x1013c600
-#define RK30_PTIMER_BASE RK30_IO_TO_VIRT0(RK30_PTIMER_PHYS)
-#define RK30_PTIMER_SIZE (SZ_2K + SZ_512)
-#define RK30_GICD_PHYS 0x1013d000
-#define RK30_GICD_BASE RK30_IO_TO_VIRT0(RK30_GICD_PHYS)
-#define RK30_GICD_SIZE SZ_2K
-
-#define RK30_CORE_PHYS RK30_L2C_PHYS
-#define RK30_CORE_BASE RK30_IO_TO_VIRT0(RK30_CORE_PHYS)
-#define RK30_CORE_SIZE (RK30_L2C_SIZE + SZ_8K)
-
-#define RK30_USBHOST11_PHYS 0x10140000
-#define RK30_USBHOST11_SIZE SZ_256K
-#define RK30_USBOTG20_PHYS 0x10180000
-#define RK30_USBOTG20_SIZE SZ_256K
-#define RK30_USBHOST20_PHYS 0x101c0000
-#define RK30_USBHOST20_SIZE SZ_256K
-
-#define RK30_MAC_PHYS 0x10204000
-#define RK30_MAC_SIZE SZ_16K
-
-#define RK30_HSADC_PHYS 0x10210000
-#define RK30_HSADC_SIZE SZ_16K
-#define RK30_SDMMC0_PHYS 0x10214000
-#define RK30_SDMMC0_SIZE SZ_16K
-#define RK30_SDIO_PHYS 0x10218000
-#define RK30_SDIO_SIZE SZ_16K
-#define RK30_EMMC_PHYS 0x1021c000
-#define RK30_EMMC_SIZE SZ_16K
-#define RK30_PIDF_PHYS 0x10220000
-#define RK30_PIDF_SIZE SZ_16K
-
-#define RK30_HSIC_PHYS 0x10240000
-#define RK30_HSIC_SIZE SZ_256K
-
-#define RK30_PERI_AXI_BUS_PHYS 0x10300000
-#define RK30_PERI_AXI_BUS_SIZE SZ_1M
-
-#define RK30_GPS_PHYS 0x10400000
-#define RK30_GPS_SIZE SZ_1M
-#define RK30_NANDC_PHYS 0x10500000
-#define RK30_NANDC_SIZE SZ_16K
-
-#define RK30_SMC_BANK0_PHYS 0x11000000
-#define RK30_SMC_BANK0_SIZE SZ_16M
-#define RK30_SMC_BANK1_PHYS 0x12000000
-#define RK30_SMC_BANK1_SIZE SZ_16M
-
-#define RK30_CPU_DEBUG_PHYS 0x1FFE0000
-#define RK30_CPU_DEBUG_SIZE SZ_128K
-#define RK30_CRU_PHYS 0x20000000
-#define RK30_CRU_BASE RK30_IO_TO_VIRT1(RK30_CRU_PHYS)
-#define RK30_CRU_SIZE SZ_16K
-#define RK30_PMU_PHYS 0x20004000
-#define RK30_PMU_BASE RK30_IO_TO_VIRT1(RK30_PMU_PHYS)
-#define RK30_PMU_SIZE SZ_16K
-#define RK30_GRF_PHYS 0x20008000
-#define RK30_GRF_BASE RK30_IO_TO_VIRT1(RK30_GRF_PHYS)
-#define RK30_GRF_SIZE SZ_8K
-#define RK30_GPIO0_PHYS 0x2000a000
-#define RK30_GPIO0_BASE RK30_IO_TO_VIRT1(RK30_GPIO0_PHYS)
-#define RK30_GPIO0_SIZE SZ_8K
-
-#define RK3188_TIMER3_PHYS 0x2000e000
-#define RK3188_TIMER3_BASE RK30_IO_TO_VIRT1(RK3188_TIMER3_PHYS)
-#define RK3188_TIMER3_SIZE SZ_8K
-#define RK30_EFUSE_PHYS 0x20010000
-#define RK30_EFUSE_BASE RK30_IO_TO_VIRT1(RK30_EFUSE_PHYS)
-#define RK30_EFUSE_SIZE SZ_16K
-#define RK30_TZPC_PHYS 0x20014000
-#define RK30_TZPC_SIZE SZ_16K
-#define RK30_DMACS1_PHYS 0x20018000
-#define RK30_DMACS1_SIZE SZ_16K
-#define RK30_DMAC1_PHYS 0x2001c000
-#define RK30_DMAC1_SIZE SZ_16K
-#define RK30_DDR_PCTL_PHYS 0x20020000
-#define RK30_DDR_PCTL_BASE RK30_IO_TO_VIRT1(RK30_DDR_PCTL_PHYS)
-#define RK30_DDR_PCTL_SIZE SZ_16K
-
-#define RK30_I2C0_PHYS 0x2002c000
-#define RK30_I2C0_SIZE SZ_8K
-#define RK30_I2C1_PHYS 0x2002e000
-#define RK30_I2C1_BASE RK30_IO_TO_VIRT1(RK30_I2C1_PHYS)
-#define RK30_I2C1_SIZE SZ_8K
-#define RK30_PWM01_PHYS 0x20030000
-#define RK30_PWM01_BASE RK30_IO_TO_VIRT1(RK30_PWM01_PHYS)
-#define RK30_PWM01_SIZE SZ_16K
-
-#define RK30_TIMER0_PHYS 0x20038000
-#define RK30_TIMER0_BASE RK30_IO_TO_VIRT1(RK30_TIMER0_PHYS)
-#define RK30_TIMER0_SIZE SZ_8K
-
-#define RK30_GPIO1_PHYS 0x2003c000
-#define RK30_GPIO1_BASE RK30_IO_TO_VIRT1(RK30_GPIO1_PHYS)
-#define RK30_GPIO1_SIZE SZ_8K
-#define RK30_GPIO2_PHYS 0x2003e000
-#define RK30_GPIO2_BASE RK30_IO_TO_VIRT1(RK30_GPIO2_PHYS)
-#define RK30_GPIO2_SIZE SZ_8K
-#define RK30_DDR_PUBL_PHYS 0x20040000
-#define RK30_DDR_PUBL_BASE RK30_IO_TO_VIRT1(RK30_DDR_PUBL_PHYS)
-#define RK30_DDR_PUBL_SIZE SZ_16K
-
-#define RK30_WDT_PHYS 0x2004c000
-#define RK30_WDT_SIZE SZ_16K
-#define RK30_PWM23_PHYS 0x20050000
-#define RK30_PWM23_BASE RK30_IO_TO_VIRT1(RK30_PWM23_PHYS)
-#define RK30_PWM23_SIZE SZ_16K
-#define RK30_I2C2_PHYS 0x20054000
-#define RK30_I2C2_SIZE SZ_16K
-#define RK30_I2C3_PHYS 0x20058000
-#define RK30_I2C3_SIZE SZ_16K
-#define RK30_I2C4_PHYS 0x2005c000
-#define RK30_I2C4_SIZE SZ_16K
-#define RK30_TSADC_PHYS 0x20060000
-#define RK30_TSADC_SIZE SZ_16K
-#define RK30_UART2_PHYS 0x20064000
-#define RK30_UART2_BASE RK30_IO_TO_VIRT1(RK30_UART2_PHYS)
-#define RK30_UART2_SIZE SZ_16K
-#define RK30_UART3_PHYS 0x20068000
-#define RK30_UART3_BASE RK30_IO_TO_VIRT1(RK30_UART3_PHYS)
-#define RK30_UART3_SIZE SZ_16K
-#define RK30_SARADC_PHYS 0x2006c000
-#define RK30_SARADC_SIZE SZ_16K
-#define RK30_SPI0_PHYS 0x20070000
-#define RK30_SPI0_SIZE SZ_16K
-#define RK30_SPI1_PHYS 0x20074000
-#define RK30_SPI1_SIZE SZ_16K
-#define RK30_DMAC2_PHYS 0x20078000
-#define RK30_DMAC2_SIZE SZ_16K
-#define RK30_SMC_PHYS 0x2007c000
-#define RK30_SMC_SIZE SZ_16K
-#define RK30_GPIO3_PHYS 0x20080000
-#define RK30_GPIO3_BASE RK30_IO_TO_VIRT1(RK30_GPIO3_PHYS)
-#define RK30_GPIO3_SIZE SZ_16K
-
-#define GIC_DIST_BASE RK30_GICD_BASE
-#define GIC_CPU_BASE RK30_GICC_BASE
-
-#endif
+++ /dev/null
-#ifndef __MACH_RK3188_IOMUX_H
-#define __MACH_RK3188_IOMUX_H
-
-#include <mach/gpio.h>
-#include <mach/grf.h>
-#include <mach/io.h>
-#include <plat/iomux.h>
-
-#define GRF_IOMUX_BASE (RK30_GRF_BASE + 0x0060)
-
-enum{
- /* GPIO0_A */
- /* GPIO0_B */
- /* GPIO0_C */
- GPIO0_C0 = 0x0c00, NAND_D8,
- GPIO0_C1 = 0x0c10, NAND_D9,
- GPIO0_C2 = 0x0c20, NAND_D10,
- GPIO0_C3 = 0x0c30, NAND_D11,
- GPIO0_C4 = 0x0c40, NAND_D12,
- GPIO0_C5 = 0x0c50, NAND_D13,
- GPIO0_C6 = 0x0c60, NAND_D14,
- GPIO0_C7 = 0x0c70, NAND_D15,
-
- /* GPIO0_D */
- GPIO0_D0 = 0x0d00, NAND_DQS, EMMC_CLKOUT,
- GPIO0_D1 = 0x0d10, NAND_CS1,
- GPIO0_D2 = 0x0d20, NAND_CS2, EMMC_CMD,
- GPIO0_D3 = 0x0d30, NAND_CS3, EMMC_RSTNOUT,
- GPIO0_D4 = 0x0d40, SPI1_RXD,
- GPIO0_D5 = 0x0d50, SPI1_TXD,
- GPIO0_D6 = 0x0d60, SPI1_CLK,
- GPIO0_D7 = 0x0d70, SPI1_CS0,
-
- /* GPIO1_A */
- GPIO1_A0 = 0x1a00, UART0_SIN,
- GPIO1_A1 = 0x1a10, UART0_SOUT,
- GPIO1_A2 = 0x1a20, UART0_CTSN,
- GPIO1_A3 = 0x1a30, UART0_RTSN,
- GPIO1_A4 = 0x1a40, UART1_SIN, SPI0_RXD,
- GPIO1_A5 = 0x1a50, UART1_SOUT, SPI0_TXD,
- GPIO1_A6 = 0x1a60, UART1_CTSN, SPI0_CLK,
- GPIO1_A7 = 0x1a70, UART1_RTSN, SPI0_CS0,
-
- /* GPIO1_B */
- GPIO1_B0 = 0x1b00, UART2_SIN, JTAG_TDI,
- GPIO1_B1 = 0x1b10, UART2_SOUT, JTAG_TDO,
- GPIO1_B2 = 0x1b20, UART3_SIN, GPS_MAG,
- GPIO1_B3 = 0x1b30, UART3_SOUT, GPS_SIG,
- GPIO1_B4 = 0x1b40, UART3_CTSN, GPS_RFCLK,
- GPIO1_B5 = 0x1b50, UART3_RTSN,
- GPIO1_B6 = 0x1b60, SPDIF_TX, SPI1_CS1,
- GPIO1_B7 = 0x1b70, SPI0_CS1,
-
- /* GPIO1_C */
- GPIO1_C0 = 0x1c00, I2S0_MCLK,
- GPIO1_C1 = 0x1c10, I2S0_SCLK,
- GPIO1_C2 = 0x1c20, I2S0_LRCKRX,
- GPIO1_C3 = 0x1c30, I2S0_LRCKTX,
- GPIO1_C4 = 0x1c40, I2S0_SDI,
- GPIO1_C5 = 0x1c50, I2S0_SDO,
-
- /* GPIO1_D */
- GPIO1_D0 = 0x1d00, I2C0_SDA,
- GPIO1_D1 = 0x1d10, I2C0_SCL,
- GPIO1_D2 = 0x1d20, I2C1_SDA,
- GPIO1_D3 = 0x1d30, I2C1_SCL,
- GPIO1_D4 = 0x1d40, I2C2_SDA,
- GPIO1_D5 = 0x1d50, I2C2_SCL,
- GPIO1_D6 = 0x1d60, I2C4_SDA,
- GPIO1_D7 = 0x1d70, I2C4_SCL,
-
- /* GPIO2_A */
- GPIO2_A0 = 0x2a00, LCDC1_D0, SMC_D0, TRACE_D0,
- GPIO2_A1 = 0x2a10, LCDC1_D1, SMC_D1, TRACE_D1,
- GPIO2_A2 = 0x2a20, LCDC1_D2, SMC_D2, TRACE_D2,
- GPIO2_A3 = 0x2a30, LCDC1_D3, SMC_D3, TRACE_D3,
- GPIO2_A4 = 0x2a40, LCDC1_D4, SMC_D4, TRACE_D4,
- GPIO2_A5 = 0x2a50, LCDC1_D5, SMC_D5, TRACE_D5,
- GPIO2_A6 = 0x2a60, LCDC1_D6, SMC_D6, TRACE_D6,
- GPIO2_A7 = 0x2a70, LCDC1_D7, SMC_D7, TRACE_D7,
-
- /* GPIO2_B */
- GPIO2_B0 = 0x2b00, LCDC1_D8, SMC_D8, TRACE_D8,
- GPIO2_B1 = 0x2b10, LCDC1_D9, SMC_D9, TRACE_D9,
- GPIO2_B2 = 0x2b20, LCDC1_D10, SMC_D10, TRACE_D10,
- GPIO2_B3 = 0x2b30, LCDC1_D11, SMC_D11, TRACE_D11,
- GPIO2_B4 = 0x2b40, LCDC1_D12, SMC_D12, TRACE_D12,
- GPIO2_B5 = 0x2b50, LCDC1_D13, SMC_D13, TRACE_D13,
- GPIO2_B6 = 0x2b60, LCDC1_D14, SMC_D14, TRACE_D14,
- GPIO2_B7 = 0x2b70, LCDC1_D15, SMC_D15, TRACE_D15,
-
- /* GPIO2_C */
- GPIO2_C0 = 0x2c00, LCDC1_D16, SMC_R0, TRACE_CLK,
- GPIO2_C1 = 0x2c10, LCDC1_D17, SMC_R1, TRACE_CTL,
- GPIO2_C2 = 0x2c20, LCDC1_D18, SMC_R2,
- GPIO2_C3 = 0x2c30, LCDC1_D19, SMC_R3,
- GPIO2_C4 = 0x2c40, LCDC1_D20, SMC_R4,
- GPIO2_C5 = 0x2c50, LCDC1_D21, SMC_R5,
- GPIO2_C6 = 0x2c60, LCDC1_D22, SMC_R6,
- GPIO2_C7 = 0x2c70, LCDC1_D23, SMC_R7,
-
- /* GPIO2_D */
- GPIO2_D0 = 0x2d00, LCDC1_DCLK, SMC_CS0,
- GPIO2_D1 = 0x2d10, LCDC1_DEN, SMC_WEN,
- GPIO2_D2 = 0x2d20, LCDC1_HSYNC, SMC_OEN,
- GPIO2_D3 = 0x2d30, LCDC1_VSYNC, SMC_ADVN,
- GPIO2_D4 = 0x2d40, SMC_BLSN0,
- GPIO2_D5 = 0x2d50, SMC_BLSN1,
- GPIO2_D6 = 0x2d60, SMC_CS1,
- GPIO2_D7 = 0x2d70, TEST_CLK_OUT,
-
- /* GPIO3_A */
- GPIO3_A0 = 0x3a00, MMC0_RSTNOUT,
- GPIO3_A1 = 0x3a10, MMC0_PWREN,
- GPIO3_A2 = 0x3a20, MMC0_CLKOUT,
- GPIO3_A3 = 0x3a30, MMC0_CMD,
- GPIO3_A4 = 0x3a40, MMC0_D0,
- GPIO3_A5 = 0x3a50, MMC0_D1,
- GPIO3_A6 = 0x3a60, MMC0_D2,
- GPIO3_A7 = 0x3a70, MMC0_D3,
-
- /* GPIO3_B */
- GPIO3_B0 = 0x3b00, MMC0_DETN,
- GPIO3_B1 = 0x3b10, MMC0_WRPRT,
- GPIO3_B3 = 0x3b30, CIF0_CLKOUT,
- GPIO3_B4 = 0x3b40, CIF0_D0, HSADC_D8,
- GPIO3_B5 = 0x3b50, CIF0_D1, HSADC_D9,
- GPIO3_B6 = 0x3b60, CIF0_D10, I2C3_SDA,
- GPIO3_B7 = 0x3b70, CIF0_D11, I2C3_SCL,
-
- /* GPIO3_C */
- GPIO3_C0 = 0x3c00, MMC1_CMD, RMII_TXEN,
- GPIO3_C1 = 0x3c10, MMC1_D0, RMII_TXD1,
- GPIO3_C2 = 0x3c20, MMC1_D1, RMII_TXD0,
- GPIO3_C3 = 0x3c30, MMC1_D2, RMII_RXD0,
- GPIO3_C4 = 0x3c40, MMC1_D3, RMII_RXD1,
- GPIO3_C5 = 0x3c50, MMC1_CLKOUT, RMII_CLKOUT, RMII_CLKIN,
- GPIO3_C6 = 0x3c60, MMC1_DETN, RMII_RXERR,
- GPIO3_C7 = 0x3c70, MMC1_WRPRT, RMII_CRS,
-
- /* GPIO3_D */
- GPIO3_D0 = 0x3d00, MMC1_PWREN, RMII_MD,
- GPIO3_D1 = 0x3d10, MMC1_BKEPWR, RMII_MDCLK,
- GPIO3_D2 = 0x3d20, MMC1_INTN,
- GPIO3_D3 = 0x3d30, PWM0,
- GPIO3_D4 = 0x3d40, PWM1, JTAG_TRSTN,
- GPIO3_D5 = 0x3d50, PWM2, JTAG_TCK, OTG_DRV_VBUS,
- GPIO3_D6 = 0x3d60, PWM3, JTAG_TMS, HOST_DRV_VBUS,
-};
-
-#define rk29_mux_api_set(name, mode) iomux_set(mode)
-#define rk30_mux_api_set(name, mode) iomux_set(mode)
-#define rk30_iomux_init() iomux_init()
-
-#endif
+++ /dev/null
-#ifndef __MACH_IRQS_H
-#define __MACH_IRQS_H
-
-#define FIQ_START 0
-
-#define IRQ_LOCALTIMER 29
-
-#define IRQ_DMAC1_0 32
-#define IRQ_DMAC1_1 33
-#define IRQ_DMAC2_0 34
-#define IRQ_DMAC2_1 35
-#define IRQ_DDR_PCTL 36
-#define IRQ_HSIC 37
-#define IRQ_OTG_BVALID 38
-#define IRQ_GPU_PP 39
-#define IRQ_GPU_MMU 40
-#define IRQ_VEPU 41
-#define IRQ_VDPU 42
-#define IRQ_CIF0 43
-#define IRQ_GPU_GP 44
-#define IRQ_LCDC0 45
-#define IRQ_LCDC1 46
-#define IRQ_IPP 47
-#define IRQ_USB_OTG 48
-#define IRQ_USB_HOST 49
-#define IRQ_GPS 50
-#define IRQ_MAC 51
-#define IRQ_GPS_TIMER 52
-
-#define IRQ_HSADC 54
-#define IRQ_SDMMC 55
-#define IRQ_SDIO 56
-#define IRQ_EMMC 57
-#define IRQ_SARADC 58
-#define IRQ_NANDC 59
-
-#define IRQ_SMC 61
-#define IRQ_PIDF 62
-
-#define IRQ_I2S1_2CH 64
-#define IRQ_SPDIF 65
-#define IRQ_UART0 66
-#define IRQ_UART1 67
-#define IRQ_UART2 68
-#define IRQ_UART3 69
-#define IRQ_SPI0 70
-#define IRQ_SPI1 71
-#define IRQ_I2C0 72
-#define IRQ_I2C1 73
-#define IRQ_I2C2 74
-#define IRQ_I2C3 75
-#define IRQ_TIMER0 76
-#define IRQ_TIMER1 77
-#define IRQ_TIMER2 78
-#define IRQ_PWM0 79
-#define IRQ_PWM1 80
-#define IRQ_PWM2 81
-#define IRQ_PWM3 82
-#define IRQ_WDT 83
-#define IRQ_I2C4 84
-#define IRQ_PMU 85
-#define IRQ_GPIO0 86
-#define IRQ_GPIO1 87
-#define IRQ_GPIO2 88
-#define IRQ_GPIO3 89
-#define IRQ_TIMER3 90
-#define IRQ_TIMER4 91
-#define IRQ_TIMER5 92
-#define IRQ_PERI_AHB_USB_ARBITER 93
-#define IRQ_PERI_AHB_EMEM_ARBITER 94
-#define IRQ_RGA 95
-#define IRQ_TIMER6 96
-
-#define IRQ_SDMMC_DETECT 98
-#define IRQ_SDIO_DETECT 99
-#define IRQ_GPU_OBSRV_MAINFAULT 100
-#define IRQ_PMU_STOP_EXIT_INT 101
-#define IRQ_OBSERVER_MAINFAULT 102
-#define IRQ_VPU_OBSRV_MAINFAULT 103
-#define IRQ_PERI_OBSRV_MAINFAULT 104
-#define IRQ_VIO1_OBSRV_MAINFAULT 105
-#define IRQ_VIO0_OBSRV_MAINFAULT 106
-#define IRQ_DMAC_OBSRV_MAINFAULT 107
-
-#define IRQ_UART_SIGNAL 112
-
-#define IRQ_ARM_PMU 151
-
-#define NR_GIC_IRQS (5 * 32)
-#define NR_GPIO_IRQS (4 * 32)
-#define NR_BOARD_IRQS 64
-#define NR_IRQS (NR_GIC_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS)
-
-#define IRQ_BOARD_BASE (NR_GIC_IRQS + NR_GPIO_IRQS)
-
-#endif
+++ /dev/null
-#include <plat/loader.h>
+++ /dev/null
-#ifndef __MACH_MEMORY_H
-#define __MACH_MEMORY_H
-
-#include <plat/memory.h>
-#include <mach/io.h>
-
-/*
- * SRAM memory whereabouts
- */
-#define SRAM_CODE_OFFSET (RK30_IMEM_BASE + 0x0100)
-#define SRAM_CODE_END (RK30_IMEM_BASE + 0x0FFF)
-#define SRAM_DATA_OFFSET (RK30_IMEM_BASE + 0x1000)
-#define SRAM_DATA_END (RK30_IMEM_BASE + 0x2FFF - 64)
-
-#endif
+++ /dev/null
-/*! \file
- \brief Declaration of library functions
-
- Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
-*/
-
-/*******************************************************************************
-* Copyright (c) 2009 MediaTek Inc.
-*
-* All rights reserved. Copying, compilation, modification, distribution
-* or any other use whatsoever of this material is strictly prohibited
-* except in accordance with a Software License Agreement with
-* MediaTek Inc.
-********************************************************************************
-*/
-
-/*******************************************************************************
-* LEGAL DISCLAIMER
-*
-* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND
-* AGREES THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK
-* SOFTWARE") RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE
-* PROVIDED TO BUYER ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY
-* DISCLAIMS ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT
-* LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-* PARTICULAR PURPOSE OR NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE
-* ANY WARRANTY WHATSOEVER WITH RESPECT TO THE SOFTWARE OF ANY THIRD PARTY
-* WHICH MAY BE USED BY, INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK
-* SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY
-* WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE
-* FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S SPECIFICATION OR TO
-* CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
-*
-* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
-* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL
-* BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT
-* ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY
-* BUYER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
-*
-* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
-* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT
-* OF LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING
-* THEREOF AND RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN
-* FRANCISCO, CA, UNDER THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE
-* (ICC).
-********************************************************************************
-*/
-
-#ifndef _MTK_WCN_CMB_STUB_H_
-#define _MTK_WCN_CMB_STUB_H_
-
-#include <linux/types.h>
- typedef enum {
- COMBO_AUDIO_STATE_0 = 0, /* 0000: BT_PCM_OFF & FM analog (line in/out) */
- COMBO_AUDIO_STATE_1 = 1, /* 0001: BT_PCM_ON & FM analog (in/out) */
- COMBO_AUDIO_STATE_2 = 2, /* 0010: BT_PCM_OFF & FM digital (I2S) */
- COMBO_AUDIO_STATE_3 = 3, /* 0011: BT_PCM_ON & FM digital (I2S) (invalid in 73evb & 1.2 phone configuration) */
- COMBO_AUDIO_STATE_MAX = 4,
- } COMBO_AUDIO_STATE;
-
- typedef enum {
- COMBO_FUNC_TYPE_BT = 0,
- COMBO_FUNC_TYPE_FM = 1,
- COMBO_FUNC_TYPE_GPS = 2,
- COMBO_FUNC_TYPE_WIFI = 3,
- COMBO_FUNC_TYPE_WMT = 4,
- COMBO_FUNC_TYPE_STP = 5,
- COMBO_FUNC_TYPE_NUM = 6
- } COMBO_FUNC_TYPE;
-
- typedef enum {
- COMBO_IF_UART = 0,
- COMBO_IF_MSDC = 1,
- COMBO_IF_MAX,
- } COMBO_IF;
-
-
- /******************************************************************************
- * F U N C T I O N D E C L A R A T I O N S
- *******************************************************************************
- */
-
-
- /* [GeorgeKuo] Stub functions for other kernel built-in modules to call.
- * Keep them unchanged temporarily. Move mt_combo functions to mtk_wcn_combo.
- */
- //extern int mt_combo_audio_ctrl_ex(COMBO_AUDIO_STATE state, u32 clt_ctrl);
- static inline int mt_combo_audio_ctrl(COMBO_AUDIO_STATE state) {
- //return mt_combo_audio_ctrl_ex(state, 1);
- return 0;
- }
- //extern int mt_combo_plt_enter_deep_idle(COMBO_IF src);
- //extern int mt_combo_plt_exit_deep_idle(COMBO_IF src);
-
- /* Use new mtk_wcn_stub APIs instead of old mt_combo ones for kernel to control
- * function on/off.
- */
- //extern void mtk_wcn_cmb_stub_func_ctrl (unsigned int type, unsigned int on);
- //extern int board_sdio_ctrl (unsigned int sdio_port_num, unsigned int on);
-//#include <mach/mt_combo.h> jake
-/*******************************************************************************
-* C O M P I L E R F L A G S
-********************************************************************************
-*/
-
-/*******************************************************************************
-* M A C R O S
-********************************************************************************
-*/
-
-
-/*******************************************************************************
-* E X T E R N A L R E F E R E N C E S
-********************************************************************************
-*/
-
-
-
-/*******************************************************************************
-* C O N S T A N T S
-********************************************************************************
-*/
-
-
-
-/*******************************************************************************
-* D A T A T Y P E S
-********************************************************************************
-*/
-typedef enum {
- CMB_STUB_AIF_0 = 0, /* 0000: BT_PCM_OFF & FM analog (line in/out) */
- CMB_STUB_AIF_1 = 1, /* 0001: BT_PCM_ON & FM analog (in/out) */
- CMB_STUB_AIF_2 = 2, /* 0010: BT_PCM_OFF & FM digital (I2S) */
- CMB_STUB_AIF_3 = 3, /* 0011: BT_PCM_ON & FM digital (I2S) (invalid in 73evb & 1.2 phone configuration) */
- CMB_STUB_AIF_MAX = 4,
-} CMB_STUB_AIF_X;
-
-/*COMBO_CHIP_AUDIO_PIN_CTRL*/
-typedef enum {
- CMB_STUB_AIF_CTRL_DIS = 0,
- CMB_STUB_AIF_CTRL_EN = 1,
- CMB_STUB_AIF_CTRL_MAX = 2,
-} CMB_STUB_AIF_CTRL;
-
-typedef void (*wmt_bgf_eirq_cb)(void);
-typedef int (*wmt_aif_ctrl_cb)(CMB_STUB_AIF_X, CMB_STUB_AIF_CTRL);
-typedef void (*wmt_func_ctrl_cb)(unsigned int, unsigned int);
-
-typedef struct _CMB_STUB_CB_ {
- unsigned int size; //structure size
- /*wmt_bgf_eirq_cb bgf_eirq_cb;*//* remove bgf_eirq_cb from stub. handle it in platform */
- wmt_aif_ctrl_cb aif_ctrl_cb;
- wmt_func_ctrl_cb func_ctrl_cb;
-} CMB_STUB_CB, *P_CMB_STUB_CB;
-
-/*******************************************************************************
-* P U B L I C D A T A
-********************************************************************************
-*/
-
-
-
-/*******************************************************************************
-* P R I V A T E D A T A
-********************************************************************************
-*/
-
-
-
-
-
-/*******************************************************************************
-* F U N C T I O N D E C L A R A T I O N S
-********************************************************************************
-*/
-
-extern int mtk_wcn_cmb_stub_reg (P_CMB_STUB_CB p_stub_cb);
-extern int mtk_wcn_cmb_stub_unreg (void);
-
-extern int mtk_wcn_cmb_stub_aif_ctrl (CMB_STUB_AIF_X state, CMB_STUB_AIF_CTRL ctrl);
-
-// TODO: [FixMe][GeorgeKuo]: put prototypes into mt_combo.h for board.c temporarily for non-finished porting
-// TODO: old: rfkill->board.c->mt_combo->wmt_lib_plat
-// TODO: new: rfkill->mtk_wcn_cmb_stub_alps->wmt_plat_alps
-#if 0
-extern int mtk_wcn_cmb_stub_func_ctrl(unsigned int type, unsigned int on);
-#endif
-
-/*******************************************************************************
-* F U N C T I O N S
-********************************************************************************
-*/
-
-
-#endif /* _MTK_WCN_CMB_STUB_H_ */
-
-
-
-
-
-
+++ /dev/null
-#ifndef __MACH_PMU_H
-#define __MACH_PMU_H
-
-#include <linux/io.h>
-
-#define PMU_WAKEUP_CFG0 0x00
-#define PMU_WAKEUP_CFG1 0x04
-#define PMU_PWRDN_CON 0x08
-#define PMU_PWRDN_ST 0x0c
-#define PMU_INT_CON 0x10
-#define PMU_INT_ST 0x14
-#define PMU_MISC_CON 0x18
-#define PMU_OSC_CNT 0x1c
-#define PMU_PLL_CNT 0x20
-#define PMU_PMU_CNT 0x24
-#define PMU_DDRIO_PWRON_CNT 0x28
-#define PMU_WAKEUP_RST_CLR_CNT 0x2c
-#define PMU_SCU_PWRDWN_CNT 0x30
-#define PMU_SCU_PWRUP_CNT 0x34
-#define PMU_MISC_CON1 0x38
-#define PMU_GPIO0_CON 0x3c
-#define PMU_SYS_REG0 0x40
-#define PMU_SYS_REG1 0x44
-#define PMU_SYS_REG2 0x48
-#define PMU_SYS_REG3 0x4c
-#define PMU_STOP_INT_DLY 0x60
-#define PMU_GPIO0A_PULL 0x64
-#define PMU_GPIO0B_PULL 0x68
-
-enum pmu_power_domain {
- PD_A9_0 = 0,
- PD_A9_1,
- PD_A9_2,
- PD_A9_3,
- PD_SCU,
- PD_CPU,
- PD_PERI,
- PD_VIO,
- PD_VIDEO,
- PD_GPU,
- PD_CS,
- PD_DBG = PD_CS,
-};
-
-static inline bool pmu_power_domain_is_on(enum pmu_power_domain pd)
-{
- return !(readl_relaxed(RK30_PMU_BASE + PMU_PWRDN_ST) & (1 << pd));
-}
-
-void pmu_set_power_domain(enum pmu_power_domain pd, bool on);
-
-enum pmu_idle_req {
- IDLE_REQ_CPU = 0,
- IDLE_REQ_PERI,
- IDLE_REQ_GPU,
- IDLE_REQ_VIDEO,
- IDLE_REQ_VIO,
- IDLE_REQ_CORE = 13,
- IDLE_REQ_DMA = 15,
-};
-
-void pmu_set_idle_request(enum pmu_idle_req req, bool idle);
-
-#endif
+++ /dev/null
-\r
-#ifndef __RKXX_REMOTECTL_H__\r
-#define __RKXX_REMOTECTL_H__\r
-#include <linux/input.h>\r
-\r
-/********************************************************************\r
-** ºê¶¨Òå *\r
-********************************************************************/\r
-#define TIME_BIT0_MIN 625 /*Bit0 1.125ms*/\r
-#define TIME_BIT0_MAX 1625\r
-\r
-#define TIME_BIT1_MIN 1700 /*Bit1 2.25ms*/\r
-#define TIME_BIT1_MAX 3000\r
-\r
-#define TIME_PRE_MIN 13000 /*4500*/\r
-#define TIME_PRE_MAX 14000 /*5500*/ /*PreLoad 4.5+0.56 = 5.06ms*/\r
-\r
-#define TIME_RPT_MIN 95000 /*101000*/\r
-#define TIME_RPT_MAX 98000 /*103000*/ /*Repeat 105-2.81=102.19ms*/ //110-9-2.25-0.56=98.19ms\r
-\r
-#define TIME_SEQ1_MIN 10000 /*2650*/\r
-#define TIME_SEQ1_MAX 12000 /*3000*/ /*sequence 2.25+0.56=2.81ms*/ //11.25ms\r
-\r
-#define TIME_SEQ2_MIN 40000 /*101000*/\r
-#define TIME_SEQ2_MAX 47000 /*103000*/ /*Repeat 105-2.81=102.19ms*/ //110-9-2.25-0.56=98.19ms\r
-\r
-/********************************************************************\r
-** ½á¹¹¶¨Òå *\r
-********************************************************************/\r
-typedef enum _RMC_STATE\r
-{\r
- RMC_IDLE,\r
- RMC_PRELOAD,\r
- RMC_USERCODE,\r
- RMC_GETDATA,\r
- RMC_SEQUENCE\r
-}eRMC_STATE;\r
-\r
-\r
-struct RKxx_remotectl_platform_data {\r
- //struct rkxx_remotectl_button *buttons;\r
- int nbuttons;\r
- int rep;\r
- int gpio;\r
- int active_low;\r
- int timer;\r
- int wakeup;\r
- void (*set_iomux)(void);\r
-};\r
-\r
-#endif\r
-\r
+++ /dev/null
-#include <../../mach-rk30/include/mach/rk30_camera.h>
+++ /dev/null
-#include <../../mach-rk30/include/mach/sram.h>
+++ /dev/null
-#include <plat/system.h>
+++ /dev/null
-#include <plat/timex.h>
+++ /dev/null
-#include <plat/uncompress.h>
+++ /dev/null
-#include <../../mach-rk30/include/mach/vmalloc.h>
+++ /dev/null
-/*
- *
- * Copyright (C) 2013 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <asm/page.h>
-#include <asm/mach/map.h>
-#include <mach/debug_uart.h>
-
-#define RK30_DEVICE(name) { \
- .virtual = (unsigned long) RK30_##name##_BASE, \
- .pfn = __phys_to_pfn(RK30_##name##_PHYS), \
- .length = RK30_##name##_SIZE, \
- .type = MT_DEVICE, \
- }
-
-static struct map_desc rk30_io_desc[] __initdata = {
- {
- .virtual = (unsigned long) RK30_ROM_BASE,
- .pfn = __phys_to_pfn(RK3188_ROM_PHYS),
- .length = RK30_ROM_SIZE,
- .type = MT_DEVICE,
- },
- RK30_DEVICE(CORE),
- RK30_DEVICE(CPU_AXI_BUS),
-#if CONFIG_RK_DEBUG_UART == 0
- RK30_DEVICE(UART0),
-#elif CONFIG_RK_DEBUG_UART == 1
- RK30_DEVICE(UART1),
-#elif CONFIG_RK_DEBUG_UART == 2
- RK30_DEVICE(UART2),
-#elif CONFIG_RK_DEBUG_UART == 3
- RK30_DEVICE(UART3),
-#endif
- RK30_DEVICE(GRF),
- RK30_DEVICE(CRU),
- RK30_DEVICE(PMU),
- RK30_DEVICE(GPIO0),
- RK30_DEVICE(GPIO1),
- RK30_DEVICE(GPIO2),
- RK30_DEVICE(GPIO3),
- RK30_DEVICE(TIMER0),
- RK30_DEVICE(EFUSE),
- {
- .virtual = (unsigned long) RK3188_TIMER3_BASE,
- .pfn = __phys_to_pfn(RK3188_TIMER3_PHYS),
- .length = RK3188_TIMER3_SIZE,
- .type = MT_DEVICE,
- },
- RK30_DEVICE(PWM01),
- RK30_DEVICE(PWM23),
- RK30_DEVICE(DDR_PCTL),
- RK30_DEVICE(DDR_PUBL),
- RK30_DEVICE(I2C1),
-};
-
-void __init rk30_map_common_io(void)
-{
- iotable_init(rk30_io_desc, ARRAY_SIZE(rk30_io_desc));
-}
+++ /dev/null
-#include <linux/platform_device.h>
-#include <asm/mach/time.h>
-#include <mach/io.h>
-#include <mach/irqs.h>
-
-#define TIMER_NAME "rk_timer"
-#define BASE RK30_TIMER0_BASE
-#define OFFSET 0x20
-
-static struct resource rk_timer_resources[] __initdata = {
- {
- .name = "cs_base",
- .start = (unsigned long) BASE + 5 * OFFSET,
- .flags = IORESOURCE_MEM,
- }, {
- .name = "cs_clk",
- .start = (unsigned long) "timer6",
- }, {
- .name = "cs_pclk",
- .start = (unsigned long) "pclk_timer0",
- },
-
- {
- .name = "ce_base0",
- .start = (unsigned long) BASE + 0 * OFFSET,
- .flags = IORESOURCE_MEM,
- }, {
- .name = "ce_irq0",
- .start = (unsigned long) IRQ_TIMER0,
- .flags = IORESOURCE_IRQ,
- }, {
- .name = "ce_clk0",
- .start = (unsigned long) "timer0",
- }, {
- .name = "ce_pclk0",
- .start = (unsigned long) "pclk_timer0",
- },
-
- {
- .name = "ce_base1",
- .start = (unsigned long) BASE + 1 * OFFSET,
- .flags = IORESOURCE_MEM,
- }, {
- .name = "ce_irq1",
- .start = (unsigned long) IRQ_TIMER1,
- .flags = IORESOURCE_IRQ,
- }, {
- .name = "ce_clk1",
- .start = (unsigned long) "timer1",
- }, {
- .name = "ce_pclk1",
- .start = (unsigned long) "pclk_timer0",
- },
-
- {
- .name = "ce_base2",
- .start = (unsigned long) BASE + 3 * OFFSET,
- .flags = IORESOURCE_MEM,
- }, {
- .name = "ce_irq2",
- .start = (unsigned long) IRQ_TIMER4,
- .flags = IORESOURCE_IRQ,
- }, {
- .name = "ce_clk2",
- .start = (unsigned long) "timer4",
- }, {
- .name = "ce_pclk2",
- .start = (unsigned long) "pclk_timer0",
- },
-
- {
- .name = "ce_base3",
- .start = (unsigned long) BASE + 4 * OFFSET,
- .flags = IORESOURCE_MEM,
- }, {
- .name = "ce_irq3",
- .start = (unsigned long) IRQ_TIMER5,
- .flags = IORESOURCE_IRQ,
- }, {
- .name = "ce_clk3",
- .start = (unsigned long) "timer5",
- }, {
- .name = "ce_pclk3",
- .start = (unsigned long) "pclk_timer0",
- },
-};
-
-static struct platform_device rk_timer_device __initdata = {
- .name = TIMER_NAME,
- .id = 0,
- .resource = rk_timer_resources,
- .num_resources = ARRAY_SIZE(rk_timer_resources),
-};
-
-static struct platform_device *rk_timer_devices[] __initdata = {
- &rk_timer_device,
-};
-
-static void __init rk_timer_init(void)
-{
- early_platform_add_devices(rk_timer_devices, ARRAY_SIZE(rk_timer_devices));
- early_platform_driver_register_all(TIMER_NAME);
- early_platform_driver_probe(TIMER_NAME, 1, 0);
-}
-
-struct sys_timer rk30_timer = {
- .init = rk_timer_init
-};
+++ /dev/null
-choice
- prompt "Rockchip SoC Type"
- depends on ARCH_RK319X
-
-config SOC_RK3190
- bool "RK3190"
- select USB_ARCH_HAS_EHCI if USB_SUPPORT
-
-endchoice
-
-choice
- prompt "RK3190 Board Type"
- depends on SOC_RK3190
-
-config MACH_RK3190_TB
- bool "RK3190 Top Board"
-
-config MACH_RK3190_FPGA
- bool "RK3188 FPGA board"
- select RK_FPGA
-
-endchoice
+++ /dev/null
-EXTRA_CFLAGS += -Os
-ifneq ($(CONFIG_RK_FPGA),y)
-obj-y += ../plat-rk/clock.o
-obj-y += clock_data.o
-obj-y += ../mach-rk30/ddr.o
-obj-y += ../mach-rk30/pmu.o
-obj-y += ../mach-rk30/reset.o
-obj-$(CONFIG_PM) += ../mach-rk30/pm.o
-obj-y += ../mach-rk30/common.o
-CFLAGS_common.o += -DTEXT_OFFSET=$(TEXT_OFFSET)
-endif
-obj-y += ../mach-rk30/devices.o
-obj-y += io.o
-obj-y += rk_timer.o
-obj-$(CONFIG_SMP) += ../mach-rk30/platsmp.o ../mach-rk30/headsmp.o
-obj-$(CONFIG_HOTPLUG_CPU) += ../mach-rk30/hotplug.o
-obj-$(CONFIG_CPU_IDLE) += ../mach-rk30/cpuidle.o
-obj-$(CONFIG_CPU_FREQ) += cpufreq.o
-obj-$(CONFIG_DVFS) += dvfs.o
-obj-y += board.o
-
-board-$(CONFIG_MACH_RK3190_FPGA) += board-rk3190-fpga.o
-board-$(CONFIG_MACH_RK3190_TB) += board-rk3190-tb.o
+++ /dev/null
- zreladdr-y := 0x00408000
-params_phys-y := 0x00088000
-initrd_phys-y := 0x00800000
+++ /dev/null
-/*
- * Copyright (C) 2013 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/skbuff.h>
-#include <linux/spi/spi.h>
-#include <linux/mmc/host.h>
-#include <linux/ion.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <linux/fb.h>
-#include <linux/regulator/machine.h>
-#include <linux/rfkill-rk.h>
-#include <linux/sensor-dev.h>
-
-#include <asm/cacheflush.h>
-#include <asm/fiq_glue.h>
-#include <asm/smp_scu.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/board.h>
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <mach/iomux.h>
-#include <mach/ddr.h>
-#include <mach/fiq.h>
-
-
-#ifdef CONFIG_VIDEO_RK29
-/*---------------- Camera Sensor Macro Define Begin ------------------------*/
-/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
-#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_OV5642 /* back camera sensor */
-#define CONFIG_SENSOR_IIC_ADDR_0 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 4
-#define CONFIG_SENSOR_ORIENTATION_0 90
-#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000
-
-#define CONFIG_SENSOR_01 RK29_CAM_SENSOR_OV5642 /* back camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_01 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 4
-#define CONFIG_SENSOR_ORIENTATION_01 90
-#define CONFIG_SENSOR_POWER_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_01 30000
-
-#define CONFIG_SENSOR_02 RK29_CAM_SENSOR_OV5640 /* back camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_02 0x00
-#define CONFIG_SENSOR_CIF_INDEX_02 0
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 4
-#define CONFIG_SENSOR_ORIENTATION_02 90
-#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000
-
-#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_OV2659 /* front camera sensor 0 */
-#define CONFIG_SENSOR_IIC_ADDR_1 0x60
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 1
-#define CONFIG_SENSOR_ORIENTATION_1 270
-#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000
-
-#define CONFIG_SENSOR_11 RK29_CAM_SENSOR_OV2659 /* front camera sensor 1 */
-#define CONFIG_SENSOR_IIC_ADDR_11 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 3
-#define CONFIG_SENSOR_ORIENTATION_11 270
-#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_11 30000
-
-#define CONFIG_SENSOR_12 RK29_CAM_SENSOR_OV2659//RK29_CAM_SENSOR_OV2655 /* front camera sensor 2 */
-#define CONFIG_SENSOR_IIC_ADDR_12 0x00
-#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 3
-#define CONFIG_SENSOR_ORIENTATION_12 270
-#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERDN_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO
-#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L
-#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L
-#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H
-#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L
-
-#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_240X160_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_CIF_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_VGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_480P_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 15000
-#define CONFIG_SENSOR_720P_FPS_FIXED_12 30000
-
-
-/*---------------- Camera Sensor Configuration Macro End------------------------*/
-#include "../../../drivers/media/video/rk30_camera.c"
-/*---------------- Camera Sensor Macro Define End ---------*/
-
-#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
-/*****************************************************************************************
- * camera devices
- * author: ddl@rock-chips.com
- *****************************************************************************************/
-#define CONFIG_SENSOR_POWER_IOCTL_USR 0 //define this refer to your board layout
-#define CONFIG_SENSOR_RESET_IOCTL_USR 0
-#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
-#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
-
-static void rk_cif_power(int on)
-{
- struct regulator *ldo_18,*ldo_28;
-
- ldo_28 = regulator_get(NULL, "ldo7"); // vcc28_cif
- ldo_18 = regulator_get(NULL, "ldo1"); // vcc18_cif
- if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)) {
- printk("get cif ldo failed!\n");
- return;
- }
- if(on == 0) {
- regulator_disable(ldo_28);
- regulator_put(ldo_28);
- regulator_disable(ldo_18);
- regulator_put(ldo_18);
- mdelay(500);
- } else {
- regulator_set_voltage(ldo_28, 2800000, 2800000);
- regulator_enable(ldo_28);
- // printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
- regulator_put(ldo_28);
-
- regulator_set_voltage(ldo_18, 1800000, 1800000);
- // regulator_set_suspend_voltage(ldo, 1800000);
- regulator_enable(ldo_18);
- // printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
- regulator_put(ldo_18);
- }
-}
-
-#if CONFIG_SENSOR_POWER_IOCTL_USR
-static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- //#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
- rk_cif_power(on);
-}
-#endif
-
-#if CONFIG_SENSOR_RESET_IOCTL_USR
-static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
-static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
-}
-#endif
-
-#if CONFIG_SENSOR_FLASH_IOCTL_USR
-static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
-{
- #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
-}
-#endif
-
-static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
- #if CONFIG_SENSOR_POWER_IOCTL_USR
- .sensor_power_cb = sensor_power_usr_cb,
- #else
- .sensor_power_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_RESET_IOCTL_USR
- .sensor_reset_cb = sensor_reset_usr_cb,
- #else
- .sensor_reset_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
- .sensor_powerdown_cb = sensor_powerdown_usr_cb,
- #else
- .sensor_powerdown_cb = NULL,
- #endif
-
- #if CONFIG_SENSOR_FLASH_IOCTL_USR
- .sensor_flash_cb = sensor_flash_usr_cb,
- #else
- .sensor_flash_cb = NULL,
- #endif
-};
-
-#if CONFIG_SENSOR_IIC_ADDR_0
-static struct reginfo_t rk_init_data_sensor_reg_0[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_0[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-
-#if CONFIG_SENSOR_IIC_ADDR_1
-static struct reginfo_t rk_init_data_sensor_reg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_1[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_01
-static struct reginfo_t rk_init_data_sensor_reg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_01[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_02
-static struct reginfo_t rk_init_data_sensor_reg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_02[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_11
-static struct reginfo_t rk_init_data_sensor_reg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_11[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-#if CONFIG_SENSOR_IIC_ADDR_12
-static struct reginfo_t rk_init_data_sensor_reg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-static struct reginfo_t rk_init_data_sensor_winseqreg_12[] =
-{
- {0x0000, 0x00,0,0}
-};
-#endif
-static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] =
-{
- #if CONFIG_SENSOR_IIC_ADDR_0
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_0,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_1
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_1,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_01
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_01,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_02
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_02,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_11
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_11,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
- #if CONFIG_SENSOR_IIC_ADDR_12
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = rk_init_data_sensor_reg_12,
- .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12,
- .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t),
- .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t),
- },
- #else
- {
- .rk_sensor_init_width = INVALID_VALUE,
- .rk_sensor_init_height = INVALID_VALUE,
- .rk_sensor_init_bus_param = INVALID_VALUE,
- .rk_sensor_init_pixelcode = INVALID_VALUE,
- .rk_sensor_init_data = NULL,
- .rk_sensor_init_winseq = NULL,
- .rk_sensor_winseq_size = 0,
- .rk_sensor_init_data_size = 0,
- },
- #endif
-
- };
-#include "../../../drivers/media/video/rk30_camera.c"
-
-#endif /* CONFIG_VIDEO_RK29 */
-
-#ifdef CONFIG_FB_ROCKCHIP
-
-#define RK_FB_MEM_SIZE 3*SZ_1M
-
-#define LCD_CS_PIN INVALID_GPIO
-#define LCD_CS_VALUE GPIO_HIGH
-
-#define LCD_EN_PIN INVALID_GPIO
-#define LCD_EN_VALUE GPIO_LOW
-
-static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
-{
- int ret = 0;
-
- if(LCD_CS_PIN != INVALID_GPIO)
- {
- ret = gpio_request(LCD_CS_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_CS_PIN);
- printk(KERN_ERR "request lcd cs pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_CS_PIN, LCD_CS_VALUE);
- }
- }
-
- if(LCD_EN_PIN != INVALID_GPIO)
- {
- ret = gpio_request(LCD_EN_PIN, NULL);
- if (ret != 0)
- {
- gpio_free(LCD_EN_PIN);
- printk(KERN_ERR "request lcd en pin fail!\n");
- return -1;
- }
- else
- {
- gpio_direction_output(LCD_EN_PIN, LCD_EN_VALUE);
- }
- }
- return 0;
-}
-static int rk_fb_io_disable(void)
-{
- if(LCD_CS_PIN != INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, !LCD_CS_VALUE);
- }
-
- if(LCD_EN_PIN != INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, !LCD_EN_VALUE);
- }
- return 0;
-}
-static int rk_fb_io_enable(void)
-{
- if(LCD_CS_PIN != INVALID_GPIO)
- {
- gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE);
- }
-
- if(LCD_EN_PIN != INVALID_GPIO)
- {
- gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE);
- }
- return 0;
-}
-
-struct rk29fb_info lcdc0_screen_info = {
- .prop = PRMRY, //primary display device
- .io_init = rk_fb_io_init,
- .io_disable = rk_fb_io_disable,
- .io_enable = rk_fb_io_enable,
- .set_screen_info = set_lcd_info,
-};
-
-struct rk29fb_info lcdc1_screen_info = {
- .prop = EXTEND, //extend display device
- .lcd_info = NULL,
- .set_screen_info = NULL,
-};
-
-static struct resource resource_fb[] = {
- [0] = {
- .name = "fb0 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "ipp buf", //for rotate
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "fb2 buf",
- .start = 0,
- .end = 0,//RK30_FB0_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device device_fb = {
- .name = "rk-fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(resource_fb),
- .resource = resource_fb,
-};
-#endif
-
-#if defined(CONFIG_LCDC0_RK3188)
-static struct resource resource_lcdc0[] = {
- [0] = {
- .name = "lcdc0 reg",
- .start = RK30_LCDC0_PHYS,
- .end = RK30_LCDC0_PHYS + RK30_LCDC0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .name = "lcdc0 irq",
- .start = IRQ_LCDC0,
- .end = IRQ_LCDC0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc0 = {
- .name = "rk3188-lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(resource_lcdc0),
- .resource = resource_lcdc0,
- .dev = {
- .platform_data = &lcdc0_screen_info,
- },
-};
-#endif
-#if defined(CONFIG_LCDC1_RK3188)
-extern struct rk29fb_info lcdc1_screen_info;
-static struct resource resource_lcdc1[] = {
- [0] = {
- .name = "lcdc1 reg",
- .start = RK30_LCDC1_PHYS,
- .end = RK30_LCDC1_PHYS + RK30_LCDC1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = "lcdc1 irq",
- .start = IRQ_LCDC1,
- .end = IRQ_LCDC1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device device_lcdc1 = {
- .name = "rk3188-lcdc",
- .id = 1,
- .num_resources = ARRAY_SIZE(resource_lcdc1),
- .resource = resource_lcdc1,
- .dev = {
- .platform_data = &lcdc1_screen_info,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata i2c0_info[] = {
-#if defined (CONFIG_SND_SOC_RK1000)
- {
- .type = "rk1000_i2c_codec",
- .addr = 0x60,
- .flags = 0,
- },
- {
- .type = "rk1000_control",
- .addr = 0x40,
- .flags = 0,
- },
-#endif
-};
-
-static struct i2c_board_info __initdata i2c1_info[] = {
-};
-
-static struct i2c_board_info __initdata i2c2_info[] = {
-};
-
-static struct i2c_board_info __initdata i2c3_info[] = {
-};
-
-static struct i2c_board_info __initdata i2c_gpio_info[] = {
-};
-
-static void __init rk30_i2c_register_board_info(void)
-{
- i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
- i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
- i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
- i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
-}
-//end of i2c
-
-static struct spi_board_info board_spi_devices[] = {
-};
-
-/***********************************************************
-* rk30 backlight
-************************************************************/
-#define PWM_ID 1
-#define PWM_MUX_NAME GPIO0A3_PWM0_NAME
-#define PWM_MUX_MODE GPIO0A_PWM0
-#define PWM_MUX_MODE_GPIO GPIO0A_GPIO0A3
-#define PWM_GPIO RK30_PIN0_PA3
-#define PWM_EFFECT_VALUE 1
-
-#define LCD_DISP_ON_PIN
-
-#ifdef LCD_DISP_ON_PIN
-
-#define BL_EN_PIN RK30_PIN6_PB3
-#define BL_EN_VALUE GPIO_HIGH
-#endif
-static int rk29_backlight_io_init(void)
-{
- int ret = 0;
- return ret;
-}
-
-static int rk29_backlight_io_deinit(void)
-{
- int ret = 0;
- return ret;
-}
-
-static int rk29_backlight_pwm_suspend(void)
-{
- int ret = 0;
- return ret;
-}
-
-static int rk29_backlight_pwm_resume(void)
-{
- return 0;
-}
-
-static struct rk29_bl_info rk29_bl_info = {
- .pwm_id = PWM_ID,
- .bl_ref = PWM_EFFECT_VALUE,
- .io_init = rk29_backlight_io_init,
- .io_deinit = rk29_backlight_io_deinit,
- .pwm_suspend = rk29_backlight_pwm_suspend,
- .pwm_resume = rk29_backlight_pwm_resume,
-};
-
-static struct platform_device rk29_device_backlight = {
- .name = "rk29_backlight",
- .id = -1,
- .dev = {
- .platform_data = &rk29_bl_info,
- }
-};
-
-/***********************************************************
-* rk30 ion device
-************************************************************/
-#define ION_RESERVE_SIZE (8 * SZ_1M)
-static struct ion_platform_data rk30_ion_pdata = {
- .nr = 1,
- .heaps = {
- {
- .type = ION_HEAP_TYPE_CARVEOUT,
- .id = ION_NOR_HEAP_ID,
- .name = "norheap",
- .size = ION_RESERVE_SIZE,
- }
- },
-};
-
-static struct platform_device device_ion = {
- .name = "ion-rockchip",
- .id = 0,
- .dev = {
- .platform_data = &rk30_ion_pdata,
- },
-};
-
-static struct platform_device *devices[] __initdata = {
-#ifdef CONFIG_FB_ROCKCHIP
- &device_fb,
-#endif
-#if defined(CONFIG_LCDC0_RK3188)
- &device_lcdc0,
-#endif
-#if defined(CONFIG_LCDC1_RK3188)
- &device_lcdc1,
-#endif
-
-#ifdef CONFIG_BACKLIGHT_RK29_BL
- &rk29_device_backlight,
-#endif
- &device_ion,
-};
-
-static void __init fpga_board_init(void)
-{
- rk30_i2c_register_board_info();
- spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
- platform_add_devices(devices, ARRAY_SIZE(devices));
-}
-
-static void __init fpga_reserve(void)
-{
-#if defined(CONFIG_FB_ROCKCHIP)
- resource_fb[0].start = board_mem_reserve_add("fb0", RK_FB_MEM_SIZE);
- resource_fb[0].end = resource_fb[0].start + RK_FB_MEM_SIZE - 1;
-#endif
-#ifdef CONFIG_ION
- rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
-#endif
-#ifdef CONFIG_VIDEO_RK29
- rk30_camera_request_reserve_mem();
-#endif
- board_mem_reserved();
-}
-
-#include <plat/key.h>
-
-static struct rk29_keys_button key_button[] = {
- {
- .desc = "menu",
- .code = EV_MENU,
- .gpio = RK30_PIN3_PB2,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol+",
- .code = KEY_VOLUMEUP,
- .gpio = RK30_PIN3_PB1,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "vol-",
- .code = KEY_VOLUMEDOWN,
- .gpio = RK30_PIN3_PB0,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "home",
- .code = KEY_HOME,
- .gpio = RK30_PIN3_PB3,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "esc",
- .code = KEY_BACK,
- .gpio = RK30_PIN3_PB4,
- .active_low = PRESS_LEV_LOW,
- },
- {
- .desc = "key6",
- .code = KEY_CAMERA,
- .gpio = RK30_PIN3_PB5,
- .active_low = PRESS_LEV_LOW,
- },
-};
-
-struct rk29_keys_platform_data rk29_keys_pdata = {
- .buttons = key_button,
- .nbuttons = ARRAY_SIZE(key_button),
- .chn = -1, //chn: 0-7, if do not use ADC,set 'chn' -1
-};
-
-static void __init fpga_fixup(struct machine_desc *desc, struct tag *tags,
- char **cmdline, struct meminfo *mi)
-{
- mi->nr_banks = 1;
- mi->bank[0].start = PLAT_PHYS_OFFSET;
- mi->bank[0].size = ddr_get_cap();
-}
-
-static void __init fpga_map_io(void)
-{
- rk30_map_common_io();
- rk29_setup_early_printk();
- rk29_sram_init();
- board_clock_init();
-}
-
-static void __init fpga_init_irq(void)
-{
- gic_init(0, IRQ_LOCALTIMER, GIC_DIST_BASE, GIC_CPU_BASE);
-#ifdef CONFIG_FIQ
- rk_fiq_init();
-#endif
-}
-
-MACHINE_START(RK30, "RK30board")
- .boot_params = PLAT_PHYS_OFFSET + 0x800,
- .fixup = fpga_fixup,
- .reserve = &fpga_reserve,
- .map_io = fpga_map_io,
- .init_irq = fpga_init_irq,
- .timer = &rk30_timer,
- .init_machine = fpga_board_init,
-MACHINE_END
-
-#include <mach/system.h>
-static void fpga_reset(char mode, const char *cmd)
-{
- sram_printascii("\nfpga reset\n");
- while (1);
-}
-void (*arch_reset)(char, const char *) = fpga_reset;
-
-int ddr_init(uint32_t dram_type, uint32_t freq)
-{
- return 0;
-}
-
-uint32_t ddr_get_cap(void)
-{
- return SZ_128M;
-}
-
-struct cpufreq_frequency_table *dvfs_get_freq_volt_table(struct clk *clk)
-{
- return NULL;
-}
-
-#include <linux/clkdev.h>
-
-struct clk {
- const char *name;
- unsigned long rate;
-};
-
-static struct clk xin24m = {
- .name = "xin24m",
- .rate = 24000000,
-};
-
-static struct clk xin12m = {
- .name = "xin12m",
- .rate = 12000000,
-};
-
-#define CLK(dev, con, ck) \
- { \
- .dev_id = dev, \
- .con_id = con, \
- .clk = ck, \
- }
-
-static struct clk_lookup clks[] = {
- CLK("rk30_i2c.0", "i2c", &xin24m),
- CLK("rk30_i2c.1", "i2c", &xin24m),
- CLK("rk30_i2c.2", "i2c", &xin24m),
- CLK("rk30_i2c.3", "i2c", &xin24m),
- CLK("rk30_i2c.4", "i2c", &xin24m),
- CLK("rk29xx_spim.0", "spi", &xin24m),
- CLK("rk29xx_spim.1", "spi", &xin24m),
-
- CLK("rk_serial.0", "uart_div", &xin24m),
- CLK("rk_serial.0", "uart_frac_div", &xin24m),
- CLK("rk_serial.0", "uart", &xin24m),
- CLK("rk_serial.0", "pclk_uart", &xin24m),
- CLK("rk_serial.1", "uart_div", &xin24m),
- CLK("rk_serial.1", "uart_frac_div", &xin24m),
- CLK("rk_serial.1", "uart", &xin24m),
- CLK("rk_serial.1", "pclk_uart", &xin24m),
- CLK("rk_serial.2", "uart_div", &xin24m),
- CLK("rk_serial.2", "uart_frac_div", &xin24m),
- CLK("rk_serial.2", "uart", &xin24m),
- CLK("rk_serial.2", "pclk_uart", &xin24m),
-
- CLK("rk29_i2s.1", "i2s_div", &xin24m),
- CLK("rk29_i2s.1", "i2s_frac_div", &xin24m),
- CLK("rk29_i2s.1", "i2s", &xin12m),
- CLK("rk29_i2s.1", "hclk_i2s", &xin24m),
-
- CLK("rk29_sdmmc.0","mmc",&xin24m),
- CLK("rk29_sdmmc.0","hclk_mmc",&xin24m),
- CLK("rk29_sdmmc.1","mmc",&xin24m),
- CLK("rk29_sdmmc.1","hclk_mmc",&xin24m),
-
- CLK(NULL,"pd_lcdc0",&xin24m),
- CLK(NULL,"hclk_lcdc0",&xin24m),
- CLK(NULL,"aclk_lcdc0",&xin24m),
- CLK(NULL,"dclk_lcdc0",&xin24m),
- CLK(NULL,"pd_lcdc1",&xin24m),
- CLK(NULL,"hclk_lcdc1",&xin24m),
- CLK(NULL,"aclk_lcdc1",&xin24m),
- CLK(NULL,"dclk_lcdc1",&xin24m),
-
- CLK(NULL,"pd_cif0",&xin24m),
- CLK(NULL,"aclk_cif0",&xin24m),
- CLK(NULL,"hclk_cif0",&xin24m),
- CLK(NULL,"cif0_in",&xin24m),
- CLK(NULL,"cif0_out",&xin24m),
-
- CLK(NULL,"pwm01",&xin24m),
-};
-
-static void __init fpga_clock_init(void)
-{
- struct clk_lookup *lk;
-
- for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) {
- clkdev_add(lk);
- }
-}
-
-void __init board_clock_init(void)
-{
- fpga_clock_init();
-}
-
-int __init clk_disable_unused(void)
-{
- return 0;
-}
-
-int clk_enable(struct clk *clk)
-{
- return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
- if (clk)
- return clk->rate;
- else
- return 24000000;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
- return 0;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
- return 0;
-}
-EXPORT_SYMBOL(clk_set_parent);
-
+++ /dev/null
-#include <../../mach-rk3188/include/mach/board.h>
+++ /dev/null
-#include <plat/clkdev.h>
+++ /dev/null
-#include <plat/clock.h>
+++ /dev/null
-#ifndef __MACH_CPU_AXI_H
-#define __MACH_CPU_AXI_H
-
-#include <plat/cpu_axi.h>
-
-#define CPU_AXI_BUS_BASE RK319X_CPU_AXI_BUS_BASE
-
-#endif
+++ /dev/null
-#include <plat/ddr.h>
+++ /dev/null
-#include <plat/debug-macro.S>
+++ /dev/null
-#include <../../mach-rk30/include/mach/debug_uart.h>
+++ /dev/null
-#include <plat/dma-pl330.h>
+++ /dev/null
-#ifndef RK_MACH_DVFS_H
-#define RK_MACH_DVFS_H
-
-#include <plat/dvfs.h>
-
-#ifdef CONFIG_DVFS
-int rk3188_dvfs_init(void);
-void dvfs_adjust_table_lmtvolt(struct clk *clk, struct cpufreq_frequency_table *table);
-#else
-static inline int rk3188_dvfs_init(void){ return 0; }
-static inline void dvfs_adjust_table_lmtvolt(struct clk *clk, struct cpufreq_frequency_table *table){}
-#endif
-
-#endif
+++ /dev/null
-#include <plat/entry-macro.S>
+++ /dev/null
-#include <plat/fiq.h>
+++ /dev/null
-#include <../../mach-rk30/include/mach/gpio.h>
+++ /dev/null
-#ifndef __MACH_GRF_H
-#define __MACH_GRF_H
-
-#include <asm/io.h>
-
-#define GRF_GPIO1A_IOMUX 0x0010
-#define GRF_GPIO1B_IOMUX 0x0014
-#define GRF_GPIO1C_IOMUX 0x0018
-#define GRF_GPIO1D_IOMUX 0x001c
-#define GRF_GPIO2A_IOMUX 0x0020
-#define GRF_GPIO2B_IOMUX 0x0024
-#define GRF_GPIO2C_IOMUX 0x0028
-#define GRF_GPIO2D_IOMUX 0x002c
-#define GRF_GPIO3A_IOMUX 0x0030
-#define GRF_GPIO3B_IOMUX 0x0034
-#define GRF_GPIO3C_IOMUX 0x0038
-#define GRF_GPIO3D_IOMUX 0x003c
-#define GRF_GPIO4A_IOMUX 0x0040
-#define GRF_GPIO4B_IOMUX 0x0044
-#define GRF_GPIO4C_IOMUX 0x0048
-#define GRF_GPIO4D_IOMUX 0x004c
-
-#define GRF_SOC_CON0 0x0060
-#define GRF_SOC_CON1 0x0064
-#define GRF_SOC_CON2 0x0068
-#define GRF_SOC_CON3 0x006c
-#define GRF_SOC_CON4 0x0070
-#define GRF_SOC_STATUS0 0x0074
-#define GRF_SOC_STATUS1 0x0078
-#define GRF_SOC_STATUS2 0x007c
-#define GRF_DMAC1_CON0 0x0080
-#define GRF_DMAC1_CON1 0x0084
-#define GRF_DMAC1_CON2 0x0088
-#define GRF_DMAC2_CON0 0x008c
-#define GRF_DMAC2_CON1 0x0090
-#define GRF_DMAC2_CON2 0x0094
-#define GRF_DMAC2_CON3 0x0098
-#define GRF_CPU_CON0 0x009c
-#define GRF_CPU_CON1 0x00a0
-#define GRF_CPU_CON2 0x00a4
-#define GRF_CPU_CON3 0x00a8
-#define GRF_CPU_CON4 0x00ac
-#define GRF_CPU_CON5 0x00b0
-#define GRF_CPU_STATUS0 0x00b4
-#define GRF_CPU_STATUS1 0x00b8
-#define GRF_DDRC_CON0 0x00bc
-#define GRF_DDRC_STAT 0x00c0
-#define GRF_UOC0_CON0 0x00c4
-#define GRF_UOC0_CON1 0x00c8
-#define GRF_UOC0_CON2 0x00cc
-#define GRF_UOC0_CON3 0x00d0
-#define GRF_UOC1_CON0 0x00d4
-#define GRF_UOC1_CON1 0x00d8
-#define GRF_UOC2_CON0 0x00e4
-#define GRF_UOC2_CON1 0x00e8
-#define GRF_UOC3_CON0 0x00ec
-#define GRF_UOC3_CON1 0x00f0
-#define GRF_PVTM_CON0 0x00f4
-#define GRF_PVTM_CON1 0x00f8
-#define GRF_PVTM_CON2 0x00fc
-#define GRF_PVTM_STATUS0 0x0100
-#define GRF_PVTM_STATUS1 0x0104
-#define GRF_PVTM_STATUS2 0x0108
-
-#define GRF_NIF_FIFO0 0x0110
-#define GRF_NIF_FIFO1 0x0114
-#define GRF_NIF_FIFO2 0x0118
-#define GRF_NIF_FIFO3 0x011c
-#define GRF_OS_REG0 0x0120
-#define GRF_OS_REG1 0x0124
-#define GRF_OS_REG2 0x0128
-#define GRF_OS_REG3 0x012c
-#define GRF_SOC_CON5 0x0130
-#define GRF_SOC_CON6 0x0134
-#define GRF_SOC_CON7 0x0138
-#define GRF_SOC_CON8 0x013c
-
-#define GRF_GPIO1A_PULL 0x0144
-#define GRF_GPIO1B_PULL 0x0148
-#define GRF_GPIO1C_PULL 0x014c
-#define GRF_GPIO1D_PULL 0x0150
-#define GRF_GPIO2A_PULL 0x0154
-#define GRF_GPIO2B_PULL 0x0158
-#define GRF_GPIO2C_PULL 0x015c
-#define GRF_GPIO2D_PULL 0x0160
-#define GRF_GPIO3A_PULL 0x0164
-#define GRF_GPIO3B_PULL 0x0168
-#define GRF_GPIO3C_PULL 0x016c
-#define GRF_GPIO3D_PULL 0x0170
-#define GRF_GPIO4A_PULL 0x0174
-#define GRF_GPIO4B_PULL 0x0178
-#define GRF_GPIO4C_PULL 0x017c
-#define GRF_GPIO4D_PULL 0x0180
-
-#define GRF_IO_VSEL 0x018c
-
-#define GRF_GPIO1L_SR 0x0198
-#define GRF_GPIO1H_SR 0x019c
-#define GRF_GPIO2L_SR 0x01a0
-#define GRF_GPIO2H_SR 0x01a4
-#define GRF_GPIO3L_SR 0x01a8
-#define GRF_GPIO3H_SR 0x01ac
-#define GRF_GPIO4L_SR 0x01b0
-#define GRF_GPIO4H_SR 0x01b4
-
-#define GRF_GPIO1A_E 0x01c8
-#define GRF_GPIO1B_E 0x01cc
-#define GRF_GPIO1C_E 0x01d0
-#define GRF_GPIO1D_E 0x01d4
-#define GRF_GPIO2A_E 0x01d8
-#define GRF_GPIO2B_E 0x01dc
-#define GRF_GPIO2C_E 0x01e0
-#define GRF_GPIO2D_E 0x01e4
-#define GRF_GPIO3A_E 0x01e8
-#define GRF_GPIO3B_E 0x01ec
-#define GRF_GPIO3C_E 0x01f0
-#define GRF_GPIO3D_E 0x01f4
-#define GRF_GPIO4A_E 0x01f8
-#define GRF_GPIO4B_E 0x01fc
-#define GRF_GPIO4C_E 0x0200
-#define GRF_GPIO4D_E 0x0204
-
-#define GRF_FLASH_DATA_PULL 0x0210
-#define GRF_FLASH_DATA_E 0x0214
-#define GRF_FLASH_DATA_SR 0x0218
-
-#define GRF_USBPHY_CON0 0x0220
-#define GRF_USBPHY_CON1 0x0224
-#define GRF_USBPHY_CON2 0x0228
-#define GRF_USBPHY_CON3 0x022c
-#define GRF_USBPHY_CON4 0x0230
-#define GRF_USBPHY_CON5 0x0234
-#define GRF_USBPHY_CON6 0x0238
-#define GRF_USBPHY_CON7 0x023c
-#define GRF_USBPHY_CON8 0x0240
-#define GRF_USBPHY_CON9 0x0244
-#define GRF_USBPHY_CON10 0x0248
-#define GRF_USBPHY_CON11 0x024c
-#define GRF_DFI_STAT0 0x0250
-#define GRF_DFI_STAT1 0x0254
-#define GRF_DFI_STAT2 0x0258
-#define GRF_DFI_STAT3 0x025c
-
-#define GRF_SECURE_BOOT_STATUS 0x0300
-
-#define BB_GRF_GPIO0A_IOMUX 0x0000
-#define BB_GRF_GPIO0B_IOMUX 0x0004
-#define BB_GRF_GPIO0C_IOMUX 0x0008
-#define BB_GRF_GPIO0D_IOMUX 0x000c
-#define BB_GRF_GPIO0A_DRV 0x0010
-#define BB_GRF_GPIO0B_DRV 0x0014
-#define BB_GRF_GPIO0C_DRV 0x0018
-#define BB_GRF_GPIO0D_DRV 0x001c
-#define BB_GRF_GPIO0A_PULL 0x0020
-#define BB_GRF_GPIO0B_PULL 0x0024
-#define BB_GRF_GPIO0C_PULL 0x0028
-#define BB_GRF_GPIO0D_PULL 0x002c
-#define BB_GRF_GPIO0L_SR 0x0030
-#define BB_GRF_GPIO0H_SR 0x0034
-
-#define BB_GRF_GLB_CON0 0x0040
-#define BB_GRF_GLB_CON1 0x0044
-#define BB_GRF_GLB_CON2 0x0048
-#define BB_GRF_GLB_CON3 0x004c
-#define BB_GRF_GLB_CON4 0x0050
-
-#define BB_GRF_GLB_STS0 0x0060
-
-enum grf_io_power_domain_voltage {
- IO_PD_VOLTAGE_3_3V = 0,
- IO_PD_VOLTAGE_2_5V = IO_PD_VOLTAGE_3_3V,
- IO_PD_VOLTAGE_1_8V = 1,
-};
-
-enum grf_io_power_domain {
- IO_PD_LCDC = 0,
- IO_PD_CIF,
- IO_PD_FLASH,
- IO_PD_WIFI_BT,
- IO_PD_AUDIO,
- IO_PD_GPIO0,
- IO_PD_GPIO1,
-};
-
-static inline void grf_set_io_power_domain_voltage(enum grf_io_power_domain pd, enum grf_io_power_domain_voltage volt)
-{
- writel_relaxed((0x10000 + volt) << pd, RK30_GRF_BASE + GRF_IO_VSEL);
- dsb();
-}
-
-static inline enum grf_io_power_domain_voltage grf_get_io_power_domain_voltage(enum grf_io_power_domain pd)
-{
- return (readl_relaxed(RK30_GRF_BASE + GRF_IO_VSEL) >> pd) & 1;
-}
-
-#endif
+++ /dev/null
-#ifndef __MACH_HARDWARE_H
-#define __MACH_HARDWARE_H
-
-#endif
+++ /dev/null
-#ifndef __MACH_IO_H
-#define __MACH_IO_H
-
-#include <plat/io.h>
-
-/*
- * RK319X IO memory map:
- *
- * Virt Phys Size What
- * ---------------------------------------------------------------------------
- * FDFF0000
- * FE900000 FE600000 1M BB
- * FEA00000 FFA00000 1M
- * FFB00000 1M Peri AXI BUS
- * FEB00000 FFC00000 4M
- * FEC00000 FFD00000
- * FED00000 FFE00000
- * FEE00000 FFF00000
- * FEF00000 FFCD0000 32K SRAM
- */
-
-#define RK319X_IO_TO_VIRT0(pa) IOMEM((pa) - 0xFE600000 + 0xFE900000)
-#define RK319X_IO_TO_VIRT1(pa) IOMEM((pa) - 0xFFA00000 + 0xFEA00000)
-#define RK319X_IO_TO_VIRT2(pa) IOMEM((pa) - 0xFFC00000 + 0xFEB00000)
-
-#define IO_ADDRESS(pa) IOMEM( \
- ((pa) >= 0xFE600000 && (pa) < 0xFE700000) ? RK319X_IO_TO_VIRT0(pa) : \
- ((pa) >= 0xFFA00000 && (pa) < 0xFFB00000) ? RK319X_IO_TO_VIRT1(pa) : \
- ((pa) >= 0xFFC00000 && (pa) <= 0xFFFFFFFF) ? RK319X_IO_TO_VIRT2(pa) : \
- 0)
-
-#define RK319X_BOOT_RAM_PHYS 0xFDFF0000
-#define RK319X_BOOT_RAM_SIZE SZ_4K
-
-#define RK319X_PMU_PHYS 0xFE600000
-#define RK319X_PMU_BASE IO_ADDRESS(RK319X_PMU_PHYS)
-#define RK319X_PMU_SIZE SZ_64K
-
-#define RK319X_BB_GRF_PHYS 0xFE620000
-#define RK319X_BB_GRF_BASE IO_ADDRESS(RK319X_BB_GRF_PHYS)
-#define RK319X_BB_GRF_SIZE SZ_64K
-
-#define RK319X_MAILBOX_PHYS 0xFE650000
-#define RK319X_MAILBOX_SIZE SZ_64K
-
-#define RK319X_GPIO0_PHYS 0xFE680000
-#define RK319X_GPIO0_BASE IO_ADDRESS(RK319X_GPIO0_PHYS)
-#define RK319X_GPIO0_SIZE SZ_8K
-
-#define RK319X_SMC_BANK0_PHYS 0xFE800000
-#define RK319X_SMC_BANK0_SIZE SZ_8M
-#define RK319X_SMC_BANK1_PHYS 0xFF000000
-#define RK319X_SMC_BANK1_SIZE SZ_8M
-#define RK319X_USBOTG20_PHYS 0xFF800000
-#define RK319X_USBOTG20_SIZE SZ_256K
-#define RK319X_USBHOST20_PHYS 0xFF840000
-#define RK319X_USBHOST20_SIZE SZ_256K
-#define RK319X_HSIC_PHYS 0xFF880000
-#define RK319X_HSIC_SIZE SZ_256K
-#define RK319X_NANDC_PHYS 0xFF8C0000
-#define RK319X_NANDC_SIZE SZ_32K
-#define RK319X_CRYPTO_PHYS 0xFF8C8000
-#define RK319X_CRYPTO_SIZE SZ_32K
-
-#define RK319X_EMMC_PHYS 0xFF900000
-#define RK319X_EMMC_SIZE SZ_64K
-#define RK319X_SDIO_PHYS 0xFF910000
-#define RK319X_SDIO_SIZE SZ_64K
-#define RK319X_SDMMC0_PHYS 0xFF920000
-#define RK319X_SDMMC0_SIZE SZ_64K
-
-#define RK319X_HSADC_PHYS 0xFF980000
-#define RK319X_HSADC_SIZE SZ_64K
-#define RK319X_GPS_PHYS 0xFF990000
-#define RK319X_GPS_SIZE SZ_64K
-
-#define RK319X_SARADC_PHYS 0xFFA00000
-#define RK319X_SARADC_SIZE SZ_64K
-
-#define RK319X_SPI0_PHYS 0xFFA10000
-#define RK319X_SPI0_SIZE SZ_64K
-#define RK319X_SPI1_PHYS 0xFFA20000
-#define RK319X_SPI1_SIZE SZ_64K
-#define RK319X_I2C2_PHYS 0xFFA30000
-#define RK319X_I2C2_SIZE SZ_64K
-#define RK319X_I2C3_PHYS 0xFFA40000
-#define RK319X_I2C3_SIZE SZ_64K
-#define RK319X_I2C4_PHYS 0xFFA50000
-#define RK319X_I2C4_SIZE SZ_64K
-#define RK319X_UART0_PHYS 0xFFA60000
-#define RK319X_UART0_BASE RK319X_IO_TO_VIRT1(RK319X_UART0_PHYS)
-#define RK319X_UART0_SIZE SZ_64K
-#define RK319X_UART1_PHYS 0xFFA70000
-#define RK319X_UART1_BASE RK319X_IO_TO_VIRT1(RK319X_UART1_PHYS)
-#define RK319X_UART1_SIZE SZ_64K
-#define RK319X_UART2_PHYS 0xFFA80000
-#define RK319X_UART2_BASE RK319X_IO_TO_VIRT1(RK319X_UART2_PHYS)
-#define RK319X_UART2_SIZE SZ_64K
-#define RK319X_UART3_PHYS 0xFFA90000
-#define RK319X_UART3_BASE RK319X_IO_TO_VIRT1(RK319X_UART3_PHYS)
-#define RK319X_UART3_SIZE SZ_64K
-#define RK319X_WDT_PHYS 0xFFAA0000
-#define RK319X_WDT_SIZE SZ_64K
-
-#define RK319X_DMAC2_PHYS 0xFFAD0000
-#define RK319X_DMAC2_SIZE SZ_64K
-#define RK319X_SMC_PHYS 0xFFAE0000
-#define RK319X_SMC_SIZE SZ_64K
-#define RK319X_TSADC_PHYS 0xFFAF0000
-#define RK319X_TSADC_SIZE SZ_64K
-#define RK319X_PERI_AXI_BUS_PHYS 0xFFB00000
-#define RK319X_PERI_AXI_BUS_SIZE SZ_1M
-#define RK319X_ROM_PHYS 0xFFC00000
-#define RK319X_ROM_BASE IO_ADDRESS(RK319X_ROM_PHYS)
-#define RK319X_ROM_SIZE SZ_64K
-#define RK319X_I2S1_2CH_PHYS 0xFFC10000
-#define RK319X_I2S1_2CH_SIZE SZ_64K
-#define RK319X_SPDIF_PHYS 0xFFC20000
-#define RK319X_SPDIF_SIZE SZ_64K
-
-#define RK319X_LCDC0_PHYS 0xFFC40000
-#define RK319X_LCDC0_SIZE SZ_64K
-#define RK319X_LCDC1_PHYS 0xFFC50000
-#define RK319X_LCDC1_SIZE SZ_64K
-#define RK319X_CIF0_PHYS 0xFFC60000
-#define RK319X_CIF0_SIZE SZ_64K
-#define RK319X_RGA_PHYS 0xFFC70000
-#define RK319X_RGA_SIZE SZ_64K
-#define RK319X_IEP_PHYS 0xFFC80000
-#define RK319X_IEP_SIZE SZ_64K
-#define RK319X_MIPI_DSI_HOST_PHYS 0xFFC90000
-#define RK319X_MIPI_DSI_HOST_SIZE SZ_64K
-#define RK319X_ISP_PHYS 0xFFCA0000
-#define RK319X_ISP_SIZE SZ_64K
-#define RK319X_VCODEC_PHYS 0xFFCB0000
-#define RK319X_VCODEC_SIZE SZ_64K
-#define RK319X_CPU_AXI_BUS_PHYS 0xFFCC0000
-#define RK319X_CPU_AXI_BUS_BASE IO_ADDRESS(RK319X_CPU_AXI_BUS_PHYS)
-#define RK319X_CPU_AXI_BUS_SIZE SZ_64K
-#define RK319X_IMEM_PHYS 0xFFCD0000
-#define RK319X_IMEM_BASE IOMEM(0xFEF00000)
-#define RK319X_IMEM_NONCACHED IO_ADDRESS(RK319X_IMEM_PHYS)
-#define RK319X_IMEM_SIZE SZ_32K
-
-#define RK319X_GPU_PHYS 0xFFD00000
-#define RK319X_GPU_SIZE SZ_64K
-
-#define RK319X_TZPC_PHYS 0xFFD20000
-#define RK319X_TZPC_SIZE SZ_64K
-#define RK319X_EFUSE_PHYS 0xFFD30000
-#define RK319X_EFUSE_BASE IO_ADDRESS(RK319X_EFUSE_PHYS)
-#define RK319X_EFUSE_SIZE SZ_64K
-#define RK319X_DMACS1_PHYS 0xFFD40000
-#define RK319X_DMACS1_SIZE SZ_64K
-
-#define RK319X_PWM_PHYS 0xFFD60000
-#define RK319X_PWM_BASE IO_ADDRESS(RK319X_PWM_PHYS)
-#define RK319X_PWM_SIZE SZ_64K
-
-#define RK319X_I2C0_PHYS 0xFFD80000
-#define RK319X_I2C0_SIZE SZ_64K
-#define RK319X_I2C1_PHYS 0xFFD90000
-#define RK319X_I2C1_BASE IO_ADDRESS(RK319X_I2C1_PHYS)
-#define RK319X_I2C1_SIZE SZ_64K
-#define RK319X_DMAC1_PHYS 0xFFDA0000
-#define RK319X_DMAC1_SIZE SZ_64K
-#define RK319X_DDR_PCTL_PHYS 0xFFDB0000
-#define RK319X_DDR_PCTL_BASE IO_ADDRESS(RK319X_DDR_PCTL_PHYS)
-#define RK319X_DDR_PCTL_SIZE SZ_64K
-#define RK319X_DDR_PUBL_PHYS 0xFFDC0000
-#define RK319X_DDR_PUBL_BASE IO_ADDRESS(RK319X_DDR_PUBL_PHYS)
-#define RK319X_DDR_PUBL_SIZE SZ_64K
-
-#define RK319X_CPU_DEBUG_PHYS 0xFFDE0000
-#define RK319X_CPU_DEBUG_SIZE SZ_128K
-#define RK319X_CRU_PHYS 0xFFE00000
-#define RK319X_CRU_BASE IO_ADDRESS(RK319X_CRU_PHYS)
-#define RK319X_CRU_SIZE SZ_64K
-#define RK319X_GRF_PHYS 0xFFE10000
-#define RK319X_GRF_BASE IO_ADDRESS(RK319X_GRF_PHYS)
-#define RK319X_GRF_SIZE SZ_64K
-#define RK319X_TIMER_PHYS 0xFFE20000
-#define RK319X_TIMER_BASE IO_ADDRESS(RK319X_TIMER_PHYS)
-#define RK319X_TIMER_SIZE SZ_64K
-#define RK319X_ACODEC_PHYS 0xFFE30000
-#define RK319X_ACODEC_SIZE SZ_16K
-#define RK319X_HDMI_PHYS 0xFFE34000
-#define RK319X_HDMI_SIZE SZ_16K
-#define RK319X_MIPI_DSI_PHY_PHYS 0xFFE38000
-#define RK319X_MIPI_DSI_PHY_SIZE SZ_16K
-
-#define RK319X_GPIO1_PHYS 0xFFE40000
-#define RK319X_GPIO1_BASE IO_ADDRESS(RK319X_GPIO1_PHYS)
-#define RK319X_GPIO1_SIZE SZ_64K
-#define RK319X_GPIO2_PHYS 0xFFE50000
-#define RK319X_GPIO2_BASE IO_ADDRESS(RK319X_GPIO2_PHYS)
-#define RK319X_GPIO2_SIZE SZ_64K
-#define RK319X_GPIO3_PHYS 0xFFE60000
-#define RK319X_GPIO3_BASE IO_ADDRESS(RK319X_GPIO3_PHYS)
-#define RK319X_GPIO3_SIZE SZ_64K
-#define RK319X_GPIO4_PHYS 0xFFE70000
-#define RK319X_GPIO4_BASE IO_ADDRESS(RK319X_GPIO4_PHYS)
-#define RK319X_GPIO4_SIZE SZ_64K
-
-#define RK319X_L2C_PHYS 0xFFF00000
-#define RK319X_L2C_BASE IO_ADDRESS(RK319X_L2C_PHYS)
-#define RK319X_L2C_SIZE SZ_16K
-#define RK319X_SCU_PHYS 0xFFF04000
-#define RK319X_SCU_BASE IO_ADDRESS(RK319X_SCU_PHYS)
-#define RK319X_SCU_SIZE SZ_256
-#define RK319X_GICC_PHYS 0xFFF04100
-#define RK319X_GICC_BASE RK319X_IO_TO_VIRT2(RK319X_GICC_PHYS)
-#define RK319X_GICC_SIZE SZ_256
-#define RK319X_GTIMER_PHYS 0xFFF04200
-#define RK319X_GTIMER_BASE IO_ADDRESS(RK319X_GTIMER_PHYS)
-#define RK319X_GTIMER_SIZE SZ_1K
-#define RK319X_PTIMER_PHYS 0xFFF04600
-#define RK319X_PTIMER_BASE IO_ADDRESS(RK319X_PTIMER_PHYS)
-#define RK319X_PTIMER_SIZE (SZ_2K + SZ_512)
-#define RK319X_GICD_PHYS 0xFFF05000
-#define RK319X_GICD_BASE IO_ADDRESS(RK319X_GICD_PHYS)
-#define RK319X_GICD_SIZE SZ_2K
-
-#define RK319X_BOOT_PHYS 0xFFFF0000
-#define RK319X_BOOT_BASE IO_ADDRESS(RK319X_BOOT_PHYS)
-
-#define RK319X_CORE_PHYS RK319X_L2C_PHYS
-#define RK319X_CORE_BASE RK319X_L2C_BASE
-#define RK319X_CORE_SIZE (RK319X_L2C_SIZE + SZ_8K)
-#define GIC_DIST_BASE RK319X_GICD_BASE
-#define GIC_CPU_BASE RK319X_GICC_BASE
-#define SRAM_NONCACHED RK319X_IMEM_NONCACHED
-#define SRAM_CACHED RK319X_IMEM_BASE
-#define SRAM_PHYS RK319X_IMEM_PHYS
-#define SRAM_SIZE RK319X_IMEM_SIZE
-
-#define RK30_PMU_PHYS RK319X_PMU_PHYS
-#define RK30_PMU_BASE RK319X_PMU_BASE
-#define RK30_PMU_SIZE RK319X_PMU_SIZE
-#define RK30_GPIO0_PHYS RK319X_GPIO0_PHYS
-#define RK30_GPIO0_BASE RK319X_GPIO0_BASE
-#define RK30_GPIO0_SIZE RK319X_GPIO0_SIZE
-#define RK30_GPIO1_PHYS RK319X_GPIO1_PHYS
-#define RK30_GPIO1_BASE RK319X_GPIO1_BASE
-#define RK30_GPIO1_SIZE RK319X_GPIO1_SIZE
-#define RK30_GPIO2_PHYS RK319X_GPIO2_PHYS
-#define RK30_GPIO2_BASE RK319X_GPIO2_BASE
-#define RK30_GPIO2_SIZE RK319X_GPIO2_SIZE
-#define RK30_GPIO3_PHYS RK319X_GPIO3_PHYS
-#define RK30_GPIO3_BASE RK319X_GPIO3_BASE
-#define RK30_GPIO3_SIZE RK319X_GPIO3_SIZE
-#define RK30_GPIO4_PHYS RK319X_GPIO4_PHYS
-#define RK30_GPIO4_BASE RK319X_GPIO4_BASE
-#define RK30_GPIO4_SIZE RK319X_GPIO4_SIZE
-#define RK30_SMC_BANK0_PHYS RK319X_SMC_BANK0_PHYS
-#define RK30_SMC_BANK0_SIZE RK319X_SMC_BANK0_SIZE
-#define RK30_SMC_BANK1_PHYS RK319X_SMC_BANK1_PHYS
-#define RK30_SMC_BANK1_SIZE RK319X_SMC_BANK1_SIZE
-#define RK30_USBOTG20_PHYS RK319X_USBOTG20_PHYS
-#define RK30_USBOTG20_SIZE RK319X_USBOTG20_SIZE
-#define RK30_USBHOST20_PHYS RK319X_USBHOST20_PHYS
-#define RK30_USBHOST20_SIZE RK319X_USBHOST20_SIZE
-#define RK30_HSIC_PHYS RK319X_HSIC_PHYS
-#define RK30_HSIC_SIZE RK319X_HSIC_SIZE
-#define RK30_NANDC_PHYS RK319X_NANDC_PHYS
-#define RK30_NANDC_SIZE RK319X_NANDC_SIZE
-#define RK30_EMMC_PHYS RK319X_EMMC_PHYS
-#define RK30_EMMC_SIZE RK319X_EMMC_SIZE
-#define RK30_SDIO_PHYS RK319X_SDIO_PHYS
-#define RK30_SDIO_SIZE RK319X_SDIO_SIZE
-#define RK30_SDMMC0_PHYS RK319X_SDMMC0_PHYS
-#define RK30_SDMMC0_SIZE RK319X_SDMMC0_SIZE
-#define RK30_HSADC_PHYS RK319X_HSADC_PHYS
-#define RK30_HSADC_SIZE RK319X_HSADC_SIZE
-#define RK30_GPS_PHYS RK319X_GPS_PHYS
-#define RK30_GPS_SIZE RK319X_GPS_SIZE
-#define RK30_SARADC_PHYS RK319X_SARADC_PHYS
-#define RK30_SARADC_SIZE RK319X_SARADC_SIZE
-#define RK30_SPI0_PHYS RK319X_SPI0_PHYS
-#define RK30_SPI0_SIZE RK319X_SPI0_SIZE
-#define RK30_SPI1_PHYS RK319X_SPI1_PHYS
-#define RK30_SPI1_SIZE RK319X_SPI1_SIZE
-#define RK30_I2C0_PHYS RK319X_I2C0_PHYS
-#define RK30_I2C0_SIZE RK319X_I2C0_SIZE
-#define RK30_I2C1_PHYS RK319X_I2C1_PHYS
-#define RK30_I2C1_BASE RK319X_I2C1_BASE
-#define RK30_I2C1_SIZE RK319X_I2C1_SIZE
-#define RK30_I2C2_PHYS RK319X_I2C2_PHYS
-#define RK30_I2C2_SIZE RK319X_I2C2_SIZE
-#define RK30_I2C3_PHYS RK319X_I2C3_PHYS
-#define RK30_I2C3_SIZE RK319X_I2C3_SIZE
-#define RK30_I2C4_PHYS RK319X_I2C4_PHYS
-#define RK30_I2C4_SIZE RK319X_I2C4_SIZE
-#define RK30_UART0_PHYS RK319X_UART0_PHYS
-#define RK30_UART0_BASE RK319X_UART0_BASE
-#define RK30_UART0_SIZE RK319X_UART0_SIZE
-#define RK30_UART1_PHYS RK319X_UART1_PHYS
-#define RK30_UART1_BASE RK319X_UART1_BASE
-#define RK30_UART1_SIZE RK319X_UART1_SIZE
-#define RK30_UART2_PHYS RK319X_UART2_PHYS
-#define RK30_UART2_BASE RK319X_UART2_BASE
-#define RK30_UART2_SIZE RK319X_UART2_SIZE
-#define RK30_UART3_PHYS RK319X_UART3_PHYS
-#define RK30_UART3_BASE RK319X_UART3_BASE
-#define RK30_UART3_SIZE RK319X_UART3_SIZE
-#define RK30_WDT_PHYS RK319X_WDT_PHYS
-#define RK30_WDT_SIZE RK319X_WDT_SIZE
-#define RK30_DMAC2_PHYS RK319X_DMAC2_PHYS
-#define RK30_DMAC2_SIZE RK319X_DMAC2_SIZE
-#define RK30_SMC_PHYS RK319X_SMC_PHYS
-#define RK30_SMC_SIZE RK319X_SMC_SIZE
-#define RK30_TSADC_PHYS RK319X_TSADC_PHYS
-#define RK30_TSADC_SIZE RK319X_TSADC_SIZE
-#define RK30_PERI_AXI_BUS_PHYS RK319X_PERI_AXI_BUS_PHYS
-#define RK30_PERI_AXI_BUS_SIZE RK319X_PERI_AXI_BUS_SIZE
-#define RK30_ROM_PHYS RK319X_ROM_PHYS
-#define RK30_ROM_BASE RK319X_ROM_BASE
-#define RK30_ROM_SIZE RK319X_ROM_SIZE
-#define RK30_I2S1_2CH_PHYS RK319X_I2S1_2CH_PHYS
-#define RK30_I2S1_2CH_SIZE RK319X_I2S1_2CH_SIZE
-#define RK30_SPDIF_PHYS RK319X_SPDIF_PHYS
-#define RK30_SPDIF_SIZE RK319X_SPDIF_SIZE
-#define RK30_LCDC0_PHYS RK319X_LCDC0_PHYS
-#define RK30_LCDC0_SIZE RK319X_LCDC0_SIZE
-#define RK30_LCDC1_PHYS RK319X_LCDC1_PHYS
-#define RK30_LCDC1_SIZE RK319X_LCDC1_SIZE
-#define RK30_CIF0_PHYS RK319X_CIF0_PHYS
-#define RK30_CIF0_SIZE RK319X_CIF0_SIZE
-#define RK30_RGA_PHYS RK319X_RGA_PHYS
-#define RK30_RGA_SIZE RK319X_RGA_SIZE
-#define RK30_VCODEC_PHYS RK319X_VCODEC_PHYS
-#define RK30_VCODEC_SIZE RK319X_VCODEC_SIZE
-#define RK30_CPU_AXI_BUS_PHYS RK319X_CPU_AXI_BUS_PHYS
-#define RK30_CPU_AXI_BUS_BASE RK319X_CPU_AXI_BUS_BASE
-#define RK30_CPU_AXI_BUS_SIZE RK319X_CPU_AXI_BUS_SIZE
-#define RK30_IMEM_PHYS RK319X_IMEM_PHYS
-#define RK30_IMEM_BASE RK319X_IMEM_BASE
-#define RK30_IMEM_NONCACHED RK319X_IMEM_NONCACHED
-#define RK30_IMEM_SIZE RK319X_IMEM_SIZE
-#define RK3188_IMEM_SIZE RK319X_IMEM_SIZE
-#define RK30_GPU_PHYS RK319X_GPU_PHYS
-#define RK30_GPU_SIZE RK319X_GPU_SIZE
-#define RK30_TZPC_PHYS RK319X_TZPC_PHYS
-#define RK30_TZPC_SIZE RK319X_TZPC_SIZE
-#define RK30_EFUSE_PHYS RK319X_EFUSE_PHYS
-#define RK30_EFUSE_BASE RK319X_EFUSE_BASE
-#define RK30_EFUSE_SIZE RK319X_EFUSE_SIZE
-#define RK30_DMACS1_PHYS RK319X_DMACS1_PHYS
-#define RK30_DMACS1_SIZE RK319X_DMACS1_SIZE
-#define RK30_PWM_PHYS RK319X_PWM_PHYS
-#define RK30_PWM_BASE RK319X_PWM_BASE
-#define RK30_PWM_SIZE RK319X_PWM_SIZE
-#define RK30_DMAC1_PHYS RK319X_DMAC1_PHYS
-#define RK30_DMAC1_SIZE RK319X_DMAC1_SIZE
-#define RK30_DDR_PCTL_PHYS RK319X_DDR_PCTL_PHYS
-#define RK30_DDR_PCTL_BASE RK319X_DDR_PCTL_BASE
-#define RK30_DDR_PCTL_SIZE RK319X_DDR_PCTL_SIZE
-#define RK30_DDR_PUBL_PHYS RK319X_DDR_PUBL_PHYS
-#define RK30_DDR_PUBL_BASE RK319X_DDR_PUBL_BASE
-#define RK30_DDR_PUBL_SIZE RK319X_DDR_PUBL_SIZE
-#define RK30_CPU_DEBUG_PHYS RK319X_CPU_DEBUG_PHYS
-#define RK30_CPU_DEBUG_SIZE RK319X_CPU_DEBUG_SIZE
-#define RK30_CRU_PHYS RK319X_CRU_PHYS
-#define RK30_CRU_BASE RK319X_CRU_BASE
-#define RK30_CRU_SIZE RK319X_CRU_SIZE
-#define RK30_GRF_PHYS RK319X_GRF_PHYS
-#define RK30_GRF_BASE RK319X_GRF_BASE
-#define RK30_GRF_SIZE RK319X_GRF_SIZE
-#define RK30_HDMI_PHYS RK319X_HDMI_PHYS
-#define RK30_HDMI_SIZE RK319X_HDMI_SIZE
-#define RK30_L2C_PHYS RK319X_L2C_PHYS
-#define RK30_L2C_BASE RK319X_L2C_BASE
-#define RK30_L2C_SIZE RK319X_L2C_SIZE
-#define RK30_SCU_PHYS RK319X_SCU_PHYS
-#define RK30_SCU_BASE RK319X_SCU_BASE
-#define RK30_SCU_SIZE RK319X_SCU_SIZE
-#define RK30_GICC_PHYS RK319X_GICC_PHYS
-#define RK30_GICC_BASE RK319X_GICC_BASE
-#define RK30_GICC_SIZE RK319X_GICC_SIZE
-#define RK30_GTIMER_PHYS RK319X_GTIMER_PHYS
-#define RK30_GTIMER_BASE RK319X_GTIMER_BASE
-#define RK30_GTIMER_SIZE RK319X_GTIMER_SIZE
-#define RK30_PTIMER_PHYS RK319X_PTIMER_PHYS
-#define RK30_PTIMER_BASE RK319X_PTIMER_BASE
-#define RK30_PTIMER_SIZE RK319X_PTIMER_SIZE
-#define RK30_GICD_PHYS RK319X_GICD_PHYS
-#define RK30_GICD_BASE RK319X_GICD_BASE
-#define RK30_GICD_SIZE RK319X_GICD_SIZE
-#define RK30_CORE_PHYS RK319X_CORE_PHYS
-#define RK30_CORE_BASE RK319X_CORE_BASE
-#define RK30_CORE_SIZE RK319X_CORE_SIZE
-
-#endif
+++ /dev/null
-#ifndef __MACH_IOMUX_H
-#define __MACH_IOMUX_H
-
-#include <mach/grf.h>
-#include <mach/io.h>
-#include <plat/iomux.h>
-
-#define GRF_IOMUX_BASE RK319X_GRF_BASE
-
-enum{
- /* GPIO0_A */
- GPIO0_A0 = 0x0a00, TSADC_TSHUT,
- GPIO0_A5 = 0x0a50, BB_TCO4, SIM0_DET,
- GPIO0_A7 = 0x0a70, PMU_SLEEP,
-
- /* GPIO0_B */
- GPIO0_B0 = 0x0b00, I2C4_SDA_T0, SIM1_DET,
- GPIO0_B1 = 0x0b10, I2C4_SCL_T0, /*BB_TCO4,*/
- GPIO0_B3 = 0x0b30, BB_TCO5 = GPIO0_B3 + 2,
- GPIO0_B4 = 0x0b40, BB_TCO6 = GPIO0_B4 + 2, SIM1_VCCSEL,
- GPIO0_B5 = 0x0b50, I2C0_SDA,
- GPIO0_B6 = 0x0b60, I2C0_SCL,
- GPIO0_B7 = 0x0b70, TEST_CLK_OUT, BB_TCO7, SIM0_VCCSEL,
-
- /* GPIO0_C */
- GPIO0_C2 = 0x0c20, SIM0_CLK,
- GPIO0_C3 = 0x0c30, SIM0_RSTN,
- GPIO0_C4 = 0x0c40, SIM0_DATA,
- GPIO0_C5 = 0x0c50, SIM1_CLK, BB_LPC0, BB_TCO0,
- GPIO0_C6 = 0x0c60, SIM1_RSTN, BB_LPC1, BB_TCO1,
- GPIO0_C7 = 0x0c70, SIM1_DATA, BB_LPC2, BB_TCO2,
-
- /* GPIO0_D */
- GPIO0_D0 = 0x0d00, RF_XCV_PDN, SPI0_RXD, UART1_SIN,
- GPIO0_D1 = 0x0d10, RF_XON, SPI0_TXD, UART1_SOUT,
- GPIO0_D2 = 0x0d20, RF_DATAEN, SPI0_CLK, UART1_CTSN,
- GPIO0_D3 = 0x0d30, RF_DATA, SPI0_CS0, UART1_RTSN,
- GPIO0_D4 = 0x0d40, RF_CTRLDATA, SPI0_CS1,
- GPIO0_D5 = 0x0d50, RF_CTRLEN,
- GPIO0_D6 = 0x0d60, RF_CTRLCLK,
- GPIO0_D7 = 0x0d70, RF_STROBE,
-
- /* GPIO1_A */
- GPIO1_A0 = 0x1a00, LCDC_DCLK, SMC_D0,
- GPIO1_A1 = 0x1a10, LCDC_VSYNC, SMC_D1,
- GPIO1_A2 = 0x1a20, LCDC_HSYNC, SMC_D2,
- GPIO1_A3 = 0x1a30, LCDC_DEN, SMC_D3,
- GPIO1_A4 = 0x1a40, LCDC_D0, SMC_D4, ARM9_JTAG_TCK,
- GPIO1_A5 = 0x1a50, LCDC_D1, SMC_D5, ARM9_JTAG_TRSTN,
- GPIO1_A6 = 0x1a60, LCDC_D2, SMC_D6, ARM9_JTAG_TMS,
- GPIO1_A7 = 0x1a70, LCDC_D3, SMC_D7, ARM9_JTAG_TDO,
-
- /* GPIO1_B */
- GPIO1_B0 = 0x1b00, LCDC_D4, SMC_R0, ARM9_JTAG_TDI,
- GPIO1_B1 = 0x1b10, LCDC_D5, SMC_R1, ARM9_JTAG_SEL,
- GPIO1_B2 = 0x1b20, LCDC_D6, SMC_R2, CEVA_JTAG_TCK,
- GPIO1_B3 = 0x1b30, LCDC_D7, SMC_R3, CEVA_JTAG_TRSTN,
- GPIO1_B4 = 0x1b40, LCDC_D8, SMC_R4, CEVA_JTAG_TMS,
- GPIO1_B5 = 0x1b50, LCDC_D9, SMC_R5, CEVA_JTAG_TDO,
- GPIO1_B6 = 0x1b60, LCDC_D10, SMC_R6, CEVA_JTAG_TDI,
- GPIO1_B7 = 0x1b70, LCDC_D11, SMC_R7, CEVA_JTAG_SEL,
-
- /* GPIO1_C */
- GPIO1_C0 = 0x1c00, LCDC_D12, SMC_CS0,
- GPIO1_C1 = 0x1c10, LCDC_D13, SMC_WEN,
- GPIO1_C2 = 0x1c20, LCDC_D14, SMC_OEN,
- GPIO1_C3 = 0x1c30, LCDC_D15, SMC_ADVN,
- GPIO1_C4 = 0x1c40, LCDC_D16, SMC_BLSN0,
- GPIO1_C5 = 0x1c50, LCDC_D17, SMC_BLSN1,
- GPIO1_C6 = 0x1c60, LCDC_D18, SMC_CS1,
- GPIO1_C7 = 0x1c70, LCDC_D19,
-
- /* GPIO1_D */
- GPIO1_D0 = 0x1d00, LCDC_D20, UART3_CTSN, I2S2_SCLK_T0,
- GPIO1_D1 = 0x1d10, LCDC_D21, UART3_RTSN, I2S2_LRCK_T0,
- GPIO1_D2 = 0x1d20, LCDC_D22, UART3_SIN, I2S2_SDI_T0,
- GPIO1_D3 = 0x1d30, LCDC_D23, UART3_SOUT, I2S2_SDO_T0,
- GPIO1_D4 = 0x1d40, CIF0_D0, I2C3_SCL, HDMI_DDC_SCL,
- GPIO1_D5 = 0x1d50, CIF0_D1, I2C3_SDA, HDMI_DDC_SDA,
- GPIO1_D6 = 0x1d60, CIF0_D10,
- GPIO1_D7 = 0x1d70, CIF0_D11,
-
- /* GPIO2_A */
- GPIO2_A0 = 0x2a00, CIF0_D2, HSADC_D0, BB_DEBUG0,
- GPIO2_A1 = 0x2a10, CIF0_D3, HSADC_D1, BB_DEBUG1,
- GPIO2_A2 = 0x2a20, CIF0_D4, HSADC_D2, BB_DEBUG2,
- GPIO2_A3 = 0x2a30, CIF0_D5, HSADC_D3, BB_DEBUG3,
- GPIO2_A4 = 0x2a40, CIF0_D6, HSADC_D4, BB_DEBUG4,
- GPIO2_A5 = 0x2a50, CIF0_D7, HSADC_D5, BB_DEBUG5,
- GPIO2_A6 = 0x2a60, CIF0_D8, HSADC_D6, BB_DEBUG6,
- GPIO2_A7 = 0x2a70, CIF0_D9, HSADC_D7, BB_DEBUG7,
-
- /* GPIO2_B */
- GPIO2_B0 = 0x2b00, CIF0_CLKOUT, HSADC_CLKIN, HSADC_CLKOUT,
- GPIO2_B1 = 0x2b10, CIF0_VSYNC,
- GPIO2_B2 = 0x2b20, CIF0_HREF,
- GPIO2_B3 = 0x2b30, CIF0_CLKIN,
- GPIO2_B4 = 0x2b40, ISP_FL_TRIG,
- GPIO2_B5 = 0x2b50, ISP_FLASH_TRIG,
- GPIO2_B6 = 0x2b60, ISP_PRELIGHT_TRIG,
- GPIO2_B7 = 0x2b70, ISP_SHUTTER_TRIG,
-
- /* GPIO2_C */
- GPIO2_C0 = 0x2c00, ISP_SHUTTER_OPEN,
- GPIO2_C4 = 0x2c40, NAND_RDY,
- GPIO2_C5 = 0x2c50, NAND_WP, EMMC_PWREN,
- GPIO2_C6 = 0x2c60, NAND_RDN,
- GPIO2_C7 = 0x2c70, NAND_ALE,
-
- /* GPIO2_D */
- GPIO2_D0 = 0x2d00, NAND_CLE,
- GPIO2_D1 = 0x2d10, NAND_WRN, I2C4_SDA_T1,
- GPIO2_D2 = 0x2d20, NAND_CS0, I2C4_SCL_T1,
- GPIO2_D3 = 0x2d30, NAND_CS1,
- GPIO2_D4 = 0x2d40, NAND_CS2, EMMC_CMD, I2C2_SDA_T0,
- GPIO2_D5 = 0x2d50, NAND_CS3, EMMC_RSTNOUT, I2C2_SCL_T0,
- GPIO2_D6 = 0x2d60, NAND_DQS, EMMC_CLKOUT,
- GPIO2_D7 = 0x2d70, PWM0_T1,
-
- /* GPIO3_A */
- GPIO3_A0 = 0x3a00, UART0_SIN, TRACE_D0, BB_UART0_SIN,
- GPIO3_A1 = 0x3a10, UART0_SOUT, TRACE_D1, BB_UART0_SOUT,
- GPIO3_A2 = 0x3a20, UART0_CTSN, TRACE_D2, BB_UART0_CTSN,
- GPIO3_A3 = 0x3a30, UART0_RTSN, TRACE_D3, BB_UART0_RTSN,
- GPIO3_A4 = 0x3a40, MMC1_D0, TRACE_D4,
- GPIO3_A5 = 0x3a50, MMC1_D1, TRACE_D5,
- GPIO3_A6 = 0x3a60, MMC1_D2, TRACE_D6,
- GPIO3_A7 = 0x3a70, MMC1_D3, TRACE_D7,
-
- /* GPIO3_B */
- GPIO3_B0 = 0x3b00, MMC1_CMD, TRACE_D8,
- GPIO3_B1 = 0x3b10, MMC1_CLKOUT, TRACE_D9,
- GPIO3_B2 = 0x3b20, MMC1_DETN, TRACE_D10, I2S2_SCLK_T1,
- GPIO3_B3 = 0x3b30, MMC1_WRPRT, TRACE_D11, I2S2_LRCK_T1,
- GPIO3_B4 = 0x3b40, MMC1_PWREN, TRACE_D12, I2S2_SDI_T1,
- GPIO3_B5 = 0x3b50, MMC1_BKEPWR, TRACE_D13, I2S2_SDO_T1,
- GPIO3_B6 = 0x3b60, MMC1_INTN, TRACE_D14,
- GPIO3_B7 = 0x3b70, TRACE_D15 = GPIO3_B7 + 2,
-
- /* GPIO3_C */
- GPIO3_C0 = 0x3c00, I2S0_MCLK,
- GPIO3_C1 = 0x3c10, I2S0_SCLK,
- GPIO3_C2 = 0x3c20, I2S0_LRCKRX,
- GPIO3_C3 = 0x3c30, I2S0_LRCKTX,
- GPIO3_C4 = 0x3c40, I2S0_SDI,
- GPIO3_C5 = 0x3c50, I2S0_SDO,
- GPIO3_C6 = 0x3c60, I2S1_SCLK, TRACE_CLK, SMC_D8,
- GPIO3_C7 = 0x3c70, I2S1_LRCKRX, TRACE_CTL, SMC_D9,
-
- /* GPIO3_D */
- GPIO3_D0 = 0x3d00, I2S1_SDI, SMC_D11 = GPIO3_D0 + 3,
- GPIO3_D1 = 0x3d10, I2S1_SDO, SMC_D12 = GPIO3_D1 + 3,
- GPIO3_D2 = 0x3d20, SMC_D13 = GPIO3_D2 + 3,
- GPIO3_D3 = 0x3d30, SMC_D14 = GPIO3_D3 + 3,
- GPIO3_D4 = 0x3d40, SMC_D15 = GPIO3_D4 + 3,
- GPIO3_D5 = 0x3d50, I2C4_SDA,
- GPIO3_D6 = 0x3d60, I2C4_SCL,
- GPIO3_D7 = 0x3d70, I2S1_LRCKTX, SMC_D10 = GPIO3_D7 + 3,
-
- /* GPIO4_A */
- GPIO4_A0 = 0x4a00, MMC0_D0,
- GPIO4_A1 = 0x4a10, MMC0_D1,
- GPIO4_A2 = 0x4a20, MMC0_D2,
- GPIO4_A3 = 0x4a30, MMC0_D3,
- GPIO4_A4 = 0x4a40, MMC0_RSTNOUT,
- GPIO4_A5 = 0x4a50, MMC0_PWREN,
- GPIO4_A6 = 0x4a60, MMC0_CLKOUT,
- GPIO4_A7 = 0x4a70, MMC0_CMD,
-
- /* GPIO4_B */
- GPIO4_B0 = 0x4b00, MMC0_DETN,
- GPIO4_B1 = 0x4b10, MMC0_WRPRT,
- GPIO4_B2 = 0x4b20, UART3_SOUT_T0, GPS_SIG_T0, HDMI_CECSDA,
- GPIO4_B3 = 0x4b30, UART3_SIN_T0, GPS_MAG_T0, HDMI_HOTPLUGIN,
- GPIO4_B4 = 0x4b40, UART3_CTSN_T0, GPS_RFCLK_T0,
- GPIO4_B5 = 0x4b50, UART3_RTSN_T0,
- GPIO4_B6 = 0x4b60, PWM0_T0, BB_UART1_RTSN = GPIO4_B6 + 3,
- GPIO4_B7 = 0x4b70, PWM1_T0, JTAG_TRSTN, BB_UART1_CTSN,
-
- /* GPIO4_C */
- GPIO4_C0 = 0x4c00, UART2_SIN, JTAG_TDI, BB_UART1_SIN,
- GPIO4_C1 = 0x4c10, UART2_SOUT, JTAG_TDO, BB_UART1_SOUT,
- GPIO4_C2 = 0x4c20, I2C2_SDA_T1, I2C2_SDA = I2C2_SDA_T1,
- GPIO4_C3 = 0x4c30, I2C2_SCL_T1, I2C2_SCL = I2C2_SCL_T1,
- GPIO4_C4 = 0x4c40, PWM2_T0, JTAG_TCK, OTG_DRV_VBUS,
- GPIO4_C5 = 0x4c50, PWM3_T0, JTAG_TMS, HOST_DRV_VBUS,
- GPIO4_C7 = 0x4c70, I2C1_SDA,
-
- /* GPIO4_D */
- GPIO4_D0 = 0x4d00, I2C1_SCL,
- GPIO4_D1 = 0x4d10, PWM1_T1, SPI1_CS1, SPDIF_TX,
- GPIO4_D2 = 0x4d20, PWM3_T1, SPI1_CLK,
- GPIO4_D3 = 0x4d30, PWM2_T1, SPI1_CS0,
- GPIO4_D4 = 0x4d40, UART3_SIN_T1, SPI1_TXD, GPS_MAG_T1,
- GPIO4_D5 = 0x4d50, UART3_SOUT_T1, SPI1_RXD, GPS_SIG_T1,
- GPIO4_D6 = 0x4d60, UART3_CTSN_T1, GPS_RFCLK_T1 = GPIO4_D6 + 3,
- GPIO4_D7 = 0x4d70, UART3_RTSN_T1,
-};
-
-#define rk30_iomux_init() iomux_init()
-
-#endif
+++ /dev/null
-#ifndef __MACH_IRQS_H
-#define __MACH_IRQS_H
-
-#define FIQ_START 0
-
-#define IRQ_LOCALTIMER 29
-
-#define IRQ_DMAC1_0 32
-#define IRQ_DMAC1_1 33
-#define IRQ_DMAC2_0 34
-#define IRQ_DMAC2_1 35
-#define IRQ_DDR_PCTL 36
-#define IRQ_GPU_PP 37
-#define IRQ_GPU_MMU 38
-#define IRQ_GPU_GP 39
-#define IRQ_RGA 40
-#define IRQ_VEPU 41
-#define IRQ_VDPU 42
-#define IRQ_VPU_MMU 43
-#define IRQ_CIF0 44
-#define IRQ_LCDC0 45
-#define IRQ_LCDC1 46
-#define IRQ_PMU 47
-#define IRQ_USB_OTG 48
-#define IRQ_USB_HOST 49
-#define IRQ_HSIC 50
-#define IRQ_GPS 51
-#define IRQ_HSADC 52
-#define IRQ_SDMMC 53
-#define IRQ_SDIO 54
-#define IRQ_EMMC 55
-#define IRQ_SDMMC_DETECT 56
-#define IRQ_SDIO_DETECT 57
-#define IRQ_SARADC 58
-#define IRQ_NANDC 59
-#define IRQ_SMC 60
-#define IRQ_I2S1_2CH 61
-#define IRQ_TSADC 62
-#define IRQ_GPS_TIMER 63
-#define IRQ_SPDIF 64
-#define IRQ_UART0 65
-#define IRQ_UART1 66
-#define IRQ_UART2 67
-#define IRQ_UART3 68
-#define IRQ_SPI0 69
-#define IRQ_SPI1 70
-#define IRQ_I2C0 71
-#define IRQ_I2C1 72
-#define IRQ_I2C2 73
-#define IRQ_I2C3 74
-#define IRQ_I2C4 75
-#define IRQ_TIMER0 76
-#define IRQ_TIMER1 77
-#define IRQ_TIMER2 78
-#define IRQ_WDT 79
-#define IRQ_PWM0 80
-#define IRQ_PWM1 81
-#define IRQ_PWM2 82
-#define IRQ_PWM3 83
-#define IRQ_TIMER3 84
-#define IRQ_TIMER4 85
-#define IRQ_GPIO0 86
-#define IRQ_GPIO1 87
-#define IRQ_GPIO2 88
-#define IRQ_GPIO3 89
-#define IRQ_GPIO4 90
-#define IRQ_PERI_AHB_USB_ARBITER 91
-#define IRQ_IEP 92
-#define IRQ_OTG_BVALID 93
-#define IRQ_OTG0_ID 94
-#define IRQ_OTG0_LINESTATE 95
-#define IRQ_OTG1_LINESTATE 96
-#define IRQ_NOC_OBSRV 97
-#define IRQ_MIPI_DSI_CONTROLLER 98
-#define IRQ_HDMI 99
-#define IRQ_CRYPTO 100
-#define IRQ_ISP 101
-#define IRQ_RK_PWM 102
-#define IRQ_MAILBOX0 103
-#define IRQ_MAILBOX1 104
-#define IRQ_MAILBOX2 105
-#define IRQ_MAILBOX3 106
-#define IRQ_BB_DMA 107
-#define IRQ_BB_WDT 108
-#define IRQ_BB_I2S0 109
-#define IRQ_BB_I2S1 110
-#define IRQ_BB_PMU 111
-#define IRQ_SD_DETECT_DOUBLE_EDGE 112
-
-#define IRQ_UART_SIGNAL 115
-
-#define IRQ_ARM_PMU 156
-
-#define NR_GIC_IRQS (5 * 32)
-#define NR_GPIO_IRQS (5 * 32)
-#define NR_BOARD_IRQS 64
-#define NR_IRQS (NR_GIC_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS)
-
-#define IRQ_BOARD_BASE (NR_GIC_IRQS + NR_GPIO_IRQS)
-
-#endif
+++ /dev/null
-#include <plat/loader.h>
+++ /dev/null
-#ifndef __MACH_MEMORY_H
-#define __MACH_MEMORY_H
-
-#include <plat/memory.h>
-#include <mach/io.h>
-
-/*
- * SRAM memory whereabouts
- */
-#define SRAM_CODE_OFFSET (RK30_IMEM_BASE + 0x0000)
-#define SRAM_CODE_END (RK30_IMEM_BASE + 0x0FFF)
-#define SRAM_DATA_OFFSET (RK30_IMEM_BASE + 0x1000)
-#define SRAM_DATA_END (RK30_IMEM_BASE + 0x2FFF)
-
-#endif
+++ /dev/null
-#ifndef __MACH_PMU_H
-#define __MACH_PMU_H
-
-#include <linux/io.h>
-
-#define PMU_WAKEUP_CFG0 0x0000
-#define PMU_WAKEUP_CFG1 0x0004
-#define PMU_WAKEUP_CFG2 0x0008
-#define PMU_PWRDN_CON 0x000C
-#define PMU_PWRDN_ST 0x0010
-#define PMU_PWRMODE_CON 0x0014
-#define PMU_SFT_CON 0x0018
-#define PMU_INT_CON 0x001C
-#define PMU_INT_ST 0x0020
-#define PMU_GPIO_INT_ST 0x0024
-#define PMU_GPIO_2EDGE_INT_ST 0x0028
-#define PMU_NOC_REQ 0x002C
-#define PMU_NOC_ST 0x0030
-#define PMU_POWER_ST 0x0034
-#define PMU_OSC_CNT 0x0040
-#define PMU_PLLLOCK_CNT 0x0044
-#define PMU_PLLRST_CNT 0x0048
-#define PMU_STABLE_CNT 0x004C
-#define PMU_DDRIO_PWRON_CNT 0x0050
-#define PMU_WAKEUP_RST_CLR_CNT 0x005C
-#define PMU_DDR_SREF_ST 0x0064
-#define PMU_SYS_REG0 0x0070
-#define PMU_SYS_REG1 0x0074
-#define PMU_SYS_REG2 0x0078
-#define PMU_SYS_REG3 0x007C
-
-#define PMU_WAKEUP_CFG_BP 0x0120
-#define PMU_PWRDN_CON_BP 0x0124
-#define PMU_PWRMODE_CON_BP 0x0128
-#define PMU_SFT_CON_BP 0x012C
-#define PMU_INT_CON_BP 0x0130
-#define PMU_INT_ST_BP 0x0134
-#define PMU_PWRDN_ST_BP 0x0138
-#define PMU_NOC_REQ_BP 0x0140
-#define PMU_NOC_ST_BP 0x0144
-#define PMU_POWER_ST_BP 0x0148
-#define PMU_OSC_CNT_BP 0x014C
-#define PMU_PLLLOCK_CNT_BP 0x0150
-#define PMU_PLLRST_CNT_BP 0x0154
-#define PMU_SYS_REG0_BP 0x0170
-#define PMU_SYS_REG1_BP 0x0174
-#define PMU_SYS_REG2_BP 0x0178
-#define PMU_SYS_REG3_BP 0x017C
-
-#endif
+++ /dev/null
-#include <../../mach-rk30/include/mach/sram.h>
+++ /dev/null
-#include <plat/system.h>
+++ /dev/null
-#include <plat/timex.h>
+++ /dev/null
-#include <plat/uncompress.h>
+++ /dev/null
-#include <../../mach-rk30/include/mach/vmalloc.h>
+++ /dev/null
-/*
- *
- * Copyright (C) 2013 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <asm/page.h>
-#include <asm/mach/map.h>
-#include <mach/debug_uart.h>
-
-#define RK319X_DEVICE(name) { \
- .virtual = (unsigned long) RK319X_##name##_BASE, \
- .pfn = __phys_to_pfn(RK319X_##name##_PHYS), \
- .length = RK319X_##name##_SIZE, \
- .type = MT_DEVICE, \
- }
-
-static struct map_desc rk319x_io_desc[] __initdata = {
- RK319X_DEVICE(ROM),
- RK319X_DEVICE(CORE),
- RK319X_DEVICE(CPU_AXI_BUS),
-#if CONFIG_RK_DEBUG_UART == 0
- RK319X_DEVICE(UART0),
-#elif CONFIG_RK_DEBUG_UART == 1
- RK319X_DEVICE(UART1),
-#elif CONFIG_RK_DEBUG_UART == 2
- RK319X_DEVICE(UART2),
-#elif CONFIG_RK_DEBUG_UART == 3
- RK319X_DEVICE(UART3),
-#endif
- RK319X_DEVICE(GRF),
- RK319X_DEVICE(BB_GRF),
- RK319X_DEVICE(CRU),
- RK319X_DEVICE(PMU),
- RK319X_DEVICE(GPIO0),
- RK319X_DEVICE(GPIO1),
- RK319X_DEVICE(GPIO2),
- RK319X_DEVICE(GPIO3),
- RK319X_DEVICE(GPIO4),
- RK319X_DEVICE(TIMER),
- RK319X_DEVICE(EFUSE),
- RK319X_DEVICE(PWM),
- RK319X_DEVICE(DDR_PCTL),
- RK319X_DEVICE(DDR_PUBL),
-};
-
-void __init rk30_map_common_io(void)
-{
- iotable_init(rk319x_io_desc, ARRAY_SIZE(rk319x_io_desc));
-}
+++ /dev/null
-#include <linux/platform_device.h>
-#include <asm/mach/time.h>
-#include <mach/io.h>
-#include <mach/irqs.h>
-
-#define TIMER_NAME "rk_timer"
-#define BASE RK319X_TIMER_BASE
-#define OFFSET 0x20
-
-static struct resource rk_timer_resources[] __initdata = {
- {
- .name = "cs_base",
- .start = (unsigned long) BASE + 4 * OFFSET,
- .flags = IORESOURCE_MEM,
- }, {
- .name = "cs_clk",
- .start = (unsigned long) "timer4",
- }, {
- .name = "cs_pclk",
- .start = (unsigned long) "pclk_timer",
- },
-
- {
- .name = "ce_base0",
- .start = (unsigned long) BASE + 0 * OFFSET,
- .flags = IORESOURCE_MEM,
- }, {
- .name = "ce_irq0",
- .start = (unsigned long) IRQ_TIMER0,
- .flags = IORESOURCE_IRQ,
- }, {
- .name = "ce_clk0",
- .start = (unsigned long) "timer0",
- }, {
- .name = "ce_pclk0",
- .start = (unsigned long) "pclk_timer",
- },
-
- {
- .name = "ce_base1",
- .start = (unsigned long) BASE + 1 * OFFSET,
- .flags = IORESOURCE_MEM,
- }, {
- .name = "ce_irq1",
- .start = (unsigned long) IRQ_TIMER1,
- .flags = IORESOURCE_IRQ,
- }, {
- .name = "ce_clk1",
- .start = (unsigned long) "timer1",
- }, {
- .name = "ce_pclk1",
- .start = (unsigned long) "pclk_timer",
- },
-
- {
- .name = "ce_base2",
- .start = (unsigned long) BASE + 2 * OFFSET,
- .flags = IORESOURCE_MEM,
- }, {
- .name = "ce_irq2",
- .start = (unsigned long) IRQ_TIMER2,
- .flags = IORESOURCE_IRQ,
- }, {
- .name = "ce_clk2",
- .start = (unsigned long) "timer2",
- }, {
- .name = "ce_pclk2",
- .start = (unsigned long) "pclk_timer",
- },
-
- {
- .name = "ce_base3",
- .start = (unsigned long) BASE + 3 * OFFSET,
- .flags = IORESOURCE_MEM,
- }, {
- .name = "ce_irq3",
- .start = (unsigned long) IRQ_TIMER3,
- .flags = IORESOURCE_IRQ,
- }, {
- .name = "ce_clk3",
- .start = (unsigned long) "timer3",
- }, {
- .name = "ce_pclk3",
- .start = (unsigned long) "pclk_timer",
- },
-};
-
-static struct platform_device rk_timer_device __initdata = {
- .name = TIMER_NAME,
- .id = 0,
- .resource = rk_timer_resources,
- .num_resources = ARRAY_SIZE(rk_timer_resources),
-};
-
-static struct platform_device *rk_timer_devices[] __initdata = {
- &rk_timer_device,
-};
-
-static void __init rk_timer_init(void)
-{
- early_platform_add_devices(rk_timer_devices, ARRAY_SIZE(rk_timer_devices));
- early_platform_driver_register_all(TIMER_NAME);
- early_platform_driver_probe(TIMER_NAME, 1, 0);
-}
-
-struct sys_timer rk30_timer = {
- .init = rk_timer_init
-};
+++ /dev/null
-if PLAT_RK
-
-choice DDR_TYPE
- prompt "DDR Memory Type"
- default DDR_TYPE_DDR3_DEFAULT
-
-config DDR_TYPE_DDRII
- bool "DDRII"
- help
- Support for DDRII memory
-
-config DDR_TYPE_LPDDR
- bool "mobile DDR"
- help
- Support for mobile DDR, MCP device
-
-config DDR_TYPE_DDR3_800D
- bool "DDR3-800 5-5-5"
-
-config DDR_TYPE_DDR3_800E
- bool "DDR3-800 6-6-6"
-
-config DDR_TYPE_DDR3_1066E
- bool "DDR3-1066 6-6-6"
-
-config DDR_TYPE_DDR3_1066F
- bool "DDR3-1066 7-7-7"
-
-config DDR_TYPE_DDR3_1066G
- bool "DDR3-1066 8-8-8"
-
-config DDR_TYPE_DDR3_1333F
- bool "DDR3-1333 7-7-7"
-
-config DDR_TYPE_DDR3_1333G
- bool "DDR3-1333 8-8-8"
-
-config DDR_TYPE_DDR3_1333H
- bool "DDR3-1333 9-9-9"
-
-config DDR_TYPE_DDR3_1333J
- bool "DDR3-1333 10-10-10"
-
-config DDR_TYPE_DDR3_1600G
- bool "DDR3-1600 8-8-8"
-
-config DDR_TYPE_DDR3_1600H
- bool "DDR3-1600 9-9-9"
-
-config DDR_TYPE_DDR3_1600J
- bool "DDR3-1600 10-10-10"
-
-config DDR_TYPE_DDR3_1600K
- bool "DDR3-1600 11-11-11"
-
-config DDR_TYPE_DDR3_1866J
- bool "DDR3-1866 10-10-10"
-
-config DDR_TYPE_DDR3_1866K
- bool "DDR3-1866 11-11-11"
-
-config DDR_TYPE_DDR3_1866L
- bool "DDR3-1866 12-12-12"
-
-config DDR_TYPE_DDR3_1866M
- bool "DDR3-1866 13-13-13"
-
-config DDR_TYPE_DDR3_2133K
- bool "DDR3-2133 11-11-11"
-
-config DDR_TYPE_DDR3_2133L
- bool "DDR3-2133 12-12-12"
-
-config DDR_TYPE_DDR3_2133M
- bool "DDR3-2133 13-13-13"
-
-config DDR_TYPE_DDR3_2133N
- bool "DDR3-2133 14-14-14"
-
-config DDR_TYPE_DDR3_DEFAULT
- bool "DDR3 (Type default)"
-
-endchoice
-
-config EMMC_IO_3_3V
- bool "Emmc io domain voltage select 3.3v"
- depends on ARCH_RK3066B || ARCH_RK3188 || ARCH_RK319X
-
-config DDR_INIT_CHANGE_FREQ
- bool "Enable change DDR frequence when ddr_init"
- default y if ARCH_RK2928 || ARCH_RK30XX
- default n if ARCH_RK3066B || ARCH_RK3188
-
-
-config DDR_SDRAM_FREQ
- int "DDR SDRAM frequence (in MHz)"
- depends on DDR_INIT_CHANGE_FREQ
- default 400
-
-config DDR_FREQ
- bool "Enable DDR frequency scaling"
- default y if ARCH_RK3066B || ARCH_RK3188 || ARCH_RK319X
- select RK_SRAM_DMA if ARCH_RK30XX
-
-config DDR_TEST
- bool "DDR Test"
- depends on !ARCH_RK29
- select CRC32
- default y
-
-config DVFS
- bool "Enable dvfs"
- depends on REGULATOR&&CPU_FREQ
- default y
-
-config DVFS_WITH_UOC
- bool "Use dvfs with uoc, no voltage difference"
- depends on DVFS && ARCH_RK3066B
- default n
-
-config RK_CLOCK_PROC
- bool "/proc/clocks support"
- depends on PROC_FS
-
-source arch/arm/plat-rk/rk_pm_tests/Kconfig
-source arch/arm/plat-rk/bid/Kconfig
-
-if !ARCH_RK29
-menu "Support for RK power manage"
-
-config CLK_SWITCH_TO_32K
- bool "Support clock switch to 32.768k"
-
-config RK30_I2C_INSRAM
- bool "Support i2c control interface in sram"
-
-
-endmenu
-endif
-
-
-choice WIFI_CONTROL
- prompt "wifi control func Type."
- default WIFI_CONTROL_FUNC
-
-config WIFI_CONTROL_FUNC
- bool "Enable WiFi control function abstraction"
- help
- Enables Power/Reset/Carddetect function abstraction
-
-config WIFI_COMBO_MODULE_CONTROL_FUNC
- bool "Enable WiFi_combo_module control function abstraction"
- help
- Enables Power/Reset/Carddetect function abstraction
-
-endchoice
-
-
-config RK29_VPU
- tristate "VPU (Video Processing Unit) service driver in kernel"
- depends on ARCH_RK29 || ARCH_RK30 || ARCH_RK2928 || ARCH_RK3026 || ARCH_RK3188
- default m
-
-config RK29_LAST_LOG
- bool "Save the last kernel log on /proc/last_log"
- depends on DEBUG_KERNEL && PRINTK
- default y
- help
- It is only intended for debugging.
-
-config RK_EARLY_PRINTK
- bool "Early printk"
- depends on PRINTK && !DEBUG_LL
- default y
- help
- Say Y here if you want to have an early console using the
- kernel low-level debugging functions.
-
-config RK_DEBUG_UART
- int "Debug UART"
- default 1 if ARCH_RK29
- default 2 if ARCH_RK30 || ARCH_RK2928 || ARCH_RK3188 || ARCH_RK3026 || ARCH_RK319X
- help
- Select a UART for debugging. -1 disable.
-
-config RK_USB_UART
- bool "Support USB UART Bypass Function"
- depends on (ARCH_RK2928 || ARCH_RK3188 || ARCH_RK3026 || ARCH_RK319X) && (RK_DEBUG_UART = 2)
-
-config RK_CONSOLE_THREAD
- bool "Console write by thread"
- depends on FIQ_DEBUGGER_CONSOLE
- default y
- help
- Normal kernel printk will write out to UART by "kconsole" kthread
-
-config RK_SRAM_DMA
- bool "Sound DMA buffer in internal SRAM"
- depends on ARCH_RK30 || ARCH_RK3188 || ARCH_RK319X
-
-config RK_PL330_DMA
- bool
- select PL330
- help
- DMA API Driver for PL330 DMAC
-
-config RK_PL330_DMA_TEST
- bool "pl330 DMA memcpy test"
- depends on RK_PL330_DMA
-
-config RK_FPGA
- bool
-
-config RK_CONFIG
- bool
-
-config MACH_RK_FAC
- bool
-
-config RK_TIMER
- bool
-
-config RK_USB_DETECT_BY_OTG_BVALID
- bool "Wakeup system by OTG BVALID interrupt when USB OTG conneted"
- depends on USB_GADGET && (ARCH_RK2928 || ARCH_RK3188 || ARCH_RK3026 || ARCH_RK319X)
- default y
-
-endif
+++ /dev/null
-EXTRA_CFLAGS += -Os
-obj-$(CONFIG_RK29_LAST_LOG) += last_log.o
-obj-$(CONFIG_USB_GADGET) += usb_detect.o
-obj-$(CONFIG_RK29_VPU) += vpu_service.o
-obj-$(CONFIG_RK_PL330_DMA) += dma-pl330.o
-obj-$(CONFIG_RK_PL330_DMA_TEST) += dma_memcpy_test.o
-obj-$(CONFIG_FIQ) += fiq.o
-obj-$(CONFIG_FIQ_DEBUGGER) += rk_fiq_debugger.o
-obj-$(CONFIG_RK_EARLY_PRINTK) += early_printk.o ../kernel/debug.o
-obj-y += mem_reserve.o
-obj-y += config.o
-obj-y += cpu.o
-obj-y += sram.o
-obj-y += iomux.o
-obj-y += efuse.o
-obj-$(CONFIG_DDR_TEST) += memtester.o ddr_test.o
-obj-$(CONFIG_DDR_FREQ) += ddr_freq.o
-obj-$(CONFIG_DVFS) += dvfs.o
-obj-y += pwm.o
-obj-$(CONFIG_RK_TIMER) += rk_timer.o
-obj-$(CONFIG_RK_PM_TESTS) += rk_pm_tests/
-obj-$(CONFIG_BOARD_ID) += bid/
+++ /dev/null
-menuconfig BOARD_ID\r
- bool "board id support for OneImage solution"\r
- default n \r
-\r
-choice
- depends on BOARD_ID\r
- prompt "board id type"\r
- \r
-config BOARD_ID_FLASH\r
-bool "board id save in flash"\r
-\r
-config BOARD_ID_AUTO_XML\r
-bool "auto print cust.xml"\r
- depends on BOARD_ID_FLASH\r
-\r
-config BOARD_ID_HW\r
-bool "board id get from hardware such as gpios"\r
-\r
-endchoice\r
+++ /dev/null
-# rockchip board id select devices\r
-\r
-obj-$(CONFIG_BOARD_ID) += board-id.o\r
-obj-$(CONFIG_BOARD_ID_FLASH) += board-id-flash.o\r
-obj-$(CONFIG_BOARD_ID_HW) += board-id-hw.o\r
+++ /dev/null
-#include <linux/kernel.h>\r
-#include <linux/irq.h>\r
-#include <linux/gpio.h>\r
-#include <linux/input.h>\r
-#include <linux/platform_device.h>\r
-#include <linux/fs.h>\r
-#include <linux/uaccess.h>\r
-#include <linux/miscdevice.h>\r
-#include <linux/circ_buf.h>\r
-#include <linux/interrupt.h>\r
-#include <linux/miscdevice.h>\r
-#include <mach/iomux.h>\r
-#include <mach/gpio.h>\r
-#include <asm/gpio.h>\r
-#include <linux/delay.h>\r
-#include <linux/poll.h>\r
-#include <linux/wait.h>\r
-#include <linux/wakelock.h>\r
-#include <linux/workqueue.h>\r
-#include <linux/slab.h>\r
-#include <linux/proc_fs.h>\r
-\r
-\r
-#include <linux/file.h>\r
-#include <linux/mm.h>\r
-#include <linux/list.h>\r
-#include <linux/debugfs.h>\r
-#include <linux/mempolicy.h>\r
-#include <linux/sched.h>\r
-#include <asm/io.h>\r
-#include <asm/uaccess.h>\r
-#include <asm/cacheflush.h>\r
-#include <linux/fb.h>\r
-#include <plat/ipp.h>\r
-\r
-\r
-#include <linux/board-id.h>\r
-\r
-\r
-extern struct board_id_private_data *g_board_id;\r
-\r
-#if defined(CONFIG_BOARD_ID_AUTO_XML)\r
-\r
-#define MAX_BUF_LEN 200\r
-static ssize_t board_id_proc_write(struct file *file, const char __user *buffer,\r
- size_t count, loff_t *data)\r
-{\r
- char c;\r
- int rc;\r
- int i = 0, num = 0, j = 0;\r
- struct board_id_private_data *board_id = g_board_id;\r
- char buf[MAX_BUF_LEN];\r
- struct device_id_name *device_id_name_start = board_id->tp_id_name; \r
- struct area_id_name *area_id_name_start = board_id->area_area_id_name;\r
- int max_id = TP_ID_NUMS + LCD_ID_NUMS + KEY_ID_NUMS + CODEC_ID_NUMS + WIFI_ID_NUMS + BT_ID_NUMS + GPS_ID_NUMS + FM_ID_NUMS + MODEM_ID_NUMS + DDR_ID_NUMS + FLASH_ID_NUMS + HDMI_ID_NUMS\r
- + BATTERY_ID_NUMS + CHARGE_ID_NUMS + BACKLIGHT_ID_NUMS + HEADSET_ID_NUMS + MICPHONE_ID_NUMS + SPEAKER_ID_NUMS + VIBRATOR_ID_NUMS + TV_ID_NUMS\r
- + ECHIP_ID_NUMS + HUB_ID_NUMS + TPAD_ID_NUMS + PMIC_ID_NUMS + REGULATOR_ID_NUMS + RTC_ID_NUMS + CAMERA_FRONT_ID_NUMS + CAMERA_BACK_ID_NUMS + ANGLE_ID_NUMS + ACCEL_ID_NUMS\r
- + COMPASS_ID_NUMS + GYRO_ID_NUMS + LIGHT_ID_NUMS + PROXIMITY_ID_NUMS + TEMPERATURE_ID_NUMS + PRESSURE_ID_NUMS;\r
- \r
- rc = get_user(c, buffer);\r
- if (rc)\r
- {\r
- atomic_set(&board_id->flags.debug_flag, 0);\r
- return rc; \r
- }\r
-\r
- \r
- num = c - '0';\r
-\r
- printk("%s command list:debug close:0,debug enable:1, create /data/board-id-data.txt :2, create /data/board-id-cust.xml:3, create /data/board-id-device.xml :4\n",__func__);\r
-\r
- switch(num)\r
- {\r
- case 0:\r
- case 1: \r
- if(board_id)\r
- atomic_set(&board_id->flags.debug_flag, num);\r
- break;\r
-\r
- case 2: \r
- printk("%s:create /data/board-id-data.txt file\n",__func__);\r
- if(!board_id->board_id_data_filp)\r
- board_id->board_id_data_filp = filp_open("/data/board-id-data.txt",O_CREAT|O_TRUNC|O_RDWR,0);\r
-\r
- if (board_id->board_id_data_filp)\r
- {\r
- board_id->board_id_data_fs = get_fs();\r
- set_fs(get_ds());\r
- }\r
- \r
- memset(buf, 0, MAX_BUF_LEN);\r
- for(i=0; i<max_id; i++)\r
- { \r
- if(device_id_name_start->type && *device_id_name_start->dev_name)\r
- {\r
- snprintf(buf, MAX_BUF_LEN, "type=%d,id=%d,name=%s:%s,%d", device_id_name_start->type, device_id_name_start->id, device_id_name_start->dev_name, device_id_name_start->description, device_id_name_start->device_id); \r
- buf[MAX_BUF_LEN-1] = '\n';\r
- board_id->board_id_data_filp->f_op->write(board_id->board_id_data_filp, buf, MAX_BUF_LEN, &board_id->board_id_data_filp->f_pos);\r
- }\r
- memset(buf,0,MAX_BUF_LEN);\r
- device_id_name_start++;\r
- }\r
-\r
- memset(buf, '\n', MAX_BUF_LEN);\r
- board_id->board_id_data_filp->f_op->write(board_id->board_id_data_filp, buf, 3, &board_id->board_id_data_filp->f_pos); \r
- device_id_name_start = board_id->device_selected;\r
- memset(buf, 0, MAX_BUF_LEN);\r
- for(i=0; i<DEVICE_NUM_TYPES; i++)\r
- { \r
- if(device_id_name_start->type && *device_id_name_start->dev_name)\r
- {\r
- snprintf(buf, MAX_BUF_LEN, "device_selected: type=%d,id=%d,name=%s:%s,%d", device_id_name_start->type, device_id_name_start->id, device_id_name_start->dev_name, device_id_name_start->description, device_id_name_start->device_id); \r
- buf[MAX_BUF_LEN-1] = '\n';\r
- board_id->board_id_data_filp->f_op->write(board_id->board_id_data_filp, buf, MAX_BUF_LEN, &board_id->board_id_data_filp->f_pos); \r
- }\r
- memset(buf, 0, MAX_BUF_LEN);\r
- device_id_name_start++;\r
- }\r
-\r
- memset(buf, '\n', MAX_BUF_LEN);\r
- board_id->board_id_data_filp->f_op->write(board_id->board_id_data_filp, buf, 3, &board_id->board_id_data_filp->f_pos); \r
- area_id_name_start = board_id->area_area_id_name;\r
- memset(buf, 0, MAX_BUF_LEN);\r
- for(i=AREA_ID_NULL; i<AREA_ID_NUMS+1; i++)\r
- { \r
- if(area_id_name_start->type && (strlen(area_id_name_start->locale_language) > 0))\r
- {\r
- if(i == AREA_ID_NUMS)\r
- snprintf(buf, MAX_BUF_LEN, "area_selected: type=%d,id=%d,name=%s_%s", area_id_name_start->type, area_id_name_start->id, area_id_name_start->locale_language, area_id_name_start->locale_region);\r
- else\r
- snprintf(buf, MAX_BUF_LEN, "type=%d,id=%d,name=%s_%s", area_id_name_start->type, area_id_name_start->id, area_id_name_start->locale_language, area_id_name_start->locale_region); \r
- buf[MAX_BUF_LEN-1] = '\n';\r
- board_id->board_id_data_filp->f_op->write(board_id->board_id_data_filp, buf, MAX_BUF_LEN, &board_id->board_id_data_filp->f_pos); \r
- }\r
- memset(buf, 0, MAX_BUF_LEN);\r
- area_id_name_start++;\r
- }\r
-\r
- \r
- break;\r
-\r
- case 3: \r
- \r
- if(!board_id->board_id_area_filp)\r
- board_id->board_id_area_filp = filp_open("/data/board-id-cust.xml",O_CREAT|O_TRUNC|O_RDWR,0);\r
-\r
- if (board_id->board_id_area_filp)\r
- {\r
- board_id->board_id_area_fs = get_fs();\r
- set_fs(get_ds());\r
- }\r
-\r
- board_id->board_id_area_filp->f_op->write(board_id->board_id_area_filp, "<?xml version=\"1.0\" encoding=\"utf-8\"?>\n", 40, &board_id->board_id_area_filp->f_pos);\r
-\r
- board_id->board_id_area_filp->f_op->write(board_id->board_id_area_filp, "<cust>\n", 7, &board_id->board_id_area_filp->f_pos); \r
- \r
- area_id_name_start = board_id->area_area_id_name;\r
- memset(buf, 0, MAX_BUF_LEN);\r
- for(i=AREA_ID_NULL; i<AREA_ID_NUMS; i++)\r
- { \r
- if(area_id_name_start->type && (strlen(area_id_name_start->locale_language) > 0) && (strlen(area_id_name_start->locale_region) > 0))\r
- \r
- {\r
- memset(buf, 0, MAX_BUF_LEN);\r
- snprintf(buf, MAX_BUF_LEN, "\t<if tid=\"%d\" bid=\"%d\" area=\"%s\">\n",area_id_name_start->type, area_id_name_start->id, area_id_name_start->country_area); \r
- board_id->board_id_area_filp->f_op->write(board_id->board_id_area_filp, buf, MAX_BUF_LEN, &board_id->board_id_area_filp->f_pos);\r
-\r
- memset(buf, 0, MAX_BUF_LEN);\r
- snprintf(buf, MAX_BUF_LEN, "\t\t<set name=\"persist.sys.language\" value=\"%s\"/>\n\t\t<set name=\"persist.sys.country\" value=\"%s\"/>\n\t\t<set name=\"persist.sys.timezone\" value=\"%s\"/>\n", area_id_name_start->locale_language, area_id_name_start->locale_region, area_id_name_start->timezone);\r
- board_id->board_id_area_filp->f_op->write(board_id->board_id_area_filp, buf, MAX_BUF_LEN, &board_id->board_id_area_filp->f_pos);\r
-\r
-\r
- memset(buf, 0, MAX_BUF_LEN);\r
- snprintf(buf, MAX_BUF_LEN, "\t\t<set name=\"ro.product.locale.language\" value=\"%s\"/>\n\t\t<set name=\"ro.product.locale.region\" value=\"%s\"/>\n", area_id_name_start->locale_language, area_id_name_start->locale_region);\r
- board_id->board_id_area_filp->f_op->write(board_id->board_id_area_filp, buf, MAX_BUF_LEN, &board_id->board_id_area_filp->f_pos);\r
- //memset(buf, 0, MAX_BUF_LEN);\r
- //snprintf(buf, MAX_BUF_LEN, "\t\t<cp src=\"cust/app/area.apk\" des=\"system/app/area.apk\" mode=\"0644\"/>\n \t\t<rm src=\"system/app/area.apk\" />\n"); \r
- //board_id->board_id_area_filp->f_op->write(board_id->board_id_area_filp, buf, MAX_BUF_LEN, &board_id->board_id_area_filp->f_pos);\r
- for(j=0; j<GMS_ID_NUMS; j++)\r
- {\r
- if(xml_config[i].gms_flag[j])\r
- {\r
- memset(buf, 0, MAX_BUF_LEN);\r
- snprintf(buf, MAX_BUF_LEN, "\t\t<rm src=\"cust/app/%s\" des=\"system/app/%s\" mode=\"0644\"/>\n", gms_name[j].gms_name, gms_name[j].gms_name); \r
- board_id->board_id_area_filp->f_op->write(board_id->board_id_area_filp, buf, MAX_BUF_LEN, &board_id->board_id_area_filp->f_pos);\r
- }\r
- }\r
- \r
- //</if> \r
- memset(buf, 0, MAX_BUF_LEN);\r
- snprintf(buf, MAX_BUF_LEN, "\t</if>\n"); \r
- board_id->board_id_area_filp->f_op->write(board_id->board_id_area_filp, buf, MAX_BUF_LEN, &board_id->board_id_area_filp->f_pos);\r
- \r
- }\r
- \r
- memset(buf, 0, MAX_BUF_LEN);\r
- if(i < AREA_ID_NUMS)\r
- area_id_name_start++;\r
- \r
- }\r
- \r
- memset(buf, 0, MAX_BUF_LEN);\r
- snprintf(buf, MAX_BUF_LEN, "\t<if area=\"!China\" language=\"!zh\" local=\"!CN\">\n");\r
- board_id->board_id_area_filp->f_op->write(board_id->board_id_area_filp, buf, MAX_BUF_LEN, &board_id->board_id_area_filp->f_pos);\r
-\r
- memset(buf, 0, MAX_BUF_LEN);\r
- snprintf(buf, MAX_BUF_LEN, "\t\t<cp src=\"cust/app/area.apk\" des=\"system/app/area.apk\" mode=\"0644\"/>\n \t\t<rm src=\"system/app/area.apk\" />\n\t</if>\n"); \r
- board_id->board_id_area_filp->f_op->write(board_id->board_id_area_filp, buf, MAX_BUF_LEN, &board_id->board_id_area_filp->f_pos); \r
-\r
- board_id->board_id_area_filp->f_op->write(board_id->board_id_area_filp, "</cust>\n", 8, &board_id->board_id_area_filp->f_pos);\r
- \r
- printk("%s:/data/board-id-cust.xml file\n",__func__);\r
- break;\r
-\r
-\r
- case 4: \r
- if(!board_id->board_id_device_filp)\r
- board_id->board_id_device_filp = filp_open("/data/board-id-device.xml",O_CREAT|O_TRUNC|O_RDWR,0);\r
-\r
- if (board_id->board_id_device_filp)\r
- {\r
- board_id->board_id_device_fs = get_fs();\r
- set_fs(get_ds());\r
- }\r
- \r
- board_id->board_id_device_filp->f_op->write(board_id->board_id_device_filp, "<?xml version=\"1.0\" encoding=\"utf-8\"?>\n", 40, &board_id->board_id_device_filp->f_pos);\r
-\r
- board_id->board_id_device_filp->f_op->write(board_id->board_id_device_filp, "<device>\n", 9, &board_id->board_id_device_filp->f_pos); \r
- \r
- device_id_name_start = board_id->tp_id_name;\r
- memset(buf, 0, MAX_BUF_LEN);\r
-\r
- for(i=DEVICE_TYPE_TP; i<DEVICE_NUM_TYPES; i++)\r
- { \r
- device_id_name_start = board_id->device_start_addr[i];\r
- \r
- device_id_name_start = board_id->tp_id_name;\r
- \r
- for(j=0; j<max_id; j++)\r
- { \r
- if((device_id_name_start->type == i) && (strlen(device_id_name_start->dev_name) > 0))\r
- {\r
-\r
- memset(buf, 0, MAX_BUF_LEN);\r
- snprintf(buf, MAX_BUF_LEN, "\t<if tid=\"%d\" bid=\"%d\" type=\"%s\" dev=\"%s\" desc=\"%s\">\n", device_id_name_start->type, device_id_name_start->id, device_id_name_start->type_name, device_id_name_start->dev_name, device_id_name_start->description); \r
- board_id->board_id_device_filp->f_op->write(board_id->board_id_device_filp, buf, MAX_BUF_LEN, &board_id->board_id_device_filp->f_pos);\r
-\r
- if(DEVICE_TYPE_KEY == device_id_name_start->type)\r
- {\r
- memset(buf, 0, MAX_BUF_LEN); //added by luodh\r
- snprintf(buf, MAX_BUF_LEN, "\t\t<set name=\"ro.product.locale.keylayout\" value=\"%s\"/>\n", device_id_name_start->dev_name);\r
- board_id->board_id_device_filp->f_op->write(board_id->board_id_device_filp, buf, MAX_BUF_LEN, &board_id->board_id_device_filp->f_pos); \r
- }\r
- memset(buf, 0, MAX_BUF_LEN);\r
- snprintf(buf, MAX_BUF_LEN, "\t\t<cp src=\"cust/so/type.dev.so\" des=\"system/lib/hw/type.dev.so\" mode=\"0644\"/>\n \t\t<rm src=\"system/lib/hw/type.dev.so\"/>\n"); \r
- board_id->board_id_device_filp->f_op->write(board_id->board_id_device_filp, buf, MAX_BUF_LEN, &board_id->board_id_device_filp->f_pos); \r
-\r
- memset(buf, 0, MAX_BUF_LEN);\r
- snprintf(buf, MAX_BUF_LEN, "\t</if>\n");\r
- board_id->board_id_device_filp->f_op->write(board_id->board_id_device_filp, buf, MAX_BUF_LEN, &board_id->board_id_device_filp->f_pos);\r
-\r
- memset(buf, 0, MAX_BUF_LEN);\r
-\r
- //printk("%s:type=%d,id=%d\n",__func__,device_id_name_start->type, device_id_name_start->id);\r
- \r
- } \r
- \r
- device_id_name_start++; \r
-\r
- }\r
-\r
- memset(buf, 0, MAX_BUF_LEN);\r
-\r
- } \r
- \r
- //board_id->board_id_device_filp->f_op->write(board_id->board_id_device_filp, "\t</type>\n", 9, &board_id->board_id_device_filp->f_pos);\r
- \r
- board_id->board_id_device_filp->f_op->write(board_id->board_id_device_filp, "</device>\n", 10, &board_id->board_id_device_filp->f_pos);\r
- \r
- printk("%s:/data/board-id-device.xml file\n",__func__);\r
- break;\r
-\r
- default:\r
- break;\r
-\r
- }\r
- \r
- printk("%s %d\n", __func__, __LINE__);\r
- return count; \r
-}\r
-\r
-static const struct file_operations board_id_proc_fops = {\r
- .owner = THIS_MODULE, \r
- .write = board_id_proc_write,\r
-};\r
-\r
-#endif\r
-\r
-static int board_id_open(struct inode *inode, struct file *file)\r
-{\r
- struct board_id_private_data *board_id = g_board_id;\r
- \r
- return 0;\r
-}\r
-\r
-static int board_id_release(struct inode *inode, struct file *file)\r
-{ \r
- struct board_id_private_data *board_id = g_board_id;\r
-\r
- return 0;\r
-}\r
-\r
-static struct device_id_name device_selected[DEVICE_NUM_TYPES]; \r
-\r
-static long board_id_ioctl(struct file *file, unsigned int cmd, unsigned long arg)\r
-{\r
- struct board_id_private_data *board_id = g_board_id;\r
- void __user *argp = (void __user *)arg;\r
- struct area_id_name area_select = board_id->area_select;\r
- struct operator_id_name operator_select = board_id->operator_select;\r
- struct reserve_id_name reserve_select = board_id->reserve_select;\r
- struct device_id_name device_selected_temp, device_selected_last_temp;\r
- struct area_id_name language_last_select; \r
- struct operator_id_name operator_last_select;\r
- struct reserve_id_name reserve_last_select;\r
- int result = 0;\r
- int i = 0;\r
- switch(cmd)\r
- {\r
- case BOARD_ID_IOCTL_READ_AREA_ID:\r
- mutex_lock(&board_id->operation_mutex);\r
- if(copy_to_user(argp, &area_select, sizeof(struct area_id_name)))\r
- {\r
- printk("%s:fail to copy area_id_name to user\n",__func__);\r
- mutex_unlock(&board_id->operation_mutex);\r
- return -EFAULT;\r
- }\r
- DBG_ID("%s:BOARD_ID_IOCTL_READ_LANGUAGE_ID:%s_%s\n",__func__,area_select.locale_language,area_select.locale_region);\r
- mutex_unlock(&board_id->operation_mutex);\r
- break;\r
-\r
- case BOARD_ID_IOCTL_READ_OPERATOR_ID:\r
- mutex_lock(&board_id->operation_mutex);\r
- if(copy_to_user(argp, &operator_select, sizeof(struct operator_id_name)))\r
- {\r
- printk("%s:fail to copy operator_id_name to user\n",__func__);\r
- mutex_unlock(&board_id->operation_mutex);\r
- return -EFAULT;\r
- }\r
- DBG_ID("%s:BOARD_ID_IOCTL_READ_operator_ID:%s_%s\n",__func__,operator_select.operator_name,operator_select.locale_region);\r
- mutex_unlock(&board_id->operation_mutex);\r
- break;\r
-\r
- case BOARD_ID_IOCTL_READ_RESERVE_ID:\r
- mutex_lock(&board_id->operation_mutex);\r
- if(copy_to_user(argp, &reserve_select, sizeof(struct reserve_id_name)))\r
- {\r
- printk("%s:fail to copy reserve_id_name to user\n",__func__);\r
- mutex_unlock(&board_id->operation_mutex);\r
- return -EFAULT;\r
- }\r
- DBG_ID("%s:BOARD_ID_IOCTL_READ_RESERVE_ID:%s,%s\n",__func__,reserve_select.reserve_name, reserve_select.locale_region);\r
- mutex_unlock(&board_id->operation_mutex);\r
- break;\r
-\r
- case BOARD_ID_IOCTL_READ_STATUS:\r
- mutex_lock(&board_id->operation_mutex);\r
- if(copy_to_user(argp, &board_id->vendor_data[DEVICE_TYPE_STATUS], sizeof(board_id->vendor_data[DEVICE_TYPE_STATUS])))\r
- {\r
- printk("%s:line=%d:fail to copy vendor_data to user\n",__func__,__LINE__); \r
- mutex_unlock(&board_id->operation_mutex); \r
- return -EFAULT;\r
- }\r
- mutex_unlock(&board_id->operation_mutex);\r
- DBG_ID("%s:BOARD_ID_IOCTL_READ_STATUS=0x%x\n",__func__,board_id->vendor_data[DEVICE_TYPE_STATUS]);\r
- break;\r
-\r
- case BOARD_ID_IOCTL_READ_VENDOR_DATA: \r
- mutex_lock(&board_id->operation_mutex); \r
- DBG_ID("%s:BOARD_ID_IOCTL_READ_VENDOR_DATA:\n",__func__);\r
- if(copy_to_user(argp, board_id->vendor_data, sizeof(board_id->vendor_data)))\r
- {\r
- printk("%s:line=%d:fail to copy vendor_data to user\n",__func__,__LINE__); \r
- mutex_unlock(&board_id->operation_mutex); \r
- return -EFAULT;\r
- }\r
- mutex_unlock(&board_id->operation_mutex);\r
- \r
- break;\r
- \r
- }\r
- \r
- mutex_lock(&board_id->operation_mutex); \r
- switch(cmd)\r
- { \r
- \r
- case BOARD_ID_IOCTL_READ_TP_ID:\r
- device_selected_temp = board_id->device_selected[DEVICE_TYPE_TP];\r
- break;\r
- case BOARD_ID_IOCTL_READ_LCD_ID:\r
- device_selected_temp = board_id->device_selected[DEVICE_TYPE_LCD];\r
- break;\r
- case BOARD_ID_IOCTL_READ_KEY_ID:\r
- device_selected_temp = board_id->device_selected[DEVICE_TYPE_KEY];\r
- break;\r
- case BOARD_ID_IOCTL_READ_CODEC_ID:\r
- device_selected_temp = board_id->device_selected[DEVICE_TYPE_CODEC];\r
- break;\r
- case BOARD_ID_IOCTL_READ_WIFI_ID:\r
- device_selected_temp = board_id->device_selected[DEVICE_TYPE_WIFI];\r
- break;\r
- case BOARD_ID_IOCTL_READ_BT_ID:\r
- device_selected_temp = board_id->device_selected[DEVICE_TYPE_BT];\r
- break;\r
- case BOARD_ID_IOCTL_READ_GPS_ID:\r
- device_selected_temp = board_id->device_selected[DEVICE_TYPE_GPS];\r
- break;\r
- case BOARD_ID_IOCTL_READ_FM_ID:\r
- device_selected_temp = board_id->device_selected[DEVICE_TYPE_FM];\r
- break;\r
- case BOARD_ID_IOCTL_READ_MODEM_ID:\r
- device_selected_temp = board_id->device_selected[DEVICE_TYPE_MODEM];\r
- break;\r
- case BOARD_ID_IOCTL_READ_DDR_ID:\r
- device_selected_temp = board_id->device_selected[DEVICE_TYPE_DDR];\r
- break;\r
- case BOARD_ID_IOCTL_READ_FLASH_ID:\r
- device_selected_temp = board_id->device_selected[DEVICE_TYPE_FLASH];\r
- break;\r
- case BOARD_ID_IOCTL_READ_HDMI_ID:\r
- device_selected_temp = board_id->device_selected[DEVICE_TYPE_HDMI];\r
- break;\r
- case BOARD_ID_IOCTL_READ_BATTERY_ID:\r
- device_selected_temp = board_id->device_selected[DEVICE_TYPE_BATTERY];\r
- break;\r
- case BOARD_ID_IOCTL_READ_CHARGE_ID:\r
- device_selected_temp = board_id->device_selected[DEVICE_TYPE_CHARGE];\r
- break;\r
- case BOARD_ID_IOCTL_READ_BACKLIGHT_ID:\r
- device_selected_temp = board_id->device_selected[DEVICE_TYPE_BACKLIGHT];\r
- break;\r
- case BOARD_ID_IOCTL_READ_HEADSET_ID:\r
- device_selected_temp = board_id->device_selected[DEVICE_TYPE_HEADSET];\r
- break;\r
- case BOARD_ID_IOCTL_READ_MICPHONE_ID:\r
- device_selected_temp = board_id->device_selected[DEVICE_TYPE_MICPHONE];\r
- break;\r
- case BOARD_ID_IOCTL_READ_SPEAKER_ID:\r
- device_selected_temp = board_id->device_selected[DEVICE_TYPE_SPEAKER];\r
- break;\r
- case BOARD_ID_IOCTL_READ_VIBRATOR_ID: \r
- device_selected_temp = board_id->device_selected[DEVICE_TYPE_VIBRATOR];\r
- break;\r
- case BOARD_ID_IOCTL_READ_TV_ID:\r
- device_selected_temp = board_id->device_selected[DEVICE_TYPE_TV];\r
- break;\r
- case BOARD_ID_IOCTL_READ_ECHIP_ID: \r
- device_selected_temp = board_id->device_selected[DEVICE_TYPE_ECHIP];\r
- break; \r
- case BOARD_ID_IOCTL_READ_HUB_ID: \r
- device_selected_temp = board_id->device_selected[DEVICE_TYPE_HUB];\r
- break;\r
- case BOARD_ID_IOCTL_READ_TPAD_ID:\r
- device_selected_temp = board_id->device_selected[DEVICE_TYPE_TPAD];\r
- break;\r
- case BOARD_ID_IOCTL_READ_PMIC_ID:\r
- device_selected_temp = board_id->device_selected[DEVICE_TYPE_PMIC];\r
- break;\r
- case BOARD_ID_IOCTL_READ_REGULATOR_ID: \r
- device_selected_temp = board_id->device_selected[DEVICE_TYPE_REGULATOR];\r
- break;\r
- case BOARD_ID_IOCTL_READ_RTC_ID:\r
- device_selected_temp = board_id->device_selected[DEVICE_TYPE_RTC];\r
- break;\r
- case BOARD_ID_IOCTL_READ_CAMERA_FRONT_ID: \r
- device_selected_temp = board_id->device_selected[DEVICE_TYPE_CAMERA_FRONT];\r
- break;\r
- case BOARD_ID_IOCTL_READ_CAMERA_BACK_ID:\r
- device_selected_temp = board_id->device_selected[DEVICE_TYPE_CAMERA_BACK];\r
- break;\r
- case BOARD_ID_IOCTL_READ_SENSOR_ANGLE_ID:\r
- device_selected_temp = board_id->device_selected[DEVICE_TYPE_ANGLE];\r
- break;\r
- case BOARD_ID_IOCTL_READ_SENSOR_ACCEL_ID: \r
- device_selected_temp = board_id->device_selected[DEVICE_TYPE_ACCEL];\r
- break;\r
- case BOARD_ID_IOCTL_READ_SENSOR_COMPASS_ID: \r
- device_selected_temp = board_id->device_selected[DEVICE_TYPE_COMPASS];\r
- break;\r
- case BOARD_ID_IOCTL_READ_SENSOR_GYRO_ID : \r
- device_selected_temp = board_id->device_selected[DEVICE_TYPE_GYRO];\r
- break;\r
- case BOARD_ID_IOCTL_READ_SENSOR_LIGHT_ID: \r
- device_selected_temp = board_id->device_selected[DEVICE_TYPE_LIGHT];\r
- break;\r
- case BOARD_ID_IOCTL_READ_SENSOR_PROXIMITY_ID:\r
- device_selected_temp = board_id->device_selected[DEVICE_TYPE_PROXIMITY];\r
- break;\r
- case BOARD_ID_IOCTL_READ_SENSOR_TEMPERATURE_ID: \r
- device_selected_temp = board_id->device_selected[DEVICE_TYPE_TEMPERATURE];\r
- break;\r
- case BOARD_ID_IOCTL_READ_SENSOR_PRESSURE_ID: \r
- device_selected_temp = board_id->device_selected[DEVICE_TYPE_PRESSURE];\r
- break;\r
- \r
- case BOARD_ID_IOCTL_WRITE_TP_ID: \r
- case BOARD_ID_IOCTL_WRITE_LCD_ID: \r
- case BOARD_ID_IOCTL_WRITE_KEY_ID: \r
- case BOARD_ID_IOCTL_WRITE_CODEC_ID: \r
- case BOARD_ID_IOCTL_WRITE_WIFI_ID: \r
- case BOARD_ID_IOCTL_WRITE_BT_ID: \r
- case BOARD_ID_IOCTL_WRITE_GPS_ID: \r
- case BOARD_ID_IOCTL_WRITE_FM_ID: \r
- case BOARD_ID_IOCTL_WRITE_MODEM_ID: \r
- case BOARD_ID_IOCTL_WRITE_DDR_ID: \r
- case BOARD_ID_IOCTL_WRITE_FLASH_ID: \r
- case BOARD_ID_IOCTL_WRITE_HDMI_ID: \r
- case BOARD_ID_IOCTL_WRITE_BATTERY_ID: \r
- case BOARD_ID_IOCTL_WRITE_CHARGE_ID: \r
- case BOARD_ID_IOCTL_WRITE_BACKLIGHT_ID: \r
- case BOARD_ID_IOCTL_WRITE_HEADSET_ID: \r
- case BOARD_ID_IOCTL_WRITE_MICPHONE_ID: \r
- case BOARD_ID_IOCTL_WRITE_SPEAKER_ID: \r
- case BOARD_ID_IOCTL_WRITE_VIBRATOR_ID: \r
- case BOARD_ID_IOCTL_WRITE_TV_ID: \r
- case BOARD_ID_IOCTL_WRITE_ECHIP_ID:\r
- case BOARD_ID_IOCTL_WRITE_HUB_ID:\r
- case BOARD_ID_IOCTL_WRITE_PMIC_ID: \r
- case BOARD_ID_IOCTL_WRITE_REGULATOR_ID: \r
- case BOARD_ID_IOCTL_WRITE_RTC_ID: \r
- case BOARD_ID_IOCTL_WRITE_CAMERA_FRONT_ID: \r
- case BOARD_ID_IOCTL_WRITE_CAMERA_BACK_ID: \r
- case BOARD_ID_IOCTL_WRITE_SENSOR_ANGLE_ID: \r
- case BOARD_ID_IOCTL_WRITE_SENSOR_ACCEL_ID: \r
- case BOARD_ID_IOCTL_WRITE_SENSOR_COMPASS_ID: \r
- case BOARD_ID_IOCTL_WRITE_SENSOR_GYRO_ID: \r
- case BOARD_ID_IOCTL_WRITE_SENSOR_LIGHT_ID: \r
- case BOARD_ID_IOCTL_WRITE_SENSOR_PROXIMITY_ID:\r
- case BOARD_ID_IOCTL_WRITE_SENSOR_TEMPERATURE_ID:\r
- case BOARD_ID_IOCTL_READ_DEVICE_NAME_BY_ID:\r
- if(copy_from_user(&device_selected_temp, argp, sizeof(struct device_id_name)))\r
- {\r
- printk("%s:line=%d:fail to copy device_id_name from user\n",__func__, __LINE__); \r
- mutex_unlock(&board_id->operation_mutex); \r
- return -EFAULT;\r
- }\r
- DBG_ID("%s:write: type=%d,id=%d,name=%s\n",__func__, (int)device_selected_temp.type, (int)device_selected_temp.id, device_selected_temp.dev_name);\r
- break;\r
- \r
- } \r
-\r
- switch(cmd)\r
- { \r
- case BOARD_ID_IOCTL_READ_TP_ID:\r
- case BOARD_ID_IOCTL_READ_LCD_ID:\r
- case BOARD_ID_IOCTL_READ_KEY_ID:\r
- case BOARD_ID_IOCTL_READ_CODEC_ID:\r
- case BOARD_ID_IOCTL_READ_WIFI_ID:\r
- case BOARD_ID_IOCTL_READ_BT_ID:\r
- case BOARD_ID_IOCTL_READ_GPS_ID:\r
- case BOARD_ID_IOCTL_READ_FM_ID:\r
- case BOARD_ID_IOCTL_READ_MODEM_ID:\r
- case BOARD_ID_IOCTL_READ_DDR_ID:\r
- case BOARD_ID_IOCTL_READ_FLASH_ID:\r
- case BOARD_ID_IOCTL_READ_HDMI_ID:\r
- case BOARD_ID_IOCTL_READ_BATTERY_ID:\r
- case BOARD_ID_IOCTL_READ_CHARGE_ID:\r
- case BOARD_ID_IOCTL_READ_BACKLIGHT_ID:\r
- case BOARD_ID_IOCTL_READ_HEADSET_ID:\r
- case BOARD_ID_IOCTL_READ_MICPHONE_ID:\r
- case BOARD_ID_IOCTL_READ_SPEAKER_ID:\r
- case BOARD_ID_IOCTL_READ_VIBRATOR_ID: \r
- case BOARD_ID_IOCTL_READ_TV_ID:\r
- case BOARD_ID_IOCTL_READ_ECHIP_ID:\r
- case BOARD_ID_IOCTL_READ_HUB_ID: \r
- case BOARD_ID_IOCTL_READ_PMIC_ID:\r
- case BOARD_ID_IOCTL_READ_REGULATOR_ID: \r
- case BOARD_ID_IOCTL_READ_RTC_ID:\r
- case BOARD_ID_IOCTL_READ_CAMERA_FRONT_ID: \r
- case BOARD_ID_IOCTL_READ_CAMERA_BACK_ID: \r
- case BOARD_ID_IOCTL_READ_SENSOR_ANGLE_ID: \r
- case BOARD_ID_IOCTL_READ_SENSOR_ACCEL_ID: \r
- case BOARD_ID_IOCTL_READ_SENSOR_COMPASS_ID: \r
- case BOARD_ID_IOCTL_READ_SENSOR_GYRO_ID : \r
- case BOARD_ID_IOCTL_READ_SENSOR_LIGHT_ID: \r
- case BOARD_ID_IOCTL_READ_SENSOR_PROXIMITY_ID:\r
- case BOARD_ID_IOCTL_READ_SENSOR_TEMPERATURE_ID: \r
- case BOARD_ID_IOCTL_READ_SENSOR_PRESSURE_ID: \r
- if(copy_to_user(argp, &device_selected_temp, sizeof(struct device_id_name)))\r
- {\r
- printk("%s:line=%d:fail to copy device_selected_temp.dev_name=%s to user\n",__func__,__LINE__,device_selected_temp.dev_name); \r
- mutex_unlock(&board_id->operation_mutex); \r
- return -EFAULT;\r
- }\r
- DBG_ID("%s:read: type=%d,id=%d,name=%s\n",__func__, (int)device_selected_temp.type, (int)device_selected_temp.id, device_selected_temp.dev_name);\r
- break;\r
- \r
-\r
-\r
- case BOARD_ID_IOCTL_WRITE_TP_ID:\r
- board_id->device_selected[DEVICE_TYPE_TP] = device_selected_temp;\r
- break; \r
- case BOARD_ID_IOCTL_WRITE_LCD_ID:\r
- board_id->device_selected[DEVICE_TYPE_LCD] = device_selected_temp;\r
- break; \r
- case BOARD_ID_IOCTL_WRITE_KEY_ID:\r
- board_id->device_selected[DEVICE_TYPE_KEY] = device_selected_temp;\r
- break; \r
- case BOARD_ID_IOCTL_WRITE_CODEC_ID:\r
- board_id->device_selected[DEVICE_TYPE_CODEC] = device_selected_temp;\r
- break; \r
- case BOARD_ID_IOCTL_WRITE_WIFI_ID:\r
- board_id->device_selected[DEVICE_TYPE_WIFI] = device_selected_temp;\r
- break; \r
- case BOARD_ID_IOCTL_WRITE_BT_ID:\r
- board_id->device_selected[DEVICE_TYPE_BT] = device_selected_temp;\r
- break; \r
- case BOARD_ID_IOCTL_WRITE_GPS_ID:\r
- board_id->device_selected[DEVICE_TYPE_GPS] = device_selected_temp;\r
- break; \r
- case BOARD_ID_IOCTL_WRITE_FM_ID:\r
- board_id->device_selected[DEVICE_TYPE_FM] = device_selected_temp;\r
- break; \r
- case BOARD_ID_IOCTL_WRITE_MODEM_ID:\r
- board_id->device_selected[DEVICE_TYPE_MODEM] = device_selected_temp;\r
- break; \r
- case BOARD_ID_IOCTL_WRITE_DDR_ID:\r
- board_id->device_selected[DEVICE_TYPE_DDR] = device_selected_temp;\r
- break; \r
- case BOARD_ID_IOCTL_WRITE_FLASH_ID:\r
- board_id->device_selected[DEVICE_TYPE_FLASH] = device_selected_temp;\r
- break; \r
- case BOARD_ID_IOCTL_WRITE_HDMI_ID:\r
- board_id->device_selected[DEVICE_TYPE_HDMI] = device_selected_temp;\r
- break; \r
- case BOARD_ID_IOCTL_WRITE_BATTERY_ID:\r
- board_id->device_selected[DEVICE_TYPE_BATTERY] = device_selected_temp;\r
- break; \r
- case BOARD_ID_IOCTL_WRITE_CHARGE_ID:\r
- board_id->device_selected[DEVICE_TYPE_CHARGE] = device_selected_temp;\r
- break; \r
- case BOARD_ID_IOCTL_WRITE_BACKLIGHT_ID:\r
- board_id->device_selected[DEVICE_TYPE_BACKLIGHT] = device_selected_temp;\r
- break; \r
- case BOARD_ID_IOCTL_WRITE_HEADSET_ID:\r
- board_id->device_selected[DEVICE_TYPE_HEADSET] = device_selected_temp;\r
- break; \r
- case BOARD_ID_IOCTL_WRITE_MICPHONE_ID:\r
- board_id->device_selected[DEVICE_TYPE_MICPHONE] = device_selected_temp;\r
- break; \r
- case BOARD_ID_IOCTL_WRITE_SPEAKER_ID:\r
- board_id->device_selected[DEVICE_TYPE_SPEAKER] = device_selected_temp;\r
- break; \r
- case BOARD_ID_IOCTL_WRITE_VIBRATOR_ID:\r
- board_id->device_selected[DEVICE_TYPE_VIBRATOR] = device_selected_temp;\r
- break; \r
- case BOARD_ID_IOCTL_WRITE_TV_ID:\r
- board_id->device_selected[DEVICE_TYPE_TV] = device_selected_temp;\r
- break; \r
- case BOARD_ID_IOCTL_WRITE_ECHIP_ID:\r
- board_id->device_selected[DEVICE_TYPE_ECHIP] = device_selected_temp;\r
- break; \r
- case BOARD_ID_IOCTL_WRITE_HUB_ID:\r
- board_id->device_selected[DEVICE_TYPE_HUB] = device_selected_temp;\r
- break; \r
- case BOARD_ID_IOCTL_WRITE_TPAD_ID:\r
- board_id->device_selected[DEVICE_TYPE_TPAD] = device_selected_temp;\r
- break; \r
- case BOARD_ID_IOCTL_WRITE_PMIC_ID:\r
- board_id->device_selected[DEVICE_TYPE_PMIC] = device_selected_temp;\r
- break; \r
- case BOARD_ID_IOCTL_WRITE_REGULATOR_ID:\r
- board_id->device_selected[DEVICE_TYPE_REGULATOR] = device_selected_temp;\r
- break; \r
- case BOARD_ID_IOCTL_WRITE_RTC_ID:\r
- board_id->device_selected[DEVICE_TYPE_RTC] = device_selected_temp;\r
- break; \r
- case BOARD_ID_IOCTL_WRITE_CAMERA_FRONT_ID:\r
- board_id->device_selected[DEVICE_TYPE_CAMERA_FRONT] = device_selected_temp;\r
- break; \r
- case BOARD_ID_IOCTL_WRITE_CAMERA_BACK_ID:\r
- board_id->device_selected[DEVICE_TYPE_CAMERA_BACK] = device_selected_temp;\r
- break; \r
- case BOARD_ID_IOCTL_WRITE_SENSOR_ANGLE_ID:\r
- board_id->device_selected[DEVICE_TYPE_ANGLE] = device_selected_temp;\r
- break; \r
- case BOARD_ID_IOCTL_WRITE_SENSOR_ACCEL_ID:\r
- board_id->device_selected[DEVICE_TYPE_ACCEL] = device_selected_temp;\r
- break; \r
- case BOARD_ID_IOCTL_WRITE_SENSOR_COMPASS_ID:\r
- board_id->device_selected[DEVICE_TYPE_COMPASS] = device_selected_temp;\r
- break; \r
- case BOARD_ID_IOCTL_WRITE_SENSOR_GYRO_ID:\r
- board_id->device_selected[DEVICE_TYPE_GYRO] = device_selected_temp;\r
- break; \r
- case BOARD_ID_IOCTL_WRITE_SENSOR_LIGHT_ID:\r
- board_id->device_selected[DEVICE_TYPE_LIGHT] = device_selected_temp;\r
- break; \r
- case BOARD_ID_IOCTL_WRITE_SENSOR_PROXIMITY_ID:\r
- board_id->device_selected[DEVICE_TYPE_PROXIMITY] = device_selected_temp;\r
- break;\r
- case BOARD_ID_IOCTL_WRITE_SENSOR_TEMPERATURE_ID:\r
- board_id->device_selected[DEVICE_TYPE_TEMPERATURE] = device_selected_temp;\r
- break;\r
- \r
- }\r
-\r
- \r
- mutex_unlock(&board_id->operation_mutex);\r
-\r
- switch(cmd)\r
- {\r
- case BOARD_ID_IOCTL_READ_DEVICE_NAME_BY_ID: \r
- mutex_lock(&board_id->operation_mutex); \r
- if(&board_id->device_start_addr[(unsigned)device_selected_temp.type][(unsigned)device_selected_temp.id])\r
- memcpy(&device_selected_last_temp, &board_id->device_start_addr[(unsigned)device_selected_temp.type][(unsigned)device_selected_temp.id], sizeof(struct device_id_name));\r
- else\r
- {\r
- printk("%s:fail to find device,type=%d,id=%d\n",__func__, device_selected_temp.type, device_selected_temp.id);\r
- mutex_unlock(&board_id->operation_mutex);\r
- return -1;\r
- }\r
- if(copy_to_user(argp, &device_selected_last_temp, sizeof(struct device_id_name)))\r
- {\r
- printk("%s:line=%d:fail to copy device_selected_last_temp.dev_name=%s to user\n",__func__,__LINE__,device_selected_last_temp.dev_name); \r
- mutex_unlock(&board_id->operation_mutex); \r
- return -EFAULT;\r
- }\r
- DBG_ID("%s:read: type=%d,id=%d,name=%s\n",__func__, (int)device_selected_last_temp.type, (int)device_selected_last_temp.id, device_selected_last_temp.dev_name);\r
- \r
- mutex_unlock(&board_id->operation_mutex); \r
- break;\r
-\r
- case BOARD_ID_IOCTL_READ_AREA_NAME_BY_ID:\r
- mutex_lock(&board_id->operation_mutex); \r
- if(copy_from_user(&language_last_select, argp, sizeof(struct area_id_name)))\r
- {\r
- printk("%s:line=%d:fail to copy area_id_name from user\n",__func__, __LINE__); \r
- mutex_unlock(&board_id->operation_mutex); \r
- return -EFAULT;\r
- } \r
- \r
- if(copy_to_user(argp, &board_id->area_area_id_name[language_last_select.id], sizeof(struct area_id_name)))\r
- {\r
- printk("%s:fail to copy area_id_name to user\n",__func__);\r
- mutex_unlock(&board_id->operation_mutex);\r
- return -EFAULT;\r
- }\r
- \r
- mutex_unlock(&board_id->operation_mutex);\r
- \r
- DBG_ID("%s:BOARD_ID_IOCTL_READ_LANGUAGE_NAME_BY_ID:%s_%s\n",__func__,language_last_select.locale_language,language_last_select.locale_region);\r
- break; \r
-\r
- case BOARD_ID_IOCTL_READ_OPERATOR_NAME_BY_ID:\r
- mutex_lock(&board_id->operation_mutex); \r
- if(copy_from_user(&operator_last_select, argp, sizeof(struct operator_id_name)))\r
- {\r
- printk("%s:line=%d:fail to copy operator_id_name from user\n",__func__, __LINE__); \r
- mutex_unlock(&board_id->operation_mutex); \r
- return -EFAULT;\r
- } \r
-\r
- for(i=OPERATOR_ID_20000_NO_OPERATOR; i<OPERATOR_ID_NUMS; i++)\r
- {\r
- if(operator_last_select.id == board_id->area_operator_id_name[i].id)\r
- {\r
- if(copy_to_user(argp, &board_id->area_operator_id_name[i], sizeof(struct operator_id_name)))\r
- {\r
- printk("%s:fail to copy operator_id_name to user\n",__func__);\r
- mutex_unlock(&board_id->operation_mutex);\r
- return -EFAULT;\r
- }\r
- }\r
- }\r
- mutex_unlock(&board_id->operation_mutex);\r
- \r
- DBG_ID("%s:BOARD_ID_IOCTL_READ_OPERATOR_NAME_BY_ID:%s_%s\n",__func__,operator_last_select.operator_name,operator_last_select.locale_region);\r
- break; \r
-\r
- case BOARD_ID_IOCTL_READ_RESERVE_NAME_BY_ID:\r
- mutex_lock(&board_id->operation_mutex); \r
- if(copy_from_user(&reserve_last_select, argp, sizeof(struct reserve_id_name)))\r
- {\r
- printk("%s:line=%d:fail to copy reserve_id_name from user\n",__func__, __LINE__); \r
- mutex_unlock(&board_id->operation_mutex); \r
- return -EFAULT;\r
- } \r
- \r
- if(copy_to_user(argp, &board_id->area_reserve_id_name[reserve_last_select.id], sizeof(struct reserve_id_name)))\r
- {\r
- printk("%s:fail to copy reserve_id_name to user\n",__func__);\r
- mutex_unlock(&board_id->operation_mutex);\r
- return -EFAULT;\r
- }\r
- \r
- mutex_unlock(&board_id->operation_mutex);\r
- \r
- DBG_ID("%s:BOARD_ID_IOCTL_READ_RESERVE_NAME_BY_ID:%s_%s\n",__func__,reserve_last_select.reserve_name, reserve_last_select.locale_region);\r
- break; \r
- \r
- }\r
-\r
- DBG_ID("%s:cmd=%d\n",__func__,cmd);\r
- return 0;\r
-}\r
-\r
-static int __init board_id_init(void)\r
-{\r
- int result ; \r
- struct proc_dir_entry *board_id_proc_entry;\r
- \r
- struct board_id_private_data *board_id = g_board_id;\r
-\r
- if(!board_id)\r
- return -1;\r
-\r
- board_id->id_fops.owner = THIS_MODULE;\r
- board_id->id_fops.open = board_id_open;\r
- board_id->id_fops.release = board_id_release; \r
- board_id->id_fops.unlocked_ioctl = board_id_ioctl;\r
-\r
- board_id->id_miscdev.minor = MISC_DYNAMIC_MINOR;\r
- board_id->id_miscdev.name = "board_id_misc";\r
- board_id->id_miscdev.fops = &board_id->id_fops;\r
- result = misc_register(&board_id->id_miscdev);\r
- if(result < 0) {\r
- printk("%s:misc_register err,ret=%d\n",__func__,result);\r
- return result;\r
- }\r
-\r
- \r
-#if defined(CONFIG_BOARD_ID_AUTO_XML)\r
- board_id_proc_entry = proc_create("driver/board_id_dbg", 0660, NULL, &board_id_proc_fops); \r
-#endif\r
- board_id->board_id_data_filp = NULL; \r
- board_id->board_id_area_filp = NULL; \r
- board_id->board_id_device_filp = NULL;\r
-\r
- printk("%s:\n",__func__);\r
-\r
- return 0;\r
- \r
-}\r
-\r
-static void __exit board_id_exit(void)\r
-{\r
- struct board_id_private_data *board_id = g_board_id;\r
-\r
- if(!board_id)\r
- return ;\r
-\r
- misc_deregister(&board_id->id_miscdev);\r
-\r
- set_fs(board_id->board_id_data_fs);\r
- filp_close(board_id->board_id_data_filp, NULL);\r
-\r
- set_fs(board_id->board_id_area_fs);\r
- filp_close(board_id->board_id_area_filp, NULL);\r
-\r
- set_fs(board_id->board_id_device_fs);\r
- filp_close(board_id->board_id_device_filp, NULL);\r
-}\r
-\r
-subsys_initcall_sync(board_id_init);\r
-module_exit(board_id_exit);\r
-\r
-MODULE_AUTHOR("ROCKCHIP Corporation:lw@rock-chips.com");\r
-MODULE_DESCRIPTION("rockchip board id misc interface for vendor");\r
-MODULE_LICENSE("GPL");\r
+++ /dev/null
-#include <linux/kernel.h>\r
-#include <linux/init.h>\r
-#include <linux/platform_device.h>\r
-#include <linux/input.h>\r
-#include <linux/io.h>\r
-#include <linux/delay.h>\r
-#include <linux/i2c.h>\r
-#include <linux/skbuff.h>\r
-\r
-#include <mach/board.h>\r
-#include <mach/io.h>\r
-#include <mach/gpio.h>\r
-#include <mach/iomux.h>\r
-\r
-#include <linux/board-id.h>\r
-\r
-#if 0\r
-#define DBG(x...) printk(x)\r
-#else\r
-#define DBG(x...)\r
-#endif\r
-\r
-extern void kernel_restart(char *cmd);\r
-\r
-struct board_id_hw_private_data {\r
- struct mutex id_mutex;\r
- int last_value[16];\r
- int board_id;\r
- struct board_id_platform_data *pdata;\r
-};\r
-\r
-static struct board_id_hw_private_data *g_id;\r
-\r
-\r
-enum board_id_hw get_board_id_hw(void)\r
-{\r
- struct board_id_hw_private_data *id = g_id;\r
- DBG("%s:id:0x%x\n",__func__,id->board_id);\r
- return id->board_id;\r
-}\r
-EXPORT_SYMBOL(get_board_id_hw);\r
-\r
-static int _get_board_id_hw(struct board_id_hw_private_data *id)\r
-{\r
- int result = 0;\r
- int value1 = 0, value2 = 0, value3 = 0;\r
- int i = 0, j = 0;\r
- \r
- id->board_id = -1;\r
- \r
- for(i=0; i<id->pdata->num_gpio; i++)\r
- {\r
- gpio_request(id->pdata->gpio_pin[i],"gpio_board_id");\r
- gpio_direction_input(id->pdata->gpio_pin[i]);\r
- gpio_pull_updown(id->pdata->gpio_pin[i], PullDisable);\r
- for(j=0; j<1000; j++)\r
- {\r
- value1 = gpio_get_value(id->pdata->gpio_pin[i]);\r
- if(value1 < 0)\r
- continue;\r
- mdelay(1);\r
- value2 = gpio_get_value(id->pdata->gpio_pin[i]);\r
- if(value2 < 0)\r
- continue;\r
- mdelay(1);\r
- value3 = gpio_get_value(id->pdata->gpio_pin[i]);\r
- if(value3 < 0)\r
- continue;\r
- if((value1 == value2) && (value2 == value3))\r
- break;\r
- }\r
- if(j >= 1000)\r
- {\r
- printk("%s:hareware error,gpio level changed always!\n",__func__); \r
- kernel_restart(NULL);\r
- }\r
- \r
- result = (value1 << i) | result;\r
- \r
- DBG("%s:gpio:%d,value:%d\n",__func__,id->pdata->gpio_pin[i],value1);\r
- }\r
-\r
- id->board_id = result;\r
-\r
- \r
- DBG("%s:num=%d,id=0x%x\n",__func__,id->pdata->num_gpio, id->board_id);\r
-\r
- return result;\r
-}\r
-\r
-\r
-static int __devinit board_id_hw_probe(struct platform_device *pdev)\r
-{\r
- struct board_id_platform_data *pdata = pdev->dev.platform_data;\r
- struct board_id_hw_private_data *id = NULL;\r
- int result = 0;\r
-\r
- if(!pdata)\r
- return -ENOMEM;\r
- \r
- id = kzalloc(sizeof(struct board_id_hw_private_data), GFP_KERNEL);\r
- if (id == NULL) {\r
- dev_err(&pdev->dev, "Unable to allocate private data\n");\r
- return -ENOMEM;\r
- }\r
-\r
- id->pdata = pdata;\r
- \r
- if(pdata->init_platform_hw)\r
- pdata->init_platform_hw();\r
- \r
- result = _get_board_id_hw(id);\r
-\r
- if(pdata->init_parameter)\r
- pdata->init_parameter(id->board_id);\r
-\r
- if(pdata->exit_platform_hw)\r
- pdata->exit_platform_hw();\r
- \r
- platform_set_drvdata(pdev, id); \r
- g_id = id;\r
- \r
- printk("%s:board id :0x%x\n",__func__,result);\r
- return 0;\r
-}\r
-\r
-static int __devexit board_id_hw_remove(struct platform_device *pdev)\r
-{\r
- //struct board_id_platform_data *pdata = pdev->dev.platform_data;\r
- struct board_id_hw_private_data *id = platform_get_drvdata(pdev);\r
- \r
- kfree(id);\r
- \r
- return 0;\r
-}\r
-\r
-static struct platform_driver board_id_hw_driver = {\r
- .probe = board_id_hw_probe,\r
- .remove = __devexit_p(board_id_hw_remove),\r
- .driver = {\r
- .name = "board_id_hw",\r
- .owner = THIS_MODULE,\r
- },\r
-};\r
-\r
-static int __init board_id_hw_init(void)\r
-{\r
- return platform_driver_register(&board_id_hw_driver);\r
-}\r
-\r
-static void __exit board_id_hw_exit(void)\r
-{\r
- platform_driver_unregister(&board_id_hw_driver);\r
-}\r
-\r
-arch_initcall_sync(board_id_hw_init);\r
-module_exit(board_id_hw_exit);\r
-\r
-MODULE_AUTHOR("ROCKCHIP Corporation:lw@rock-chips.com");\r
-MODULE_DESCRIPTION("Interface for get board id");\r
-MODULE_LICENSE("GPL");\r
-\r
-\r
+++ /dev/null
-#include <linux/module.h>\r
-#include <linux/kernel.h>\r
-#include <linux/irq.h>\r
-#include <linux/gpio.h>\r
-#include <linux/input.h>\r
-#include <linux/platform_device.h>\r
-#include <linux/fs.h>\r
-#include <linux/uaccess.h>\r
-#include <linux/miscdevice.h>\r
-#include <linux/circ_buf.h>\r
-#include <linux/interrupt.h>\r
-#include <linux/miscdevice.h>\r
-#include <mach/iomux.h>\r
-#include <mach/gpio.h>\r
-#include <asm/gpio.h>\r
-#include <linux/delay.h>\r
-#include <linux/poll.h>\r
-#include <linux/wait.h>\r
-#include <linux/wakelock.h>\r
-#include <linux/workqueue.h>\r
-#include <linux/slab.h>\r
-#include <linux/spi/spi.h>\r
-#include <mach/board.h>\r
-#include <linux/board-id.h>\r
-\r
-\r
-struct board_id_private_data *g_board_id;\r
-\r
-extern char GetSNSectorInfoBeforeNandInit(char * pbuf);\r
-extern char GetVendor0InfoBeforeNandInit(char * pbuf);\r
-\r
-static struct device_id_name tp_id_name[TP_ID_NUMS] = {\r
- {DEVICE_TYPE_TP, TP_ID_NULL, "tp", "no_tp", "no", "no_tp", ((DEVICE_TYPE_TP<<8)+TP_ID_NULL)},\r
- {DEVICE_TYPE_TP, TP_ID_GT813, "tp", "Goodix-TS", "Goodix-TS", "gt813", ((DEVICE_TYPE_TP<<8)+TP_ID_GT813)},\r
- {DEVICE_TYPE_TP, TP_ID_EKTF2K, "tp", "elan-ktf2k", "elan-ktf2k", "elan-ktf2k", ((DEVICE_TYPE_TP<<8)+TP_ID_EKTF2K)},\r
- \r
-};\r
-\r
-\r
-static struct device_id_name lcd_id_name[LCD_ID_NUMS] = {\r
- {DEVICE_TYPE_LCD, LCD_ID_NULL, "lcd", "no_lcd", "no", "no_lcd", ((DEVICE_TYPE_LCD<<8)+LCD_ID_NULL)},\r
- {DEVICE_TYPE_LCD, LCD_ID_IVO_M101_NWN8, "lcd", "IVO_M101_NWN8", "IVO_M101_NWN8", "101' 1280*800", ((DEVICE_TYPE_LCD<<8)+LCD_ID_IVO_M101_NWN8)}, \r
- {DEVICE_TYPE_LCD, LCD_ID_EDID_I2C, "lcd", "lcd_edid_i2c", "edid", "auto lcd edid", ((DEVICE_TYPE_LCD<<8)+LCD_ID_EDID_I2C)},\r
-\r
-};\r
-\r
-\r
-static struct device_id_name key_id_name[KEY_ID_NUMS] = {\r
- {DEVICE_TYPE_KEY, KEY_ID_NULL, "key", "no_key", "no", "no_key", ((DEVICE_TYPE_KEY<<8)+KEY_ID_NULL)},\r
- {DEVICE_TYPE_KEY, KEY_ID_SHUTTLE, "key", "shuttle_key", "shuttle", "shuttle_key", ((DEVICE_TYPE_KEY<<8)+KEY_ID_SHUTTLE)},\r
- {DEVICE_TYPE_KEY, KEY_ID_BITLAND, "key", "blueberry_kb", "bitland", "bitland_key", ((DEVICE_TYPE_KEY<<8)+KEY_ID_BITLAND)},\r
- {DEVICE_TYPE_KEY, KEY_ID_MALATA, "key", "malata_key", "malata", "malata_key", ((DEVICE_TYPE_KEY<<8)+KEY_ID_MALATA)},\r
- {DEVICE_TYPE_KEY, KEY_ID_CAPSENSE, "key", "cy8c20236", "cy8c20236", "cy8c20236_key", ((DEVICE_TYPE_KEY<<8)+KEY_ID_CAPSENSE)},\r
-\r
- // type id type_name driver_name dev_name description device_id \r
- {DEVICE_TYPE_KEY, KEY_ID_ENGLISH_US, "key", "blueberry_kb", "english_us", "english_us_key", ((DEVICE_TYPE_KEY<<8)+KEY_ID_ENGLISH_US)},\r
- {DEVICE_TYPE_KEY, KEY_ID_ENGLISH_UK, "key", "blueberry_kb", "english_uk", "english_uk_key", ((DEVICE_TYPE_KEY<<8)+KEY_ID_ENGLISH_UK)},\r
-\r
- {DEVICE_TYPE_KEY, KEY_ID_TURKISH, "key", "blueberry_kb", "turkish", "turkish_key", ((DEVICE_TYPE_KEY<<8)+KEY_ID_TURKISH)},\r
- {DEVICE_TYPE_KEY, KEY_ID_SLOVENIAN, "key", "blueberry_kb", "slovenian", "slovenian_key", ((DEVICE_TYPE_KEY<<8)+KEY_ID_SLOVENIAN)},\r
- {DEVICE_TYPE_KEY, KEY_ID_RUSSIAN, "key", "blueberry_kb", "russian", "russian_key", ((DEVICE_TYPE_KEY<<8)+KEY_ID_RUSSIAN)},\r
- {DEVICE_TYPE_KEY, KEY_ID_CZECH, "key", "blueberry_kb", "czech", "czech_key", ((DEVICE_TYPE_KEY<<8)+KEY_ID_CZECH)},\r
- {DEVICE_TYPE_KEY, KEY_ID_HUNGARIAN, "key", "blueberry_kb", "hungarian", "hungarian_key", ((DEVICE_TYPE_KEY<<8)+KEY_ID_HUNGARIAN)},\r
- {DEVICE_TYPE_KEY, KEY_ID_HINDI, "key", "blueberry_kb", "hindi", "hindi_key", ((DEVICE_TYPE_KEY<<8)+KEY_ID_HINDI)},\r
- {DEVICE_TYPE_KEY, KEY_ID_THAI, "key", "blueberry_kb", "thai", "thai_key", ((DEVICE_TYPE_KEY<<8)+KEY_ID_THAI)},\r
- {DEVICE_TYPE_KEY, KEY_ID_PORTUGUESE, "key", "blueberry_kb", "portuguese", "portuguese_key", ((DEVICE_TYPE_KEY<<8)+KEY_ID_PORTUGUESE)},\r
- {DEVICE_TYPE_KEY, KEY_ID_ARABIC, "key", "blueberry_kb", "arabic", "arabic_key", ((DEVICE_TYPE_KEY<<8)+KEY_ID_ARABIC)},\r
- {DEVICE_TYPE_KEY, KEY_ID_GREEK, "key", "blueberry_kb", "greek", "greek_key", ((DEVICE_TYPE_KEY<<8)+KEY_ID_GREEK)},\r
- //Nordics \r
- {DEVICE_TYPE_KEY, KEY_ID_SWEDISH, "key", "blueberry_kb", "swedish", "swedish_key", ((DEVICE_TYPE_KEY<<8)+KEY_ID_SWEDISH)},\r
- {DEVICE_TYPE_KEY, KEY_ID_NORWEGIAN, "key", "blueberry_kb", "norwegian", "norwegian_key", ((DEVICE_TYPE_KEY<<8)+KEY_ID_NORWEGIAN)},\r
- {DEVICE_TYPE_KEY, KEY_ID_FINNISH, "key", "blueberry_kb", "finnish", "finnish_key", ((DEVICE_TYPE_KEY<<8)+KEY_ID_FINNISH)},\r
- {DEVICE_TYPE_KEY, KEY_ID_DANISH, "key", "blueberry_kb", "danish", "danish_key", ((DEVICE_TYPE_KEY<<8)+KEY_ID_DANISH)},\r
- {DEVICE_TYPE_KEY, KEY_ID_ESTONIAN, "key", "blueberry_kb", "estonian", "estonian_key", ((DEVICE_TYPE_KEY<<8)+KEY_ID_ESTONIAN)},\r
-\r
- {DEVICE_TYPE_KEY, KEY_ID_FRENCH, "key", "blueberry_kb", "french", "french_key", ((DEVICE_TYPE_KEY<<8)+KEY_ID_FRENCH)},\r
- {DEVICE_TYPE_KEY, KEY_ID_GERMAN, "key", "blueberry_kb", "german", "german_key", ((DEVICE_TYPE_KEY<<8)+KEY_ID_GERMAN)},\r
- {DEVICE_TYPE_KEY, KEY_ID_HEBREW, "key", "blueberry_kb", "hebrew", "hebrew_key", ((DEVICE_TYPE_KEY<<8)+KEY_ID_HEBREW)},\r
- {DEVICE_TYPE_KEY, KEY_ID_ITALIAN, "key", "blueberry_kb", "italian", "italian_key", ((DEVICE_TYPE_KEY<<8)+KEY_ID_ITALIAN)},\r
- {DEVICE_TYPE_KEY, KEY_ID_SPANISH, "key", "blueberry_kb", "spanish", "spanish_key", ((DEVICE_TYPE_KEY<<8)+KEY_ID_SPANISH)},\r
-\r
- {DEVICE_TYPE_KEY, KEY_ID_SWISS, "key", "blueberry_kb", "swiss", "swiss_key", ((DEVICE_TYPE_KEY<<8)+KEY_ID_SWISS)},\r
- {DEVICE_TYPE_KEY, KEY_ID_DUTCH, "key", "blueberry_kb", "dutch", "dutch_key", ((DEVICE_TYPE_KEY<<8)+KEY_ID_DUTCH)},\r
- {DEVICE_TYPE_KEY, KEY_ID_BELGIAN, "key", "blueberry_kb", "belgian", "belgian_key", ((DEVICE_TYPE_KEY<<8)+KEY_ID_BELGIAN)},\r
- {DEVICE_TYPE_KEY, KEY_ID_NORDIC, "key", "blueberry_kb", "nordic", "nordic_kb", ((DEVICE_TYPE_KEY<<8)+KEY_ID_NORDIC)},\r
-\r
-\r
-};\r
-\r
-\r
-static struct device_id_name codec_id_name[CODEC_ID_NUMS] = { \r
- {DEVICE_TYPE_CODEC, CODEC_ID_NULL, "codec", "no_codec", "no", "no_codec", ((DEVICE_TYPE_CODEC<<8)+CODEC_ID_NULL)}, \r
- //to add\r
- {DEVICE_TYPE_CODEC, CODEC_ID_WM8994, "codec", "wm8994", "wm8994", "wm8994", ((DEVICE_TYPE_CODEC<<8)+CODEC_ID_WM8994)}, \r
- {DEVICE_TYPE_CODEC, CODEC_ID_WM8900, "codec", "wm8900", "wm8900", "wm8900", ((DEVICE_TYPE_CODEC<<8)+CODEC_ID_WM8900)}, \r
- {DEVICE_TYPE_CODEC, CODEC_ID_WM8988, "codec", "wm8988", "wm8988", "wm8988", ((DEVICE_TYPE_CODEC<<8)+CODEC_ID_WM8988)}, \r
- {DEVICE_TYPE_CODEC, CODEC_ID_RT5616, "codec", "rt5616", "rt5616", "rt5616", ((DEVICE_TYPE_CODEC<<8)+CODEC_ID_RT5616)}, \r
- {DEVICE_TYPE_CODEC, CODEC_ID_RT5621, "codec", "rt5621", "rt5621", "rt5621", ((DEVICE_TYPE_CODEC<<8)+CODEC_ID_RT5621)}, \r
- {DEVICE_TYPE_CODEC, CODEC_ID_RT5623, "codec", "rt5623", "rt5623", "rt5623", ((DEVICE_TYPE_CODEC<<8)+CODEC_ID_RT5623)}, \r
- {DEVICE_TYPE_CODEC, CODEC_ID_RT3224, "codec", "rt3224", "rt3224", "rt3224", ((DEVICE_TYPE_CODEC<<8)+CODEC_ID_RT3224)}, \r
- {DEVICE_TYPE_CODEC, CODEC_ID_RT5625, "codec", "rt5625", "rt5625", "rt5625", ((DEVICE_TYPE_CODEC<<8)+CODEC_ID_RT5625)}, \r
- {DEVICE_TYPE_CODEC, CODEC_ID_RT5631, "codec", "rt5631", "rt5631", "rt5631", ((DEVICE_TYPE_CODEC<<8)+CODEC_ID_RT5631)}, \r
- {DEVICE_TYPE_CODEC, CODEC_ID_RT5639, "codec", "rt5639", "rt5639", "rt5639", ((DEVICE_TYPE_CODEC<<8)+CODEC_ID_RT5639)}, \r
- {DEVICE_TYPE_CODEC, CODEC_ID_RT5640, "codec", "rt5640", "rt5640", "rt5640", ((DEVICE_TYPE_CODEC<<8)+CODEC_ID_RT5640)}, \r
- {DEVICE_TYPE_CODEC, CODEC_ID_RT5642, "codec", "rt5642", "rt5642", "rt5642", ((DEVICE_TYPE_CODEC<<8)+CODEC_ID_RT5642)}, \r
- {DEVICE_TYPE_CODEC, CODEC_ID_RT3261, "codec", "rt3261", "rt3261", "rt3261", ((DEVICE_TYPE_CODEC<<8)+CODEC_ID_RT3261)}, \r
- {DEVICE_TYPE_CODEC, CODEC_ID_AIC3262, "codec", "aic3262", "aic3262", "aic3262", ((DEVICE_TYPE_CODEC<<8)+CODEC_ID_AIC3262)}, \r
- {DEVICE_TYPE_CODEC, CODEC_ID_RK610, "codec", "rk610_i2c_codec", "rk610", "rk610", ((DEVICE_TYPE_CODEC<<8)+CODEC_ID_RK610)}, \r
- {DEVICE_TYPE_CODEC, CODEC_ID_RK616, "codec", "rk616", "rk616", "rk616", ((DEVICE_TYPE_CODEC<<8)+CODEC_ID_RK616)},\r
- {DEVICE_TYPE_CODEC, CODEC_ID_RK1000, "codec", "rk1000", "rk1000", "rk1000", ((DEVICE_TYPE_CODEC<<8)+CODEC_ID_RK1000)},\r
- {DEVICE_TYPE_CODEC, CODEC_ID_CS42L52, "codec", "cs42l52", "cs42l52", "cs42l52", ((DEVICE_TYPE_CODEC<<8)+CODEC_ID_CS42L52)},\r
- {DEVICE_TYPE_CODEC, CODEC_ID_ES8323, "codec", "es8323", "es8323", "es8323", ((DEVICE_TYPE_CODEC<<8)+CODEC_ID_ES8323)},\r
- \r
-};\r
-\r
-\r
-static struct device_id_name wifi_id_name[WIFI_ID_NUMS] = {\r
- {DEVICE_TYPE_WIFI, WIFI_ID_NULL, "wifi", "no_wifi", "no", "no_wifi", ((DEVICE_TYPE_WIFI<<8)+WIFI_ID_NULL)},\r
- {DEVICE_TYPE_WIFI, WIFI_ID_BCM, "wifi", "bcmdhd_wlan", "bcm", "WIFI_MODULE_BCM product", ((DEVICE_TYPE_WIFI<<8)+WIFI_ID_BCM)},\r
- {DEVICE_TYPE_WIFI, WIFI_ID_BCM4319, "wifi", "bcmdhd_wlan", "bcm4319", "WIFI_MODULE_BCM4319", ((DEVICE_TYPE_WIFI<<8)+WIFI_ID_BCM4319)}, \r
- {DEVICE_TYPE_WIFI, WIFI_ID_BCM4330, "wifi", "bcmdhd_wlan", "bcm4330", "WIFI_MODULE_BCM4330", ((DEVICE_TYPE_WIFI<<8)+WIFI_ID_BCM4330)},\r
- {DEVICE_TYPE_WIFI, WIFI_ID_RK903_26M, "wifi", "bcmdhd_wlan", "rk903_26m", "WIFI_MODULE_RK903_26M", ((DEVICE_TYPE_WIFI<<8)+WIFI_ID_RK903_26M)},\r
- {DEVICE_TYPE_WIFI, WIFI_ID_RK903_37M, "wifi", "bcmdhd_wlan", "rk903_37m", "WIFI_MODULE_RK903_37M", ((DEVICE_TYPE_WIFI<<8)+WIFI_ID_RK903_37M)},\r
- {DEVICE_TYPE_WIFI, WIFI_ID_BCM4329, "wifi", "bcmdhd_wlan", "bcm4329", "WIFI_MODULE_BCM4329", ((DEVICE_TYPE_WIFI<<8)+WIFI_ID_BCM4329)}, \r
- {DEVICE_TYPE_WIFI, WIFI_ID_RK901, "wifi", "bcmdhd_wlan", "rk901", "WIFI_MODULE_RK901", ((DEVICE_TYPE_WIFI<<8)+WIFI_ID_RK901)},\r
- {DEVICE_TYPE_WIFI, WIFI_ID_AP6181, "wifi", "ap6181", "ap6181", "WIFI_MODULE_AP6181", ((DEVICE_TYPE_WIFI<<8)+WIFI_ID_AP6181)},\r
- {DEVICE_TYPE_WIFI, WIFI_ID_AP6210, "wifi", "ap6210", "ap6210", "WIFI_MODULE_AP6210", ((DEVICE_TYPE_WIFI<<8)+WIFI_ID_AP6210)},\r
- {DEVICE_TYPE_WIFI, WIFI_ID_AP6330, "wifi", "ap6330", "ap6330", "WIFI_MODULE_AP6330", ((DEVICE_TYPE_WIFI<<8)+WIFI_ID_AP6330)},\r
- {DEVICE_TYPE_WIFI, WIFI_ID_AP6476, "wifi", "ap6476", "ap6476", "WIFI_MODULE_AP6476", ((DEVICE_TYPE_WIFI<<8)+WIFI_ID_AP6476)},\r
- {DEVICE_TYPE_WIFI, WIFI_ID_AP6493, "wifi", "ap6493", "ap6493", "WIFI_MODULE_AP6493", ((DEVICE_TYPE_WIFI<<8)+WIFI_ID_AP6493)},\r
- {DEVICE_TYPE_WIFI, WIFI_ID_GB86302I, "wifi", "gb86302i", "gb86302i", "WIFI_MODULE_GB86302I", ((DEVICE_TYPE_WIFI<<8)+WIFI_ID_GB86302I)},\r
-\r
- {DEVICE_TYPE_WIFI, WIFI_ID_RTL8192CU, "wifi", "rtl8192cu_usb", "rtl8192cu_usb", "WIFI_MODULE_RTL8192CU_USB", ((DEVICE_TYPE_WIFI<<8)+WIFI_ID_RTL8192CU)},\r
- {DEVICE_TYPE_WIFI, WIFI_ID_RTL8188EU, "wifi", "rt8188eu_usb", "rt8188eu_usb", "WIFI_MODULE_RTL8188EU_USB", ((DEVICE_TYPE_WIFI<<8)+WIFI_ID_RTL8188EU)},\r
- {DEVICE_TYPE_WIFI, WIFI_ID_RTL8723AU, "wifi", "rtl8723au_usb", "rtl8723au_usb", "WIFI_MODULE_RTL8723AU_USB", ((DEVICE_TYPE_WIFI<<8)+WIFI_ID_RTL8723AU)},\r
-\r
- \r
- {DEVICE_TYPE_WIFI, WIFI_ID_COMBO, "wifi", "combo-wifi", "combo-wifi", "WIFI_MODULE_MT product", ((DEVICE_TYPE_WIFI<<8)+WIFI_ID_COMBO)},\r
- {DEVICE_TYPE_WIFI, WIFI_ID_MT5931, "wifi", "combo-wifi", "mt5931", "WIFI_MODULE_MT5931", ((DEVICE_TYPE_WIFI<<8)+WIFI_ID_MT5931)},\r
- {DEVICE_TYPE_WIFI, WIFI_ID_RT5370, "wifi", "rt5370_usb", "rt5370", "WIFI_MODULE_RT5370_USB", ((DEVICE_TYPE_WIFI<<8)+WIFI_ID_RT5370)},\r
-\r
-};\r
-\r
-\r
-static struct device_id_name bt_id_name[BT_ID_NUMS] = {\r
- {DEVICE_TYPE_BT, BT_ID_NULL, "bt", "no_bluetooth", "no", "no_bluetooth", ((DEVICE_TYPE_BT<<8)+BT_ID_NULL)},\r
- {DEVICE_TYPE_BT, BT_ID_NH660, "bt", "nh660", "nh660", "BT_MODULE_NH660", ((DEVICE_TYPE_BT<<8)+BT_ID_NH660)}, \r
- {DEVICE_TYPE_BT, BT_ID_BCM4330, "bt", "rfkill_rk", "bcm4330", "BT_MODULE_BCM4330", ((DEVICE_TYPE_BT<<8)+BT_ID_BCM4330)},\r
- {DEVICE_TYPE_BT, BT_ID_RK903_26M, "bt", "rfkill_rk", "rk903_26m", "BT_MODULE_RK903_26M", ((DEVICE_TYPE_BT<<8)+BT_ID_RK903_26M)},\r
- {DEVICE_TYPE_BT, BT_ID_RK903, "bt", "rfkill_rk", "rk903", "BT_MODULE_RK903_37M", ((DEVICE_TYPE_BT<<8)+BT_ID_RK903)},\r
- {DEVICE_TYPE_BT, BT_ID_BCM4329, "bt", "rfkill_rk", "bcm4329", "BT_MODULE_BCM4329", ((DEVICE_TYPE_BT<<8)+BT_ID_BCM4329)},\r
- {DEVICE_TYPE_BT, BT_ID_MV8787, "bt", "rfkill_rk", "mv8787", "BT_MODULE_MV8787", ((DEVICE_TYPE_BT<<8)+BT_ID_MV8787)},\r
- {DEVICE_TYPE_BT, BT_ID_AP6210, "bt", "rfkill_rk", "ap6210", "BT_MODULE_AP6210", ((DEVICE_TYPE_BT<<8)+BT_ID_AP6210)},\r
- {DEVICE_TYPE_BT, BT_ID_AP6330, "bt", "rfkill_rk", "ap6330", "BT_MODULE_AP6330", ((DEVICE_TYPE_BT<<8)+BT_ID_AP6330)},\r
- {DEVICE_TYPE_BT, BT_ID_AP6476, "bt", "rfkill_rk", "ap6476", "BT_MODULE_AP6476", ((DEVICE_TYPE_BT<<8)+BT_ID_AP6476)},\r
- {DEVICE_TYPE_BT, BT_ID_AP6493, "bt", "rfkill_rk", "ap6493", "BT_MODULE_AP6493", ((DEVICE_TYPE_BT<<8)+BT_ID_AP6493)},\r
- {DEVICE_TYPE_BT, BT_ID_RFKILL, "bt", "rfkill_rk", "bcm", "bcm product", ((DEVICE_TYPE_BT<<8)+BT_ID_RFKILL)},\r
- {DEVICE_TYPE_BT, BT_ID_RTL8723, "bt", "rfkill_rk", "rtl8723", "BT_MODULE_RTL8723", ((DEVICE_TYPE_BT<<8)+BT_ID_RTL8723)},\r
- {DEVICE_TYPE_BT, BT_ID_MT6622, "bt", "mt6622", "mt6622", "BT_MODULE_MT6622", ((DEVICE_TYPE_BT<<8)+BT_ID_MT6622)},\r
- \r
-};\r
- \r
-static struct device_id_name gps_id_name[GPS_ID_NUMS] = {\r
- {DEVICE_TYPE_GPS, GPS_ID_NULL, "gps", "no_gps", "no", "no_gps", ((DEVICE_TYPE_GPS<<8)+GPS_ID_NULL)}, \r
- \r
- //to add\r
- {DEVICE_TYPE_GPS, GPS_ID_RK_HV5820, "gps", "gps_hv5820b", "hv5820b", "gps rk2928", ((DEVICE_TYPE_GPS<<8)+GPS_ID_RK_HV5820)},\r
- {DEVICE_TYPE_GPS, GPS_ID_BCM4751, "gps", "bcm4751", "bcm4751", "gps bcm4751", ((DEVICE_TYPE_GPS<<8)+GPS_ID_BCM4751)},\r
- {DEVICE_TYPE_GPS, GPS_ID_GNS7560, "gps", "gns7560", "gns7560", "gps gns7560", ((DEVICE_TYPE_GPS<<8)+GPS_ID_GNS7560)},\r
- {DEVICE_TYPE_GPS, GPS_ID_MT3326, "gps", "mt3326", "mt3326", "gps mt3326", ((DEVICE_TYPE_GPS<<8)+GPS_ID_MT3326)},\r
- \r
-};\r
-\r
-static struct device_id_name fm_id_name[FM_ID_NUMS] = {\r
- {DEVICE_TYPE_FM, FM_ID_NULL, "fm", "no_fm", "no", "no_fm", ((DEVICE_TYPE_FM<<8)+FM_ID_NULL)}, \r
- \r
- //to add\r
-};\r
-\r
-\r
-static struct device_id_name modem_id_name[MODEM_ID_NUMS] = {\r
- {DEVICE_TYPE_MODEM, MODEM_ID_NULL, "modem", "no_modem", "no", "no_modem", ((DEVICE_TYPE_MODEM<<8)+MODEM_ID_NULL)}, \r
- \r
- //to add\r
- {DEVICE_TYPE_MODEM, MODEM_ID_MT6229, "modem", "bp-auto", "mt6229", "USI MT6229 WCDMA", ((DEVICE_TYPE_MODEM<<8)+MODEM_ID_MT6229)}, \r
- {DEVICE_TYPE_MODEM, MODEM_ID_MU509, "modem", "bp-auto", "mu509", "huawei MU509 WCDMA", ((DEVICE_TYPE_MODEM<<8)+MODEM_ID_MU509)}, \r
- {DEVICE_TYPE_MODEM, MODEM_ID_MI700, "modem", "bp-auto", "mi700", "thinkwill MI700 WCDMA", ((DEVICE_TYPE_MODEM<<8)+MODEM_ID_MI700)}, \r
- {DEVICE_TYPE_MODEM, MODEM_ID_MW100, "modem", "bp-auto", "mw100", "thinkwill MW100 WCDMA", ((DEVICE_TYPE_MODEM<<8)+MODEM_ID_MW100)}, \r
- {DEVICE_TYPE_MODEM, MODEM_ID_TD8801, "modem", "bp-auto", "td8801", "spreadtrum SC8803 TD-SCDMA", ((DEVICE_TYPE_MODEM<<8)+MODEM_ID_TD8801)}, \r
- {DEVICE_TYPE_MODEM, MODEM_ID_SC6610, "modem", "bp-auto", "sc6610", "spreadtrum SC6610 GSM", ((DEVICE_TYPE_MODEM<<8)+MODEM_ID_SC6610)}, \r
- {DEVICE_TYPE_MODEM, MODEM_ID_M50, "modem", "bp-auto", "m50", "spreadtrum RDA GSM", ((DEVICE_TYPE_MODEM<<8)+MODEM_ID_M50)}, \r
- {DEVICE_TYPE_MODEM, MODEM_ID_MT6250, "modem", "bp-auto", "mt6250", "ZINN M50 EDGE", ((DEVICE_TYPE_MODEM<<8)+MODEM_ID_MT6250)}, \r
- {DEVICE_TYPE_MODEM, MODEM_ID_C66A, "modem", "bp-auto", "c66a", "zhongben w200 gsm", ((DEVICE_TYPE_MODEM<<8)+MODEM_ID_C66A)},\r
- \r
-};\r
- \r
-static struct device_id_name ddr_id_name[DDR_ID_NUMS] = {\r
- {DEVICE_TYPE_DDR, DDR_ID_NULL, "ddr", "no_ddr", "no", "no_ddr", ((DEVICE_TYPE_DDR<<8)+DDR_ID_NULL)},\r
- \r
- //to add\r
-};\r
-\r
-static struct device_id_name flash_id_name[FLASH_ID_NUMS] = {\r
- {DEVICE_TYPE_FLASH, FLASH_ID_NULL, "flash", "no_flash", "no", "no_flash", ((DEVICE_TYPE_FLASH<<8)+FLASH_ID_NULL)}, \r
- \r
- //to add\r
-};\r
-\r
-\r
-static struct device_id_name hdmi_id_name[HDMI_ID_NUMS] = {\r
- {DEVICE_TYPE_HDMI, HDMI_ID_NULL, "hdmi", "no_hdmi", "no", "no_hdmi", ((DEVICE_TYPE_HDMI<<8)+HDMI_ID_NULL)}, \r
- \r
- //to add\r
- {DEVICE_TYPE_HDMI, HDMI_ID_RK30, "hdmi", "rk_hdmi", "rk", "rk3066 hdmi", ((DEVICE_TYPE_HDMI<<8)+HDMI_ID_RK30)},\r
- {DEVICE_TYPE_HDMI, HDMI_ID_CAT66121, "hdmi", "cat66121_hdmi", "cat66121", "hdmi cat66121", ((DEVICE_TYPE_HDMI<<8)+HDMI_ID_CAT66121)},\r
- {DEVICE_TYPE_HDMI, HDMI_ID_RK610, "hdmi", "rk610_hdmi", "rk610", "hdmi rk610", ((DEVICE_TYPE_HDMI<<8)+HDMI_ID_RK610)},\r
- \r
-};\r
-\r
-\r
-static struct device_id_name battery_id_name[BATTERY_ID_NUMS] = {\r
- {DEVICE_TYPE_BATTERY, BATTERY_ID_NULL, "battery", "no_battery", "no", "no_battery", ((DEVICE_TYPE_BATTERY<<8)+BATTERY_ID_NULL)}, \r
- \r
- //to add\r
- {DEVICE_TYPE_BATTERY, BATTERY_ID_3300MAH, "battery", "rk30-battery", "3300mah", "3300mah battery", ((DEVICE_TYPE_BATTERY<<8)+BATTERY_ID_3300MAH)},\r
- {DEVICE_TYPE_BATTERY, BATTERY_ID_3600MAH, "battery", "rk30-battery", "3600mah", "3600mah battery", ((DEVICE_TYPE_BATTERY<<8)+BATTERY_ID_3600MAH)},\r
- {DEVICE_TYPE_BATTERY, BATTERY_ID_4700MAH, "battery", "rk30-battery", "4700mah", "4700mah battery", ((DEVICE_TYPE_BATTERY<<8)+BATTERY_ID_4700MAH)},\r
- {DEVICE_TYPE_BATTERY, BATTERY_ID_7000MAH, "battery", "rk30-battery", "7000mah", "7000mah battery", ((DEVICE_TYPE_BATTERY<<8)+BATTERY_ID_7000MAH)},\r
- {DEVICE_TYPE_BATTERY, BATTERY_ID_7700MAH, "battery", "rk30-battery", "7700mah", "7700mah battery", ((DEVICE_TYPE_BATTERY<<8)+BATTERY_ID_7700MAH)},\r
- {DEVICE_TYPE_BATTERY, BATTERY_ID_9000MAH, "battery", "rk30-battery", "9000mah", "9000mah battery", ((DEVICE_TYPE_BATTERY<<8)+BATTERY_ID_9000MAH)},\r
- {DEVICE_TYPE_BATTERY, BATTERY_ID_BLUEBERRY, "battery", "blueberry_bat", "blueberry", "blueberry battery", ((DEVICE_TYPE_BATTERY<<8)+BATTERY_ID_BLUEBERRY)},\r
- \r
-};\r
-\r
-\r
-\r
-static struct device_id_name charge_id_name[CHARGE_ID_NUMS] = {\r
- {DEVICE_TYPE_CHARGE, CHARGE_ID_NULL, "charge", "no_charge", "no", "no_charge", ((DEVICE_TYPE_CHARGE<<8)+CHARGE_ID_NULL)}, \r
- \r
- //to add\r
- {DEVICE_TYPE_CHARGE, CHARGE_ID_CW2015, "charge", "cw2015", "cw2015", "charge cw2015", ((DEVICE_TYPE_CHARGE<<8)+CHARGE_ID_CW2015)}, \r
- {DEVICE_TYPE_CHARGE, CHARGE_ID_BQ24193, "charge", "bq24193", "bq24193", "charge BQ24193", ((DEVICE_TYPE_CHARGE<<8)+CHARGE_ID_BQ24193)}, \r
- {DEVICE_TYPE_CHARGE, CHARGE_ID_BQ27541, "charge", "bq27541", "bq27541", "charge BQ27541", ((DEVICE_TYPE_CHARGE<<8)+CHARGE_ID_BQ27541)}, \r
- {DEVICE_TYPE_CHARGE, CHARGE_ID_OZ8806, "charge", "oz8806", "oz8806", "charge OZ8806", ((DEVICE_TYPE_CHARGE<<8)+CHARGE_ID_OZ8806)}, \r
- \r
-};\r
-\r
- \r
-static struct device_id_name backlight_id_name[BACKLIGHT_ID_NUMS] = {\r
- {DEVICE_TYPE_BACKLIGHT, BACKLIGHT_ID_NULL, "backlight", "no_backlight", "no", "no_backlight", ((DEVICE_TYPE_BACKLIGHT<<8)+BACKLIGHT_ID_NULL)}, \r
- \r
- //to add\r
- {DEVICE_TYPE_BACKLIGHT, BACKLIGHT_ID_RK29, "backlight", "rk29_backlight", "rk29_backlight", "rk29_backlight", ((DEVICE_TYPE_BACKLIGHT<<8)+BACKLIGHT_ID_RK29)},\r
- {DEVICE_TYPE_BACKLIGHT, BACKLIGHT_ID_WM831X, "backlight", "wm831x", "wm831x", "wm831x_backlight", ((DEVICE_TYPE_BACKLIGHT<<8)+BACKLIGHT_ID_WM831X)},\r
- \r
-};\r
-\r
-static struct device_id_name headset_id_name[HEADSET_ID_NUMS] = {\r
- {DEVICE_TYPE_HEADSET, HEADSET_ID_NULL, "headset", "no_headset", "no", "no_headset", ((DEVICE_TYPE_HEADSET<<8)+HEADSET_ID_NULL)}, \r
- \r
- //to add\r
- {DEVICE_TYPE_HEADSET, HEADSET_ID_RK29, "headset", "rk_headsetdet", "rk_headsetdet", "rk29 headset", ((DEVICE_TYPE_HEADSET<<8)+HEADSET_ID_RK29)},\r
- \r
-};\r
-\r
-\r
-\r
-static struct device_id_name micphone_id_name[MICPHONE_ID_NUMS] = {\r
- {DEVICE_TYPE_MICPHONE, MICPHONE_ID_NULL, "micphone", "no_micphone", "no", "no_micphone", ((DEVICE_TYPE_MICPHONE<<8)+MICPHONE_ID_NULL)}, \r
- \r
- //to add\r
- {DEVICE_TYPE_MICPHONE, MICPHONE_ID_ANALOGIC, "micphone", "analogic", "analogic", "micphone analogic", ((DEVICE_TYPE_MICPHONE<<8)+MICPHONE_ID_ANALOGIC)}, \r
- {DEVICE_TYPE_MICPHONE, MICPHONE_ID_DIGITAL, "micphone", "digital", "digital", "micphone digital", ((DEVICE_TYPE_MICPHONE<<8)+MICPHONE_ID_DIGITAL)}, \r
-};\r
-\r
-\r
-static struct device_id_name speaker_id_name[SPEAKER_ID_NUMS] = {\r
- {DEVICE_TYPE_SPEAKER, SPEAKER_ID_NULL, "speaker", "no_speaker", "no", "no_speaker", ((DEVICE_TYPE_SPEAKER<<8)+SPEAKER_ID_NULL)}, \r
- \r
- //to add\r
- {DEVICE_TYPE_SPEAKER, SPEAKER_ID_0W8, "speaker", "speaker_08w", "speaker_08w", "speaker 0.8W", ((DEVICE_TYPE_SPEAKER<<8)+SPEAKER_ID_0W8)},\r
- {DEVICE_TYPE_SPEAKER, SPEAKER_ID_1W0, "speaker", "speaker_10w", "speaker_10w", "speaker 1.0W", ((DEVICE_TYPE_SPEAKER<<8)+SPEAKER_ID_1W0)},\r
- {DEVICE_TYPE_SPEAKER, SPEAKER_ID_1W5, "speaker", "speaker_15w", "speaker_15w", "speaker 1.5W", ((DEVICE_TYPE_SPEAKER<<8)+SPEAKER_ID_1W5)},\r
- \r
-};\r
-\r
-static struct device_id_name vibrator_id_name[VIBRATOR_ID_NUMS] = {\r
- {DEVICE_TYPE_VIBRATOR, VIBRATOR_ID_NULL, "vibrator", "no_vibrator", "no", "no_vibrator", ((DEVICE_TYPE_VIBRATOR<<8)+VIBRATOR_ID_NULL)}, \r
- \r
- //to add \r
- {DEVICE_TYPE_VIBRATOR, VIBRATOR_ID_RK29, "vibrator", "timed-gpio", "timed-gpio", "vibrator gpio", ((DEVICE_TYPE_VIBRATOR<<8)+VIBRATOR_ID_RK29)}, \r
-};\r
-\r
-static struct device_id_name tv_id_name[TV_ID_NUMS] = {\r
- {DEVICE_TYPE_TV, TV_ID_NULL, "tv", "no_tv", "no", "no_tv", ((DEVICE_TYPE_TV<<8)+TV_ID_NULL)}, \r
- \r
- //to add\r
- {DEVICE_TYPE_TV, TV_ID_RK610, "tv", "rk610_tvout", "rk610_tvout", "tv rk610", ((DEVICE_TYPE_TV<<8)+TV_ID_RK610)},\r
-};\r
-\r
-\r
-static struct device_id_name echip_id_name[ECHIP_ID_NUMS] = {\r
- {DEVICE_TYPE_ECHIP, ECHIP_ID_NULL, "echip", "no_ec", "no", "no_ec", ((DEVICE_TYPE_ECHIP<<8)+ECHIP_ID_NULL)}, \r
- \r
- //to add\r
- {DEVICE_TYPE_ECHIP, ECHIP_ID_IT8561, "echip", "ec_dev_i2c", "ec_dev_i2c", "ec it8561", ((DEVICE_TYPE_ECHIP<<8)+ECHIP_ID_IT8561)},\r
- {DEVICE_TYPE_ECHIP, ECHIP_ID_ITE, "echip", "ite", "ite", "ec ite", ((DEVICE_TYPE_ECHIP<<8)+ECHIP_ID_ITE)},\r
-};\r
-\r
-\r
-static struct device_id_name hub_id_name[HUB_ID_NUMS] = {\r
- {DEVICE_TYPE_HUB, HUB_ID_NULL, "hub", "no_hub", "no", "no_hub", ((DEVICE_TYPE_HUB<<8)+HUB_ID_NULL)}, \r
- \r
- //to add\r
- {DEVICE_TYPE_HUB, HUB_ID_USB4604, "hub", "usb4604", "usb4604", "3 ports", ((DEVICE_TYPE_HUB<<8)+HUB_ID_USB4604)},\r
-};\r
-\r
-static struct device_id_name tpad_id_name[TPAD_ID_NUMS] = {\r
- {DEVICE_TYPE_TPAD, TPAD_ID_NULL, "tpad", "no_tpad", "no", "no_tpad", ((DEVICE_TYPE_TPAD<<8)+TPAD_ID_NULL)}, \r
- \r
- //to add\r
- {DEVICE_TYPE_TPAD, TPAD_ID_ELAN, "tpad", "blueberry_tp", "elan", "elan", ((DEVICE_TYPE_TPAD<<8)+TPAD_ID_ELAN)},\r
- {DEVICE_TYPE_TPAD, TPAD_ID_SYNS, "tpad", "a10_tp_syn", "syns", "syns", ((DEVICE_TYPE_TPAD<<8)+TPAD_ID_SYNS)},\r
-};\r
-\r
- \r
-\r
-static struct device_id_name pmic_id_name[PMIC_ID_NUMS] = {\r
- {DEVICE_TYPE_PMIC, PMIC_ID_NULL, "pmic", "no_pmic", "no", "no_pmic", ((DEVICE_TYPE_PMIC<<8)+PMIC_ID_NULL)}, \r
- \r
- //to add\r
- {DEVICE_TYPE_PMIC, PMIC_ID_WM831X, "pmic", "wm831x", "wm831x", "wm831x", ((DEVICE_TYPE_PMIC<<8)+PMIC_ID_WM831X)},\r
- {DEVICE_TYPE_PMIC, PMIC_ID_WM8326, "pmic", "wm8326", "wm8326", "wm8326", ((DEVICE_TYPE_PMIC<<8)+PMIC_ID_WM8326)},\r
- {DEVICE_TYPE_PMIC, PMIC_ID_TPS65910, "pmic", "tps65910", "tps65910", "tps65910", ((DEVICE_TYPE_PMIC<<8)+PMIC_ID_TPS65910)},\r
- {DEVICE_TYPE_PMIC, PMIC_ID_ACT8846, "pmic", "act8846", "act8846", "act8846", ((DEVICE_TYPE_PMIC<<8)+PMIC_ID_ACT8846)},\r
- \r
-};\r
-\r
-static struct device_id_name regulator_id_name[REGULATOR_ID_NUMS] = {\r
- {DEVICE_TYPE_REGULATOR, REGULATOR_ID_NULL, "regulator", "no_regulator", "no", "no_regulator", ((DEVICE_TYPE_REGULATOR<<8)+REGULATOR_ID_NULL)}, \r
- \r
- //to add\r
- {DEVICE_TYPE_REGULATOR, REGULATOR_ID_PWM3, "regulator", "pwm3", "pwm3", "regulator pwm3", ((DEVICE_TYPE_REGULATOR<<8)+REGULATOR_ID_PWM3)},\r
- \r
-};\r
-\r
-\r
-static struct device_id_name rtc_id_name[RTC_ID_NUMS] = {\r
- {DEVICE_TYPE_RTC, RTC_ID_NULL, "rtc", "no_rtc", "no", "no_rtc", ((DEVICE_TYPE_RTC<<8)+RTC_ID_NULL)}, \r
- \r
- //to add\r
- {DEVICE_TYPE_RTC, RTC_ID_HYM8563, "rtc", "rtc_hym8563", "hym8563", "hym8563", ((DEVICE_TYPE_RTC<<8)+RTC_ID_HYM8563)}, \r
- {DEVICE_TYPE_RTC, RTC_ID_PCF8563, "rtc", "rtc-pcf8563", "pcf8563", "pcf8563", ((DEVICE_TYPE_RTC<<8)+RTC_ID_PCF8563)}, \r
- {DEVICE_TYPE_RTC, RTC_ID_TPS65910, "rtc", "rtc_tps65910", "tps65910", "tps65910", ((DEVICE_TYPE_RTC<<8)+RTC_ID_TPS65910)}, \r
- {DEVICE_TYPE_RTC, RTC_ID_WM8326, "rtc", "rtc_wm8326", "wm8326", "wm8326", ((DEVICE_TYPE_RTC<<8)+RTC_ID_WM8326)}, \r
- {DEVICE_TYPE_RTC, RTC_ID_RK, "rtc", "rk_rtc", "rk", "rk_rtc", ((DEVICE_TYPE_RTC<<8)+RTC_ID_RK)}, \r
- \r
-};\r
-\r
-static struct device_id_name camera_front_id_name[CAMERA_FRONT_ID_NUMS] = {\r
- {DEVICE_TYPE_CAMERA_FRONT, CAMERA_FRONT_ID_NULL, "camera_front", "no_front", "no", "no_camera_front", ((DEVICE_TYPE_CAMERA_FRONT<<8)\r
-\r
-+CAMERA_FRONT_ID_NULL)}, \r
- \r
- //to add\r
- \r
-};\r
-\r
-static struct device_id_name camera_back_id_name[CAMERA_BACK_ID_NUMS] = {\r
- {DEVICE_TYPE_CAMERA_BACK, CAMERA_BACK_ID_NULL, "camera_back", "no_back", "no", "no_camera_back", ((DEVICE_TYPE_CAMERA_BACK<<8)+CAMERA_BACK_ID_NULL)}, \r
- \r
- //to add\r
-};\r
- \r
-static struct device_id_name sensor_angle_id_name[ANGLE_ID_NUMS] = {\r
- {DEVICE_TYPE_ANGLE, ANGLE_ID_NULL, "angle", "no_angle", "no", "no_angle_sensor", ((DEVICE_TYPE_ANGLE<<8)+ANGLE_ID_NULL)}, \r
- \r
- //to add\r
- \r
-};\r
-\r
-static struct device_id_name sensor_accel_id_name[ACCEL_ID_NUMS] = {\r
- {DEVICE_TYPE_ACCEL, ACCEL_ID_NULL, "accel", "no_accel", "no", "no_accel_sensor", ((DEVICE_TYPE_ACCEL<<8)+ACCEL_ID_NULL)}, \r
- \r
- //to add\r
- \r
-};\r
-\r
-static struct device_id_name sensor_compass_id_name[COMPASS_ID_NUMS] = {\r
- {DEVICE_TYPE_COMPASS, COMPASS_ID_NULL, "compass", "no_compass", "no", "no_compass_sensor", ((DEVICE_TYPE_COMPASS<<8)+COMPASS_ID_NULL)}, \r
- \r
- //to add\r
- \r
-};\r
-\r
-static struct device_id_name sensor_gyroscope_id_name[GYRO_ID_NUMS] = {\r
- {DEVICE_TYPE_GYRO, GYRO_ID_NULL, "gyro", "no_gyro", "no", "no_gyro_sensor", ((DEVICE_TYPE_GYRO<<8)+GYRO_ID_NULL)}, \r
- \r
- //to add\r
- \r
-};\r
-\r
-static struct device_id_name sensor_light_id_name[LIGHT_ID_NUMS] = {\r
- {DEVICE_TYPE_LIGHT, LIGHT_ID_NULL, "light", "no_light", "no", "no_light_sensor", ((DEVICE_TYPE_LIGHT<<8)+LIGHT_ID_NULL)}, \r
- \r
- //to add\r
- \r
-};\r
-\r
-static struct device_id_name sensor_proximity_id_name[PROXIMITY_ID_NUMS] = {\r
- {DEVICE_TYPE_PROXIMITY, PROXIMITY_ID_NULL, "proximity", "no_proximity", "no", "no_proximity_sensor", ((DEVICE_TYPE_PROXIMITY<<8)+PROXIMITY_ID_NULL)}, \r
- \r
- //to add\r
- \r
-};\r
-\r
-static struct device_id_name sensor_temperature_id_name[TEMPERATURE_ID_NUMS] = {\r
- {DEVICE_TYPE_TEMPERATURE, TEMPERATURE_ID_NULL, "temperature", "no_temp", "no", "no_temperature_sensor", ((DEVICE_TYPE_TEMPERATURE<<8)\r
-\r
-+TEMPERATURE_ID_NULL)}, \r
- \r
- //to add\r
- \r
-};\r
- \r
-static struct device_id_name sensor_pressure_id_name[PRESSURE_ID_NUMS] = {\r
- {DEVICE_TYPE_PRESSURE, PRESSURE_ID_NULL, "pressure", "no_pressure", "no", "no_pressure_sensor", ((DEVICE_TYPE_PRESSURE<<8)+PRESSURE_ID_NULL)}, \r
- \r
- //to add\r
- \r
-};\r
-\r
-static struct area_id_name area_area_id_name[AREA_ID_NUMS] = {\r
- {DEVICE_TYPE_AREA, AREA_ID_NULL, "no", "no", "no", "no", "no", USER_DEFINE_NULL}, \r
- {DEVICE_TYPE_AREA,AREA_ID_ALBANIA,"Albania",LOCALE_LANGUAGE_EL,LOCALE_REGION_AL,COUNTRY_GEO_NULL,TIME_ZONE_BELGRADE,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_ALGERIA,"Algeria",LOCALE_LANGUAGE_AR,LOCALE_REGION_DZ,COUNTRY_GEO_NULL,TIME_ZONE_WINDHOEK,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_ANGOLA,"Angola",LOCALE_LANGUAGE_PT,LOCALE_REGION_AO,COUNTRY_GEO_NULL,TIME_ZONE_WINDHOEK,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_ARGENTINA,"Argentina",LOCALE_LANGUAGE_ES,LOCALE_REGION_AR,COUNTRY_GEO_NULL,TIME_ZONE_BUENOS_AIRES,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_AUSTRALIA,"Australia",LOCALE_LANGUAGE_EN,LOCALE_REGION_AU,COUNTRY_GEO_NULL,TIME_ZONE_PERTH,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_AUSTRIA,"Austria",LOCALE_LANGUAGE_DE,LOCALE_REGION_AT,COUNTRY_GEO_NULL,TIME_ZONE_BELGRADE,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_AZERBAIJAN,"Azerbaijan",LOCALE_LANGUAGE_RU,LOCALE_REGION_AZ,COUNTRY_GEO_NULL,TIME_ZONE_BAKU,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_BAHRAIN,"Bahrain",LOCALE_LANGUAGE_AR,LOCALE_REGION_BH,COUNTRY_GEO_NULL,TIME_ZONE_KUWAIT,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_BANGLADESH,"Bangladesh",LOCALE_LANGUAGE_EN,LOCALE_REGION_BD,COUNTRY_GEO_NULL,TIME_ZONE_ASTANA,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_BARBADOS,"Barbados",LOCALE_LANGUAGE_EN,LOCALE_REGION_BB,COUNTRY_GEO_NULL,TIME_ZONE_ATLANTIC_TIME_BARBADOS,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_BELARUS,"Belarus",LOCALE_LANGUAGE_BE,LOCALE_REGION_BY,COUNTRY_GEO_NULL,TIME_ZONE_MINSK,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_BELGIUM,"Belgium",LOCALE_LANGUAGE_FR,LOCALE_REGION_BE,COUNTRY_GEO_NULL,TIME_ZONE_BRUSSELS,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_BOLIVIA,"Bolivia",LOCALE_LANGUAGE_ES,LOCALE_REGION_BO,COUNTRY_GEO_NULL,TIME_ZONE_SANTIAGO,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_BOSNIA_AND_HERZEGOVINA,"Bosnia and Herzegovina",LOCALE_LANGUAGE_SR,LOCALE_REGION_BA,COUNTRY_GEO_NULL,TIME_ZONE_SARAJEVO,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_BOTSWANA,"Botswana",LOCALE_LANGUAGE_EN,LOCALE_REGION_BW,COUNTRY_GEO_NULL,TIME_ZONE_HARARE,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_BRAZIL,"Brazil",LOCALE_LANGUAGE_PT,LOCALE_REGION_BR,COUNTRY_GEO_NULL,TIME_ZONE_BRASILIA,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_BULGARIA,"Bulgaria",LOCALE_LANGUAGE_BG,LOCALE_REGION_BG,COUNTRY_GEO_NULL,TIME_ZONE_ATHENS_ISTANBUL,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_CANADA,"Canada",LOCALE_LANGUAGE_EN,LOCALE_REGION_CA,COUNTRY_GEO_NULL,TIME_ZONE_NEWFOUNDLAND,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_CHILE,"Chile",LOCALE_LANGUAGE_ES,LOCALE_REGION_CL,COUNTRY_GEO_NULL,TIME_ZONE_SANTIAGO,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_CHINA,"China",LOCALE_LANGUAGE_ZH,LOCALE_REGION_CN,COUNTRY_GEO_NULL,TIME_ZONE_BEIJING,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_COLOMBIA,"Colombia",LOCALE_LANGUAGE_ES,LOCALE_REGION_CO,COUNTRY_GEO_NULL,TIME_ZONE_BOGOTA,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_COTE_D_IVOIRE,"Cote d'Ivoire",LOCALE_LANGUAGE_FR,LOCALE_REGION_CI,COUNTRY_GEO_NULL,TIME_ZONE_LONDON_DUBLIN,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_CROATIA,"Croatia",LOCALE_LANGUAGE_HR,LOCALE_REGION_HR,COUNTRY_GEO_NULL,TIME_ZONE_BELGRADE,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_CYPRUS,"Cyprus",LOCALE_LANGUAGE_EN,LOCALE_REGION_CY,COUNTRY_GEO_NULL,TIME_ZONE_BEIRUT_LEBANON,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_CZECH_REPUBLIC,"Czech Republic",LOCALE_LANGUAGE_CS,LOCALE_REGION_CZ,COUNTRY_GEO_NULL,TIME_ZONE_BRUSSELS,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_DENMARK,"Denmark",LOCALE_LANGUAGE_DA,LOCALE_REGION_DK,COUNTRY_GEO_NULL,TIME_ZONE_BRUSSELS,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_ECUADOR,"Ecuador",LOCALE_LANGUAGE_ES,LOCALE_REGION_EC,COUNTRY_GEO_NULL,TIME_ZONE_MEXICO_CITY,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_EGYPT,"Egypt",LOCALE_LANGUAGE_AR,LOCALE_REGION_EG,COUNTRY_GEO_NULL,TIME_ZONE_CAIRO,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_ESTONIA,"Estonia",LOCALE_LANGUAGE_ET,LOCALE_REGION_EE,COUNTRY_GEO_NULL,TIME_ZONE_HELSINKI,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_FINLAND,"Finland",LOCALE_LANGUAGE_FI,LOCALE_REGION_FI,COUNTRY_GEO_NULL,TIME_ZONE_HELSINKI,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_FRANCE_INC_GUADELOUPE,"France (inc Guadeloupe)",LOCALE_LANGUAGE_FR,LOCALE_REGION_FR,COUNTRY_GEO_NULL,TIME_ZONE_BRUSSELS,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_GEORGIA,"Georgia",LOCALE_LANGUAGE_RU,LOCALE_REGION_GE,COUNTRY_GEO_NULL,TIME_ZONE_TBILISI,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_GERMANY,"Germany",LOCALE_LANGUAGE_DE,LOCALE_REGION_DE,COUNTRY_GEO_NULL,TIME_ZONE_BRUSSELS,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_GREECE,"Greece",LOCALE_LANGUAGE_EL,LOCALE_REGION_GR,COUNTRY_GEO_NULL,TIME_ZONE_ATHENS_ISTANBUL,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_HAITI,"Haiti",LOCALE_LANGUAGE_FR,LOCALE_REGION_HT,COUNTRY_GEO_NULL,TIME_ZONE_BOGOTA,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_HONDURAS,"Honduras",LOCALE_LANGUAGE_ES,LOCALE_REGION_HN,COUNTRY_GEO_NULL,TIME_ZONE_CENTRAL_AMERICA,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_HONG_KONG,"Hong Kong",LOCALE_LANGUAGE_ZH,LOCALE_REGION_HK,COUNTRY_GEO_NULL,TIME_ZONE_HONG_KONG,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_HUNGARY,"Hungary",LOCALE_LANGUAGE_HU,LOCALE_REGION_HU,COUNTRY_GEO_NULL,TIME_ZONE_BELGRADE,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_ICELAND,"Iceland",LOCALE_LANGUAGE_EN,LOCALE_REGION_IS,COUNTRY_GEO_NULL,TIME_ZONE_LONDON_DUBLIN,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_INDIA,"India en_US",LOCALE_LANGUAGE_EN,LOCALE_REGION_IN,COUNTRY_GEO_NULL,TIME_ZONE_KOLKATA,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_INDONESIA,"Indonesia",LOCALE_LANGUAGE_IN,LOCALE_REGION_ID,COUNTRY_GEO_NULL,TIME_ZONE_HONG_KONG,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_IRELAND,"Ireland",LOCALE_LANGUAGE_EN,LOCALE_REGION_IE,COUNTRY_GEO_NULL,TIME_ZONE_LONDON_DUBLIN,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_ISRAEL,"Israel iw",LOCALE_LANGUAGE_IW,LOCALE_REGION_IL,COUNTRY_GEO_NULL,TIME_ZONE_JERUSALEM,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_ITALY,"Italy",LOCALE_LANGUAGE_IT,LOCALE_REGION_IT,COUNTRY_GEO_NULL,TIME_ZONE_BRUSSELS,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_JAMAICA,"Jamaica",LOCALE_LANGUAGE_EN,LOCALE_REGION_JM,COUNTRY_GEO_NULL,TIME_ZONE_EASTERN_TIME,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_JAPAN,"Japan",LOCALE_LANGUAGE_JA,LOCALE_REGION_JP,COUNTRY_GEO_NULL,TIME_ZONE_TOKYO_OSAKA,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_JORDAN,"Jordan",LOCALE_LANGUAGE_AR,LOCALE_REGION_JO,COUNTRY_GEO_NULL,TIME_ZONE_AMMAN_JORDAN,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_KAZAKHSTAN,"Kazakhstan",LOCALE_LANGUAGE_RU,LOCALE_REGION_KZ,COUNTRY_GEO_NULL,TIME_ZONE_MOSCOW,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_KENYA,"Kenya",LOCALE_LANGUAGE_SW,LOCALE_REGION_KE,COUNTRY_GEO_NULL,TIME_ZONE_NAIROBI,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_KOREA_SOUTH,"Korea (South)",LOCALE_LANGUAGE_KO,LOCALE_REGION_KR,COUNTRY_GEO_NULL,TIME_ZONE_SEOUL,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_KUWAIT,"Kuwait",LOCALE_LANGUAGE_AR,LOCALE_REGION_KW,COUNTRY_GEO_NULL,TIME_ZONE_KUWAIT,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_LATVIA,"Latvia",LOCALE_LANGUAGE_LV,LOCALE_REGION_LV,COUNTRY_GEO_NULL,TIME_ZONE_MINSK,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_LEBANON,"Lebanon",LOCALE_LANGUAGE_AR,LOCALE_REGION_LB,COUNTRY_GEO_NULL,TIME_ZONE_BEIRUT_LEBANON,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_LITHUANIA,"Lithuania",LOCALE_LANGUAGE_LT,LOCALE_REGION_LT,COUNTRY_GEO_NULL,TIME_ZONE_MINSK,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_LUXEMBOURG,"Luxembourg",LOCALE_LANGUAGE_FR,LOCALE_REGION_LU,COUNTRY_GEO_NULL,TIME_ZONE_BRUSSELS,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_MACEDONIA,"Macedonia",LOCALE_LANGUAGE_EN,LOCALE_REGION_MK,COUNTRY_GEO_NULL,TIME_ZONE_AMSTERDAM_BERLIN,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_MALAYSIA,"Malaysia",LOCALE_LANGUAGE_MS,LOCALE_REGION_MY,COUNTRY_GEO_NULL,TIME_ZONE_KUALA_LUMPUR,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_MEXICO,"Mexico",LOCALE_LANGUAGE_ES,LOCALE_REGION_MX,COUNTRY_GEO_NULL,TIME_ZONE_CHIHUAHUA,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_MOLDOVA,"Moldova",LOCALE_LANGUAGE_RU,LOCALE_REGION_MD,COUNTRY_GEO_NULL,TIME_ZONE_ATHENS_ISTANBUL,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_MOROCCO,"Morocco",LOCALE_LANGUAGE_AR,LOCALE_REGION_MA,COUNTRY_GEO_NULL,TIME_ZONE_CASABLANCA,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_NEPAL,"Nepal",LOCALE_LANGUAGE_EN,LOCALE_REGION_NP,COUNTRY_GEO_NULL,TIME_ZONE_KATHMANDU,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_NETHERLAND_ANTILLES,"Netherland Antilles",LOCALE_LANGUAGE_NL,LOCALE_REGION_AN,COUNTRY_GEO_NULL,TIME_ZONE_SANTIAGO,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_NETHERLANDS_INC_BONAIRE,"Netherlands (inc Bonn) nl",LOCALE_LANGUAGE_NL,LOCALE_REGION_NL,COUNTRY_GEO_NULL,TIME_ZONE_AMSTERDAM_BERLIN,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_NEW_ZEALAND,"New Zealand",LOCALE_LANGUAGE_EN,LOCALE_REGION_NZ,COUNTRY_GEO_NULL,TIME_ZONE_AUCKLAND,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_NIGERIA,"Nigeria",LOCALE_LANGUAGE_EN,LOCALE_REGION_NG,COUNTRY_GEO_NULL,TIME_ZONE_WINDHOEK,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_NORWAY,"Norway",LOCALE_LANGUAGE_NO,LOCALE_REGION_NO,COUNTRY_GEO_NULL,TIME_ZONE_AMSTERDAM_BERLIN,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_OMAN,"Oman",LOCALE_LANGUAGE_AR,LOCALE_REGION_OM,COUNTRY_GEO_NULL,TIME_ZONE_DUBAI,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_PAKISTAN,"Pakistan",LOCALE_LANGUAGE_EN,LOCALE_REGION_PK,COUNTRY_GEO_NULL,TIME_ZONE_ISLAMABAD_KARACHI,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_PARAGUAY,"Paraguay",LOCALE_LANGUAGE_ES,LOCALE_REGION_PY,COUNTRY_GEO_NULL,TIME_ZONE_SANTIAGO,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_PERU,"Peru",LOCALE_LANGUAGE_ES,LOCALE_REGION_PE,COUNTRY_GEO_NULL,TIME_ZONE_EASTERN_TIME,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_PHILIPPINES,"Philippines",LOCALE_LANGUAGE_TL,LOCALE_REGION_PH,COUNTRY_GEO_NULL,TIME_ZONE_KUALA_LUMPUR,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_POLAND,"Poland",LOCALE_LANGUAGE_PL,LOCALE_REGION_PL,COUNTRY_GEO_NULL,TIME_ZONE_BELGRADE,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_PORTUGAL,"Portugal",LOCALE_LANGUAGE_PT,LOCALE_REGION_PT,COUNTRY_GEO_NULL,TIME_ZONE_LONDON_DUBLIN,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_QATAR,"Qatar",LOCALE_LANGUAGE_AR,LOCALE_REGION_QA,COUNTRY_GEO_NULL,TIME_ZONE_MOSCOW,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_ROMANIA,"Romania",LOCALE_LANGUAGE_RO,LOCALE_REGION_RO,COUNTRY_GEO_NULL,TIME_ZONE_HELSINKI,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_RUSSIA,"Russia",LOCALE_LANGUAGE_RU,LOCALE_REGION_RU,COUNTRY_GEO_NULL,TIME_ZONE_VLADIVOSTOK,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_SAUDI_ARABIA,"Saudi Arabia",LOCALE_LANGUAGE_AR,LOCALE_REGION_SA,COUNTRY_GEO_NULL,TIME_ZONE_KUWAIT,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_SERBIA,"Serbia",LOCALE_LANGUAGE_SR,LOCALE_REGION_CS,COUNTRY_GEO_NULL,TIME_ZONE_BELGRADE,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_SINGAPORE,"Singapore",LOCALE_LANGUAGE_EN,LOCALE_REGION_SG,COUNTRY_GEO_NULL,TIME_ZONE_HONG_KONG,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_SLOVAKIA,"Slovakia",LOCALE_LANGUAGE_SK,LOCALE_REGION_SK,COUNTRY_GEO_NULL,TIME_ZONE_AMSTERDAM_BERLIN,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_SLOVENIA,"Slovenia",LOCALE_LANGUAGE_SL,LOCALE_REGION_SI,COUNTRY_GEO_NULL,TIME_ZONE_AMSTERDAM_BERLIN,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_SOUTH_AFRICA,"South Africa",LOCALE_LANGUAGE_EN,LOCALE_REGION_ZA,COUNTRY_GEO_NULL,TIME_ZONE_CAIRO,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_SPAIN,"Spain",LOCALE_LANGUAGE_ES,LOCALE_REGION_ES,COUNTRY_GEO_NULL,TIME_ZONE_AMSTERDAM_BERLIN,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_SRI_LANKA,"Sri Lanka",LOCALE_LANGUAGE_EN,LOCALE_REGION_LK,COUNTRY_GEO_NULL,TIME_ZONE_SRI_LANKA,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_SWEDEN,"Sweden",LOCALE_LANGUAGE_SV,LOCALE_REGION_SE,COUNTRY_GEO_NULL,TIME_ZONE_AMSTERDAM_BERLIN,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_SWITZERLAND,"Switzerland",LOCALE_LANGUAGE_DE,LOCALE_REGION_CH,COUNTRY_GEO_NULL,TIME_ZONE_AMSTERDAM_BERLIN,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_TAIWAN,"Taiwan",LOCALE_LANGUAGE_ZH,LOCALE_REGION_TW,COUNTRY_GEO_NULL,TIME_ZONE_TAIPEI,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_THAILAND,"Thailand",LOCALE_LANGUAGE_TH,LOCALE_REGION_TH,COUNTRY_GEO_NULL,TIME_ZONE_BANGKOK,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_TRINIDAD_TOBAGO,"Trinidad Tobago",LOCALE_LANGUAGE_EN,LOCALE_REGION_TT,COUNTRY_GEO_NULL,TIME_ZONE_MANAUS,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_TUNISIA,"Tunisia",LOCALE_LANGUAGE_AR,LOCALE_REGION_TN,COUNTRY_GEO_NULL,TIME_ZONE_WINDHOEK,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_TURKEY,"Turkey",LOCALE_LANGUAGE_TR,LOCALE_REGION_TR,COUNTRY_GEO_NULL,TIME_ZONE_JERUSALEM,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_TURKMENISTAN,"Turkmenistan",LOCALE_LANGUAGE_RU,LOCALE_REGION_TM,COUNTRY_GEO_NULL,TIME_ZONE_ISLAMABAD_KARACHI,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_UGANDA,"Uganda",LOCALE_LANGUAGE_EN,LOCALE_REGION_UG,COUNTRY_GEO_NULL,TIME_ZONE_TEHRAN,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_UKRAINE,"Ukraine",LOCALE_LANGUAGE_UK,LOCALE_REGION_UA,COUNTRY_GEO_NULL,TIME_ZONE_ATHENS_ISTANBUL,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_UNITED_KINGDOM,"United Kingdom",LOCALE_LANGUAGE_EN,LOCALE_REGION_GB,COUNTRY_GEO_NULL,TIME_ZONE_LONDON_DUBLIN,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_UNITED_STATES,"United States",LOCALE_LANGUAGE_EN,LOCALE_REGION_US,COUNTRY_GEO_NULL,TIME_ZONE_ARIZONA,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_URUGUAY,"Uruguay",LOCALE_LANGUAGE_ES,LOCALE_REGION_UY,COUNTRY_GEO_NULL,TIME_ZONE_MONTEVIDEO,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_UZBEKISTAN,"Uzbekistan",LOCALE_LANGUAGE_RU,LOCALE_REGION_UZ,COUNTRY_GEO_NULL,TIME_ZONE_YEKATERINBURG,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_VENEZUELA,"Venezuela",LOCALE_LANGUAGE_ES,LOCALE_REGION_VE,COUNTRY_GEO_NULL,TIME_ZONE_VENEZUELA,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_VIETNAM,"Vietnam",LOCALE_LANGUAGE_VI,LOCALE_REGION_VN,COUNTRY_GEO_NULL,TIME_ZONE_BANGKOK,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_NORDICS,"Nordics",LOCALE_LANGUAGE_EN,LOCALE_REGION_SE,COUNTRY_GEO_NULL,TIME_ZONE_AMSTERDAM_BERLIN,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_BALTIC,"Baltic",LOCALE_LANGUAGE_EN,LOCALE_REGION_LT,COUNTRY_GEO_NULL,TIME_ZONE_MINSK,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_CZECH_SLOVAKIA,"Czech-Slovakia",LOCALE_LANGUAGE_EN,LOCALE_REGION_CZ,COUNTRY_GEO_NULL,TIME_ZONE_BRUSSELS,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_CROATIA_SLOVENIA,"Croatia-Slovenia",LOCALE_LANGUAGE_EN,LOCALE_REGION_HR,COUNTRY_GEO_NULL,TIME_ZONE_BELGRADE,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_LA_GROUP,"LA Group",LOCALE_LANGUAGE_ES,LOCALE_REGION_BO,COUNTRY_GEO_NULL,TIME_ZONE_SANTIAGO,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_UNITED_ARAB_EMIRATES,"UAE ar",LOCALE_LANGUAGE_EN,LOCALE_REGION_BH,COUNTRY_GEO_NULL,TIME_ZONE_KUWAIT,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_EMAT_UK,"EMAT-UK",LOCALE_LANGUAGE_EN,LOCALE_REGION_KE,COUNTRY_GEO_NULL,TIME_ZONE_NAIROBI,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_EMAT_FR,"EMAT-FR",LOCALE_LANGUAGE_FR,LOCALE_REGION_CI,COUNTRY_GEO_NULL,TIME_ZONE_LONDON_DUBLIN,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_EMAT_PO,"EMAT-PO",LOCALE_LANGUAGE_PT,LOCALE_REGION_AO,COUNTRY_GEO_NULL,TIME_ZONE_WINDHOEK,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_INDIA_HI,"India hi",LOCALE_LANGUAGE_EN,LOCALE_REGION_IN,COUNTRY_GEO_NULL,TIME_ZONE_KOLKATA,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_UAE_EN,"UAE en",LOCALE_LANGUAGE_EN,LOCALE_REGION_BH,COUNTRY_GEO_NULL,TIME_ZONE_KUWAIT,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_ISRAEL_AR,"Israel ar",LOCALE_LANGUAGE_IW,LOCALE_REGION_IL,COUNTRY_GEO_NULL,TIME_ZONE_JERUSALEM,USER_DEFINE_NULL},\r
- {DEVICE_TYPE_AREA,AREA_ID_NETHERLANDS_INC_BONAIRE_ENUS,"Netherlands(inc Bonn) en_US",LOCALE_LANGUAGE_NL,LOCALE_REGION_NL,COUNTRY_GEO_NULL,TIME_ZONE_AMSTERDAM_BERLIN,USER_DEFINE_NULL},\r
-};\r
-\r
-\r
-static int board_id_init_data(struct board_id_private_data *board_id)\r
-{\r
- int result = 0;\r
- \r
- memcpy(board_id->area_area_id_name, area_area_id_name, sizeof(area_area_id_name)); \r
- memcpy(board_id->area_operator_id_name, area_operator_id_name, sizeof(area_operator_id_name));\r
- memcpy(board_id->area_reserve_id_name, area_reserve_id_name, sizeof(area_reserve_id_name));\r
- memcpy(board_id->tp_id_name, tp_id_name, sizeof(tp_id_name));\r
- memcpy(board_id->lcd_id_name, lcd_id_name, sizeof(lcd_id_name));\r
- memcpy(board_id->key_id_name, key_id_name, sizeof(key_id_name));\r
- memcpy(board_id->codec_id_name, codec_id_name, sizeof(codec_id_name));\r
- memcpy(board_id->wifi_id_name, wifi_id_name, sizeof(wifi_id_name));\r
- memcpy(board_id->bt_id_name, bt_id_name, sizeof(bt_id_name)); \r
- memcpy(board_id->gps_id_name, gps_id_name, sizeof(gps_id_name));\r
- memcpy(board_id->fm_id_name, fm_id_name, sizeof(fm_id_name));\r
- memcpy(board_id->modem_id_name, modem_id_name, sizeof(modem_id_name)); \r
- memcpy(board_id->ddr_id_name, ddr_id_name, sizeof(ddr_id_name));\r
- memcpy(board_id->flash_id_name, flash_id_name, sizeof(flash_id_name));\r
- memcpy(board_id->hdmi_id_name, hdmi_id_name, sizeof(hdmi_id_name));\r
- memcpy(board_id->battery_id_name, battery_id_name, sizeof(battery_id_name));\r
- memcpy(board_id->charge_id_name, charge_id_name, sizeof(charge_id_name)); \r
- memcpy(board_id->backlight_id_name, backlight_id_name, sizeof(backlight_id_name));\r
- memcpy(board_id->headset_id_name, headset_id_name, sizeof(headset_id_name));\r
- memcpy(board_id->micphone_id_name, micphone_id_name, sizeof(micphone_id_name));\r
- memcpy(board_id->speaker_id_name, speaker_id_name, sizeof(speaker_id_name));\r
- memcpy(board_id->vibrator_id_name, vibrator_id_name, sizeof(vibrator_id_name));\r
- memcpy(board_id->tv_id_name, tv_id_name, sizeof(tv_id_name)); \r
- memcpy(board_id->echip_id_name, echip_id_name, sizeof(echip_id_name)); \r
- memcpy(board_id->hub_id_name, hub_id_name, sizeof(hub_id_name));\r
- memcpy(board_id->tpad_id_name, tpad_id_name, sizeof(tpad_id_name));\r
- \r
- memcpy(board_id->pmic_id_name, pmic_id_name, sizeof(pmic_id_name));\r
- memcpy(board_id->regulator_id_name, regulator_id_name, sizeof(regulator_id_name));\r
- memcpy(board_id->rtc_id_name, rtc_id_name, sizeof(rtc_id_name));\r
- memcpy(board_id->camera_front_id_name, camera_front_id_name, sizeof(camera_front_id_name));\r
- memcpy(board_id->camera_back_id_name, camera_back_id_name, sizeof(camera_back_id_name)); \r
- memcpy(board_id->sensor_angle_id_name, sensor_angle_id_name, sizeof(sensor_angle_id_name));\r
- memcpy(board_id->sensor_accel_id_name, sensor_accel_id_name, sizeof(sensor_accel_id_name));\r
- memcpy(board_id->sensor_compass_id_name, sensor_compass_id_name, sizeof(sensor_compass_id_name));\r
- memcpy(board_id->sensor_gyroscope_id_name, sensor_gyroscope_id_name, sizeof(sensor_gyroscope_id_name));\r
- memcpy(board_id->sensor_light_id_name, sensor_light_id_name, sizeof(sensor_light_id_name));\r
- memcpy(board_id->sensor_proximity_id_name, sensor_proximity_id_name, sizeof(sensor_proximity_id_name));\r
- memcpy(board_id->sensor_temperature_id_name, sensor_temperature_id_name, sizeof(sensor_temperature_id_name)); \r
- memcpy(board_id->sensor_pressure_id_name, sensor_pressure_id_name, sizeof(sensor_pressure_id_name));\r
-\r
- board_id->device_start_addr[DEVICE_TYPE_TP] = board_id->tp_id_name;\r
- board_id->device_start_addr[DEVICE_TYPE_LCD] = board_id->lcd_id_name; \r
- board_id->device_start_addr[DEVICE_TYPE_KEY] = board_id->key_id_name; \r
- board_id->device_start_addr[DEVICE_TYPE_CODEC] = board_id->codec_id_name;\r
- board_id->device_start_addr[DEVICE_TYPE_WIFI] = board_id->wifi_id_name;\r
- board_id->device_start_addr[DEVICE_TYPE_BT] = board_id->bt_id_name; \r
- board_id->device_start_addr[DEVICE_TYPE_GPS] = board_id->gps_id_name; \r
- board_id->device_start_addr[DEVICE_TYPE_FM] = board_id->fm_id_name; \r
- board_id->device_start_addr[DEVICE_TYPE_MODEM] = board_id->modem_id_name; \r
- board_id->device_start_addr[DEVICE_TYPE_DDR] = board_id->ddr_id_name;\r
- board_id->device_start_addr[DEVICE_TYPE_FLASH] = board_id->flash_id_name;\r
- board_id->device_start_addr[DEVICE_TYPE_HDMI] = board_id->hdmi_id_name;\r
- board_id->device_start_addr[DEVICE_TYPE_BATTERY] = board_id->battery_id_name;\r
- board_id->device_start_addr[DEVICE_TYPE_CHARGE] = board_id->charge_id_name; \r
- board_id->device_start_addr[DEVICE_TYPE_BACKLIGHT] = board_id->backlight_id_name;\r
- board_id->device_start_addr[DEVICE_TYPE_HEADSET] = board_id->headset_id_name;\r
- board_id->device_start_addr[DEVICE_TYPE_MICPHONE] = board_id->micphone_id_name;\r
- board_id->device_start_addr[DEVICE_TYPE_SPEAKER] = board_id->speaker_id_name;\r
- board_id->device_start_addr[DEVICE_TYPE_VIBRATOR] = board_id->vibrator_id_name;\r
- board_id->device_start_addr[DEVICE_TYPE_TV] = board_id->tv_id_name;\r
- board_id->device_start_addr[DEVICE_TYPE_ECHIP] = board_id->echip_id_name;\r
- board_id->device_start_addr[DEVICE_TYPE_HUB] = board_id->hub_id_name;\r
- board_id->device_start_addr[DEVICE_TYPE_TPAD] = board_id->tpad_id_name;\r
- \r
- board_id->device_start_addr[DEVICE_TYPE_PMIC] = board_id->pmic_id_name;\r
- board_id->device_start_addr[DEVICE_TYPE_REGULATOR] = board_id->regulator_id_name;\r
- board_id->device_start_addr[DEVICE_TYPE_RTC] = board_id->rtc_id_name;\r
- board_id->device_start_addr[DEVICE_TYPE_CAMERA_FRONT] = board_id->camera_front_id_name;\r
- board_id->device_start_addr[DEVICE_TYPE_CAMERA_BACK] = board_id->camera_back_id_name; \r
- board_id->device_start_addr[DEVICE_TYPE_ANGLE] = board_id->sensor_angle_id_name;\r
- board_id->device_start_addr[DEVICE_TYPE_ACCEL] = board_id->sensor_accel_id_name;\r
- board_id->device_start_addr[DEVICE_TYPE_COMPASS] = board_id->sensor_compass_id_name;\r
- board_id->device_start_addr[DEVICE_TYPE_GYRO] = board_id->sensor_gyroscope_id_name;\r
- board_id->device_start_addr[DEVICE_TYPE_LIGHT] = board_id->sensor_light_id_name;\r
- board_id->device_start_addr[DEVICE_TYPE_PROXIMITY] = board_id->sensor_proximity_id_name;\r
- board_id->device_start_addr[DEVICE_TYPE_TEMPERATURE] = board_id->sensor_temperature_id_name; \r
- board_id->device_start_addr[DEVICE_TYPE_PRESSURE] = board_id->sensor_pressure_id_name;\r
-\r
-\r
- board_id->device_num_max[DEVICE_TYPE_TP] = TP_ID_NUMS;\r
- board_id->device_num_max[DEVICE_TYPE_LCD] = LCD_ID_NUMS; \r
- board_id->device_num_max[DEVICE_TYPE_KEY] = KEY_ID_NUMS; \r
- board_id->device_num_max[DEVICE_TYPE_CODEC] = CODEC_ID_NUMS;\r
- board_id->device_num_max[DEVICE_TYPE_WIFI] = WIFI_ID_NUMS;\r
- board_id->device_num_max[DEVICE_TYPE_BT] = BT_ID_NUMS; \r
- board_id->device_num_max[DEVICE_TYPE_GPS] = GPS_ID_NUMS; \r
- board_id->device_num_max[DEVICE_TYPE_FM] = FM_ID_NUMS; \r
- board_id->device_num_max[DEVICE_TYPE_MODEM] = MODEM_ID_NUMS; \r
- board_id->device_num_max[DEVICE_TYPE_DDR] = DDR_ID_NUMS;\r
- board_id->device_num_max[DEVICE_TYPE_FLASH] = FLASH_ID_NUMS;\r
- board_id->device_num_max[DEVICE_TYPE_HDMI] = HDMI_ID_NUMS;\r
- board_id->device_num_max[DEVICE_TYPE_BATTERY] = BATTERY_ID_NUMS;\r
- board_id->device_num_max[DEVICE_TYPE_CHARGE] = CHARGE_ID_NUMS; \r
- board_id->device_num_max[DEVICE_TYPE_BACKLIGHT] = BACKLIGHT_ID_NUMS;\r
- board_id->device_num_max[DEVICE_TYPE_HEADSET] = HEADSET_ID_NUMS;\r
- board_id->device_num_max[DEVICE_TYPE_MICPHONE] = MICPHONE_ID_NUMS;\r
- board_id->device_num_max[DEVICE_TYPE_SPEAKER] = SPEAKER_ID_NUMS;\r
- board_id->device_num_max[DEVICE_TYPE_VIBRATOR] = VIBRATOR_ID_NUMS;\r
- board_id->device_num_max[DEVICE_TYPE_TV] = TV_ID_NUMS;\r
- board_id->device_num_max[DEVICE_TYPE_ECHIP] = ECHIP_ID_NUMS;\r
- board_id->device_num_max[DEVICE_TYPE_HUB] = HUB_ID_NUMS;\r
- board_id->device_num_max[DEVICE_TYPE_TPAD] = TPAD_ID_NUMS;\r
- \r
- board_id->device_num_max[DEVICE_TYPE_PMIC] = PMIC_ID_NUMS;\r
- board_id->device_num_max[DEVICE_TYPE_REGULATOR] = REGULATOR_ID_NUMS;\r
- board_id->device_num_max[DEVICE_TYPE_RTC] = RTC_ID_NUMS;\r
- board_id->device_num_max[DEVICE_TYPE_CAMERA_FRONT] = CAMERA_FRONT_ID_NUMS;\r
- board_id->device_num_max[DEVICE_TYPE_CAMERA_BACK] = CAMERA_BACK_ID_NUMS; \r
- board_id->device_num_max[DEVICE_TYPE_ANGLE] = ANGLE_ID_NUMS;\r
- board_id->device_num_max[DEVICE_TYPE_ACCEL] = ACCEL_ID_NUMS;\r
- board_id->device_num_max[DEVICE_TYPE_COMPASS] = COMPASS_ID_NUMS;\r
- board_id->device_num_max[DEVICE_TYPE_GYRO] = GYRO_ID_NUMS;\r
- board_id->device_num_max[DEVICE_TYPE_LIGHT] = LIGHT_ID_NUMS;\r
- board_id->device_num_max[DEVICE_TYPE_PROXIMITY] = PROXIMITY_ID_NUMS;\r
- board_id->device_num_max[DEVICE_TYPE_TEMPERATURE] = TEMPERATURE_ID_NUMS; \r
- board_id->device_num_max[DEVICE_TYPE_PRESSURE] = PRESSURE_ID_NUMS;\r
- \r
- \r
- return result;\r
-\r
-}\r
-\r
-\r
-char board_id_get(enum type_devices type)\r
-{\r
- return g_board_id->device_selected[type].id;\r
-}\r
-EXPORT_SYMBOL_GPL(board_id_get);\r
-\r
-\r
-#include <asm/pgtable.h>\r
-static __init void rk30_get_vender_sector(u8 *buf)\r
-{\r
-#define RK30_NANDC_BASE IOMEM(0xFEC00000)\r
- u32 v, a;\r
- u32 flag = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ;\r
-\r
- a = (u32)pgd_val(pgd_offset_k((u32)RK30_NANDC_BASE));\r
- v = readl_relaxed(a);\r
- writel_relaxed(flag | ((RK30_NANDC_PHYS >> 20) << 20), a);\r
-\r
- memcpy(buf, RK30_NANDC_BASE + 0x1400 + 0x08, 0x200 - 0x08);\r
-\r
- writel_relaxed(v, a);\r
-}\r
-\r
-\r
-static __init void rk30_get_idb_sector(u8 *buf)\r
-{\r
-#define RK30_NANDC_BASE IOMEM(0xFEC00000)\r
- u32 v, a;\r
- u32 flag = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ;\r
-\r
- a = (u32)pgd_val(pgd_offset_k((u32)RK30_NANDC_BASE));\r
- v = readl_relaxed(a);\r
- writel_relaxed(flag | ((RK30_NANDC_PHYS >> 20) << 20), a);\r
-\r
- memcpy(buf, RK30_NANDC_BASE + 0x1600, 0x200);\r
-\r
- writel_relaxed(v, a);\r
-}\r
-\r
-static int board_id_vendor_data_check(char *pbuf)\r
-{\r
- int sum = 0;\r
- int i = 0;\r
- int temp = 0;\r
-\r
- //for(i=DEVICE_TYPE_NULL; i<DEVICE_NUM_TYPES; i++)\r
- //printk("buf[%d]=0x%x\n",i, pbuf[i]);\r
-\r
- temp = ((int)(pbuf[DEVICE_TYPE_SUM] << 24) | ((int)(pbuf[DEVICE_TYPE_SUM+1] << 16)) | ((int)(pbuf[DEVICE_TYPE_SUM+2] << 8)) | (int)(pbuf[DEVICE_TYPE_SUM+3]));\r
- \r
- for(i=DEVICE_TYPE_AREA; i<DEVICE_NUM_TYPES; i++)\r
- sum += pbuf[i];\r
-\r
- if((temp != sum) || (temp == 0) || (sum == 0))\r
- {\r
- printk("%s:sum=0x%x, temp=0x%x\n", __func__, sum, temp);\r
- return -1;\r
- }\r
-\r
- return 0;\r
-}\r
-\r
-int board_id_get_from_flash(char *pbuf, int type)\r
-{\r
- char sn_buf[512];\r
- char vendor_buf[504]; \r
- static char vendor_buf_temp[504];\r
- int i = 0;\r
-\r
- printk("%s:\n",__func__);\r
- memset(sn_buf,0,512); \r
- memset(vendor_buf,0,504); \r
- memset(vendor_buf_temp,0,504);\r
- if(type == BID_MM_IOMEM)\r
- {\r
- rk30_get_idb_sector(sn_buf);\r
- //print_hex_dump(KERN_INFO, "idb: ", DUMP_PREFIX_OFFSET, 16, 1, sn_buf, 0x200, true);\r
- rk30_get_vender_sector(vendor_buf_temp); \r
- //print_hex_dump(KERN_INFO, "idb: ", DUMP_PREFIX_OFFSET, 16, 1, vendor_buf_temp, 504, true);\r
- }\r
- else\r
- {\r
- GetSNSectorInfoBeforeNandInit(sn_buf);\r
- GetVendor0InfoBeforeNandInit(vendor_buf_temp);\r
- }\r
-\r
- printk("%s GUID:",__func__);\r
- for(i=480; i<496; i++)\r
- {\r
- printk("%02x",sn_buf[i]);\r
- if((i==483) || (i==485) || (i==487) || (i==489))\r
- printk("-");\r
- }\r
- printk("\n");\r
- \r
- \r
- memcpy(&vendor_buf[DEVICE_TYPE_SUM], vendor_buf_temp, 127-DEVICE_TYPE_AREA+1);\r
- \r
- if(!board_id_vendor_data_check(vendor_buf))\r
- {\r
- memcpy(pbuf, vendor_buf, DEVICE_NUM_TYPES);\r
-\r
- printk("%s:vendor data is valid\n",__func__);\r
- }\r
- else if(!board_id_vendor_data_check(sn_buf))\r
- {\r
- memcpy(pbuf, sn_buf, DEVICE_NUM_TYPES); \r
- \r
- printk("%s:idblock data is valid\n",__func__);\r
- }\r
- else\r
- {\r
- pbuf[DEVICE_TYPE_AREA] = AREA_ID_UNITED_STATES; \r
- pbuf[DEVICE_TYPE_OPERATOR] = (20000 >> 8); \r
- pbuf[DEVICE_TYPE_OPERATOR+1] = (20000 & 0xff); //no\r
- pbuf[DEVICE_TYPE_RESERVE] = 0; \r
- pbuf[DEVICE_TYPE_STATUS] = 0x01;\r
- \r
- pbuf[DEVICE_TYPE_TP] = TP_ID_EKTF2K; \r
- pbuf[DEVICE_TYPE_LCD] = LCD_ID_EDID_I2C;\r
- pbuf[DEVICE_TYPE_KEY] = KEY_ID_ENGLISH_US; \r
- pbuf[DEVICE_TYPE_CODEC] = CODEC_ID_RT5640;\r
- pbuf[DEVICE_TYPE_WIFI] = WIFI_ID_BCM;\r
- pbuf[DEVICE_TYPE_BT] = BT_ID_RFKILL; \r
- pbuf[DEVICE_TYPE_GPS] = GPS_ID_RK_HV5820;\r
- pbuf[DEVICE_TYPE_FM] = FM_ID_NULL;\r
- pbuf[DEVICE_TYPE_MODEM] = MODEM_ID_NULL; \r
- pbuf[DEVICE_TYPE_DDR] = DDR_ID_NULL;\r
- pbuf[DEVICE_TYPE_FLASH] = DDR_ID_NULL;\r
- pbuf[DEVICE_TYPE_HDMI] = HDMI_ID_CAT66121;\r
- pbuf[DEVICE_TYPE_BATTERY] = BATTERY_ID_BLUEBERRY;\r
- pbuf[DEVICE_TYPE_CHARGE] = CHARGE_ID_NULL;\r
- pbuf[DEVICE_TYPE_BACKLIGHT] = BACKLIGHT_ID_RK29;\r
- pbuf[DEVICE_TYPE_HEADSET] = HEADSET_ID_RK29;\r
- pbuf[DEVICE_TYPE_MICPHONE] = MICPHONE_ID_NULL;\r
- pbuf[DEVICE_TYPE_SPEAKER] = SPEAKER_ID_1W5;\r
- pbuf[DEVICE_TYPE_VIBRATOR] = VIBRATOR_ID_RK29;\r
- pbuf[DEVICE_TYPE_TV] = TV_ID_NULL; \r
- pbuf[DEVICE_TYPE_ECHIP] = ECHIP_ID_IT8561; \r
- pbuf[DEVICE_TYPE_HUB] = HUB_ID_USB4604;\r
- pbuf[DEVICE_TYPE_TPAD] = TPAD_ID_ELAN;\r
- \r
- pbuf[DEVICE_TYPE_PMIC] = PMIC_ID_NULL;\r
- pbuf[DEVICE_TYPE_REGULATOR] = REGULATOR_ID_NULL;\r
- pbuf[DEVICE_TYPE_RTC] = RTC_ID_HYM8563;\r
- pbuf[DEVICE_TYPE_CAMERA_FRONT] = CAMERA_FRONT_ID_NULL;\r
- pbuf[DEVICE_TYPE_CAMERA_BACK] = CAMERA_BACK_ID_NULL; \r
- pbuf[DEVICE_TYPE_ANGLE] = ANGLE_ID_NULL;\r
- pbuf[DEVICE_TYPE_ACCEL] = ACCEL_ID_NULL;\r
- pbuf[DEVICE_TYPE_COMPASS] = COMPASS_ID_NULL;\r
- pbuf[DEVICE_TYPE_GYRO] = GYRO_ID_NULL;\r
- pbuf[DEVICE_TYPE_LIGHT] = LIGHT_ID_NULL;\r
- pbuf[DEVICE_TYPE_PROXIMITY] = PROXIMITY_ID_NULL;\r
- pbuf[DEVICE_TYPE_TEMPERATURE] = TEMPERATURE_ID_NULL;\r
- pbuf[DEVICE_TYPE_PRESSURE] = PRESSURE_ID_NULL;\r
- \r
- printk("%s:vendor and idblock data is invalid,use default config\n",__func__);\r
- \r
- }\r
-\r
- return 0;\r
-\r
-}\r
-EXPORT_SYMBOL_GPL(board_id_get_from_flash);\r
-\r
-\r
-\r
-int __init board_id_resolve(struct board_id_private_data *board_id)\r
-{\r
- int result = 0;\r
- int i = 0, j=0;\r
- \r
- board_id_get_from_flash(board_id->vendor_data, BID_MM_IOREMAP);\r
- \r
- board_id->area_select = board_id->area_area_id_name[(unsigned)board_id->vendor_data[DEVICE_TYPE_AREA]];\r
-\r
- for(j=OPERATOR_ID_20000_NO_OPERATOR; j<OPERATOR_ID_NUMS; j++)\r
- {\r
- if(board_id->area_operator_id_name[j].id == ((int)(board_id->vendor_data[DEVICE_TYPE_OPERATOR] << 8) | (int)(board_id->vendor_data[DEVICE_TYPE_OPERATOR+1])))\r
- {\r
- board_id->operator_select = board_id->area_operator_id_name[j];\r
- break;\r
- }\r
- }\r
- \r
- board_id->reserve_select = board_id->area_reserve_id_name[(unsigned)board_id->vendor_data[DEVICE_TYPE_RESERVE]];\r
- \r
- printk("%s:area type=%d,id=%d,country_area=%s,locale_region=%s,locale_language=%s\n",__func__,board_id->area_select.type,board_id->area_select.id,board_id->area_select.country_area,board_id->area_select.locale_region, board_id->area_select.locale_language); \r
- //printk("%s:operator type=%d,id=%d,locale_region=%s,operator_name=%s\n",__func__,board_id->operator_select.type,board_id->operator_select.id,board_id->operator_select.locale_region, board_id->operator_select.operator_name);\r
- //printk("%s:reserve type=%d,id=%d,locale_region=%s,reserve_name=%s\n",__func__,board_id->reserve_select.type,board_id->reserve_select.id,board_id->reserve_select.locale_region,board_id->reserve_select.reserve_name);\r
- \r
- for(j=AREA_ID_NULL; j<AREA_ID_NUMS; j++)\r
- {\r
- if(board_id->area_area_id_name[j].id != j)\r
- printk("%s:type=%d, country_area=%s, id=%d != j=%d\n",__func__,board_id->area_area_id_name[j].type, board_id->area_area_id_name[j].country_area, board_id->area_area_id_name[j].id, j);\r
- }\r
- \r
- for(i=DEVICE_TYPE_TP; i<DEVICE_NUM_TYPES; i++)\r
- {\r
- board_id->device_selected[i] = board_id->device_start_addr[i][(unsigned)board_id->vendor_data[i]];\r
- \r
- if(board_id->device_selected[i].id != board_id->vendor_data[i])\r
- printk("%s:id error! device_selected[%d].id = %d, vendor_data[%d] =%d\n",__func__, i, board_id->device_selected[i].id, i, board_id->vendor_data[i]);\r
-\r
- for(j=0; j<board_id->device_num_max[i]; j++)\r
- {\r
- if(board_id->device_start_addr[i][j].id != j)\r
- printk("%s:warning type=%d, name=%s,id=%d != j=%d\n",__func__, board_id->device_start_addr[i][j].type, board_id->device_start_addr[i][j].type_name, board_id->device_start_addr[i][j].id, j);\r
- }\r
- \r
- //printk("buf[%d].id = %d,type=%s, dev=%s\n",i, board_id->device_selected[i].id, board_id->device_selected[i].type_name, board_id->device_selected[i].dev_name);\r
- }\r
- printk("\n");\r
- \r
- return result;\r
-}\r
-\r
-\r
-static int __init board_id_add_devices(struct board_id_private_data *board_id, struct board_device_table *device_table, int device_table_size)\r
-{ \r
- int num = 0;\r
- int i = 0, j=0, k=0;\r
- struct i2c_board_info *i2c_info_temp = NULL;\r
- struct spi_board_info *spi_info_temp = NULL;\r
- struct platform_device **devices = NULL;\r
- struct valid_invalid_name *valid_name = NULL;\r
- char *buf = board_id->vendor_data;\r
- struct device_id_name *device_id_name_start = board_id->tp_id_name;\r
-\r
- if(device_table[BOARD_DEVICE_TYPE_VALID].type == BOARD_DEVICE_TYPE_VALID)\r
- valid_name = (struct valid_invalid_name*)device_table[BOARD_DEVICE_TYPE_VALID].addr;\r
- \r
- for(num=0; num<device_table_size; num++)\r
- {\r
- switch(device_table[num].type)\r
- {\r
- case BOARD_DEVICE_TYPE_I2C:\r
- i2c_info_temp = (struct i2c_board_info *)device_table[num].addr;\r
- if(!i2c_info_temp)\r
- continue;\r
-\r
- \r
- for(i=0; i<device_table[num].size; i++)\r
- { \r
-\r
- \r
- #if 1\r
- for(j=0; j<device_table[BOARD_DEVICE_TYPE_VALID].size; j++)\r
- {\r
- \r
- if(!valid_name) break;\r
-\r
- if(!strcmp(i2c_info_temp[i].type, valid_name[j].name))\r
- {\r
- i2c_register_board_info(device_table[num].bus, &i2c_info_temp[i], 1);\r
- printk("%s:i2c%d_info[%d] name=%s valid always\n",__func__,device_table[num].bus, i, i2c_info_temp[i].type);\r
- continue;\r
- }\r
- }\r
-\r
- #endif\r
- for(j=DEVICE_TYPE_TP; j<DEVICE_NUM_TYPES; j++)\r
- { \r
- device_id_name_start = board_id->device_start_addr[j];\r
-\r
- for(k=0; k<board_id->device_num_max[j]; k++)\r
- {\r
- if(!device_id_name_start)\r
- {\r
- printk("%s:address is null,type=%d,id=%d\n",__func__, j, k);\r
- break;\r
- }\r
-\r
- if((device_id_name_start->type == j) && (buf[j] == device_id_name_start->id) && (!strcmp(i2c_info_temp[i].type, device_id_name_start->driver_name)))\r
- {\r
- i2c_register_board_info(device_table[num].bus, &i2c_info_temp[i], 1);\r
- printk("%s:i2c%d_info[%d] name=%s,type=%d,id=%d\n",__func__, device_table[num].bus, i, i2c_info_temp[i].type, device_id_name_start->type, device_id_name_start->id);\r
- }\r
-\r
- device_id_name_start++;\r
- }\r
-\r
- }\r
- \r
- \r
- }\r
- \r
- break;\r
-\r
- case BOARD_DEVICE_TYPE_SPI:\r
- spi_info_temp = (struct spi_board_info *)device_table[num].addr;\r
- if(!spi_info_temp)\r
- continue;\r
-\r
- \r
- for(i=0; i<device_table[num].size; i++)\r
- { \r
- \r
- for(j=0; j<device_table[BOARD_DEVICE_TYPE_VALID].size; j++)\r
- {\r
- \r
- if(!valid_name) break;\r
- \r
- if(!strcmp(spi_info_temp[i].modalias, valid_name[j].name))\r
- {\r
- spi_register_board_info(&spi_info_temp[i], 1);\r
- printk("%s:spi%d_info[%d] name=%s valid always\n",__func__, spi_info_temp[i].bus_num, i, spi_info_temp[i].modalias);\r
- continue;\r
- }\r
- }\r
-\r
- \r
- for(j=DEVICE_TYPE_TP; j<DEVICE_NUM_TYPES; j++)\r
- { \r
- device_id_name_start = board_id->device_start_addr[j];\r
-\r
- for(k=0; k<board_id->device_num_max[j]; k++)\r
- {\r
- if(!device_id_name_start)\r
- {\r
- printk("%s:address is null,type=%d,id=%d\n",__func__, j, k);\r
- break;\r
- }\r
-\r
- if((device_id_name_start->type == j) && (buf[j] == device_id_name_start->id) && (!strcmp(spi_info_temp[i].modalias, device_id_name_start->driver_name)))\r
- {\r
- spi_register_board_info(&spi_info_temp[i], 1);\r
- printk("%s:spi%d_info[%d] name=%s,type=%d,id=%d\n",__func__, spi_info_temp[i].bus_num, i, spi_info_temp[i].modalias, device_id_name_start->type, device_id_name_start->id);\r
- }\r
-\r
- device_id_name_start++;\r
- }\r
-\r
- }\r
- \r
- \r
- }\r
- \r
- break;\r
-\r
- case BOARD_DEVICE_TYPE_PLATFORM: \r
- devices = (struct platform_device**)(device_table[num].addr);\r
- if(!devices)\r
- continue;\r
- \r
- for(i=0; i<device_table[num].size; i++)\r
- {\r
-\r
- for(j=0; j<device_table[BOARD_DEVICE_TYPE_VALID].size; j++)\r
- { \r
- if(!valid_name) break;\r
- \r
- if(!strcmp(devices[i]->name, valid_name[j].name))\r
- {\r
- platform_add_devices(&devices[i], 1);\r
- printk("%s:devices[%d] name=%s valid always\n",__func__, i, devices[i]->name);\r
- continue;\r
- }\r
- }\r
-\r
-\r
- for(j=DEVICE_TYPE_TP; j<DEVICE_NUM_TYPES; j++)\r
- { \r
- device_id_name_start = board_id->device_start_addr[j];\r
- \r
- for(k=0; k<board_id->device_num_max[j]; k++)\r
- {\r
- if(!device_id_name_start)\r
- {\r
- printk("%s:address is null,type=%d,id=%d\n",__func__, j, k);\r
- break;\r
- }\r
-\r
- if((device_id_name_start->type == j) && (buf[j] == device_id_name_start->id) && (!strcmp(devices[i]->name, device_id_name_start->driver_name)))\r
- {\r
- platform_add_devices(&devices[i], 1);\r
- \r
- printk("%s:devices[%d] name=%s,type=%d, id=%d\n",__func__, i, devices[i]->name, device_id_name_start->type, device_id_name_start->id);\r
- \r
- }\r
-\r
- device_id_name_start++;\r
- }\r
-\r
- }\r
- }\r
-\r
- \r
- break;\r
- \r
- default:\r
- printk("%s:ignore type=%d\n",__func__, device_table[num].type);\r
- break;\r
- \r
- }\r
-\r
-\r
- }\r
-\r
- return 0;\r
-\r
-}\r
-\r
-\r
-\r
-static int __init board_id_probe(struct platform_device *pdev)\r
-{\r
- struct board_id_platform_data *pdata = pdev->dev.platform_data;\r
- struct board_id_private_data *board_id = NULL;\r
- int i = 0, result; \r
-\r
- if(!pdata)\r
- return -1;\r
- \r
- if(pdata->init_platform_hw)\r
- pdata->init_platform_hw();\r
- \r
- board_id = kzalloc(sizeof(struct board_id_private_data), GFP_KERNEL);\r
- if(board_id == NULL)\r
- {\r
- printk("%s:fail malloc board_id data\n",__func__);\r
- return -1;\r
- }\r
-\r
- result = board_id_init_data(board_id);\r
- if (result < 0) {\r
- printk("%s:copydata error\n",__func__);\r
- return result;\r
- }\r
-\r
- result = board_id_resolve(board_id);\r
- if (result < 0) {\r
- printk("%s:resolve boardid error\n",__func__);\r
- return result;\r
- }\r
-\r
- \r
- if(pdata->device_table && pdata->device_table_size)\r
- board_id_add_devices(board_id, pdata->device_table, pdata->device_table_size);\r
- \r
- board_id->pdata = pdata;\r
- board_id->dev = &pdev->dev;\r
- \r
- \r
- platform_set_drvdata(pdev, board_id); \r
- \r
- mutex_init(&board_id->operation_mutex); \r
- \r
- g_board_id = board_id;\r
- \r
- printk("%s:init success\n",__func__);\r
- return result;\r
-\r
-}\r
-\r
-int board_id_suspend(struct platform_device *pdev, pm_message_t state)\r
-{\r
- struct board_id_private_data *board_id = platform_get_drvdata(pdev);\r
- \r
- \r
- return 0;\r
-}\r
-\r
-int board_id_resume(struct platform_device *pdev)\r
-{\r
- struct board_id_private_data *board_id = platform_get_drvdata(pdev);\r
- \r
-\r
- return 0;\r
-}\r
-\r
-void board_id_shutdown(struct platform_device *pdev)\r
-{\r
- struct board_id_private_data *board_id = platform_get_drvdata(pdev);\r
-\r
- \r
-}\r
-\r
-static struct platform_driver board_id_driver = {\r
- //.shutdown = board_id_shutdown,\r
- .suspend = board_id_suspend,\r
- .resume = board_id_resume,\r
- .driver = {\r
- .name = "board_id",\r
- .owner = THIS_MODULE,\r
- },\r
-};\r
-\r
-static int __init board_id_init(void)\r
-{\r
- return platform_driver_probe(&board_id_driver, board_id_probe);\r
-}\r
-\r
-static void __exit board_id_exit(void)\r
-{\r
- platform_driver_unregister(&board_id_driver);\r
-}\r
-\r
-//arch_initcall_sync(board_id_init);\r
-arch_initcall(board_id_init);\r
-module_exit(board_id_exit);\r
-\r
-MODULE_AUTHOR("ROCKCHIP Corporation:lw@rock-chips.com");\r
-MODULE_DESCRIPTION("rockchip board id driver");\r
-MODULE_LICENSE("GPL");\r
-\r
+++ /dev/null
-/* linux/arch/arm/mach-rk30/clock.c
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/module.h>
-#include <linux/hardirq.h>
-#include <linux/delay.h>
-#include <mach/clock.h>
-#include <mach/dvfs.h>
-#include <linux/delay.h>
-
-#define CLOCK_PRINTK_DBG(fmt, args...) pr_debug(fmt, ## args);
-#define CLOCK_PRINTK_ERR(fmt, args...) pr_err(fmt, ## args);
-#define CLOCK_PRINTK_LOG(fmt, args...) pr_debug(fmt, ## args);
-
-/* Clock flags */
-/* bit 0 is free */
-#define RATE_FIXED (1 << 1) /* Fixed clock rate */
-#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */
-
-#define MHZ (1000*1000)
-#define KHZ (1000)
-
-static void __clk_recalc(struct clk *clk);
-static void __propagate_rate(struct clk *tclk);
-static void __clk_reparent(struct clk *child, struct clk *parent);
-
-static LIST_HEAD(clocks);
-static DEFINE_MUTEX(clocks_mutex);
-static DEFINE_SPINLOCK(clockfw_lock);
-static LIST_HEAD(root_clks);
-static void clk_notify(struct clk *clk, unsigned long msg,
- unsigned long old_rate, unsigned long new_rate);
-
-#define LOCK() do { WARN_ON(in_irq()); if (!irqs_disabled()) spin_lock_bh(&clockfw_lock); } while (0)
-#define UNLOCK() do { if (!irqs_disabled()) spin_unlock_bh(&clockfw_lock); } while (0)
-/**********************************************for clock data****************************************************/
-struct list_head *get_rk_clocks_head(void)
-{
- return &clocks;
-}
-
-static struct clk *def_ops_clk=NULL;
-
-void clk_register_default_ops_clk(struct clk *clk)
-{
- def_ops_clk=clk;
-}
-
-static struct clk *clk_default_get_parent(struct clk *clk)
-{
- if(def_ops_clk&&def_ops_clk->get_parent)
- return def_ops_clk->get_parent(clk);
- else return NULL;
-
-
-
-}
-static int clk_default_set_parent(struct clk *clk, struct clk *parent)
-{
- if(def_ops_clk&&def_ops_clk->set_parent)
- return def_ops_clk->set_parent(clk,parent);
- else
- return -EINVAL;
-}
-
-int __init clk_disable_unused(void)
-{
- struct clk *ck;
- list_for_each_entry(ck, &clocks, node) {
- if (ck->usecount > 0 || ck->mode == NULL || (ck->flags & IS_PD))
- continue;
- LOCK();
- clk_enable_nolock(ck);
- clk_disable_nolock(ck);
- UNLOCK();
- }
- return 0;
-}
-/**
- * recalculate_root_clocks - recalculate and propagate all root clocks
- *
- * Recalculates all root clocks (clocks with no parent), which if the
- * clock's .recalc is set correctly, should also propagate their rates.
- * Called at init.
- */
-void clk_recalculate_root_clocks_nolock(void)
-{
- struct clk *clkp;
-
- list_for_each_entry(clkp, &root_clks, sibling) {
- __clk_recalc(clkp);
- __propagate_rate(clkp);
- }
-}
-/*
-void clk_recalculate_root_clocks(void)
-{
- LOCK();
- clk_recalculate_root_clocks_nolock();
- UNLOCK();
-}*/
-
-/**
- * clk_preinit - initialize any fields in the struct clk before clk init
- * @clk: struct clk * to initialize
- *
- * Initialize any struct clk fields needed before normal clk initialization
- * can run. No return value.
- */
-int clk_register(struct clk *clk)
-{
- if (clk == NULL || IS_ERR(clk))
- return -EINVAL;
- //INIT_LIST_HEAD(&clk->sibling);
- INIT_LIST_HEAD(&clk->children);
-
- /*
- * trap out already registered clocks
- */
- if (clk->node.next || clk->node.prev)
- return 0;
-
- mutex_lock(&clocks_mutex);
- if (clk->get_parent)
- clk->parent = clk->get_parent(clk);
- else if (clk->parents)
- clk->parent =clk_default_get_parent(clk);
-
- if (clk->parent)
- list_add(&clk->sibling, &clk->parent->children);
- else
- list_add(&clk->sibling, &root_clks);
- list_add(&clk->node, &clocks);
- mutex_unlock(&clocks_mutex);
- return 0;
-}
-
-/************************************************************/
-static void __clk_recalc(struct clk *clk)
-{
- if (unlikely(clk->flags & RATE_FIXED))
- return;
- if (clk->recalc)
- clk->rate = clk->recalc(clk);
- else if (clk->parent)
- clk->rate = clk->parent->rate;
-}
-static void __clk_reparent(struct clk *child, struct clk *parent)
-{
- if (child->parent == parent)
- return;
- //CLOCK_PRINTK_DBG("%s reparent to %s (was %s)\n", child->name, parent->name, ((child->parent) ? child->parent->name : "NULL"));
-
- list_del_init(&child->sibling);
- if (parent)
- list_add(&child->sibling, &parent->children);
- child->parent = parent;
-}
-
-/* Propagate rate to children */
-static void __propagate_rate(struct clk *tclk)
-{
- struct clk *clkp;
-
- //CLOCK_PRINTK_DBG("propagate_rate clk %s\n",clkp->name);
-
- list_for_each_entry(clkp, &tclk->children, sibling) {
- __clk_recalc(clkp);
- __propagate_rate(clkp);
- }
- //CLOCK_PRINTK_DBG("propagate_rate clk %s end\n",clkp->name);
-}
-
-int clk_enable_nolock(struct clk *clk)
-{
- int ret = 0;
-
- if (clk->usecount == 0) {
- if (clk->parent) {
- ret = clk_enable_nolock(clk->parent);
- if (ret)
- return ret;
- }
-
- if (clk->notifier_count)
- clk_notify(clk, CLK_PRE_ENABLE, clk->rate, clk->rate);
- if (clk->mode)
- ret = clk->mode(clk, 1);
- if (clk->notifier_count)
- clk_notify(clk, ret ? CLK_ABORT_ENABLE : CLK_POST_ENABLE, clk->rate, clk->rate);
- if (ret) {
- if (clk->parent)
- clk_disable_nolock(clk->parent);
- return ret;
- }
- pr_debug("%s enabled\n", clk->name);
- }
- clk->usecount++;
-
- return ret;
-}
-
-void clk_disable_nolock(struct clk *clk)
-{
- if (clk->usecount == 0) {
- CLOCK_PRINTK_ERR(KERN_ERR "Trying disable clock %s with 0 usecount\n", clk->name);
- WARN_ON(1);
- return;
- }
- if (--clk->usecount == 0) {
- int ret = 0;
- if (clk->notifier_count)
- clk_notify(clk, CLK_PRE_DISABLE, clk->rate, clk->rate);
- if (clk->mode)
- ret = clk->mode(clk, 0);
- if (clk->notifier_count)
- clk_notify(clk, ret ? CLK_ABORT_DISABLE : CLK_POST_DISABLE, clk->rate, clk->rate);
- pr_debug("%s disabled\n", clk->name);
- if (ret == 0 && clk->parent)
- clk_disable_nolock(clk->parent);
- }
-}
-/* Given a clock and a rate apply a clock specific rounding function */
-long clk_round_rate_nolock(struct clk *clk, unsigned long rate)
-{
- if (clk->round_rate)
- return clk->round_rate(clk, rate);
-
- if (clk->flags & RATE_FIXED)
- CLOCK_PRINTK_ERR("clock: clk_round_rate called on fixed-rate clock %s\n", clk->name);
-
- return clk->rate;
-}
-int is_suport_round_rate(struct clk *clk)
-{
- return (clk->round_rate) ? 0:(-1);
-}
-
-int clk_set_rate_nolock(struct clk *clk, unsigned long rate)
-{
- int ret;
- unsigned long old_rate;
-
- if (rate == clk->rate)
- return 0;
- if (clk->flags & CONFIG_PARTICIPANT)
- return -EINVAL;
-
- if (!clk->set_rate)
- return -EINVAL;
-
- //CLOCK_PRINTK_LOG("**will set %s rate %lu\n", clk->name, rate);
-
- old_rate = clk->rate;
- if (clk->notifier_count)
- clk_notify(clk, CLK_PRE_RATE_CHANGE, old_rate, rate);
-
- ret = clk->set_rate(clk, rate);
-
- if (ret == 0) {
- __clk_recalc(clk);
- CLOCK_PRINTK_LOG("**set %s rate recalc=%lu\n",clk->name,clk->rate);
- __propagate_rate(clk);
- }
-
- clk->last_set_rate = rate;
-
- if (clk->notifier_count)
- clk_notify(clk, ret ? CLK_ABORT_RATE_CHANGE : CLK_POST_RATE_CHANGE, old_rate, clk->rate);
-
- return ret;
-}
-
-int clk_set_parent_nolock(struct clk *clk, struct clk *parent)
-{
- int ret;
- int enabled = clk->usecount > 0;
- struct clk *old_parent = clk->parent;
-
- if (clk->parent == parent)
- return 0;
-
- /* if clk is already enabled, enable new parent first and disable old parent later. */
- if (enabled)
- clk_enable_nolock(parent);
-
- if (clk->set_parent)
- ret = clk->set_parent(clk, parent);
- else
- ret = clk_default_set_parent(clk,parent);
-
- if (ret == 0) {
- /* OK */
-
- //CLOCK_PRINTK_DBG("set_parent %s reparent\n",clk->name,parent->name);
- __clk_reparent(clk, parent);
- __clk_recalc(clk);
- __propagate_rate(clk);
- if (enabled)
- clk_disable_nolock(old_parent);
- } else {
- //CLOCK_PRINTK_DBG("set_parent err\n",clk->name,parent->name);
- if (enabled)
- clk_disable_nolock(parent);
- }
-
- return ret;
-}
-/**********************************dvfs****************************************************/
-int clk_set_rate_locked(struct clk * clk,unsigned long rate)
-{
- int ret;
- //CLOCK_PRINTK_DBG("%s dvfs clk_set_locked\n",clk->name);
- LOCK();
- ret=clk_set_rate_nolock(clk, rate);;
- UNLOCK();
- return ret;
-
-}
-void clk_register_dvfs(struct clk_node *dvfs_clk, struct clk *clk)
-{
- clk->dvfs_info = dvfs_clk;
-}
-int clk_set_enable_locked(struct clk * clk,int on)
-{
- int ret=0;
- LOCK();
- if(on)
- ret=clk_enable_nolock(clk);
- else
- clk_disable_nolock(clk);
- UNLOCK();
- return ret;
-}
-EXPORT_SYMBOL(clk_set_enable_locked);
-/*-------------------------------------------------------------------------
- * Optional clock functions defined in include/linux/clk.h
- *-------------------------------------------------------------------------*/
-#ifdef RK30_CLK_OFFBOARD_TEST
-long rk30_clk_round_rate(struct clk *clk, unsigned long rate)
-#else
-long clk_round_rate(struct clk *clk, unsigned long rate)
-#endif
-{
- long ret = 0;
-
- if (clk == NULL || IS_ERR(clk))
- return ret;
-
- LOCK();
- ret = clk_round_rate_nolock(clk, rate);
- UNLOCK();
-
- return ret;
-}
-
-#ifdef RK30_CLK_OFFBOARD_TEST
-EXPORT_SYMBOL(rk30_clk_round_rate);
-#else
-EXPORT_SYMBOL(clk_round_rate);
-#endif
-
-#ifdef RK30_CLK_OFFBOARD_TEST
-unsigned long rk30_clk_get_rate(struct clk *clk)
-#else
-unsigned long clk_get_rate(struct clk *clk)
-#endif
-{
- if (clk == NULL || IS_ERR(clk))
- return 0;
-
- return clk->rate;
-}
-#ifdef RK30_CLK_OFFBOARD_TEST
-EXPORT_SYMBOL(rk30_clk_get_rate);
-#else
-EXPORT_SYMBOL(clk_get_rate);
-#endif
-
-
-/* Set the clock rate for a clock source */
-#ifdef RK30_CLK_OFFBOARD_TEST
-int rk30_clk_set_rate(struct clk *clk, unsigned long rate)
-#else
-int clk_set_rate(struct clk *clk, unsigned long rate)
-#endif
-{
- int ret = -EINVAL;
- if (clk == NULL || IS_ERR(clk)){
- return ret;
- }
- if (rate == clk->rate)
- return 0;
- if (dvfs_support_clk_set_rate(clk->dvfs_info)==true)
- return dvfs_vd_clk_set_rate(clk, rate);
-
- LOCK();
- ret = clk_set_rate_nolock(clk, rate);
- UNLOCK();
-
- return ret;
-}
-#ifdef RK30_CLK_OFFBOARD_TEST
-EXPORT_SYMBOL(rk30_clk_set_rate);
-#else
-EXPORT_SYMBOL(clk_set_rate);
-#endif
-
-
-#ifdef RK30_CLK_OFFBOARD_TEST
-int rk30_clk_set_parent(struct clk *clk, struct clk *parent)
-#else
-int clk_set_parent(struct clk *clk, struct clk *parent)
-#endif
-{
- int ret = -EINVAL;
-
- if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent))
- return ret;
-
- if (clk->parents == NULL)
- return ret;
-
- LOCK();
- if (clk->usecount == 0)
- ret = clk_set_parent_nolock(clk, parent);
- else
- ret = -EBUSY;
- UNLOCK();
-
- return ret;
-}
-int clk_set_parent_force(struct clk *clk, struct clk *parent)
-{
- int ret = -EINVAL;
-
- if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent))
- return ret;
-
- if (clk->parents == NULL)
- return ret;
- LOCK();
- ret = clk_set_parent_nolock(clk, parent);
- UNLOCK();
- return ret;
-}
-
-#ifdef RK30_CLK_OFFBOARD_TEST
-EXPORT_SYMBOL(rk30_clk_set_parent);
-#else
-EXPORT_SYMBOL(clk_set_parent);
-#endif
-
-#ifdef RK30_CLK_OFFBOARD_TEST
-struct clk *rk30_clk_get_parent(struct clk *clk)
-#else
-struct clk *clk_get_parent(struct clk *clk)
-#endif
-{
- if (clk == NULL || IS_ERR(clk)) {
- return ERR_PTR(-EINVAL);
- }
- return clk->parent;
-}
-
-#ifdef RK30_CLK_OFFBOARD_TEST
-EXPORT_SYMBOL(rk30_clk_get_parent);
-#else
-EXPORT_SYMBOL(clk_get_parent);
-#endif
-
-#ifdef RK30_CLK_OFFBOARD_TEST
-void rk30_clk_disable(struct clk *clk)
-#else
-void clk_disable(struct clk *clk)
-#endif
-{
- if (clk == NULL || IS_ERR(clk))
- return;
- if (dvfs_support_clk_disable(clk->dvfs_info) == true) {
- dvfs_vd_clk_disable(clk, 0);
- return;
- }
-
- LOCK();
- clk_disable_nolock(clk);
- UNLOCK();
-}
-#ifdef RK30_CLK_OFFBOARD_TEST
-EXPORT_SYMBOL(rk30_clk_disable);
-#else
-EXPORT_SYMBOL(clk_disable);
-#endif
-
-#ifdef RK30_CLK_OFFBOARD_TEST
-int rk30_clk_enable(struct clk *clk)
-#else
-int clk_enable(struct clk *clk)
-#endif
-{
- int ret = 0;
-
- if (clk == NULL || IS_ERR(clk))
- return -EINVAL;
- if (dvfs_support_clk_disable(clk->dvfs_info)==true)
- return dvfs_vd_clk_disable(clk, 1);
-
- LOCK();
- ret = clk_enable_nolock(clk);
- UNLOCK();
-
- return ret;
-}
-#ifdef RK30_CLK_OFFBOARD_TEST
-EXPORT_SYMBOL(rk30_clk_enable);
-#else
-EXPORT_SYMBOL(clk_enable);
-#endif
-
-/* Clk notifier implementation */
-
-/**
- * struct clk_notifier - associate a clk with a notifier
- * @clk: struct clk * to associate the notifier with
- * @notifier_head: a raw_notifier_head for this clk
- * @node: linked list pointers
- *
- * A list of struct clk_notifier is maintained by the notifier code.
- * An entry is created whenever code registers the first notifier on a
- * particular @clk. Future notifiers on that @clk are added to the
- * @notifier_head.
- */
-struct clk_notifier {
- struct clk *clk;
- struct raw_notifier_head notifier_head;
- struct list_head node;
-};
-static LIST_HEAD(clk_notifier_list);
-/**
- * _clk_free_notifier_chain - safely remove struct clk_notifier
- * @cn: struct clk_notifier *
- *
- * Removes the struct clk_notifier @cn from the clk_notifier_list and
- * frees it.
- */
-static void _clk_free_notifier_chain(struct clk_notifier *cn)
-{
- list_del(&cn->node);
- kfree(cn);
-}
-
-/**
- * clk_notify - call clk notifier chain
- * @clk: struct clk * that is changing rate
- * @msg: clk notifier type (i.e., CLK_POST_RATE_CHANGE; see mach/clock.h)
- * @old_rate: old rate
- * @new_rate: new rate
- *
- * Triggers a notifier call chain on the post-clk-rate-change notifier
- * for clock 'clk'. Passes a pointer to the struct clk and the
- * previous and current rates to the notifier callback. Intended to be
- * called by internal clock code only. No return value.
- */
-static void clk_notify(struct clk *clk, unsigned long msg,
- unsigned long old_rate, unsigned long new_rate)
-{
- struct clk_notifier *cn;
- struct clk_notifier_data cnd;
-
- cnd.clk = clk;
- cnd.old_rate = old_rate;
- cnd.new_rate = new_rate;
-
- UNLOCK();
- list_for_each_entry(cn, &clk_notifier_list, node) {
- if (cn->clk == clk) {
- pr_debug("%s msg %lu rate %lu -> %lu\n", clk->name, msg, old_rate, new_rate);
- raw_notifier_call_chain(&cn->notifier_head, msg, &cnd);
- break;
- }
- }
- LOCK();
-}
-
-/**
- * clk_notifier_register - add a clock parameter change notifier
- * @clk: struct clk * to watch
- * @nb: struct notifier_block * with callback info
- *
- * Request notification for changes to the clock 'clk'. This uses a
- * blocking notifier. Callback code must not call into the clock
- * framework, as clocks_mutex is held. Pre-notifier callbacks will be
- * passed the previous and new rate of the clock.
- *
- * clk_notifier_register() must be called from process
- * context. Returns -EINVAL if called with null arguments, -ENOMEM
- * upon allocation failure; otherwise, passes along the return value
- * of blocking_notifier_chain_register().
- */
-int clk_notifier_register(struct clk *clk, struct notifier_block *nb)
-{
- struct clk_notifier *cn = NULL, *cn_new = NULL;
- int r;
- struct clk *clkp;
-
- if (!clk || IS_ERR(clk) || !nb)
- return -EINVAL;
-
- mutex_lock(&clocks_mutex);
-
- list_for_each_entry(cn, &clk_notifier_list, node)
- if (cn->clk == clk)
- break;
-
- if (cn->clk != clk) {
- cn_new = kzalloc(sizeof(struct clk_notifier), GFP_KERNEL);
- if (!cn_new) {
- r = -ENOMEM;
- goto cnr_out;
- };
-
- cn_new->clk = clk;
- RAW_INIT_NOTIFIER_HEAD(&cn_new->notifier_head);
-
- list_add(&cn_new->node, &clk_notifier_list);
- cn = cn_new;
- }
-
- r = raw_notifier_chain_register(&cn->notifier_head, nb);
- if (!IS_ERR_VALUE(r)) {
- clkp = clk;
- do {
- clkp->notifier_count++;
- } while ((clkp = clkp->parent));
- } else {
- if (cn_new)
- _clk_free_notifier_chain(cn);
- }
-
-cnr_out:
- mutex_unlock(&clocks_mutex);
-
- return r;
-}
-EXPORT_SYMBOL(clk_notifier_register);
-
-/**
- * clk_notifier_unregister - remove a clock change notifier
- * @clk: struct clk *
- * @nb: struct notifier_block * with callback info
- *
- * Request no further notification for changes to clock 'clk'.
- * Returns -EINVAL if called with null arguments; otherwise, passes
- * along the return value of blocking_notifier_chain_unregister().
- */
-int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb)
-{
- struct clk_notifier *cn = NULL;
- struct clk *clkp;
- int r = -EINVAL;
-
- if (!clk || IS_ERR(clk) || !nb)
- return -EINVAL;
-
- mutex_lock(&clocks_mutex);
-
- list_for_each_entry(cn, &clk_notifier_list, node)
- if (cn->clk == clk)
- break;
-
- if (cn->clk != clk) {
- r = -ENOENT;
- goto cnu_out;
- };
-
- r = raw_notifier_chain_unregister(&cn->notifier_head, nb);
- if (!IS_ERR_VALUE(r)) {
- clkp = clk;
- do {
- clkp->notifier_count--;
- } while ((clkp = clkp->parent));
- }
-
- /*
- * XXX ugh, layering violation. There should be some
- * support in the notifier code for this.
- */
- if (!cn->notifier_head.head)
- _clk_free_notifier_chain(cn);
-
-cnu_out:
- mutex_unlock(&clocks_mutex);
-
- return r;
-}
-EXPORT_SYMBOL(clk_notifier_unregister);
-
-#ifdef CONFIG_PROC_FS
-static struct clk_dump_ops *dump_def_ops;
-
-void clk_register_dump_ops(struct clk_dump_ops *ops)
-{
- dump_def_ops=ops;
-}
-#endif
-
-#ifdef CONFIG_RK_CLOCK_PROC
-static int proc_clk_show(struct seq_file *s, void *v)
-{
- struct clk* clk;
-
- if(!dump_def_ops)
- return 0;
-
- if(dump_def_ops->dump_clk)
- {
- mutex_lock(&clocks_mutex);
- list_for_each_entry(clk, &clocks, node) {
- if (!clk->parent)
- {
- dump_def_ops->dump_clk(s, clk, 0,&clocks);
- }
- }
- mutex_unlock(&clocks_mutex);
- }
- if(dump_def_ops->dump_regs)
- dump_def_ops->dump_regs(s);
- return 0;
-}
-
-
-static int proc_clk_open(struct inode *inode, struct file *file)
-{
- return single_open(file, proc_clk_show, NULL);
-}
-
-static const struct file_operations proc_clk_fops = {
- .open = proc_clk_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-static int __init clk_proc_init(void)
-{
- proc_create("clocks", S_IFREG | S_IRUSR | S_IRGRP, NULL, &proc_clk_fops);
- return 0;
-
-}
-late_initcall(clk_proc_init);
-#endif /* CONFIG_RK_CLOCK_PROC */
-
-static int clk_panic(struct notifier_block *this, unsigned long ev, void *ptr)
-{
-#ifdef RK30_CRU_BASE
-#define CRU_BASE RK30_CRU_BASE
-#elif defined(RK2928_CRU_BASE)
-#define CRU_BASE RK2928_CRU_BASE
-#endif
-#ifdef CRU_BASE
- print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_ADDRESS, 16, 4, CRU_BASE, 0x150, false);
-#endif
- return NOTIFY_DONE;
-}
-
-static struct notifier_block clk_panic_block = {
- .notifier_call = clk_panic,
-};
-
-static int __init clk_panic_init(void)
-{
- return atomic_notifier_chain_register(&panic_notifier_list, &clk_panic_block);
-}
-pure_initcall(clk_panic_init);
+++ /dev/null
-#include <mach/gpio.h>
-#include <mach/board.h>
-
-int port_output_init(unsigned int value, int on, char *name)
-{
- int ret = 0;
- struct port_config port;
-
- port = get_port_config(value);
- ret = gpio_request(port.gpio, name);
- if(ret < 0)
- return ret;
- if(port.io.pull_mode == PULL_MODE_DISABLE)
- gpio_pull_updown(port.gpio, 0);
- if(port.io.pull_mode == PULL_MODE_ENABLE)
- gpio_pull_updown(port.gpio, 1);
- #ifdef CONFIG_MACH_RK_FAC
- //gpio_direction_output(port.gpio, (on)? !port.io.active_low: !!port.io.active_low);
- #else
- gpio_direction_output(port.gpio, (on)? !port.io.active_low: !!port.io.active_low);
- #endif
-
- return 0;
-}
-EXPORT_SYMBOL(port_output_init);
-void port_output_on(unsigned int value)
-{
- struct port_config port;
-
- port = get_port_config(value);
- gpio_set_value(port.gpio, !port.io.active_low);
-}
-EXPORT_SYMBOL(port_output_on);
-void port_output_off(unsigned int value)
-{
- struct port_config port;
-
- port = get_port_config(value);
- gpio_set_value(port.gpio, !!port.io.active_low);
-}
-EXPORT_SYMBOL(port_output_off);
-void port_deinit(unsigned int value)
-{
- struct port_config port;
-
- port = get_port_config(value);
- gpio_free(port.gpio);
-}
-EXPORT_SYMBOL(port_deinit);
-int port_input_init(unsigned int value, char *name)
-{
- int ret = 0;
- struct port_config port;
-
- port = get_port_config(value);
- ret = gpio_request(port.gpio, name);
- if(ret < 0)
- return ret;
- if(port.io.pull_mode == PULL_MODE_DISABLE)
- gpio_pull_updown(port.gpio, 0);
- if(port.io.pull_mode == PULL_MODE_ENABLE)
- gpio_pull_updown(port.gpio, 1);
- gpio_direction_input(port.gpio);
-
- return 0;
-}
-EXPORT_SYMBOL(port_input_init);
-int port_get_value(unsigned int value)
-{
- struct port_config port;
-
- port = get_port_config(value);
- return gpio_get_value(port.gpio);
-}
-EXPORT_SYMBOL(port_get_value);
-
-
+++ /dev/null
-#include <linux/kernel.h>
-#include <linux/cpu.h>
-#include <plat/cpu.h>
-
-static ssize_t show_type(struct sysdev_class *dev, struct sysdev_class_attribute *attr, char *buf)
-{
- const char *type;
-
- if (cpu_is_rk319x())
- type = "rk319x";
- else if (cpu_is_rk3188())
- type = "rk3188";
- else if (cpu_is_rk3066b())
- type = "rk3066b";
- else if (cpu_is_rk3026())
- type = "rk3026";
- else if (cpu_is_rk30xx())
- type = "rk30xx";
- else if (cpu_is_rk2928())
- type = "rk2928";
- else
- type = "";
-
- return sprintf(buf, "%s\n", type);
-}
-
-static SYSDEV_CLASS_ATTR(type, 0444, show_type, NULL);
-
-static ssize_t show_soc(struct sysdev_class *dev, struct sysdev_class_attribute *attr, char *buf)
-{
- const char *soc;
-
- if (soc_is_rk3190())
- soc = "rk3190";
- else if (soc_is_rk3188plus())
- soc = "rk3188+";
- else if (soc_is_rk3188())
- soc = "rk3188";
- else if (soc_is_rk3168())
- soc = "rk3168";
- else if (soc_is_rk3028())
- soc = "rk3028";
- else if (soc_is_rk3066b())
- soc = "rk3066b";
- else if (soc_is_rk3028a())
- soc = "rk3028a";
- else if (soc_is_rk3026())
- soc = "rk3026";
- else if (soc_is_rk2928g())
- soc = "rk2928g";
- else if (soc_is_rk2928l())
- soc = "rk2928l";
- else if (soc_is_rk2926())
- soc = "rk2926";
- else if (soc_is_rk3066())
- soc = "rk3066";
- else if (soc_is_rk3068())
- soc = "rk3068";
- else if (soc_is_rk3000())
- soc = "rk3000";
- else
- soc = "";
-
- return sprintf(buf, "%s\n", soc);
-}
-
-static SYSDEV_CLASS_ATTR(soc, 0444, show_soc, NULL);
-
-static int __init rk_cpu_init(void)
-{
- int err;
-
- err = sysfs_create_file(&cpu_sysdev_class.kset.kobj, &attr_type.attr);
- err = sysfs_create_file(&cpu_sysdev_class.kset.kobj, &attr_soc.attr);
-
- return err;
-}
-late_initcall(rk_cpu_init);
+++ /dev/null
-#define pr_fmt(fmt) "ddrfreq: " fmt
-#include <linux/clk.h>
-#include <linux/cpu.h>
-#include <linux/cpufreq.h>
-#include <linux/delay.h>
-#include <linux/earlysuspend.h>
-#include <linux/freezer.h>
-#include <linux/fs.h>
-#include <linux/kthread.h>
-#include <linux/miscdevice.h>
-#include <linux/module.h>
-#include <linux/reboot.h>
-#include <linux/slab.h>
-#include <linux/uaccess.h>
-
-#include <mach/board.h>
-#include <mach/clock.h>
-#include <mach/ddr.h>
-#include <mach/dvfs.h>
-
-#include <linux/rk_fb.h>
-//#include <linux/delay.h>
-
-#include <asm/cacheflush.h>
-#include <asm/tlbflush.h>
-#include <linux/vmalloc.h>
-
-enum {
- DEBUG_DDR = 1U << 0,
- DEBUG_VIDEO_STATE = 1U << 1,
- DEBUG_SUSPEND = 1U << 2,
- DEBUG_VERBOSE = 1U << 3,
-};
-static int debug_mask = DEBUG_DDR;
-module_param(debug_mask, int, S_IRUGO | S_IWUSR | S_IWGRP);
-#define dprintk(mask, fmt, ...) do { if (mask & debug_mask) pr_info(fmt, ##__VA_ARGS__); } while (0)
-
-#define MHZ (1000*1000)
-#define KHZ 1000
-
-enum SYS_STATUS {
- SYS_STATUS_SUSPEND = 0, // 0x01
- SYS_STATUS_VIDEO, // 0x02
- SYS_STATUS_VIDEO_720P, // 0x04
- SYS_STATUS_VIDEO_1080P, // 0x08
- SYS_STATUS_GPU, // 0x10
- SYS_STATUS_RGA, // 0x20
- SYS_STATUS_CIF0, // 0x40
- SYS_STATUS_CIF1, // 0x80
- SYS_STATUS_REBOOT, // 0x100
- SYS_STATUS_LCDC0, // 0x200
- SYS_STATUS_LCDC1, // 0x400
-};
-
-struct ddr {
-#ifdef CONFIG_HAS_EARLYSUSPEND
- struct early_suspend early_suspend;
-#endif
- struct clk *pll;
- struct clk *clk;
- unsigned long normal_rate;
- unsigned long video_rate;
- unsigned long video_low_rate;
- unsigned long dualview_rate;
- unsigned long idle_rate;
- unsigned long suspend_rate;
- unsigned long reboot_rate;
- char video_state;
- bool auto_self_refresh;
- char *mode;
- unsigned long sys_status;
- struct task_struct *task;
- wait_queue_head_t wait;
-};
-static struct ddr ddr;
-
-module_param_named(sys_status, ddr.sys_status, ulong, S_IRUGO);
-module_param_named(video_state, ddr.video_state, byte, S_IRUGO);
-module_param_named(auto_self_refresh, ddr.auto_self_refresh, bool, S_IRUGO);
-module_param_named(mode, ddr.mode, charp, S_IRUGO);
-
-static noinline void ddrfreq_set_sys_status(enum SYS_STATUS status)
-{
- set_bit(status, &ddr.sys_status);
- wake_up(&ddr.wait);
-}
-
-static noinline void ddrfreq_clear_sys_status(enum SYS_STATUS status)
-{
- clear_bit(status, &ddr.sys_status);
- wake_up(&ddr.wait);
-}
-
-static void ddrfreq_mode(bool auto_self_refresh, unsigned long *target_rate, char *name)
-{
- ddr.mode = name;
- if (auto_self_refresh != ddr.auto_self_refresh) {
- ddr_set_auto_self_refresh(auto_self_refresh);
- ddr.auto_self_refresh = auto_self_refresh;
- dprintk(DEBUG_DDR, "change auto self refresh to %d when %s\n", auto_self_refresh, name);
- }
- if (*target_rate != clk_get_rate(ddr.clk)) {
- if (clk_set_rate(ddr.clk, *target_rate) == 0) {
- *target_rate = clk_get_rate(ddr.clk);
- dprintk(DEBUG_DDR, "change freq to %lu MHz when %s\n", *target_rate / MHZ, name);
- }
- }
-}
-
-static noinline void ddrfreq_work(unsigned long sys_status)
-{
- static struct clk *cpu = NULL;
- static struct clk *gpu = NULL;
- unsigned long s = sys_status;
-
- if (!cpu)
- cpu = clk_get(NULL, "cpu");
- if (!gpu)
- gpu = clk_get(NULL, "gpu");
- dprintk(DEBUG_VERBOSE, "sys_status %02lx\n", sys_status);
- if (ddr.reboot_rate && (s & (1 << SYS_STATUS_REBOOT))) {
- ddrfreq_mode(false, &ddr.reboot_rate, "shutdown/reboot");
- } else if (ddr.suspend_rate && (s & (1 << SYS_STATUS_SUSPEND))) {
- ddrfreq_mode(true, &ddr.suspend_rate, "suspend");
- } else if (ddr.dualview_rate
- && (s & (1 << SYS_STATUS_LCDC0))
- && (s & (1 << SYS_STATUS_LCDC1))
- ) {
- ddrfreq_mode(false, &ddr.dualview_rate, "dual-view");
- } else if ((ddr.video_rate || ddr.video_low_rate) && (s & (1 << SYS_STATUS_VIDEO))) {
- if(ddr.video_low_rate && (s & (1 << SYS_STATUS_VIDEO_720P)))
- ddrfreq_mode(false, &ddr.video_low_rate, "video low");
- else if(ddr.video_rate && (s & (1 << SYS_STATUS_VIDEO_1080P)))
- ddrfreq_mode(false, &ddr.video_rate, "video");
- else
- ddrfreq_mode(false, &ddr.normal_rate, "video normal");
- } else if (ddr.idle_rate
- && !(s & (1 << SYS_STATUS_GPU))
- && !(s & (1 << SYS_STATUS_RGA))
- && !(s & (1 << SYS_STATUS_CIF0))
- && !(s & (1 << SYS_STATUS_CIF1))
- && (clk_get_rate(cpu) < 816 * MHZ)
- && (clk_get_rate(gpu) <= 200 * MHZ)
- ) {
- ddrfreq_mode(false, &ddr.idle_rate, "idle");
- } else {
- ddrfreq_mode(false, &ddr.normal_rate, "normal");
- }
-}
-
-static int ddrfreq_task(void *data)
-{
- set_freezable();
-
- do {
- unsigned long status = ddr.sys_status;
- ddrfreq_work(status);
- wait_event_freezable(ddr.wait, (status != ddr.sys_status) || kthread_should_stop());
- } while (!kthread_should_stop());
-
- return 0;
-}
-
-#ifdef CONFIG_SMP
-static volatile bool __sramdata cpu_pause[NR_CPUS];
-static inline bool is_cpu0_paused(unsigned int cpu) { smp_rmb(); return cpu_pause[0]; }
-static inline bool is_cpuX_paused(unsigned int cpu) { smp_rmb(); return cpu_pause[cpu]; }
-static inline void set_cpuX_paused(unsigned int cpu, bool pause) { cpu_pause[cpu] = pause; smp_wmb(); }
-static inline void set_cpu0_paused(bool pause)
-{
- cpu_pause[0] = pause;
- smp_wmb();
-}
-#define MAX_TIMEOUT (16000000UL << 6) //>0.64s
-
-/* Do not use stack, safe on SMP */
-static void __sramfunc pause_cpu(void *info)
-{
- unsigned int cpu = raw_smp_processor_id();
-
- set_cpuX_paused(cpu, true);
- while (is_cpu0_paused(cpu));
- set_cpuX_paused(cpu, false);
-}
-
-static void wait_cpu(void *info)
-{
-}
-
-static int _ddr_change_freq_(uint32_t nMHz,struct ddr_freq_t ddr_freq_t)
-{
- u32 timeout = MAX_TIMEOUT;
- unsigned int cpu;
- unsigned int this_cpu = smp_processor_id();
- int ret = 0;
-
- cpu_maps_update_begin();
- local_bh_disable();
- set_cpu0_paused(true);
- smp_call_function((smp_call_func_t)pause_cpu, NULL, 0);
- for_each_online_cpu(cpu) {
- if (cpu == this_cpu)
- continue;
- while (!is_cpuX_paused(cpu) && --timeout);
- if (timeout == 0) {
- pr_err("pause cpu %d timeout\n", cpu);
- goto out;
- }
- }
-
- ret = ddr_change_freq_sram(nMHz,ddr_freq_t);
-
-out:
- set_cpu0_paused(false);
- local_bh_enable();
- smp_call_function(wait_cpu, NULL, true);
- cpu_maps_update_done();
-
- return ret;
-}
-
-static void _ddr_change_freq(uint32_t nMHz)
-{
- struct ddr_freq_t ddr_freq_t;
- int test_count=0;
-
- ddr_freq_t.screen_ft_us = 0;
- ddr_freq_t.t0 = 0;
- ddr_freq_t.t1 = 0;
-
-#if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
- do
- {
- if(rk_fb_poll_wait_frame_complete() == true)
- {
- ddr_freq_t.t0 = cpu_clock(0);
- ddr_freq_t.screen_ft_us = rk_fb_get_prmry_screen_ft();
-
- test_count++;
- if(test_count > 10) //test 10 times
- {
- ddr_freq_t.screen_ft_us = 0xfefefefe;
- dprintk(DEBUG_DDR,"%s:test_count exceed maximum!\n",__func__);
- }
- dprintk(DEBUG_VERBOSE,"%s:test_count=%d\n",__func__,test_count);
- usleep_range(ddr_freq_t.screen_ft_us-test_count*1000,ddr_freq_t.screen_ft_us-test_count*1000);
-
- flush_cache_all();
- outer_flush_all();
- flush_tlb_all();
- }
- }while(_ddr_change_freq_(nMHz,ddr_freq_t)==0);
-#else
- _ddr_change_freq_(nMHz,ddr_freq_t);
-#endif
-}
-#else
-static void _ddr_change_freq(uint32_t nMHz)
-{
- ddr_change_freq(nMHz);
-}
-#endif
-
-static void ddr_set_rate(uint32_t nMHz)
-{
- _ddr_change_freq(nMHz);
- ddr.clk->rate = ddr.clk->recalc(ddr.clk);
-}
-
-#ifdef CONFIG_HAS_EARLYSUSPEND
-static void ddrfreq_early_suspend(struct early_suspend *h)
-{
- dprintk(DEBUG_SUSPEND, "early suspend\n");
- ddrfreq_set_sys_status(SYS_STATUS_SUSPEND);
-}
-
-static void ddrfreq_late_resume(struct early_suspend *h)
-{
- dprintk(DEBUG_SUSPEND, "late resume\n");
- ddrfreq_clear_sys_status(SYS_STATUS_SUSPEND);
-}
-#endif
-
-static int video_state_release(struct inode *inode, struct file *file)
-{
- dprintk(DEBUG_VIDEO_STATE, "video_state release\n");
- ddr.video_state = '0';
- ddrfreq_clear_sys_status(SYS_STATUS_VIDEO);
- return 0;
-}
-
-#define VIDEO_LOW_RESOLUTION (1080*720)
-static ssize_t video_state_write(struct file *file, const char __user *buffer,
- size_t count, loff_t *ppos)
-{
- char state;
- char *cookie_pot;
- char *p;
- char *buf = vzalloc(count);
- uint32_t v_width=0,v_height=0,v_sync=0;
- cookie_pot = buf;
-
- if(!buf)
- return -ENOMEM;
-
- if (count < 1){
- vfree(buf);
- return -EPERM;
- }
-
- if (copy_from_user(cookie_pot, buffer, count)) {
- vfree(buf);
- return -EFAULT;
- }
-
- dprintk(DEBUG_VIDEO_STATE, "video_state write %s,len %d\n", cookie_pot,count);
-
- state=cookie_pot[0];
- if( (count>=3) && (cookie_pot[2]=='w') )
- {
- strsep(&cookie_pot,",");
- strsep(&cookie_pot,"=");
- p=strsep(&cookie_pot,",");
- v_width = simple_strtol(p,NULL,10);
- strsep(&cookie_pot,"=");
- p=strsep(&cookie_pot,",");
- v_height= simple_strtol(p,NULL,10);
- strsep(&cookie_pot,"=");
- p=strsep(&cookie_pot,",");
- v_sync= simple_strtol(p,NULL,10);
- dprintk(DEBUG_VIDEO_STATE, "video_state %c,width=%d,height=%d,sync=%d\n", state,v_width,v_height,v_sync);
- }
-
- switch (state) {
- case '0':
- ddrfreq_clear_sys_status(SYS_STATUS_VIDEO);
- ddrfreq_clear_sys_status(SYS_STATUS_VIDEO_720P);
- ddrfreq_clear_sys_status(SYS_STATUS_VIDEO_1080P);
- break;
- case '1':
- ddrfreq_set_sys_status(SYS_STATUS_VIDEO);
-
- if( (v_width == 0) && (v_height == 0)){
- ddrfreq_set_sys_status(SYS_STATUS_VIDEO_1080P);
- }
- else if(v_sync==1){
- if(ddr.video_low_rate && ((v_width*v_height) <= VIDEO_LOW_RESOLUTION) )
- ddrfreq_set_sys_status(SYS_STATUS_VIDEO_720P);
- else
- ddrfreq_set_sys_status(SYS_STATUS_VIDEO_1080P);
- }
- else{
- ddrfreq_clear_sys_status(SYS_STATUS_VIDEO_720P);
- ddrfreq_clear_sys_status(SYS_STATUS_VIDEO_1080P);
- }
- break;
- default:
- vfree(buf);
- return -EINVAL;
-
- }
- ddr.video_state = state;
- vfree(buf);
- return count;
-}
-
-static const struct file_operations video_state_fops = {
- .owner = THIS_MODULE,
- .release= video_state_release,
- .write = video_state_write,
-};
-
-static struct miscdevice video_state_dev = {
- .fops = &video_state_fops,
- .name = "video_state",
- .minor = MISC_DYNAMIC_MINOR,
-};
-
-static int ddrfreq_clk_event(enum SYS_STATUS status, unsigned long event)
-{
- switch (event) {
- case CLK_PRE_ENABLE:
- ddrfreq_set_sys_status(status);
- break;
- case CLK_ABORT_ENABLE:
- case CLK_POST_DISABLE:
- ddrfreq_clear_sys_status(status);
- break;
- }
-
- return NOTIFY_OK;
-}
-
-#define CLK_NOTIFIER(name, status) \
-static int ddrfreq_clk_##name##_event(struct notifier_block *this, unsigned long event, void *ptr) \
-{ \
- return ddrfreq_clk_event(SYS_STATUS_##status, event); \
-} \
-static struct notifier_block ddrfreq_clk_##name##_notifier = { .notifier_call = ddrfreq_clk_##name##_event };
-
-#define REGISTER_CLK_NOTIFIER(name) \
-do { \
- struct clk *clk = clk_get(NULL, #name); \
- clk_notifier_register(clk, &ddrfreq_clk_##name##_notifier); \
- clk_put(clk); \
-} while (0)
-
-#define UNREGISTER_CLK_NOTIFIER(name) \
-do { \
- struct clk *clk = clk_get(NULL, #name); \
- clk_notifier_unregister(clk, &ddrfreq_clk_##name##_notifier); \
- clk_put(clk); \
-} while (0)
-
-CLK_NOTIFIER(pd_gpu, GPU);
-CLK_NOTIFIER(pd_rga, RGA);
-CLK_NOTIFIER(pd_cif0, CIF0);
-CLK_NOTIFIER(pd_cif1, CIF1);
-CLK_NOTIFIER(pd_lcdc0, LCDC0);
-CLK_NOTIFIER(pd_lcdc1, LCDC1);
-
-static int ddrfreq_reboot_notifier_event(struct notifier_block *this, unsigned long event, void *ptr)
-{
- u32 timeout = 1000; // 10s
- ddrfreq_set_sys_status(SYS_STATUS_REBOOT);
- while (clk_get_rate(ddr.clk) != ddr.reboot_rate && --timeout) {
- msleep(10);
- }
- if (!timeout) {
- pr_err("failed to set ddr clk from %luMHz to %luMHz when shutdown/reboot\n", clk_get_rate(ddr.clk) / MHZ, ddr.reboot_rate / MHZ);
- }
- return NOTIFY_OK;
-}
-
-static struct notifier_block ddrfreq_reboot_notifier = {
- .notifier_call = ddrfreq_reboot_notifier_event,
-};
-
-static int ddr_scale_rate_for_dvfs(struct clk *clk, unsigned long rate, dvfs_set_rate_callback set_rate)
-{
- ddr_set_rate(rate/(1000*1000));
- /* return 0 when ok */
- return !( (clk_get_rate(clk)/MHZ) == (rate/MHZ));
-}
-
-#if defined(CONFIG_ARCH_RK3066B)
-static int ddrfreq_scanfreq_datatraing_3168(void)
-{
- struct cpufreq_frequency_table *table;
- uint32_t dqstr_freq,dqstr_value;
- uint32_t min_freq,max_freq;
- int i;
- table = dvfs_get_freq_volt_table(clk_get(NULL, "ddr"));
- if (!table)
- {
- pr_err("failed to get ddr freq volt table\n");
- }
- for (i = 0; table && table[i].frequency != CPUFREQ_TABLE_END; i++)
- {
- if(i == 0)
- min_freq = table[i].frequency / 1000;
-
- max_freq = table[i].frequency / 1000;
- }
-
- //get data training value for RK3066B ddr_change_freq
- for(dqstr_freq=min_freq; dqstr_freq<=max_freq; dqstr_freq=dqstr_freq+50)
- {
- if (clk_set_rate(ddr.clk, dqstr_freq*MHZ) != 0)
- {
- pr_err("failed to clk_set_rate ddr.clk %dhz\n",dqstr_freq*MHZ);
- }
- dqstr_value=(dqstr_freq-min_freq+1)/50;
-
- ddr_get_datatraing_value_3168(false,dqstr_value,min_freq);
- }
- ddr_get_datatraing_value_3168(true,0,min_freq);
- dprintk(DEBUG_DDR,"get datatraing from %dMhz to %dMhz\n",min_freq,max_freq);
- return 0;
-}
-#endif
-
-static int ddrfreq_init(void)
-{
- int i, ret;
- struct cpufreq_frequency_table *table;
- int ddrfreq_version = 0;
-
- init_waitqueue_head(&ddr.wait);
- ddr.video_state = '0';
- ddr.mode = "normal";
-
- ddr.pll = clk_get(NULL, "ddr_pll");
- ddr.clk = clk_get(NULL, "ddr");
- if (IS_ERR(ddr.clk)) {
- ret = PTR_ERR(ddr.clk);
- ddr.clk = NULL;
- pr_err("failed to get ddr clk, error %d\n", ret);
- return ret;
- }
- dvfs_clk_register_set_rate_callback(ddr.clk, ddr_scale_rate_for_dvfs);
-
- ddr.normal_rate = clk_get_rate(ddr.clk);
- ddr.reboot_rate = ddr.normal_rate;
-
- table = dvfs_get_freq_volt_table(ddr.clk);
- if (!table) {
- pr_err("failed to get ddr freq volt table\n");
- }
-
- for (i = 0; table && table[i].frequency != CPUFREQ_TABLE_END; i++) {
- if (table[i].frequency % 1000) {
- ddrfreq_version = 1;
- }
-
- if (table[i].frequency % 1000 > 100) {
- ddrfreq_version = 2;
- break;
- }
- }
-
- if (ddrfreq_version==0) {
- ddr.video_rate = 300 * MHZ;
- ddr.dualview_rate = ddr.normal_rate;
- ddr.suspend_rate = 200 * MHZ;
- }
-
- for (i = 0; ddrfreq_version == 1 && table && table[i].frequency != CPUFREQ_TABLE_END; i++) {
- unsigned int mode = table[i].frequency % 1000;
- unsigned long rate;
-
- table[i].frequency -= mode;
- rate = table[i].frequency * 1000;
-
- switch (mode) {
- case DDR_FREQ_NORMAL:
- ddr.normal_rate = rate;
- break;
- case DDR_FREQ_VIDEO_LOW:
- ddr.video_low_rate = rate;
- break;
- case DDR_FREQ_VIDEO:
- ddr.video_rate = rate;
- break;
- case DDR_FREQ_DUALVIEW:
- ddr.dualview_rate= rate;
- break;
- case DDR_FREQ_IDLE:
- ddr.idle_rate = rate;
- break;
- case DDR_FREQ_SUSPEND:
- ddr.suspend_rate = rate;
- break;
- }
- }
-
- for (i = 0; ddrfreq_version == 2 && table && table[i].frequency != CPUFREQ_TABLE_END; i++) {
- unsigned int mode = table[i].frequency % 1000;
- unsigned long rate;
-
- table[i].frequency -= mode;
- rate = table[i].frequency * 1000;
-
- if( (mode&DDR_FREQ_NORMAL) == DDR_FREQ_NORMAL)
- ddr.normal_rate = rate;
-
- if( (mode&DDR_FREQ_VIDEO_LOW) == DDR_FREQ_VIDEO_LOW)
- ddr.video_low_rate = rate;
-
- if( (mode&DDR_FREQ_VIDEO) == DDR_FREQ_VIDEO)
- ddr.video_rate = rate;
-
- if( (mode&DDR_FREQ_DUALVIEW) == DDR_FREQ_DUALVIEW)
- ddr.dualview_rate= rate;
-
- if( (mode&DDR_FREQ_IDLE) == DDR_FREQ_IDLE)
- ddr.idle_rate = rate;
-
- if( (mode&DDR_FREQ_SUSPEND) == DDR_FREQ_SUSPEND)
- ddr.suspend_rate = rate;
- }
-
- if (ddr.idle_rate) {
- REGISTER_CLK_NOTIFIER(pd_gpu);
- REGISTER_CLK_NOTIFIER(pd_rga);
- REGISTER_CLK_NOTIFIER(pd_cif0);
- REGISTER_CLK_NOTIFIER(pd_cif1);
- }
-
- if (ddr.dualview_rate) {
- REGISTER_CLK_NOTIFIER(pd_lcdc0);
- REGISTER_CLK_NOTIFIER(pd_lcdc1);
- }
-
- return 0;
-
-}
-core_initcall(ddrfreq_init);
-
-static int ddrfreq_late_init(void)
-{
- int ret;
- struct sched_param param = { .sched_priority = MAX_RT_PRIO - 1 };
-
- if (!ddr.clk) {
- return -EINVAL;
- }
-
- ret = misc_register(&video_state_dev);
- if (unlikely(ret)) {
- pr_err("failed to register video_state misc device! error %d\n", ret);
- goto err;
- }
-
-#ifdef CONFIG_HAS_EARLYSUSPEND
- ddr.early_suspend.suspend = ddrfreq_early_suspend;
- ddr.early_suspend.resume = ddrfreq_late_resume;
- ddr.early_suspend.level = EARLY_SUSPEND_LEVEL_DISABLE_FB + 50;
- register_early_suspend(&ddr.early_suspend);
-#endif
-
-#if defined(CONFIG_ARCH_RK3066B)
- ddrfreq_scanfreq_datatraing_3168();
-#endif
-
- ddr.task = kthread_create(ddrfreq_task, NULL, "ddrfreqd");
- if (IS_ERR(ddr.task)) {
- ret = PTR_ERR(ddr.task);
- pr_err("failed to create kthread! error %d\n", ret);
- goto err1;
- }
-
- sched_setscheduler_nocheck(ddr.task, SCHED_FIFO, ¶m);
- get_task_struct(ddr.task);
- kthread_bind(ddr.task, 0);
- wake_up_process(ddr.task);
-
- register_reboot_notifier(&ddrfreq_reboot_notifier);
-
- pr_info("verion 3.2 20130917\n");
- pr_info("fix cpu pause bug\n");
- dprintk(DEBUG_DDR, "normal %luMHz video %luMHz video_low %luMHz dualview %luMHz idle %luMHz suspend %luMHz reboot %luMHz\n",
- ddr.normal_rate / MHZ, ddr.video_rate / MHZ, ddr.video_low_rate / MHZ, ddr.dualview_rate / MHZ, ddr.idle_rate / MHZ, ddr.suspend_rate / MHZ, ddr.reboot_rate / MHZ);
-
- return 0;
-
-err1:
-#ifdef CONFIG_HAS_EARLYSUSPEND
- unregister_early_suspend(&ddr.early_suspend);
-#endif
- misc_deregister(&video_state_dev);
-err:
- if (ddr.idle_rate) {
- UNREGISTER_CLK_NOTIFIER(pd_gpu);
- UNREGISTER_CLK_NOTIFIER(pd_rga);
- UNREGISTER_CLK_NOTIFIER(pd_cif0);
- UNREGISTER_CLK_NOTIFIER(pd_cif1);
- }
- if (ddr.dualview_rate) {
- UNREGISTER_CLK_NOTIFIER(pd_lcdc0);
- UNREGISTER_CLK_NOTIFIER(pd_lcdc1);
- }
-
- return ret;
-}
-late_initcall(ddrfreq_late_init);
+++ /dev/null
-#if defined(CONFIG_DDR_TEST) && defined(CONFIG_DDR_FREQ)
-#include <linux/slab.h>
-#include <linux/cpu.h>
-#include <linux/delay.h>
-#include <linux/proc_fs.h>
-#include <linux/vmalloc.h>
-#include <linux/random.h>
-#include <linux/uaccess.h>
-#include <linux/clk.h>
-
-#include <linux/freezer.h>
-#include <linux/kthread.h>
-
-#include <mach/ddr.h>
-
-struct ddrtest {
- struct clk *pll;
- struct clk *clk;
- volatile unsigned int freq;
- volatile bool change_end;
- struct task_struct *task;
- wait_queue_head_t wait;
-};
-static struct ddrtest ddrtest;
-
-static ssize_t ddr_proc_write(struct file *file, const char __user *buffer,
- unsigned long len, void *data)
-{
- char *cookie_pot;
- char *p;
- uint32_t value, value1, value2;
- uint32_t count, total;
- char tmp;
- struct clk *clk_ddr = NULL;
- int ret = len;
- char *buf = vzalloc(len);
-
- cookie_pot = buf;
-
- if (!cookie_pot)
- {
- return -ENOMEM;
- }
- else
- {
- if (copy_from_user( cookie_pot, buffer, len )) {
- ret = -EFAULT;
- goto out;
- }
- }
-
- clk_ddr = clk_get(NULL, "ddr");
- if (IS_ERR(clk_ddr)) {
- ret = PTR_ERR(clk_ddr);
- clk_ddr = NULL;
- goto out;
- }
-
- switch(cookie_pot[0])
- {
- case 'c':
- case 'C':
- printk("change ddr freq:\n");
- if(cookie_pot[1] ==':')
- {
- strsep(&cookie_pot,":");
- p=strsep(&cookie_pot,"M");
- value = simple_strtol(p,NULL,10);
- printk("change!!! freq=%dMHz\n", value);
- //clk_set_rate(clk_ddr, value * 1000000);
- ddrtest.freq = value;
- ddrtest.change_end = false;
- wake_up(&ddrtest.wait);
- while(ddrtest.change_end != true); //wait change freq end
- value = clk_get_rate(clk_ddr) / 1000000;
- printk("success!!! freq=%dMHz\n", value);
- msleep(64);
- printk("\n");
- }
- else
- {
- printk("Error auto change ddr freq debug.\n");
- printk("-->'c&&C' change freq,Example: echo 'c:400M' > ddr_test\n");
- }
- break;
-
- case 'a':
- case 'A':
- printk("auto change ddr freq test (random):\n");
- if(cookie_pot[1] ==':')
- {
- strsep(&cookie_pot,":");
- p=strsep(&cookie_pot,"M");
- value1 = simple_strtol(p,NULL,10);
- strsep(&cookie_pot,"-");
- p=strsep(&cookie_pot,"M");
- value2 = simple_strtol(p,NULL,10);
- strsep(&cookie_pot,"-");
- p=strsep(&cookie_pot,"T");
- total = simple_strtol(p,NULL,10);
-
- count = 0;
-
- while ( count < total )
- {
- printk("auto change ddr freq test (random):[%d-%d]\n",count,total);
- do
- {
- value = value1 + random32();
- value %= value2;
- }while(value < value1);
-
- printk("change!!! freq=%dMHz\n", value);
- //clk_set_rate(clk_ddr, value * 1000000);
- ddrtest.freq = value;
- ddrtest.change_end = false;
- wake_up(&ddrtest.wait);
- while(ddrtest.change_end != true); //wait change freq end
- value = clk_get_rate(clk_ddr) / 1000000;
- printk("success!!! freq=%dMHz\n", value);
- msleep(64);
- count++;
- }
-
- }
- else
- {
- printk("Error auto change ddr freq test debug.\n");
- printk("-->'a&&A' auto change ddr freq test (random),Example: echo 'a:200M-400M-1000T' > ddr_test\n");
- }
- break;
-
- case 'b':
- case 'B':
- printk("auto change ddr freq test (specific):\n");
- if(cookie_pot[1] ==':')
- {
- strsep(&cookie_pot,":");
- p=strsep(&cookie_pot,"M");
- value1 = simple_strtol(p,NULL,10);
- strsep(&cookie_pot,"-");
- p=strsep(&cookie_pot,"M");
- value2 = simple_strtol(p,NULL,10);
- strsep(&cookie_pot,"-");
- p=strsep(&cookie_pot,"T");
- total = simple_strtol(p,NULL,10);
-
- count = 0;
- tmp = 0;
-
- while ( count < total )
- {
- printk("auto change ddr freq test (specific):[%d-%d]\n",count,total);
- if(tmp == 1)
- {
- value = value1;
- tmp = 0;
- }
- else
- {
- value = value2;
- tmp = 1;
- }
-
- printk("change!!! freq=%dMHz\n", value);
- //clk_set_rate(clk_ddr, value * 1000000);
- ddrtest.freq = value;
- ddrtest.change_end = false;
- wake_up(&ddrtest.wait);
- while(ddrtest.change_end != true); //wait change freq end
- value = clk_get_rate(clk_ddr) / 1000000;
- printk("success!!! freq=%dMHz\n", value);
- msleep(64);
- count++;
- }
-
- }
- else
- {
- printk("Error auto change ddr freq test debug.\n");
- printk("-->'b&&B' auto change ddr freq test (specific),Example: echo 'a:200M-400M-1000T' > ddr_test\n");
- }
- break;
-
- case 'h':
- case 'H':
- default:
- printk("Help for ddr_ts .\n-->The Cmd list: \n");
- printk("-->'a&&A' auto change ddr freq test (random),Example: echo 'a:200M-400M-100T' > ddr_test\n");
- printk("-->'b&&B' auto change ddr freq test (specific),Example: echo 'b:200M-400M-100T' > ddr_test\n");
- printk("-->'c&&C' change freq,Example: echo 'c:400M' > ddr_test\n");
- break;
- }
-
-out:
- if (clk_ddr)
- clk_put(clk_ddr);
- vfree(buf);
- return ret;
-}
-
-static const struct file_operations ddr_proc_fops = {
- .owner = THIS_MODULE,
-};
-
-static void ddrtest_work(unsigned int value)
-{
-
- clk_set_rate(ddrtest.clk, value * 1000000);
- ddrtest.change_end = true;
-}
-
-static int ddrtest_task(void *data)
-{
- set_freezable();
-
- do {
- //unsigned long status = ddr.sys_status;
- ddrtest_work(ddrtest.freq);
- wait_event_freezable(ddrtest.wait, (ddrtest.change_end == false ) || kthread_should_stop());
- } while (!kthread_should_stop());
-
- return 0;
-}
-
-static int ddr_proc_init(void)
-{
- struct proc_dir_entry *ddr_proc_entry;
- int ret;
- struct sched_param param = { .sched_priority = MAX_RT_PRIO - 1 };
- init_waitqueue_head(&ddrtest.wait);
-
- ddrtest.pll = clk_get(NULL, "ddr_pll");
- ddrtest.clk = clk_get(NULL, "ddr");
- if (IS_ERR(ddrtest.clk)) {
- ret = PTR_ERR(ddrtest.clk);
- ddrtest.clk = NULL;
- pr_err("failed to get ddr clk, error %d\n", ret);
- return ret;
- }
-
- ddr_proc_entry = create_proc_entry("driver/ddr_ts", 0777, NULL);
- if(ddr_proc_entry != NULL)
- {
- ddr_proc_entry->write_proc = ddr_proc_write;
- //return -1;
- }
- else
- {
- printk("create proc error !\n");
- }
-
- ddrtest.task = kthread_create(ddrtest_task, NULL, "ddrtestd");
- if (IS_ERR(ddrtest.task)) {
- ret = PTR_ERR(ddrtest.task);
- pr_err("failed to create kthread! error %d\n", ret);
- goto err;
- }
- sched_setscheduler_nocheck(ddrtest.task,SCHED_FIFO, ¶m);
- get_task_struct(ddrtest.task);
- kthread_bind(ddrtest.task, 0);
- wake_up_process(ddrtest.task);
-
-err:
- return 0;
-}
-
-late_initcall(ddr_proc_init);
-#endif // CONFIG_DDR_TEST && CONFIG_DDR_FREQ
+++ /dev/null
-/* linux/arch/arm/plat-samsung/rk29-pl330.c
- *
- * Copyright (C) 2010 Samsung Electronics Co. Ltd.
- * Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/platform_device.h>
-
-#include <asm/hardware/pl330.h>
-
-#include <plat/dma-pl330.h>
-
-/**
- * struct rk29_pl330_dmac - Logical representation of a PL330 DMAC.
- * @busy_chan: Number of channels currently busy.
- * @peri: List of IDs of peripherals this DMAC can work with.
- * @node: To attach to the global list of DMACs.
- * @pi: PL330 configuration info for the DMAC.
- * @kmcache: Pool to quickly allocate xfers for all channels in the dmac.
- */
-struct rk29_pl330_dmac {
- unsigned busy_chan;
- enum dma_ch *peri;
- struct list_head node;
- struct pl330_info *pi;
- struct kmem_cache *kmcache;
-};
-
-/**
- * struct rk29_pl330_xfer - A request submitted by rk29 DMA clients.
- * @token: Xfer ID provided by the client.
- * @node: To attach to the list of xfers on a channel.
- * @px: Xfer for PL330 core.
- * @chan: Owner channel of this xfer.
- */
-struct rk29_pl330_xfer {
- void *token;
- struct list_head node;
- struct pl330_xfer px;
- struct rk29_pl330_chan *chan;
-};
-
-/**
- * struct rk29_pl330_chan - Logical channel to communicate with
- * a Physical peripheral.
- * @pl330_chan_id: Token of a hardware channel thread of PL330 DMAC.
- * NULL if the channel is available to be acquired.
- * @id: ID of the peripheral that this channel can communicate with.
- * @options: Options specified by the client.
- * @sdaddr: Address provided via rk29_dma_devconfig.
- * @node: To attach to the global list of channels.
- * @lrq: Pointer to the last submitted pl330_req to PL330 core.
- * @xfer_list: To manage list of xfers enqueued.
- * @req: Two requests to communicate with the PL330 engine.
- * @callback_fn: Callback function to the client.
- * @rqcfg: Channel configuration for the xfers.
- * @xfer_head: Pointer to the xfer to be next executed.
- * @dmac: Pointer to the DMAC that manages this channel, NULL if the
- * channel is available to be acquired.
- * @client: Client of this channel. NULL if the
- * channel is available to be acquired.
- */
-struct rk29_pl330_chan {
- void *pl330_chan_id;
- enum dma_ch id;
- unsigned int options;
- unsigned long sdaddr;
- struct list_head node;
- struct pl330_req *lrq;
- struct list_head xfer_list;
- struct pl330_req req[2];
- rk29_dma_cbfn_t callback_fn;
- struct pl330_reqcfg rqcfg;
- struct rk29_pl330_xfer *xfer_head;
- struct rk29_pl330_dmac *dmac;
- struct rk29_dma_client *client;
-};
-
-/* All DMACs in the platform */
-static LIST_HEAD(dmac_list);
-
-/* All channels to peripherals in the platform */
-static LIST_HEAD(chan_list);
-
-/*
- * Since we add resources(DMACs and Channels) to the global pool,
- * we need to guard access to the resources using a global lock
- */
-static DEFINE_SPINLOCK(res_lock);
-
-/* Returns the channel with ID 'id' in the chan_list */
-static struct rk29_pl330_chan *id_to_chan(const enum dma_ch id)
-{
- struct rk29_pl330_chan *ch;
-
- list_for_each_entry(ch, &chan_list, node)
- if (ch->id == id)
- return ch;
-
- return NULL;
-}
-
-/* Allocate a new channel with ID 'id' and add to chan_list */
-static void chan_add(const enum dma_ch id)
-{
- struct rk29_pl330_chan *ch = id_to_chan(id);
-
- /* Return if the channel already exists */
- if (ch)
- return;
-
- ch = kmalloc(sizeof(*ch), GFP_KERNEL);
- /* Return silently to work with other channels */
- if (!ch)
- return;
-
- ch->id = id;
- ch->dmac = NULL;
-
- list_add_tail(&ch->node, &chan_list);
-}
-
-/* If the channel is not yet acquired by any client */
-static bool chan_free(struct rk29_pl330_chan *ch)
-{
- if (!ch)
- return false;
-
- /* Channel points to some DMAC only when it's acquired */
- return ch->dmac ? false : true;
-}
-
-/*
- * Returns 0 is peripheral i/f is invalid or not present on the dmac.
- * Index + 1, otherwise.
- */
-static unsigned iface_of_dmac(struct rk29_pl330_dmac *dmac, enum dma_ch ch_id)
-{
- enum dma_ch *id = dmac->peri;
- int i;
-
- /* Discount invalid markers */
- if (ch_id == DMACH_MAX)
- return 0;
-
- for (i = 0; i < PL330_MAX_PERI; i++)
- if (id[i] == ch_id)
- return i + 1;
-
- return 0;
-}
-
-/* If all channel threads of the DMAC are busy */
-static inline bool dmac_busy(struct rk29_pl330_dmac *dmac)
-{
- struct pl330_info *pi = dmac->pi;
-
- return (dmac->busy_chan < pi->pcfg.num_chan) ? false : true;
-}
-
-/*
- * Returns the number of free channels that
- * can be handled by this dmac only.
- */
-static unsigned ch_onlyby_dmac(struct rk29_pl330_dmac *dmac)
-{
- enum dma_ch *id = dmac->peri;
- struct rk29_pl330_dmac *d;
- struct rk29_pl330_chan *ch;
- unsigned found, count = 0;
- enum dma_ch p;
- int i;
-
- for (i = 0; i < PL330_MAX_PERI; i++) {
- p = id[i];
- ch = id_to_chan(p);
-
- if (p == DMACH_MAX || !chan_free(ch))
- continue;
-
- found = 0;
- list_for_each_entry(d, &dmac_list, node) {
- if (d != dmac && iface_of_dmac(d, ch->id)) {
- found = 1;
- break;
- }
- }
- if (!found)
- count++;
- }
-
- return count;
-}
-
-/*
- * Measure of suitability of 'dmac' handling 'ch'
- *
- * 0 indicates 'dmac' can not handle 'ch' either
- * because it is not supported by the hardware or
- * because all dmac channels are currently busy.
- *
- * >0 vlaue indicates 'dmac' has the capability.
- * The bigger the value the more suitable the dmac.
- */
-#define MAX_SUIT UINT_MAX
-#define MIN_SUIT 0
-
-static unsigned suitablility(struct rk29_pl330_dmac *dmac,
- struct rk29_pl330_chan *ch)
-{
- struct pl330_info *pi = dmac->pi;
- enum dma_ch *id = dmac->peri;
- struct rk29_pl330_dmac *d;
- unsigned s;
- int i;
-
- s = MIN_SUIT;
- /* If all the DMAC channel threads are busy */
- if (dmac_busy(dmac))
- return s;
-
- for (i = 0; i < PL330_MAX_PERI; i++)
- if (id[i] == ch->id)
- break;
-
- /* If the 'dmac' can't talk to 'ch' */
- if (i == PL330_MAX_PERI)
- return s;
-
- s = MAX_SUIT;
- list_for_each_entry(d, &dmac_list, node) {
- /*
- * If some other dmac can talk to this
- * peri and has some channel free.
- */
- if (d != dmac && iface_of_dmac(d, ch->id) && !dmac_busy(d)) {
- s = 0;
- break;
- }
- }
- if (s)
- return s;
-
- s = 100;
-
- /* Good if free chans are more, bad otherwise */
- s += (pi->pcfg.num_chan - dmac->busy_chan) - ch_onlyby_dmac(dmac);
-
- return s;
-}
-
-/* More than one DMAC may have capability to transfer data with the
- * peripheral. This function assigns most suitable DMAC to manage the
- * channel and hence communicate with the peripheral.
- */
-static struct rk29_pl330_dmac *map_chan_to_dmac(struct rk29_pl330_chan *ch)
-{
- struct rk29_pl330_dmac *d, *dmac = NULL;
- unsigned sn, sl = MIN_SUIT;
-
- list_for_each_entry(d, &dmac_list, node) {
- sn = suitablility(d, ch);
-
- if (sn == MAX_SUIT)
- return d;
-
- if (sn > sl)
- dmac = d;
- }
-
- return dmac;
-}
-
-/* Acquire the channel for peripheral 'id' */
-static struct rk29_pl330_chan *chan_acquire(const enum dma_ch id)
-{
- struct rk29_pl330_chan *ch = id_to_chan(id);
- struct rk29_pl330_dmac *dmac;
-
- /* If the channel doesn't exist or is already acquired */
- if (!ch || !chan_free(ch)) {
- ch = NULL;
- goto acq_exit;
- }
-
- dmac = map_chan_to_dmac(ch);
- /* If couldn't map */
- if (!dmac) {
- ch = NULL;
- goto acq_exit;
- }
-
- dmac->busy_chan++;
- ch->dmac = dmac;
-
-acq_exit:
- return ch;
-}
-
-/* Delete xfer from the queue */
-static inline void del_from_queue(struct rk29_pl330_xfer *xfer)
-{
- struct rk29_pl330_xfer *t;
- struct rk29_pl330_chan *ch;
- int found;
-
- if (!xfer)
- return;
-
- ch = xfer->chan;
-
- /* Make sure xfer is in the queue */
- found = 0;
- list_for_each_entry(t, &ch->xfer_list, node)
- if (t == xfer) {
- found = 1;
- break;
- }
-
- if (!found)
- return;
-
- /* If xfer is last entry in the queue */
- if (xfer->node.next == &ch->xfer_list)
- t = list_entry(ch->xfer_list.next,
- struct rk29_pl330_xfer, node);
- else
- t = list_entry(xfer->node.next,
- struct rk29_pl330_xfer, node);
-
- /* If there was only one node left */
- if (t == xfer)
- ch->xfer_head = NULL;
- else if (ch->xfer_head == xfer)
- ch->xfer_head = t;
-
- list_del(&xfer->node);
-}
-
-/* Provides pointer to the next xfer in the queue.
- * If CIRCULAR option is set, the list is left intact,
- * otherwise the xfer is removed from the list.
- * Forced delete 'pluck' can be set to override the CIRCULAR option.
- */
-static struct rk29_pl330_xfer *get_from_queue(struct rk29_pl330_chan *ch,
- int pluck)
-{
- struct rk29_pl330_xfer *xfer = ch->xfer_head;
-
- if (!xfer)
- return NULL;
-
- /* If xfer is last entry in the queue */
- if (xfer->node.next == &ch->xfer_list)
- ch->xfer_head = list_entry(ch->xfer_list.next,
- struct rk29_pl330_xfer, node);
- else
- ch->xfer_head = list_entry(xfer->node.next,
- struct rk29_pl330_xfer, node);
-
- if (pluck || !(ch->options & RK29_DMAF_CIRCULAR))
- del_from_queue(xfer);
-
- return xfer;
-}
-
-static inline void add_to_queue(struct rk29_pl330_chan *ch,
- struct rk29_pl330_xfer *xfer, int front)
-{
- struct pl330_xfer *xt;
-
- /* If queue empty */
- if (ch->xfer_head == NULL)
- ch->xfer_head = xfer;
-
- xt = &ch->xfer_head->px;
- /* If the head already submitted (CIRCULAR head) */
- if (ch->options & RK29_DMAF_CIRCULAR &&
- (xt == ch->req[0].x || xt == ch->req[1].x))
- ch->xfer_head = xfer;
-
- /* If this is a resubmission, it should go at the head */
- if (front) {
- ch->xfer_head = xfer;
- list_add(&xfer->node, &ch->xfer_list);
- } else {
- list_add_tail(&xfer->node, &ch->xfer_list);
- }
-}
-
-static inline void _finish_off(struct rk29_pl330_xfer *xfer,
- enum rk29_dma_buffresult res, int ffree)
-{
- struct rk29_pl330_chan *ch;
-
- if (!xfer)
- return;
-
- ch = xfer->chan;
-
- /* Do callback */
-
- if (ch->callback_fn)
- ch->callback_fn(xfer->token, xfer->px.bytes, res);
-
- /* Force Free or if buffer is not needed anymore */
- if (ffree || !(ch->options & RK29_DMAF_CIRCULAR))
- kmem_cache_free(ch->dmac->kmcache, xfer);
-}
-
-static inline int rk29_pl330_submit(struct rk29_pl330_chan *ch,
- struct pl330_req *r)
-{
- struct rk29_pl330_xfer *xfer;
- int ret = 0;
-
- /* If already submitted */
- if (r->x)
- return 0;
-
- xfer = get_from_queue(ch, 0);
-
- if (xfer) {
- r->x = &xfer->px;
-
- /* Use max bandwidth for M<->M xfers */
- if (r->rqtype == MEMTOMEM) {
- struct pl330_info *pi = xfer->chan->dmac->pi;
- int burst = 1 << ch->rqcfg.brst_size;
- u32 bytes = r->x->bytes;
- int bl;
-
- bl = pi->pcfg.data_bus_width / 8;
- bl *= pi->pcfg.data_buf_dep;
- bl /= burst;
-
- /* src/dst_burst_len can't be more than 16 */
- if (bl > 16)
- bl = 16;
-
- while (bl > 1) {
- if (!(bytes % (bl * burst)))
- break;
- bl--;
- }
-
- ch->rqcfg.brst_len = bl;
- }else {
- if(ch->id == DMACH_EMMC)
- ch->rqcfg.brst_len = 16; //yk
- //else
- // ch->rqcfg.brst_len = 1;
- }
-
- ret = pl330_submit_req(ch->pl330_chan_id, r);
-
- /* If submission was successful */
- if (!ret) {
- ch->lrq = r; /* latest submitted req */
- return 0;
- }
-
- r->x = NULL;
-
- /* If both of the PL330 ping-pong buffers filled */
- if (ret == -EAGAIN) {
- dev_err(ch->dmac->pi->dev, "%s:%d!\n",
- __func__, __LINE__);
- /* Queue back again */
- add_to_queue(ch, xfer, 1);
- ret = 0;
- } else {
- dev_err(ch->dmac->pi->dev, "%s:%d!\n",
- __func__, __LINE__);
- _finish_off(xfer, RK29_RES_ERR, 0);
- }
- }
-
- return ret;
-}
-
-static void rk29_pl330_rq(struct rk29_pl330_chan *ch,
- struct pl330_req *r, enum pl330_op_err err)
-{
- unsigned long flags;
- struct rk29_pl330_xfer *xfer;
- struct pl330_xfer *xl;
- enum rk29_dma_buffresult res;
-
- spin_lock_irqsave(&res_lock, flags);
- xl = r->x;
- if (!r->infiniteloop) {
- r->x = NULL;
-
- rk29_pl330_submit(ch, r);
- }
-
- spin_unlock_irqrestore(&res_lock, flags);
-
- /* Map result to rk29 DMA API */
- if (err == PL330_ERR_NONE)
- res = RK29_RES_OK;
- else if (err == PL330_ERR_ABORT)
- res = RK29_RES_ABORT;
- else
- res = RK29_RES_ERR;
-
- /* If last request had some xfer */
- if (!r->infiniteloop) {
- if (xl) {
- xfer = container_of(xl, struct rk29_pl330_xfer, px);
- _finish_off(xfer, res, 0);
- } else {
- dev_info(ch->dmac->pi->dev, "%s:%d No Xfer?!\n",
- __func__, __LINE__);
- }
- } else {
- /* Do callback */
-
- xfer = container_of(xl, struct rk29_pl330_xfer, px);
- if (ch->callback_fn)
- ch->callback_fn(xfer->token, xfer->px.bytes, res);
- }
-}
-
-static void rk29_pl330_rq0(void *token, enum pl330_op_err err)
-{
- struct pl330_req *r = token;
- struct rk29_pl330_chan *ch = container_of(r,
- struct rk29_pl330_chan, req[0]);
- rk29_pl330_rq(ch, r, err);
-}
-
-static void rk29_pl330_rq1(void *token, enum pl330_op_err err)
-{
- struct pl330_req *r = token;
- struct rk29_pl330_chan *ch = container_of(r,
- struct rk29_pl330_chan, req[1]);
- rk29_pl330_rq(ch, r, err);
-}
-
-/* Release an acquired channel */
-static void chan_release(struct rk29_pl330_chan *ch)
-{
- struct rk29_pl330_dmac *dmac;
-
- if (chan_free(ch))
- return;
-
- dmac = ch->dmac;
- ch->dmac = NULL;
- dmac->busy_chan--;
-}
-
-int rk29_dma_ctrl(enum dma_ch id, enum rk29_chan_op op)
-{
- struct rk29_pl330_xfer *xfer;
- enum pl330_chan_op pl330op;
- struct rk29_pl330_chan *ch;
- unsigned long flags;
- int idx, ret;
-
- spin_lock_irqsave(&res_lock, flags);
-
- ch = id_to_chan(id);
-
- if (!ch || chan_free(ch)) {
- ret = -EINVAL;
- goto ctrl_exit;
- }
-
- switch (op) {
- case RK29_DMAOP_START:
- /* Make sure both reqs are enqueued */
- idx = (ch->lrq == &ch->req[0]) ? 1 : 0;
- rk29_pl330_submit(ch, &ch->req[idx]);
- rk29_pl330_submit(ch, &ch->req[1 - idx]);
- pl330op = PL330_OP_START;
- break;
-
- case RK29_DMAOP_STOP:
- pl330op = PL330_OP_ABORT;
- break;
-
- case RK29_DMAOP_FLUSH:
- pl330op = PL330_OP_FLUSH;
- break;
-
- case RK29_DMAOP_PAUSE:
- case RK29_DMAOP_RESUME:
- case RK29_DMAOP_TIMEOUT:
- case RK29_DMAOP_STARTED:
- spin_unlock_irqrestore(&res_lock, flags);
- return 0;
-
- default:
- spin_unlock_irqrestore(&res_lock, flags);
- return -EINVAL;
- }
-
- ret = pl330_chan_ctrl(ch->pl330_chan_id, pl330op);
-
- if (pl330op == PL330_OP_START) {
- spin_unlock_irqrestore(&res_lock, flags);
- return ret;
- }
-
- idx = (ch->lrq == &ch->req[0]) ? 1 : 0;
-
- /* Abort the current xfer */
- if (ch->req[idx].x) {
- xfer = container_of(ch->req[idx].x,
- struct rk29_pl330_xfer, px);
-
- /* Drop xfer during FLUSH */
- if (pl330op == PL330_OP_FLUSH)
- del_from_queue(xfer);
-
- ch->req[idx].x = NULL;
-
- spin_unlock_irqrestore(&res_lock, flags);
- _finish_off(xfer, RK29_RES_ABORT,
- pl330op == PL330_OP_FLUSH ? 1 : 0);
- spin_lock_irqsave(&res_lock, flags);
- }
-
- /* Flush the whole queue */
- if (pl330op == PL330_OP_FLUSH) {
-
- if (ch->req[1 - idx].x) {
- xfer = container_of(ch->req[1 - idx].x,
- struct rk29_pl330_xfer, px);
-
- del_from_queue(xfer);
-
- ch->req[1 - idx].x = NULL;
-
- spin_unlock_irqrestore(&res_lock, flags);
- _finish_off(xfer, RK29_RES_ABORT, 1);
- spin_lock_irqsave(&res_lock, flags);
- }
-
- /* Finish off the remaining in the queue */
- xfer = ch->xfer_head;
- while (xfer) {
-
- del_from_queue(xfer);
-
- spin_unlock_irqrestore(&res_lock, flags);
- _finish_off(xfer, RK29_RES_ABORT, 1);
- spin_lock_irqsave(&res_lock, flags);
-
- xfer = ch->xfer_head;
- }
- }
-
-ctrl_exit:
- spin_unlock_irqrestore(&res_lock, flags);
-
- return ret;
-}
-EXPORT_SYMBOL(rk29_dma_ctrl);
-//hhb@rock-chips.com 2012-06-14
-int rk29_dma_enqueue_ring(enum dma_ch id, void *token,
- dma_addr_t addr, int size, int numofblock, bool sev)
-{
- struct rk29_pl330_chan *ch;
- struct rk29_pl330_xfer *xfer;
- unsigned long flags;
- int idx, ret = 0;
-
- spin_lock_irqsave(&res_lock, flags);
-
- ch = id_to_chan(id);
-
- /* Error if invalid or free channel */
- if (!ch || chan_free(ch)) {
- ret = -EINVAL;
- goto enq_exit;
- }
-
- /* Error if size is unaligned */
- if (ch->rqcfg.brst_size && size % (1 << ch->rqcfg.brst_size)) {
- ret = -EINVAL;
- goto enq_exit;
- }
-
- xfer = kmem_cache_alloc(ch->dmac->kmcache, GFP_ATOMIC);
- if (!xfer) {
- ret = -ENOMEM;
- goto enq_exit;
- }
-
- xfer->token = token;
- xfer->chan = ch;
- xfer->px.bytes = size;
- xfer->px.next = NULL; /* Single request */
-
- /* For rk29 DMA API, direction is always fixed for all xfers */
- if (ch->req[0].rqtype == MEMTODEV) {
- xfer->px.src_addr = addr;
- xfer->px.dst_addr = ch->sdaddr;
- } else {
- xfer->px.src_addr = ch->sdaddr;
- xfer->px.dst_addr = addr;
- }
-
- add_to_queue(ch, xfer, 0);
-
- /* Try submitting on either request */
- idx = (ch->lrq == &ch->req[0]) ? 1 : 0;
-
- if (!ch->req[idx].x) {
- ch->req[idx].infiniteloop = numofblock;
- if(numofblock)
- ch->req[idx].infiniteloop_sev = sev;
- rk29_pl330_submit(ch, &ch->req[idx]);
- } else {
- ch->req[1 - idx].infiniteloop = numofblock;
- if(numofblock)
- ch->req[1 - idx].infiniteloop_sev = sev;
- rk29_pl330_submit(ch, &ch->req[1 - idx]);
- }
- spin_unlock_irqrestore(&res_lock, flags);
-
- if (ch->options & RK29_DMAF_AUTOSTART)
- rk29_dma_ctrl(id, RK29_DMAOP_START);
-
- return 0;
-
-enq_exit:
- spin_unlock_irqrestore(&res_lock, flags);
-
- return ret;
-}
-EXPORT_SYMBOL(rk29_dma_enqueue_ring);
-
-int rk29_dma_enqueue(enum dma_ch id, void *token,
- dma_addr_t addr, int size)
-{
- return rk29_dma_enqueue_ring(id, token, addr, size, 0, false);
-}
-EXPORT_SYMBOL(rk29_dma_enqueue);
-
-int rk29_dma_request(enum dma_ch id,
- struct rk29_dma_client *client,
- void *dev)
-{
- struct rk29_pl330_dmac *dmac;
- struct rk29_pl330_chan *ch;
- unsigned long flags;
- int ret = 0;
-
- spin_lock_irqsave(&res_lock, flags);
-
- ch = chan_acquire(id);
- if (!ch) {
- ret = -EBUSY;
- goto req_exit;
- }
-
- dmac = ch->dmac;
-
- ch->pl330_chan_id = pl330_request_channel(id, dmac->pi);
- if (!ch->pl330_chan_id) {
- chan_release(ch);
- ret = -EBUSY;
- goto req_exit;
- }
-
- ch->client = client;
- ch->options = 0; /* Clear any option */
- ch->callback_fn = NULL; /* Clear any callback */
- ch->lrq = NULL;
-
- ch->rqcfg.brst_size = 2; /* Default word size */
- ch->rqcfg.swap = SWAP_NO;
- ch->rqcfg.scctl = SCCTRL0; /* Noncacheable and nonbufferable */
- ch->rqcfg.dcctl = DCCTRL0; /* Noncacheable and nonbufferable */
- ch->rqcfg.privileged = 0;
- ch->rqcfg.insnaccess = 0;
-
- /* Set invalid direction */
- ch->req[0].rqtype = DEVTODEV;
- ch->req[1].rqtype = ch->req[0].rqtype;
-
- ch->req[0].cfg = &ch->rqcfg;
- ch->req[1].cfg = ch->req[0].cfg;
-
- ch->req[0].peri = iface_of_dmac(dmac, id) - 1; /* Original index */
- ch->req[1].peri = ch->req[0].peri;
-
- ch->req[0].token = &ch->req[0];
- ch->req[0].xfer_cb = rk29_pl330_rq0;
- ch->req[1].token = &ch->req[1];
- ch->req[1].xfer_cb = rk29_pl330_rq1;
-
- ch->req[0].x = NULL;
- ch->req[1].x = NULL;
-
- /* Reset xfer list */
- INIT_LIST_HEAD(&ch->xfer_list);
- ch->xfer_head = NULL;
-
-req_exit:
- spin_unlock_irqrestore(&res_lock, flags);
-
- return ret;
-}
-EXPORT_SYMBOL(rk29_dma_request);
-
-int rk29_dma_free(enum dma_ch id, struct rk29_dma_client *client)
-{
- struct rk29_pl330_chan *ch;
- struct rk29_pl330_xfer *xfer;
- unsigned long flags;
- int ret = 0;
- unsigned idx;
-
- spin_lock_irqsave(&res_lock, flags);
-
- ch = id_to_chan(id);
-
- if (!ch || chan_free(ch))
- goto free_exit;
-
- /* Refuse if someone else wanted to free the channel */
- if (ch->client != client) {
- ret = -EBUSY;
- goto free_exit;
- }
-
- /* Stop any active xfer, Flushe the queue and do callbacks */
- pl330_chan_ctrl(ch->pl330_chan_id, PL330_OP_FLUSH);
-
- /* Abort the submitted requests */
- idx = (ch->lrq == &ch->req[0]) ? 1 : 0;
-
- if (ch->req[idx].x) {
- xfer = container_of(ch->req[idx].x,
- struct rk29_pl330_xfer, px);
-
- ch->req[idx].x = NULL;
- del_from_queue(xfer);
-
- spin_unlock_irqrestore(&res_lock, flags);
- _finish_off(xfer, RK29_RES_ABORT, 1);
- spin_lock_irqsave(&res_lock, flags);
- }
-
- if (ch->req[1 - idx].x) {
- xfer = container_of(ch->req[1 - idx].x,
- struct rk29_pl330_xfer, px);
-
- ch->req[1 - idx].x = NULL;
- del_from_queue(xfer);
-
- spin_unlock_irqrestore(&res_lock, flags);
- _finish_off(xfer, RK29_RES_ABORT, 1);
- spin_lock_irqsave(&res_lock, flags);
- }
-
- /* Pluck and Abort the queued requests in order */
- do {
- xfer = get_from_queue(ch, 1);
-
- spin_unlock_irqrestore(&res_lock, flags);
- _finish_off(xfer, RK29_RES_ABORT, 1);
- spin_lock_irqsave(&res_lock, flags);
- } while (xfer);
-
- ch->client = NULL;
-
- pl330_release_channel(ch->pl330_chan_id);
-
- ch->pl330_chan_id = NULL;
-
- chan_release(ch);
-
-free_exit:
- spin_unlock_irqrestore(&res_lock, flags);
-
- return ret;
-}
-EXPORT_SYMBOL(rk29_dma_free);
-
-/**
-* yk@rk 20110622
-* config the burst length when dma init or brst_len change
-* every peripher has to determine burst width and length by its FIFO
-*
-* param:
-* id: dma request id
-* xferunit: burst width in byte
-* brst_len: burst length every transfer
-*/
-int rk29_dma_config(enum dma_ch id, int xferunit, int brst_len)
-{
- struct rk29_pl330_chan *ch;
- unsigned long flags;
- int i, ret = 0;
-
- spin_lock_irqsave(&res_lock, flags);
-
- ch = id_to_chan(id);
-
- if (!ch || chan_free(ch)) {
- ret = -EINVAL;
- goto cfg_exit;
- }
-#if 0
- int dbwidth;
- struct pl330_info *pi;
-
- pi = ch->dmac->pi;
- dbwidth = pi->pcfg.data_bus_width / 8;
-
- /* Max size of xfer can be pcfg.data_bus_width */
- if (xferunit > dbwidth) {
- ret = -EINVAL;
- goto cfg_exit;
- }
-
- i = 0;
- while (xferunit != (1 << i))
- i++;
-
- /* If valid value */
- if (xferunit == (1 << i))
- ch->rqcfg.brst_size = i;
- else
- ret = -EINVAL;
-#else
- i = 0;
- while (xferunit != (1 << i))
- i++;
-
- if(xferunit > 8)
- goto cfg_exit;
- else
- ch->rqcfg.brst_size = i;
-
- if(brst_len > 16)
- goto cfg_exit;
- else
- ch->rqcfg.brst_len = brst_len;
-#endif
-cfg_exit:
- spin_unlock_irqrestore(&res_lock, flags);
-
- return ret;
-}
-EXPORT_SYMBOL(rk29_dma_config);
-
-/* Options that are supported by this driver */
-#define RK29_PL330_FLAGS (RK29_DMAF_CIRCULAR | RK29_DMAF_AUTOSTART)
-
-int rk29_dma_setflags(enum dma_ch id, unsigned int options)
-{
- struct rk29_pl330_chan *ch;
- unsigned long flags;
- int ret = 0;
-
- spin_lock_irqsave(&res_lock, flags);
-
- ch = id_to_chan(id);
-
- if (!ch || chan_free(ch) || options & ~(RK29_PL330_FLAGS))
- ret = -EINVAL;
- else
- ch->options = options;
-
- spin_unlock_irqrestore(&res_lock, flags);
-
- return 0;
-}
-EXPORT_SYMBOL(rk29_dma_setflags);
-
-int rk29_dma_set_buffdone_fn(enum dma_ch id, rk29_dma_cbfn_t rtn)
-{
- struct rk29_pl330_chan *ch;
- unsigned long flags;
- int ret = 0;
-
- spin_lock_irqsave(&res_lock, flags);
-
- ch = id_to_chan(id);
-
- if (!ch || chan_free(ch))
- ret = -EINVAL;
- else
- ch->callback_fn = rtn;
-
- spin_unlock_irqrestore(&res_lock, flags);
-
- return ret;
-}
-EXPORT_SYMBOL(rk29_dma_set_buffdone_fn);
-
-int rk29_dma_devconfig(enum dma_ch id, enum rk29_dmasrc source,
- unsigned long address)
-{
- struct rk29_pl330_chan *ch;
- unsigned long flags;
- int ret = 0;
-
- spin_lock_irqsave(&res_lock, flags);
-
- ch = id_to_chan(id);
-
- if (!ch || chan_free(ch)) {
- ret = -EINVAL;
- goto devcfg_exit;
- }
-
- switch (source) {
- case RK29_DMASRC_HW: /* P->M */
- ch->req[0].rqtype = DEVTOMEM;
- ch->req[1].rqtype = DEVTOMEM;
- ch->rqcfg.src_inc = 0;
- ch->rqcfg.dst_inc = 1;
- break;
- case RK29_DMASRC_MEM: /* M->P */
- ch->req[0].rqtype = MEMTODEV;
- ch->req[1].rqtype = MEMTODEV;
- ch->rqcfg.src_inc = 1;
- ch->rqcfg.dst_inc = 0;
- break;
- case RK29_DMASRC_MEMTOMEM:
- ch->req[0].rqtype = MEMTOMEM;
- ch->req[1].rqtype = MEMTOMEM;
- ch->rqcfg.src_inc = 1;
- ch->rqcfg.dst_inc = 1;
- break;
- default:
- ret = -EINVAL;
- goto devcfg_exit;
- }
-
- ch->sdaddr = address;
-
-devcfg_exit:
- spin_unlock_irqrestore(&res_lock, flags);
-
- return ret;
-}
-EXPORT_SYMBOL(rk29_dma_devconfig);
-
-int rk29_dma_getposition(enum dma_ch id, dma_addr_t *src, dma_addr_t *dst)
-{
- struct rk29_pl330_chan *ch = id_to_chan(id);
- struct pl330_chanstatus status;
- int ret;
-
- if (!ch || chan_free(ch))
- return -EINVAL;
-
- ret = pl330_chan_status(ch->pl330_chan_id, &status);
- if (ret < 0)
- return ret;
-
- *src = status.src_addr;
- *dst = status.dst_addr;
-
- return 0;
-}
-EXPORT_SYMBOL(rk29_dma_getposition);
-
-static irqreturn_t pl330_irq_handler(int irq, void *data)
-{
- if (pl330_update(data))
- return IRQ_HANDLED;
- else
- return IRQ_NONE;
-}
-
-static int pl330_probe(struct platform_device *pdev)
-{
- struct rk29_pl330_dmac *rk29_pl330_dmac;
- struct rk29_pl330_platdata *pl330pd;
- struct pl330_info *pl330_info;
- struct resource *res;
- int i, n = 0, ret = 0, irq;
-
- pl330pd = pdev->dev.platform_data;
-
- /* Can't do without the list of _32_ peripherals */
- if (!pl330pd || !pl330pd->peri) {
- dev_err(&pdev->dev, "platform data missing!\n");
- return -ENODEV;
- }
-
- pl330_info = kzalloc(sizeof(*pl330_info), GFP_KERNEL);
- if (!pl330_info)
- return -ENOMEM;
-
- pl330_info->pl330_data = NULL;
- pl330_info->dev = &pdev->dev;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res) {
- ret = -ENODEV;
- goto probe_err1;
- }
-
- request_mem_region(res->start, resource_size(res), pdev->name);
-
- pl330_info->base = ioremap(res->start, resource_size(res));
- if (!pl330_info->base) {
- ret = -ENXIO;
- goto probe_err2;
- }
-
- res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
- if (!res) {
- ret = -ENODEV;
- goto probe_err3;
- }
-
- for(irq = res->start; irq <= res->end; irq++){
- ret = request_irq(irq, pl330_irq_handler, 0,
- dev_name(&pdev->dev), pl330_info);
- if(0 == ret){
- n++;
- }
- }
- if(0 == n){
- goto probe_err4;
- }
-#if 0
- irq = platform_get_irq(pdev, 0);
- if (irq < 0) {
- ret = irq;
- goto probe_err3;
- }
-
- ret = request_irq(irq, pl330_irq_handler, 0,
- dev_name(&pdev->dev), pl330_info);
-
- if(pdev->id == 0){
- WARN_ON(request_irq(IRQ_DMAC0_1, pl330_irq_handler, 0,
- dev_name(&pdev->dev), pl330_info) < 0);
- WARN_ON(request_irq(IRQ_DMAC0_2, pl330_irq_handler, 0,
- dev_name(&pdev->dev), pl330_info) < 0);
- WARN_ON(request_irq(IRQ_DMAC0_3, pl330_irq_handler, 0,
- dev_name(&pdev->dev), pl330_info) < 0);
- }
-
- if(pdev->id == 1){
- WARN_ON(request_irq(IRQ_DMAC1_1, pl330_irq_handler, 0,
- dev_name(&pdev->dev), pl330_info) < 0);
- WARN_ON(request_irq(IRQ_DMAC1_2, pl330_irq_handler, 0,
- dev_name(&pdev->dev), pl330_info) < 0);
- WARN_ON(request_irq(IRQ_DMAC1_3, pl330_irq_handler, 0,
- dev_name(&pdev->dev), pl330_info) < 0);
- WARN_ON(request_irq(IRQ_DMAC1_4, pl330_irq_handler, 0,
- dev_name(&pdev->dev), pl330_info) < 0);
- }
-
- if (ret)
- goto probe_err4;
-#endif
- ret = pl330_add(pl330_info);
- if (ret)
- goto probe_err5;
-
- /* Allocate a new DMAC */
- rk29_pl330_dmac = kmalloc(sizeof(*rk29_pl330_dmac), GFP_KERNEL);
- if (!rk29_pl330_dmac) {
- ret = -ENOMEM;
- goto probe_err6;
- }
-
- /* Hook the info */
- rk29_pl330_dmac->pi = pl330_info;
-
- /* No busy channels */
- rk29_pl330_dmac->busy_chan = 0;
-
- rk29_pl330_dmac->kmcache = kmem_cache_create(dev_name(&pdev->dev),
- sizeof(struct rk29_pl330_xfer), 0, 0, NULL);
-
- if (!rk29_pl330_dmac->kmcache) {
- ret = -ENOMEM;
- goto probe_err7;
- }
-
- /* Get the list of peripherals */
- rk29_pl330_dmac->peri = pl330pd->peri;
-
- /* Attach to the list of DMACs */
- list_add_tail(&rk29_pl330_dmac->node, &dmac_list);
-
- /* Create a channel for each peripheral in the DMAC
- * that is, if it doesn't already exist
- */
- for (i = 0; i < PL330_MAX_PERI; i++)
- if (rk29_pl330_dmac->peri[i] != DMACH_MAX)
- chan_add(rk29_pl330_dmac->peri[i]);
-
- printk(KERN_INFO
- "Loaded driver for PL330 DMAC-%d %s\n", pdev->id, pdev->name);
- printk(KERN_INFO
- "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
- pl330_info->pcfg.data_buf_dep,
- pl330_info->pcfg.data_bus_width / 8, pl330_info->pcfg.num_chan,
- pl330_info->pcfg.num_peri, pl330_info->pcfg.num_events);
-
- return 0;
-
-probe_err7:
- kfree(rk29_pl330_dmac);
-probe_err6:
- pl330_del(pl330_info);
-probe_err5:
- free_irq(irq, pl330_info);
-probe_err4:
-probe_err3:
- iounmap(pl330_info->base);
-probe_err2:
- release_mem_region(res->start, resource_size(res));
-probe_err1:
- kfree(pl330_info);
-
- return ret;
-}
-
-static int pl330_remove(struct platform_device *pdev)
-{
- struct rk29_pl330_dmac *dmac, *d;
- struct rk29_pl330_chan *ch;
- struct rk29_pl330_chan *ch_temp;
- unsigned long flags;
- int del, found;
-
- if (!pdev->dev.platform_data)
- return -EINVAL;
-
- spin_lock_irqsave(&res_lock, flags);
-
- found = 0;
- list_for_each_entry(d, &dmac_list, node)
- if (d->pi->dev == &pdev->dev) {
- found = 1;
- break;
- }
-
- if (!found) {
- spin_unlock_irqrestore(&res_lock, flags);
- return 0;
- }
-
- dmac = d;
-
- /* Remove all Channels that are managed only by this DMAC */
- list_for_each_entry_safe(ch, ch_temp, &chan_list, node) {
-
- /* Only channels that are handled by this DMAC */
- if (iface_of_dmac(dmac, ch->id))
- del = 1;
- else
- continue;
-
- /* Don't remove if some other DMAC has it too */
- list_for_each_entry(d, &dmac_list, node)
- if (d != dmac && iface_of_dmac(d, ch->id)) {
- del = 0;
- break;
- }
-
- if (del) {
- spin_unlock_irqrestore(&res_lock, flags);
- rk29_dma_free(ch->id, ch->client);
- spin_lock_irqsave(&res_lock, flags);
- list_del(&ch->node);
- kfree(ch);
- }
- }
-
- /* Remove the DMAC */
- list_del(&dmac->node);
- kfree(dmac);
-
- spin_unlock_irqrestore(&res_lock, flags);
-
- return 0;
-}
-
-static struct platform_driver pl330_driver = {
- .driver = {
- .owner = THIS_MODULE,
- .name = "rk29-pl330",
- },
- .probe = pl330_probe,
- .remove = pl330_remove,
-};
-
-static int __init pl330_init(void)
-{
- return platform_driver_register(&pl330_driver);
-}
-arch_initcall_sync(pl330_init);
-
-static void __exit pl330_exit(void)
-{
- platform_driver_unregister(&pl330_driver);
- return;
-}
-module_exit(pl330_exit);
-
-MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
-MODULE_DESCRIPTION("Driver for PL330 DMA Controller");
-MODULE_LICENSE("GPL");
+++ /dev/null
-/*
- *
- * arch/arm/plat-rk/dma_memcpy_test.c
- *
- * Copyright (C) 2012 Rochchip.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * Author: hhb@rock-chips.com
- * Create Date: 2012.03.26
- *
- * HOW TO USE IT?
- * enter the follow command at command line
- * echo 1 > sys/module/dma_memcpy_test/parameters/debug enable log output,default is enable
- * echo 1000 > sys/module/dma_memcpy_test/parameters/interval set dma transfer interval, default is 1000ms
- * echo 1 > /sys/devices/platform/dma_memcpy.0/dmamemcpy to start the dma test
- *
- */
-
-/*
-* Driver Version Note
-*
-*v1.0 : 1. add dam thread number from 2 to 8;
-*
-*
-*/
-#define VERSION_AND_TIME "dma_memcpy_test.c v1.0 2012-08-13"
-
-#include <linux/module.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/wait.h>
-#include <linux/sched.h>
-#include <linux/delay.h>
-#include <mach/io.h>
-#include <plat/dma-pl330.h>
-#include <asm/uaccess.h>
-#include <asm/current.h>
-
-#define DMA_TEST_BUFFER_SIZE 4096
-static DECLARE_WAIT_QUEUE_HEAD(wq);
-static int wq_condition = 0;
-
-struct Dma_MemToMem {
- dma_addr_t SrcAddr; //phy address
- dma_addr_t DstAddr;
- unsigned char* src; //virtual address
- unsigned char* dst;
- int MenSize;
-};
-//wait_queue_head_t dma_memcpy_wait;
-
-//enable log output
-static int debug = 8;
-module_param(debug,int,S_IRUGO|S_IWUSR);
-//set dma transfer interval time (unit ms)
-static int interval = 1000;
-module_param(interval,int,S_IRUGO|S_IWUSR);
-
-
-#define DMA_THREAD 2
-#define MEMCPY_DMA_DBG(fmt...) {if(debug > 0) printk(fmt);}
-
-static struct Dma_MemToMem DmaMemInfo0;
-static struct Dma_MemToMem DmaMemInfo1;
-static struct Dma_MemToMem DmaMemInfo2;
-static struct Dma_MemToMem DmaMemInfo3;
-static struct Dma_MemToMem DmaMemInfo4;
-static struct Dma_MemToMem DmaMemInfo5;
-static struct Dma_MemToMem DmaMemInfo6;
-static struct Dma_MemToMem DmaMemInfo7;
-
-static struct rk29_dma_client rk29_dma_memcpy_client = {
- .name = "rk29-dma-memcpy",
-};
-
-static void rk29_dma_memcpy_callback0(void *buf_id, int size, enum rk29_dma_buffresult result)
-{
- if(result != RK29_RES_OK) {
- MEMCPY_DMA_DBG("%s error:%d\n", __func__, result);
- return;
- }
- MEMCPY_DMA_DBG("%s ok\n", __func__);
- if(wq_condition == 0) {
- wq_condition = 1;
- wake_up_interruptible(&wq);
- }
-
-}
-
-static void rk29_dma_memcpy_callback1(void *buf_id, int size, enum rk29_dma_buffresult result)
-{
- if(result != RK29_RES_OK) {
- MEMCPY_DMA_DBG("%s error:%d\n", __func__, result);
- }
- else
- MEMCPY_DMA_DBG("%s ok\n", __func__);
-}
-
-static void rk29_dma_memcpy_callback2(void *buf_id, int size, enum rk29_dma_buffresult result)
-{
- if(result != RK29_RES_OK) {
- MEMCPY_DMA_DBG("%s error:%d\n", __func__, result);
- }
- else
- MEMCPY_DMA_DBG("%s ok\n", __func__);
-}
-
-static void rk29_dma_memcpy_callback3(void *buf_id, int size, enum rk29_dma_buffresult result)
-{
- if(result != RK29_RES_OK) {
- MEMCPY_DMA_DBG("%s error:%d\n", __func__, result);
- }
- else
- MEMCPY_DMA_DBG("%s ok\n", __func__);
-}
-
-static void rk29_dma_memcpy_callback4(void *buf_id, int size, enum rk29_dma_buffresult result)
-{
- if(result != RK29_RES_OK) {
- MEMCPY_DMA_DBG("%s error:%d\n", __func__, result);
- }
- else
- MEMCPY_DMA_DBG("%s ok\n", __func__);
-}
-
-static void rk29_dma_memcpy_callback5(void *buf_id, int size, enum rk29_dma_buffresult result)
-{
- if(result != RK29_RES_OK) {
- MEMCPY_DMA_DBG("%s error:%d\n", __func__, result);
- }
- else
- MEMCPY_DMA_DBG("%s ok\n", __func__);
-}
-
-
-static void rk29_dma_memcpy_callback6(void *buf_id, int size, enum rk29_dma_buffresult result)
-{
- if(result != RK29_RES_OK) {
- MEMCPY_DMA_DBG("%s error:%d\n", __func__, result);
- }
- else
- MEMCPY_DMA_DBG("%s ok\n", __func__);
-}
-
-
-static void rk29_dma_memcpy_callback7(void *buf_id, int size, enum rk29_dma_buffresult result)
-{
- if(result != RK29_RES_OK) {
- MEMCPY_DMA_DBG("%s error:%d\n", __func__, result);
- }
- else
- MEMCPY_DMA_DBG("%s ok\n", __func__);
-}
-
-//int slecount = 0;
-static ssize_t memcpy_dma_read(struct device *device,struct device_attribute *attr, char *argv)
-{
-
- return 0;
-}
-
-static ssize_t memcpy_dma_write(struct device *device, struct device_attribute *attr, const char *argv, size_t count)
-{
- int i;
- MEMCPY_DMA_DBG("memcpy_dma_write\n");
-
- switch(DMA_THREAD) {
- case 8:
- memset(DmaMemInfo7.src, 0x77, DMA_TEST_BUFFER_SIZE);
- memset(DmaMemInfo7.dst, 0x0, DMA_TEST_BUFFER_SIZE);
- rk29_dma_devconfig(DMACH_DMAC7_MEMTOMEM, RK29_DMASRC_MEMTOMEM, DmaMemInfo7.SrcAddr);
- rk29_dma_enqueue(DMACH_DMAC7_MEMTOMEM, NULL, DmaMemInfo7.DstAddr, DmaMemInfo7.MenSize);
- case 7:
- memset(DmaMemInfo6.src, 0x66, DMA_TEST_BUFFER_SIZE);
- memset(DmaMemInfo6.dst, 0x0, DMA_TEST_BUFFER_SIZE);
- rk29_dma_devconfig(DMACH_DMAC6_MEMTOMEM, RK29_DMASRC_MEMTOMEM, DmaMemInfo6.SrcAddr);
- rk29_dma_enqueue(DMACH_DMAC6_MEMTOMEM, NULL, DmaMemInfo6.DstAddr, DmaMemInfo6.MenSize);
- case 6:
- memset(DmaMemInfo5.src, 0x55, DMA_TEST_BUFFER_SIZE);
- memset(DmaMemInfo5.dst, 0x0, DMA_TEST_BUFFER_SIZE);
- rk29_dma_devconfig(DMACH_DMAC5_MEMTOMEM, RK29_DMASRC_MEMTOMEM, DmaMemInfo5.SrcAddr);
- rk29_dma_enqueue(DMACH_DMAC5_MEMTOMEM, NULL, DmaMemInfo5.DstAddr, DmaMemInfo5.MenSize);
- case 5:
- memset(DmaMemInfo4.src, 0x44, DMA_TEST_BUFFER_SIZE);
- memset(DmaMemInfo4.dst, 0x0, DMA_TEST_BUFFER_SIZE);
- rk29_dma_devconfig(DMACH_DMAC4_MEMTOMEM, RK29_DMASRC_MEMTOMEM, DmaMemInfo4.SrcAddr);
- rk29_dma_enqueue(DMACH_DMAC4_MEMTOMEM, NULL, DmaMemInfo4.DstAddr, DmaMemInfo4.MenSize);
- case 4:
- memset(DmaMemInfo3.src, 0x33, DMA_TEST_BUFFER_SIZE);
- memset(DmaMemInfo3.dst, 0x0, DMA_TEST_BUFFER_SIZE);
- rk29_dma_devconfig(DMACH_DMAC3_MEMTOMEM, RK29_DMASRC_MEMTOMEM, DmaMemInfo3.SrcAddr);
- rk29_dma_enqueue(DMACH_DMAC3_MEMTOMEM, NULL, DmaMemInfo3.DstAddr, DmaMemInfo3.MenSize);
- case 3:
- memset(DmaMemInfo2.src, 0x22, DMA_TEST_BUFFER_SIZE);
- memset(DmaMemInfo2.dst, 0x0, DMA_TEST_BUFFER_SIZE);
- rk29_dma_devconfig(DMACH_DMAC2_MEMTOMEM, RK29_DMASRC_MEMTOMEM, DmaMemInfo2.SrcAddr);
- rk29_dma_enqueue(DMACH_DMAC2_MEMTOMEM, NULL, DmaMemInfo2.DstAddr, DmaMemInfo2.MenSize);
- case 2:
- memset(DmaMemInfo1.src, 0xaa, DMA_TEST_BUFFER_SIZE);
- memset(DmaMemInfo1.dst, 0x0, DMA_TEST_BUFFER_SIZE);
- rk29_dma_devconfig(DMACH_DMAC1_MEMTOMEM, RK29_DMASRC_MEMTOMEM, DmaMemInfo1.SrcAddr);
- rk29_dma_enqueue(DMACH_DMAC1_MEMTOMEM, NULL, DmaMemInfo1.DstAddr, DmaMemInfo1.MenSize);
- case 1:
- memset(DmaMemInfo0.src, 0xaa, DMA_TEST_BUFFER_SIZE);
- memset(DmaMemInfo0.dst, 0x0, DMA_TEST_BUFFER_SIZE);
- rk29_dma_devconfig(DMACH_DMAC0_MEMTOMEM, RK29_DMASRC_MEMTOMEM, DmaMemInfo0.SrcAddr);
- rk29_dma_enqueue(DMACH_DMAC0_MEMTOMEM, NULL, DmaMemInfo0.DstAddr, DmaMemInfo0.MenSize);
- break;
- default:
- printk("%s no channel\n", __func__);
- break;
-
- }
-
- switch(DMA_THREAD) {
- case 8:
- rk29_dma_ctrl(DMACH_DMAC7_MEMTOMEM, RK29_DMAOP_START);
- case 7:
- rk29_dma_ctrl(DMACH_DMAC6_MEMTOMEM, RK29_DMAOP_START);
- case 6:
- rk29_dma_ctrl(DMACH_DMAC5_MEMTOMEM, RK29_DMAOP_START);
- case 5:
- rk29_dma_ctrl(DMACH_DMAC4_MEMTOMEM, RK29_DMAOP_START);
- case 4:
- rk29_dma_ctrl(DMACH_DMAC3_MEMTOMEM, RK29_DMAOP_START);
- case 3:
- rk29_dma_ctrl(DMACH_DMAC2_MEMTOMEM, RK29_DMAOP_START);
- case 2:
- rk29_dma_ctrl(DMACH_DMAC1_MEMTOMEM, RK29_DMAOP_START);
- case 1:
- rk29_dma_ctrl(DMACH_DMAC0_MEMTOMEM, RK29_DMAOP_START);
- break;
- default:
- printk("%s no channel\n", __func__);
- break;
-
- }
-
- wait_event_interruptible_timeout(wq, wq_condition, 500);
-
- switch(DMA_THREAD) {
- case 8:
- for(i = 0; i < 16; i++) {
- MEMCPY_DMA_DBG("src7:%x", *(DmaMemInfo7.src + i*(DMA_TEST_BUFFER_SIZE/16)));
- MEMCPY_DMA_DBG(" -> dst7:%x\n", *(DmaMemInfo7.dst + i*(DMA_TEST_BUFFER_SIZE/16)));
- }
- case 7:
- for(i = 0; i < 16; i++) {
- MEMCPY_DMA_DBG("src6:%x", *(DmaMemInfo6.src + i*(DMA_TEST_BUFFER_SIZE/16)));
- MEMCPY_DMA_DBG(" -> dst6:%x\n", *(DmaMemInfo6.dst + i*(DMA_TEST_BUFFER_SIZE/16)));
- }
- case 6:
- for(i = 0; i < 16; i++) {
- MEMCPY_DMA_DBG("src5:%x", *(DmaMemInfo5.src + i*(DMA_TEST_BUFFER_SIZE/16)));
- MEMCPY_DMA_DBG(" -> dst5:%x\n", *(DmaMemInfo5.dst + i*(DMA_TEST_BUFFER_SIZE/16)));
- }
- case 5:
- for(i = 0; i < 16; i++) {
- MEMCPY_DMA_DBG("src4:%x", *(DmaMemInfo4.src + i*(DMA_TEST_BUFFER_SIZE/16)));
- MEMCPY_DMA_DBG(" -> dst4:%x\n", *(DmaMemInfo4.dst + i*(DMA_TEST_BUFFER_SIZE/16)));
- }
- case 4:
- for(i = 0; i < 16; i++) {
- MEMCPY_DMA_DBG("src3:%x", *(DmaMemInfo3.src + i*(DMA_TEST_BUFFER_SIZE/16)));
- MEMCPY_DMA_DBG(" -> dst3:%x\n", *(DmaMemInfo3.dst + i*(DMA_TEST_BUFFER_SIZE/16)));
- }
- case 3:
- for(i = 0; i < 16; i++) {
- MEMCPY_DMA_DBG("src2:%x", *(DmaMemInfo2.src + i*(DMA_TEST_BUFFER_SIZE/16)));
- MEMCPY_DMA_DBG(" -> dst2:%x\n", *(DmaMemInfo2.dst + i*(DMA_TEST_BUFFER_SIZE/16)));
- }
- case 2:
- for(i = 0; i < 16; i++) {
- MEMCPY_DMA_DBG("src1:%x", *(DmaMemInfo1.src + i*(DMA_TEST_BUFFER_SIZE/16)));
- MEMCPY_DMA_DBG(" -> dst1:%x\n", *(DmaMemInfo1.dst + i*(DMA_TEST_BUFFER_SIZE/16)));
- }
- case 1:
- for(i = 0; i < 16; i++) {
- MEMCPY_DMA_DBG("src0:%x", *(DmaMemInfo0.src + i*(DMA_TEST_BUFFER_SIZE/16)));
- MEMCPY_DMA_DBG(" -> dst0:%x\n", *(DmaMemInfo0.dst + i*(DMA_TEST_BUFFER_SIZE/16)));
- }
- break;
- default:
- printk("%s no channel\n", __func__);
- break;
- }
-
- wq_condition = 0;
- return 0;
-}
-
-static DEVICE_ATTR(dmamemcpy, S_IRUGO|S_IALLUGO, memcpy_dma_read, memcpy_dma_write);
-
-
-static int __devinit dma_memcpy_probe(struct platform_device *pdev)
-{
- int ret;
-
- ret = device_create_file(&pdev->dev, &dev_attr_dmamemcpy);
- printk(">>>>>>>>>>>>>>>>>>>>> dam_test_probe <<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
-
- switch(DMA_THREAD) {
- case 8:
- if (rk29_dma_request(DMACH_DMAC7_MEMTOMEM, &rk29_dma_memcpy_client, NULL) == -EBUSY) {
- printk("DMACH_DMAC7_MEMTOMEM request fail\n");
- } else {
- rk29_dma_config(DMACH_DMAC7_MEMTOMEM, 8, 16);
- rk29_dma_set_buffdone_fn(DMACH_DMAC7_MEMTOMEM, rk29_dma_memcpy_callback7);
- DmaMemInfo7.src = dma_alloc_coherent(NULL, DMA_TEST_BUFFER_SIZE, &DmaMemInfo7.SrcAddr, GFP_KERNEL);
- DmaMemInfo7.dst = dma_alloc_coherent(NULL, DMA_TEST_BUFFER_SIZE, &DmaMemInfo7.DstAddr, GFP_KERNEL);
- DmaMemInfo7.MenSize = DMA_TEST_BUFFER_SIZE;
- if(DmaMemInfo7.src == NULL || DmaMemInfo7.dst == NULL)
- printk("DMACH_DMAC7_MEMTOMEM alloc memory fail\n");
- else
- printk("DMACH_DMAC7_MEMTOMEM request sucess\n");
- }
-
- case 7:
- if (rk29_dma_request(DMACH_DMAC6_MEMTOMEM, &rk29_dma_memcpy_client, NULL) == -EBUSY) {
- printk("DMACH_DMAC6_MEMTOMEM request fail\n");
- } else {
- rk29_dma_config(DMACH_DMAC6_MEMTOMEM, 8, 16);
- rk29_dma_set_buffdone_fn(DMACH_DMAC6_MEMTOMEM, rk29_dma_memcpy_callback6);
- DmaMemInfo6.src = dma_alloc_coherent(NULL, DMA_TEST_BUFFER_SIZE, &DmaMemInfo6.SrcAddr, GFP_KERNEL);
- DmaMemInfo6.dst = dma_alloc_coherent(NULL, DMA_TEST_BUFFER_SIZE, &DmaMemInfo6.DstAddr, GFP_KERNEL);
- DmaMemInfo6.MenSize = DMA_TEST_BUFFER_SIZE;
- if(DmaMemInfo6.src == NULL || DmaMemInfo6.dst == NULL)
- printk("DMACH_DMAC6_MEMTOMEM alloc memory fail\n");
- else
- printk("DMACH_DMAC6_MEMTOMEM request sucess\n");
- }
-
- case 6:
- if (rk29_dma_request(DMACH_DMAC5_MEMTOMEM, &rk29_dma_memcpy_client, NULL) == -EBUSY) {
- printk("DMACH_DMAC5_MEMTOMEM request fail\n");
- } else {
- rk29_dma_config(DMACH_DMAC5_MEMTOMEM, 8, 16);
- rk29_dma_set_buffdone_fn(DMACH_DMAC5_MEMTOMEM, rk29_dma_memcpy_callback5);
- DmaMemInfo5.src = dma_alloc_coherent(NULL, DMA_TEST_BUFFER_SIZE, &DmaMemInfo5.SrcAddr, GFP_KERNEL);
- DmaMemInfo5.dst = dma_alloc_coherent(NULL, DMA_TEST_BUFFER_SIZE, &DmaMemInfo5.DstAddr, GFP_KERNEL);
- DmaMemInfo5.MenSize = DMA_TEST_BUFFER_SIZE;
- if(DmaMemInfo5.src == NULL || DmaMemInfo5.dst == NULL)
- printk("DMACH_DMAC5_MEMTOMEM alloc memory fail\n");
- else
- printk("DMACH_DMAC5_MEMTOMEM request sucess\n");
- }
-
- case 5:
- if (rk29_dma_request(DMACH_DMAC4_MEMTOMEM, &rk29_dma_memcpy_client, NULL) == -EBUSY) {
- printk("DMACH_DMAC4_MEMTOMEM request fail\n");
- } else {
- rk29_dma_config(DMACH_DMAC4_MEMTOMEM, 8, 16);
- rk29_dma_set_buffdone_fn(DMACH_DMAC4_MEMTOMEM, rk29_dma_memcpy_callback4);
- DmaMemInfo4.src = dma_alloc_coherent(NULL, DMA_TEST_BUFFER_SIZE, &DmaMemInfo4.SrcAddr, GFP_KERNEL);
- DmaMemInfo4.dst = dma_alloc_coherent(NULL, DMA_TEST_BUFFER_SIZE, &DmaMemInfo4.DstAddr, GFP_KERNEL);
- DmaMemInfo4.MenSize = DMA_TEST_BUFFER_SIZE;
- if(DmaMemInfo4.src == NULL || DmaMemInfo4.dst == NULL)
- printk("DMACH_DMAC4_MEMTOMEM alloc memory fail\n");
- else
- printk("DMACH_DMAC4_MEMTOMEM request sucess\n");
- }
-
- case 4:
- if (rk29_dma_request(DMACH_DMAC3_MEMTOMEM, &rk29_dma_memcpy_client, NULL) == -EBUSY) {
- printk("DMACH_DMAC3_MEMTOMEM request fail\n");
- } else {
- rk29_dma_config(DMACH_DMAC3_MEMTOMEM, 8, 16);
- rk29_dma_set_buffdone_fn(DMACH_DMAC3_MEMTOMEM, rk29_dma_memcpy_callback3);
- DmaMemInfo3.src = dma_alloc_coherent(NULL, DMA_TEST_BUFFER_SIZE, &DmaMemInfo3.SrcAddr, GFP_KERNEL);
- DmaMemInfo3.dst = dma_alloc_coherent(NULL, DMA_TEST_BUFFER_SIZE, &DmaMemInfo3.DstAddr, GFP_KERNEL);
- DmaMemInfo3.MenSize = DMA_TEST_BUFFER_SIZE;
- if(DmaMemInfo3.src == NULL || DmaMemInfo3.dst == NULL)
- printk("DMACH_DMAC3_MEMTOMEM alloc memory fail\n");
- else
- printk("DMACH_DMAC3_MEMTOMEM request sucess\n");
- }
-
- case 3:
- if (rk29_dma_request(DMACH_DMAC2_MEMTOMEM, &rk29_dma_memcpy_client, NULL) == -EBUSY) {
- printk("DMACH_DMAC2_MEMTOMEM request fail\n");
- } else {
- rk29_dma_config(DMACH_DMAC2_MEMTOMEM, 8, 16);
- rk29_dma_set_buffdone_fn(DMACH_DMAC2_MEMTOMEM, rk29_dma_memcpy_callback2);
- DmaMemInfo2.src = dma_alloc_coherent(NULL, DMA_TEST_BUFFER_SIZE, &DmaMemInfo2.SrcAddr, GFP_KERNEL);
- DmaMemInfo2.dst = dma_alloc_coherent(NULL, DMA_TEST_BUFFER_SIZE, &DmaMemInfo2.DstAddr, GFP_KERNEL);
- DmaMemInfo2.MenSize = DMA_TEST_BUFFER_SIZE;
- if(DmaMemInfo2.src == NULL || DmaMemInfo2.dst == NULL)
- printk("DMACH_DMAC2_MEMTOMEM alloc memory fail\n");
- else
- printk("DMACH_DMAC2_MEMTOMEM request sucess\n");
- }
-
- case 2:
- if (rk29_dma_request(DMACH_DMAC1_MEMTOMEM, &rk29_dma_memcpy_client, NULL) == -EBUSY) {
- printk("DMACH_DMAC1_MEMTOMEM request fail\n");
- } else {
- rk29_dma_config(DMACH_DMAC1_MEMTOMEM, 8, 16);
- rk29_dma_set_buffdone_fn(DMACH_DMAC1_MEMTOMEM, rk29_dma_memcpy_callback1);
- DmaMemInfo1.src = dma_alloc_coherent(NULL, DMA_TEST_BUFFER_SIZE, &DmaMemInfo1.SrcAddr, GFP_KERNEL);
- DmaMemInfo1.dst = dma_alloc_coherent(NULL, DMA_TEST_BUFFER_SIZE, &DmaMemInfo1.DstAddr, GFP_KERNEL);
- DmaMemInfo1.MenSize = DMA_TEST_BUFFER_SIZE;
- if(DmaMemInfo1.src == NULL || DmaMemInfo1.dst == NULL)
- printk("DMACH_DMAC1_MEMTOMEM alloc memory fail\n");
- else
- printk("DMACH_DMAC1_MEMTOMEM request sucess\n");
- }
-
- case 1:
- if (rk29_dma_request(DMACH_DMAC0_MEMTOMEM, &rk29_dma_memcpy_client, NULL) == -EBUSY) {
- printk("DMACH_DMAC0_MEMTOMEM request fail\n");
- } else {
- rk29_dma_config(DMACH_DMAC0_MEMTOMEM, 8, 16);
- rk29_dma_set_buffdone_fn(DMACH_DMAC0_MEMTOMEM, rk29_dma_memcpy_callback0);
- DmaMemInfo0.src = dma_alloc_coherent(NULL, DMA_TEST_BUFFER_SIZE, &DmaMemInfo0.SrcAddr, GFP_KERNEL);
- DmaMemInfo0.dst = dma_alloc_coherent(NULL, DMA_TEST_BUFFER_SIZE, &DmaMemInfo0.DstAddr, GFP_KERNEL);
- DmaMemInfo0.MenSize = DMA_TEST_BUFFER_SIZE;
- if(DmaMemInfo0.src == NULL || DmaMemInfo0.dst == NULL)
- printk("DMACH_DMAC0_MEMTOMEM alloc memory fail\n");
- else
- printk("DMACH_DMAC0_MEMTOMEM request sucess\n");
- }
- break;
- default:
- printk("%s no channel\n", __func__);
- break;
- }
- return 0;
-}
-
-static int __devexit dma_memcpy_remove(struct platform_device *pdev)
-{
- device_remove_file(&pdev->dev, &dev_attr_dmamemcpy);
-
- return 0;
-}
-
-static struct platform_driver dma_mempcy_driver = {
- .driver = {
- .name = "dma_memcpy",
- .owner = THIS_MODULE,
- },
- .probe = dma_memcpy_probe,
- .remove = __devexit_p(dma_memcpy_remove),
-};
-
-struct platform_device rk29_device_dma_cpy = {
- .name = "dma_memcpy",
- .id = 0,
-
-};
-
-
-static int __init dma_test_init(void)
-{
- platform_device_register(&rk29_device_dma_cpy);
- return platform_driver_register(&dma_mempcy_driver);
-}
-
-static void __exit dma_test_exit(void)
-{
- platform_driver_unregister(&dma_mempcy_driver);
-}
-
-module_init(dma_test_init);
-module_exit(dma_test_exit);
-
-MODULE_DESCRIPTION("RK29 PL330 Dma Test Deiver");
-MODULE_LICENSE("GPL V2");
-MODULE_AUTHOR("ZhenFu Fang <fzf@rock-chips.com>");
-MODULE_AUTHOR("Hong Huibin<hhb@rock-chips.com>");
+++ /dev/null
-/* arch/arm/mach-rk30/rk30_dvfs.c\r
- *\r
- * Copyright (C) 2012 ROCKCHIP, Inc.\r
- *\r
- * This software is licensed under the terms of the GNU General Public\r
- * License version 2, as published by the Free Software Foundation, and\r
- * may be copied, distributed, and modified under those terms.\r
- *\r
- * This program is distributed in the hope that it will be useful,\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- * GNU General Public License for more details.\r
- *\r
- */\r
-\r
-#include <linux/kernel.h>\r
-#include <linux/err.h>\r
-#include <linux/spinlock.h>\r
-#include <linux/list.h>\r
-#include <linux/slab.h>\r
-#include <linux/clk.h>\r
-#include <linux/cpufreq.h>\r
-#include <mach/dvfs.h>\r
-#include <mach/clock.h>\r
-#include <linux/regulator/consumer.h>\r
-#include <linux/delay.h>\r
-#include <linux/io.h>\r
-#include <linux/hrtimer.h>\r
-\r
-#define MHz (1000 * 1000)\r
-static LIST_HEAD(rk_dvfs_tree);\r
-static DEFINE_MUTEX(mutex);\r
-static DEFINE_MUTEX(rk_dvfs_mutex);\r
-\r
-static int dump_dbg_map(char *buf);\r
-\r
-#define PD_ON 1\r
-#define PD_OFF 0\r
-#define DVFS_STR_DISABLE(on) ((on)?"enable":"disable")\r
-\r
-#define get_volt_up_delay(new_volt, old_volt) \\r
- ((new_volt) > (old_volt) ? (((new_volt) - (old_volt)) >> 9) : 0)\r
-\r
-\r
-\r
-/**************************************vd regulator functions***************************************/\r
-static void dvfs_volt_up_delay(struct vd_node *vd,int new_volt, int old_volt)\r
-{\r
- int u_time;\r
- if(new_volt<=old_volt)\r
- return;\r
- if(vd->volt_time_flag>0) \r
- u_time=regulator_set_voltage_time(vd->regulator,old_volt,new_volt);\r
- else\r
- u_time=-1; \r
- if(u_time<0)// regulator is not suported time,useing default time\r
- {\r
- DVFS_DBG("%s:vd %s is not suported getting delay time,so we use default\n",\r
- __FUNCTION__,vd->name);\r
- u_time=((new_volt) - (old_volt)) >> 9;\r
- }\r
- DVFS_DBG("%s:vd %s volt %d to %d delay %d us\n",__FUNCTION__,vd->name,\r
- old_volt,new_volt,u_time);\r
- if (u_time >= 1000) {\r
- mdelay(u_time / 1000);\r
- udelay(u_time % 1000);\r
- DVFS_ERR("regulator set vol delay is larger 1ms,old is %d,new is %d\n",old_volt,new_volt);\r
- } else if (u_time) {\r
- udelay(u_time);\r
- } \r
-}\r
-int dvfs_regulator_set_voltage_readback(struct regulator *regulator, int min_uV, int max_uV)\r
-{\r
- int ret = 0, read_back = 0;\r
- ret = dvfs_regulator_set_voltage(regulator, max_uV, max_uV);\r
- if (ret < 0) {\r
- DVFS_ERR("%s now read back to check voltage\n", __func__);\r
-\r
- /* read back to judge if it is already effect */\r
- mdelay(2);\r
- read_back = dvfs_regulator_get_voltage(regulator);\r
- if (read_back == max_uV) {\r
- DVFS_ERR("%s set ERROR but already effected, volt=%d\n", __func__, read_back);\r
- ret = 0;\r
- } else {\r
- DVFS_ERR("%s set ERROR AND NOT effected, volt=%d\n", __func__, read_back);\r
- }\r
- }\r
- return ret;\r
-}\r
-// for clk enable case to get vd regulator info\r
-void clk_enable_dvfs_regulator_check(struct vd_node *vd)\r
-{\r
- vd->cur_volt = dvfs_regulator_get_voltage(vd->regulator);\r
- if(vd->cur_volt<=0)\r
- {\r
- vd->volt_set_flag = DVFS_SET_VOLT_FAILURE;\r
- }\r
- vd->volt_set_flag = DVFS_SET_VOLT_SUCCESS;\r
-}\r
-\r
-static void dvfs_get_vd_regulator_volt_list(struct vd_node *vd)\r
-{\r
- unsigned i,selector=dvfs_regulator_count_voltages(vd->regulator);\r
- int sel_volt=0;\r
- \r
- if(selector>VD_VOL_LIST_CNT)\r
- selector=VD_VOL_LIST_CNT;\r
- \r
- mutex_lock(&mutex);\r
- for (i = 0; i<selector; i++) {\r
- sel_volt=dvfs_regulator_list_voltage(vd->regulator,i);\r
- if(sel_volt<=0)\r
- { \r
- DVFS_WARNING("%s : selector=%u,but volt <=0\n",vd->name,i);\r
- break;\r
- }\r
- vd->volt_list[i]=sel_volt; \r
- DVFS_DBG("%s:selector=%u,volt %d\n",vd->name,i,sel_volt);\r
- }\r
- vd->n_voltages=selector;\r
- mutex_unlock(&mutex);\r
-}\r
-\r
-// >= volt\r
-static int vd_regulator_round_volt_max(struct vd_node *vd, int volt)\r
-{\r
- int sel_volt;\r
- unsigned i;\r
- \r
- for (i = 0; i<vd->n_voltages; i++) {\r
- sel_volt=vd->volt_list[i];\r
- if(sel_volt<=0)\r
- { \r
- DVFS_WARNING("%s:list_volt : selector=%u,but volt <=0\n",__FUNCTION__,i);\r
- return -1;\r
- }\r
- if(sel_volt>=volt)\r
- return sel_volt; \r
- }\r
- return -1;\r
-}\r
-// >=volt\r
-static int vd_regulator_round_volt_min(struct vd_node *vd, int volt)\r
-{\r
- int sel_volt;\r
- unsigned i;\r
- \r
- for (i = 0; i<vd->n_voltages; i++) {\r
- sel_volt=vd->volt_list[i];\r
- if(sel_volt<=0)\r
- { \r
- DVFS_WARNING("%s:list_volt : selector=%u,but volt <=0\n",__FUNCTION__,i);\r
- return -1;\r
- }\r
- if(sel_volt>volt)\r
- {\r
- if(i>0)\r
- return vd->volt_list[i-1];\r
- else\r
- return -1;\r
- } \r
- }\r
- return -1;\r
-}\r
-\r
-// >=volt\r
-int vd_regulator_round_volt(struct vd_node *vd, int volt,int flags)\r
-{\r
- if(!vd->n_voltages)\r
- return -1;\r
- if(flags==VD_LIST_RELATION_L)\r
- return vd_regulator_round_volt_min(vd,volt);\r
- else\r
- return vd_regulator_round_volt_max(vd,volt); \r
-}\r
-EXPORT_SYMBOL(vd_regulator_round_volt);\r
-\r
-\r
-static void dvfs_table_round_volt(struct clk_node *dvfs_clk)\r
-{\r
- int i,test_volt;\r
-\r
- if(!dvfs_clk->dvfs_table||!dvfs_clk->vd||IS_ERR_OR_NULL(dvfs_clk->vd->regulator))\r
- return;\r
- mutex_lock(&mutex);\r
- for (i = 0; (dvfs_clk->dvfs_table[i].frequency != CPUFREQ_TABLE_END); i++) {\r
-\r
- test_volt=vd_regulator_round_volt(dvfs_clk->vd,dvfs_clk->dvfs_table[i].index,VD_LIST_RELATION_H);\r
- if(test_volt<=0)\r
- { \r
- DVFS_WARNING("clk %s:round_volt : is %d,but list <=0\n",dvfs_clk->name,dvfs_clk->dvfs_table[i].index);\r
- break;\r
- }\r
- DVFS_DBG("clk %s:round_volt %d to %d\n",dvfs_clk->name,dvfs_clk->dvfs_table[i].index,test_volt);\r
- dvfs_clk->dvfs_table[i].index=test_volt; \r
- }\r
- mutex_unlock(&mutex);\r
-}\r
-void dvfs_vd_get_regulator_volt_time_info(struct vd_node *vd)\r
-{\r
- if(vd->volt_time_flag<=0)// check regulator support get uping vol timer\r
- {\r
- vd->volt_time_flag=dvfs_regulator_set_voltage_time(vd->regulator,vd->cur_volt,vd->cur_volt+200*1000);\r
- if(vd->volt_time_flag<0)\r
- {\r
- DVFS_DBG("%s,vd %s volt_time is no support\n",__FUNCTION__,vd->name);\r
- }\r
- else\r
- {\r
- DVFS_DBG("%s,vd %s volt_time is support,up 200mv need delay %d us\n",__FUNCTION__,vd->name,vd->volt_time_flag);\r
-\r
- } \r
- }\r
-}\r
-\r
-void dvfs_vd_get_regulator_mode_info(struct vd_node *vd)\r
-{\r
- //REGULATOR_MODE_FAST\r
- if(vd->mode_flag<=0)// check regulator support get uping vol timer\r
- {\r
- vd->mode_flag=dvfs_regulator_get_mode(vd->regulator);\r
- if(vd->mode_flag==REGULATOR_MODE_FAST||vd->mode_flag==REGULATOR_MODE_NORMAL\r
- ||vd->mode_flag==REGULATOR_MODE_IDLE||vd->mode_flag==REGULATOR_MODE_STANDBY)\r
- {\r
- if(dvfs_regulator_set_mode(vd->regulator,vd->mode_flag)<0)\r
- {\r
- vd->mode_flag=0;// check again\r
- }\r
- \r
- }\r
- if(vd->mode_flag>0)\r
- {\r
- DVFS_DBG("%s,vd %s mode(now is %d) support\n",__FUNCTION__,vd->name,vd->mode_flag);\r
- }\r
- else\r
- {\r
- DVFS_DBG("%s,vd %s mode is not support now check\n",__FUNCTION__,vd->name);\r
-\r
- }\r
- \r
- }\r
-}\r
-struct regulator *dvfs_get_regulator(char *regulator_name) \r
-{\r
- struct vd_node *vd;\r
- list_for_each_entry(vd, &rk_dvfs_tree, node) {\r
- if (strcmp(regulator_name, vd->regulator_name) == 0) {\r
- return vd->regulator;\r
- }\r
- }\r
- return NULL;\r
-}\r
-\r
-int dvfs_get_rate_range(struct clk *clk)\r
-{\r
- struct clk_node *dvfs_clk = clk_get_dvfs_info(clk);\r
- struct cpufreq_frequency_table *table;\r
- int i = 0;\r
-\r
- if (!dvfs_clk)\r
- return -1;\r
-\r
- dvfs_clk->min_rate = 0;\r
- dvfs_clk->max_rate = 0;\r
-\r
- table = dvfs_clk->dvfs_table;\r
- for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) {\r
- dvfs_clk->max_rate = table[i].frequency / 1000 * 1000 * 1000;\r
- if (i == 0)\r
- dvfs_clk->min_rate = table[i].frequency / 1000 * 1000 * 1000;\r
- }\r
-\r
- DVFS_DBG("%s: clk %s, limit rate [min, max] = [%lu, %lu]\n",\r
- __func__, dvfs_clk->name, dvfs_clk->min_rate, dvfs_clk->max_rate);\r
-\r
- return 0;\r
-}\r
-\r
-/**************************************dvfs clocks functions***************************************/\r
-int dvfs_clk_enable_limit(struct clk *clk, unsigned int min_rate, unsigned max_rate)\r
-{\r
- struct clk_node *dvfs_clk;\r
- u32 rate = 0, ret = 0;\r
- dvfs_clk = clk_get_dvfs_info(clk);\r
- if (IS_ERR_OR_NULL(dvfs_clk)) {\r
- DVFS_ERR("%s: can not get dvfs clk(%s)\n", __func__, clk->name);\r
- return -1;\r
-\r
- }\r
-\r
- if (dvfs_clk->vd && dvfs_clk->vd->vd_dvfs_target){\r
- mutex_lock(&rk_dvfs_mutex);\r
-\r
- dvfs_clk->freq_limit_en = 1;\r
- dvfs_clk->min_rate = min_rate;\r
- dvfs_clk->max_rate = max_rate;\r
- if (clk->last_set_rate == 0)\r
- rate = clk_get_rate(clk);\r
- else\r
- rate = clk->last_set_rate;\r
- ret = dvfs_clk->vd->vd_dvfs_target(clk, rate);\r
- clk->last_set_rate = rate;\r
-\r
- mutex_unlock(&rk_dvfs_mutex);\r
- }\r
-\r
- DVFS_DBG("%s: clk(%s) last_set_rate=%d; [min_rate, max_rate]=[%d, %d]\n",\r
- __func__, clk->name, clk->last_set_rate, dvfs_clk->min_rate, dvfs_clk->max_rate);\r
- return 0;\r
-}\r
-\r
-int dvfs_clk_disable_limit(struct clk *clk)\r
-{\r
- struct clk_node *dvfs_clk;\r
- u32 ret = 0;\r
- dvfs_clk = clk_get_dvfs_info(clk);\r
- if (IS_ERR_OR_NULL(dvfs_clk)) {\r
- DVFS_ERR("%s: can not get dvfs clk(%s)\n", __func__, clk->name);\r
- return -1;\r
-\r
- }\r
-\r
- if (dvfs_clk->vd && dvfs_clk->vd->vd_dvfs_target){\r
- mutex_lock(&rk_dvfs_mutex);\r
- /* To reset dvfs_clk->min_rate/max_rate */\r
- dvfs_get_rate_range(clk);\r
-\r
- dvfs_clk->freq_limit_en = 0;\r
- ret = dvfs_clk->vd->vd_dvfs_target(clk, clk->last_set_rate);\r
-\r
- mutex_unlock(&rk_dvfs_mutex);\r
- }\r
-\r
- DVFS_DBG("%s: clk(%s) last_set_rate=%d; [min_rate, max_rate]=[%d, %d]\n",\r
- __func__, clk->name, clk->last_set_rate, dvfs_clk->min_rate, dvfs_clk->max_rate);\r
- return 0;\r
-}\r
-\r
-int dvfs_vd_clk_set_rate(struct clk *clk, unsigned long rate)\r
-{\r
- int ret = -1;\r
- struct clk_node *dvfs_info=clk_get_dvfs_info(clk);\r
- \r
- DVFS_DBG("%s(%s(%lu))\n", __func__, dvfs_info->name, rate);\r
-\r
- #if 0 // judge by reference func in rk\r
- if (dvfs_support_clk_set_rate(dvfs_info)==false) {\r
- DVFS_ERR("dvfs func:%s is not support!\n", __func__);\r
- return ret;\r
- }\r
- #endif\r
- \r
- if(dvfs_info->vd&&dvfs_info->vd->vd_dvfs_target){\r
- // mutex_lock(&vd->dvfs_mutex);\r
- mutex_lock(&rk_dvfs_mutex);\r
- ret = dvfs_info->vd->vd_dvfs_target(clk, rate);\r
- mutex_unlock(&rk_dvfs_mutex);\r
- // mutex_unlock(&vd->dvfs_mutex);\r
- }\r
- else\r
- {\r
- DVFS_WARNING("%s(%s),vd is no target callback\n", __func__, clk->name); \r
- return -1;\r
- }\r
- DVFS_DBG("%s(%s(%lu)),is end\n", __func__, clk->name, rate);\r
- return ret;\r
-}\r
-EXPORT_SYMBOL(dvfs_vd_clk_set_rate);\r
-\r
-int dvfs_vd_clk_disable(struct clk *clk, int on)\r
-{\r
- int ret = -1;\r
- struct clk_node *dvfs_info=clk_get_dvfs_info(clk); \r
- DVFS_DBG("%s(%s(%s,%lu))\n", __func__, dvfs_info->name, DVFS_STR_DISABLE(on),clk_get_rate(clk));\r
-\r
-\r
- #if 0 // judge by reference func in rk\r
- if (dvfs_support_clk_disable(dvfs_info)==false) {\r
- DVFS_ERR("dvfs func:%s is not support!\n", __func__);\r
- return ret;\r
- }\r
- #endif\r
- \r
- if(dvfs_info->vd&&dvfs_info->vd->vd_clk_disable_target){\r
- // mutex_lock(&vd->dvfs_mutex);\r
- mutex_lock(&rk_dvfs_mutex);\r
- ret = dvfs_info->vd->vd_clk_disable_target(clk, on);\r
- mutex_unlock(&rk_dvfs_mutex);\r
- // mutex_unlock(&vd->dvfs_mutex);\r
- }\r
- else\r
- {\r
- DVFS_WARNING("%s(%s),vd is no target callback\n", __func__, clk->name); \r
- return -1;\r
- }\r
- DVFS_DBG("%s(%s(%s)),is end\n", __func__, dvfs_info->name, DVFS_STR_DISABLE(on));\r
-\r
- return ret;\r
-}\r
-\r
-EXPORT_SYMBOL(dvfs_vd_clk_disable);\r
-\r
-static void dvfs_table_round_clk_rate(struct clk_node *dvfs_clk)\r
-{\r
- int i;\r
- unsigned long temp_rate;\r
- int rate;\r
- int flags;\r
- \r
- if(!dvfs_clk->dvfs_table||dvfs_clk->clk==NULL||is_suport_round_rate(dvfs_clk->clk)<0)\r
- return;\r
- \r
- mutex_lock(&mutex);\r
- for (i = 0; (dvfs_clk->dvfs_table[i].frequency != CPUFREQ_TABLE_END); i++) {\r
- //ddr rate = real rate+flags\r
- flags=dvfs_clk->dvfs_table[i].frequency%1000;\r
- rate=(dvfs_clk->dvfs_table[i].frequency/1000)*1000;\r
- temp_rate=clk_round_rate(dvfs_clk->clk,rate*1000);\r
- if(temp_rate<=0)\r
- { \r
- DVFS_WARNING("clk %s:round_clk_rate : is %d,but round <=0",dvfs_clk->name,dvfs_clk->dvfs_table[i].frequency);\r
- break;\r
- }\r
- \r
- /* Set rate unit as MHZ */\r
- if (temp_rate % MHz != 0)\r
- temp_rate = (temp_rate / MHz + 1) * MHz;\r
-\r
- temp_rate = (temp_rate / 1000) + flags;\r
- \r
- DVFS_DBG("clk %s round_clk_rate %d to %d\n",\r
- dvfs_clk->name,dvfs_clk->dvfs_table[i].frequency,(int)(temp_rate));\r
- \r
- dvfs_clk->dvfs_table[i].frequency=temp_rate; \r
- }\r
- mutex_unlock(&mutex);\r
-}\r
-\r
-/***************************************************************************************************/\r
-static int dvfs_clk_get_ref_volt_depend(struct depend_list *depend, int rate_khz,\r
- struct cpufreq_frequency_table *clk_fv)\r
-{\r
- int i = 0;\r
- if (rate_khz == 0 || !depend || !depend->dep_table) {\r
- return -1;\r
- }\r
- clk_fv->frequency = rate_khz;\r
- clk_fv->index = 0;\r
-\r
- for (i = 0; (depend->dep_table[i].frequency != CPUFREQ_TABLE_END); i++) {\r
- if (depend->dep_table[i].frequency >= rate_khz) {\r
- clk_fv->frequency = depend->dep_table[i].frequency;\r
- clk_fv->index = depend->dep_table[i].index;\r
- return 0;\r
- }\r
- }\r
- clk_fv->frequency = 0;\r
- clk_fv->index = 0;\r
- return -1;\r
-}\r
-int dvfs_clk_get_ref_volt(struct clk_node *dvfs_clk, int rate_khz,\r
- struct cpufreq_frequency_table *clk_fv)\r
-{\r
- int i = 0;\r
- if (rate_khz == 0 || !dvfs_clk || !dvfs_clk->dvfs_table) {\r
- /* since no need */\r
- return -1;\r
- }\r
- clk_fv->frequency = rate_khz;\r
- clk_fv->index = 0;\r
-\r
- for (i = 0; (dvfs_clk->dvfs_table[i].frequency != CPUFREQ_TABLE_END); i++) {\r
- if (dvfs_clk->dvfs_table[i].frequency >= rate_khz) {\r
- clk_fv->frequency = dvfs_clk->dvfs_table[i].frequency;\r
- clk_fv->index = dvfs_clk->dvfs_table[i].index;\r
- // DVFS_DBG("%s,%s rate=%ukhz(vol=%d)\n",__func__,dvfs_clk->name,\r
- // clk_fv->frequency, clk_fv->index);\r
- return 0;\r
- }\r
- }\r
- clk_fv->frequency = 0;\r
- clk_fv->index = 0;\r
- // DVFS_DBG("%s get corresponding voltage error! out of bound\n", dvfs_clk->name);\r
- return -1;\r
-}\r
-\r
-static int dvfs_pd_get_newvolt_byclk(struct pd_node *pd, struct clk_node *dvfs_clk)\r
-{\r
- struct clk_list *child;\r
- int volt_max = 0;\r
-\r
- if (!pd || !dvfs_clk)\r
- return 0;\r
-\r
- if (dvfs_clk->set_volt >= pd->cur_volt) {\r
- return dvfs_clk->set_volt;\r
- }\r
-\r
- list_for_each_entry(child, &pd->clk_list, node) {\r
- // DVFS_DBG("%s ,pd(%s),dvfs(%s),volt(%u)\n",__func__,pd->name,\r
- // dvfs_clk->name,dvfs_clk->set_volt);\r
- volt_max = max(volt_max, child->dvfs_clk->set_volt);\r
- }\r
- return volt_max;\r
-}\r
-\r
-void dvfs_update_clk_pds_volt(struct clk_node *dvfs_clk)\r
-{\r
- struct pd_node *pd;\r
- int i;\r
- if (!dvfs_clk)\r
- return;\r
- for (i = 0; (dvfs_clk->pds[i].pd != NULL); i++) {\r
- pd = dvfs_clk->pds[i].pd;\r
- // DVFS_DBG("%s dvfs(%s),pd(%s)\n",__func__,dvfs_clk->name,pd->name);\r
- pd->cur_volt = dvfs_pd_get_newvolt_byclk(pd, dvfs_clk);\r
- }\r
-}\r
-\r
-int dvfs_vd_get_newvolt_bypd(struct vd_node *vd)\r
-{\r
- struct pd_node *pd;\r
- struct depend_list *depend;\r
- int volt_max_vd = 0;\r
- list_for_each_entry(pd, &vd->pd_list, node) {\r
- // DVFS_DBG("%s pd(%s,%u)\n",__func__,pd->name,pd->cur_volt);\r
- volt_max_vd = max(volt_max_vd, pd->cur_volt);\r
- }\r
-\r
- /* some clks depend on this voltage domain */\r
- if (!list_empty(&vd->req_volt_list)) {\r
- list_for_each_entry(depend, &vd->req_volt_list, node2vd) {\r
- volt_max_vd = max(volt_max_vd, depend->req_volt);\r
- }\r
- }\r
- return volt_max_vd;\r
-}\r
-\r
-int dvfs_vd_get_newvolt_byclk(struct clk_node *dvfs_clk)\r
-{\r
- if (!dvfs_clk)\r
- return -1;\r
- dvfs_update_clk_pds_volt(dvfs_clk);\r
- return dvfs_vd_get_newvolt_bypd(dvfs_clk->vd);\r
-}\r
-\r
-void dvfs_clk_register_set_rate_callback(struct clk *clk, clk_dvfs_target_callback clk_dvfs_target)\r
-{\r
- struct clk_node *dvfs_clk = clk_get_dvfs_info(clk);\r
- if (IS_ERR_OR_NULL(dvfs_clk)) {\r
- DVFS_ERR("%s %s get dvfs_clk err\n", __func__, clk->name);\r
- return ;\r
- }\r
- dvfs_clk->clk_dvfs_target = clk_dvfs_target;\r
-}\r
-\r
-/************************************************ freq volt table************************************/\r
-struct cpufreq_frequency_table *dvfs_get_freq_volt_table(struct clk *clk) \r
-{\r
- struct clk_node *info = clk_get_dvfs_info(clk);\r
- struct cpufreq_frequency_table *table;\r
- if (!info || !info->dvfs_table) {\r
- return NULL;\r
- }\r
- mutex_lock(&mutex);\r
- table = info->dvfs_table;\r
- mutex_unlock(&mutex);\r
- return table;\r
-}\r
-EXPORT_SYMBOL(dvfs_get_freq_volt_table);\r
-\r
-int dvfs_set_freq_volt_table(struct clk *clk, struct cpufreq_frequency_table *table)\r
-{\r
- struct clk_node *info = clk_get_dvfs_info(clk);\r
-\r
- if (!info)\r
- return -1; \r
- if (!table)\r
- { \r
- info->min_rate=0; \r
- info->max_rate=0; \r
- return -1;\r
- }\r
-\r
- mutex_lock(&mutex);\r
- info->dvfs_table = table;\r
- dvfs_get_rate_range(clk);\r
- mutex_unlock(&mutex);\r
-\r
- dvfs_table_round_clk_rate(info);\r
- dvfs_table_round_volt(info);\r
- return 0;\r
-}\r
-EXPORT_SYMBOL(dvfs_set_freq_volt_table);\r
-\r
-int dvfs_set_depend_table(struct clk *clk, char *vd_name, struct cpufreq_frequency_table *table)\r
-{\r
- struct vd_node *vd;\r
- struct depend_list *depend;\r
- struct clk_node *info;\r
-\r
- info = clk_get_dvfs_info(clk);\r
- if (!table || !info || !vd_name) {\r
- DVFS_ERR("%s :DVFS SET DEPEND TABLE ERROR! table or info or name empty\n", __func__);\r
- return -1;\r
- }\r
-\r
- list_for_each_entry(vd, &rk_dvfs_tree, node) {\r
- if (0 == strcmp(vd->name, vd_name)) {\r
- DVFS_DBG("FOUND A MATCH\n");\r
- mutex_lock(&mutex);\r
- list_for_each_entry(depend, &info->depend_list, node2clk) {\r
- if (vd == depend->dep_vd && info == depend->dvfs_clk) {\r
- depend->dep_table = table;\r
- break;\r
- }\r
- }\r
- mutex_unlock(&mutex);\r
- return 0;\r
- }\r
- }\r
- DVFS_ERR("%s :DVFS SET DEPEND TABLE ERROR! can not find vd:%s\n", __func__, vd_name);\r
-\r
- return 0;\r
-}\r
-\r
-int dvfs_set_arm_logic_volt(struct dvfs_arm_table *dvfs_cpu_logic_table,\r
- struct cpufreq_frequency_table *cpu_dvfs_table,\r
- struct cpufreq_frequency_table *dep_cpu2core_table)\r
-{\r
- int i = 0;\r
- for (i = 0; dvfs_cpu_logic_table[i].frequency != CPUFREQ_TABLE_END; i++) {\r
- cpu_dvfs_table[i].frequency = dvfs_cpu_logic_table[i].frequency;\r
- cpu_dvfs_table[i].index = dvfs_cpu_logic_table[i].cpu_volt;\r
-\r
- dep_cpu2core_table[i].frequency = dvfs_cpu_logic_table[i].frequency;\r
- dep_cpu2core_table[i].index = dvfs_cpu_logic_table[i].logic_volt;\r
- }\r
-\r
- cpu_dvfs_table[i].frequency = CPUFREQ_TABLE_END;\r
- dep_cpu2core_table[i].frequency = CPUFREQ_TABLE_END;\r
-\r
- dvfs_set_freq_volt_table(clk_get(NULL, "cpu"), cpu_dvfs_table);\r
- dvfs_set_depend_table(clk_get(NULL, "cpu"), "vd_core", dep_cpu2core_table);\r
- return 0;\r
-}\r
-\r
-\r
-int clk_enable_dvfs(struct clk *clk)\r
-{\r
- struct clk_node *dvfs_clk;\r
- struct cpufreq_frequency_table clk_fv;\r
- if (!clk) {\r
- DVFS_ERR("clk enable dvfs error\n");\r
- return -1;\r
- }\r
- dvfs_clk = clk_get_dvfs_info(clk);\r
- if (!dvfs_clk || !dvfs_clk->vd) {\r
- DVFS_ERR("%s clk(%s) not support dvfs!\n", __func__, clk->name);\r
- return -1;\r
- }\r
- if (dvfs_clk->enable_dvfs == 0) {\r
-\r
- if (IS_ERR_OR_NULL(dvfs_clk->vd->regulator)) {\r
- //regulator = NULL;\r
- if (dvfs_clk->vd->regulator_name)\r
- dvfs_clk->vd->regulator = dvfs_regulator_get(NULL, dvfs_clk->vd->regulator_name);\r
- if (!IS_ERR_OR_NULL(dvfs_clk->vd->regulator)) {\r
- // DVFS_DBG("dvfs_regulator_get(%s)\n",dvfs_clk->vd->regulator_name);\r
- clk_enable_dvfs_regulator_check(dvfs_clk->vd);\r
- dvfs_get_vd_regulator_volt_list(dvfs_clk->vd);\r
- dvfs_vd_get_regulator_volt_time_info(dvfs_clk->vd);\r
- //dvfs_vd_get_regulator_mode_info(dvfs_clk->vd);\r
- } else {\r
- //dvfs_clk->vd->regulator = NULL;\r
- dvfs_clk->enable_dvfs = 0;\r
- DVFS_ERR("%s can't get regulator in %s\n", dvfs_clk->name, __func__);\r
- return -1;\r
- }\r
- } else {\r
- clk_enable_dvfs_regulator_check(dvfs_clk->vd);\r
- // DVFS_DBG("%s(%s) vd volt=%u\n",__func__,dvfs_clk->name,dvfs_clk->vd->cur_volt);\r
- }\r
-\r
- dvfs_table_round_clk_rate(dvfs_clk);\r
- dvfs_table_round_volt(dvfs_clk);\r
- dvfs_clk->set_freq = dvfs_clk_get_rate_kz(clk);\r
- // DVFS_DBG("%s ,%s get freq%u!\n",__func__,dvfs_clk->name,dvfs_clk->set_freq);\r
-\r
- if (dvfs_clk_get_ref_volt(dvfs_clk, dvfs_clk->set_freq, &clk_fv)) {\r
- if (dvfs_clk->dvfs_table[0].frequency == CPUFREQ_TABLE_END) {\r
- DVFS_ERR("%s table empty\n", __func__);\r
- dvfs_clk->enable_dvfs = 0;\r
- return -1;\r
- } else {\r
- DVFS_WARNING("%s table all value are smaller than default, use default, just enable dvfs\n", __func__);\r
- dvfs_clk->enable_dvfs++;\r
- return 0;\r
- }\r
- }\r
-\r
- dvfs_clk->set_volt = clk_fv.index;\r
- dvfs_vd_get_newvolt_byclk(dvfs_clk);\r
- // DVFS_DBG("%s,%s,freq%u(ref vol %u)\n",__func__,dvfs_clk->name,\r
- // dvfs_clk->set_freq,dvfs_clk->set_volt);\r
-#if 0\r
- if (dvfs_clk->dvfs_nb) {\r
- // must unregister when clk disable\r
- clk_notifier_register(clk, dvfs_clk->dvfs_nb);\r
- }\r
-#endif\r
-\r
-#if 0\r
- if(dvfs_clk->vd->cur_volt < dvfs_clk->set_volt) {\r
- int ret;\r
- mutex_lock(&rk_dvfs_mutex);\r
- ret = dvfs_regulator_set_voltage_readback(dvfs_clk->vd->regulator, dvfs_clk->set_volt, dvfs_clk->set_volt);\r
- if (ret < 0) {\r
- dvfs_clk->vd->volt_set_flag = DVFS_SET_VOLT_FAILURE;\r
- dvfs_clk->enable_dvfs = 0;\r
- DVFS_ERR("dvfs enable clk %s,set volt error \n", dvfs_clk->name);\r
- mutex_unlock(&rk_dvfs_mutex);\r
- return -1;\r
- }\r
- dvfs_clk->vd->volt_set_flag = DVFS_SET_VOLT_SUCCESS;\r
- mutex_unlock(&rk_dvfs_mutex);\r
- }\r
-#endif\r
- dvfs_clk->enable_dvfs++;\r
- } else {\r
- DVFS_ERR("dvfs already enable clk enable = %d!\n", dvfs_clk->enable_dvfs);\r
- dvfs_clk->enable_dvfs++;\r
- }\r
- return 0;\r
-}\r
-\r
-int clk_disable_dvfs(struct clk *clk)\r
-{\r
- struct clk_node *dvfs_clk;\r
- dvfs_clk = clk->dvfs_info;\r
- if (!dvfs_clk->enable_dvfs) {\r
- DVFS_DBG("clk is already closed!\n");\r
- return -1;\r
- } else {\r
- dvfs_clk->enable_dvfs--;\r
- if (0 == dvfs_clk->enable_dvfs) {\r
- DVFS_ERR("clk closed!\n");\r
-#if 0\r
- clk_notifier_unregister(clk, dvfs_clk->dvfs_nb);\r
- DVFS_DBG("clk unregister nb!\n");\r
-#endif\r
- }\r
- }\r
- return 0;\r
-}\r
-struct clk_node *dvfs_get_dvfs_clk_byname(char *name) \r
-{\r
- struct vd_node *vd;\r
- struct pd_node *pd;\r
- struct clk_list *child;\r
- list_for_each_entry(vd, &rk_dvfs_tree, node) {\r
- list_for_each_entry(pd, &vd->pd_list, node) {\r
- list_for_each_entry(child, &pd->clk_list, node) {\r
- if (0 == strcmp(child->dvfs_clk->name, name)) {\r
- return child->dvfs_clk;\r
- }\r
- }\r
- }\r
- }\r
- return NULL;\r
-}\r
-int rk_regist_vd(struct vd_node *vd)\r
-{\r
- if (!vd)\r
- return -1;\r
- mutex_lock(&mutex);\r
- //mutex_init(&vd->dvfs_mutex);\r
- list_add(&vd->node, &rk_dvfs_tree);\r
- INIT_LIST_HEAD(&vd->pd_list);\r
- INIT_LIST_HEAD(&vd->req_volt_list);\r
- vd->mode_flag=0;\r
- vd->volt_time_flag=0;\r
- vd->n_voltages=0;\r
- mutex_unlock(&mutex);\r
- return 0;\r
-}\r
-\r
-int rk_regist_pd(struct pd_node_lookup *pd_lookup)\r
-{\r
- struct vd_node *vd;\r
- struct pd_node *pd;\r
-\r
- mutex_lock(&mutex);\r
- pd = pd_lookup->pd;\r
-\r
- list_for_each_entry(vd, &rk_dvfs_tree, node) {\r
- if (vd == pd->vd) {\r
- list_add(&pd->node, &vd->pd_list);\r
- INIT_LIST_HEAD(&pd->clk_list);\r
- break;\r
- }\r
- }\r
- mutex_unlock(&mutex);\r
- return 0;\r
-}\r
-\r
-int rk_regist_clk(struct clk_node *dvfs_clk)\r
-{\r
- struct pd_node *pd;\r
- struct clk_list *child;\r
- struct clk *clk;\r
- int i = 0;\r
-\r
- if (!dvfs_clk)\r
- return -1;\r
-\r
- if (!dvfs_clk->pds)\r
- return -1;\r
- mutex_lock(&mutex);\r
- dvfs_clk->enable_dvfs = 0;\r
- dvfs_clk->vd = dvfs_clk->pds[0].pd->vd;\r
- for (i = 0; dvfs_clk->pds[i].pd != NULL; i++) {\r
- child = &(dvfs_clk->pds[i].clk_list);\r
- child->dvfs_clk = dvfs_clk;\r
- pd = dvfs_clk->pds[i].pd;\r
- list_add(&child->node, &pd->clk_list);\r
- }\r
- clk = dvfs_clk_get(NULL, dvfs_clk->name);\r
- dvfs_clk->clk = clk;\r
- clk_register_dvfs(dvfs_clk, clk);\r
- INIT_LIST_HEAD(&dvfs_clk->depend_list);\r
- mutex_unlock(&mutex);\r
- return 0;\r
-}\r
-\r
-int rk_regist_depends(struct depend_lookup *dep_node)\r
-{\r
- struct depend_list *depend_list;\r
- struct clk_node *dvfs_clk;\r
-\r
- if (!dep_node) {\r
- DVFS_ERR("%s : DVFS BAD depend node!\n", __func__);\r
- return -1;\r
- }\r
-\r
- if (!dep_node->clk_name || !dep_node->dep_vd) {\r
- DVFS_ERR("%s : DVFS BAD depend members!\n", __func__);\r
- return -1;\r
- }\r
-\r
- depend_list = &dep_node->dep_list;\r
- dvfs_clk = dvfs_get_dvfs_clk_byname(dep_node->clk_name);\r
-\r
- mutex_lock(&mutex);\r
-\r
- depend_list->dvfs_clk = dvfs_clk;\r
- depend_list->dep_vd = dep_node->dep_vd;\r
- depend_list->dep_table = dep_node->dep_table;\r
-\r
- list_add(&depend_list->node2clk, &dvfs_clk->depend_list);\r
- list_add(&depend_list->node2vd, &depend_list->dep_vd->req_volt_list);\r
-\r
- mutex_unlock(&mutex);\r
- return 0;\r
-}\r
-\r
-int correct_volt(int *volt_clk, int *volt_dep, int clk_biger_than_dep, int dep_biger_than_clk)\r
-{\r
- int up_boundary = 0, low_boundary = 0;\r
-\r
- up_boundary = *volt_clk + dep_biger_than_clk;\r
- low_boundary = *volt_clk - clk_biger_than_dep;\r
-\r
- if (*volt_dep < low_boundary || *volt_dep > up_boundary) {\r
-\r
- if (*volt_dep < low_boundary) {\r
- *volt_dep = low_boundary;\r
-\r
- } else if (*volt_dep > up_boundary) {\r
- *volt_clk = *volt_dep - dep_biger_than_clk;\r
- }\r
- }\r
-\r
- return 0;\r
-}\r
-\r
-int dvfs_scale_volt(struct vd_node *vd_clk, struct vd_node *vd_dep,\r
- int volt_old, int volt_new, int volt_dep_old, int volt_dep_new, int clk_biger_than_dep, int dep_biger_than_clk)\r
-{\r
- struct regulator *regulator, *regulator_dep;\r
- int volt = 0, volt_dep = 0, step = 0, step_dep = 0;\r
- int volt_tmp = 0, volt_dep_tmp = 0;\r
- int volt_pre = 0, volt_dep_pre = 0;\r
- int ret = 0;\r
-\r
- DVFS_DBG("ENTER %s, volt=%d(old=%d), volt_dep=%d(dep_old=%d)\n", __func__, volt_new, volt_old, volt_dep_new, volt_dep_old);\r
- regulator = vd_clk->regulator;\r
- regulator_dep = vd_dep->regulator;\r
-\r
- if (IS_ERR_OR_NULL(regulator) || IS_ERR(regulator_dep)) {\r
- DVFS_ERR("%s dvfs_clk->vd->regulator or depend->dep_vd->regulator == NULL\n", __func__);\r
- return -1;\r
- }\r
-\r
- volt = volt_old;\r
- volt_dep = volt_dep_old;\r
-\r
- step = volt_new - volt_old > 0 ? 1 : (-1);\r
- step_dep = volt_dep_new - volt_dep_old > 0 ? 1 : (-1);\r
-\r
- DVFS_DBG("step=%d step_dep=%d %d\n", step, step_dep, step * step_dep);\r
-\r
- DVFS_DBG("Volt_new=%d(old=%d), volt_dep_new=%d(dep_old=%d)\n",\r
- volt_new, volt_old, volt_dep_new, volt_dep_old);\r
- do {\r
- volt_pre = volt;\r
- volt_dep_pre = volt_dep;\r
- if (step * step_dep < 0) {\r
- // target is between volt_old and volt_dep_old, just\r
- // need one step\r
- DVFS_DBG("step * step_dep < 0\n");\r
- volt = volt_new;\r
- volt_dep = volt_dep_new;\r
-\r
- } else if (step > 0) {\r
- // up voltage\r
- DVFS_DBG("step > 0\n");\r
- volt_tmp = volt_dep + clk_biger_than_dep;\r
- volt_dep_tmp = volt + dep_biger_than_clk;\r
-\r
- volt = volt_tmp > volt_new ? volt_new : volt_tmp;\r
- volt_dep = volt_dep_tmp > volt_dep_new ? volt_dep_new : volt_dep_tmp;\r
-\r
- } else if (step < 0) {\r
- // down voltage\r
- DVFS_DBG("step < 0\n");\r
-\r
- volt_tmp = volt_dep - dep_biger_than_clk;\r
- volt_dep_tmp = volt - clk_biger_than_dep;\r
-\r
- volt = volt_tmp < volt_new ? volt_new : volt_tmp;\r
- volt_dep = volt_dep_tmp < volt_dep_new ? volt_dep_new : volt_dep_tmp;\r
-\r
- } else {\r
- DVFS_ERR("Oops, some bugs here:Volt_new=%d(old=%d), volt_dep_new=%d(dep_old=%d)\n",\r
- volt_new, volt_old, volt_dep_new, volt_dep_old);\r
- goto fail;\r
- }\r
-\r
- if (vd_clk->cur_volt != volt) {\r
- DVFS_DBG("\t\t%s:%d->%d\n", vd_clk->name, vd_clk->cur_volt, volt);\r
- ret = dvfs_regulator_set_voltage_readback(regulator, volt, volt);\r
- //udelay(get_volt_up_delay(volt, volt_pre));\r
- dvfs_volt_up_delay(vd_clk,volt, volt_pre);\r
- if (ret < 0) {\r
- DVFS_ERR("%s %s set voltage up err ret = %d, Vnew = %d(was %d)mV\n",\r
- __func__, vd_clk->name, ret, volt_new, volt_old);\r
- goto fail;\r
- }\r
- vd_clk->cur_volt = volt;\r
- }\r
- if (vd_dep->cur_volt != volt_dep) {\r
- DVFS_DBG("\t\t%s:%d->%d\n", vd_dep->name, vd_dep->cur_volt, volt_dep);\r
- ret = dvfs_regulator_set_voltage_readback(regulator_dep, volt_dep, volt_dep);\r
- //udelay(get_volt_up_delay(volt_dep, volt_dep_pre));\r
- dvfs_volt_up_delay(vd_dep,volt_dep, volt_dep_pre);\r
- if (ret < 0) {\r
- DVFS_ERR("depend %s %s set voltage up err ret = %d, Vnew = %d(was %d)mV\n",\r
- __func__, vd_dep->name, ret, volt_dep_new, volt_dep_old);\r
- goto fail;\r
- }\r
- vd_dep->cur_volt = volt_dep;\r
- }\r
-\r
- DVFS_DBG("\t\tNOW:Volt=%d, volt_dep=%d\n", volt, volt_dep);\r
-\r
- } while (volt != volt_new || volt_dep != volt_dep_new);\r
-\r
- vd_clk->volt_set_flag = DVFS_SET_VOLT_SUCCESS;\r
- vd_clk->cur_volt = volt_new;\r
-\r
- return 0;\r
-fail:\r
- DVFS_ERR("+++++++++++++++++FAIL AREA\n");\r
- vd_clk->cur_volt = volt_old;\r
- vd_dep->cur_volt = volt_dep_old;\r
- vd_clk->volt_set_flag = DVFS_SET_VOLT_FAILURE;\r
- ret = dvfs_regulator_set_voltage_readback(regulator, volt_old, volt_old);\r
- if (ret < 0) {\r
- vd_clk->volt_set_flag = DVFS_SET_VOLT_FAILURE;\r
- DVFS_ERR("%s %s set callback voltage err ret = %d, Vnew = %d(was %d)mV\n",\r
- __func__, vd_clk->name, ret, volt_new, volt_old);\r
- }\r
-\r
- ret = dvfs_regulator_set_voltage_readback(regulator_dep, volt_dep_old, volt_dep_old);\r
- if (ret < 0) {\r
- vd_dep->volt_set_flag = DVFS_SET_VOLT_FAILURE;\r
- DVFS_ERR("%s %s set callback voltage err ret = %d, Vnew = %d(was %d)mV\n",\r
- __func__, vd_dep->name, ret, volt_dep_new, volt_dep_old);\r
- }\r
-\r
- return -1;\r
-}\r
-\r
-int dvfs_scale_volt_direct(struct vd_node *vd_clk, int volt_new)\r
-{\r
- int ret = 0;\r
- DVFS_DBG("ENTER %s, volt=%d(old=%d)\n", __func__, volt_new, vd_clk->cur_volt);\r
- if (IS_ERR_OR_NULL(vd_clk)) {\r
- DVFS_ERR("%s vd_node error\n", __func__);\r
- return -1;\r
- }\r
-\r
- DVFS_DBG("ENTER %s, volt=%d(old=%d)\n", __func__, volt_new, vd_clk->cur_volt);\r
- if (!IS_ERR_OR_NULL(vd_clk->regulator)) {\r
- ret = dvfs_regulator_set_voltage_readback(vd_clk->regulator, volt_new, volt_new);\r
- //udelay(get_volt_up_delay(volt_new, vd_clk->cur_volt));\r
- dvfs_volt_up_delay(vd_clk,volt_new, vd_clk->cur_volt);\r
- if (ret < 0) {\r
- vd_clk->volt_set_flag = DVFS_SET_VOLT_FAILURE;\r
- DVFS_ERR("%s %s set voltage up err ret = %d, Vnew = %d(was %d)mV\n",\r
- __func__, vd_clk->name, ret, volt_new, vd_clk->cur_volt);\r
- return -1;\r
- }\r
-\r
- } else {\r
- DVFS_ERR("%s up volt dvfs_clk->vd->regulator == NULL\n", __func__);\r
- return -1;\r
- }\r
-\r
- vd_clk->volt_set_flag = DVFS_SET_VOLT_SUCCESS;\r
- vd_clk->cur_volt = volt_new;\r
-\r
- return 0;\r
-\r
-}\r
-\r
-int dvfs_scale_volt_bystep(struct vd_node *vd_clk, struct vd_node *vd_dep, int volt_new, int volt_dep_new,\r
- int cur_clk_biger_than_dep, int cur_dep_biger_than_clk, int new_clk_biger_than_dep, int new_dep_biger_than_clk)\r
-{\r
-\r
- struct regulator *regulator, *regulator_dep;\r
- int volt_new_corrected = 0, volt_dep_new_corrected = 0;\r
- int volt_old = 0, volt_dep_old = 0;\r
- int ret = 0;\r
-\r
- volt_old = vd_clk->cur_volt;\r
- volt_dep_old = vd_dep->cur_volt;\r
-\r
- DVFS_DBG("ENTER %s, volt=%d(old=%d) vd_dep=%d(dep_old=%d)\n", __func__,\r
- volt_new, volt_old, volt_dep_new, volt_dep_old);\r
- DVFS_DBG("ENTER %s, VOLT_DIFF: clk_cur=%d(clk_new=%d) dep_cur=%d(dep_new=%d)\n", __func__,\r
- cur_clk_biger_than_dep, new_clk_biger_than_dep, \r
- cur_dep_biger_than_clk, new_dep_biger_than_clk);\r
-\r
- volt_new_corrected = volt_new;\r
- volt_dep_new_corrected = volt_dep_new;\r
- correct_volt(&volt_new_corrected, &volt_dep_new_corrected, cur_clk_biger_than_dep, cur_dep_biger_than_clk);\r
- ret = dvfs_scale_volt(vd_clk, vd_dep, volt_old, volt_new_corrected, volt_dep_old, volt_dep_new_corrected,\r
- cur_clk_biger_than_dep, cur_dep_biger_than_clk);\r
- if (ret < 0) {\r
- vd_clk->volt_set_flag = DVFS_SET_VOLT_FAILURE;\r
- DVFS_ERR("set volt error\n");\r
- return -1;\r
- }\r
-\r
- if (cur_clk_biger_than_dep != new_clk_biger_than_dep || cur_dep_biger_than_clk != new_dep_biger_than_clk) {\r
- regulator = vd_clk->regulator;\r
- regulator_dep = vd_dep->regulator;\r
-\r
- volt_new_corrected = volt_new;\r
- volt_dep_new_corrected = volt_dep_new;\r
- correct_volt(&volt_new_corrected, &volt_dep_new_corrected, new_clk_biger_than_dep, new_dep_biger_than_clk);\r
-\r
- if (vd_clk->cur_volt != volt_new_corrected) {\r
- DVFS_DBG("%s:%d->%d\n", vd_clk->name, vd_clk->cur_volt, volt_new_corrected);\r
- ret = dvfs_regulator_set_voltage_readback(regulator, volt_new_corrected, volt_new_corrected);\r
- //udelay(get_volt_up_delay(volt_new_corrected, vd_clk->cur_volt));\r
- dvfs_volt_up_delay(vd_clk,volt_new_corrected, vd_clk->cur_volt);\r
- if (ret < 0) {\r
- DVFS_ERR("%s %s set voltage up err ret = %d, Vnew = %d(was %d)mV\n",\r
- __func__, vd_clk->name, ret, volt_new_corrected, vd_clk->cur_volt);\r
- return -1;\r
- }\r
- vd_clk->cur_volt = volt_new_corrected;\r
- }\r
- if (vd_dep->cur_volt != volt_dep_new_corrected) {\r
- DVFS_DBG("%s:%d->%d\n", vd_clk->name, vd_clk->cur_volt, volt_dep_new_corrected);\r
- ret = dvfs_regulator_set_voltage_readback(regulator_dep, volt_dep_new_corrected, volt_dep_new_corrected);\r
- //udelay(get_volt_up_delay(volt_dep_new_corrected, vd_dep->cur_volt));\r
- dvfs_volt_up_delay(vd_dep,volt_dep_new_corrected, vd_dep->cur_volt);\r
- if (ret < 0) {\r
- DVFS_ERR("depend %s %s set voltage up err ret = %d, Vnew = %d(was %d)mV\n",\r
- __func__, vd_dep->name, ret, volt_dep_new_corrected, vd_dep->cur_volt);\r
- return -1;\r
- }\r
- vd_dep->cur_volt = volt_dep_new_corrected;\r
- }\r
- }\r
-\r
- return 0;\r
-}\r
-\r
-int dvfs_reset_volt(struct vd_node *dvfs_vd)\r
-{\r
- int flag_set_volt_correct = 0;\r
- if (!IS_ERR_OR_NULL(dvfs_vd->regulator))\r
- flag_set_volt_correct = dvfs_regulator_get_voltage(dvfs_vd->regulator);\r
- else {\r
- DVFS_ERR("dvfs regulator is ERROR\n");\r
- return -1;\r
- }\r
- if (flag_set_volt_correct <= 0) {\r
- DVFS_ERR("%s (vd:%s), try to reload volt ,by it is error again(%d)!!! stop scaling\n",\r
- __func__, dvfs_vd->name, flag_set_volt_correct);\r
- return -1;\r
- }\r
- dvfs_vd->volt_set_flag = DVFS_SET_VOLT_SUCCESS;\r
- DVFS_WARNING("%s (vd:%s), try to reload volt = %d\n",\r
- __func__, dvfs_vd->name, flag_set_volt_correct);\r
-\r
- /* Reset vd's voltage */\r
- dvfs_vd->cur_volt = flag_set_volt_correct;\r
-\r
- return dvfs_vd->cur_volt;\r
-}\r
-\r
-int dvfs_get_depend_volt(struct clk_node *dvfs_clk, struct vd_node *dvfs_vd_dep, int rate_new)\r
-{\r
- struct depend_list *depend;\r
- struct cpufreq_frequency_table clk_fv_dep;\r
- int ret = 0;\r
-\r
- DVFS_DBG("ENTER %s, rate_new=%d\n", __func__, rate_new);\r
- list_for_each_entry(depend, &dvfs_clk->depend_list, node2clk) {\r
- DVFS_DBG("--round depend clk:%s(depend:%s)\n", depend->dvfs_clk->name, depend->dep_vd->name);\r
- // this place just consider ONE depend voltage domain,\r
- // multi-depends must have some differece\r
- clk_fv_dep.index = 0;\r
- if (depend->dep_vd == dvfs_vd_dep) {\r
- ret = dvfs_clk_get_ref_volt_depend(depend, rate_new / 1000, &clk_fv_dep);\r
- if (ret < 0) {\r
- DVFS_ERR("%s get dvfs_ref_volt_depend error\n", __func__);\r
- return -1;\r
- }\r
- depend->req_volt = clk_fv_dep.index;\r
- return depend->req_volt;\r
- }\r
- }\r
-\r
- DVFS_ERR("%s can not find vd node %s\n", __func__, dvfs_vd_dep->name);\r
- return -1;\r
-}\r
-\r
-/**\r
- * dump_dbg_map() : Draw all informations of dvfs while debug\r
- */\r
-static int dump_dbg_map(char *buf)\r
-{\r
- int i;\r
- struct vd_node *vd;\r
- struct pd_node *pd, *clkparent;\r
- struct clk_list *child;\r
- struct clk_node *dvfs_clk;\r
- struct depend_list *depend;\r
- char *s = buf;\r
- mutex_lock(&rk_dvfs_mutex);\r
-\r
- printk( "-------------DVFS TREE-----------\n\n\n");\r
- printk( "DVFS TREE:\n");\r
- list_for_each_entry(vd, &rk_dvfs_tree, node) {\r
- printk( "|\n|- voltage domain:%s\n", vd->name);\r
- printk( "|- current voltage:%d\n", vd->cur_volt);\r
- list_for_each_entry(depend, &vd->req_volt_list, node2vd) {\r
- printk( "|- request voltage:%d, clk:%s\n", depend->req_volt, depend->dvfs_clk->name);\r
- }\r
-\r
- list_for_each_entry(pd, &vd->pd_list, node) {\r
- printk( "| |\n| |- power domain:%s, status = %s, current volt = %d\n",\r
- pd->name, (pd->pd_status == PD_ON) ? "ON" : "OFF", pd->cur_volt);\r
-\r
- list_for_each_entry(child, &pd->clk_list, node) {\r
- dvfs_clk = child->dvfs_clk;\r
- printk( "| | |\n| | |- clock: %s current: rate %d, volt = %d,"\r
- " enable_dvfs = %s\n",\r
- dvfs_clk->name, dvfs_clk->set_freq, dvfs_clk->set_volt,\r
- dvfs_clk->enable_dvfs == 0 ? "DISABLE" : "ENABLE");\r
- printk( "| | |- clk limit:[%d, %d]; last set rate = %lu\n",\r
- dvfs_clk->min_rate, dvfs_clk->max_rate,\r
- dvfs_clk->clk->last_set_rate);\r
-\r
- for (i = 0; dvfs_clk->pds[i].pd != NULL; i++) {\r
- clkparent = dvfs_clk->pds[i].pd;\r
- printk( "| | | |- clock parents: %s, vd_parent = %s\n",\r
- clkparent->name, clkparent->vd->name);\r
- }\r
-\r
- for (i = 0; (dvfs_clk->dvfs_table[i].frequency != CPUFREQ_TABLE_END); i++) {\r
- printk( "| | | |- freq = %d, volt = %d\n",\r
- dvfs_clk->dvfs_table[i].frequency,\r
- dvfs_clk->dvfs_table[i].index);\r
-\r
- }\r
-\r
- list_for_each_entry(depend, &dvfs_clk->depend_list, node2clk) {\r
- printk( "| | | | |- DEPEND VD: %s\n", depend->dep_vd->name);\r
- for (i = 0; (depend->dep_table[i].frequency != CPUFREQ_TABLE_END); i++) {\r
- printk( "| | | | |- freq = %d, req_volt = %d\n",\r
- depend->dep_table[i].frequency,\r
-\r
- depend->dep_table[i].index);\r
- }\r
- }\r
- }\r
- }\r
- }\r
- printk( "-------------DVFS TREE END------------\n");\r
- \r
- mutex_unlock(&rk_dvfs_mutex);\r
- return s - buf;\r
-}\r
-/*******************************AVS AREA****************************************/\r
-/*\r
- * To use AVS function, you must call avs_init in machine_rk30_board_init(void)(board-rk30-sdk.c)\r
- * And then call(vdd_log):\r
- * regulator_set_voltage(dcdc, 1100000, 1100000);\r
- * avs_init_val_get(1,1100000,"wm8326 init");\r
- * udelay(600);\r
- * avs_set_scal_val(AVS_BASE);\r
- * in wm831x_post_init(board-rk30-sdk-wm8326.c)\r
- * AVS_BASE can use 172\r
- */\r
-\r
-static struct avs_ctr_st *avs_ctr_data=NULL;\r
-#define init_avs_times 10\r
-#define init_avs_st_num 5\r
-\r
-struct init_avs_st {\r
- int is_set;\r
- u8 paramet[init_avs_times];\r
- int vol;\r
- char *s;\r
-};\r
-\r
-static struct init_avs_st init_avs_paramet[init_avs_st_num];\r
-\r
-void avs_board_init(struct avs_ctr_st *data)\r
-{\r
- \r
- avs_ctr_data=data;\r
-}\r
-void avs_init(void)\r
-{\r
- memset(&init_avs_paramet[0].is_set, 0, sizeof(init_avs_paramet));\r
- if(avs_ctr_data&&avs_ctr_data->avs_init)\r
- avs_ctr_data->avs_init();\r
- avs_init_val_get(0, 1200000,"board_init");\r
-}\r
-static u8 rk_get_avs_val(void)\r
-{\r
- \r
- if(avs_ctr_data&&avs_ctr_data->avs_get_val)\r
- { \r
- return avs_ctr_data->avs_get_val();\r
- }\r
- return 0;\r
-\r
-}\r
-/******************************int val get**************************************/\r
-void avs_init_val_get(int index, int vol, char *s)\r
-{\r
- int i;\r
- if(index >= init_avs_times)\r
- return;\r
- init_avs_paramet[index].vol = vol;\r
- init_avs_paramet[index].s = s;\r
- init_avs_paramet[index].is_set++;\r
- printk("DVFS MSG:\tAVS Value(index=%d): ", index);\r
- for(i = 0; i < init_avs_times; i++) {\r
- init_avs_paramet[index].paramet[i] = rk_get_avs_val();\r
- mdelay(1);\r
- printk("%d ", init_avs_paramet[index].paramet[i]);\r
- }\r
- printk("\n");\r
-}\r
-int avs_set_scal_val(u8 avs_base)\r
-{\r
- return 0;\r
-}\r
-\r
-/*************************interface to get avs value and dvfs tree*************************/\r
-#define USE_NORMAL_TIME\r
-#ifdef USE_NORMAL_TIME\r
-static struct timer_list avs_timer;\r
-#else\r
-static struct hrtimer dvfs_hrtimer;\r
-#endif\r
-\r
-static u32 avs_dyn_start = 0;\r
-static u32 avs_dyn_data_cnt;\r
-static u8 *avs_dyn_data = NULL;\r
-static u32 show_line_cnt = 0;\r
-static u8 dly_min;\r
-static u8 dly_max;\r
-\r
-#define val_per_line (30)\r
-#define line_pre_show (30)\r
-#define avs_dyn_data_num (3*1000*1000)\r
-\r
-static u32 print_avs_init(char *buf)\r
-{\r
- char *s = buf;\r
- int i, j;\r
-\r
- for(j = 0; j < init_avs_st_num; j++) {\r
- if(init_avs_paramet[j].vol <= 0)\r
- continue;\r
- s += sprintf(s, "%s ,vol=%d,paramet following\n",\r
- init_avs_paramet[j].s, init_avs_paramet[j].vol);\r
- for(i = 0; i < init_avs_times; i++) {\r
- s += sprintf(s, "%d ", init_avs_paramet[j].paramet[i]);\r
- }\r
-\r
- s += sprintf(s, "\n");\r
- }\r
- return (s - buf);\r
-}\r
-\r
-static ssize_t avs_init_show(struct kobject *kobj, struct kobj_attribute *attr,\r
- char *buf)\r
-{\r
- return print_avs_init(buf);\r
-}\r
-\r
-static ssize_t avs_init_store(struct kobject *kobj, struct kobj_attribute *attr,\r
- const char *buf, size_t n)\r
-{\r
-\r
- return n;\r
-}\r
-static ssize_t avs_now_show(struct kobject *kobj, struct kobj_attribute *attr,\r
- char *buf)\r
-{\r
- return sprintf(buf, "%d\n", rk_get_avs_val());\r
-}\r
-\r
-static ssize_t avs_now_store(struct kobject *kobj, struct kobj_attribute *attr,\r
- const char *buf, size_t n)\r
-{\r
- return n;\r
-}\r
-static ssize_t avs_dyn_show(struct kobject *kobj, struct kobj_attribute *attr,\r
- char *buf)\r
-{\r
- char *s = buf;\r
- u32 i;\r
-\r
- if(avs_dyn_data == NULL)\r
- return (s - buf);\r
-\r
- if(avs_dyn_start) {\r
- int start_cnt;\r
- int end_cnt;\r
- end_cnt = (avs_dyn_data_cnt ? (avs_dyn_data_cnt - 1) : 0);\r
- if(end_cnt > (line_pre_show * val_per_line))\r
- start_cnt = end_cnt - (line_pre_show * val_per_line);\r
- else\r
- start_cnt = 0;\r
-\r
- dly_min = avs_dyn_data[start_cnt];\r
- dly_max = avs_dyn_data[start_cnt];\r
-\r
- //s += sprintf(s,"data start=%d\n",i);\r
- for(i = start_cnt; i <= end_cnt;) {\r
- s += sprintf(s, "%d", avs_dyn_data[i]);\r
- dly_min = min(dly_min, avs_dyn_data[i]);\r
- dly_max = max(dly_max, avs_dyn_data[i]);\r
- i++;\r
- if(!(i % val_per_line)) {\r
- s += sprintf(s, "\n");\r
- } else\r
- s += sprintf(s, " ");\r
- }\r
-\r
- s += sprintf(s, "\n");\r
-\r
- s += sprintf(s, "new data is from=%d to %d\n", start_cnt, end_cnt);\r
- //s += sprintf(s,"\n max=%d,min=%d,totolcnt=%d,line=%d\n",dly_max,dly_min,avs_dyn_data_cnt,show_line_cnt);\r
-\r
-\r
- } else {\r
- if(show_line_cnt == 0) {\r
- dly_min = avs_dyn_data[0];\r
- dly_max = avs_dyn_data[0];\r
- }\r
-\r
-\r
- for(i = show_line_cnt * (line_pre_show * val_per_line); i < avs_dyn_data_cnt;) {\r
- s += sprintf(s, "%d", avs_dyn_data[i]);\r
- dly_min = min(dly_min, avs_dyn_data[i]);\r
- dly_max = max(dly_max, avs_dyn_data[i]);\r
- i++;\r
- if(!(i % val_per_line)) {\r
- s += sprintf(s, "\n");\r
- } else\r
- s += sprintf(s, " ");\r
- if(i >= ((show_line_cnt + 1)*line_pre_show * val_per_line))\r
- break;\r
- }\r
-\r
- s += sprintf(s, "\n");\r
-\r
- s += sprintf(s, "max=%d,min=%d,totolcnt=%d,line=%d\n",\r
- dly_max, dly_min, avs_dyn_data_cnt, show_line_cnt);\r
- show_line_cnt++;\r
- if(((show_line_cnt * line_pre_show)*val_per_line) >= avs_dyn_data_cnt) {\r
-\r
- show_line_cnt = 0;\r
-\r
- s += sprintf(s, "data is over\n");\r
- }\r
- }\r
- return (s - buf);\r
-}\r
-\r
-static ssize_t avs_dyn_store(struct kobject *kobj, struct kobj_attribute *attr,\r
- const char *buf, size_t n)\r
-{\r
- const char *pbuf;\r
-\r
- if((strncmp(buf, "start", strlen("start")) == 0)) {\r
- if(avs_dyn_data == NULL)\r
- avs_dyn_data = kmalloc(avs_dyn_data_num, GFP_KERNEL);\r
- if(avs_dyn_data == NULL)\r
- return n;\r
-\r
- pbuf = &buf[strlen("start")];\r
- avs_dyn_data_cnt = 0;\r
- show_line_cnt = 0;\r
- if(avs_dyn_data) {\r
-#ifdef USE_NORMAL_TIME\r
- mod_timer(&avs_timer, jiffies + msecs_to_jiffies(5));\r
-#else\r
- hrtimer_start(&dvfs_hrtimer, ktime_set(0, 5 * 1000 * 1000), HRTIMER_MODE_REL);\r
-#endif\r
- avs_dyn_start = 1;\r
- }\r
- //sscanf(pbuf, "%d %d", &number, &voltage);\r
- //DVFS_DBG("---------ldo %d %d\n", number, voltage);\r
-\r
- } else if((strncmp(buf, "stop", strlen("stop")) == 0)) {\r
- pbuf = &buf[strlen("stop")];\r
- avs_dyn_start = 0;\r
- show_line_cnt = 0;\r
- //sscanf(pbuf, "%d %d", &number, &voltage);\r
- //DVFS_DBG("---------dcdc %d %d\n", number, voltage);\r
- }\r
-\r
-\r
-\r
- return n;\r
-}\r
-\r
-static ssize_t dvfs_tree_store(struct kobject *kobj, struct kobj_attribute *attr,\r
- const char *buf, size_t n)\r
-{\r
- return n;\r
-}\r
-static ssize_t dvfs_tree_show(struct kobject *kobj, struct kobj_attribute *attr,\r
- char *buf)\r
-{\r
- return dump_dbg_map(buf);\r
-\r
-}\r
-\r
-static void avs_timer_fn(unsigned long data)\r
-{\r
- int i;\r
- for(i = 0; i < 1; i++) {\r
- if(avs_dyn_data_cnt >= avs_dyn_data_num)\r
- return;\r
- avs_dyn_data[avs_dyn_data_cnt] = rk_get_avs_val();\r
- avs_dyn_data_cnt++;\r
- }\r
- if(avs_dyn_start)\r
- mod_timer(&avs_timer, jiffies + msecs_to_jiffies(10));\r
-}\r
-#if 0\r
-struct hrtimer dvfs_hrtimer;\r
-static enum hrtimer_restart dvfs_hrtimer_timer_func(struct hrtimer *timer)\r
-{\r
- int i;\r
- for(i = 0; i < 1; i++) {\r
- if(avs_dyn_data_cnt >= avs_dyn_data_num)\r
- return HRTIMER_NORESTART;\r
- avs_dyn_data[avs_dyn_data_cnt] = rk_get_avs_val();\r
- avs_dyn_data_cnt++;\r
- }\r
- if(avs_dyn_start)\r
- hrtimer_start(timer, ktime_set(0, 1 * 1000 * 1000), HRTIMER_MODE_REL);\r
-\r
-}\r
-#endif\r
-/*********************************************************************************/\r
-static struct kobject *dvfs_kobj;\r
-struct dvfs_attribute {\r
- struct attribute attr;\r
- ssize_t (*show)(struct kobject *kobj, struct kobj_attribute *attr,\r
- char *buf);\r
- ssize_t (*store)(struct kobject *kobj, struct kobj_attribute *attr,\r
- const char *buf, size_t n);\r
-};\r
-\r
-static struct dvfs_attribute dvfs_attrs[] = {\r
- /* node_name permision show_func store_func */\r
-#ifdef CONFIG_RK_CLOCK_PROC\r
- __ATTR(dvfs_tree, S_IRUSR | S_IRGRP | S_IWUSR, dvfs_tree_show, dvfs_tree_store),\r
- __ATTR(avs_init, S_IRUSR | S_IRGRP | S_IWUSR, avs_init_show, avs_init_store),\r
-// __ATTR(avs_dyn, S_IRUSR | S_IRGRP | S_IWUSR, avs_dyn_show, avs_dyn_store),\r
- __ATTR(avs_now, S_IRUSR | S_IRGRP | S_IWUSR, avs_now_show, avs_now_store),\r
-#endif\r
-};\r
-\r
-static int __init dvfs_init(void)\r
-{\r
- int i, ret = 0;\r
-#ifdef USE_NORMAL_TIME\r
- init_timer(&avs_timer);\r
- //avs_timer.expires = jiffies+msecs_to_jiffies(1);\r
- avs_timer.function = avs_timer_fn;\r
- //mod_timer(&avs_timer,jiffies+msecs_to_jiffies(1));\r
-#else\r
- hrtimer_init(&dvfs_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);\r
- dvfs_hrtimer.function = dvfs_hrtimer_timer_func;\r
- //hrtimer_start(&dvfs_hrtimer,ktime_set(0, 5*1000*1000),HRTIMER_MODE_REL);\r
-#endif\r
-\r
- dvfs_kobj = kobject_create_and_add("dvfs", NULL);\r
- if (!dvfs_kobj)\r
- return -ENOMEM;\r
- for (i = 0; i < ARRAY_SIZE(dvfs_attrs); i++) {\r
- ret = sysfs_create_file(dvfs_kobj, &dvfs_attrs[i].attr);\r
- if (ret != 0) {\r
- DVFS_ERR("create index %d error\n", i);\r
- return ret;\r
- }\r
- }\r
-\r
- return ret;\r
-}\r
-subsys_initcall(dvfs_init);\r
+++ /dev/null
-/*
- * arch/arm/mach-rk29/early_printk.c
- *
- * Copyright (C) 2009 Sascha Hauer <s.hauer@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/console.h>
-#include <linux/init.h>
-
-#ifndef CONFIG_DEBUG_LL
-extern void printch(int);
-
-static void early_write(const char *s, unsigned n)
-{
- while (n-- > 0) {
- if (*s == '\n')
- printch('\r');
- printch(*s);
- s++;
- }
-}
-
-static void early_console_write(struct console *con, const char *s, unsigned n)
-{
- early_write(s, n);
-}
-
-static struct console early_console = {
- .name = "earlycon",
- .write = early_console_write,
- .flags = CON_PRINTBUFFER | CON_BOOT,
- .index = -1,
-};
-#endif
-
-void __init rk29_setup_early_printk(void)
-{
-#ifndef CONFIG_DEBUG_LL
- register_console(&early_console);
-#endif
-}
+++ /dev/null
-/*
- * Copyright (C) 2013 ROCKCHIP, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/delay.h>
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/spinlock.h>
-#include <plat/efuse.h>
-
-#if defined(CONFIG_ARCH_RK3188) || defined(CONFIG_SOC_RK3028) || defined(CONFIG_ARCH_RK3066B)
-#define efuse_readl(offset) readl_relaxed(RK30_EFUSE_BASE + offset)
-#define efuse_writel(val, offset) writel_relaxed(val, RK30_EFUSE_BASE + offset)
-#endif
-
-#if defined(CONFIG_ARCH_RK3026)
-#define efuse_readl(offset) readl_relaxed(RK2928_EFUSE_BASE + offset)
-#define efuse_writel(val, offset) writel_relaxed(val, RK2928_EFUSE_BASE + offset)
-#endif
-
-u8 efuse_buf[32 + 1] = {0, 0};
-
-static int efuse_readregs(u32 addr, u32 length, u8 *buf)
-{
-#ifndef efuse_readl
- return 0;
-#else
- unsigned long flags;
- static DEFINE_SPINLOCK(efuse_lock);
- int ret = length;
-
- if (!length)
- return 0;
-
- spin_lock_irqsave(&efuse_lock, flags);
-
- efuse_writel(EFUSE_CSB, REG_EFUSE_CTRL);
- efuse_writel(EFUSE_LOAD | EFUSE_PGENB, REG_EFUSE_CTRL);
- udelay(2);
- do {
- efuse_writel(efuse_readl(REG_EFUSE_CTRL) & (~(EFUSE_A_MASK << EFUSE_A_SHIFT)), REG_EFUSE_CTRL);
- efuse_writel(efuse_readl(REG_EFUSE_CTRL) | ((addr & EFUSE_A_MASK) << EFUSE_A_SHIFT), REG_EFUSE_CTRL);
- udelay(2);
- efuse_writel(efuse_readl(REG_EFUSE_CTRL) | EFUSE_STROBE, REG_EFUSE_CTRL);
- udelay(2);
- *buf = efuse_readl(REG_EFUSE_DOUT);
- efuse_writel(efuse_readl(REG_EFUSE_CTRL) & (~EFUSE_STROBE), REG_EFUSE_CTRL);
- udelay(2);
- buf++;
- addr++;
- } while(--length);
- udelay(2);
- efuse_writel(efuse_readl(REG_EFUSE_CTRL) | EFUSE_CSB, REG_EFUSE_CTRL);
- udelay(1);
-
- spin_unlock_irqrestore(&efuse_lock, flags);
- return ret;
-#endif
-}
-
-void rk_efuse_init(void)
-{
-#if defined(CONFIG_ARCH_RK3026)
- u8 tmp_buf[32];
- int i, j, err = 0;
-
- efuse_readregs(0x0, 32, efuse_buf);
-
- /*
- * i = 10, need time = 2,860,875 ns
- * i = 100, need time = 27,327,000 ns
- */
- for (i = 0; i < 10; i++){
- efuse_readregs(0x0, 32, tmp_buf);
- for (j = 0; j < 32; j++){
- if (efuse_buf[j] != tmp_buf[j]){
- printk(KERN_WARNING ":%s:rk3026 efuse bit err\n", __func__);
- efuse_readregs(0x0, 32, efuse_buf);
- i = 0;
- err++;
- break;
- }
- }
-
- if (err >= 500) {
- printk(KERN_ERR "%s:rk3026 get efuse err\n", __func__);
- efuse_buf[5] = 0x00; /* set default SOC version */
- efuse_buf[22] = 0x00; /* clean msg about leakage */
- break;
- }
- }
-#else
- efuse_readregs(0x0, 32, efuse_buf);
-#endif
-}
-
-int rk_pll_flag(void)
-{
- return efuse_buf[22] & 0x3;
-}
-int rk_tflag(void)
-{
- return efuse_buf[22] & (0x1 << 3);
-}
-
-int rk_leakage_val(void)
-{
- /*
- * efuse_buf[22]
- * bit[2]:
- * 0:enable leakage level auto voltage scale
- * 1:disalbe leakage level avs
- */
- if ((efuse_buf[22] >> 2) & 0x1)
- return 0;
- else
- return (efuse_buf[22] >> 4) & 0x0f;
-}
-
-int rk3028_version_val(void)
-{
- return efuse_buf[5];
-}
-
-int rk3026_version_val(void)
-{
- return efuse_buf[5];
-}
+++ /dev/null
-/*
- * Copyright (C) 2010 Google, Inc.
- *
- * Author:
- * Brian Swetland <swetland@google.com>
- * Iliyan Malchev <malchev@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-
-#include <asm/hardware/gic.h>
-#include <asm/fiq.h>
-#include <mach/io.h>
-#include <mach/fiq.h>
-#include <mach/debug_uart.h>
-
-
-// GIC ICDISR
-#define GIC_DIST_SECURITY 0x080
-
-#define FIRST_SGI_PPI_IRQ 32
-
-static void rk_fiq_mask(struct irq_data *d)
-{
- u32 i = 0;
- void __iomem *base = GIC_DIST_BASE;
-
- if (d->irq < FIRST_SGI_PPI_IRQ)
- return;
- // ICDISR each bit 0 -- Secure 1--Non-Secure
- // FIQ output from secure , so set bit Non-Secure to mask the fiq
- base += GIC_DIST_SECURITY + ((d->irq / 32) << 2);
- i = readl_relaxed(base);
- i |= 1 << (d->irq % 32);
- writel_relaxed(i, base);
- dsb();
-}
-
-static void rk_fiq_unmask(struct irq_data *d)
-{
- u32 i = 0;
- void __iomem *base = GIC_DIST_BASE;
-
- if (d->irq < FIRST_SGI_PPI_IRQ)
- return;
- // ICDISR each bit 0 -- Secure 1--Non-Secure
- // FIQ output from secure , so set bit Secure to unmask the fiq
- base += GIC_DIST_SECURITY + ((d->irq / 32) << 2);
- i = readl_relaxed(base);
- i &= ~(1 << (d->irq % 32));
- writel_relaxed(i, base);
- dsb();
-}
-
-void rk_fiq_enable(int irq)
-{
- rk_fiq_unmask(irq_get_irq_data(irq));
- enable_fiq(irq);
-}
-
-void rk_fiq_disable(int irq)
-{
- rk_fiq_mask(irq_get_irq_data(irq));
- disable_fiq(irq);
-}
-
-void rk_irq_setpending(int irq)
-{
- writel_relaxed(1<<(irq%32), GIC_DIST_BASE + GIC_DIST_PENDING_SET + (irq/32)*4);
- dsb();
-}
-
-void rk_irq_clearpending(int irq)
-{
- writel_relaxed(1<<(irq%32), GIC_DIST_BASE + GIC_DIST_PENDING_CLEAR + (irq/32)*4);
- dsb();
-}
-
-void rk_fiq_init(void)
-{
- unsigned int gic_irqs, i;
-
- // read gic info to know how many irqs in our chip
- gic_irqs = readl_relaxed(GIC_DIST_BASE + GIC_DIST_CTR) & 0x1f;
- // set all the interrupt to non-secure state
- for (i = 0; i < (gic_irqs + 1); i++) {
- writel_relaxed(0xffffffff, GIC_DIST_BASE + GIC_DIST_SECURITY + (i<<2));
- }
- dsb();
- writel_relaxed(0x3, GIC_DIST_BASE + GIC_DIST_CTRL);
- writel_relaxed(0x0f, GIC_CPU_BASE + GIC_CPU_CTRL);
-#ifdef IRQ_DEBUG_UART
- // set the debug uart priority a little higher than other interrupts (normal is 0xa0)
- writeb_relaxed(0x90, GIC_DIST_BASE + GIC_DIST_PRI + IRQ_DEBUG_UART);
-#endif
- dsb();
-}
+++ /dev/null
-#ifndef __PLAT_BOARD_H
-#define __PLAT_BOARD_H
-
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/rk_screen.h>
-#include <plat/sram.h>
-
-struct adc_platform_data {
- int ref_volt;
- int base_chn;
- int (*get_base_volt)(void);
-};
-enum {
- I2C_IDLE = 0,
- I2C_SDA_LOW,
- I2C_SCL_LOW,
- BOTH_LOW,
-};
-
-struct akm8963_platform_data {
- int gpio_DRDY;
- int gpio_RST;
- char layout;
- char outbit;
-};
-
-struct rk30_i2c_platform_data {
- char *name;
- int bus_num;
-#define I2C_RK29_ADAP 0
-#define I2C_RK30_ADAP 1
- int adap_type;
- int is_div_from_arm;
- u32 flags;
- int scl_mode;
- int sda_mode;
- int (*io_init)(void);
- int (*io_deinit)(void);
-};
-
-struct spi_cs_gpio {
- const char *name;
- unsigned int cs_gpio;
- char *cs_iomux_name;
- unsigned int cs_iomux_mode;
-};
-
-struct rk29xx_spi_platform_data {
- int (*io_init)(struct spi_cs_gpio*, int);
- int (*io_deinit)(struct spi_cs_gpio*, int);
- int (*io_fix_leakage_bug)(void);
- int (*io_resume_leakage_bug)(void);
- struct spi_cs_gpio *chipselect_gpios;
- u16 num_chipselect;
-};
-
-enum {
- BRIGHTNESS_MODE_LINE=0,
- BRIGHTNESS_MODE_CONIC =1,
-};
-
-
-struct rk29_bl_info {
- u32 pwm_id;
- u32 bl_ref;
- int (*io_init)(void);
- int (*io_deinit)(void);
- int (*pwm_suspend)(void);
- int (*pwm_resume)(void);
- int min_brightness; /* 0 ~ 255 */
- int max_brightness; /* 0 ~ 255 */
- int brightness_mode;
- unsigned int delay_ms; /* in milliseconds */
- int pre_div;
-};
-
-struct rk29_io_t {
- unsigned long io_addr;
- unsigned long enable;
- unsigned long disable;
- int (*io_init)(void);
-};
-
-enum {
- PMIC_TYPE_NONE =0,
- PMIC_TYPE_WM8326 =1,
- PMIC_TYPE_TPS65910 =2,
- PMIC_TYPE_ACT8931 =3,
- PMIC_TYPE_ACT8846 =3,
- PMIC_TYPE_RK808 =4,
- PMIC_TYPE_RICOH619 =5,
- PMIC_TYPE_RT5025 =6,
- PMIC_TYPE_MAX,
-};
-extern __sramdata int g_pmic_type;
-#define pmic_is_wm8326() (g_pmic_type == PMIC_TYPE_WM8326)
-#define pmic_is_tps65910() (g_pmic_type == PMIC_TYPE_TPS65910)
-#define pmic_is_act8931() (g_pmic_type == PMIC_TYPE_ACT8931)
-#define pmic_is_act8846() (g_pmic_type == PMIC_TYPE_ACT8846)
-#define pmic_is_rk808() (g_pmic_type == PMIC_TYPE_RK808)
-#define pmic_is_ricoh619() (g_pmic_type == PMIC_TYPE_RICOH619)
-#define pmic_is_rt5025() (g_pmic_type == PMIC_TYPE_RT5025)
-
-struct pmu_info {
- char *name;
- int min_uv;
- int max_uv;
- int suspend_vol;
-};
-
-
-struct rksdmmc_iomux {
- char *name; //set the MACRO of gpio
- int fgpio;
- int fmux;
-};
-
-struct rksdmmc_gpio {
- int io; //set the address of gpio
- char name[64]; //
- int enable; // disable = !enable //set the default value,i.e,GPIO_HIGH or GPIO_LOW
- struct rksdmmc_iomux iomux;
-};
-
-
-struct rksdmmc_gpio_board {
- struct rksdmmc_gpio clk_gpio;
- struct rksdmmc_gpio cmd_gpio;
- struct rksdmmc_gpio data0_gpio;
- struct rksdmmc_gpio data1_gpio;
- struct rksdmmc_gpio data2_gpio;
- struct rksdmmc_gpio data3_gpio;
-
- struct rksdmmc_gpio detect_irq;
- struct rksdmmc_gpio power_en_gpio;
- struct rksdmmc_gpio write_prt;
- struct rksdmmc_gpio sdio_irq_gpio;
-};
-
-
-struct rksdmmc_gpio_wifi_moudle {
- struct rksdmmc_gpio power_n; //PMU_EN
- struct rksdmmc_gpio reset_n; //SYSRET_B, DAIRST
- struct rksdmmc_gpio vddio; //power source
- struct rksdmmc_gpio bgf_int_b;
- struct rksdmmc_gpio wifi_int_b;
- struct rksdmmc_gpio gps_sync;
- struct rksdmmc_gpio ANTSEL2; //pin5--ANTSEL2
- struct rksdmmc_gpio ANTSEL3; //pin6--ANTSEL3
- struct rksdmmc_gpio GPS_LAN; //pin33--GPS_LAN
-};
-
-
-struct rk29_sdmmc_platform_data {
- unsigned int host_caps;
- unsigned int host_ocr_avail;
- unsigned int use_dma:1;
- char dma_name[8];
- int (*io_init)(void);
- int (*io_deinit)(void);
- void (*set_iomux)(int device_id, unsigned int bus_width);//added by xbw at 2011-10-13
- int (*status)(struct device *);
- int (*register_status_notify)(void (*callback)(int card_present, void *dev_id), void *dev_id);
- int detect_irq;
- int insert_card_level;
- int power_en;
- int power_en_level;
- int enable_sd_wakeup;
- int write_prt;
- int write_prt_enalbe_level;
- unsigned int sdio_INT_gpio;
- int sdio_INT_level;
-#define USE_SDIO_INT_LEVEL /*In order to be compatible with old project, those who do not define the member sdio_INT_level */
- struct rksdmmc_gpio det_pin_info;
- int (*sd_vcc_reset)(void);
-};
-
-struct gsensor_platform_data {
- u16 model;
- u16 swap_xy;
- u16 swap_xyz;
- signed char orientation[9];
- int (*get_pendown_state)(void);
- int (*init_platform_hw)(void);
- int (*gsensor_platform_sleep)(void);
- int (*gsensor_platform_wakeup)(void);
- void (*exit_platform_hw)(void);
-};
-
-struct akm8975_platform_data {
- short m_layout[4][3][3];
- char project_name[64];
- int gpio_DRDY;
-};
-
-struct akm_platform_data {
- short m_layout[4][3][3];
- char project_name[64];
- char layout;
- char outbit;
- int gpio_DRDY;
- int gpio_RST;
-};
-
-
-struct sensor_platform_data {
- int type;
- int irq;
- int power_pin;
- int reset_pin;
- int standby_pin;
- int irq_enable; //if irq_enable=1 then use irq else use polling
- int poll_delay_ms; //polling
- int x_min; //filter
- int y_min;
- int z_min;
- int factory;
- int layout;
- unsigned char address;
- signed char orientation[9];
- short m_layout[4][3][3];
- char project_name[64];
- int (*init_platform_hw)(void);
- void (*exit_platform_hw)(void);
- int (*power_on)(void);
- int (*power_off)(void);
-};
-
-/* Platform data for the board id */
-struct board_id_platform_data {
- int gpio_pin[32];
- int num_gpio;
- char *board_id_buf;
- int (*init_platform_hw)(void);
- int (*exit_platform_hw)(void);
- struct board_device_table *device_table;
- int device_table_size;
- int (*init_parameter)(int id);
-};
-
-struct ft5506_platform_data {
- int (*get_pendown_state)(void);
- int (*init_platform_hw)(void);
- int (*platform_sleep)(void);
- int (*platform_wakeup)(void);
- void (*exit_platform_hw)(void);
-};
-struct cm3217_platform_data {
- int irq_pin;
- int power_pin;
- int (*init_platform_hw)(void);
- void (*exit_platform_hw)(void);
-};
-
-struct irda_info {
- u32 intr_pin;
- int (*iomux_init)(void);
- int (*iomux_deinit)(void);
- int (*irda_pwr_ctl)(int en);
-};
-
-struct rk29_gpio_expander_info {
- unsigned int gpio_num;
- unsigned int pin_type; //GPIO_IN or GPIO_OUT
- unsigned int pin_value; //GPIO_HIGH or GPIO_LOW
-};
-
-/*vmac*/
-struct rk29_vmac_platform_data {
- int (*vmac_register_set)(void);
- int (*rmii_io_init)(void);
- int (*rmii_io_deinit)(void);
- int (*rmii_power_control)(int enable);
- int(*rmii_speed_switch)(int speed);
- int(*rmii_extclk_sel)(void);
-};
-/* adc battery */
-#define LCDC_ON 0x0001
-#define BACKLIGHT_ON 0x0002
-struct rk30_adc_battery_platform_data {
- int (*io_init)(void);
- int (*io_deinit)(void);
- int (*is_dc_charging)(void);
- int (*charging_ok)(void);
-
- int (*is_usb_charging)(void);
- int spport_usb_charging ;
- int (*control_usb_charging)(int);
-
- int usb_det_pin;
- int dc_det_pin;
- int batt_low_pin;
- int charge_ok_pin;
- int charge_set_pin;
- int back_light_pin;
-
- int ctrl_charge_led_pin;
- int ctrl_charge_enable;
- void (*ctrl_charge_led)(int);
-
- int dc_det_level;
- int batt_low_level;
- int charge_ok_level;
- int charge_set_level;
- int usb_det_level;
-
- int adc_channel;
-
- int dc_det_pin_pull; //pull up/down enable/disbale
- int batt_low_pin_pull;
- int charge_ok_pin_pull;
- int charge_set_pin_pull;
-
- int low_voltage_protection; // low voltage protection
-
- int charging_sleep; // don't have lock,if chargeing_sleep = 0;else have lock
-
- int is_reboot_charging;
- int save_capacity; //save capacity to /data/bat_last_capacity.dat, suggested use
-
- int reference_voltage; // the rK2928 is 3300;RK3066 and rk29 are 2500;rk3066B is 1800;
- int pull_up_res; //divider resistance , pull-up resistor
- int pull_down_res; //divider resistance , pull-down resistor
-
- int time_down_discharge; //the time of capactiy drop 1% --discharge
- int time_up_charge; //the time of capacity up 1% ---charging
-
- int use_board_table;
- int table_size;
- int *discharge_table;
- int *charge_table;
- int *property_tabel;
- int *board_batt_table;
- int chargeArray[11];
- int dischargeArray[11];
-
-
-};
-
-#ifndef _LINUX_WLAN_PLAT_H_
-struct wifi_platform_data {
- int (*set_power)(int val);
- int (*set_reset)(int val);
- int (*set_carddetect)(int val);
- void *(*mem_prealloc)(int section, unsigned long size);
- int (*get_mac_addr)(unsigned char *buf);
-};
-#endif
-
-struct goodix_platform_data {
- int model ;
- int rest_pin;
- int irq_pin ;
- int (*get_pendown_state)(void);
- int (*init_platform_hw)(void);
- int (*platform_sleep)(void);
- int (*platform_wakeup)(void);
- void (*exit_platform_hw)(void);
-};
-
-struct tp_platform_data {
- int model;
- int x_max;
- int y_max;
- int reset_pin;
- int irq_pin ;
- int firmVer;
- int (*get_pendown_state)(void);
- int (*init_platform_hw)(void);
- int (*platform_sleep)(void);
- int (*platform_wakeup)(void);
- void (*exit_platform_hw)(void);
-};
-
-
-struct codec_platform_data {
- int spk_pin;
- int hp_pin ;
-};
-
-struct ac_usb_switch_platform_data {
- int usb_switch_pin;
- int pc_state_pin ;
-};
-struct ct360_platform_data {
- u16 model;
- u16 x_max;
- u16 y_max;
- void (*hw_init)(void);
- void (*shutdown)(int);
-};
-
-struct ft5606_platform_data {
- int (*get_pendown_state)(void);
- int (*init_platform_hw)(void);
- int (*platform_sleep)(void);
- int (*platform_wakeup)(void);
- void (*exit_platform_hw)(void);
-};
-
-#if defined(CONFIG_TOUCHSCREEN_FT5306) || defined(CONFIG_TOUCHSCREEN_FT5306_WPX2)
-struct ft5x0x_platform_data{
- u16 model;
- int max_x;
- int max_y;
- int key_min_x;
- int key_min_y;
- int xy_swap;
- int x_revert;
- int y_revert;
- int (*get_pendown_state)(void);
- int (*init_platform_hw)(void);
- int (*ft5x0x_platform_sleep)(void);
- int (*ft5x0x_platform_wakeup)(void);
- void (*exit_platform_hw)(void);
-};
-#endif
-
-#if defined (CONFIG_TOUCHSCREEN_SITRONIX_A720)
-struct ft5x0x_platform_data{
- u16 model;
- int (*get_pendown_state)(void);
- int (*init_platform_hw)(void);
- int (*ft5x0x_platform_sleep)(void);
- int (*ft5x0x_platform_wakeup)(void);
- void (*exit_platform_hw)(void);
- int (*direction_otation)(int *x ,int *y );
-};
-#endif
-
-#if defined (CONFIG_TOUCHSCREEN_I30)
-struct ft5306_platform_data {
- int rest_pin;
- int irq_pin;
- int (*get_pendown_state)(void);
- int (*init_platform_hw)(void);
- int (*platform_sleep)(void);
- int (*platform_wakeup)(void);
- void (*exit_platform_hw)(void);
-};
-#endif
-
-#if defined (CONFIG_EETI_EGALAX)
-struct eeti_egalax_platform_data {
- u16 model;
- int (*get_pendown_state)(void);
- int (*init_platform_hw)(void);
- int (*eeti_egalax_platform_sleep)(void);
- int (*eeti_egalax_platform_wakeup)(void);
- void (*exit_platform_hw)(void);
- int standby_pin;
- int standby_value;
- int disp_on_pin;
- int disp_on_value;
-};
-#endif
-
-struct ts_hw_data {
- int reset_gpio;
- int touch_en_gpio;
- int (*init_platform_hw)(void);
-};
-
-#if defined(CONFIG_TOUCHSCREEN_BYD693X)
-struct byd_platform_data {
- u16 model;
- int pwr_pin;
- int int_pin;
- int rst_pin;
- int pwr_on_value;
- int *tp_flag;
-
- uint16_t screen_max_x;
- uint16_t screen_max_y;
- u8 swap_xy :1;
- u8 xpol :1;
- u8 ypol :1;
-};
-#endif
-
-struct codec_io_info {
- char iomux_name[50];
- int iomux_mode;
-};
-
-struct rt3261_platform_data {
- unsigned int codec_en_gpio;
- struct codec_io_info codec_en_gpio_info;
- int (*io_init)(int, char *, int);
- unsigned int spk_num;
- unsigned int modem_input_mode;
- unsigned int lout_to_modem_mode;
- unsigned int spk_amplify;
- unsigned int playback_if1_data_control;
- unsigned int playback_if2_data_control;
-};
-
-struct rk610_codec_platform_data {
- unsigned int spk_ctl_io;
- int (*io_init)(void);
- int boot_depop;//if found boot pop,set boot_depop 1 test
- /*
- Some amplifiers enable a longer time.
- config after pa_enable_io delay pa_enable_time(ms)
- default = 0,preferably not more than 1000ms
- so value range is 0 - 1000.
- */
- unsigned int pa_enable_time;
-};
-
-struct rk_hdmi_platform_data {
- int (*io_init)(void);
-};
-#define BOOT_MODE_NORMAL 0
-#define BOOT_MODE_FACTORY2 1
-#define BOOT_MODE_RECOVERY 2
-#define BOOT_MODE_CHARGE 3
-#define BOOT_MODE_POWER_TEST 4
-#define BOOT_MODE_OFFMODE_CHARGING 5
-#define BOOT_MODE_REBOOT 6
-#define BOOT_MODE_PANIC 7
-#define BOOT_MODE_WATCHDOG 8
-int board_boot_mode(void);
-
-static inline const char *boot_mode_name(u32 mode)
-{
- switch (mode) {
- case BOOT_MODE_NORMAL: return "NORMAL";
- case BOOT_MODE_FACTORY2: return "FACTORY2";
- case BOOT_MODE_RECOVERY: return "RECOVERY";
- case BOOT_MODE_CHARGE: return "CHARGE";
- case BOOT_MODE_POWER_TEST: return "POWER_TEST";
- case BOOT_MODE_OFFMODE_CHARGING: return "OFFMODE_CHARGING";
- case BOOT_MODE_REBOOT: return "REBOOT";
- case BOOT_MODE_PANIC: return "PANIC";
- case BOOT_MODE_WATCHDOG: return "WATCHDOG";
- default: return "";
- }
-}
-
-/* for USB detection */
-#if defined(CONFIG_USB_GADGET) && !defined(CONFIG_RK_USB_DETECT_BY_OTG_BVALID)
-int __init board_usb_detect_init(unsigned gpio);
-#else
-static int inline board_usb_detect_init(unsigned gpio) { return 0; }
-#endif
-
-#ifdef CONFIG_RK_EARLY_PRINTK
-void __init rk29_setup_early_printk(void);
-#else
-static void inline rk29_setup_early_printk(void) {}
-#endif
-
-/* for wakeup Android */
-void rk28_send_wakeup_key(void);
-
-/* for reserved memory
- * function: board_mem_reserve_add
- * return value: start address of reserved memory */
-phys_addr_t __init board_mem_reserve_add(char *name, size_t size);
-void __init board_mem_reserved(void);
-
-extern struct rk29_sdmmc_platform_data default_sdmmc0_data;
-extern struct rk29_sdmmc_platform_data default_sdmmc1_data;
-
-extern struct i2c_gpio_platform_data default_i2c_gpio_data;
-extern struct rk29_vmac_platform_data board_vmac_data;
-
-void __init board_clock_init(void);
-void board_gpio_suspend(void);
-void board_gpio_resume(void);
-void __sramfunc board_pmu_suspend(void);
-void __sramfunc board_pmu_resume(void);
-
-/*
- * For DDR frequency scaling setup. Board code something like this:
- *
- * This array _must_ be sorted in ascending frequency (without DDR_FREQ_*) order.
- * static struct cpufreq_frequency_table dvfs_ddr_table[] = {
- * {.frequency = 200 * 1000 + DDR_FREQ_IDLE, .index = xxxx * 1000},
- * {.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = xxxx * 1000},
- * {.frequency = 400 * 1000 + DDR_FREQ_NORMAL, .index = xxxx * 1000},
- * {.frequency = CPUFREQ_TABLE_END},
- *};
- */
-enum ddr_freq_mode {
- DDR_FREQ_SUSPEND=(0x1<<0), // when early suspend
- DDR_FREQ_VIDEO=(0x1<<1), // when video is playing
- DDR_FREQ_VIDEO_LOW=(0x1<<2), // when video is playing low
- DDR_FREQ_DUALVIEW=(0x1<<3), // when dual view,lcdc0 and lcdc1 open at the same time
- DDR_FREQ_IDLE=(0x1<<4), // when screen is idle
- DDR_FREQ_NORMAL=(0x1<<8), // default
-};
-
-#endif
+++ /dev/null
-#ifndef __PLAT_CLKDEV_H
-#define __PLAT_CLKDEV_H
-
-static inline int __clk_get(struct clk *clk)
-{
- return 1;
-}
-
-static inline void __clk_put(struct clk *clk)
-{
-}
-
-#endif
+++ /dev/null
-#ifndef __PLAT_CLOCK_H__
-#define __PLAT_CLOCK_H__
-
-//#define RK30_CLK_OFFBOARD_TEST
-
-
-/* Clock flags */
-/* bit 0 is free */
-#define RATE_FIXED (1 << 1) /* Fixed clock rate */
-#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */
-#define IS_PD (1 << 2) /* Power Domain */
-
-enum _clk_i2s_rate_support {
- i2s_8192khz = 8192000,
- i2s_11289_6khz = 11289600,
- i2s_12288khz = 12288000,
- i2s_22579_2khz = 22579200,
- i2s_24576khz = 24576000,//HDMI
- i2s_49152khz = 24576000,//HDMI
-};
-
-struct _pll_data{
- u8 id;
- void *table;
-};
-//struct clk_node;
-struct clk {
- struct list_head node;
- const char *name;
- struct clk *parent;
- struct list_head children;
- struct list_head sibling; /* node for children */
-
- int (*mode)(struct clk *clk, int on);
- unsigned long (*recalc)(struct clk *); /* if null, follow parent */
- int (*set_rate)(struct clk *, unsigned long);
- long (*round_rate)(struct clk *, unsigned long);
- struct clk* (*get_parent)(struct clk *); /* get clk's parent from the hardware. default is clksel_get_parent if parents present */
- int (*set_parent)(struct clk *, struct clk *); /* default is clksel_set_parent if parents present */
-
- unsigned long rate;
- unsigned long last_set_rate;
- u32 flags;
- s16 usecount;
- u16 notifier_count;
- u8 gate_idx;
- struct _pll_data *pll;
- u32 clksel_con;
- u32 div_mask;
- u32 div_shift;
- u32 div_max;
- u32 src_mask;
- u32 src_shift;
-
- struct clk **parents;
- u8 parents_num;
- struct clk_node *dvfs_info;
-
-};
-
-int __init clk_disable_unused(void);
-void clk_recalculate_root_clocks_nolock(void);
-void clk_recalculate_root_clocks(void);
-int clk_register(struct clk *clk);
-void clk_register_default_ops_clk(struct clk *clk);
-
-int clk_enable_nolock(struct clk *clk);
-void clk_disable_nolock(struct clk *clk);
-long clk_round_rate_nolock(struct clk *clk, unsigned long rate);
-int clk_set_rate_nolock(struct clk *clk, unsigned long rate);
-int clk_set_parent_nolock(struct clk *clk, struct clk *parent);
-int clk_set_rate_locked(struct clk * clk,unsigned long rate);
-void clk_register_dvfs(struct clk_node *dvfs_clk, struct clk *clk);
-int is_suport_round_rate(struct clk *clk);
-int clk_set_enable_locked(struct clk * clk,int on);
-/************************inline fun*****************************/
-static inline struct clk_node *clk_get_dvfs_info(struct clk *clk)
-{
- return clk->dvfs_info;
-}
-static inline s16 clk_used_count(struct clk * clk)
-{
- return (clk->usecount);
-}
-
-#ifdef RK30_CLK_OFFBOARD_TEST
-#include <linux/device.h>
-struct clk *rk30_clk_get(struct device *dev, const char *con_id);
-#endif
-
-#ifdef CONFIG_PROC_FS
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-
-struct clk_dump_ops {
- void (*dump_clk)(struct seq_file *s, struct clk *clk, int deep,const struct list_head *root_clocks);
- void (*dump_regs)(struct seq_file *s);
-};
-
-void clk_register_dump_ops(struct clk_dump_ops *ops);
-#else
-#define clk_register_dump_ops(ops) do {} while (0)
-#endif
-
-/**
- * struct clk_notifier_data - rate data to pass to the notifier callback
- * @clk: struct clk * being changed
- * @old_rate: previous rate of this clock
- * @new_rate: new rate of this clock
- *
- * For a pre-notifier, old_rate is the clock's rate before this rate
- * change, and new_rate is what the rate will be in the future. For a
- * post-notifier, old_rate and new_rate are both set to the clock's
- * current rate (this was done to optimize the implementation).
- */
-struct clk_notifier_data {
- struct clk *clk;
- unsigned long old_rate;
- unsigned long new_rate;
-};
-
-/*
- * Clk notifier callback types
- *
- * Since the notifier is called with interrupts disabled, any actions
- * taken by callbacks must be extremely fast and lightweight.
- *
- * CLK_PRE_RATE_CHANGE - called after all callbacks have approved the
- * rate change, immediately before the clock rate is changed, to
- * indicate that the rate change will proceed. Drivers must
- * immediately terminate any operations that will be affected by
- * the rate change. Callbacks must always return NOTIFY_DONE.
- *
- * CLK_ABORT_RATE_CHANGE: called if the rate change failed for some
- * reason after CLK_PRE_RATE_CHANGE. In this case, all registered
- * notifiers on the clock will be called with
- * CLK_ABORT_RATE_CHANGE. Callbacks must always return
- * NOTIFY_DONE.
- *
- * CLK_POST_RATE_CHANGE - called after the clock rate change has
- * successfully completed. Callbacks must always return
- * NOTIFY_DONE.
- *
- */
-#define CLK_PRE_RATE_CHANGE 1
-#define CLK_POST_RATE_CHANGE 2
-#define CLK_ABORT_RATE_CHANGE 3
-
-#define CLK_PRE_ENABLE 4
-#define CLK_POST_ENABLE 5
-#define CLK_ABORT_ENABLE 6
-
-#define CLK_PRE_DISABLE 7
-#define CLK_POST_DISABLE 8
-#define CLK_ABORT_DISABLE 9
-
-struct notifier_block;
-
-extern int clk_notifier_register(struct clk *clk, struct notifier_block *nb);
-extern int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb);
-
-#endif
+++ /dev/null
-#ifndef __MACH_CONFIG_H
-#define __MACH_CONFIG_H
-#include <mach/board.h>
-//#include <mach/iomux-rk30.h>
-
-//#include <mach/iomux.h>
-#define BOARD_DEFAULT
-//#define BOARD_RK3168_86V
-//#define BOARD_RK3168_86V_RK616
-//#define BOARD_RK3028_86V
-
-#define INVALID_VALUE -1
-#define INVALID_GPIO -1
-
-
-
-enum {
- CODEC_TYPE_NONE = 0,
- CODEC_TYPE_RT5631,
- CODEC_TYPE_ES8323,
- CODEC_TYPE_RK616,
- CODEC_TYPE_MAX,
-};
-
-enum {
- TP_TYPE_NONE = 0,
- TP_TYPE_GSLX680,
- TP_TYPE_GT811_86V,
- TP_TYPE_GT8XX,
- TP_TYPE_MAX,
-};
-
-enum {
- GS_TYPE_NONE = 0,
- GS_TYPE_MMA7660,
- GS_TYPE_LIS3DH,
- GS_TYPE_MXC6225,
- GS_TYPE_DMARAD10,
- GS_TYPE_MMA8452,
- GS_TYPE_LSM303D,
- GS_TYPE_MAX,
-};
-
-enum {
- WIFI_TYPE_NONE = 0,
- WIFI_TYPE_RTL8188CU,
- WIFI_TYPE_RTL8188EU,
- WIFI_TYPE_MT7601,
- WIFI_TYPE_RTL8188ETV,
- WIFI_TYPE_MT5370,
- WIFI_TYPE_MAX,
-};
-
-
-enum {
- OUT_TYPE_INDEX = 0,
- OUT_FACE_INDEX,
- LVDS_FORMAT_INDEX,
- OUT_CLK_INDEX,
- LCDC_ACLK_INDEX,
- H_PW_INDEX,
- H_BP_INDEX,
- H_VD_INDEX,
- H_FP_INDEX,
- V_PW_INDEX,
- V_BP_INDEX,
- V_VD_INDEX,
- V_FP_INDEX,
- LCD_WIDTH_INDEX,
- LCD_HEIGHT_INDEX,
- DCLK_POL_INDEX,
- SWAP_RB_INDEX,
- LCD_PARAM_MAX,
-};
-
-#ifdef BOARD_DEFAULT
-////////////////////////////////////////////////////////////
-/*system*/
-enum {
- DEF_PWR_ON = -1,
-};
-////////////////////////////////////////////////////////////
-/*lcd*/
-enum {
- DEF_LCD_EN = -1,
- DEF_LCD_CS = -1,
- DEF_LCD_STD=-1,
-};
-
-
-#define DEF_LCD_PARAM {SCREEN_RGB, OUT_P888, 0,\
- 50000000, 500000000,\
- 30, 10, 1024, 210,\
- 13, 10, 600, 22,\
- 154, 85,\
- 1, 0 }
-//////////////////////////////////////////////////////////////
-/* backlight */
-
-enum{
- DEF_BL_EN = -1,
- DEF_BL_PWMID =-1,
- DEF_BL_PWM_MOD=-1,
- DEF_BL_MOD = -1,
- DEF_BL_DIV = -1,
- DEF_BL_REF = -1,
- DEF_BL_MIN = -1,
- DEF_BL_MAX = -1,
-};
-//////////////////////////////////////////////////////////////
-/*tp*/
-enum {
- DEF_TP_TYPE= -1,
- DEF_TP_IRQ = -1,
- DEF_TP_RST = -1,
- DEF_TP_I2C = -1,
- DEF_TP_ADDR = -1,
- DEF_X_MAX = -1,
- DEF_Y_MAX = -1,
- DEF_FIRMVER = -1,
-};
-//////////////////////////////////////////////////////////////
-/*key*/
-enum{
- DEF_KEY_ADC = -1,
- DEF_PLAY_KEY = -1,
- DEF_VOLDN_KEY = -1,
- DEF_VOLUP_KEY = -1,
- DEF_MENU_KEY = -1,
- DEF_ESC_KEY = -1,
- DEF_HOME_KEY = -1,
- //DEF_CAM_KEY = -1
- };
-//////////////////////////////////////////////////////////////
-/* gsensor */
-enum {
- DEF_GS_TYPE = -1,
- DEF_GS_IRQ = -1,
- DEF_GS_I2C = -1,
- DEF_GS_ADDR = -1,
-
-};
-#define DEF_GS_ORIG {-1, 0, 0, 0, -1, 0, 0, 0, 1}
-////////////////////////////////////////////////////////////////
-/* codec */
-enum {
- DEF_CODEC_TYPE=-1,
- DEF_CODEC_POWER=-1,
- DEF_CODEC_RST=-1,
- DEF_CODEC_HDMI_IRQ=-1,
- DEF_SPK_CTL = -1,
- DEF_HP_DET = -1,
- DEF_CODEC_I2C= -1,
- DEF_CODEC_ADDR=-1,
-};
-/////////////////////////////////////////////////////////////////
-/* charge */
-enum {
- DEF_DC_DET = -1,
- DEF_BAT_LOW = -1,
- DEF_CHG_OK = -1,
- DEF_CHG_SET = -1,
- DEF_USB_DET = -1,
- DEF_REF_VOL = -1,
- DEF_UP_RES = -1,
- DEF_DOWN_RES = -1,
- DEF_ROOT_CHG = -1,
- DEF_SAVE_CAP = -1,
- DEF_LOW_VOL = -1,
- DEF_NUM = 0,
-};
-#define DEF_BAT_CHARGE {3600, 3700, 3760, 3810, 3870, 3910, 3960, 4020, 4080, 4130, 4180};
-#define DEF_BAT_DISCHARGE {3495, 3570, 3630, 3700, 3740, 3790, 3825, 3865, 3920, 3980, 4050} ;
-//////////////////////////////////////////////////////////////////
-/*wifi*/
-enum {
- DEF_WIFI_TYPE = -1,
- DEF_WIFI_POWER = -1,
-};
-#endif
-
-#ifdef BOARD_RK3168_86V
-////////////////////////////////////////////////////////////
-/*system*/
-enum {
- DEF_PWR_ON = 0x000000a0,
-};
-////////////////////////////////////////////////////////////
-/*lcd*/
-enum {
- DEF_LCD_EN = 0x000100b0,
- DEF_LCD_CS = 0x000003d4,
- DEF_LCD_STD=0x000102c6,
-};
-
-#define DEF_LCD_PARAM {SCREEN_RGB, OUT_P888, 0,\
- 50000000, 500000000, \
- 30, 10, 1024, 210, \
- 13, 10, 600, 22, \
- 154, 85, \
- 0, 0 }
-
-
-//////////////////////////////////////////////////////////////
-/* backlight */
-
-enum{
- DEF_BL_EN = 0x000000a2,
- DEF_BL_PWMID = 3,
- DEF_BL_PWM_MOD=PWM3,
- DEF_BL_MOD = 1,
- DEF_BL_DIV = 20*1000,
- DEF_BL_REF = 0,
- DEF_BL_MIN = 60,
- DEF_BL_MAX = 255,
-};
-//////////////////////////////////////////////////////////////
-/*tp*/
-enum {
- DEF_TP_TYPE= TP_TYPE_GSLX680,
- DEF_TP_IRQ = 0x000001b7,
- DEF_TP_RST = 0x000000b6,
- DEF_TP_I2C = 2,
- DEF_TP_ADDR = 0x40,
- DEF_X_MAX = 1024,
- DEF_Y_MAX = 600,
- DEF_FIRMVER = 0,
-};
-//////////////////////////////////////////////////////////////
-/*key*/
-enum{
- DEF_KEY_ADC = 1,
- DEF_PLAY_KEY = 0x000100a4,
- DEF_VOLDN_KEY = 0x80000096,
- DEF_VOLUP_KEY = 0x80000001,
- DEF_MENU_KEY = 0x80000000,
- DEF_ESC_KEY = 0x80000000,
- DEF_HOME_KEY = 0x80000000,
- };
-//////////////////////////////////////////////////////////////
-/* gsensor */
-enum {
- DEF_GS_TYPE = GS_TYPE_MXC6225,
- DEF_GS_IRQ = 0x008000b7,
- DEF_GS_I2C = 0,
- DEF_GS_ADDR = 0x15,
-
-};
-#define DEF_GS_ORIG {-1, 0, 0, 0, -1, 0, 0, 0, 1}
-////////////////////////////////////////////////////////////////
-/* codec */
-enum {
- DEF_CODEC_TYPE=CODEC_TYPE_ES8323,
- DEF_CODEC_POWER=-1,
- DEF_CODEC_RST=-1,
- DEF_CODEC_HDMI_IRQ=-1,
- DEF_SPK_CTL = 0x000002d7,
- DEF_HP_DET = 0x000000b5,
- DEF_CODEC_I2C= 4,
- DEF_CODEC_ADDR=0x10,
-};
-/////////////////////////////////////////////////////////////////
-/* charge */
-enum {
- DEF_DC_DET = 0x000100b2,
- DEF_BAT_LOW = INVALID_GPIO,
- DEF_CHG_OK = 0x000000a6,
- DEF_CHG_SET = INVALID_GPIO,
- DEF_USB_DET = INVALID_GPIO,
- DEF_REF_VOL = 1800,
- DEF_UP_RES = 200,
- DEF_DOWN_RES = 120,
- DEF_ROOT_CHG = 1,
- DEF_SAVE_CAP = 1,
- DEF_LOW_VOL = 3600,
- DEF_NUM = 0,
-};
-#define DEF_BAT_CHARGE {3600, 3700, 3760, 3810, 3870, 3910, 3960, 4020, 4080, 4130, 4180};
-#define DEF_BAT_DISCHARGE {3495, 3570, 3630, 3700, 3740, 3790, 3825, 3865, 3920, 3980, 4050};
-//////////////////////////////////////////////////////////////////
-/*wifi*/
-enum {
- DEF_WIFI_TYPE = WIFI_TYPE_RTL8188EU,
- DEF_WIFI_POWER = 0x000100d5,
-};
-#endif
-
-#ifdef BOARD_RK3168_86V_RK616
-////////////////////////////////////////////////////////////
-/*system*/
-enum {
- DEF_PWR_ON = 0x000000a0,
-};
-////////////////////////////////////////////////////////////
-/*lcd*/
-enum {
- DEF_LCD_EN = 0x000100b0,
- DEF_LCD_CS = 0x000003d4,
- DEF_LCD_STD=0x000102c6,
-};
-/*
-#define DEF_LCD_PARAM {SCREEN_RGB, OUT_P888, \
- 50000000, 500000000, \
- 30, 10, 1024, 210, \
- 13, 10, 600, 22, \
- 154, 85, \
- 1, 0 }
-*/
-
-#define DEF_LCD_PARAM {SCREEN_RGB, OUT_P888,0,\
- 33000000, 150000000,\
- 1,88,800,40,\
- 3,29,480,13,\
- 154, 85,\
- 0, 0 }
-
-//////////////////////////////////////////////////////////////
-/* backlight */
-
-enum{
- DEF_BL_EN = 0x000000a2,
- DEF_BL_PWMID = 3,
- DEF_BL_PWM_MOD=PWM3,
- DEF_BL_MOD = 1,
- DEF_BL_DIV = 20*1000,
- DEF_BL_REF = 0,
- DEF_BL_MIN = 60,
- DEF_BL_MAX = 255,
-};
-//////////////////////////////////////////////////////////////
-/*tp*/
-enum {
- DEF_TP_TYPE= TP_TYPE_GSLX680,
- DEF_TP_IRQ = 0x000001b7,
- DEF_TP_RST = 0x000000b6,
- DEF_TP_I2C = 2,
- DEF_TP_ADDR = 0x40,
- DEF_X_MAX = 1024,
- DEF_Y_MAX = 600,
- DEF_FIRMVER= 0,
-};
-//////////////////////////////////////////////////////////////
-/*key*/
-enum{
- DEF_KEY_ADC = 1,
- DEF_PLAY_KEY = 0x000100a4,
- DEF_VOLDN_KEY = 0x80000096,
- DEF_VOLUP_KEY = 0x80000001,
- DEF_MENU_KEY = 0x80000000,
- DEF_ESC_KEY = 0x80000000,
- DEF_HOME_KEY = 0x80000000,
- };
-//////////////////////////////////////////////////////////////
-/* gsensor */
-enum {
- DEF_GS_TYPE = GS_TYPE_MMA7660,
- DEF_GS_IRQ = 0x008000b7,
- DEF_GS_I2C = 0,
- DEF_GS_ADDR = 0x4c,
-
-};
-#define DEF_GS_ORIG {1, 0, 0, 0, -1, 0, 0, 0, 1}
-////////////////////////////////////////////////////////////////
-/* codec */
-enum {
- DEF_CODEC_TYPE=CODEC_TYPE_RK616,
- DEF_CODEC_POWER=0x000000a3,
- DEF_CODEC_RST=0x000003b2,
- DEF_CODEC_HDMI_IRQ=0x000002d6,
- DEF_SPK_CTL = 0x000002d7,
- DEF_HP_DET = -1,
- DEF_CODEC_I2C= 4,
- DEF_CODEC_ADDR=0x50,
-};
-/////////////////////////////////////////////////////////////////
-/* charge */
-enum {
- DEF_DC_DET = 0x000100b2,
- DEF_BAT_LOW = INVALID_GPIO,
- DEF_CHG_OK = 0x000000a6,
- DEF_CHG_SET = INVALID_GPIO,
- DEF_USB_DET = INVALID_GPIO,
- DEF_REF_VOL = 1800,
- DEF_UP_RES = 200,
- DEF_DOWN_RES = 120,
- DEF_ROOT_CHG = 1,
- DEF_SAVE_CAP = 1,
- DEF_LOW_VOL = 3600,
- DEF_NUM = 0,
-};
-#define DEF_BAT_CHARGE {3600, 3700, 3760, 3810, 3870, 3910, 3960, 4020, 4080, 4130, 4180};
-#define DEF_BAT_DISCHARGE {3495, 3570, 3630, 3700, 3740, 3790, 3825, 3865, 3920, 3980, 4050} ;
-//////////////////////////////////////////////////////////////////
-/*wifi*/
-enum {
- DEF_WIFI_TYPE = WIFI_TYPE_RTL8188EU,
- DEF_WIFI_POWER = 0x000100d5,
-};
-#endif
-
-#ifdef BOARD_RK3028_86V
-////////////////////////////////////////////////////////////
-/*system*/
-enum {
- DEF_PWR_ON = 0x000001a1,
-};
-////////////////////////////////////////////////////////////
-/*lcd*/
-enum {
- DEF_LCD_EN = 0x000103d2,
- DEF_LCD_CS = -1,
- DEF_LCD_STD=-1,
-};
-
-#define DEF_LCD_PARAM {SCREEN_RGB, OUT_P666, 0,\
- 50000000, 500000000, \
- 30, 10, 1024, 210, \
- 13, 10, 600, 22, \
- 154, 85, \
- 0, 0 }
-
-
-//////////////////////////////////////////////////////////////
-/* backlight */
-
-enum{
- DEF_BL_EN = 0x000003c5,
- DEF_BL_PWMID = 0,
- DEF_BL_PWM_MOD=PWM0,
- DEF_BL_MOD = 1,
- DEF_BL_DIV = 20*1000,
- DEF_BL_REF = 0,
- DEF_BL_MIN = 60,
- DEF_BL_MAX = 255,
-};
-//////////////////////////////////////////////////////////////
-/*tp*/
-enum {
- DEF_TP_TYPE= TP_TYPE_GSLX680,
- DEF_TP_IRQ = 0x000103c7,
- DEF_TP_RST = 0x000003c3,
- DEF_TP_I2C = 2,
- DEF_TP_ADDR = 0x40,
- DEF_X_MAX = 1024,
- DEF_Y_MAX = 600,
- DEF_FIRMVER = 0,
-};
-//////////////////////////////////////////////////////////////
-/*key*/
-enum{
- DEF_KEY_ADC = 1,
- DEF_PLAY_KEY = 0x000100a4,
- DEF_VOLDN_KEY = 0x80000000,
- DEF_VOLUP_KEY = 0x80000000,
- DEF_MENU_KEY = 0x80000000,
- DEF_ESC_KEY = 0x80000000,
- DEF_HOME_KEY = 0x80000000,
- };
-//////////////////////////////////////////////////////////////
-/* gsensor */
-enum {
- DEF_GS_TYPE = GS_TYPE_MXC6225,
- DEF_GS_IRQ = 0x008000b7,
- DEF_GS_I2C = 0,
- DEF_GS_ADDR = 0x15,
-
-};
-#define DEF_GS_ORIG {-1, 0, 0, 0, -1, 0, 0, 0, 1}
-////////////////////////////////////////////////////////////////
-/* codec */
-enum {
- DEF_CODEC_TYPE=CODEC_TYPE_ES8323,
- DEF_CODEC_POWER=-1,
- DEF_CODEC_RST=-1,
- DEF_CODEC_HDMI_IRQ=-1,
- DEF_SPK_CTL = 0x000002d7,
- DEF_HP_DET = 0x000000b5,
- DEF_CODEC_I2C= 4,
- DEF_CODEC_ADDR=0x10,
-};
-/////////////////////////////////////////////////////////////////
-/* charge */
-enum {
- DEF_DC_DET = 0x000101b4,
- DEF_BAT_LOW = INVALID_GPIO,
- DEF_CHG_OK = 0x000001a0,
- DEF_CHG_SET = INVALID_GPIO,
- DEF_USB_DET = INVALID_GPIO,
- DEF_REF_VOL = 3300,
- DEF_UP_RES = 200,
- DEF_DOWN_RES = 120,
- DEF_ROOT_CHG = 1,
- DEF_SAVE_CAP = 1,
- DEF_LOW_VOL = 3600,
- DEF_NUM = 0,
-};
-#define DEF_BAT_CHARGE {3600, 3700, 3760, 3810, 3870, 3910, 3960, 4020, 4080, 4130, 4180};
-#define DEF_BAT_DISCHARGE {3495, 3570, 3630, 3700, 3740, 3790, 3825, 3865, 3920, 3980, 4050};
-//////////////////////////////////////////////////////////////////
-/*wifi*/
-enum {
- DEF_WIFI_TYPE = WIFI_TYPE_RTL8188EU,
- DEF_WIFI_POWER = 0x000103d3,
-};
-#endif
-
-#endif
-
-
-
-
+++ /dev/null
-#ifndef __PLAT_CPU_H
-#define __PLAT_CPU_H
-
-#include <mach/io.h>
-#include <mach/gpio.h>
-#include <linux/io.h>
-
-#ifdef CONFIG_ARCH_RK2928
-#define SOC_RK2928G 0x01
-#define SOC_RK2928L 0x02
-#define SOC_RK2926 0x00
-
-static inline bool soc_is_rk2928g(void)
-{
- return ((readl_relaxed(RK2928_GPIO3_BASE + 0x50) & 0x07) == SOC_RK2928G);
-}
-
-static inline bool soc_is_rk2928l(void)
-{
- return ((readl_relaxed(RK2928_GPIO3_BASE + 0x50) & 0x07) == SOC_RK2928L);
-}
-
-static inline bool soc_is_rk2926(void)
-{
- return ((readl_relaxed(RK2928_GPIO3_BASE + 0x50) & 0x07) == SOC_RK2926);
-}
-
-static inline bool cpu_is_rk2928(void) { return true; }
-#else
-static inline bool cpu_is_rk2928(void) { return false; }
-static inline bool soc_is_rk2928g(void) { return false; }
-static inline bool soc_is_rk2928l(void) { return false; }
-static inline bool soc_is_rk2926(void) { return false; }
-#endif
-
-#if defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK3188) || defined(CONFIG_ARCH_RK3026) || defined(CONFIG_ARCH_RK319X)
-static inline bool cpu_is_rk30xx(void)
-{
- return readl_relaxed(RK30_ROM_BASE + 0x27f0) == 0x33303041
- && readl_relaxed(RK30_ROM_BASE + 0x27f4) == 0x32303131
- && readl_relaxed(RK30_ROM_BASE + 0x27f8) == 0x31313131
- && readl_relaxed(RK30_ROM_BASE + 0x27fc) == 0x56313031;
-}
-
-static inline bool cpu_is_rk3066b(void)
-{
- return(readl_relaxed(RK30_ROM_BASE + 0x27f0) == 0x33303041
- && readl_relaxed(RK30_ROM_BASE + 0x27f4) == 0x32303131
- && readl_relaxed(RK30_ROM_BASE + 0x27f8) == 0x31313131
- && readl_relaxed(RK30_ROM_BASE + 0x27fc) == 0x56313030)
- ||(readl_relaxed(RK30_ROM_BASE + 0x27f0) == 0x33303042
- && readl_relaxed(RK30_ROM_BASE + 0x27f4) == 0x32303132
- && readl_relaxed(RK30_ROM_BASE + 0x27f8) == 0x31303031
- && readl_relaxed(RK30_ROM_BASE + 0x27fc) == 0x56313030);
-}
-
-static inline bool soc_is_rk3188(void)
-{
- return readl_relaxed(RK30_ROM_BASE + 0x27f0) == 0x33313042
- && readl_relaxed(RK30_ROM_BASE + 0x27f4) == 0x32303132
- && readl_relaxed(RK30_ROM_BASE + 0x27f8) == 0x31313330
- && readl_relaxed(RK30_ROM_BASE + 0x27fc) == 0x56313030;
-}
-
-static inline bool soc_is_rk3188plus(void)
-{
- return readl_relaxed(RK30_ROM_BASE + 0x27f0) == 0x33313042
- && readl_relaxed(RK30_ROM_BASE + 0x27f4) == 0x32303133
- && readl_relaxed(RK30_ROM_BASE + 0x27f8) == 0x30313331
- && readl_relaxed(RK30_ROM_BASE + 0x27fc) == 0x56313031;
-}
-
-static inline bool cpu_is_rk3026(void)
-{
- return readl_relaxed(RK30_ROM_BASE + 0x3ff0) == 0x32393243
- && readl_relaxed(RK30_ROM_BASE + 0x3ff4) == 0x32303133
- && readl_relaxed(RK30_ROM_BASE + 0x3ff8) == 0x30353239
- && readl_relaxed(RK30_ROM_BASE + 0x3ffc) == 0x56313031;
-}
-
-static inline bool cpu_is_rk319x(void)
-{
- return readl_relaxed(RK30_ROM_BASE + 0x3ff0) == 0x33313042
- && readl_relaxed(RK30_ROM_BASE + 0x3ff4) == 0x32303133
- && readl_relaxed(RK30_ROM_BASE + 0x3ff8) == 0x30383237
- && readl_relaxed(RK30_ROM_BASE + 0x3ffc) == 0x56313031;
-}
-#else
-static inline bool cpu_is_rk30xx(void) { return false; }
-static inline bool cpu_is_rk3066b(void) { return false; }
-static inline bool soc_is_rk3188(void) { return false; }
-static inline bool soc_is_rk3188plus(void) { return false; }
-static inline bool cpu_is_rk3026(void) { return false; }
-static inline bool cpu_is_rk319x(void) { return false; }
-#endif
-
-#if defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK3188)
-static inline bool soc_is_rk3066b(void)
-{
- return cpu_is_rk3066b() && (((readl_relaxed(RK30_GPIO1_BASE + GPIO_EXT_PORT) >> 22) & 3) == 0);
-}
-
-static inline bool soc_is_rk3108(void)
-{
- return cpu_is_rk3066b() && (((readl_relaxed(RK30_GPIO1_BASE + GPIO_EXT_PORT) >> 22) & 3) == 1);
-}
-
-static inline bool soc_is_rk3168m(void)
-{
- return cpu_is_rk3066b() && (((readl_relaxed(RK30_GPIO1_BASE + GPIO_EXT_PORT) >> 22) & 3) == 3);
-}
-#else
-static inline bool soc_is_rk3066b(void) { return false; }
-static inline bool soc_is_rk3108(void) { return false; }
-static inline bool soc_is_rk3168m(void) { return false; }
-#endif
-
-static inline bool cpu_is_rk3188(void)
-{
- return soc_is_rk3188plus() || soc_is_rk3188();
-}
-
-#ifdef CONFIG_SOC_RK3188M
-static inline bool soc_is_rk3188m(void) { return true; }
-#else
-static inline bool soc_is_rk3188m(void) { return false; }
-#endif
-
-static inline bool soc_is_rk3028(void) { return soc_is_rk3168m(); }
-static inline bool soc_is_rk3168(void) { return soc_is_rk3108(); }
-
-#ifdef CONFIG_SOC_RK3000
-static inline bool soc_is_rk3000(void) { return true; }
-#else
-static inline bool soc_is_rk3000(void) { return false; }
-#endif
-
-#ifdef CONFIG_SOC_RK3066
-static inline bool soc_is_rk3066(void) { return true; }
-#else
-static inline bool soc_is_rk3066(void) { return false; }
-#endif
-
-#ifdef CONFIG_SOC_RK3068
-static inline bool soc_is_rk3068(void) { return true; }
-#else
-static inline bool soc_is_rk3068(void) { return false; }
-#endif
-
-#ifdef CONFIG_ARCH_RK3026
-static inline bool soc_is_rk3026(void)
-{
- return cpu_is_rk3026() && ((readl_relaxed(RK2928_GPIO3_BASE + GPIO_EXT_PORT) & 7) == 4);
-}
-
-static inline bool soc_is_rk3028a(void)
-{
- return cpu_is_rk3026() && ((readl_relaxed(RK2928_GPIO3_BASE + GPIO_EXT_PORT) & 7) == 3);
-}
-#else
-static inline bool soc_is_rk3026(void) { return false; }
-static inline bool soc_is_rk3028a(void) { return false; }
-#endif
-
-#ifdef CONFIG_SOC_RK3190
-static inline bool soc_is_rk3190(void) { return true; }
-#else
-static inline bool soc_is_rk3190(void) { return false; }
-#endif
-
-#endif
+++ /dev/null
-#ifndef __PLAT_CPU_AXI_H
-#define __PLAT_CPU_AXI_H
-
-#define CPU_AXI_QOS_PRIORITY 0x08
-#define CPU_AXI_QOS_MODE 0x0c
-#define CPU_AXI_QOS_BANDWIDTH 0x10
-#define CPU_AXI_QOS_SATURATION 0x14
-
-#define CPU_AXI_QOS_MODE_NONE 0
-#define CPU_AXI_QOS_MODE_FIXED 1
-#define CPU_AXI_QOS_MODE_LIMITER 2
-#define CPU_AXI_QOS_MODE_REGULATOR 3
-
-#define CPU_AXI_QOS_PRIORITY_LEVEL(h, l) (((h & 3) << 2) | (l & 3))
-#define CPU_AXI_SET_QOS_PRIORITY(h, l, NAME) \
- writel_relaxed(CPU_AXI_QOS_PRIORITY_LEVEL(h, l), CPU_AXI_##NAME##_QOS_BASE + CPU_AXI_QOS_PRIORITY)
-#define CPU_AXI_QOS_NUM_REGS 4
-#define CPU_AXI_SAVE_QOS(array, NAME) do { \
- array[0] = readl_relaxed(CPU_AXI_##NAME##_QOS_BASE + CPU_AXI_QOS_PRIORITY); \
- array[1] = readl_relaxed(CPU_AXI_##NAME##_QOS_BASE + CPU_AXI_QOS_MODE); \
- array[2] = readl_relaxed(CPU_AXI_##NAME##_QOS_BASE + CPU_AXI_QOS_BANDWIDTH); \
- array[3] = readl_relaxed(CPU_AXI_##NAME##_QOS_BASE + CPU_AXI_QOS_SATURATION); \
-} while (0)
-#define CPU_AXI_RESTORE_QOS(array, NAME) do { \
- writel_relaxed(array[0], CPU_AXI_##NAME##_QOS_BASE + CPU_AXI_QOS_PRIORITY); \
- writel_relaxed(array[1], CPU_AXI_##NAME##_QOS_BASE + CPU_AXI_QOS_MODE); \
- writel_relaxed(array[2], CPU_AXI_##NAME##_QOS_BASE + CPU_AXI_QOS_BANDWIDTH); \
- writel_relaxed(array[3], CPU_AXI_##NAME##_QOS_BASE + CPU_AXI_QOS_SATURATION); \
-} while (0)
-
-#endif
+++ /dev/null
-/*
- *
- * Copyright (C) 2011 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __PLAT_DDR_H
-#define __PLAT_DDR_H
-
-#include <linux/types.h>
-#include <mach/sram.h>
-
-#ifdef CONFIG_DDR_SDRAM_FREQ
-#define DDR_FREQ (CONFIG_DDR_SDRAM_FREQ)
-#else
-#define DDR_FREQ 0
-#endif
-
-#define DDR3_800D (0) // 5-5-5
-#define DDR3_800E (1) // 6-6-6
-#define DDR3_1066E (2) // 6-6-6
-#define DDR3_1066F (3) // 7-7-7
-#define DDR3_1066G (4) // 8-8-8
-#define DDR3_1333F (5) // 7-7-7
-#define DDR3_1333G (6) // 8-8-8
-#define DDR3_1333H (7) // 9-9-9
-#define DDR3_1333J (8) // 10-10-10
-#define DDR3_1600G (9) // 8-8-8
-#define DDR3_1600H (10) // 9-9-9
-#define DDR3_1600J (11) // 10-10-10
-#define DDR3_1600K (12) // 11-11-11
-#define DDR3_1866J (13) // 10-10-10
-#define DDR3_1866K (14) // 11-11-11
-#define DDR3_1866L (15) // 12-12-12
-#define DDR3_1866M (16) // 13-13-13
-#define DDR3_2133K (17) // 11-11-11
-#define DDR3_2133L (18) // 12-12-12
-#define DDR3_2133M (19) // 13-13-13
-#define DDR3_2133N (20) // 14-14-14
-#define DDR3_DEFAULT (21)
-#define DDR_DDR2 (22)
-#define DDR_LPDDR (23)
-#define DDR_LPDDR2 (24)
-
-#ifdef CONFIG_DDR_TYPE_DDR3_800D
-#define DDR_TYPE DDR3_800D
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_800E
-#define DDR_TYPE DDR3_800E
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_1066E
-#define DDR_TYPE DDR3_1066E
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_1066F
-#define DDR_TYPE DDR3_1066F
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_1066G
-#define DDR_TYPE DDR3_1066G
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_1333F
-#define DDR_TYPE DDR3_1333F
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_1333G
-#define DDR_TYPE DDR3_1333G
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_1333H
-#define DDR_TYPE DDR3_1333H
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_1333J
-#define DDR_TYPE DDR3_1333J
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_1600G
-#define DDR_TYPE DDR3_1600G
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_1600H
-#define DDR_TYPE DDR3_1600H
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_1600J
-#define DDR_TYPE DDR3_1600J
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_1866J
-#define DDR_TYPE DDR3_1866J
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_1866K
-#define DDR_TYPE DDR3_1866K
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_1866L
-#define DDR_TYPE DDR3_1866L
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_1866M
-#define DDR_TYPE DDR3_1866M
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_2133K
-#define DDR_TYPE DDR3_2133K
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_2133L
-#define DDR_TYPE DDR3_2133L
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_2133M
-#define DDR_TYPE DDR3_2133M
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_2133N
-#define DDR_TYPE DDR3_2133N
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDR3_DEFAULT
-#define DDR_TYPE DDR3_DEFAULT
-#endif
-
-#ifdef CONFIG_DDR_TYPE_DDRII
-#define DDR_TYPE DDR_DDRII
-#endif
-
-#ifdef CONFIG_DDR_TYPE_LPDDR
-#define DDR_TYPE DDR_LPDDR
-#endif
-
-struct ddr_freq_t {
- unsigned long screen_ft_us;
- unsigned long long t0;
- unsigned long long t1;
- unsigned long t2;
-};
-
-void __sramfunc ddr_suspend(void);
-void __sramfunc ddr_resume(void);
-//void __sramlocalfunc delayus(uint32_t us);
-uint32_t ddr_change_freq(uint32_t nMHz);
-uint32_t __sramfunc ddr_change_freq_sram(uint32_t nMHz , struct ddr_freq_t ddr_freq_t);
-uint32_t ddr_get_cap(void);
-int ddr_init(uint32_t dram_type, uint32_t freq);
-void ddr_set_auto_self_refresh(bool en);
-uint32_t __sramlocalfunc ddr_set_pll(uint32_t nMHz, uint32_t set);
-uint32_t __sramlocalfunc ddr_set_pll_rk3066b(uint32_t nMHz, uint32_t set);
-#if defined(CONFIG_ARCH_RK3066B)
-int ddr_get_datatraing_value_3168(bool end_flag,uint32_t dqstr_value,uint32_t min_freq);
-#endif
-
-#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188) || defined(CONFIG_ARCH_RK3026)
-#if !defined(CONFIG_MACH_RK3188_FT)&&!defined(CONFIG_MACH_RK3168_FT) && !defined(CONFIG_MACH_RK3026_FT)
-#define DDR_CHANGE_FREQ_IN_LCDC_VSYNC
-#endif
-#endif
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <mach/io.h>
-#include <mach/debug_uart.h>
-
-#ifdef DEBUG_UART_PHYS
- .macro addruart, rp, rv
- ldr \rp, = DEBUG_UART_PHYS
- ldr \rv, = DEBUG_UART_BASE
- .endm
-
-#define UART_SHIFT 2
-#include <asm/hardware/debug-8250.S>
-#else
- .macro addruart, rp, rv
- .endm
- .macro senduart, rd, rx
- .endm
- .macro busyuart, rd, rx
- .endm
- .macro waituart, rd, rx
- .endm
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2010 RockChip Electronics Co. Ltd.
- * ZhenFu Fang <fzf@rock-chips.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef __RK29_DMA_PL330_H_
-#define __RK29_DMA_PL330_H_
-
-#define RK29_DMAF_AUTOSTART (1 << 0)
-#define RK29_DMAF_CIRCULAR (1 << 1)
-
-enum rk29_dma_buffresult {
- RK29_RES_OK,
- RK29_RES_ERR,
- RK29_RES_ABORT
-};
-
-enum rk29_dmasrc {
- RK29_DMASRC_HW, /* source is memory */
- RK29_DMASRC_MEM, /* source is hardware */
- RK29_DMASRC_MEMTOMEM
-};
-
-/* enum rk29_chan_op
- *
- * operation codes passed to the DMA code by the user, and also used
- * to inform the current channel owner of any changes to the system state
-*/
-
-enum rk29_chan_op {
- RK29_DMAOP_START,
- RK29_DMAOP_STOP,
- RK29_DMAOP_PAUSE,
- RK29_DMAOP_RESUME,
- RK29_DMAOP_FLUSH,
- RK29_DMAOP_TIMEOUT, /* internal signal to handler */
- RK29_DMAOP_STARTED, /* indicate channel started */
-};
-
-struct rk29_dma_client {
- char *name;
-};
-
-/* rk29_dma_cbfn_t
- *
- * buffer callback routine type
-*/
-
-typedef void (*rk29_dma_cbfn_t)(void *buf, int size,
- enum rk29_dma_buffresult result);
-
-typedef int (*rk29_dma_opfn_t)(enum rk29_chan_op );
-
-/*
- * PL330 can assign any channel to communicate with
- * any of the peripherals attched to the DMAC.
- * For the sake of consistency across client drivers,
- * We keep the channel names unchanged and only add
- * missing peripherals are added.
- * Order is not important since rk PL330 API driver
- * use these just as IDs.
- */
-enum dma_ch {
-
- DMACH_UART0_TX,
- DMACH_UART0_RX,
- DMACH_UART1_TX,
- DMACH_UART1_RX,
- DMACH_I2S0_8CH_TX,
- DMACH_I2S0_8CH_RX,
- DMACH_I2S1_2CH_TX,
- DMACH_I2S1_2CH_RX,
- DMACH_SPDIF_TX,
- DMACH_I2S2_2CH_TX,
- DMACH_I2S2_2CH_RX,
-
- DMACH_HSADC,
- DMACH_SDMMC,
- DMACH_SDIO,
- DMACH_EMMC,
- DMACH_PID_FILTER,
- DMACH_UART2_TX,
- DMACH_UART2_RX,
- DMACH_UART3_TX,
- DMACH_UART3_RX,
- DMACH_SPI0_TX,
- DMACH_SPI0_RX,
- DMACH_SPI1_TX,
- DMACH_SPI1_RX,
- DMACH_DMAC0_MEMTOMEM,
- DMACH_DMAC1_MEMTOMEM,
- DMACH_DMAC2_MEMTOMEM,
- DMACH_DMAC3_MEMTOMEM,
- DMACH_DMAC4_MEMTOMEM,
- DMACH_DMAC5_MEMTOMEM,
- DMACH_DMAC6_MEMTOMEM,
- DMACH_DMAC7_MEMTOMEM,
- /* END Marker, also used to denote a reserved channel */
- DMACH_MAX,
-};
-
-static inline bool rk29_dma_has_circular(void)
-{
- return true;
-}
-static inline bool rk29_dma_has_infiniteloop(void)
-{
- return true;
-}
-/*
- * Every PL330 DMAC has max 32 peripheral interfaces,
- * of which some may be not be really used in your
- * DMAC's configuration.
- * Populate this array of 32 peri i/fs with relevant
- * channel IDs for used peri i/f and DMACH_MAX for
- * those unused.
- *
- * The platforms just need to provide this info
- * to the rk DMA API driver for PL330.
- */
-struct rk29_pl330_platdata {
- enum dma_ch peri[32];
-};
-
-
-
-/* rk29_dma_request
- *
- * request a dma channel exclusivley
-*/
-
-extern int rk29_dma_request(unsigned int channel,
- struct rk29_dma_client *, void *dev);
-
-
-/* rk29_dma_ctrl
- *
- * change the state of the dma channel
-*/
-
-extern int rk29_dma_ctrl(unsigned int channel, enum rk29_chan_op op);
-
-/* rk29_dma_setflags
- *
- * set the channel's flags to a given state
-*/
-
-extern int rk29_dma_setflags(unsigned int channel,
- unsigned int flags);
-
-/* rk29_dma_free
- *
- * free the dma channel (will also abort any outstanding operations)
-*/
-
-extern int rk29_dma_free(unsigned int channel, struct rk29_dma_client *);
-
-/* rk29_dma_enqueue_ring
- *
- * place the given buffer onto the queue of operations for the channel.
- * The buffer must be allocated from dma coherent memory, or the Dcache/WB
- * drained before the buffer is given to the DMA system.
-*/
-
-extern int rk29_dma_enqueue_ring(enum dma_ch channel, void *id,
- dma_addr_t data, int size, int numofblock, bool sev);
-
-/* rk29_dma_enqueue
- *
- * place the given buffer onto the queue of operations for the channel.
- * The buffer must be allocated from dma coherent memory, or the Dcache/WB
- * drained before the buffer is given to the DMA system.
-*/
-
-extern int rk29_dma_enqueue(enum dma_ch channel, void *id,
- dma_addr_t data, int size);
-
-
-/* rk29_dma_config
- *
- * configure the dma channel
-*/
-
-extern int rk29_dma_config(unsigned int channel, int xferunit, int brst_len);
-
-/* rk29_dma_devconfig
- *
- * configure the device we're talking to
-*/
-
-extern int rk29_dma_devconfig(unsigned int channel,
- enum rk29_dmasrc source, unsigned long devaddr);
-
-/* rk29_dma_getposition
- *
- * get the position that the dma transfer is currently at
-*/
-
-extern int rk29_dma_getposition(unsigned int channel,
- dma_addr_t *src, dma_addr_t *dest);
-
-extern int rk29_dma_set_opfn(unsigned int, rk29_dma_opfn_t rtn);
-extern int rk29_dma_set_buffdone_fn(unsigned int, rk29_dma_cbfn_t rtn);
-
-#endif /* __RK29_DMA_PL330_H_ */
+++ /dev/null
-/* arch/arm/mach-rk30/rk30_dvfs.h\r
- *\r
- * Copyright (C) 2012 ROCKCHIP, Inc.\r
- *\r
- * This software is licensed under the terms of the GNU General Public\r
- * License version 2, as published by the Free Software Foundation, and\r
- * may be copied, distributed, and modified under those terms.\r
- *\r
- * This program is distributed in the hope that it will be useful,\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- * GNU General Public License for more details.\r
- *\r
- */\r
-#ifndef _RK30_DVFS_H_\r
-#define _RK30_DVFS_H_\r
-\r
-#include <mach/clock.h>\r
-\r
-//typedef int (*vd_dvfs_target_callback)(struct clk *clk, unsigned long rate);\r
-typedef int (*dvfs_set_rate_callback)(struct clk *clk, unsigned long rate);\r
-typedef int (*clk_dvfs_target_callback)(struct clk *clk, unsigned long rate,\r
- dvfs_set_rate_callback set_rate);\r
-typedef int (*dvfs_clk_disable_callback)(struct clk *clk,int on);\r
-\r
-/**\r
- * struct vd_node: To Store All Voltage Domains' info\r
- * @name: Voltage Domain's Name\r
- * @regulator_name: Voltage domain's regulator name\r
- * @cur_volt: Voltage Domain's Current Voltage\r
- * @regulator: Voltage Domain's regulator point\r
- * @node: Point of he Voltage Domain List Node\r
- * @pd_list: Head of Power Domain List Belongs to This Voltage Domain\r
- * @req_volt_list: The list of clocks requests\r
- * @dvfs_mutex: Lock\r
- * @vd_dvfs_target: Callback function \r
- */\r
- #define VD_VOL_LIST_CNT (200)\r
- #define VD_LIST_RELATION_L 0\r
- #define VD_LIST_RELATION_H 1\r
-\r
-struct vd_node {\r
- char *name;\r
- char *regulator_name;\r
- int volt_time_flag;// =0 ,is no initing checking ,>0 ,support,<0 not support\r
- int mode_flag;// =0 ,is no initing checking ,>0 ,support,<0 not support\r
- int cur_volt;\r
- int volt_set_flag;\r
- struct regulator *regulator;\r
- struct list_head node;\r
- struct list_head pd_list;\r
- struct list_head req_volt_list;\r
- //struct mutex dvfs_mutex;\r
- dvfs_clk_disable_callback vd_clk_disable_target;\r
- dvfs_set_rate_callback vd_dvfs_target;\r
- unsigned n_voltages;\r
- int volt_list[VD_VOL_LIST_CNT];\r
-};\r
-\r
-/**\r
- * struct pd_node: To Store All Power Domains' info\r
- * @name: Power Domain's Name\r
- * @cur_volt: Power Domain's Current Voltage\r
- * @pd_status: Power Domain's status\r
- * @vd: Voltage Domain the power domain belongs to\r
- * @pd_clk: Look power domain as a clock\r
- * @node: List node to Voltage Domain\r
- * @clk_list: Head of Power Domain's Clocks List\r
- */\r
-struct pd_node {\r
- char *name;\r
- int cur_volt;\r
- unsigned char pd_status;\r
- struct vd_node *vd;\r
- //struct clk *pd_clk;\r
- struct list_head node;\r
- struct list_head clk_list;\r
-};\r
-\r
-struct pd_node_lookup {\r
- struct pd_node *pd;\r
-};\r
-\r
-struct clk_list{\r
- struct clk_node *dvfs_clk;\r
- struct list_head node;\r
-};\r
-\r
-struct pds_list {\r
- struct clk_list clk_list;\r
- struct pd_node *pd;\r
-};\r
-\r
-struct depend_list {\r
- int req_volt;\r
- struct clk_node *dvfs_clk;\r
- struct vd_node *dep_vd;\r
- struct list_head node2clk;\r
- struct list_head node2vd;\r
- struct cpufreq_frequency_table *dep_table;\r
-};\r
-\r
-struct depend_lookup {\r
- char *clk_name;\r
- struct clk_node *dvfs_clk;\r
- struct vd_node *dep_vd;\r
- struct depend_list dep_list;\r
- struct cpufreq_frequency_table *dep_table;\r
-};\r
-struct clk_disable_ctr {\r
- dvfs_clk_disable_callback clk_disable_target;\r
- struct clk_node *dvfs_clk;\r
-};\r
-/**\r
- * struct clk_node: To Store All dvfs clocks' info\r
- * @name: Dvfs clock's Name\r
- * @set_freq: Dvfs clock's Current Frequency\r
- * @set_volt: Dvfs clock's Current Voltage\r
- * @enable_dvfs: Sign if DVFS clock enable\r
- * @clk: System clk's point\r
- * @pds: Power Domains dvfs clock belongs to\r
- * @vd: Voltage Domains dvfs clock belongs to\r
- * @depend_list: Dvfs Clock depend list\r
- * @dvfs_nb: Notify list\r
- * @dvfs_table: Frequency and voltage table for dvfs\r
- * @clk_dvfs_target: Callback function\r
- */\r
-struct clk_node {\r
- char *name;\r
- int set_freq; //KHZ\r
- int set_volt; //MV\r
- int enable_dvfs;\r
- int freq_limit_en; //sign if use limit frequency\r
- unsigned int min_rate; //limit min frequency\r
- unsigned int max_rate; //limit max frequency\r
- struct clk *clk;\r
- struct pds_list *pds;\r
- struct vd_node *vd;\r
- struct list_head depend_list;\r
- struct notifier_block *dvfs_nb;\r
- struct cpufreq_frequency_table *dvfs_table;\r
- clk_dvfs_target_callback clk_dvfs_target;\r
- struct clk_disable_ctr *disable_ctr;\r
-};\r
-\r
-struct dvfs_arm_table {\r
- unsigned int frequency; /* kHz - doesn't need to be in ascending\r
- * order */\r
- unsigned int cpu_volt; /* any */\r
-\r
- unsigned int logic_volt;\r
-};\r
-\r
-\r
-#define DVFS_MHZ (1000*1000)\r
-#define DVFS_KHZ (1000)\r
-\r
-#define DVFS_V (1000*1000)\r
-#define DVFS_MV (1000)\r
-#if 0\r
-#define DVFS_DBG(fmt, args...) printk(KERN_DEBUG "DVFS DBG:\t"fmt, ##args)\r
-#else\r
-#define DVFS_DBG(fmt, args...) {while(0);}\r
-#endif\r
-\r
-#define DVFS_ERR(fmt, args...) printk(KERN_ERR "DVFS ERR:\t"fmt, ##args)\r
-#define DVFS_LOG(fmt, args...) printk(KERN_DEBUG "DVFS LOG:\t"fmt, ##args)\r
-#define DVFS_WARNING(fmt, args...) printk(KERN_WARNING "DVFS WARNING:\t"fmt, ##args)\r
-\r
-\r
-\r
-#define DVFS_SET_VOLT_FAILURE 1\r
-#define DVFS_SET_VOLT_SUCCESS 0\r
-\r
-\r
-#define dvfs_regulator_get(dev,id) regulator_get((dev),(id))\r
-#define dvfs_regulator_put(regu) regulator_put((regu))\r
-#define dvfs_regulator_set_voltage(regu,min_uV,max_uV) regulator_set_voltage((regu),(min_uV),(max_uV))\r
-#define dvfs_regulator_get_voltage(regu) regulator_get_voltage((regu))\r
-#define dvfs_regulator_set_voltage_time(regu, old_uV, new_uV) regulator_set_voltage_time((regu), (old_uV), (new_uV))\r
-#define dvfs_regulator_set_mode(regu, mode) regulator_set_mode((regu), (mode))\r
-#define dvfs_regulator_get_mode(regu) regulator_get_mode((regu))\r
-#define dvfs_regulator_list_voltage(regu,selector) regulator_list_voltage((regu),(selector))\r
-#define dvfs_regulator_count_voltages(regu) regulator_count_voltages((regu))\r
-\r
-#define dvfs_clk_get(a,b) clk_get((a),(b))\r
-#define dvfs_clk_get_rate_kz(a) (clk_get_rate((a))/1000)\r
-#define dvfs_clk_set_rate(a,b) clk_set_rate((a),(b))\r
-\r
-\r
-\r
-\r
-typedef void (*avs_init_fn)(void);\r
-typedef u8 (*avs_get_val_fn)(void);\r
-struct avs_ctr_st {\r
- avs_init_fn avs_init;\r
- avs_get_val_fn avs_get_val;\r
-};\r
-\r
-\r
-\r
-\r
-#ifdef CONFIG_DVFS\r
-/***********************************************************************************/\r
-int dvfs_clk_get_ref_volt(struct clk_node *dvfs_clk, int rate_khz,\r
- struct cpufreq_frequency_table *clk_fv);\r
-struct clk_node *clk_get_dvfs_info(struct clk *clk);\r
-int dvfs_reset_volt(struct vd_node *dvfs_vd);\r
-int dvfs_vd_get_newvolt_byclk(struct clk_node *dvfs_clk);\r
-int dvfs_get_depend_volt(struct clk_node *dvfs_clk, struct vd_node *dvfs_vd_dep, int rate_new);\r
-int dvfs_vd_get_newvolt_bypd(struct vd_node *vd);\r
-int dvfs_scale_volt_bystep(struct vd_node *vd_clk, struct vd_node *vd_dep, int volt_new, int volt_dep_new,\r
- int cur_clk_biger_than_dep, int cur_dep_biger_than_clk, int new_clk_biger_than_dep, int new_dep_biger_than_clk);\r
-int rk_regist_vd(struct vd_node *vd);\r
-int rk_regist_pd(struct pd_node_lookup *pd_lookup);\r
-int rk_regist_clk(struct clk_node *dvfs_clk);\r
-int rk_regist_depends(struct depend_lookup *dep_node);\r
-struct clk_node *dvfs_get_dvfs_clk_byname(char *name);\r
-int vd_regulator_round_volt(struct vd_node *vd, int volt,int flags);\r
-int dvfs_vd_clk_disable_target(struct clk *clk, int on);\r
-void dvfs_clk_disable_delay_work(struct work_struct *work);\r
-\r
-/*********************************if not define dvfs ,the following function is need defined func{}******************************/\r
-int dvfs_vd_clk_set_rate(struct clk *clk, unsigned long rate);\r
-int dvfs_vd_clk_disable(struct clk *clk, int on);\r
-int clk_enable_dvfs(struct clk *clk);\r
-int clk_disable_dvfs(struct clk *clk);\r
-void dvfs_clk_register_set_rate_callback(struct clk *clk, clk_dvfs_target_callback clk_dvfs_target);\r
-struct cpufreq_frequency_table *dvfs_get_freq_volt_table(struct clk *clk);\r
-int dvfs_set_freq_volt_table(struct clk *clk, struct cpufreq_frequency_table *table);\r
-int dvfs_set_depend_table(struct clk *clk, char *vd_name, struct cpufreq_frequency_table *table);\r
-int dvfs_set_arm_logic_volt(struct dvfs_arm_table *dvfs_cpu_logic_table, struct cpufreq_frequency_table *cpu_dvfs_table, struct cpufreq_frequency_table *dep_cpu2core_table);\r
-struct regulator* dvfs_get_regulator(char *regulator_name);\r
-int dvfs_clk_enable_limit(struct clk *clk, unsigned int min_rate, unsigned max_rate);\r
-int dvfs_clk_disable_limit(struct clk *clk);\r
-int dvfs_scale_volt_direct(struct vd_node *vd_clk, int volt_new);\r
-/******************************** inline *******************************/\r
-static inline bool dvfs_support_clk_set_rate(struct clk_node *dvfs_info)\r
-{\r
- return (dvfs_info&&dvfs_info->enable_dvfs);\r
-}\r
-static inline bool dvfs_support_clk_disable(struct clk_node *dvfs_info)\r
-{\r
- return (dvfs_info&&dvfs_info->disable_ctr&&dvfs_info->enable_dvfs);\r
-}\r
-/********************************avs*******************************/\r
-void avs_init(void);\r
-void avs_init_val_get(int index,int vol,char *s);\r
-int avs_set_scal_val(u8 avs_base);\r
-void avs_board_init(struct avs_ctr_st *data);\r
-\r
-#else\r
-static inline bool dvfs_support_clk_set_rate(struct clk_node *dvfs_info) { return 0; }\r
-static inline bool dvfs_support_clk_disable(struct clk_node *dvfs_info) { return 0; }\r
-\r
-static inline int dvfs_vd_clk_set_rate(struct clk *clk, unsigned long rate) { return 0; }\r
-static inline int dvfs_vd_clk_disable(struct clk *clk, int on) { return 0; }\r
-static inline int clk_enable_dvfs(struct clk *clk) { return 0; }\r
-static inline int clk_disable_dvfs(struct clk *clk) { return 0; }\r
-static inline void dvfs_clk_register_set_rate_callback(struct clk *clk, clk_dvfs_target_callback clk_dvfs_target) {}\r
-static inline struct cpufreq_frequency_table *dvfs_get_freq_volt_table(struct clk *clk) { return NULL; }\r
-static inline int dvfs_set_freq_volt_table(struct clk *clk, struct cpufreq_frequency_table *table) { return 0; }\r
-static inline int dvfs_set_depend_table(struct clk *clk, char *vd_name, struct cpufreq_frequency_table *table) {return 0;}\r
-static inline int dvfs_set_arm_logic_volt(struct dvfs_arm_table *dvfs_cpu_logic_table, struct cpufreq_frequency_table *cpu_dvfs_table, struct cpufreq_frequency_table *dep_cpu2core_table){ return 0; }\r
-static inline struct regulator* dvfs_get_regulator(char *regulator_name){ return NULL; }\r
-static inline int dvfs_clk_enable_limit(struct clk *clk, unsigned int min_rate, unsigned max_rate){ return 0; }\r
-static inline int dvfs_clk_disable_limit(struct clk *clk){ return 0; };\r
-static inline int dvfs_scale_volt_direct(struct vd_node *vd_clk, int volt_new){ return 0; };\r
-\r
-static inline void avs_init(void){};\r
-static inline void avs_init_val_get(int index, int vol, char *s){};\r
-static inline int avs_set_scal_val(u8 avs_base){ return 0; };\r
-static inline void avs_board_init(struct avs_ctr_st *data){};\r
-#endif\r
-\r
-#endif\r
+++ /dev/null
-#ifndef __PLAT_EFUSE_H
-#define __PLAT_EFUSE_H
-
-#include <asm/types.h>
-
-/* eFuse controller register */
-#if defined(CONFIG_ARCH_RK3026)
-#define EFUSE_A_SHIFT (8)
-#else
-#define EFUSE_A_SHIFT (6)
-#endif
-#define EFUSE_A_MASK (0xFF)
-//#define EFUSE_PD (1 << 5)
-//#define EFUSE_PS (1 << 4)
-#define EFUSE_PGENB (1 << 3) //active low
-#define EFUSE_LOAD (1 << 2)
-#define EFUSE_STROBE (1 << 1)
-#define EFUSE_CSB (1 << 0) //active low
-
-#define REG_EFUSE_CTRL (0x0000)
-#define REG_EFUSE_DOUT (0x0004)
-
-/* Interfaces to get efuse informations */
-void rk_efuse_init(void);
-int rk_pll_flag(void);
-int rk_tflag(void);
-int rk_leakage_val(void);
-int rk3028_version_val(void);
-int rk3026_version_val(void);
-
-#endif
+++ /dev/null
-#include <mach/io.h>
-
-#define HAVE_GET_IRQNR_PREAMBLE
-#include <asm/hardware/entry-macro-gic.S>
-
- .macro disable_fiq
- .endm
-
- .macro get_irqnr_preamble, base, tmp
- ldr \base, =GIC_CPU_BASE
- .endm
-
- .macro arch_ret_to_user, tmp1, tmp2
- .endm
+++ /dev/null
-#ifndef __PLAT_FIQ_H
-#define __PLAT_FIQ_H
-
-/* enable/disable an interrupt that is an FIQ (safe from FIQ context?) */
-void rk_fiq_enable(int n);
-void rk_fiq_disable(int n);
-void rk_irq_setpending(int irq);
-void rk_irq_clearpending(int irq);
-void rk_fiq_init(void);
-
-#endif
+++ /dev/null
-#ifndef __PLAT_GPIO_H
-#define __PLAT_GPIO_H
-
-#include <linux/types.h>
-
-//定义GPIO相关寄存器偏移地址
-#define GPIO_SWPORT_DR 0x00
-#define GPIO_SWPORT_DDR 0x04
-#define GPIO_INTEN 0x30
-#define GPIO_INTMASK 0x34
-#define GPIO_INTTYPE_LEVEL 0x38
-#define GPIO_INT_POLARITY 0x3c
-#define GPIO_INT_STATUS 0x40
-#define GPIO_INT_RAWSTATUS 0x44
-#define GPIO_DEBOUNCE 0x48
-#define GPIO_PORTS_EOI 0x4c
-#define GPIO_EXT_PORT 0x50
-#define GPIO_LS_SYNC 0x60
-
-#define NUM_GROUP 32
-
-#define PIN_BASE NR_GIC_IRQS
-
-#define CPU_TOTOL_GPIO_NUM NR_GPIO_IRQS
-
-#define SPI_FPGA_EXPANDER_BASE (PIN_BASE + CPU_TOTOL_GPIO_NUM)
-
-#if defined(CONFIG_IOEXTEND_TCA6424)
-#define TCA6424_TOTOL_GPIO_NUM 24
-#else
-#define TCA6424_TOTOL_GPIO_NUM 0
-#endif
-#define TCA6424_GPIO_EXPANDER_BASE (SPI_FPGA_EXPANDER_BASE + CONFIG_SPI_FPGA_GPIO_NUM)
-
-#if defined(CONFIG_GPIO_WM831X)
-#define WM831X_TOTOL_GPIO_NUM 12
-#else
-#define WM831X_TOTOL_GPIO_NUM 0
-#endif
-#define WM831X_GPIO_EXPANDER_BASE (TCA6424_GPIO_EXPANDER_BASE + TCA6424_TOTOL_GPIO_NUM)
-
-#if defined(CONFIG_GPIO_WM8994)
-#define CONFIG_GPIO_WM8994_NUM 11
-#else
-#define CONFIG_GPIO_WM8994_NUM 0
-#endif
-#define WM8994_GPIO_EXPANDER_BASE (WM831X_GPIO_EXPANDER_BASE + WM831X_TOTOL_GPIO_NUM)
-
-#if defined(CONFIG_GPIO_TPS65910)
-#define CONFIG_GPIO_TPS65910_NUM 9
-#else
-#define CONFIG_GPIO_TPS65910_NUM 0
-#endif
-#define TPS65910_GPIO_EXPANDER_BASE (WM8994_GPIO_EXPANDER_BASE + CONFIG_GPIO_WM8994_NUM)
-
-//定义GPIO的PIN口最大数目。CONFIG_SPI_FPGA_GPIO_NUM表示FPGA的PIN脚数。
-#define ARCH_NR_GPIOS (PIN_BASE + CPU_TOTOL_GPIO_NUM + TCA6424_TOTOL_GPIO_NUM + WM831X_TOTOL_GPIO_NUM + CONFIG_SPI_FPGA_GPIO_NUM + CONFIG_GPIO_WM8994_NUM + CONFIG_GPIO_TPS65910_NUM)
-
-#define INVALID_GPIO -1
-
-#if defined(CONFIG_SPI_FPGA_GPIO)
-#define FPGA_PIO0_00 (SPI_FPGA_EXPANDER_BASE + 0*8 + 0)
-#define FPGA_PIO0_01 (SPI_FPGA_EXPANDER_BASE + 0*8 + 1)
-#define FPGA_PIO0_02 (SPI_FPGA_EXPANDER_BASE + 0*8 + 2)
-#define FPGA_PIO0_03 (SPI_FPGA_EXPANDER_BASE + 0*8 + 3)
-#define FPGA_PIO0_04 (SPI_FPGA_EXPANDER_BASE + 0*8 + 4)
-#define FPGA_PIO0_05 (SPI_FPGA_EXPANDER_BASE + 0*8 + 5)
-#define FPGA_PIO0_06 (SPI_FPGA_EXPANDER_BASE + 0*8 + 6)
-#define FPGA_PIO0_07 (SPI_FPGA_EXPANDER_BASE + 0*8 + 7)
-
-#define FPGA_PIO0_08 (SPI_FPGA_EXPANDER_BASE + 1*8 + 0)
-#define FPGA_PIO0_09 (SPI_FPGA_EXPANDER_BASE + 1*8 + 1)
-#define FPGA_PIO0_10 (SPI_FPGA_EXPANDER_BASE + 1*8 + 2)
-#define FPGA_PIO0_11 (SPI_FPGA_EXPANDER_BASE + 1*8 + 3)
-#define FPGA_PIO0_12 (SPI_FPGA_EXPANDER_BASE + 1*8 + 4)
-#define FPGA_PIO0_13 (SPI_FPGA_EXPANDER_BASE + 1*8 + 5)
-#define FPGA_PIO0_14 (SPI_FPGA_EXPANDER_BASE + 1*8 + 6)
-#define FPGA_PIO0_15 (SPI_FPGA_EXPANDER_BASE + 1*8 + 7)
-
-#define FPGA_PIO1_00 (SPI_FPGA_EXPANDER_BASE + 2*8 + 0)
-#define FPGA_PIO1_01 (SPI_FPGA_EXPANDER_BASE + 2*8 + 1)
-#define FPGA_PIO1_02 (SPI_FPGA_EXPANDER_BASE + 2*8 + 2)
-#define FPGA_PIO1_03 (SPI_FPGA_EXPANDER_BASE + 2*8 + 3)
-#define FPGA_PIO1_04 (SPI_FPGA_EXPANDER_BASE + 2*8 + 4)
-#define FPGA_PIO1_05 (SPI_FPGA_EXPANDER_BASE + 2*8 + 5)
-#define FPGA_PIO1_06 (SPI_FPGA_EXPANDER_BASE + 2*8 + 6)
-#define FPGA_PIO1_07 (SPI_FPGA_EXPANDER_BASE + 2*8 + 7)
-
-#define FPGA_PIO1_08 (SPI_FPGA_EXPANDER_BASE + 3*8 + 0)
-#define FPGA_PIO1_09 (SPI_FPGA_EXPANDER_BASE + 3*8 + 1)
-#define FPGA_PIO1_10 (SPI_FPGA_EXPANDER_BASE + 3*8 + 2)
-#define FPGA_PIO1_11 (SPI_FPGA_EXPANDER_BASE + 3*8 + 3)
-#define FPGA_PIO1_12 (SPI_FPGA_EXPANDER_BASE + 3*8 + 4)
-#define FPGA_PIO1_13 (SPI_FPGA_EXPANDER_BASE + 3*8 + 5)
-#define FPGA_PIO1_14 (SPI_FPGA_EXPANDER_BASE + 3*8 + 6)
-#define FPGA_PIO1_15 (SPI_FPGA_EXPANDER_BASE + 3*8 + 7)
-
-#define FPGA_PIO2_00 (SPI_FPGA_EXPANDER_BASE + 4*8 + 0)
-#define FPGA_PIO2_01 (SPI_FPGA_EXPANDER_BASE + 4*8 + 1)
-#define FPGA_PIO2_02 (SPI_FPGA_EXPANDER_BASE + 4*8 + 2)
-#define FPGA_PIO2_03 (SPI_FPGA_EXPANDER_BASE + 4*8 + 3)
-#define FPGA_PIO2_04 (SPI_FPGA_EXPANDER_BASE + 4*8 + 4)
-#define FPGA_PIO2_05 (SPI_FPGA_EXPANDER_BASE + 4*8 + 5)
-#define FPGA_PIO2_06 (SPI_FPGA_EXPANDER_BASE + 4*8 + 6)
-#define FPGA_PIO2_07 (SPI_FPGA_EXPANDER_BASE + 4*8 + 7)
-
-#define FPGA_PIO2_08 (SPI_FPGA_EXPANDER_BASE + 5*8 + 0)
-#define FPGA_PIO2_09 (SPI_FPGA_EXPANDER_BASE + 5*8 + 1)
-#define FPGA_PIO2_10 (SPI_FPGA_EXPANDER_BASE + 5*8 + 2)
-#define FPGA_PIO2_11 (SPI_FPGA_EXPANDER_BASE + 5*8 + 3)
-#define FPGA_PIO2_12 (SPI_FPGA_EXPANDER_BASE + 5*8 + 4)
-#define FPGA_PIO2_13 (SPI_FPGA_EXPANDER_BASE + 5*8 + 5)
-#define FPGA_PIO2_14 (SPI_FPGA_EXPANDER_BASE + 5*8 + 6)
-#define FPGA_PIO2_15 (SPI_FPGA_EXPANDER_BASE + 5*8 + 7)
-
-#define FPGA_PIO3_00 (SPI_FPGA_EXPANDER_BASE + 6*8 + 0)
-#define FPGA_PIO3_01 (SPI_FPGA_EXPANDER_BASE + 6*8 + 1)
-#define FPGA_PIO3_02 (SPI_FPGA_EXPANDER_BASE + 6*8 + 2)
-#define FPGA_PIO3_03 (SPI_FPGA_EXPANDER_BASE + 6*8 + 3)
-#define FPGA_PIO3_04 (SPI_FPGA_EXPANDER_BASE + 6*8 + 4)
-#define FPGA_PIO3_05 (SPI_FPGA_EXPANDER_BASE + 6*8 + 5)
-#define FPGA_PIO3_06 (SPI_FPGA_EXPANDER_BASE + 6*8 + 6)
-#define FPGA_PIO3_07 (SPI_FPGA_EXPANDER_BASE + 6*8 + 7)
-
-#define FPGA_PIO3_08 (SPI_FPGA_EXPANDER_BASE + 7*8 + 0)
-#define FPGA_PIO3_09 (SPI_FPGA_EXPANDER_BASE + 7*8 + 1)
-#define FPGA_PIO3_10 (SPI_FPGA_EXPANDER_BASE + 7*8 + 2)
-#define FPGA_PIO3_11 (SPI_FPGA_EXPANDER_BASE + 7*8 + 3)
-#define FPGA_PIO3_12 (SPI_FPGA_EXPANDER_BASE + 7*8 + 4)
-#define FPGA_PIO3_13 (SPI_FPGA_EXPANDER_BASE + 7*8 + 5)
-#define FPGA_PIO3_14 (SPI_FPGA_EXPANDER_BASE + 7*8 + 6)
-#define FPGA_PIO3_15 (SPI_FPGA_EXPANDER_BASE + 7*8 + 7)
-
-#define FPGA_PIO4_00 (SPI_FPGA_EXPANDER_BASE + 8*8 + 0)
-#define FPGA_PIO4_01 (SPI_FPGA_EXPANDER_BASE + 8*8 + 1)
-#define FPGA_PIO4_02 (SPI_FPGA_EXPANDER_BASE + 8*8 + 2)
-#define FPGA_PIO4_03 (SPI_FPGA_EXPANDER_BASE + 8*8 + 3)
-#define FPGA_PIO4_04 (SPI_FPGA_EXPANDER_BASE + 8*8 + 4)
-#define FPGA_PIO4_05 (SPI_FPGA_EXPANDER_BASE + 8*8 + 5)
-#define FPGA_PIO4_06 (SPI_FPGA_EXPANDER_BASE + 8*8 + 6)
-#define FPGA_PIO4_07 (SPI_FPGA_EXPANDER_BASE + 8*8 + 7)
-
-#define FPGA_PIO4_08 (SPI_FPGA_EXPANDER_BASE + 9*8 + 0)
-#define FPGA_PIO4_09 (SPI_FPGA_EXPANDER_BASE + 9*8 + 1)
-#define FPGA_PIO4_10 (SPI_FPGA_EXPANDER_BASE + 9*8 + 2)
-#define FPGA_PIO4_11 (SPI_FPGA_EXPANDER_BASE + 9*8 + 3)
-#define FPGA_PIO4_12 (SPI_FPGA_EXPANDER_BASE + 9*8 + 4)
-#define FPGA_PIO4_13 (SPI_FPGA_EXPANDER_BASE + 9*8 + 5)
-#define FPGA_PIO4_14 (SPI_FPGA_EXPANDER_BASE + 9*8 + 6)
-#define FPGA_PIO4_15 (SPI_FPGA_EXPANDER_BASE + 9*8 + 7)
-
-#define FPGA_PIO5_00 (SPI_FPGA_EXPANDER_BASE + 10*8 + 0)
-#define FPGA_PIO5_01 (SPI_FPGA_EXPANDER_BASE + 10*8 + 1)
-#define FPGA_PIO5_02 (SPI_FPGA_EXPANDER_BASE + 10*8 + 2)
-#define FPGA_PIO5_03 (SPI_FPGA_EXPANDER_BASE + 10*8 + 3)
-#define FPGA_PIO5_04 (SPI_FPGA_EXPANDER_BASE + 10*8 + 4)
-#define FPGA_PIO5_05 (SPI_FPGA_EXPANDER_BASE + 10*8 + 5)
-#define FPGA_PIO5_06 (SPI_FPGA_EXPANDER_BASE + 10*8 + 6)
-#define FPGA_PIO5_07 (SPI_FPGA_EXPANDER_BASE + 10*8 + 7)
-
-#define FPGA_PIO5_08 (SPI_FPGA_EXPANDER_BASE + 11*8 + 0)
-#define FPGA_PIO5_09 (SPI_FPGA_EXPANDER_BASE + 11*8 + 1)
-#define FPGA_PIO5_10 (SPI_FPGA_EXPANDER_BASE + 11*8 + 2)
-#define FPGA_PIO5_11 (SPI_FPGA_EXPANDER_BASE + 11*8 + 3)
-#define FPGA_PIO5_12 (SPI_FPGA_EXPANDER_BASE + 11*8 + 4)
-#define FPGA_PIO5_13 (SPI_FPGA_EXPANDER_BASE + 11*8 + 5)
-#define FPGA_PIO5_14 (SPI_FPGA_EXPANDER_BASE + 11*8 + 6)
-#define FPGA_PIO5_15 (SPI_FPGA_EXPANDER_BASE + 11*8 + 7)
-#endif
-
-#if defined(CONFIG_IOEXTEND_TCA6424)
-#define TCA6424_P00 (TCA6424_GPIO_EXPANDER_BASE + 0*8 + 0)
-#define TCA6424_P01 (TCA6424_GPIO_EXPANDER_BASE + 0*8 + 1)
-#define TCA6424_P02 (TCA6424_GPIO_EXPANDER_BASE + 0*8 + 2)
-#define TCA6424_P03 (TCA6424_GPIO_EXPANDER_BASE + 0*8 + 3)
-#define TCA6424_P04 (TCA6424_GPIO_EXPANDER_BASE + 0*8 + 4)
-#define TCA6424_P05 (TCA6424_GPIO_EXPANDER_BASE + 0*8 + 5)
-#define TCA6424_P06 (TCA6424_GPIO_EXPANDER_BASE + 0*8 + 6)
-#define TCA6424_P07 (TCA6424_GPIO_EXPANDER_BASE + 0*8 + 7)
-
-#define TCA6424_P10 (TCA6424_GPIO_EXPANDER_BASE + 1*8 + 0)
-#define TCA6424_P11 (TCA6424_GPIO_EXPANDER_BASE + 1*8 + 1)
-#define TCA6424_P12 (TCA6424_GPIO_EXPANDER_BASE + 1*8 + 2)
-#define TCA6424_P13 (TCA6424_GPIO_EXPANDER_BASE + 1*8 + 3)
-#define TCA6424_P14 (TCA6424_GPIO_EXPANDER_BASE + 1*8 + 4)
-#define TCA6424_P15 (TCA6424_GPIO_EXPANDER_BASE + 1*8 + 5)
-#define TCA6424_P16 (TCA6424_GPIO_EXPANDER_BASE + 1*8 + 6)
-#define TCA6424_P17 (TCA6424_GPIO_EXPANDER_BASE + 1*8 + 7)
-
-#define TCA6424_P20 (TCA6424_GPIO_EXPANDER_BASE + 2*8 + 0)
-#define TCA6424_P21 (TCA6424_GPIO_EXPANDER_BASE + 2*8 + 1)
-#define TCA6424_P22 (TCA6424_GPIO_EXPANDER_BASE + 2*8 + 2)
-#define TCA6424_P23 (TCA6424_GPIO_EXPANDER_BASE + 2*8 + 3)
-#define TCA6424_P24 (TCA6424_GPIO_EXPANDER_BASE + 2*8 + 4)
-#define TCA6424_P25 (TCA6424_GPIO_EXPANDER_BASE + 2*8 + 5)
-#define TCA6424_P26 (TCA6424_GPIO_EXPANDER_BASE + 2*8 + 6)
-#define TCA6424_P27 (TCA6424_GPIO_EXPANDER_BASE + 2*8 + 7)
-#endif
-
-#if defined(CONFIG_GPIO_WM831X)
-#define WM831X_P01 (WM831X_GPIO_EXPANDER_BASE + 0*8 + 0)
-#define WM831X_P02 (WM831X_GPIO_EXPANDER_BASE + 0*8 + 1)
-#define WM831X_P03 (WM831X_GPIO_EXPANDER_BASE + 0*8 + 2)
-#define WM831X_P04 (WM831X_GPIO_EXPANDER_BASE + 0*8 + 3)
-#define WM831X_P05 (WM831X_GPIO_EXPANDER_BASE + 0*8 + 4)
-#define WM831X_P06 (WM831X_GPIO_EXPANDER_BASE + 0*8 + 5)
-#define WM831X_P07 (WM831X_GPIO_EXPANDER_BASE + 0*8 + 6)
-#define WM831X_P08 (WM831X_GPIO_EXPANDER_BASE + 0*8 + 7)
-
-#define WM831X_P09 (WM831X_GPIO_EXPANDER_BASE + 1*8 + 0)
-#define WM831X_P10 (WM831X_GPIO_EXPANDER_BASE + 1*8 + 1)
-#define WM831X_P11 (WM831X_GPIO_EXPANDER_BASE + 1*8 + 2)
-#define WM831X_P12 (WM831X_GPIO_EXPANDER_BASE + 1*8 + 3)
-#endif
-
-/*
- * tp_int = <bank><goff><off><driving force><wake_en><irq_flags><reserve>
- * tp_rst = <bank><goff><off><driving force><active_low><pull_mode><reserve>
- * gpio = RKXX_PIN(bank)_P(goff)(off)
- * e.g. bank=2, goff=A, off=3 ==>gpio is RKXX_PIN2_PA3
- */
-enum {
- PULL_MODE_NONE = 0,
- PULL_MODE_DISABLE,
- PULL_MODE_ENABLE,
-};
-struct irq_config{
- unsigned int off:4, //bit[3:0]
- goff:4,
- bank:4,
- driving_force:4,
- wake_en:4,
- irq_flags:4,
- reserve:8;
-};
-struct gpio_config{
- unsigned int off:4, //bit[3:0]
- goff:4,
- bank:4,
- driving_force:4,
- active_low:4,
- pull_mode:4,
- reserve:8;
-};
-struct port_config {
- union{
- struct irq_config irq;
- struct gpio_config io;
- unsigned int v;
- };
- int gpio;
-};
-static inline struct port_config get_port_config(unsigned int value)
-{
- struct port_config port;
-
- port.v = value;
- if(value == 0xffffffff)
- port.gpio = INVALID_GPIO;
- else
- port.gpio = PIN_BASE + port.io.bank * 32 + (port.io.goff - 0x0A) * 8 + port.io.off;
-
- return port;
-}
-void gpio_set_iomux(int gpio);
-int port_output_init(unsigned int value, int on, char *name);
-void port_output_on(unsigned int value);
-void port_output_off(unsigned int value);
-int port_input_init(unsigned int value, char *name);
-int port_get_value(unsigned int value);
-void port_deinit(unsigned int value);
-
-typedef enum eGPIOPinLevel
-{
- GPIO_LOW=0,
- GPIO_HIGH
-}eGPIOPinLevel_t;
-
-typedef enum eGPIOPinDirection
-{
- GPIO_IN=0,
- GPIO_OUT
-}eGPIOPinDirection_t;
-
-typedef enum GPIOPullType {
- PullDisable = 0,
- PullEnable = 1,
- GPIONormal = PullDisable,
- GPIOPullUp = 1,
- GPIOPullDown = 2,
-}eGPIOPullType_t;
-
-typedef enum GPIOIntType {
- GPIOLevelLow=0,
- GPIOLevelHigh,
- GPIOEdgelFalling,
- GPIOEdgelRising
-}eGPIOIntType_t;
-
-static inline bool gpio_is_valid(int number)
-{
- return number >= PIN_BASE && number < ARCH_NR_GPIOS;
-}
-
-#define gpio_is_valid gpio_is_valid
-
-extern void __init rk30_gpio_init(void);
-
-static inline int gpio_to_irq(unsigned gpio)
-{
- return gpio - PIN_BASE + NR_GIC_IRQS;
-}
-
-static inline int irq_to_gpio(unsigned irq)
-{
- return irq - NR_GIC_IRQS + PIN_BASE;
-}
-
-#include <asm/errno.h>
-#include <asm-generic/gpio.h> /* cansleep wrappers */
-
-#define gpio_get_value __gpio_get_value
-#define gpio_set_value __gpio_set_value
-#define gpio_cansleep __gpio_cansleep
-
-#endif
+++ /dev/null
-#ifndef __PLAT_IO_H
-#define __PLAT_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-#define __io(a) __typesafe_io(a)
-#define __mem_pci(a) (a)
-
-#ifdef __ASSEMBLER__
-#define IOMEM(x) (x)
-#else
-#define IOMEM(x) ((void __force __iomem *)(x))
-#endif
-
-#endif
+++ /dev/null
-#ifndef __PLAT_IOMUX_H
-#define __PLAT_IOMUX_H
-
-#define INVALID_MODE 0xffffffff
-
-#define iomux_switch_gpio_mode(m) ((m) & (~0x03))
-
-int iomux_gpio_to_mode(int gpio);
-int iomux_mode_to_gpio(unsigned int mode);
-void iomux_set_gpio_mode(int gpio);
-void iomux_set(unsigned int mode);
-void __init iomux_init(void);
-
-/* return value:
- * -1: mode is invalide
- * 0: mode is not set
- * 1: mode is set
- */
-int iomux_is_set(unsigned int);
-
-#endif
+++ /dev/null
-#ifndef _RK29_IPP_DRIVER_H_\r
-#define _RK29_IPP_DRIVER_H_\r
-\r
-\r
-#define IPP_BLIT_SYNC 0x5017\r
-#define IPP_BLIT_ASYNC 0x5018\r
-#define IPP_GET_RESULT 0x5019\r
-\r
-\r
-/* Image data */\r
-struct rk29_ipp_image\r
-{\r
- uint32_t YrgbMst; // image Y/rgb address\r
- uint32_t CbrMst; // image CbCr address\r
- uint32_t w; // image full width\r
- uint32_t h; // image full height\r
- uint32_t fmt; // color format\r
-};\r
-\r
-struct rk29_ipp_req {\r
- struct rk29_ipp_image src0; // source0 image\r
- struct rk29_ipp_image dst0; // destination0 image\r
- //struct rk29_ipp_image src1; // source1 image\r
- //struct rk29_ipp_image dst1; // destination1 image\r
- uint32_t src_vir_w;\r
- uint32_t dst_vir_w;\r
- uint32_t timeout;\r
- \r
- uint32_t flag; //rotate\r
-\r
- /*store_clip_mode \r
- 0:when src width is not 64-bits aligned,use dummy data make it 64-bits aligned 1:packed\r
- we usually set to 0\r
- */\r
- uint8_t store_clip_mode;\r
- \r
- //deinterlace_enable 0:disable 1:enable 2:query\r
- uint8_t deinterlace_enable;\r
- //the sum of three paras should be 32,and single para should be less than 32\r
- uint8_t deinterlace_para0;\r
- uint8_t deinterlace_para1;\r
- uint8_t deinterlace_para2;\r
- \r
- /* completion is reported through a callback */\r
- void (*complete)(int retval);\r
- \r
-};\r
-\r
-//format enum\r
-enum\r
-{\r
- IPP_XRGB_8888 = 0,\r
- IPP_RGB_565 =1 ,\r
- IPP_Y_CBCR_H2V1 = 2, //yuv 422sp\r
- IPP_Y_CBCR_H2V2 = 3, //yuv 420sp\r
- IPP_Y_CBCR_H1V1 =6, //yuv 444sp\r
- IPP_IMGTYPE_LIMIT\r
-};\r
-\r
-typedef enum\r
- {\r
- IPP_ROT_90,\r
- IPP_ROT_180,\r
- IPP_ROT_270,\r
- IPP_ROT_X_FLIP,\r
- IPP_ROT_Y_FLIP,\r
- IPP_ROT_0,\r
- IPP_ROT_LIMIT\r
- } ROT_DEG;\r
-\r
- struct ipp_regs {\r
- uint32_t ipp_config;\r
- uint32_t ipp_src_img_info;\r
- uint32_t ipp_dst_img_info;\r
- uint32_t ipp_img_vir;\r
- uint32_t ipp_int;\r
- uint32_t ipp_src0_y_mst;\r
- uint32_t ipp_src0_Cbr_mst;\r
- uint32_t ipp_src1_y_mst;\r
- uint32_t ipp_src1_Cbr_mst;\r
- uint32_t ipp_dst0_y_mst;\r
- uint32_t ipp_dst0_Cbr_mst;\r
- uint32_t ipp_dst1_y_mst;\r
- uint32_t ipp_dst1_Cbr_mst;\r
- uint32_t ipp_pre_scl_para;\r
- uint32_t ipp_post_scl_para;\r
- uint32_t ipp_swap_ctrl;\r
- uint32_t ipp_pre_img_info;\r
- uint32_t ipp_axi_id;\r
- uint32_t ipp_process_st;\r
-};\r
-\r
-#define IPP_CONFIG (0x00)\r
-#define IPP_SRC_IMG_INFO (0x04)\r
-#define IPP_DST_IMG_INFO (0x08)\r
-#define IPP_IMG_VIR (0x0c)\r
-#define IPP_INT (0x10)\r
-#define IPP_SRC0_Y_MST (0x14)\r
-#define IPP_SRC0_CBR_MST (0x18)\r
-#define IPP_SRC1_Y_MST (0x1c)\r
-#define IPP_SRC1_CBR_MST (0x20)\r
-#define IPP_DST0_Y_MST (0x24)\r
-#define IPP_DST0_CBR_MST (0x28)\r
-#define IPP_DST1_Y_MST (0x2c)\r
-#define IPP_DST1_CBR_MST (0x30)\r
-#define IPP_PRE_SCL_PARA (0x34)\r
-#define IPP_POST_SCL_PARA (0x38)\r
-#define IPP_SWAP_CTRL (0x3c)\r
-#define IPP_PRE_IMG_INFO (0x40)\r
-#define IPP_AXI_ID (0x44)\r
-#define IPP_SRESET (0x48)\r
-#define IPP_PROCESS_ST (0x50)\r
-\r
-/*ipp config*/\r
-#define STORE_CLIP_MODE (1<<26)\r
-#define DEINTERLACE_ENABLE (1<<24)\r
-#define ROT_ENABLE (1<<8)\r
-#define PRE_SCALE (1<<4)\r
-#define POST_SCALE (1<<3)\r
-\r
-#define IPP_BLIT_COMPLETE_EVENT BIT(1)\r
-\r
-#define IS_YCRCB(img) ((img == IPP_Y_CBCR_H2V1) | (img == IPP_Y_CBCR_H2V2) | \\r
- (img == IPP_Y_CBCR_H1V1) )\r
-#define IS_RGB(img) ((img == IPP_RGB_565) | (img == IPP_ARGB_8888) | \\r
- (img == IPP_XRGB_8888) ))\r
-#define HAS_ALPHA(img) (img == IPP_ARGB_8888)\r
-\r
-\r
-int ipp_blit_async(const struct rk29_ipp_req *req);\r
-//int ipp_blit_sync(const struct rk29_ipp_req *req);\r
-extern int (*ipp_blit_sync)(const struct rk29_ipp_req *req);\r
-#endif /*_RK29_IPP_DRIVER_H_*/
\ No newline at end of file
+++ /dev/null
-#ifndef __RK29_KEYS_H__
-#define __RK29_KEYS_H__
-#include <linux/input.h>
-
-#define DEFAULT_DEBOUNCE_INTERVAL 10 //10ms
-#define LONG_PRESS_COUNT 100 //100 * 10 = 1000ms
-#define ONE_SEC_COUNT (1000/DEFAULT_DEBOUNCE_INTERVAL)
-
-#define ADC_SAMPLE_TIME 100
-
-#define EV_ENCALL KEY_F4
-#define EV_MENU KEY_F1
-
-#define PRESS_LEV_LOW 1
-#define PRESS_LEV_HIGH 0
-
-struct rk29_keys_button {
- int code;
- int code_long_press;
- int gpio;
- int adc_value;
- int adc_state;
- int active_low;
- char *desc;
- int wakeup;
-};
-
-
-struct rk29_keys_platform_data {
- struct rk29_keys_button *buttons;
- int nbuttons;
- int chn;
- int rep;
-};
-
-#endif
+++ /dev/null
-#ifndef __PLAT_LOADER_H
-#define __PLAT_LOADER_H
-
-#define SYS_LOADER_REBOOT_FLAG 0x5242C300 //high 24 bits is tag, low 8 bits is type
-#define SYS_KERNRL_REBOOT_FLAG 0xC3524200 //high 24 bits is tag, low 8 bits is type
-
-enum {
- BOOT_NORMAL = 0, /* normal boot */
- BOOT_LOADER, /* enter loader rockusb mode */
- BOOT_MASKROM, /* enter maskrom rockusb mode (not support now) */
- BOOT_RECOVER, /* enter recover */
- BOOT_NORECOVER, /* do not enter recover */
- BOOT_SECONDOS, /* boot second OS (not support now)*/
- BOOT_WIPEDATA, /* enter recover and wipe data. */
- BOOT_WIPEALL, /* enter recover and wipe all data. */
- BOOT_CHECKIMG, /* check firmware img with backup part(in loader mode)*/
- BOOT_FASTBOOT, /* enter fast boot mode (not support now) */
- BOOT_MAX /* MAX VALID BOOT TYPE.*/
-};
-
-static inline const char *boot_flag_name(u32 flag)
-{
- flag -= SYS_KERNRL_REBOOT_FLAG;
- switch (flag) {
- case BOOT_NORMAL: return "NORMAL";
- case BOOT_LOADER: return "LOADER";
- case BOOT_MASKROM: return "MASKROM";
- case BOOT_RECOVER: return "RECOVER";
- case BOOT_NORECOVER: return "NORECOVER";
- case BOOT_SECONDOS: return "SECONDOS";
- case BOOT_WIPEDATA: return "WIPEDATA";
- case BOOT_WIPEALL: return "WIPEALL";
- case BOOT_CHECKIMG: return "CHECKIMG";
- case BOOT_FASTBOOT: return "FASTBOOT";
- default: return "";
- }
-}
-
-#endif
+++ /dev/null
-#ifndef __PLAT_MEMORY_H
-#define __PLAT_MEMORY_H
-
-#include <linux/version.h>
-
-/*
- * Physical DRAM offset.
- */
-#if defined(CONFIG_ARCH_RK319X)
-#define PLAT_PHYS_OFFSET UL(0x00000000)
-#else
-#define PLAT_PHYS_OFFSET UL(0x60000000)
-#endif
-
-#define CONSISTENT_DMA_SIZE SZ_8M
-
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34))
-#define dmac_clean_range(start, end) dmac_map_area(start, end - start, DMA_TO_DEVICE)
-#define dmac_inv_range(start, end) dmac_unmap_area(start, end - start, DMA_FROM_DEVICE)
-#endif
-
-#endif
+++ /dev/null
-#ifndef __PLAT_PWM_H
-#define __PLAT_PWM_H
-
-#include <linux/io.h>
-
-enum pwm_div {
- PWM_DIV2 = (0x0 << 9),
- PWM_DIV4 = (0x1 << 9),
- PWM_DIV8 = (0x2 << 9),
- PWM_DIV16 = (0x3 << 9),
- PWM_DIV32 = (0x4 << 9),
- PWM_DIV64 = (0x5 << 9),
- PWM_DIV128 = (0x6 << 9),
- PWM_DIV256 = (0x7 << 9),
- PWM_DIV512 = (0x8 << 9),
- PWM_DIV1024 = (0x9 << 9),
- PWM_DIV2048 = (0xa << 9),
- PWM_DIV4096 = (0xb << 9),
- PWM_DIV8192 = (0xc << 9),
- PWM_DIV16384 = (0xd << 9),
- PWM_DIV32768 = (0xe << 9),
- PWM_DIV65536 = (0xf << 9),
-};
-
-#define PWM_DIV_MASK (0xf << 9)
-#define PWM_CAPTURE (1 << 8)
-#define PWM_RESET (1 << 7)
-#define PWM_INTCLR (1 << 6)
-#define PWM_INTEN (1 << 5)
-#define PWM_SINGLE (1 << 4)
-
-#define PWM_ENABLE (1 << 3)
-#define PWM_TIMER_EN (1 << 0)
-#define PWM_TimeEN PWM_TIMER_EN
-
-#define PWM_REG_CNTR 0x00
-#define PWM_REG_HRC 0x04
-#define PWM_REG_LRC 0x08
-#define PWM_REG_CTRL 0x0c
-
-static inline void __rk_pwm_setup(const void __iomem *base, enum pwm_div div, u32 hrc, u32 lrc)
-{
- u32 off = div | PWM_RESET;
- u32 on = div | PWM_ENABLE | PWM_TIMER_EN;
-
- barrier();
- writel_relaxed(off, base + PWM_REG_CTRL);
- dsb();
- writel_relaxed(hrc, base + PWM_REG_HRC);
- writel_relaxed(lrc, base + PWM_REG_LRC);
- writel_relaxed(0, base + PWM_REG_CNTR);
- dsb();
- writel_relaxed(on, base + PWM_REG_CTRL);
- dsb();
-}
-
-struct clk *rk_pwm_get_clk(unsigned pwm_id);
-void __iomem *rk_pwm_get_base(unsigned pwm_id);
-void rk_pwm_setup(unsigned pwm_id, enum pwm_div div, u32 hrc, u32 lrc);
-
-#endif
+++ /dev/null
-/*
- camera.h - PXA camera driver header file
-
- Copyright (C) 2003, Intel Corporation
- Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-*/
-
-#ifndef __ASM_ARCH_CAMERA_RK_H_
-#define __ASM_ARCH_CAMERA_RK_H_
-
-#include <linux/videodev2.h>
-#include <media/soc_camera.h>
-#include <linux/i2c.h>
-
-#define RK29_CAM_PLATFORM_DEV_ID 33
-#define RK_CAM_PLATFORM_DEV_ID_0 RK29_CAM_PLATFORM_DEV_ID
-#define RK_CAM_PLATFORM_DEV_ID_1 (RK_CAM_PLATFORM_DEV_ID_0+1)
-#define INVALID_VALUE -1
-#ifndef INVALID_GPIO
-#define INVALID_GPIO INVALID_VALUE
-#endif
-#define RK29_CAM_IO_SUCCESS 0
-#define RK29_CAM_EIO_INVALID -3
-#define RK29_CAM_EIO_REQUESTFAIL -2
-
-#define RK29_CAM_POWERACTIVE_BITPOS 0x00
-#define RK29_CAM_RESETACTIVE_BITPOS 0x01
-#define RK29_CAM_POWERDNACTIVE_BITPOS 0x02
-#define RK29_CAM_FLASHACTIVE_BITPOS 0x03
-
-#define RK_CAM_NUM 6
-#define RK29_CAM_SUPPORT_NUMS RK_CAM_NUM
-#define RK_CAM_SUPPORT_RESOLUTION 0x800000
-
-#define _CONS(a,b) a##b
-#define CONS(a,b) _CONS(a,b)
-
-#define _CONS4(a,b,c,d) a##b##c##d
-#define CONS4(a,b,c,d) _CONS4(a,b,c,d)
-
-#define __STR(x) #x
-#define _STR(x) __STR(x)
-#define STR(x) _STR(x)
-
-#define new_camera_device_ex(sensor_name,\
- face,\
- ori,\
- pwr_io,\
- pwr_active,\
- rst_io,\
- rst_active,\
- pwdn_io,\
- pwdn_active,\
- flash_attach,\
- res,\
- mir,\
- i2c_chl,\
- i2c_spd,\
- i2c_addr,\
- cif_chl,\
- mclk)\
- {\
- .dev = {\
- .i2c_cam_info = {\
- I2C_BOARD_INFO(STR(sensor_name), i2c_addr>>1),\
- },\
- .link_info = {\
- .bus_id= RK29_CAM_PLATFORM_DEV_ID+cif_chl,\
- .i2c_adapter_id = i2c_chl,\
- .module_name = STR(sensor_name),\
- },\
- .device_info = {\
- .name = "soc-camera-pdrv",\
- .dev = {\
- .init_name = STR(CONS(_CONS(sensor_name,_),face)),\
- },\
- },\
- },\
- .io = {\
- .gpio_power = pwr_io,\
- .gpio_reset = rst_io,\
- .gpio_powerdown = pwdn_io,\
- .gpio_flash = INVALID_GPIO,\
- .gpio_flag = ((pwr_active&0x01)<<RK29_CAM_POWERACTIVE_BITPOS)|((rst_active&0x01)<<RK29_CAM_RESETACTIVE_BITPOS)|((pwdn_active&0x01)<<RK29_CAM_POWERDNACTIVE_BITPOS),\
- },\
- .orientation = ori,\
- .resolution = res,\
- .mirror = mir,\
- .i2c_rate = i2c_spd,\
- .flash = flash_attach,\
- .pwdn_info = ((pwdn_active&0x10)|0x01),\
- .powerup_sequence = CONS(sensor_name,_PWRSEQ),\
- .mclk_rate = mclk,\
- }
-
-#define new_camera_device(sensor_name,\
- face,\
- pwdn_io,\
- flash_attach,\
- mir,\
- i2c_chl,\
- cif_chl)\
- new_camera_device_ex(sensor_name,\
- face,\
- INVALID_VALUE,\
- INVALID_VALUE,\
- INVALID_VALUE,\
- INVALID_VALUE,\
- INVALID_VALUE,\
- pwdn_io,\
- CONS(sensor_name,_PWRDN_ACTIVE),\
- flash_attach,\
- CONS(sensor_name,_FULL_RESOLUTION),\
- mir,i2c_chl,\
- 100000,\
- CONS(sensor_name,_I2C_ADDR),\
- cif_chl,\
- 24)
-
-#define new_camera_device_raw_ex(sensor_name,\
- face,\
- ori,\
- pwr_io,\
- pwr_active,\
- rst_io,\
- rst_active,\
- pwdn_io,\
- pwdn_active,\
- flash_attach,\
- res,\
- mir,\
- i2c_chl,\
- i2c_spd,\
- i2c_addr,\
- cif_chl,\
- mclk)\
- .dev = {\
- .i2c_cam_info = {\
- I2C_BOARD_INFO(STR(sensor_name), i2c_addr>>1),\
- },\
- .link_info = {\
- .bus_id= RK29_CAM_PLATFORM_DEV_ID+cif_chl,\
- .i2c_adapter_id = i2c_chl,\
- .module_name = STR(sensor_name),\
- },\
- .device_info = {\
- .name = "soc-camera-pdrv",\
- .dev = {\
- .init_name = STR(CONS(_CONS(sensor_name,_),face)),\
- },\
- },\
- },\
- .io = {\
- .gpio_power = pwr_io,\
- .gpio_reset = rst_io,\
- .gpio_powerdown = pwdn_io,\
- .gpio_flash = INVALID_GPIO,\
- .gpio_flag = ((pwr_active&0x01)<<RK29_CAM_POWERACTIVE_BITPOS)|((rst_active&0x01)<<RK29_CAM_RESETACTIVE_BITPOS)|((pwdn_active&0x01)<<RK29_CAM_POWERDNACTIVE_BITPOS),\
- },\
- .orientation = ori,\
- .resolution = res,\
- .mirror = mir,\
- .i2c_rate = i2c_spd,\
- .flash = flash_attach,\
- .pwdn_info = ((pwdn_active&0x10)|0x01),\
- .powerup_sequence = CONS(sensor_name,_PWRSEQ),\
- .mclk_rate = mclk,\
-
-
-#define new_camera_device_raw(sensor_name,\
- face,\
- pwdn_io,\
- flash_attach,\
- mir,\
- i2c_chl,\
- cif_chl)\
- new_camera_device_raw_ex(sensor_name,\
- face,\
- INVALID_VALUE,\
- INVALID_VALUE,\
- INVALID_VALUE,\
- INVALID_VALUE,\
- INVALID_VALUE,\
- pwdn_io,\
- CONS(sensor_name,_PWRDN_ACTIVE),\
- flash_attach,\
- CONS(sensor_name,_FULL_RESOLUTION),\
- mir,i2c_chl,\
- 100000,\
- CONS(sensor_name,_I2C_ADDR),\
- cif_chl,\
- 24)
-
-#define new_camera_device_fov(a,b)\
- .fov_h = a,\
- .fov_v = b,
-
-
-#define new_camera_device_end new_camera_device_ex(end,end,\
- INVALID_VALUE,INVALID_VALUE,INVALID_VALUE,INVALID_VALUE,\
- INVALID_VALUE,INVALID_VALUE,INVALID_VALUE,INVALID_VALUE,\
- INVALID_VALUE,INVALID_VALUE,INVALID_VALUE,INVALID_VALUE,INVALID_VALUE,INVALID_VALUE,INVALID_VALUE)
-
-
-/*---------------- Camera Sensor Must Define Macro Begin ------------------------*/
-#define RK29_CAM_SENSOR_OV7675 ov7675
-#define RK29_CAM_SENSOR_OV9650 ov9650
-#define RK29_CAM_SENSOR_OV2640 ov2640
-#define RK29_CAM_SENSOR_OV2655 ov2655
-#define RK29_CAM_SENSOR_OV2659 ov2659
-#define RK29_CAM_SENSOR_OV7690 ov7690
-#define RK29_CAM_SENSOR_OV3640 ov3640
-#define RK29_CAM_SENSOR_OV3660 ov3660
-#define RK29_CAM_SENSOR_OV5640 ov5640
-#define RK29_CAM_SENSOR_OV5642 ov5642
-#define RK29_CAM_SENSOR_S5K6AA s5k6aa
-#define RK29_CAM_SENSOR_MT9D112 mt9d112
-#define RK29_CAM_SENSOR_MT9D113 mt9d113
-#define RK29_CAM_SENSOR_MT9P111 mt9p111
-#define RK29_CAM_SENSOR_MT9T111 mt9t111
-#define RK29_CAM_SENSOR_GT2005 gt2005
-#define RK29_CAM_SENSOR_GC0307 gc0307
-#define RK29_CAM_SENSOR_GC0308 gc0308
-#define RK29_CAM_SENSOR_GC0309 gc0309
-#define RK29_CAM_SENSOR_GC2015 gc2015
-#define RK29_CAM_SENSOR_GC0328 gc0328
-#define RK29_CAM_SENSOR_GC0329 gc0329
-#define RK29_CAM_SENSOR_GC2035 gc2035
-#define RK29_CAM_SENSOR_SIV120B siv120b
-#define RK29_CAM_SENSOR_SIV121D siv121d
-#define RK29_CAM_SENSOR_SID130B sid130B
-#define RK29_CAM_SENSOR_HI253 hi253
-#define RK29_CAM_SENSOR_HI704 hi704
-#define RK29_CAM_SENSOR_NT99250 nt99250
-#define RK29_CAM_SENSOR_SP0718 sp0718
-#define RK29_CAM_SENSOR_SP0838 sp0838
-#define RK29_CAM_SENSOR_SP2518 sp2518
-#define RK29_CAM_SENSOR_S5K5CA s5k5ca
-#define RK29_CAM_ISP_MTK9335 mtk9335isp
-#define RK29_CAM_SENSOR_HM2057 hm2057
-#define RK29_CAM_SENSOR_HM5065 hm5065
-#define RK29_CAM_SENSOR_NT99160 nt99160 //oyyf@rock-chips.com
-#define RK29_CAM_SENSOR_NT99240 nt99240 //oyyf@rock-chips.com
-#define RK29_CAM_SENSOR_NT99252 nt99252 //oyyf@rock-chips.com
-#define RK29_CAM_SENSOR_NT99340 nt99340 //oyyf@rock-chips.com
-#define RK29_CAM_ISP_ICATCH7002_MI1040 icatchmi1040
-#define RK29_CAM_ISP_ICATCH7002_OV5693 icatchov5693
-#define RK29_CAM_ISP_ICATCH7002_OV8825 icatchov8825 //zyt
-#define RK29_CAM_ISP_ICATCH7002_OV2720 icatchov2720 //zyt
-
-#define RK29_CAM_SENSOR_NAME_OV7675 "ov7675"
-#define RK29_CAM_SENSOR_NAME_OV9650 "ov9650"
-#define RK29_CAM_SENSOR_NAME_OV2640 "ov2640"
-#define RK29_CAM_SENSOR_NAME_OV2655 "ov2655"
-#define RK29_CAM_SENSOR_NAME_OV2659 "ov2659"
-#define RK29_CAM_SENSOR_NAME_OV7690 "ov7690"
-#define RK29_CAM_SENSOR_NAME_OV3640 "ov3640"
-#define RK29_CAM_SENSOR_NAME_OV3660 "ov3660"
-#define RK29_CAM_SENSOR_NAME_OV5640 "ov5640"
-#define RK29_CAM_SENSOR_NAME_OV5642 "ov5642"
-#define RK29_CAM_SENSOR_NAME_S5K6AA "s5k6aa"
-#define RK29_CAM_SENSOR_NAME_MT9D112 "mt9d112"
-#define RK29_CAM_SENSOR_NAME_MT9D113 "mt9d113"
-#define RK29_CAM_SENSOR_NAME_MT9P111 "mt9p111"
-#define RK29_CAM_SENSOR_NAME_MT9T111 "mt9t111"
-#define RK29_CAM_SENSOR_NAME_GT2005 "gt2005"
-#define RK29_CAM_SENSOR_NAME_GC0307 "gc0307"
-#define RK29_CAM_SENSOR_NAME_GC0308 "gc0308"
-#define RK29_CAM_SENSOR_NAME_GC0309 "gc0309"
-#define RK29_CAM_SENSOR_NAME_GC2015 "gc2015"
-#define RK29_CAM_SENSOR_NAME_GC0328 "gc0328"
-#define RK29_CAM_SENSOR_NAME_GC2035 "gc2035"
-#define RK29_CAM_SENSOR_NAME_GC0329 "gc0329"
-#define RK29_CAM_SENSOR_NAME_SIV120B "siv120b"
-#define RK29_CAM_SENSOR_NAME_SIV121D "siv121d"
-#define RK29_CAM_SENSOR_NAME_SID130B "sid130B"
-#define RK29_CAM_SENSOR_NAME_HI253 "hi253"
-#define RK29_CAM_SENSOR_NAME_HI704 "hi704"
-#define RK29_CAM_SENSOR_NAME_NT99250 "nt99250"
-#define RK29_CAM_SENSOR_NAME_SP0718 "sp0718"
-#define RK29_CAM_SENSOR_NAME_SP0838 "sp0838"
-#define RK29_CAM_SENSOR_NAME_SP2518 "sp2518"
-#define RK29_CAM_SENSOR_NAME_S5K5CA "s5k5ca"
-#define RK29_CAM_ISP_NAME_MTK9335ISP "mtk9335isp"
-#define RK29_CAM_SENSOR_NAME_HM2057 "hm2057"
-#define RK29_CAM_SENSOR_NAME_HM5065 "hm5065"
-#define RK29_CAM_ISP_NAME_ICATCH7002_MI1040 "icatchmi1040"
-#define RK29_CAM_ISP_NAME_ICATCH7002_OV5693 "icatchov5693"
-#define RK29_CAM_ISP_NAME_ICATCH7002_OV8825 "icatchov8825" //zyt
-#define RK29_CAM_ISP_NAME_ICATCH7002_OV2720 "icatchov2720" //zyt
-
-//Sensor full resolution define
-#define ov7675_FULL_RESOLUTION 0x30000 // 0.3 megapixel
-#define ov9650_FULL_RESOLUTION 0x130000 // 1.3 megapixel
-#define ov2640_FULL_RESOLUTION 0x200000 // 2 megapixel
-#define ov2655_FULL_RESOLUTION 0x200000 // 2 megapixel
-#define ov2659_FULL_RESOLUTION 0x200000 // 2 megapixel
-#define ov7690_FULL_RESOLUTION 0x300000 // 2 megapixel
-#define ov3640_FULL_RESOLUTION 0x300000 // 3 megapixel
-#define ov3660_FULL_RESOLUTION 0x300000 // 3 megapixel
-#define ov5640_FULL_RESOLUTION 0x500000 // 5 megapixel
-#if defined(CONFIG_SOC_CAMERA_OV5642_INTERPOLATION_8M)
- #define ov5642_FULL_RESOLUTION 0x800000 // 8 megapixel
-#else
- #define ov5642_FULL_RESOLUTION 0x500000 // 5 megapixel
-#endif
-#define s5k6aa_FULL_RESOLUTION 0x130000 // 1.3 megapixel
-#define mt9d112_FULL_RESOLUTION 0x200000 // 2 megapixel
-#define mt9d113_FULL_RESOLUTION 0x200000 // 2 megapixel
-#define mt9t111_FULL_RESOLUTION 0x300000 // 3 megapixel
-#define mt9p111_FULL_RESOLUTION 0x500000 // 5 megapixel
-#define gt2005_FULL_RESOLUTION 0x200000 // 2 megapixel
-#if defined(CONFIG_SOC_CAMERA_GC0308_INTERPOLATION_5M)
- #define gc0308_FULL_RESOLUTION 0x500000 // 5 megapixel
-#elif defined(CONFIG_SOC_CAMERA_GC0308_INTERPOLATION_3M)
- #define gc0308_FULL_RESOLUTION 0x300000 // 3 megapixel
-#elif defined(CONFIG_SOC_CAMERA_GC0308_INTERPOLATION_2M)
- #define gc0308_FULL_RESOLUTION 0x200000 // 2 megapixel
-#else
- #define gc0308_FULL_RESOLUTION 0x30000 // 0.3 megapixel#endif
-#endif
-#define gc0328_FULL_RESOLUTION 0x30000 // 0.3 megapixel
-#define gc0307_FULL_RESOLUTION 0x30000 // 0.3 megapixel
-#define gc0309_FULL_RESOLUTION 0x30000 // 0.3 megapixel
-#define gc2015_FULL_RESOLUTION 0x200000 // 2 megapixel
-#define siv120b_FULL_RESOLUTION 0x30000 // 0.3 megapixel
-#define siv121d_FULL_RESOLUTION 0x30000 // 0.3 megapixel
-#define sid130B_FULL_RESOLUTION 0x200000 // 2 megapixel
-
-#if defined(CONFIG_SOC_CAMERA_HI253_INTERPOLATION_5M)
- #define hi253_FULL_RESOLUTION 0x500000 // 5 megapixel
-#elif defined(CONFIG_SOC_CAMERA_HI253_INTERPOLATION_3M)
- #define hi253_FULL_RESOLUTION 0x300000 // 3 megapixel
-#else
- #define hi253_FULL_RESOLUTION 0x200000 // 2 megapixel
-#endif
-
-#define hi704_FULL_RESOLUTION 0x30000 // 0.3 megapixel
-#define nt99250_FULL_RESOLUTION 0x200000 // 2 megapixel
-#define sp0718_FULL_RESOLUTION 0x30000 // 0.3 megapixel
-#define sp0838_FULL_RESOLUTION 0x30000 // 0.3 megapixel
-#define sp2518_FULL_RESOLUTION 0x200000 // 2 megapixel
-#define gc0329_FULL_RESOLUTION 0x30000 // 0.3 megapixel
-#define s5k5ca_FULL_RESOLUTION 0x300000 // 3 megapixel
-#define mtk9335isp_FULL_RESOLUTION 0x500000 //5 megapixel
-#define gc2035_FULL_RESOLUTION 0x200000 // 2 megapixel
-#define hm2057_FULL_RESOLUTION 0x200000 // 2 megapixel
-#define hm5065_FULL_RESOLUTION 0x500000 // 5 megapixel
-#define nt99160_FULL_RESOLUTION 0x100000 // oyyf@rock-chips.com: 1 megapixel 1280*720
-#define nt99240_FULL_RESOLUTION 0x200000 // oyyf@rock-chips.com: 2 megapixel 1600*1200
-#define nt99252_FULL_RESOLUTION 0x200000 // oyyf@rock-chips.com: 2 megapixel 1600*1200
-#define nt99340_FULL_RESOLUTION 0x300000 // oyyf@rock-chips.com: 3 megapixel 2048*1536
-#define icatchmi1040_FULL_RESOLUTION 0x200000
-#define icatchov5693_FULL_RESOLUTION 0x500000
-#define icatchov8825_FULL_RESOLUTION 0x800000 //zyt
-#define icatchov2720_FULL_RESOLUTION 0x210000 //zyt
-#define end_FULL_RESOLUTION 0x00
-
-//Sensor i2c addr define
-#define ov7675_I2C_ADDR 0x78
-#define ov9650_I2C_ADDR 0x60
-#define ov2640_I2C_ADDR 0x60
-#define ov2655_I2C_ADDR 0x60
-#define ov2659_I2C_ADDR 0x60
-#define ov7690_I2C_ADDR 0x42
-#define ov3640_I2C_ADDR 0x78
-#define ov3660_I2C_ADDR 0x78
-#define ov5640_I2C_ADDR 0x78
-#define ov5642_I2C_ADDR 0x78
-
-#define s5k6aa_I2C_ADDR 0x78 //0x5a
-#define s5k5ca_I2C_ADDR 0x78 //0x5a
-
-#define mt9d112_I2C_ADDR 0x78
-#define mt9d113_I2C_ADDR 0x78
-#define mt9t111_I2C_ADDR 0x78 // 0x7a
-
-#define mt9p111_I2C_ADDR 0x78 //0x7a
-#define gt2005_I2C_ADDR 0x78
-#define gc0307_I2C_ADDR 0x42
-#define gc0328_I2C_ADDR 0x42
-#define gc0308_I2C_ADDR 0x42
-#define gc0309_I2C_ADDR 0x42
-#define gc0329_I2C_ADDR 0x62
-#define gc2015_I2C_ADDR 0x60
-#define gc2035_I2C_ADDR 0x78
-
-#define siv120b_I2C_ADDR INVALID_VALUE
-#define siv121d_I2C_ADDR INVALID_VALUE
-#define sid130B_I2C_ADDR 0x37
-
-#define hi253_I2C_ADDR 0x40
-#define hi704_I2C_ADDR 0x60
-
-#define nt99160_I2C_ADDR 0x54
-#define nt99240_I2C_ADDR 0x6c
-#define nt99250_I2C_ADDR 0x6c
-#define nt99252_I2C_ADDR 0x6c
-#define nt99340_I2C_ADDR 0x76
-
-#define sp0718_I2C_ADDR 0x42
-#define sp0838_I2C_ADDR INVALID_VALUE
-#define sp0a19_I2C_ADDR 0x7a
-#define sp1628_I2C_ADDR 0x78
-#define sp2518_I2C_ADDR 0x60
-#define mtk9335isp_I2C_ADDR 0x50
-#define hm2057_I2C_ADDR 0x48
-#define hm5065_I2C_ADDR 0x3e
-#define icatchmi1040_I2C_ADDR 0x78
-#define icatchov5693_I2C_ADDR 0x78
-#define icatchov8825_I2C_ADDR 0x78 //zyt
-#define icatchov2720_I2C_ADDR 0x78 //zyt
-#define end_I2C_ADDR INVALID_VALUE
-
-
-//Sensor power down active level define
-#define ov7675_PWRDN_ACTIVE 0x01
-#define ov9650_PWRDN_ACTIVE 0x01
-#define ov2640_PWRDN_ACTIVE 0x01
-#define ov2655_PWRDN_ACTIVE 0x01
-#define ov2659_PWRDN_ACTIVE 0x01
-#define ov7690_PWRDN_ACTIVE 0x01
-#define ov3640_PWRDN_ACTIVE 0x01
-#define ov3660_PWRDN_ACTIVE 0x01
-#define ov5640_PWRDN_ACTIVE 0x01
-#define ov5642_PWRDN_ACTIVE 0x01
-
-#define s5k6aa_PWRDN_ACTIVE 0x00
-#define s5k5ca_PWRDN_ACTIVE 0x00
-
-#define mt9d112_PWRDN_ACTIVE 0x01
-#define mt9d113_PWRDN_ACTIVE 0x01
-#define mt9t111_PWRDN_ACTIVE 0x01
-#define mt9p111_PWRDN_ACTIVE 0x01
-
-#define gt2005_PWRDN_ACTIVE 0x00
-#define gc0307_PWRDN_ACTIVE 0x01
-#define gc0308_PWRDN_ACTIVE 0x01
-#define gc0328_PWRDN_ACTIVE 0x01
-#define gc0309_PWRDN_ACTIVE 0x01
-#define gc0329_PWRDN_ACTIVE 0x01
-#define gc2015_PWRDN_ACTIVE 0x01
-#define gc2035_PWRDN_ACTIVE 0x01
-
-#define siv120b_PWRDN_ACTIVE INVALID_VALUE
-#define siv121d_PWRDN_ACTIVE INVALID_VALUE
-#define sid130B_PWRDN_ACTIVE 0x37
-
-#define hi253_PWRDN_ACTIVE 0x01
-#define hi704_PWRDN_ACTIVE 0x01
-
-#define nt99160_PWRDN_ACTIVE 0x01
-#define nt99240_PWRDN_ACTIVE 0x01
-#define nt99250_PWRDN_ACTIVE 0x01
-#define nt99252_PWRDN_ACTIVE 0x01
-#define nt99340_PWRDN_ACTIVE 0x01
-
-#define sp0718_PWRDN_ACTIVE 0x01
-#define sp0838_PWRDN_ACTIVE 0x01
-#define sp0a19_PWRDN_ACTIVE 0x01
-#define sp1628_PWRDN_ACTIVE 0x01
-#define sp2518_PWRDN_ACTIVE 0x01
-#define hm2057_PWRDN_ACTIVE 0x01
-#define hm5065_PWRDN_ACTIVE 0x00
-#define mtk9335isp_PWRDN_ACTIVE 0x01
-#define end_PWRDN_ACTIVE INVALID_VALUE
-
-
-//Sensor power up sequence define
-//type: bit0-bit4
-#define SENSOR_PWRSEQ_BEGIN 0x00
-#define SENSOR_PWRSEQ_AVDD 0x01
-#define SENSOR_PWRSEQ_DOVDD 0x02
-#define SENSOR_PWRSEQ_DVDD 0x03
-#define SENSOR_PWRSEQ_PWR 0x04
-#define SENSOR_PWRSEQ_HWRST 0x05
-#define SENSOR_PWRSEQ_PWRDN 0x06
-#define SENSOR_PWRSEQ_CLKIN 0x07
-#define SENSOR_PWRSEQ_END 0x0F
-
-#define SENSOR_PWRSEQ_SET(type,idx) (type<<(idx*4))
-#define SENSOR_PWRSEQ_GET(seq,idx) ((seq>>(idx*4))&0x0f)
-
-#define sensor_PWRSEQ_DEFAULT (SENSOR_PWRSEQ_SET(SENSOR_PWRSEQ_PWR,0)|\
- SENSOR_PWRSEQ_SET(SENSOR_PWRSEQ_HWRST,1)|\
- SENSOR_PWRSEQ_SET(SENSOR_PWRSEQ_PWRDN,2)|\
- SENSOR_PWRSEQ_SET(SENSOR_PWRSEQ_CLKIN,3))
-
-#define ov7675_PWRSEQ sensor_PWRSEQ_DEFAULT
-#define ov9650_PWRSEQ sensor_PWRSEQ_DEFAULT
-#define ov2640_PWRSEQ sensor_PWRSEQ_DEFAULT
-#define ov2655_PWRSEQ sensor_PWRSEQ_DEFAULT
-#define ov2659_PWRSEQ sensor_PWRSEQ_DEFAULT
-#define ov7690_PWRSEQ sensor_PWRSEQ_DEFAULT
-#define ov3640_PWRSEQ sensor_PWRSEQ_DEFAULT
-#define ov3660_PWRSEQ sensor_PWRSEQ_DEFAULT
-#define ov5640_PWRSEQ sensor_PWRSEQ_DEFAULT
-#define ov5642_PWRSEQ sensor_PWRSEQ_DEFAULT
-
-#define s5k6aa_PWRSEQ sensor_PWRSEQ_DEFAULT
-#define s5k5ca_PWRSEQ sensor_PWRSEQ_DEFAULT
-
-#define mt9d112_PWRSEQ sensor_PWRSEQ_DEFAULT
-#define mt9d113_PWRSEQ sensor_PWRSEQ_DEFAULT
-#define mt9t111_PWRSEQ sensor_PWRSEQ_DEFAULT
-#define mt9p111_PWRSEQ sensor_PWRSEQ_DEFAULT
-
-#define gt2005_PWRSEQ sensor_PWRSEQ_DEFAULT
-#define gc0307_PWRSEQ sensor_PWRSEQ_DEFAULT
-#define gc0308_PWRSEQ sensor_PWRSEQ_DEFAULT
-#define gc0328_PWRSEQ sensor_PWRSEQ_DEFAULT
-#define gc0309_PWRSEQ sensor_PWRSEQ_DEFAULT
-#define gc0329_PWRSEQ sensor_PWRSEQ_DEFAULT
-#define gc2015_PWRSEQ sensor_PWRSEQ_DEFAULT
-#define gc2035_PWRSEQ sensor_PWRSEQ_DEFAULT
-
-#define siv120b_PWRSEQ sensor_PWRSEQ_DEFAULT
-#define siv121d_PWRSEQ sensor_PWRSEQ_DEFAULT
-#define sid130B_PWRSEQ sensor_PWRSEQ_DEFAULT
-
-#define hi253_PWRSEQ sensor_PWRSEQ_DEFAULT
-#define hi704_PWRSEQ sensor_PWRSEQ_DEFAULT
-
-#define nt99160_PWRSEQ sensor_PWRSEQ_DEFAULT
-#define nt99240_PWRSEQ sensor_PWRSEQ_DEFAULT
-#define nt99250_PWRSEQ sensor_PWRSEQ_DEFAULT
-#define nt99252_PWRSEQ sensor_PWRSEQ_DEFAULT
-#define nt99340_PWRSEQ sensor_PWRSEQ_DEFAULT
-
-#define sp0718_PWRSEQ sensor_PWRSEQ_DEFAULT
-#define sp0838_PWRSEQ sensor_PWRSEQ_DEFAULT
-#define sp0a19_PWRSEQ sensor_PWRSEQ_DEFAULT
-#define sp1628_PWRSEQ sensor_PWRSEQ_DEFAULT
-#define sp2518_PWRSEQ sensor_PWRSEQ_DEFAULT
-#define hm2057_PWRSEQ sensor_PWRSEQ_DEFAULT
-#define hm5065_PWRSEQ (SENSOR_PWRSEQ_SET(SENSOR_PWRSEQ_PWR,1)|\
- SENSOR_PWRSEQ_SET(SENSOR_PWRSEQ_HWRST,2)|\
- SENSOR_PWRSEQ_SET(SENSOR_PWRSEQ_PWRDN,0)|\
- SENSOR_PWRSEQ_SET(SENSOR_PWRSEQ_CLKIN,3))
-#define mtk9335isp_PWRSEQ sensor_PWRSEQ_DEFAULT
-#define icatchov5693_PWRSEQ (SENSOR_PWRSEQ_SET(SENSOR_PWRSEQ_PWR,0)|\
- SENSOR_PWRSEQ_SET(SENSOR_PWRSEQ_HWRST,2)|\
- SENSOR_PWRSEQ_SET(SENSOR_PWRSEQ_CLKIN,1))
-
-#define icatchov8825_PWRSEQ (SENSOR_PWRSEQ_SET(SENSOR_PWRSEQ_PWR,0)|\
- SENSOR_PWRSEQ_SET(SENSOR_PWRSEQ_HWRST,2)|\
- SENSOR_PWRSEQ_SET(SENSOR_PWRSEQ_CLKIN,1)) //zyt
-
-#define icatchov2720_PWRSEQ (SENSOR_PWRSEQ_SET(SENSOR_PWRSEQ_PWR,0)|\
- SENSOR_PWRSEQ_SET(SENSOR_PWRSEQ_HWRST,2)|\
- SENSOR_PWRSEQ_SET(SENSOR_PWRSEQ_CLKIN,1)) //zyt
-
-#define icatchmi1040_PWRSEQ (SENSOR_PWRSEQ_SET(SENSOR_PWRSEQ_PWR,0)|\
- SENSOR_PWRSEQ_SET(SENSOR_PWRSEQ_HWRST,2)|\
- SENSOR_PWRSEQ_SET(SENSOR_PWRSEQ_CLKIN,1))
-
-#define end_PWRSEQ 0xffffffff
-
-
-
-/*---------------- Camera Sensor Must Define Macro End ------------------------*/
-
-
-//#define RK29_CAM_POWERACTIVE_BITPOS 0x00
-#define RK29_CAM_POWERACTIVE_MASK (1<<RK29_CAM_POWERACTIVE_BITPOS)
-#define RK29_CAM_POWERACTIVE_H (0x01<<RK29_CAM_POWERACTIVE_BITPOS)
-#define RK29_CAM_POWERACTIVE_L (0x00<<RK29_CAM_POWERACTIVE_BITPOS)
-
-//#define RK29_CAM_RESETACTIVE_BITPOS 0x01
-#define RK29_CAM_RESETACTIVE_MASK (1<<RK29_CAM_RESETACTIVE_BITPOS)
-#define RK29_CAM_RESETACTIVE_H (0x01<<RK29_CAM_RESETACTIVE_BITPOS)
-#define RK29_CAM_RESETACTIVE_L (0x00<<RK29_CAM_RESETACTIVE_BITPOS)
-
-//#define RK29_CAM_POWERDNACTIVE_BITPOS 0x02
-#define RK29_CAM_POWERDNACTIVE_MASK (1<<RK29_CAM_POWERDNACTIVE_BITPOS)
-#define RK29_CAM_POWERDNACTIVE_H (0x01<<RK29_CAM_POWERDNACTIVE_BITPOS)
-#define RK29_CAM_POWERDNACTIVE_L (0x00<<RK29_CAM_POWERDNACTIVE_BITPOS)
-
-//#define RK29_CAM_FLASHACTIVE_BITPOS 0x03
-#define RK29_CAM_FLASHACTIVE_MASK (1<<RK29_CAM_FLASHACTIVE_BITPOS)
-#define RK29_CAM_FLASHACTIVE_H (0x01<<RK29_CAM_FLASHACTIVE_BITPOS)
-#define RK29_CAM_FLASHACTIVE_L (0x00<<RK29_CAM_FLASHACTIVE_BITPOS)
-
-
-#define RK_CAM_SCALE_CROP_ARM 0
-#define RK_CAM_SCALE_CROP_IPP 1
-#define RK_CAM_SCALE_CROP_RGA 2
-#define RK_CAM_SCALE_CROP_PP 3
-
-#define RK_CAM_INPUT_FMT_YUV422 (1<<0)
-#define RK_CAM_INPUT_FMT_RAW10 (1<<1)
-#define RK_CAM_INPUT_FMT_RAW12 (1<<2)
-
-/* v4l2_subdev_core_ops.ioctl ioctl_cmd macro */
-#define RK29_CAM_SUBDEV_ACTIVATE 0x00
-#define RK29_CAM_SUBDEV_DEACTIVATE 0x01
-#define RK29_CAM_SUBDEV_IOREQUEST 0x02
-#define RK29_CAM_SUBDEV_CB_REGISTER 0x03
-
-#define Sensor_HasBeen_PwrOff(a) (a&0x01)
-#define Sensor_Support_DirectResume(a) ((a&0x10)==0x10)
-
-#define Sensor_CropSet(a,b) a->reserved[1] = b;
-#define Sensor_CropGet(a) a->reserved[1]
-
-#define RK29_CAM_SUBDEV_HDR_EXPOSURE 0x04
-
-#define RK_VIDEOBUF_HDR_EXPOSURE_MINUS_1 0x00
-#define RK_VIDEOBUF_HDR_EXPOSURE_NORMAL 0x01
-#define RK_VIDEOBUF_HDR_EXPOSURE_PLUS_1 0x02
-#define RK_VIDEOBUF_HDR_EXPOSURE_FINISH 0x03
-#define RK_VIDEOBUF_CODE_SET(rk_code,type) rk_code = (('R'<<24)|('K'<<16)|type)
-#define RK_VIDEOBUF_CODE_CHK(rk_code) ((rk_code&(('R'<<24)|('K'<<16)))==(('R'<<24)|('K'<<16)))
-
-enum rk29camera_ioctrl_cmd
-{
- Cam_Power,
- Cam_Reset,
- Cam_PowerDown,
- Cam_Flash,
- Cam_Mclk
-};
-
-enum rk29sensor_power_cmd
-{
- Sensor_Power,
- Sensor_Reset,
- Sensor_PowerDown,
- Sensor_Flash
-};
-
-enum rk29camera_flash_cmd
-{
- Flash_Off,
- Flash_On,
- Flash_Torch
-};
-
-struct rk29camera_gpio_res {
- unsigned int gpio_reset;
- unsigned int gpio_power;
- unsigned int gpio_powerdown;
- unsigned int gpio_flash;
- unsigned int gpio_flag;
- unsigned int gpio_init;
- const char *dev_name;
-};
-
-struct rk29camera_mem_res {
- const char *name;
- unsigned int start;
- unsigned int size;
- void __iomem *vbase;
-};
-struct rk29camera_info {
- const char *dev_name;
- unsigned int orientation;
- struct v4l2_frmivalenum fival[10];
-};
-
-struct reginfo_t
-{
- u16 reg;
- u16 val;
- u16 reg_len;
- u16 rev;
-};
-typedef struct rk_sensor_user_init_data{
- int rk_sensor_init_width;
- int rk_sensor_init_height;
- unsigned long rk_sensor_init_bus_param;
- enum v4l2_mbus_pixelcode rk_sensor_init_pixelcode;
- struct reginfo_t * rk_sensor_init_data;
- int rk_sensor_winseq_size;
- struct reginfo_t * rk_sensor_init_winseq;
- int rk_sensor_init_data_size;
-}rk_sensor_user_init_data_s;
-
-typedef struct rk_camera_device_register_info {
- struct i2c_board_info i2c_cam_info;
- struct soc_camera_link link_info;
- struct platform_device device_info;
-}rk_camera_device_register_info_t;
-
-struct rkcamera_platform_data {
- rk_camera_device_register_info_t dev;
- char dev_name[32];
- struct rk29camera_gpio_res io;
- int orientation;
- int resolution;
- int mirror; /* bit0: 0: mirror off
- 1: mirror on
- bit1: 0: flip off
- 1: flip on
- */
- int i2c_rate; /* 100KHz = 100000 */
- bool flash; /* true: the sensor attached flash;
- false: the sensor haven't attach flash;
-
- */
- int pwdn_info; /* bit4: 1: sensor isn't need to be init after exit stanby, it can streaming directly
- 0: sensor must be init after exit standby;
-
- bit0: 1: sensor power have been turn off;
- 0: sensor power is always on;
- */
-
- long powerup_sequence; /*
- bit0-bit3 --- power up sequence first step;
- bit4-bit7 --- power up sequence second step;
- .....
- */
- int mclk_rate; /* MHz : 24/48 */
- int fov_h; /* fied of view horizontal */
- int fov_v; /* fied of view vertical */
-
-};
-
-struct rk29camera_platform_data {
- int (*io_init)(void);
- int (*io_deinit)(int sensor);
- int (*iomux)(int pin);
- int (*sensor_ioctrl)(struct device *dev,enum rk29camera_ioctrl_cmd cmd,int on);
-
- int (*sensor_register)(void);
- int (*sensor_mclk)(int cif_idx, int on, int clk_rate);
-
- rk_sensor_user_init_data_s* sensor_init_data[RK_CAM_NUM];
- struct rk29camera_gpio_res gpio_res[RK_CAM_NUM];
- struct rk29camera_mem_res meminfo;
- struct rk29camera_mem_res meminfo_cif1;
- struct rk29camera_info info[RK_CAM_NUM];
- rk_camera_device_register_info_t register_dev[RK_CAM_NUM];
- struct rkcamera_platform_data *register_dev_new;
-};
-
-struct rk29camera_platform_ioctl_cb {
- int (*sensor_power_cb)(struct rk29camera_gpio_res *res, int on);
- int (*sensor_reset_cb)(struct rk29camera_gpio_res *res, int on);
- int (*sensor_powerdown_cb)(struct rk29camera_gpio_res *res, int on);
- int (*sensor_flash_cb)(struct rk29camera_gpio_res *res, int on);
-};
-
-typedef struct rk29_camera_sensor_cb {
- int (*sensor_cb)(void *arg);
- int (*scale_crop_cb)(struct work_struct *work);
-}rk29_camera_sensor_cb_s;
-#endif /* __ASM_ARCH_CAMERA_H_ */
-
+++ /dev/null
-#ifndef __PLAT_RK_FIQ_DEBUGGER_H
-#define __PLAT_RK_FIQ_DEBUGGER_H
-
-#ifdef CONFIG_FIQ_DEBUGGER
-void rk_serial_debug_init(void __iomem *base, int irq, int signal_irq, int wakeup_irq);
-#else
-static inline void rk_serial_debug_init(void __iomem *base, int irq, int signal_irq, int wakeup_irq)
-{
-}
-#endif
-
-#endif
+++ /dev/null
-#ifndef __PLAT_SRAM_H
-#define __PLAT_SRAM_H
-
-#ifdef CONFIG_PLAT_RK
-
-#include <linux/init.h>
-
-/* Tag variables with this */
-#define __sramdata __section(.sram.data)
-/* Tag constants with this */
-#define __sramconst __section(.sram.rodata)
-/* Tag functions inside SRAM called from outside SRAM with this */
-#define __sramfunc __attribute__((long_call)) __section(.sram.text) noinline
-/* Tag function inside SRAM called from inside SRAM with this */
-#define __sramlocalfunc __section(.sram.text)
-
-#define GPIO_SWPORTA_DR 0x0000
-#define GPIO_SWPORTA_DDR 0x0004
-
-struct sram_gpio_data {
- void __iomem *base;
- unsigned int offset;
-};
-
-extern struct sram_gpio_data __sramdata pmic_sleep,pmic_vsel;
-int sram_gpio_init(int gpio, struct sram_gpio_data *data);
-void __sramfunc sram_gpio_set_value(struct sram_gpio_data data, unsigned int value);
-
-int __init rk29_sram_init(void);
-
-static inline unsigned long ddr_save_sp(unsigned long new_sp)
-{
- unsigned long old_sp;
-
- asm volatile ("mov %0, sp" : "=r" (old_sp));
- asm volatile ("mov sp, %0" :: "r" (new_sp));
- return old_sp;
-}
-
-// save_sp ±ØÐ붨ÒåΪȫ¾Ö±äÁ¿
-#define DDR_SAVE_SP(save_sp) do { save_sp = ddr_save_sp(((unsigned long)SRAM_DATA_END & (~7))); } while (0)
-#define DDR_RESTORE_SP(save_sp) do { ddr_save_sp(save_sp); } while (0)
-
-extern void __sramfunc sram_printch(char byte);
-extern void __sramfunc sram_printascii(const char *s);
-extern void __sramfunc sram_printhex(unsigned int hex);
-extern void __sramfunc sram_log_char(char c);
-extern void __sramfunc sram_log_reset(void);
-
-#endif /* CONFIG_PLAT_RK */
-#endif
-
+++ /dev/null
-#ifndef __PLAT_SYSTEM_H
-#define __PLAT_SYSTEM_H
-
-#include <asm/proc-fns.h>
-
-static inline void arch_idle(void)
-{
- cpu_do_idle();
-}
-
-extern void (*arch_reset)(char, const char *);
-
-#endif
+++ /dev/null
-#ifndef __PLAT_TIMEX_H
-#define __PLAT_TIMEX_H
-
-#define CLOCK_TICK_RATE (HZ * 100000UL)
-
-#endif
+++ /dev/null
-#ifndef __PLAT_UNCOMPRESS_H
-#define __PLAT_UNCOMPRESS_H
-
-#include <linux/serial_reg.h>
-#include <mach/io.h>
-#include <mach/debug_uart.h>
-
-#ifdef DEBUG_UART_PHYS
-static volatile u32 *UART = (u32 *)DEBUG_UART_PHYS;
-
-static void putc(int c)
-{
- int i = 1000;
- while (i-- && !(UART[UART_LSR] & UART_LSR_THRE))
- barrier();
- UART[UART_TX] = c;
-}
-#else
-static inline void putc(int c)
-{
-}
-#endif
-
-static inline void flush(void)
-{
-}
-
-static inline void arch_decomp_setup(void)
-{
-}
-
-static inline void arch_decomp_wdog(void)
-{
-}
-
-#endif
+++ /dev/null
-/* arch/arm/mach-rk29/include/mach/vpu_service.h
- *
- * Copyright (C) 2010 ROCKCHIP, Inc.
- * author: chenhengming chm@rock-chips.com
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ARCH_ARM_MACH_RK29_VPU_SERVICE_H
-#define __ARCH_ARM_MACH_RK29_VPU_SERVICE_H
-
-#include <linux/ioctl.h> /* needed for the _IOW etc stuff used later */
-
-/*
- * Ioctl definitions
- */
-
-/* Use 'k' as magic number */
-#define VPU_IOC_MAGIC 'l'
-
-#define VPU_IOC_SET_CLIENT_TYPE _IOW(VPU_IOC_MAGIC, 1, unsigned long)
-#define VPU_IOC_GET_HW_FUSE_STATUS _IOW(VPU_IOC_MAGIC, 2, unsigned long)
-
-#define VPU_IOC_SET_REG _IOW(VPU_IOC_MAGIC, 3, unsigned long)
-#define VPU_IOC_GET_REG _IOW(VPU_IOC_MAGIC, 4, unsigned long)
-
-typedef enum VPU_CLIENT_TYPE {
- VPU_ENC = 0x0,
- VPU_DEC = 0x1,
- VPU_PP = 0x2,
- VPU_DEC_PP = 0x3,
- VPU_TYPE_BUTT ,
-
-} VPU_CLIENT_TYPE;
-
-/* Hardware decoder configuration description */
-
-typedef struct VPUHwDecConfig {
- unsigned long maxDecPicWidth; /* Maximum video decoding width supported */
- unsigned long maxPpOutPicWidth; /* Maximum output width of Post-Processor */
- unsigned long h264Support; /* HW supports h.264 */
- unsigned long jpegSupport; /* HW supports JPEG */
- unsigned long mpeg4Support; /* HW supports MPEG-4 */
- unsigned long customMpeg4Support; /* HW supports custom MPEG-4 features */
- unsigned long vc1Support; /* HW supports VC-1 Simple */
- unsigned long mpeg2Support; /* HW supports MPEG-2 */
- unsigned long ppSupport; /* HW supports post-processor */
- unsigned long ppConfig; /* HW post-processor functions bitmask */
- unsigned long sorensonSparkSupport; /* HW supports Sorenson Spark */
- unsigned long refBufSupport; /* HW supports reference picture buffering */
- unsigned long vp6Support; /* HW supports VP6 */
- unsigned long vp7Support; /* HW supports VP7 */
- unsigned long vp8Support; /* HW supports VP8 */
- unsigned long avsSupport; /* HW supports AVS */
- unsigned long jpegESupport; /* HW supports JPEG extensions */
- unsigned long rvSupport; /* HW supports REAL */
- unsigned long mvcSupport; /* HW supports H264 MVC extension */
-} VPUHwDecConfig_t;
-
-/* Hardware encoder configuration description */
-
-typedef struct VPUHwEndConfig
-{
- unsigned long maxEncodedWidth; /* Maximum supported width for video encoding (not JPEG) */
- unsigned long h264Enabled; /* HW supports H.264 */
- unsigned long jpegEnabled; /* HW supports JPEG */
- unsigned long mpeg4Enabled; /* HW supports MPEG-4 */
- unsigned long vsEnabled; /* HW supports video stabilization */
- unsigned long rgbEnabled; /* HW supports RGB input */
- unsigned long reg_size;
- unsigned long reserv[2]; /* reverved */
-} VPUHwEncConfig_t;
-
-typedef struct VPUHwCfgReq
-{
- unsigned long *cfg;
- unsigned long size;
-} VPUHwCfgReq_t;
-
-#define DWL_MPEG2_E 31 /* 1 bit */
-#define DWL_VC1_E 29 /* 2 bits */
-#define DWL_JPEG_E 28 /* 1 bit */
-#define DWL_MPEG4_E 26 /* 2 bits */
-#define DWL_H264_E 24 /* 2 bits */
-#define DWL_VP6_E 23 /* 1 bit */
-#define DWL_PJPEG_E 22 /* 1 bit */
-#define DWL_REF_BUFF_E 20 /* 1 bit */
-
-#define DWL_JPEG_EXT_E 31 /* 1 bit */
-#define DWL_REF_BUFF_ILACE_E 30 /* 1 bit */
-#define DWL_MPEG4_CUSTOM_E 29 /* 1 bit */
-#define DWL_REF_BUFF_DOUBLE_E 28 /* 1 bit */
-#define DWL_RV_E 26 /* 2 bits */
-#define DWL_VP7_E 24 /* 1 bit */
-#define DWL_VP8_E 23 /* 1 bit */
-#define DWL_AVS_E 22 /* 1 bit */
-#define DWL_MVC_E 20 /* 2 bits */
-
-#define DWL_CFG_E 24 /* 4 bits */
-#define DWL_PP_E 16 /* 1 bit */
-
-#define DWL_SORENSONSPARK_E 11 /* 1 bit */
-
-#define DWL_H264_FUSE_E 31 /* 1 bit */
-#define DWL_MPEG4_FUSE_E 30 /* 1 bit */
-#define DWL_MPEG2_FUSE_E 29 /* 1 bit */
-#define DWL_SORENSONSPARK_FUSE_E 28 /* 1 bit */
-#define DWL_JPEG_FUSE_E 27 /* 1 bit */
-#define DWL_VP6_FUSE_E 26 /* 1 bit */
-#define DWL_VC1_FUSE_E 25 /* 1 bit */
-#define DWL_PJPEG_FUSE_E 24 /* 1 bit */
-#define DWL_CUSTOM_MPEG4_FUSE_E 23 /* 1 bit */
-#define DWL_RV_FUSE_E 22 /* 1 bit */
-#define DWL_VP7_FUSE_E 21 /* 1 bit */
-#define DWL_VP8_FUSE_E 20 /* 1 bit */
-#define DWL_AVS_FUSE_E 19 /* 1 bit */
-#define DWL_MVC_FUSE_E 18 /* 1 bit */
-
-#define DWL_DEC_MAX_1920_FUSE_E 15 /* 1 bit */
-#define DWL_DEC_MAX_1280_FUSE_E 14 /* 1 bit */
-#define DWL_DEC_MAX_720_FUSE_E 13 /* 1 bit */
-#define DWL_DEC_MAX_352_FUSE_E 12 /* 1 bit */
-#define DWL_REF_BUFF_FUSE_E 7 /* 1 bit */
-
-
-#define DWL_PP_FUSE_E 31 /* 1 bit */
-#define DWL_PP_DEINTERLACE_FUSE_E 30 /* 1 bit */
-#define DWL_PP_ALPHA_BLEND_FUSE_E 29 /* 1 bit */
-#define DWL_PP_MAX_1920_FUSE_E 15 /* 1 bit */
-#define DWL_PP_MAX_1280_FUSE_E 14 /* 1 bit */
-#define DWL_PP_MAX_720_FUSE_E 13 /* 1 bit */
-#define DWL_PP_MAX_352_FUSE_E 12 /* 1 bit */
-
-
-#define MPEG4_NOT_SUPPORTED (u32)(0x00)
-#define MPEG4_SIMPLE_PROFILE (u32)(0x01)
-#define MPEG4_ADVANCED_SIMPLE_PROFILE (u32)(0x02)
-#define MPEG4_CUSTOM_NOT_SUPPORTED (u32)(0x00)
-#define MPEG4_CUSTOM_FEATURE_1 (u32)(0x01)
-#define H264_NOT_SUPPORTED (u32)(0x00)
-#define H264_BASELINE_PROFILE (u32)(0x01)
-#define H264_MAIN_PROFILE (u32)(0x02)
-#define H264_HIGH_PROFILE (u32)(0x03)
-#define VC1_NOT_SUPPORTED (u32)(0x00)
-#define VC1_SIMPLE_PROFILE (u32)(0x01)
-#define VC1_MAIN_PROFILE (u32)(0x02)
-#define VC1_ADVANCED_PROFILE (u32)(0x03)
-#define MPEG2_NOT_SUPPORTED (u32)(0x00)
-#define MPEG2_MAIN_PROFILE (u32)(0x01)
-#define JPEG_NOT_SUPPORTED (u32)(0x00)
-#define JPEG_BASELINE (u32)(0x01)
-#define JPEG_PROGRESSIVE (u32)(0x02)
-#define PP_NOT_SUPPORTED (u32)(0x00)
-#define PP_SUPPORTED (u32)(0x01)
-#define PP_DITHERING (u32)(0x10000000)
-#define PP_SCALING (u32)(0x0C000000)
-#define PP_DEINTERLACING (u32)(0x02000000)
-#define PP_ALPHA_BLENDING (u32)(0x01000000)
-#define SORENSON_SPARK_NOT_SUPPORTED (u32)(0x00)
-#define SORENSON_SPARK_SUPPORTED (u32)(0x01)
-#define VP6_NOT_SUPPORTED (u32)(0x00)
-#define VP6_SUPPORTED (u32)(0x01)
-#define VP7_NOT_SUPPORTED (u32)(0x00)
-#define VP7_SUPPORTED (u32)(0x01)
-#define VP8_NOT_SUPPORTED (u32)(0x00)
-#define VP8_SUPPORTED (u32)(0x01)
-#define REF_BUF_NOT_SUPPORTED (u32)(0x00)
-#define REF_BUF_SUPPORTED (u32)(0x01)
-#define REF_BUF_INTERLACED (u32)(0x02)
-#define REF_BUF_DOUBLE (u32)(0x04)
-#define AVS_NOT_SUPPORTED (u32)(0x00)
-#define AVS_SUPPORTED (u32)(0x01)
-#define JPEG_EXT_NOT_SUPPORTED (u32)(0x00)
-#define JPEG_EXT_SUPPORTED (u32)(0x01)
-#define RV_NOT_SUPPORTED (u32)(0x00)
-#define RV_SUPPORTED (u32)(0x01)
-#define MVC_NOT_SUPPORTED (u32)(0x00)
-#define MVC_SUPPORTED (u32)(0x01)
-
-#define H264_NOT_SUPPORTED_FUSE (u32)(0x00)
-#define H264_FUSE_ENABLED (u32)(0x01)
-#define MPEG4_NOT_SUPPORTED_FUSE (u32)(0x00)
-#define MPEG4_FUSE_ENABLED (u32)(0x01)
-#define MPEG2_NOT_SUPPORTED_FUSE (u32)(0x00)
-#define MPEG2_FUSE_ENABLED (u32)(0x01)
-#define SORENSON_SPARK_NOT_SUPPORTED_FUSE (u32)(0x00)
-#define SORENSON_SPARK_ENABLED (u32)(0x01)
-#define JPEG_NOT_SUPPORTED_FUSE (u32)(0x00)
-#define JPEG_FUSE_ENABLED (u32)(0x01)
-#define VP6_NOT_SUPPORTED_FUSE (u32)(0x00)
-#define VP6_FUSE_ENABLED (u32)(0x01)
-#define VP7_NOT_SUPPORTED_FUSE (u32)(0x00)
-#define VP7_FUSE_ENABLED (u32)(0x01)
-#define VP8_NOT_SUPPORTED_FUSE (u32)(0x00)
-#define VP8_FUSE_ENABLED (u32)(0x01)
-#define VC1_NOT_SUPPORTED_FUSE (u32)(0x00)
-#define VC1_FUSE_ENABLED (u32)(0x01)
-#define JPEG_PROGRESSIVE_NOT_SUPPORTED_FUSE (u32)(0x00)
-#define JPEG_PROGRESSIVE_FUSE_ENABLED (u32)(0x01)
-#define REF_BUF_NOT_SUPPORTED_FUSE (u32)(0x00)
-#define REF_BUF_FUSE_ENABLED (u32)(0x01)
-#define AVS_NOT_SUPPORTED_FUSE (u32)(0x00)
-#define AVS_FUSE_ENABLED (u32)(0x01)
-#define RV_NOT_SUPPORTED_FUSE (u32)(0x00)
-#define RV_FUSE_ENABLED (u32)(0x01)
-#define MVC_NOT_SUPPORTED_FUSE (u32)(0x00)
-#define MVC_FUSE_ENABLED (u32)(0x01)
-
-#define PP_NOT_SUPPORTED_FUSE (u32)(0x00)
-#define PP_FUSE_ENABLED (u32)(0x01)
-#define PP_FUSE_DEINTERLACING_ENABLED (u32)(0x40000000)
-#define PP_FUSE_ALPHA_BLENDING_ENABLED (u32)(0x20000000)
-#define MAX_PP_OUT_WIDHT_1920_FUSE_ENABLED (u32)(0x00008000)
-#define MAX_PP_OUT_WIDHT_1280_FUSE_ENABLED (u32)(0x00004000)
-#define MAX_PP_OUT_WIDHT_720_FUSE_ENABLED (u32)(0x00002000)
-#define MAX_PP_OUT_WIDHT_352_FUSE_ENABLED (u32)(0x00001000)
-
-#define VPU_DEC_HWCFG0 50
-#define VPU_DEC_HWCFG1 51
-#define VPU_DEC_HW_FUSE_CFG 57
-#define VPU_PP_HW_SYNTH_CFG 40
-#define VPU_PP_HW_FUSE_CFG 41
-
-typedef struct VPUHwFuseStatus
-{
- u32 h264SupportFuse; /* HW supports h.264 */
- u32 mpeg4SupportFuse; /* HW supports MPEG-4 */
- u32 mpeg2SupportFuse; /* HW supports MPEG-2 */
- u32 sorensonSparkSupportFuse; /* HW supports Sorenson Spark */
- u32 jpegSupportFuse; /* HW supports JPEG */
- u32 vp6SupportFuse; /* HW supports VP6 */
- u32 vp7SupportFuse; /* HW supports VP6 */
- u32 vp8SupportFuse; /* HW supports VP6 */
- u32 vc1SupportFuse; /* HW supports VC-1 Simple */
- u32 jpegProgSupportFuse; /* HW supports Progressive JPEG */
- u32 ppSupportFuse; /* HW supports post-processor */
- u32 ppConfigFuse; /* HW post-processor functions bitmask */
- u32 maxDecPicWidthFuse; /* Maximum video decoding width supported */
- u32 maxPpOutPicWidthFuse; /* Maximum output width of Post-Processor */
- u32 refBufSupportFuse; /* HW supports reference picture buffering */
- u32 avsSupportFuse; /* one of the AVS values defined above */
- u32 rvSupportFuse; /* one of the REAL values defined above */
- u32 mvcSupportFuse;
- u32 customMpeg4SupportFuse; /* Fuse for custom MPEG-4 */
-
-} VPUHwFuseStatus_t;
-
-
-#endif
-
+++ /dev/null
-#include <linux/init.h>
-#include <linux/module.h>
-#include <mach/iomux.h>
-#include <mach/gpio.h>
-#include <asm/io.h>
-
-#if 0
-#define DBG(x...) INFO(KERN_INFO x)
-#else
-#define DBG(x...)
-#endif
-
-#define INFO(x...) printk(KERN_INFO x)
-
-struct iomux_mode{
- unsigned int mode:4,
- off:4,
- goff:4,
- bank:4,
- reserve:16;
-};
-struct union_mode{
- union{
- struct iomux_mode mux;
- unsigned int mode;
- };
-};
-
-static inline int mode_is_valid(unsigned int mode)
-{
- struct union_mode m;
-
- m.mode = mode;
- if(mode == INVALID_MODE || m.mux.bank >= GPIO_BANKS)
- return 0;
- else
- return 1;
-
-}
-
-int iomux_mode_to_gpio(unsigned int mode)
-{
- struct union_mode m;
-
- if(!mode_is_valid(mode)){
- INFO("<%s> mode(0x%x) is invalid\n", __func__, mode);
- return INVALID_GPIO;
- }
-
- m.mode = mode;
- return PIN_BASE + m.mux.bank * 32 + (m.mux.goff - 0x0A) * 8 + m.mux.off;
-}
-EXPORT_SYMBOL(iomux_mode_to_gpio);
-
-int iomux_gpio_to_mode(int gpio)
-{
- unsigned int off;
- struct union_mode m;
-
- if(!gpio_is_valid(gpio)){
- INFO("<%s> gpio(%d), is invalid\n", __func__, gpio);
- return INVALID_MODE;
- }
-
- off = gpio - PIN_BASE;
- m.mux.bank = off/32;
- m.mux.goff = (off%32)/8 + 0x0A;
- m.mux.off = (off%32)%8;
-
- if(!mode_is_valid(m.mode)){
- INFO("<%s> gpio(gpio%d_%x%d) is invalid\n", __func__, m.mux.bank, m.mux.goff, m.mux.off);
- return INVALID_MODE;
- }
-
- return m.mode;
-}
-EXPORT_SYMBOL(iomux_gpio_to_mode);
-
-#ifdef GRF_IOMUX_BASE
-void iomux_set(unsigned int mode)
-{
- unsigned int v, addr, mask;
- struct union_mode m;
-
- m.mode = mode;
- if(!mode_is_valid(mode)){
- INFO("<%s> mode(0x%x) is invalid\n", __func__, mode);
- return;
- }
- //mask = (m.mux.mode < 2)?1:3;
- mask = 3;
- v = (m.mux.mode << (m.mux.off * 2)) + (mask << (m.mux.off * 2 + 16));
-#if defined(CONFIG_ARCH_RK319X)
- if (m.mux.bank == 0)
- addr = (unsigned int)RK319X_BB_GRF_BASE + BB_GRF_GPIO0A_IOMUX + 4 * (m.mux.goff - 0x0A);
- else
-#endif
- addr = (unsigned int)GRF_IOMUX_BASE + 16 * m.mux.bank + 4 * (m.mux.goff - 0x0A);
-
- DBG("<%s> mode(0x%04x), reg_addr(0x%08x), set_value(0x%08x)\n", __func__, mode, addr, v);
-
- writel_relaxed(v, (void *)addr);
-}
-int iomux_is_set(unsigned int mode)
-{
- unsigned int v, addr, mask;
- struct union_mode m;
-
- m.mode = mode;
- if(!mode_is_valid(mode)){
- INFO("<%s> mode(0x%x) is invalid\n", __func__, mode);
- return -1;
- }
- mask = 3;
- v = (m.mux.mode << (m.mux.off * 2)) + (mask << (m.mux.off * 2 + 16));
-#if defined(CONFIG_ARCH_RK319X)
- if (m.mux.bank == 0)
- addr = (unsigned int)RK319X_BB_GRF_BASE + BB_GRF_GPIO0A_IOMUX + 4 * (m.mux.goff - 0x0A);
- else
-#endif
- addr = (unsigned int)GRF_IOMUX_BASE + 16 * m.mux.bank + 4 * (m.mux.goff - 0x0A);
-
- if((readl_relaxed((void *)addr) & v) != 0)
- return 1;
- else if((mode & 0x03) == 0) //gpio mode
- return 1;
- else
- return 0;
-}
-#else
-void iomux_set(unsigned int mode)
-{
- INFO("%s is not support\n", __func__);
- return;
-}
-int iomux_is_set(unsigned int mode)
-{
- INFO("%s is not support\n", __func__);
- return;
-}
-#endif
-EXPORT_SYMBOL(iomux_set);
-
-void iomux_set_gpio_mode(int gpio)
-{
- unsigned int mode;
-
- mode = iomux_gpio_to_mode(gpio);
- if(mode_is_valid(mode))
- iomux_set(mode);
-}
-EXPORT_SYMBOL(iomux_set_gpio_mode);
-
-static unsigned int default_mode[] = {
-#ifdef GRF_IOMUX_BASE
- #if defined(CONFIG_UART0_RK29) || (CONFIG_RK_DEBUG_UART == 0)
- UART0_SOUT, UART0_SIN,
- #ifdef CONFIG_UART0_CTS_RTS_RK29
- UART0_RTSN, UART0_CTSN,
- #endif
- #endif
-
- #if defined(CONFIG_UART1_RK29) || (CONFIG_RK_DEBUG_UART == 1)
- UART1_SIN, UART1_SOUT,
- #ifdef CONFIG_UART1_CTS_RTS_RK29
- UART1_CTSN, UART1_RTSN,
- #endif
- #endif
-
- #if defined(CONFIG_UART2_RK29) || (CONFIG_RK_DEBUG_UART == 2)
- UART2_SIN, UART2_SOUT,
- #ifdef CONFIG_UART2_CTS_RTS_RK29
- UART2_CTSN, UART2_RTSN,
- #endif
- #endif
-
- #if defined(CONFIG_UART3_RK29) || (CONFIG_RK_DEBUG_UART == 3)
- UART3_SIN, UART3_SOUT,
- #ifdef CONFIG_UART3_CTS_RTS_RK29
- UART3_CTSN, UART3_RTSN,
- #endif
- #endif
-
- #ifdef CONFIG_SPIM0_RK29
- SPI0_CLK, SPI0_TXD, SPI0_RXD, SPI0_CS0,
- #endif
-
- #ifdef CONFIG_SPIM1_RK29
- SPI1_CLK, SPI1_TXD, SPI1_RXD, SPI1_CS0,
- #endif
-
- #ifdef CONFIG_I2C0_RK30
- I2C0_SCL, I2C0_SDA,
- #endif
-
- #ifdef CONFIG_I2C1_RK30
- I2C1_SCL, I2C1_SDA,
- #endif
-
- #ifdef CONFIG_I2C2_RK30
- I2C2_SDA, I2C2_SCL,
- #endif
-
- #ifdef CONFIG_I2C3_RK30
- I2C3_SDA, I2C3_SCL,
- #endif
-
- #ifdef CONFIG_I2C4_RK30
- I2C4_SDA, I2C4_SCL,
- #endif
-
- #ifdef CONFIG_RK30_VMAC
- RMII_CLKOUT, RMII_TXEN, RMII_TXD1, RMII_TXD0, RMII_RXERR,
- RMII_CRS, RMII_RXD1, RMII_RXD0, RMII_MD, RMII_MDCLK,
- #endif
-#endif
-};
-
-void __init iomux_init(void)
-{
- int i, len;
-
- len = ARRAY_SIZE(default_mode);
- for(i = 0; i < len; i++)
- iomux_set(default_mode[i]);
-
- return;
-}
-EXPORT_SYMBOL(iomux_init);
-
+++ /dev/null
-/*
- * arch/arm/mach-rk29/last_log.c
- *
- * Copyright (C) 2011 ROCKCHIP, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#define pr_fmt(fmt) "last_log: " fmt
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/proc_fs.h>
-#include <linux/vmalloc.h>
-#include <asm/uaccess.h>
-#include <asm/io.h>
-
-#define LOG_BUF_LEN (1 << CONFIG_LOG_BUF_SHIFT)
-#define LOG_BUF_PAGE_ORDER (CONFIG_LOG_BUF_SHIFT - PAGE_SHIFT)
-static char last_log_buf[LOG_BUF_LEN];
-extern void __init switch_log_buf(char *new_log_buf, unsigned size);
-
-char *last_log_get(unsigned *size)
-{
- *size = LOG_BUF_LEN;
- return last_log_buf;
-}
-
-static ssize_t last_log_read(struct file *file, char __user *buf,
- size_t len, loff_t *offset)
-{
- loff_t pos = *offset;
- ssize_t count;
-
- if (pos >= LOG_BUF_LEN)
- return 0;
-
- count = min(len, (size_t)(LOG_BUF_LEN - pos));
- if (copy_to_user(buf, &last_log_buf[pos], count))
- return -EFAULT;
-
- *offset += count;
- return count;
-}
-
-static const struct file_operations last_log_file_ops = {
- .owner = THIS_MODULE,
- .read = last_log_read,
-};
-
-static void * __init last_log_vmap(phys_addr_t start, unsigned int page_count)
-{
- struct page *pages[page_count + 1];
- unsigned int i;
-
- for (i = 0; i < page_count; i++) {
- phys_addr_t addr = start + i * PAGE_SIZE;
- pages[i] = pfn_to_page(addr >> PAGE_SHIFT);
- }
- pages[page_count] = pfn_to_page(start >> PAGE_SHIFT);
- return vmap(pages, page_count + 1, VM_MAP, pgprot_noncached(PAGE_KERNEL));
-}
-
-static int __init last_log_init(void)
-{
- char *log_buf, *new_log_buf;
- struct proc_dir_entry *entry;
-
- log_buf = (char *)__get_free_pages(GFP_KERNEL, LOG_BUF_PAGE_ORDER);
- if (!log_buf) {
- pr_err("failed to __get_free_pages(%d)\n", LOG_BUF_PAGE_ORDER);
- return 0;
- }
-
- new_log_buf = last_log_vmap(virt_to_phys(log_buf), 1 << LOG_BUF_PAGE_ORDER);
- if (!new_log_buf) {
- pr_err("failed to map %d pages at 0x%08x\n", 1 << LOG_BUF_PAGE_ORDER, virt_to_phys(log_buf));
- return 0;
- }
-
- pr_info("0x%p map to 0x%p and copy to 0x%p (version 2.1)\n", log_buf, new_log_buf, last_log_buf);
-
- memcpy(last_log_buf, new_log_buf, LOG_BUF_LEN);
- memset(new_log_buf, 0, LOG_BUF_LEN);
- switch_log_buf(new_log_buf, LOG_BUF_LEN);
-
- entry = create_proc_entry("last_log", S_IFREG | S_IRUGO, NULL);
- if (!entry) {
- pr_err("failed to create proc entry\n");
- return 0;
- }
-
- entry->proc_fops = &last_log_file_ops;
- entry->size = LOG_BUF_LEN;
-
-#ifndef CONFIG_ANDROID_RAM_CONSOLE
- proc_symlink("last_kmsg", NULL, "last_log");
-#endif
-
- return 0;
-}
-
-postcore_initcall(last_log_init);
-
+++ /dev/null
-#include <plat/board.h>
-#include <linux/memblock.h>
-#include <asm/setup.h>
-/* Macros for Data Alignment : size */
-#define ALIGN_SZ(p, a) \
- (((p) + ((a) - 1)) & ~((a) - 1))
-
-static size_t reserved_size = 0;
-static phys_addr_t reserved_base_end = 0;
-
-phys_addr_t __init board_mem_reserve_add(char *name, size_t size)
-{
- phys_addr_t base = 0;
- size_t align_size = ALIGN_SZ(size, SZ_1M);
-
- if (reserved_base_end == 0) {
- reserved_base_end = meminfo.bank[meminfo.nr_banks - 1].start + meminfo.bank[meminfo.nr_banks - 1].size;
- /* Workaround for RGA driver, which may overflow on physical memory address parameter */
- if (reserved_base_end > 0xA0000000)
- reserved_base_end = 0xA0000000;
- }
-
- reserved_size += align_size;
- base = reserved_base_end - reserved_size;
- pr_info("memory reserve: Memory(base:0x%x size:%dM) reserved for <%s>\n",
- base, align_size/SZ_1M, name);
- return base;
-}
-
-void __init board_mem_reserved(void)
-{
- phys_addr_t base = reserved_base_end - reserved_size;
-
- if(reserved_size){
- memblock_remove(base, reserved_size);
- pr_info("memory reserve: Total reserved %dM\n", reserved_size/SZ_1M);
- }
-}
+++ /dev/null
-/*
- * Very simple but very effective user-space memory tester.
- * Originally by Simon Kirby <sim@stormix.com> <sim@neato.org>
- * Version 2 by Charles Cazabon <charlesc-memtester@pyropus.ca>
- * Version 3 not publicly released.
- * Version 4 rewrite:
- * Copyright (C) 2004-2010 Charles Cazabon <charlesc-memtester@pyropus.ca>
- * Licensed under the terms of the GNU General Public License version 2 (only).
- * See the file COPYING for details.
- *
- * This file contains the functions for the actual tests, called from the
- * main routine in memtester.c. See other comments in that file.
- *
- */
-#include <linux/kernel.h>
-#include <linux/random.h>
-#include <linux/slab.h>
-#include <plat/sram.h>
-
-//#if (ULONG_MAX == 4294967295UL)
-#if 1
- #define rand_ul() random32()
- #define UL_ONEBITS 0xffffffff
- #define UL_LEN 32
- #define CHECKERBOARD1 0x55555555
- #define CHECKERBOARD2 0xaaaaaaaa
- #define UL_BYTE(x) ((x | x << 8 | x << 16 | x << 24))
-#elif (ULONG_MAX == 18446744073709551615ULL)
- #define rand64() (((ul) rand32()) << 32 | ((ul) rand32()))
- #define rand_ul() rand64()
- #define UL_ONEBITS 0xffffffffffffffffUL
- #define UL_LEN 64
- #define CHECKERBOARD1 0x5555555555555555
- #define CHECKERBOARD2 0xaaaaaaaaaaaaaaaa
- #define UL_BYTE(x) (((ul)x | (ul)x<<8 | (ul)x<<16 | (ul)x<<24 | (ul)x<<32 | (ul)x<<40 | (ul)x<<48 | (ul)x<<56))
-#else
- #error long on this platform is not 32 or 64 bits
-#endif
-
-#define TEST_ALL
-
-#ifdef TEST_ALL // TEST_ALL的时候这些都不动
-#define TEST_RANDOM
-#define TEST_XOR
-#define TEST_SUB
-#define TEST_MUL
-#define TEST_DIV
-#define TEST_OR
-#define TEST_AND
-#define TEST_SEQINC
-#define TEST_SOLID_BIT
-#define TEST_BLOCK_SEQ
-#define TEST_CHECK_BOARD
-#define TEST_BIT_SPREAD
-#define TEST_BIT_FLIP
-#define TEST_ONE
-#define TEST_ZERO
-#define TEST_NARROW_WRITES
-#else //这些配置用于增删
-//#define TEST_RANDOM
-//#define TEST_XOR
-//#define TEST_SUB
-//#define TEST_MUL
-//#define TEST_DIV
-//#define TEST_OR
-//#define TEST_AND
-//#define TEST_SEQINC
-//#define TEST_SOLID_BIT
-//#define TEST_BLOCK_SEQ
-//#define TEST_CHECK_BOARD
-//#define TEST_BIT_SPREAD
-#define TEST_BIT_FLIP
-//#define TEST_ONE
-//#define TEST_ZERO
-//#define TEST_NARROW_WRITES
-#endif
-
-
-typedef unsigned long ul;
-typedef unsigned long long ull;
-typedef unsigned long volatile ulv;
-typedef unsigned char volatile u8v;
-typedef unsigned short volatile u16v;
-
-struct test
-{
- char *name;
- int (*fp)(ulv *bufa, ulv *bufb, size_t count);
-};
-
-union {
- unsigned char bytes[UL_LEN/8];
- ul val;
-} mword8;
-
-union {
- unsigned short u16s[UL_LEN/16];
- ul val;
-} mword16;
-
-#define printf(s) sram_printascii(s)
-#define fflush(out) do {} while (0)
-#define putchar(c) sram_printch(c)
-
-static void print(const char *s)
-{
- sram_printascii(s);
-}
-
-static void print_Hex(unsigned int hex)
-{
- sram_printhex(hex);
-}
-
-static void print_Dec (uint32_t n)
-{
- if (n >= 10)
- {
- print_Dec(n / 10);
- n %= 10;
- }
- sram_printch((char)(n + '0'));
-}
-
-static void print_Dec_3(uint32_t value)
-{
- if(value<10)
- {
- print(" ");
- }
- else if(value<100)
- {
- print(" ");
- }
- else
- {
- }
- print_Dec(value);
-}
-
-static const char progress[] = "-\\|/";
-#define PROGRESSLEN 4
-#define PROGRESSOFTEN 2500
-#define ONE 0x00000001L
-
-/* Function definitions. */
-
-static int compare_regions(ulv *bufa, ulv *bufb, size_t count) {
- int r = 0;
- size_t i;
- ulv *p1 = bufa;
- ulv *p2 = bufb;
- int n=0;
-
- for (i = 0; i < count; i++, p1++, p2++) {
- if (*p1 != *p2) {
- {
- print("FAILURE: 0x");
- print_Hex((ul) *p1);
- print(" != 0x");
- print_Hex((ul) *p2);
- print(" at offset 0x");
- print_Hex((ul) i);
- print(".\n");
- }
- /* printf("Skipping to next test..."); */
- r = -1;
- n++;
- if(n>10)
- {
- break;
- }
- }
- }
- return r;
-}
-
-static int compare_regions_reverse(ulv *bufa, ulv *bufb, size_t count) {
- int r = 0;
- size_t i;
- ulv *p1 = bufa;
- ulv *p2 = bufb;
- int n=0;
-
- for (i = 0; i < count; i++, p1++, p2++) {
- if (*p1 != ~(*p2)) {
- {
- print("FAILURE: 0x");
- print_Hex((ul) *p1);
- print(" != 0x");
- print_Hex((ul) *p2);
- print(" at offset 0x");
- print_Hex((ul) i);
- print(".\n");
- }
- /* printf("Skipping to next test..."); */
- r = -1;
- n++;
- if(n>10)
- {
- break;
- }
- }
- }
- return r;
-}
-
-static int test_stuck_address(ulv *bufa, size_t count) {
- ulv *p1 = bufa;
- unsigned int j;
- size_t i;
-
- print(" ");
- for (j = 0; j < 16; j++) {
- print("\b\b\b\b\b\b\b\b\b\b\b");
- p1 = (ulv *) bufa;
- print("setting ");
- print_Dec_3(j);
- for (i = 0; i < count; i++) {
- *p1 = ((j + i) % 2) == 0 ? (ul) p1 : ~((ul) p1);
- *p1++;
- }
- print("\b\b\b\b\b\b\b\b\b\b\b");
- print("testing ");
- print_Dec_3(j);
- p1 = (ulv *) bufa;
- for (i = 0; i < count; i++, p1++) {
- if (*p1 != (((j + i) % 2) == 0 ? (ul) p1 : ~((ul) p1))) {
- {
- print("FAILURE: possible bad address line at offset 0x");
- print_Hex((ul) i);
- print(".\n");
- }
- print("Skipping to next test...\n");
- return -1;
- }
- }
- }
- print("\b\b\b\b\b\b\b\b\b\b\b \b\b\b\b\b\b\b\b\b\b\b");
- return 0;
-}
-
-#ifdef TEST_RANDOM
-static int test_random_value(ulv *bufa, ulv *bufb, size_t count) {
- ulv *p1 = bufa;
- ulv *p2 = bufb;
- size_t i;
-
- for (i = 0; i < count; i++) {
- *p1++ = *p2++ = rand_ul();
- if (!(i % PROGRESSOFTEN)) {
- }
- }
- print("\b \b");
- return compare_regions(bufa, bufb, count);
-}
-#endif
-
-#ifdef TEST_XOR
-static int test_xor_comparison(ulv *bufa, ulv *bufb, size_t count) {
- ulv *p1 = bufa;
- ulv *p2 = bufb;
- size_t i;
- ul q = rand_ul();
-
- for (i = 0; i < count; i++) {
- *p1++ ^= q;
- *p2++ ^= q;
- }
- return compare_regions(bufa, bufb, count);
-}
-#endif
-
-#ifdef TEST_SUB
-static int test_sub_comparison(ulv *bufa, ulv *bufb, size_t count) {
- ulv *p1 = bufa;
- ulv *p2 = bufb;
- size_t i;
- ul q = rand_ul();
-
- for (i = 0; i < count; i++) {
- *p1++ -= q;
- *p2++ -= q;
- }
- return compare_regions(bufa, bufb, count);
-}
-#endif
-
-#ifdef TEST_MUL
-static int test_mul_comparison(ulv *bufa, ulv *bufb, size_t count) {
- ulv *p1 = bufa;
- ulv *p2 = bufb;
- size_t i;
- ul q = rand_ul();
-
- for (i = 0; i < count; i++) {
- *p1++ *= q;
- *p2++ *= q;
- }
- return compare_regions(bufa, bufb, count);
-}
-#endif
-
-#ifdef TEST_DIV
-static int test_div_comparison(ulv *bufa, ulv *bufb, size_t count) {
- ulv *p1 = bufa;
- ulv *p2 = bufb;
- size_t i;
- ul q = rand_ul();
-
- for (i = 0; i < count; i++) {
- if (!q) {
- q++;
- }
- *p1++ /= q;
- *p2++ /= q;
- }
- return compare_regions(bufa, bufb, count);
-}
-#endif
-
-#ifdef TEST_OR
-static int test_or_comparison(ulv *bufa, ulv *bufb, size_t count) {
- ulv *p1 = bufa;
- ulv *p2 = bufb;
- size_t i;
- ul q = rand_ul();
-
- for (i = 0; i < count; i++) {
- *p1++ |= q;
- *p2++ |= q;
- }
- return compare_regions(bufa, bufb, count);
-}
-#endif
-
-#ifdef TEST_AND
-static int test_and_comparison(ulv *bufa, ulv *bufb, size_t count) {
- ulv *p1 = bufa;
- ulv *p2 = bufb;
- size_t i;
- ul q = rand_ul();
-
- for (i = 0; i < count; i++) {
- *p1++ &= q;
- *p2++ &= q;
- }
- return compare_regions(bufa, bufb, count);
-}
-#endif
-
-#ifdef TEST_SEQINC
-static int test_seqinc_comparison(ulv *bufa, ulv *bufb, size_t count) {
- ulv *p1 = bufa;
- ulv *p2 = bufb;
- size_t i;
- ul q = rand_ul();
- ul value;
-
- for (i = 0; i < count; i++) {
- value = (i+q);
- *p1++ = value;
- *p2++ = ~value;
- //*p1++ = *p2++ = (i + q);
- }
- return compare_regions_reverse(bufa, bufb, count);
-}
-#endif
-
-#ifdef TEST_SOLID_BIT
-static int test_solidbits_comparison(ulv *bufa, ulv *bufb, size_t count) {
- ulv *p1 = bufa;
- ulv *p2 = bufb;
- unsigned int j;
- ul q;
- size_t i;
- ul value;
-
- print(" ");
- for (j = 0; j < 64; j++) {
- print("\b\b\b\b\b\b\b\b\b\b\b");
- q = (j % 2) == 0 ? UL_ONEBITS : 0;
- print("setting ");
- print_Dec_3(j);
- p1 = (ulv *) bufa;
- p2 = (ulv *) bufb;
- for (i = 0; i < count; i++) {
- value = (i % 2) == 0 ? q : ~q;
- *p1++ = value;
- *p2++ = ~value;
- //*p1++ = *p2++ = (i % 2) == 0 ? q : ~q;
- }
- print("\b\b\b\b\b\b\b\b\b\b\b");
- print("testing ");
- print_Dec_3(j);
- if (compare_regions_reverse(bufa, bufb, count)) {
- return -1;
- }
- }
- print("\b\b\b\b\b\b\b\b\b\b\b \b\b\b\b\b\b\b\b\b\b\b");
- return 0;
-}
-#endif
-
-#ifdef TEST_CHECK_BOARD
-static int test_checkerboard_comparison(ulv *bufa, ulv *bufb, size_t count) {
- ulv *p1 = bufa;
- ulv *p2 = bufb;
- unsigned int j;
- ul q;
- size_t i;
- ul value;
-
- print(" ");
- for (j = 0; j < 64; j++) {
- print("\b\b\b\b\b\b\b\b\b\b\b");
- q = (j % 2) == 0 ? CHECKERBOARD1 : CHECKERBOARD2;
- print("setting ");
- print_Dec_3(j);
- p1 = (ulv *) bufa;
- p2 = (ulv *) bufb;
- for (i = 0; i < count; i++) {
- value = (i % 2) == 0 ? q : ~q;
- *p1++ = value;
- *p2++ = ~value;
- //*p1++ = *p2++ = (i % 2) == 0 ? q : ~q;
- }
- print("\b\b\b\b\b\b\b\b\b\b\b");
- print("testing ");
- print_Dec_3(j);
- if (compare_regions_reverse(bufa, bufb, count)) {
- return -1;
- }
- }
- print("\b\b\b\b\b\b\b\b\b\b\b \b\b\b\b\b\b\b\b\b\b\b");
- return 0;
-}
-#endif
-
-#ifdef TEST_BLOCK_SEQ
-static int test_blockseq_comparison(ulv *bufa, ulv *bufb, size_t count) {
- ulv *p1 = bufa;
- ulv *p2 = bufb;
- unsigned int j;
- size_t i;
- ul value;
-
- print(" ");
- for (j = 0; j < 256; j++) {
- print("\b\b\b\b\b\b\b\b\b\b\b");
- p1 = (ulv *) bufa;
- p2 = (ulv *) bufb;
- print("setting ");
- print_Dec_3(j);
- for (i = 0; i < count; i++) {
- value = (ul) UL_BYTE(j);
- *p1++ = value;
- *p2++ = ~value;
- //*p1++ = *p2++ = (ul) UL_BYTE(j);
- }
- print("\b\b\b\b\b\b\b\b\b\b\b");
- print("testing ");
- print_Dec_3(j);
- if (compare_regions_reverse(bufa, bufb, count)) {
- return -1;
- }
- }
- print("\b\b\b\b\b\b\b\b\b\b\b \b\b\b\b\b\b\b\b\b\b\b");
- return 0;
-}
-#endif
-
-#ifdef TEST_ZERO
-static int test_walkbits0_comparison(ulv *bufa, ulv *bufb, size_t count) {
- ulv *p1 = bufa;
- ulv *p2 = bufb;
- unsigned int j;
- size_t i;
- ul value;
-
- print(" ");
- for (j = 0; j < UL_LEN * 2; j++) {
- print("\b\b\b\b\b\b\b\b\b\b\b");
- p1 = (ulv *) bufa;
- p2 = (ulv *) bufb;
- print("setting ");
- print_Dec_3(j);
- for (i = 0; i < count; i++) {
- if (j < UL_LEN) { /* Walk it up. */
- //*p1++ = *p2++ = ONE << j;
- value = ONE << j;
- *p1++ = value;
- *p2++ = ~value;
- } else { /* Walk it back down. */
- //*p1++ = *p2++ = ONE << (UL_LEN * 2 - j - 1);
- value = ONE << (UL_LEN * 2 - j - 1);
- *p1++ = value;
- *p2++ = ~value;
- }
- }
- print("\b\b\b\b\b\b\b\b\b\b\b");
- print("testing ");
- print_Dec_3(j);
- if (compare_regions_reverse(bufa, bufb, count)) {
- return -1;
- }
- }
- print("\b\b\b\b\b\b\b\b\b\b\b \b\b\b\b\b\b\b\b\b\b\b");
- return 0;
-}
-#endif
-
-#ifdef TEST_ONE
-static int test_walkbits1_comparison(ulv *bufa, ulv *bufb, size_t count) {
- ulv *p1 = bufa;
- ulv *p2 = bufb;
- unsigned int j;
- size_t i;
- ul value;
-
- print(" ");
- for (j = 0; j < UL_LEN * 2; j++) {
- print("\b\b\b\b\b\b\b\b\b\b\b");
- p1 = (ulv *) bufa;
- p2 = (ulv *) bufb;
- print("setting ");
- print_Dec_3(j);
- for (i = 0; i < count; i++) {
- if (j < UL_LEN) { /* Walk it up. */
- //*p1++ = *p2++ = UL_ONEBITS ^ (ONE << j);
- value = UL_ONEBITS ^ (ONE << j);
- *p1++ = value;
- *p2++ = ~value;
- } else { /* Walk it back down. */
- //*p1++ = *p2++ = UL_ONEBITS ^ (ONE << (UL_LEN * 2 - j - 1));
- value = UL_ONEBITS ^ (ONE << (UL_LEN * 2 - j - 1));
- *p1++ = value;
- *p2++ = ~value;
- }
- }
- print("\b\b\b\b\b\b\b\b\b\b\b");
- print("testing ");
- print_Dec_3(j);
- if (compare_regions_reverse(bufa, bufb, count)) {
- return -1;
- }
- }
- print("\b\b\b\b\b\b\b\b\b\b\b \b\b\b\b\b\b\b\b\b\b\b");
- return 0;
-}
-#endif
-
-#ifdef TEST_BIT_SPREAD
-static int test_bitspread_comparison(ulv *bufa, ulv *bufb, size_t count) {
- ulv *p1 = bufa;
- ulv *p2 = bufb;
- unsigned int j;
- size_t i;
- ul value;
-
- print(" ");
- for (j = 0; j < UL_LEN * 2; j++) {
- print("\b\b\b\b\b\b\b\b\b\b\b");
- p1 = (ulv *) bufa;
- p2 = (ulv *) bufb;
- print("setting ");
- print_Dec_3(j);
- for (i = 0; i < count; i++) {
- if (j < UL_LEN) { /* Walk it up. */
- //*p1++ = *p2++ = (i % 2 == 0)
- // ? (ONE << j) | (ONE << (j + 2))
- // : UL_ONEBITS ^ ((ONE << j)
- // | (ONE << (j + 2)));
- value = (i % 2 == 0)
- ? (ONE << j) | (ONE << (j + 2))
- : UL_ONEBITS ^ ((ONE << j)
- | (ONE << (j + 2)));
- *p1++ = value;
- *p2++ = ~value;
- } else { /* Walk it back down. */
- //*p1++ = *p2++ = (i % 2 == 0)
- // ? (ONE << (UL_LEN * 2 - 1 - j)) | (ONE << (UL_LEN * 2 + 1 - j))
- // : UL_ONEBITS ^ (ONE << (UL_LEN * 2 - 1 - j)
- // | (ONE << (UL_LEN * 2 + 1 - j)));
- value = (i % 2 == 0)
- ? (ONE << (UL_LEN * 2 - 1 - j)) | (ONE << (UL_LEN * 2 + 1 - j))
- : UL_ONEBITS ^ (ONE << (UL_LEN * 2 - 1 - j)
- | (ONE << (UL_LEN * 2 + 1 - j)));
- *p1++ = value;
- *p2++ = ~value;
- }
- }
- print("\b\b\b\b\b\b\b\b\b\b\b");
- print("testing ");
- print_Dec_3(j);
- if (compare_regions_reverse(bufa, bufb, count)) {
- return -1;
- }
- }
- print("\b\b\b\b\b\b\b\b\b\b\b \b\b\b\b\b\b\b\b\b\b\b");
- return 0;
-}
-#endif
-
-#ifdef TEST_BIT_FLIP
-static int test_bitflip_comparison(ulv *bufa, ulv *bufb, size_t count) {
- ulv *p1 = bufa;
- ulv *p2 = bufb;
- unsigned int j, k;
- ul q;
- size_t i;
- ul value;
-
- print(" ");
- for (k = 0; k < UL_LEN; k++) {
- q = ONE << k;
- for (j = 0; j < 8; j++) {
- print("\b\b\b\b\b\b\b\b\b\b\b");
- q = ~q;
- print("setting ");
- print_Dec_3(k * 8 + j);
- p1 = (ulv *) bufa;
- p2 = (ulv *) bufb;
- for (i = 0; i < count; i++) {
- //*p1++ = *p2++ = (i % 2) == 0 ? q : ~q;
- value = (i % 2) == 0 ? q : ~q;
- *p1++ = value;
- *p2++ = ~value;
- }
- print("\b\b\b\b\b\b\b\b\b\b\b");
- print("testing ");
- print_Dec_3(k * 8 + j);
- if (compare_regions_reverse(bufa, bufb, count)) {
- return -1;
- }
- }
- }
- print("\b\b\b\b\b\b\b\b\b\b\b \b\b\b\b\b\b\b\b\b\b\b");
- return 0;
-}
-#endif
-
-#ifdef TEST_NARROW_WRITES
-static int test_8bit_wide_random(ulv* bufa, ulv* bufb, size_t count) {
- u8v *p1, *t;
- ulv *p2;
- int attempt;
- unsigned int b, j = 0;
- size_t i;
-
- putchar(' ');
- fflush(stdout);
- for (attempt = 0; attempt < 2; attempt++) {
- if (attempt & 1) {
- p1 = (u8v *) bufa;
- p2 = bufb;
- } else {
- p1 = (u8v *) bufb;
- p2 = bufa;
- }
- for (i = 0; i < count; i++) {
- t = mword8.bytes;
- *p2++ = mword8.val = rand_ul();
- for (b=0; b < UL_LEN/8; b++) {
- *p1++ = *t++;
- }
- if (!(i % PROGRESSOFTEN)) {
- putchar('\b');
- putchar(progress[++j % PROGRESSLEN]);
- fflush(stdout);
- }
- }
- if (compare_regions(bufa, bufb, count)) {
- return -1;
- }
- }
- printf("\b \b");
- fflush(stdout);
- return 0;
-}
-
-static int test_16bit_wide_random(ulv* bufa, ulv* bufb, size_t count) {
- u16v *p1, *t;
- ulv *p2;
- int attempt;
- unsigned int b, j = 0;
- size_t i;
-
- putchar( ' ' );
- fflush( stdout );
- for (attempt = 0; attempt < 2; attempt++) {
- if (attempt & 1) {
- p1 = (u16v *) bufa;
- p2 = bufb;
- } else {
- p1 = (u16v *) bufb;
- p2 = bufa;
- }
- for (i = 0; i < count; i++) {
- t = mword16.u16s;
- *p2++ = mword16.val = rand_ul();
- for (b = 0; b < UL_LEN/16; b++) {
- *p1++ = *t++;
- }
- if (!(i % PROGRESSOFTEN)) {
- putchar('\b');
- putchar(progress[++j % PROGRESSLEN]);
- fflush(stdout);
- }
- }
- if (compare_regions(bufa, bufb, count)) {
- return -1;
- }
- }
- printf("\b \b");
- fflush(stdout);
- return 0;
-}
-#endif
-
-#define EXIT_FAIL_NONSTARTER 0x01
-#define EXIT_FAIL_ADDRESSLINES 0x02
-#define EXIT_FAIL_OTHERTEST 0x04
-
-static struct test tests[]
-= {
- #ifdef TEST_RANDOM
- { "Random Value", test_random_value },
- #endif
- #ifdef TEST_XOR
- { "Compare XOR", test_xor_comparison },
- #endif
- #ifdef TEST_SUB
- { "Compare SUB", test_sub_comparison },
- #endif
- #ifdef TEST_MUL
- { "Compare MUL", test_mul_comparison },
- #endif
- #ifdef TEST_DIV
- { "Compare DIV",test_div_comparison },
- #endif
- #ifdef TEST_OR
- { "Compare OR", test_or_comparison },
- #endif
- #ifdef TEST_AND
- { "Compare AND", test_and_comparison },
- #endif
- #ifdef TEST_SEQINC
- { "Sequential Increment", test_seqinc_comparison },
- #endif
- #ifdef TEST_SOLID_BIT
- { "Solid Bits", test_solidbits_comparison },
- #endif
- #ifdef TEST_BLOCK_SEQ
- { "Block Sequential", test_blockseq_comparison },
- #endif
- #ifdef TEST_CHECK_BOARD
- { "Checkerboard", test_checkerboard_comparison },
- #endif
- #ifdef TEST_BIT_SPREAD
- { "Bit Spread", test_bitspread_comparison },
- #endif
- #ifdef TEST_BIT_FLIP
- { "Bit Flip", test_bitflip_comparison },
- #endif
- #ifdef TEST_ONE
- { "Walking Ones", test_walkbits1_comparison },
- #endif
- #ifdef TEST_ZERO
- { "Walking Zeroes", test_walkbits0_comparison },
- #endif
-#ifdef TEST_NARROW_WRITES
- { "8-bit Writes", test_8bit_wide_random },
- { "16-bit Writes", test_16bit_wide_random },
-#endif
- { NULL, NULL }
-};
-
-static int exit_code = 0;
-static ul cap = 2*1024*1024;
-
-int memtester(void) {
- ul loops, loop, i;
- size_t pagesize, wantraw, wantmb, wantbytes, wantbytes_orig, bufsize,
- halflen, count;
- ptrdiff_t pagesizemask;
- void volatile *buf, *aligned;
- ulv *bufa, *bufb;
- int memshift;
-
- print("Copyright (C) 2010 Charles Cazabon.\n");
- print("Licensed under the GNU General Public License version 2 (only).\n");
- print("\n");
- pagesize = 1024;
- pagesizemask = (ptrdiff_t) ~(pagesize - 1);
- print("pagesizemask is 0x");
- print_Hex(pagesizemask);
- print("\n");
-
- wantraw = cap>>20;
- memshift = 20; /* megabytes */
-
- wantbytes_orig = wantbytes = ((size_t) wantraw << memshift);
- wantmb = (wantbytes_orig >> 20);
-
- loops = 10;
-
- print("want ");
- print_Dec((ull) wantmb);
- print("MB (");
- print_Dec((ull) wantbytes);
- print(" bytes)\n");
- buf = NULL;
-
- buf = (void volatile *) kmalloc(wantbytes, GFP_KERNEL);
- // buf = (void volatile *)0x60000000;
- bufsize = wantbytes;
- aligned = buf;
-
- halflen = bufsize / 2;
- count = halflen / sizeof(ul);
- bufa = (ulv *) aligned;
- bufb = (ulv *) ((size_t) aligned + halflen);
-
- for(loop=1; ((!loops) || loop <= loops); loop++) {
- print("Loop ");
- print_Dec(loop);
- //if (loops) {
- // print_Dec(loops);
- //}
- print(":\n");
- print(" Stuck Address: ");
- if (!test_stuck_address(aligned, bufsize / sizeof(ul))) {
- print("ok\n");
- } else {
- exit_code |= EXIT_FAIL_ADDRESSLINES;
- goto error;
- }
- for (i=0;;i++) {
- if (!tests[i].name) break;
- print(" ");
- print(tests[i].name);
- print(": ");
- if (!tests[i].fp(bufa, bufb, count)) {
- print("ok\n");
- } else {
- exit_code |= EXIT_FAIL_OTHERTEST;
- goto error;
- }
- }
- print("\n");
- }
- kfree((const void *)buf);
- print("Done.\n");
- return 0;
-error:
- print("failed\n");
- return 1;
-}
-
-#include <linux/module.h>
-static int set_cap(const char *val, const struct kernel_param *kp)
-{
- int ret;
-
- ret = param_set_ulong(val, kp);
- if (ret < 0)
- return ret;
-
- memtester();
-
- return 0;
-}
-
-static struct kernel_param_ops cap_param_ops = {
- .set = set_cap,
- .get = param_get_ulong,
-};
-
-module_param_cb(cap, &cap_param_ops, &cap, 0644);
+++ /dev/null
-#define pr_fmt(fmt) "pwm: " fmt
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/spinlock.h>
-#include <plat/pwm.h>
-#include <mach/io.h>
-
-static spinlock_t pwm_lock[4] = {
- __SPIN_LOCK_UNLOCKED(pwm_lock0),
- __SPIN_LOCK_UNLOCKED(pwm_lock1),
- __SPIN_LOCK_UNLOCKED(pwm_lock2),
- __SPIN_LOCK_UNLOCKED(pwm_lock3),
-};
-
-struct clk *rk_pwm_get_clk(unsigned id)
-{
-#if defined(CONFIG_ARCH_RK29)
- if (id < 4)
- return clk_get(NULL, "pwm");
-#elif defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK3188)
- if (id == 0 || id == 1)
- return clk_get(NULL, "pwm01");
- else if (id== 2 || id == 3)
- return clk_get(NULL, "pwm23");
-#elif defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK3026)
- if (id < 3)
- return clk_get(NULL, "pwm01");
-#endif
- pr_err("invalid pwm id %d\n", id);
- BUG();
- return ERR_PTR(-ENOENT);
-}
-EXPORT_SYMBOL(rk_pwm_get_clk);
-
-void __iomem *rk_pwm_get_base(unsigned id)
-{
-#if defined(CONFIG_ARCH_RK29)
- if (id < 4)
- return RK29_PWM_BASE + id * 0x10;
-#elif defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK3188)
- if (id == 0 || id == 1)
- return RK30_PWM01_BASE + id * 0x10;
- else if (id== 2 || id == 3)
- return RK30_PWM23_BASE + id * 0x10;
-#elif defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK3026)
- if (id < 3)
- return RK2928_PWM_BASE + id * 0x10;
-#endif
- pr_err("invalid pwm id %d\n", id);
- BUG();
- return 0;
-}
-EXPORT_SYMBOL(rk_pwm_get_base);
-
-void rk_pwm_setup(unsigned id, enum pwm_div div, u32 hrc, u32 lrc)
-{
- unsigned long flags;
- spinlock_t *lock;
- const void __iomem *base = rk_pwm_get_base(id);
-
- if (hrc > lrc) {
- pr_err("invalid hrc %d lrc %d\n", hrc, lrc);
- return;
- }
-
- lock = &pwm_lock[id];
- spin_lock_irqsave(lock, flags);
- __rk_pwm_setup(base, div, hrc, lrc);
- spin_unlock_irqrestore(lock, flags);
-}
-EXPORT_SYMBOL(rk_pwm_setup);
+++ /dev/null
-#if 1
-#define CONFIG_ERR(v, name) do { printk("%s: Invalid parameter: %s(%d)\n", __func__, (name), (v)); } while(0)
-#else
-#define CONFIG_ERR(v, name)
-#endif
-#include <plat/config.h>
-
-
-/* keyboard */
-uint key_adc = DEF_KEY_ADC;
-module_param(key_adc, uint, 0644);
-uint key_val_size = 6;
-uint key_val[] = {DEF_PLAY_KEY, DEF_VOLDN_KEY, DEF_VOLUP_KEY, DEF_MENU_KEY, DEF_ESC_KEY, DEF_HOME_KEY};
-module_param_array(key_val, uint, &key_val_size, 0644);
-static inline int check_key_param(void)
-{
- return 0;
-}
-
-/* backlight */
-static int bl_en = DEF_BL_EN;
-module_param(bl_en, int, 0644);
-static uint bl_pwmid = DEF_BL_PWMID;
-module_param(bl_pwmid, uint, 0644);
-
-static uint bl_pwm_mode =DEF_BL_PWM_MOD;
-
-static uint bl_mode = DEF_BL_MOD;
-module_param(bl_mode, uint, 0644);
-static uint bl_div = DEF_BL_DIV;
-module_param(bl_div, uint, 0644);
-static uint bl_ref = DEF_BL_REF;
-module_param(bl_ref, uint, 0644);
-static uint bl_min = DEF_BL_MIN;
-module_param(bl_min, uint, 0644);
-static uint bl_max = DEF_BL_MAX;
-module_param(bl_max, uint, 0644);
-
-static inline int check_bl_param(void){
- if(bl_pwmid < 0 || bl_pwmid > 3){
- CONFIG_ERR(bl_pwmid, "bl_pwm");
- return -EINVAL;
- }
- if(bl_ref != 0 && bl_ref != 1){
- CONFIG_ERR(bl_ref, "bl_ref");
- return -EINVAL;
- }
- if(bl_min < 0||bl_min > 255){
- CONFIG_ERR(bl_min, "bl_min");
- return -EINVAL;
- }
- if(bl_max < 0||bl_max > 255){
- CONFIG_ERR(bl_max, "bl_max");
- return -EINVAL;
- }
-
- return 0;
-}
-
-/* lcd */
-static int lcd_cs = DEF_LCD_CS;
-module_param(lcd_cs, int, 0644);
-static int lcd_en = DEF_LCD_EN;
-module_param(lcd_en, int, 0644);
-static int lcd_std = DEF_LCD_STD;
-module_param(lcd_std, int, 0644);
-
-static inline int check_lcd_param(void)
-{
- return 0;
-}
-uint lcd_param[LCD_PARAM_MAX] = DEF_LCD_PARAM;
-module_param_array(lcd_param, uint, NULL, 0644);
-
-
-/*codec*/
-int codec_type = DEF_CODEC_TYPE;
-module_param(codec_type, int, 0644);
-int codec_power = DEF_CODEC_POWER;
-module_param(codec_power, int, 0644);
-int codec_rst = DEF_CODEC_RST;
-module_param(codec_rst, int, 0644);
-int codec_hdmi_irq = DEF_CODEC_HDMI_IRQ;
-module_param(codec_hdmi_irq, int, 0644);
-static int spk_ctl = DEF_SPK_CTL;
-module_param(spk_ctl, int, 0644);
-static int hp_det = DEF_HP_DET;
-module_param(hp_det, int, 0644);
-static int codec_i2c = DEF_CODEC_I2C; // i2c channel
-module_param(codec_i2c, int, 0644);
-static int codec_addr = DEF_CODEC_ADDR; // i2c addr
-module_param(codec_addr, int, 0644);
-static inline int check_codec_param(void)
-{
- return 0;
-}
-
-/*tp*/
-static int tp_type = DEF_TP_TYPE;
-module_param(tp_type, int, 0644);
-static int tp_irq = DEF_TP_IRQ;
-module_param(tp_irq, int, 0644);
-static int tp_rst =DEF_TP_RST;
-module_param(tp_rst, int, 0644);
-static int tp_i2c = DEF_TP_I2C; // i2c channel
-module_param(tp_i2c, int, 0644);
-static int tp_addr = DEF_TP_ADDR; // i2c addr
-module_param(tp_addr, int, 0644);
-static int tp_xmax = DEF_X_MAX;
-module_param(tp_xmax, int, 0644);
-static int tp_ymax = DEF_Y_MAX;
-module_param(tp_ymax, int, 0644);
-static int tp_firmVer= DEF_FIRMVER;
-module_param(tp_firmVer, int, 0644);
-static inline int check_tp_param(void)
-{
- if(tp_type == TP_TYPE_NONE)
- return 0;
- if(tp_type < TP_TYPE_NONE || tp_type > TP_TYPE_MAX){
- CONFIG_ERR(tp_type, "tp_type");
- return -EINVAL;
- }
- if(tp_i2c < 0 || tp_i2c > 3){
- CONFIG_ERR(tp_i2c, "tp_i2c");
- return -EINVAL;
- }
- if(tp_addr < 0 || tp_addr > 0x7f){
- CONFIG_ERR(tp_addr, "tp_addr");
- return -EINVAL;
- }
-
- if(tp_xmax < 0 || tp_xmax >1920){
- CONFIG_ERR(tp_xmax, "tp_xmax");
- return -EINVAL;
- }
-
- if(tp_ymax < 0 || tp_ymax >1920){
- CONFIG_ERR(tp_ymax, "tp_ymax");
- return -EINVAL;
- }
-
- return 0;
-}
-
-/* gsensor */
-static int gs_type = DEF_GS_TYPE;
-module_param(gs_type, int, 0644);
-static int gs_irq = DEF_GS_IRQ;
-module_param(gs_irq, int, 0644);
-static int gs_i2c = DEF_GS_I2C;
-module_param(gs_i2c, int, 0644);
-static int gs_addr = DEF_GS_ADDR;
-module_param(gs_addr, int, 0644);
-static int gs_orig[9] = DEF_GS_ORIG;
-module_param_array(gs_orig, int, NULL, 0644);
-static inline int check_gs_param(void)
-{
- int i;
- if(gs_type == GS_TYPE_NONE)
- return 0;
- if(gs_type < GS_TYPE_NONE || gs_type > GS_TYPE_MAX){
- CONFIG_ERR(gs_type, "gs_type");
- return -EINVAL;
- }
- if(gs_i2c < 0 || gs_i2c > 3){
- CONFIG_ERR(gs_i2c, "gs_i2c");
- return -EINVAL;
- }
- if(gs_addr < 0 || gs_addr > 0x7f){
- CONFIG_ERR(gs_i2c, "gs_addr");
- return -EINVAL;
- }
- for(i = 0; i < 9; i++){
- if(gs_orig[i] != 1 && gs_orig[i] != 0 && gs_orig[i] != -1)
- {
- CONFIG_ERR(gs_orig[i], "gs_orig[x]");
- return -EINVAL;
- }
- }
- return 0;
-}
-
-/* charge */
-static int dc_det = DEF_DC_DET;
-module_param(dc_det, int, 0644);
-static int bat_low = DEF_BAT_LOW;
-module_param(bat_low, int, 0644);
-static int chg_ok = DEF_CHG_OK;
-module_param(chg_ok, int, 0644);
-static int chg_set = DEF_CHG_SET;
-module_param(chg_set, int, 0644);
-static int usb_det = DEF_USB_DET;
-module_param(usb_det, int, 0644);
-static int ref_vol = DEF_REF_VOL;
-module_param(ref_vol, int, 0644);
-static int up_res = DEF_UP_RES;
-module_param(up_res, int, 0644);
-static int down_res = DEF_DOWN_RES;
-module_param(down_res, int, 0644);
-static int root_chg = DEF_ROOT_CHG;
-module_param(root_chg, int, 0644);
-static int save_cap = DEF_SAVE_CAP;
-module_param(save_cap, int, 0644);
-static int low_vol = DEF_LOW_VOL;
-module_param(low_vol, int, 0644);
-int bat_charge[11] = DEF_BAT_CHARGE;
-module_param_array(bat_charge, int, NULL, 0644);
-int bat_discharge[11] = DEF_BAT_DISCHARGE;
-module_param_array(bat_discharge, int, NULL, 0644);
-static inline int check_chg_param(void)
-{
- return 0;
-}
-
-/*wifi*/
-int wifi_type = DEF_WIFI_TYPE;
-module_param(wifi_type, int, 0644);
-int wifi_pwr = DEF_WIFI_POWER;
-module_param(wifi_pwr, int, 0644);
-static inline int check_wifi_param(void)
-{
- return 0;
-}
-
-/* global */
-static int pwr_on = DEF_PWR_ON;
-module_param(pwr_on, int, 0644);
-static inline int rk_power_on(void)
-{
- int ret;
- ret=port_output_init(pwr_on, 1, "pwr_on");
- if(ret<0)
- CONFIG_ERR(pwr_on, "pwr_on");
-
- port_output_on(pwr_on);
-
- return 0;
-}
-
+++ /dev/null
-/***************************************************************************************************
- * arch/arm/palt-rk/rk-sdmmc-ops.c
- *
- * Copyright (C) 2013 ROCKCHIP, Inc.
- *
- * Description: define the gpio for SDMMC module on various platforms
- *
- * Author: Michael Xie
- * E-mail: xbw@rock-chips.com
- *
- * History:
- * ver1.0 Unified function interface for new imoux-API, created at 2013-01-15
- * ver1.1 add drive strength control and the setting of IO-voltage, created at 2013-01-29
- *
- **************************************************************************************************/
-
-//use the new iomux-API
-#if 1//defined(CONFIG_ARCH_RK3066B)||defined(CONFIG_ARCH_RK3168)||defined(CONFIG_ARCH_RK3188)
-#define SDMMC_USE_NEW_IOMUX_API 1
-#else
-#define SDMMC_USE_NEW_IOMUX_API 0
-#endif
-
-//define IO volatga
-#if defined(CONFIG_ARCH_RK3066B)||defined(CONFIG_ARCH_RK3168)||defined(CONFIG_ARCH_RK3188)
-#define SDMMC_SET_IO_VOLTAGE 1
-#else
-#define SDMMC_SET_IO_VOLTAGE 0
-#endif
-
-#if SDMMC_SET_IO_VOLTAGE
-//GRF_IO_CON2 0x0FC
-#define SDMMC0_DRIVER_STRENGTH_2MA (0x00 << 6)
-#define SDMMC0_DRIVER_STRENGTH_4MA (0x01 << 6)
-#define SDMMC0_DRIVER_STRENGTH_8MA (0x02 << 6)
-#define SDMMC0_DRIVER_STRENGTH_12MA (0x03 << 6)
-#define SDMMC0_DRIVER_STRENGTH_MASK (0x03 << 22)
-
-//GRF_IO_CON3 0x100
-#define SDMMC1_DRIVER_STRENGTH_2MA (0x00 << 2)
-#define SDMMC1_DRIVER_STRENGTH_4MA (0x01 << 2)
-#define SDMMC1_DRIVER_STRENGTH_8MA (0x02 << 2)
-#define SDMMC1_DRIVER_STRENGTH_12MA (0x03 << 2)
-#define SDMMC1_DRIVER_STRENGTH_MASK (0x03 << 18)
-
-//GRF_IO_CON4 0x104
-#define SDMMC0_IO_VOLTAGE_33 (0x00 << 12)
-#define SDMMC0_IO_VOLTAGE_18 (0x01 << 12)
-#define SDMMC0_IO_VOLTAGE_MASK (0x01 << 28)
-
-#define SDMMC1_IO_VOLTAGE_33 (0x00 << 8)
-#define SDMMC1_IO_VOLTAGE_18 (0x01 << 8)
-#define SDMMC1_IO_VOLTAGE_MASK (0x01 << 24)
-
-#define SDMMC_write_grf_reg(addr, val) __raw_writel(val, addr+RK30_GRF_BASE)
-#define SDMMC_read_grf_reg(addr) __raw_readl(addr+RK30_GRF_BASE)
-#define SDMMC_mask_grf_reg(addr, msk, val) write_grf_reg(addr,(val)|((~(msk))&read_grf_reg(addr)))
-#else
-#define SDMMC_write_grf_reg(addr, val)
-#define SDMMC_read_grf_reg(addr)
-#define SDMMC_mask_grf_reg(addr, msk, val)
-#endif
-
-int rk31sdk_wifi_voltage_select(void)
-{
- int voltage;
- int voltage_flag = 0;
-
- voltage = rk31sdk_get_sdio_wifi_voltage();
-
- if(voltage >= 2700)
- voltage_flag = 0;
- else if(voltage <= 2000)
- voltage_flag = 1;
- else
- voltage_flag = 1;
-
- return voltage_flag;
-}
-
-
-#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
-/*
-* define the gpio for sdmmc0
-*/
-static struct rksdmmc_gpio_board rksdmmc0_gpio_init = {
-
- .clk_gpio = {
- .io = RK30_PIN3_PA2,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mmc0_clkout",
- .fgpio = GPIO3_A2,
- .fmux = MMC0_CLKOUT,
- },
- },
-
- .cmd_gpio = {
- .io = RK30_PIN3_PA3,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mmc0_cmd",
- .fgpio = GPIO3_A3,
- .fmux = MMC0_CMD,
- },
- },
-
- .data0_gpio = {
- .io = RK30_PIN3_PA4,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mmc0_d0",
- .fgpio = GPIO3_A4,
- .fmux = MMC0_D0,
- },
- },
-
- .data1_gpio = {
- .io = RK30_PIN3_PA5,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mmc0_d1",
- .fgpio = GPIO3_A5,
- .fmux = MMC0_D1,
- },
- },
-
- .data2_gpio = {
- .io = RK30_PIN3_PA6,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mmc0_d2",
- .fgpio = GPIO3_A6,
- .fmux = MMC0_D2,
- },
- },
-
- .data3_gpio = {
- .io = RK30_PIN3_PA7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mmc0_d3",
- .fgpio = GPIO3_A7,
- .fmux = MMC0_D3,
- },
- },
-
-
- .power_en_gpio = {
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .io = RK29SDK_SD_CARD_PWR_EN,
- .enable = RK29SDK_SD_CARD_PWR_EN_LEVEL,
- #ifdef RK29SDK_SD_CARD_PWR_EN_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_PWR_EN_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_PWR_EN_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_PWR_EN_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_PWR_EN_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_PWR_EN_IOMUX_FMUX,
- #endif
- },
- #endif
-#else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-
- .detect_irq = {
-#if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
-#else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-
-};
-
-
-/*
-* define the gpio for sdmmc1
-*/
-static struct rksdmmc_gpio_board rksdmmc1_gpio_init = {
-
- .clk_gpio = {
- .io = RK30_PIN3_PC5,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mmc1_clkout",
- .fgpio = GPIO3_C5,
- .fmux = MMC1_CLKOUT,
- },
- },
-
- .cmd_gpio = {
- .io = RK30_PIN3_PC0,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mmc1_cmd",
- .fgpio = GPIO3_C0,
- .fmux = MMC1_CMD,
- },
- },
-
- .data0_gpio = {
- .io = RK30_PIN3_PC1,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mmc1_d0",
- .fgpio = GPIO3_C1,
- .fmux = MMC1_D0,
- },
- },
-
- .data1_gpio = {
- .io = RK30_PIN3_PC2,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mmc1_d1",
- .fgpio = GPIO3_C2,
- .fmux = MMC1_D1,
- },
- },
-
- .data2_gpio = {
- .io = RK30_PIN3_PC3,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mmc1_d2",
- .fgpio = GPIO3_C3,
- .fmux = MMC1_D2,
- },
- },
-
- .data3_gpio = {
- .io = RK30_PIN3_PC4,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mmc1_d3",
- .fgpio = GPIO3_C4,
- .fmux = MMC1_D3,
- },
- },
-};
-// ---end -#if defined(CONFIG_ARCH_RK3066B)
-
-#elif defined(CONFIG_ARCH_RK2928)
-/*
-* define the gpio for sdmmc0
-*/
-static struct rksdmmc_gpio_board rksdmmc0_gpio_init = {
-
- .clk_gpio = {
- .io = RK2928_PIN1_PC0,
- .enable = GPIO_HIGH,
- .iomux = {
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- .name = GPIO1C0_MMC0_CLKOUT_NAME,
- .fgpio = GPIO1C_GPIO1C0,
- .fmux = GPIO1C_MMC0_CLKOUT,
- #endif
- },
- },
-
- .cmd_gpio = {
- .io = RK2928_PIN1_PC7,
- .enable = GPIO_HIGH,
- .iomux = {
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- .name = GPIO1B7_MMC0_CMD_NAME,
- .fgpio = GPIO1B_GPIO1B7,
- .fmux = GPIO1B_MMC0_CMD,
- #endif
- },
- },
-
- .data0_gpio = {
- .io = RK2928_PIN1_PC2,
- .enable = GPIO_HIGH,
- .iomux = {
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- .name = GPIO1C2_MMC0_D0_NAME,
- .fgpio = GPIO1C_GPIO1C2,
- .fmux = GPIO1C_MMC0_D0,
- #endif
- },
- },
-
- .data1_gpio = {
- .io = RK2928_PIN1_PC3,
- .enable = GPIO_HIGH,
- .iomux = {
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- .name = GPIO1C3_MMC0_D1_NAME,
- .fgpio = GPIO1C_GPIO1C3,
- .fmux = GPIO1C_MMC0_D1,
- #endif
- },
- },
-
- .data2_gpio = {
- .io = RK2928_PIN1_PC4,
- .enable = GPIO_HIGH,
- .iomux = {
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- .name = GPIO1C4_MMC0_D2_NAME,
- .fgpio = GPIO1C_GPIO1C4,
- .fmux = GPIO1C_MMC0_D2,
- #endif
- },
- },
-
- .data3_gpio = {
- .io = RK2928_PIN1_PC5,
- .enable = GPIO_HIGH,
- .iomux = {
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- .name = GPIO1C5_MMC0_D3_NAME,
- .fgpio = GPIO1C_GPIO1C5,
- .fmux = GPIO1C_MMC0_D3,
- #endif
- },
- },
-
-
- .power_en_gpio = {
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .io = RK29SDK_SD_CARD_PWR_EN,
- .enable = RK29SDK_SD_CARD_PWR_EN_LEVEL,
- #ifdef RK29SDK_SD_CARD_PWR_EN_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_PWR_EN_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_PWR_EN_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_PWR_EN_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_PWR_EN_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_PWR_EN_IOMUX_FMUX,
- #endif
- },
- #endif
-#else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-
- .detect_irq = {
-#if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
-#else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-};
-
-
-/*
-* define the gpio for sdmmc1
-*/
-static struct rksdmmc_gpio_board rksdmmc1_gpio_init = {
-
- .clk_gpio = {
- .io = RK2928_PIN0_PB1,
- .enable = GPIO_HIGH,
- .iomux = {
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- .name = GPIO0B1_MMC1_CLKOUT_NAME,
- .fgpio = GPIO0B_GPIO0B1,
- .fmux = GPIO0B_MMC1_CLKOUT,
- #endif
- },
- },
-
- .cmd_gpio = {
- .io = RK2928_PIN0_PB0,
- .enable = GPIO_HIGH,
- .iomux = {
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- .name = GPIO0B0_MMC1_CMD_NAME,
- .fgpio = GPIO0B_GPIO0B0,
- .fmux = GPIO0B_MMC1_CMD,
- #endif
- },
- },
-
- .data0_gpio = {
- .io = RK2928_PIN0_PB3,
- .enable = GPIO_HIGH,
- .iomux = {
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- .name = GPIO0B3_MMC1_D0_NAME,
- .fgpio = GPIO0B_GPIO0B3,
- .fmux = GPIO0B_MMC1_D0,
- #endif
- },
- },
-
- .data1_gpio = {
- .io = RK2928_PIN0_PB4,
- .enable = GPIO_HIGH,
- .iomux = {
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- .name = GPIO0B4_MMC1_D1_NAME,
- .fgpio = GPIO0B_GPIO0B4,
- .fmux = GPIO0B_MMC1_D1,
- #endif
- },
- },
-
- .data2_gpio = {
- .io = RK2928_PIN0_PB5,
- .enable = GPIO_HIGH,
- .iomux = {
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- .name = GPIO0B5_MMC1_D2_NAME,
- .fgpio = GPIO0B_GPIO0B5,
- .fmux = GPIO0B_MMC1_D2,
- #endif
- },
- },
-
- .data3_gpio = {
- .io = RK2928_PIN0_PB6,
- .enable = GPIO_HIGH,
- .iomux = {
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- .name = GPIO0B6_MMC1_D3_NAME,
- .fgpio = GPIO0B_GPIO0B6,
- .fmux = GPIO0B_MMC1_D3,
- #endif
- },
- },
-
-
-};
-// ---end -#if defined(CONFIG_ARCH_RK2928)
-#elif defined(CONFIG_ARCH_RK3026)
-/*
-* define the gpio for sdmmc0
-*/
-static struct rksdmmc_gpio_board rksdmmc0_gpio_init = {
-
- .clk_gpio = {
- .io = RK30_PIN1_PC0,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mmc0_clk",
- .fgpio = GPIO1_C0,
- .fmux = MMC0_CLKOUT,
- },
- },
-
- .cmd_gpio = {
- .io = RK30_PIN1_PB7,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mmc0_cmd",
- .fgpio = GPIO1_B7,
- .fmux = MMC0_CMD,
- },
- },
-
- .data0_gpio = {
- .io = RK30_PIN1_PC2,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mmc0_d0",
- .fgpio = GPIO1_C2,
- .fmux = MMC0_D0,
- },
- },
-
- .data1_gpio = {
- .io = RK30_PIN1_PC3,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mmc0_d1",
- .fgpio = GPIO1_C3,
- .fmux = MMC0_D1,
- },
- },
-
- .data2_gpio = {
- .io = RK30_PIN1_PC4,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mmc0_d2",
- .fgpio = GPIO1_C4,
- .fmux = MMC0_D2,
- },
- },
-
- .data3_gpio = {
- .io = RK30_PIN1_PC5,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mmc0_d3",
- .fgpio = GPIO1_C5,
- .fmux = MMC0_D3,
- },
- },
-
-
- .power_en_gpio = {
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .io = RK29SDK_SD_CARD_PWR_EN,
- .enable = RK29SDK_SD_CARD_PWR_EN_LEVEL,
- #ifdef RK29SDK_SD_CARD_PWR_EN_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_PWR_EN_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_PWR_EN_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_PWR_EN_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_PWR_EN_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_PWR_EN_IOMUX_FMUX,
- #endif
- },
- #endif
-#else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-
- .detect_irq = {
-#if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
-#else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-};
-
-
-/*
-* define the gpio for sdmmc1
-*/
-static struct rksdmmc_gpio_board rksdmmc1_gpio_init = {
-
- .clk_gpio = {
- .io = RK30_PIN0_PB1,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mmc1_clk",
- .fgpio = GPIO0_B1,
- .fmux = MMC1_CLKOUT,
- },
- },
-
- .cmd_gpio = {
- .io = RK30_PIN0_PB0,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mmc1_cmd",
- .fgpio = GPIO0_B0,
- .fmux = MMC1_CMD,
- },
- },
-
- .data0_gpio = {
- .io = RK30_PIN0_PB3,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mmc1_d0",
- .fgpio = GPIO0_B3,
- .fmux = MMC1_D0,
- },
- },
-
- .data1_gpio = {
- .io = RK30_PIN0_PB4,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mmc1_d1",
- .fgpio = GPIO0_B4,
- .fmux = MMC1_D1,
- },
- },
-
- .data2_gpio = {
- .io = RK30_PIN0_PB5,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mmc1_d2",
- .fgpio = GPIO0_B5,
- .fmux = MMC1_D2,
- },
- },
-
- .data3_gpio = {
- .io = RK30_PIN0_PB6,
- .enable = GPIO_HIGH,
- .iomux = {
- .name = "mmc1_d3",
- .fgpio = GPIO0_B6,
- .fmux = MMC1_D3,
- },
- },
-
-
-};
-// ---end -#if defined(CONFIG_ARCH_RK3026)
-
-#else //default for RK30,RK3066 SDK
-/*
-* define the gpio for sdmmc0
-*/
-struct rksdmmc_gpio_board rksdmmc0_gpio_init = {
-
- .clk_gpio = {
- .io = RK30_PIN3_PB0,
- .enable = GPIO_HIGH,
- .iomux = {
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- .name = GPIO3B0_SDMMC0CLKOUT_NAME,
- .fgpio = GPIO3B_GPIO3B0,
- .fmux = GPIO3B_SDMMC0_CLKOUT,
- #endif
- },
- },
-
- .cmd_gpio = {
- .io = RK30_PIN3_PB1,
- .enable = GPIO_HIGH,
- .iomux = {
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- .name = GPIO3B1_SDMMC0CMD_NAME,
- .fgpio = GPIO3B_GPIO3B1,
- .fmux = GPIO3B_SDMMC0_CMD,
- #endif
- },
- },
-
- .data0_gpio = {
- .io = RK30_PIN3_PB2,
- .enable = GPIO_HIGH,
- .iomux = {
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- .name = GPIO3B2_SDMMC0DATA0_NAME,
- .fgpio = GPIO3B_GPIO3B2,
- .fmux = GPIO3B_SDMMC0_DATA0,
- #endif
- },
- },
-
- .data1_gpio = {
- .io = RK30_PIN3_PB3,
- .enable = GPIO_HIGH,
- .iomux = {
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- .name = GPIO3B3_SDMMC0DATA1_NAME,
- .fgpio = GPIO3B_GPIO3B3,
- .fmux = GPIO3B_SDMMC0_DATA1,
- #endif
- },
- },
-
- .data2_gpio = {
- .io = RK30_PIN3_PB4,
- .enable = GPIO_HIGH,
- .iomux = {
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- .name = GPIO3B4_SDMMC0DATA2_NAME,
- .fgpio = GPIO3B_GPIO3B4,
- .fmux = GPIO3B_SDMMC0_DATA2,
- #endif
- },
- },
-
- .data3_gpio = {
- .io = RK30_PIN3_PB5,
- .enable = GPIO_HIGH,
- .iomux = {
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- .name = GPIO3B5_SDMMC0DATA3_NAME,
- .fgpio = GPIO3B_GPIO3B5,
- .fmux = GPIO3B_SDMMC0_DATA3,
- #endif
- },
- },
-
- .power_en_gpio = {
-#if defined(RK29SDK_SD_CARD_PWR_EN) || (INVALID_GPIO != RK29SDK_SD_CARD_PWR_EN)
- .io = RK29SDK_SD_CARD_PWR_EN,
- .enable = RK29SDK_SD_CARD_PWR_EN_LEVEL,
- #ifdef RK29SDK_SD_CARD_PWR_EN_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_PWR_EN_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_PWR_EN_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_PWR_EN_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_PWR_EN_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_PWR_EN_IOMUX_FMUX,
- #endif
- },
- #endif
-#else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-
- .detect_irq = {
-#if defined(RK29SDK_SD_CARD_DETECT_N) || (INVALID_GPIO != RK29SDK_SD_CARD_DETECT_N)
- .io = RK29SDK_SD_CARD_DETECT_N,
- .enable = RK29SDK_SD_CARD_INSERT_LEVEL,
- #ifdef RK29SDK_SD_CARD_DETECT_PIN_NAME
- .iomux = {
- .name = RK29SDK_SD_CARD_DETECT_PIN_NAME,
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO
- .fgpio = RK29SDK_SD_CARD_DETECT_IOMUX_FGPIO,
- #endif
- #ifdef RK29SDK_SD_CARD_DETECT_IOMUX_FMUX
- .fmux = RK29SDK_SD_CARD_DETECT_IOMUX_FMUX,
- #endif
- },
- #endif
-#else
- .io = INVALID_GPIO,
- .enable = GPIO_LOW,
-#endif
- },
-};
-
-
-/*
-* define the gpio for sdmmc1
-*/
-static struct rksdmmc_gpio_board rksdmmc1_gpio_init = {
-
- .clk_gpio = {
- .io = RK30_PIN3_PC5,
- .enable = GPIO_HIGH,
- .iomux = {
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- .name = GPIO3C5_SDMMC1CLKOUT_NAME,
- .fgpio = GPIO3C_GPIO3C5,
- .fmux = GPIO3B_SDMMC0_CLKOUT,
- #endif
- },
- },
-
- .cmd_gpio = {
- .io = RK30_PIN3_PC0,
- .enable = GPIO_HIGH,
- .iomux = {
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- .name = GPIO3C0_SMMC1CMD_NAME,
- .fgpio = GPIO3C_GPIO3C0,
- .fmux = GPIO3B_SDMMC0_CMD,
- #endif
- },
- },
-
- .data0_gpio = {
- .io = RK30_PIN3_PC1,
- .enable = GPIO_HIGH,
- .iomux = {
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- .name = GPIO3C1_SDMMC1DATA0_NAME,
- .fgpio = GPIO3C_GPIO3C1,
- .fmux = GPIO3B_SDMMC0_DATA0,
- #endif
- },
- },
-
- .data1_gpio = {
- .io = RK30_PIN3_PC2,
- .enable = GPIO_HIGH,
- .iomux = {
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- .name = GPIO3C2_SDMMC1DATA1_NAME,
- .fgpio = GPIO3C_GPIO3C2,
- .fmux = GPIO3B_SDMMC0_DATA1,
- #endif
- },
- },
-
- .data2_gpio = {
- .io = RK30_PIN3_PC3,
- .enable = GPIO_HIGH,
- .iomux = {
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- .name = GPIO3C3_SDMMC1DATA2_NAME,
- .fgpio = GPIO3C_GPIO3C3,
- .fmux = GPIO3B_SDMMC0_DATA2,
- #endif
- },
- },
-
- .data3_gpio = {
- .io = RK30_PIN3_PC4,
- .enable = GPIO_HIGH,
- .iomux = {
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- .name = GPIO3C4_SDMMC1DATA3_NAME,
- .fgpio = GPIO3C_GPIO3C4,
- .fmux = GPIO3B_SDMMC0_DATA3,
- #endif
- },
- },
-};
- // ---end -defualt rk30sdk,rk3066sdk
-
-#endif
-
-
-
-//1.Part 3: The various operations of the SDMMC-SDIO module
-/*************************************************************************
-* define the varaious operations for SDMMC module
-* Generally only the author of SDMMC module will modify this section.
-*************************************************************************/
-#if !defined(CONFIG_SDMMC_RK29_OLD)
-//static void rk29_sdmmc_gpio_open(int device_id, int on)
-void rk29_sdmmc_gpio_open(int device_id, int on)
-{
- switch(device_id)
- {
- case 0://mmc0
- {
- #ifdef CONFIG_SDMMC0_RK29
- if(on)
- {
- gpio_direction_output(rksdmmc0_gpio_init.clk_gpio.io, GPIO_HIGH);//set mmc0-clk to high
- gpio_direction_output(rksdmmc0_gpio_init.cmd_gpio.io, GPIO_HIGH);// set mmc0-cmd to high.
- gpio_direction_output(rksdmmc0_gpio_init.data0_gpio.io,GPIO_HIGH);//set mmc0-data0 to high.
- gpio_direction_output(rksdmmc0_gpio_init.data1_gpio.io,GPIO_HIGH);//set mmc0-data1 to high.
- gpio_direction_output(rksdmmc0_gpio_init.data2_gpio.io,GPIO_HIGH);//set mmc0-data2 to high.
- gpio_direction_output(rksdmmc0_gpio_init.data3_gpio.io,GPIO_HIGH);//set mmc0-data3 to high.
-
- mdelay(30);
- }
- else
- {
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- rk30_mux_api_set(rksdmmc0_gpio_init.clk_gpio.iomux.name, rksdmmc0_gpio_init.clk_gpio.iomux.fgpio);
- #endif
- gpio_request(rksdmmc0_gpio_init.clk_gpio.io, "mmc0-clk");
- gpio_direction_output(rksdmmc0_gpio_init.clk_gpio.io,GPIO_LOW);//set mmc0-clk to low.
-
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- rk30_mux_api_set(rksdmmc0_gpio_init.cmd_gpio.iomux.name, rksdmmc0_gpio_init.cmd_gpio.iomux.fgpio);
- #endif
- gpio_request(rksdmmc0_gpio_init.cmd_gpio.io, "mmc0-cmd");
- gpio_direction_output(rksdmmc0_gpio_init.cmd_gpio.io,GPIO_LOW);//set mmc0-cmd to low.
-
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- rk30_mux_api_set(rksdmmc0_gpio_init.data0_gpio.iomux.name, rksdmmc0_gpio_init.data0_gpio.iomux.fgpio);
- #endif
- gpio_request(rksdmmc0_gpio_init.data0_gpio.io, "mmc0-data0");
- gpio_direction_output(rksdmmc0_gpio_init.data0_gpio.io,GPIO_LOW);//set mmc0-data0 to low.
-
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- rk30_mux_api_set(rksdmmc0_gpio_init.data1_gpio.iomux.name, rksdmmc0_gpio_init.data1_gpio.iomux.fgpio);
- #endif
- gpio_request(rksdmmc0_gpio_init.data1_gpio.io, "mmc0-data1");
- gpio_direction_output(rksdmmc0_gpio_init.data1_gpio.io,GPIO_LOW);//set mmc0-data1 to low.
-
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- rk30_mux_api_set(rksdmmc0_gpio_init.data2_gpio.iomux.name, rksdmmc0_gpio_init.data2_gpio.iomux.fgpio);
- #endif
- gpio_request(rksdmmc0_gpio_init.data2_gpio.io, "mmc0-data2");
- gpio_direction_output(rksdmmc0_gpio_init.data2_gpio.io,GPIO_LOW);//set mmc0-data2 to low.
-
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- rk30_mux_api_set(rksdmmc0_gpio_init.data3_gpio.iomux.name, rksdmmc0_gpio_init.data3_gpio.iomux.fgpio);
- #endif
- gpio_request(rksdmmc0_gpio_init.data3_gpio.io, "mmc0-data3");
- gpio_direction_output(rksdmmc0_gpio_init.data3_gpio.io,GPIO_LOW);//set mmc0-data3 to low.
-
- mdelay(30);
- }
- #endif
- }
- break;
-
- case 1://mmc1
- {
- #ifdef CONFIG_SDMMC1_RK29
- if(on)
- {
- gpio_direction_output(rksdmmc1_gpio_init.clk_gpio.io,GPIO_HIGH);//set mmc1-clk to high
- gpio_direction_output(rksdmmc1_gpio_init.cmd_gpio.io,GPIO_HIGH);//set mmc1-cmd to high.
- gpio_direction_output(rksdmmc1_gpio_init.data0_gpio.io,GPIO_HIGH);//set mmc1-data0 to high.
- gpio_direction_output(rksdmmc1_gpio_init.data1_gpio.io,GPIO_HIGH);//set mmc1-data1 to high.
- gpio_direction_output(rksdmmc1_gpio_init.data2_gpio.io,GPIO_HIGH);//set mmc1-data2 to high.
- gpio_direction_output(rksdmmc1_gpio_init.data3_gpio.io,GPIO_HIGH);//set mmc1-data3 to high.
- mdelay(100);
- }
- else
- {
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- rk30_mux_api_set(rksdmmc1_gpio_init.clk_gpio.iomux.name, rksdmmc1_gpio_init.clk_gpio.iomux.fgpio);
- #endif
- gpio_request(rksdmmc1_gpio_init.clk_gpio.io, "mmc1-clk");
- gpio_direction_output(rksdmmc1_gpio_init.clk_gpio.io,GPIO_LOW);//set mmc1-clk to low.
-
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- rk30_mux_api_set(rksdmmc1_gpio_init.cmd_gpio.iomux.name, rksdmmc1_gpio_init.cmd_gpio.iomux.fgpio);
- #endif
- gpio_request(rksdmmc1_gpio_init.cmd_gpio.io, "mmc1-cmd");
- gpio_direction_output(rksdmmc1_gpio_init.cmd_gpio.io,GPIO_LOW);//set mmc1-cmd to low.
-
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- rk30_mux_api_set(rksdmmc1_gpio_init.data0_gpio.iomux.name, rksdmmc1_gpio_init.data0_gpio.iomux.fgpio);
- #endif
- gpio_request(rksdmmc1_gpio_init.data0_gpio.io, "mmc1-data0");
- gpio_direction_output(rksdmmc1_gpio_init.data0_gpio.io,GPIO_LOW);//set mmc1-data0 to low.
-
- #if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) || defined(CONFIG_MT5931) || defined(CONFIG_MT5931_MT6622)
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- rk29_mux_api_set(rksdmmc1_gpio_init.data1_gpio.iomux.name, rksdmmc1_gpio_init.data1_gpio.iomux.fgpio);
- #endif
- gpio_request(rksdmmc1_gpio_init.data1_gpio.io, "mmc1-data1");
- gpio_direction_output(rksdmmc1_gpio_init.data1_gpio.io,GPIO_LOW);//set mmc1-data1 to low.
-
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- rk29_mux_api_set(rksdmmc1_gpio_init.data2_gpio.iomux.name, rksdmmc1_gpio_init.data2_gpio.iomux.fgpio);
- #endif
- gpio_request(rksdmmc1_gpio_init.data2_gpio.io, "mmc1-data2");
- gpio_direction_output(rksdmmc1_gpio_init.data2_gpio.io,GPIO_LOW);//set mmc1-data2 to low.
-
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- rk29_mux_api_set(rksdmmc1_gpio_init.data3_gpio.iomux.name, rksdmmc1_gpio_init.data3_gpio.iomux.fgpio);
- #endif
- gpio_request(rksdmmc1_gpio_init.data3_gpio.io, "mmc1-data3");
- gpio_direction_output(rksdmmc1_gpio_init.data3_gpio.io,GPIO_LOW);//set mmc1-data3 to low.
- #endif
- mdelay(100);
- }
- #endif
- }
- break;
-
- case 2: //mmc2
- break;
-
- default:
- break;
- }
-}
-
-static void rk29_sdmmc_set_iomux_mmc0(unsigned int bus_width)
-{
- switch (bus_width)
- {
-
- case 1://SDMMC_CTYPE_4BIT:
- {
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(rksdmmc0_gpio_init.data1_gpio.iomux.fmux);
- iomux_set(rksdmmc0_gpio_init.data2_gpio.iomux.fmux);
- iomux_set(rksdmmc0_gpio_init.data3_gpio.iomux.fmux);
- #else
- rk30_mux_api_set(rksdmmc0_gpio_init.data1_gpio.iomux.name, rksdmmc0_gpio_init.data1_gpio.iomux.fmux);
- rk30_mux_api_set(rksdmmc0_gpio_init.data2_gpio.iomux.name, rksdmmc0_gpio_init.data2_gpio.iomux.fmux);
- rk30_mux_api_set(rksdmmc0_gpio_init.data3_gpio.iomux.name, rksdmmc0_gpio_init.data3_gpio.iomux.fmux);
- #endif
- }
- break;
-
- case 0x10000://SDMMC_CTYPE_8BIT:
- break;
- case 0xFFFF: //gpio_reset
- {
- #if (!!SDMMC_USE_NEW_IOMUX_API) && !defined(CONFIG_SDMMC0_RK29_SDCARD_DET_FROM_GPIO)
- iomux_set(MMC0_DETN);
- #endif
-
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- rk30_mux_api_set(rksdmmc0_gpio_init.power_en_gpio.iomux.name, rksdmmc0_gpio_init.power_en_gpio.iomux.fgpio);
- #endif
- gpio_request(rksdmmc0_gpio_init.power_en_gpio.io,"sdmmc-power");
- gpio_direction_output(rksdmmc0_gpio_init.power_en_gpio.io, !(rksdmmc0_gpio_init.power_en_gpio.enable)); //power-off
-
- #if 0 //replace the power control into rk29_sdmmc_set_ios(); modifyed by xbw at 2012-08-12
- rk29_sdmmc_gpio_open(0, 0);
-
- gpio_direction_output(rksdmmc0_gpio_init.power_en_gpio.io, rksdmmc0_gpio_init.power_en_gpio.enable); //power-on
-
- rk29_sdmmc_gpio_open(0, 1);
- #endif
- }
- break;
-
- default: //case 0://SDMMC_CTYPE_1BIT:
- {
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(rksdmmc0_gpio_init.cmd_gpio.iomux.fmux);
- iomux_set(rksdmmc0_gpio_init.clk_gpio.iomux.fmux);
- iomux_set(rksdmmc0_gpio_init.data0_gpio.iomux.fmux);
- #else
- rk30_mux_api_set(rksdmmc0_gpio_init.cmd_gpio.iomux.name, rksdmmc0_gpio_init.cmd_gpio.iomux.fmux);
- rk30_mux_api_set(rksdmmc0_gpio_init.clk_gpio.iomux.name, rksdmmc0_gpio_init.clk_gpio.iomux.fmux);
- rk30_mux_api_set(rksdmmc0_gpio_init.data0_gpio.iomux.name, rksdmmc0_gpio_init.data0_gpio.iomux.fmux);
- #endif
-
- //IO voltage(vccio);
- #ifdef RK31SDK_SET_SDMMC0_PIN_VOLTAGE
- if(rk31sdk_get_sdmmc0_pin_io_voltage() > 2700)
- SDMMC_write_grf_reg(GRF_IO_CON4, (SDMMC0_IO_VOLTAGE_MASK |SDMMC0_IO_VOLTAGE_33)); //set SDMMC0 pin to 3.3v
- else
- SDMMC_write_grf_reg(GRF_IO_CON4, (SDMMC0_IO_VOLTAGE_MASK |SDMMC0_IO_VOLTAGE_18));//set SDMMC0 pin to 1.8v
- #else
- //default set the voltage of SDMMC0 to 3.3V
- SDMMC_write_grf_reg(GRF_IO_CON4, (SDMMC0_IO_VOLTAGE_MASK |SDMMC0_IO_VOLTAGE_33));
- #endif
-
- //sdmmc drive strength control
- SDMMC_write_grf_reg(GRF_IO_CON2, (SDMMC0_DRIVER_STRENGTH_MASK |SDMMC0_DRIVER_STRENGTH_8MA));
-
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- rk30_mux_api_set(rksdmmc0_gpio_init.data1_gpio.iomux.name, rksdmmc0_gpio_init.data1_gpio.iomux.fgpio);
- #endif
- gpio_request(rksdmmc0_gpio_init.data1_gpio.io, "mmc0-data1");
- gpio_direction_output(rksdmmc0_gpio_init.data1_gpio.io,GPIO_HIGH);//set mmc0-data1 to high.
-
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- rk30_mux_api_set(rksdmmc0_gpio_init.data2_gpio.iomux.name, rksdmmc0_gpio_init.data2_gpio.iomux.fgpio);
- #endif
- gpio_request(rksdmmc0_gpio_init.data2_gpio.io, "mmc0-data2");
- gpio_direction_output(rksdmmc0_gpio_init.data2_gpio.io,GPIO_HIGH);//set mmc0-data2 to high.
-
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- rk30_mux_api_set(rksdmmc0_gpio_init.data3_gpio.iomux.name, rksdmmc0_gpio_init.data3_gpio.iomux.fgpio);
- #endif
- gpio_request(rksdmmc0_gpio_init.data3_gpio.io, "mmc0-data3");
- gpio_direction_output(rksdmmc0_gpio_init.data3_gpio.io,GPIO_HIGH);//set mmc0-data3 to high.
- }
- break;
- }
-}
-
-static void rk29_sdmmc_set_iomux_mmc1(unsigned int bus_width)
-{
- #if SDMMC_USE_NEW_IOMUX_API
- iomux_set(rksdmmc1_gpio_init.cmd_gpio.iomux.fmux);
- iomux_set(rksdmmc1_gpio_init.clk_gpio.iomux.fmux);
- iomux_set(rksdmmc1_gpio_init.data0_gpio.iomux.fmux);
- iomux_set(rksdmmc1_gpio_init.data1_gpio.iomux.fmux);
- iomux_set(rksdmmc1_gpio_init.data2_gpio.iomux.fmux);
- iomux_set(rksdmmc1_gpio_init.data3_gpio.iomux.fmux);
- #else
- rk30_mux_api_set(rksdmmc1_gpio_init.cmd_gpio.iomux.name, rksdmmc1_gpio_init.cmd_gpio.iomux.fmux);
- rk30_mux_api_set(rksdmmc1_gpio_init.clk_gpio.iomux.name, rksdmmc1_gpio_init.clk_gpio.iomux.fmux);
- rk30_mux_api_set(rksdmmc1_gpio_init.data0_gpio.iomux.name, rksdmmc1_gpio_init.data0_gpio.iomux.fmux);
- rk30_mux_api_set(rksdmmc1_gpio_init.data1_gpio.iomux.name, rksdmmc1_gpio_init.data1_gpio.iomux.fmux);
- rk30_mux_api_set(rksdmmc1_gpio_init.data2_gpio.iomux.name, rksdmmc1_gpio_init.data2_gpio.iomux.fmux);
- rk30_mux_api_set(rksdmmc1_gpio_init.data3_gpio.iomux.name, rksdmmc1_gpio_init.data3_gpio.iomux.fmux);
- #endif
-
- //IO voltage(vcc-ap0)
- if(rk31sdk_wifi_voltage_select())
- SDMMC_write_grf_reg(GRF_IO_CON4, (SDMMC1_IO_VOLTAGE_MASK|SDMMC1_IO_VOLTAGE_18));
- else
- SDMMC_write_grf_reg(GRF_IO_CON4, (SDMMC1_IO_VOLTAGE_MASK|SDMMC1_IO_VOLTAGE_33));
-
- //sdmmc1 drive strength control
- SDMMC_write_grf_reg(GRF_IO_CON3, (SDMMC1_DRIVER_STRENGTH_MASK|SDMMC1_DRIVER_STRENGTH_12MA));
-
-}
-
-static void rk29_sdmmc_set_iomux_mmc2(unsigned int bus_width)
-{
- ;//
-}
-
-static void rk29_sdmmc_set_iomux(int device_id, unsigned int bus_width)
-{
- switch(device_id)
- {
- case 0:
- #ifdef CONFIG_SDMMC0_RK29
- rk29_sdmmc_set_iomux_mmc0(bus_width);
- #endif
- break;
- case 1:
- #ifdef CONFIG_SDMMC1_RK29
- rk29_sdmmc_set_iomux_mmc1(bus_width);
- #endif
- break;
- case 2:
- rk29_sdmmc_set_iomux_mmc2(bus_width);
- break;
- default:
- break;
- }
-}
-
-#endif
-
-
+++ /dev/null
-/******************************************************************************************
- * arch/arm/palt-rk/rk-sdmmc-wifi.c
- *
- * Copyright (C) 2013 ROCKCHIP, Inc.
- *
- * Description: define the varaious operations for Wifi module
- *
- * Author: Michael Xie
- * E-mail: xbw@rock-chips.com
- *
- * History:
- * ver1.0 Unified function interface for new imoux-API, created at 2013-01-15
- *
- *******************************************************************************************/
-
-static int rk29sdk_wifi_status(struct device *dev);
-static int rk29sdk_wifi_status_register(void (*callback)(int card_presend, void *dev_id), void *dev_id);
-
-#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
-static int rk29sdk_wifi_mmc0_status(struct device *dev);
-static int rk29sdk_wifi_mmc0_status_register(void (*callback)(int card_presend, void *dev_id), void *dev_id);
-static int rk29sdk_wifi_mmc0_cd = 0; /* wifi virtual 'card detect' status */
-static void (*wifi_mmc0_status_cb)(int card_present, void *dev_id);
-static void *wifi_mmc0_status_cb_devid;
-
-int rk29sdk_wifi_power_state = 0;
-int rk29sdk_bt_power_state = 0;
-
- #if defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- /////////////////////////////////////////////////////////////////////////////////////
- // set the gpio to develop wifi EVB if you select the macro of CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD
- #define USE_SDMMC_CONTROLLER_FOR_WIFI 0
- #define COMBO_MODULE_MT6620_CDT 0 //- 1--use Cdtech chip; 0--unuse CDT chip
- //power
- #define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PD0
- #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_POWER_PIN_NAME GPIO3D0_SDMMC1PWREN_NAME
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO GPIO3D_GPIO3D0
- #define RK30SDK_WIFI_GPIO_POWER_IOMUX_FMUX GPIO3D_SDMMC1_PWR_EN
- //reset
- #define RK30SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD1
- #define RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_RESET_PIN_NAME GPIO3D1_SDMMC1BACKENDPWR_NAME
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FGPIO GPIO3D_GPIO3D1
- #define RK30SDK_WIFI_GPIO_RESET_IOMUX_FMUX GPIO3D_SDMMC1_BACKEND_PWR
- //VDDIO
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL RK30_PIN2_PC5
- //#define RK30SDK_WIFI_GPIO_VCCIO_WL_ENABLE_VALUE GPIO_HIGH
- //WIFI_INT_B
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B RK30_PIN3_PD2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_PIN_NAME GPIO3D2_SDMMC1INTN_NAME
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FGPIO GPIO3D_GPIO3D2
- #define RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FMUX GPIO3D_SDMMC1_INT_N
- //BGF_INT_B
- #define RK30SDK_WIFI_GPIO_BGF_INT_B RK30_PIN3_PC6
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_PIN_NAME GPIO3C6_SDMMC1DETECTN_NAME
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FGPIO GPIO3C_GPIO3C6
- #define RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FMUX GPIO3C_SDMMC1_DETECT_N
- //GPS_SYNC
- #define RK30SDK_WIFI_GPIO_GPS_SYNC RK30_PIN3_PC7
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_ENABLE_VALUE GPIO_HIGH
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_PIN_NAME GPIO3C7_SDMMC1WRITEPRT_NAME
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FGPIO GPIO3C_GPIO3C7
- #define RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FMUX GPIO3C_SDMMC1_WRITE_PRT
-
- #if COMBO_MODULE_MT6620_CDT
- //ANTSEL2
- #define RK30SDK_WIFI_GPIO_ANTSEL2 RK30_PIN4_PD4
- #define RK30SDK_WIFI_GPIO_ANTSEL2_ENABLE_VALUE GPIO_LOW //use 6620 in CDT chip, LOW--work; High--no work.
- #define RK30SDK_WIFI_GPIO_ANTSEL2_PIN_NAME GPIO4D4_SMCDATA12_TRACEDATA12_NAME
- #define RK30SDK_WIFI_GPIO_ANTSEL2_IOMUX_FGPIO GPIO4D_GPIO4D4
- #define RK30SDK_WIFI_GPIO_ANTSEL2_IOMUX_FMUX GPIO4D_TRACE_DATA12
- //ANTSEL3
- #define RK30SDK_WIFI_GPIO_ANTSEL3 RK30_PIN4_PD3
- #define RK30SDK_WIFI_GPIO_ANTSEL3_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- #define RK30SDK_WIFI_GPIO_ANTSEL3_PIN_NAME GPIO4D3_SMCDATA11_TRACEDATA11_NAME
- #define RK30SDK_WIFI_GPIO_ANTSEL3_IOMUX_FGPIO GPIO4D_GPIO4D3
- #define RK30SDK_WIFI_GPIO_ANTSEL3_IOMUX_FMUX GPIO4D_TRACE_DATA11
- //GPS_LAN
- #define RK30SDK_WIFI_GPIO_GPS_LAN RK30_PIN4_PD6
- #define RK30SDK_WIFI_GPIO_GPS_LAN_ENABLE_VALUE GPIO_HIGH //use 6620 in CDT chip, High--work; Low--no work..
- #define RK30SDK_WIFI_GPIO_GPS_LAN_PIN_NAME GPIO4D6_SMCDATA14_TRACEDATA14_NAME
- #define RK30SDK_WIFI_GPIO_GPS_LAN_IOMUX_FGPIO GPIO4D_GPIO4D6
- #define RK30SDK_WIFI_GPIO_GPS_LAN_IOMUX_FMUX GPIO4D_TRACE_DATA14
- #endif // #if COMBO_MODULE_MT6620_CDT--#endif
-
- #endif // #if defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)---#endif
-#endif // #if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) ---#endif
-
-static int rk29sdk_wifi_cd = 0; /* wifi virtual 'card detect' status */
-static void (*wifi_status_cb)(int card_present, void *dev_id);
-static void *wifi_status_cb_devid;
-
-#if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
-#define RK29SDK_WIFI_SDIO_CARD_INT RK30SDK_WIFI_GPIO_WIFI_INT_B
-#endif
-
-struct rksdmmc_gpio_wifi_moudle rk_platform_wifi_gpio = {
- .power_n = {
- .io = RK30SDK_WIFI_GPIO_POWER_N,
- .enable = RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE,
- #ifdef RK30SDK_WIFI_GPIO_POWER_PIN_NAME
- .iomux = {
- .name = RK30SDK_WIFI_GPIO_POWER_PIN_NAME,
- .fgpio = RK30SDK_WIFI_GPIO_POWER_IOMUX_FGPIO,
- #ifdef RK30SDK_WIFI_GPIO_POWER_IOMUX_FMUX
- .fmux = RK30SDK_WIFI_GPIO_POWER_IOMUX_FMUX,
- #endif
- },
- #endif
- },
-
- #ifdef RK30SDK_WIFI_GPIO_RESET_N
- .reset_n = {
- .io = RK30SDK_WIFI_GPIO_RESET_N,
- .enable = RK30SDK_WIFI_GPIO_RESET_ENABLE_VALUE,
- #ifdef RK30SDK_WIFI_GPIO_RESET_PIN_NAME
- .iomux = {
- .name = RK30SDK_WIFI_GPIO_RESET_PIN_NAME,
- .fgpio = RK30SDK_WIFI_GPIO_RESET_IOMUX_FGPIO,
- #ifdef RK30SDK_WIFI_GPIO_RESET_IOMUX_FMUX
- .fmux = RK30SDK_WIFI_GPIO_RESET_IOMUX_FMUX,
- #endif
- },
- #endif
- },
- #endif
-
- #ifdef RK30SDK_WIFI_GPIO_WIFI_INT_B
- .wifi_int_b = {
- .io = RK30SDK_WIFI_GPIO_WIFI_INT_B,
- .enable = RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE,
- #ifdef RK30SDK_WIFI_GPIO_WIFI_INT_B_PIN_NAME
- .iomux = {
- .name = RK30SDK_WIFI_GPIO_WIFI_INT_B_PIN_NAME,
- .fgpio = RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FGPIO,
- #ifdef RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FMUX
- .fmux = RK30SDK_WIFI_GPIO_WIFI_INT_B_IOMUX_FMUX,
- #endif
- },
- #endif
- },
- #endif
-
- #ifdef RK30SDK_WIFI_GPIO_VCCIO_WL
- .vddio = {
- .io = RK30SDK_WIFI_GPIO_VCCIO_WL,
- .enable = RK30SDK_WIFI_GPIO_VCCIO_WL_ENABLE_VALUE,
- #ifdef RK30SDK_WIFI_GPIO_VCCIO_WL_PIN_NAME
- .iomux = {
- .name = RK30SDK_WIFI_GPIO_VCCIO_WL_PIN_NAME,
- .fgpio = RK30SDK_WIFI_GPIO_VCCIO_WL_IOMUX_FGPIO,
- #ifdef RK30SDK_WIFI_GPIO_VCCIO_WL_IOMUX_FMUX
- .fmux = RK30SDK_WIFI_GPIO_VCCIO_WL_IOMUX_FMUX,
- #endif
- },
- #endif
- },
- #endif
-
- #ifdef RK30SDK_WIFI_GPIO_BGF_INT_B
- .bgf_int_b = {
- .io = RK30SDK_WIFI_GPIO_BGF_INT_B,
- .enable = RK30SDK_WIFI_GPIO_BGF_INT_B_ENABLE_VALUE,
- #ifdef RK30SDK_WIFI_GPIO_BGF_INT_B_PIN_NAME
- .iomux = {
- .name = RK30SDK_WIFI_GPIO_BGF_INT_B_PIN_NAME,
- .fgpio = RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FGPIO,
- #ifdef RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FMUX
- .fmux = RK30SDK_WIFI_GPIO_BGF_INT_B_IOMUX_FMUX,
- #endif
- },
- #endif
- },
- #endif
-
- #ifdef RK30SDK_WIFI_GPIO_GPS_SYNC
- .gps_sync = {
- .io = RK30SDK_WIFI_GPIO_GPS_SYNC,
- .enable = RK30SDK_WIFI_GPIO_GPS_SYNC_ENABLE_VALUE,
- #ifdef RK30SDK_WIFI_GPIO_GPS_SYNC_PIN_NAME
- .iomux = {
- .name = RK30SDK_WIFI_GPIO_GPS_SYNC_PIN_NAME,
- .fgpio = RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FGPIO,
- #ifdef RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FMUX
- .fmux = RK30SDK_WIFI_GPIO_GPS_SYNC_IOMUX_FMUX,
- #endif
- },
- #endif
- },
- #endif
-
-#if defined(COMBO_MODULE_MT6620_CDT) && COMBO_MODULE_MT6620_CDT
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL2
- .ANTSEL2 = {
- .io = RK30SDK_WIFI_GPIO_ANTSEL2,
- .enable = RK30SDK_WIFI_GPIO_ANTSEL2_ENABLE_VALUE,
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL2_PIN_NAME
- .iomux = {
- .name = RK30SDK_WIFI_GPIO_ANTSEL2_PIN_NAME,
- .fgpio = RK30SDK_WIFI_GPIO_ANTSEL2_IOMUX_FGPIO,
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL2_IOMUX_FMUX
- .fmux = RK30SDK_WIFI_GPIO_ANTSEL2_IOMUX_FMUX,
- #endif
- },
- #endif
- },
- #endif
-
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL3
- .ANTSEL3 = {
- .io = RK30SDK_WIFI_GPIO_ANTSEL3,
- .enable = RK30SDK_WIFI_GPIO_ANTSEL3_ENABLE_VALUE,
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL3_PIN_NAME
- .iomux = {
- .name = RK30SDK_WIFI_GPIO_ANTSEL3_PIN_NAME,
- .fgpio = RK30SDK_WIFI_GPIO_ANTSEL3_IOMUX_FGPIO,
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL3_IOMUX_FMUX
- .fmux = RK30SDK_WIFI_GPIO_ANTSEL3_IOMUX_FMUX,
- #endif
- },
- #endif
- },
- #endif
-
- #ifdef RK30SDK_WIFI_GPIO_GPS_LAN
- .GPS_LAN = {
- .io = RK30SDK_WIFI_GPIO_GPS_LAN,
- .enable = RK30SDK_WIFI_GPIO_GPS_LAN_ENABLE_VALUE,
- #ifdef RK30SDK_WIFI_GPIO_GPS_LAN_PIN_NAME
- .iomux = {
- .name = RK30SDK_WIFI_GPIO_GPS_LAN_PIN_NAME,
- .fgpio = RK30SDK_WIFI_GPIO_GPS_LAN_IOMUX_FGPIO,
- #ifdef RK30SDK_WIFI_GPIO_GPS_LAN_IOMUX_FMUX
- .fmux = RK30SDK_WIFI_GPIO_GPS_LAN_IOMUX_FMUX,
- #endif
- },
- #endif
- },
- #endif
-#endif // #if COMBO_MODULE_MT6620_CDT--#endif
-};
-
-
-
-#ifdef CONFIG_WIFI_CONTROL_FUNC
-#if defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
-static int rk29sdk_wifi_mmc0_status(struct device *dev);
-static int rk29sdk_wifi_mmc0_status_register(void (*callback)(int card_presend, void *dev_id), void *dev_id);
-static int rk29sdk_wifi_mmc0_cd = 0; /* wifi virtual 'card detect' status */
-static void (*wifi_mmc0_status_cb)(int card_present, void *dev_id);
-static void *wifi_mmc0_status_cb_devid;
-#endif
-
-#define PREALLOC_WLAN_SEC_NUM 4
-#define PREALLOC_WLAN_BUF_NUM 160
-#define PREALLOC_WLAN_SECTION_HEADER 24
-
-#define WLAN_SECTION_SIZE_0 (PREALLOC_WLAN_BUF_NUM * 128)
-#define WLAN_SECTION_SIZE_1 (PREALLOC_WLAN_BUF_NUM * 128)
-#define WLAN_SECTION_SIZE_2 (PREALLOC_WLAN_BUF_NUM * 512)
-#define WLAN_SECTION_SIZE_3 (PREALLOC_WLAN_BUF_NUM * 1024)
-
-#define WLAN_SKB_BUF_NUM 16
-
-static struct sk_buff *wlan_static_skb[WLAN_SKB_BUF_NUM];
-
-struct wifi_mem_prealloc {
- void *mem_ptr;
- unsigned long size;
-};
-
-static struct wifi_mem_prealloc wifi_mem_array[PREALLOC_WLAN_SEC_NUM] = {
- {NULL, (WLAN_SECTION_SIZE_0 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_1 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_2 + PREALLOC_WLAN_SECTION_HEADER)},
- {NULL, (WLAN_SECTION_SIZE_3 + PREALLOC_WLAN_SECTION_HEADER)}
-};
-
-static void *rk29sdk_mem_prealloc(int section, unsigned long size)
-{
- if (section == PREALLOC_WLAN_SEC_NUM)
- return wlan_static_skb;
-
- if ((section < 0) || (section > PREALLOC_WLAN_SEC_NUM))
- return NULL;
-
- if (wifi_mem_array[section].size < size)
- return NULL;
-
- return wifi_mem_array[section].mem_ptr;
-}
-
-static int __init rk29sdk_init_wifi_mem(void)
-{
- int i;
- int j;
-
- for (i = 0 ; i < WLAN_SKB_BUF_NUM ; i++) {
- wlan_static_skb[i] = dev_alloc_skb(
- ((i < (WLAN_SKB_BUF_NUM / 2)) ? 4096 : 8192));
-
- if (!wlan_static_skb[i])
- goto err_skb_alloc;
- }
-
- for (i = 0 ; i < PREALLOC_WLAN_SEC_NUM ; i++) {
- wifi_mem_array[i].mem_ptr =
- kmalloc(wifi_mem_array[i].size, GFP_KERNEL);
-
- if (!wifi_mem_array[i].mem_ptr)
- goto err_mem_alloc;
- }
- return 0;
-
-err_mem_alloc:
- pr_err("Failed to mem_alloc for WLAN\n");
- for (j = 0 ; j < i ; j++)
- kfree(wifi_mem_array[j].mem_ptr);
-
- i = WLAN_SKB_BUF_NUM;
-
-err_skb_alloc:
- pr_err("Failed to skb_alloc for WLAN\n");
- for (j = 0 ; j < i ; j++)
- dev_kfree_skb(wlan_static_skb[j]);
-
- return -ENOMEM;
-}
-
-
-#if defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
-static int rk29sdk_wifi_mmc0_status(struct device *dev)
-
-{
- return rk29sdk_wifi_mmc0_cd;
-}
-
-static int rk29sdk_wifi_mmc0_status_register(void (*callback)(int card_present, void *dev_id), void *dev_id)
-{
- if(wifi_mmc0_status_cb)
- return -EAGAIN;
- wifi_mmc0_status_cb = callback;
- wifi_mmc0_status_cb_devid = dev_id;
- return 0;
-}
-#else
-static int rk29sdk_wifi_status(struct device *dev)
-{
- return rk29sdk_wifi_cd;
-}
-
-static int rk29sdk_wifi_status_register(void (*callback)(int card_present, void *dev_id), void *dev_id)
-{
- if(wifi_status_cb)
- return -EAGAIN;
- wifi_status_cb = callback;
- wifi_status_cb_devid = dev_id;
- return 0;
-}
-#endif
-
-static int __init rk29sdk_wifi_bt_gpio_control_init(void)
-{
- rk29sdk_init_wifi_mem();
- rk29_mux_api_set(rk_platform_wifi_gpio.power_n.iomux.name, rk_platform_wifi_gpio.power_n.iomux.fgpio);
-
-#ifdef CONFIG_MACH_RK_FAC
- if(wifi_pwr!=-1)
- port_output_init(wifi_pwr, 1, "wifi_pwr");
-#else
- if (rk_platform_wifi_gpio.power_n.io != INVALID_GPIO) {
- if (gpio_request(rk_platform_wifi_gpio.power_n.io, "wifi_power")) {
- pr_info("%s: request wifi power gpio failed\n", __func__);
- return -1;
- }
- }
-#endif
-
-#ifdef RK30SDK_WIFI_GPIO_RESET_N
- if (rk_platform_wifi_gpio.reset_n.io != INVALID_GPIO) {
- if (gpio_request(rk_platform_wifi_gpio.reset_n.io, "wifi reset")) {
- pr_info("%s: request wifi reset gpio failed\n", __func__);
- gpio_free(rk_platform_wifi_gpio.power_n.io);
- return -1;
- }
- }
-#endif
-
-#ifdef CONFIG_MACH_RK_FAC
- if(wifi_pwr!=-1)
- port_output_off(wifi_pwr);
-#else
- if (rk_platform_wifi_gpio.power_n.io != INVALID_GPIO)
- gpio_direction_output(rk_platform_wifi_gpio.power_n.io, !(rk_platform_wifi_gpio.power_n.enable) );
-#endif
-
-#ifdef RK30SDK_WIFI_GPIO_RESET_N
- if (rk_platform_wifi_gpio.reset_n.io != INVALID_GPIO)
- gpio_direction_output(rk_platform_wifi_gpio.reset_n.io, !(rk_platform_wifi_gpio.reset_n.enable) );
-#endif
-
- #if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
-
- #if !defined(CONFIG_MT5931) && !defined(CONFIG_MT5931_MT6622)
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- rk29_mux_api_set(rksdmmc1_gpio_init.data1_gpio.iomux.name, rksdmmc1_gpio_init.data1_gpio.iomux.fgpio);
- #endif
- gpio_request(rksdmmc1_gpio_init.data1_gpio.io, "mmc1-data1");
- gpio_direction_output(rksdmmc1_gpio_init.data1_gpio.io,GPIO_LOW);//set mmc1-data1 to low.
-
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- rk29_mux_api_set(rksdmmc1_gpio_init.data2_gpio.iomux.name, rksdmmc1_gpio_init.data2_gpio.iomux.fgpio);
- #endif
- gpio_request(rksdmmc1_gpio_init.data2_gpio.io, "mmc1-data2");
- gpio_direction_output(rksdmmc1_gpio_init.data2_gpio.io,GPIO_LOW);//set mmc1-data2 to low.
-
- #if !(!!SDMMC_USE_NEW_IOMUX_API)
- rk29_mux_api_set(rksdmmc1_gpio_init.data3_gpio.iomux.name, rksdmmc1_gpio_init.data3_gpio.iomux.fgpio);
- #endif
- gpio_request(rksdmmc1_gpio_init.data3_gpio.io, "mmc1-data3");
- gpio_direction_output(rksdmmc1_gpio_init.data3_gpio.io,GPIO_LOW);//set mmc1-data3 to low.
- #endif
-
- rk29_sdmmc_gpio_open(1, 0); //added by xbw at 2011-10-13
- #endif
- pr_info("%s: init finished\n",__func__);
-
- return 0;
-}
-
-#if (defined(CONFIG_RTL8192CU) || defined(CONFIG_RTL8188EU) || defined(CONFIG_RTL8723AU)) \
- && (defined(CONFIG_ARCH_RK2928) || defined(CONFIG_MACH_RK3026_86V) ||defined(CONFIG_MACH_RK3026_86V_FAC))
-static int usbwifi_power_status = 1;
-int rk29sdk_wifi_power(int on)
-{
- pr_info("%s: %d\n", __func__, on);
- if (on){
- #if defined(CONFIG_USB_WIFI_POWER_CONTROLED_BY_GPIO)
- gpio_set_value(rk_platform_wifi_gpio.power_n.io, rk_platform_wifi_gpio.power_n.enable);
- mdelay(100);
- #else
- if(usbwifi_power_status == 1) {
- rkusb_wifi_power(0);
- mdelay(50);
- }
- rkusb_wifi_power(1);
- #endif
- usbwifi_power_status = 1;
- pr_info("wifi turn on power\n");
- }else{
- #if defined(CONFIG_USB_WIFI_POWER_CONTROLED_BY_GPIO)
- gpio_set_value(rk_platform_wifi_gpio.power_n.io, !(rk_platform_wifi_gpio.power_n.enable));
- mdelay(100);
- #else
- rkusb_wifi_power(0);
- usbwifi_power_status = 0;
- #endif
- pr_info("wifi shut off power\n");
- }
- return 0;
-}
-#else
-int rk29sdk_wifi_power(int on)
-{
- pr_info("%s: %d\n", __func__, on);
- if (on){
- #ifdef CONFIG_MACH_RK_FAC
- if(wifi_pwr!=-1)
- port_output_on(wifi_pwr);
- #else
- gpio_set_value(rk_platform_wifi_gpio.power_n.io, rk_platform_wifi_gpio.power_n.enable);
- #endif
- mdelay(50);
-
- #if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
- rk29_sdmmc_gpio_open(1, 1); //added by xbw at 2011-10-13
- #endif
-
- #ifdef RK30SDK_WIFI_GPIO_RESET_N
- if (rk_platform_wifi_gpio.reset_n.io != INVALID_GPIO)
- gpio_set_value(rk_platform_wifi_gpio.reset_n.io, rk_platform_wifi_gpio.reset_n.enable);
- #endif
- mdelay(100);
- pr_info("wifi turn on power\n");
- }else{
-// if (!rk29sdk_bt_power_state){
- #ifdef CONFIG_MACH_RK_FAC
- if(wifi_pwr!=-1)
- port_output_off(wifi_pwr);
- #else
- gpio_set_value(rk_platform_wifi_gpio.power_n.io, !(rk_platform_wifi_gpio.power_n.enable));
- #endif
- #if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
- rk29_sdmmc_gpio_open(1, 0); //added by xbw at 2011-10-13
- #endif
-
- mdelay(100);
- pr_info("wifi shut off power\n");
-// }else
-// {
-// pr_info("wifi shouldn't shut off power, bt is using it!\n");
-// }
-#ifdef RK30SDK_WIFI_GPIO_RESET_N
- if (rk_platform_wifi_gpio.reset_n.io != INVALID_GPIO)
- gpio_set_value(rk_platform_wifi_gpio.reset_n.io, !(rk_platform_wifi_gpio.reset_n.enable));
-#endif
- }
-
-// rk29sdk_wifi_power_state = on;
- return 0;
-}
-#endif
-EXPORT_SYMBOL(rk29sdk_wifi_power);
-
-static int rk29sdk_wifi_reset_state;
-static int rk29sdk_wifi_reset(int on)
-{
- pr_info("%s: %d\n", __func__, on);
- //mdelay(100);
- rk29sdk_wifi_reset_state = on;
- return 0;
-}
-
-#if defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)\r
-int rk29sdk_wifi_set_carddetect(int val)\r
-{\r
- printk("%s:%d\n", __func__, val);\r
- rk29sdk_wifi_mmc0_cd = val;\r
- if (wifi_mmc0_status_cb){\r
- wifi_mmc0_status_cb(val, wifi_mmc0_status_cb_devid);\r
- }else {\r
- pr_warning("%s,in mmc0 nobody to notify\n", __func__);\r
- }\r
- return 0; \r
-}\r
-#else
-int rk29sdk_wifi_set_carddetect(int val)
-{
- pr_info("%s:%d\n", __func__, val);
- rk29sdk_wifi_cd = val;
- if (wifi_status_cb){
- wifi_status_cb(val, wifi_status_cb_devid);
- }else {
- pr_warning("%s, nobody to notify\n", __func__);
- }
- return 0;
-}
-#endif
-EXPORT_SYMBOL(rk29sdk_wifi_set_carddetect);
-
-#include <linux/etherdevice.h>
-u8 wifi_custom_mac_addr[6] = {0,0,0,0,0,0};
-extern char GetSNSectorInfo(char * pbuf);
-static int rk29sdk_wifi_mac_addr(unsigned char *buf)
-{
- printk("rk29sdk_wifi_mac_addr.\n");
-
- // from vflash
- if(is_zero_ether_addr(wifi_custom_mac_addr)) {
- int i;
- char *tempBuf = kmalloc(512, GFP_KERNEL);
- if(tempBuf) {
- GetSNSectorInfo(tempBuf);
- for (i = 506; i <= 511; i++)
- wifi_custom_mac_addr[i-506] = tempBuf[i];
- kfree(tempBuf);
- }
- }
-
- memcpy(buf, wifi_custom_mac_addr, 6);
- return 0;
-}
-EXPORT_SYMBOL(rk29sdk_wifi_mac_addr);
-
-//#define WIFI_HOST_WAKE RK30_PIN3_PD2
-
-static struct resource resources[] = {
- {
-#ifdef RK30SDK_WIFI_GPIO_WIFI_INT_B
- .start = RK30SDK_WIFI_GPIO_WIFI_INT_B,
-#endif
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL | IORESOURCE_IRQ_SHAREABLE,
- .name = "bcmdhd_wlan_irq",
- },
-};
- //#if defined(CONFIG_WIFI_CONTROL_FUNC)----#elif
-
-///////////////////////////////////////////////////////////////////////////////////
-#elif defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
-
-#define debug_combo_system 0
-
-int rk29sdk_wifi_combo_get_BGFgpio(void)
-{
- return rk_platform_wifi_gpio.bgf_int_b.io;
-}
-EXPORT_SYMBOL(rk29sdk_wifi_combo_get_BGFgpio);
-
-
-int rk29sdk_wifi_combo_get_GPS_SYNC_gpio(void)
-{
- return rk_platform_wifi_gpio.gps_sync.io;
-}
-EXPORT_SYMBOL(rk29sdk_wifi_combo_get_GPS_SYNC_gpio);
-
-
-static int rk29sdk_wifi_combo_module_gpio_init(void)
-{
- //VDDIO
- #ifdef RK30SDK_WIFI_GPIO_VCCIO_WL
- #ifdef RK30SDK_WIFI_GPIO_VCCIO_WL_PIN_NAME
- rk30_mux_api_set(rk_platform_wifi_gpio.vddio.iomux.name, rk_platform_wifi_gpio.vddio.iomux.fgpio);
- #endif
- gpio_request(rk_platform_wifi_gpio.vddio.io, "combo-VDDIO");
- gpio_direction_output(rk_platform_wifi_gpio.vddio.io, !(rk_platform_wifi_gpio.power_n.enable));
- #endif
-
- //BGF_INT_B
- #ifdef RK30SDK_WIFI_GPIO_BGF_INT_B_PIN_NAME
- rk30_mux_api_set(rk_platform_wifi_gpio.bgf_int_b.iomux.name, rk_platform_wifi_gpio.bgf_int_b.iomux.fgpio);
- #endif
- gpio_request(rk_platform_wifi_gpio.bgf_int_b.io, "combo-BGFINT");
- gpio_pull_updown(rk_platform_wifi_gpio.bgf_int_b.io, GPIOPullUp);
- gpio_direction_input(rk_platform_wifi_gpio.bgf_int_b.io);
-
- //WIFI_INT_B
- #ifdef RK30SDK_WIFI_GPIO_WIFI_INT_B_PIN_NAME
- rk30_mux_api_set(rk_platform_wifi_gpio.bgf_int_b.iomux.name, rk_platform_wifi_gpio.bgf_int_b.iomux.fgpio);
- #endif
- gpio_request(rk_platform_wifi_gpio.wifi_int_b.io, "combo-WIFIINT");
- gpio_pull_updown(rk_platform_wifi_gpio.wifi_int_b.io, GPIOPullUp);
- gpio_direction_input(rk_platform_wifi_gpio.wifi_int_b.io);
-
- //reset
- #ifdef RK30SDK_WIFI_GPIO_RESET_PIN_NAME
- rk30_mux_api_set(rk_platform_wifi_gpio.reset_n.iomux.name, rk_platform_wifi_gpio.reset_n.iomux.fgpio);
- #endif
- gpio_request(rk_platform_wifi_gpio.reset_n.io, "combo-RST");
- gpio_direction_output(rk_platform_wifi_gpio.reset_n.io, !(rk_platform_wifi_gpio.reset_n.enable));
-
- //power
- #ifdef RK30SDK_WIFI_GPIO_POWER_PIN_NAME
- rk30_mux_api_set(rk_platform_wifi_gpio.power_n.iomux.name, rk_platform_wifi_gpio.power_n.iomux.fgpio);
- #endif
- gpio_request(rk_platform_wifi_gpio.power_n.io, "combo-PMUEN");
- gpio_direction_output(rk_platform_wifi_gpio.power_n.io, !(rk_platform_wifi_gpio.power_n.enable));
-
- #if defined(COMBO_MODULE_MT6620_CDT) && COMBO_MODULE_MT6620_CDT
- //ANTSEL2
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL2
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL2_PIN_NAME
- rk30_mux_api_set(rk_platform_wifi_gpio.ANTSEL2.iomux.name, rk_platform_wifi_gpio.ANTSEL2.iomux.fgpio);
- #endif
- gpio_request(rk_platform_wifi_gpio.ANTSEL2.io, "combo-ANTSEL2");
- gpio_direction_output(rk_platform_wifi_gpio.ANTSEL2.io, rk_platform_wifi_gpio.ANTSEL2.enable);
- #endif
-
- //ANTSEL3
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL3
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL3_PIN_NAME
- rk30_mux_api_set(rk_platform_wifi_gpio.ANTSEL3.iomux.name, rk_platform_wifi_gpio.ANTSEL3.iomux.fgpio);
- #endif
- gpio_request(rk_platform_wifi_gpio.ANTSEL3.io, "combo-ANTSEL3");
- gpio_direction_output(rk_platform_wifi_gpio.ANTSEL3.io, !(rk_platform_wifi_gpio.ANTSEL3.enable));
- #endif
-
- //GPS_LAN
- #ifdef RK30SDK_WIFI_GPIO_GPS_LAN
- #ifdef RK30SDK_WIFI_GPIO_GPS_LAN_PIN_NAME
- rk30_mux_api_set(rk_platform_wifi_gpio.GPS_LAN.iomux.name, rk_platform_wifi_gpio.GPS_LAN.iomux.fgpio);
- #endif
- gpio_request(rk_platform_wifi_gpio.GPS_LAN.io, "combo-GPSLAN");
- gpio_direction_output(rk_platform_wifi_gpio.GPS_LAN.io, rk_platform_wifi_gpio.GPS_LAN.enable);
- #endif
-
- #endif//#if COMBO_MODULE_MT6620_CDT ---#endif
-
- return 0;
-}
-
-
-int rk29sdk_wifi_combo_module_power(int on)
-{
- if(on)
- {
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL2
- gpio_direction_output(rk_platform_wifi_gpio.ANTSEL2.io, rk_platform_wifi_gpio.ANTSEL2.enable);
- #endif
-
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL3
- gpio_direction_output(rk_platform_wifi_gpio.ANTSEL3.io, rk_platform_wifi_gpio.ANTSEL3.enable);
- #endif
-
- #ifdef RK30SDK_WIFI_GPIO_GPS_LAN
- gpio_direction_output(rk_platform_wifi_gpio.GPS_LAN.io, rk_platform_wifi_gpio.GPS_LAN.enable);
- #endif
-
- #ifdef RK30SDK_WIFI_GPIO_VCCIO_WL
- gpio_set_value(rk_platform_wifi_gpio.vddio.io, rk_platform_wifi_gpio.vddio.enable);
- mdelay(10);
- #endif
-
- gpio_set_value(rk_platform_wifi_gpio.power_n.io, rk_platform_wifi_gpio.power_n.enable);
- mdelay(10);
- pr_info("combo-module turn on power\n");
- }
- else
- {
- gpio_set_value(rk_platform_wifi_gpio.power_n.io, !(rk_platform_wifi_gpio.power_n.enable) );
- mdelay(10);
-
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL2
- //Because the foot is pulled low, therefore, continue to remain low
- gpio_direction_output(rk_platform_wifi_gpio.ANTSEL2.io, rk_platform_wifi_gpio.ANTSEL2.enable);
- #endif
-
- #ifdef RK30SDK_WIFI_GPIO_ANTSEL3
- gpio_direction_output(rk_platform_wifi_gpio.ANTSEL3.io, !(rk_platform_wifi_gpio.ANTSEL3.enable));
- #endif
-
- #ifdef RK30SDK_WIFI_GPIO_GPS_LAN
- gpio_direction_output(rk_platform_wifi_gpio.GPS_LAN.io, !(rk_platform_wifi_gpio.GPS_LAN.enable));
- #endif
-
- #ifdef RK30SDK_WIFI_GPIO_VCCIO_WL
- gpio_set_value(rk_platform_wifi_gpio.vddio.io, !(rk_platform_wifi_gpio.vddio.enable));
- #endif
-
- pr_info("combo-module turn off power\n");
- }
- return 0;
-
-}
-EXPORT_SYMBOL(rk29sdk_wifi_combo_module_power);
-
-
-int rk29sdk_wifi_combo_module_reset(int on)
-{
- if(on)
- {
- gpio_set_value(rk_platform_wifi_gpio.reset_n.io, rk_platform_wifi_gpio.reset_n.enable);
- pr_info("combo-module reset out 1\n");
- }
- else
- {
- gpio_set_value(rk_platform_wifi_gpio.reset_n.io, !(rk_platform_wifi_gpio.reset_n.enable) );
- pr_info("combo-module reset out 0\n");
- }
-
- return 0;
-}
-EXPORT_SYMBOL(rk29sdk_wifi_combo_module_reset);
-
-
-static int rk29sdk_wifi_mmc0_status(struct device *dev)
-{
- return rk29sdk_wifi_mmc0_cd;
-}
-
-static int rk29sdk_wifi_mmc0_status_register(void (*callback)(int card_present, void *dev_id), void *dev_id)
-{
- if(wifi_mmc0_status_cb)
- return -EAGAIN;
- wifi_mmc0_status_cb = callback;
- wifi_mmc0_status_cb_devid = dev_id;
- return 0;
-}
-
-
-static int rk29sdk_wifi_status(struct device *dev)
-{
- return rk29sdk_wifi_cd;
-}
-
-static int rk29sdk_wifi_status_register(void (*callback)(int card_present, void *dev_id), void *dev_id)
-{
- if(wifi_status_cb)
- return -EAGAIN;
- wifi_status_cb = callback;
- wifi_status_cb_devid = dev_id;
- return 0;
-}
-
-int rk29sdk_wifi_power(int on)
-{
- pr_info("%s: %d\n", __func__, on);
- if (on){
-
- #if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
-
- #if defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- rk29_sdmmc_gpio_open(0, 1);
- #else
- rk29_sdmmc_gpio_open(1, 0);
- mdelay(10);
- rk29_sdmmc_gpio_open(1, 1);
- #endif
- #endif
-
- mdelay(100);
- pr_info("wifi turn on power\n");
- }
- else
- {
-#if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
- #if defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
- rk29_sdmmc_gpio_open(0, 0);
- #else
- rk29_sdmmc_gpio_open(1, 0);
- #endif
-#endif
- mdelay(100);
- pr_info("wifi shut off power\n");
-
- }
-
- rk29sdk_wifi_power_state = on;
- return 0;
-
-}
-EXPORT_SYMBOL(rk29sdk_wifi_power);
-
-
-int rk29sdk_wifi_reset(int on)
-{
- return 0;
-}
-EXPORT_SYMBOL(rk29sdk_wifi_reset);
-
-
-#if defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
-int rk29sdk_wifi_set_carddetect(int val)
-{
- pr_info("%s:%d\n", __func__, val);
- rk29sdk_wifi_mmc0_cd = val;
- if (wifi_mmc0_status_cb){
- wifi_mmc0_status_cb(val, wifi_mmc0_status_cb_devid);
- }else {
- pr_warning("%s,in mmc0 nobody to notify\n", __func__);
- }
- return 0;
-}
-
-#else
-int rk29sdk_wifi_set_carddetect(int val)
-{
- pr_info("%s:%d\n", __func__, val);
- rk29sdk_wifi_cd = val;
- if (wifi_status_cb){
- wifi_status_cb(val, wifi_status_cb_devid);
- }else {
- pr_warning("%s,in mmc1 nobody to notify\n", __func__);
- }
- return 0;
-}
-#endif
-
-EXPORT_SYMBOL(rk29sdk_wifi_set_carddetect);
-
-///////////////////////////////////////////////////////////////////////////////////
-#endif //#if defined(CONFIG_WIFI_CONTROL_FUNC)---#elif defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC) --#endif
-
-
-
-#if defined(CONFIG_WIFI_CONTROL_FUNC)
-static struct wifi_platform_data rk29sdk_wifi_control = {
- .set_power = rk29sdk_wifi_power,
- .set_reset = rk29sdk_wifi_reset,
- .set_carddetect = rk29sdk_wifi_set_carddetect,
- .mem_prealloc = rk29sdk_mem_prealloc,
-// .get_mac_addr = rk29sdk_wifi_mac_addr,
-};
-
-static struct platform_device rk29sdk_wifi_device = {
- .name = "bcmdhd_wlan",
- .id = 1,
- .num_resources = ARRAY_SIZE(resources),
- .resource = resources,
- .dev = {
- .platform_data = &rk29sdk_wifi_control,
- },
-};
-
-#elif defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
-
- #if debug_combo_system
- static struct combo_module_platform_data rk29sdk_combo_module_control = {
- .set_power = rk29sdk_wifi_combo_module_power,
- .set_reset = rk29sdk_wifi_combo_module_reset,
- };
-
- static struct platform_device rk29sdk_combo_module_device = {
- .name = "combo-system",
- .id = 1,
- .dev = {
- .platform_data = &rk29sdk_combo_module_control,
- },
- };
- #endif
-
-static struct wifi_platform_data rk29sdk_wifi_control = {
- .set_power = rk29sdk_wifi_power,
- .set_reset = rk29sdk_wifi_reset,
- .set_carddetect = rk29sdk_wifi_set_carddetect,
-};
-
-static struct platform_device rk29sdk_wifi_device = {
- .name = "combo-wifi",
- .id = 1,
- .dev = {
- .platform_data = &rk29sdk_wifi_control,
- },
-};
-
-#endif
-
-
+++ /dev/null
-#include <plat/rk_camera.h> \r
-\r
-#ifndef PMEM_CAM_SIZE\r
-#ifdef CONFIG_VIDEO_RK29 \r
-/*---------------- Camera Sensor Fixed Macro Begin ------------------------*/\r
-// Below Macro is fixed, programer don't change it!!!!!!\r
-\r
-#if defined (CONFIG_SENSOR_IIC_ADDR_0) && (CONFIG_SENSOR_IIC_ADDR_0 != 0x00)\r
-#define PMEM_SENSOR_FULL_RESOLUTION_0 CONS(CONFIG_SENSOR_0,_FULL_RESOLUTION)\r
-\r
- #ifdef CONFIG_SENSOR_CIF_INDEX_0\r
- #define SENSOR_CIF_BUSID_0 CONS(RK_CAM_PLATFORM_DEV_ID_,CONFIG_SENSOR_CIF_INDEX_0)\r
- #else\r
- #define SENSOR_CIF_BUSID_0 RK29_CAM_PLATFORM_DEV_ID\r
- #endif\r
- \r
- #if !(PMEM_SENSOR_FULL_RESOLUTION_0)\r
- #undef PMEM_SENSOR_FULL_RESOLUTION_0\r
- #define PMEM_SENSOR_FULL_RESOLUTION_0 RK_CAM_SUPPORT_RESOLUTION\r
- #endif\r
- \r
- #if(SENSOR_CIF_BUSID_0 == RK_CAM_PLATFORM_DEV_ID_0)\r
- #define PMEM_SENSOR_FULL_RESOLUTION_CIF_0 PMEM_SENSOR_FULL_RESOLUTION_0\r
- #define PMEM_SENSOR_FULL_RESOLUTION_CIF_1 0\r
- #else\r
- #define PMEM_SENSOR_FULL_RESOLUTION_CIF_1 PMEM_SENSOR_FULL_RESOLUTION_0\r
- #define PMEM_SENSOR_FULL_RESOLUTION_CIF_0 0\r
- #endif\r
-#else\r
-#define PMEM_SENSOR_FULL_RESOLUTION_CIF_0 0x00\r
-#define PMEM_SENSOR_FULL_RESOLUTION_CIF_1 0x00\r
-#endif\r
- \r
-#if defined (CONFIG_SENSOR_IIC_ADDR_1) && (CONFIG_SENSOR_IIC_ADDR_1 != 0x00)\r
-#define PMEM_SENSOR_FULL_RESOLUTION_1 CONS(CONFIG_SENSOR_1,_FULL_RESOLUTION)\r
-\r
- #ifdef CONFIG_SENSOR_CIF_INDEX_1\r
- #define SENSOR_CIF_BUSID_1 CONS(RK_CAM_PLATFORM_DEV_ID_,CONFIG_SENSOR_CIF_INDEX_1)\r
- #else\r
- #define SENSOR_CIF_BUSID_1 RK29_CAM_PLATFORM_DEV_ID\r
- #endif\r
- \r
- #if !(PMEM_SENSOR_FULL_RESOLUTION_1)\r
- #undef PMEM_SENSOR_FULL_RESOLUTION_1\r
- #define PMEM_SENSOR_FULL_RESOLUTION_1 RK_CAM_SUPPORT_RESOLUTION\r
- #endif\r
- #if (SENSOR_CIF_BUSID_1 == RK_CAM_PLATFORM_DEV_ID_0)\r
- #if (PMEM_SENSOR_FULL_RESOLUTION_CIF_0 < PMEM_SENSOR_FULL_RESOLUTION_1)\r
- #undef PMEM_SENSOR_FULL_RESOLUTION_CIF_0\r
- #define PMEM_SENSOR_FULL_RESOLUTION_CIF_0 PMEM_SENSOR_FULL_RESOLUTION_1\r
- #endif\r
- #else\r
- #if (PMEM_SENSOR_FULL_RESOLUTION_CIF_1 < PMEM_SENSOR_FULL_RESOLUTION_1)\r
- #undef PMEM_SENSOR_FULL_RESOLUTION_CIF_1\r
- #define PMEM_SENSOR_FULL_RESOLUTION_CIF_1 PMEM_SENSOR_FULL_RESOLUTION_1\r
- #endif\r
- #endif\r
-#endif\r
-\r
-#if defined (CONFIG_SENSOR_IIC_ADDR_01) && (CONFIG_SENSOR_IIC_ADDR_01!=0x00)\r
-#define PMEM_SENSOR_FULL_RESOLUTION_01 CONS(CONFIG_SENSOR_01,_FULL_RESOLUTION)\r
-\r
- #ifdef CONFIG_SENSOR_CIF_INDEX_01\r
- #define SENSOR_CIF_BUSID_01 CONS(RK_CAM_PLATFORM_DEV_ID_,CONFIG_SENSOR_CIF_INDEX_01)\r
- #else\r
- #define SENSOR_CIF_BUSID_01 RK29_CAM_PLATFORM_DEV_ID\r
- #endif\r
- \r
- #if !(PMEM_SENSOR_FULL_RESOLUTION_01)\r
- #undef PMEM_SENSOR_FULL_RESOLUTION_01\r
- #define PMEM_SENSOR_FULL_RESOLUTION_01 RK_CAM_SUPPORT_RESOLUTION\r
- #endif\r
- #if (SENSOR_CIF_BUSID_01 == RK_CAM_PLATFORM_DEV_ID_0)\r
- #if (PMEM_SENSOR_FULL_RESOLUTION_CIF_0 < PMEM_SENSOR_FULL_RESOLUTION_01)\r
- #undef PMEM_SENSOR_FULL_RESOLUTION_CIF_0\r
- #define PMEM_SENSOR_FULL_RESOLUTION_CIF_0 PMEM_SENSOR_FULL_RESOLUTION_01\r
- #endif\r
- #else\r
- #if (PMEM_SENSOR_FULL_RESOLUTION_CIF_1 < PMEM_SENSOR_FULL_RESOLUTION_01)\r
- #undef PMEM_SENSOR_FULL_RESOLUTION_CIF_1\r
- #define PMEM_SENSOR_FULL_RESOLUTION_CIF_1 PMEM_SENSOR_FULL_RESOLUTION_01\r
- #endif\r
- #endif\r
-#endif\r
-\r
-#if defined (CONFIG_SENSOR_IIC_ADDR_02) && (CONFIG_SENSOR_IIC_ADDR_02!=0x00)\r
-#define PMEM_SENSOR_FULL_RESOLUTION_02 CONS(CONFIG_SENSOR_02,_FULL_RESOLUTION)\r
-\r
- #ifdef CONFIG_SENSOR_CIF_INDEX_02\r
- #define SENSOR_CIF_BUSID_02 CONS(RK_CAM_PLATFORM_DEV_ID_,CONFIG_SENSOR_CIF_INDEX_02)\r
- #else\r
- #define SENSOR_CIF_BUSID_02 RK29_CAM_PLATFORM_DEV_ID\r
- #endif\r
- \r
- #if !(PMEM_SENSOR_FULL_RESOLUTION_02)\r
- #undef PMEM_SENSOR_FULL_RESOLUTION_02\r
- #define PMEM_SENSOR_FULL_RESOLUTION_02 RK_CAM_SUPPORT_RESOLUTION\r
- #endif\r
- #if (SENSOR_CIF_BUSID_02 == RK_CAM_PLATFORM_DEV_ID_0)\r
- #if (PMEM_SENSOR_FULL_RESOLUTION_CIF_0 < PMEM_SENSOR_FULL_RESOLUTION_02)\r
- #undef PMEM_SENSOR_FULL_RESOLUTION_CIF_0\r
- #define PMEM_SENSOR_FULL_RESOLUTION_CIF_0 PMEM_SENSOR_FULL_RESOLUTION_02\r
- #endif\r
- #else\r
- #if (PMEM_SENSOR_FULL_RESOLUTION_CIF_1 < PMEM_SENSOR_FULL_RESOLUTION_02)\r
- #undef PMEM_SENSOR_FULL_RESOLUTION_CIF_1\r
- #define PMEM_SENSOR_FULL_RESOLUTION_CIF_1 PMEM_SENSOR_FULL_RESOLUTION_02\r
- #endif\r
- #endif\r
-#endif\r
-\r
-#ifdef CONFIG_SENSOR_IIC_ADDR_11\r
-#if (CONFIG_SENSOR_IIC_ADDR_11 != 0x00)\r
-#define PMEM_SENSOR_FULL_RESOLUTION_11 CONS(CONFIG_SENSOR_11,_FULL_RESOLUTION)\r
-\r
- #ifdef CONFIG_SENSOR_CIF_INDEX_11\r
- #define SENSOR_CIF_BUSID_11 CONS(RK_CAM_PLATFORM_DEV_ID_,CONFIG_SENSOR_CIF_INDEX_11)\r
- #else\r
- #define SENSOR_CIF_BUSID_11 RK29_CAM_PLATFORM_DEV_ID\r
- #endif\r
- \r
- #if !(PMEM_SENSOR_FULL_RESOLUTION_11)\r
- #undef PMEM_SENSOR_FULL_RESOLUTION_11\r
- #define PMEM_SENSOR_FULL_RESOLUTION_11 RK_CAM_SUPPORT_RESOLUTION\r
- #endif\r
- #if (SENSOR_CIF_BUSID_11 == RK_CAM_PLATFORM_DEV_ID_0)\r
- #if (PMEM_SENSOR_FULL_RESOLUTION_CIF_0 < PMEM_SENSOR_FULL_RESOLUTION_11)\r
- #undef PMEM_SENSOR_FULL_RESOLUTION_CIF_0\r
- #define PMEM_SENSOR_FULL_RESOLUTION_CIF_0 PMEM_SENSOR_FULL_RESOLUTION_11\r
- #endif\r
- #else\r
- #if (PMEM_SENSOR_FULL_RESOLUTION_CIF_1 < PMEM_SENSOR_FULL_RESOLUTION_11)\r
- #undef PMEM_SENSOR_FULL_RESOLUTION_CIF_1\r
- #define PMEM_SENSOR_FULL_RESOLUTION_CIF_1 PMEM_SENSOR_FULL_RESOLUTION_11\r
- #endif\r
- #endif\r
-#endif\r
-#endif\r
-\r
-\r
-#ifdef CONFIG_SENSOR_IIC_ADDR_12\r
-#if (CONFIG_SENSOR_IIC_ADDR_12 != 0x00)\r
-#define PMEM_SENSOR_FULL_RESOLUTION_12 CONS(CONFIG_SENSOR_12,_FULL_RESOLUTION)\r
-\r
- #ifdef CONFIG_SENSOR_CIF_INDEX_12\r
- #define SENSOR_CIF_BUSID_12 CONS(RK_CAM_PLATFORM_DEV_ID_,CONFIG_SENSOR_CIF_INDEX_12)\r
- #else\r
- #define SENSOR_CIF_BUSID_12 RK29_CAM_PLATFORM_DEV_ID\r
- #endif\r
- \r
- #if !(PMEM_SENSOR_FULL_RESOLUTION_12)\r
- #undef PMEM_SENSOR_FULL_RESOLUTION_12\r
- #define PMEM_SENSOR_FULL_RESOLUTION_12 RK_CAM_SUPPORT_RESOLUTION\r
- #endif\r
- #if (SENSOR_CIF_BUSID_12 == RK_CAM_PLATFORM_DEV_ID_0)\r
- #if (PMEM_SENSOR_FULL_RESOLUTION_CIF_0 < PMEM_SENSOR_FULL_RESOLUTION_12)\r
- #undef PMEM_SENSOR_FULL_RESOLUTION_CIF_0\r
- #define PMEM_SENSOR_FULL_RESOLUTION_CIF_0 PMEM_SENSOR_FULL_RESOLUTION_12\r
- #endif\r
- #else\r
- #if (PMEM_SENSOR_FULL_RESOLUTION_CIF_1 < PMEM_SENSOR_FULL_RESOLUTION_12)\r
- #undef PMEM_SENSOR_FULL_RESOLUTION_CIF_1\r
- #define PMEM_SENSOR_FULL_RESOLUTION_CIF_1 PMEM_SENSOR_FULL_RESOLUTION_12\r
- #endif\r
- #endif\r
-#endif\r
-#endif\r
-\r
-#if (PMEM_SENSOR_FULL_RESOLUTION_CIF_0 > RK_CAM_SUPPORT_RESOLUTION)\r
- #error "PMEM_SENSOR_FULL_RESOLUTION_CIF_0 is larger than 5Meag"\r
-#endif\r
-\r
-#if (PMEM_SENSOR_FULL_RESOLUTION_CIF_1 > RK_CAM_SUPPORT_RESOLUTION)\r
- #error "PMEM_SENSOR_FULL_RESOLUTION_CIF_1 is larger than 5Meag"\r
-#endif\r
-\r
-//CIF 0\r
-#if (PMEM_SENSOR_FULL_RESOLUTION_CIF_0 == 0x800000) /* ddl@rock-chips.com : It is only support 5Mega interplate to 8Mega */\r
-#define PMEM_CAM_NECESSARY_CIF_0 0x1900000 /* 1280*720*1.5*4(preview) + 12M(capture raw) + 7M(jpeg encode output) */\r
-#define PMEM_CAMIPP_NECESSARY_CIF_0 0x800000\r
-#elif (PMEM_SENSOR_FULL_RESOLUTION_CIF_0 == 0x500000)\r
-#define PMEM_CAM_NECESSARY_CIF_0 0x1400000 /* 1280*720*1.5*4(preview) + 7.5M(capture raw) + 4M(jpeg encode output) */\r
-#define PMEM_CAMIPP_NECESSARY_CIF_0 0x800000\r
-#elif (PMEM_SENSOR_FULL_RESOLUTION_CIF_0 == 0x300000)\r
-#define PMEM_CAM_NECESSARY_CIF_0 0xf00000 /* 1280*720*1.5*4(preview) + 4.5M(capture raw) + 3M(jpeg encode output) */\r
-#define PMEM_CAMIPP_NECESSARY_CIF_0 0x600000\r
-#elif (PMEM_SENSOR_FULL_RESOLUTION_CIF_0 == 0x200000) /* 1280*720*1.5*4(preview) + 3M(capture raw) + 3M(jpeg encode output) */\r
-#define PMEM_CAM_NECESSARY_CIF_0 0xc00000\r
-#define PMEM_CAMIPP_NECESSARY_CIF_0 0x600000\r
-#elif ((PMEM_SENSOR_FULL_RESOLUTION_CIF_0 == 0x100000) || (PMEM_SENSOR_FULL_RESOLUTION_CIF_0 == 0x130000))\r
-#define PMEM_CAM_NECESSARY_CIF_0 0xa00000 /* 800*600*1.5*4(preview) + 2M(capture raw) + 2M(jpeg encode output) */\r
-#define PMEM_CAMIPP_NECESSARY_CIF_0 0x600000\r
-#elif (PMEM_SENSOR_FULL_RESOLUTION_CIF_0 == 0x30000)\r
-#define PMEM_CAM_NECESSARY_CIF_0 0x600000 /* 640*480*1.5*4(preview) + 1M(capture raw) + 1M(jpeg encode output) */\r
-#define PMEM_CAMIPP_NECESSARY_CIF_0 0x600000\r
-#elif (PMEM_SENSOR_FULL_RESOLUTION_CIF_0 == 0x00)\r
-#define PMEM_CAM_NECESSARY_CIF_0 0x00\r
-#define PMEM_CAMIPP_NECESSARY_CIF_0 0x00\r
-#else\r
-#define PMEM_CAM_NECESSARY_CIF_0 0x1400000\r
-#define PMEM_CAMIPP_NECESSARY_CIF_0 0x800000\r
-#endif\r
-\r
-//CIF 1\r
-#if (PMEM_SENSOR_FULL_RESOLUTION_CIF_1 == 0x800000) /* ddl@rock-chips.com : It is only support 5Mega interplate to 8Mega */\r
-#define PMEM_CAM_NECESSARY_CIF_1 0x1900000 /* 1280*720*1.5*4(preview) + 12M(capture raw) + 7M(jpeg encode output) */\r
-#define PMEM_CAMIPP_NECESSARY_CIF_1 0x800000\r
-#elif (PMEM_SENSOR_FULL_RESOLUTION_CIF_1 == 0x500000)\r
-#define PMEM_CAM_NECESSARY_CIF_1 0x1400000 /* 1280*720*1.5*4(preview) + 7.5M(capture raw) + 4M(jpeg encode output) */\r
-#define PMEM_CAMIPP_NECESSARY_CIF_1 0x800000\r
-#elif (PMEM_SENSOR_FULL_RESOLUTION_CIF_1 == 0x300000)\r
-#define PMEM_CAM_NECESSARY_CIF_1 0xf00000 /* 1280*720*1.5*4(preview) + 4.5M(capture raw) + 3M(jpeg encode output) */\r
-#define PMEM_CAMIPP_NECESSARY_CIF_1 0x600000\r
-#elif (PMEM_SENSOR_FULL_RESOLUTION_CIF_1== 0x200000) /* 1280*720*1.5*4(preview) + 3M(capture raw) + 3M(jpeg encode output) */\r
-#define PMEM_CAM_NECESSARY_CIF_1 0xc00000\r
-#define PMEM_CAMIPP_NECESSARY_CIF_1 0x600000\r
-#elif ((PMEM_SENSOR_FULL_RESOLUTION_CIF_1 == 0x100000) || (PMEM_SENSOR_FULL_RESOLUTION_CIF_1 == 0x130000))\r
-#define PMEM_CAM_NECESSARY_CIF_1 0xa00000 /* 800*600*1.5*4(preview) + 2M(capture raw) + 2M(jpeg encode output) */\r
-#define PMEM_CAMIPP_NECESSARY_CIF_1 0x600000\r
-#elif (PMEM_SENSOR_FULL_RESOLUTION_CIF_1 == 0x30000)\r
-#define PMEM_CAM_NECESSARY_CIF_1 0x600000 /* 640*480*1.5*4(preview) + 1M(capture raw) + 1M(jpeg encode output) */\r
-#define PMEM_CAMIPP_NECESSARY_CIF_1 0x600000\r
-#elif (PMEM_SENSOR_FULL_RESOLUTION_CIF_1 == 0x00)\r
-#define PMEM_CAM_NECESSARY_CIF_1 0x00\r
-#define PMEM_CAMIPP_NECESSARY_CIF_1 0x00\r
-#else\r
-#define PMEM_CAM_NECESSARY_CIF_1 0x1400000\r
-#define PMEM_CAMIPP_NECESSARY_CIF_1 0x800000\r
-#endif\r
-\r
-\r
-#ifdef CONFIG_VIDEO_RKCIF_WORK_SIMUL_OFF\r
- #if (PMEM_CAM_NECESSARY_CIF_0 > PMEM_CAM_NECESSARY_CIF_1)\r
- #define PMEM_CAM_NECESSARY PMEM_CAM_NECESSARY_CIF_0\r
- #define PMEM_CAMIPP_NECESSARY PMEM_CAMIPP_NECESSARY_CIF_0\r
- #else\r
- #define PMEM_CAM_NECESSARY PMEM_CAM_NECESSARY_CIF_1\r
- #define PMEM_CAMIPP_NECESSARY PMEM_CAMIPP_NECESSARY_CIF_1\r
- #endif\r
-#endif\r
-\r
-#if (!defined(CONFIG_VIDEO_RKCIF_WORK_SIMUL_OFF) && !defined(CONFIG_VIDEO_RKCIF_WORK_SIMUL_ON))\r
- #if PMEM_CAM_NECESSARY_CIF_0\r
- #define PMEM_CAM_NECESSARY PMEM_CAM_NECESSARY_CIF_0\r
- #define PMEM_CAMIPP_NECESSARY PMEM_CAMIPP_NECESSARY_CIF_0 \r
- #else\r
- #define PMEM_CAM_NECESSARY PMEM_CAM_NECESSARY_CIF_1\r
- #define PMEM_CAMIPP_NECESSARY PMEM_CAMIPP_NECESSARY_CIF_1 \r
- #endif\r
-#endif\r
-\r
-#ifdef CONFIG_VIDEO_RK29_CAMMEM_ION\r
- #undef PMEM_CAM_NECESSARY\r
- #define PMEM_CAM_NECESSARY 0x00000000\r
-#endif\r
-\r
-\r
-/*---------------- Camera Sensor Fixed Macro End ------------------------*/\r
-#else //#ifdef CONFIG_VIDEO_RK \r
-#define PMEM_CAM_NECESSARY 0x00000000\r
-#endif\r
-\r
-#else // #ifndef PMEM_CAM_SIZE\r
-/*\r
-* Driver Version Note\r
-*v0.0.1: this driver is compatible with generic_sensor\r
-*v0.1.1:\r
-* Cam_Power return success in rk_sensor_ioctrl when power io havn't config;\r
-*v0.1.3:\r
-* 1. this version support fov configuration in new_camera_device;\r
-* 2. Reduce delay time after power off or power down camera;\r
-*v0.1.5:\r
-* 1. if sensor power callback failed, power down sensor;\r
-*v0.1.6:\r
- 1. when power down,HWRST just need to set to powerdown mode.\r
-*/\r
-static int camio_version = KERNEL_VERSION(0,1,6);\r
-module_param(camio_version, int, S_IRUGO);\r
-\r
-\r
-static int camera_debug;\r
-module_param(camera_debug, int, S_IRUGO|S_IWUSR); \r
-\r
-#undef CAMMODULE_NAME\r
-#define CAMMODULE_NAME "rk_cam_io"\r
-\r
-#define ddprintk(level, fmt, arg...) do { \\r
- if (camera_debug >= level) \\r
- printk(KERN_WARNING"%s(%d):" fmt"\n", CAMMODULE_NAME,__LINE__,## arg); } while (0)\r
-\r
-#define dprintk(format, ...) ddprintk(1, format, ## __VA_ARGS__) \r
-#define eprintk(format, ...) printk(KERN_ERR "%s(%d):" format"\n",CAMMODULE_NAME,__LINE__,## __VA_ARGS__) \r
-\r
-#define SENSOR_NAME_0 STR(CONFIG_SENSOR_0) /* back camera sensor 0 */\r
-#define SENSOR_NAME_1 STR(CONFIG_SENSOR_1) /* front camera sensor 0 */\r
-#define SENSOR_DEVICE_NAME_0 STR(CONS(CONFIG_SENSOR_0, _back))\r
-#define SENSOR_DEVICE_NAME_1 STR(CONS(CONFIG_SENSOR_1, _front))\r
-#ifdef CONFIG_SENSOR_01\r
-#define SENSOR_NAME_01 STR(CONFIG_SENSOR_01) /* back camera sensor 1 */\r
-#define SENSOR_DEVICE_NAME_01 STR(CONS(CONFIG_SENSOR_01, _back_1))\r
-#endif\r
-#ifdef CONFIG_SENSOR_02\r
-#define SENSOR_NAME_02 STR(CONFIG_SENSOR_02) /* back camera sensor 2 */\r
-#define SENSOR_DEVICE_NAME_02 STR(CONS(CONFIG_SENSOR_02, _back_2))\r
-#endif\r
-#ifdef CONFIG_SENSOR_11\r
-#define SENSOR_NAME_11 STR(CONFIG_SENSOR_11) /* front camera sensor 1 */\r
-#define SENSOR_DEVICE_NAME_11 STR(CONS(CONFIG_SENSOR_11, _front_1))\r
-#endif\r
-#ifdef CONFIG_SENSOR_12\r
-#define SENSOR_NAME_12 STR(CONFIG_SENSOR_12) /* front camera sensor 2 */\r
-#define SENSOR_DEVICE_NAME_12 STR(CONS(CONFIG_SENSOR_12, _front_2))\r
-#endif\r
-\r
-static int rk_sensor_io_init(void);\r
-static int rk_sensor_io_deinit(int sensor);\r
-static int rk_sensor_ioctrl(struct device *dev,enum rk29camera_ioctrl_cmd cmd, int on);\r
-static int rk_sensor_power(struct device *dev, int on);\r
-static int rk_sensor_register(void);\r
-//static int rk_sensor_reset(struct device *dev);\r
-\r
-static int rk_sensor_powerdown(struct device *dev, int on);\r
-\r
-static struct rk29camera_platform_data rk_camera_platform_data = {\r
- .io_init = rk_sensor_io_init,\r
- .io_deinit = rk_sensor_io_deinit,\r
- .iomux = rk_sensor_iomux,\r
- .sensor_ioctrl = rk_sensor_ioctrl,\r
- .sensor_register = rk_sensor_register,\r
- .gpio_res = {\r
- {\r
- #if defined CONFIG_SENSOR_IIC_ADDR_0 && CONFIG_SENSOR_IIC_ADDR_0 \r
- .gpio_reset = CONFIG_SENSOR_RESET_PIN_0,\r
- .gpio_power = CONFIG_SENSOR_POWER_PIN_0,\r
- .gpio_powerdown = CONFIG_SENSOR_POWERDN_PIN_0,\r
- .gpio_flash = CONFIG_SENSOR_FALSH_PIN_0,\r
- .gpio_flag = (CONFIG_SENSOR_POWERACTIVE_LEVEL_0|CONFIG_SENSOR_RESETACTIVE_LEVEL_0|CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0|CONFIG_SENSOR_FLASHACTIVE_LEVEL_0),\r
- .gpio_init = 0, \r
- .dev_name = SENSOR_DEVICE_NAME_0,\r
- #else\r
- .gpio_reset = INVALID_GPIO,\r
- .gpio_power = INVALID_GPIO,\r
- .gpio_powerdown = INVALID_GPIO,\r
- .gpio_flash = INVALID_GPIO,\r
- .gpio_flag = 0,\r
- .gpio_init = 0, \r
- .dev_name = NULL,\r
- #endif\r
- }, {\r
- #if defined CONFIG_SENSOR_IIC_ADDR_1 && CONFIG_SENSOR_IIC_ADDR_1 \r
- .gpio_reset = CONFIG_SENSOR_RESET_PIN_1,\r
- .gpio_power = CONFIG_SENSOR_POWER_PIN_1,\r
- .gpio_powerdown = CONFIG_SENSOR_POWERDN_PIN_1,\r
- .gpio_flash = CONFIG_SENSOR_FALSH_PIN_1,\r
- .gpio_flag = (CONFIG_SENSOR_POWERACTIVE_LEVEL_1|CONFIG_SENSOR_RESETACTIVE_LEVEL_1|CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1|CONFIG_SENSOR_FLASHACTIVE_LEVEL_1),\r
- .gpio_init = 0,\r
- .dev_name = SENSOR_DEVICE_NAME_1,\r
- #else\r
- .gpio_reset = INVALID_GPIO,\r
- .gpio_power = INVALID_GPIO,\r
- .gpio_powerdown = INVALID_GPIO,\r
- .gpio_flash = INVALID_GPIO,\r
- .gpio_flag = 0,\r
- .gpio_init = 0, \r
- .dev_name = NULL,\r
- #endif\r
- }, \r
- #ifdef CONFIG_SENSOR_01\r
- {\r
- #if CONFIG_SENSOR_IIC_ADDR_01\r
- .gpio_reset = CONFIG_SENSOR_RESET_PIN_01,\r
- .gpio_power = CONFIG_SENSOR_POWER_PIN_01,\r
- .gpio_powerdown = CONFIG_SENSOR_POWERDN_PIN_01,\r
- .gpio_flash = CONFIG_SENSOR_FALSH_PIN_01,\r
- .gpio_flag = (CONFIG_SENSOR_POWERACTIVE_LEVEL_01|CONFIG_SENSOR_RESETACTIVE_LEVEL_01|CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01|CONFIG_SENSOR_FLASHACTIVE_LEVEL_01),\r
- .gpio_init = 0, \r
- .dev_name = SENSOR_DEVICE_NAME_01,\r
- #else\r
- .gpio_reset = INVALID_GPIO,\r
- .gpio_power = INVALID_GPIO,\r
- .gpio_powerdown = INVALID_GPIO,\r
- .gpio_flash = INVALID_GPIO,\r
- .gpio_flag = 0,\r
- .gpio_init = 0, \r
- .dev_name = NULL,\r
- #endif\r
- }, \r
- #endif\r
- #ifdef CONFIG_SENSOR_02\r
- {\r
- #if CONFIG_SENSOR_IIC_ADDR_02\r
- .gpio_reset = CONFIG_SENSOR_RESET_PIN_02,\r
- .gpio_power = CONFIG_SENSOR_POWER_PIN_02,\r
- .gpio_powerdown = CONFIG_SENSOR_POWERDN_PIN_02,\r
- .gpio_flash = CONFIG_SENSOR_FALSH_PIN_02,\r
- .gpio_flag = (CONFIG_SENSOR_POWERACTIVE_LEVEL_02|CONFIG_SENSOR_RESETACTIVE_LEVEL_02|CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02|CONFIG_SENSOR_FLASHACTIVE_LEVEL_02),\r
- .gpio_init = 0, \r
- .dev_name = SENSOR_DEVICE_NAME_02, \r
- #else\r
- .gpio_reset = INVALID_GPIO,\r
- .gpio_power = INVALID_GPIO,\r
- .gpio_powerdown = INVALID_GPIO,\r
- .gpio_flash = INVALID_GPIO,\r
- .gpio_flag = 0,\r
- .gpio_init = 0, \r
- .dev_name = NULL,\r
- #endif \r
- },\r
- #endif\r
- #ifdef CONFIG_SENSOR_11\r
- {\r
- #if CONFIG_SENSOR_IIC_ADDR_11\r
- .gpio_reset = CONFIG_SENSOR_RESET_PIN_11,\r
- .gpio_power = CONFIG_SENSOR_POWER_PIN_11,\r
- .gpio_powerdown = CONFIG_SENSOR_POWERDN_PIN_11,\r
- .gpio_flash = CONFIG_SENSOR_FALSH_PIN_11,\r
- .gpio_flag = (CONFIG_SENSOR_POWERACTIVE_LEVEL_11|CONFIG_SENSOR_RESETACTIVE_LEVEL_11|CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11|CONFIG_SENSOR_FLASHACTIVE_LEVEL_11),\r
- .gpio_init = 0,\r
- .dev_name = SENSOR_DEVICE_NAME_11,\r
- #else\r
- .gpio_reset = INVALID_GPIO,\r
- .gpio_power = INVALID_GPIO,\r
- .gpio_powerdown = INVALID_GPIO,\r
- .gpio_flash = INVALID_GPIO,\r
- .gpio_flag = 0,\r
- .gpio_init = 0, \r
- .dev_name = NULL,\r
- #endif \r
- }, \r
- #endif\r
- #ifdef CONFIG_SENSOR_12\r
- {\r
- #if CONFIG_SENSOR_IIC_ADDR_12\r
- .gpio_reset = CONFIG_SENSOR_RESET_PIN_12,\r
- .gpio_power = CONFIG_SENSOR_POWER_PIN_12,\r
- .gpio_powerdown = CONFIG_SENSOR_POWERDN_PIN_12,\r
- .gpio_flash = CONFIG_SENSOR_FALSH_PIN_12,\r
- .gpio_flag = (CONFIG_SENSOR_POWERACTIVE_LEVEL_12|CONFIG_SENSOR_RESETACTIVE_LEVEL_12|CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12|CONFIG_SENSOR_FLASHACTIVE_LEVEL_12),\r
- .gpio_init = 0,\r
- .dev_name = SENSOR_DEVICE_NAME_12,\r
- #else\r
- .gpio_reset = INVALID_GPIO,\r
- .gpio_power = INVALID_GPIO,\r
- .gpio_powerdown = INVALID_GPIO,\r
- .gpio_flash = INVALID_GPIO,\r
- .gpio_flag = 0,\r
- .gpio_init = 0, \r
- .dev_name = NULL,\r
- #endif\r
- }\r
- #endif\r
- },\r
- \r
- #ifdef CONFIG_VIDEO_RK29_WORK_IPP\r
- #ifdef MEM_CAMIPP_BASE\r
- .meminfo = {\r
- .name = "camera_ipp_mem",\r
- .start = MEM_CAMIPP_BASE,\r
- .size = MEM_CAMIPP_SIZE,\r
- },\r
- #endif\r
- #endif\r
- \r
- .info = {\r
- {\r
- #ifdef CONFIG_SENSOR_0 \r
- .dev_name = SENSOR_DEVICE_NAME_0,\r
- .orientation = CONFIG_SENSOR_ORIENTATION_0, \r
- #else\r
- .dev_name = NULL,\r
- .orientation = 0x00, \r
- #endif\r
- },{\r
- #ifdef CONFIG_SENSOR_1\r
- .dev_name = SENSOR_DEVICE_NAME_1,\r
- .orientation = CONFIG_SENSOR_ORIENTATION_1,\r
- #else\r
- .dev_name = NULL,\r
- .orientation = 0x00, \r
- #endif\r
- #ifdef CONFIG_SENSOR_01\r
- },{\r
- .dev_name = SENSOR_DEVICE_NAME_01,\r
- .orientation = CONFIG_SENSOR_ORIENTATION_01, \r
- #else\r
- },{\r
- .dev_name = NULL,\r
- .orientation = 0x00, \r
- #endif\r
- #ifdef CONFIG_SENSOR_02\r
- },{\r
- .dev_name = SENSOR_DEVICE_NAME_02,\r
- .orientation = CONFIG_SENSOR_ORIENTATION_02, \r
- #else\r
- },{\r
- .dev_name = NULL,\r
- .orientation = 0x00, \r
- #endif\r
- \r
- #ifdef CONFIG_SENSOR_11 \r
- },{\r
- .dev_name = SENSOR_DEVICE_NAME_11,\r
- .orientation = CONFIG_SENSOR_ORIENTATION_11, \r
- #else\r
- },{\r
- .dev_name = NULL,\r
- .orientation = 0x00, \r
- #endif\r
- #ifdef CONFIG_SENSOR_12\r
- },{\r
- .dev_name = SENSOR_DEVICE_NAME_12,\r
- .orientation = CONFIG_SENSOR_ORIENTATION_12, \r
- #else\r
- },{\r
- .dev_name = NULL,\r
- .orientation = 0x00, \r
- #endif\r
- },\r
- },\r
- \r
- .register_dev = {\r
- #ifdef CONFIG_SENSOR_0\r
- {\r
- #if (CONFIG_SENSOR_IIC_ADDR_0 != 0x00)\r
- .i2c_cam_info = {\r
- I2C_BOARD_INFO(SENSOR_NAME_0, CONFIG_SENSOR_IIC_ADDR_0>>1),\r
- },\r
- .link_info = {\r
- #ifdef SENSOR_CIF_BUSID_0\r
- .bus_id= SENSOR_CIF_BUSID_0,\r
- #else\r
- .bus_id= RK29_CAM_PLATFORM_DEV_ID,\r
- #endif\r
- .power = rk_sensor_power,\r
- #if (CONFIG_SENSOR_RESET_PIN_0 != INVALID_GPIO)\r
- .reset = rk_sensor_reset,\r
- #endif \r
- .powerdown = rk_sensor_powerdown,\r
- //.board_info = &rk_i2c_cam_info_0[0],\r
- \r
- .i2c_adapter_id = CONFIG_SENSOR_IIC_ADAPTER_ID_0,\r
- .module_name = SENSOR_NAME_0,\r
- },\r
- .device_info = {\r
- .name = "soc-camera-pdrv",\r
- //.id = 0,\r
- .dev = {\r
- .init_name = SENSOR_DEVICE_NAME_0,\r
- //.platform_data = &rk_iclink_0,\r
- }\r
- }\r
- #endif\r
- },\r
- #endif\r
- #ifdef CONFIG_SENSOR_1\r
- {\r
- #if (CONFIG_SENSOR_IIC_ADDR_1 != 0x00)\r
- .i2c_cam_info = {\r
- I2C_BOARD_INFO(SENSOR_NAME_1, CONFIG_SENSOR_IIC_ADDR_1>>1)\r
- },\r
- .link_info = {\r
- #ifdef SENSOR_CIF_BUSID_1\r
- .bus_id= SENSOR_CIF_BUSID_1,\r
- #else\r
- .bus_id= RK29_CAM_PLATFORM_DEV_ID,\r
- #endif\r
- .power = rk_sensor_power,\r
- #if (CONFIG_SENSOR_RESET_PIN_1 != INVALID_GPIO)\r
- .reset = rk_sensor_reset,\r
- #endif \r
- .powerdown = rk_sensor_powerdown,\r
- //.board_info = &rk_i2c_cam_info_0[0],\r
- \r
- .i2c_adapter_id = CONFIG_SENSOR_IIC_ADAPTER_ID_1,\r
- .module_name = SENSOR_NAME_1,\r
- },\r
- .device_info = {\r
- .name = "soc-camera-pdrv",\r
- //.id = 1,\r
- .dev = {\r
- .init_name = SENSOR_DEVICE_NAME_1,\r
- //.platform_data = &rk_iclink_0,\r
- }\r
- }\r
- #endif\r
- },\r
- #endif\r
- #ifdef CONFIG_SENSOR_01\r
- {\r
- #if (CONFIG_SENSOR_IIC_ADDR_01 != 0x00)\r
- .i2c_cam_info = {\r
- I2C_BOARD_INFO(SENSOR_NAME_01, CONFIG_SENSOR_IIC_ADDR_01>>1)\r
- },\r
- .link_info = {\r
- #ifdef SENSOR_CIF_BUSID_01\r
- .bus_id= SENSOR_CIF_BUSID_01,\r
- #else\r
- .bus_id= RK29_CAM_PLATFORM_DEV_ID,\r
- #endif\r
- .power = rk_sensor_power,\r
- #if (CONFIG_SENSOR_RESET_PIN_01 != INVALID_GPIO)\r
- .reset = rk_sensor_reset,\r
- #endif \r
- .powerdown = rk_sensor_powerdown,\r
- //.board_info = &rk_i2c_cam_info_0[0],\r
- \r
- .i2c_adapter_id = CONFIG_SENSOR_IIC_ADAPTER_ID_01,\r
- .module_name = SENSOR_NAME_01,\r
- },\r
- .device_info = {\r
- .name = "soc-camera-pdrv",\r
- //.id = 1,\r
- .dev = {\r
- .init_name = SENSOR_DEVICE_NAME_01,\r
- //.platform_data = &rk_iclink_0,\r
- }\r
- }\r
- #endif\r
- },\r
- #endif\r
- #ifdef CONFIG_SENSOR_02 \r
- {\r
- #if (CONFIG_SENSOR_IIC_ADDR_02 != 0x00)\r
- .i2c_cam_info = {\r
- I2C_BOARD_INFO(SENSOR_NAME_02, CONFIG_SENSOR_IIC_ADDR_02>>1)\r
- },\r
- .link_info = {\r
- #ifdef SENSOR_CIF_BUSID_02\r
- .bus_id= SENSOR_CIF_BUSID_02,\r
- #else\r
- .bus_id= RK29_CAM_PLATFORM_DEV_ID,\r
- #endif\r
- .power = rk_sensor_power,\r
- #if (CONFIG_SENSOR_RESET_PIN_02 != INVALID_GPIO)\r
- .reset = rk_sensor_reset,\r
- #endif \r
- .powerdown = rk_sensor_powerdown,\r
- //.board_info = &rk_i2c_cam_info_0[0],\r
- \r
- .i2c_adapter_id = CONFIG_SENSOR_IIC_ADAPTER_ID_02,\r
- .module_name = SENSOR_NAME_02,\r
- },\r
- .device_info = {\r
- .name = "soc-camera-pdrv",\r
- //.id = 1,\r
- .dev = {\r
- .init_name = SENSOR_DEVICE_NAME_02,\r
- //.platform_data = &rk_iclink_0,\r
- }\r
- }\r
- #endif\r
- },\r
- #endif\r
- #ifdef CONFIG_SENSOR_11\r
- { \r
- #if (CONFIG_SENSOR_IIC_ADDR_11 != 0x00)\r
- .i2c_cam_info = {\r
- I2C_BOARD_INFO(SENSOR_NAME_11, CONFIG_SENSOR_IIC_ADDR_11>>1)\r
- },\r
- .link_info = {\r
- #ifdef SENSOR_CIF_BUSID_11\r
- .bus_id= SENSOR_CIF_BUSID_11,\r
- #else\r
- .bus_id= RK29_CAM_PLATFORM_DEV_ID,\r
- #endif\r
- .power = rk_sensor_power,\r
- #if (CONFIG_SENSOR_RESET_PIN_11 != INVALID_GPIO)\r
- .reset = rk_sensor_reset,\r
- #endif \r
- .powerdown = rk_sensor_powerdown,\r
- //.board_info = &rk_i2c_cam_info_0[0],\r
- \r
- .i2c_adapter_id = CONFIG_SENSOR_IIC_ADAPTER_ID_11,\r
- .module_name = SENSOR_NAME_11,\r
- },\r
- .device_info = {\r
- .name = "soc-camera-pdrv",\r
- //.id = 1,\r
- .dev = {\r
- .init_name = SENSOR_DEVICE_NAME_11,\r
- //.platform_data = &rk_iclink_0,\r
- }\r
- }\r
- #endif \r
- },\r
- #endif\r
- #ifdef CONFIG_SENSOR_12\r
- { \r
- #if (CONFIG_SENSOR_IIC_ADDR_12 != 0x00)\r
- .i2c_cam_info = {\r
- I2C_BOARD_INFO(SENSOR_NAME_12, CONFIG_SENSOR_IIC_ADDR_12>>1)\r
- },\r
- .link_info = {\r
- #ifdef SENSOR_CIF_BUSID_12\r
- .bus_id= SENSOR_CIF_BUSID_12,\r
- #else\r
- .bus_id= RK29_CAM_PLATFORM_DEV_ID,\r
- #endif\r
- .power = rk_sensor_power,\r
- #if (CONFIG_SENSOR_RESET_PIN_12 != INVALID_GPIO)\r
- .reset = rk_sensor_reset,\r
- #endif \r
- .powerdown = rk_sensor_powerdown,\r
- //.board_info = &rk_i2c_cam_info_0[0],\r
- \r
- .i2c_adapter_id = CONFIG_SENSOR_IIC_ADAPTER_ID_12,\r
- .module_name = SENSOR_NAME_12,\r
- },\r
- .device_info = {\r
- .name = "soc-camera-pdrv",\r
- //.id = 1,\r
- .dev = {\r
- .init_name = SENSOR_DEVICE_NAME_12,\r
- //.platform_data = &rk_iclink_0,\r
- }\r
- }\r
- #endif \r
- },\r
- #endif\r
- },\r
- .register_dev_new = new_camera,\r
-};\r
-\r
-\r
-static int sensor_power_default_cb (struct rk29camera_gpio_res *res, int on)\r
-{\r
- int camera_power = res->gpio_power;\r
- int camera_ioflag = res->gpio_flag;\r
- int camera_io_init = res->gpio_init;\r
- int ret = 0;\r
- \r
- if (camera_power != INVALID_GPIO) {\r
- if (camera_io_init & RK29_CAM_POWERACTIVE_MASK) {\r
- if (on) {\r
- gpio_set_value(camera_power, ((camera_ioflag&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));\r
- dprintk("%s PowerPin=%d ..PinLevel = %x",res->dev_name, camera_power, ((camera_ioflag&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));\r
- msleep(10);\r
- } else {\r
- gpio_set_value(camera_power, (((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));\r
- dprintk("%s PowerPin=%d ..PinLevel = %x",res->dev_name, camera_power, (((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));\r
- }\r
- } else {\r
- ret = RK29_CAM_EIO_REQUESTFAIL;\r
- eprintk("%s PowerPin=%d request failed!", res->dev_name,camera_power);\r
- } \r
- } else {\r
- ret = RK29_CAM_EIO_INVALID;\r
- } \r
-\r
- return ret;\r
-}\r
-\r
-static int sensor_reset_default_cb (struct rk29camera_gpio_res *res, int on)\r
-{\r
- int camera_reset = res->gpio_reset;\r
- int camera_ioflag = res->gpio_flag;\r
- int camera_io_init = res->gpio_init; \r
- int ret = 0;\r
- \r
- if (camera_reset != INVALID_GPIO) {\r
- if (camera_io_init & RK29_CAM_RESETACTIVE_MASK) {\r
- if (on) {\r
- gpio_set_value(camera_reset, ((camera_ioflag&RK29_CAM_RESETACTIVE_MASK)>>RK29_CAM_RESETACTIVE_BITPOS));\r
- dprintk("%s ResetPin=%d ..PinLevel = %x",res->dev_name,camera_reset, ((camera_ioflag&RK29_CAM_RESETACTIVE_MASK)>>RK29_CAM_RESETACTIVE_BITPOS));\r
- } else {\r
- gpio_set_value(camera_reset,(((~camera_ioflag)&RK29_CAM_RESETACTIVE_MASK)>>RK29_CAM_RESETACTIVE_BITPOS));\r
- dprintk("%s ResetPin= %d..PinLevel = %x",res->dev_name, camera_reset, (((~camera_ioflag)&RK29_CAM_RESETACTIVE_MASK)>>RK29_CAM_RESETACTIVE_BITPOS));\r
- }\r
- } else {\r
- ret = RK29_CAM_EIO_REQUESTFAIL;\r
- eprintk("%s ResetPin=%d request failed!", res->dev_name,camera_reset);\r
- }\r
- } else {\r
- ret = RK29_CAM_EIO_INVALID;\r
- }\r
-\r
- return ret;\r
-}\r
-\r
-static int sensor_powerdown_default_cb (struct rk29camera_gpio_res *res, int on)\r
-{\r
- int camera_powerdown = res->gpio_powerdown;\r
- int camera_ioflag = res->gpio_flag;\r
- int camera_io_init = res->gpio_init; \r
- int ret = 0; \r
-\r
- if (camera_powerdown != INVALID_GPIO) {\r
- if (camera_io_init & RK29_CAM_POWERDNACTIVE_MASK) {\r
- if (on) {\r
- gpio_set_value(camera_powerdown, ((camera_ioflag&RK29_CAM_POWERDNACTIVE_MASK)>>RK29_CAM_POWERDNACTIVE_BITPOS));\r
- dprintk("%s PowerDownPin=%d ..PinLevel = %x" ,res->dev_name,camera_powerdown, ((camera_ioflag&RK29_CAM_POWERDNACTIVE_MASK)>>RK29_CAM_POWERDNACTIVE_BITPOS));\r
- } else {\r
- gpio_set_value(camera_powerdown,(((~camera_ioflag)&RK29_CAM_POWERDNACTIVE_MASK)>>RK29_CAM_POWERDNACTIVE_BITPOS));\r
- dprintk("%s PowerDownPin= %d..PinLevel = %x" ,res->dev_name, camera_powerdown, (((~camera_ioflag)&RK29_CAM_POWERDNACTIVE_MASK)>>RK29_CAM_POWERDNACTIVE_BITPOS));\r
- }\r
- } else {\r
- ret = RK29_CAM_EIO_REQUESTFAIL;\r
- dprintk("%s PowerDownPin=%d request failed!", res->dev_name,camera_powerdown);\r
- }\r
- } else {\r
- ret = RK29_CAM_EIO_INVALID;\r
- }\r
- return ret;\r
-}\r
-\r
-\r
-static int sensor_flash_default_cb (struct rk29camera_gpio_res *res, int on)\r
-{\r
- int camera_flash = res->gpio_flash;\r
- int camera_ioflag = res->gpio_flag;\r
- int camera_io_init = res->gpio_init; \r
- int ret = 0; \r
-\r
- if (camera_flash != INVALID_GPIO) {\r
- if (camera_io_init & RK29_CAM_FLASHACTIVE_MASK) {\r
- switch (on)\r
- {\r
- case Flash_Off:\r
- {\r
- gpio_set_value(camera_flash,(((~camera_ioflag)&RK29_CAM_FLASHACTIVE_MASK)>>RK29_CAM_FLASHACTIVE_BITPOS));\r
- dprintk("%s FlashPin= %d..PinLevel = %x", res->dev_name, camera_flash, (((~camera_ioflag)&RK29_CAM_FLASHACTIVE_MASK)>>RK29_CAM_FLASHACTIVE_BITPOS)); \r
- break;\r
- }\r
-\r
- case Flash_On:\r
- {\r
- gpio_set_value(camera_flash, ((camera_ioflag&RK29_CAM_FLASHACTIVE_MASK)>>RK29_CAM_FLASHACTIVE_BITPOS));\r
- dprintk("%s FlashPin=%d ..PinLevel = %x", res->dev_name,camera_flash, ((camera_ioflag&RK29_CAM_FLASHACTIVE_MASK)>>RK29_CAM_FLASHACTIVE_BITPOS));\r
- break;\r
- }\r
-\r
- case Flash_Torch:\r
- {\r
- gpio_set_value(camera_flash, ((camera_ioflag&RK29_CAM_FLASHACTIVE_MASK)>>RK29_CAM_FLASHACTIVE_BITPOS));\r
- dprintk("%s FlashPin=%d ..PinLevel = %x", res->dev_name,camera_flash, ((camera_ioflag&RK29_CAM_FLASHACTIVE_MASK)>>RK29_CAM_FLASHACTIVE_BITPOS));\r
- break;\r
- }\r
-\r
- default:\r
- {\r
- eprintk("%s Flash command(%d) is invalidate", res->dev_name,on);\r
- break;\r
- }\r
- }\r
- } else {\r
- ret = RK29_CAM_EIO_REQUESTFAIL;\r
- eprintk("%s FlashPin=%d request failed!", res->dev_name,camera_flash);\r
- }\r
- } else {\r
- ret = RK29_CAM_EIO_INVALID;\r
- }\r
- return ret;\r
-}\r
-static void rk29_sensor_fps_get(int idx, unsigned int *val, int w, int h)\r
-{\r
- switch (idx)\r
- {\r
- #ifdef CONFIG_SENSOR_0\r
- case 0:\r
- {\r
- if ((w==176) && (h==144)) {\r
- *val = CONFIG_SENSOR_QCIF_FPS_FIXED_0;\r
- #ifdef CONFIG_SENSOR_240X160_FPS_FIXED_0\r
- } else if ((w==240) && (h==160)) {\r
- *val = CONFIG_SENSOR_240X160_FPS_FIXED_0;\r
- #endif\r
- } else if ((w==320) && (h==240)) {\r
- *val = CONFIG_SENSOR_QVGA_FPS_FIXED_0;\r
- } else if ((w==352) && (h==288)) {\r
- *val = CONFIG_SENSOR_CIF_FPS_FIXED_0;\r
- } else if ((w==640) && (h==480)) {\r
- *val = CONFIG_SENSOR_VGA_FPS_FIXED_0;\r
- } else if ((w==720) && (h==480)) {\r
- *val = CONFIG_SENSOR_480P_FPS_FIXED_0;\r
- } else if ((w==800) && (h==600)) {\r
- *val = CONFIG_SENSOR_SVGA_FPS_FIXED_0;\r
- } else if ((w==1280) && (h==720)) {\r
- *val = CONFIG_SENSOR_720P_FPS_FIXED_0;\r
- }\r
- break;\r
- }\r
- #endif\r
- #ifdef CONFIG_SENSOR_1\r
- case 1:\r
- {\r
- if ((w==176) && (h==144)) {\r
- *val = CONFIG_SENSOR_QCIF_FPS_FIXED_1;\r
- #ifdef CONFIG_SENSOR_240X160_FPS_FIXED_1\r
- } else if ((w==240) && (h==160)) {\r
- *val = CONFIG_SENSOR_240X160_FPS_FIXED_1;\r
- #endif\r
- } else if ((w==320) && (h==240)) {\r
- *val = CONFIG_SENSOR_QVGA_FPS_FIXED_1;\r
- } else if ((w==352) && (h==288)) {\r
- *val = CONFIG_SENSOR_CIF_FPS_FIXED_1;\r
- } else if ((w==640) && (h==480)) {\r
- *val = CONFIG_SENSOR_VGA_FPS_FIXED_1;\r
- } else if ((w==720) && (h==480)) {\r
- *val = CONFIG_SENSOR_480P_FPS_FIXED_1;\r
- } else if ((w==800) && (h==600)) {\r
- *val = CONFIG_SENSOR_SVGA_FPS_FIXED_1;\r
- } else if ((w==1280) && (h==720)) {\r
- *val = CONFIG_SENSOR_720P_FPS_FIXED_1;\r
- }\r
- break;\r
- }\r
- #endif\r
- #ifdef CONFIG_SENSOR_01\r
- case 2:\r
- {\r
- if ((w==176) && (h==144)) {\r
- *val = CONFIG_SENSOR_QCIF_FPS_FIXED_01;\r
- #ifdef CONFIG_SENSOR_240X160_FPS_FIXED_01\r
- } else if ((w==240) && (h==160)) {\r
- *val = CONFIG_SENSOR_240X160_FPS_FIXED_01;\r
- #endif\r
- } else if ((w==320) && (h==240)) {\r
- *val = CONFIG_SENSOR_QVGA_FPS_FIXED_01;\r
- } else if ((w==352) && (h==288)) {\r
- *val = CONFIG_SENSOR_CIF_FPS_FIXED_01;\r
- } else if ((w==640) && (h==480)) {\r
- *val = CONFIG_SENSOR_VGA_FPS_FIXED_01;\r
- } else if ((w==720) && (h==480)) {\r
- *val = CONFIG_SENSOR_480P_FPS_FIXED_01;\r
- } else if ((w==800) && (h==600)) {\r
- *val = CONFIG_SENSOR_SVGA_FPS_FIXED_01;\r
- } else if ((w==1280) && (h==720)) {\r
- *val = CONFIG_SENSOR_720P_FPS_FIXED_01;\r
- }\r
- break;\r
- }\r
- #endif\r
- #ifdef CONFIG_SENSOR_02\r
- case 3:\r
- {\r
- if ((w==176) && (h==144)) {\r
- *val = CONFIG_SENSOR_QCIF_FPS_FIXED_02;\r
- #ifdef CONFIG_SENSOR_240X160_FPS_FIXED_02\r
- } else if ((w==240) && (h==160)) {\r
- *val = CONFIG_SENSOR_240X160_FPS_FIXED_02;\r
- #endif\r
- } else if ((w==320) && (h==240)) {\r
- *val = CONFIG_SENSOR_QVGA_FPS_FIXED_02;\r
- } else if ((w==352) && (h==288)) {\r
- *val = CONFIG_SENSOR_CIF_FPS_FIXED_02;\r
- } else if ((w==640) && (h==480)) {\r
- *val = CONFIG_SENSOR_VGA_FPS_FIXED_02;\r
- } else if ((w==720) && (h==480)) {\r
- *val = CONFIG_SENSOR_480P_FPS_FIXED_02;\r
- } else if ((w==800) && (h==600)) {\r
- *val = CONFIG_SENSOR_SVGA_FPS_FIXED_02;\r
- } else if ((w==1280) && (h==720)) {\r
- *val = CONFIG_SENSOR_720P_FPS_FIXED_02;\r
- }\r
- break;\r
- }\r
- #endif\r
- \r
- #ifdef CONFIG_SENSOR_11\r
- case 4:\r
- {\r
- if ((w==176) && (h==144)) {\r
- *val = CONFIG_SENSOR_QCIF_FPS_FIXED_11;\r
- #ifdef CONFIG_SENSOR_240X160_FPS_FIXED_11\r
- } else if ((w==240) && (h==160)) {\r
- *val = CONFIG_SENSOR_240X160_FPS_FIXED_11;\r
- #endif\r
- } else if ((w==320) && (h==240)) {\r
- *val = CONFIG_SENSOR_QVGA_FPS_FIXED_11;\r
- } else if ((w==352) && (h==288)) {\r
- *val = CONFIG_SENSOR_CIF_FPS_FIXED_11;\r
- } else if ((w==640) && (h==480)) {\r
- *val = CONFIG_SENSOR_VGA_FPS_FIXED_11;\r
- } else if ((w==720) && (h==480)) {\r
- *val = CONFIG_SENSOR_480P_FPS_FIXED_11;\r
- } else if ((w==800) && (h==600)) {\r
- *val = CONFIG_SENSOR_SVGA_FPS_FIXED_11;\r
- } else if ((w==1280) && (h==720)) {\r
- *val = CONFIG_SENSOR_720P_FPS_FIXED_11;\r
- }\r
- break;\r
- }\r
- #endif\r
- #ifdef CONFIG_SENSOR_12\r
- case 5:\r
- {\r
- if ((w==176) && (h==144)) {\r
- *val = CONFIG_SENSOR_QCIF_FPS_FIXED_12;\r
- #ifdef CONFIG_SENSOR_240X160_FPS_FIXED_12\r
- } else if ((w==240) && (h==160)) {\r
- *val = CONFIG_SENSOR_240X160_FPS_FIXED_12;\r
- #endif\r
- } else if ((w==320) && (h==240)) {\r
- *val = CONFIG_SENSOR_QVGA_FPS_FIXED_12;\r
- } else if ((w==352) && (h==288)) {\r
- *val = CONFIG_SENSOR_CIF_FPS_FIXED_12;\r
- } else if ((w==640) && (h==480)) {\r
- *val = CONFIG_SENSOR_VGA_FPS_FIXED_12;\r
- } else if ((w==720) && (h==480)) {\r
- *val = CONFIG_SENSOR_480P_FPS_FIXED_12;\r
- } else if ((w==800) && (h==600)) {\r
- *val = CONFIG_SENSOR_SVGA_FPS_FIXED_12;\r
- } else if ((w==1280) && (h==720)) {\r
- *val = CONFIG_SENSOR_720P_FPS_FIXED_12;\r
- }\r
- break;\r
- }\r
- #endif\r
- default:\r
- eprintk(" sensor-%d have not been define in board file!",idx);\r
- }\r
-}\r
-static int _rk_sensor_io_init_(struct rk29camera_gpio_res *gpio_res)\r
-{\r
- int ret = 0, i;\r
- unsigned int camera_reset = INVALID_GPIO, camera_power = INVALID_GPIO;\r
- unsigned int camera_powerdown = INVALID_GPIO, camera_flash = INVALID_GPIO;\r
- unsigned int camera_ioflag;\r
- struct rk29camera_gpio_res *io_res;\r
- bool io_requested_in_camera;\r
-\r
- camera_reset = gpio_res->gpio_reset;\r
- camera_power = gpio_res->gpio_power;\r
- camera_powerdown = gpio_res->gpio_powerdown;\r
- camera_flash = gpio_res->gpio_flash;\r
- camera_ioflag = gpio_res->gpio_flag;\r
- gpio_res->gpio_init = 0;\r
-\r
- if (camera_power != INVALID_GPIO) {\r
- ret = gpio_request(camera_power, "camera power");\r
- if (ret) {\r
- io_requested_in_camera = false;\r
- for (i=0; i<RK_CAM_NUM; i++) {\r
- io_res = &rk_camera_platform_data.gpio_res[i];\r
- if (io_res->gpio_init & RK29_CAM_POWERACTIVE_MASK) {\r
- if (io_res->gpio_power == camera_power)\r
- io_requested_in_camera = true; \r
- }\r
- }\r
-\r
- if (io_requested_in_camera==false) {\r
- i=0;\r
- while (strstr(new_camera[i].dev_name,"end")==NULL) {\r
- io_res = &new_camera[i].io;\r
- if (io_res->gpio_init & RK29_CAM_POWERACTIVE_MASK) {\r
- if (io_res->gpio_power == camera_power)\r
- io_requested_in_camera = true; \r
- }\r
- i++;\r
- }\r
- }\r
- \r
- if (io_requested_in_camera==false) {\r
- printk( "%s power pin(%d) init failed\n", gpio_res->dev_name,camera_power);\r
- goto _rk_sensor_io_init_end_;\r
- } else {\r
- ret =0;\r
- }\r
- }\r
-\r
- if (rk_camera_platform_data.iomux(camera_power) < 0) {\r
- ret = -1;\r
- eprintk("%s power pin(%d) iomux init failed",gpio_res->dev_name,camera_power);\r
- goto _rk_sensor_io_init_end_;\r
- }\r
- \r
- gpio_res->gpio_init |= RK29_CAM_POWERACTIVE_MASK;\r
- gpio_set_value(camera_reset, (((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));\r
- gpio_direction_output(camera_power, (((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));\r
-\r
- dprintk("%s power pin(%d) init success(0x%x)" ,gpio_res->dev_name,camera_power,(((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));\r
-\r
- }\r
-\r
- if (camera_reset != INVALID_GPIO) {\r
- ret = gpio_request(camera_reset, "camera reset");\r
- if (ret) {\r
- io_requested_in_camera = false;\r
- for (i=0; i<RK_CAM_NUM; i++) {\r
- io_res = &rk_camera_platform_data.gpio_res[i];\r
- if (io_res->gpio_init & RK29_CAM_RESETACTIVE_MASK) {\r
- if (io_res->gpio_reset == camera_reset)\r
- io_requested_in_camera = true; \r
- }\r
- }\r
-\r
- if (io_requested_in_camera==false) {\r
- i=0;\r
- while (strstr(new_camera[i].dev_name,"end")==NULL) {\r
- io_res = &new_camera[i].io;\r
- if (io_res->gpio_init & RK29_CAM_RESETACTIVE_MASK) {\r
- if (io_res->gpio_reset == camera_reset)\r
- io_requested_in_camera = true; \r
- }\r
- i++;\r
- }\r
- }\r
- \r
- if (io_requested_in_camera==false) {\r
- eprintk("%s reset pin(%d) init failed" ,gpio_res->dev_name,camera_reset);\r
- goto _rk_sensor_io_init_end_;\r
- } else {\r
- ret =0;\r
- }\r
- }\r
-\r
- if (rk_camera_platform_data.iomux(camera_reset) < 0) {\r
- ret = -1;\r
- eprintk("%s reset pin(%d) iomux init failed", gpio_res->dev_name,camera_reset);\r
- goto _rk_sensor_io_init_end_;\r
- }\r
- \r
- gpio_res->gpio_init |= RK29_CAM_RESETACTIVE_MASK;\r
- gpio_set_value(camera_reset, ((camera_ioflag&RK29_CAM_RESETACTIVE_MASK)>>RK29_CAM_RESETACTIVE_BITPOS));\r
- gpio_direction_output(camera_reset, ((camera_ioflag&RK29_CAM_RESETACTIVE_MASK)>>RK29_CAM_RESETACTIVE_BITPOS));\r
-\r
- dprintk("%s reset pin(%d) init success(0x%x)" ,gpio_res->dev_name,camera_reset,((camera_ioflag&RK29_CAM_RESETACTIVE_MASK)>>RK29_CAM_RESETACTIVE_BITPOS));\r
-\r
- }\r
-\r
- if (camera_powerdown != INVALID_GPIO) {\r
- ret = gpio_request(camera_powerdown, "camera powerdown");\r
- if (ret) {\r
- io_requested_in_camera = false;\r
- for (i=0; i<RK_CAM_NUM; i++) {\r
- io_res = &rk_camera_platform_data.gpio_res[i];\r
- if (io_res->gpio_init & RK29_CAM_POWERDNACTIVE_MASK) {\r
- if (io_res->gpio_powerdown == camera_powerdown)\r
- io_requested_in_camera = true; \r
- }\r
- }\r
-\r
- if (io_requested_in_camera==false) {\r
- i=0;\r
- while (strstr(new_camera[i].dev_name,"end")==NULL) {\r
- io_res = &new_camera[i].io;\r
- if (io_res->gpio_init & RK29_CAM_POWERDNACTIVE_MASK) {\r
- if (io_res->gpio_powerdown == camera_powerdown)\r
- io_requested_in_camera = true; \r
- }\r
- i++;\r
- }\r
- }\r
- \r
- if (io_requested_in_camera==false) {\r
- eprintk("%s powerdown pin(%d) init failed",gpio_res->dev_name,camera_powerdown);\r
- goto _rk_sensor_io_init_end_;\r
- } else {\r
- ret =0;\r
- }\r
- }\r
-\r
- if (rk_camera_platform_data.iomux(camera_powerdown) < 0) {\r
- ret = -1;\r
- eprintk("%s powerdown pin(%d) iomux init failed",gpio_res->dev_name,camera_powerdown);\r
- goto _rk_sensor_io_init_end_;\r
- }\r
- \r
- gpio_res->gpio_init |= RK29_CAM_POWERDNACTIVE_MASK;\r
- gpio_set_value(camera_powerdown, ((camera_ioflag&RK29_CAM_POWERDNACTIVE_MASK)>>RK29_CAM_POWERDNACTIVE_BITPOS));\r
- gpio_direction_output(camera_powerdown, ((camera_ioflag&RK29_CAM_POWERDNACTIVE_MASK)>>RK29_CAM_POWERDNACTIVE_BITPOS));\r
-\r
- dprintk("%s powerdown pin(%d) init success(0x%x)" ,gpio_res->dev_name,camera_powerdown,((camera_ioflag&RK29_CAM_POWERDNACTIVE_BITPOS)>>RK29_CAM_POWERDNACTIVE_BITPOS));\r
-\r
- }\r
-\r
- if (camera_flash != INVALID_GPIO) {\r
- ret = gpio_request(camera_flash, "camera flash");\r
- if (ret) {\r
- io_requested_in_camera = false;\r
- for (i=0; i<RK_CAM_NUM; i++) {\r
- io_res = &rk_camera_platform_data.gpio_res[i];\r
- if (io_res->gpio_init & RK29_CAM_POWERDNACTIVE_MASK) {\r
- if (io_res->gpio_powerdown == camera_powerdown)\r
- io_requested_in_camera = true; \r
- }\r
- }\r
-\r
- if (io_requested_in_camera==false) {\r
- i=0;\r
- while (strstr(new_camera[i].dev_name,"end")==NULL) {\r
- io_res = &new_camera[i].io;\r
- if (io_res->gpio_init & RK29_CAM_POWERDNACTIVE_MASK) {\r
- if (io_res->gpio_powerdown == camera_powerdown)\r
- io_requested_in_camera = true; \r
- }\r
- i++;\r
- }\r
- }\r
- \r
- ret = 0; //ddl@rock-chips.com : flash is only a function, sensor is also run;\r
- if (io_requested_in_camera==false) {\r
- eprintk("%s flash pin(%d) init failed",gpio_res->dev_name,camera_flash);\r
- goto _rk_sensor_io_init_end_;\r
- }\r
- }\r
-\r
- if (rk_camera_platform_data.iomux(camera_flash) < 0) {\r
- printk("%s flash pin(%d) iomux init failed\n",gpio_res->dev_name,camera_flash); \r
- }\r
- \r
- gpio_res->gpio_init |= RK29_CAM_FLASHACTIVE_MASK;\r
- gpio_set_value(camera_flash, ((~camera_ioflag&RK29_CAM_FLASHACTIVE_MASK)>>RK29_CAM_FLASHACTIVE_BITPOS)); /* falsh off */\r
- gpio_direction_output(camera_flash, ((~camera_ioflag&RK29_CAM_FLASHACTIVE_MASK)>>RK29_CAM_FLASHACTIVE_BITPOS));\r
-\r
- dprintk("%s flash pin(%d) init success(0x%x)",gpio_res->dev_name, camera_flash,((camera_ioflag&RK29_CAM_FLASHACTIVE_MASK)>>RK29_CAM_FLASHACTIVE_BITPOS));\r
-\r
- } \r
-_rk_sensor_io_init_end_:\r
- return ret;\r
-\r
-}\r
-\r
-static int _rk_sensor_io_deinit_(struct rk29camera_gpio_res *gpio_res)\r
-{\r
- unsigned int camera_reset = INVALID_GPIO, camera_power = INVALID_GPIO;\r
- unsigned int camera_powerdown = INVALID_GPIO, camera_flash = INVALID_GPIO;\r
- \r
- camera_reset = gpio_res->gpio_reset;\r
- camera_power = gpio_res->gpio_power;\r
- camera_powerdown = gpio_res->gpio_powerdown;\r
- camera_flash = gpio_res->gpio_flash;\r
-\r
- if (gpio_res->gpio_init & RK29_CAM_POWERACTIVE_MASK) {\r
- if (camera_power != INVALID_GPIO) {\r
- gpio_direction_input(camera_power);\r
- gpio_free(camera_power);\r
- }\r
- }\r
-\r
- if (gpio_res->gpio_init & RK29_CAM_RESETACTIVE_MASK) {\r
- if (camera_reset != INVALID_GPIO) {\r
- gpio_direction_input(camera_reset);\r
- gpio_free(camera_reset);\r
- }\r
- }\r
-\r
- if (gpio_res->gpio_init & RK29_CAM_POWERDNACTIVE_MASK) {\r
- if (camera_powerdown != INVALID_GPIO) {\r
- gpio_direction_input(camera_powerdown);\r
- gpio_free(camera_powerdown);\r
- }\r
- }\r
-\r
- if (gpio_res->gpio_init & RK29_CAM_FLASHACTIVE_MASK) {\r
- if (camera_flash != INVALID_GPIO) {\r
- gpio_direction_input(camera_flash);\r
- gpio_free(camera_flash);\r
- }\r
- }\r
- gpio_res->gpio_init = 0;\r
- \r
- return 0;\r
-}\r
-\r
-static int rk_sensor_io_init(void)\r
-{\r
- int i,j;\r
- static bool is_init = false;\r
- struct rk29camera_platform_data* plat_data = &rk_camera_platform_data;\r
-\r
- if(is_init) { \r
- return 0;\r
- } else {\r
- is_init = true;\r
- }\r
- \r
- if (sensor_ioctl_cb.sensor_power_cb == NULL)\r
- sensor_ioctl_cb.sensor_power_cb = sensor_power_default_cb;\r
- if (sensor_ioctl_cb.sensor_reset_cb == NULL)\r
- sensor_ioctl_cb.sensor_reset_cb = sensor_reset_default_cb;\r
- if (sensor_ioctl_cb.sensor_powerdown_cb == NULL)\r
- sensor_ioctl_cb.sensor_powerdown_cb = sensor_powerdown_default_cb;\r
- if (sensor_ioctl_cb.sensor_flash_cb == NULL)\r
- sensor_ioctl_cb.sensor_flash_cb = sensor_flash_default_cb;\r
- \r
- for(i = 0;i < RK_CAM_NUM; i++) {\r
- if (plat_data->gpio_res[i].dev_name == NULL)\r
- continue;\r
- \r
- if (_rk_sensor_io_init_(&plat_data->gpio_res[i])<0)\r
- goto sensor_io_init_erro;\r
- \r
- for (j=0; j<10; j++) {\r
- memset(&plat_data->info[i].fival[j],0x00,sizeof(struct v4l2_frmivalenum));\r
-\r
- if (j==0) {\r
- plat_data->info[i].fival[j].width = 176;\r
- plat_data->info[i].fival[j].height = 144;\r
- } else if (j==1) {\r
- plat_data->info[i].fival[j].width = 320;\r
- plat_data->info[i].fival[j].height = 240;\r
- } else if (j==2) {\r
- plat_data->info[i].fival[j].width = 352;\r
- plat_data->info[i].fival[j].height = 288;\r
- } else if (j==3) {\r
- plat_data->info[i].fival[j].width = 640;\r
- plat_data->info[i].fival[j].height = 480;\r
- } else if (j==4) {\r
- plat_data->info[i].fival[j].width = 720;\r
- plat_data->info[i].fival[j].height = 480;\r
- } else if (j==5) {\r
- plat_data->info[i].fival[j].width = 1280;\r
- plat_data->info[i].fival[j].height = 720;\r
- } else if (j==6) {\r
- plat_data->info[i].fival[j].width = 240;\r
- plat_data->info[i].fival[j].height = 160;\r
- } else if (j==7) {\r
- plat_data->info[i].fival[j].width = 800;\r
- plat_data->info[i].fival[j].height = 600;\r
- } \r
- if (plat_data->info[i].fival[j].width && plat_data->info[i].fival[j].height) {\r
- rk29_sensor_fps_get(i,&plat_data->info[i].fival[j].discrete.denominator,\r
- plat_data->info[i].fival[j].width,plat_data->info[i].fival[j].height);\r
- plat_data->info[i].fival[j].discrete.numerator= 1000;\r
- plat_data->info[i].fival[j].index = 0;\r
- plat_data->info[i].fival[j].pixel_format = V4L2_PIX_FMT_NV12;\r
- plat_data->info[i].fival[j].type = V4L2_FRMIVAL_TYPE_DISCRETE;\r
- }\r
- }\r
- \r
- continue;\r
-sensor_io_init_erro:\r
- _rk_sensor_io_deinit_(&plat_data->gpio_res[i]);\r
- }\r
- \r
- i = 0;\r
- while (strstr(new_camera[i].dev_name,"end")==NULL) {\r
- if (_rk_sensor_io_init_(&new_camera[i].io)<0)\r
- _rk_sensor_io_deinit_(&new_camera[i].io);\r
-\r
- i++;\r
- }\r
- return 0;\r
-}\r
-\r
-static int rk_sensor_io_deinit(int sensor)\r
-{\r
- int i;\r
- struct rk29camera_platform_data* plat_data = &rk_camera_platform_data;\r
- \r
- for(i = 0;i < RK_CAM_NUM; i++) {\r
- if (plat_data->gpio_res[i].dev_name == NULL)\r
- continue;\r
- \r
- _rk_sensor_io_deinit_(&plat_data->gpio_res[i]);\r
- }\r
-\r
- i = 0;\r
- while (strstr(new_camera[i].dev_name,"end")==NULL) {\r
- _rk_sensor_io_deinit_(&new_camera[i].io);\r
-\r
- i++;\r
- }\r
- \r
- return 0;\r
-}\r
-static int rk_sensor_ioctrl(struct device *dev,enum rk29camera_ioctrl_cmd cmd, int on)\r
-{\r
- struct rk29camera_gpio_res *res = NULL;\r
- struct rkcamera_platform_data *new_cam_dev = NULL;\r
- struct rk29camera_platform_data* plat_data = &rk_camera_platform_data;\r
- int ret = RK29_CAM_IO_SUCCESS,i = 0;\r
- struct soc_camera_link *dev_icl = NULL;\r
-\r
- //for test reg\r
- for(i = 0;i < RK_CAM_NUM;i++){\r
- if(plat_data->gpio_res[i].dev_name && (strcmp(plat_data->gpio_res[i].dev_name, dev_name(dev)) == 0)) {\r
- res = (struct rk29camera_gpio_res *)&plat_data->gpio_res[i];\r
- dev_icl = &plat_data->register_dev[i].link_info;\r
- break;\r
- } \r
- }\r
-\r
- if (res == NULL) {\r
- i = 0;\r
- while (strstr(new_camera[i].dev_name,"end")==NULL) {\r
- if (strcmp(new_camera[i].dev_name, dev_name(dev)) == 0) {\r
- res = (struct rk29camera_gpio_res *)&new_camera[i].io; \r
- new_cam_dev = &new_camera[i];\r
- dev_icl = &new_camera[i].dev.link_info;\r
- break;\r
- }\r
- i++;\r
- }\r
- }\r
- \r
- if (res == NULL) {\r
- eprintk("%s is not regisiterd in rk29_camera_platform_data!!",dev_name(dev));\r
- ret = RK29_CAM_EIO_INVALID;\r
- goto rk_sensor_ioctrl_end;\r
- }\r
- \r
- switch (cmd)\r
- {\r
- case Cam_Power:\r
- {\r
- if (sensor_ioctl_cb.sensor_power_cb) {\r
- ret = sensor_ioctl_cb.sensor_power_cb(res, on); \r
- ret = (ret != RK29_CAM_EIO_INVALID)?ret:0; /* ddl@rock-chips.com: v0.1.1 */ \r
- } else {\r
- eprintk("sensor_ioctl_cb.sensor_power_cb is NULL");\r
- WARN_ON(1);\r
- }\r
-\r
- printk("ret: %d\n",ret);\r
- break;\r
- }\r
- case Cam_Reset:\r
- {\r
- if (sensor_ioctl_cb.sensor_reset_cb) {\r
- ret = sensor_ioctl_cb.sensor_reset_cb(res, on);\r
-\r
- ret = (ret != RK29_CAM_EIO_INVALID)?ret:0;\r
- } else {\r
- eprintk( "sensor_ioctl_cb.sensor_reset_cb is NULL");\r
- WARN_ON(1);\r
- }\r
- break;\r
- }\r
-\r
- case Cam_PowerDown:\r
- {\r
- if (sensor_ioctl_cb.sensor_powerdown_cb) {\r
- ret = sensor_ioctl_cb.sensor_powerdown_cb(res, on);\r
- } else {\r
- eprintk( "sensor_ioctl_cb.sensor_powerdown_cb is NULL");\r
- WARN_ON(1);\r
- }\r
- break;\r
- }\r
-\r
- case Cam_Flash:\r
- {\r
- if (sensor_ioctl_cb.sensor_flash_cb) {\r
- ret = sensor_ioctl_cb.sensor_flash_cb(res, on);\r
- } else {\r
- eprintk( "sensor_ioctl_cb.sensor_flash_cb is NULL!");\r
- WARN_ON(1);\r
- }\r
- break;\r
- }\r
-\r
- case Cam_Mclk:\r
- {\r
- if (plat_data->sensor_mclk && dev_icl) {\r
- plat_data->sensor_mclk(dev_icl->bus_id,(on!=0)?1:0,on);\r
- } else { \r
- eprintk( "%s(%d): sensor_mclk(%p) or dev_icl(%p) is NULL",\r
- __FUNCTION__,__LINE__,plat_data->sensor_mclk,dev_icl);\r
- }\r
- break;\r
- }\r
- \r
- default:\r
- {\r
- eprintk("%s cmd(0x%x) is unknown!",__FUNCTION__, cmd);\r
- break;\r
- }\r
- }\r
-rk_sensor_ioctrl_end:\r
- return ret;\r
-}\r
-\r
-static int rk_sensor_pwrseq(struct device *dev,int powerup_sequence, int on, int mclk_rate)\r
-{\r
- int ret =0;\r
- int i,powerup_type;\r
- \r
- for (i=0; i<8; i++) {\r
-\r
- if (on == 1)\r
- powerup_type = SENSOR_PWRSEQ_GET(powerup_sequence,i);\r
- else\r
- powerup_type = SENSOR_PWRSEQ_GET(powerup_sequence,(7-i));\r
- \r
- switch (powerup_type)\r
- {\r
- case SENSOR_PWRSEQ_AVDD:\r
- case SENSOR_PWRSEQ_DOVDD:\r
- case SENSOR_PWRSEQ_DVDD:\r
- case SENSOR_PWRSEQ_PWR:\r
- { \r
- ret = rk_sensor_ioctrl(dev,Cam_Power, on);\r
- if (ret<0) {\r
- eprintk("SENSOR_PWRSEQ_PWR failed");\r
- } else { \r
- msleep(10);\r
- dprintk("SensorPwrSeq-power: %d",on);\r
- }\r
- break;\r
- }\r
-\r
- case SENSOR_PWRSEQ_HWRST:\r
- {\r
- if(!on){\r
- rk_sensor_ioctrl(dev,Cam_Reset, 1);\r
- }else{\r
- ret = rk_sensor_ioctrl(dev,Cam_Reset, 1);\r
- msleep(2);\r
- ret |= rk_sensor_ioctrl(dev,Cam_Reset, 0); \r
- }\r
- if (ret<0) {\r
- eprintk("SENSOR_PWRSEQ_HWRST failed");\r
- } else {\r
- dprintk("SensorPwrSeq-reset: %d",on);\r
- }\r
- break;\r
- }\r
-\r
- case SENSOR_PWRSEQ_PWRDN:\r
- { \r
- ret = rk_sensor_ioctrl(dev,Cam_PowerDown, !on);\r
- if (ret<0) {\r
- eprintk("SENSOR_PWRSEQ_PWRDN failed");\r
- } else {\r
- dprintk("SensorPwrSeq-power down: %d",!on);\r
- }\r
- break;\r
- }\r
-\r
- case SENSOR_PWRSEQ_CLKIN:\r
- {\r
- ret = rk_sensor_ioctrl(dev,Cam_Mclk, (on?mclk_rate:on));\r
- if (ret<0) {\r
- eprintk("SENSOR_PWRSEQ_CLKIN failed");\r
- } else {\r
- dprintk("SensorPwrSeq-clock: %d",on);\r
- }\r
- break;\r
- }\r
-\r
- default:\r
- break;\r
- }\r
- \r
- } \r
-\r
- return ret;\r
-}\r
-\r
-static int rk_sensor_power(struct device *dev, int on)\r
-{\r
- int i, powerup_sequence,mclk_rate;\r
- \r
- struct rk29camera_platform_data* plat_data = &rk_camera_platform_data;\r
- struct rk29camera_gpio_res *dev_io = NULL;\r
- struct rkcamera_platform_data *new_camera=NULL, *new_device=NULL;\r
- bool real_pwroff = true;\r
- int ret = 0;\r
- \r
- //ddl@rock-chips.com: other sensor must switch into standby before turn on power;\r
- for(i = 0;i < RK_CAM_NUM; i++) {\r
- if (plat_data->gpio_res[i].dev_name == NULL)\r
- continue;\r
-\r
- if (plat_data->gpio_res[i].gpio_powerdown != INVALID_GPIO) {\r
- gpio_direction_output(plat_data->gpio_res[i].gpio_powerdown,\r
- ((plat_data->gpio_res[i].gpio_flag&RK29_CAM_POWERDNACTIVE_MASK)>>RK29_CAM_POWERDNACTIVE_BITPOS)); \r
- }\r
- \r
- if (strcmp(plat_data->gpio_res[i].dev_name,dev_name(dev))) {\r
- if (sensor_ioctl_cb.sensor_powerdown_cb && on)\r
- sensor_ioctl_cb.sensor_powerdown_cb(&plat_data->gpio_res[i],1);\r
- } else { \r
- dev_io = &plat_data->gpio_res[i];\r
- real_pwroff = true;\r
- }\r
- }\r
-\r
- new_camera = plat_data->register_dev_new;\r
- while (strstr(new_camera->dev_name,"end")==NULL) {\r
-\r
- if (new_camera->io.gpio_powerdown != INVALID_GPIO) {\r
- gpio_direction_output(new_camera->io.gpio_powerdown,\r
- ((new_camera->io.gpio_flag&RK29_CAM_POWERDNACTIVE_MASK)>>RK29_CAM_POWERDNACTIVE_BITPOS)); \r
- }\r
- \r
- if (strcmp(new_camera->dev_name,dev_name(dev))) {\r
- if (sensor_ioctl_cb.sensor_powerdown_cb && on)\r
- sensor_ioctl_cb.sensor_powerdown_cb(&new_camera->io,1);\r
- } else {\r
- new_device = new_camera;\r
- dev_io = &new_camera->io;\r
- \r
- if (!Sensor_Support_DirectResume(new_camera->pwdn_info))\r
- real_pwroff = true;\r
- else\r
- real_pwroff = false;\r
- }\r
- new_camera++;\r
- }\r
-\r
- if (new_device != NULL) {\r
- powerup_sequence = new_device->powerup_sequence;\r
- if ((new_device->mclk_rate == 24) || (new_device->mclk_rate == 48))\r
- mclk_rate = new_device->mclk_rate*1000000;\r
- else \r
- mclk_rate = 24000000;\r
- } else {\r
- powerup_sequence = sensor_PWRSEQ_DEFAULT;\r
- mclk_rate = 24000000;\r
- }\r
- \r
- if (on) {\r
- rk_sensor_pwrseq(dev, powerup_sequence, on,mclk_rate); \r
- } else {\r
- if (real_pwroff) {\r
- if (rk_sensor_pwrseq(dev, powerup_sequence, on,mclk_rate)<0) /* ddl@rock-chips.com: v0.1.5 */\r
- goto PowerDown;\r
- \r
- /*ddl@rock-chips.com: all power down switch to Hi-Z after power off*/\r
- for(i = 0;i < RK_CAM_NUM; i++) {\r
- if (plat_data->gpio_res[i].dev_name == NULL)\r
- continue;\r
- if (plat_data->gpio_res[i].gpio_powerdown != INVALID_GPIO) {\r
- gpio_direction_input(plat_data->gpio_res[i].gpio_powerdown); \r
- }\r
- }\r
- \r
- new_camera = plat_data->register_dev_new;\r
- while (strstr(new_camera->dev_name,"end")==NULL) {\r
- if (new_camera->io.gpio_powerdown != INVALID_GPIO) {\r
- gpio_direction_input(new_camera->io.gpio_powerdown); \r
- }\r
- new_camera->pwdn_info |= 0x01;\r
- new_camera++;\r
- }\r
- } else { \r
-PowerDown:\r
- rk_sensor_ioctrl(dev,Cam_PowerDown, !on);\r
-\r
- rk_sensor_ioctrl(dev,Cam_Mclk, 0);\r
- }\r
-\r
- mdelay(10);/* ddl@rock-chips.com: v0.1.3 */\r
- }\r
- return ret;\r
-}\r
-#if 0\r
-static int rk_sensor_reset(struct device *dev)\r
-{\r
-#if 0\r
- rk_sensor_ioctrl(dev,Cam_Reset,1);\r
- msleep(2);\r
- rk_sensor_ioctrl(dev,Cam_Reset,0);\r
-#else\r
- /*\r
- *ddl@rock-chips.com : the rest function invalidate, because this operate is put together in rk_sensor_power;\r
- */\r
-#endif\r
- return 0;\r
-}\r
-#endif\r
-static int rk_sensor_powerdown(struct device *dev, int on)\r
-{\r
- return rk_sensor_ioctrl(dev,Cam_PowerDown,on);\r
-}\r
-#if ((defined PMEM_CAM_NECESSARY)&&(defined CONFIG_VIDEO_RK29_CAMMEM_PMEM))\r
-static struct android_pmem_platform_data android_pmem_cam_pdata = {\r
- .name = "pmem_cam",\r
- .start = PMEM_CAM_BASE,\r
- .size = PMEM_CAM_SIZE,\r
- .no_allocator = 1,\r
- .cached = 1,\r
-};\r
-\r
-static struct platform_device android_pmem_cam_device = {\r
- .name = "android_pmem",\r
- .id = 1,\r
- .dev = {\r
- .platform_data = &android_pmem_cam_pdata,\r
- },\r
-};\r
-#endif\r
-#ifdef CONFIG_RK_CONFIG\r
-int camera_set_platform_param(int id, int i2c, int gpio)\r
-{\r
- int i;\r
- char *dev_name[] = {\r
- SENSOR_DEVICE_NAME_0, \r
- SENSOR_DEVICE_NAME_01, \r
- SENSOR_DEVICE_NAME_02, \r
- SENSOR_DEVICE_NAME_1, \r
- SENSOR_DEVICE_NAME_11, \r
- SENSOR_DEVICE_NAME_12\r
- };\r
- char *module_name[] = {\r
- SENSOR_NAME_0,\r
- SENSOR_NAME_01,\r
- SENSOR_NAME_02,\r
- SENSOR_NAME_1,\r
- SENSOR_NAME_11,\r
- SENSOR_NAME_12\r
- };\r
-\r
- if(id < 0 || id >= 6)\r
- return -EINVAL;\r
- for(i = 0; i < 6; i++){\r
- if(i == id){\r
- printk("%s: id = %d, i2c = %d, gpio = %d\n", __func__, id, i2c, gpio);\r
- }\r
- if(rk_camera_platform_data.gpio_res[i].dev_name &&\r
- strcmp(rk_camera_platform_data.gpio_res[i].dev_name, dev_name[id]) == 0)\r
- rk_camera_platform_data.gpio_res[i].gpio_powerdown = gpio;\r
- if(rk_camera_platform_data.register_dev[i].link_info.module_name &&\r
- strcmp(rk_camera_platform_data.register_dev[i].link_info.module_name, module_name[id]) == 0)\r
- rk_camera_platform_data.register_dev[i].link_info.i2c_adapter_id = i2c;\r
- }\r
-\r
- return 0;\r
-}\r
-#else\r
-int camera_set_platform_param(int id, int i2c, int gpio)\r
-{\r
- return 0;\r
-}\r
-#endif\r
-\r
-int rk_sensor_register(void)\r
-{\r
- int i;\r
- \r
- i = 0;\r
- while (strstr(new_camera[i].dev.device_info.dev.init_name,"end")==NULL) {\r
-\r
- if (new_camera[i].dev.i2c_cam_info.addr == INVALID_VALUE) {\r
- WARN(1, \r
- KERN_ERR "%s(%d): new_camera[%d] i2c addr is invalidate!",\r
- __FUNCTION__,__LINE__,i);\r
- continue;\r
- }\r
- \r
- sprintf(new_camera[i].dev_name,"%s_%d",new_camera[i].dev.device_info.dev.init_name,i+3);\r
- new_camera[i].dev.device_info.dev.init_name =(const char*)&new_camera[i].dev_name[0];\r
- new_camera[i].io.dev_name =(const char*)&new_camera[i].dev_name[0];\r
- \r
- if (new_camera[i].orientation == INVALID_VALUE) {\r
- if (strstr(new_camera[i].dev_name,"back")) {\r
- new_camera[i].orientation = 90;\r
- } else {\r
- new_camera[i].orientation = 270;\r
- }\r
- }\r
- /* ddl@rock-chips.com: v0.1.3 */\r
- if ((new_camera[i].fov_h <= 0) || (new_camera[i].fov_h>360))\r
- new_camera[i].fov_h = 100;\r
- \r
- if ((new_camera[i].fov_v <= 0) || (new_camera[i].fov_v>360))\r
- new_camera[i].fov_v = 100; \r
-\r
- new_camera[i].dev.link_info.power = rk_sensor_power;\r
- new_camera[i].dev.link_info.powerdown = rk_sensor_powerdown; \r
-\r
- new_camera[i].dev.link_info.board_info =&new_camera[i].dev.i2c_cam_info;\r
- new_camera[i].dev.device_info.id = i+6;\r
- new_camera[i].dev.device_info.dev.platform_data = &new_camera[i].dev.link_info;\r
-\r
- if (new_camera[i].flash == true) {\r
- if (CONFIG_SENSOR_FLASH_IOCTL_USR == 0) {\r
- eprintk("new_camera[%d] have been configed as attach flash, but CONFIG_SENSOR_FLASH_IOCTL_USR isn't turn on!",i);\r
-\r
- new_camera[i].flash = false; \r
- }\r
- }\r
-\r
- new_camera[i].dev.link_info.priv_usr = &rk_camera_platform_data;\r
- platform_device_register(&new_camera[i].dev.device_info);\r
- i++;\r
- }\r
- \r
- sprintf(new_camera[i].dev_name,"%s",new_camera[i].dev.device_info.dev.init_name);\r
-\r
- return 0;\r
-}\r
-#endif\r
-\r
+++ /dev/null
-/*
- * arch/arm/plat-rk/rk_fiq_debugger.c
- *
- * Serial Debugger Interface for Rockchip
- *
- * Copyright (C) 2012 ROCKCHIP, Inc.
- * Copyright (C) 2008 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdarg.h>
-#include <linux/module.h>
-#include <linux/io.h>
-#include <linux/interrupt.h>
-#include <linux/clk.h>
-#include <linux/platform_device.h>
-#include <linux/irq.h>
-#include <linux/serial_reg.h>
-#include <linux/slab.h>
-#include <linux/stacktrace.h>
-#include <linux/uaccess.h>
-#include <linux/kfifo.h>
-#include <linux/kthread.h>
-#include <asm/fiq_debugger.h>
-#include <asm/hardware/gic.h>
-#include <plat/rk_fiq_debugger.h>
-#include <plat/fiq.h>
-
-struct rk_fiq_debugger {
- struct fiq_debugger_pdata pdata;
- void __iomem *debug_port_base;
- bool break_seen;
-#ifdef CONFIG_RK_CONSOLE_THREAD
- struct task_struct *console_task;
-#endif
-};
-
-static inline void rk_fiq_write(struct rk_fiq_debugger *t,
- unsigned int val, unsigned int off)
-{
- __raw_writeb(val, t->debug_port_base + off * 4);
-}
-
-static inline unsigned int rk_fiq_read(struct rk_fiq_debugger *t,
- unsigned int off)
-{
- return __raw_readb(t->debug_port_base + off * 4);
-}
-
-static inline unsigned int rk_fiq_read_lsr(struct rk_fiq_debugger *t)
-{
- unsigned int lsr;
-
- lsr = rk_fiq_read(t, UART_LSR);
- if (lsr & UART_LSR_BI)
- t->break_seen = true;
-
- return lsr;
-}
-
-static int debug_port_init(struct platform_device *pdev)
-{
- struct rk_fiq_debugger *t;
- t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
-
- if (rk_fiq_read(t, UART_LSR) & UART_LSR_DR)
- (void)rk_fiq_read(t, UART_RX);
- /* enable rx and lsr interrupt */
- rk_fiq_write(t, UART_IER_RLSI | UART_IER_RDI, UART_IER);
- /* interrupt on every character when receive,but we can enable fifo for TX
- I found that if we enable the RX fifo, some problem may vanish such as when
- you continuously input characters in the command line the uart irq may be disable
- because of the uart irq is served when CPU is at IRQ exception,but it is
- found unregistered, so it is disable.
- hhb@rock-chips.com */
- rk_fiq_write(t, 0xc1, UART_FCR);
-
- return 0;
-}
-
-static int debug_getc(struct platform_device *pdev)
-{
- unsigned int lsr;
- struct rk_fiq_debugger *t;
- t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
-
- lsr = rk_fiq_read_lsr(t);
-
- if (lsr & UART_LSR_BI || t->break_seen) {
- t->break_seen = false;
- return FIQ_DEBUGGER_BREAK;
- }
-
- if (lsr & UART_LSR_DR)
- return rk_fiq_read(t, UART_RX);
-
- return FIQ_DEBUGGER_NO_CHAR;
-}
-
-static void debug_putc(struct platform_device *pdev, unsigned int c)
-{
- struct rk_fiq_debugger *t;
- t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
-
-// while (!(rk_fiq_read_lsr(t) & UART_LSR_THRE))
-// cpu_relax();
- //enable TX FIFO
- while (!(rk_fiq_read(t, 0x1F) & 0x02))
- cpu_relax();
- rk_fiq_write(t, c, UART_TX);
-}
-
-static void debug_flush(struct platform_device *pdev)
-{
- struct rk_fiq_debugger *t;
- t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
-
- while (!(rk_fiq_read_lsr(t) & UART_LSR_TEMT))
- cpu_relax();
-}
-
-#ifdef CONFIG_RK_CONSOLE_THREAD
-static DEFINE_KFIFO(fifo, unsigned char, SZ_64K);
-
-static int console_thread(void *data)
-{
- struct platform_device *pdev = data;
- struct rk_fiq_debugger *t;
- unsigned char c;
- t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
-
- while (1) {
- set_current_state(TASK_INTERRUPTIBLE);
- schedule();
- if (kthread_should_stop())
- break;
- set_current_state(TASK_RUNNING);
- while (kfifo_get(&fifo, &c))
- debug_putc(pdev, c);
- debug_flush(pdev);
- }
-
- return 0;
-}
-
-static void console_write(struct platform_device *pdev, const char *s, unsigned int count)
-{
- unsigned char c, r = '\r';
- static bool oops = false;
- struct rk_fiq_debugger *t;
- t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
-
- if (oops_in_progress || oops) {
- debug_flush(pdev);
- while (kfifo_get(&fifo, &c))
- debug_putc(pdev, c);
- while (count--) {
- if (*s == '\n') {
- debug_putc(pdev, r);
- }
- debug_putc(pdev, *s++);
- }
- debug_flush(pdev);
- oops = true;
- return;
- }
-
- while (count--) {
- if (*s == '\n') {
- kfifo_put(&fifo, &r);
- }
- kfifo_put(&fifo, s++);
- }
- wake_up_process(t->console_task);
-}
-#endif
-
-static void fiq_enable(struct platform_device *pdev, unsigned int irq, bool on)
-{
- if (on)
- rk_fiq_enable(irq);
- else
- rk_fiq_disable(irq);
-}
-
-static void force_irq(struct platform_device *pdev, unsigned int irq)
-{
- rk_irq_setpending(irq);
-}
-
-static int rk_fiq_debugger_id;
-
-void rk_serial_debug_init(void __iomem *base, int irq, int signal_irq, int wakeup_irq)
-{
- struct rk_fiq_debugger *t = NULL;
- struct platform_device *pdev = NULL;
- struct resource *res = NULL;
- int res_count = 0;
-
- if (!base) {
- pr_err("Invalid fiq debugger uart base\n");
- return;
- }
-
- t = kzalloc(sizeof(struct rk_fiq_debugger), GFP_KERNEL);
- if (!t) {
- pr_err("Failed to allocate for fiq debugger\n");
- return;
- }
-
- t->pdata.uart_init = debug_port_init;
- t->pdata.uart_getc = debug_getc;
- t->pdata.uart_putc = debug_putc;
-#ifndef CONFIG_RK_CONSOLE_THREAD
- t->pdata.uart_flush = debug_flush;
-#endif
- t->pdata.fiq_enable = fiq_enable;
- t->pdata.force_irq = force_irq;
- t->debug_port_base = base;
-
- res = kzalloc(sizeof(struct resource) * 3, GFP_KERNEL);
- if (!res) {
- pr_err("Failed to alloc fiq debugger resources\n");
- goto out2;
- }
-
- pdev = kzalloc(sizeof(struct platform_device), GFP_KERNEL);
- if (!pdev) {
- pr_err("Failed to alloc fiq debugger platform device\n");
- goto out3;
- };
-
- if (irq >= 0) {
- res[0].flags = IORESOURCE_IRQ;
- res[0].start = irq;
- res[0].end = irq;
- res[0].name = "fiq";
- res_count++;
- }
-
- if (signal_irq >= 0) {
- res[1].flags = IORESOURCE_IRQ;
- res[1].start = signal_irq;
- res[1].end = signal_irq;
- res[1].name = "signal";
- res_count++;
- }
-
- if (wakeup_irq >= 0) {
- res[2].flags = IORESOURCE_IRQ;
- res[2].start = wakeup_irq;
- res[2].end = wakeup_irq;
- res[2].name = "wakeup";
- res_count++;
- }
-
-#ifdef CONFIG_RK_CONSOLE_THREAD
- t->console_task = kthread_create(console_thread, pdev, "kconsole");
- if (!IS_ERR(t->console_task)) {
- struct sched_param param = { .sched_priority = MAX_RT_PRIO - 1 };
- t->pdata.console_write = console_write;
- sched_setscheduler_nocheck(t->console_task, SCHED_FIFO, ¶m);
- }
-#endif
-
- pdev->name = "fiq_debugger";
- pdev->id = rk_fiq_debugger_id++;
- pdev->dev.platform_data = &t->pdata;
- pdev->resource = res;
- pdev->num_resources = res_count;
- if (platform_device_register(pdev)) {
- pr_err("Failed to register fiq debugger\n");
- goto out4;
- }
- return;
-
-out4:
- kfree(pdev);
-out3:
- kfree(res);
-out2:
- kfree(t);
-}
+++ /dev/null
-menuconfig RK_PM_TESTS
- tristate "/sys/pm_tests/ support"
- help
- PM tests tools
-
-if RK_PM_TESTS
-
-config PM_TEST_CLK_RATE
- bool "Scale clock rate"
- default y
- help
- Use to set clock rate
-
-config PM_TEST_CLK_VOLT
- bool "Scale voltage"
- default y
- help
- Use to set voltage domain's voltage
-
-config PM_TEST_MAXFREQ
- bool "For max runable frequency test"
- default y
- help
- Use to test the max runable frequency of a fixed voltage
-
-config PM_TEST_FREQ_LIMIT
- bool "Limit clocks' frequency"
- help
- Use to limit clocks' frequency
-
-config PM_TEST_CPU_USAGE
- bool "Set cpu running at a fixed frequency"
- help
- Use to Set cpu running at a fixed frequency
-
-config PM_TEST_SUSPEND_DBG
- bool "suspend debug control"
- help
- Use to suspend debug
-
-config PM_TEST_CLK_AUTO_VOLT
- bool "Auto scale voltage"
- help
- Use to auto scale regulator's voltage by step
-
-config PM_TEST_DVFS_TABLE_SCAN
- bool "dvfs table scan"
- help
- Use to scan dvfs table
-
-config PM_TEST_DVFS_TABLE_RESET
- bool "dvfs table reset"
- help
- Use to reset dvfs table
-
-config PM_TEST_DELAYLINE
- bool "Get delayline value"
- help
- Use to get delayline value
-
-config PM_TEST_FT
- bool "Test kernel for FT"
- help
- Use to test kernel for FT
-
-endif
+++ /dev/null
-obj-$(CONFIG_RK_PM_TESTS) += rk_pm_test.o
-rk_pm_test-y += rk_pm_tests.o
-
-# Optional functions
-# set_volt: change dvfs_table to change voltage
-rk_pm_test-$(CONFIG_PM_TEST_CLK_RATE) += clk_rate.o
-rk_pm_test-$(CONFIG_PM_TEST_CLK_VOLT) += clk_volt.o
-rk_pm_test-$(CONFIG_PM_TEST_MAXFREQ) += maxfreq.o
-rk_pm_test-$(CONFIG_PM_TEST_FREQ_LIMIT) += freq_limit.o
-rk_pm_test-$(CONFIG_PM_TEST_CPU_USAGE) += cpu_usage.o
-rk_pm_test-$(CONFIG_PM_TEST_SUSPEND_DBG) += rk_suspend_test.o
-rk_pm_test-$(CONFIG_PM_TEST_CLK_AUTO_VOLT) += clk_auto_volt.o
-rk_pm_test-$(CONFIG_PM_TEST_DELAYLINE) += delayline.o
-rk_pm_test-$(CONFIG_PM_TEST_DVFS_TABLE_SCAN) += dvfs_table_scan.o
-rk_pm_test-$(CONFIG_PM_TEST_DVFS_TABLE_RESET) += dvfs_table_reset.o
-obj-$(CONFIG_PM_TEST_FT) += ft/
+++ /dev/null
-#include <linux/clk.h>
-#include <linux/kobject.h>
-#include <linux/string.h>
-#include <linux/workqueue.h>
-#include <linux/regulator/machine.h>
-#include <mach/dvfs.h>
-
-#include "rk_pm_tests.h"
-#include "clk_auto_volt.h"
-/***************************************************************************/
-#define VOLT_UP 1
-#define VOLT_DOWN 0
-
-static int wq_is_run = 0;
-static unsigned int volt_direction;
-static unsigned int begin_volt;
-static unsigned int stop_volt;
-static unsigned int volt;
-static unsigned int volt_step = 25000;
-static struct regulator *regulator = NULL;
-
-static struct workqueue_struct *scal_volt_wq = NULL;
-static struct delayed_work scal_volt_work;
-
-static unsigned int timer_tick;
-
-static void scal_volt_func(struct work_struct *work)
-{
- int ret = 0;
-
- ret = regulator_set_voltage(regulator, volt, volt);
- if (ret) {
- PM_ERR("regulator_set_voltage failed!\n");
- PM_ERR("stop!\n");
- return;
- }
- else
- PM_DBG("regulator_set_voltage: %d(uV)\n",volt);
-
- if (volt_direction == VOLT_DOWN) {
- volt = volt - volt_step;
- if(volt < stop_volt) {
- PM_DBG("stop!\n");
- return;
- }
- }
- else if (volt_direction == VOLT_UP) {
- volt = volt + volt_step;
- if (volt > stop_volt) {
- PM_DBG("stop!\n");
- return;
- }
- }
-
- queue_delayed_work(scal_volt_wq, &scal_volt_work, msecs_to_jiffies(timer_tick*1000));
-}
-
-ssize_t clk_auto_volt_show(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf)
-{
- char *str = buf;
- str += sprintf(str, "[start/stop] [up/down] [regulator_name] [begin_volt(uV)] [stop_volt(uv)] [volt_step(uv)] [timer_tick(s)]\n");
-
- return (str - buf);
-}
-
-ssize_t clk_auto_volt_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n)
-{
- char cmd[10];
- char volt_flag[10];
- char regulator_name[20];
-
- sscanf(buf, "%s %s %s %u %u %u %u", cmd, volt_flag, regulator_name, &begin_volt, &stop_volt, &volt_step, &timer_tick);
-
- if (0 == strncmp(cmd, "start", strlen("start"))) {
- if (0 == strncmp(volt_flag, "up", strlen("up"))) {
- if (begin_volt >= stop_volt) {
- PM_ERR("wrong! begin_volt >= stop_volt!\n");
- return -EINVAL;
- }
- volt_direction = VOLT_UP;
-
- } else if (0 == strncmp(volt_flag, "down", strlen("down"))) {
- if (begin_volt <= stop_volt) {
- PM_ERR("wrong! begin_volt <= stop_volt!\n");
- return -EINVAL;
- }
- volt_direction = VOLT_DOWN;
-
- } else {
- PM_ERR("argument %s is invalid!\n",volt_flag);
- return -EINVAL;
- }
-
- regulator = dvfs_get_regulator(regulator_name);
- if (IS_ERR_OR_NULL(regulator)) {
- PM_ERR("%s get dvfs_regulator %s error\n", __func__, regulator_name);
- return -ENOMEM;
- }
-
- if (wq_is_run == 1) {
- cancel_delayed_work(&scal_volt_work);
- flush_workqueue(scal_volt_wq);
- //destroy_workqueue(scal_volt_wq);
- wq_is_run = 0;
- }
-
- PM_DBG("begin!\n");
-
- volt = begin_volt;
-
- scal_volt_wq = create_workqueue("scal volt wq");
- INIT_DELAYED_WORK(&scal_volt_work, scal_volt_func);
- queue_delayed_work(scal_volt_wq, &scal_volt_work, msecs_to_jiffies(timer_tick*1000));
-
- wq_is_run = 1;
-
- } else if (0 == strncmp(cmd, "stop", strlen("stop"))) {
- if (wq_is_run == 1) {
- cancel_delayed_work(&scal_volt_work);
- flush_workqueue(scal_volt_wq);
- //destroy_workqueue(scal_volt_wq);
- wq_is_run = 0;
- }
-
- } else {
- PM_ERR("argument %s is invalid!\n", cmd);
- return -EINVAL;
- }
-
- return n;
-}
-
+++ /dev/null
-#ifndef _CLK_AUTO_VOLT_H_
-#define _CLK_AUTO_VOLT_H_
-ssize_t clk_auto_volt_show(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf);
-ssize_t clk_auto_volt_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n);
-
-#endif
+++ /dev/null
-#include <linux/clk.h>
-#include <linux/kobject.h>
-#include <linux/string.h>
-#include <linux/resume-trace.h>
-#include <linux/workqueue.h>
-#include <linux/mutex.h>
-#include <linux/module.h>
-#include <linux/syscalls.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/cpu.h>
-#include <linux/slab.h>
-#include <linux/dma-mapping.h>
-#include <linux/regulator/machine.h>
-#include <plat/dma-pl330.h>
-#include <linux/mfd/wm831x/core.h>
-#include <linux/sysfs.h>
-#include <linux/err.h>
-#include <mach/ddr.h>
-#include <mach/dvfs.h>
-
-#include <linux/fs.h>
-#include <asm/unistd.h>
-#include <asm/uaccess.h>
-#include "rk_pm_tests.h"
-#include "clk_rate.h"
-/***************************************************************************/
-#define FILE_GOV_MODE "/sys/devices/system/cpu/cpu0/cpufreq/scaling_governor"
-#define FILE_SETSPEED "/sys/devices/system/cpu/cpu0/cpufreq/scaling_setspeed"
-#define FILE_CUR_FREQ "/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq"
-
-static int file_read(char *file_path, char *buf)
-{
- struct file *file = NULL;
- mm_segment_t old_fs;
- loff_t offset = 0;
-
- PM_DBG("read %s\n", file_path);
- file = filp_open(file_path, O_RDONLY, 0);
-
- if (IS_ERR(file)) {
- PM_ERR("%s error open file %s\n", __func__, file_path);
- return -1;
- }
-
- old_fs = get_fs();
- set_fs(KERNEL_DS);
-
- file->f_op->read(file, (char *)buf, 32, &offset);
- sscanf(buf, "%s", buf);
-
- set_fs(old_fs);
- filp_close(file, NULL);
-
- file = NULL;
-
- return 0;
-
-}
-
-static int file_write(char *file_path, char *buf)
-{
- struct file *file = NULL;
- mm_segment_t old_fs;
- loff_t offset = 0;
-
- PM_DBG("write %s %s size = %d\n", file_path, buf, strlen(buf));
- file = filp_open(file_path, O_RDWR, 0);
-
- if (IS_ERR(file)) {
- PM_ERR("%s error open file %s\n", __func__, file_path);
- return -1;
- }
-
- old_fs = get_fs();
- set_fs(KERNEL_DS);
-
- file->f_op->write(file, (char *)buf, strlen(buf), &offset);
-
- set_fs(old_fs);
- filp_close(file, NULL);
-
- file = NULL;
-
- return 0;
-
-}
-
-ssize_t clk_rate_show(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf)
-{
- char *str = buf;
- str += sprintf(str, "set [clk_name] [rate(Hz)]\n"
- "reset [clk_name] [rate(Hz) = 0]\n");
- if (str != buf)
- *(str - 1) = '\n';
- return (str - buf);
-
-}
-
-ssize_t clk_rate_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n)
-{
- char cmd[20], clk_name[20], msg[50];
- int rate;
- struct clk *clk;
- sscanf(buf, "%s %s %d", cmd, clk_name, &rate);
-
-
- clk = clk_get(NULL, clk_name);
- if (IS_ERR(clk)) {
- PM_ERR("%s get clk %s error\n", __func__, clk_name);
- return n;
- }
-
- if (0 == strncmp(cmd, "set", strlen("set"))) {
- PM_DBG("Get command set %s %dHz\n", clk_name, rate);
- if (file_read(FILE_GOV_MODE, msg) != 0) {
- PM_ERR("read current governor error\n");
- return n;
- } else {
- PM_DBG("current governor = %s\n", msg);
- }
-
- strcpy(msg, "userspace");
- if (file_write(FILE_GOV_MODE, msg) != 0) {
- PM_ERR("set current governor error\n");
- return n;
- }
-
- dvfs_clk_enable_limit(clk, rate, rate);
- clk_set_rate(clk, rate);
-
- } else if (0 == strncmp(cmd, "reset", strlen("reset"))) {
- PM_DBG("Get command reset %s\n", clk_name);
- if (file_read(FILE_GOV_MODE, msg) != 0) {
- PM_ERR("read current governor error\n");
- return n;
- } else {
- PM_DBG("current governor = %s\n", msg);
- }
-
- strcpy(msg, "interactive");
- if (file_write(FILE_GOV_MODE, msg) != 0) {
- PM_ERR("set current governor error\n");
- return n;
- }
-
- dvfs_clk_disable_limit(clk);
- }
-
- return n;
-}
-
+++ /dev/null
-#ifndef _CLK_RATE_H_
-#define _CLK_RATE_H_
-ssize_t clk_rate_show(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf);
-ssize_t clk_rate_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n);
-
-#endif
+++ /dev/null
-#include <linux/clk.h>
-#include <linux/kobject.h>
-#include <linux/string.h>
-#include <linux/resume-trace.h>
-#include <linux/workqueue.h>
-#include <linux/mutex.h>
-#include <linux/module.h>
-#include <linux/syscalls.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/cpu.h>
-#include <linux/slab.h>
-#include <linux/dma-mapping.h>
-#include <linux/regulator/machine.h>
-#include <plat/dma-pl330.h>
-#include <linux/mfd/wm831x/core.h>
-#include <linux/sysfs.h>
-#include <linux/err.h>
-#include <mach/ddr.h>
-#include <mach/dvfs.h>
-
-#include "rk_pm_tests.h"
-#include "clk_volt.h"
-/***************************************************************************/
-ssize_t clk_volt_show(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf)
-{
- char *str = buf;
- str += sprintf(str, "usage:\n");
- str += sprintf(str, "get voltage:get [regulaotr_name]\n");
- str += sprintf(str, "set voltage:set [regulaotr_name] [voltage(uV)]\n");
- str += sprintf(str, "set suspend voltage:set [regulaotr_name] [voltage(uV)+1]\n");
- if (str != buf)
- *(str - 1) = '\n';
- return (str - buf);
-
-}
-
-#define SET_SUSPEND_VOLT_FLAG (1<<0)
-
-ssize_t clk_volt_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n)
-{
- char cmd[20], regulator_name[20];
- unsigned int volt;
- int ret = 0;
- int need_put_regulator=0;
- struct regulator *regulator;
-
- sscanf(buf, "%s %s %u", cmd, regulator_name, &volt);
-
- regulator = dvfs_get_regulator(regulator_name);
- if (IS_ERR_OR_NULL(regulator)) {
- regulator = regulator_get(NULL, regulator_name);
- if (IS_ERR(regulator)){
- PM_ERR("%s get dvfs_regulator %s error\n", __func__, regulator_name);
- return n;
- }
- need_put_regulator = 1;
- }
-
- if (0 == strncmp(cmd, "set", strlen("set"))){
- if (volt & SET_SUSPEND_VOLT_FLAG){
- volt &= ~SET_SUSPEND_VOLT_FLAG;
- ret = regulator_set_suspend_voltage(regulator, volt);
- if (!ret)
- printk("set %s suspend volt to %uuV ok\n", regulator_name, volt);
- else
- printk("regulator_set_suspend_voltage err:%d\n", ret);
- }else{
- ret = regulator_set_voltage(regulator, volt, volt);
- if (!ret)
- printk("set %s volt to %uuV ok\n", regulator_name, regulator_get_voltage(regulator));
- else
- printk("regulator_set_voltage err:%d\n", ret);
- }
-
- }
- if (0 == strncmp(cmd, "get", strlen("get"))){
- printk("%s:%duV\n", regulator_name, regulator_get_voltage(regulator));
- }
-
- if (need_put_regulator)
- regulator_put(regulator);
-
-// if (0 == strncmp(cmd, "enable", strlen("enable"))) {
- return n;
-}
-
+++ /dev/null
-#ifndef _CLK_VOLT_H_
-#define _CLK_VOLT_H_
-ssize_t clk_volt_show(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf);
-ssize_t clk_volt_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n);
-
-#endif
+++ /dev/null
-#include <linux/clk.h>
-#include <linux/kobject.h>
-#include <linux/string.h>
-#include <linux/resume-trace.h>
-#include <linux/workqueue.h>
-#include <linux/mutex.h>
-#include <linux/module.h>
-#include <linux/syscalls.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/cpu.h>
-#include <linux/slab.h>
-#include <linux/dma-mapping.h>
-#include <linux/regulator/machine.h>
-#include <plat/dma-pl330.h>
-#include <linux/mfd/wm831x/core.h>
-#include <linux/sysfs.h>
-#include <linux/err.h>
-#include <mach/cru.h>
-#include <mach/dvfs.h>
-#include <mach/sram.h>
-#include <linux/random.h>
-
-#include <linux/fs.h>
-#include <asm/unistd.h>
-#include <asm/uaccess.h>
-#include "rk_pm_tests.h"
-#include "cpu_usage.h"
-/***************************************************************************/
-static DEFINE_PER_CPU(struct work_struct, work_cpu_usage);
-static DEFINE_PER_CPU(struct workqueue_struct *, workqueue_cpu_usage);
-
-int cpu_usage_run = 0;
-int cpu_usage_percent = 0;
-
-struct timer_list arm_mode_timer;
-#define ARM_MODE_TIMER_MSEC 100
-static void arm_mode_timer_handler(unsigned long data)
-{
- int i;
- PM_DBG("enter %s\n", __func__);
- if (cpu_usage_run == 0) {
- PM_DBG("STOP\n");
- return ;
- }
-
- arm_mode_timer.expires = jiffies + msecs_to_jiffies(ARM_MODE_TIMER_MSEC);
- add_timer(&arm_mode_timer);
- for(i = 0; i < cpu_usage_percent; i++) {
- mdelay(1);
- }
-}
-
-static void handler_cpu_usage(struct work_struct *work)
-{
-#if 1
- while(cpu_usage_run) {
- barrier();
- }
-#else
- del_timer(&arm_mode_timer);
- arm_mode_timer.expires = jiffies + msecs_to_jiffies(ARM_MODE_TIMER_MSEC);
- add_timer(&arm_mode_timer);
-#endif
-}
-ssize_t cpu_usage_show(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf)
-{
- char *str = buf;
- str += sprintf(str, "HELLO\n");
- if (str != buf)
- *(str - 1) = '\n';
- return (str - buf);
-
-}
-ssize_t cpu_usage_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n)
-{
- struct workqueue_struct *workqueue;
- struct work_struct *work;
- char cmd[20];
- int usage = 0;
- int cpu;
-
- sscanf(buf, "%s %d", cmd, &usage);
-
- if((strncmp(cmd, "start", strlen("start")) == 0)) {
- PM_DBG("get cmd start\n");
- cpu_usage_run = 1;
-
- cpu_usage_percent = (ARM_MODE_TIMER_MSEC * usage) / 100;
-
-
- for_each_online_cpu(cpu){
- work = &per_cpu(work_cpu_usage, cpu);
- workqueue = per_cpu(workqueue_cpu_usage, cpu);
- if (!work || !workqueue){
- PM_ERR("work or workqueue NULL\n");
- return n;
- }
- queue_work_on(cpu, workqueue, work);
- }
-#if 0
- del_timer(&arm_mode_timer);
- arm_mode_timer.expires = jiffies + msecs_to_jiffies(ARM_MODE_TIMER_MSEC);
- add_timer(&arm_mode_timer);
-#endif
-
- } else if (strncmp(cmd, "stop", strlen("stop")) == 0) {
- PM_DBG("get cmd stop\n");
- cpu_usage_run = 0;
- }
-
- return n;
-}
-
-static int __init cpu_usage_init(void)
-{
- struct workqueue_struct **workqueue;
- struct work_struct *work;
- int cpu;
-
- for_each_online_cpu(cpu){
- work = &per_cpu(work_cpu_usage, cpu);
- workqueue = &per_cpu(workqueue_cpu_usage, cpu);
- if (!work || !workqueue){
- PM_ERR("work or workqueue NULL\n");
- return -1;
- }
-
- *workqueue = create_singlethread_workqueue("workqueue_cpu_usage");
- INIT_WORK(work, handler_cpu_usage);
- }
-
- setup_timer(&arm_mode_timer, arm_mode_timer_handler, (unsigned int)NULL);
- return 0;
-}
-late_initcall(cpu_usage_init);
+++ /dev/null
-#ifndef _CPU_USAGE_H_
-#define _CPU_USAGE_H_
-ssize_t cpu_usage_show(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf);
-ssize_t cpu_usage_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n);
-
-#endif
+++ /dev/null
-#include <linux/clk.h>
-#include <linux/kobject.h>
-#include <linux/string.h>
-#include <linux/resume-trace.h>
-#include <linux/workqueue.h>
-#include <linux/mutex.h>
-#include <linux/module.h>
-#include <linux/syscalls.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/cpu.h>
-#include <linux/slab.h>
-#include <linux/dma-mapping.h>
-#include <linux/regulator/machine.h>
-#include <plat/dma-pl330.h>
-#include <linux/mfd/wm831x/core.h>
-#include <linux/sysfs.h>
-#include <linux/err.h>
-#include <linux/cpufreq.h>
-#include <mach/ddr.h>
-#include <mach/dvfs.h>
-
-#include <linux/fs.h>
-#include <asm/unistd.h>
-#include <asm/uaccess.h>
-#include "rk_pm_tests.h"
-#include "delayline.h"
-/***************************************************************************/
-#define ARM_MODE_TIMER_MSEC 500
-static int delayline_time_msec = ARM_MODE_TIMER_MSEC;
-
-static struct timer_list delayline_timer;
-int running = 0;
-extern int rk3188_get_delayline_value(void);
-
-static void timer_handler(unsigned long data)
-{
- int delayline = rk3188_get_delayline_value();
- PM_DBG("enter %s\n", __func__);
-
- if (running == 0) {
- PM_DBG("STOP\n");
- return ;
- }
-
- mod_timer(&delayline_timer, jiffies + msecs_to_jiffies(delayline_time_msec));
- printk("Current delayline value = %d\n", delayline);
-}
-
-ssize_t delayline_show(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf)
-{
- char *str = buf;
- int delayline = rk3188_get_delayline_value();
- str += sprintf(str, "Current delayline value = %d\necho start [time] > delayline\n", delayline);
- if (str != buf)
- *(str - 1) = '\n';
- return (str - buf);
-
-}
-
-ssize_t delayline_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n)
-{
-
- char cmd[20];
- sscanf(buf, "%s %d", cmd, &delayline_time_msec);
-
- if((strncmp(cmd, "start", strlen("start")) == 0)) {
- PM_DBG("get cmd start, time = %d\n", delayline_time_msec);
- running = 1;
- delayline_timer.expires = jiffies + msecs_to_jiffies(delayline_time_msec);
- add_timer(&delayline_timer);
- }else if ((strncmp(cmd, "stop", strlen("stop")) == 0)) {
- PM_DBG("get cmd stop\n");
- running = 0;
- }
- return n;
-}
-
-static int __init delayline_init(void)
-{
- setup_timer(&delayline_timer, timer_handler, (unsigned int)NULL);
- return 0;
-}
-late_initcall(delayline_init);
+++ /dev/null
-#ifndef _DELAYLINE_H_
-#define _DELAYLINE_H_
-ssize_t delayline_show(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf);
-ssize_t delayline_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n);
-
-#endif
+++ /dev/null
-#include <linux/clk.h>
-#include <linux/kobject.h>
-#include <linux/string.h>
-#include <linux/resume-trace.h>
-#include <linux/workqueue.h>
-#include <linux/mutex.h>
-#include <linux/module.h>
-#include <linux/syscalls.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/cpu.h>
-#include <linux/slab.h>
-#include <linux/dma-mapping.h>
-#include <linux/regulator/machine.h>
-#include <plat/dma-pl330.h>
-#include <linux/mfd/wm831x/core.h>
-#include <linux/sysfs.h>
-#include <linux/err.h>
-#include <mach/ddr.h>
-#include <mach/dvfs.h>
-#include <linux/cpufreq.h>
-
-#include "rk_pm_tests.h"
-#include "dvfs_table_reset.h"
-/***************************************************************************/
-#define ARM_TABLE_CHANGE 1
-#define GPU_TABLE_CHANGE 0
-#define DDR_TABLE_CHANGE 0
-#define VOLT_MODIFY_FREQ_L 37500
-#define VOLT_MODIFY_FREQ_H 25000
-#if ARM_TABLE_CHANGE
-static struct cpufreq_frequency_table *arm_table;
-#endif
-#if GPU_TABLE_CHANGE
-static struct cpufreq_frequency_table *gpu_table;
-#endif
-#if DDR_TABLE_CHANGE
-static struct cpufreq_frequency_table *ddr_table;
-#endif
-struct clk *clk_arm, *clk_gpu, *clk_ddr;
-static int __init dvfs_table_reset_init(void)
-{
- int i = 0;
- printk("get arm clk OK\n");
-#if ARM_TABLE_CHANGE
- clk_arm = clk_get(NULL, "cpu");
- if (IS_ERR(clk_arm))
- return PTR_ERR(clk_arm);
- PM_DBG("get arm clk OK\n");
- arm_table = dvfs_get_freq_volt_table(clk_arm);
-
- for (i = 0; arm_table[i].frequency != CPUFREQ_TABLE_END; i++) {
- if (arm_table[i].frequency <= 1008 * 1000) {
- printk("%s: set freq(%d), volt(%d), modify(%d)\n", __func__,
- arm_table[i].frequency, arm_table[i].index, VOLT_MODIFY_FREQ_L);
- arm_table[i].index -= VOLT_MODIFY_FREQ_L;
- printk("%s: set freq(%d), volt(%d), modify(%d)\n", __func__,
- arm_table[i].frequency, arm_table[i].index, VOLT_MODIFY_FREQ_L);
- } else {
- printk("%s: set freq(%d), volt(%d), modify(%d)\n", __func__,
- arm_table[i].frequency, arm_table[i].index, VOLT_MODIFY_FREQ_H);
- arm_table[i].index -= VOLT_MODIFY_FREQ_H;
- printk("%s: set freq(%d), volt(%d), modify(%d)\n", __func__,
- arm_table[i].frequency, arm_table[i].index, VOLT_MODIFY_FREQ_H);
- }
- }
- dvfs_set_freq_volt_table(clk_arm, arm_table);
-#endif
-
-#if GPU_TABLE_CHANGE
- clk_gpu = clk_get(NULL, "gpu");
- if (IS_ERR(clk_gpu))
- return PTR_ERR(clk_gpu);
- PM_DBG("get gpu clk OK\n");
- gpu_table = dvfs_get_freq_volt_table(clk_gpu);
-
- for (i = 0; gpu_table[i].frequency != CPUFREQ_TABLE_END; i++) {
- gpu_table[i].index -= VOLT_MODIFY_FREQ_H;
- }
- dvfs_set_freq_volt_table(clk_gpu, gpu_table);
-#endif
-
-#if DDR_TABLE_CHANGE
- clk_ddr = clk_get(NULL, "ddr");
- if (IS_ERR(clk_ddr))
- return PTR_ERR(clk_ddr);
- PM_DBG("get ddr clk OK\n");
- ddr_table = dvfs_get_freq_volt_table(clk_ddr);
-
- for (i = 0; gpu_table[i].frequency != CPUFREQ_TABLE_END; i++) {
- ddr_table[i] -= VOLT_MODIFY_FREQ_H;
- }
- dvfs_set_freq_volt_table(clk_ddr, ddr_table);
-#endif
-
- return 0;
-}
-
-static void __exit dvfs_table_reset_exit(void)
-{
- int i = 0;
-#if ARM_TABLE_CHANGE
- for (i = 0; arm_table[i].frequency != CPUFREQ_TABLE_END; i++) {
- if (arm_table[i].frequency <= 1008 * 1000)
- arm_table[i].index += VOLT_MODIFY_FREQ_L;
- else
- arm_table[i].index += VOLT_MODIFY_FREQ_H;
- }
- dvfs_set_freq_volt_table(clk_arm, arm_table);
-#endif
-
-#if GPU_TABLE_CHANGE
- for (i = 0; gpu_table[i].frequency != CPUFREQ_TABLE_END; i++) {
- gpu_table[i].index += VOLT_MODIFY_FREQ_H;
- }
- dvfs_set_freq_volt_table(clk_gpu, gpu_table);
-#endif
-
-#if DDR_TABLE_CHANGE
- for (i = 0; ddr_table[i].frequency != CPUFREQ_TABLE_END; i++) {
- ddr_table[i].index += VOLT_MODIFY_FREQ_H;
- }
- dvfs_set_freq_volt_table(clk_ddr, ddr_table);
-#endif
-
-}
-
-module_init(dvfs_table_reset_init);
-module_exit(dvfs_table_reset_exit);
+++ /dev/null
-#ifndef _DVFS_TABLE_RESET_H_
-#define _DVFS_TABLE_RESET_H_
-ssize_t dvfs_table_reset_show(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf);
-ssize_t dvfs_table_reset_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n);
-
-#endif
+++ /dev/null
-#include <linux/clk.h>
-#include <linux/kobject.h>
-#include <linux/string.h>
-#include <linux/resume-trace.h>
-#include <linux/workqueue.h>
-#include <linux/mutex.h>
-#include <linux/module.h>
-#include <linux/syscalls.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/cpu.h>
-#include <linux/slab.h>
-#include <linux/dma-mapping.h>
-#include <linux/regulator/machine.h>
-#include <plat/dma-pl330.h>
-#include <linux/mfd/wm831x/core.h>
-#include <linux/sysfs.h>
-#include <linux/err.h>
-#include <mach/ddr.h>
-#include <mach/dvfs.h>
-
-#include <linux/fs.h>
-#include <asm/unistd.h>
-#include <asm/uaccess.h>
-#include "rk_pm_tests.h"
-#include "maxfreq.h"
-#include "rk_pm_tests.h"
-#include "dvfs_table_scan.h"
-/***************************************************************************/
-#if defined(CONFIG_ARCH_RK3026)
-#define TTYS3_FILE_PATH "/dev/ttyS1"
-#else
-#define TTYS3_FILE_PATH "/dev/ttyS3"
-#endif
-struct workqueue_struct *workqueue_dvfs_table_scan;
-struct work_struct work_dvfs_table_scan;
-struct timer_list dvfs_table_scan_timer;
-#define DVFS_TABLE_T_MSEC 1000
-struct file *file = NULL;
-mm_segment_t old_fs;
-loff_t offset = 0;
-static int dvfs_table_scan_run = 0;
-static int file_read(char *file_path, char *buf)
-{
- PM_DBG("read %s\n", file_path);
-
- file->f_op->read(file, (char *)buf, 32, &offset);
-
- return 0;
-}
-
-static int file_write(char *file_path, char *buf)
-{
- PM_DBG("write %s %s size = %d\n", file_path, buf, strlen(buf));
-
- file->f_op->write(file, (char *)buf, strlen(buf), &offset);
-
- return 0;
-}
-static void dvfs_table_scan_timer_handler(unsigned long data)
-{
- //PM_DBG("enter %s\n", __func__);
- char sendbuf[20];
- //static int sendcnt = 0;
- memset(sendbuf, 0, sizeof(sendbuf));
- if (dvfs_table_scan_run == 0) {
- PM_DBG("%s: STOP\n", __func__);
- return ;
- }
- //sprintf(sendbuf, "alive%d", sendcnt++);
- sprintf(sendbuf, "alive");
- PM_DBG("Sending alive signal...... %s\n", sendbuf);
- file_write(TTYS3_FILE_PATH, sendbuf);
-
- mod_timer(&dvfs_table_scan_timer, jiffies + msecs_to_jiffies(DVFS_TABLE_T_MSEC));
-}
-static void handler_dvfs_table_scan(struct work_struct *work)
-{
- char buf[100];
- int ret = 0;
- while (dvfs_table_scan_run) {
- memset(buf, 0, sizeof(buf));
- ret = file_read(TTYS3_FILE_PATH, buf);
- //if (ret < 0)
- // PM_ERR("read error %d\n", ret);
- if (strlen(buf) != 0)
- PM_DBG("%s: get %s|len=%d\n", __func__, buf, strlen(buf));
- //mdelay(100);
- }
-}
-
-static void uart_init(void)
-{
- file = filp_open(TTYS3_FILE_PATH, O_RDWR | O_NOCTTY, 0);
- //file = filp_open(TTYS3_FILE_PATH, O_RDWR, 0);
- if (IS_ERR(file)) {
- PM_ERR("%s error open file %s\n", __func__, TTYS3_FILE_PATH);
- return ;
- }
- old_fs = get_fs();
- set_fs(KERNEL_DS);
-}
-static void uart_deinit(void)
-{
- set_fs(old_fs);
- filp_close(file, NULL);
-}
-ssize_t dvfs_table_scan_show(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf)
-{
- char *str = buf;
- str += sprintf(str, "start: \tstart scan dvfs table, send alive every 1s\n"
- "stop: \tstop send alive signal\n");
- if (str != buf)
- *(str - 1) = '\n';
- return (str - buf);
-
-}
-ssize_t dvfs_table_scan_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n)
-{
- char cmd[20];
-
- sscanf(buf, "%s", cmd);
- PM_DBG("%s: get command <%s>\n", __func__, cmd);
- if (0 == strncmp(cmd, "start", strlen("start"))) {
- uart_init();
- dvfs_table_scan_run = 1;
- file_write(TTYS3_FILE_PATH, "start");
- //queue_work(workqueue_dvfs_table_scan, &work_dvfs_table_scan);
- //dvfs_table_scan_timer.expires = jiffies + msecs_to_jiffies(DVFS_TABLE_T_MSEC);
- //add_timer(&dvfs_table_scan_timer);
- uart_deinit();
-
- } else if (0 == strncmp(cmd, "alive", strlen("alive"))) {
- uart_init();
- file_write(TTYS3_FILE_PATH, "alive");
- uart_deinit();
-
- } else if (0 == strncmp(cmd, "stop", strlen("stop"))) {
- uart_init();
- file_write(TTYS3_FILE_PATH, "stop");
- dvfs_table_scan_run = 0;
- uart_deinit();
- }
- return n;
-}
-
-static int __init dvfs_table_scan_init(void)
-{
- workqueue_dvfs_table_scan = create_singlethread_workqueue("workqueue_dvfs_table_scan");
- INIT_WORK(&work_dvfs_table_scan, handler_dvfs_table_scan);
- setup_timer(&dvfs_table_scan_timer, dvfs_table_scan_timer_handler, (unsigned int)NULL);
- return 0;
-}
-late_initcall(dvfs_table_scan_init);
+++ /dev/null
-#ifndef _DVFS_TABLE_SCAN_H_
-#define _DVFS_TABLE_SCAN_H_
-ssize_t dvfs_table_scan_show(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf);
-ssize_t dvfs_table_scan_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n);
-
-#endif
+++ /dev/null
-#include <linux/clk.h>
-#include <linux/kobject.h>
-#include <linux/string.h>
-#include <linux/resume-trace.h>
-#include <linux/workqueue.h>
-#include <linux/mutex.h>
-#include <linux/module.h>
-#include <linux/syscalls.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/cpu.h>
-#include <linux/slab.h>
-#include <linux/dma-mapping.h>
-#include <linux/regulator/machine.h>
-#include <plat/dma-pl330.h>
-#include <linux/mfd/wm831x/core.h>
-#include <linux/sysfs.h>
-#include <linux/err.h>
-#include <mach/ddr.h>
-#include <mach/dvfs.h>
-
-#include "rk_pm_tests.h"
-#include "freq_limit.h"
-/***************************************************************************/
-ssize_t freq_limit_show(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf)
-{
- char *str = buf;
- str += sprintf(str, "command(enable/disable) clk_name min_rate max_rate\n");
- if (str != buf)
- *(str - 1) = '\n';
- return (str - buf);
-
-}
-
-ssize_t freq_limit_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n)
-{
- char cmd[20], clk_name[20];
- unsigned int min_rate, max_rate;
- struct clk *clk;
- sscanf(buf, "%s %s %u %u", cmd, clk_name, &min_rate, &max_rate);
-
- clk = clk_get(NULL, clk_name);
- if (IS_ERR(clk)) {
- PM_ERR("get clk %s error\n", __func__);
- return n;
- }
-
- if (0 == strncmp(cmd, "enable", strlen("enable"))) {
- PM_DBG("limit enable clk(%s) min(%d) max(%d)\n", clk_name, min_rate, max_rate);
- dvfs_clk_enable_limit(clk, min_rate, max_rate);
-
- } else if (0 == strncmp(cmd, "disable", strlen("disable"))) {
- PM_DBG("limit disable clk(%s)\n", clk_name);
- dvfs_clk_disable_limit(clk);
-
- } else {
- PM_ERR("unknown command\n");
- }
- return n;
-}
-
+++ /dev/null
-#ifndef _FREQ_LIMIT_H_
-#define _FREQ_LIMIT_H_
-ssize_t freq_limit_show(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf);
-ssize_t freq_limit_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n);
-
-#endif
+++ /dev/null
-obj-y += ft_cpu_tst.o
-obj-y += ft_cpu_tst1.o
-obj-y += ft_test.o
-obj-y += ft_pwm.o
+++ /dev/null
-
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-//#include <asm/memory.h>
-//#include <mach/io.h>
-
-.text
-
-
- //_off 12 -20
- .macro test_cpus_pc_jump , _base,_reg, _off
-
- ldr \_reg,[pc]
- str \_reg,[\_base]
- mov \_reg,pc
- str \_reg,[\_base,#4]
- add \_reg,\_off //pc offset
- str \_reg,[\_base,#8]// offset start
- ldr pc, [\_base,#8]
- ldr \_reg,[pc]
- ldr \_reg,[pc]
- .endm
-
-
- .macro cpus_tst_get_opcode, _reg0
- lsl \_reg0,\_reg0,#4
- lsr \_reg0,\_reg0,#24
- .endm
-
-
- .macro cpus_tst_code_lsl , _reg0
- ldr \_reg0,[pc]
- mov \_reg0,\_reg0
- lsl \_reg0,\_reg0,#4
- lsr \_reg0,\_reg0,#24
- cmp \_reg0,#0x1a
- bne l1_test_error
- .endm
-
- .macro cpus_tst_code_lsr , _reg0
- ldr \_reg0,[pc]
- lsl \_reg0,\_reg0,#4
- lsr \_reg0,\_reg0,#24
- cmp \_reg0,#0x1a
- bne l1_test_error
- .endm
-
-
- .macro cpus_tst_code_cmp, _reg0
- ldr \_reg0,[pc,#4]
- lsl \_reg0,\_reg0,#4
- lsr \_reg0,\_reg0,#24
- cmp \_reg0,#0x35
- bne l1_test_error
- .endm
-
-
-
- .macro cpus_tst_code_sub, _reg0,_reg1
- mov \_reg0,pc
- sub \_reg0,#4
- ldr \_reg1,[\_reg0]
- lsl \_reg1,\_reg1,#4
- lsr \_reg1,\_reg1,#24
- cmp \_reg1,#0x24
- bne l1_test_error
- .endm
-
-
- .macro cpus_tst_code_ldr, _reg0,_reg1
- mov \_reg0,pc
- sub \_reg0,#0
- ldr \_reg1,[\_reg0]
- lsl \_reg1,\_reg1,#4
- lsr \_reg1,\_reg1,#24
- cmp \_reg1,#0x59
- bne l1_test_error
- .endm
-
- .macro cpus_tst_code_bne, _reg0,_reg1
- ldr \_reg0,[pc,#12]
-
- lsr \_reg1,\_reg0,#28
- lsl \_reg0,\_reg0,#4
- lsr \_reg0,\_reg0,#24
-
- cmp \_reg1,#0x1 //
- bne l1_test_error
- cmp \_reg0,#0xa0
- bne l1_test_error
-
- .endm
-
-
-
-.macro test_cpus_l1_code_base
- //r4 base
- mov r5,#16
- test_cpus_pc_jump r4,r3,r5
-
- //add r4,#8
- mov r6,r4
- mov r8,#20
- test_cpus_pc_jump r6,r7,r8
-
- //add r4,#8
-
- cpus_tst_code_lsl r5
-
- cpus_tst_code_lsr r7
-
- cpus_tst_code_cmp r9
-
-
- cpus_tst_code_sub r11,r10,
-
- cpus_tst_code_ldr r12,r8
-
- cpus_tst_code_bne r6,r7
-
-.endm
-
-
-.macro test_cpus_l1_code_base_
-
-
- mov r4,r4
- mov r6,r6
- mov r7,r7
- mov r8,r8
- mov r4,r4
- mov r6,r6
- mov r7,r7
- mov r8,r8
- mov r4,r4
- mov r6,r6
-
- mov r4,r4
- mov r6,r6
- mov r7,r7
- mov r8,r8
- mov r4,r4
- mov r6,r6
- mov r7,r7
- mov r8,r8
- mov r4,r4
- mov r6,r6
-
-
-
- mov r7,r7
- mov r8,r8
- mov r4,r4
- mov r6,r6
- mov r7,r7
-
-
-
-
-
-
-.endm
-
-
-.macro test_cpus_l1_loop_100
-
-.endm
-
-.macro test_cpus_l1_loop_500
-#if 1
- test_cpus_l1_code_base
- test_cpus_l1_code_base
-#else
-
- test_cpus_l1_code_base_
- test_cpus_l1_code_base_
-
- test_cpus_l1_code_base_
- test_cpus_l1_code_base_
- test_cpus_l1_code_base_
-
- test_cpus_l1_code_base_
-
-#endif
-.endm
-
-
-.macro test_cpus_l1_loop_1_k
- test_cpus_l1_loop_500
- test_cpus_l1_loop_500
-.endm
-
-
-.macro test_cpus_l1_loop_4_k
- test_cpus_l1_loop_1_k
- test_cpus_l1_loop_1_k
- test_cpus_l1_loop_1_k
- test_cpus_l1_loop_1_k
- test_cpus_l1_loop_500
-.endm
-
-
-
-.macro test_cpus_l1_loop_10_k
- test_cpus_l1_loop_4_k
- test_cpus_l1_loop_4_k
- test_cpus_l1_loop_4_k
- test_cpus_l1_loop_4_k
-.endm
-
-
-.macro test_cpus_l1_loop_50_k
- test_cpus_l1_loop_10_k
- test_cpus_l1_loop_10_k
- test_cpus_l1_loop_10_k
- test_cpus_l1_loop_10_k
- test_cpus_l1_loop_10_k
-.endm
-
-.macro test_cpus_l1_loop_200_k
- test_cpus_l1_loop_50_k
- test_cpus_l1_loop_50_k
- test_cpus_l1_loop_50_k
- test_cpus_l1_loop_50_k
-
-.endm
-
-
+++ /dev/null
-
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include "cpu_test.h"
-
-.text
-
-//r0,array0
-ENTRY(test_cpus_l0)
-
- stmfd sp!, { r1 - r12, lr }
-1: mov r0,r0
- //b 1b
- mov r4,r0
-
- test_cpus_l1_loop_200_k
- test_cpus_l1_loop_200_k
- test_cpus_l1_loop_200_k
- test_cpus_l1_loop_200_k
- test_cpus_l1_loop_200_k
-
- test_cpus_l1_loop_200_k
- test_cpus_l1_loop_200_k
- test_cpus_l1_loop_200_k
- test_cpus_l1_loop_200_k
- test_cpus_l1_loop_200_k
-
- //test_cpus_l1_loop_200_k
- //test_cpus_l1_loop_200_k
- //test_cpus_l1_loop_200_k
-
-
-1: mov r1,r1
- //b 1b
- ldmfd sp!, { r1 - r12, pc }
-l1_test_error:
- mov r1,r1
- mov r1,r1
- mov r1,r1
- 1: mov r1,r1
- b 1b
-ENDPROC(test_cpus_l0)
-
-
-//r0 adr base,r1 end adr,r2 tst date
-ENTRY(test_cpus_l2)
-
- stmfd sp!, { r3 - r12, lr }
-1: mov r0,r0
- //b 1b
-
- mov r4,r0
- sub r5,r1,#4
-
-l2_write:
- str r2,[r4],#4
-
- cmp r4,r5
- bls l2_write
-
- mov r4,r0
-l2_check:
- ldr r6,[r4],#4
- cmp r6,r2
- bne l2_test_error
- mov r6,#0
- cmp r4,r5
- bhi l2_tst_end
-
- ldr r7,[r4],#4
- cmp r7,r2
- bne l2_test_error
- mov r7,#0
-
- cmp r4,r5
- bls l2_check
-
-l2_tst_end:
-3: mov r0,#0
- //b 3b
- ldmfd sp!, { r3 - r12, pc }
-l2_test_error:
-1: mov r0,#1
- //b 1b
- ldmfd sp!, { r3 - r12, pc }
-ENDPROC(test_cpus_l2)
-
-//r0 adr base,r1 end adr,r2 tst date
-ENTRY(test_cpus_mem_set)
-
- stmfd sp!, { r3 - r12, lr }
-1: mov r0,r0
- //b 1b
-
- mov r4,r0
- sub r5,r1,#4
-
-mem_set:
- str r2,[r4],#4
-
- cmp r4,r5
- bls mem_set
-
-1: mov r0,#1
- //b 1b
- ldmfd sp!, { r3 - r12, pc }
-ENDPROC(test_cpus_mem_set)
-
-
-
-//r0 adr base,r1 end adr,r2 tst date
-ENTRY(test_cpus_mem_check)
-
- stmfd sp!, { r3 - r12, lr }
-1: mov r0,r0
- //b 1b
- mov r4,r0
- sub r5,r1,#4
-
-mem_check:
- ldr r6,[r4],#4
- cmp r6,r2
- bne mem_check_error
- mov r6,#0
- cmp r4,r5
- bhi mem_check_end
-
- ldr r7,[r4],#4
- cmp r7,r2
- bne mem_check_error
- mov r7,#0
-
- cmp r4,r5
- bls mem_check
-
-mem_check_end:
-3: mov r0,#0
- //b 3b
- ldmfd sp!, { r3 - r12, pc }
-mem_check_error:
-1: mov r0,#1
- //b 1b
- ldmfd sp!, { r3 - r12, pc }
-
-ENDPROC(test_cpus_mem_check)
-/***************while for dbg***************/
-ENTRY(rk30_cpu_while_tst)
-stmfd sp!, { r3 - r12, lr }
-
-1: mov r3,r3
- b 1b
-
-ldmfd sp!, { r3 - r12, pc }
-
-ENDPROC(rk30_cpu_while_tst)
-
+++ /dev/null
-
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-//#include <asm/memory.h>
-//#include <mach/io.h>
-#include "cpu_test.h"
-
-.text
-
-//r0,array0
-ENTRY(test_cpus_l1)
- stmfd sp!, { r1 - r12, lr }
-1: mov r0,r0
- //b 1b
- mov r4,r0
-
- test_cpus_l1_loop_200_k
- test_cpus_l1_loop_200_k
- test_cpus_l1_loop_200_k
- test_cpus_l1_loop_200_k
- test_cpus_l1_loop_200_k
-
-
- test_cpus_l1_loop_200_k
- test_cpus_l1_loop_200_k
- test_cpus_l1_loop_200_k
- test_cpus_l1_loop_200_k
- test_cpus_l1_loop_200_k
-
-
-1: mov r1,r1
- //b 1b
- ldmfd sp!, { r1- r12, pc }
-l1_test_error:
-1: mov r1,r1
- b 1b
-ENDPROC(test_cpus_l1)
-
-
-
-
-
-
-
+++ /dev/null
-/*
- *
- * Copyright (C) 2013 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/bug.h>
-#include <linux/err.h>
-#include <linux/platform_device.h>
-#include <linux/kernel.h>
-#include <linux/clk.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-#include <linux/slab.h>
-#include <linux/regulator/driver.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-#include <mach/iomux.h>
-#include <linux/gpio.h>
-#include <mach/board.h>
-#include <plat/pwm.h>
-#include "ft_pwm.h"
-#if 0
-#define DBG(x...) printk(KERN_INFO x)
-#else
-#define DBG(x...)
-#endif
-
-#if defined(CONFIG_SOC_RK3168) || defined(CONFIG_SOC_RK3168M) || defined(CONFIG_ARCH_RK3188) || defined(CONFIG_ARCH_RK3026)
-const static int pwm_voltage_map[] = {
- 800000,825000,850000, 875000,900000, 925000 ,950000, 975000,1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000,1375000
-};
-#else
-const static int pwm_voltage_map[] = {
- 950000, 975000,1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000, 1375000, 1400000
-};
-#endif
-#if 0
-struct ft_pwm_data {
- int pwm_id;
- char* gpio_name;
- char* pwm_iomux_name;
- unsigned int pwm_gpio;
- unsigned int pwm_iomux_pwm;
- unsigned int pwm_iomux_gpio;
- int pwm_voltage;
- int suspend_voltage;
- int min_uV;
- int max_uV;
- int coefficient;
- const int *pwm_voltage_map;
-};
-#endif
-static struct ft_pwm_data ft_pwm[2] = {
- {
- .pwm_id = 0,
- .min_uV = 830000,
- .max_uV = 1380000,
- .coefficient = 550, //(550 * 10)uV every 1% duty cycle
- .pwm_voltage_map = pwm_voltage_map,
- }, {
- .pwm_id = 1,
- .min_uV = 830000,
- .max_uV = 1380000,
- .coefficient = 550, //(550 * 10)uV every 1% duty cycle
- .pwm_voltage_map = pwm_voltage_map,
- },
-};
-
-int ft_pwm_set_rate(struct ft_pwm_data* pwm, int nHz, u32 rate)
-{
- u32 lrc, hrc;
- unsigned long clkrate;
-
- clkrate = clk_get_rate(clk_get(NULL, "pwm01"));
-
- printk("%s: out_rate=%d, get clkrate=%lu\n", __func__, nHz, clkrate);
- gpio_request(pwm->pwm_gpio, "ft pwm gpio");
- if (rate == 0) {
- // iomux pwm to gpio
- rk30_mux_api_set(pwm->gpio_name, pwm->pwm_iomux_gpio);
- //disable pull up or down
- gpio_pull_updown(pwm->pwm_gpio, PullDisable);
- // set gpio to low level
- gpio_direction_output(pwm->pwm_gpio, GPIO_LOW);
-
- } else if (rate < 100) {
- // iomux pwm to gpio
- lrc = clkrate / nHz;
- lrc = lrc >> (1 + (PWM_DIV >> 9));
- lrc = lrc ? lrc : 1;
- hrc = lrc * rate / 100;
- hrc = hrc ? hrc : 1;
-
- // iomux pwm
- rk30_mux_api_set(pwm->pwm_iomux_name, pwm->pwm_iomux_pwm);
-
- printk("%s: lrc=%d, hrc=%d\n", __func__, lrc, hrc);
- rk_pwm_setup(pwm->pwm_id, PWM_DIV, hrc, lrc);
-
- } else if (rate == 100) {
- // iomux pwm to gpio
- rk30_mux_api_set(pwm->gpio_name, pwm->pwm_iomux_gpio);
- //disable pull up or down
- gpio_pull_updown(pwm->pwm_gpio, PullDisable);
- // set gpio to low level
- gpio_direction_output(pwm->pwm_gpio, GPIO_HIGH);
-
- } else {
- printk("%s:rate error\n",__func__);
- return -1;
- }
-
- usleep_range(10 * 1000, 10 * 1000);
-
- return (0);
-}
-
-int ft_pwm_regulator_get_voltage(char* name)
-{
- DBG("%s: get %s voltage\n", __func__, name);
-
- return 0;
-}
-
-int ft_pwm_set_voltage(char *name, int vol)
-{
- int ret = 0;
- // VDD12 = 1.40 - 0.455*D , 其中D为PWM占空比,
- int pwm_value, pwm_id = 0;
-
- if (strcmp(name, "arm") == 0) {
- pwm_id = 0;
-
- } else if (strcmp(name, "logic") == 0) {
- pwm_id = 1;
-
- } else {
- printk("unknown name");
- return -EINVAL;
- }
-
- printk("%s: name=%s, pwm_id=%d, vol=%d\n", __func__, name, pwm_id, vol);
- /* pwm_value %, coefficient * 1000 */
- pwm_value = (ft_pwm[pwm_id].max_uV - vol) / ft_pwm[pwm_id].coefficient / 10;
- printk("%s: name=%s, pwm_id=%d, duty=%d%%, [min,max]=[%d, %d], coefficient=%d\n",
- __func__, name, pwm_id, pwm_value,
- ft_pwm[pwm_id].min_uV,
- ft_pwm[pwm_id].max_uV,
- ft_pwm[pwm_id].coefficient);
- ret = ft_pwm_set_rate(&ft_pwm[pwm_id], 1000 * 1000, pwm_value);
-
- if (ret != 0) {
- printk("%s: fail to set pwm rate, pwm_value = %d\n", __func__, pwm_value);
- return -1;
- }
-
- return 0;
-
-
-}
-static int pwm_mode[] = {PWM0, PWM1, PWM2};
-void ft_pwm_init(void)
-{
- int i = 0;
- for (i = 0; i < ARRAY_SIZE(ft_pwm); i++) {
- ft_pwm[i].pwm_gpio = iomux_mode_to_gpio(pwm_mode[ft_pwm[i].pwm_id]);
- ft_pwm[i].pwm_iomux_pwm = pwm_mode[ft_pwm[i].pwm_id];
- ft_pwm[i].pwm_iomux_gpio = iomux_switch_gpio_mode(pwm_mode[ft_pwm[i].pwm_id]);
- }
-}
+++ /dev/null
-/*
- *
- * Copyright (C) 2013 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/bug.h>
-#include <linux/err.h>
-#include <linux/platform_device.h>
-#include <linux/kernel.h>
-#include <linux/clk.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-#include <linux/slab.h>
-#include <linux/regulator/driver.h>
-#include <linux/regulator/rk29-pwm-regulator.h>
-#include <mach/iomux.h>
-#include <linux/gpio.h>
-#include <mach/board.h>
-#include <plat/pwm.h>
-
-struct ft_pwm_data {
- int pwm_id;
- char* gpio_name;
- char* pwm_iomux_name;
- unsigned int pwm_gpio;
- unsigned int pwm_iomux_pwm;
- unsigned int pwm_iomux_gpio;
- int pwm_voltage;
- int suspend_voltage;
- int min_uV;
- int max_uV;
- int coefficient;
- const int *pwm_voltage_map;
-};
-
-int ft_pwm_set_rate(struct ft_pwm_data* pwm, int nHz, u32 rate);
-int ft_pwm_regulator_get_voltage(char* name);
-int ft_pwm_set_voltage(char *name, int vol);
-void ft_pwm_init(void);
-
+++ /dev/null
-/* arch/arm/mach-rk30/rk_pm_tests.c
- *
- * Copyright (C) 2010 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-
-/*************************************************************************/
-/* COPYRIGHT (C) ROCK-CHIPS FUZHOU . ALL RIGHTS RESERVED.*/
-/*************************************************************************
-FILE : rk_pm_tests.c
-DESC : Power management in dynning state
-AUTHOR : chenxing
-DATE : 2012-7-2
-NOTES :
-$LOG: GPIO.C,V $
-REVISION 0.01
-#include <linux/clk.h>
-#include <linux/kobject.h>
- ***************************************************************************/
-#include <linux/string.h>
-#include <linux/resume-trace.h>
-#include <linux/workqueue.h>
-#include <linux/mutex.h>
-#include <linux/module.h>
-#include <linux/syscalls.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/cpu.h>
-#include <linux/slab.h>
-#include <linux/freezer.h>
-
-#include <linux/dma-mapping.h>
-#include <linux/regulator/machine.h>
-#include <plat/dma-pl330.h>
-#include <linux/mfd/wm831x/core.h>
-#include <linux/sysfs.h>
-#include <linux/err.h>
-#include <linux/kthread.h>
-#include <linux/clk.h>
-#include <linux/suspend.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include "ft_pwm.h"
-
-
-#if 0
-#define ft_printk(fmt, arg...) \
- printk(KERN_EMERG fmt, ##arg)
- //KERN_DEBUG
-#define ft_printk_dbg(fmt, arg...) \
- printk(KERN_EMERG fmt, ##arg)
-
- //KERN_WARNING
-#define ft_printk_info(fmt, arg...) \
- printk(KERN_EMERG fmt, ##arg)
-#else
-
-#define ft_printk(fmt, arg...) \
- printk(KERN_EMERG fmt, ##arg)
- //KERN_DEBUG
-#define ft_printk_dbg(fmt, arg...) {while(0);}
-
- //KERN_WARNING
-#define ft_printk_info(fmt, arg...) {while(0);}
-#endif
-
-#define FT_PWM 0
-
-int pwm_volt[5] = {900000, 1250000, 1350000, 0, 0};
-
-#define MHZ (1000*1000)
-#define TST_SETUPS (4)
-#define FT_END_CNT (0x23)
-
-#define ENABLE_FT_TEST_GPIO // for ft seting 1.6G volt
-
-//#define ENABLE_FT_SUSPEND_TST // for ft seting 1.6G volt
-
-static struct semaphore sem_step0 = __SEMAPHORE_INITIALIZER(sem_step0, 0);
-static struct semaphore sem_step1 = __SEMAPHORE_INITIALIZER(sem_step1, 0);
-static struct semaphore sem_step2 = __SEMAPHORE_INITIALIZER(sem_step2, 0);
-static struct semaphore sem_step3 = __SEMAPHORE_INITIALIZER(sem_step3, 0);
-
-static struct semaphore *sem_steps[TST_SETUPS]={&sem_step0,&sem_step1,&sem_step2,&sem_step3};
-
-static int setups_flag[TST_SETUPS]={0,0,0,0};
-
-
-#if defined(CONFIG_ARCH_RK3188)
-
-#if 0 // Á½µµ²âÊÔ
-const static unsigned long arm_setups_rate[TST_SETUPS]={816*MHZ,1608*MHZ*1,0,0};
-const static unsigned long l1_tst_cnt[TST_SETUPS]={5*10*1,5*10*1,5*10*21,5*10*1};
-const static unsigned long l2_cpy_cnt[TST_SETUPS]={5*1+2,5*2+4,5*2+4,5*2+4};
-
-#else
-
-//const static unsigned long arm_setups_rate[TST_SETUPS]={312*MHZ,1656*MHZ*1,1608*MHZ*1,312*MHZ*1};
-const static unsigned long arm_setups_rate[TST_SETUPS]={816*MHZ,1656*MHZ*1,1608*MHZ*1,312*MHZ*1};
-//const static unsigned long arm_setups_rate[TST_SETUPS]={816*MHZ,1608*MHZ*1,816*MHZ*1,1608*MHZ*1};
-const static unsigned long l1_tst_cnt[TST_SETUPS]={5*10*2,5*10*2,5*10*2,5*10*2};
-const static unsigned long l2_cpy_cnt[TST_SETUPS]={5*1+2,5*2+4,5*2+4,5*2+4};
-
-#endif
-
-#define FT_CLIENT_READY_PIN RK30_PIN3_PB3
-#define FT_CLIENT_IDLE_PIN RK30_PIN0_PA3
-
-#elif defined(CONFIG_SOC_RK3168)
-
-const static unsigned long arm_setups_rate[4] = {552 * MHZ, 1200 * MHZ, 1608 * MHZ, 0};
-//const static unsigned long arm_setups_rate[4]={552*MHZ,0,0,0};
-
-const static unsigned long l1_tst_cnt[TST_SETUPS]={5*10,5*10,0,0};
-const static unsigned long l2_cpy_cnt[TST_SETUPS]={5*3,5*4,0,0};
-
-
-#define FT_CLIENT_READY_PIN RK30_PIN3_PB3
-#define FT_CLIENT_IDLE_PIN RK30_PIN0_PA3
-
-#elif defined(CONFIG_SOC_RK3028)
-
-const static unsigned long arm_setups_rate[4]={552*MHZ,1200*MHZ*1,0,0};
-
-const static unsigned long l1_tst_cnt[TST_SETUPS]={5*10,5*10,0,0};
-const static unsigned long l2_cpy_cnt[TST_SETUPS]={5*3,5*4,0,0};
-
-#define FT_CLIENT_READY_PIN RK30_PIN1_PA2
-#define FT_CLIENT_IDLE_PIN RK30_PIN3_PD4
-
-#elif defined(CONFIG_ARCH_RK3026)
-
-const static unsigned long arm_setups_rate[4] = {312 * MHZ, 816 * MHZ, 1008 * MHZ, 0};
-const static unsigned long l1_tst_cnt[TST_SETUPS]={5 * 10, 5 * 10, 0, 0};
-const static unsigned long l2_cpy_cnt[TST_SETUPS]={5 * 3, 5 * 4, 0, 0};
-
-#define FT_CLIENT_READY_PIN RK30_PIN2_PA7
-#define FT_CLIENT_IDLE_PIN RK30_PIN0_PA3
-
-#else
-
-const static unsigned long arm_setups_rate[4]={552*MHZ,0,0,0};
-
-const static unsigned long l1_tst_cnt[TST_SETUPS]={5*10,5*10,0,0};
-const static unsigned long l2_cpy_cnt[TST_SETUPS]={5*3,5*4,0,0};
-
-#define FT_CLIENT_READY_PIN RK30_PIN3_PB3
-#define FT_CLIENT_IDLE_PIN RK30_PIN0_PA3
-#endif
-
-
-//0-7 :test setup1
-#define CPU_TST_L1_STP0 (1<<0)
-#define CPU_TST_L2_STP0 (1<<1)
-#define CPU_TST_SETUP0_MSK (0xff)
-//7-15 :test setup2
-#define CPU_TST_L1_STP1 (1<<8)
-#define CPU_TST_L2_STP1 (1<<9)
-#define CPU_TST_SETUP1_MSK (0xff00)
-//16-23:test stetup3
-#define CPU_TST_L1_STP2 (1<<16)
-#define CPU_TST_L2_STP2 (1<<17)
-#define CPU_TST_SETUP2_MSK (0xff0000)
-
-//24-31:test stetup4
-#define CPU_TST_L1_STP3 (1<<24)
-#define CPU_TST_L2_STP3 (1<<25)
-#define CPU_TST_SETUP3_MSK (0xff000000)
-
-const static unsigned int setup_l1_bits[TST_SETUPS]={CPU_TST_L1_STP0,CPU_TST_L1_STP1,CPU_TST_L1_STP2,CPU_TST_L1_STP3};
-const static unsigned int setup_l2_bits[TST_SETUPS]={CPU_TST_L2_STP0,CPU_TST_L2_STP1,CPU_TST_L2_STP2,CPU_TST_L2_STP3};
-const static unsigned int setup_bits_msk[TST_SETUPS]={CPU_TST_SETUP0_MSK,CPU_TST_SETUP1_MSK,CPU_TST_SETUP2_MSK,CPU_TST_SETUP3_MSK};
-
-
-static DEFINE_PER_CPU(int, cpu_tst_flags)=(
- CPU_TST_L1_STP0|CPU_TST_L2_STP0
- |CPU_TST_L1_STP1|CPU_TST_L2_STP1
- |CPU_TST_L1_STP2|CPU_TST_L2_STP2
- |CPU_TST_L1_STP3|CPU_TST_L2_STP3
- );
-
-static struct clk *arm_clk;
-static DEFINE_PER_CPU(wait_queue_head_t [TST_SETUPS], wait_setups);
-
-unsigned long __init ft_test_init_arm_rate(void)
-{
- return arm_setups_rate[0];
-
-}
-
-/************************************l1 tst***************************************/
-void test_cpus_l1(u32 *data);
-void test_cpus_l0(u32 *data);
-
-void ft_cpu_l1_test(u32 cnt)
-{
- u32 cpu = smp_processor_id();
- int test_array[100];
- int i;
- for(i=0;i<cnt;i++)
- {
- test_cpus_l1(&test_array[0]);
- barrier();
-
- }
- if(cpu==0)
- ft_printk(".");
- for(i=0;i<cnt;i++)
- {
- test_cpus_l0(&test_array[0]);
- barrier();
-
- }
-
-}
-
-/************************************l2 tst***************************************/
-
-int test_cpus_l2(char *data_s,char *data_e,u32 data);
-
-int test_cpus_mem_set(char *data_s,char *data_e,u32 data);
-int test_cpus_mem_check(char *data_s,char *data_e,u32 data);
-#define l1_DCACHE_SIZE (32*1024)
-#define l1_DCACHE_SIZE_M (l1_DCACHE_SIZE*32)
-
-#define l2_DCACHE_SIZE (512*1024)
-#define BUF_SIZE (l2_DCACHE_SIZE*8)// tst buf size
-
-#define BUF_SIZE_M (BUF_SIZE)// tst buf size
-
-
-static char memtest_buf0[BUF_SIZE] __attribute__((aligned(4096)));
-#if (NR_CPUS>=2)
-static char memtest_buf1[BUF_SIZE] __attribute__((aligned(4096)));
-#if (NR_CPUS>=4)
-static char memtest_buf2[BUF_SIZE] __attribute__((aligned(4096)));
-static char memtest_buf3[BUF_SIZE] __attribute__((aligned(4096)));
-#if (NR_CPUS>=8)
-static char memtest_buf4[BUF_SIZE] __attribute__((aligned(4096)));
-static char memtest_buf5[BUF_SIZE] __attribute__((aligned(4096)));
-static char memtest_buf6[BUF_SIZE] __attribute__((aligned(4096)));
-static char memtest_buf7[BUF_SIZE] __attribute__((aligned(4096)));
-#endif
-#endif
-#endif
-
-static char *l2_test_buf[NR_CPUS]=
-{
- memtest_buf0,
-#if (NR_CPUS>=2)
- memtest_buf1,
-#if (NR_CPUS>=4)
- memtest_buf2,
- memtest_buf3,
-#if (NR_CPUS>=8)
- memtest_buf4,
- memtest_buf5,
- memtest_buf6,
- memtest_buf7,
-#endif
-#endif
-#endif
-
-};
-
-static char *l2_test_mbuf[NR_CPUS]=
-{
-NULL,
-};
-
-#if 0
-int ft_test_cpus_l2(char *data_s,u32 buf_size,u32 cnt)
-{
- int i,j;
- int ret=0;
- int test_size=l1_DCACHE_SIZE;
- for(j=0;j<cnt;j++)
- {
- for(i=0;i<buf_size;)
- {
-
- ret=test_cpus_l2(data_s+i,data_s+i+test_size,0xffffffff);
- if(ret)
- {
- return 0xff;
- }
- ret=test_cpus_l2(data_s+i,data_s+i+test_size,0);
- if(ret)
- {
- return 0x1;
- }
- ret=test_cpus_l2(data_s+i,data_s+i+test_size,0xaaaaaaaa);
- if(ret)
- {
- return 0xaa;
- }
-
- i+=test_size;
-
- if((i+test_size)>buf_size)
- break;
-
- }
- }
-
- return 0;
-}
-
-int test_cpus_l2_m(char *data_s,char *data_d,int size,char data)
-{
- char *start;
- char *data_end=data_s+size;
- for(start=data_s;start<data_end;start++)
- {
- *start=data;
- barrier();
- }
-
- memcpy(data_d,data_s,size);
-
- data_end=data_d+size;
- for(start=data_d;start<data_end;start++)
- {
- if(*start!=data)
- {
- barrier();
- return -1;
- }
- }
- return 0;
-}
-
-
-int ft_test_cpus_l2_m(char *data_s,char *data_d,u32 buf_size,u32 cnt)
-{
- int i,j;
- int ret=0;
- int test_size=l1_DCACHE_SIZE;
- for(j=0;j<cnt;j++)
- {
- for(i=0;i<buf_size;)
- {
-
- ret=test_cpus_l2_m(data_s+i,data_d+i,test_size,0xff);
-
- if(ret)
- {
- return 0xff;
- }
- ret=test_cpus_l2_m(data_s+i,data_d+i,test_size,0);
- if(ret)
- {
- return 0x1;
- }
- ret=test_cpus_l2_m(data_s+i,data_d+i,test_size,0xaa);
- if(ret)
- {
- return 0xaa;
- }
-
- i+=test_size;
-
- if((i+test_size)>buf_size)
- break;
-
- }
- }
-
- return 0;
-}
-#endif
-
-int ft_test_cpus_l2_memcpy(char *data_d,char *data_s,u32 buf_size,u32 cnt)
-{
-
- u32 cpu = smp_processor_id();
- int j;
- int ret=0;
- int test_size;
- char *mem_start;
- char *mem_end;
-
- char *cpy_start;
- char *cpy_end;
-
- test_size=(buf_size/(2*l2_DCACHE_SIZE))*(2*l2_DCACHE_SIZE);
-
- for(j=0;j<cnt;j++)
- {
- mem_start=data_s;
- mem_end=data_s+test_size;
-
- if(data_d)
- {
- cpy_start=data_d;
- cpy_end=data_d+test_size;
- }
- else
- cpy_start=NULL;
-
- for(;mem_start<=(mem_end-2*l2_DCACHE_SIZE);)
- {
-
-
- test_cpus_mem_set(mem_start,mem_start+l2_DCACHE_SIZE,0xaaaaaaaa);
- test_cpus_mem_set(mem_start+l2_DCACHE_SIZE,mem_start+l2_DCACHE_SIZE*2,0x55555555);
-
-
- //ret=test_cpus_mem_check(mem_start,mem_start+l2_DCACHE_SIZE,0xaaaaaaaa);
- //ft_printk("mem_start end=%x,%x\n",mem_start+l2_DCACHE_SIZE,ret);
-
-
- if(test_cpus_mem_check(mem_start,mem_start+l2_DCACHE_SIZE,0xaaaaaaaa))
- {
- ret=0xaa;
- return ret;
- }
-
- if(test_cpus_mem_check(mem_start+l2_DCACHE_SIZE,mem_start+l2_DCACHE_SIZE*2,0x55555555))
- {
- ret=0x55;
- return ret;
- }
-#if 1
- if(cpy_start)
- {
- memcpy(cpy_start,mem_start,l2_DCACHE_SIZE);
- memcpy(cpy_start+l2_DCACHE_SIZE,mem_start+l2_DCACHE_SIZE,l2_DCACHE_SIZE);
-
- if(test_cpus_mem_check(cpy_start,cpy_start+l2_DCACHE_SIZE,0xaaaaaaaa))
- {
- ret=0x1aa;
- return ret;
- }
-
- if(test_cpus_mem_check(cpy_start+l2_DCACHE_SIZE,cpy_start+l2_DCACHE_SIZE*2,0x55555555))
- {
- ret=0x155;
- return ret;
- }
- }
-
-
- test_cpus_mem_set(mem_start+l2_DCACHE_SIZE,mem_start+l2_DCACHE_SIZE*2,0xaaaaaaaa);
- test_cpus_mem_set(mem_start,mem_start+l2_DCACHE_SIZE,0x55555555);
-
-
- if(test_cpus_mem_check(mem_start+l2_DCACHE_SIZE,mem_start+l2_DCACHE_SIZE*2,0xaaaaaaaa))
- {
- ret=0x2aa;
- return ret;
- }
-
- if(test_cpus_mem_check(mem_start,mem_start+l2_DCACHE_SIZE,0x55555555))
- {
- ret=0x255;
- return ret;
- }
-
- //cpy_start is aa mem_start is 55
-
- if(cpy_start)
- {
- memcpy(cpy_start+l2_DCACHE_SIZE,mem_start+l2_DCACHE_SIZE,l2_DCACHE_SIZE);//aa
- memcpy(cpy_start,mem_start,l2_DCACHE_SIZE);//55
-
- if(test_cpus_mem_check(cpy_start+l2_DCACHE_SIZE,cpy_start+l2_DCACHE_SIZE*2,0xaaaaaaaa))
- {
- ret=0x3aa;
- return ret;
- }
-
- if(test_cpus_mem_check(cpy_start,cpy_start+l2_DCACHE_SIZE,0x55555555))
- {
- ret=0x355;
- return ret;
- }
- }
-#endif
- mem_start+=2*l2_DCACHE_SIZE;
- if(cpy_start)
- {
- cpy_start+=2*l2_DCACHE_SIZE;
- }
-
-
- }
- if((j%20==0)&&(cpu==0))
- ft_printk(".");
- }
-
- return 0;
-}
-
-/*************************************816 tst case**************************************/
-
-void ft_cpu_test_type0(int steps)
-{
- u32 temp=-1;
- u32 cpu = smp_processor_id();
-
- ft_printk_dbg("test typ0 step%d cpu=%d start\n",steps,cpu);
- //arm rate init
- ft_cpu_l1_test(l1_tst_cnt[steps]);
-#if FT_PWM
- ft_pwm_set_voltage("arm", pwm_volt[0]);
- mdelay(5);
-#endif
- per_cpu(cpu_tst_flags, cpu)&=~setup_l1_bits[steps];
-
- //temp=ft_test_cpus_l2(l2_test_buf[cpu],sizeof(char)*BUF_SIZE,20);
- temp=ft_test_cpus_l2_memcpy(NULL,l2_test_buf[cpu],sizeof(char)*BUF_SIZE,l2_cpy_cnt[steps]);
-
- if(!temp)
- per_cpu(cpu_tst_flags, cpu)&=~setup_l2_bits[steps];
-
- ft_printk_dbg("test typ0 step%d cpu=%d end\n",steps,cpu);
-
-}
-
-int ft_cpu_test_type0_check(int steps,const char *str)
-{
-
- int cpu, ret = 0;
-
- for (cpu = 0; cpu < NR_CPUS; cpu++)
- down(sem_steps[steps]);
-
-
- for (cpu = 0; cpu < NR_CPUS; cpu++)
- {
- ret|=per_cpu(cpu_tst_flags, cpu);
- ft_printk_dbg("setup%d,cpu%d flags=%x(%x)\n",
- steps, cpu, per_cpu(cpu_tst_flags, cpu) & setup_bits_msk[steps],
- per_cpu(cpu_tst_flags, cpu));
- }
-
- ret&=setup_bits_msk[steps];// test setup1
- ft_printk("setup%d end:ret=%x,arm=%lu,ddr=%lu\n",
- steps,ret,clk_get_rate(arm_clk)/MHZ,clk_get_rate(clk_get(NULL, "ddr"))/MHZ);
- if(ret)
- {
- ft_printk("#R01%s*\n",str);
- while(1);
- }
- else
- ft_printk("#R00%s*\n",str);
-
- return ret;
-}
-
-
-/*************************************type1 rate tst case**************************************/
-
-void ft_cpu_test_type1(int steps)
-{
- u32 temp=-1;
- u32 cpu = smp_processor_id();
- //int i;
-
- ft_printk_dbg("test typ1 step%d cpu=%d start\n",steps,cpu);
-
- //arm rate init
- ft_cpu_l1_test(l1_tst_cnt[steps]);
-
- per_cpu(cpu_tst_flags, cpu)&=~setup_l1_bits[steps];
-
- //ft_printk_dbg("ft test cpus l2 begin\n");
-
- temp=ft_test_cpus_l2_memcpy(l2_test_mbuf[cpu],l2_test_buf[cpu],sizeof(char)*BUF_SIZE_M,l2_cpy_cnt[steps]);
-
- if(!temp)
- per_cpu(cpu_tst_flags, cpu)&=~setup_l2_bits[steps];
-
- #if 0
- if(cpu==0)
- ft_printk(".");
- for(i=0;i<1200;i++)
- {
- usleep_range(200, 200);//200
- if(( i%700 == 0)&&cpu==0)
- ft_printk(".");
- }
- #endif
-
- ft_printk_dbg("test typ1 step%d cpu=%d end\n",steps,cpu);
-
-}
-
-int ft_cpu_test_type1_check(int steps,const char *str)
-{
- int cpu, ret = 0;
- int rate;
-
- if(arm_setups_rate[steps])
- {
- setups_flag[steps]=1;
-
- ft_printk("#S%s*\n",str);
-
-
- rate=clk_get_rate(arm_clk);
-
- if(arm_setups_rate[steps]<rate)
- clk_set_rate(arm_clk,arm_setups_rate[steps]);
-
-#if FT_PWM
- ft_pwm_set_voltage("arm", pwm_volt[steps]);
- mdelay(5);
-#else
-#ifdef ENABLE_FT_TEST_GPIO
- // send msg to ctr board to up the volt
- gpio_request(FT_CLIENT_READY_PIN, "client ready");
- gpio_request(FT_CLIENT_IDLE_PIN, "client idle");
-
- gpio_direction_output(FT_CLIENT_READY_PIN, GPIO_HIGH);
- gpio_direction_input(FT_CLIENT_IDLE_PIN);
-
- // waiting for volt upping ok
- if((steps%2))
- while( 0 == gpio_get_value(FT_CLIENT_IDLE_PIN));
- else
- while( 1 == gpio_get_value(FT_CLIENT_IDLE_PIN));
-
- gpio_set_value(FT_CLIENT_READY_PIN, GPIO_LOW);
-#endif
-#endif
-
- if(arm_setups_rate[steps]>=rate)
- clk_set_rate(arm_clk,arm_setups_rate[steps]);
-
- for (cpu = 0; cpu < NR_CPUS; cpu++)
- wake_up(&per_cpu(wait_setups, cpu)[steps]);
-
-
- for (cpu = 0; cpu < NR_CPUS; cpu++)
- down(sem_steps[steps]);
-
- ret=0;
- for (cpu = 0; cpu < NR_CPUS; cpu++)
- {
- ret|=per_cpu(cpu_tst_flags, cpu);
- ft_printk_dbg("setup%d,cpu%d flags=%x(%x)\n",
- steps, cpu, per_cpu(cpu_tst_flags, cpu) & setup_bits_msk[steps],
- per_cpu(cpu_tst_flags, cpu));
- }
-
- ret&=setup_bits_msk[steps];// test setup2
-
- ft_printk("setup%d end:ret=%x,arm=%lu,ddr=%lu\n",
- steps,ret,clk_get_rate(arm_clk)/MHZ,clk_get_rate(clk_get(NULL, "ddr"))/MHZ);
- if(ret)
- {
- ft_printk("#R01%s*\n",str);
- while(1);
- }
- else
- ft_printk("#R00%s*\n",str);
-
- }
- return ret;
-
-}
-
-// tst thread callback for per cpu
-static int ft_cpu_test(void *data)
-{
- u32 cpu = smp_processor_id();
-
- ft_cpu_test_type0(0);
- up(sem_steps[0]);
-
- wait_event_freezable(per_cpu(wait_setups, cpu)[1],(setups_flag[1]==1)||kthread_should_stop());
- ft_cpu_test_type1(1);
- up(sem_steps[1]);
-
- wait_event_freezable(per_cpu(wait_setups, cpu)[2],(setups_flag[2]==1)||kthread_should_stop());
- ft_cpu_test_type1(2);
- up(sem_steps[2]);
-
- wait_event_freezable(per_cpu(wait_setups, cpu)[3],(setups_flag[3]==1)||kthread_should_stop());
- ft_cpu_test_type1(3);
- up(sem_steps[3]);
-
- return 0;
-}
-
-
-static int __init rk_ft_tests_init(void)
-{
- int cpu, i,ret = 0;
- struct sched_param param = { .sched_priority = 0 };
- char *buf;
- arm_clk=clk_get(NULL, "cpu");
-
- ft_pwm_init();
- for (cpu = 0; cpu < NR_CPUS; cpu++) {
- l2_test_mbuf[cpu]=NULL;
- buf = kmalloc(BUF_SIZE_M, GFP_KERNEL);
-
- if (buf)
- {
- l2_test_mbuf[cpu]=buf;
- //printk("xdbg but=%x\n",(void*)buf);
- }
- }
-
- for (cpu = 0; cpu < NR_CPUS; cpu++) {
- for(i=0;i<TST_SETUPS;i++)
- {
- init_waitqueue_head(&per_cpu(wait_setups, cpu)[i]);
- }
-
- }
-
- for (cpu = 0; cpu < NR_CPUS; cpu++) {
- struct task_struct *task = kthread_create(ft_cpu_test, NULL, "ft_cpu_test%d", cpu);
- sched_setscheduler_nocheck(task, SCHED_RR, ¶m);
- get_task_struct(task);
- kthread_bind(task, cpu);
- wake_up_process(task);
- }
-
- return ret;
-}
-core_initcall(rk_ft_tests_init);
-
-void ft_test_flag_seting(void);
-
-static int rk_ft_tests_over(void)
-{
- int ret = 0;
-
- ft_cpu_test_type0_check(0,"KERNEL");
-
- ft_cpu_test_type1_check(1,"HSPEED");
-
- ft_cpu_test_type1_check(2,"HSPEED2");
-
- ft_cpu_test_type1_check(3,"KERNEL2");
-
- ft_printk("#END%x*\n",FT_END_CNT);
-
-
- #ifdef ENABLE_FT_SUSPEND_TST
- {
- ft_test_flag_seting();
- pm_suspend(PM_SUSPEND_MEM);
- }
- #endif
-
- while(1);
-
- return ret;
-}
-
-
-late_initcall_sync(rk_ft_tests_over);
-
-
-
-
+++ /dev/null
-#include <linux/clk.h>
-#include <linux/kobject.h>
-#include <linux/string.h>
-#include <linux/resume-trace.h>
-#include <linux/workqueue.h>
-#include <linux/mutex.h>
-#include <linux/module.h>
-#include <linux/syscalls.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/cpu.h>
-#include <linux/slab.h>
-#include <linux/dma-mapping.h>
-#include <linux/regulator/machine.h>
-#include <plat/dma-pl330.h>
-#include <linux/mfd/wm831x/core.h>
-#include <linux/sysfs.h>
-#include <linux/err.h>
-#include <linux/cpufreq.h>
-#include <mach/ddr.h>
-#include <mach/dvfs.h>
-
-#include <linux/fs.h>
-#include <asm/unistd.h>
-#include <asm/uaccess.h>
-#include "rk_pm_tests.h"
-#include "maxfreq.h"
-/*
- * Warning: Must set ddr_freq = 200M, gpu_freq = 200M; to make sure ddr
- * and gpu can run under log = 1V.
- * Remember to close cpufreq's max freq limit
- *
- * */
-static struct cpufreq_frequency_table *dvfs_arm_table_save;
-static struct cpufreq_frequency_table dvfs_arm_table_maxfreq[] = {
- {.frequency = 252 * 1000, .index = 1000 * 1000},
- {.frequency = 312 * 1000, .index = 1000 * 1000},
- {.frequency = 504 * 1000, .index = 1000 * 1000},
- {.frequency = 816 * 1000, .index = 1000 * 1000},
- {.frequency = 912 * 1000, .index = 1000 * 1000},
- {.frequency = 936 * 1000, .index = 1000 * 1000},
- {.frequency = 960 * 1000, .index = 1000 * 1000},
- {.frequency = 984 * 1000, .index = 1000 * 1000},
- {.frequency = 1008 * 1000, .index = 1000 * 1000},
- {.frequency = 1032 * 1000, .index = 1000 * 1000},
- {.frequency = 1056 * 1000, .index = 1000 * 1000},
- {.frequency = 1080 * 1000, .index = 1000 * 1000},
- {.frequency = 1104 * 1000, .index = 1000 * 1000},
- {.frequency = 1128 * 1000, .index = 1000 * 1000},
- {.frequency = 1152 * 1000, .index = 1000 * 1000},
- {.frequency = 1176 * 1000, .index = 1000 * 1000},
- {.frequency = 1200 * 1000, .index = 1000 * 1000},
- {.frequency = 1224 * 1000, .index = 1000 * 1000},
- {.frequency = 1248 * 1000, .index = 1000 * 1000},
- {.frequency = 1272 * 1000, .index = 1000 * 1000},
- {.frequency = 1296 * 1000, .index = 1000 * 1000},
- {.frequency = 1320 * 1000, .index = 1000 * 1000},
- {.frequency = 1344 * 1000, .index = 1000 * 1000},
- {.frequency = 1368 * 1000, .index = 1000 * 1000},
- {.frequency = 1392 * 1000, .index = 1000 * 1000},
- {.frequency = 1416 * 1000, .index = 1000 * 1000},
- {.frequency = 1440 * 1000, .index = 1000 * 1000},
- {.frequency = 1464 * 1000, .index = 1000 * 1000},
- {.frequency = 1488 * 1000, .index = 1000 * 1000},
- {.frequency = 1512 * 1000, .index = 1000 * 1000},
- {.frequency = 1536 * 1000, .index = 1000 * 1000},
- {.frequency = 1560 * 1000, .index = 1000 * 1000},
- {.frequency = 1584 * 1000, .index = 1000 * 1000},
- {.frequency = 1608 * 1000, .index = 1000 * 1000},
- {.frequency = 1632 * 1000, .index = 1000 * 1000},
- {.frequency = 1656 * 1000, .index = 1000 * 1000},
- {.frequency = 1680 * 1000, .index = 1000 * 1000},
- {.frequency = 1704 * 1000, .index = 1000 * 1000},
- {.frequency = 1728 * 1000, .index = 1000 * 1000},
- {.frequency = 1752 * 1000, .index = 1000 * 1000},
- {.frequency = 1776 * 1000, .index = 1000 * 1000},
- {.frequency = 1800 * 1000, .index = 1000 * 1000},
- {.frequency = 1824 * 1000, .index = 1000 * 1000},
- {.frequency = 1848 * 1000, .index = 1000 * 1000},
- {.frequency = 1872 * 1000, .index = 1000 * 1000},
- {.frequency = 1896 * 1000, .index = 1000 * 1000},
- {.frequency = 1920 * 1000, .index = 1000 * 1000},
- {.frequency = 1944 * 1000, .index = 1000 * 1000},
- {.frequency = 1968 * 1000, .index = 1000 * 1000},
- {.frequency = 1992 * 1000, .index = 1000 * 1000},
- {.frequency = 2016 * 1000, .index = 1000 * 1000},
- {.frequency = 2040 * 1000, .index = 1000 * 1000},
- {.frequency = 2064 * 1000, .index = 1000 * 1000},
- {.frequency = 2088 * 1000, .index = 1000 * 1000},
- {.frequency = 2112 * 1000, .index = 1000 * 1000},
- {.frequency = 2136 * 1000, .index = 1000 * 1000},
- {.frequency = 2160 * 1000, .index = 1000 * 1000},
- {.frequency = 2184 * 1000, .index = 1000 * 1000},
- {.frequency = 2208 * 1000, .index = 1000 * 1000},
- {.frequency = CPUFREQ_TABLE_END},
-};
-static int curr_mode = 0;
-/***************************************************************************/
-#define FILE_GOV_MODE "/sys/devices/system/cpu/cpu0/cpufreq/scaling_governor"
-#define FILE_SETSPEED "/sys/devices/system/cpu/cpu0/cpufreq/scaling_setspeed"
-#define FILE_CUR_FREQ "/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq"
-
-static int file_read(char *file_path, char *buf)
-{
- struct file *file = NULL;
- mm_segment_t old_fs;
- loff_t offset = 0;
-
- PM_DBG("read %s\n", file_path);
- file = filp_open(file_path, O_RDONLY, 0);
-
- if (IS_ERR(file)) {
- PM_ERR("%s error open file %s\n", __func__, file_path);
- return -1;
- }
-
- old_fs = get_fs();
- set_fs(KERNEL_DS);
-
- file->f_op->read(file, (char *)buf, 32, &offset);
- sscanf(buf, "%s", buf);
-
- set_fs(old_fs);
- filp_close(file, NULL);
-
- file = NULL;
-
- return 0;
-
-}
-
-static int file_write(char *file_path, char *buf)
-{
- struct file *file = NULL;
- mm_segment_t old_fs;
- loff_t offset = 0;
-
- PM_DBG("write %s %s size = %d\n", file_path, buf, strlen(buf));
- file = filp_open(file_path, O_RDWR, 0);
-
- if (IS_ERR(file)) {
- PM_ERR("%s error open file %s\n", __func__, file_path);
- return -1;
- }
-
- old_fs = get_fs();
- set_fs(KERNEL_DS);
-
- file->f_op->write(file, (char *)buf, strlen(buf), &offset);
-
- set_fs(old_fs);
- filp_close(file, NULL);
-
- file = NULL;
-
- return 0;
-
-}
-
-ssize_t maxfreq_show(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf)
-{
- char *str = buf;
- str += sprintf(str, "setarmvolt [ArmVoltage(mV)]\n"
- "reset\n");
- if (str != buf)
- *(str - 1) = '\n';
- return (str - buf);
-
-}
-
-ssize_t maxfreq_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n)
-{
- char cmd[20], gov_mode[50];
- int armVolt, i = 0;
- struct clk *clk;
- sscanf(buf, "%s %d", cmd, &armVolt);
-
-
- clk = clk_get(NULL, "cpu");
- if (IS_ERR(clk)) {
- PM_ERR("%s get arm clk error\n", __func__);
- return n;
- }
-
- if (0 == strncmp(cmd, "setarmvolt", strlen("setarmvolt"))) {
- if (armVolt < 500000 || armVolt > 1500000) {
- PM_ERR("Arm Volt = %d, out of bound\n", armVolt);
- return n;
- }
-
- PM_DBG("Get command Set Arm Volt = %d mV\n", armVolt);
- if (file_read(FILE_GOV_MODE, gov_mode) != 0) {
- PM_ERR("read current governor error\n");
- return n;
- } else {
- PM_DBG("current governor = %s\n", gov_mode);
- }
-
- strcpy(gov_mode, "userspace");
- if (file_write(FILE_GOV_MODE, gov_mode) != 0) {
- PM_ERR("set current governor error\n");
- return n;
- }
-
- if (curr_mode == 0) {
- // save normal table
- PM_DBG("save dvfs normal table\n");
- dvfs_arm_table_save = dvfs_get_freq_volt_table(clk);
- curr_mode = 1;
- }
- for (i = 0; dvfs_arm_table_maxfreq[i].frequency != CPUFREQ_TABLE_END; i++) {
- dvfs_arm_table_maxfreq[i].index = armVolt;
- }
-
- dvfs_set_freq_volt_table(clk, dvfs_arm_table_maxfreq);
- clk_set_rate(clk, dvfs_arm_table_maxfreq[0].frequency * 1000);
-
- } else if (0 == strncmp(cmd, "reset", strlen("reset"))) {
- PM_DBG("Get command reset\n");
- if (file_read(FILE_GOV_MODE, gov_mode) != 0) {
- PM_ERR("read current governor error\n");
- return n;
- } else {
- PM_DBG("current governor = %s\n", gov_mode);
- }
-
- dvfs_set_freq_volt_table(clk, dvfs_arm_table_save);
- strcpy(gov_mode, "interactive");
- if (file_write(FILE_GOV_MODE, gov_mode) != 0) {
- PM_ERR("set current governor error\n");
- return n;
- }
- curr_mode = 0;
- }
-
- return n;
-}
-
+++ /dev/null
-#ifndef _MAXFREQ_H_
-#define _MAXFREQ_H_
-ssize_t maxfreq_show(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf);
-ssize_t maxfreq_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n);
-
-#endif
+++ /dev/null
-/* arch/arm/mach-rk30/rk_pm_tests.c
- *
- * Copyright (C) 2010 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-
-/*************************************************************************/
-/* COPYRIGHT (C) ROCK-CHIPS FUZHOU . ALL RIGHTS RESERVED.*/
-/*************************************************************************
-FILE : rk_pm_tests.c
-DESC : Power management in dynning state
-AUTHOR : chenxing
-DATE : 2012-7-2
-NOTES :
-$LOG: GPIO.C,V $
-REVISION 0.01
-#include <linux/clk.h>
-#include <linux/kobject.h>
- ***************************************************************************/
-#include <linux/string.h>
-#include <linux/resume-trace.h>
-#include <linux/workqueue.h>
-#include <linux/mutex.h>
-#include <linux/module.h>
-#include <linux/syscalls.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/cpu.h>
-#include <linux/slab.h>
-#include <linux/dma-mapping.h>
-#include <linux/regulator/machine.h>
-#include <plat/dma-pl330.h>
-#include <linux/mfd/wm831x/core.h>
-#include <linux/sysfs.h>
-#include <linux/err.h>
-//#include <mach/ddr.h>
-
-#include "rk_pm_tests.h"
-
-#include "clk_rate.h"
-#include "clk_volt.h"
-#include "maxfreq.h"
-#include "freq_limit.h"
-#include "cpu_usage.h"
-#include "rk_suspend_test.h"
-#include "clk_auto_volt.h"
-#include "dvfs_table_scan.h"
-#include "delayline.h"
-//#include "rk2928_freq.h"
-//#include "rk2928_max_freq.h"
-//#include "cpu_calc.h"
-//#include "ddr_scale_freq.h"
-//#include "pmic_delay.h"
-//#include "rk30_volt_diff.h"
-
-static struct kobject *pm_tests_kobj;
-struct pm_attribute {
- struct attribute attr;
- ssize_t (*show)(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf);
- ssize_t (*store)(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n);
-};
-
-static struct pm_attribute pm_attrs[] = {
- /* node_name permision show_func store_func*/
-#ifdef CONFIG_PM_TEST_CLK_RATE
- __ATTR(clk_rate, S_IRUGO | S_IWUSR, clk_rate_show, clk_rate_store),
-#endif
-#ifdef CONFIG_PM_TEST_CLK_VOLT
- __ATTR(clk_volt, S_IRUGO | S_IWUSR | S_IWUGO, clk_volt_show, clk_volt_store),
-#endif
-#ifdef CONFIG_PM_TEST_MAXFREQ
- __ATTR(maxfreq_volt, S_IRUGO | S_IWUSR, maxfreq_show, maxfreq_store),
-#endif
-#ifdef CONFIG_PM_TEST_FREQ_LIMIT
- __ATTR(freq_limit, S_IRUGO | S_IWUSR, freq_limit_show, freq_limit_store),
-#endif
-#ifdef CONFIG_PM_TEST_CPU_USAGE
- __ATTR(cpu_usage, S_IRUGO | S_IWUSR, cpu_usage_show, cpu_usage_store),
-#endif
-#ifdef CONFIG_PM_TEST_SUSPEND_DBG
- __ATTR(auto_wakeup, S_IRUGO | S_IWUSR, auto_wakeup_show, auto_wakeup_store),
- __ATTR(suspend_test, S_IRUGO | S_IWUSR, suspend_test_show, suspend_test_store),
-#endif
-#ifdef CONFIG_PM_TEST_CLK_AUTO_VOLT
- __ATTR(clk_auto_volt, S_IRUGO | S_IWUSR, clk_auto_volt_show, clk_auto_volt_store),
-#endif
-#ifdef CONFIG_PM_TEST_DVFS_TABLE_SCAN
- __ATTR(dvfs_table_scan, S_IRUGO | S_IWUSR | S_IWUGO, dvfs_table_scan_show, dvfs_table_scan_store),
-#endif
-#ifdef CONFIG_PM_TEST_DELAYLINE
- __ATTR(delayline, S_IRUGO | S_IWUSR, delayline_show, delayline_store),
-#endif
-#if 0
- __ATTR(ddr_scale_freq, S_IRUGO | S_IWUSR, ddr_scale_freq_show, ddr_scale_freq_store),
- __ATTR(pmic_delay, S_IRUGO | S_IWUSR, pmic_delay_show, pmic_delay_store),
-#endif
-// __ATTR(rk2928_freq, S_IRUGO | S_IWUSR, rk2928_freq_show, rk2928_freq_store),
-// __ATTR(rk2928_max_freq, S_IRUGO | S_IWUSR, rk2928_max_freq_show, rk2928_max_freq_store),
-// __ATTR(cpu_calc, S_IRUGO | S_IWUSR, cpu_calc_show, cpu_calc_store),
-// __ATTR(rk30_volt_diff, S_IRUGO | S_IWUSR, rk30_volt_diff_show, rk30_volt_diff_store),
-};
-
-static void __exit rk_pm_tests_exit(void)
-{
- kobject_put(pm_tests_kobj);
-}
-
-static int __init rk_pm_tests_init(void)
-{
- int i, ret = 0;
- pm_tests_kobj = kobject_create_and_add("pm_tests", NULL);
-
- if (!pm_tests_kobj)
- return -ENOMEM;
-
- for (i = 0; i < ARRAY_SIZE(pm_attrs); i++) {
- ret = sysfs_create_file(pm_tests_kobj, &pm_attrs[i].attr);
- if (ret != 0) {
- PM_ERR("create index %d error\n", i);
- return ret;
- }
- }
-
- return ret;
-}
-
-late_initcall(rk_pm_tests_init);
-module_exit(rk_pm_tests_exit);
+++ /dev/null
-#ifndef _RK_PM_TESTS_H_
-#define _RK_PM_TESTS_H_
-#define PM_DBG(fmt, args...) printk(KERN_DEBUG "PM_TESTS_DBG:\t"fmt, ##args)
-#define PM_ERR(fmt, args...) printk(KERN_ERR "PM_TESTS_ERR:\t"fmt, ##args)
-#endif
+++ /dev/null
-#include <linux/android_alarm.h>\r
-#include <linux/mutex.h>\r
-#include <linux/kobject.h>\r
-#include <linux/string.h>\r
-\r
-#include "rk_pm_tests.h"\r
-#include "rk_suspend_test.h"\r
-static struct alarm alarm;\r
-static struct timespec period;\r
-static int alarm_status = 0;\r
-static DEFINE_MUTEX(mutex);\r
-\r
-static int get_alarm_status(void)\r
-{\r
- return alarm_status;\r
-}\r
-\r
-static void alarm_update(struct alarm *alarm)\r
-{\r
- struct timespec now_time;\r
- struct timespec new_time;\r
-\r
- now_time = ktime_to_timespec(alarm_get_elapsed_realtime());\r
-\r
- PM_DBG("now_time %ld\n",now_time.tv_sec);\r
-\r
- new_time.tv_sec = now_time.tv_sec + period.tv_sec;\r
- new_time.tv_nsec = now_time.tv_nsec + period.tv_nsec;\r
-\r
- alarm_start_range(alarm, timespec_to_ktime(new_time), timespec_to_ktime(new_time));\r
-}\r
-\r
-static void stop_auto_wakeup(void)\r
-{\r
- mutex_lock(&mutex);\r
-\r
- if(alarm_status) {\r
- alarm_cancel(&alarm);\r
- alarm_status = 0;\r
- }\r
-\r
- mutex_unlock(&mutex);\r
-}\r
-\r
-static void start_auto_wakeup(long second)\r
-{\r
- stop_auto_wakeup();\r
-\r
- mutex_lock(&mutex);\r
-\r
- period.tv_sec = second;\r
- period.tv_nsec = 0;\r
-\r
- alarm_init(&alarm, ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP, alarm_update); \r
- alarm_update(&alarm);\r
- alarm_status = 1;\r
-\r
- mutex_unlock(&mutex);\r
-}\r
-\r
-ssize_t auto_wakeup_show(struct kobject *kobj, struct kobj_attribute *attr,\r
- char *buf)\r
-{\r
- char *s = buf;\r
-\r
- if(get_alarm_status())\r
- s += sprintf(s, "%s\n", "on");\r
- else\r
- s += sprintf(s, "%s\n", "off");\r
-\r
- return (s - buf);\r
-}\r
-\r
-ssize_t auto_wakeup_store(struct kobject *kobj, struct kobj_attribute *attr,\r
- const char *buf, size_t n)\r
-{\r
- char cmd[10];\r
- long val;\r
- int len;\r
- int error = -EINVAL;\r
-\r
- sscanf(buf, "%s %ld", cmd, &val);\r
- len = strlen(cmd);\r
-\r
- if (len == strlen("on") && !strncmp(cmd,"on",len)) {\r
- start_auto_wakeup(val);\r
- error = 0;\r
- }\r
- else if(len == strlen("off") && !strncmp(cmd,"off",len)) {\r
- stop_auto_wakeup();\r
- error = 0;\r
- }\r
-\r
- return error ? error : n;\r
-}\r
-\r
-void rk_soc_pm_ctr_bits_set(u32 flags);\r
-u32 rk_soc_pm_ctr_bits_get(void);\r
-ssize_t rk_soc_pm_helps_sprintf(char *buf);\r
-ssize_t suspend_test_show(struct kobject *kobj, struct kobj_attribute *attr,\r
- char *buf)\r
-{\r
- char *s = buf;\r
-\r
- s += sprintf(s, "control bits is 0X%x,if bit is 1,information is following\n", rk_soc_pm_ctr_bits_get());\r
- s += rk_soc_pm_helps_sprintf(s);\r
-\r
- return (s - buf);\r
-\r
-}\r
-ssize_t suspend_test_store(struct kobject *kobj, struct kobj_attribute *attr,\r
- const char *buf, size_t n)\r
-{\r
- long val;\r
- int len;\r
- char cmd0[20];\r
- int bits;\r
- sscanf(buf,"%s %x", cmd0, &bits);\r
- \r
- //printk("auto_wakeup_store %x\n",bits);\r
- if (0 == strncmp(cmd0, "bits", strlen("bits"))) {\r
- //printk("auto_wakeup_store %x\n",bits);\r
- rk_soc_pm_ctr_bits_set(bits);\r
- } \r
- return n;\r
-}\r
-\r
-\r
+++ /dev/null
-#ifndef __AUTO_WAKEUP_H \r
-#define __AUTO_WAKEUP_H \r
-\r
-ssize_t auto_wakeup_show(struct kobject *kobj, struct kobj_attribute *attr,\r
- char *buf);\r
-ssize_t auto_wakeup_store(struct kobject *kobj, struct kobj_attribute *attr,\r
- const char *buf, size_t n);\r
-ssize_t suspend_test_store(struct kobject *kobj, struct kobj_attribute *attr,\r
- const char *buf, size_t n);\r
-ssize_t suspend_test_show(struct kobject *kobj, struct kobj_attribute *attr,\r
- char *buf);\r
-\r
-\r
-#endif\r
-\r
+++ /dev/null
-/*
- *
- * Copyright (C) 2013 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/init.h>
-#include <linux/time.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/clk.h>
-#include <linux/clockchips.h>
-#include <linux/platform_device.h>
-
-#include <asm/localtimer.h>
-#include <asm/sched_clock.h>
-
-#define TIMER_NAME "rk_timer"
-
-#define TIMER_LOAD_COUNT0 0x00
-#define TIMER_LOAD_COUNT1 0x04
-#define TIMER_CURRENT_VALUE0 0x08
-#define TIMER_CURRENT_VALUE1 0x0c
-#define TIMER_CONTROL_REG 0x10
-#define TIMER_INT_STATUS 0x18
-
-#define TIMER_DISABLE (0 << 0)
-#define TIMER_ENABLE (1 << 0)
-#define TIMER_MODE_FREE_RUNNING (0 << 1)
-#define TIMER_MODE_USER_DEFINED_COUNT (1 << 1)
-#define TIMER_INT_MASK (0 << 2)
-#define TIMER_INT_UNMASK (1 << 2)
-
-static inline void rk_timer_disable(void __iomem *base)
-{
- writel_relaxed(TIMER_DISABLE, base + TIMER_CONTROL_REG);
- dsb();
-}
-
-static inline void rk_timer_enable(void __iomem *base, u32 flags)
-{
- writel_relaxed(TIMER_ENABLE | flags, base + TIMER_CONTROL_REG);
- dsb();
-}
-
-static inline u32 rk_timer_read_current_value(void __iomem *base)
-{
- return readl_relaxed(base + TIMER_CURRENT_VALUE0);
-}
-
-struct rk_timer {
- void __iomem *cs_base;
- struct clk *cs_clk;
- struct clk *cs_pclk;
-
- void __iomem *ce_base[NR_CPUS];
- struct irqaction ce_irq[NR_CPUS];
- bool ce_irq_disabled[NR_CPUS];
- struct clk *ce_clk[NR_CPUS];
- struct clk *ce_pclk[NR_CPUS];
- char ce_name[NR_CPUS][16];
-};
-static struct rk_timer timer;
-
-static const char *platform_get_string_byname(struct platform_device *dev, const char *name)
-{
- struct resource *r = platform_get_resource_byname(dev, 0, name);
-
- return r ? (const char *)r->start : NULL;
-}
-
-static int rk_timer_set_next_event(unsigned long cycles, struct clock_event_device *evt)
-{
- unsigned int cpu = smp_processor_id();
- void __iomem *base = timer.ce_base[cpu];
-
- rk_timer_disable(base);
- writel_relaxed(cycles, base + TIMER_LOAD_COUNT0);
- writel_relaxed(0, base + TIMER_LOAD_COUNT1);
- dsb();
- rk_timer_enable(base, TIMER_MODE_USER_DEFINED_COUNT | TIMER_INT_UNMASK);
- return 0;
-}
-
-static void rk_timer_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
-{
- unsigned int cpu = smp_processor_id();
- void __iomem *base = timer.ce_base[cpu];
- int irq = timer.ce_irq[cpu].irq;
-
- switch (mode) {
- case CLOCK_EVT_MODE_PERIODIC:
- rk_timer_disable(base);
- writel_relaxed(24000000 / HZ - 1, base + TIMER_LOAD_COUNT0);
- dsb();
- rk_timer_enable(base, TIMER_MODE_FREE_RUNNING | TIMER_INT_UNMASK);
- case CLOCK_EVT_MODE_RESUME:
- case CLOCK_EVT_MODE_ONESHOT:
- if (timer.ce_irq_disabled[cpu]) {
- enable_irq(irq);
- timer.ce_irq_disabled[cpu] = false;
- }
- break;
- case CLOCK_EVT_MODE_UNUSED:
- case CLOCK_EVT_MODE_SHUTDOWN:
- rk_timer_disable(base);
- if (!timer.ce_irq_disabled[cpu]) {
- disable_irq(irq);
- timer.ce_irq_disabled[cpu] = true;
- }
- break;
- }
-}
-
-static irqreturn_t rk_timer_clockevent_interrupt(int irq, void *dev_id)
-{
- unsigned int cpu = smp_processor_id();
- struct clock_event_device *evt = dev_id;
- void __iomem *base = timer.ce_base[cpu];
-
- /* clear interrupt */
- writel_relaxed(1, base + TIMER_INT_STATUS);
- if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
- writel_relaxed(TIMER_DISABLE, base + TIMER_CONTROL_REG);
- }
- dsb();
-
- evt->event_handler(evt);
-
- return IRQ_HANDLED;
-}
-
-static __cpuinit int rk_timer_init_clockevent(struct clock_event_device *ce, unsigned int cpu)
-{
- struct irqaction *irq = &timer.ce_irq[cpu];
- void __iomem *base = timer.ce_base[cpu];
-
- if (!base)
- return 0;
-
- ce->name = timer.ce_name[cpu];
- ce->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
- ce->set_next_event = rk_timer_set_next_event;
- ce->set_mode = rk_timer_set_mode;
- ce->irq = irq->irq;
- ce->cpumask = cpumask_of(cpu);
-
- writel_relaxed(1, base + TIMER_INT_STATUS);
- rk_timer_disable(base);
-
- irq->dev_id = ce;
- irq_set_affinity(irq->irq, cpumask_of(cpu));
- setup_irq(irq->irq, irq);
-
- clockevents_config_and_register(ce, 24000000, 0xF, 0xFFFFFFFF);
-
- return 0;
-}
-
-static cycle_t rk_timer_read(struct clocksource *cs)
-{
- return ~rk_timer_read_current_value(timer.cs_base);
-}
-
-/*
- * Constants generated by clocksource_hz2mult(24000000, 26).
- * This gives a resolution of about 41ns and a wrap period of about 178s.
- */
-#define MULT 2796202667u
-#define SHIFT 26
-#define MASK (u32)~0
-
-static struct clocksource rk_timer_clocksource = {
- .name = TIMER_NAME,
- .rating = 200,
- .read = rk_timer_read,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-static void __init rk_timer_init_clocksource(void)
-{
- static char err[] __initdata = KERN_ERR "%s: can't register clocksource!\n";
- struct clocksource *cs = &rk_timer_clocksource;
- void __iomem *base = timer.cs_base;
-
- clk_enable(timer.cs_pclk);
- clk_enable(timer.cs_clk);
-
- rk_timer_disable(base);
- writel_relaxed(0xFFFFFFFF, base + TIMER_LOAD_COUNT0);
- writel_relaxed(0xFFFFFFFF, base + TIMER_LOAD_COUNT1);
- dsb();
- rk_timer_enable(base, TIMER_MODE_FREE_RUNNING | TIMER_INT_MASK);
-
- if (clocksource_register_hz(cs, 24000000))
- printk(err, cs->name);
-}
-
-static DEFINE_CLOCK_DATA(cd);
-
-unsigned long long notrace sched_clock(void)
-{
- cycle_t cyc;
-
- if (!timer.cs_base)
- return 0;
-
- cyc = ~rk_timer_read_current_value(timer.cs_base);
- return cyc_to_fixed_sched_clock(&cd, cyc, MASK, MULT, SHIFT);
-}
-
-static void notrace rk_timer_update_sched_clock(void)
-{
- u32 cyc = ~rk_timer_read_current_value(timer.cs_base);
- update_sched_clock(&cd, cyc, MASK);
-}
-
-static void __init rk_timer_init_sched_clock(void)
-{
- init_fixed_sched_clock(&cd, rk_timer_update_sched_clock, 32, 24000000, MULT, SHIFT);
-}
-
-#if !defined(CONFIG_LOCAL_TIMERS) || defined(CONFIG_HAVE_ARM_TWD)
-static struct clock_event_device rk_timer_clockevent;
-#endif
-
-static int __init rk_timer_probe(struct platform_device *pdev)
-{
- struct resource *res;
- int cpu;
-
- timer.cs_clk = clk_get(NULL, platform_get_string_byname(pdev, "cs_clk"));
- timer.cs_pclk = clk_get(NULL, platform_get_string_byname(pdev, "cs_pclk"));
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cs_base");
- timer.cs_base = (void *)res->start;
-
- for (cpu = 0; cpu < NR_CPUS; cpu++) {
- char name[16];
- struct irqaction *irq = &timer.ce_irq[cpu];
-
- snprintf(timer.ce_name[cpu], sizeof(timer.ce_name[cpu]), TIMER_NAME "%d", cpu);
-
- snprintf(name, sizeof(name), "ce_base%d", cpu);
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
- if (!res)
- continue;
- timer.ce_base[cpu] = (void *)res->start;
-
- snprintf(name, sizeof(name), "ce_clk%d", cpu);
- timer.ce_clk[cpu] = clk_get(NULL, platform_get_string_byname(pdev, name));
-
- snprintf(name, sizeof(name), "ce_pclk%d", cpu);
- timer.ce_pclk[cpu] = clk_get(NULL, platform_get_string_byname(pdev, name));
-
- snprintf(name, sizeof(name), "ce_irq%d", cpu);
- irq->irq = platform_get_irq_byname(pdev, name);
- irq->name = timer.ce_name[cpu];
- irq->flags = IRQF_DISABLED | IRQF_TIMER | IRQF_NOBALANCING | IRQF_PERCPU;
- irq->handler = rk_timer_clockevent_interrupt;
-
- clk_enable(timer.ce_pclk[cpu]);
- clk_enable(timer.ce_clk[cpu]);
- }
-
- rk_timer_init_clocksource();
-#if !defined(CONFIG_LOCAL_TIMERS) || defined(CONFIG_HAVE_ARM_TWD)
- rk_timer_clockevent.rating = 400;
- rk_timer_init_clockevent(&rk_timer_clockevent, 0);
-#endif
- rk_timer_init_sched_clock();
-
- printk("rk_timer: version 1.3\n");
- return 0;
-}
-
-static struct platform_driver rk_timer_driver __initdata = {
- .probe = rk_timer_probe,
- .driver = {
- .name = TIMER_NAME,
- }
-};
-
-early_platform_init(TIMER_NAME, &rk_timer_driver);
-
-#if defined(CONFIG_LOCAL_TIMERS) && !defined(CONFIG_HAVE_ARM_TWD)
-/*
- * Setup the local clock events for a CPU.
- */
-static int __cpuinit rk_local_timer_setup(struct clock_event_device *clk)
-{
- clk->rating = 450;
- return rk_timer_init_clockevent(clk, smp_processor_id());
-}
-
-/*
- * Setup the local clock events for a CPU.
- */
-int __cpuinit local_timer_setup(struct clock_event_device *evt)
-{
- return rk_local_timer_setup(evt);
-}
-
-/*
- * local_timer_ack: checks for a local timer interrupt.
- *
- * If a local timer interrupt has occurred, acknowledge and return 1.
- * Otherwise, return 0.
- */
-int local_timer_ack(void)
-{
- return 0;
-}
-#endif
+++ /dev/null
-/*
- * License terms: GNU General Public License (GPL) version 2
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/stddef.h>
-#include <linux/ioport.h>
-#include <linux/genalloc.h>
-#include <linux/string.h> /* memcpy */
-#include <asm/page.h> /* PAGE_SHIFT */
-#include <asm/cputype.h>
-#include <asm/mach/map.h>
-#include <asm/tlbflush.h>
-#include <asm/cacheflush.h>
-#include <mach/memory.h>
-#include <plat/sram.h>
-#include <mach/gpio.h>
-#include <mach/debug_uart.h>
-
-/* SRAM section definitions from the linker */
-extern char __sram_code_start, __ssram_code_text, __esram_code_text;
-extern char __sram_data_start, __ssram_data, __esram_data;
-
-#if defined(CONFIG_ARCH_RK30)
-#define SRAM_NONCACHED RK30_IMEM_NONCACHED
-#define SRAM_CACHED RK30_IMEM_BASE
-#define SRAM_PHYS RK30_IMEM_PHYS
-#define SRAM_SIZE RK30_IMEM_SIZE
-#elif defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK3026)
-#define SRAM_NONCACHED RK2928_IMEM_NONCACHED
-#define SRAM_CACHED RK2928_IMEM_BASE
-#define SRAM_PHYS RK2928_IMEM_PHYS
-#define SRAM_SIZE RK2928_IMEM_SIZE
-#elif defined(CONFIG_ARCH_RK3188)
-#define SRAM_NONCACHED RK30_IMEM_NONCACHED
-#define SRAM_CACHED RK30_IMEM_BASE
-#define SRAM_PHYS RK30_IMEM_PHYS
-#define SRAM_SIZE RK3188_IMEM_SIZE
-#endif
-
-static struct map_desc sram_io_desc[] __initdata = {
- {
- .virtual = (unsigned long) SRAM_CACHED,
- .pfn = __phys_to_pfn(0x0),
- .length = SZ_1M,
- .type = MT_MEMORY,
- },
- {
- .virtual = (unsigned long) SRAM_NONCACHED,
- .pfn = __phys_to_pfn(SRAM_PHYS),
- .length = SRAM_SIZE,
- .type = MT_MEMORY_NONCACHED,
- },
-};
-
-#define SRAM_LOG_BUF_LEN 64
-static char __sramdata *sram_log_buf;
-static unsigned char __sramdata sram_log_end;
-#define SRAM_LOG_BUF_MASK (SRAM_LOG_BUF_LEN-1)
-#define SRAM_LOG_BUF(idx) (sram_log_buf[(idx) & SRAM_LOG_BUF_MASK])
-
-void __sramfunc sram_log_char(char c)
-{
- if (!sram_log_buf)
- return;
- SRAM_LOG_BUF(sram_log_end) = c;
- sram_log_end++;
-}
-
-void __sramfunc sram_log_reset(void)
-{
- int i;
- if (!sram_log_buf)
- return;
- for (i = 0; i < SRAM_LOG_BUF_LEN; i++)
- sram_log_buf[i] = 0;
- sram_log_end = 0;
-}
-
-#include <linux/ctype.h>
-void __init sram_log_dump(void)
-{
- int i;
-
- if ((u32)SRAM_DATA_END & SRAM_LOG_BUF_LEN)
- sram_log_buf = NULL;
- else
- sram_log_buf = SRAM_NONCACHED + (SRAM_DATA_END - SRAM_CACHED) + 1;
- if (!sram_log_buf)
- return;
-
- printk("sram_log: ");
- for (i = 0; i < SRAM_LOG_BUF_LEN; i++) {
- char c = sram_log_buf[i];
- if (isascii(c) && isprint(c))
- printk(KERN_CONT "%c", c);
- else
- printk(KERN_CONT " ");
- }
- printk(KERN_CONT "\n");
-}
-
-int __init rk29_sram_init(void)
-{
- char *start;
- char *end;
- char *ram;
-
- iotable_init(sram_io_desc, ARRAY_SIZE(sram_io_desc));
-
- /*
- * Normally devicemaps_init() would flush caches and tlb after
- * mdesc->map_io(), but since we're called from map_io(), we
- * must do it here.
- */
- local_flush_tlb_all();
- flush_cache_all();
-
- memset((char *)SRAM_CODE_OFFSET,0x0,(SRAM_CODE_END - SRAM_CODE_OFFSET + 1));
- memset((char *)SRAM_DATA_OFFSET,0x0,(SRAM_DATA_END - SRAM_DATA_OFFSET + 1));
-
- /* Copy code from RAM to SRAM CODE */
- start = &__ssram_code_text;
- end = &__esram_code_text;
- ram = &__sram_code_start;
- memcpy(start, ram, (end-start));
- flush_icache_range((unsigned long) start, (unsigned long) end);
-
- printk("CPU SRAM: copied sram code from %p to %p - %p\n", ram, start, end);
-
- /* Copy data from RAM to SRAM DATA */
- start = &__ssram_data;
- end = &__esram_data;
- ram = &__sram_data_start;
- memcpy(start, ram, (end-start));
-
- printk("CPU SRAM: copied sram data from %p to %p - %p\n", ram, start, end);
-
- sram_log_dump();
-
- return 0;
-}
-
-__weak void __sramfunc sram_printch(char byte)
-{
- sram_log_char(byte);
-#ifdef DEBUG_UART_BASE
- writel_relaxed(byte, DEBUG_UART_BASE);
- dsb();
-
- /* loop check LSR[6], Transmitter Empty bit */
- while (!(readl_relaxed(DEBUG_UART_BASE + 0x14) & 0x40))
- barrier();
-
- if (byte == '\n')
- sram_printch('\r');
-#endif
-}
-
-void __sramfunc sram_printascii(const char *s)
-{
- while (*s) {
- sram_printch(*s);
- s++;
- }
-}
-
-void __sramfunc sram_printhex(unsigned int hex)
-{
- int i = 8;
- sram_printch('0');
- sram_printch('x');
- while (i--) {
- unsigned char c = (hex & 0xF0000000) >> 28;
- sram_printch(c < 0xa ? c + '0' : c - 0xa + 'a');
- hex <<= 4;
- }
-}
-
-struct sram_gpio_data __sramdata pmic_sleep,pmic_vsel;
-#if defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK3026)
-static void __iomem *gpio_base[] = {RK2928_GPIO0_BASE, RK2928_GPIO1_BASE, RK2928_GPIO2_BASE, RK2928_GPIO3_BASE};
-#elif defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
-static void __iomem *gpio_base[] = {RK30_GPIO0_BASE, RK30_GPIO1_BASE, RK30_GPIO2_BASE, RK30_GPIO3_BASE};
-#elif defined(CONFIG_ARCH_RK30)
-static void __iomem *gpio_base[] = {RK30_GPIO0_BASE, RK30_GPIO1_BASE, RK30_GPIO2_BASE, RK30_GPIO3_BASE,
- RK30_GPIO4_BASE, 0, RK30_GPIO6_BASE};
-#elif defined(CONFIG_ARCH_RK319X)
-static void __iomem *gpio_base[] = {RK319X_GPIO0_BASE, RK319X_GPIO1_BASE, RK319X_GPIO2_BASE, RK319X_GPIO3_BASE, RK319X_GPIO4_BASE};
-#endif
-
-int sram_gpio_init(int gpio, struct sram_gpio_data *data)
-{
- unsigned index;
-
- if(gpio == INVALID_GPIO)
- return -EINVAL;
- index = gpio - PIN_BASE;
- if(index/NUM_GROUP >= ARRAY_SIZE(gpio_base))
- return -EINVAL;
-
- data->base = gpio_base[index/NUM_GROUP];
- if(data->base == 0)
- return -EINVAL;
-
- data->offset = index%NUM_GROUP;
-
- return 0;
-}
-
-void __sramfunc sram_gpio_set_value(struct sram_gpio_data data, uint value)
-{
- writel_relaxed(readl_relaxed(data.base + GPIO_SWPORTA_DDR)| (1<<data.offset),
- data.base + GPIO_SWPORTA_DDR);
- if(value)
- writel_relaxed(readl_relaxed(data.base + GPIO_SWPORTA_DR) | (1<<data.offset),
- data.base + GPIO_SWPORTA_DR);
- else
- writel_relaxed(readl_relaxed(data.base + GPIO_SWPORTA_DR) & ~(1<<data.offset),
- data.base + GPIO_SWPORTA_DR);
-}
-
-
+++ /dev/null
-#include <linux/wakelock.h>
-#include <linux/workqueue.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <mach/board.h>
-
-#define WAKE_LOCK_TIMEOUT (10 * HZ)
-
-static irqreturn_t usb_detect_irq_handler(int irq, void *dev_id);
-static int detect_gpio = INVALID_GPIO;
-
-static void usb_detect_do_wakeup(struct work_struct *work)
-{
- int ret;
- int irq = gpio_to_irq(detect_gpio);
- unsigned int type;
-
- rk28_send_wakeup_key();
- type = gpio_get_value(detect_gpio) ? IRQ_TYPE_EDGE_FALLING : IRQ_TYPE_EDGE_RISING;
- ret = irq_set_irq_type(irq, type);
- if (ret < 0) {
- pr_err("%s: irq_set_irq_type(%d, %d) failed\n", __func__, irq, type);
- }
- enable_irq(irq);
-}
-
-static DECLARE_DELAYED_WORK(wakeup_work, usb_detect_do_wakeup);
-static bool wakelock_inited;
-static struct wake_lock usb_wakelock;
-
-static irqreturn_t usb_detect_irq_handler(int irq, void *dev_id)
-{
- disable_irq_nosync(irq); // for irq debounce
- wake_lock_timeout(&usb_wakelock, WAKE_LOCK_TIMEOUT);
- schedule_delayed_work(&wakeup_work, HZ / 10);
- return IRQ_HANDLED;
-}
-
-#ifndef CONFIG_RK_USB_DETECT_BY_OTG_BVALID
-int __init board_usb_detect_init(unsigned gpio)
-{
- int ret;
- int irq = gpio_to_irq(gpio);
- unsigned long flags;
-
- if (detect_gpio != INVALID_GPIO) {
- pr_err("only support call %s once\n", __func__);
- return -EINVAL;
- }
-
- ret = gpio_request(gpio, "usb_detect");
- if (ret < 0) {
- pr_err("%s: gpio_request(%d) failed\n", __func__, gpio);
- return ret;
- }
-
- if (!wakelock_inited) {
- wake_lock_init(&usb_wakelock, WAKE_LOCK_SUSPEND, "usb_detect");
- wakelock_inited = true;
- }
-
- gpio_direction_input(gpio);
-
- detect_gpio = gpio;
-
- flags = gpio_get_value(gpio) ? IRQF_TRIGGER_FALLING : IRQF_TRIGGER_RISING;
- ret = request_irq(irq, usb_detect_irq_handler, flags, "usb_detect", NULL);
- if (ret < 0) {
- pr_err("%s: request_irq(%d) failed\n", __func__, irq);
- gpio_free(gpio);
- detect_gpio = INVALID_GPIO;
- return ret;
- }
- enable_irq_wake(irq);
-
- return 0;
-}
-#endif
-
-#ifdef IRQ_OTG_BVALID
-#include <linux/io.h>
-#include <mach/iomux.h>
-
-static irqreturn_t bvalid_irq_handler(int irq, void *dev_id)
-{
- /* clear irq */
-#ifdef CONFIG_ARCH_RK2928
- writel_relaxed((1 << 31) | (1 << 15), RK2928_GRF_BASE + GRF_UOC0_CON5);
-#ifdef CONFIG_RK_USB_UART
- /* usb otg dp/dm switch to usb phy */
- writel_relaxed((3 << (12 + 16)),RK2928_GRF_BASE + GRF_UOC1_CON4);
-#endif
-#elif defined(CONFIG_ARCH_RK3188)
- writel_relaxed((1 << 31) | (1 << 15), RK30_GRF_BASE + GRF_UOC0_CON3);
-#ifdef CONFIG_RK_USB_UART
- /* usb otg dp/dm switch to usb phy */
- writel_relaxed((0x0300 << 16), RK30_GRF_BASE + GRF_UOC0_CON0);
-#endif
-#endif
-
-#ifdef CONFIG_RK_USB_DETECT_BY_OTG_BVALID
- wake_lock_timeout(&usb_wakelock, WAKE_LOCK_TIMEOUT);
- rk28_send_wakeup_key();
-#endif
-
- return IRQ_HANDLED;
-}
-
-static int __init bvalid_init(void)
-{
- int ret;
- int irq = IRQ_OTG_BVALID;
-
-#ifndef CONFIG_RK_USB_UART
- if (detect_gpio != INVALID_GPIO) {
- printk("usb detect inited by board_usb_detect_init, disable detect by bvalid irq\n");
- return 0;
- }
-#endif
-
-#ifdef CONFIG_RK_USB_DETECT_BY_OTG_BVALID
- if (!wakelock_inited) {
- wake_lock_init(&usb_wakelock, WAKE_LOCK_SUSPEND, "usb_detect");
- wakelock_inited = true;
- }
-#endif
-
- ret = request_irq(irq, bvalid_irq_handler, 0, "bvalid", NULL);
- if (ret < 0) {
- pr_err("%s: request_irq(%d) failed\n", __func__, irq);
- return ret;
- }
-
- /* clear & enable bvalid irq */
-#ifdef CONFIG_ARCH_RK2928
- writel_relaxed((3 << 30) | (3 << 14), RK2928_GRF_BASE + GRF_UOC0_CON5);
-#elif defined(CONFIG_ARCH_RK3188)
- writel_relaxed((3 << 30) | (3 << 14), RK30_GRF_BASE + GRF_UOC0_CON3);
-#endif
-
-#ifdef CONFIG_RK_USB_DETECT_BY_OTG_BVALID
- enable_irq_wake(irq);
-#endif
-
- return 0;
-}
-#if defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK3188)
-late_initcall(bvalid_init);
-#endif
-#endif
-
+++ /dev/null
-/* arch/arm/mach-rk29/vpu.c
- *
- * Copyright (C) 2010 ROCKCHIP, Inc.
- * author: chenhengming chm@rock-chips.com
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifdef CONFIG_RK29_VPU_DEBUG
-#define DEBUG
-#define pr_fmt(fmt) "VPU_SERVICE: %s: " fmt, __func__
-#else
-#define pr_fmt(fmt) "VPU_SERVICE: " fmt
-#endif
-
-
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/fs.h>
-#include <linux/ioport.h>
-#include <linux/miscdevice.h>
-#include <linux/mm.h>
-#include <linux/poll.h>
-#include <linux/platform_device.h>
-#include <linux/sched.h>
-#include <linux/slab.h>
-#include <linux/wakelock.h>
-
-#include <asm/uaccess.h>
-
-#include <mach/irqs.h>
-#include <mach/pmu.h>
-#include <mach/cru.h>
-
-#include <plat/vpu_service.h>
-#include <plat/cpu.h>
-
-typedef enum {
- VPU_DEC_ID_9190 = 0x6731,
- VPU_ID_8270 = 0x8270,
- VPU_ID_4831 = 0x4831,
-} VPU_HW_ID;
-
-typedef enum {
- VPU_DEC_TYPE_9190 = 0,
- VPU_ENC_TYPE_8270 = 0x100,
- VPU_ENC_TYPE_4831 ,
-} VPU_HW_TYPE_E;
-
-typedef enum VPU_FREQ {
- VPU_FREQ_200M,
- VPU_FREQ_266M,
- VPU_FREQ_300M,
- VPU_FREQ_400M,
- VPU_FREQ_DEFAULT,
- VPU_FREQ_BUT,
-} VPU_FREQ;
-
-typedef struct {
- VPU_HW_ID hw_id;
- unsigned long hw_addr;
- unsigned long enc_offset;
- unsigned long enc_reg_num;
- unsigned long enc_io_size;
- unsigned long dec_offset;
- unsigned long dec_reg_num;
- unsigned long dec_io_size;
-} VPU_HW_INFO_E;
-
-#define VPU_SERVICE_SHOW_TIME 0
-
-#if VPU_SERVICE_SHOW_TIME
-static struct timeval enc_start, enc_end;
-static struct timeval dec_start, dec_end;
-static struct timeval pp_start, pp_end;
-#endif
-
-#define MHZ (1000*1000)
-
-#define VCODEC_PHYS (0x10104000)
-
-#define REG_NUM_9190_DEC (60)
-#define REG_NUM_9190_PP (41)
-#define REG_NUM_9190_DEC_PP (REG_NUM_9190_DEC+REG_NUM_9190_PP)
-
-#define REG_NUM_DEC_PP (REG_NUM_9190_DEC+REG_NUM_9190_PP)
-
-#define REG_NUM_ENC_8270 (96)
-#define REG_SIZE_ENC_8270 (0x200)
-#define REG_NUM_ENC_4831 (164)
-#define REG_SIZE_ENC_4831 (0x400)
-
-#define SIZE_REG(reg) ((reg)*4)
-
-VPU_HW_INFO_E vpu_hw_set[] = {
- [0] = {
- .hw_id = VPU_ID_8270,
- .hw_addr = VCODEC_PHYS,
- .enc_offset = 0x0,
- .enc_reg_num = REG_NUM_ENC_8270,
- .enc_io_size = REG_NUM_ENC_8270 * 4,
- .dec_offset = REG_SIZE_ENC_8270,
- .dec_reg_num = REG_NUM_9190_DEC_PP,
- .dec_io_size = REG_NUM_9190_DEC_PP * 4,
- },
- [1] = {
- .hw_id = VPU_ID_4831,
- .hw_addr = VCODEC_PHYS,
- .enc_offset = 0x0,
- .enc_reg_num = REG_NUM_ENC_4831,
- .enc_io_size = REG_NUM_ENC_4831 * 4,
- .dec_offset = REG_SIZE_ENC_4831,
- .dec_reg_num = REG_NUM_9190_DEC_PP,
- .dec_io_size = REG_NUM_9190_DEC_PP * 4,
- },
-};
-
-
-#define DEC_INTERRUPT_REGISTER 1
-#define PP_INTERRUPT_REGISTER 60
-#define ENC_INTERRUPT_REGISTER 1
-
-#define DEC_INTERRUPT_BIT 0x100
-#define DEC_BUFFER_EMPTY_BIT 0x4000
-#define PP_INTERRUPT_BIT 0x100
-#define ENC_INTERRUPT_BIT 0x1
-
-#define VPU_REG_EN_ENC 14
-#define VPU_REG_ENC_GATE 2
-#define VPU_REG_ENC_GATE_BIT (1<<4)
-
-#define VPU_REG_EN_DEC 1
-#define VPU_REG_DEC_GATE 2
-#define VPU_REG_DEC_GATE_BIT (1<<10)
-#define VPU_REG_EN_PP 0
-#define VPU_REG_PP_GATE 1
-#define VPU_REG_PP_GATE_BIT (1<<8)
-#define VPU_REG_EN_DEC_PP 1
-#define VPU_REG_DEC_PP_GATE 61
-#define VPU_REG_DEC_PP_GATE_BIT (1<<8)
-
-/**
- * struct for process session which connect to vpu
- *
- * @author ChenHengming (2011-5-3)
- */
-typedef struct vpu_session {
- VPU_CLIENT_TYPE type;
- /* a linked list of data so we can access them for debugging */
- struct list_head list_session;
- /* a linked list of register data waiting for process */
- struct list_head waiting;
- /* a linked list of register data in processing */
- struct list_head running;
- /* a linked list of register data processed */
- struct list_head done;
- wait_queue_head_t wait;
- pid_t pid;
- atomic_t task_running;
-} vpu_session;
-
-/**
- * struct for process register set
- *
- * @author ChenHengming (2011-5-4)
- */
-typedef struct vpu_reg {
- VPU_CLIENT_TYPE type;
- VPU_FREQ freq;
- vpu_session *session;
- struct list_head session_link; /* link to vpu service session */
- struct list_head status_link; /* link to register set list */
- unsigned long size;
- unsigned long *reg;
-} vpu_reg;
-
-typedef struct vpu_device {
- atomic_t irq_count_codec;
- atomic_t irq_count_pp;
- unsigned long iobaseaddr;
- unsigned int iosize;
- volatile u32 *hwregs;
-} vpu_device;
-
-typedef struct vpu_service_info {
- struct wake_lock wake_lock;
- struct delayed_work power_off_work;
- struct mutex lock;
- struct list_head waiting; /* link to link_reg in struct vpu_reg */
- struct list_head running; /* link to link_reg in struct vpu_reg */
- struct list_head done; /* link to link_reg in struct vpu_reg */
- struct list_head session; /* link to list_session in struct vpu_session */
- atomic_t total_running;
- bool enabled;
- vpu_reg *reg_codec;
- vpu_reg *reg_pproc;
- vpu_reg *reg_resev;
- VPUHwDecConfig_t dec_config;
- VPUHwEncConfig_t enc_config;
- VPU_HW_INFO_E *hw_info;
- unsigned long reg_size;
- bool auto_freq;
- bool bug_dec_addr;
- atomic_t freq_status;
-} vpu_service_info;
-
-typedef struct vpu_request
-{
- unsigned long *req;
- unsigned long size;
-} vpu_request;
-
-static struct clk *pd_video;
-static struct clk *aclk_vepu;
-static struct clk *hclk_vepu;
-static struct clk *aclk_ddr_vepu;
-static struct clk *hclk_cpu_vcodec;
-static vpu_service_info service;
-static vpu_device dec_dev;
-static vpu_device enc_dev;
-static unsigned int irq_vdpu = IRQ_VDPU;
-static unsigned int irq_vepu = IRQ_VEPU;
-
-#define VPU_POWER_OFF_DELAY 4*HZ /* 4s */
-#define VPU_TIMEOUT_DELAY 2*HZ /* 2s */
-
-static void vpu_get_clk(void)
-{
- pd_video = clk_get(NULL, "pd_video");
- if (IS_ERR(pd_video)) {
- pr_err("failed on clk_get pd_video\n");
- }
- aclk_vepu = clk_get(NULL, "aclk_vepu");
- if (IS_ERR(aclk_vepu)) {
- pr_err("failed on clk_get aclk_vepu\n");
- }
- hclk_vepu = clk_get(NULL, "hclk_vepu");
- if (IS_ERR(hclk_vepu)) {
- pr_err("failed on clk_get hclk_vepu\n");
- }
- aclk_ddr_vepu = clk_get(NULL, "aclk_ddr_vepu");
- if (IS_ERR(aclk_ddr_vepu)) {
- ;//pr_err("failed on clk_get aclk_ddr_vepu\n");
- }
- hclk_cpu_vcodec = clk_get(NULL, "hclk_cpu_vcodec");
- if (IS_ERR(hclk_cpu_vcodec)) {
- ;//pr_err("failed on clk_get hclk_cpu_vcodec\n");
- }
-}
-
-static void vpu_put_clk(void)
-{
- clk_put(pd_video);
- clk_put(aclk_vepu);
- clk_put(hclk_vepu);
- clk_put(aclk_ddr_vepu);
- clk_put(hclk_cpu_vcodec);
-}
-
-static void vpu_reset(void)
-{
-#if defined(CONFIG_ARCH_RK29)
- clk_disable(aclk_ddr_vepu);
- cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, true);
- cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, true);
- cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, true);
- cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, true);
- mdelay(10);
- cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, false);
- cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, false);
- cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, false);
- cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, false);
- clk_enable(aclk_ddr_vepu);
-#elif defined(CONFIG_ARCH_RK30)
- pmu_set_idle_request(IDLE_REQ_VIDEO, true);
- cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);
- cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, true);
- cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);
- cru_set_soft_reset(SOFT_RST_VCODEC_AXI, true);
- mdelay(1);
- cru_set_soft_reset(SOFT_RST_VCODEC_AXI, false);
- cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);
- cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, false);
- cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);
- pmu_set_idle_request(IDLE_REQ_VIDEO, false);
-#endif
- service.reg_codec = NULL;
- service.reg_pproc = NULL;
- service.reg_resev = NULL;
-}
-
-static void reg_deinit(vpu_reg *reg);
-static void vpu_service_session_clear(vpu_session *session)
-{
- vpu_reg *reg, *n;
- list_for_each_entry_safe(reg, n, &session->waiting, session_link) {
- reg_deinit(reg);
- }
- list_for_each_entry_safe(reg, n, &session->running, session_link) {
- reg_deinit(reg);
- }
- list_for_each_entry_safe(reg, n, &session->done, session_link) {
- reg_deinit(reg);
- }
-}
-
-static void vpu_service_dump(void)
-{
- int running;
- vpu_reg *reg, *reg_tmp;
- vpu_session *session, *session_tmp;
-
- running = atomic_read(&service.total_running);
- printk("total_running %d\n", running);
-
- printk("reg_codec 0x%.8x\n", (unsigned int)service.reg_codec);
- printk("reg_pproc 0x%.8x\n", (unsigned int)service.reg_pproc);
- printk("reg_resev 0x%.8x\n", (unsigned int)service.reg_resev);
-
- list_for_each_entry_safe(session, session_tmp, &service.session, list_session) {
- printk("session pid %d type %d:\n", session->pid, session->type);
- running = atomic_read(&session->task_running);
- printk("task_running %d\n", running);
- list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {
- printk("waiting register set 0x%.8x\n", (unsigned int)reg);
- }
- list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {
- printk("running register set 0x%.8x\n", (unsigned int)reg);
- }
- list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {
- printk("done register set 0x%.8x\n", (unsigned int)reg);
- }
- }
-}
-
-static void vpu_service_power_off(void)
-{
- int total_running;
- if (!service.enabled) {
- return;
- }
-
- service.enabled = false;
- total_running = atomic_read(&service.total_running);
- if (total_running) {
- pr_alert("alert: power off when %d task running!!\n", total_running);
- mdelay(50);
- pr_alert("alert: delay 50 ms for running task\n");
- vpu_service_dump();
- }
-
- printk("vpu: power off...");
-#ifdef CONFIG_ARCH_RK29
- pmu_set_power_domain(PD_VCODEC, false);
-#else
- clk_disable(pd_video);
-#endif
- udelay(10);
- clk_disable(hclk_cpu_vcodec);
- clk_disable(aclk_ddr_vepu);
- clk_disable(hclk_vepu);
- clk_disable(aclk_vepu);
- wake_unlock(&service.wake_lock);
- printk("done\n");
-}
-
-static inline void vpu_queue_power_off_work(void)
-{
- queue_delayed_work(system_nrt_wq, &service.power_off_work, VPU_POWER_OFF_DELAY);
-}
-
-static void vpu_power_off_work(struct work_struct *work)
-{
- if (mutex_trylock(&service.lock)) {
- vpu_service_power_off();
- mutex_unlock(&service.lock);
- } else {
- /* Come back later if the device is busy... */
- vpu_queue_power_off_work();
- }
-}
-
-static void vpu_service_power_on(void)
-{
- static ktime_t last;
- ktime_t now = ktime_get();
- if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {
- cancel_delayed_work_sync(&service.power_off_work);
- vpu_queue_power_off_work();
- last = now;
- }
- if (service.enabled)
- return ;
-
- service.enabled = true;
- printk("vpu: power on\n");
-
- clk_enable(aclk_vepu);
- clk_enable(hclk_vepu);
- clk_enable(hclk_cpu_vcodec);
- udelay(10);
-#ifdef CONFIG_ARCH_RK29
- pmu_set_power_domain(PD_VCODEC, true);
-#else
- clk_enable(pd_video);
-#endif
- udelay(10);
- clk_enable(aclk_ddr_vepu);
- wake_lock(&service.wake_lock);
-}
-
-static inline bool reg_check_rmvb_wmv(vpu_reg *reg)
-{
- unsigned long type = (reg->reg[3] & 0xF0000000) >> 28;
- return ((type == 8) || (type == 4));
-}
-
-static inline bool reg_check_interlace(vpu_reg *reg)
-{
- unsigned long type = (reg->reg[3] & (1 << 23));
- return (type > 0);
-}
-
-static vpu_reg *reg_init(vpu_session *session, void __user *src, unsigned long size)
-{
- vpu_reg *reg = kmalloc(sizeof(vpu_reg)+service.reg_size, GFP_KERNEL);
- if (NULL == reg) {
- pr_err("error: kmalloc fail in reg_init\n");
- return NULL;
- }
-
- if (size > service.reg_size) {
- printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, service.reg_size);
- size = service.reg_size;
- }
- reg->session = session;
- reg->type = session->type;
- reg->size = size;
- reg->freq = VPU_FREQ_DEFAULT;
- reg->reg = (unsigned long *)®[1];
- INIT_LIST_HEAD(®->session_link);
- INIT_LIST_HEAD(®->status_link);
-
- if (copy_from_user(®->reg[0], (void __user *)src, size)) {
- pr_err("error: copy_from_user failed in reg_init\n");
- kfree(reg);
- return NULL;
- }
-
- mutex_lock(&service.lock);
- list_add_tail(®->status_link, &service.waiting);
- list_add_tail(®->session_link, &session->waiting);
- mutex_unlock(&service.lock);
-
- if (service.auto_freq) {
- if (!soc_is_rk2928g()) {
- if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
- if (reg_check_rmvb_wmv(reg)) {
- reg->freq = VPU_FREQ_200M;
- } else {
- if (reg_check_interlace(reg)) {
- reg->freq = VPU_FREQ_400M;
- }
- }
- }
- if (reg->type == VPU_PP) {
- reg->freq = VPU_FREQ_400M;
- }
- }
- }
-
- return reg;
-}
-
-static void reg_deinit(vpu_reg *reg)
-{
- list_del_init(®->session_link);
- list_del_init(®->status_link);
- if (reg == service.reg_codec) service.reg_codec = NULL;
- if (reg == service.reg_pproc) service.reg_pproc = NULL;
- kfree(reg);
-}
-
-static void reg_from_wait_to_run(vpu_reg *reg)
-{
- list_del_init(®->status_link);
- list_add_tail(®->status_link, &service.running);
-
- list_del_init(®->session_link);
- list_add_tail(®->session_link, ®->session->running);
-}
-
-static void reg_copy_from_hw(vpu_reg *reg, volatile u32 *src, u32 count)
-{
- int i;
- u32 *dst = (u32 *)®->reg[0];
- for (i = 0; i < count; i++)
- *dst++ = *src++;
-}
-
-static void reg_from_run_to_done(vpu_reg *reg)
-{
- list_del_init(®->status_link);
- list_add_tail(®->status_link, &service.done);
-
- list_del_init(®->session_link);
- list_add_tail(®->session_link, ®->session->done);
-
- switch (reg->type) {
- case VPU_ENC : {
- service.reg_codec = NULL;
- reg_copy_from_hw(reg, enc_dev.hwregs, service.hw_info->enc_reg_num);
- break;
- }
- case VPU_DEC : {
- service.reg_codec = NULL;
- reg_copy_from_hw(reg, dec_dev.hwregs, REG_NUM_9190_DEC);
- break;
- }
- case VPU_PP : {
- service.reg_pproc = NULL;
- reg_copy_from_hw(reg, dec_dev.hwregs + PP_INTERRUPT_REGISTER, REG_NUM_9190_PP);
- dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
- break;
- }
- case VPU_DEC_PP : {
- service.reg_codec = NULL;
- service.reg_pproc = NULL;
- reg_copy_from_hw(reg, dec_dev.hwregs, REG_NUM_9190_DEC_PP);
- dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
- break;
- }
- default : {
- pr_err("error: copy reg from hw with unknown type %d\n", reg->type);
- break;
- }
- }
- atomic_sub(1, ®->session->task_running);
- atomic_sub(1, &service.total_running);
- wake_up(®->session->wait);
-}
-
-static void vpu_service_set_freq(vpu_reg *reg)
-{
- VPU_FREQ curr = atomic_read(&service.freq_status);
- if (curr == reg->freq) {
- return ;
- }
- atomic_set(&service.freq_status, reg->freq);
- switch (reg->freq) {
- case VPU_FREQ_200M : {
- clk_set_rate(aclk_vepu, 200*MHZ);
- //printk("default: 200M\n");
- } break;
- case VPU_FREQ_266M : {
- clk_set_rate(aclk_vepu, 266*MHZ);
- //printk("default: 266M\n");
- } break;
- case VPU_FREQ_300M : {
- clk_set_rate(aclk_vepu, 300*MHZ);
- //printk("default: 300M\n");
- } break;
- case VPU_FREQ_400M : {
- clk_set_rate(aclk_vepu, 400*MHZ);
- //printk("default: 400M\n");
- } break;
- default : {
- if (soc_is_rk2928g()) {
- clk_set_rate(aclk_vepu, 400*MHZ);
- } else {
- clk_set_rate(aclk_vepu, 300*MHZ);
- }
- //printk("default: 300M\n");
- } break;
- }
-}
-
-static void reg_copy_to_hw(vpu_reg *reg)
-{
- int i;
- u32 *src = (u32 *)®->reg[0];
- atomic_add(1, &service.total_running);
- atomic_add(1, ®->session->task_running);
- if (service.auto_freq) {
- vpu_service_set_freq(reg);
- }
- switch (reg->type) {
- case VPU_ENC : {
- int enc_count = service.hw_info->enc_reg_num;
- u32 *dst = (u32 *)enc_dev.hwregs;
- if (service.bug_dec_addr) {
- cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);
- cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);
- cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);
- cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);
- }
-
- service.reg_codec = reg;
-
- dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC] & 0x6;
-
- for (i = 0; i < VPU_REG_EN_ENC; i++)
- dst[i] = src[i];
-
- for (i = VPU_REG_EN_ENC + 1; i < enc_count; i++)
- dst[i] = src[i];
-
- dsb();
-
- dst[VPU_REG_ENC_GATE] = src[VPU_REG_ENC_GATE] | VPU_REG_ENC_GATE_BIT;
- dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC];
-
-#if VPU_SERVICE_SHOW_TIME
- do_gettimeofday(&enc_start);
-#endif
-
- } break;
- case VPU_DEC : {
- u32 *dst = (u32 *)dec_dev.hwregs;
- service.reg_codec = reg;
-
- for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)
- dst[i] = src[i];
-
- dsb();
-
- dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;
- dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
-
-#if VPU_SERVICE_SHOW_TIME
- do_gettimeofday(&dec_start);
-#endif
-
- } break;
- case VPU_PP : {
- u32 *dst = (u32 *)dec_dev.hwregs + PP_INTERRUPT_REGISTER;
- service.reg_pproc = reg;
-
- dst[VPU_REG_PP_GATE] = src[VPU_REG_PP_GATE] | VPU_REG_PP_GATE_BIT;
-
- for (i = VPU_REG_PP_GATE + 1; i < REG_NUM_9190_PP; i++)
- dst[i] = src[i];
-
- dsb();
-
- dst[VPU_REG_EN_PP] = src[VPU_REG_EN_PP];
-
-#if VPU_SERVICE_SHOW_TIME
- do_gettimeofday(&pp_start);
-#endif
-
- } break;
- case VPU_DEC_PP : {
- u32 *dst = (u32 *)dec_dev.hwregs;
- service.reg_codec = reg;
- service.reg_pproc = reg;
-
- for (i = VPU_REG_EN_DEC_PP + 1; i < REG_NUM_9190_DEC_PP; i++)
- dst[i] = src[i];
-
- dst[VPU_REG_EN_DEC_PP] = src[VPU_REG_EN_DEC_PP] | 0x2;
- dsb();
-
- dst[VPU_REG_DEC_PP_GATE] = src[VPU_REG_DEC_PP_GATE] | VPU_REG_PP_GATE_BIT;
- dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;
- dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
-
-#if VPU_SERVICE_SHOW_TIME
- do_gettimeofday(&dec_start);
-#endif
-
- } break;
- default : {
- pr_err("error: unsupport session type %d", reg->type);
- atomic_sub(1, &service.total_running);
- atomic_sub(1, ®->session->task_running);
- break;
- }
- }
-}
-
-static void try_set_reg(void)
-{
- // first get reg from reg list
- if (!list_empty(&service.waiting)) {
- int can_set = 0;
- vpu_reg *reg = list_entry(service.waiting.next, vpu_reg, status_link);
-
- vpu_service_power_on();
-
- switch (reg->type) {
- case VPU_ENC : {
- if ((NULL == service.reg_codec) && (NULL == service.reg_pproc))
- can_set = 1;
- } break;
- case VPU_DEC : {
- if (NULL == service.reg_codec)
- can_set = 1;
- if (service.auto_freq && (NULL != service.reg_pproc)) {
- can_set = 0;
- }
- } break;
- case VPU_PP : {
- if (NULL == service.reg_codec) {
- if (NULL == service.reg_pproc)
- can_set = 1;
- } else {
- if ((VPU_DEC == service.reg_codec->type) && (NULL == service.reg_pproc))
- can_set = 1;
- // can not charge frequency when vpu is working
- if (service.auto_freq) {
- can_set = 0;
- }
- }
- } break;
- case VPU_DEC_PP : {
- if ((NULL == service.reg_codec) && (NULL == service.reg_pproc))
- can_set = 1;
- } break;
- default : {
- printk("undefined reg type %d\n", reg->type);
- } break;
- }
- if (can_set) {
- reg_from_wait_to_run(reg);
- reg_copy_to_hw(reg);
- }
- }
-}
-
-static int return_reg(vpu_reg *reg, u32 __user *dst)
-{
- int ret = 0;
- switch (reg->type) {
- case VPU_ENC : {
- if (copy_to_user(dst, ®->reg[0], service.hw_info->enc_io_size))
- ret = -EFAULT;
- break;
- }
- case VPU_DEC : {
- if (copy_to_user(dst, ®->reg[0], SIZE_REG(REG_NUM_9190_DEC)))
- ret = -EFAULT;
- break;
- }
- case VPU_PP : {
- if (copy_to_user(dst, ®->reg[0], SIZE_REG(REG_NUM_9190_PP)))
- ret = -EFAULT;
- break;
- }
- case VPU_DEC_PP : {
- if (copy_to_user(dst, ®->reg[0], SIZE_REG(REG_NUM_9190_DEC_PP)))
- ret = -EFAULT;
- break;
- }
- default : {
- ret = -EFAULT;
- pr_err("error: copy reg to user with unknown type %d\n", reg->type);
- break;
- }
- }
- reg_deinit(reg);
- return ret;
-}
-
-static long vpu_service_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
-{
- vpu_session *session = (vpu_session *)filp->private_data;
- if (NULL == session) {
- return -EINVAL;
- }
-
- switch (cmd) {
- case VPU_IOC_SET_CLIENT_TYPE : {
- session->type = (VPU_CLIENT_TYPE)arg;
- break;
- }
- case VPU_IOC_GET_HW_FUSE_STATUS : {
- vpu_request req;
- if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {
- pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_from_user failed\n");
- return -EFAULT;
- } else {
- if (VPU_ENC != session->type) {
- if (copy_to_user((void __user *)req.req, &service.dec_config, sizeof(VPUHwDecConfig_t))) {
- pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);
- return -EFAULT;
- }
- } else {
- if (copy_to_user((void __user *)req.req, &service.enc_config, sizeof(VPUHwEncConfig_t))) {
- pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);
- return -EFAULT;
- }
- }
- }
-
- break;
- }
- case VPU_IOC_SET_REG : {
- vpu_request req;
- vpu_reg *reg;
- if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {
- pr_err("error: VPU_IOC_SET_REG copy_from_user failed\n");
- return -EFAULT;
- }
- reg = reg_init(session, (void __user *)req.req, req.size);
- if (NULL == reg) {
- return -EFAULT;
- } else {
- mutex_lock(&service.lock);
- try_set_reg();
- mutex_unlock(&service.lock);
- }
-
- break;
- }
- case VPU_IOC_GET_REG : {
- vpu_request req;
- vpu_reg *reg;
- if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {
- pr_err("error: VPU_IOC_GET_REG copy_from_user failed\n");
- return -EFAULT;
- } else {
- int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);
- if (!list_empty(&session->done)) {
- if (ret < 0) {
- pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);
- }
- ret = 0;
- } else {
- if (unlikely(ret < 0)) {
- pr_err("error: pid %d wait task ret %d\n", session->pid, ret);
- } else if (0 == ret) {
- pr_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
- ret = -ETIMEDOUT;
- }
- }
- if (ret < 0) {
- int task_running = atomic_read(&session->task_running);
- mutex_lock(&service.lock);
- vpu_service_dump();
- if (task_running) {
- atomic_set(&session->task_running, 0);
- atomic_sub(task_running, &service.total_running);
- printk("%d task is running but not return, reset hardware...", task_running);
- vpu_reset();
- printk("done\n");
- }
- vpu_service_session_clear(session);
- mutex_unlock(&service.lock);
- return ret;
- }
- }
- mutex_lock(&service.lock);
- reg = list_entry(session->done.next, vpu_reg, session_link);
- return_reg(reg, (u32 __user *)req.req);
- mutex_unlock(&service.lock);
- break;
- }
- default : {
- pr_err("error: unknow vpu service ioctl cmd %x\n", cmd);
- break;
- }
- }
-
- return 0;
-}
-
-static int vpu_service_check_hw(vpu_service_info *p, unsigned long hw_addr)
-{
- int ret = -EINVAL, i = 0;
- volatile u32 *tmp = (volatile u32 *)ioremap_nocache(hw_addr, 0x4);
- u32 enc_id = *tmp;
- enc_id = (enc_id >> 16) & 0xFFFF;
- pr_info("checking hw id %x\n", enc_id);
- p->hw_info = NULL;
- for (i = 0; i < ARRAY_SIZE(vpu_hw_set); i++) {
- if (enc_id == vpu_hw_set[i].hw_id) {
- p->hw_info = &vpu_hw_set[i];
- ret = 0;
- break;
- }
- }
- iounmap((void *)tmp);
- return ret;
-}
-
-static void vpu_service_release_io(void)
-{
- if (dec_dev.hwregs) {
- iounmap((void *)dec_dev.hwregs);
- dec_dev.hwregs = NULL;
- }
- if (dec_dev.iobaseaddr) {
- release_mem_region(dec_dev.iobaseaddr, dec_dev.iosize);
- dec_dev.iobaseaddr = 0;
- dec_dev.iosize = 0;
- }
-
- if (enc_dev.hwregs) {
- iounmap((void *)enc_dev.hwregs);
- enc_dev.hwregs = NULL;
- }
- if (enc_dev.iobaseaddr) {
- release_mem_region(enc_dev.iobaseaddr, enc_dev.iosize);
- enc_dev.iobaseaddr = 0;
- enc_dev.iosize = 0;
- }
-}
-
-static int vpu_service_reserve_io(void)
-{
- unsigned long iobaseaddr;
- unsigned long iosize;
-
- iobaseaddr = dec_dev.iobaseaddr;
- iosize = dec_dev.iosize;
-
- if (!request_mem_region(iobaseaddr, iosize, "vdpu_io")) {
- pr_info("failed to reserve dec HW regs\n");
- return -EBUSY;
- }
-
- dec_dev.hwregs = (volatile u32 *)ioremap_nocache(iobaseaddr, iosize);
-
- if (dec_dev.hwregs == NULL) {
- pr_info("failed to ioremap dec HW regs\n");
- goto err;
- }
-
- iobaseaddr = enc_dev.iobaseaddr;
- iosize = enc_dev.iosize;
-
- if (!request_mem_region(iobaseaddr, iosize, "vepu_io")) {
- pr_info("failed to reserve enc HW regs\n");
- goto err;
- }
-
- enc_dev.hwregs = (volatile u32 *)ioremap_nocache(iobaseaddr, iosize);
-
- if (enc_dev.hwregs == NULL) {
- pr_info("failed to ioremap enc HW regs\n");
- goto err;
- }
-
- return 0;
-
-err:
- return -EBUSY;
-}
-
-static int vpu_service_open(struct inode *inode, struct file *filp)
-{
- vpu_session *session = (vpu_session *)kmalloc(sizeof(vpu_session), GFP_KERNEL);
- if (NULL == session) {
- pr_err("error: unable to allocate memory for vpu_session.");
- return -ENOMEM;
- }
-
- session->type = VPU_TYPE_BUTT;
- session->pid = current->pid;
- INIT_LIST_HEAD(&session->waiting);
- INIT_LIST_HEAD(&session->running);
- INIT_LIST_HEAD(&session->done);
- INIT_LIST_HEAD(&session->list_session);
- init_waitqueue_head(&session->wait);
- atomic_set(&session->task_running, 0);
- mutex_lock(&service.lock);
- list_add_tail(&session->list_session, &service.session);
- filp->private_data = (void *)session;
- mutex_unlock(&service.lock);
-
- pr_debug("dev opened\n");
- return nonseekable_open(inode, filp);
-}
-
-static int vpu_service_release(struct inode *inode, struct file *filp)
-{
- int task_running;
- vpu_session *session = (vpu_session *)filp->private_data;
- if (NULL == session)
- return -EINVAL;
-
- task_running = atomic_read(&session->task_running);
- if (task_running) {
- pr_err("error: vpu_service session %d still has %d task running when closing\n", session->pid, task_running);
- msleep(50);
- }
- wake_up(&session->wait);
-
- mutex_lock(&service.lock);
- /* remove this filp from the asynchronusly notified filp's */
- list_del_init(&session->list_session);
- vpu_service_session_clear(session);
- kfree(session);
- filp->private_data = NULL;
- mutex_unlock(&service.lock);
-
- pr_debug("dev closed\n");
- return 0;
-}
-
-static const struct file_operations vpu_service_fops = {
- .unlocked_ioctl = vpu_service_ioctl,
- .open = vpu_service_open,
- .release = vpu_service_release,
- //.fasync = vpu_service_fasync,
-};
-
-static struct miscdevice vpu_service_misc_device = {
- .minor = MISC_DYNAMIC_MINOR,
- .name = "vpu_service",
- .fops = &vpu_service_fops,
-};
-
-static struct platform_device vpu_service_device = {
- .name = "vpu_service",
- .id = -1,
-};
-
-static int vpu_probe(struct platform_device *pdev)
-{
- int irq;
-
- irq = platform_get_irq_byname(pdev, "irq_vdpu");
- if (irq > 0)
- irq_vdpu = irq;
- irq = platform_get_irq_byname(pdev, "irq_vepu");
- if (irq > 0)
- irq_vepu = irq;
-
- return 0;
-}
-
-static struct platform_driver vpu_driver = {
- .probe = vpu_probe,
- .driver = {
- .name = "vpu",
- .owner = THIS_MODULE,
- },
-};
-
-static struct platform_driver vpu_service_driver = {
- .driver = {
- .name = "vpu_service",
- .owner = THIS_MODULE,
- },
-};
-
-static void get_hw_info(void)
-{
- VPUHwDecConfig_t *dec = &service.dec_config;
- VPUHwEncConfig_t *enc = &service.enc_config;
- u32 configReg = dec_dev.hwregs[VPU_DEC_HWCFG0];
- u32 asicID = dec_dev.hwregs[0];
-
- dec->h264Support = (configReg >> DWL_H264_E) & 0x3U;
- dec->jpegSupport = (configReg >> DWL_JPEG_E) & 0x01U;
- if (dec->jpegSupport && ((configReg >> DWL_PJPEG_E) & 0x01U))
- dec->jpegSupport = JPEG_PROGRESSIVE;
- dec->mpeg4Support = (configReg >> DWL_MPEG4_E) & 0x3U;
- dec->vc1Support = (configReg >> DWL_VC1_E) & 0x3U;
- dec->mpeg2Support = (configReg >> DWL_MPEG2_E) & 0x01U;
- dec->sorensonSparkSupport = (configReg >> DWL_SORENSONSPARK_E) & 0x01U;
- dec->refBufSupport = (configReg >> DWL_REF_BUFF_E) & 0x01U;
- dec->vp6Support = (configReg >> DWL_VP6_E) & 0x01U;
- dec->maxDecPicWidth = configReg & 0x07FFU;
-
- /* 2nd Config register */
- configReg = dec_dev.hwregs[VPU_DEC_HWCFG1];
- if (dec->refBufSupport) {
- if ((configReg >> DWL_REF_BUFF_ILACE_E) & 0x01U)
- dec->refBufSupport |= 2;
- if ((configReg >> DWL_REF_BUFF_DOUBLE_E) & 0x01U)
- dec->refBufSupport |= 4;
- }
- dec->customMpeg4Support = (configReg >> DWL_MPEG4_CUSTOM_E) & 0x01U;
- dec->vp7Support = (configReg >> DWL_VP7_E) & 0x01U;
- dec->vp8Support = (configReg >> DWL_VP8_E) & 0x01U;
- dec->avsSupport = (configReg >> DWL_AVS_E) & 0x01U;
-
- /* JPEG xtensions */
- if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U)) {
- dec->jpegESupport = (configReg >> DWL_JPEG_EXT_E) & 0x01U;
- } else {
- dec->jpegESupport = JPEG_EXT_NOT_SUPPORTED;
- }
-
- if (((asicID >> 16) >= 0x9170U) || ((asicID >> 16) == 0x6731U) ) {
- dec->rvSupport = (configReg >> DWL_RV_E) & 0x03U;
- } else {
- dec->rvSupport = RV_NOT_SUPPORTED;
- }
-
- dec->mvcSupport = (configReg >> DWL_MVC_E) & 0x03U;
-
- if (dec->refBufSupport && (asicID >> 16) == 0x6731U ) {
- dec->refBufSupport |= 8; /* enable HW support for offset */
- }
-
- {
- VPUHwFuseStatus_t hwFuseSts;
- /* Decoder fuse configuration */
- u32 fuseReg = dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];
-
- hwFuseSts.h264SupportFuse = (fuseReg >> DWL_H264_FUSE_E) & 0x01U;
- hwFuseSts.mpeg4SupportFuse = (fuseReg >> DWL_MPEG4_FUSE_E) & 0x01U;
- hwFuseSts.mpeg2SupportFuse = (fuseReg >> DWL_MPEG2_FUSE_E) & 0x01U;
- hwFuseSts.sorensonSparkSupportFuse = (fuseReg >> DWL_SORENSONSPARK_FUSE_E) & 0x01U;
- hwFuseSts.jpegSupportFuse = (fuseReg >> DWL_JPEG_FUSE_E) & 0x01U;
- hwFuseSts.vp6SupportFuse = (fuseReg >> DWL_VP6_FUSE_E) & 0x01U;
- hwFuseSts.vc1SupportFuse = (fuseReg >> DWL_VC1_FUSE_E) & 0x01U;
- hwFuseSts.jpegProgSupportFuse = (fuseReg >> DWL_PJPEG_FUSE_E) & 0x01U;
- hwFuseSts.rvSupportFuse = (fuseReg >> DWL_RV_FUSE_E) & 0x01U;
- hwFuseSts.avsSupportFuse = (fuseReg >> DWL_AVS_FUSE_E) & 0x01U;
- hwFuseSts.vp7SupportFuse = (fuseReg >> DWL_VP7_FUSE_E) & 0x01U;
- hwFuseSts.vp8SupportFuse = (fuseReg >> DWL_VP8_FUSE_E) & 0x01U;
- hwFuseSts.customMpeg4SupportFuse = (fuseReg >> DWL_CUSTOM_MPEG4_FUSE_E) & 0x01U;
- hwFuseSts.mvcSupportFuse = (fuseReg >> DWL_MVC_FUSE_E) & 0x01U;
-
- /* check max. decoder output width */
-
- if (fuseReg & 0x8000U)
- hwFuseSts.maxDecPicWidthFuse = 1920;
- else if (fuseReg & 0x4000U)
- hwFuseSts.maxDecPicWidthFuse = 1280;
- else if (fuseReg & 0x2000U)
- hwFuseSts.maxDecPicWidthFuse = 720;
- else if (fuseReg & 0x1000U)
- hwFuseSts.maxDecPicWidthFuse = 352;
- else /* remove warning */
- hwFuseSts.maxDecPicWidthFuse = 352;
-
- hwFuseSts.refBufSupportFuse = (fuseReg >> DWL_REF_BUFF_FUSE_E) & 0x01U;
-
- /* Pp configuration */
- configReg = dec_dev.hwregs[VPU_PP_HW_SYNTH_CFG];
-
- if ((configReg >> DWL_PP_E) & 0x01U) {
- dec->ppSupport = 1;
- dec->maxPpOutPicWidth = configReg & 0x07FFU;
- /*pHwCfg->ppConfig = (configReg >> DWL_CFG_E) & 0x0FU; */
- dec->ppConfig = configReg;
- } else {
- dec->ppSupport = 0;
- dec->maxPpOutPicWidth = 0;
- dec->ppConfig = 0;
- }
-
- /* check the HW versio */
- if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U)) {
- /* Pp configuration */
- configReg = dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];
-
- if ((configReg >> DWL_PP_E) & 0x01U) {
- /* Pp fuse configuration */
- u32 fuseRegPp = dec_dev.hwregs[VPU_PP_HW_FUSE_CFG];
-
- if ((fuseRegPp >> DWL_PP_FUSE_E) & 0x01U) {
- hwFuseSts.ppSupportFuse = 1;
- /* check max. pp output width */
- if (fuseRegPp & 0x8000U) hwFuseSts.maxPpOutPicWidthFuse = 1920;
- else if (fuseRegPp & 0x4000U) hwFuseSts.maxPpOutPicWidthFuse = 1280;
- else if (fuseRegPp & 0x2000U) hwFuseSts.maxPpOutPicWidthFuse = 720;
- else if (fuseRegPp & 0x1000U) hwFuseSts.maxPpOutPicWidthFuse = 352;
- else hwFuseSts.maxPpOutPicWidthFuse = 352;
- hwFuseSts.ppConfigFuse = fuseRegPp;
- } else {
- hwFuseSts.ppSupportFuse = 0;
- hwFuseSts.maxPpOutPicWidthFuse = 0;
- hwFuseSts.ppConfigFuse = 0;
- }
- } else {
- hwFuseSts.ppSupportFuse = 0;
- hwFuseSts.maxPpOutPicWidthFuse = 0;
- hwFuseSts.ppConfigFuse = 0;
- }
-
- if (dec->maxDecPicWidth > hwFuseSts.maxDecPicWidthFuse)
- dec->maxDecPicWidth = hwFuseSts.maxDecPicWidthFuse;
- if (dec->maxPpOutPicWidth > hwFuseSts.maxPpOutPicWidthFuse)
- dec->maxPpOutPicWidth = hwFuseSts.maxPpOutPicWidthFuse;
- if (!hwFuseSts.h264SupportFuse) dec->h264Support = H264_NOT_SUPPORTED;
- if (!hwFuseSts.mpeg4SupportFuse) dec->mpeg4Support = MPEG4_NOT_SUPPORTED;
- if (!hwFuseSts.customMpeg4SupportFuse) dec->customMpeg4Support = MPEG4_CUSTOM_NOT_SUPPORTED;
- if (!hwFuseSts.jpegSupportFuse) dec->jpegSupport = JPEG_NOT_SUPPORTED;
- if ((dec->jpegSupport == JPEG_PROGRESSIVE) && !hwFuseSts.jpegProgSupportFuse)
- dec->jpegSupport = JPEG_BASELINE;
- if (!hwFuseSts.mpeg2SupportFuse) dec->mpeg2Support = MPEG2_NOT_SUPPORTED;
- if (!hwFuseSts.vc1SupportFuse) dec->vc1Support = VC1_NOT_SUPPORTED;
- if (!hwFuseSts.vp6SupportFuse) dec->vp6Support = VP6_NOT_SUPPORTED;
- if (!hwFuseSts.vp7SupportFuse) dec->vp7Support = VP7_NOT_SUPPORTED;
- if (!hwFuseSts.vp8SupportFuse) dec->vp8Support = VP8_NOT_SUPPORTED;
- if (!hwFuseSts.ppSupportFuse) dec->ppSupport = PP_NOT_SUPPORTED;
-
- /* check the pp config vs fuse status */
- if ((dec->ppConfig & 0xFC000000) && ((hwFuseSts.ppConfigFuse & 0xF0000000) >> 5)) {
- u32 deInterlace = ((dec->ppConfig & PP_DEINTERLACING) >> 25);
- u32 alphaBlend = ((dec->ppConfig & PP_ALPHA_BLENDING) >> 24);
- u32 deInterlaceFuse = (((hwFuseSts.ppConfigFuse >> 5) & PP_DEINTERLACING) >> 25);
- u32 alphaBlendFuse = (((hwFuseSts.ppConfigFuse >> 5) & PP_ALPHA_BLENDING) >> 24);
-
- if (deInterlace && !deInterlaceFuse) dec->ppConfig &= 0xFD000000;
- if (alphaBlend && !alphaBlendFuse) dec->ppConfig &= 0xFE000000;
- }
- if (!hwFuseSts.sorensonSparkSupportFuse) dec->sorensonSparkSupport = SORENSON_SPARK_NOT_SUPPORTED;
- if (!hwFuseSts.refBufSupportFuse) dec->refBufSupport = REF_BUF_NOT_SUPPORTED;
- if (!hwFuseSts.rvSupportFuse) dec->rvSupport = RV_NOT_SUPPORTED;
- if (!hwFuseSts.avsSupportFuse) dec->avsSupport = AVS_NOT_SUPPORTED;
- if (!hwFuseSts.mvcSupportFuse) dec->mvcSupport = MVC_NOT_SUPPORTED;
- }
- }
- configReg = enc_dev.hwregs[63];
- enc->maxEncodedWidth = configReg & ((1 << 11) - 1);
- enc->h264Enabled = (configReg >> 27) & 1;
- enc->mpeg4Enabled = (configReg >> 26) & 1;
- enc->jpegEnabled = (configReg >> 25) & 1;
- enc->vsEnabled = (configReg >> 24) & 1;
- enc->rgbEnabled = (configReg >> 28) & 1;
- //enc->busType = (configReg >> 20) & 15;
- //enc->synthesisLanguage = (configReg >> 16) & 15;
- //enc->busWidth = (configReg >> 12) & 15;
- enc->reg_size = service.reg_size;
- enc->reserv[0] = enc->reserv[1] = 0;
-
- service.auto_freq = soc_is_rk2928g() || soc_is_rk2928l() || soc_is_rk2926();
- if (service.auto_freq) {
- printk("vpu_service set to auto frequency mode\n");
- atomic_set(&service.freq_status, VPU_FREQ_BUT);
- }
- service.bug_dec_addr = cpu_is_rk30xx();
- //printk("cpu 3066b bug %d\n", service.bug_dec_addr);
-}
-
-static irqreturn_t vdpu_irq(int irq, void *dev_id)
-{
- vpu_device *dev = (vpu_device *) dev_id;
- u32 irq_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);
-
- pr_debug("vdpu_irq\n");
-
- if (irq_status & DEC_INTERRUPT_BIT) {
- pr_debug("vdpu_isr dec %x\n", irq_status);
- if ((irq_status & 0x40001) == 0x40001)
- {
- do {
- irq_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);
- } while ((irq_status & 0x40001) == 0x40001);
- }
- /* clear dec IRQ */
- writel(irq_status & (~DEC_INTERRUPT_BIT|DEC_BUFFER_EMPTY_BIT), dev->hwregs + DEC_INTERRUPT_REGISTER);
- atomic_add(1, &dev->irq_count_codec);
- }
-
- irq_status = readl(dev->hwregs + PP_INTERRUPT_REGISTER);
- if (irq_status & PP_INTERRUPT_BIT) {
- pr_debug("vdpu_isr pp %x\n", irq_status);
- /* clear pp IRQ */
- writel(irq_status & (~DEC_INTERRUPT_BIT), dev->hwregs + PP_INTERRUPT_REGISTER);
- atomic_add(1, &dev->irq_count_pp);
- }
-
- return IRQ_WAKE_THREAD;
-}
-
-static irqreturn_t vdpu_isr(int irq, void *dev_id)
-{
- vpu_device *dev = (vpu_device *) dev_id;
-
- mutex_lock(&service.lock);
- if (atomic_read(&dev->irq_count_codec)) {
-#if VPU_SERVICE_SHOW_TIME
- do_gettimeofday(&dec_end);
- printk("dec task: %ld ms\n",
- (dec_end.tv_sec - dec_start.tv_sec) * 1000 +
- (dec_end.tv_usec - dec_start.tv_usec) / 1000);
-#endif
- atomic_sub(1, &dev->irq_count_codec);
- if (NULL == service.reg_codec) {
- pr_err("error: dec isr with no task waiting\n");
- } else {
- reg_from_run_to_done(service.reg_codec);
- }
- }
-
- if (atomic_read(&dev->irq_count_pp)) {
-
-#if VPU_SERVICE_SHOW_TIME
- do_gettimeofday(&pp_end);
- printk("pp task: %ld ms\n",
- (pp_end.tv_sec - pp_start.tv_sec) * 1000 +
- (pp_end.tv_usec - pp_start.tv_usec) / 1000);
-#endif
-
- atomic_sub(1, &dev->irq_count_pp);
- if (NULL == service.reg_pproc) {
- pr_err("error: pp isr with no task waiting\n");
- } else {
- reg_from_run_to_done(service.reg_pproc);
- }
- }
- try_set_reg();
- mutex_unlock(&service.lock);
- return IRQ_HANDLED;
-}
-
-static irqreturn_t vepu_irq(int irq, void *dev_id)
-{
- struct vpu_device *dev = (struct vpu_device *) dev_id;
- u32 irq_status = readl(dev->hwregs + ENC_INTERRUPT_REGISTER);
-
- pr_debug("vepu_irq irq status %x\n", irq_status);
-
-#if VPU_SERVICE_SHOW_TIME
- do_gettimeofday(&enc_end);
- printk("enc task: %ld ms\n",
- (enc_end.tv_sec - enc_start.tv_sec) * 1000 +
- (enc_end.tv_usec - enc_start.tv_usec) / 1000);
-#endif
-
- if (likely(irq_status & ENC_INTERRUPT_BIT)) {
- /* clear enc IRQ */
- writel(irq_status & (~ENC_INTERRUPT_BIT), dev->hwregs + ENC_INTERRUPT_REGISTER);
- atomic_add(1, &dev->irq_count_codec);
- }
-
- return IRQ_WAKE_THREAD;
-}
-
-static irqreturn_t vepu_isr(int irq, void *dev_id)
-{
- struct vpu_device *dev = (struct vpu_device *) dev_id;
-
- mutex_lock(&service.lock);
- if (atomic_read(&dev->irq_count_codec)) {
- atomic_sub(1, &dev->irq_count_codec);
- if (NULL == service.reg_codec) {
- pr_err("error: enc isr with no task waiting\n");
- } else {
- reg_from_run_to_done(service.reg_codec);
- }
- }
- try_set_reg();
- mutex_unlock(&service.lock);
- return IRQ_HANDLED;
-}
-
-#ifdef CONFIG_PROC_FS
-static int __init vpu_service_proc_init(void);
-#else
-static inline int vpu_service_proc_init(void) { return 0; }
-#endif
-
-static int __init vpu_service_init(void)
-{
- int ret;
-
- platform_driver_register(&vpu_driver);
- pr_debug("baseaddr = 0x%08x vdpu irq = %d vepu irq = %d\n", VCODEC_PHYS, irq_vdpu, irq_vepu);
-
- wake_lock_init(&service.wake_lock, WAKE_LOCK_SUSPEND, "vpu");
- INIT_LIST_HEAD(&service.waiting);
- INIT_LIST_HEAD(&service.running);
- INIT_LIST_HEAD(&service.done);
- INIT_LIST_HEAD(&service.session);
- mutex_init(&service.lock);
- service.reg_codec = NULL;
- service.reg_pproc = NULL;
- atomic_set(&service.total_running, 0);
- service.enabled = false;
-
- vpu_get_clk();
-
- INIT_DELAYED_WORK(&service.power_off_work, vpu_power_off_work);
-
- vpu_service_power_on();
- ret = vpu_service_check_hw(&service, VCODEC_PHYS);
- if (ret < 0) {
- pr_err("error: hw info check faild\n");
- goto err_hw_id_check;
- }
-
- atomic_set(&dec_dev.irq_count_codec, 0);
- atomic_set(&dec_dev.irq_count_pp, 0);
- dec_dev.iobaseaddr = service.hw_info->hw_addr + service.hw_info->dec_offset;
- dec_dev.iosize = service.hw_info->dec_io_size;
- atomic_set(&enc_dev.irq_count_codec, 0);
- atomic_set(&enc_dev.irq_count_pp, 0);
- enc_dev.iobaseaddr = service.hw_info->hw_addr + service.hw_info->enc_offset;
- enc_dev.iosize = service.hw_info->enc_io_size;;
- service.reg_size = max(dec_dev.iosize, enc_dev.iosize);
-
- ret = vpu_service_reserve_io();
- if (ret < 0) {
- pr_err("error: reserve io failed\n");
- goto err_reserve_io;
- }
-
- /* get the IRQ line */
- ret = request_threaded_irq(irq_vdpu, vdpu_irq, vdpu_isr, 0, "vdpu", (void *)&dec_dev);
- if (ret) {
- pr_err("error: can't request vdpu irq %d\n", irq_vdpu);
- goto err_req_vdpu_irq;
- }
-
- ret = request_threaded_irq(irq_vepu, vepu_irq, vepu_isr, 0, "vepu", (void *)&enc_dev);
- if (ret) {
- pr_err("error: can't request vepu irq %d\n", irq_vepu);
- goto err_req_vepu_irq;
- }
-
- ret = misc_register(&vpu_service_misc_device);
- if (ret) {
- pr_err("error: misc_register failed\n");
- goto err_register;
- }
-
- platform_device_register(&vpu_service_device);
- platform_driver_probe(&vpu_service_driver, NULL);
- get_hw_info();
- vpu_service_power_off();
- pr_info("init success\n");
-
- vpu_service_proc_init();
- return 0;
-
-err_register:
- free_irq(irq_vepu, (void *)&enc_dev);
-err_req_vepu_irq:
- free_irq(irq_vdpu, (void *)&dec_dev);
-err_req_vdpu_irq:
- pr_info("init failed\n");
-err_reserve_io:
- vpu_service_release_io();
-err_hw_id_check:
- vpu_service_power_off();
- vpu_put_clk();
- wake_lock_destroy(&service.wake_lock);
- pr_info("init failed\n");
- return ret;
-}
-
-#ifdef CONFIG_PROC_FS
-static void __exit vpu_service_proc_release(void);
-#else
-#define vpu_service_proc_release() do {} while (0)
-#endif
-
-static void __exit vpu_service_exit(void)
-{
- vpu_service_proc_release();
- vpu_service_power_off();
- platform_device_unregister(&vpu_service_device);
- platform_driver_unregister(&vpu_service_driver);
- misc_deregister(&vpu_service_misc_device);
- free_irq(irq_vepu, (void *)&enc_dev);
- free_irq(irq_vdpu, (void *)&dec_dev);
- vpu_service_release_io();
- vpu_put_clk();
- wake_lock_destroy(&service.wake_lock);
-}
-
-module_init(vpu_service_init);
-module_exit(vpu_service_exit);
-
-#ifdef CONFIG_PROC_FS
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-
-static int proc_vpu_service_show(struct seq_file *s, void *v)
-{
- unsigned int i, n;
- vpu_reg *reg, *reg_tmp;
- vpu_session *session, *session_tmp;
-
- mutex_lock(&service.lock);
- vpu_service_power_on();
- seq_printf(s, "\nENC Registers:\n");
- n = enc_dev.iosize >> 2;
- for (i = 0; i < n; i++) {
- seq_printf(s, "\tswreg%d = %08X\n", i, readl(enc_dev.hwregs + i));
- }
- seq_printf(s, "\nDEC Registers:\n");
- n = dec_dev.iosize >> 2;
- for (i = 0; i < n; i++) {
- seq_printf(s, "\tswreg%d = %08X\n", i, readl(dec_dev.hwregs + i));
- }
-
- seq_printf(s, "\nvpu service status:\n");
- list_for_each_entry_safe(session, session_tmp, &service.session, list_session) {
- seq_printf(s, "session pid %d type %d:\n", session->pid, session->type);
- //seq_printf(s, "waiting reg set %d\n");
- list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {
- seq_printf(s, "waiting register set\n");
- }
- list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {
- seq_printf(s, "running register set\n");
- }
- list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {
- seq_printf(s, "done register set\n");
- }
- }
- mutex_unlock(&service.lock);
-
- return 0;
-}
-
-static int proc_vpu_service_open(struct inode *inode, struct file *file)
-{
- return single_open(file, proc_vpu_service_show, NULL);
-}
-
-static const struct file_operations proc_vpu_service_fops = {
- .open = proc_vpu_service_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-static int __init vpu_service_proc_init(void)
-{
- proc_create("vpu_service", 0, NULL, &proc_vpu_service_fops);
- return 0;
-
-}
-static void __exit vpu_service_proc_release(void)
-{
- remove_proc_entry("vpu_service", NULL);
-}
-#endif /* CONFIG_PROC_FS */
-
+++ /dev/null
-/* -*- linux-c -*-
- *
- * $Id: sysrq.c,v 1.15 1998/08/23 14:56:41 mj Exp $
- *
- * Linux Magic System Request Key Hacks
- *
- * (c) 1997 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
- * based on ideas by Pavel Machek <pavel@atrey.karlin.mff.cuni.cz>
- *
- * (c) 2000 Crutcher Dunnavant <crutcher+kernel@datastacks.com>
- * overhauled to use key registration
- * based upon discusions in irc://irc.openprojects.net/#kernelnewbies
- */
-
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/mm.h>
-#include <linux/fs.h>
-#include <linux/tty.h>
-#include <linux/mount.h>
-#include <linux/kdev_t.h>
-#include <linux/major.h>
-#include <linux/reboot.h>
-#include <linux/sysrq.h>
-#include <linux/kbd_kern.h>
-#include <linux/proc_fs.h>
-#include <linux/nmi.h>
-#include <linux/quotaops.h>
-#include <linux/perf_event.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/suspend.h>
-#include <linux/writeback.h>
-#include <linux/buffer_head.h> /* for fsync_bdev() */
-#include <linux/swap.h>
-#include <linux/spinlock.h>
-#include <linux/vt_kern.h>
-#include <linux/workqueue.h>
-#include <linux/hrtimer.h>
-#include <linux/oom.h>
-#include <linux/version.h>
-
-#include <asm/ptrace.h>
-#include <asm/irq_regs.h>
-
-#include <linux/io.h>
-#include <mach/gpio.h>
-#include <mach/rk29_iomap.h>
-#include <mach/iomux.h>
-
-#include <asm/gpio.h>
-
-#define GPIO_SWPORTA_DR 0x00
-#define GPIO_SWPORTA_DDR 0x04
-
-#define GPIO_SWPORTB_DR 0x0c
-#define GPIO_SWPORTB_DDR 0x10
-
-#define GPIO_SWPORTC_DR 0x18
-#define GPIO_SWPORTC_DDR 0x1c
-
-#define GPIO_SWPORTD_DR 0x24
-#define GPIO_SWPORTD_DDR 0x28
-
-#define RK_SYSRQ_GPIO_RES(name,resn0,resn1,oft0,oft1,oft2,oft3) \
- { \
- .res_name = name, \
- .resmap[0] = { \
- .id = 0, \
- .resname = resn0, \
- }, \
- .resmap[1] = { \
- .id = 1, \
- .resname = resn1, \
- }, \
- .res_off = {oft0,oft1,oft2,oft3,0xffff}, \
- }
-
-#define RK_SYSRQ_GPIO(name,base) \
- { \
- .rk_sysrq_gpio_name = name, \
- .regbase = (const unsigned char __iomem *) base, \
- .res_table = rk_sysrq_gpio_printres_table,\
- .res_table_count = ARRAY_SIZE(rk_sysrq_gpio_printres_table), \
- }
-
-#define RK_SYSRQ_IOMUX_RES(offt,start,mask,desc0,desc1,desc2,desc3) \
- { \
- .off = offt, \
- .reg_description[0] = desc0, \
- .reg_description[1] = desc1, \
- .reg_description[2] = desc2, \
- .reg_description[3] = desc3, \
- .start_bit = start,\
- .mask_bit = mask, \
- }
-#define RK_SYSRQ_IOMUX_CFG(name,msg,regbase,table) \
- { \
- .reg_name = name, \
- .message = msg, \
- .reg_base = (const unsigned char __iomem *) regbase, \
- .regres_table = rk_sysrq_iomux_res_gpio##table, \
- .res_table_count = ARRAY_SIZE(rk_sysrq_iomux_res_gpio##table),\
- }
-struct res_map
-{
- const int id;
- const char *resname;
-};
-struct rk_sysrq_gpio_printres
-{
- const char *res_name;
- struct res_map resmap[2];
- unsigned int res_off[5];
-
-};
-struct rk_sysrq_gpio
-{
- const char *rk_sysrq_gpio_name;
- const unsigned char __iomem *regbase;
- struct rk_sysrq_gpio_printres *res_table;
- unsigned int res_table_count;
-};
-struct rk_sysrq_iomux
-{
- const char *reg_name;
- const char *message;
- const unsigned char __iomem *reg_base;
- struct rk_sysrq_iomux_regres *regres_table;
- unsigned int res_table_count;
-};
-struct rk_sysrq_iomux_regres
-{
- const unsigned short off;
- const char *reg_description[4];
- const unsigned char start_bit;
- const unsigned short mask_bit;
-
-};
-
-struct rk_sysrq_iomux_regres rk_sysrq_iomux_res_gpio0l[] = {
- RK_SYSRQ_IOMUX_RES(0x48,30,3,"GPIO0_B[7]","ebc_gdoe","smc_oe_n",NULL),
- RK_SYSRQ_IOMUX_RES(0x48,28,3,"GPIO0_B[6]","ebc_sdshr","smc_bls_n_1","host_int"),
- RK_SYSRQ_IOMUX_RES(0x48,26,3,"GPIO0_B[5]","ebc_vcom","smc_bls_n_0",NULL),
- RK_SYSRQ_IOMUX_RES(0x48,24,3,"GPIO0_B[4]","ebc_border1","smc_we_n",NULL),
- RK_SYSRQ_IOMUX_RES(0x48,22,3,"GPIO0_B[3]","ebc_border0","smc_addr[3]","host_data[3]"),
- RK_SYSRQ_IOMUX_RES(0x48,20,3,"GPIO0_B[2]","ebc_sdce2","smc_addr[2]","host_data[2]"),
- RK_SYSRQ_IOMUX_RES(0x48,18,3,"GPIO0_B[1]","ebc_sdce1","smc_addr[1]","host_data[1]"),
- RK_SYSRQ_IOMUX_RES(0x48,16,3,"GPIO0_B[0]","ebc_sdce0","smc_addr[0]","host_data[0]"),
-
- RK_SYSRQ_IOMUX_RES(0x48,14,3,"GPIO0_A[7]","mii_mdclk",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x48,12,3,"GPIO0_A[6]","mii_md",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x48,10,3,"GPIO0_A[5]","flash_dqs",NULL,NULL),
-};
-struct rk_sysrq_iomux_regres rk_sysrq_iomux_res_gpio0h[] = {
- RK_SYSRQ_IOMUX_RES(0x4c,30,3,"GPIO0_D[7]","flash_csn6",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x4c,28,3,"GPIO0_D[6]","flash_csn5",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x4c,26,3,"GPIO0_D[5]","flash_csn4",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x4c,24,3,"GPIO0_D[4]","flash_csn3",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x4c,22,3,"GPIO0_D[3]","flash_csn2",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x4c,20,3,"GPIO0_D[2]","flash_csn1",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x4c,18,3,"GPIO0_D[1]","ebc_gdclk","smc_addr[4]","host_data[4]"),
- RK_SYSRQ_IOMUX_RES(0x4c,16,3,"GPIO0_D[0]","ebc_sdoe","smc_adv_n",""),
-
- RK_SYSRQ_IOMUX_RES(0x4c,14,3,"GPIO0_C[7]","ebc_sdce5","smc_data15",NULL),
- RK_SYSRQ_IOMUX_RES(0x4c,12,3,"GPIO0_C[6]","ebc_sdce4","smc_data14",NULL),
- RK_SYSRQ_IOMUX_RES(0x4c,10,3,"GPIO0_C[5]","ebc_sdce3","smc_data13",NULL),
- RK_SYSRQ_IOMUX_RES(0x4c,8,3,"GPIO0_C[4]","ebc_gdpwr2","smc_data12",NULL),
- RK_SYSRQ_IOMUX_RES(0x4c,6,3,"GPIO0_C[3]","ebc_gdpwr1","smc_data11",NULL),
- RK_SYSRQ_IOMUX_RES(0x4c,4,3,"GPIO0_C[2]","ebc_gdpwr0","smc_data10",NULL),
- RK_SYSRQ_IOMUX_RES(0x4c,2,3,"GPIO0_C[1]","ebc_gdrl","smc_data9",NULL),
- RK_SYSRQ_IOMUX_RES(0x4c,0,3,"GPIO0_C[0]","ebc_gdsp","smc_data8",NULL),
-};
-struct rk_sysrq_iomux_regres rk_sysrq_iomux_res_gpio1l[] = {
- RK_SYSRQ_IOMUX_RES(0x50,30,3,"GPIO1_B[7]","uart0_sout",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x50,28,3,"GPIO1_B[6]","uart0_sin",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x50,26,3,"GPIO1_B[5]","pwm0",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x50,24,3,"GPIO1_B[4]","vip_clkout",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x50,22,3,"GPIO1_B[3]","vip_data[3]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x50,20,3,"GPIO1_B[2]","vip_data[2]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x50,18,3,"GPIO1_B[1]","vip_data[1]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x50,16,3,"GPIO1_B[0]","vip_data[0]",NULL,NULL),
-
- RK_SYSRQ_IOMUX_RES(0x50,14,3,"GPIO1_A[7]","i2c1_scl",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x50,12,3,"GPIO1_A[6]","i2c1_sda",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x50,10,3,"GPIO1_A[5]","emmc_pwr_en","pwm3",NULL),
- RK_SYSRQ_IOMUX_RES(0x50,8,3,"GPIO1_A[4]","emmc_write_prt","spi0_csn1",NULL),
- RK_SYSRQ_IOMUX_RES(0x50,6,3,"GPIO1_A[3]","emmc_detect_n","spi1_csn1",NULL),
- RK_SYSRQ_IOMUX_RES(0x50,4,3,"GPIO1_A[2]","smc_csn1",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x50,2,3,"GPIO1_A[1]","smc_csn0",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x50,0,3,"GPIO1_A[0]","flash_cs7","mddr_tq",NULL),
-
-};
-struct rk_sysrq_iomux_regres rk_sysrq_iomux_res_gpio1h[] = {
- RK_SYSRQ_IOMUX_RES(0x54,30,3,"GPIO1_D[7]","sdmmc0_data[5]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x54,28,3,"GPIO1_D[6]","sdmmc0_data[4]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x54,26,3,"GPIO1_D[5]","sdmmc0_data[3]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x54,24,3,"GPIO1_D[4]","sdmmc0_data[2]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x54,22,3,"GPIO1_D[3]","sdmmc0_data[1]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x54,20,3,"GPIO1_D[2]","sdmmc0_data[0]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x54,18,3,"GPIO1_D[1]","sdmmc0_cmd",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x54,16,3,"GPIO1_D[0]","sdmmc0_clkout",NULL,NULL),
-
- RK_SYSRQ_IOMUX_RES(0x54,14,3,"GPIO1_C[7]","sdmmc1_clkout",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x54,12,3,"GPIO1_C[6]","sdmmc1_data[3]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x54,10,3,"GPIO1_C[5]","sdmmc1_data[2]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x54,8,3,"GPIO1_C[4]","sdmmc1_data[1]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x54,6,3,"GPIO1_C[3]","sdmmc1_data[0]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x54,4,3,"GPIO1_C[2]","sdmmc1_cmd",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x54,2,3,"GPIO1_C[1]","uart0_rts_n","sdmmc1_write_prt",NULL),
- RK_SYSRQ_IOMUX_RES(0x54,0,3,"GPIO1_C[0]","uart0_cts_n","sdmmc1_detect_n",NULL),
-};
-struct rk_sysrq_iomux_regres rk_sysrq_iomux_res_gpio2l[] = {
- RK_SYSRQ_IOMUX_RES(0x58,30,3,"GPIO2_B[7]","i2c0_scl",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x58,28,3,"GPIO2_B[6]","i2c0_sda",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x58,26,3,"GPIO2_B[5]","uart3_rts_n","i2c3_scl",NULL),
- RK_SYSRQ_IOMUX_RES(0x58,24,3,"GPIO2_B[4]","uart3_cts_n","i2c3_sda",NULL),
- RK_SYSRQ_IOMUX_RES(0x58,22,3,"GPIO2_B[3]","uart3_sout",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x58,20,3,"GPIO2_B[2]","uart3_sin",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x58,18,3,"GPIO2_B[1]","uart2_sout",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x58,16,3,"GPIO2_B[0]","uart2_sin",NULL,NULL),
-
- RK_SYSRQ_IOMUX_RES(0x58,14,3,"GPIO2_A[7]","uart2_rts_n",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x58,12,3,"GPIO2_A[6]","uart2_cts_n",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x58,10,3,"GPIO2_A[5]","uart1_sout",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x58,8,3,"GPIO2_A[4]","uart1_sin",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x58,6,3,"GPIO2_A[3]","sdmmc0_write_prt","pwm2","uart1_sir_out_n"),
- RK_SYSRQ_IOMUX_RES(0x58,4,3,"GPIO2_A[2]","sdmmc0_detect_n",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x58,2,3,"GPIO2_A[1]","sdmmc0_data[7]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x58,0,3,"GPIO2_A[0]","sdmmc0_data[6]",NULL,NULL),
-};
-struct rk_sysrq_iomux_regres rk_sysrq_iomux_res_gpio2h[] = {
- RK_SYSRQ_IOMUX_RES(0x5c,30,3,"GPIO2_D[7]","i2s0_sdo3","mii_txd[3]",NULL),
- RK_SYSRQ_IOMUX_RES(0x5c,28,3,"GPIO2_D[6]","i2s0_sdo2","mii_txd[2]",NULL),
- RK_SYSRQ_IOMUX_RES(0x5c,26,3,"GPIO2_D[5]","i2s0_sdo1","mii_rxd[3]",NULL),
- RK_SYSRQ_IOMUX_RES(0x5c,24,3,"GPIO2_D[4]","i2s0_sdo0","mii_rxd[2]",NULL),
- RK_SYSRQ_IOMUX_RES(0x5c,22,3,"GPIO2_D[3]","i2s0_sdi","mii_col",NULL),
- RK_SYSRQ_IOMUX_RES(0x5c,20,3,"GPIO2_D[2]","i2s0_lrck_rx","mii_tx_err",NULL),
- RK_SYSRQ_IOMUX_RES(0x5c,18,3,"GPIO2_D[1]","i2s0_sclk","mii_crs",NULL),
- RK_SYSRQ_IOMUX_RES(0x5c,16,3,"GPIO2_D[0]","i2s0_clk","mii_rx_clkin",NULL),
-
- RK_SYSRQ_IOMUX_RES(0x5c,14,3,"GPIO2_C[7]","spi1_rxd",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x5c,12,3,"GPIO2_C[6]","spi1_txd",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x5c,10,3,"GPIO2_C[5]","spi1_csn0",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x5c,8,3,"GPIO2_C[4]","spi1_clk",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x5c,6,3,"GPIO2_C[3]","spi0_rxd",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x5c,4,3,"GPIO2_C[2]","spi0_txd",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x5c,2,3,"GPIO2_C[1]","spi0_csn0",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x5c,0,3,"GPIO2_C[0]","spi0_clk",NULL,NULL),
-};
-struct rk_sysrq_iomux_regres rk_sysrq_iomux_res_gpio3l[] = {
- RK_SYSRQ_IOMUX_RES(0x60,30,3,"GPIO3_B[7]","emmc_data[5]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x60,28,3,"GPIO3_B[6]","emmc_data[4]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x60,26,3,"GPIO3_B[5]","emmc_data[3]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x60,24,3,"GPIO3_B[4]","emmc_data[2]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x60,22,3,"GPIO3_B[3]","emmc_data[1]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x60,20,3,"GPIO3_B[2]","emmc_data[0]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x60,18,3,"GPIO3_B[1]","emmc_cmd",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x60,16,3,"GPIO3_B[0]","emmc_clkout",NULL,NULL),
-
- RK_SYSRQ_IOMUX_RES(0x60,14,3,"GPIO3_A[7]","smc_addr[15]","host_data[15]",NULL),
- RK_SYSRQ_IOMUX_RES(0x60,12,3,"GPIO3_A[6]","smc_addr[14]","host_data[14]",NULL),
- RK_SYSRQ_IOMUX_RES(0x60,10,3,"GPIO3_A[5]","i2s1_lrck_tx",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x60,8,3,"GPIO3_A[4]","i2s1_sdo",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x60,6,3,"GPIO3_A[3]","i2s1_sdi",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x60,4,3,"GPIO3_A[2]","i2s1_lrck_rx",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x60,2,3,"GPIO3_A[1]","i2s1_sclk",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x60,0,3,"GPIO3_A[0]","i2s1_clk",NULL,NULL),
-};
-struct rk_sysrq_iomux_regres rk_sysrq_iomux_res_gpio3h[] = {
- RK_SYSRQ_IOMUX_RES(0x64,30,3,"GPIO3_D[7]","smc_addr[9]","host_data[9]",NULL),
- RK_SYSRQ_IOMUX_RES(0x64,28,3,"GPIO3_D[6]","smc_addr[8]","host_data[8]",NULL),
- RK_SYSRQ_IOMUX_RES(0x64,26,3,"GPIO3_D[5]","smc_addr[7]","host_data[7]",NULL),
- RK_SYSRQ_IOMUX_RES(0x64,24,3,"GPIO3_D[4]","host_wrn",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x64,22,3,"GPIO3_D[3]","host_rdn",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x64,20,3,"GPIO3_D[2]","host_csn",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x64,18,3,"GPIO3_D[1]","smc_addr[19]","host_addr[1]",NULL),
- RK_SYSRQ_IOMUX_RES(0x64,16,3,"GPIO3_D[0]","smc_addr[18]","host_addr[0]",NULL),
-
- RK_SYSRQ_IOMUX_RES(0x64,14,3,"GPIO3_C[7]","smc_addr[17]","host_data[17]",NULL),
- RK_SYSRQ_IOMUX_RES(0x64,12,3,"GPIO3_C[6]","smc_addr[16]","host_data[16]",NULL),
- RK_SYSRQ_IOMUX_RES(0x64,10,3,"GPIO3_C[5]","smc_addr[12]","host_data[12]",NULL),
- RK_SYSRQ_IOMUX_RES(0x64,8,3,"GPIO3_C[4]","smc_addr[11]","host_data[11]",NULL),
- RK_SYSRQ_IOMUX_RES(0x64,6,3,"GPIO3_C[3]","smc_addr[10]","host_data[10]",NULL),
- RK_SYSRQ_IOMUX_RES(0x64,4,3,"GPIO3_C[2]","smc_addr[13]","host_data[13]",NULL),
- RK_SYSRQ_IOMUX_RES(0x64,2,3,"GPIO3_C[1]","emmc_data[7]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x64,0,3,"GPIO3_C[0]","emmc_data[6]",NULL,NULL),
-};
-struct rk_sysrq_iomux_regres rk_sysrq_iomux_res_gpio4l[] = {
- RK_SYSRQ_IOMUX_RES(0X68,30,3,"GPIO4_B[7]","flash_data[15]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0X68,28,3,"GPIO4_B[6]","flash_data[14]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0X68,26,3,"GPIO4_B[5]","flash_data[13]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0X68,24,3,"GPIO4_B[4]","flash_data[12]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0X68,22,3,"GPIO4_B[3]","flash_data[11]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0X68,20,3,"GPIO4_B[2]","flash_data[10]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0X68,18,3,"GPIO4_B[1]","flash_data[9]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0X68,16,3,"GPIO4_B[0]","flash_data[8]",NULL,NULL),
-
- RK_SYSRQ_IOMUX_RES(0X68,14,3,"GPIO4_A[7]","spdif_tx",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0X68,12,3,"GPIO4_A[6]","otg1_drv_vbus",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0X68,10,3,"GPIO4_A[5]","otg0_drv_vbus",NULL,NULL),
-};
-struct rk_sysrq_iomux_regres rk_sysrq_iomux_res_gpio4h[] = {
- RK_SYSRQ_IOMUX_RES(0X6c,30,3,"GPIO4_D[7]","i2s0_lrck_tx1",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0X6c,28,3,"GPIO4_D[6]","i2s0_lrck_tx0",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0X6c,26,3,"GPIO4_D[5]","trace_ctl",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0X6c,24,3,"GPIO4_D[4]","cpu trace_clk",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0X6c,22,3,"GPIO6_C[7:6]","cpu trace_data[7:6]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0X6c,20,3,"GPIO6_C[5:4]","cpu trace_data[5:4]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0X6c,18,3,"GPIO4_D[3:2]","cpu trace_data[3:2]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0X6c,16,3,"GPIO4_D[1:0]","cpu trace_data[1:0]",NULL,NULL),
-
- RK_SYSRQ_IOMUX_RES(0X6c,14,3,"GPIO4_C[7]","rmii_rxd[0]","mii_rxd[0]",NULL),
- RK_SYSRQ_IOMUX_RES(0X6c,12,3,"GPIO4_C[6]","rmii_rxd[1]","mii_rxd[1]",NULL),
- RK_SYSRQ_IOMUX_RES(0X6c,10,3,"GPIO4_C[5]","rmii_csr_dvalid","mii_rxd_valid",NULL),
- RK_SYSRQ_IOMUX_RES(0X6c,8,3,"GPIO4_C[4]","rmii_rx_err","mii_rx_err",NULL),
- RK_SYSRQ_IOMUX_RES(0X6c,6,3,"GPIO4_C[3]","rmii_txd[0]","mii_txd[0]",NULL),
- RK_SYSRQ_IOMUX_RES(0X6c,4,3,"GPIO4_C[2]","rmii_txd[1]","mii_txd[1]",NULL),
- RK_SYSRQ_IOMUX_RES(0X6c,2,3,"GPIO4_C[1]","rmii_tx_en","mii_tx_en",NULL),
- RK_SYSRQ_IOMUX_RES(0X6c,0,3,"GPIO4_C[0]","rmii_clkout","rmii_clkin",NULL),
-};
-struct rk_sysrq_iomux_regres rk_sysrq_iomux_res_gpio5l[] = {
- RK_SYSRQ_IOMUX_RES(0x70,30,3,"GPIO5_B[7]","hsadc_clkout ","gps_clk ",NULL),
- RK_SYSRQ_IOMUX_RES(0x70,28,3,"GPIO5_B[6]","hsadc_data[9]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x70,26,3,"GPIO5_B[5]","hsadc_data[8]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x70,24,3,"GPIO5_B[4]","hsadc_data[7]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x70,22,3,"GPIO5_B[3]","hsadc_data[6]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x70,20,3,"GPIO5_B[2]","hsadc_data[5]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x70,18,3,"GPIO5_B[1]","hsadc_data[4]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x70,16,3,"GPIO5_B[0]","hsadc_data[3]",NULL,NULL),
-
- RK_SYSRQ_IOMUX_RES(0x70,14,3,"GPIO5_A[7]","hsadc_data[2]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x70,12,3,"GPIO5_A[6]","hsadc_data[1]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x70,10,3,"GPIO5_A[5]","hsadc_data[0]",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x70,8,3,"GPIO5_A[4]","ts_sync",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x70,6,3,"GPIO5_A[3]","mii_tx_clkin",NULL,NULL),
-};
-struct rk_sysrq_iomux_regres rk_sysrq_iomux_res_gpio5h[] = {
- RK_SYSRQ_IOMUX_RES(0x74,28,3,"GPIO5_D[6]","sdmmc1_pwr_en",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x74,26,3,"GPIO5_D[5]","sdmmc0_pwr_en",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x74,24,3,"GPIO5_D[4]","i2c2_scl",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x74,22,3,"GPIO5_D[3]","i2c2_sda",NULL,NULL),
- RK_SYSRQ_IOMUX_RES(0x74,20,3,"GPIO5_D[2]","pwm1","uart1_sir_in",NULL),
- RK_SYSRQ_IOMUX_RES(0x74,18,3,"GPIO5_D[1]","ebc_sdclk","smc_addr[6]","host_data[6]"),
- RK_SYSRQ_IOMUX_RES(0x74,16,3,"GPIO5_D[0]","ebc_sdle","smc_addr[5]","host_data[5]"),
-
- RK_SYSRQ_IOMUX_RES(0x74,14,3,"GPIO5_C[7]","ebc_sddo7","smc_data7",NULL),
- RK_SYSRQ_IOMUX_RES(0x74,12,3,"GPIO5_C[6]","ebc_sddo6","smc_data6",NULL),
- RK_SYSRQ_IOMUX_RES(0x74,10,3,"GPIO5_C[5]","ebc_sddo5","smc_data5",NULL),
- RK_SYSRQ_IOMUX_RES(0x74,8,3,"GPIO5_C[4]","ebc_sddo4","smc_data4",NULL),
- RK_SYSRQ_IOMUX_RES(0x74,6,3,"GPIO5_C[3]","ebc_sddo3","smc_data3",NULL),
- RK_SYSRQ_IOMUX_RES(0x74,4,3,"GPIO5_C[2]","ebc_sddo2","smc_data2",NULL),
- RK_SYSRQ_IOMUX_RES(0x74,2,3,"GPIO5_C[1]","ebc_sddo1","smc_data1",NULL),
- RK_SYSRQ_IOMUX_RES(0x74,0,3,"GPIO5_C[0]","ebc_sddo0","smc_data0",NULL),
-};
-struct rk_sysrq_gpio_printres rk_sysrq_gpio_printres_table[] = {
- RK_SYSRQ_GPIO_RES("gpio pin data\0","L","H",GPIO_SWPORTA_DR,GPIO_SWPORTB_DR,GPIO_SWPORTC_DR,GPIO_SWPORTD_DR),
- RK_SYSRQ_GPIO_RES("gpio pin driction\0","O","I",GPIO_SWPORTA_DDR,GPIO_SWPORTB_DDR,GPIO_SWPORTB_DDR,GPIO_SWPORTB_DDR),
- RK_SYSRQ_GPIO_RES("gpio int enable\0","G","I",GPIO_INTEN,0xffff,0xffff,0xffff),
- RK_SYSRQ_GPIO_RES("gpio int MASK\0","I","M",GPIO_INTMASK,0xffff,0xffff,0xffff),
- RK_SYSRQ_GPIO_RES("gpio int type\0","L","E",GPIO_INTTYPE_LEVEL,0xffff,0xffff,0xffff),
- RK_SYSRQ_GPIO_RES("gpio int polarity\0","L","H",GPIO_INT_POLARITY,0xffff,0xffff,0xffff),
- RK_SYSRQ_GPIO_RES("gpio int status\0","N","I",GPIO_INT_STATUS,0xffff,0xffff,0xffff),
-
-};
-struct rk_sysrq_iomux rk_sysrq_iomux_table[] = {
- RK_SYSRQ_IOMUX_CFG("GRF_GPIO0l_IOMUX",NULL,RK29_GRF_BASE,0l),
- RK_SYSRQ_IOMUX_CFG("GRF_GPIO0h_IOMUX",NULL,RK29_GRF_BASE,0h),
- RK_SYSRQ_IOMUX_CFG("GRF_GPIO1l_IOMUX",NULL,RK29_GRF_BASE,1l),
- RK_SYSRQ_IOMUX_CFG("GRF_GPIO1h_IOMUX",NULL,RK29_GRF_BASE,1h),
- RK_SYSRQ_IOMUX_CFG("GRF_GPIO2l_IOMUX",NULL,RK29_GRF_BASE,2l),
- RK_SYSRQ_IOMUX_CFG("GRF_GPIO2h_IOMUX",NULL,RK29_GRF_BASE,2h),
- RK_SYSRQ_IOMUX_CFG("GRF_GPIO3l_IOMUX",NULL,RK29_GRF_BASE,3l),
- RK_SYSRQ_IOMUX_CFG("GRF_GPIO3h_IOMUX",NULL,RK29_GRF_BASE,3h),
- RK_SYSRQ_IOMUX_CFG("GRF_GPIO4l_IOMUX",NULL,RK29_GRF_BASE,4l),
- RK_SYSRQ_IOMUX_CFG("GRF_GPIO4h_IOMUX",NULL,RK29_GRF_BASE,4l),
- RK_SYSRQ_IOMUX_CFG("GRF_GPIO5l_IOMUX",NULL,RK29_GRF_BASE,5l),
- RK_SYSRQ_IOMUX_CFG("GRF_GPIO5h_IOMUX",NULL,RK29_GRF_BASE,5h),
-};
-struct rk_sysrq_gpio rk_sysrq_gpio_table[] = {
- RK_SYSRQ_GPIO("GPIO 0",RK29_GPIO0_BASE),
- RK_SYSRQ_GPIO("GPIO 1",RK29_GPIO1_BASE),
- RK_SYSRQ_GPIO("GPIO 2",RK29_GPIO2_BASE),
- RK_SYSRQ_GPIO("GPIO 3",RK29_GPIO3_BASE),
- RK_SYSRQ_GPIO("GPIO 4",RK29_GPIO4_BASE),
- RK_SYSRQ_GPIO("GPIO 5",RK29_GPIO5_BASE),
- //RK_SYSRQ_GPIO("GPIO 0"),
- //RK_SYSRQ_GPIO("GPIO2",RK2818_GPIO2_BASE),
- //RK_SYSRQ_GPIO("GPIO3",RK2818_GPIO3_BASE),
-};
-
-
-static inline unsigned int rk_sysrq_reg_read(const unsigned char __iomem *regbase, unsigned int regOff)
-{
- return __raw_readl(regbase + regOff);
-}
-char rk_sysrq_table_fistline_buf[1024];
-#if 0
-void rk_sysrq_draw_table(a,_)int a;int _;{
-
- char line_buf[129];
- int i,j;
- for(j = 0; j < 100; j++){
- if(j%3){
- for(i = 0; i < 100; i++){
- if(i%16)
- line_buf[i] = ' ';
- else
- line_buf[i] = '+';
- }
- line_buf[100] = 0;
- printk("%s\n",line_buf);
- }
-
- else{
- printk("%s\n",rk_sysrq_table_fistline_buf);
- }
-
- }
- printk("%s\n",rk_sysrq_table_fistline_buf);
-}
-#endif
-
-/* Whether we react on sysrq keys or just ignore them */
-int __read_mostly __rk_sysrq_enabled = 1;
-
-static int __read_mostly rk_sysrq_always_enabled;
-
-int rk_sysrq_on(void)
-{
- return __rk_sysrq_enabled || rk_sysrq_always_enabled;
-}
-
-/*
- * A value of 1 means 'all', other nonzero values are an op mask:
- */
-static inline int rk_sysrq_on_mask(int mask)
-{
- return rk_sysrq_always_enabled || __rk_sysrq_enabled == 1 ||
- (__rk_sysrq_enabled & mask);
-}
-
-static int __init rk_sysrq_always_enabled_setup(char *str)
-{
- rk_sysrq_always_enabled = 1;
- printk(KERN_INFO "debug: rk_sysrq always enabled.\n");
-
- return 1;
-}
-
-__setup("rk_sysrq_always_enabled", rk_sysrq_always_enabled_setup);
-
-
-void rk_sysrq_get_gpio_status(void)
-{
-
- return ;
-}
-
-
-static void rk_sysrq_gpio_show_reg(struct rk_sysrq_gpio *gpio_res)
-{
- char rk_sysrq_line_buf[129];
- char *temp;
- unsigned int reg;
- int i = 0,j = 0, k = 0;
- rk_sysrq_line_buf[128] = 0xff;
- k = gpio_res->res_table_count;
-
- printk("-->%s ::\n",gpio_res->rk_sysrq_gpio_name);
- while(k--){
- for(j = 0; gpio_res->res_table[k].res_off[j] != 0xffff ; j++){
- temp = rk_sysrq_line_buf;
- memset(rk_sysrq_line_buf,0,128);
- printk("%s P[%c]: ",gpio_res->res_table[k].res_name,j+65);
- reg = rk_sysrq_reg_read(gpio_res->regbase, gpio_res->res_table[k].res_off[j]);
- for(i = 0; i < 8; i++){
- *temp++ = '[';
- *temp++ = (i+48);
- *temp++ = ']';
- *temp++ = ':';
- *temp++ = *(gpio_res->res_table[k].resmap[reg&1].resname);
- *temp++ = ' ';
- reg = reg>>1;
- }
-
- printk("%s\n",rk_sysrq_line_buf);
- }
- printk("\n");
- }
-}
-static void rk_sysrq_iomux_show_reg(struct rk_sysrq_iomux *mux)
-{
- char *temp;
- const char *temp2;
- unsigned int reg;
- int i = 0,k = 0;
- if(mux->message)
- printk("%s\n",mux->message);
- reg = rk_sysrq_reg_read(mux->reg_base,mux->regres_table[0].off);
- for(i = 0 ; i < mux->res_table_count; i ++){
- unsigned int mask = mux->regres_table[i].mask_bit;
- unsigned int start_bit = mux->regres_table[i].start_bit;
- memset(rk_sysrq_table_fistline_buf,0,1024);
- temp = rk_sysrq_table_fistline_buf;
- for(k = 0 ; k < (mask + 1) ; k++){
- temp2 = mux->regres_table[i].reg_description[k];
- *temp++ = '[';*temp++ = (((k >> 1)&1) + '0');*temp++ = ((k&1) + '0');*temp++ = ']';*temp++ = ':';
- if(temp2 == NULL){
- *temp++ = 'r';*temp++ = 'e';*temp++ = 's';
- }else{
- while(*temp2)
- *temp++ = *temp2++;
- }
- *temp++ = ' ';
- }
- printk("%s\n",rk_sysrq_table_fistline_buf);
- memset(rk_sysrq_table_fistline_buf,0,1024);
- temp = rk_sysrq_table_fistline_buf;
- temp2 = mux->regres_table[i].reg_description[(reg >> start_bit)&mask];
- if(temp2 == NULL){
- *temp++ = 'r';*temp++ = 'e';*temp++ = 's';
- }else{
- while(*temp2)
- *temp++ = *temp2++;
- }
- printk("current set is : %s \n\n",rk_sysrq_table_fistline_buf);
- }
- return ;
-}
-static void rk_sysrq_handle_dump_gpio(int key, struct tty_struct *tty)
-{
- int i,count = 0;
- count = ARRAY_SIZE(rk_sysrq_gpio_table);
- for(i = 0; i < count ; i++){
- rk_sysrq_gpio_show_reg(&rk_sysrq_gpio_table[i]);
- }
- count = ARRAY_SIZE(rk_sysrq_iomux_table);
- for(i = 0; i < count ; i++){
- rk_sysrq_iomux_show_reg(&rk_sysrq_iomux_table[i]);
- }
-
- return ;
-}
-static void rk_sysrq_handle_show_gpio(int key, struct tty_struct *tty)
-{
- int i,count = 0;
- count = ARRAY_SIZE(rk_sysrq_gpio_table);
- for(i = 0; i < count ; i++){
- rk_sysrq_gpio_show_reg(&rk_sysrq_gpio_table[i]);
- }
-
- return ;
-}
-static void rk_sysrq_handle_show_iomux(int key, struct tty_struct *tty)
-{
- int i,count = 0;
-
- count = ARRAY_SIZE(rk_sysrq_iomux_table);
- for(i = 0; i < count ; i++){
- rk_sysrq_iomux_show_reg(&rk_sysrq_iomux_table[i]);
- }
-
- return ;
-}
-static struct sysrq_key_op rk_sysrq_dump_gpio_op = {
- .handler = rk_sysrq_handle_dump_gpio,
- .help_msg = "dump gpio state(d)",
- .action_msg = "Nice All RT Tasks",
- .enable_mask = SYSRQ_ENABLE_RTNICE,
-};
-static struct sysrq_key_op rk_sysrq_show_gpio_op = {
- .handler = rk_sysrq_handle_show_gpio,
- .help_msg = "dump gpio state(o)",
- .action_msg = "Nice All RT Tasks",
- .enable_mask = SYSRQ_ENABLE_RTNICE,
-};
-static struct sysrq_key_op rk_sysrq_show_iomux_op = {
- .handler = rk_sysrq_handle_show_iomux,
- .help_msg = "dump gpio state(m)",
- .action_msg = "Nice All RT Tasks",
- .enable_mask = SYSRQ_ENABLE_RTNICE,
-};
-/* Key Operations table and lock */
-static DEFINE_SPINLOCK(rk_sysrq_key_table_lock);
-
-static struct sysrq_key_op *rk_sysrq_key_table[36] = {
- #if 0
- &sysrq_loglevel_op, /* 0 */
- &sysrq_loglevel_op, /* 1 */
- &sysrq_loglevel_op, /* 2 */
- &sysrq_loglevel_op, /* 3 */
- &sysrq_loglevel_op, /* 4 */
- &sysrq_loglevel_op, /* 5 */
- &sysrq_loglevel_op, /* 6 */
- &sysrq_loglevel_op, /* 7 */
- &sysrq_loglevel_op, /* 8 */
- &sysrq_loglevel_op, /* 9 */
-
- /*
- * a: Don't use for system provided sysrqs, it is handled specially on
- * sparc and will never arrive.
- */
- NULL, /* a */
- &sysrq_reboot_op, /* b */
- &sysrq_crash_op, /* c & ibm_emac driver debug */
- &sysrq_showlocks_op, /* d */
- &sysrq_term_op, /* e */
- &sysrq_moom_op, /* f */
- /* g: May be registered for the kernel debugger */
- NULL, /* g */
- NULL, /* h - reserved for help */
- &sysrq_kill_op, /* i */
-#ifdef CONFIG_BLOCK
- &sysrq_thaw_op, /* j */
-#else
- NULL, /* j */
-#endif
- &sysrq_SAK_op, /* k */
-#ifdef CONFIG_SMP
- &sysrq_showallcpus_op, /* l */
-#else
- NULL, /* l */
-#endif
- &sysrq_showmem_op, /* m */
- &sysrq_unrt_op, /* n */
- /* o: This will often be registered as 'Off' at init time */
- NULL, /* o */
- &sysrq_showregs_op, /* p */
- &sysrq_show_timers_op, /* q */
- &sysrq_unraw_op, /* r */
- &sysrq_sync_op, /* s */
- &sysrq_showstate_op, /* t */
- &sysrq_mountro_op, /* u */
- /* v: May be registered for frame buffer console restore */
- NULL, /* v */
- &sysrq_showstate_blocked_op, /* w */
- /* x: May be registered on ppc/powerpc for xmon */
- NULL, /* x */
- /* y: May be registered on sparc64 for global register dump */
- NULL, /* y */
- &sysrq_ftrace_dump_op, /* z */
- #endif
- NULL, /*0*/
- NULL, /*1*/
- NULL, /*2*/
- NULL, /*3*/
- NULL, /*4*/
- NULL, /*5*/
- NULL, /*6*/
- NULL, /*7*/
- NULL, /*8*/
- NULL, /*9*/
- NULL, /*a*/
- NULL, /*b*/
- NULL, /*c*/
- &rk_sysrq_dump_gpio_op, /*d*/
- NULL, /*e*/
- NULL, /*f*/
- NULL, /*g*/
- NULL, /*h*/
- NULL, /*i*/
- NULL, /*j*/
- NULL, /*k*/
- NULL, /*l*/
- &rk_sysrq_show_iomux_op, /*m*/
- NULL, /*n*/
- &rk_sysrq_show_gpio_op, /*o*/
- NULL, /*p*/
- NULL, /*q*/
- NULL, /*r*/
- NULL, /*s*/
- NULL, /*t*/
- NULL, /*u*/
- NULL, /*v*/
- NULL, /*w*/
- NULL, /*x*/
- NULL, /*y*/
- NULL, /*z*/
-
-};
-
-/* key2index calculation, -1 on invalid index */
-static int rk_sysrq_key_table_key2index(int key)
-{
- int retval;
-
- if ((key >= '0') && (key <= '9'))
- retval = key - '0';
- else if ((key >= 'a') && (key <= 'z'))
- retval = key + 10 - 'a';
- else
- retval = -1;
- return retval;
-}
-
-/*
- * get and put functions for the table, exposed to modules.
- */
-struct sysrq_key_op *__rk_sysrq_get_key_op(int key)
-{
- struct sysrq_key_op *op_p = NULL;
- int i;
- i = rk_sysrq_key_table_key2index(key);
- if (i != -1)
- op_p = rk_sysrq_key_table[i];
- return op_p;
-}
-
-static void __rk_sysrq_put_key_op(int key, struct sysrq_key_op *op_p)
-{
- int i = rk_sysrq_key_table_key2index(key);
-
- if (i != -1)
- rk_sysrq_key_table[i] = op_p;
-}
-
-/*
- * This is the non-locking version of handle_sysrq. It must/can only be called
- * by sysrq key handlers, as they are inside of the lock
- */
-void __rk_handle_sysrq(int key, struct tty_struct *tty, int check_mask)
-{
- struct sysrq_key_op *op_p;
- int orig_log_level;
- int i;
- unsigned long flags;
- spin_lock_irqsave(&rk_sysrq_key_table_lock, flags);
- /*
- * Raise the apparent loglevel to maximum so that the sysrq header
- * is shown to provide the user with positive feedback. We do not
- * simply emit this at KERN_EMERG as that would change message
- * routing in the consumers of /proc/kmsg.
- */
- orig_log_level = console_loglevel;
- console_loglevel = 7;
- printk(KERN_INFO "rk_SysRq : ");
-
- op_p = __rk_sysrq_get_key_op(key);
- if (op_p) {
- /*
- * Should we check for enabled operations (/proc/sysrq-trigger
- * should not) and is the invoked operation enabled?
- */
- if (!check_mask || rk_sysrq_on_mask(op_p->enable_mask)) {
- printk("%s\n", op_p->action_msg);
- console_loglevel = orig_log_level;
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36))
- op_p->handler(key);
-#else
- op_p->handler(key, tty);
-#endif
- } else {
- printk("This sysrq operation is disabled.\n");
- }
- } else {
- printk("HELP : ");
- /* Only print the help msg once per handler */
- for (i = 0; i < ARRAY_SIZE(rk_sysrq_key_table); i++) {
- if (rk_sysrq_key_table[i]) {
- int j;
-
- for (j = 0; rk_sysrq_key_table[i] !=
- rk_sysrq_key_table[j]; j++)
- ;
- if (j != i)
- continue;
- printk("%s ", rk_sysrq_key_table[i]->help_msg);
- }
- }
- printk("\n");
- console_loglevel = orig_log_level;
- }
- spin_unlock_irqrestore(&rk_sysrq_key_table_lock, flags);
-}
-
-/*
- * This function is called by the keyboard handler when SysRq is pressed
- * and any other keycode arrives.
- */
-void rk_handle_sysrq(int key, struct tty_struct *tty)
-{
- if (rk_sysrq_on())
- __rk_handle_sysrq(key, tty, 1);
-}
-EXPORT_SYMBOL(rk_handle_sysrq);
-
-static int __rk_sysrq_swap_key_ops(int key, struct sysrq_key_op *insert_op_p,
- struct sysrq_key_op *remove_op_p)
-{
-
- int retval;
- unsigned long flags;
- spin_lock_irqsave(&rk_sysrq_key_table_lock, flags);
- if (__rk_sysrq_get_key_op(key) == remove_op_p) {
- __rk_sysrq_put_key_op(key, insert_op_p);
- retval = 0;
- } else {
- retval = -1;
- }
- spin_unlock_irqrestore(&rk_sysrq_key_table_lock, flags);
- return retval;
-}
-
-int rk_register_sysrq_key(int key, struct sysrq_key_op *op_p)
-{
- return __rk_sysrq_swap_key_ops(key, op_p, NULL);
-}
-EXPORT_SYMBOL(rk_register_sysrq_key);
-
-int rk_unregister_sysrq_key(int key, struct sysrq_key_op *op_p)
-{
- return __rk_sysrq_swap_key_ops(key, NULL, op_p);
-}
-EXPORT_SYMBOL(rk_unregister_sysrq_key);
-
-#ifdef CONFIG_PROC_FS
-/*
- * writing 'C' to /proc/sysrq-trigger is like sysrq-C
- */
-static ssize_t rk_write_sysrq_trigger(struct file *file, const char __user *buf,
- size_t count, loff_t *ppos)
-{
- if (count) {
- char c;
- if (get_user(c, buf))
- return -EFAULT;
- __rk_handle_sysrq(c, NULL, 0);
- }
- return count;
-}
-
-static const struct file_operations rk_proc_sysrq_trigger_operations = {
- .write = rk_write_sysrq_trigger,
-};
-
-static int __init rk_sysrq_init(void)
-{
- memset(rk_sysrq_table_fistline_buf, '+', 128);
- rk_sysrq_table_fistline_buf[100] = 0;
- proc_create("rk-sysrq-trigger", S_IWUSR, NULL, &rk_proc_sysrq_trigger_operations);
- return 0;
-}
-module_init(rk_sysrq_init);
-#endif
+++ /dev/null
-#
-# Makefile for rk_scu drivers.
-#
-obj-y :=wrapcall.o debug.o kobj.o
-
-
-
+++ /dev/null
-/*
- * function for test and debug
- *
- * Copyright (C) 2011 Rochchip, Inc.
- * Author: Hsl
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * relative files: drivers/dbg/ , arch/arm/kernel/entry-common.S
- * LOG:
- * 20110127, HSL@RK,add get user regs support and kernel io support.
- */
-
-/* #define DEBUG */
-#include <linux/kallsyms.h>
-#include <linux/delay.h>
-#include <linux/version.h>
-#include <linux/slab.h>
-
-/*
- * 20090725,hsl,some debug function start from here
- */
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/mmzone.h>
-#include <linux/rtc.h>
-
-#include <asm/sections.h>
-#include <asm/stacktrace.h>
-#include <asm/io.h>
-
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,31)
-#define FIND_TASK_BY_PID(x) pid_task(find_vpid(x), PIDTYPE_PID)
-#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
-#define FIND_TASK_BY_PID(x) find_task_by_vpid(x)
-#else
-#define FIND_TASK_BY_PID(x) find_task_by_pid(x)
-#endif
-
-extern int __scu_call_wrap(unsigned long *argv , int argc , int fun );
-extern void ret_fast_syscall( void );
-
-void rk28_printk_mem( unsigned int * addr , int words , unsigned int* show_addr )
-{
- unsigned int * reg_base = addr ;
- if( show_addr == NULL ){
- show_addr = addr;
- }
- while( words > 0 ) {
- printk("%p:%08x %08x %08x %08x\n" ,show_addr ,
- reg_base[0],reg_base[1],reg_base[2],reg_base[3]);
- words -= 4;
- reg_base += 4;
- show_addr += 4;
- }
-}
-
-/*
- * type define :
- * first for function name ,
- * ',' for argument.
- * \' : char
- * \" : string.
- * other : for int,short,0x for hex.0 for octal.
- * 20090811,for easy use , 0x or 0-9 start means num , other ,means string .
- * len = 1 string for char.
- * 20100420,add nagative support.
- */
-int dbg_get_arg( char ** pp )
-{
- char * p = *pp;
- char *t;
- int ret;
- int len ;
- int nag = 0;
- int bnum = 0;
- if( p[0] == '-' ) {
- nag = 1;
- p++;
- }
- if( p[0] == '0' ) {
- if( ( p[1] == 'x' || p[1] == 'X' ) ) {
- p+= 2;
- len = sscanf(p,"%x" , &ret );
- p += len;
- } else {
- if( p[1] == 0 || p[1] == ',' ) {
- ret = 0; /* only one '0' , must be zero */
- p++;
- } else {
- p+= 1;
- len = sscanf(p,"%o" , &ret );
- p += len;
- }
- }
- bnum = 1;
- } else if( p[0] >= '1' && p[0] <= '9' ) {
- len = sscanf(p,"%d" , (int*)&ret );
- p += len;
- bnum = 1;
- } else if( p[0] == '\'' ) {
- ret = p[1];
- p++;
- } else { /* all for string */
- if ( p[0] == '\"' ) {
- if( p[1] == '\"' ) { /* NULL string */
- ret = 0;
- p+=2;
- } else {
- ret = (unsigned long)(p+1);
- t = strchr( p+1 , '\"' );
- if( t ) {
- *t = 0;
- p = t+1 ;
- } else {
- p++;
- }
- }
- } else {
- if( *p == ',' ) {/* empty ,as NULL string */
- ret = 0;
- p--;
- } else if( *p == ' ' || *p == 0 ) /* one char string ,as char.*/
- ret = *p;
- else /* as string */
- ret = (unsigned long)(p);
- p++;
- }
- }
- t = strchr( p , ',' );
- if( t ) {
- *t = 0;
- *pp = t+1;
- } else { /* p should be the last one */
- while(*p != ' ' && *p != 0 && *p != '\n' )
- p++;
- *p = 0;
- *pp = p;
- }
- if( nag && bnum )
- ret = 0-ret;
- return ret;
-}
-int dbg_parse_cmd( char * cdb )
-{
- unsigned long reg[6];
- unsigned long fun;
- int argc = 0 ;
- char *p = cdb ;
- char *sym = p;
- int ret;
-
- //SCU_BUG("CMD=%s\n" , cdb);
- memset( reg , 0 , sizeof reg );
- p = strchr(p , ',');
- if( p ) {
- *p++ = 0;
- while( *p && argc < 6) {
- reg[argc++] = (unsigned long)dbg_get_arg( &p );
- }
- }
- //debug_print("sym=%s,argc=%d,db=%s\n" , sym ,argc , cdb );
- if( sym[0] == '0' && ( sym[1] == 'x' || sym[1] == 'X' ) ) {
- fun = 0;
- sscanf(sym+2,"%lx" , &fun );
- } else {
- fun = kallsyms_lookup_name(sym);
- //debug_print("after lookup symbols,sym=%s,fun=0x%p\n" , sym ,fun);
- }
-
- /* 20100409,HSL@RK,use printk to print to buffer.
- */
- printk("@CALL@ %s(0x%p),argc=%d\n" , sym , (void*)fun , argc);
- if( fun ) {
- ret = __scu_call_wrap( reg,argc,fun);
- } else {
- ret = -EIO;
- }
- /* 20100722,"@return" for function print end tag.
- */
- printk("@return 0x%x(%d)\n" , ret , ret);
- return ret;
-}
-
-#if 0
-/**
- * check arg be a string or int or symbol addr .
- * 1: string , 2: kernel sym , 0:other
- */
-int rk28_arg_string( unsigned long arg )
-{
- if( arg > (unsigned long)&_end && arg < 0xc8000000 )
- return 1;
- if( arg >= (unsigned long)&_text && arg < (unsigned long)&_end )
- return 2;
- return 0;
-}
-#endif
-
-static struct pt_regs * unwind_get_regs(struct task_struct *tsk)
-{
- struct stackframe frame;
- register unsigned long current_sp asm ("sp");
- int found = 0;
- //unsigned long sc;
-
- if (!tsk)
- tsk = current;
-
- printk("tsk = %p,comm=%s,pid=%d,pgd=0x%p\n", tsk , tsk->comm , tsk->pid , tsk->mm->pgd );
- if (tsk == current) {
- frame.fp = (unsigned long)__builtin_frame_address(0);
- frame.sp = current_sp;
- frame.lr = (unsigned long)__builtin_return_address(0);
- frame.pc = (unsigned long)unwind_get_regs;
- } else {
- /* task blocked in __switch_to */
- frame.fp = thread_saved_fp(tsk);
- frame.sp = thread_saved_sp(tsk);
- /*
- * The function calling __switch_to cannot be a leaf function
- * so LR is recovered from the stack.
- */
- frame.lr = 0;
- frame.pc = thread_saved_pc(tsk);
- }
-
- while (1) {
- int urc;
- //unsigned long where = frame.pc;
-
- urc = unwind_frame(&frame);
- if (urc < 0)
- break;
- //dump_backtrace_entry(where, frame.pc, frame.sp - 4);
- if( frame.pc == (unsigned long)ret_fast_syscall ){
- found = 1;
- break;
- }
- }
- if( !found )
- return NULL;
- #if 0
- //printk("FRAME:sp=0x%lx,pc=0x%lx,lr=0x%lx,fp=0x%lx\n" , frame.sp,frame.pc,frame.lr,frame.fp );
- //rk28_printk_mem((unsigned int*)(frame.sp-sizeof(struct pt_regs)),2*sizeof(struct pt_regs)/4+8, NULL );
- sc =*( (unsigned long*)(frame.sp-4));
- if( sc >= (unsigned long)&_text && sc < (unsigned long)&_end ){
- print_symbol("sys call=%s\n",sc );
- }
- #endif
- return (struct pt_regs *)(frame.sp+8); // 8 for reg r4,r5 as fifth and sixth args.
-}
-
-struct pt_regs * __scu_get_regs( void )
-{
- return unwind_get_regs( NULL );
-}
-
-struct pt_regs * scu_get_task_regs( int pid )
-{
- struct task_struct *t = FIND_TASK_BY_PID( pid );
- return unwind_get_regs( t );
-}
-
-/*
- * f: bit0: show kernel , bit1: dump user.
- */
-int tstack( int pid , int f)
-{
- struct pt_regs * preg;
- struct task_struct *t = FIND_TASK_BY_PID( pid );
-
- if( !t ){
- printk("NO task found for pid %d\n" ,pid );
- t = current ;
- }
- preg = unwind_get_regs( t );
- if( f& 1 ) {
- show_stack( t , NULL );
- }
- if( !preg ) {
- printk("NO user stack found for task %s(%d)\n" , t->comm , t->pid );
- } else {
- //printk("user stack found for task %s(%d):\n" , t->comm , t->pid );
- __show_regs( preg );
- if( f & 2 ) {
- #define SHOW_STACK_SIZE (2*1024)
- int len;
- unsigned int *ps = (unsigned int*)kmalloc( SHOW_STACK_SIZE , GFP_KERNEL);
- if( ps ) {
- len = access_process_vm( t , preg->ARM_sp , ps , SHOW_STACK_SIZE, 0 );
- rk28_printk_mem( ps , len/4 , (unsigned int* )preg->ARM_sp );
- kfree( ps );
- }
- }
- }
- return pid;
-}
-
-#if 0
-void __rk_force_signal(struct task_struct *tsk, unsigned long addr,
- unsigned int sig, int code )
-{
- struct siginfo si;
- printk("%s::send sig %d to task %s\n" , __func__ , sig , tsk->comm );
- si.si_signo = sig;
- si.si_errno = 0;
- si.si_code = code;
- si.si_addr = (void __user *)addr;
- force_sig_info(sig, &si, tsk);
-}
-int rksignal( int pid , int sig )
-{
- struct task_struct *t = FIND_TASK_BY_PID( pid );
- if( !t )
- t = current ;
- __rk_force_signal( t , 0xc0002234 , sig , 0x524b4b52 );
- return 0x201;
-}
-
-#include <linux/tty.h>
-#include <linux/console.h>
-#include <linux/tty_flip.h>
-extern struct console *console_drivers;
-// like : echo rk28_uart_input,"\"pwd|ls,echo fdfdf\"">active
-int rk28_uart_input( char * str )
-{
- char * p = str;
- int indx;
- struct tty_driver *tty_drv = console_drivers->device( console_drivers , &indx );
- struct tty_struct *tty_s = tty_drv->ttys[indx ];
- int flag = TTY_NORMAL;
-
- printk("indx=%d, tty drv=%p,tty_s=%p,cur console=%s,next console=%p\n", indx , tty_drv , tty_s ,
- console_drivers->name , console_drivers->next );
- //printk("cmd=%s\n" , str );
- if( !p )
- return -EIO;
-
- while( *p ) {
- if( *p == ',' )
- *p = '\n';
- p++;
- }
- *p++ = '\n';
- *p = 0;
-
- p = str;
- while( *p ) {
- tty_insert_flip_char(tty_s, *p , flag);
- p++;
- }
-
- tty_flip_buffer_push( tty_s );
- return 0x28;
-}
-#endif
-
-#if 0
-extern int kernel_getlog( char ** start , int * offset , int* len );
-int rk28_write_file( char *filename )
-{
- char *procmtd = "/proc/mtd";
- struct file *filp = NULL;
- loff_t pos;
- long fd;
-
- ssize_t l=0;
- char pathname[64];
- char buf[1024] ;
- mm_segment_t old_fs;
- struct rtc_time tm;
- ktime_t now;
- char *tmpbuf;
- int mtdidx=0;
- int mtdsize = 0x200000; // 2M
- char *log_buf;
- int log_len;
-
- debug_print("%s: filename=%s\n" , __func__ , filename );
-
- old_fs = get_fs();
- set_fs(KERNEL_DS);
- fd = sys_open( procmtd , O_RDONLY , 0 );
- if( fd >= 0 ) {
- memset( buf , 0 , 1024 );
- l = sys_read( fd , buf , 1024 );
- // debug_print("/proc/mtd,total byte=%d\n" , l );
- tmpbuf = strstr( buf , filename );
- if( tmpbuf ) {
- tmpbuf[10] = 0;
- mtdsize = simple_strtoul(tmpbuf-19, NULL , 16);
- mtdidx = tmpbuf[-22];
- //debug_print("size=%s\n,idx=%s\nmtdsize=%x , mtdidx=%d" , tmpbuf-19 , tmpbuf - 22 ,
- // mtdsize , mtdidx );
- mtdsize *= 512;
- mtdidx -= '0';
- }
- sys_close( fd );
- } else {
- debug_print("open %s failed\n" , procmtd );
- }
- sprintf(pathname , "/dev/block/mtdblock%d" , mtdidx );
- filp = filp_open(pathname, O_WRONLY , 0);
- if( IS_ERR(filp) ) {
- debug_print("open %s failed n" , pathname );
- goto out_print;
- }
- if (!(filp->f_op->write || filp->f_op->aio_write)) {
- debug_print("can not write file %s \n" , pathname );
- goto close_file;
- }
- now = ktime_get();
- rtc_time_to_tm( now.tv.sec , &tm );
- printk( "\n+++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n"
- "++++++++++RECORD LOG AT %04d-%02d-%02d %02d:%02d:%02d++++++++++\n"
- "+++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n\n\n\n"
- ,
- tm.tm_year+1900 , tm.tm_mon , tm.tm_mday , tm.tm_hour , tm.tm_min , tm.tm_sec );
- /* 20090924,HSL,FTL only intial first 256M at loader , MUST write 32 sector one time */
- //debug_print("write first pack , pos=%d\n" , pos ); /* pos = 2 ?? */
- kernel_getlog(&log_buf , NULL , &log_len );
- log_len = (log_len+(32*512-1)) / (32*512) * (32*512);
- pos = 0;
- l = vfs_write( filp , log_buf , log_len , &pos );
- do_fsync(filp, 1);
-close_file:
- filp_close(filp , NULL);
-out_print:
- set_fs(old_fs);
- debug_print("\nlog len=%d,write=%d\n" ,log_len , l);
- return 0x2b;
-}
-#endif
-
-#if 1
-/*
- *
- * 20091027,2808SDK,
- * lcd off:byte:81748000,word:39100000.
- * lcd on: byte:90742000,word:43158000 %9.5
- *
- * 20091111,2806 ruiguan,
- * lcd off: byte: 81883000,word: 39209000
- * lcd on: byte: 90843000,word: 43260000
-
- * 20100516,281x, 133 ddr , lcd on.
- * need 151432000 ns to copy 4096 Kbytes
- * need 85340000 ns to copy 1024 Kwords
- LCD OFF.
- * need 144880000 ns to copy 4096 Kbytes
- * need 83100000 ns to copy 1024 Kwords
- 20100517,281x,200M ddr lcd on.
- * need 90024000 ns to copy 4096 Kbytes
- * need 47668000 ns to copy 1024 Kwords
- lcd off
- need 87564000 ns to copy 4096 Kbytes
- need 46956000 ns to copy 1024 Kwords
- 20100518,266M ddr. lcd on
- need 84460000 ns to copy 4096 Kbytes
- need 41036000 ns to copy 1024 Kwords
-
- need 204568000 ns to copy 4096 Kbytes
-need 116388000 ns to copy 1024 Kwords
-
- ddr 330M,lcd on.
- need 81944000 ns to copy 4096 Kbytes
- need 37640000 ns to copy 1024 Kwords
- ahb 180M.ddr 330M.
- need 88908000 ns to copy 4096 Kbytes
- need 38108000 ns to copy 1024 Kwords
-
- ahb 200M,DDR 380M,lcd on.
- need 79456000 ns to copy 4096 Kbytes
- need 34216000 ns to copy 1024 Kwords %0.14.
-
- need 79432000 ns to copy 4096 Kbytes
-need 34204000 ns to copy 1024 Kwords
-LCD OFF.
- need 77260000 ns to copy 4096 Kbytes
- need 33768000 ns to copy 1024 Kwords
-
- need 77228000 ns to copy 4096 Kbytes
-need 33764000 ns to copy 1024 Kwords %0.01
- */
-
-/*
-on rk29
-dyn desktop:
-[ 63.010000] @CALL@ rk28_memcpy(0xc070148c),argc=0
-[ 63.100000] need 90342667 ns to copy 4096 Kbytes
-[ 63.140000] need 38885333 ns to copy 1024 Kwords
-[ 63.160000] need 13030791 ns to memcpy 4096 Kbytes
-[ 63.160000] @return 0x2c(44)
-# echo rk28_memcpy > cal
-[ 65.680000] @CALL@ rk28_memcpy(0xc070148c),argc=0
-[ 65.740000] need 57542915 ns to copy 4096 Kbytes
-[ 65.770000] need 30017666 ns to copy 1024 Kwords
-[ 65.810000] need 32929083 ns to memcpy 4096 Kbytes
-[ 65.810000] @return 0x2c(44)
-# echo rk28_memcpy > cal
-[ 67.400000] @CALL@ rk28_memcpy(0xc070148c),argc=0
-[ 67.460000] need 52001876 ns to copy 4096 Kbytes
-[ 67.490000] need 29809209 ns to copy 1024 Kwords
-# [ 67.510000] need 20318709 ns to memcpy 4096 Kbytes
-[ 67.510000] @return 0x2c(44)
-# echo rk28_memcpy > cal
-[ 71.800000] @CALL@ rk28_memcpy(0xc070148c),argc=0
-[ 71.860000] need 57265835 ns to copy 4096 Kbytes
-[ 71.900000] need 32522127 ns to copy 1024 Kwords
-[ 71.930000] need 27615668 ns to memcpy 4096 Kbytes
-[ 71.930000] @return 0x2c(44)
-
-
-static desktop:
-
-[ 171.880000] @CALL@ rk28_memcpy(0xc070148c),argc=0
-[ 171.910000] need 27547043 ns to copy 4096 Kbytes
-[ 171.920000] need 8993501 ns to copy 1024 Kwords
-[ 171.930000] need 6791584 ns to memcpy 4096 Kbytes
-[ 171.930000] @return 0x2c(44)
-# echo rk28_memcpy > cal
-[ 174.050000] @CALL@ rk28_memcpy(0xc070148c),argc=0
-[ 174.080000] need 26437334 ns to copy 4096 Kbytes
-[ 174.090000] need 8701667 ns to copy 1024 Kwords
-[ 174.100000] need 6639375 ns to memcpy 4096 Kbytes
-[ 174.100000] @return 0x2c(44)
-# echo rk28_memcpy > cal
-[ 176.290000] @CALL@ rk28_memcpy(0xc070148c),argc=0
-[ 176.320000] need 26692502 ns to copy 4096 Kbytes
-[ 176.330000] need 8659126 ns to copy 1024 Kwords
-[ 176.340000] need 6702001 ns to memcpy 4096 Kbytes
-[ 176.340000] @return 0x2c(44)
-# echo rk28_memcpy > cal
-[ 177.710000] @CALL@ rk28_memcpy(0xc070148c),argc=0
-[ 177.740000] need 27578291 ns to copy 4096 Kbytes
-[ 177.750000] need 8740042 ns to copy 1024 Kwords
-[ 177.760000] need 6727458 ns to memcpy 4096 Kbytes
-[ 177.760000] @return 0x2c(44)
-
-*/
-int rkmemcpy( void )
-{
-#define PAGE_ORDER 7
- ktime_t now0,now1;
-
- unsigned long pg;
- unsigned long src = 0xc0010000;
- int i = 8,k=0;
- int bytes = ((1<<PAGE_ORDER)*PAGE_SIZE);
-
- pg = __get_free_pages(GFP_KERNEL , PAGE_ORDER );
- if( !pg ) {
- printk("alloc %d pages total %dK bytes failed\n" , (1<<PAGE_ORDER) , bytes/(1024));
- return -ENOMEM;
- }
- now0 = ktime_get();
- while( k < i ) {
- char *p = (char*)pg;
- char *q = (char*)src;
- char *m = q+bytes;
- while( q < m )
- *p++ = *q++;
- k++;
- }
- now1 = ktime_get();;
- printk("need %Ld ns to copy %d Kbytes \n" ,
- ktime_to_ns( ktime_sub( now1 , now0 ) ), bytes * i /1024 );
- now0 = ktime_get();
- k = 0;
- while( k < i ) {
- int *p = (int*)pg;
- int *q = (int*)src;
- int *m = q+bytes/sizeof(int);
- while( q < m )
- *p++ = *q++;
- k++;
- }
- now1 = ktime_get();
-
- printk("need %Ld ns to copy %d Kwords \n" ,
- ktime_to_ns( ktime_sub( now1 , now0 ) ), bytes * i / sizeof (int) /1024 );
-
- now0 = ktime_get();
- for( k = 0 ; k < i ; k++ )
- memcpy((void*)pg,(void*)src , bytes );
- now1 = ktime_get();
- printk("need %Ld ns to memcpy %d Kbytes \n" ,
- ktime_to_ns( ktime_sub( now1 , now0 ) ), bytes * i / 1024 );
-
- free_pages( pg , PAGE_ORDER );
- return 0x2c;
-}
-#endif
-
-int rknow( int loop , int prtk )
-{
- ktime_t ktime_now;
- struct timespec ts;
- struct rtc_time tm;
-
- if( loop > 20 )
- loop = 20;
- do {
- ktime_now = ktime_get();
- getnstimeofday(&ts);
- rtc_time_to_tm(ts.tv_sec, &tm);
- printk("now=%lld ns "
- "(%d-%02d-%02d %02d:%02d:%02d.%09lu UTC)\n",
- ktime_to_ns(ktime_now),
- tm.tm_year + 1900, tm.tm_mon + 1, tm.tm_mday,
- tm.tm_hour, tm.tm_min, tm.tm_sec, ts.tv_nsec);
- udelay( 31 );
- loop --;
- }while( loop > 0 );
- return 0x2c;
-}
-
-#if 0
-/* 1,2=0 , 0 = lr */
-void rk28_return( void )
-{
- printk("return addr:\n 0: 0x%p " "1: 0x%p " "2: 0x%p\n", __builtin_return_address(0) ,
- __builtin_return_address(1) , __builtin_return_address(2));
-}
-#endif
-
-int dl( int ms )
-{
- mdelay( ms );
- printk("delay %d ms\n" , ms );
- return ms;
-}
-
-int irq_dl( int ms )
-{
- unsigned long flags;
- local_irq_save(flags);
- mdelay( ms );
- local_irq_restore(flags);
- printk("delay %d ms\n" , ms );
- return ms;
-}
-
-/*
- * read a phy addr value , len is word.
-*/
-int dd( unsigned int phy_addr,int len ,unsigned int value )
-{
- int size = len*4;
- unsigned int * ptr;
- int wr = 0;
- int map = 0;
- if( !len ){
- printk("invalid len=%d\n" , len );
- return 0;
- }
- /* we want to write? write 0?*/
- if( value || len == 1 ) {
- size = 4;
- wr = 1;
- }
- if(phy_addr < PAGE_OFFSET ) {
- ptr = (unsigned int *)ioremap( phy_addr , size );
- if( !ptr ) {
- printk("map addr 0x%x failed\n" , phy_addr );
- return -ENOMEM;
- }
- map = 1;
- } else {
- ptr = (unsigned int *)phy_addr;
- }
- if( wr ) {
- *ptr = value ;
- dmb();
- }
- rk28_printk_mem( ptr , len , (unsigned int*)phy_addr );
- if( map ) {
- iounmap(ptr);
- }
- return size;
-}
-
+++ /dev/null
-/*
- * kobj.c
- *
- * (C) Copyright hsl 2009
- * Released under GPL v2.
- *
- *
- * log:
- * for debug function by sysfs
- *
- */
-
-
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-
-#include <linux/fs.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/cdev.h>
-#include <linux/io.h>
-#include <linux/wait.h>
-
-#include <linux/uaccess.h>
-#include <linux/errno.h>
-#include <linux/poll.h>
-#include <linux/timer.h>
-#include <linux/spinlock_types.h>
-#include <linux/string.h>
-#include <linux/sysfs.h>
-#include <linux/delay.h>
-#include <linux/kallsyms.h>
-#include <linux/rtc.h>
-#include <asm/atomic.h>
-#include <asm/signal.h>
-
-static struct kobject *dbg_kobj;
-
-extern int dbg_parse_cmd( char * cdb );
-
-static char dbg_lastcmd[512];
-
-/* default kobject attribute operations */
-static ssize_t dbg_call_attr_show(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf)
-{
- strcpy( buf , dbg_lastcmd );
- strcat(buf,"\n");
- return strlen(buf)+1;
-}
-static ssize_t dbg_call_attr_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t count)
-{
- char cmd[512];
- int len = sizeof(dbg_lastcmd)>count ? count:sizeof(dbg_lastcmd);
- //printk("count=%d,cmd=%s!\n" , count , buf );
- strncpy( dbg_lastcmd , buf , len );
- if( dbg_lastcmd[len-1] == '\n' ){
- dbg_lastcmd[len-1] = 0;
- len--;
- }
- strncpy( cmd , dbg_lastcmd , sizeof(cmd) );
- dbg_parse_cmd( cmd );
- return count;
-}
-
-
-
-static struct kobj_attribute _call_attr = {
- .attr = {
- .name = "dbg",
- .mode = 0644,
- },
- .show = dbg_call_attr_show,
- .store = dbg_call_attr_store,
-};
-
-static struct attribute * g[] = {
- &_call_attr.attr,
- NULL,
-};
-
-static struct attribute_group attr_group = {
- .attrs = g,
-};
-
-
-int dbg_init( void )
-{
- //dbg_kobj = kobject_create_and_add("dbg", NULL ); /*kernel_kobj*/
- //if (!dbg_kobj)
- // return -ENOMEM;
- //return sysfs_create_group(dbg_kobj, &attr_group);
- return sysfs_create_group(kernel_kobj, &attr_group);
-}
-
-late_initcall(dbg_init);
-
+++ /dev/null
-#include <linux/linkage.h>
-#include <asm/memory.h>
-#include <asm/glue.h>
-#include <asm/vfpmacros.h>
-#include <asm/thread_notify.h>
-#include <asm/ptrace.h>
-#include <asm/assembler.h>
-#include <asm/asm-offsets.h>
-#include <mach/rk29_iomap.h>
-
-#__scu_call_wrap:
-#
-# call to the defined funcion.
-# r0: func argument array , max = 6
-# r1: argument num.
-# r2: the function number.
-
-#; EXPORT __scu_call_wrap
-#;
-#; CODE32
-#; AREA ||funwrap||, CODE, READONLY
-ENTRY(__scu_call_wrap)
- STMFD r13!,{r4,r5,r6,lr}
- mov r6,r2
- ldmia r0, {r0-r5}
- STMFD r13!,{r4,r5}
- mov lr , pc
- mov pc , r6
- add r13 , r13 ,#8
- LDMFD r13!,{r4,r5,r6,pc}
-
-/**
- * 20091126,HSL@RK,change to get syscall struct pt_regs *.
- * way: search stack frame for lr = ret_fast_syscall.
- * code from bachtrace.S -- __backtrace.
- * 20110126,not support at 2.6.32(no fp)
- * 20110127,support at debug.c,use c funtion.
- */
-#define frame r4
-#define sv_fp r5
-#define sv_pc r6
-#define mask r7
-#define offset r8
-/*
-ENTRY(__scu_get_usr_regs)
- mov r0, #0
- mov pc, lr
-*/
-
-/*
- * 20091215,continue running from break point.
- * r0 is the struct pt_regs *.
- */
-ENTRY(__scu_bk_continue)
- mov r12, r0
- ldr r0, [r12, #S_PSR]
- msr spsr_cxsf, r0
- ldmia r12, {r0 - pc}^ @ load r0 - pc, cpsr
-
-ENTRY(__run)
- mov r0, r0
- mov pc, lr
-
-
-/* 20110212,HSL@RK, USE parm0 for debug.
- *
- */
-ENTRY(__rb)
- mov r7,r0
-/* adr r0 , __rb_info
- adr r8, __prk
- ldr r8,[r8,#0]
- adr r1 , __rb
- mov lr , pc
- bx r8
- mov r0,#0x10000
- bl __rb_delay
-*/
- mov r8,r7
-/* adr r0 , __prk_info
-1:
- ldrb r1,[r0],#1
- cmp r1,#0
- strne r1,[r8,#0]
- bne 1b
- mov r0,#0x20000
- bl __rb_delay*/
-
- MRC p15,0,r0,c1,c0,0
- BIC r0,r0,#(1<<0) @disable mmu
- BIC r0,r0,#(1<<13) @set vector to 0x00000000
- BIC r0,r0,#(1<<12) @disable I CACHE
- BIC r0,r0,#(1<<2) @disable D DACHE
- BIC r0,r0,#(1<<11) @disable Z
- BIC r0,r0,#(1<<28) @disable TRE
- MCR p15,0,r0,c1,c0,0
- MOV r0,#0
- mcr p15, 0, r0, c7, c10, 5
- mcr p15, 0, r0, c7, c10, 4
- isb
- dsb
- nop
- nop
- nop
-
- adr r7,__regs
-
- ldr r8,[r7,#0x10] @uart1 reg
- adr r3 , __dbg_info
-2:
- ldrb r1,[r3],#1
- cmp r1,#0
- strne r1,[r8,#0]
- bne 2b
-
- mov r0,#0x20000
- bl __rb_delay
-
-wait:
- @b wait
- @arm slow mod.
- ldr r8,[r7,#0xc] @CRU reg
- ldr r9,[r8,#0x10]
- bic r9,r9,#0x3 @CPU slow mode
- bic r9,r9,#(0x3<<2) @Peri slow mode
- str r9,[r8,#0]
- dsb
- mov r0,#0x10000
- bl __rb_delay
-
- @recover SPI clk
- ldr r9,[r8,#0x0c] @CRU_PPLL_CON bit 15=1, Peri PLL power down
- bic r9,r9,#(0x1<<15)
- str r9,[r8,#0x0c]
- dsb
- mov r0,#0x10000
- bl __rb_delay
-
- ldr r9,[r8,#0x2c] @CRU_CLKSEL6_CON bit [8:2] = 7, bit [1:0] =0
- bic r9,r9,#(0x7F<<2)
- bic r9,r9,#(0x3)
- orr r9,r9,#(0x7<<2)
- str r9,[r8,#0x2c]
-
- @recover eMMC clk
- ldr r9,[r8,#0x30] @CRU_CLKSEL7_CON bit [23:18] = 0x17, bit [1:0] = 0
- bic r9,r9,#(0x3F<<18)
- bic r9,r9,#0x3
- orr r9,r9,#(0x17<<18)
- str r9,[r8,#0x30]
-
- @recover UART1 clk
- ldr r9,[r8,#0x34] @CRU_CLKSEL8_CON bit [21:20] = 0x2, bit [19:14] = 0, bit [2:0] = 0
- bic r9,r9,#(0x3<<20)
- bic r9,r9,#(0x3F<<14)
- bic r9,r9,#0x7
- orr r9,r9,#(0x2<<20)
- str r9,[r8,#0x34]
-
- @clk enable
- ldr r9,[r8,#0x5c] @CRU_CLKGATE0_CON
- bic r9,r9,#(0x1<<31) @GRF clk enable
- bic r9,r9,#(0x1<<30) @PMU clk enable
- bic r9,r9,#(0x1<<27) @DEBUG clk enable
- bic r9,r9,#(0x7<<18) @DDR clk enable
- bic r9,r9,#(0x1<<14) @mask rom clk enable
- bic r9,r9,#(0x1<<12) @Int Mem clk enable
- bic r9,r9,#(0x1<<11) @GIC clk enable
- bic r9,r9,#(0xFF) @CPU clk enable
- bic r9,r9,#(0x1<<8)
- str r9,[r8,#0x5c]
-
- ldr r9,[r8,#0x60] @CRU_CLKGATE1_CON
- bic r9,r9,#(0x3<<25) @USB clk enable
- bic r9,r9,#(0x3<<23) @eMMC clk enable
- bic r9,r9,#(0x1<<16) @NANC clk enable
- bic r9,r9,#(0x1<<6) @DDR PERIPH AXI clk enable
- bic r9,r9,#0x17 @PERIPH clk enable
- str r9,[r8,#0x60]
-
- ldr r9,[r8,#0x64] @CRU_CLKGATE2_CON
- bic r9,r9,#(0x1<<26) @JTAG clk enable
- bic r9,r9,#(0x1<<15) @SPI0 clk enable
- bic r9,r9,#0x1 @UART1 clk enable
- str r9,[r8,#0x64]
-
- @soft de-reset
- ldr r9,[r8,#0x6c] @CRU_SOFTRST0_CON
- bic r9,r9,#(0x1<<25) @ARM core DEBUG soft de-reset
- bic r9,r9,#(0x1<<12) @mask rom soft de-reset
- bic r9,r9,#(0x1<<9) @Int Mem soft de-reset
- bic r9,r9,#(0x1<<8) @GIC soft de-reset
- bic r9,r9,#0x3F @CPU soft de-reset
- str r9,[r8,#0x6c]
-
- ldr r9,[r8,#0x70] @CRU_SOFTRST1_CON
- bic r9,r9,#(0x1<<28) @UART1 soft de-reset
- bic r9,r9,#(0x1<<25) @SPI0 soft de-reset
- bic r9,r9,#(0x7<<16) @USB0 soft de-reset
- bic r9,r9,#(0x1<<15) @EMMC soft de-reset
- bic r9,r9,#(0x1<<9) @NANC soft de-reset
- bic r9,r9,#0x3F @PERIPH soft de-reset
- str r9,[r8,#0x70]
-
- ldr r9,[r8,#0x74] @CRU_SOFTRST2_CON
- bic r9,r9,#(0x1F<<8) @DDR soft de-reset
- str r9,[r8,#0x74]
-
- @ unremap, and axi.
- ldr r8,[r7,#0] @GRF reg
- ldr r9,[r8,#0xc0]
- bic r9,r9,#(1<<21)
- str r9,[r8,#0xc0]
-
- mov r9,#0
- ldr r8,[r7,#4] @CPU_AXI_BUS0
- str r9,[r8,#0]
-
- ldr r8,[r7,#8] @AXI1
- str r9,[r8,#0]
- dsb
-
- @eMMC register recover
- ldr r8,[r7,#0] @GRF reg
- ldr r9,[r8,#0xbc] @GRF_SOC_CON0
- bic r9,r9,#(0x1<<9) @emmc_and_boot_en control=0
- str r9,[r8,#0xbc]
-
- ldr r8,[r7,#14] @eMMC reg
- mov r9,#0
- str r9,[r8,#0xc] @SDMMC_CLKSRC=0, clk_source=clock divider 0
- str r9,[r8,#0x18] @SDMMC_CTYPE=0, card_width=1 bit mode
- mov r9,#0x200
- str r9,[r8,#0x1c] @SDMMC_BLKSIZ=0x200, Block size=512
-
- ldr r8,[r7,#0x10] @uart1_reg
- adr r0 , __dbg_info1
-3:
- ldrb r1,[r0],#1
- cmp r1,#0
- strne r1,[r8,#0]
- bne 3b
-
- mov r0,#0x10000
- bl __rb_delay
-
- mov r4, #0
- mov pc, r4
-
-__prk:
- .long printk
-__rb_info:
- .asciz "at reboot function,pc=0x%x\n"
-__prk_info:
- .asciz "after printk!\n\r"
-__dbg_info:
- .asciz "AFTER DIS MMU\n\r"
-__dbg_info1:
- .asciz "LAST JUMP TO 0\n\r"
- .align
-__regs:
- .long RK29_GRF_PHYS @ 0x20008000 , unremap
- .long RK29_CPU_AXI_BUS0_PHYS @ 0x15000000
- .long RK29_AXI1_PHYS @ 0x10000000
- .long RK29_CRU_PHYS @ 0x20000000
- .long RK29_UART1_PHYS @ 0x20060000 , printk for debug.
- .long RK29_EMMC_PHYS @ 0x1021C000
- .align
-
-__rb_delay:
- subs r0, r0, #1
- bhi __rb_delay
- mov pc, lr
-
-#if FIQ_ENABLE
- .align
-ENTRY(rk28_fiq_handle)
- mrs r8, spsr
- adr r9,__fiq_save
- stmia r9 , {r0-r8,lr}
- mov r0,r9 @save addr.
- mov r5,#(SVC_MODE|PSR_I_BIT|PSR_F_BIT)
- msr cpsr_cxsf,r5 @ to svc mod.disable irq,fiq.
- sub r1, sp, #(S_FRAME_SIZE)
-
- add r2 , r1 , #32 @ r0--r7.
- stmia r2,{r8-lr} @ the svc sp not change here.
- ldmia r0,{r3-r10}
- stmia r1,{r3-r10}
- ldr r9,[r0,#36] @get fiq lr.
- sub r9,r9,#4
- str r9 , [r1,#S_PC]
- ldr r10,[r0,#32] @get fiq spsr.
- str r10, [r1,#S_PSR]
- mov r5,r1
- mov sp,r5 @stack frame
- mov r0,r5
- ldr r11,1f
- blx r11
- b 3f
-1:
- .long rk28_debug_fiq
-3:
- msr spsr_cxsf,r10
- ldmia r5, {r0 - pc}^
-__fiq_save: @for save fiq spsr r0-r7,spsr,lr.
- .long 0
- .previous
-#endif
-
projects / firefly-linux-kernel-4.4.55.git / commitdiff