[ARM] tegra: fix packet alignment and padding

tegra's DMA controller expects to start transfers at word boundaries,
and the standard packet alignment (2) was resulting in data corruption

also, provide a full cacheline of padding between skbuffs, to eliminate
coherency issues between the processor and USB networking devices.

Change-Id: Ibb508b512f43c8934d35eb182c8738370b7be585
Signed-off-by: Gary King <gking@nvidia.com>

diff --git a/arch/arm/mach-tegra/include/mach/memory.h b/arch/arm/mach-tegra/include/mach/memory.h
index 6151bab62af207078960e8df6518ed6f55fd85f9..4ebc3e055ed1eb10fe460e94685d9e954082ca4f 100644 (file)
--- a/arch/arm/mach-tegra/include/mach/memory.h
+++ b/arch/arm/mach-tegra/include/mach/memory.h
@@ -24,5 +24,8 @@
 /* physical offset of RAM */
 #define PHYS_OFFSET            UL(0)
 
+#define NET_IP_ALIGN   0
+#define NET_SKB_PAD    L1_CACHE_BYTES
+
 #endif