gpio/davinci: add interrupt support for GPIOs 16-31

Interrupts for GPIOs 16 through 31 are enabled by bit 1 in the
"binten" register (offset 8). Previous versions of GPIO only
used bit 0, which enables GPIO 0-15 interrupts.

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c
index c5e05c82d67c6c2cd8fdeac5996413e99455a3d1..86cfe1892caea0f0cd4d3a76590e245e52943362 100644 (file)
--- a/drivers/gpio/gpio-davinci.c
+++ b/drivers/gpio/gpio-davinci.c
@@ -545,7 +545,7 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev)
                chips[0].chip.to_irq = gpio_to_irq_unbanked;
                chips[0].gpio_irq = bank_irq;
                chips[0].gpio_unbanked = pdata->gpio_unbanked;
-               binten = BIT(0);
+               binten = GENMASK(pdata->gpio_unbanked / 16, 0);
 
                /* AINTC handles mask/unmask; GPIO handles triggering */
                irq = bank_irq;