Fix a bug in the coalescer where it didn't check if a live interval existed before...

was exposed by fast isel's handling of shifts on X86-64.  With this, FreeBench/pcompress2 passes on X86-64 in fast isel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56067 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SimpleRegisterCoalescing.cpp b/lib/CodeGen/SimpleRegisterCoalescing.cpp
index cca891d7735ee7bf1a8c31d8b678d8ea09539fba..c6d4576e9c9306c9e2371ecda92896b1a3d90550 100644 (file)
--- a/lib/CodeGen/SimpleRegisterCoalescing.cpp
+++ b/lib/CodeGen/SimpleRegisterCoalescing.cpp
@@ -464,7 +464,7 @@ bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
     MachineOperand &MO = CopyMI->getOperand(i);
     if (MO.isReg() && MO.isImplicit())
       NewMI->addOperand(MO);
-    if (MO.isDef()) {
+    if (MO.isDef() && li_->hasInterval(MO.getReg())) {
       unsigned Reg = MO.getReg();
       DLR = li_->getInterval(Reg).getLiveRangeContaining(DefIdx);
       if (DLR && DLR->valno->copy == CopyMI)