drm/i915: s/_TRANSA_CHICKEN/TRANS_CHICKEN(PIPE_A)/

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8e4fb80497a16e0e7b158ac7c8bc06467176e2cf..e7a3c1b4fc561bdb0b4c4ffc84c6b33fc9b9c9db 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2050,9 +2050,9 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
        assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
 
        /* Workaround: set timing override bit. */
-       val = I915_READ(_TRANSA_CHICKEN2);
+       val = I915_READ(TRANS_CHICKEN2(PIPE_A));
        val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
-       I915_WRITE(_TRANSA_CHICKEN2, val);
+       I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
 
        val = TRANS_ENABLE;
        pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
@@ -2110,9 +2110,9 @@ static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
                DRM_ERROR("Failed to disable PCH transcoder\n");
 
        /* Workaround: clear timing override bit. */
-       val = I915_READ(_TRANSA_CHICKEN2);
+       val = I915_READ(TRANS_CHICKEN2(PIPE_A));
        val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
-       I915_WRITE(_TRANSA_CHICKEN2, val);
+       I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
 }
 
 /**

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9643a7c433d8080d81d2cf3e2b7a3ca356b223e7..cb409c2f7860b917b0fa78e4f956eceeaa754771 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6640,8 +6640,8 @@ static void lpt_init_clock_gating(struct drm_device *dev)
                           PCH_LP_PARTITION_LEVEL_DISABLE);
 
        /* WADPOClockGatingDisable:hsw */
-       I915_WRITE(_TRANSA_CHICKEN1,
-                  I915_READ(_TRANSA_CHICKEN1) |
+       I915_WRITE(TRANS_CHICKEN1(PIPE_A),
+                  I915_READ(TRANS_CHICKEN1(PIPE_A)) |
                   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
 }