call computeRegisterProperties

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29780 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 56d61165c3c3d4793ab3e8133423ad5a76b17b96..cf23f2a4409a2878fbee2fd9f3b54f23f128886d 100644 (file)
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -42,11 +42,17 @@ namespace {
 
 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
   : TargetLowering(TM) {
+  addRegisterClass(MVT::i32, ARM::IntRegsRegisterClass);
+
+  //LLVM requires that a register class supports MVT::f64!
+  addRegisterClass(MVT::f64, ARM::IntRegsRegisterClass);
+
   setOperationAction(ISD::RET,           MVT::Other, Custom);
   setOperationAction(ISD::GlobalAddress, MVT::i32,   Custom);
   setOperationAction(ISD::ConstantPool,  MVT::i32,   Custom);
 
   setSchedulingPreference(SchedulingForRegPressure);
+  computeRegisterProperties();
 }
 
 namespace llvm {