Add operand encoding for Thumb2 subw SP + imm. rdar://8745434

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121310 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index 6e71dcb6692d7457c9f2fd3c9c7a85e6b45b2d59..108a96e4d022c873ece47704412ac1d2c92c7a50 100644 (file)
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -1195,12 +1195,16 @@ def t2SUBrSPi   : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$sp, t2_so_imm:$imm),
 }
 def t2SUBrSPi12 : T2TwoRegImm<(outs GPR:$Rd), (ins GPR:$sp, imm0_4095:$imm),
                        IIC_iALUi, "subw", "\t$Rd, $sp, $imm", []> {
+  bits<4> Rd;
+  bits<12> imm;
   let Inst{31-27} = 0b11110;
-  let Inst{25} = 1;
-  let Inst{24-21} = 0b0101;
-  let Inst{20} = 0; // The S bit.
+  let Inst{26} = imm{11};
+  let Inst{25-20} = 0b101010;
   let Inst{19-16} = 0b1101; // Rn = sp
   let Inst{15} = 0;
+  let Inst{14-12} = imm{10-8};
+  let Inst{11-8} = Rd;
+  let Inst{7-0} = imm{7-0};
 }
 
 // SUB r, sp, so_reg