$(Echo) "Building $(<F) \"fast\" instruction selector implementation with tblgen"
$(Verb) $(TableGen) -gen-fast-isel -o $(call SYSPATH, $@) $<
-$(TARGET:%=$(ObjDir)/%GenSubtarget.inc.tmp): \
-$(ObjDir)/%GenSubtarget.inc.tmp : %.td $(ObjDir)/.dir
+$(TARGET:%=$(ObjDir)/%GenSubtargetInfo.inc.tmp): \
+$(ObjDir)/%GenSubtargetInfo.inc.tmp : %.td $(ObjDir)/.dir
$(Echo) "Building $(<F) subtarget information with tblgen"
$(Verb) $(TableGen) -gen-subtarget -o $(call SYSPATH, $@) $<
#define GET_SUBTARGETINFO_CTOR
#define GET_SUBTARGETINFO_MC_DESC
#define GET_SUBTARGETINFO_TARGET_DESC
-#include "ARMGenSubtarget.inc"
+#include "ARMGenSubtargetInfo.inc"
using namespace llvm;
#include <string>
#define GET_SUBTARGETINFO_HEADER
-#include "ARMGenSubtarget.inc"
+#include "ARMGenSubtargetInfo.inc"
namespace llvm {
class GlobalValue;
tablegen(ARMGenDAGISel.inc -gen-dag-isel)
tablegen(ARMGenFastISel.inc -gen-fast-isel)
tablegen(ARMGenCallingConv.inc -gen-callingconv)
-tablegen(ARMGenSubtarget.inc -gen-subtarget)
+tablegen(ARMGenSubtargetInfo.inc -gen-subtarget)
tablegen(ARMGenEDInfo.inc -gen-enhanced-disassembly-info)
tablegen(ARMGenDecoderTables.inc -gen-arm-decoder)
# Make sure that tblgen is run, first thing.
BUILT_SOURCES = ARMGenRegisterInfo.inc ARMGenInstrInfo.inc \
ARMGenAsmWriter.inc ARMGenAsmMatcher.inc \
- ARMGenDAGISel.inc ARMGenSubtarget.inc \
+ ARMGenDAGISel.inc ARMGenSubtargetInfo.inc \
ARMGenCodeEmitter.inc ARMGenCallingConv.inc \
ARMGenDecoderTables.inc ARMGenEDInfo.inc \
ARMGenFastISel.inc ARMGenMCCodeEmitter.inc
#include "AlphaSubtarget.h"
#include "Alpha.h"
-#include "AlphaGenSubtarget.inc"
#define GET_SUBTARGETINFO_CTOR
#define GET_SUBTARGETINFO_MC_DESC
#define GET_SUBTARGETINFO_TARGET_DESC
-#include "AlphaGenSubtarget.inc"
+#include "AlphaGenSubtargetInfo.inc"
using namespace llvm;
#include <string>
#define GET_SUBTARGETINFO_HEADER
-#include "AlphaGenSubtarget.inc"
+#include "AlphaGenSubtargetInfo.inc"
namespace llvm {
tablegen(AlphaGenAsmWriter.inc -gen-asm-writer)
tablegen(AlphaGenDAGISel.inc -gen-dag-isel)
tablegen(AlphaGenCallingConv.inc -gen-callingconv)
-tablegen(AlphaGenSubtarget.inc -gen-subtarget)
+tablegen(AlphaGenSubtargetInfo.inc -gen-subtarget)
add_llvm_target(AlphaCodeGen
AlphaAsmPrinter.cpp
# Make sure that tblgen is run, first thing.
BUILT_SOURCES = AlphaGenRegisterInfo.inc AlphaGenInstrInfo.inc \
AlphaGenAsmWriter.inc AlphaGenDAGISel.inc \
- AlphaGenCallingConv.inc AlphaGenSubtarget.inc
+ AlphaGenCallingConv.inc AlphaGenSubtargetInfo.inc
DIRS = TargetInfo
#define GET_SUBTARGETINFO_CTOR
#define GET_SUBTARGETINFO_MC_DESC
#define GET_SUBTARGETINFO_TARGET_DESC
-#include "BlackfinGenSubtarget.inc"
+#include "BlackfinGenSubtargetInfo.inc"
using namespace llvm;
#include <string>
#define GET_SUBTARGETINFO_HEADER
-#include "BlackfinGenSubtarget.inc"
+#include "BlackfinGenSubtargetInfo.inc"
namespace llvm {
tablegen(BlackfinGenInstrInfo.inc -gen-instr-info)
tablegen(BlackfinGenAsmWriter.inc -gen-asm-writer)
tablegen(BlackfinGenDAGISel.inc -gen-dag-isel)
-tablegen(BlackfinGenSubtarget.inc -gen-subtarget)
+tablegen(BlackfinGenSubtargetInfo.inc -gen-subtarget)
tablegen(BlackfinGenCallingConv.inc -gen-callingconv)
tablegen(BlackfinGenIntrinsics.inc -gen-tgt-intrinsic)
# Make sure that tblgen is run, first thing.
BUILT_SOURCES = BlackfinGenRegisterInfo.inc BlackfinGenInstrInfo.inc \
BlackfinGenAsmWriter.inc \
- BlackfinGenDAGISel.inc BlackfinGenSubtarget.inc \
+ BlackfinGenDAGISel.inc BlackfinGenSubtargetInfo.inc \
BlackfinGenCallingConv.inc BlackfinGenIntrinsics.inc
DIRS = TargetInfo
tablegen(SPUGenRegisterInfo.inc -gen-register-info)
tablegen(SPUGenInstrInfo.inc -gen-instr-info)
tablegen(SPUGenDAGISel.inc -gen-dag-isel)
-tablegen(SPUGenSubtarget.inc -gen-subtarget)
+tablegen(SPUGenSubtargetInfo.inc -gen-subtarget)
tablegen(SPUGenCallingConv.inc -gen-callingconv)
add_llvm_target(CellSPUCodeGen
BUILT_SOURCES = SPUGenInstrInfo.inc SPUGenRegisterInfo.inc \
SPUGenAsmWriter.inc SPUGenCodeEmitter.inc \
SPUGenDAGISel.inc \
- SPUGenSubtarget.inc SPUGenCallingConv.inc
+ SPUGenSubtargetInfo.inc SPUGenCallingConv.inc
DIRS = TargetInfo
#define GET_SUBTARGETINFO_CTOR
#define GET_SUBTARGETINFO_MC_DESC
#define GET_SUBTARGETINFO_TARGET_DESC
-#include "SPUGenSubtarget.inc"
+#include "SPUGenSubtargetInfo.inc"
using namespace llvm;
#include <string>
#define GET_SUBTARGETINFO_HEADER
-#include "SPUGenSubtarget.inc"
+#include "SPUGenSubtargetInfo.inc"
namespace llvm {
class GlobalValue;
tablegen(MBlazeGenAsmMatcher.inc -gen-asm-matcher)
tablegen(MBlazeGenDAGISel.inc -gen-dag-isel)
tablegen(MBlazeGenCallingConv.inc -gen-callingconv)
-tablegen(MBlazeGenSubtarget.inc -gen-subtarget)
+tablegen(MBlazeGenSubtargetInfo.inc -gen-subtarget)
tablegen(MBlazeGenIntrinsics.inc -gen-tgt-intrinsic)
tablegen(MBlazeGenEDInfo.inc -gen-enhanced-disassembly-info)
#define GET_SUBTARGETINFO_CTOR
#define GET_SUBTARGETINFO_MC_DESC
#define GET_SUBTARGETINFO_TARGET_DESC
-#include "MBlazeGenSubtarget.inc"
+#include "MBlazeGenSubtargetInfo.inc"
using namespace llvm;
#include <string>
#define GET_SUBTARGETINFO_HEADER
-#include "MBlazeGenSubtarget.inc"
+#include "MBlazeGenSubtargetInfo.inc"
namespace llvm {
MBlazeGenAsmWriter.inc \
MBlazeGenDAGISel.inc MBlazeGenAsmMatcher.inc \
MBlazeGenCodeEmitter.inc MBlazeGenCallingConv.inc \
- MBlazeGenSubtarget.inc MBlazeGenIntrinsics.inc \
+ MBlazeGenSubtargetInfo.inc MBlazeGenIntrinsics.inc \
MBlazeGenEDInfo.inc
DIRS = InstPrinter AsmParser Disassembler TargetInfo
tablegen(MSP430GenAsmWriter.inc -gen-asm-writer)
tablegen(MSP430GenDAGISel.inc -gen-dag-isel)
tablegen(MSP430GenCallingConv.inc -gen-callingconv)
-tablegen(MSP430GenSubtarget.inc -gen-subtarget)
+tablegen(MSP430GenSubtargetInfo.inc -gen-subtarget)
add_llvm_target(MSP430CodeGen
MSP430BranchSelector.cpp
#define GET_SUBTARGETINFO_CTOR
#define GET_SUBTARGETINFO_MC_DESC
#define GET_SUBTARGETINFO_TARGET_DESC
-#include "MSP430GenSubtarget.inc"
+#include "MSP430GenSubtargetInfo.inc"
using namespace llvm;
#include "llvm/Target/TargetSubtargetInfo.h"
#define GET_SUBTARGETINFO_HEADER
-#include "MSP430GenSubtarget.inc"
+#include "MSP430GenSubtargetInfo.inc"
#include <string>
BUILT_SOURCES = MSP430GenRegisterInfo.inc MSP430GenInstrInfo.inc \
MSP430GenAsmWriter.inc \
MSP430GenDAGISel.inc MSP430GenCallingConv.inc \
- MSP430GenSubtarget.inc
+ MSP430GenSubtargetInfo.inc
DIRS = InstPrinter TargetInfo
tablegen(MipsGenAsmWriter.inc -gen-asm-writer)
tablegen(MipsGenDAGISel.inc -gen-dag-isel)
tablegen(MipsGenCallingConv.inc -gen-callingconv)
-tablegen(MipsGenSubtarget.inc -gen-subtarget)
+tablegen(MipsGenSubtargetInfo.inc -gen-subtarget)
add_llvm_target(MipsCodeGen
MipsAsmPrinter.cpp
BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrInfo.inc \
MipsGenAsmWriter.inc \
MipsGenDAGISel.inc MipsGenCallingConv.inc \
- MipsGenSubtarget.inc
+ MipsGenSubtargetInfo.inc
DIRS = TargetInfo
#define GET_SUBTARGETINFO_CTOR
#define GET_SUBTARGETINFO_MC_DESC
#define GET_SUBTARGETINFO_TARGET_DESC
-#include "MipsGenSubtarget.inc"
+#include "MipsGenSubtargetInfo.inc"
using namespace llvm;
#include <string>
#define GET_SUBTARGETINFO_HEADER
-#include "MipsGenSubtarget.inc"
+#include "MipsGenSubtargetInfo.inc"
namespace llvm {
tablegen(PTXGenDAGISel.inc -gen-dag-isel)
tablegen(PTXGenInstrInfo.inc -gen-instr-info)
tablegen(PTXGenRegisterInfo.inc -gen-register-info)
-tablegen(PTXGenSubtarget.inc -gen-subtarget)
+tablegen(PTXGenSubtargetInfo.inc -gen-subtarget)
add_llvm_target(PTXCodeGen
PTXAsmPrinter.cpp
PTXGenDAGISel.inc \
PTXGenInstrInfo.inc \
PTXGenRegisterInfo.inc \
- PTXGenSubtarget.inc
+ PTXGenSubtargetInfo.inc
DIRS = TargetInfo
#define GET_SUBTARGETINFO_CTOR
#define GET_SUBTARGETINFO_MC_DESC
#define GET_SUBTARGETINFO_TARGET_DESC
-#include "PTXGenSubtarget.inc"
+#include "PTXGenSubtargetInfo.inc"
using namespace llvm;
case PTX_VERSION_2_3: return "2.3";
}
}
-
-#include "PTXGenSubtarget.inc"
#include "llvm/Target/TargetSubtargetInfo.h"
#define GET_SUBTARGETINFO_HEADER
-#include "PTXGenSubtarget.inc"
+#include "PTXGenSubtargetInfo.inc"
namespace llvm {
class PTXSubtarget : public PTXGenSubtargetInfo {
tablegen(PPCGenInstrInfo.inc -gen-instr-info)
tablegen(PPCGenDAGISel.inc -gen-dag-isel)
tablegen(PPCGenCallingConv.inc -gen-callingconv)
-tablegen(PPCGenSubtarget.inc -gen-subtarget)
+tablegen(PPCGenSubtargetInfo.inc -gen-subtarget)
add_llvm_target(PowerPCCodeGen
PPCAsmBackend.cpp
BUILT_SOURCES = PPCGenRegisterInfo.inc \
PPCGenAsmWriter.inc PPCGenCodeEmitter.inc \
PPCGenInstrInfo.inc PPCGenDAGISel.inc \
- PPCGenSubtarget.inc PPCGenCallingConv.inc \
+ PPCGenSubtargetInfo.inc PPCGenCallingConv.inc \
PPCGenMCCodeEmitter.inc
DIRS = InstPrinter TargetInfo
#define GET_SUBTARGETINFO_CTOR
#define GET_SUBTARGETINFO_MC_DESC
#define GET_SUBTARGETINFO_TARGET_DESC
-#include "PPCGenSubtarget.inc"
+#include "PPCGenSubtargetInfo.inc"
using namespace llvm;
#include <string>
#define GET_SUBTARGETINFO_HEADER
-#include "PPCGenSubtarget.inc"
+#include "PPCGenSubtargetInfo.inc"
// GCC #defines PPC on Linux but we use it as our namespace name
#undef PPC
tablegen(SparcGenInstrInfo.inc -gen-instr-info)
tablegen(SparcGenAsmWriter.inc -gen-asm-writer)
tablegen(SparcGenDAGISel.inc -gen-dag-isel)
-tablegen(SparcGenSubtarget.inc -gen-subtarget)
+tablegen(SparcGenSubtargetInfo.inc -gen-subtarget)
tablegen(SparcGenCallingConv.inc -gen-callingconv)
add_llvm_target(SparcCodeGen
# Make sure that tblgen is run, first thing.
BUILT_SOURCES = SparcGenRegisterInfo.inc SparcGenInstrInfo.inc \
- SparcGenAsmWriter.inc \
- SparcGenDAGISel.inc SparcGenSubtarget.inc SparcGenCallingConv.inc
+ SparcGenAsmWriter.inc SparcGenDAGISel.inc \
+ SparcGenSubtargetInfo.inc SparcGenCallingConv.inc
DIRS = TargetInfo
#define GET_SUBTARGETINFO_CTOR
#define GET_SUBTARGETINFO_MC_DESC
#define GET_SUBTARGETINFO_TARGET_DESC
-#include "SparcGenSubtarget.inc"
+#include "SparcGenSubtargetInfo.inc"
using namespace llvm;
#include <string>
#define GET_SUBTARGETINFO_HEADER
-#include "SparcGenSubtarget.inc"
+#include "SparcGenSubtargetInfo.inc"
namespace llvm {
tablegen(SystemZGenAsmWriter.inc -gen-asm-writer)
tablegen(SystemZGenDAGISel.inc -gen-dag-isel)
tablegen(SystemZGenCallingConv.inc -gen-callingconv)
-tablegen(SystemZGenSubtarget.inc -gen-subtarget)
+tablegen(SystemZGenSubtargetInfo.inc -gen-subtarget)
add_llvm_target(SystemZCodeGen
SystemZAsmPrinter.cpp
# Make sure that tblgen is run, first thing.
BUILT_SOURCES = SystemZGenRegisterInfo.inc SystemZGenInstrInfo.inc \
- SystemZGenAsmWriter.inc \
- SystemZGenDAGISel.inc SystemZGenSubtarget.inc SystemZGenCallingConv.inc
+ SystemZGenAsmWriter.inc SystemZGenDAGISel.inc \
+ SystemZGenSubtargetInfo.inc SystemZGenCallingConv.inc
DIRS = TargetInfo
#define GET_SUBTARGETINFO_CTOR
#define GET_SUBTARGETINFO_MC_DESC
#define GET_SUBTARGETINFO_TARGET_DESC
-#include "SystemZGenSubtarget.inc"
+#include "SystemZGenSubtargetInfo.inc"
using namespace llvm;
#include <string>
#define GET_SUBTARGETINFO_HEADER
-#include "SystemZGenSubtarget.inc"
+#include "SystemZGenSubtargetInfo.inc"
namespace llvm {
class GlobalValue;
tablegen(X86GenDAGISel.inc -gen-dag-isel)
tablegen(X86GenFastISel.inc -gen-fast-isel)
tablegen(X86GenCallingConv.inc -gen-callingconv)
-tablegen(X86GenSubtarget.inc -gen-subtarget)
+tablegen(X86GenSubtargetInfo.inc -gen-subtarget)
tablegen(X86GenEDInfo.inc -gen-enhanced-disassembly-info)
set(sources
#include "X86GenInstrInfo.inc"
#define GET_SUBTARGETINFO_MC_DESC
-#include "X86GenSubtarget.inc"
+#include "X86GenSubtargetInfo.inc"
using namespace llvm;
X86GenAsmWriter.inc X86GenAsmMatcher.inc \
X86GenAsmWriter1.inc X86GenDAGISel.inc \
X86GenDisassemblerTables.inc X86GenFastISel.inc \
- X86GenCallingConv.inc X86GenSubtarget.inc \
+ X86GenCallingConv.inc X86GenSubtargetInfo.inc \
X86GenEDInfo.inc
DIRS = InstPrinter AsmParser Disassembler TargetInfo MCTargetDesc Utils
#define GET_SUBTARGETINFO_CTOR
#define GET_SUBTARGETINFO_MC_DESC
#define GET_SUBTARGETINFO_TARGET_DESC
-#include "X86GenSubtarget.inc"
+#include "X86GenSubtargetInfo.inc"
using namespace llvm;
#include <string>
#define GET_SUBTARGETINFO_HEADER
-#include "X86GenSubtarget.inc"
+#include "X86GenSubtargetInfo.inc"
namespace llvm {
class GlobalValue;
tablegen(XCoreGenAsmWriter.inc -gen-asm-writer)
tablegen(XCoreGenDAGISel.inc -gen-dag-isel)
tablegen(XCoreGenCallingConv.inc -gen-callingconv)
-tablegen(XCoreGenSubtarget.inc -gen-subtarget)
+tablegen(XCoreGenSubtargetInfo.inc -gen-subtarget)
add_llvm_target(XCoreCodeGen
XCoreAsmPrinter.cpp
BUILT_SOURCES = XCoreGenRegisterInfo.inc XCoreGenInstrInfo.inc \
XCoreGenAsmWriter.inc \
XCoreGenDAGISel.inc XCoreGenCallingConv.inc \
- XCoreGenSubtarget.inc
+ XCoreGenSubtargetInfo.inc
DIRS = TargetInfo
#define GET_SUBTARGETINFO_CTOR
#define GET_SUBTARGETINFO_MC_DESC
#define GET_SUBTARGETINFO_TARGET_DESC
-#include "XCoreGenSubtarget.inc"
+#include "XCoreGenSubtargetInfo.inc"
using namespace llvm;
#include <string>
#define GET_SUBTARGETINFO_HEADER
-#include "XCoreGenSubtarget.inc"
+#include "XCoreGenSubtargetInfo.inc"
namespace llvm {