git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110762
91177308-0d34-0410-b5e6-
96231b3b80d8
AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpValue) const {
switch (MI->getOpcode()) {
default: break;
+ case ARM::CMPri:
+ case ARM::CMPzri:
case ARM::t2CMPri:
case ARM::t2CMPzri:
SrcReg = MI->getOperand(0).getReg();
// Set the "zero" bit in CPSR.
switch (MI->getOpcode()) {
default: break;
+ case ARM::ADDri:
+ case ARM::SUBri:
+ case ARM::t2ADDri:
case ARM::t2SUBri: {
MI->RemoveOperand(5);
MachineInstrBuilder MB(MI);