Specify the value type for the register, not just the size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7357 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/SparcV9/SparcV9_Reg.td b/lib/Target/SparcV9/SparcV9_Reg.td
index 3997e031fe181a42ac80561270ea074c1e41564c..136620e78808e7064ffa32f9579c046ae44923f1 100644 (file)
--- a/lib/Target/SparcV9/SparcV9_Reg.td
+++ b/lib/Target/SparcV9/SparcV9_Reg.td
@@ -9,7 +9,10 @@
 class V9Reg : Register { set Namespace = "SparcV9"; }
 
 // Ri - One of the 32 64 bit integer registers
-class Ri<bits<5> num> : V9Reg { set Size = 64; field bits<5> Num = num; }
+class Ri<bits<5> num> : V9Reg {
+  set RegType = i64;              // All integer registers are 64 bits in size
+  field bits<5> Num = num;        // Numbers are identified with a 5 bit ID
+}
 
 def G0 : Ri< 0>;    def G1 : Ri< 1>;    def G2 : Ri< 2>;    def G3 : Ri< 3>;
 def G4 : Ri< 4>;    def G5 : Ri< 5>;    def G6 : Ri< 6>;    def G7 : Ri< 7>;