davinci: Add NAND flash support for DA850/OMAP-L138
authorSudhakar Rajashekhara <sudhakar.raj@ti.com>
Thu, 13 Aug 2009 20:21:11 +0000 (16:21 -0400)
committerKevin Hilman <khilman@deeprootsystems.com>
Wed, 26 Aug 2009 08:55:56 +0000 (11:55 +0300)
This patch adds platform data for the 512MB NAND Flash
found on DA850/OMAP-L138 EVM. Currently it supports
only 1-bit ECC.

Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
arch/arm/mach-davinci/board-da850-evm.c
arch/arm/mach-davinci/da850.c
arch/arm/mach-davinci/include/mach/da8xx.h
arch/arm/mach-davinci/include/mach/mux.h

index eb998ce6d46573c0cc77e1d7ebb0dae0a68c6920..62d37cb6f29d26388290637ffdf0b46da0d566bd 100644 (file)
 #include <linux/i2c.h>
 #include <linux/i2c/at24.h>
 #include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -26,6 +30,7 @@
 #include <mach/irqs.h>
 #include <mach/cp_intc.h>
 #include <mach/da8xx.h>
+#include <mach/nand.h>
 
 #define DA850_EVM_PHY_MASK             0x1
 #define DA850_EVM_MDIO_FREQUENCY       2200000 /* PHY bus frequency */
 #define DA850_MMCSD_CD_PIN             GPIO_TO_PIN(4, 0)
 #define DA850_MMCSD_WP_PIN             GPIO_TO_PIN(4, 1)
 
+/* DA850/OMAP-L138 EVM includes a 512 MByte large-page NAND flash
+ * (128K blocks). It may be used instead of the (default) SPI flash
+ * to boot, using TI's tools to install the secondary boot loader
+ * (UBL) and U-Boot.
+ */
+struct mtd_partition da850_evm_nandflash_partition[] = {
+       {
+               .name           = "u-boot env",
+               .offset         = 0,
+               .size           = SZ_128K,
+               .mask_flags     = MTD_WRITEABLE,
+        },
+       {
+               .name           = "UBL",
+               .offset         = MTDPART_OFS_APPEND,
+               .size           = SZ_128K,
+               .mask_flags     = MTD_WRITEABLE,
+       },
+       {
+               .name           = "u-boot",
+               .offset         = MTDPART_OFS_APPEND,
+               .size           = 4 * SZ_128K,
+               .mask_flags     = MTD_WRITEABLE,
+       },
+       {
+               .name           = "kernel",
+               .offset         = 0x200000,
+               .size           = SZ_2M,
+               .mask_flags     = 0,
+       },
+       {
+               .name           = "filesystem",
+               .offset         = MTDPART_OFS_APPEND,
+               .size           = MTDPART_SIZ_FULL,
+               .mask_flags     = 0,
+       },
+};
+
+static struct davinci_nand_pdata da850_evm_nandflash_data = {
+       .parts          = da850_evm_nandflash_partition,
+       .nr_parts       = ARRAY_SIZE(da850_evm_nandflash_partition),
+       .ecc_mode       = NAND_ECC_HW,
+       .options        = NAND_USE_FLASH_BBT,
+};
+
+static struct resource da850_evm_nandflash_resource[] = {
+       {
+               .start  = DA8XX_AEMIF_CS3_BASE,
+               .end    = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               .start  = DA8XX_AEMIF_CTL_BASE,
+               .end    = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct platform_device da850_evm_nandflash_device = {
+       .name           = "davinci_nand",
+       .id             = 1,
+       .dev            = {
+               .platform_data  = &da850_evm_nandflash_data,
+       },
+       .num_resources  = ARRAY_SIZE(da850_evm_nandflash_resource),
+       .resource       = da850_evm_nandflash_resource,
+};
+
 static struct davinci_i2c_platform_data da850_evm_i2c_0_pdata = {
        .bus_freq       = 100,  /* kHz */
        .bus_delay      = 0,    /* usec */
@@ -45,6 +118,10 @@ static struct davinci_uart_config da850_evm_uart_config __initdata = {
        .enabled_uarts = 0x7,
 };
 
+static struct platform_device *da850_evm_devices[] __initdata = {
+       &da850_evm_nandflash_device,
+};
+
 /* davinci da850 evm audio machine driver */
 static u8 da850_iis_serializer_direction[] = {
        INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,
@@ -120,6 +197,14 @@ static __init void da850_evm_init(void)
        struct davinci_soc_info *soc_info = &davinci_soc_info;
        int ret;
 
+       ret = da8xx_pinmux_setup(da850_nand_pins);
+       if (ret)
+               pr_warning("da850_evm_init: nand mux setup failed: %d\n",
+                               ret);
+
+       platform_add_devices(da850_evm_devices,
+                               ARRAY_SIZE(da850_evm_devices));
+
        ret = da8xx_register_edma();
        if (ret)
                pr_warning("da850_evm_init: edma registration failed: %d\n",
index 9debd57deb71aa05e51daffc0a7d096707e6df21..db4209413450959df5c06e1d057fc455c4b9d1f5 100644 (file)
@@ -310,6 +310,13 @@ static struct clk mmcsd_clk = {
        .lpsc           = DA8XX_LPSC0_MMC_SD,
 };
 
+static struct clk aemif_clk = {
+       .name           = "aemif",
+       .parent         = &pll0_sysclk3,
+       .lpsc           = DA8XX_LPSC0_EMIF25,
+       .flags          = ALWAYS_ENABLED,
+};
+
 static struct davinci_clk da850_clks[] = {
        CLK(NULL,               "ref",          &ref_clk),
        CLK(NULL,               "pll0",         &pll0_clk),
@@ -350,6 +357,7 @@ static struct davinci_clk da850_clks[] = {
        CLK("davinci-mcasp.0",  NULL,           &mcasp_clk),
        CLK("da8xx_lcdc.0",     NULL,           &lcdc_clk),
        CLK("davinci_mmc.0",    NULL,           &mmcsd_clk),
+       CLK(NULL,               "aemif",        &aemif_clk),
        CLK(NULL,               NULL,           NULL),
 };
 
@@ -448,6 +456,21 @@ static const struct mux_config da850_pins[] = {
        MUX_CFG(DA850, MMCSD0_DAT_3,    10,     20,     15,     2,      false)
        MUX_CFG(DA850, MMCSD0_CLK,      10,     0,      15,     2,      false)
        MUX_CFG(DA850, MMCSD0_CMD,      10,     4,      15,     2,      false)
+       /* EMIF2.5/EMIFA function */
+       MUX_CFG(DA850, EMA_D_7,         9,      0,      15,     1,      false)
+       MUX_CFG(DA850, EMA_D_6,         9,      4,      15,     1,      false)
+       MUX_CFG(DA850, EMA_D_5,         9,      8,      15,     1,      false)
+       MUX_CFG(DA850, EMA_D_4,         9,      12,     15,     1,      false)
+       MUX_CFG(DA850, EMA_D_3,         9,      16,     15,     1,      false)
+       MUX_CFG(DA850, EMA_D_2,         9,      20,     15,     1,      false)
+       MUX_CFG(DA850, EMA_D_1,         9,      24,     15,     1,      false)
+       MUX_CFG(DA850, EMA_D_0,         9,      28,     15,     1,      false)
+       MUX_CFG(DA850, EMA_A_1,         12,     24,     15,     1,      false)
+       MUX_CFG(DA850, EMA_A_2,         12,     20,     15,     1,      false)
+       MUX_CFG(DA850, NEMA_CS_3,       7,      4,      15,     1,      false)
+       MUX_CFG(DA850, NEMA_CS_4,       7,      8,      15,     1,      false)
+       MUX_CFG(DA850, NEMA_WE,         7,      16,     15,     1,      false)
+       MUX_CFG(DA850, NEMA_OE,         7,      20,     15,     1,      false)
        /* GPIO function */
        MUX_CFG(DA850, GPIO2_15,        5,      0,      15,     8,      false)
        MUX_CFG(DA850, GPIO8_10,        18,     28,     15,     8,      false)
@@ -514,6 +537,14 @@ const short da850_mmcsd0_pins[] __initdata = {
        -1
 };
 
+const short da850_nand_pins[] __initdata = {
+       DA850_EMA_D_7, DA850_EMA_D_6, DA850_EMA_D_5, DA850_EMA_D_4,
+       DA850_EMA_D_3, DA850_EMA_D_2, DA850_EMA_D_1, DA850_EMA_D_0,
+       DA850_EMA_A_1, DA850_EMA_A_2, DA850_NEMA_CS_3, DA850_NEMA_CS_4,
+       DA850_NEMA_WE, DA850_NEMA_OE,
+       -1
+};
+
 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
 static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
        [IRQ_DA8XX_COMMTX]              = 7,
index 0af141ffc3b4a48b3d7e706c9fcc2a68814cb9ba..77e5d2398e2127337ee8ffc961ab5f48dce46d37 100644 (file)
@@ -40,6 +40,8 @@
 #define DA8XX_PSC1_BASE                0x01e27000
 #define DA8XX_LCD_CNTRL_BASE   0x01e13000
 #define DA8XX_MMCSD0_BASE      0x01c40000
+#define DA8XX_AEMIF_CS3_BASE   0x62000000
+#define DA8XX_AEMIF_CTL_BASE   0x68000000
 
 #define PINMUX0                        0x00
 #define PINMUX1                        0x04
@@ -110,6 +112,7 @@ extern const short da850_cpgmac_pins[];
 extern const short da850_mcasp_pins[];
 extern const short da850_lcdcntl_pins[];
 extern const short da850_mmcsd0_pins[];
+extern const short da850_nand_pins[];
 
 int da8xx_pinmux_setup(const short pins[]);
 
index b2335640c222661ced12baa84c46e17b546d7949..ee6f29db4452b3e937daeb5291139cf74bdecda4 100644 (file)
@@ -806,6 +806,22 @@ enum davinci_da850_index {
        DA850_MMCSD0_CLK,
        DA850_MMCSD0_CMD,
 
+       /* EMIF2.5/EMIFA function */
+       DA850_EMA_D_7,
+       DA850_EMA_D_6,
+       DA850_EMA_D_5,
+       DA850_EMA_D_4,
+       DA850_EMA_D_3,
+       DA850_EMA_D_2,
+       DA850_EMA_D_1,
+       DA850_EMA_D_0,
+       DA850_EMA_A_1,
+       DA850_EMA_A_2,
+       DA850_NEMA_CS_3,
+       DA850_NEMA_CS_4,
+       DA850_NEMA_WE,
+       DA850_NEMA_OE,
+
        /* GPIO function */
        DA850_GPIO2_15,
        DA850_GPIO8_10,