Thumb assembly parsing and encoding for B.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137891 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 74d34e1443043daa2653a332e812452ed195b3ee..f89968f670bc198329607c9a19754bcdcdbb452c 100644 (file)
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -3035,6 +3035,10 @@ processInstruction(MCInst &Inst,
     if (Inst.getOperand(3).getImm() < 8)
       Inst.setOpcode(ARM::tADDi3);
     break;
+  case ARM::tBcc:
+    // If the conditional is AL, we really want tB.
+    if (Inst.getOperand(1).getImm() == ARMCC::AL)
+      Inst.setOpcode(ARM::tB);
   }
 }
 

diff --git a/test/MC/ARM/basic-thumb-instructions.s b/test/MC/ARM/basic-thumb-instructions.s
index 7899a550f2a7a150f90d3edbcc05c109ae48501e..f690c55b74e8c2f462d7107d3cc7ed78ca6a1a8c 100644 (file)
--- a/test/MC/ARM/basic-thumb-instructions.s
+++ b/test/MC/ARM/basic-thumb-instructions.s
@@ -76,3 +76,15 @@ _func:
         asrs r5, r2
 
 @ CHECK: asrs  r5, r2                  @ encoding: [0x15,0x41]
+
+
+@------------------------------------------------------------------------------
+@ B
+@------------------------------------------------------------------------------
+        b _baz
+        beq _bar
+
+@ CHECK: b     _baz                    @ encoding: [A,0xe0'A']
+             @   fixup A - offset: 0, value: _baz, kind: fixup_arm_thumb_br
+@ CHECK: beq   _bar                    @ encoding: [A,0xd0]
+             @   fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_bcc