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rk3066b: delete aclk_gpu gate_mode
author
chenxing
<chenxing@rock-chips.com>
Fri, 7 Sep 2012 03:29:58 +0000
(11:29 +0800)
committer
chenxing
<chenxing@rock-chips.com>
Fri, 7 Sep 2012 03:29:58 +0000
(11:29 +0800)
arch/arm/mach-rk30/clock_data-rk3066b.c
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diff --git
a/arch/arm/mach-rk30/clock_data-rk3066b.c
b/arch/arm/mach-rk30/clock_data-rk3066b.c
index 976b02fd380889e1ce84ef1445942113ed24e8ee..8e7ffabb5310b33d79204c09b283eecbbd39dcbf 100644
(file)
--- a/
arch/arm/mach-rk30/clock_data-rk3066b.c
+++ b/
arch/arm/mach-rk30/clock_data-rk3066b.c
@@
-1288,7
+1288,6
@@
static struct clk *gpu_aclk_parents[2] = {&codec_pll_clk, &general_pll_clk};
static struct clk aclk_gpu = {
.name = "aclk_gpu",
- .mode = gate_mode,
.recalc = clksel_recalc_div,
.round_rate = clk_freediv_round_autosel_parents_rate,
.set_rate = clkset_rate_freediv_autosel_parents,
@@
-1978,7
+1977,7
@@
static struct clk clk_saradc = {
.mode = gate_mode,
.recalc = clksel_recalc_div,
.set_rate = clksel_set_rate_freediv,
- .gate_idx =
CLK_GATE_SARADC_SRC,
+ .gate_idx = CLK_GATE_SARADC_SRC,
.clksel_con = CRU_CLKSELS_CON(24),
CRU_DIV_SET(0xff, 8, 256),
};